104 files changed, 0 insertions, 153771 deletions

diff --git a/libgloss/bfin/include/blackfin.h b/libgloss/bfin/include/blackfin.h
deleted file mode 100644
index 464ac7757..000000000
--- a/libgloss/bfin/include/blackfin.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#ifndef _BLACKFIN_H
-#define _BLACKFIN_H
-#include <sys/platform.h>
-#endif
diff --git a/libgloss/bfin/include/builtins.h b/libgloss/bfin/include/builtins.h
deleted file mode 100644
index d33d2e952..000000000
--- a/libgloss/bfin/include/builtins.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_2_4)
-#pragma diag(suppress:misra_rule_5_3)
-#pragma diag(suppress:misra_rule_6_3)
-#pragma diag(suppress:misra_rule_8_1)
-#pragma diag(suppress:misra_rule_8_8)
-#pragma diag(suppress:misra_rule_8_5)
-#pragma diag(suppress:misra_rule_19_7)
-#pragma diag(suppress:misra_rule_19_15)
-#pragma diag(suppress:misra_rule_20_2)
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if !defined(__NO_BUILTIN)
-
-/* VDSP -> GCC glue */
-#define __builtin_NOP()            __asm__ __volatile__ ("NOP;")
-#define __builtin_cli()            ({ unsigned int __rval; __asm__ __volatile__ ("cli %0;" : "=r"(__rval)); __rval; })
-#define __builtin_sti(x)           __asm__ __volatile__ ("sti %0;" : : "r"(x))
-#define __builtin_idle()           __asm__ __volatile__ ("IDLE;")
-#define __builtin_raise(x)         __asm__ __volatile__ ("raise %0;" : : "n"(x))
-#define __builtin_excpt(x)         __asm__ __volatile__ ("excpt %0;" : : "n"(x))
-#define __builtin_prefetch(x)      __asm__ __volatile__ ("PREFETCH[%0];" : : "p"(x))
-#define __builtin_prefetchmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("PREFETCH[%0++];" : "+p"(__p)); __p; })
-#define __builtin_flushinv(x)      __asm__ __volatile__ ("FLUSHINV[%0];" : : "p"(x))
-#define __builtin_flushinvmodup(x) ({ void *__p = &(x); __asm__ __volatile__ ("FLUSHINV[%0++];" : "+p"(__p)); __p; })
-#define __builtin_flush(x)         __asm__ __volatile__ ("FLUSH[%0];" : : "p"(x))
-#define __builtin_flushmodup(x)    ({ void *__p = &(x); __asm__ __volatile__ ("FLUSH[%0++];" : "+p"(__p)); __p; })
-#define __builtin_iflush(x)        __asm__ __volatile__ ("IFLUSH[%0];" : : "p"(x))
-#define __builtin_iflushmodup(x)   ({ void *__p = &(x); __asm__ __volatile__ ("IFLUSH[%0++];" : "+p"(__p)); __p; })
-#define __builtin_csync()          __builtin_bfin_csync()
-#define __builtin_ssync()          __builtin_bfin_ssync()
-
-#endif /* __NO_BUILTIN */
-
-
-#if !defined(__NO_BUILTIN) && !defined(__NO_SHORTNAMES)
-
-#if (!defined(__DEFINED_NOP) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_NOP)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_NOP))))
-
-#define __DEFINED_NOP
-
-/* Insert a normal 16 bit NOP, which is treated as volatile.
-*/
-
-#pragma inline
-#pragma always_inline
-static void  NOP(void) {
-  __builtin_NOP();
-}
-
-#endif /* __DEFINED_NOP */
-
-#if (!defined(__DEFINED_CLI) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_CLI)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_CLI))))
-
-#define __DEFINED_CLI
-
-#pragma inline
-#pragma always_inline
-static unsigned int  cli(void) {
-  unsigned int  __rval = __builtin_cli();
-  return __rval;
-}
-
-#endif /* __DEFINED_CLI */
-
-#if (!defined(__DEFINED_STI) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_STI)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_STI))))
-
-#define __DEFINED_STI
-
-#pragma inline
-#pragma always_inline
-static void  sti(unsigned int  __a) {
-  __builtin_sti(__a);
-}
-
-#endif /* __DEFINED_STI */
-
-#if (!defined(__DEFINED_IDLE) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IDLE)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IDLE))))
-
-#define __DEFINED_IDLE
-
-#pragma inline
-#pragma always_inline
-static void  idle(void) {
-  __builtin_idle();
-}
-
-#endif /* __DEFINED_IDLE */
-
-#if (!defined(__DEFINED_RAISE_INTR) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_RAISE_INTR)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_RAISE_INTR))))
-
-#define __DEFINED_RAISE_INTR
-
-#define raise_intr(A) (__builtin_raise((A)))
-
-#endif /* __DEFINED_RAISE_INTR */
-
-#if (!defined(__DEFINED_EXCPT) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_EXCPT)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_EXCPT))))
-
-#define __DEFINED_EXCPT
-
-#define excpt(A) (__builtin_excpt((A)))
-
-#endif /* __DEFINED_EXCPT */
-
-#if (!defined(__DEFINED_PREFETCH) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_PREFETCH)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_PREFETCH))))
-
-#define __DEFINED_PREFETCH
-
-#pragma inline
-#pragma always_inline
-static void  prefetch(void * __a) {
-  __builtin_prefetch(__a);
-}
-
-#endif /* __DEFINED_PREFETCH */
-
-#if (!defined(__DEFINED_PREFETCHMODUP) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_PREFETCHMODUP)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_PREFETCHMODUP))))
-
-#define __DEFINED_PREFETCHMODUP
-
-#pragma inline
-#pragma always_inline
-static void * prefetchmodup(void * __a) {
-  void * __rval = __builtin_prefetchmodup(__a);
-  return __rval;
-}
-
-#endif /* __DEFINED_PREFETCHMODUP */
-
-#if (!defined(__DEFINED_FLUSHINV) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHINV)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHINV))))
-
-#define __DEFINED_FLUSHINV
-
-#pragma inline
-#pragma always_inline
-static void  flushinv(void * __a) {
-  __builtin_flushinv(__a);
-}
-
-#endif /* __DEFINED_FLUSHINV */
-
-#if (!defined(__DEFINED_FLUSHINVMODUP) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHINVMODUP)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHINVMODUP))))
-
-#define __DEFINED_FLUSHINVMODUP
-
-#pragma inline
-#pragma always_inline
-static void * flushinvmodup(void * __a) {
-  void * __rval = __builtin_flushinvmodup(__a);
-  return __rval;
-}
-
-#endif /* __DEFINED_FLUSHINVMODUP */
-
-#if (!defined(__DEFINED_FLUSH) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSH)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSH))))
-
-#define __DEFINED_FLUSH
-
-#pragma inline
-#pragma always_inline
-static void  flush(void * __a) {
-  __builtin_flush(__a);
-}
-
-#endif /* __DEFINED_FLUSH */
-
-#if (!defined(__DEFINED_FLUSHMODUP) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_FLUSHMODUP)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_FLUSHMODUP))))
-
-#define __DEFINED_FLUSHMODUP
-
-#pragma inline
-#pragma always_inline
-static void * flushmodup(void * __a) {
-  void * __rval = __builtin_flushmodup(__a);
-  return __rval;
-}
-
-#endif /* __DEFINED_FLUSHMODUP */
-
-#if (!defined(__DEFINED_IFLUSH) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IFLUSH)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IFLUSH))))
-
-#define __DEFINED_IFLUSH
-
-#pragma inline
-#pragma always_inline
-static void  iflush(void * __a) {
-  __builtin_iflush(__a);
-}
-
-#endif /* __DEFINED_IFLUSH */
-
-#if (!defined(__DEFINED_IFLUSHMODUP) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_IFLUSHMODUP)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_IFLUSHMODUP))))
-
-#define __DEFINED_IFLUSHMODUP
-
-#pragma inline
-#pragma always_inline
-static void * iflushmodup(void * __a) {
-  void * __rval = __builtin_iflushmodup(__a);
-  return __rval;
-}
-
-#endif /* __DEFINED_IFLUSHMODUP */
-
-#if (!defined(__DEFINED_CSYNC) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_CSYNC)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_CSYNC))))
-
-#define __DEFINED_CSYNC
-
-/* generate a csync instruction protected by CLI/STI for anomaly 05-00-0312;
-** you can generate an unprotected csync by using csync_int
-*/
-
-#pragma inline
-#pragma always_inline
-static void csync(void) {
-  __builtin_csync();
-}
-
-#endif /* __DEFINED_CSYNC */
-
-#if (!defined(__DEFINED_SSYNC) && \
-     ((defined(__SPECIFIC_NAMES) && defined(__ENABLE_SSYNC)) || \
-       (!defined(__SPECIFIC_NAMES) && !defined(__DISABLE_SSYNC))))
-
-#define __DEFINED_SSYNC
-
-/* generate a ssync instruction protected by CLI/STI for anomaly 05-00-0312;
-** you can generate an unprotected ssync by using ssync_int
-*/
-
-#pragma inline
-#pragma always_inline
-static void ssync(void) {
-  __builtin_ssync();
-}
-
-#endif /* __DEFINED_SSYNC */
-
-#endif /* __NO_BUILTIN */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/libgloss/bfin/include/ccblkfn.h b/libgloss/bfin/include/ccblkfn.h
deleted file mode 100644
index 190da2d43..000000000
--- a/libgloss/bfin/include/ccblkfn.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#ifndef _CCBLKFN_H
-#define _CCBLKFN_H
-
-#include <stdlib.h>
-
-#include <builtins.h>
-#include <sys/anomaly_macros_rtl.h>
-
-#include <sys/mc_typedef.h>
-
-#endif
diff --git a/libgloss/bfin/include/cdefBF504.h b/libgloss/bfin/include/cdefBF504.h
deleted file mode 100644
index cb698fc18..000000000
--- a/libgloss/bfin/include/cdefBF504.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF504 processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _CDEF_BF504_H
-#define _CDEF_BF504_H
-
-/* Include all Core registers and bit definitions */
-#include <cdef_LPBlackfin.h>
-
-/* Include cdefBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <cdefBF50x_base.h>
-
-/* Define the set of macros that are specific to the ADSP-BF504 processor */
-
-#endif /* _CDEF_BF504_H */
diff --git a/libgloss/bfin/include/cdefBF504F.h b/libgloss/bfin/include/cdefBF504F.h
deleted file mode 100644
index 31f3caffb..000000000
--- a/libgloss/bfin/include/cdefBF504F.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF504F processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _CDEF_BF504F_H
-#define _CDEF_BF504F_H
-
-/* Include all Core registers and bit definitions */
-#include <cdef_LPBlackfin.h>
-
-/* Include cdefBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <cdefBF50x_base.h>
-
-/* Define the set of macros that are specific to the ADSP-BF504F processor */
-
-#endif /* _CDEF_BF504F_H */
diff --git a/libgloss/bfin/include/cdefBF506F.h b/libgloss/bfin/include/cdefBF506F.h
deleted file mode 100644
index f75d73cae..000000000
--- a/libgloss/bfin/include/cdefBF506F.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF506F processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _CDEF_BF506F_H
-#define _CDEF_BF506F_H
-
-/* Include all Core registers and bit definitions */
-#include <cdef_LPBlackfin.h>
-
-/* Include cdefBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <cdefBF50x_base.h>
-
-#endif /* _CDEF_BF506F_H */
diff --git a/libgloss/bfin/include/cdefBF50x_base.h b/libgloss/bfin/include/cdefBF50x_base.h
deleted file mode 100644
index 58de0833b..000000000
--- a/libgloss/bfin/include/cdefBF50x_base.h
+++ /dev/null
@@ -1,1159 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF50x_base.h
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the system MMRs common to the ADSP-BF50x parts
-** peripherals.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _CDEF_BF50X_H
-#define _CDEF_BF50X_H
-
-#include <defBF50x_base.h>
-#include <stdint.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-# ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#  define _PTR_TO_VOL_VOID_PTR _PTR_TO_VOL_VOID_PTR
-# else
-#  define _PTR_TO_VOL_VOID_PTR (volatile void **)
-# endif
-#endif
-
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL            ((volatile uint16_t *)PLL_CTL)
-#define pPLL_DIV            ((volatile uint16_t *)PLL_DIV)
-#define pVR_CTL             ((volatile uint16_t *)VR_CTL)
-#define pPLL_STAT       ((volatile uint16_t *)PLL_STAT)
-#define pPLL_LOCKCNT        ((volatile uint16_t *)PLL_LOCKCNT)
-#define pCHIPID         ((volatile uint32_t *)CHIPID)
-
-
-/* System Interrupt Controller  (0xFFC00100 - 0xFFC001FF) */
-#define pSWRST          ((volatile uint16_t *)SWRST)
-#define pSYSCR          ((volatile uint16_t *)SYSCR)
-
-#define pSIC_IMASK0         ((volatile uint32_t *)SIC_IMASK0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IMASK      ((volatile uint32_t *)SIC_IMASK0)
-#define pSIC_IAR0       ((volatile uint32_t *)SIC_IAR0)
-#define pSIC_IAR1       ((volatile uint32_t *)SIC_IAR1)
-#define pSIC_IAR2       ((volatile uint32_t *)SIC_IAR2)
-#define pSIC_IAR3       ((volatile uint32_t *)SIC_IAR3)
-#define pSIC_ISR0       ((volatile uint32_t *)SIC_ISR0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_ISR            ((volatile uint32_t *)SIC_ISR0)
-#define pSIC_IWR0       ((volatile uint32_t *)SIC_IWR0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IWR            ((volatile uint32_t *)SIC_IWR0)
-
-/* SIC Additions to ADSP-BF50x  (0xFFC0014C - 0xFFC00162) */
-#define pSIC_IMASK1     ((volatile uint32_t *)SIC_IMASK1)
-#define pSIC_IAR4           ((volatile uint32_t *)SIC_IAR4)
-#define pSIC_IAR5           ((volatile uint32_t *)SIC_IAR5)
-#define pSIC_IAR6           ((volatile uint32_t *)SIC_IAR6)
-#define pSIC_ISR1           ((volatile uint32_t *)SIC_ISR1)
-#define pSIC_IWR1           ((volatile uint32_t *)SIC_IWR1)
-
-/* Watchdog Timer           (0xFFC00200 - 0xFFC002FF) */
-#define pWDOG_CTL       ((volatile uint16_t *)WDOG_CTL)
-#define pWDOG_CNT       ((volatile uint32_t *)WDOG_CNT)
-#define pWDOG_STAT      ((volatile uint32_t *)WDOG_STAT)
-
-
-/* UART0 Controller         (0xFFC00400 - 0xFFC004FF) */
-#define pUART0_DLL      ((volatile uint16_t *)UART0_DLL)
-#define pUART0_DLH      ((volatile uint16_t *)UART0_DLH)
-#define pUART0_GCTL     ((volatile uint16_t *)UART0_GCTL)
-#define pUART0_LCR      ((volatile uint16_t *)UART0_LCR)
-#define pUART0_MCR      ((volatile uint16_t *)UART0_MCR)
-#define pUART0_LSR      ((volatile uint16_t *)UART0_LSR)
-#define pUART0_MSR      ((volatile uint16_t *)UART0_MSR)
-#define pUART0_SCR      ((volatile uint16_t *)UART0_SCR)
-#define pUART0_IER_SET  ((volatile uint16_t *)UART0_IER_SET)
-#define pUART0_IER_CLEAR    ((volatile uint16_t *)UART0_IER_CLEAR)
-#define pUART0_THR      ((volatile uint16_t *)UART0_THR)
-#define pUART0_RBR      ((volatile uint16_t *)UART0_RBR)
-
-
-/* SPI0 Controller          (0xFFC00500 - 0xFFC005FF)*/
-#define pSPI0_CTL       ((volatile uint16_t *)SPI0_CTL)
-#define pSPI0_FLG       ((volatile uint16_t *)SPI0_FLG)
-#define pSPI0_STAT      ((volatile uint16_t *)SPI0_STAT)
-#define pSPI0_TDBR      ((volatile uint16_t *)SPI0_TDBR)
-#define pSPI0_RDBR      ((volatile uint16_t *)SPI0_RDBR)
-#define pSPI0_BAUD      ((volatile uint16_t *)SPI0_BAUD)
-#define pSPI0_SHADOW        ((volatile uint16_t *)SPI0_SHADOW)
-/* legacy register names (below) provided for backwards code compatibility */
-#define pSPI_CTL            (pSPI0_CTL)
-#define pSPI_FLG            (pSPI0_FLG)
-#define pSPI_STAT           (pSPI0_STAT)
-#define pSPI_TDBR           (pSPI0_TDBR)
-#define pSPI_RDBR           (pSPI0_RDBR)
-#define pSPI_BAUD           (pSPI0_BAUD)
-#define pSPI_SHADOW     (pSPI0_SHADOW)
-
-
-/* TIMER0-7 Registers       (0xFFC00600 - 0xFFC006FF) */
-#define pTIMER0_CONFIG      ((volatile uint16_t *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER     ((volatile uint32_t *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD      ((volatile uint32_t *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH       ((volatile uint32_t *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG      ((volatile uint16_t *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER     ((volatile uint32_t *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD      ((volatile uint32_t *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH       ((volatile uint32_t *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG      ((volatile uint16_t *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER     ((volatile uint32_t *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD      ((volatile uint32_t *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH       ((volatile uint32_t *)TIMER2_WIDTH)
-
-#define pTIMER3_CONFIG      ((volatile uint16_t *)TIMER3_CONFIG)
-#define pTIMER3_COUNTER     ((volatile uint32_t *)TIMER3_COUNTER)
-#define pTIMER3_PERIOD      ((volatile uint32_t *)TIMER3_PERIOD)
-#define pTIMER3_WIDTH       ((volatile uint32_t *)TIMER3_WIDTH)
-
-#define pTIMER4_CONFIG      ((volatile uint16_t *)TIMER4_CONFIG)
-#define pTIMER4_COUNTER     ((volatile uint32_t *)TIMER4_COUNTER)
-#define pTIMER4_PERIOD      ((volatile uint32_t *)TIMER4_PERIOD)
-#define pTIMER4_WIDTH       ((volatile uint32_t *)TIMER4_WIDTH)
-
-#define pTIMER5_CONFIG      ((volatile uint16_t *)TIMER5_CONFIG)
-#define pTIMER5_COUNTER     ((volatile uint32_t *)TIMER5_COUNTER)
-#define pTIMER5_PERIOD      ((volatile uint32_t *)TIMER5_PERIOD)
-#define pTIMER5_WIDTH       ((volatile uint32_t *)TIMER5_WIDTH)
-
-#define pTIMER6_CONFIG      ((volatile uint16_t *)TIMER6_CONFIG)
-#define pTIMER6_COUNTER     ((volatile uint32_t *)TIMER6_COUNTER)
-#define pTIMER6_PERIOD      ((volatile uint32_t *)TIMER6_PERIOD)
-#define pTIMER6_WIDTH       ((volatile uint32_t *)TIMER6_WIDTH)
-
-#define pTIMER7_CONFIG      ((volatile uint16_t *)TIMER7_CONFIG)
-#define pTIMER7_COUNTER     ((volatile uint32_t *)TIMER7_COUNTER)
-#define pTIMER7_PERIOD      ((volatile uint32_t *)TIMER7_PERIOD)
-#define pTIMER7_WIDTH       ((volatile uint32_t *)TIMER7_WIDTH)
-
-#define pTIMER_ENABLE       ((volatile uint16_t *)TIMER_ENABLE)
-#define pTIMER_DISABLE      ((volatile uint16_t *)TIMER_DISABLE)
-#define pTIMER_STATUS       ((volatile uint32_t *)TIMER_STATUS)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define pPORTFIO            ((volatile uint16_t *)PORTFIO)
-#define pPORTFIO_CLEAR      ((volatile uint16_t *)PORTFIO_CLEAR)
-#define pPORTFIO_SET        ((volatile uint16_t *)PORTFIO_SET)
-#define pPORTFIO_TOGGLE     ((volatile uint16_t *)PORTFIO_TOGGLE)
-#define pPORTFIO_MASKA      ((volatile uint16_t *)PORTFIO_MASKA)
-#define pPORTFIO_MASKA_CLEAR    ((volatile uint16_t *)PORTFIO_MASKA_CLEAR)
-#define pPORTFIO_MASKA_SET  ((volatile uint16_t *)PORTFIO_MASKA_SET)
-#define pPORTFIO_MASKA_TOGGLE ((volatile uint16_t *)PORTFIO_MASKA_TOGGLE)
-#define pPORTFIO_MASKB      ((volatile uint16_t *)PORTFIO_MASKB)
-#define pPORTFIO_MASKB_CLEAR    ((volatile uint16_t *)PORTFIO_MASKB_CLEAR)
-#define pPORTFIO_MASKB_SET  ((volatile uint16_t *)PORTFIO_MASKB_SET)
-#define pPORTFIO_MASKB_TOGGLE ((volatile uint16_t *)PORTFIO_MASKB_TOGGLE)
-#define pPORTFIO_DIR        ((volatile uint16_t *)PORTFIO_DIR)
-#define pPORTFIO_POLAR      ((volatile uint16_t *)PORTFIO_POLAR)
-#define pPORTFIO_EDGE       ((volatile uint16_t *)PORTFIO_EDGE)
-#define pPORTFIO_BOTH       ((volatile uint16_t *)PORTFIO_BOTH)
-#define pPORTFIO_INEN       ((volatile uint16_t *)PORTFIO_INEN)
-
-
-/* SPORT0 Controller        (0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1        ((volatile uint16_t *)SPORT0_TCR1)
-#define pSPORT0_TCR2        ((volatile uint16_t *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV     ((volatile uint16_t *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV      ((volatile uint16_t *)SPORT0_TFSDIV)
-#define pSPORT0_TX          ((volatile uint32_t *)SPORT0_TX)
-#define pSPORT0_RX          ((volatile uint32_t *)SPORT0_RX)
-#define pSPORT0_TX32        ((volatile uint32_t *)SPORT0_TX)
-#define pSPORT0_RX32        ((volatile uint32_t *)SPORT0_RX)
-#define pSPORT0_TX16        ((volatile uint16_t *)SPORT0_TX)
-#define pSPORT0_RX16        ((volatile uint16_t *)SPORT0_RX)
-#define pSPORT0_RCR1        ((volatile uint16_t *)SPORT0_RCR1)
-#define pSPORT0_RCR2        ((volatile uint16_t *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV     ((volatile uint16_t *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV      ((volatile uint16_t *)SPORT0_RFSDIV)
-#define pSPORT0_STAT        ((volatile uint16_t *)SPORT0_STAT)
-#define pSPORT0_CHNL        ((volatile uint16_t *)SPORT0_CHNL)
-#define pSPORT0_MCMC1       ((volatile uint16_t *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2       ((volatile uint16_t *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0       ((volatile uint32_t *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1       ((volatile uint32_t *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2       ((volatile uint32_t *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3       ((volatile uint32_t *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0       ((volatile uint32_t *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1       ((volatile uint32_t *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2       ((volatile uint32_t *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3       ((volatile uint32_t *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller        (0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1        ((volatile uint16_t *)SPORT1_TCR1)
-#define pSPORT1_TCR2        ((volatile uint16_t *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV     ((volatile uint16_t *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV      ((volatile uint16_t *)SPORT1_TFSDIV)
-#define pSPORT1_TX          ((volatile uint32_t *)SPORT1_TX)
-#define pSPORT1_RX          ((volatile uint32_t *)SPORT1_RX)
-#define pSPORT1_TX32        ((volatile uint32_t *)SPORT1_TX)
-#define pSPORT1_RX32        ((volatile uint32_t *)SPORT1_RX)
-#define pSPORT1_TX16        ((volatile uint16_t *)SPORT1_TX)
-#define pSPORT1_RX16        ((volatile uint16_t *)SPORT1_RX)
-#define pSPORT1_RCR1        ((volatile uint16_t *)SPORT1_RCR1)
-#define pSPORT1_RCR2        ((volatile uint16_t *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV     ((volatile uint16_t *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV      ((volatile uint16_t *)SPORT1_RFSDIV)
-#define pSPORT1_STAT        ((volatile uint16_t *)SPORT1_STAT)
-#define pSPORT1_CHNL        ((volatile uint16_t *)SPORT1_CHNL)
-#define pSPORT1_MCMC1       ((volatile uint16_t *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2       ((volatile uint16_t *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0       ((volatile uint32_t *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1       ((volatile uint32_t *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2       ((volatile uint32_t *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3       ((volatile uint32_t *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0       ((volatile uint32_t *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1       ((volatile uint32_t *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2       ((volatile uint32_t *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3       ((volatile uint32_t *)SPORT1_MRCS3)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define pEBIU_AMGCTL        ((volatile uint16_t *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL        ((volatile uint32_t *)EBIU_AMBCTL)
-#define pEBIU_MODE          ((volatile uint16_t *)EBIU_MODE)
-#define pEBIU_FCTL          ((volatile uint16_t *)EBIU_FCTL)
-#define pEBIU_AMBCTL0       ((volatile uint32_t *)EBIU_AMBCTL)
-
-
-/* DMA Traffic Control Registers    (0xFFC00B00 - 0xFFC00BFF) */
-#define pDMA_TC_PER     ((volatile uint16_t *)DMA_TC_PER)
-#define pDMA_TC_CNT     ((volatile uint16_t *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA_TCPER      ((volatile uint16_t *)DMA_TCPER)
-#define pDMA_TCCNT      ((volatile uint16_t *)DMA_TCCNT)
-
-/* DMA Controller           (0xFFC00C00 - FFC00FFF)*/
-#define pDMA0_CONFIG        ((volatile uint16_t *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT       ((volatile uint16_t *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT       ((volatile uint16_t *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY      ((volatile int16_t *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY      ((volatile int16_t *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT  ((volatile uint16_t *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT  ((volatile uint16_t *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS    ((volatile uint16_t *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP    ((volatile uint16_t *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG        ((volatile uint16_t *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT       ((volatile uint16_t *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT       ((volatile uint16_t *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY      ((volatile int16_t *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY      ((volatile int16_t *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT  ((volatile uint16_t *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT  ((volatile uint16_t *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS    ((volatile uint16_t *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP    ((volatile uint16_t *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG        ((volatile uint16_t *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT       ((volatile uint16_t *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT       ((volatile uint16_t *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY      ((volatile int16_t *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY      ((volatile int16_t *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT  ((volatile uint16_t *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT  ((volatile uint16_t *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS    ((volatile uint16_t *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP    ((volatile uint16_t *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG        ((volatile uint16_t *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT       ((volatile uint16_t *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT       ((volatile uint16_t *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY      ((volatile int16_t *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY      ((volatile int16_t *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT  ((volatile uint16_t *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT  ((volatile uint16_t *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS    ((volatile uint16_t *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP    ((volatile uint16_t *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG        ((volatile uint16_t *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT       ((volatile uint16_t *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT       ((volatile uint16_t *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY      ((volatile int16_t *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY      ((volatile int16_t *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT  ((volatile uint16_t *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT  ((volatile uint16_t *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS    ((volatile uint16_t *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP    ((volatile uint16_t *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG        ((volatile uint16_t *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT       ((volatile uint16_t *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT       ((volatile uint16_t *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY      ((volatile int16_t *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY      ((volatile int16_t *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT  ((volatile uint16_t *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT  ((volatile uint16_t *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS    ((volatile uint16_t *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP    ((volatile uint16_t *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG        ((volatile uint16_t *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT       ((volatile uint16_t *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT       ((volatile uint16_t *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY      ((volatile int16_t *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY      ((volatile int16_t *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT  ((volatile uint16_t *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT  ((volatile uint16_t *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS    ((volatile uint16_t *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP    ((volatile uint16_t *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG        ((volatile uint16_t *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT       ((volatile uint16_t *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT       ((volatile uint16_t *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY      ((volatile int16_t *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY      ((volatile int16_t *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT  ((volatile uint16_t *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT  ((volatile uint16_t *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS    ((volatile uint16_t *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP    ((volatile uint16_t *)DMA7_PERIPHERAL_MAP)
-
-#define pDMA8_CONFIG        ((volatile uint16_t *)DMA8_CONFIG)
-#define pDMA8_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
-#define pDMA8_X_COUNT       ((volatile uint16_t *)DMA8_X_COUNT)
-#define pDMA8_Y_COUNT       ((volatile uint16_t *)DMA8_Y_COUNT)
-#define pDMA8_X_MODIFY      ((volatile int16_t *)DMA8_X_MODIFY)
-#define pDMA8_Y_MODIFY      ((volatile int16_t *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
-#define pDMA8_CURR_X_COUNT  ((volatile uint16_t *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT  ((volatile uint16_t *)DMA8_CURR_Y_COUNT)
-#define pDMA8_IRQ_STATUS    ((volatile uint16_t *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP    ((volatile uint16_t *)DMA8_PERIPHERAL_MAP)
-
-#define pDMA9_CONFIG        ((volatile uint16_t *)DMA9_CONFIG)
-#define pDMA9_NEXT_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR    (_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
-#define pDMA9_X_COUNT       ((volatile uint16_t *)DMA9_X_COUNT)
-#define pDMA9_Y_COUNT       ((volatile uint16_t *)DMA9_Y_COUNT)
-#define pDMA9_X_MODIFY      ((volatile int16_t *)DMA9_X_MODIFY)
-#define pDMA9_Y_MODIFY      ((volatile int16_t *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR     (_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR     (_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
-#define pDMA9_CURR_X_COUNT  ((volatile uint16_t *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT  ((volatile uint16_t *)DMA9_CURR_Y_COUNT)
-#define pDMA9_IRQ_STATUS    ((volatile uint16_t *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP    ((volatile uint16_t *)DMA9_PERIPHERAL_MAP)
-
-#define pDMA10_CONFIG       ((volatile uint16_t *)DMA10_CONFIG)
-#define pDMA10_NEXT_DESC_PTR    (_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR   (_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
-#define pDMA10_X_COUNT      ((volatile uint16_t *)DMA10_X_COUNT)
-#define pDMA10_Y_COUNT      ((volatile uint16_t *)DMA10_Y_COUNT)
-#define pDMA10_X_MODIFY     ((volatile int16_t *)DMA10_X_MODIFY)
-#define pDMA10_Y_MODIFY     ((volatile int16_t *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR    (_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR    (_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
-#define pDMA10_CURR_X_COUNT     ((volatile uint16_t *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT     ((volatile uint16_t *)DMA10_CURR_Y_COUNT)
-#define pDMA10_IRQ_STATUS   ((volatile uint16_t *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP ((volatile uint16_t *)DMA10_PERIPHERAL_MAP)
-
-#define pDMA11_CONFIG       ((volatile uint16_t *)DMA11_CONFIG)
-#define pDMA11_NEXT_DESC_PTR    (_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR   (_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
-#define pDMA11_X_COUNT      ((volatile uint16_t *)DMA11_X_COUNT)
-#define pDMA11_Y_COUNT      ((volatile uint16_t *)DMA11_Y_COUNT)
-#define pDMA11_X_MODIFY     ((volatile int16_t *)DMA11_X_MODIFY)
-#define pDMA11_Y_MODIFY     ((volatile int16_t *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR    (_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR    (_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
-#define pDMA11_CURR_X_COUNT     ((volatile uint16_t *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT     ((volatile uint16_t *)DMA11_CURR_Y_COUNT)
-#define pDMA11_IRQ_STATUS   ((volatile uint16_t *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP ((volatile uint16_t *)DMA11_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG     ((volatile uint16_t *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR     (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT    ((volatile uint16_t *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT    ((volatile uint16_t *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY   ((volatile int16_t *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY   ((volatile int16_t *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR    (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT ((volatile uint16_t *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT ((volatile uint16_t *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS     ((volatile uint16_t *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG     ((volatile uint16_t *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR     (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT    ((volatile uint16_t *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT    ((volatile uint16_t *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY   ((volatile int16_t *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY   ((volatile int16_t *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT ((volatile uint16_t *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT ((volatile uint16_t *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS     ((volatile uint16_t *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_S0_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG     ((volatile uint16_t *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR     (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT    ((volatile uint16_t *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT    ((volatile uint16_t *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY   ((volatile int16_t *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY   ((volatile int16_t *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT ((volatile uint16_t *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT ((volatile uint16_t *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS     ((volatile uint16_t *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG     ((volatile uint16_t *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR     (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT    ((volatile uint16_t *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT    ((volatile uint16_t *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY   ((volatile int16_t *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY   ((volatile int16_t *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT ((volatile uint16_t *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT ((volatile uint16_t *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS     ((volatile uint16_t *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_S1_PERIPHERAL_MAP)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define pPPI_CONTROL        ((volatile uint16_t *)PPI_CONTROL)
-#define pPPI_STATUS         ((volatile uint16_t *)PPI_STATUS)
-#define pPPI_DELAY      ((volatile uint16_t *)PPI_DELAY)
-#define pPPI_COUNT      ((volatile uint16_t *)PPI_COUNT)
-#define pPPI_FRAME      ((volatile uint16_t *)PPI_FRAME)
-
-
-/* Two-Wire Interface       (0xFFC01400 - 0xFFC014FF) */
-#define pTWI_CLKDIV     ((volatile uint16_t *)TWI_CLKDIV)
-#define pTWI_CONTROL        ((volatile uint16_t *)TWI_CONTROL)
-#define pTWI_SLAVE_CTL      ((volatile uint16_t *)TWI_SLAVE_CTL)
-#define pTWI_SLAVE_STAT     ((volatile uint16_t *)TWI_SLAVE_STAT)
-#define pTWI_SLAVE_ADDR     ((volatile uint16_t *)TWI_SLAVE_ADDR)
-#define pTWI_MASTER_CTL     ((volatile uint16_t *)TWI_MASTER_CTL)
-#define pTWI_MASTER_STAT    ((volatile uint16_t *)TWI_MASTER_STAT)
-#define pTWI_MASTER_ADDR    ((volatile uint16_t *)TWI_MASTER_ADDR)
-#define pTWI_INT_STAT       ((volatile uint16_t *)TWI_INT_STAT)
-#define pTWI_INT_MASK       ((volatile uint16_t *)TWI_INT_MASK)
-#define pTWI_FIFO_CTL       ((volatile uint16_t *)TWI_FIFO_CTL)
-#define pTWI_FIFO_STAT      ((volatile uint16_t *)TWI_FIFO_STAT)
-#define pTWI_XMT_DATA8      ((volatile uint16_t *)TWI_XMT_DATA8)
-#define pTWI_XMT_DATA16     ((volatile uint16_t *)TWI_XMT_DATA16)
-#define pTWI_RCV_DATA8      ((volatile uint16_t *)TWI_RCV_DATA8)
-#define pTWI_RCV_DATA16     ((volatile uint16_t *)TWI_RCV_DATA16)
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define pPORTGIO            ((volatile uint16_t *)PORTGIO)
-#define pPORTGIO_CLEAR      ((volatile uint16_t *)PORTGIO_CLEAR)
-#define pPORTGIO_SET        ((volatile uint16_t *)PORTGIO_SET)
-#define pPORTGIO_TOGGLE     ((volatile uint16_t *)PORTGIO_TOGGLE)
-#define pPORTGIO_MASKA      ((volatile uint16_t *)PORTGIO_MASKA)
-#define pPORTGIO_MASKA_CLEAR    ((volatile uint16_t *)PORTGIO_MASKA_CLEAR)
-#define pPORTGIO_MASKA_SET  ((volatile uint16_t *)PORTGIO_MASKA_SET)
-#define pPORTGIO_MASKA_TOGGLE   ((volatile uint16_t *)PORTGIO_MASKA_TOGGLE)
-#define pPORTGIO_MASKB      ((volatile uint16_t *)PORTGIO_MASKB)
-#define pPORTGIO_MASKB_CLEAR    ((volatile uint16_t *)PORTGIO_MASKB_CLEAR)
-#define pPORTGIO_MASKB_SET  ((volatile uint16_t *)PORTGIO_MASKB_SET)
-#define pPORTGIO_MASKB_TOGGLE   ((volatile uint16_t *)PORTGIO_MASKB_TOGGLE)
-#define pPORTGIO_DIR        ((volatile uint16_t *)PORTGIO_DIR)
-#define pPORTGIO_POLAR      ((volatile uint16_t *)PORTGIO_POLAR)
-#define pPORTGIO_EDGE       ((volatile uint16_t *)PORTGIO_EDGE)
-#define pPORTGIO_BOTH       ((volatile uint16_t *)PORTGIO_BOTH)
-#define pPORTGIO_INEN       ((volatile uint16_t *)PORTGIO_INEN)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define pPORTHIO            ((volatile uint16_t *)PORTHIO)
-#define pPORTHIO_CLEAR      ((volatile uint16_t *)PORTHIO_CLEAR)
-#define pPORTHIO_SET        ((volatile uint16_t *)PORTHIO_SET)
-#define pPORTHIO_TOGGLE     ((volatile uint16_t *)PORTHIO_TOGGLE)
-#define pPORTHIO_MASKA      ((volatile uint16_t *)PORTHIO_MASKA)
-#define pPORTHIO_MASKA_CLEAR    ((volatile uint16_t *)PORTHIO_MASKA_CLEAR)
-#define pPORTHIO_MASKA_SET  ((volatile uint16_t *)PORTHIO_MASKA_SET)
-#define pPORTHIO_MASKA_TOGGLE   ((volatile uint16_t *)PORTHIO_MASKA_TOGGLE)
-#define pPORTHIO_MASKB      ((volatile uint16_t *)PORTHIO_MASKB)
-#define pPORTHIO_MASKB_CLEAR    ((volatile uint16_t *)PORTHIO_MASKB_CLEAR)
-#define pPORTHIO_MASKB_SET  ((volatile uint16_t *)PORTHIO_MASKB_SET)
-#define pPORTHIO_MASKB_TOGGLE   ((volatile uint16_t *)PORTHIO_MASKB_TOGGLE)
-#define pPORTHIO_DIR        ((volatile uint16_t *)PORTHIO_DIR)
-#define pPORTHIO_POLAR      ((volatile uint16_t *)PORTHIO_POLAR)
-#define pPORTHIO_EDGE       ((volatile uint16_t *)PORTHIO_EDGE)
-#define pPORTHIO_BOTH       ((volatile uint16_t *)PORTHIO_BOTH)
-#define pPORTHIO_INEN       ((volatile uint16_t *)PORTHIO_INEN)
-
-
-/* UART1 Controller         (0xFFC02000 - 0xFFC020FF) */
-#define pUART1_DLL      ((volatile uint16_t *)UART1_DLL)
-#define pUART1_DLH      ((volatile uint16_t *)UART1_DLH)
-#define pUART1_GCTL     ((volatile uint16_t *)UART1_GCTL)
-#define pUART1_LCR      ((volatile uint16_t *)UART1_LCR)
-#define pUART1_MCR      ((volatile uint16_t *)UART1_MCR)
-#define pUART1_LSR      ((volatile uint16_t *)UART1_LSR)
-#define pUART1_MSR      ((volatile uint16_t *)UART1_MSR)
-#define pUART1_SCR      ((volatile uint16_t *)UART1_SCR)
-#define pUART1_IER_SET  ((volatile uint16_t *)UART1_IER_SET)
-#define pUART1_IER_CLEAR    ((volatile uint16_t *)UART1_IER_CLEAR)
-#define pUART1_THR      ((volatile uint16_t *)UART1_THR)
-#define pUART1_RBR      ((volatile uint16_t *)UART1_RBR)
-
-
-/* CAN Controller           (0xFFC02A00 - 0xFFC02FFF) */
-/* For Mailboxes 0-15 */
-#define pCAN_MC1            ((volatile uint16_t *)CAN_MC1)
-#define pCAN_MD1            ((volatile uint16_t *)CAN_MD1)
-#define pCAN_TRS1           ((volatile uint16_t *)CAN_TRS1)
-#define pCAN_TRR1           ((volatile uint16_t *)CAN_TRR1)
-#define pCAN_TA1            ((volatile uint16_t *)CAN_TA1)
-#define pCAN_AA1            ((volatile uint16_t *)CAN_AA1)
-#define pCAN_RMP1           ((volatile uint16_t *)CAN_RMP1)
-#define pCAN_RML1           ((volatile uint16_t *)CAN_RML1)
-#define pCAN_MBTIF1         ((volatile uint16_t *)CAN_MBTIF1)
-#define pCAN_MBRIF1         ((volatile uint16_t *)CAN_MBRIF1)
-#define pCAN_MBIM1          ((volatile uint16_t *)CAN_MBIM1)
-#define pCAN_RFH1           ((volatile uint16_t *)CAN_RFH1)
-#define pCAN_OPSS1          ((volatile uint16_t *)CAN_OPSS1)
-
-/* For Mailboxes 16-31 */
-#define pCAN_MC2            ((volatile uint16_t *)CAN_MC2)
-#define pCAN_MD2            ((volatile uint16_t *)CAN_MD2)
-#define pCAN_TRS2           ((volatile uint16_t *)CAN_TRS2)
-#define pCAN_TRR2           ((volatile uint16_t *)CAN_TRR2)
-#define pCAN_TA2            ((volatile uint16_t *)CAN_TA2)
-#define pCAN_AA2            ((volatile uint16_t *)CAN_AA2)
-#define pCAN_RMP2           ((volatile uint16_t *)CAN_RMP2)
-#define pCAN_RML2           ((volatile uint16_t *)CAN_RML2)
-#define pCAN_MBTIF2         ((volatile uint16_t *)CAN_MBTIF2)
-#define pCAN_MBRIF2         ((volatile uint16_t *)CAN_MBRIF2)
-#define pCAN_MBIM2          ((volatile uint16_t *)CAN_MBIM2)
-#define pCAN_RFH2           ((volatile uint16_t *)CAN_RFH2)
-#define pCAN_OPSS2          ((volatile uint16_t *)CAN_OPSS2)
-
-#define pCAN_CLOCK          ((volatile uint16_t *)CAN_CLOCK)
-#define pCAN_TIMING         ((volatile uint16_t *)CAN_TIMING)
-#define pCAN_DEBUG          ((volatile uint16_t *)CAN_DEBUG)
-#define pCAN_STATUS         ((volatile uint16_t *)CAN_STATUS)
-#define pCAN_CEC            ((volatile uint16_t *)CAN_CEC)
-#define pCAN_GIS            ((volatile uint16_t *)CAN_GIS)
-#define pCAN_GIM            ((volatile uint16_t *)CAN_GIM)
-#define pCAN_GIF            ((volatile uint16_t *)CAN_GIF)
-#define pCAN_CONTROL        ((volatile uint16_t *)CAN_CONTROL)
-#define pCAN_INTR           ((volatile uint16_t *)CAN_INTR)
-#define pCAN_MBTD           ((volatile uint16_t *)CAN_MBTD)
-#define pCAN_EWR            ((volatile uint16_t *)CAN_EWR)
-#define pCAN_ESR            ((volatile uint16_t *)CAN_ESR)
-#define pCAN_UCCNT          ((volatile uint16_t *)CAN_UCCNT)
-#define pCAN_UCRC           ((volatile uint16_t *)CAN_UCRC)
-#define pCAN_UCCNF          ((volatile uint16_t *)CAN_UCCNF)
-
-/* Mailbox Acceptance Masks                                             */
-#define pCAN_AM00L          ((volatile uint16_t *)CAN_AM00L)
-#define pCAN_AM00H          ((volatile uint16_t *)CAN_AM00H)
-#define pCAN_AM01L          ((volatile uint16_t *)CAN_AM01L)
-#define pCAN_AM01H          ((volatile uint16_t *)CAN_AM01H)
-#define pCAN_AM02L          ((volatile uint16_t *)CAN_AM02L)
-#define pCAN_AM02H          ((volatile uint16_t *)CAN_AM02H)
-#define pCAN_AM03L          ((volatile uint16_t *)CAN_AM03L)
-#define pCAN_AM03H          ((volatile uint16_t *)CAN_AM03H)
-#define pCAN_AM04L          ((volatile uint16_t *)CAN_AM04L)
-#define pCAN_AM04H          ((volatile uint16_t *)CAN_AM04H)
-#define pCAN_AM05L          ((volatile uint16_t *)CAN_AM05L)
-#define pCAN_AM05H          ((volatile uint16_t *)CAN_AM05H)
-#define pCAN_AM06L          ((volatile uint16_t *)CAN_AM06L)
-#define pCAN_AM06H          ((volatile uint16_t *)CAN_AM06H)
-#define pCAN_AM07L          ((volatile uint16_t *)CAN_AM07L)
-#define pCAN_AM07H          ((volatile uint16_t *)CAN_AM07H)
-#define pCAN_AM08L          ((volatile uint16_t *)CAN_AM08L)
-#define pCAN_AM08H          ((volatile uint16_t *)CAN_AM08H)
-#define pCAN_AM09L          ((volatile uint16_t *)CAN_AM09L)
-#define pCAN_AM09H          ((volatile uint16_t *)CAN_AM09H)
-#define pCAN_AM10L          ((volatile uint16_t *)CAN_AM10L)
-#define pCAN_AM10H          ((volatile uint16_t *)CAN_AM10H)
-#define pCAN_AM11L          ((volatile uint16_t *)CAN_AM11L)
-#define pCAN_AM11H          ((volatile uint16_t *)CAN_AM11H)
-#define pCAN_AM12L          ((volatile uint16_t *)CAN_AM12L)
-#define pCAN_AM12H          ((volatile uint16_t *)CAN_AM12H)
-#define pCAN_AM13L          ((volatile uint16_t *)CAN_AM13L)
-#define pCAN_AM13H          ((volatile uint16_t *)CAN_AM13H)
-#define pCAN_AM14L          ((volatile uint16_t *)CAN_AM14L)
-#define pCAN_AM14H          ((volatile uint16_t *)CAN_AM14H)
-#define pCAN_AM15L          ((volatile uint16_t *)CAN_AM15L)
-#define pCAN_AM15H          ((volatile uint16_t *)CAN_AM15H)
-
-#define pCAN_AM16L          ((volatile uint16_t *)CAN_AM16L)
-#define pCAN_AM16H          ((volatile uint16_t *)CAN_AM16H)
-#define pCAN_AM17L          ((volatile uint16_t *)CAN_AM17L)
-#define pCAN_AM17H          ((volatile uint16_t *)CAN_AM17H)
-#define pCAN_AM18L          ((volatile uint16_t *)CAN_AM18L)
-#define pCAN_AM18H          ((volatile uint16_t *)CAN_AM18H)
-#define pCAN_AM19L          ((volatile uint16_t *)CAN_AM19L)
-#define pCAN_AM19H          ((volatile uint16_t *)CAN_AM19H)
-#define pCAN_AM20L          ((volatile uint16_t *)CAN_AM20L)
-#define pCAN_AM20H          ((volatile uint16_t *)CAN_AM20H)
-#define pCAN_AM21L          ((volatile uint16_t *)CAN_AM21L)
-#define pCAN_AM21H          ((volatile uint16_t *)CAN_AM21H)
-#define pCAN_AM22L          ((volatile uint16_t *)CAN_AM22L)
-#define pCAN_AM22H          ((volatile uint16_t *)CAN_AM22H)
-#define pCAN_AM23L          ((volatile uint16_t *)CAN_AM23L)
-#define pCAN_AM23H          ((volatile uint16_t *)CAN_AM23H)
-#define pCAN_AM24L          ((volatile uint16_t *)CAN_AM24L)
-#define pCAN_AM24H          ((volatile uint16_t *)CAN_AM24H)
-#define pCAN_AM25L          ((volatile uint16_t *)CAN_AM25L)
-#define pCAN_AM25H          ((volatile uint16_t *)CAN_AM25H)
-#define pCAN_AM26L          ((volatile uint16_t *)CAN_AM26L)
-#define pCAN_AM26H          ((volatile uint16_t *)CAN_AM26H)
-#define pCAN_AM27L          ((volatile uint16_t *)CAN_AM27L)
-#define pCAN_AM27H          ((volatile uint16_t *)CAN_AM27H)
-#define pCAN_AM28L          ((volatile uint16_t *)CAN_AM28L)
-#define pCAN_AM28H          ((volatile uint16_t *)CAN_AM28H)
-#define pCAN_AM29L          ((volatile uint16_t *)CAN_AM29L)
-#define pCAN_AM29H          ((volatile uint16_t *)CAN_AM29H)
-#define pCAN_AM30L          ((volatile uint16_t *)CAN_AM30L)
-#define pCAN_AM30H          ((volatile uint16_t *)CAN_AM30H)
-#define pCAN_AM31L          ((volatile uint16_t *)CAN_AM31L)
-#define pCAN_AM31H          ((volatile uint16_t *)CAN_AM31H)
-
-/* CAN Acceptance Mask Area Macros  */
-#define pCAN_AM_L(x)        ((volatile uint16_t *)CAN_AM_L(x))
-#define pCAN_AM_H(x)        ((volatile uint16_t *)CAN_AM_H(x))
-
-/* Mailbox Registers                                                        */
-#define pCAN_MB00_DATA0     ((volatile uint16_t *)CAN_MB00_DATA0)
-#define pCAN_MB00_DATA1     ((volatile uint16_t *)CAN_MB00_DATA1)
-#define pCAN_MB00_DATA2     ((volatile uint16_t *)CAN_MB00_DATA2)
-#define pCAN_MB00_DATA3     ((volatile uint16_t *)CAN_MB00_DATA3)
-#define pCAN_MB00_LENGTH    ((volatile uint16_t *)CAN_MB00_LENGTH)
-#define pCAN_MB00_TIMESTAMP ((volatile uint16_t *)CAN_MB00_TIMESTAMP)
-#define pCAN_MB00_ID0       ((volatile uint16_t *)CAN_MB00_ID0)
-#define pCAN_MB00_ID1       ((volatile uint16_t *)CAN_MB00_ID1)
-
-#define pCAN_MB01_DATA0     ((volatile uint16_t *)CAN_MB01_DATA0)
-#define pCAN_MB01_DATA1     ((volatile uint16_t *)CAN_MB01_DATA1)
-#define pCAN_MB01_DATA2     ((volatile uint16_t *)CAN_MB01_DATA2)
-#define pCAN_MB01_DATA3     ((volatile uint16_t *)CAN_MB01_DATA3)
-#define pCAN_MB01_LENGTH    ((volatile uint16_t *)CAN_MB01_LENGTH)
-#define pCAN_MB01_TIMESTAMP ((volatile uint16_t *)CAN_MB01_TIMESTAMP)
-#define pCAN_MB01_ID0       ((volatile uint16_t *)CAN_MB01_ID0)
-#define pCAN_MB01_ID1       ((volatile uint16_t *)CAN_MB01_ID1)
-
-#define pCAN_MB02_DATA0     ((volatile uint16_t *)CAN_MB02_DATA0)
-#define pCAN_MB02_DATA1     ((volatile uint16_t *)CAN_MB02_DATA1)
-#define pCAN_MB02_DATA2     ((volatile uint16_t *)CAN_MB02_DATA2)
-#define pCAN_MB02_DATA3     ((volatile uint16_t *)CAN_MB02_DATA3)
-#define pCAN_MB02_LENGTH    ((volatile uint16_t *)CAN_MB02_LENGTH)
-#define pCAN_MB02_TIMESTAMP ((volatile uint16_t *)CAN_MB02_TIMESTAMP)
-#define pCAN_MB02_ID0       ((volatile uint16_t *)CAN_MB02_ID0)
-#define pCAN_MB02_ID1       ((volatile uint16_t *)CAN_MB02_ID1)
-
-#define pCAN_MB03_DATA0     ((volatile uint16_t *)CAN_MB03_DATA0)
-#define pCAN_MB03_DATA1     ((volatile uint16_t *)CAN_MB03_DATA1)
-#define pCAN_MB03_DATA2     ((volatile uint16_t *)CAN_MB03_DATA2)
-#define pCAN_MB03_DATA3     ((volatile uint16_t *)CAN_MB03_DATA3)
-#define pCAN_MB03_LENGTH    ((volatile uint16_t *)CAN_MB03_LENGTH)
-#define pCAN_MB03_TIMESTAMP ((volatile uint16_t *)CAN_MB03_TIMESTAMP)
-#define pCAN_MB03_ID0       ((volatile uint16_t *)CAN_MB03_ID0)
-#define pCAN_MB03_ID1       ((volatile uint16_t *)CAN_MB03_ID1)
-
-#define pCAN_MB04_DATA0     ((volatile uint16_t *)CAN_MB04_DATA0)
-#define pCAN_MB04_DATA1     ((volatile uint16_t *)CAN_MB04_DATA1)
-#define pCAN_MB04_DATA2     ((volatile uint16_t *)CAN_MB04_DATA2)
-#define pCAN_MB04_DATA3     ((volatile uint16_t *)CAN_MB04_DATA3)
-#define pCAN_MB04_LENGTH    ((volatile uint16_t *)CAN_MB04_LENGTH)
-#define pCAN_MB04_TIMESTAMP ((volatile uint16_t *)CAN_MB04_TIMESTAMP)
-#define pCAN_MB04_ID0       ((volatile uint16_t *)CAN_MB04_ID0)
-#define pCAN_MB04_ID1       ((volatile uint16_t *)CAN_MB04_ID1)
-
-#define pCAN_MB05_DATA0     ((volatile uint16_t *)CAN_MB05_DATA0)
-#define pCAN_MB05_DATA1     ((volatile uint16_t *)CAN_MB05_DATA1)
-#define pCAN_MB05_DATA2     ((volatile uint16_t *)CAN_MB05_DATA2)
-#define pCAN_MB05_DATA3     ((volatile uint16_t *)CAN_MB05_DATA3)
-#define pCAN_MB05_LENGTH    ((volatile uint16_t *)CAN_MB05_LENGTH)
-#define pCAN_MB05_TIMESTAMP ((volatile uint16_t *)CAN_MB05_TIMESTAMP)
-#define pCAN_MB05_ID0       ((volatile uint16_t *)CAN_MB05_ID0)
-#define pCAN_MB05_ID1       ((volatile uint16_t *)CAN_MB05_ID1)
-
-#define pCAN_MB06_DATA0     ((volatile uint16_t *)CAN_MB06_DATA0)
-#define pCAN_MB06_DATA1     ((volatile uint16_t *)CAN_MB06_DATA1)
-#define pCAN_MB06_DATA2     ((volatile uint16_t *)CAN_MB06_DATA2)
-#define pCAN_MB06_DATA3     ((volatile uint16_t *)CAN_MB06_DATA3)
-#define pCAN_MB06_LENGTH    ((volatile uint16_t *)CAN_MB06_LENGTH)
-#define pCAN_MB06_TIMESTAMP ((volatile uint16_t *)CAN_MB06_TIMESTAMP)
-#define pCAN_MB06_ID0       ((volatile uint16_t *)CAN_MB06_ID0)
-#define pCAN_MB06_ID1       ((volatile uint16_t *)CAN_MB06_ID1)
-
-#define pCAN_MB07_DATA0     ((volatile uint16_t *)CAN_MB07_DATA0)
-#define pCAN_MB07_DATA1     ((volatile uint16_t *)CAN_MB07_DATA1)
-#define pCAN_MB07_DATA2     ((volatile uint16_t *)CAN_MB07_DATA2)
-#define pCAN_MB07_DATA3     ((volatile uint16_t *)CAN_MB07_DATA3)
-#define pCAN_MB07_LENGTH    ((volatile uint16_t *)CAN_MB07_LENGTH)
-#define pCAN_MB07_TIMESTAMP ((volatile uint16_t *)CAN_MB07_TIMESTAMP)
-#define pCAN_MB07_ID0       ((volatile uint16_t *)CAN_MB07_ID0)
-#define pCAN_MB07_ID1       ((volatile uint16_t *)CAN_MB07_ID1)
-
-#define pCAN_MB08_DATA0     ((volatile uint16_t *)CAN_MB08_DATA0)
-#define pCAN_MB08_DATA1     ((volatile uint16_t *)CAN_MB08_DATA1)
-#define pCAN_MB08_DATA2     ((volatile uint16_t *)CAN_MB08_DATA2)
-#define pCAN_MB08_DATA3     ((volatile uint16_t *)CAN_MB08_DATA3)
-#define pCAN_MB08_LENGTH    ((volatile uint16_t *)CAN_MB08_LENGTH)
-#define pCAN_MB08_TIMESTAMP ((volatile uint16_t *)CAN_MB08_TIMESTAMP)
-#define pCAN_MB08_ID0       ((volatile uint16_t *)CAN_MB08_ID0)
-#define pCAN_MB08_ID1       ((volatile uint16_t *)CAN_MB08_ID1)
-
-#define pCAN_MB09_DATA0     ((volatile uint16_t *)CAN_MB09_DATA0)
-#define pCAN_MB09_DATA1     ((volatile uint16_t *)CAN_MB09_DATA1)
-#define pCAN_MB09_DATA2     ((volatile uint16_t *)CAN_MB09_DATA2)
-#define pCAN_MB09_DATA3     ((volatile uint16_t *)CAN_MB09_DATA3)
-#define pCAN_MB09_LENGTH    ((volatile uint16_t *)CAN_MB09_LENGTH)
-#define pCAN_MB09_TIMESTAMP ((volatile uint16_t *)CAN_MB09_TIMESTAMP)
-#define pCAN_MB09_ID0       ((volatile uint16_t *)CAN_MB09_ID0)
-#define pCAN_MB09_ID1       ((volatile uint16_t *)CAN_MB09_ID1)
-
-#define pCAN_MB10_DATA0     ((volatile uint16_t *)CAN_MB10_DATA0)
-#define pCAN_MB10_DATA1     ((volatile uint16_t *)CAN_MB10_DATA1)
-#define pCAN_MB10_DATA2     ((volatile uint16_t *)CAN_MB10_DATA2)
-#define pCAN_MB10_DATA3     ((volatile uint16_t *)CAN_MB10_DATA3)
-#define pCAN_MB10_LENGTH    ((volatile uint16_t *)CAN_MB10_LENGTH)
-#define pCAN_MB10_TIMESTAMP ((volatile uint16_t *)CAN_MB10_TIMESTAMP)
-#define pCAN_MB10_ID0       ((volatile uint16_t *)CAN_MB10_ID0)
-#define pCAN_MB10_ID1       ((volatile uint16_t *)CAN_MB10_ID1)
-
-#define pCAN_MB11_DATA0     ((volatile uint16_t *)CAN_MB11_DATA0)
-#define pCAN_MB11_DATA1     ((volatile uint16_t *)CAN_MB11_DATA1)
-#define pCAN_MB11_DATA2     ((volatile uint16_t *)CAN_MB11_DATA2)
-#define pCAN_MB11_DATA3     ((volatile uint16_t *)CAN_MB11_DATA3)
-#define pCAN_MB11_LENGTH    ((volatile uint16_t *)CAN_MB11_LENGTH)
-#define pCAN_MB11_TIMESTAMP ((volatile uint16_t *)CAN_MB11_TIMESTAMP)
-#define pCAN_MB11_ID0       ((volatile uint16_t *)CAN_MB11_ID0)
-#define pCAN_MB11_ID1       ((volatile uint16_t *)CAN_MB11_ID1)
-
-#define pCAN_MB12_DATA0     ((volatile uint16_t *)CAN_MB12_DATA0)
-#define pCAN_MB12_DATA1     ((volatile uint16_t *)CAN_MB12_DATA1)
-#define pCAN_MB12_DATA2     ((volatile uint16_t *)CAN_MB12_DATA2)
-#define pCAN_MB12_DATA3     ((volatile uint16_t *)CAN_MB12_DATA3)
-#define pCAN_MB12_LENGTH    ((volatile uint16_t *)CAN_MB12_LENGTH)
-#define pCAN_MB12_TIMESTAMP ((volatile uint16_t *)CAN_MB12_TIMESTAMP)
-#define pCAN_MB12_ID0       ((volatile uint16_t *)CAN_MB12_ID0)
-#define pCAN_MB12_ID1       ((volatile uint16_t *)CAN_MB12_ID1)
-
-#define pCAN_MB13_DATA0     ((volatile uint16_t *)CAN_MB13_DATA0)
-#define pCAN_MB13_DATA1     ((volatile uint16_t *)CAN_MB13_DATA1)
-#define pCAN_MB13_DATA2     ((volatile uint16_t *)CAN_MB13_DATA2)
-#define pCAN_MB13_DATA3     ((volatile uint16_t *)CAN_MB13_DATA3)
-#define pCAN_MB13_LENGTH    ((volatile uint16_t *)CAN_MB13_LENGTH)
-#define pCAN_MB13_TIMESTAMP ((volatile uint16_t *)CAN_MB13_TIMESTAMP)
-#define pCAN_MB13_ID0       ((volatile uint16_t *)CAN_MB13_ID0)
-#define pCAN_MB13_ID1       ((volatile uint16_t *)CAN_MB13_ID1)
-
-#define pCAN_MB14_DATA0     ((volatile uint16_t *)CAN_MB14_DATA0)
-#define pCAN_MB14_DATA1     ((volatile uint16_t *)CAN_MB14_DATA1)
-#define pCAN_MB14_DATA2     ((volatile uint16_t *)CAN_MB14_DATA2)
-#define pCAN_MB14_DATA3     ((volatile uint16_t *)CAN_MB14_DATA3)
-#define pCAN_MB14_LENGTH    ((volatile uint16_t *)CAN_MB14_LENGTH)
-#define pCAN_MB14_TIMESTAMP ((volatile uint16_t *)CAN_MB14_TIMESTAMP)
-#define pCAN_MB14_ID0       ((volatile uint16_t *)CAN_MB14_ID0)
-#define pCAN_MB14_ID1       ((volatile uint16_t *)CAN_MB14_ID1)
-
-#define pCAN_MB15_DATA0     ((volatile uint16_t *)CAN_MB15_DATA0)
-#define pCAN_MB15_DATA1     ((volatile uint16_t *)CAN_MB15_DATA1)
-#define pCAN_MB15_DATA2     ((volatile uint16_t *)CAN_MB15_DATA2)
-#define pCAN_MB15_DATA3     ((volatile uint16_t *)CAN_MB15_DATA3)
-#define pCAN_MB15_LENGTH    ((volatile uint16_t *)CAN_MB15_LENGTH)
-#define pCAN_MB15_TIMESTAMP ((volatile uint16_t *)CAN_MB15_TIMESTAMP)
-#define pCAN_MB15_ID0       ((volatile uint16_t *)CAN_MB15_ID0)
-#define pCAN_MB15_ID1       ((volatile uint16_t *)CAN_MB15_ID1)
-
-#define pCAN_MB16_DATA0     ((volatile uint16_t *)CAN_MB16_DATA0)
-#define pCAN_MB16_DATA1     ((volatile uint16_t *)CAN_MB16_DATA1)
-#define pCAN_MB16_DATA2     ((volatile uint16_t *)CAN_MB16_DATA2)
-#define pCAN_MB16_DATA3     ((volatile uint16_t *)CAN_MB16_DATA3)
-#define pCAN_MB16_LENGTH    ((volatile uint16_t *)CAN_MB16_LENGTH)
-#define pCAN_MB16_TIMESTAMP ((volatile uint16_t *)CAN_MB16_TIMESTAMP)
-#define pCAN_MB16_ID0       ((volatile uint16_t *)CAN_MB16_ID0)
-#define pCAN_MB16_ID1       ((volatile uint16_t *)CAN_MB16_ID1)
-
-#define pCAN_MB17_DATA0     ((volatile uint16_t *)CAN_MB17_DATA0)
-#define pCAN_MB17_DATA1     ((volatile uint16_t *)CAN_MB17_DATA1)
-#define pCAN_MB17_DATA2     ((volatile uint16_t *)CAN_MB17_DATA2)
-#define pCAN_MB17_DATA3     ((volatile uint16_t *)CAN_MB17_DATA3)
-#define pCAN_MB17_LENGTH    ((volatile uint16_t *)CAN_MB17_LENGTH)
-#define pCAN_MB17_TIMESTAMP ((volatile uint16_t *)CAN_MB17_TIMESTAMP)
-#define pCAN_MB17_ID0       ((volatile uint16_t *)CAN_MB17_ID0)
-#define pCAN_MB17_ID1       ((volatile uint16_t *)CAN_MB17_ID1)
-
-#define pCAN_MB18_DATA0     ((volatile uint16_t *)CAN_MB18_DATA0)
-#define pCAN_MB18_DATA1     ((volatile uint16_t *)CAN_MB18_DATA1)
-#define pCAN_MB18_DATA2     ((volatile uint16_t *)CAN_MB18_DATA2)
-#define pCAN_MB18_DATA3     ((volatile uint16_t *)CAN_MB18_DATA3)
-#define pCAN_MB18_LENGTH    ((volatile uint16_t *)CAN_MB18_LENGTH)
-#define pCAN_MB18_TIMESTAMP ((volatile uint16_t *)CAN_MB18_TIMESTAMP)
-#define pCAN_MB18_ID0       ((volatile uint16_t *)CAN_MB18_ID0)
-#define pCAN_MB18_ID1       ((volatile uint16_t *)CAN_MB18_ID1)
-
-#define pCAN_MB19_DATA0     ((volatile uint16_t *)CAN_MB19_DATA0)
-#define pCAN_MB19_DATA1     ((volatile uint16_t *)CAN_MB19_DATA1)
-#define pCAN_MB19_DATA2     ((volatile uint16_t *)CAN_MB19_DATA2)
-#define pCAN_MB19_DATA3     ((volatile uint16_t *)CAN_MB19_DATA3)
-#define pCAN_MB19_LENGTH    ((volatile uint16_t *)CAN_MB19_LENGTH)
-#define pCAN_MB19_TIMESTAMP ((volatile uint16_t *)CAN_MB19_TIMESTAMP)
-#define pCAN_MB19_ID0       ((volatile uint16_t *)CAN_MB19_ID0)
-#define pCAN_MB19_ID1       ((volatile uint16_t *)CAN_MB19_ID1)
-
-#define pCAN_MB20_DATA0     ((volatile uint16_t *)CAN_MB20_DATA0)
-#define pCAN_MB20_DATA1     ((volatile uint16_t *)CAN_MB20_DATA1)
-#define pCAN_MB20_DATA2     ((volatile uint16_t *)CAN_MB20_DATA2)
-#define pCAN_MB20_DATA3     ((volatile uint16_t *)CAN_MB20_DATA3)
-#define pCAN_MB20_LENGTH    ((volatile uint16_t *)CAN_MB20_LENGTH)
-#define pCAN_MB20_TIMESTAMP ((volatile uint16_t *)CAN_MB20_TIMESTAMP)
-#define pCAN_MB20_ID0       ((volatile uint16_t *)CAN_MB20_ID0)
-#define pCAN_MB20_ID1       ((volatile uint16_t *)CAN_MB20_ID1)
-
-#define pCAN_MB21_DATA0     ((volatile uint16_t *)CAN_MB21_DATA0)
-#define pCAN_MB21_DATA1     ((volatile uint16_t *)CAN_MB21_DATA1)
-#define pCAN_MB21_DATA2     ((volatile uint16_t *)CAN_MB21_DATA2)
-#define pCAN_MB21_DATA3     ((volatile uint16_t *)CAN_MB21_DATA3)
-#define pCAN_MB21_LENGTH    ((volatile uint16_t *)CAN_MB21_LENGTH)
-#define pCAN_MB21_TIMESTAMP ((volatile uint16_t *)CAN_MB21_TIMESTAMP)
-#define pCAN_MB21_ID0       ((volatile uint16_t *)CAN_MB21_ID0)
-#define pCAN_MB21_ID1       ((volatile uint16_t *)CAN_MB21_ID1)
-
-#define pCAN_MB22_DATA0     ((volatile uint16_t *)CAN_MB22_DATA0)
-#define pCAN_MB22_DATA1     ((volatile uint16_t *)CAN_MB22_DATA1)
-#define pCAN_MB22_DATA2     ((volatile uint16_t *)CAN_MB22_DATA2)
-#define pCAN_MB22_DATA3     ((volatile uint16_t *)CAN_MB22_DATA3)
-#define pCAN_MB22_LENGTH    ((volatile uint16_t *)CAN_MB22_LENGTH)
-#define pCAN_MB22_TIMESTAMP ((volatile uint16_t *)CAN_MB22_TIMESTAMP)
-#define pCAN_MB22_ID0       ((volatile uint16_t *)CAN_MB22_ID0)
-#define pCAN_MB22_ID1       ((volatile uint16_t *)CAN_MB22_ID1)
-
-#define pCAN_MB23_DATA0     ((volatile uint16_t *)CAN_MB23_DATA0)
-#define pCAN_MB23_DATA1     ((volatile uint16_t *)CAN_MB23_DATA1)
-#define pCAN_MB23_DATA2     ((volatile uint16_t *)CAN_MB23_DATA2)
-#define pCAN_MB23_DATA3     ((volatile uint16_t *)CAN_MB23_DATA3)
-#define pCAN_MB23_LENGTH    ((volatile uint16_t *)CAN_MB23_LENGTH)
-#define pCAN_MB23_TIMESTAMP ((volatile uint16_t *)CAN_MB23_TIMESTAMP)
-#define pCAN_MB23_ID0       ((volatile uint16_t *)CAN_MB23_ID0)
-#define pCAN_MB23_ID1       ((volatile uint16_t *)CAN_MB23_ID1)
-
-#define pCAN_MB24_DATA0     ((volatile uint16_t *)CAN_MB24_DATA0)
-#define pCAN_MB24_DATA1     ((volatile uint16_t *)CAN_MB24_DATA1)
-#define pCAN_MB24_DATA2     ((volatile uint16_t *)CAN_MB24_DATA2)
-#define pCAN_MB24_DATA3     ((volatile uint16_t *)CAN_MB24_DATA3)
-#define pCAN_MB24_LENGTH    ((volatile uint16_t *)CAN_MB24_LENGTH)
-#define pCAN_MB24_TIMESTAMP ((volatile uint16_t *)CAN_MB24_TIMESTAMP)
-#define pCAN_MB24_ID0       ((volatile uint16_t *)CAN_MB24_ID0)
-#define pCAN_MB24_ID1       ((volatile uint16_t *)CAN_MB24_ID1)
-
-#define pCAN_MB25_DATA0     ((volatile uint16_t *)CAN_MB25_DATA0)
-#define pCAN_MB25_DATA1     ((volatile uint16_t *)CAN_MB25_DATA1)
-#define pCAN_MB25_DATA2     ((volatile uint16_t *)CAN_MB25_DATA2)
-#define pCAN_MB25_DATA3     ((volatile uint16_t *)CAN_MB25_DATA3)
-#define pCAN_MB25_LENGTH    ((volatile uint16_t *)CAN_MB25_LENGTH)
-#define pCAN_MB25_TIMESTAMP ((volatile uint16_t *)CAN_MB25_TIMESTAMP)
-#define pCAN_MB25_ID0       ((volatile uint16_t *)CAN_MB25_ID0)
-#define pCAN_MB25_ID1       ((volatile uint16_t *)CAN_MB25_ID1)
-
-#define pCAN_MB26_DATA0     ((volatile uint16_t *)CAN_MB26_DATA0)
-#define pCAN_MB26_DATA1     ((volatile uint16_t *)CAN_MB26_DATA1)
-#define pCAN_MB26_DATA2     ((volatile uint16_t *)CAN_MB26_DATA2)
-#define pCAN_MB26_DATA3     ((volatile uint16_t *)CAN_MB26_DATA3)
-#define pCAN_MB26_LENGTH    ((volatile uint16_t *)CAN_MB26_LENGTH)
-#define pCAN_MB26_TIMESTAMP ((volatile uint16_t *)CAN_MB26_TIMESTAMP)
-#define pCAN_MB26_ID0       ((volatile uint16_t *)CAN_MB26_ID0)
-#define pCAN_MB26_ID1       ((volatile uint16_t *)CAN_MB26_ID1)
-
-#define pCAN_MB27_DATA0     ((volatile uint16_t *)CAN_MB27_DATA0)
-#define pCAN_MB27_DATA1     ((volatile uint16_t *)CAN_MB27_DATA1)
-#define pCAN_MB27_DATA2     ((volatile uint16_t *)CAN_MB27_DATA2)
-#define pCAN_MB27_DATA3     ((volatile uint16_t *)CAN_MB27_DATA3)
-#define pCAN_MB27_LENGTH    ((volatile uint16_t *)CAN_MB27_LENGTH)
-#define pCAN_MB27_TIMESTAMP ((volatile uint16_t *)CAN_MB27_TIMESTAMP)
-#define pCAN_MB27_ID0       ((volatile uint16_t *)CAN_MB27_ID0)
-#define pCAN_MB27_ID1       ((volatile uint16_t *)CAN_MB27_ID1)
-
-#define pCAN_MB28_DATA0     ((volatile uint16_t *)CAN_MB28_DATA0)
-#define pCAN_MB28_DATA1     ((volatile uint16_t *)CAN_MB28_DATA1)
-#define pCAN_MB28_DATA2     ((volatile uint16_t *)CAN_MB28_DATA2)
-#define pCAN_MB28_DATA3     ((volatile uint16_t *)CAN_MB28_DATA3)
-#define pCAN_MB28_LENGTH    ((volatile uint16_t *)CAN_MB28_LENGTH)
-#define pCAN_MB28_TIMESTAMP ((volatile uint16_t *)CAN_MB28_TIMESTAMP)
-#define pCAN_MB28_ID0       ((volatile uint16_t *)CAN_MB28_ID0)
-#define pCAN_MB28_ID1       ((volatile uint16_t *)CAN_MB28_ID1)
-
-#define pCAN_MB29_DATA0     ((volatile uint16_t *)CAN_MB29_DATA0)
-#define pCAN_MB29_DATA1     ((volatile uint16_t *)CAN_MB29_DATA1)
-#define pCAN_MB29_DATA2     ((volatile uint16_t *)CAN_MB29_DATA2)
-#define pCAN_MB29_DATA3     ((volatile uint16_t *)CAN_MB29_DATA3)
-#define pCAN_MB29_LENGTH    ((volatile uint16_t *)CAN_MB29_LENGTH)
-#define pCAN_MB29_TIMESTAMP ((volatile uint16_t *)CAN_MB29_TIMESTAMP)
-#define pCAN_MB29_ID0       ((volatile uint16_t *)CAN_MB29_ID0)
-#define pCAN_MB29_ID1       ((volatile uint16_t *)CAN_MB29_ID1)
-
-#define pCAN_MB30_DATA0     ((volatile uint16_t *)CAN_MB30_DATA0)
-#define pCAN_MB30_DATA1     ((volatile uint16_t *)CAN_MB30_DATA1)
-#define pCAN_MB30_DATA2     ((volatile uint16_t *)CAN_MB30_DATA2)
-#define pCAN_MB30_DATA3     ((volatile uint16_t *)CAN_MB30_DATA3)
-#define pCAN_MB30_LENGTH    ((volatile uint16_t *)CAN_MB30_LENGTH)
-#define pCAN_MB30_TIMESTAMP ((volatile uint16_t *)CAN_MB30_TIMESTAMP)
-#define pCAN_MB30_ID0       ((volatile uint16_t *)CAN_MB30_ID0)
-#define pCAN_MB30_ID1       ((volatile uint16_t *)CAN_MB30_ID1)
-
-#define pCAN_MB31_DATA0     ((volatile uint16_t *)CAN_MB31_DATA0)
-#define pCAN_MB31_DATA1     ((volatile uint16_t *)CAN_MB31_DATA1)
-#define pCAN_MB31_DATA2     ((volatile uint16_t *)CAN_MB31_DATA2)
-#define pCAN_MB31_DATA3     ((volatile uint16_t *)CAN_MB31_DATA3)
-#define pCAN_MB31_LENGTH    ((volatile uint16_t *)CAN_MB31_LENGTH)
-#define pCAN_MB31_TIMESTAMP ((volatile uint16_t *)CAN_MB31_TIMESTAMP)
-#define pCAN_MB31_ID0       ((volatile uint16_t *)CAN_MB31_ID0)
-#define pCAN_MB31_ID1       ((volatile uint16_t *)CAN_MB31_ID1)
-
-
-/* CAN Mailbox Area Macros      */
-#define pCAN_MB_ID1(x)          ((volatile uint16_t *)CAN_MB_ID1(x))
-#define pCAN_MB_ID0(x)          ((volatile uint16_t *)CAN_MB_ID0(x))
-#define pCAN_MB_TIMESTAMP(x)    ((volatile uint16_t *)CAN_MB_TIMESTAMP(x))
-#define pCAN_MB_LENGTH(x)       ((volatile uint16_t *)CAN_MB_LENGTH(x))
-#define pCAN_MB_DATA3(x)        ((volatile uint16_t *)CAN_MB_DATA3(x))
-#define pCAN_MB_DATA2(x)        ((volatile uint16_t *)CAN_MB_DATA2(x))
-#define pCAN_MB_DATA1(x)        ((volatile uint16_t *)CAN_MB_DATA1(x))
-#define pCAN_MB_DATA0(x)        ((volatile uint16_t *)CAN_MB_DATA0(x))
-
-
-/* Motor Control PWM1 Registers (0xFFC03000 - 0xFFC030FF) */
-#define pPWM1_CTRL     ((volatile uint16_t *)PWM1_CTRL)
-#define pPWM1_STAT     ((volatile uint16_t *)PWM1_STAT)
-#define pPWM1_TM       ((volatile uint16_t *)PWM1_TM)
-#define pPWM1_DT       ((volatile uint16_t *)PWM1_DT)
-#define pPWM1_GATE     ((volatile uint16_t *)PWM1_GATE)
-#define pPWM1_CHA      ((volatile uint16_t *)PWM1_CHA)
-#define pPWM1_CHB      ((volatile uint16_t *)PWM1_CHB)
-#define pPWM1_CHC      ((volatile uint16_t *)PWM1_CHC)
-#define pPWM1_SEG      ((volatile uint16_t *)PWM1_SEG)
-#define pPWM1_SYNCWT   ((volatile uint16_t *)PWM1_SYNCWT)
-#define pPWM1_CHAL     ((volatile uint16_t *)PWM1_CHAL)
-#define pPWM1_CHBL     ((volatile uint16_t *)PWM1_CHBL)
-#define pPWM1_CHCL     ((volatile uint16_t *)PWM1_CHCL)
-#define pPWM1_LSI      ((volatile uint16_t *)PWM1_LSI)
-#define pPWM1_STAT2    ((volatile uint16_t *)PWM1_STAT2)
-
-
-/* ADC Controller Module Registers (0xFFC03100 - 0xFFC031FF) */
-#define pACM_CTL        ((volatile uint16_t *)ACM_CTL)
-#define pACM_TC0        ((volatile uint16_t *)ACM_TC0)
-#define pACM_TC1        ((volatile uint16_t *)ACM_TC1)
-#define pACM_STAT       ((volatile uint16_t *)ACM_STAT)
-#define pACM_ES         ((volatile uint16_t *)ACM_ES)
-#define pACM_IMSK       ((volatile uint16_t *)ACM_IMSK)
-#define pACM_MS         ((volatile uint16_t *)ACM_MS)
-#define pACM_EMSK       ((volatile uint16_t *)ACM_EMSK)
-
-#define pACM_ER0        ((volatile uint16_t *)ACM_ER0)
-#define pACM_ER1        ((volatile uint16_t *)ACM_ER1)
-#define pACM_ER2        ((volatile uint16_t *)ACM_ER2)
-#define pACM_ER3        ((volatile uint16_t *)ACM_ER3)
-#define pACM_ER4        ((volatile uint16_t *)ACM_ER4)
-#define pACM_ER5        ((volatile uint16_t *)ACM_ER5)
-#define pACM_ER6        ((volatile uint16_t *)ACM_ER6)
-#define pACM_ER7        ((volatile uint16_t *)ACM_ER7)
-#define pACM_ER8        ((volatile uint16_t *)ACM_ER8)
-#define pACM_ER9        ((volatile uint16_t *)ACM_ER9)
-#define pACM_ER10       ((volatile uint16_t *)ACM_ER10)
-#define pACM_ER11       ((volatile uint16_t *)ACM_ER11)
-#define pACM_ER12       ((volatile uint16_t *)ACM_ER12)
-#define pACM_ER13       ((volatile uint16_t *)ACM_ER13)
-#define pACM_ER14       ((volatile uint16_t *)ACM_ER14)
-#define pACM_ER15       ((volatile uint16_t *)ACM_ER15)
-
-#define pACM_ET0        ((volatile uint32_t *)ACM_ET0)
-#define pACM_ET1        ((volatile uint32_t *)ACM_ET1)
-#define pACM_ET2        ((volatile uint32_t *)ACM_ET2)
-#define pACM_ET3        ((volatile uint32_t *)ACM_ET3)
-#define pACM_ET4        ((volatile uint32_t *)ACM_ET4)
-#define pACM_ET5        ((volatile uint32_t *)ACM_ET5)
-#define pACM_ET6        ((volatile uint32_t *)ACM_ET6)
-#define pACM_ET7        ((volatile uint32_t *)ACM_ET7)
-#define pACM_ET8        ((volatile uint32_t *)ACM_ET8)
-#define pACM_ET9        ((volatile uint32_t *)ACM_ET9)
-#define pACM_ET10       ((volatile uint32_t *)ACM_ET10)
-#define pACM_ET11       ((volatile uint32_t *)ACM_ET11)
-#define pACM_ET12       ((volatile uint32_t *)ACM_ET12)
-#define pACM_ET13       ((volatile uint32_t *)ACM_ET13)
-#define pACM_ET14       ((volatile uint32_t *)ACM_ET14)
-#define pACM_ET15       ((volatile uint32_t *)ACM_ET15)
-
-#define pACM_TMR0       ((volatile uint32_t *)ACM_TMR0)
-#define pACM_TMR1       ((volatile uint32_t *)ACM_TMR1)
-
-
-/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
-#define pPORTF_FER      ((volatile uint16_t *)PORTF_FER)
-#define pPORTG_FER      ((volatile uint16_t *)PORTG_FER)
-#define pPORTH_FER      ((volatile uint16_t *)PORTH_FER)
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define pPORTF_MUX        ((volatile uint16_t *)PORTF_MUX)
-#define pPORTG_MUX        ((volatile uint16_t *)PORTG_MUX)
-#define pPORTH_MUX        ((volatile uint16_t *)PORTH_MUX)
-#define pPORTF_HYSTERESIS ((volatile uint16_t *)PORTF_HYSTERESIS)
-#define pPORTG_HYSTERESIS ((volatile uint16_t *)PORTG_HYSTERESIS)
-#define pPORTH_HYSTERESIS ((volatile uint16_t *)PORTH_HYSTERESIS)
-
-#define pNONGPIO_DRIVE      ((volatile uint16_t *)NONGPIO_DRIVE)
-#define pNONGPIO_HYSTERESIS ((volatile uint16_t *)NONGPIO_HYSTERESIS)
-
-#define pFLASH_CONTROL        ((volatile uint16_t *)FLASH_CONTROL)
-#define pFLASH_CONTROL_SET    ((volatile uint16_t *)FLASH_CONTROL_SET)
-#define pFLASH_CONTROL_CLEAR  ((volatile uint16_t *)FLASH_CONTROL_CLEAR)
-
-
-/* Counter 1 Registers      (0xFFC03300 - 0xFFC033FF)*/
-#define pCNT1_CONFIG        ((volatile uint16_t *)CNT1_CONFIG)
-#define pCNT1_IMASK         ((volatile uint16_t *)CNT1_IMASK)
-#define pCNT1_STATUS        ((volatile uint16_t *)CNT1_STATUS)
-#define pCNT1_COMMAND       ((volatile uint16_t *)CNT1_COMMAND)
-#define pCNT1_DEBOUNCE      ((volatile uint16_t *)CNT1_DEBOUNCE)
-#define pCNT1_COUNTER       ((volatile uint32_t *)CNT1_COUNTER)
-#define pCNT1_MAX           ((volatile uint32_t *)CNT1_MAX)
-#define pCNT1_MIN           ((volatile uint32_t *)CNT1_MIN)
-
-
-/* SPI1 Controller      (0xFFC03400 - 0xFFC034FF)*/
-#define pSPI1_CTL       ((volatile uint16_t *)SPI1_CTL)
-#define pSPI1_FLG       ((volatile uint16_t *)SPI1_FLG)
-#define pSPI1_STAT      ((volatile uint16_t *)SPI1_STAT)
-#define pSPI1_TDBR      ((volatile uint16_t *)SPI1_TDBR)
-#define pSPI1_RDBR      ((volatile uint16_t *)SPI1_RDBR)
-#define pSPI1_BAUD      ((volatile uint16_t *)SPI1_BAUD)
-#define pSPI1_SHADOW        ((volatile uint16_t *)SPI1_SHADOW)
-
-
-/* Counter 0 Registers      (0xFFC03500 - 0xFFC035FF)*/
-#define pCNT0_CONFIG        ((volatile uint16_t *)CNT0_CONFIG)
-#define pCNT0_IMASK         ((volatile uint16_t *)CNT0_IMASK)
-#define pCNT0_STATUS        ((volatile uint16_t *)CNT0_STATUS)
-#define pCNT0_COMMAND       ((volatile uint16_t *)CNT0_COMMAND)
-#define pCNT0_DEBOUNCE      ((volatile uint16_t *)CNT0_DEBOUNCE)
-#define pCNT0_COUNTER       ((volatile uint32_t *)CNT0_COUNTER)
-#define pCNT0_MAX           ((volatile uint32_t *)CNT0_MAX)
-#define pCNT0_MIN           ((volatile uint32_t *)CNT0_MIN)
-
-
-/* Motor Control PWM0 Registers (0xFFC03700 - 0xFFC037FF) */
-#define pPWM0_CTRL     ((volatile uint16_t *)PWM0_CTRL)
-#define pPWM0_STAT     ((volatile uint16_t *)PWM0_STAT)
-#define pPWM0_TM       ((volatile uint16_t *)PWM0_TM)
-#define pPWM0_DT       ((volatile uint16_t *)PWM0_DT)
-#define pPWM0_GATE     ((volatile uint16_t *)PWM0_GATE)
-#define pPWM0_CHA      ((volatile uint16_t *)PWM0_CHA)
-#define pPWM0_CHB      ((volatile uint16_t *)PWM0_CHB)
-#define pPWM0_CHC      ((volatile uint16_t *)PWM0_CHC)
-#define pPWM0_SEG      ((volatile uint16_t *)PWM0_SEG)
-#define pPWM0_SYNCWT   ((volatile uint16_t *)PWM0_SYNCWT)
-#define pPWM0_CHAL     ((volatile uint16_t *)PWM0_CHAL)
-#define pPWM0_CHBL     ((volatile uint16_t *)PWM0_CHBL)
-#define pPWM0_CHCL     ((volatile uint16_t *)PWM0_CHCL)
-#define pPWM0_LSI      ((volatile uint16_t *)PWM0_LSI)
-#define pPWM0_STAT2    ((volatile uint16_t *)PWM0_STAT2)
-
-
-/* RSI Registers (0xFFC03800 - 0xFFC03CFF) */
-#define pRSI_PWR_CONTROL        ((volatile uint16_t *)RSI_PWR_CONTROL)
-#define pRSI_CLK_CONTROL        ((volatile uint16_t *)RSI_CLK_CONTROL)
-#define pRSI_ARGUMENT           ((volatile uint32_t *)RSI_ARGUMENT)
-#define pRSI_COMMAND            ((volatile uint16_t *)RSI_COMMAND)
-#define pRSI_RESP_CMD           ((volatile uint16_t *)RSI_RESP_CMD)
-#define pRSI_RESPONSE0          ((volatile uint32_t *)RSI_RESPONSE0)
-#define pRSI_RESPONSE1          ((volatile uint32_t *)RSI_RESPONSE1)
-#define pRSI_RESPONSE2          ((volatile uint32_t *)RSI_RESPONSE2)
-#define pRSI_RESPONSE3          ((volatile uint32_t *)RSI_RESPONSE3)
-#define pRSI_DATA_TIMER         ((volatile uint32_t *)RSI_DATA_TIMER)
-#define pRSI_DATA_LGTH          ((volatile uint16_t *)RSI_DATA_LGTH)
-#define pRSI_DATA_CONTROL       ((volatile uint16_t *)RSI_DATA_CONTROL)
-#define pRSI_DATA_CNT           ((volatile uint16_t *)RSI_DATA_CNT)
-#define pRSI_STATUS         ((volatile uint32_t *)RSI_STATUS)
-#define pRSI_STATUSCL           ((volatile uint16_t *)RSI_STATUSCL)
-#define pRSI_MASK0          ((volatile uint32_t *)RSI_MASK0)
-#define pRSI_MASK1          ((volatile uint32_t *)RSI_MASK1)
-#define pRSI_FIFO_CNT           ((volatile uint16_t *)RSI_FIFO_CNT)
-#define pRSI_CEATA_CONTROL      ((volatile uint16_t *)RSI_CEATA_CONTROL)
-#define pRSI_FIFO               ((volatile uint32_t *)RSI_FIFO)
-#define pRSI_ESTAT          ((volatile uint16_t *)RSI_ESTAT)
-#define pRSI_EMASK          ((volatile uint16_t *)RSI_EMASK)
-#define pRSI_CONFIG         ((volatile uint16_t *)RSI_CONFIG)
-#define pRSI_RD_WAIT_EN         ((volatile uint16_t *)RSI_RD_WAIT_EN)
-#define pRSI_PID0               ((volatile uint16_t *)RSI_PID0)
-#define pRSI_PID1               ((volatile uint16_t *)RSI_PID1)
-#define pRSI_PID2               ((volatile uint16_t *)RSI_PID2)
-#define pRSI_PID3               ((volatile uint16_t *)RSI_PID3)
-
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif  /*_CDEF_BF50X_H*/
diff --git a/libgloss/bfin/include/cdefBF512.h b/libgloss/bfin/include/cdefBF512.h
deleted file mode 100644
index 1288d12e5..000000000
--- a/libgloss/bfin/include/cdefBF512.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF512 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF512_H
-#define _CDEF_BF512_H
-
-/* include all Core registers and bit definitions */
-#include <defBF512.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <cdefBF51x_base.h>
-
-#endif /* _CDEF_BF512_H */
diff --git a/libgloss/bfin/include/cdefBF514.h b/libgloss/bfin/include/cdefBF514.h
deleted file mode 100644
index 59c1a45db..000000000
--- a/libgloss/bfin/include/cdefBF514.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF514 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF514_H
-#define _CDEF_BF514_H
-
-/* include all Core registers and bit definitions */
-#include <defBF514.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <cdefBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
-
-/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pSDH_PWR_CTL			((volatile unsigned short *)SDH_PWR_CTL)
-#define pSDH_CLK_CTL			((volatile unsigned short *)SDH_CLK_CTL)
-#define pSDH_ARGUMENT			((volatile unsigned long  *)SDH_ARGUMENT)
-#define pSDH_COMMAND			((volatile unsigned short *)SDH_COMMAND)
-#define pSDH_RESP_CMD			((volatile unsigned short *)SDH_RESP_CMD)
-#define pSDH_RESPONSE0			((volatile unsigned long  *)SDH_RESPONSE0)
-#define pSDH_RESPONSE1			((volatile unsigned long  *)SDH_RESPONSE1)
-#define pSDH_RESPONSE2			((volatile unsigned long  *)SDH_RESPONSE2)
-#define pSDH_RESPONSE3			((volatile unsigned long  *)SDH_RESPONSE3)
-#define pSDH_DATA_TIMER			((volatile unsigned long  *)SDH_DATA_TIMER)
-#define pSDH_DATA_LGTH			((volatile unsigned short *)SDH_DATA_LGTH)
-#define pSDH_DATA_CTL			((volatile unsigned short *)SDH_DATA_CTL)
-#define pSDH_DATA_CNT			((volatile unsigned short *)SDH_DATA_CNT)
-#define pSDH_STATUS			((volatile unsigned long  *)SDH_STATUS)
-#define pSDH_STATUS_CLR			((volatile unsigned short *)SDH_STATUS_CLR)
-#define pSDH_MASK0			((volatile unsigned long  *)SDH_MASK0)
-#define pSDH_MASK1			((volatile unsigned long  *)SDH_MASK1)
-#define pSDH_FIFO_CNT			((volatile unsigned short *)SDH_FIFO_CNT)
-#define pSDH_FIFO				((volatile unsigned long  *)SDH_FIFO)
-#define pSDH_E_STATUS			((volatile unsigned short *)SDH_E_STATUS)
-#define pSDH_E_MASK			((volatile unsigned short *)SDH_E_MASK)
-#define pSDH_CFG				((volatile unsigned short *)SDH_CFG)
-#define pSDH_RD_WAIT_EN			((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define pSDH_PID0				((volatile unsigned short *)SDH_PID0)
-#define pSDH_PID1				((volatile unsigned short *)SDH_PID1)
-#define pSDH_PID2				((volatile unsigned short *)SDH_PID2)
-#define pSDH_PID3				((volatile unsigned short *)SDH_PID3)
-#define pSDH_PID4				((volatile unsigned short *)SDH_PID4)
-#define pSDH_PID5				((volatile unsigned short *)SDH_PID5)
-#define pSDH_PID6				((volatile unsigned short *)SDH_PID6)
-#define pSDH_PID7				((volatile unsigned short *)SDH_PID7)
-
-
-/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pRSI_PWR_CONTROL		((volatile unsigned short *)RSI_PWR_CONTROL)
-#define pRSI_CLK_CONTROL		((volatile unsigned short *)RSI_CLK_CONTROL)
-#define pRSI_ARGUMENT			((volatile unsigned long  *)RSI_ARGUMENT)
-#define pRSI_COMMAND			((volatile unsigned short *)RSI_COMMAND)
-#define pRSI_RESP_CMD			((volatile unsigned short *)RSI_RESP_CMD)
-#define pRSI_RESPONSE0			((volatile unsigned long  *)RSI_RESPONSE0)
-#define pRSI_RESPONSE1			((volatile unsigned long  *)RSI_RESPONSE1)
-#define pRSI_RESPONSE2			((volatile unsigned long  *)RSI_RESPONSE2)
-#define pRSI_RESPONSE3			((volatile unsigned long  *)RSI_RESPONSE3)
-#define pRSI_DATA_TIMER			((volatile unsigned long  *)RSI_DATA_TIMER)
-#define pRSI_DATA_LGTH			((volatile unsigned short *)RSI_DATA_LGTH)
-#define pRSI_DATA_CONTROL		((volatile unsigned short *)RSI_DATA_CONTROL)
-#define pRSI_DATA_CNT			((volatile unsigned short *)RSI_DATA_CNT)
-#define pRSI_STATUS			((volatile unsigned long  *)RSI_STATUS)
-#define pRSI_STATUSCL			((volatile unsigned short *)RSI_STATUSCL)
-#define pRSI_MASK0			((volatile unsigned long  *)RSI_MASK0)
-#define pRSI_MASK1			((volatile unsigned long  *)RSI_MASK1)
-#define pRSI_FIFO_CNT			((volatile unsigned short *)RSI_FIFO_CNT)
-#define pRSI_CEATA_CONTROL		((volatile unsigned short *)RSI_CEATA_CONTROL)
-#define pRSI_FIFO				((volatile unsigned long  *)RSI_FIFO)
-#define pRSI_ESTAT			((volatile unsigned short *)RSI_ESTAT)
-#define pRSI_EMASK			((volatile unsigned short *)RSI_EMASK)
-#define pRSI_CONFIG			((volatile unsigned short *)RSI_CONFIG)
-#define pRSI_RD_WAIT_EN			((volatile unsigned short *)RSI_RD_WAIT_EN)
-#define pRSI_PID0				((volatile unsigned short *)RSI_PID0)
-#define pRSI_PID1				((volatile unsigned short *)RSI_PID1)
-#define pRSI_PID2				((volatile unsigned short *)RSI_PID2)
-#define pRSI_PID3				((volatile unsigned short *)RSI_PID3)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF514_H */
diff --git a/libgloss/bfin/include/cdefBF516.h b/libgloss/bfin/include/cdefBF516.h
deleted file mode 100644
index a7ee6a144..000000000
--- a/libgloss/bfin/include/cdefBF516.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF516 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF516_H
-#define _CDEF_BF516_H
-
-/* include all Core registers and bit definitions */
-#include <defBF516.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <cdefBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-
-/* 10/100 Ethernet Controller */
-#define pEMAC_OPMODE            	((volatile unsigned long  *)EMAC_OPMODE)
-#define pEMAC_ADDRLO            	((volatile unsigned long  *)EMAC_ADDRLO)
-#define pEMAC_ADDRHI            	((volatile unsigned long  *)EMAC_ADDRHI)
-#define pEMAC_HASHLO            	((volatile unsigned long  *)EMAC_HASHLO)
-#define pEMAC_HASHHI            	((volatile unsigned long  *)EMAC_HASHHI)
-#define pEMAC_STAADD            	((volatile unsigned long  *)EMAC_STAADD)
-#define pEMAC_STADAT            	((volatile unsigned long  *)EMAC_STADAT)
-#define pEMAC_FLC               	((volatile unsigned long  *)EMAC_FLC)
-#define pEMAC_VLAN1             	((volatile unsigned long  *)EMAC_VLAN1)
-#define pEMAC_VLAN2             	((volatile unsigned long  *)EMAC_VLAN2)
-#define pEMAC_WKUP_CTL          	((volatile unsigned long  *)EMAC_WKUP_CTL)
-#define pEMAC_WKUP_FFMSK0       	((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
-#define pEMAC_WKUP_FFMSK1       	((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
-#define pEMAC_WKUP_FFMSK2       	((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
-#define pEMAC_WKUP_FFMSK3       	((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
-#define pEMAC_WKUP_FFCMD        	((volatile unsigned long  *)EMAC_WKUP_FFCMD)
-#define pEMAC_WKUP_FFOFF        	((volatile unsigned long  *)EMAC_WKUP_FFOFF)
-#define pEMAC_WKUP_FFCRC0       	((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
-#define pEMAC_WKUP_FFCRC1       	((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
-
-#define pEMAC_SYSCTL            	((volatile unsigned long  *)EMAC_SYSCTL)
-#define pEMAC_SYSTAT            	((volatile unsigned long  *)EMAC_SYSTAT)
-#define pEMAC_RX_STAT           	((volatile unsigned long  *)EMAC_RX_STAT)
-#define pEMAC_RX_STKY           	((volatile unsigned long  *)EMAC_RX_STKY)
-#define pEMAC_RX_IRQE           	((volatile unsigned long  *)EMAC_RX_IRQE)
-#define pEMAC_TX_STAT          	((volatile unsigned long  *)EMAC_TX_STAT)
-#define pEMAC_TX_STKY          	((volatile unsigned long  *)EMAC_TX_STKY)
-#define pEMAC_TX_IRQE           	((volatile unsigned long  *)EMAC_TX_IRQE)
-
-#define pEMAC_MMC_CTL           	((volatile unsigned long  *)EMAC_MMC_CTL)
-#define pEMAC_MMC_RIRQS         	((volatile unsigned long  *)EMAC_MMC_RIRQS)
-#define pEMAC_MMC_RIRQE         	((volatile unsigned long  *)EMAC_MMC_RIRQE)
-#define pEMAC_MMC_TIRQS         	((volatile unsigned long  *)EMAC_MMC_TIRQS)
-#define pEMAC_MMC_TIRQE         	((volatile unsigned long  *)EMAC_MMC_TIRQE)
-
-#define pEMAC_RXC_OK            	((volatile unsigned long  *)EMAC_RXC_OK)
-#define pEMAC_RXC_FCS           	((volatile unsigned long  *)EMAC_RXC_FCS)
-#define pEMAC_RXC_ALIGN         	((volatile unsigned long  *)EMAC_RXC_ALIGN)
-#define pEMAC_RXC_OCTET         	((volatile unsigned long  *)EMAC_RXC_OCTET)
-#define pEMAC_RXC_DMAOVF        	((volatile unsigned long  *)EMAC_RXC_DMAOVF)
-#define pEMAC_RXC_UNICST        	((volatile unsigned long  *)EMAC_RXC_UNICST)
-#define pEMAC_RXC_MULTI         	((volatile unsigned long  *)EMAC_RXC_MULTI)
-#define pEMAC_RXC_BROAD         	((volatile unsigned long  *)EMAC_RXC_BROAD)
-#define pEMAC_RXC_LNERRI        	((volatile unsigned long  *)EMAC_RXC_LNERRI)
-#define pEMAC_RXC_LNERRO        	((volatile unsigned long  *)EMAC_RXC_LNERRO)
-#define pEMAC_RXC_LONG          	((volatile unsigned long  *)EMAC_RXC_LONG)
-#define pEMAC_RXC_MACCTL        	((volatile unsigned long  *)EMAC_RXC_MACCTL)
-#define pEMAC_RXC_OPCODE        	((volatile unsigned long  *)EMAC_RXC_OPCODE)
-#define pEMAC_RXC_PAUSE         	((volatile unsigned long  *)EMAC_RXC_PAUSE)
-#define pEMAC_RXC_ALLFRM        	((volatile unsigned long  *)EMAC_RXC_ALLFRM)
-#define pEMAC_RXC_ALLOCT        	((volatile unsigned long  *)EMAC_RXC_ALLOCT)
-#define pEMAC_RXC_TYPED         	((volatile unsigned long  *)EMAC_RXC_TYPED)
-#define pEMAC_RXC_SHORT         	((volatile unsigned long  *)EMAC_RXC_SHORT)
-#define pEMAC_RXC_EQ64          	((volatile unsigned long  *)EMAC_RXC_EQ64)
-#define pEMAC_RXC_LT128         	((volatile unsigned long  *)EMAC_RXC_LT128)
-#define pEMAC_RXC_LT256         	((volatile unsigned long  *)EMAC_RXC_LT256)
-#define pEMAC_RXC_LT512         	((volatile unsigned long  *)EMAC_RXC_LT512)
-#define pEMAC_RXC_LT1024        	((volatile unsigned long  *)EMAC_RXC_LT1024)
-#define pEMAC_RXC_GE1024        	((volatile unsigned long  *)EMAC_RXC_GE1024)
-
-#define pEMAC_TXC_OK            	((volatile unsigned long  *)EMAC_TXC_OK)
-#define pEMAC_TXC_1COL          	((volatile unsigned long  *)EMAC_TXC_1COL)
-#define pEMAC_TXC_GT1COL        	((volatile unsigned long  *)EMAC_TXC_GT1COL)
-#define pEMAC_TXC_OCTET         	((volatile unsigned long  *)EMAC_TXC_OCTET)
-#define pEMAC_TXC_DEFER         	((volatile unsigned long  *)EMAC_TXC_DEFER)
-#define pEMAC_TXC_LATECL        	((volatile unsigned long  *)EMAC_TXC_LATECL)
-#define pEMAC_TXC_XS_COL        	((volatile unsigned long  *)EMAC_TXC_XS_COL)
-#define pEMAC_TXC_DMAUND        	((volatile unsigned long  *)EMAC_TXC_DMAUND)
-#define pEMAC_TXC_CRSERR        	((volatile unsigned long  *)EMAC_TXC_CRSERR)
-#define pEMAC_TXC_UNICST        	((volatile unsigned long  *)EMAC_TXC_UNICST)
-#define pEMAC_TXC_MULTI         	((volatile unsigned long  *)EMAC_TXC_MULTI)
-#define pEMAC_TXC_BROAD         	((volatile unsigned long  *)EMAC_TXC_BROAD)
-#define pEMAC_TXC_XS_DFR        	((volatile unsigned long  *)EMAC_TXC_XS_DFR)
-#define pEMAC_TXC_MACCTL        	((volatile unsigned long  *)EMAC_TXC_MACCTL)
-#define pEMAC_TXC_ALLFRM        	((volatile unsigned long  *)EMAC_TXC_ALLFRM)
-#define pEMAC_TXC_ALLOCT        	((volatile unsigned long  *)EMAC_TXC_ALLOCT)
-#define pEMAC_TXC_EQ64          	((volatile unsigned long  *)EMAC_TXC_EQ64)
-#define pEMAC_TXC_LT128         	((volatile unsigned long  *)EMAC_TXC_LT128)
-#define pEMAC_TXC_LT256         	((volatile unsigned long  *)EMAC_TXC_LT256)
-#define pEMAC_TXC_LT512         	((volatile unsigned long  *)EMAC_TXC_LT512)
-#define pEMAC_TXC_LT1024        	((volatile unsigned long  *)EMAC_TXC_LT1024)
-#define pEMAC_TXC_GE1024        	((volatile unsigned long  *)EMAC_TXC_GE1024)
-#define pEMAC_TXC_ABORT         	((volatile unsigned long  *)EMAC_TXC_ABORT)
-
-
-/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pSDH_PWR_CTL			((volatile unsigned short *)SDH_PWR_CTL)
-#define pSDH_CLK_CTL			((volatile unsigned short *)SDH_CLK_CTL)
-#define pSDH_ARGUMENT			((volatile unsigned long  *)SDH_ARGUMENT)
-#define pSDH_COMMAND			((volatile unsigned short *)SDH_COMMAND)
-#define pSDH_RESP_CMD			((volatile unsigned short *)SDH_RESP_CMD)
-#define pSDH_RESPONSE0			((volatile unsigned long  *)SDH_RESPONSE0)
-#define pSDH_RESPONSE1			((volatile unsigned long  *)SDH_RESPONSE1)
-#define pSDH_RESPONSE2			((volatile unsigned long  *)SDH_RESPONSE2)
-#define pSDH_RESPONSE3			((volatile unsigned long  *)SDH_RESPONSE3)
-#define pSDH_DATA_TIMER			((volatile unsigned long  *)SDH_DATA_TIMER)
-#define pSDH_DATA_LGTH			((volatile unsigned short *)SDH_DATA_LGTH)
-#define pSDH_DATA_CTL			((volatile unsigned short *)SDH_DATA_CTL)
-#define pSDH_DATA_CNT			((volatile unsigned short *)SDH_DATA_CNT)
-#define pSDH_STATUS			((volatile unsigned long  *)SDH_STATUS)
-#define pSDH_STATUS_CLR			((volatile unsigned short *)SDH_STATUS_CLR)
-#define pSDH_MASK0			((volatile unsigned long  *)SDH_MASK0)
-#define pSDH_MASK1			((volatile unsigned long  *)SDH_MASK1)
-#define pSDH_FIFO_CNT			((volatile unsigned short *)SDH_FIFO_CNT)
-#define pSDH_FIFO				((volatile unsigned long  *)SDH_FIFO)
-#define pSDH_E_STATUS			((volatile unsigned short *)SDH_E_STATUS)
-#define pSDH_E_MASK			((volatile unsigned short *)SDH_E_MASK)
-#define pSDH_CFG				((volatile unsigned short *)SDH_CFG)
-#define pSDH_RD_WAIT_EN			((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define pSDH_PID0				((volatile unsigned short *)SDH_PID0)
-#define pSDH_PID1				((volatile unsigned short *)SDH_PID1)
-#define pSDH_PID2				((volatile unsigned short *)SDH_PID2)
-#define pSDH_PID3				((volatile unsigned short *)SDH_PID3)
-#define pSDH_PID4				((volatile unsigned short *)SDH_PID4)
-#define pSDH_PID5				((volatile unsigned short *)SDH_PID5)
-#define pSDH_PID6				((volatile unsigned short *)SDH_PID6)
-#define pSDH_PID7				((volatile unsigned short *)SDH_PID7)
-
-
-/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pRSI_PWR_CONTROL		((volatile unsigned short *)RSI_PWR_CONTROL)
-#define pRSI_CLK_CONTROL		((volatile unsigned short *)RSI_CLK_CONTROL)
-#define pRSI_ARGUMENT			((volatile unsigned long  *)RSI_ARGUMENT)
-#define pRSI_COMMAND			((volatile unsigned short *)RSI_COMMAND)
-#define pRSI_RESP_CMD			((volatile unsigned short *)RSI_RESP_CMD)
-#define pRSI_RESPONSE0			((volatile unsigned long  *)RSI_RESPONSE0)
-#define pRSI_RESPONSE1			((volatile unsigned long  *)RSI_RESPONSE1)
-#define pRSI_RESPONSE2			((volatile unsigned long  *)RSI_RESPONSE2)
-#define pRSI_RESPONSE3			((volatile unsigned long  *)RSI_RESPONSE3)
-#define pRSI_DATA_TIMER			((volatile unsigned long  *)RSI_DATA_TIMER)
-#define pRSI_DATA_LGTH			((volatile unsigned short *)RSI_DATA_LGTH)
-#define pRSI_DATA_CONTROL		((volatile unsigned short *)RSI_DATA_CONTROL)
-#define pRSI_DATA_CNT			((volatile unsigned short *)RSI_DATA_CNT)
-#define pRSI_STATUS			((volatile unsigned long  *)RSI_STATUS)
-#define pRSI_STATUSCL			((volatile unsigned short *)RSI_STATUSCL)
-#define pRSI_MASK0			((volatile unsigned long  *)RSI_MASK0)
-#define pRSI_MASK1			((volatile unsigned long  *)RSI_MASK1)
-#define pRSI_FIFO_CNT			((volatile unsigned short *)RSI_FIFO_CNT)
-#define pRSI_CEATA_CONTROL		((volatile unsigned short *)RSI_CEATA_CONTROL)
-#define pRSI_FIFO				((volatile unsigned long  *)RSI_FIFO)
-#define pRSI_ESTAT			((volatile unsigned short *)RSI_ESTAT)
-#define pRSI_EMASK			((volatile unsigned short *)RSI_EMASK)
-#define pRSI_CONFIG			((volatile unsigned short *)RSI_CONFIG)
-#define pRSI_RD_WAIT_EN			((volatile unsigned short *)RSI_RD_WAIT_EN)
-#define pRSI_PID0				((volatile unsigned short *)RSI_PID0)
-#define pRSI_PID1				((volatile unsigned short *)RSI_PID1)
-#define pRSI_PID2				((volatile unsigned short *)RSI_PID2)
-#define pRSI_PID3				((volatile unsigned short *)RSI_PID3)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF516_H */
diff --git a/libgloss/bfin/include/cdefBF518.h b/libgloss/bfin/include/cdefBF518.h
deleted file mode 100644
index 8455edcaf..000000000
--- a/libgloss/bfin/include/cdefBF518.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF518 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF518_H
-#define _CDEF_BF518_H
-
-/* include all Core registers and bit definitions */
-#include <defBF518.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
-
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <cdefBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
-
-/* 10/100 Ethernet Controller */
-#define pEMAC_OPMODE            	((volatile unsigned long  *)EMAC_OPMODE)
-#define pEMAC_ADDRLO            	((volatile unsigned long  *)EMAC_ADDRLO)
-#define pEMAC_ADDRHI            	((volatile unsigned long  *)EMAC_ADDRHI)
-#define pEMAC_HASHLO            	((volatile unsigned long  *)EMAC_HASHLO)
-#define pEMAC_HASHHI            	((volatile unsigned long  *)EMAC_HASHHI)
-#define pEMAC_STAADD            	((volatile unsigned long  *)EMAC_STAADD)
-#define pEMAC_STADAT            	((volatile unsigned long  *)EMAC_STADAT)
-#define pEMAC_FLC               	((volatile unsigned long  *)EMAC_FLC)
-#define pEMAC_VLAN1             	((volatile unsigned long  *)EMAC_VLAN1)
-#define pEMAC_VLAN2             	((volatile unsigned long  *)EMAC_VLAN2)
-#define pEMAC_WKUP_CTL          	((volatile unsigned long  *)EMAC_WKUP_CTL)
-#define pEMAC_WKUP_FFMSK0       	((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
-#define pEMAC_WKUP_FFMSK1       	((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
-#define pEMAC_WKUP_FFMSK2       	((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
-#define pEMAC_WKUP_FFMSK3       	((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
-#define pEMAC_WKUP_FFCMD        	((volatile unsigned long  *)EMAC_WKUP_FFCMD)
-#define pEMAC_WKUP_FFOFF        	((volatile unsigned long  *)EMAC_WKUP_FFOFF)
-#define pEMAC_WKUP_FFCRC0       	((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
-#define pEMAC_WKUP_FFCRC1       	((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
-
-#define pEMAC_SYSCTL            	((volatile unsigned long  *)EMAC_SYSCTL)
-#define pEMAC_SYSTAT            	((volatile unsigned long  *)EMAC_SYSTAT)
-#define pEMAC_RX_STAT           	((volatile unsigned long  *)EMAC_RX_STAT)
-#define pEMAC_RX_STKY           	((volatile unsigned long  *)EMAC_RX_STKY)
-#define pEMAC_RX_IRQE           	((volatile unsigned long  *)EMAC_RX_IRQE)
-#define pEMAC_TX_STAT          	((volatile unsigned long  *)EMAC_TX_STAT)
-#define pEMAC_TX_STKY          	((volatile unsigned long  *)EMAC_TX_STKY)
-#define pEMAC_TX_IRQE           	((volatile unsigned long  *)EMAC_TX_IRQE)
-
-#define pEMAC_MMC_CTL           	((volatile unsigned long  *)EMAC_MMC_CTL)
-#define pEMAC_MMC_RIRQS         	((volatile unsigned long  *)EMAC_MMC_RIRQS)
-#define pEMAC_MMC_RIRQE         	((volatile unsigned long  *)EMAC_MMC_RIRQE)
-#define pEMAC_MMC_TIRQS         	((volatile unsigned long  *)EMAC_MMC_TIRQS)
-#define pEMAC_MMC_TIRQE         	((volatile unsigned long  *)EMAC_MMC_TIRQE)
-
-#define pEMAC_RXC_OK            	((volatile unsigned long  *)EMAC_RXC_OK)
-#define pEMAC_RXC_FCS           	((volatile unsigned long  *)EMAC_RXC_FCS)
-#define pEMAC_RXC_ALIGN         	((volatile unsigned long  *)EMAC_RXC_ALIGN)
-#define pEMAC_RXC_OCTET         	((volatile unsigned long  *)EMAC_RXC_OCTET)
-#define pEMAC_RXC_DMAOVF        	((volatile unsigned long  *)EMAC_RXC_DMAOVF)
-#define pEMAC_RXC_UNICST        	((volatile unsigned long  *)EMAC_RXC_UNICST)
-#define pEMAC_RXC_MULTI         	((volatile unsigned long  *)EMAC_RXC_MULTI)
-#define pEMAC_RXC_BROAD         	((volatile unsigned long  *)EMAC_RXC_BROAD)
-#define pEMAC_RXC_LNERRI        	((volatile unsigned long  *)EMAC_RXC_LNERRI)
-#define pEMAC_RXC_LNERRO        	((volatile unsigned long  *)EMAC_RXC_LNERRO)
-#define pEMAC_RXC_LONG          	((volatile unsigned long  *)EMAC_RXC_LONG)
-#define pEMAC_RXC_MACCTL        	((volatile unsigned long  *)EMAC_RXC_MACCTL)
-#define pEMAC_RXC_OPCODE        	((volatile unsigned long  *)EMAC_RXC_OPCODE)
-#define pEMAC_RXC_PAUSE         	((volatile unsigned long  *)EMAC_RXC_PAUSE)
-#define pEMAC_RXC_ALLFRM        	((volatile unsigned long  *)EMAC_RXC_ALLFRM)
-#define pEMAC_RXC_ALLOCT        	((volatile unsigned long  *)EMAC_RXC_ALLOCT)
-#define pEMAC_RXC_TYPED         	((volatile unsigned long  *)EMAC_RXC_TYPED)
-#define pEMAC_RXC_SHORT         	((volatile unsigned long  *)EMAC_RXC_SHORT)
-#define pEMAC_RXC_EQ64          	((volatile unsigned long  *)EMAC_RXC_EQ64)
-#define pEMAC_RXC_LT128         	((volatile unsigned long  *)EMAC_RXC_LT128)
-#define pEMAC_RXC_LT256         	((volatile unsigned long  *)EMAC_RXC_LT256)
-#define pEMAC_RXC_LT512         	((volatile unsigned long  *)EMAC_RXC_LT512)
-#define pEMAC_RXC_LT1024        	((volatile unsigned long  *)EMAC_RXC_LT1024)
-#define pEMAC_RXC_GE1024        	((volatile unsigned long  *)EMAC_RXC_GE1024)
-
-#define pEMAC_TXC_OK            	((volatile unsigned long  *)EMAC_TXC_OK)
-#define pEMAC_TXC_1COL          	((volatile unsigned long  *)EMAC_TXC_1COL)
-#define pEMAC_TXC_GT1COL        	((volatile unsigned long  *)EMAC_TXC_GT1COL)
-#define pEMAC_TXC_OCTET         	((volatile unsigned long  *)EMAC_TXC_OCTET)
-#define pEMAC_TXC_DEFER         	((volatile unsigned long  *)EMAC_TXC_DEFER)
-#define pEMAC_TXC_LATECL        	((volatile unsigned long  *)EMAC_TXC_LATECL)
-#define pEMAC_TXC_XS_COL        	((volatile unsigned long  *)EMAC_TXC_XS_COL)
-#define pEMAC_TXC_DMAUND        	((volatile unsigned long  *)EMAC_TXC_DMAUND)
-#define pEMAC_TXC_CRSERR        	((volatile unsigned long  *)EMAC_TXC_CRSERR)
-#define pEMAC_TXC_UNICST        	((volatile unsigned long  *)EMAC_TXC_UNICST)
-#define pEMAC_TXC_MULTI         	((volatile unsigned long  *)EMAC_TXC_MULTI)
-#define pEMAC_TXC_BROAD         	((volatile unsigned long  *)EMAC_TXC_BROAD)
-#define pEMAC_TXC_XS_DFR        	((volatile unsigned long  *)EMAC_TXC_XS_DFR)
-#define pEMAC_TXC_MACCTL        	((volatile unsigned long  *)EMAC_TXC_MACCTL)
-#define pEMAC_TXC_ALLFRM        	((volatile unsigned long  *)EMAC_TXC_ALLFRM)
-#define pEMAC_TXC_ALLOCT        	((volatile unsigned long  *)EMAC_TXC_ALLOCT)
-#define pEMAC_TXC_EQ64          	((volatile unsigned long  *)EMAC_TXC_EQ64)
-#define pEMAC_TXC_LT128         	((volatile unsigned long  *)EMAC_TXC_LT128)
-#define pEMAC_TXC_LT256         	((volatile unsigned long  *)EMAC_TXC_LT256)
-#define pEMAC_TXC_LT512         	((volatile unsigned long  *)EMAC_TXC_LT512)
-#define pEMAC_TXC_LT1024        	((volatile unsigned long  *)EMAC_TXC_LT1024)
-#define pEMAC_TXC_GE1024        	((volatile unsigned long  *)EMAC_TXC_GE1024)
-#define pEMAC_TXC_ABORT         	((volatile unsigned long  *)EMAC_TXC_ABORT)
-
-
-/* EMAC PTP (IEEE 1588) (0xFFC030A0 - 0xFFC030EC)*/
-#define pEMAC_PTP_CTL			((volatile unsigned short *)EMAC_PTP_CTL)
-#define pEMAC_PTP_IE			((volatile unsigned short *)EMAC_PTP_IE)
-#define pEMAC_PTP_ISTAT			((volatile unsigned short *)EMAC_PTP_ISTAT)
-#define pEMAC_PTP_FOFF			((volatile unsigned long  *)EMAC_PTP_FOFF)
-#define pEMAC_PTP_FV1			((volatile unsigned long  *)EMAC_PTP_FV1)
-#define pEMAC_PTP_FV2			((volatile unsigned long  *)EMAC_PTP_FV2)
-#define pEMAC_PTP_FV3			((volatile unsigned long  *)EMAC_PTP_FV3)
-#define pEMAC_PTP_ADDEND		((volatile unsigned long  *)EMAC_PTP_ADDEND)
-#define pEMAC_PTP_ACCR			((volatile unsigned long  *)EMAC_PTP_ACCR)
-#define pEMAC_PTP_OFFSET		((volatile unsigned long  *)EMAC_PTP_OFFSET)
-#define pEMAC_PTP_TIMELO		((volatile unsigned long  *)EMAC_PTP_TIMELO)
-#define pEMAC_PTP_TIMEHI		((volatile unsigned long  *)EMAC_PTP_TIMEHI)
-#define pEMAC_PTP_RXSNAPLO		((volatile unsigned long  *)EMAC_PTP_RXSNAPLO)
-#define pEMAC_PTP_RXSNAPHI		((volatile unsigned long  *)EMAC_PTP_RXSNAPHI)
-#define pEMAC_PTP_TXSNAPLO		((volatile unsigned long  *)EMAC_PTP_TXSNAPLO)
-#define pEMAC_PTP_TXSNAPHI		((volatile unsigned long  *)EMAC_PTP_TXSNAPHI)
-#define pEMAC_PTP_ALARMLO		((volatile unsigned long  *)EMAC_PTP_ALARMLO)
-#define pEMAC_PTP_ALARMHI		((volatile unsigned long  *)EMAC_PTP_ALARMHI)
-#define pEMAC_PTP_ID_OFF		((volatile unsigned short *)EMAC_PTP_ID_OFF)
-#define pEMAC_PTP_ID_SNAP		((volatile unsigned long  *)EMAC_PTP_ID_SNAP)
-#define pEMAC_PTP_PPS_STARTLO		((volatile unsigned long  *)EMAC_PTP_PPS_STARTLO)
-#define pEMAC_PTP_PPS_STARTHI		((volatile unsigned long  *)EMAC_PTP_PPS_STARTHI)
-#define pEMAC_PTP_PPS_PERIOD		((volatile unsigned long  *)EMAC_PTP_PPS_PERIOD)
-
-
-/* SDH Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pSDH_PWR_CTL			((volatile unsigned short *)SDH_PWR_CTL)
-#define pSDH_CLK_CTL			((volatile unsigned short *)SDH_CLK_CTL)
-#define pSDH_ARGUMENT			((volatile unsigned long  *)SDH_ARGUMENT)
-#define pSDH_COMMAND			((volatile unsigned short *)SDH_COMMAND)
-#define pSDH_RESP_CMD			((volatile unsigned short *)SDH_RESP_CMD)
-#define pSDH_RESPONSE0			((volatile unsigned long  *)SDH_RESPONSE0)
-#define pSDH_RESPONSE1			((volatile unsigned long  *)SDH_RESPONSE1)
-#define pSDH_RESPONSE2			((volatile unsigned long  *)SDH_RESPONSE2)
-#define pSDH_RESPONSE3			((volatile unsigned long  *)SDH_RESPONSE3)
-#define pSDH_DATA_TIMER			((volatile unsigned long  *)SDH_DATA_TIMER)
-#define pSDH_DATA_LGTH			((volatile unsigned short *)SDH_DATA_LGTH)
-#define pSDH_DATA_CTL			((volatile unsigned short *)SDH_DATA_CTL)
-#define pSDH_DATA_CNT			((volatile unsigned short *)SDH_DATA_CNT)
-#define pSDH_STATUS			((volatile unsigned long  *)SDH_STATUS)
-#define pSDH_STATUS_CLR			((volatile unsigned short *)SDH_STATUS_CLR)
-#define pSDH_MASK0			((volatile unsigned long  *)SDH_MASK0)
-#define pSDH_MASK1			((volatile unsigned long  *)SDH_MASK1)
-#define pSDH_FIFO_CNT			((volatile unsigned short *)SDH_FIFO_CNT)
-#define pSDH_FIFO				((volatile unsigned long  *)SDH_FIFO)
-#define pSDH_E_STATUS			((volatile unsigned short *)SDH_E_STATUS)
-#define pSDH_E_MASK			((volatile unsigned short *)SDH_E_MASK)
-#define pSDH_CFG				((volatile unsigned short *)SDH_CFG)
-#define pSDH_RD_WAIT_EN			((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define pSDH_PID0				((volatile unsigned short *)SDH_PID0)
-#define pSDH_PID1				((volatile unsigned short *)SDH_PID1)
-#define pSDH_PID2				((volatile unsigned short *)SDH_PID2)
-#define pSDH_PID3				((volatile unsigned short *)SDH_PID3)
-#define pSDH_PID4				((volatile unsigned short *)SDH_PID4)
-#define pSDH_PID5				((volatile unsigned short *)SDH_PID5)
-#define pSDH_PID6				((volatile unsigned short *)SDH_PID6)
-#define pSDH_PID7				((volatile unsigned short *)SDH_PID7)
-
-
-/* RSI Registers (0xFFC03800 - 0xFFC03CFF)*/
-#define pRSI_PWR_CONTROL		((volatile unsigned short *)RSI_PWR_CONTROL)
-#define pRSI_CLK_CONTROL		((volatile unsigned short *)RSI_CLK_CONTROL)
-#define pRSI_ARGUMENT			((volatile unsigned long  *)RSI_ARGUMENT)
-#define pRSI_COMMAND			((volatile unsigned short *)RSI_COMMAND)
-#define pRSI_RESP_CMD			((volatile unsigned short *)RSI_RESP_CMD)
-#define pRSI_RESPONSE0			((volatile unsigned long  *)RSI_RESPONSE0)
-#define pRSI_RESPONSE1			((volatile unsigned long  *)RSI_RESPONSE1)
-#define pRSI_RESPONSE2			((volatile unsigned long  *)RSI_RESPONSE2)
-#define pRSI_RESPONSE3			((volatile unsigned long  *)RSI_RESPONSE3)
-#define pRSI_DATA_TIMER			((volatile unsigned long  *)RSI_DATA_TIMER)
-#define pRSI_DATA_LGTH			((volatile unsigned short *)RSI_DATA_LGTH)
-#define pRSI_DATA_CONTROL		((volatile unsigned short *)RSI_DATA_CONTROL)
-#define pRSI_DATA_CNT			((volatile unsigned short *)RSI_DATA_CNT)
-#define pRSI_STATUS			((volatile unsigned long  *)RSI_STATUS)
-#define pRSI_STATUSCL			((volatile unsigned short *)RSI_STATUSCL)
-#define pRSI_MASK0			((volatile unsigned long  *)RSI_MASK0)
-#define pRSI_MASK1			((volatile unsigned long  *)RSI_MASK1)
-#define pRSI_FIFO_CNT			((volatile unsigned short *)RSI_FIFO_CNT)
-#define pRSI_CEATA_CONTROL		((volatile unsigned short *)RSI_CEATA_CONTROL)
-#define pRSI_FIFO				((volatile unsigned long  *)RSI_FIFO)
-#define pRSI_ESTAT			((volatile unsigned short *)RSI_ESTAT)
-#define pRSI_EMASK			((volatile unsigned short *)RSI_EMASK)
-#define pRSI_CONFIG			((volatile unsigned short *)RSI_CONFIG)
-#define pRSI_RD_WAIT_EN			((volatile unsigned short *)RSI_RD_WAIT_EN)
-#define pRSI_PID0				((volatile unsigned short *)RSI_PID0)
-#define pRSI_PID1				((volatile unsigned short *)RSI_PID1)
-#define pRSI_PID2				((volatile unsigned short *)RSI_PID2)
-#define pRSI_PID3				((volatile unsigned short *)RSI_PID3)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF518_H */
diff --git a/libgloss/bfin/include/cdefBF51x_base.h b/libgloss/bfin/include/cdefBF51x_base.h
deleted file mode 100644
index 1b2ceece0..000000000
--- a/libgloss/bfin/include/cdefBF51x_base.h
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF51x_base.h
-**
-** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF51x peripherals.
-**
-***************************************************************/
-
-#ifndef _CDEF_BF51X_H
-#define _CDEF_BF51X_H
-
-#include <defBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-
-/* Clock and System Control 	(0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL 			((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 			((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 			((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 		((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID			((volatile unsigned long  *)CHIPID)
-
-
-/* System Interrupt Controller(0xFFC00100 - 0xFFC001FF) */
-#define pSWRST 			((volatile unsigned short *)SWRST)
-#define pSYSCR 			((volatile unsigned short *)SYSCR)
-
-#define pSIC_IMASK0 		((volatile unsigned long  *)SIC_IMASK0)			/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IMASK 		((volatile unsigned long  *)SIC_IMASK0)
-#define pSIC_IAR0 		((volatile unsigned long  *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile unsigned long  *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile unsigned long  *)SIC_IAR2)
-#define pSIC_IAR3 		((volatile unsigned long  *)SIC_IAR3)
-#define pSIC_ISR0 		((volatile unsigned long  *)SIC_ISR0)			/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_ISR 			((volatile unsigned long  *)SIC_ISR0)
-#define pSIC_IWR0 		((volatile unsigned long  *)SIC_IWR0)			/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IWR 			((volatile unsigned long  *)SIC_IWR0)
-
-/* SIC Additions to ADSP-BF51x(0xFFC0014C - 0xFFC00162) */
-#define pSIC_IMASK1		((volatile unsigned long  *)SIC_IMASK1)
-#define pSIC_IAR4			((volatile unsigned long  *)SIC_IAR4)
-#define pSIC_IAR5			((volatile unsigned long  *)SIC_IAR5)
-#define pSIC_IAR6			((volatile unsigned long  *)SIC_IAR6)
-#define pSIC_IAR7			((volatile unsigned long  *)SIC_IAR7)
-#define pSIC_ISR1			((volatile unsigned long  *)SIC_ISR1)
-#define pSIC_IWR1			((volatile unsigned long  *)SIC_IWR1)
-
-/* Watchdog Timer 		(0xFFC00200 - 0xFFC002FF) */
-#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile unsigned long  *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile unsigned long  *)WDOG_STAT)
-
-
-/* Real Time Clock 		(0xFFC00300 - 0xFFC003FF) */
-#define pRTC_STAT 		((volatile unsigned long  *)RTC_STAT)
-#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM 		((volatile unsigned long  *)RTC_ALARM)
-#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
-
-
-/* UART0 Controller 		(0xFFC00400 - 0xFFC004FF) */
-#define pUART0_THR 		((volatile unsigned short *)UART0_THR)
-#define pUART0_RBR 		((volatile unsigned short *)UART0_RBR)
-#define pUART0_DLL 		((volatile unsigned short *)UART0_DLL)
-#define pUART0_IER 		((volatile unsigned short *)UART0_IER)
-#define pUART0_DLH 		((volatile unsigned short *)UART0_DLH)
-#define pUART0_IIR 		((volatile unsigned short *)UART0_IIR)
-#define pUART0_LCR 		((volatile unsigned short *)UART0_LCR)
-#define pUART0_MCR 		((volatile unsigned short *)UART0_MCR)
-#define pUART0_LSR 		((volatile unsigned short *)UART0_LSR)
-#define pUART0_SCR 		((volatile unsigned short *)UART0_SCR)
-#define pUART0_GCTL 		((volatile unsigned short *)UART0_GCTL)
-
-
-/* SPI0 Controller  		(0xFFC00500 - 0xFFC005FF)*/
-#define pSPI0_CTL 		((volatile unsigned short *)SPI0_CTL)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_CTL			pSPI0_CTL
-#define pSPI0_FLG 		((volatile unsigned short *)SPI0_FLG)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_FLG			pSPI0_FLG
-#define pSPI0_STAT 		((volatile unsigned short *)SPI0_STAT)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_STAT			pSPI0_STAT
-#define pSPI0_TDBR 		((volatile unsigned short *)SPI0_TDBR)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_TDBR			pSPI0_TDBR
-#define pSPI0_RDBR 		((volatile unsigned short *)SPI0_RDBR)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_RDBR			pSPI0_RDBR
-#define pSPI0_BAUD 		((volatile unsigned short *)SPI0_BAUD)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_BAUD			pSPI0_BAUD
-#define pSPI0_SHADOW 		((volatile unsigned short *)SPI0_SHADOW)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSPI_SHADOW		pSPI0_SHADOW
-
-
-/* TIMER0-7 Registers 		(0xFFC00600 - 0xFFC006FF) */
-#define pTIMER0_CONFIG 		((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER 	((volatile unsigned long  *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 		((volatile unsigned long  *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 		((volatile unsigned long  *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 		((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER 	((volatile unsigned long  *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 		((volatile unsigned long  *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 		((volatile unsigned long  *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 		((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER 	((volatile unsigned long  *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 		((volatile unsigned long  *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 		((volatile unsigned long  *)TIMER2_WIDTH)
-
-#define pTIMER3_CONFIG 		((volatile unsigned short *)TIMER3_CONFIG)
-#define pTIMER3_COUNTER 	((volatile unsigned long  *)TIMER3_COUNTER)
-#define pTIMER3_PERIOD 		((volatile unsigned long  *)TIMER3_PERIOD)
-#define pTIMER3_WIDTH 		((volatile unsigned long  *)TIMER3_WIDTH)
-
-#define pTIMER4_CONFIG 		((volatile unsigned short *)TIMER4_CONFIG)
-#define pTIMER4_COUNTER 	((volatile unsigned long  *)TIMER4_COUNTER)
-#define pTIMER4_PERIOD 		((volatile unsigned long  *)TIMER4_PERIOD)
-#define pTIMER4_WIDTH 		((volatile unsigned long  *)TIMER4_WIDTH)
-
-#define pTIMER5_CONFIG 		((volatile unsigned short *)TIMER5_CONFIG)
-#define pTIMER5_COUNTER 	((volatile unsigned long  *)TIMER5_COUNTER)
-#define pTIMER5_PERIOD 		((volatile unsigned long  *)TIMER5_PERIOD)
-#define pTIMER5_WIDTH 		((volatile unsigned long  *)TIMER5_WIDTH)
-
-#define pTIMER6_CONFIG 		((volatile unsigned short *)TIMER6_CONFIG)
-#define pTIMER6_COUNTER 	((volatile unsigned long  *)TIMER6_COUNTER)
-#define pTIMER6_PERIOD 		((volatile unsigned long  *)TIMER6_PERIOD)
-#define pTIMER6_WIDTH 		((volatile unsigned long  *)TIMER6_WIDTH)
-
-#define pTIMER7_CONFIG 		((volatile unsigned short *)TIMER7_CONFIG)
-#define pTIMER7_COUNTER 	((volatile unsigned long  *)TIMER7_COUNTER)
-#define pTIMER7_PERIOD 		((volatile unsigned long  *)TIMER7_PERIOD)
-#define pTIMER7_WIDTH 		((volatile unsigned long  *)TIMER7_WIDTH)
-
-#define pTIMER_ENABLE 		((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE 		((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS		((volatile unsigned long  *)TIMER_STATUS)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define pPORTFIO 			((volatile unsigned short *)PORTFIO)
-#define pPORTFIO_CLEAR	 	((volatile unsigned short *)PORTFIO_CLEAR)
-#define pPORTFIO_SET	 	((volatile unsigned short *)PORTFIO_SET)
-#define pPORTFIO_TOGGLE 	((volatile unsigned short *)PORTFIO_TOGGLE)
-#define pPORTFIO_MASKA 		((volatile unsigned short *)PORTFIO_MASKA)
-#define pPORTFIO_MASKA_CLEAR 	((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
-#define pPORTFIO_MASKA_SET 	((volatile unsigned short *)PORTFIO_MASKA_SET)
-#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
-#define pPORTFIO_MASKB	 	((volatile unsigned short *)PORTFIO_MASKB)
-#define pPORTFIO_MASKB_CLEAR 	((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
-#define pPORTFIO_MASKB_SET 	((volatile unsigned short *)PORTFIO_MASKB_SET)
-#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
-#define pPORTFIO_DIR 		((volatile unsigned short *)PORTFIO_DIR)
-#define pPORTFIO_POLAR 		((volatile unsigned short *)PORTFIO_POLAR)
-#define pPORTFIO_EDGE 		((volatile unsigned short *)PORTFIO_EDGE)
-#define pPORTFIO_BOTH 		((volatile unsigned short *)PORTFIO_BOTH)
-#define pPORTFIO_INEN 		((volatile unsigned short *)PORTFIO_INEN)
-
-
-/* SPORT0 Controller 		(0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1 		((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 		((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV 	((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 		((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX32 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX32 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX16 		((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 		((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 		((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 		((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV 	((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 		((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 		((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 		((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 		((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 		((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 		((volatile unsigned long  *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 		((volatile unsigned long  *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 		((volatile unsigned long  *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 		((volatile unsigned long  *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 		((volatile unsigned long  *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 		((volatile unsigned long  *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 		((volatile unsigned long  *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 		((volatile unsigned long  *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1 		((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 		((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV 	((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 		((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX32 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX32 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX16 		((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 		((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 		((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 		((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV 	((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 		((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 		((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 		((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 		((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 		((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 		((volatile unsigned long  *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 		((volatile unsigned long  *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 		((volatile unsigned long  *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 		((volatile unsigned long  *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 		((volatile unsigned long  *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 		((volatile unsigned long  *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 		((volatile unsigned long  *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 		((volatile unsigned long  *)SPORT1_MRCS3)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define pEBIU_AMGCTL 		((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 		((volatile unsigned long  *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 		((volatile unsigned long  *)EBIU_AMBCTL1)
-#define pEBIU_SDGCTL 		((volatile unsigned long  *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 		((volatile unsigned short *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 		((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 		((volatile unsigned short *)EBIU_SDSTAT)
-
-
-/* DMA Traffic Control Registers	(0xFFC00B00 - 0xFFC00BFF) */
-#define	pDMA_TC_PER		((volatile unsigned short *)DMA_TC_PER)
-#define	pDMA_TC_CNT		((volatile unsigned short *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define	pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
-#define	pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
-
-/* DMA Controller			(0xFFC00C00 - FFC00FFF)*/
-#define pDMA0_CONFIG 		((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 		((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 		((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 		((volatile signed   short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 		((volatile signed   short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 	((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 	((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 	((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 		((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 		((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 		((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 		((volatile signed   short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 		((volatile signed   short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 	((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 	((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 		((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 		((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 		((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 		((volatile signed   short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 		((volatile signed   short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 	((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 	((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 		((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 		((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 		((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 		((volatile signed   short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 		((volatile signed   short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 	((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 	((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 	((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 		((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 		((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 		((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 		((volatile signed   short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 		((volatile signed   short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 	((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 	((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 	((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 		((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 		((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 		((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 		((volatile signed   short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 		((volatile signed   short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 	((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 	((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 	((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 		((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 		((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 		((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 		((volatile signed   short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 		((volatile signed   short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 	((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 	((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 	((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 		((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 		((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 		((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 		((volatile signed   short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 		((volatile signed   short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 	((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 	((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 	((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pDMA8_CONFIG 		((volatile unsigned short *)DMA8_CONFIG)
-#define pDMA8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
-#define pDMA8_X_COUNT 		((volatile unsigned short *)DMA8_X_COUNT)
-#define pDMA8_Y_COUNT 		((volatile unsigned short *)DMA8_Y_COUNT)
-#define pDMA8_X_MODIFY 		((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_MODIFY 		((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
-#define pDMA8_CURR_X_COUNT 	((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 	((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-#define pDMA8_IRQ_STATUS 	((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 	((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-
-#define pDMA9_CONFIG 		((volatile unsigned short *)DMA9_CONFIG)
-#define pDMA9_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
-#define pDMA9_X_COUNT 		((volatile unsigned short *)DMA9_X_COUNT)
-#define pDMA9_Y_COUNT 		((volatile unsigned short *)DMA9_Y_COUNT)
-#define pDMA9_X_MODIFY 		((volatile signed   short *)DMA9_X_MODIFY)
-#define pDMA9_Y_MODIFY 		((volatile signed   short *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
-#define pDMA9_CURR_X_COUNT 	((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT 	((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-#define pDMA9_IRQ_STATUS 	((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP 	((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-
-#define pDMA10_CONFIG 		((volatile unsigned short *)DMA10_CONFIG)
-#define pDMA10_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
-#define pDMA10_X_COUNT 		((volatile unsigned short *)DMA10_X_COUNT)
-#define pDMA10_Y_COUNT 		((volatile unsigned short *)DMA10_Y_COUNT)
-#define pDMA10_X_MODIFY 	((volatile signed   short *)DMA10_X_MODIFY)
-#define pDMA10_Y_MODIFY 	((volatile signed   short *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
-#define pDMA10_CURR_X_COUNT 	((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT 	((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-#define pDMA10_IRQ_STATUS 	((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-
-#define pDMA11_CONFIG 		((volatile unsigned short *)DMA11_CONFIG)
-#define pDMA11_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
-#define pDMA11_X_COUNT 		((volatile unsigned short *)DMA11_X_COUNT)
-#define pDMA11_Y_COUNT 		((volatile unsigned short *)DMA11_Y_COUNT)
-#define pDMA11_X_MODIFY 	((volatile signed   short *)DMA11_X_MODIFY)
-#define pDMA11_Y_MODIFY 	((volatile signed   short *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
-#define pDMA11_CURR_X_COUNT 	((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT 	((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-#define pDMA11_IRQ_STATUS 	((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG 	((volatile unsigned short *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT 	((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT 	((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY 	((volatile signed   short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY 	((volatile signed   short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR 	  (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG 	((volatile unsigned short *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT 	((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT 	((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY 	((volatile signed   short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY 	((volatile signed   short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG 	((volatile unsigned short *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT 	((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT 	((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY 	((volatile signed   short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY 	((volatile signed   short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG 	((volatile unsigned short *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT 	((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT 	((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY 	((volatile signed   short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY 	((volatile signed   short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define pPPI_CONTROL 		((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS 		((volatile unsigned short *)PPI_STATUS)
-#define pPPI_DELAY 		((volatile unsigned short *)PPI_DELAY)
-#define pPPI_COUNT 		((volatile unsigned short *)PPI_COUNT)
-#define pPPI_FRAME 		((volatile unsigned short *)PPI_FRAME)
-
-
-/* Two-Wire Interface 		(0xFFC01400 - 0xFFC014FF) */
-#define pTWI_CLKDIV		((volatile unsigned short *)TWI_CLKDIV)
-#define pTWI_CONTROL		((volatile unsigned short *)TWI_CONTROL)
-#define pTWI_SLAVE_CTL		((volatile unsigned short *)TWI_SLAVE_CTL)
-#define pTWI_SLAVE_STAT		((volatile unsigned short *)TWI_SLAVE_STAT)
-#define pTWI_SLAVE_ADDR		((volatile unsigned short *)TWI_SLAVE_ADDR)
-#define pTWI_MASTER_CTL		((volatile unsigned short *)TWI_MASTER_CTL)
-#define pTWI_MASTER_STAT	((volatile unsigned short *)TWI_MASTER_STAT)
-#define pTWI_MASTER_ADDR	((volatile unsigned short *)TWI_MASTER_ADDR)
-#define pTWI_INT_STAT		((volatile unsigned short *)TWI_INT_STAT)
-#define pTWI_INT_MASK		((volatile unsigned short *)TWI_INT_MASK)
-#define pTWI_FIFO_CTL		((volatile unsigned short *)TWI_FIFO_CTL)
-#define pTWI_FIFO_STAT		((volatile unsigned short *)TWI_FIFO_STAT)
-#define pTWI_XMT_DATA8		((volatile unsigned short *)TWI_XMT_DATA8)
-#define pTWI_XMT_DATA16		((volatile unsigned short *)TWI_XMT_DATA16)
-#define pTWI_RCV_DATA8		((volatile unsigned short *)TWI_RCV_DATA8)
-#define pTWI_RCV_DATA16		((volatile unsigned short *)TWI_RCV_DATA16)
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define pPORTGIO	 		((volatile unsigned short *)PORTGIO)
-#define pPORTGIO_CLEAR	 	((volatile unsigned short *)PORTGIO_CLEAR)
-#define pPORTGIO_SET	 	((volatile unsigned short *)PORTGIO_SET)
-#define pPORTGIO_TOGGLE 	((volatile unsigned short *)PORTGIO_TOGGLE)
-#define pPORTGIO_MASKA		((volatile unsigned short *)PORTGIO_MASKA)
-#define pPORTGIO_MASKA_CLEAR	((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
-#define pPORTGIO_MASKA_SET	((volatile unsigned short *)PORTGIO_MASKA_SET)
-#define pPORTGIO_MASKA_TOGGLE	((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
-#define pPORTGIO_MASKB		((volatile unsigned short *)PORTGIO_MASKB)
-#define pPORTGIO_MASKB_CLEAR	((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
-#define pPORTGIO_MASKB_SET	((volatile unsigned short *)PORTGIO_MASKB_SET)
-#define pPORTGIO_MASKB_TOGGLE	((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
-#define pPORTGIO_DIR 		((volatile unsigned short *)PORTGIO_DIR)
-#define pPORTGIO_POLAR 		((volatile unsigned short *)PORTGIO_POLAR)
-#define pPORTGIO_EDGE 		((volatile unsigned short *)PORTGIO_EDGE)
-#define pPORTGIO_BOTH 		((volatile unsigned short *)PORTGIO_BOTH)
-#define pPORTGIO_INEN 		((volatile unsigned short *)PORTGIO_INEN)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
-#define pPORTHIO	 		((volatile unsigned short *)PORTHIO)
-#define pPORTHIO_CLEAR	 	((volatile unsigned short *)PORTHIO_CLEAR)
-#define pPORTHIO_SET	 	((volatile unsigned short *)PORTHIO_SET)
-#define pPORTHIO_TOGGLE 	((volatile unsigned short *)PORTHIO_TOGGLE)
-#define pPORTHIO_MASKA		((volatile unsigned short *)PORTHIO_MASKA)
-#define pPORTHIO_MASKA_CLEAR	((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
-#define pPORTHIO_MASKA_SET	((volatile unsigned short *)PORTHIO_MASKA_SET)
-#define pPORTHIO_MASKA_TOGGLE	((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
-#define pPORTHIO_MASKB		((volatile unsigned short *)PORTHIO_MASKB)
-#define pPORTHIO_MASKB_CLEAR	((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
-#define pPORTHIO_MASKB_SET	((volatile unsigned short *)PORTHIO_MASKB_SET)
-#define pPORTHIO_MASKB_TOGGLE	((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
-#define pPORTHIO_DIR 		((volatile unsigned short *)PORTHIO_DIR)
-#define pPORTHIO_POLAR 		((volatile unsigned short *)PORTHIO_POLAR)
-#define pPORTHIO_EDGE 		((volatile unsigned short *)PORTHIO_EDGE)
-#define pPORTHIO_BOTH 		((volatile unsigned short *)PORTHIO_BOTH)
-#define pPORTHIO_INEN 		((volatile unsigned short *)PORTHIO_INEN)
-
-
-/* UART1 Controller 		(0xFFC02000 - 0xFFC020FF) */
-#define pUART1_THR 		((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR 		((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL 		((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER 		((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH 		((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR 		((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR 		((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR 		((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR 		((volatile unsigned short *)UART1_LSR)
-#define pUART1_SCR 		((volatile unsigned short *)UART1_SCR)
-#define pUART1_GCTL 		((volatile unsigned short *)UART1_GCTL)
-
-
-/* Pin Control Registers 	(0xFFC03200 - 0xFFC032FF) */
-#define pPORTF_FER		((volatile unsigned short *)PORTF_FER)
-#define pPORTG_FER		((volatile unsigned short *)PORTG_FER)
-#define pPORTH_FER		((volatile unsigned short *)PORTH_FER)
-
-
-/* Handshake MDMA Registers 	(0xFFC03300 - 0xFFC033FF) */
-#define pHMDMA0_CONTROL		((volatile unsigned short *)HMDMA0_CONTROL)
-#define pHMDMA0_ECINIT		((volatile unsigned short *)HMDMA0_ECINIT)
-#define pHMDMA0_BCINIT		((volatile unsigned short *)HMDMA0_BCINIT)
-#define pHMDMA0_ECURGENT	((volatile unsigned short *)HMDMA0_ECURGENT)
-#define pHMDMA0_ECOVERFLOW	((volatile unsigned short *)HMDMA0_ECOVERFLOW)
-#define pHMDMA0_ECOUNT		((volatile unsigned short *)HMDMA0_ECOUNT)
-#define pHMDMA0_BCOUNT		((volatile unsigned short *)HMDMA0_BCOUNT)
-
-#define pHMDMA1_CONTROL		((volatile unsigned short *)HMDMA1_CONTROL)
-#define pHMDMA1_ECINIT		((volatile unsigned short *)HMDMA1_ECINIT)
-#define pHMDMA1_BCINIT		((volatile unsigned short *)HMDMA1_BCINIT)
-#define pHMDMA1_ECURGENT	((volatile unsigned short *)HMDMA1_ECURGENT)
-#define pHMDMA1_ECOVERFLOW	((volatile unsigned short *)HMDMA1_ECOVERFLOW)
-#define pHMDMA1_ECOUNT		((volatile unsigned short *)HMDMA1_ECOUNT)
-#define pHMDMA1_BCOUNT		((volatile unsigned short *)HMDMA1_BCOUNT)
-
-
-/* GPIO PIN mux 			(0xFFC03210 - OxFFC03288) */
-#define pPORTF_MUX 		((volatile unsigned short *)PORTF_MUX)
-#define pPORTG_MUX 		((volatile unsigned short *)PORTG_MUX)
-#define pPORTH_MUX 		((volatile unsigned short *)PORTH_MUX)
-#define pPORTF_DRIVE 		((volatile unsigned short *)PORTF_DRIVE)
-#define pPORTG_DRIVE 		((volatile unsigned short *)PORTG_DRIVE)
-#define pPORTH_DRIVE 		((volatile unsigned short *)PORTH_DRIVE)
-#define pPORTF_HYSTERESIS 	((volatile unsigned short *)PORTF_HYSTERESIS)
-#define pPORTG_HYSTERESIS 	((volatile unsigned short *)PORTG_HYSTERESIS)
-#define pPORTH_HYSTERESIS 	((volatile unsigned short *)PORTH_HYSTERESIS)
-#define pNONGPIO_DRIVE 		((volatile unsigned short *)NONGPIO_DRIVE)
-#define pNONGPIO_HYSTERESIS 	((volatile unsigned short *)NONGPIO_HYSTERESIS)
-
-
-/* SPI1 Controller 		(0xFFC03400 - 0xFFC034FF)*/
-#define pSPI1_CTL 		((volatile unsigned short *)SPI1_CTL)
-#define pSPI1_FLG 		((volatile unsigned short *)SPI1_FLG)
-#define pSPI1_STAT 		((volatile unsigned short *)SPI1_STAT)
-#define pSPI1_TDBR 		((volatile unsigned short *)SPI1_TDBR)
-#define pSPI1_RDBR 		((volatile unsigned short *)SPI1_RDBR)
-#define pSPI1_BAUD 		((volatile unsigned short *)SPI1_BAUD)
-#define pSPI1_SHADOW 		((volatile unsigned short *)SPI1_SHADOW)
-
-
-/* Counter Registers 		(0xFFC03500 - 0xFFC035FF)*/
-#define pCNT_CONFIG 		((volatile unsigned short *)CNT_CONFIG)
-#define pCNT_IMASK 		((volatile unsigned short *)CNT_IMASK)
-#define pCNT_STATUS 		((volatile unsigned short *)CNT_STATUS)
-#define pCNT_COMMAND 		((volatile unsigned short *)CNT_COMMAND)
-#define pCNT_DEBOUNCE 		((volatile unsigned short *)CNT_DEBOUNCE)
-#define pCNT_COUNTER 		((volatile unsigned long *)CNT_COUNTER)
-#define pCNT_MAX 			((volatile unsigned long *)CNT_MAX)
-#define pCNT_MIN 			((volatile unsigned long *)CNT_MIN)
-
-
-/* OTP Registers 			(0xFFC03600 - 0xFFC036FF) */
-/* Security Registers */
-#define pSECURE_SYSSWT 		((volatile unsigned long *)SECURE_SYSSWT)
-#define pSECURE_CONTROL 	((volatile unsigned short *)SECURE_CONTROL)
-#define pSECURE_STATUS 		((volatile unsigned short *)SECURE_STATUS)
-
-/* OTP Read/Write Data Buffer Registers */
-#define pOTP_DATA0 		((volatile unsigned long *)OTP_DATA0)
-#define pOTP_DATA1 		((volatile unsigned long *)OTP_DATA1)
-#define pOTP_DATA2 		((volatile unsigned long *)OTP_DATA2)
-#define pOTP_DATA3 		((volatile unsigned long *)OTP_DATA3)
-
-
-/* PWM 3PHASE 			(0xFFC03700 - 0xFFC037FF)*/
-#define pPWM_CTRL			((volatile unsigned short *)PWM_CTRL)
-#define pPWM_STAT			((volatile unsigned short *)PWM_STAT)
-#define pPWM_TM			((volatile unsigned short *)PWM_TM)
-#define pPWM_DT			((volatile unsigned short *)PWM_DT)
-#define pPWM_GATE			((volatile unsigned short *)PWM_GATE)
-#define pPWM_CHA			((volatile unsigned short *)PWM_CHA)
-#define pPWM_CHB			((volatile unsigned short *)PWM_CHB)
-#define pPWM_CHC			((volatile unsigned short *)PWM_CHC)
-#define pPWM_SEG			((volatile unsigned short *)PWM_SEG)
-#define pPWM_SYNCWT		((volatile unsigned short *)PWM_SYNCWT)
-#define pPWM_CHAL			((volatile unsigned short *)PWM_CHAL)
-#define pPWM_CHBL			((volatile unsigned short *)PWM_CHBL)
-#define pPWM_CHCL			((volatile unsigned short *)PWM_CHCL)
-#define pPWM_LSI			((volatile unsigned short *)PWM_LSI)
-#define pPWM_STAT2		((volatile unsigned short *)PWM_STAT2)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-
-#endif  /*_CDEF_BF51X_H*/
diff --git a/libgloss/bfin/include/cdefBF522.h b/libgloss/bfin/include/cdefBF522.h
deleted file mode 100644
index cc13e4120..000000000
--- a/libgloss/bfin/include/cdefBF522.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF522 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* include all Core registers and bit definitions */
-#include <defBF522.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#endif /* _CDEF_BF522_H */
diff --git a/libgloss/bfin/include/cdefBF523.h b/libgloss/bfin/include/cdefBF523.h
deleted file mode 100644
index be25ee0cc..000000000
--- a/libgloss/bfin/include/cdefBF523.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF523 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF523_H
-#define _CDEF_BF523_H
-
-/* include all Core registers and bit definitions */
-#include <defBF523.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF523 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#endif /* _CDEF_BF523_H */
diff --git a/libgloss/bfin/include/cdefBF524.h b/libgloss/bfin/include/cdefBF524.h
deleted file mode 100644
index 580f7257b..000000000
--- a/libgloss/bfin/include/cdefBF524.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF524 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF524_H
-#define _CDEF_BF524_H
-
-/* include all Core registers and bit definitions */
-#include <defBF524.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF524 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF524 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-
-/* USB Endpoint 1 Control Registers */
-
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-
-/* USB Endpoint 2 Control Registers */
-
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-
-/* USB Endpoint 3 Control Registers */
-
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-
-/* USB Endpoint 4 Control Registers */
-
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-
-/* USB Endpoint 5 Control Registers */
-
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-
-/* USB Endpoint 6 Control Registers */
-
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-
-/* USB Endpoint 7 Control Registers */
-
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF524_H */
diff --git a/libgloss/bfin/include/cdefBF525.h b/libgloss/bfin/include/cdefBF525.h
deleted file mode 100644
index 608a9cb45..000000000
--- a/libgloss/bfin/include/cdefBF525.h
+++ /dev/null
@@ -1,294 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF525 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* include all Core registers and bit definitions */
-#include <defBF525.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-
-/* USB Endpoint 1 Control Registers */
-
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-
-/* USB Endpoint 2 Control Registers */
-
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-
-/* USB Endpoint 3 Control Registers */
-
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-
-/* USB Endpoint 4 Control Registers */
-
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-
-/* USB Endpoint 5 Control Registers */
-
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-
-/* USB Endpoint 6 Control Registers */
-
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-
-/* USB Endpoint 7 Control Registers */
-
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF525_H */
diff --git a/libgloss/bfin/include/cdefBF526.h b/libgloss/bfin/include/cdefBF526.h
deleted file mode 100644
index 7d8f4ff7d..000000000
--- a/libgloss/bfin/include/cdefBF526.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF526 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF526_H
-#define _CDEF_BF526_H
-
-/* include all Core registers and bit definitions */
-#include <defBF526.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF526 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF526 that are not in the common header */
-
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define pEMAC_OPMODE            ((volatile unsigned long  *)EMAC_OPMODE)
-#define pEMAC_ADDRLO            ((volatile unsigned long  *)EMAC_ADDRLO)
-#define pEMAC_ADDRHI            ((volatile unsigned long  *)EMAC_ADDRHI)
-#define pEMAC_HASHLO            ((volatile unsigned long  *)EMAC_HASHLO)
-#define pEMAC_HASHHI            ((volatile unsigned long  *)EMAC_HASHHI)
-#define pEMAC_STAADD            ((volatile unsigned long  *)EMAC_STAADD)
-#define pEMAC_STADAT            ((volatile unsigned long  *)EMAC_STADAT)
-#define pEMAC_FLC               ((volatile unsigned long  *)EMAC_FLC)
-#define pEMAC_VLAN1             ((volatile unsigned long  *)EMAC_VLAN1)
-#define pEMAC_VLAN2             ((volatile unsigned long  *)EMAC_VLAN2)
-#define pEMAC_WKUP_CTL          ((volatile unsigned long  *)EMAC_WKUP_CTL)
-#define pEMAC_WKUP_FFMSK0       ((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
-#define pEMAC_WKUP_FFMSK1       ((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
-#define pEMAC_WKUP_FFMSK2       ((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
-#define pEMAC_WKUP_FFMSK3       ((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
-#define pEMAC_WKUP_FFCMD        ((volatile unsigned long  *)EMAC_WKUP_FFCMD)
-#define pEMAC_WKUP_FFOFF        ((volatile unsigned long  *)EMAC_WKUP_FFOFF)
-#define pEMAC_WKUP_FFCRC0       ((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
-#define pEMAC_WKUP_FFCRC1       ((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
-
-#define pEMAC_SYSCTL            ((volatile unsigned long  *)EMAC_SYSCTL)
-#define pEMAC_SYSTAT            ((volatile unsigned long  *)EMAC_SYSTAT)
-#define pEMAC_RX_STAT           ((volatile unsigned long  *)EMAC_RX_STAT)
-#define pEMAC_RX_STKY           ((volatile unsigned long  *)EMAC_RX_STKY)
-#define pEMAC_RX_IRQE           ((volatile unsigned long  *)EMAC_RX_IRQE)
-#define pEMAC_TX_STAT           ((volatile unsigned long  *)EMAC_TX_STAT)
-#define pEMAC_TX_STKY           ((volatile unsigned long  *)EMAC_TX_STKY)
-#define pEMAC_TX_IRQE           ((volatile unsigned long  *)EMAC_TX_IRQE)
-
-#define pEMAC_MMC_CTL           ((volatile unsigned long  *)EMAC_MMC_CTL)
-#define pEMAC_MMC_RIRQS         ((volatile unsigned long  *)EMAC_MMC_RIRQS)
-#define pEMAC_MMC_RIRQE         ((volatile unsigned long  *)EMAC_MMC_RIRQE)
-#define pEMAC_MMC_TIRQS         ((volatile unsigned long  *)EMAC_MMC_TIRQS)
-#define pEMAC_MMC_TIRQE         ((volatile unsigned long  *)EMAC_MMC_TIRQE)
-
-#define pEMAC_RXC_OK            ((volatile unsigned long  *)EMAC_RXC_OK)
-#define pEMAC_RXC_FCS           ((volatile unsigned long  *)EMAC_RXC_FCS)
-#define pEMAC_RXC_ALIGN         ((volatile unsigned long  *)EMAC_RXC_ALIGN)
-#define pEMAC_RXC_OCTET         ((volatile unsigned long  *)EMAC_RXC_OCTET)
-#define pEMAC_RXC_DMAOVF        ((volatile unsigned long  *)EMAC_RXC_DMAOVF)
-#define pEMAC_RXC_UNICST        ((volatile unsigned long  *)EMAC_RXC_UNICST)
-#define pEMAC_RXC_MULTI         ((volatile unsigned long  *)EMAC_RXC_MULTI)
-#define pEMAC_RXC_BROAD         ((volatile unsigned long  *)EMAC_RXC_BROAD)
-#define pEMAC_RXC_LNERRI        ((volatile unsigned long  *)EMAC_RXC_LNERRI)
-#define pEMAC_RXC_LNERRO        ((volatile unsigned long  *)EMAC_RXC_LNERRO)
-#define pEMAC_RXC_LONG          ((volatile unsigned long  *)EMAC_RXC_LONG)
-#define pEMAC_RXC_MACCTL        ((volatile unsigned long  *)EMAC_RXC_MACCTL)
-#define pEMAC_RXC_OPCODE        ((volatile unsigned long  *)EMAC_RXC_OPCODE)
-#define pEMAC_RXC_PAUSE         ((volatile unsigned long  *)EMAC_RXC_PAUSE)
-#define pEMAC_RXC_ALLFRM        ((volatile unsigned long  *)EMAC_RXC_ALLFRM)
-#define pEMAC_RXC_ALLOCT        ((volatile unsigned long  *)EMAC_RXC_ALLOCT)
-#define pEMAC_RXC_TYPED         ((volatile unsigned long  *)EMAC_RXC_TYPED)
-#define pEMAC_RXC_SHORT         ((volatile unsigned long  *)EMAC_RXC_SHORT)
-#define pEMAC_RXC_EQ64          ((volatile unsigned long  *)EMAC_RXC_EQ64)
-#define pEMAC_RXC_LT128         ((volatile unsigned long  *)EMAC_RXC_LT128)
-#define pEMAC_RXC_LT256         ((volatile unsigned long  *)EMAC_RXC_LT256)
-#define pEMAC_RXC_LT512         ((volatile unsigned long  *)EMAC_RXC_LT512)
-#define pEMAC_RXC_LT1024        ((volatile unsigned long  *)EMAC_RXC_LT1024)
-#define pEMAC_RXC_GE1024        ((volatile unsigned long  *)EMAC_RXC_GE1024)
-
-#define pEMAC_TXC_OK            ((volatile unsigned long  *)EMAC_TXC_OK)
-#define pEMAC_TXC_1COL          ((volatile unsigned long  *)EMAC_TXC_1COL)
-#define pEMAC_TXC_GT1COL        ((volatile unsigned long  *)EMAC_TXC_GT1COL)
-#define pEMAC_TXC_OCTET         ((volatile unsigned long  *)EMAC_TXC_OCTET)
-#define pEMAC_TXC_DEFER         ((volatile unsigned long  *)EMAC_TXC_DEFER)
-#define pEMAC_TXC_LATECL        ((volatile unsigned long  *)EMAC_TXC_LATECL)
-#define pEMAC_TXC_XS_COL        ((volatile unsigned long  *)EMAC_TXC_XS_COL)
-#define pEMAC_TXC_DMAUND        ((volatile unsigned long  *)EMAC_TXC_DMAUND)
-#define pEMAC_TXC_CRSERR        ((volatile unsigned long  *)EMAC_TXC_CRSERR)
-#define pEMAC_TXC_UNICST        ((volatile unsigned long  *)EMAC_TXC_UNICST)
-#define pEMAC_TXC_MULTI         ((volatile unsigned long  *)EMAC_TXC_MULTI)
-#define pEMAC_TXC_BROAD         ((volatile unsigned long  *)EMAC_TXC_BROAD)
-#define pEMAC_TXC_XS_DFR        ((volatile unsigned long  *)EMAC_TXC_XS_DFR)
-#define pEMAC_TXC_MACCTL        ((volatile unsigned long  *)EMAC_TXC_MACCTL)
-#define pEMAC_TXC_ALLFRM        ((volatile unsigned long  *)EMAC_TXC_ALLFRM)
-#define pEMAC_TXC_ALLOCT        ((volatile unsigned long  *)EMAC_TXC_ALLOCT)
-#define pEMAC_TXC_EQ64          ((volatile unsigned long  *)EMAC_TXC_EQ64)
-#define pEMAC_TXC_LT128         ((volatile unsigned long  *)EMAC_TXC_LT128)
-#define pEMAC_TXC_LT256         ((volatile unsigned long  *)EMAC_TXC_LT256)
-#define pEMAC_TXC_LT512         ((volatile unsigned long  *)EMAC_TXC_LT512)
-#define pEMAC_TXC_LT1024        ((volatile unsigned long  *)EMAC_TXC_LT1024)
-#define pEMAC_TXC_GE1024        ((volatile unsigned long  *)EMAC_TXC_GE1024)
-#define pEMAC_TXC_ABORT         ((volatile unsigned long  *)EMAC_TXC_ABORT)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-
-/* USB Endpoint 1 Control Registers */
-
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-
-/* USB Endpoint 2 Control Registers */
-
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-
-/* USB Endpoint 3 Control Registers */
-
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-
-/* USB Endpoint 4 Control Registers */
-
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-
-/* USB Endpoint 5 Control Registers */
-
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-
-/* USB Endpoint 6 Control Registers */
-
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-
-/* USB Endpoint 7 Control Registers */
-
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF526_H */
diff --git a/libgloss/bfin/include/cdefBF527.h b/libgloss/bfin/include/cdefBF527.h
deleted file mode 100644
index aad8818e6..000000000
--- a/libgloss/bfin/include/cdefBF527.h
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF527 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* include all Core registers and bit definitions */
-#include <defBF527.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <cdefBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define pEMAC_OPMODE            ((volatile unsigned long  *)EMAC_OPMODE)
-#define pEMAC_ADDRLO            ((volatile unsigned long  *)EMAC_ADDRLO)
-#define pEMAC_ADDRHI            ((volatile unsigned long  *)EMAC_ADDRHI)
-#define pEMAC_HASHLO            ((volatile unsigned long  *)EMAC_HASHLO)
-#define pEMAC_HASHHI            ((volatile unsigned long  *)EMAC_HASHHI)
-#define pEMAC_STAADD            ((volatile unsigned long  *)EMAC_STAADD)
-#define pEMAC_STADAT            ((volatile unsigned long  *)EMAC_STADAT)
-#define pEMAC_FLC               ((volatile unsigned long  *)EMAC_FLC)
-#define pEMAC_VLAN1             ((volatile unsigned long  *)EMAC_VLAN1)
-#define pEMAC_VLAN2             ((volatile unsigned long  *)EMAC_VLAN2)
-#define pEMAC_WKUP_CTL          ((volatile unsigned long  *)EMAC_WKUP_CTL)
-#define pEMAC_WKUP_FFMSK0       ((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
-#define pEMAC_WKUP_FFMSK1       ((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
-#define pEMAC_WKUP_FFMSK2       ((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
-#define pEMAC_WKUP_FFMSK3       ((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
-#define pEMAC_WKUP_FFCMD        ((volatile unsigned long  *)EMAC_WKUP_FFCMD)
-#define pEMAC_WKUP_FFOFF        ((volatile unsigned long  *)EMAC_WKUP_FFOFF)
-#define pEMAC_WKUP_FFCRC0       ((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
-#define pEMAC_WKUP_FFCRC1       ((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
-
-#define pEMAC_SYSCTL            ((volatile unsigned long  *)EMAC_SYSCTL)
-#define pEMAC_SYSTAT            ((volatile unsigned long  *)EMAC_SYSTAT)
-#define pEMAC_RX_STAT           ((volatile unsigned long  *)EMAC_RX_STAT)
-#define pEMAC_RX_STKY           ((volatile unsigned long  *)EMAC_RX_STKY)
-#define pEMAC_RX_IRQE           ((volatile unsigned long  *)EMAC_RX_IRQE)
-#define pEMAC_TX_STAT           ((volatile unsigned long  *)EMAC_TX_STAT)
-#define pEMAC_TX_STKY           ((volatile unsigned long  *)EMAC_TX_STKY)
-#define pEMAC_TX_IRQE           ((volatile unsigned long  *)EMAC_TX_IRQE)
-
-#define pEMAC_MMC_CTL           ((volatile unsigned long  *)EMAC_MMC_CTL)
-#define pEMAC_MMC_RIRQS         ((volatile unsigned long  *)EMAC_MMC_RIRQS)
-#define pEMAC_MMC_RIRQE         ((volatile unsigned long  *)EMAC_MMC_RIRQE)
-#define pEMAC_MMC_TIRQS         ((volatile unsigned long  *)EMAC_MMC_TIRQS)
-#define pEMAC_MMC_TIRQE         ((volatile unsigned long  *)EMAC_MMC_TIRQE)
-
-#define pEMAC_RXC_OK            ((volatile unsigned long  *)EMAC_RXC_OK)
-#define pEMAC_RXC_FCS           ((volatile unsigned long  *)EMAC_RXC_FCS)
-#define pEMAC_RXC_ALIGN         ((volatile unsigned long  *)EMAC_RXC_ALIGN)
-#define pEMAC_RXC_OCTET         ((volatile unsigned long  *)EMAC_RXC_OCTET)
-#define pEMAC_RXC_DMAOVF        ((volatile unsigned long  *)EMAC_RXC_DMAOVF)
-#define pEMAC_RXC_UNICST        ((volatile unsigned long  *)EMAC_RXC_UNICST)
-#define pEMAC_RXC_MULTI         ((volatile unsigned long  *)EMAC_RXC_MULTI)
-#define pEMAC_RXC_BROAD         ((volatile unsigned long  *)EMAC_RXC_BROAD)
-#define pEMAC_RXC_LNERRI        ((volatile unsigned long  *)EMAC_RXC_LNERRI)
-#define pEMAC_RXC_LNERRO        ((volatile unsigned long  *)EMAC_RXC_LNERRO)
-#define pEMAC_RXC_LONG          ((volatile unsigned long  *)EMAC_RXC_LONG)
-#define pEMAC_RXC_MACCTL        ((volatile unsigned long  *)EMAC_RXC_MACCTL)
-#define pEMAC_RXC_OPCODE        ((volatile unsigned long  *)EMAC_RXC_OPCODE)
-#define pEMAC_RXC_PAUSE         ((volatile unsigned long  *)EMAC_RXC_PAUSE)
-#define pEMAC_RXC_ALLFRM        ((volatile unsigned long  *)EMAC_RXC_ALLFRM)
-#define pEMAC_RXC_ALLOCT        ((volatile unsigned long  *)EMAC_RXC_ALLOCT)
-#define pEMAC_RXC_TYPED         ((volatile unsigned long  *)EMAC_RXC_TYPED)
-#define pEMAC_RXC_SHORT         ((volatile unsigned long  *)EMAC_RXC_SHORT)
-#define pEMAC_RXC_EQ64          ((volatile unsigned long  *)EMAC_RXC_EQ64)
-#define pEMAC_RXC_LT128         ((volatile unsigned long  *)EMAC_RXC_LT128)
-#define pEMAC_RXC_LT256         ((volatile unsigned long  *)EMAC_RXC_LT256)
-#define pEMAC_RXC_LT512         ((volatile unsigned long  *)EMAC_RXC_LT512)
-#define pEMAC_RXC_LT1024        ((volatile unsigned long  *)EMAC_RXC_LT1024)
-#define pEMAC_RXC_GE1024        ((volatile unsigned long  *)EMAC_RXC_GE1024)
-
-#define pEMAC_TXC_OK            ((volatile unsigned long  *)EMAC_TXC_OK)
-#define pEMAC_TXC_1COL          ((volatile unsigned long  *)EMAC_TXC_1COL)
-#define pEMAC_TXC_GT1COL        ((volatile unsigned long  *)EMAC_TXC_GT1COL)
-#define pEMAC_TXC_OCTET         ((volatile unsigned long  *)EMAC_TXC_OCTET)
-#define pEMAC_TXC_DEFER         ((volatile unsigned long  *)EMAC_TXC_DEFER)
-#define pEMAC_TXC_LATECL        ((volatile unsigned long  *)EMAC_TXC_LATECL)
-#define pEMAC_TXC_XS_COL        ((volatile unsigned long  *)EMAC_TXC_XS_COL)
-#define pEMAC_TXC_DMAUND        ((volatile unsigned long  *)EMAC_TXC_DMAUND)
-#define pEMAC_TXC_CRSERR        ((volatile unsigned long  *)EMAC_TXC_CRSERR)
-#define pEMAC_TXC_UNICST        ((volatile unsigned long  *)EMAC_TXC_UNICST)
-#define pEMAC_TXC_MULTI         ((volatile unsigned long  *)EMAC_TXC_MULTI)
-#define pEMAC_TXC_BROAD         ((volatile unsigned long  *)EMAC_TXC_BROAD)
-#define pEMAC_TXC_XS_DFR        ((volatile unsigned long  *)EMAC_TXC_XS_DFR)
-#define pEMAC_TXC_MACCTL        ((volatile unsigned long  *)EMAC_TXC_MACCTL)
-#define pEMAC_TXC_ALLFRM        ((volatile unsigned long  *)EMAC_TXC_ALLFRM)
-#define pEMAC_TXC_ALLOCT        ((volatile unsigned long  *)EMAC_TXC_ALLOCT)
-#define pEMAC_TXC_EQ64          ((volatile unsigned long  *)EMAC_TXC_EQ64)
-#define pEMAC_TXC_LT128         ((volatile unsigned long  *)EMAC_TXC_LT128)
-#define pEMAC_TXC_LT256         ((volatile unsigned long  *)EMAC_TXC_LT256)
-#define pEMAC_TXC_LT512         ((volatile unsigned long  *)EMAC_TXC_LT512)
-#define pEMAC_TXC_LT1024        ((volatile unsigned long  *)EMAC_TXC_LT1024)
-#define pEMAC_TXC_GE1024        ((volatile unsigned long  *)EMAC_TXC_GE1024)
-#define pEMAC_TXC_ABORT         ((volatile unsigned long  *)EMAC_TXC_ABORT)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-
-/* USB Endpoint 1 Control Registers */
-
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-
-/* USB Endpoint 2 Control Registers */
-
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-
-/* USB Endpoint 3 Control Registers */
-
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-
-/* USB Endpoint 4 Control Registers */
-
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-
-/* USB Endpoint 5 Control Registers */
-
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-
-/* USB Endpoint 6 Control Registers */
-
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-
-/* USB Endpoint 7 Control Registers */
-
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF527_H */
diff --git a/libgloss/bfin/include/cdefBF52x_base.h b/libgloss/bfin/include/cdefBF52x_base.h
deleted file mode 100644
index 9d980e860..000000000
--- a/libgloss/bfin/include/cdefBF52x_base.h
+++ /dev/null
@@ -1,669 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF52x_base.h
-**
-** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
-**
-***************************************************************/
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <defBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* ==== begin from cdefBF534.h ==== */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-
-/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
-#define pPLL_CTL 		((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 		((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 		((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 		((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID      ((volatile unsigned long*)CHIPID)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
-#define pSWRST 			((volatile unsigned short *)SWRST)
-#define pSYSCR 			((volatile unsigned short *)SYSCR)
-
-#define pSIC_IMASK0 		((volatile unsigned long  *)SIC_IMASK0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IMASK 		((volatile unsigned long  *)SIC_IMASK0)
-
-#define pSIC_IAR0 		((volatile unsigned long  *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile unsigned long  *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile unsigned long  *)SIC_IAR2)
-#define pSIC_IAR3 		((volatile unsigned long  *)SIC_IAR3)
-
-#define pSIC_ISR0 		((volatile unsigned long  *)SIC_ISR0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_ISR 		((volatile unsigned long  *)SIC_ISR0)
-
-#define pSIC_IWR0 		((volatile unsigned long  *)SIC_IWR0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IWR 		((volatile unsigned long  *)SIC_IWR0)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define pSIC_IMASK1             ((volatile unsigned long  *)SIC_IMASK1)
-#define pSIC_IAR4               ((volatile unsigned long  *)SIC_IAR4)
-#define pSIC_IAR5               ((volatile unsigned long  *)SIC_IAR5)
-#define pSIC_IAR6               ((volatile unsigned long  *)SIC_IAR6)
-#define pSIC_IAR7               ((volatile unsigned long  *)SIC_IAR7)
-#define pSIC_ISR1               ((volatile unsigned long  *)SIC_ISR1)
-#define pSIC_IWR1               ((volatile unsigned long  *)SIC_IWR1)
-
-/* Watchdog Timer		(0xFFC00200 - 0xFFC002FF)									*/
-#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile unsigned long  *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile unsigned long  *)WDOG_STAT)
-
-
-/* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
-#define pRTC_STAT 		((volatile unsigned long  *)RTC_STAT)
-#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM 		((volatile unsigned long  *)RTC_ALARM)
-#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
-
-
-/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
-#define pUART0_THR 		((volatile unsigned short *)UART0_THR)
-#define pUART0_RBR 		((volatile unsigned short *)UART0_RBR)
-#define pUART0_DLL 		((volatile unsigned short *)UART0_DLL)
-#define pUART0_IER 		((volatile unsigned short *)UART0_IER)
-#define pUART0_DLH 		((volatile unsigned short *)UART0_DLH)
-#define pUART0_IIR 		((volatile unsigned short *)UART0_IIR)
-#define pUART0_LCR 		((volatile unsigned short *)UART0_LCR)
-#define pUART0_MCR 		((volatile unsigned short *)UART0_MCR)
-#define pUART0_LSR 		((volatile unsigned short *)UART0_LSR)
-#define pUART0_SCR 		((volatile unsigned short *)UART0_SCR)
-#define pUART0_GCTL 		((volatile unsigned short *)UART0_GCTL)
-
-
-/* SPI Controller		(0xFFC00500 - 0xFFC005FF)									*/
-#define pSPI_CTL 		((volatile unsigned short *)SPI_CTL)
-#define pSPI_FLG 		((volatile unsigned short *)SPI_FLG)
-#define pSPI_STAT 		((volatile unsigned short *)SPI_STAT)
-#define pSPI_TDBR 		((volatile unsigned short *)SPI_TDBR)
-#define pSPI_RDBR 		((volatile unsigned short *)SPI_RDBR)
-#define pSPI_BAUD 		((volatile unsigned short *)SPI_BAUD)
-#define pSPI_SHADOW 		((volatile unsigned short *)SPI_SHADOW)
-
-
-/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
-#define pTIMER0_CONFIG 		((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER 	((volatile unsigned long  *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 		((volatile unsigned long  *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 		((volatile unsigned long  *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 		((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER 	((volatile unsigned long  *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 		((volatile unsigned long  *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 		((volatile unsigned long  *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 		((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER 	((volatile unsigned long  *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 		((volatile unsigned long  *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 		((volatile unsigned long  *)TIMER2_WIDTH)
-
-#define pTIMER3_CONFIG 		((volatile unsigned short *)TIMER3_CONFIG)
-#define pTIMER3_COUNTER 	((volatile unsigned long  *)TIMER3_COUNTER)
-#define pTIMER3_PERIOD 		((volatile unsigned long  *)TIMER3_PERIOD)
-#define pTIMER3_WIDTH 		((volatile unsigned long  *)TIMER3_WIDTH)
-
-#define pTIMER4_CONFIG 		((volatile unsigned short *)TIMER4_CONFIG)
-#define pTIMER4_COUNTER 	((volatile unsigned long  *)TIMER4_COUNTER)
-#define pTIMER4_PERIOD 		((volatile unsigned long  *)TIMER4_PERIOD)
-#define pTIMER4_WIDTH 		((volatile unsigned long  *)TIMER4_WIDTH)
-
-#define pTIMER5_CONFIG 		((volatile unsigned short *)TIMER5_CONFIG)
-#define pTIMER5_COUNTER 	((volatile unsigned long  *)TIMER5_COUNTER)
-#define pTIMER5_PERIOD 		((volatile unsigned long  *)TIMER5_PERIOD)
-#define pTIMER5_WIDTH 		((volatile unsigned long  *)TIMER5_WIDTH)
-
-#define pTIMER6_CONFIG 		((volatile unsigned short *)TIMER6_CONFIG)
-#define pTIMER6_COUNTER 	((volatile unsigned long  *)TIMER6_COUNTER)
-#define pTIMER6_PERIOD 		((volatile unsigned long  *)TIMER6_PERIOD)
-#define pTIMER6_WIDTH 		((volatile unsigned long  *)TIMER6_WIDTH)
-
-#define pTIMER7_CONFIG 		((volatile unsigned short *)TIMER7_CONFIG)
-#define pTIMER7_COUNTER 	((volatile unsigned long  *)TIMER7_COUNTER)
-#define pTIMER7_PERIOD 		((volatile unsigned long  *)TIMER7_PERIOD)
-#define pTIMER7_WIDTH 		((volatile unsigned long  *)TIMER7_WIDTH)
-
-#define pTIMER_ENABLE 		((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE 		((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS		((volatile unsigned long  *)TIMER_STATUS)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)								*/
-#define pPORTFIO	 	((volatile unsigned short *)PORTFIO)
-#define pPORTFIO_CLEAR	 	((volatile unsigned short *)PORTFIO_CLEAR)
-#define pPORTFIO_SET	 	((volatile unsigned short *)PORTFIO_SET)
-#define pPORTFIO_TOGGLE 	((volatile unsigned short *)PORTFIO_TOGGLE)
-#define pPORTFIO_MASKA 		((volatile unsigned short *)PORTFIO_MASKA)
-#define pPORTFIO_MASKA_CLEAR 	((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
-#define pPORTFIO_MASKA_SET 	((volatile unsigned short *)PORTFIO_MASKA_SET)
-#define pPORTFIO_MASKA_TOGGLE 	((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
-#define pPORTFIO_MASKB	 	((volatile unsigned short *)PORTFIO_MASKB)
-#define pPORTFIO_MASKB_CLEAR 	((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
-#define pPORTFIO_MASKB_SET 	((volatile unsigned short *)PORTFIO_MASKB_SET)
-#define pPORTFIO_MASKB_TOGGLE 	((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
-#define pPORTFIO_DIR 		((volatile unsigned short *)PORTFIO_DIR)
-#define pPORTFIO_POLAR 		((volatile unsigned short *)PORTFIO_POLAR)
-#define pPORTFIO_EDGE 		((volatile unsigned short *)PORTFIO_EDGE)
-#define pPORTFIO_BOTH 		((volatile unsigned short *)PORTFIO_BOTH)
-#define pPORTFIO_INEN 		((volatile unsigned short *)PORTFIO_INEN)
-
-
-/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)								*/
-#define pSPORT0_TCR1 		((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 		((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV 	((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 		((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX32 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX32 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX16 		((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 		((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 		((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 		((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV 	((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 		((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 		((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 		((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 		((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 		((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 		((volatile unsigned long  *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 		((volatile unsigned long  *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 		((volatile unsigned long  *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 		((volatile unsigned long  *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 		((volatile unsigned long  *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 		((volatile unsigned long  *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 		((volatile unsigned long  *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 		((volatile unsigned long  *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)								*/
-#define pSPORT1_TCR1 		((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 		((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV 	((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 		((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX32 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX32 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX16 		((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 		((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 		((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 		((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV 	((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 		((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 		((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 		((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 		((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 		((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 		((volatile unsigned long  *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 		((volatile unsigned long  *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 		((volatile unsigned long  *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 		((volatile unsigned long  *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 		((volatile unsigned long  *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 		((volatile unsigned long  *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 		((volatile unsigned long  *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 		((volatile unsigned long  *)SPORT1_MRCS3)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)							*/
-#define pEBIU_AMGCTL 		((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 		((volatile unsigned long  *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 		((volatile unsigned long  *)EBIU_AMBCTL1)
-#define pEBIU_SDGCTL 		((volatile unsigned long  *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 		((volatile unsigned short *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 		((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 		((volatile unsigned short *)EBIU_SDSTAT)
-
-
-/* DMA Traffic Control Registers													*/
-#define	pDMA_TC_PER		((volatile unsigned short *)DMA_TC_PER)
-#define	pDMA_TC_CNT		((volatile unsigned short *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define	pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
-#define	pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
-
-/* DMA Controller																	*/
-#define pDMA0_CONFIG 		((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 		((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 		((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 		((volatile signed   short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 		((volatile signed   short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 	((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 	((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 	((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 		((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 		((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 		((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 		((volatile signed   short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 		((volatile signed   short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 	((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 	((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 		((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 		((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 		((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 		((volatile signed   short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 		((volatile signed   short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 	((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 	((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 		((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 		((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 		((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 		((volatile signed   short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 		((volatile signed   short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 	((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 	((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 	((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 		((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 		((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 		((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 		((volatile signed   short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 		((volatile signed   short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 	((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 	((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 	((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 		((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 		((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 		((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 		((volatile signed   short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 		((volatile signed   short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 	((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 	((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 	((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 		((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 		((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 		((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 		((volatile signed   short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 		((volatile signed   short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 	((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 	((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 	((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 		((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 		((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 		((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 		((volatile signed   short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 		((volatile signed   short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 	((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 	((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 	((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pDMA8_CONFIG 		((volatile unsigned short *)DMA8_CONFIG)
-#define pDMA8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
-#define pDMA8_X_COUNT 		((volatile unsigned short *)DMA8_X_COUNT)
-#define pDMA8_Y_COUNT 		((volatile unsigned short *)DMA8_Y_COUNT)
-#define pDMA8_X_MODIFY 		((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_MODIFY 		((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
-#define pDMA8_CURR_X_COUNT 	((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 	((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-#define pDMA8_IRQ_STATUS 	((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 	((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-
-#define pDMA9_CONFIG 		((volatile unsigned short *)DMA9_CONFIG)
-#define pDMA9_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
-#define pDMA9_X_COUNT 		((volatile unsigned short *)DMA9_X_COUNT)
-#define pDMA9_Y_COUNT 		((volatile unsigned short *)DMA9_Y_COUNT)
-#define pDMA9_X_MODIFY 		((volatile signed   short *)DMA9_X_MODIFY)
-#define pDMA9_Y_MODIFY 		((volatile signed   short *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
-#define pDMA9_CURR_X_COUNT 	((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT 	((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-#define pDMA9_IRQ_STATUS 	((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP 	((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-
-#define pDMA10_CONFIG 		((volatile unsigned short *)DMA10_CONFIG)
-#define pDMA10_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
-#define pDMA10_X_COUNT 		((volatile unsigned short *)DMA10_X_COUNT)
-#define pDMA10_Y_COUNT 		((volatile unsigned short *)DMA10_Y_COUNT)
-#define pDMA10_X_MODIFY 	((volatile signed   short *)DMA10_X_MODIFY)
-#define pDMA10_Y_MODIFY 	((volatile signed   short *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
-#define pDMA10_CURR_X_COUNT 	((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT 	((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-#define pDMA10_IRQ_STATUS 	((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP 	((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-
-#define pDMA11_CONFIG 		((volatile unsigned short *)DMA11_CONFIG)
-#define pDMA11_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
-#define pDMA11_X_COUNT 		((volatile unsigned short *)DMA11_X_COUNT)
-#define pDMA11_Y_COUNT 		((volatile unsigned short *)DMA11_Y_COUNT)
-#define pDMA11_X_MODIFY 	((volatile signed   short *)DMA11_X_MODIFY)
-#define pDMA11_Y_MODIFY 	((volatile signed   short *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
-#define pDMA11_CURR_X_COUNT 	((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT 	((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-#define pDMA11_IRQ_STATUS 	((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP 	((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG 	((volatile unsigned short *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT 	((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT 	((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY 	((volatile signed   short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY 	((volatile signed   short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG 	((volatile unsigned short *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT 	((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT 	((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY 	((volatile signed   short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY 	((volatile signed   short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG 	((volatile unsigned short *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT 	((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT 	((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY 	((volatile signed   short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY 	((volatile signed   short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG 	((volatile unsigned short *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT 	((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT 	((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY 	((volatile signed   short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY 	((volatile signed   short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)							*/
-#define pPPI_CONTROL 		((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS 		((volatile unsigned short *)PPI_STATUS)
-#define pPPI_DELAY 		((volatile unsigned short *)PPI_DELAY)
-#define pPPI_COUNT 		((volatile unsigned short *)PPI_COUNT)
-#define pPPI_FRAME 		((volatile unsigned short *)PPI_FRAME)
-
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
-#define pTWI_CLKDIV		((volatile unsigned short *)TWI_CLKDIV)
-#define pTWI_CONTROL		((volatile unsigned short *)TWI_CONTROL)
-#define pTWI_SLAVE_CTL		((volatile unsigned short *)TWI_SLAVE_CTL)
-#define pTWI_SLAVE_STAT		((volatile unsigned short *)TWI_SLAVE_STAT)
-#define pTWI_SLAVE_ADDR		((volatile unsigned short *)TWI_SLAVE_ADDR)
-#define pTWI_MASTER_CTL		((volatile unsigned short *)TWI_MASTER_CTL)
-#define pTWI_MASTER_STAT	((volatile unsigned short *)TWI_MASTER_STAT)
-#define pTWI_MASTER_ADDR	((volatile unsigned short *)TWI_MASTER_ADDR)
-#define pTWI_INT_STAT		((volatile unsigned short *)TWI_INT_STAT)
-#define pTWI_INT_MASK		((volatile unsigned short *)TWI_INT_MASK)
-#define pTWI_FIFO_CTL		((volatile unsigned short *)TWI_FIFO_CTL)
-#define pTWI_FIFO_STAT		((volatile unsigned short *)TWI_FIFO_STAT)
-#define pTWI_XMT_DATA8		((volatile unsigned short *)TWI_XMT_DATA8)
-#define pTWI_XMT_DATA16		((volatile unsigned short *)TWI_XMT_DATA16)
-#define pTWI_RCV_DATA8		((volatile unsigned short *)TWI_RCV_DATA8)
-#define pTWI_RCV_DATA16		((volatile unsigned short *)TWI_RCV_DATA16)
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/
-#define pPORTGIO	 	((volatile unsigned short *)PORTGIO)
-#define pPORTGIO_CLEAR	 	((volatile unsigned short *)PORTGIO_CLEAR)
-#define pPORTGIO_SET	 	((volatile unsigned short *)PORTGIO_SET)
-#define pPORTGIO_TOGGLE 	((volatile unsigned short *)PORTGIO_TOGGLE)
-#define pPORTGIO_MASKA		((volatile unsigned short *)PORTGIO_MASKA)
-#define pPORTGIO_MASKA_CLEAR	((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
-#define pPORTGIO_MASKA_SET	((volatile unsigned short *)PORTGIO_MASKA_SET)
-#define pPORTGIO_MASKA_TOGGLE	((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
-#define pPORTGIO_MASKB		((volatile unsigned short *)PORTGIO_MASKB)
-#define pPORTGIO_MASKB_CLEAR	((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
-#define pPORTGIO_MASKB_SET	((volatile unsigned short *)PORTGIO_MASKB_SET)
-#define pPORTGIO_MASKB_TOGGLE	((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
-#define pPORTGIO_DIR 		((volatile unsigned short *)PORTGIO_DIR)
-#define pPORTGIO_POLAR 		((volatile unsigned short *)PORTGIO_POLAR)
-#define pPORTGIO_EDGE 		((volatile unsigned short *)PORTGIO_EDGE)
-#define pPORTGIO_BOTH 		((volatile unsigned short *)PORTGIO_BOTH)
-#define pPORTGIO_INEN 		((volatile unsigned short *)PORTGIO_INEN)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)								*/
-#define pPORTHIO	 	((volatile unsigned short *)PORTHIO)
-#define pPORTHIO_CLEAR	 	((volatile unsigned short *)PORTHIO_CLEAR)
-#define pPORTHIO_SET	 	((volatile unsigned short *)PORTHIO_SET)
-#define pPORTHIO_TOGGLE 	((volatile unsigned short *)PORTHIO_TOGGLE)
-#define pPORTHIO_MASKA		((volatile unsigned short *)PORTHIO_MASKA)
-#define pPORTHIO_MASKA_CLEAR	((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
-#define pPORTHIO_MASKA_SET	((volatile unsigned short *)PORTHIO_MASKA_SET)
-#define pPORTHIO_MASKA_TOGGLE	((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
-#define pPORTHIO_MASKB		((volatile unsigned short *)PORTHIO_MASKB)
-#define pPORTHIO_MASKB_CLEAR	((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
-#define pPORTHIO_MASKB_SET	((volatile unsigned short *)PORTHIO_MASKB_SET)
-#define pPORTHIO_MASKB_TOGGLE	((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
-#define pPORTHIO_DIR 		((volatile unsigned short *)PORTHIO_DIR)
-#define pPORTHIO_POLAR 		((volatile unsigned short *)PORTHIO_POLAR)
-#define pPORTHIO_EDGE 		((volatile unsigned short *)PORTHIO_EDGE)
-#define pPORTHIO_BOTH 		((volatile unsigned short *)PORTHIO_BOTH)
-#define pPORTHIO_INEN 		((volatile unsigned short *)PORTHIO_INEN)
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define pUART1_THR 		((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR 		((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL 		((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER 		((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH 		((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR 		((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR 		((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR 		((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR 		((volatile unsigned short *)UART1_LSR)
-#define pUART1_SCR 		((volatile unsigned short *)UART1_SCR)
-#define pUART1_GCTL 		((volatile unsigned short *)UART1_GCTL)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)								*/
-#define pPORTF_FER		((volatile unsigned short *)PORTF_FER)
-#define pPORTG_FER		((volatile unsigned short *)PORTG_FER)
-#define pPORTH_FER		((volatile unsigned short *)PORTH_FER)
-
-
-/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)								*/
-#define pHMDMA0_CONTROL		((volatile unsigned short *)HMDMA0_CONTROL)
-#define pHMDMA0_ECINIT		((volatile unsigned short *)HMDMA0_ECINIT)
-#define pHMDMA0_BCINIT		((volatile unsigned short *)HMDMA0_BCINIT)
-#define pHMDMA0_ECURGENT	((volatile unsigned short *)HMDMA0_ECURGENT)
-#define pHMDMA0_ECOVERFLOW	((volatile unsigned short *)HMDMA0_ECOVERFLOW)
-#define pHMDMA0_ECOUNT		((volatile unsigned short *)HMDMA0_ECOUNT)
-#define pHMDMA0_BCOUNT		((volatile unsigned short *)HMDMA0_BCOUNT)
-
-#define pHMDMA1_CONTROL		((volatile unsigned short *)HMDMA1_CONTROL)
-#define pHMDMA1_ECINIT		((volatile unsigned short *)HMDMA1_ECINIT)
-#define pHMDMA1_BCINIT		((volatile unsigned short *)HMDMA1_BCINIT)
-#define pHMDMA1_ECURGENT	((volatile unsigned short *)HMDMA1_ECURGENT)
-#define pHMDMA1_ECOVERFLOW	((volatile unsigned short *)HMDMA1_ECOVERFLOW)
-#define pHMDMA1_ECOUNT		((volatile unsigned short *)HMDMA1_ECOUNT)
-#define pHMDMA1_BCOUNT		((volatile unsigned short *)HMDMA1_BCOUNT)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define                        pPORTF_MUX ((volatile unsigned short *)PORTF_MUX)
-#define                        pPORTG_MUX ((volatile unsigned short *)PORTG_MUX)
-#define                        pPORTH_MUX ((volatile unsigned short *)PORTH_MUX)
-
-#define                      pPORTF_DRIVE ((volatile unsigned short *)PORTF_DRIVE)
-#define                      pPORTG_DRIVE ((volatile unsigned short *)PORTG_DRIVE)
-#define                      pPORTH_DRIVE ((volatile unsigned short *)PORTH_DRIVE)
-#define                 pPORTF_HYSTERESIS ((volatile unsigned short *)PORTF_HYSTERESIS)
-#define                 pPORTG_HYSTERESIS ((volatile unsigned short *)PORTG_HYSTERESIS)
-#define                 pPORTH_HYSTERESIS ((volatile unsigned short *)PORTH_HYSTERESIS)
-#define                   pNONGPIO_DRIVE ((volatile unsigned short *)NONGPIO_DRIVE)
-#define              pNONGPIO_HYSTERESIS ((volatile unsigned short *)NONGPIO_HYSTERESIS)
-
-/* HOST Port Registers */
-
-#define                     pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
-#define                      pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
-#define                     pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
-
-/* Counter Registers */
-
-#define                       pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
-#define                        pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
-#define                       pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
-#define                      pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
-#define                     pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
-#define                      pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
-#define                          pCNT_MAX ((volatile unsigned long *)CNT_MAX)
-#define                          pCNT_MIN ((volatile unsigned long *)CNT_MIN)
-
-/* Security Registers */
-
-#define                    pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
-#define                   pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
-#define                    pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
-#define                        pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
-#define                        pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
-#define                        pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
-
-/* NFC Registers */
-
-#define                          pNFC_CTL ((volatile unsigned short *)NFC_CTL)
-#define                         pNFC_STAT ((volatile unsigned short *)NFC_STAT)
-#define                      pNFC_IRQSTAT ((volatile unsigned short *)NFC_IRQSTAT)
-#define                      pNFC_IRQMASK ((volatile unsigned short *)NFC_IRQMASK)
-#define                         pNFC_ECC0 ((volatile unsigned short *)NFC_ECC0)
-#define                         pNFC_ECC1 ((volatile unsigned short *)NFC_ECC1)
-#define                         pNFC_ECC2 ((volatile unsigned short *)NFC_ECC2)
-#define                         pNFC_ECC3 ((volatile unsigned short *)NFC_ECC3)
-#define                        pNFC_COUNT ((volatile unsigned short *)NFC_COUNT)
-#define                          pNFC_RST ((volatile unsigned short *)NFC_RST)
-#define                        pNFC_PGCTL ((volatile unsigned short *)NFC_PGCTL)
-#define                         pNFC_READ ((volatile unsigned short *)NFC_READ)
-#define                         pNFC_ADDR ((volatile unsigned short *)NFC_ADDR)
-#define                          pNFC_CMD ((volatile unsigned short *)NFC_CMD)
-#define                      pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
-#define                      pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF52X_H */
diff --git a/libgloss/bfin/include/cdefBF531.h b/libgloss/bfin/include/cdefBF531.h
deleted file mode 100644
index 18f9fa4fe..000000000
--- a/libgloss/bfin/include/cdefBF531.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF531.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF531_H
-#define _CDEFBF531_H
-
-#include <cdefBF532.h>
-
-#endif /* _CDEFBF531_H */
diff --git a/libgloss/bfin/include/cdefBF532.h b/libgloss/bfin/include/cdefBF532.h
deleted file mode 100644
index bbd5ebfc2..000000000
--- a/libgloss/bfin/include/cdefBF532.h
+++ /dev/null
@@ -1,403 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF532.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-#if !defined(__ADSPLPBLACKFIN__)
-#warning cdefBF532.h should only be included for 532 compatible chips.
-#endif
-/* include all Core registers and bit definitions */
-#include <defBF532.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* include built-in mneumonic macros */
-#include <ccblkfn.h>
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-/* Clock/Regulator Control */
-#define pPLL_CTL 		((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 		((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 		((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 	((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID			((volatile unsigned long *)CHIPID)
-
-
-/* System Interrupt Controller */
-#define pSWRST 			((volatile unsigned short *)SWRST)
-#define pSYSCR 			((volatile unsigned short *)SYSCR)
-#define pSIC_IMASK 		((volatile unsigned long *)SIC_IMASK)
-#define pSIC_IAR0 		((volatile unsigned long *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile unsigned long *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile unsigned long *)SIC_IAR2)
-#define pSIC_ISR 		((volatile unsigned long *)SIC_ISR)
-#define pSIC_IWR 		((volatile unsigned long *)SIC_IWR)
-
-
-/* Watchdog Timer */
-#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile unsigned long *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile unsigned long *)WDOG_STAT)
-
-
-/* Real Time Clock */
-#define pRTC_STAT 		((volatile unsigned long *)RTC_STAT)
-#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM 		((volatile unsigned long *)RTC_ALARM)
-#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
-
-
-/* UART Controller */
-#define pUART_THR 		((volatile unsigned short *)UART_THR)
-#define pUART_RBR 		((volatile unsigned short *)UART_RBR)
-#define pUART_DLL 		((volatile unsigned short *)UART_DLL)
-#define pUART_IER 		((volatile unsigned short *)UART_IER)
-#define pUART_DLH 		((volatile unsigned short *)UART_DLH)
-#define pUART_IIR 		((volatile unsigned short *)UART_IIR)
-#define pUART_LCR 		((volatile unsigned short *)UART_LCR)
-#define pUART_MCR 		((volatile unsigned short *)UART_MCR)
-#define pUART_LSR 		((volatile unsigned short *)UART_LSR)
-#define pUART_SCR 		((volatile unsigned short *)UART_SCR)
-#define pUART_GCTL 		((volatile unsigned short *)UART_GCTL)
-
-
-/* SPI Controller */
-#define pSPI_CTL 		((volatile unsigned short *)SPI_CTL)
-#define pSPI_FLG 		((volatile unsigned short *)SPI_FLG)
-#define pSPI_STAT 		((volatile unsigned short *)SPI_STAT)
-#define pSPI_TDBR 		((volatile unsigned short *)SPI_TDBR)
-#define pSPI_RDBR 		((volatile unsigned short *)SPI_RDBR)
-#define pSPI_BAUD 		((volatile unsigned short *)SPI_BAUD)
-#define pSPI_SHADOW 	((volatile unsigned short *)SPI_SHADOW)
-
-
-/* TIMER 0, 1, 2 Registers */
-#define pTIMER0_CONFIG 	((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 	((volatile unsigned long *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 	((volatile unsigned long *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 	((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 	((volatile unsigned long *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 	((volatile unsigned long *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 	((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 	((volatile unsigned long *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 	((volatile unsigned long *)TIMER2_WIDTH)
-
-#define pTIMER_ENABLE 	((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE 	((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS 	((volatile unsigned short *)TIMER_STATUS)
-
-
-/* General Purpose IO */
-#define pFIO_FLAG_D 	((volatile unsigned short *)FIO_FLAG_D)
-#define pFIO_FLAG_C 	((volatile unsigned short *)FIO_FLAG_C)
-#define pFIO_FLAG_S 	((volatile unsigned short *)FIO_FLAG_S)
-#define pFIO_FLAG_T 	((volatile unsigned short *)FIO_FLAG_T)
-#define pFIO_MASKA_D 	((volatile unsigned short *)FIO_MASKA_D)
-#define pFIO_MASKA_C 	((volatile unsigned short *)FIO_MASKA_C)
-#define pFIO_MASKA_S 	((volatile unsigned short *)FIO_MASKA_S)
-#define pFIO_MASKA_T 	((volatile unsigned short *)FIO_MASKA_T)
-#define pFIO_MASKB_D 	((volatile unsigned short *)FIO_MASKB_D)
-#define pFIO_MASKB_C 	((volatile unsigned short *)FIO_MASKB_C)
-#define pFIO_MASKB_S 	((volatile unsigned short *)FIO_MASKB_S)
-#define pFIO_MASKB_T 	((volatile unsigned short *)FIO_MASKB_T)
-#define pFIO_DIR 		((volatile unsigned short *)FIO_DIR)
-#define pFIO_POLAR 		((volatile unsigned short *)FIO_POLAR)
-#define pFIO_EDGE 		((volatile unsigned short *)FIO_EDGE)
-#define pFIO_BOTH 		((volatile unsigned short *)FIO_BOTH)
-#define pFIO_INEN 		((volatile unsigned short *)FIO_INEN)
-
-
-/* SPORT0 Controller */
-#define pSPORT0_TCR1 	((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 	((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 	((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 		((volatile long *)SPORT0_TX)
-#define pSPORT0_RX 		((volatile long *)SPORT0_RX)
-#define pSPORT0_TX32	((volatile long *)SPORT0_TX)
-#define pSPORT0_RX32 	((volatile long *)SPORT0_RX)
-#define pSPORT0_TX16 	((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 	((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 	((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 	((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 	((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 	((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 	((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 	((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 	((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 	((volatile unsigned long *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 	((volatile unsigned long *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 	((volatile unsigned long *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 	((volatile unsigned long *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 	((volatile unsigned long *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 	((volatile unsigned long *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 	((volatile unsigned long *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 	((volatile unsigned long *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller */
-#define pSPORT1_TCR1 	((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 	((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 	((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile long *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile long *)SPORT1_RX)
-#define pSPORT1_TX32 	((volatile long *)SPORT1_TX)
-#define pSPORT1_RX32 	((volatile long *)SPORT1_RX)
-#define pSPORT1_TX16 	((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 	((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 	((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 	((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 	((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 	((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 	((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 	((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 	((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 	((volatile unsigned long *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 	((volatile unsigned long *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 	((volatile unsigned long *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 	((volatile unsigned long *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 	((volatile unsigned long *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 	((volatile unsigned long *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 	((volatile unsigned long *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 	((volatile unsigned long *)SPORT1_MRCS3)
-
-
-/* External Bus Interface Unit */
-/* Aysnchronous Memory Controller */
-#define pEBIU_AMGCTL 	((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 	((volatile unsigned long *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 	((volatile unsigned long *)EBIU_AMBCTL1)
-
-/* SDRAM Controller */
-#define pEBIU_SDGCTL 	((volatile unsigned long *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 	((volatile unsigned short *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 	((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 	((volatile unsigned short *)EBIU_SDSTAT)
-
-
-/* DMA Traffic controls */
-#define pDMA_TC_PER 	((volatile unsigned short *)DMA_TC_PER)
-#define pDMA_TC_CNT 	((volatile unsigned short *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA_TCPER 		((volatile unsigned short *)DMA_TCPER)
-#define pDMA_TCCNT 		((volatile unsigned short *)DMA_TCCNT)
-
-
-/* DMA Controller */
-#define pDMA0_CONFIG 			((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 			((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 			((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 			((volatile signed short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 			((volatile signed short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 		((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 		((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 		((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 			((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 			((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 			((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 			((volatile signed short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 			((volatile signed short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 		((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 		((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 		((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 			((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 			((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 			((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 			((volatile signed short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 			((volatile signed short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 		((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 		((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 		((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 			((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 			((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 			((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 			((volatile signed short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 			((volatile signed short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 		((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 		((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 		((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 			((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 			((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 			((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 			((volatile signed short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 			((volatile signed short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 		((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 		((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 		((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 			((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 			((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 			((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 			((volatile signed short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 			((volatile signed short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 		((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 		((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 		((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 			((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 			((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 			((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 			((volatile signed short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 			((volatile signed short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 		((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 		((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 		((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 			((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 			((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 			((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 			((volatile signed short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 			((volatile signed short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 		((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 		((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 		((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG 		((volatile unsigned short *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT 		((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT 		((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY 		((volatile signed short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY 		((volatile signed short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG 		((volatile unsigned short *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT 		((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT 		((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY 		((volatile signed short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY 		((volatile signed short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG 		((volatile unsigned short *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT 		((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT 		((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY 		((volatile signed short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY 		((volatile signed short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG 		((volatile unsigned short *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT 		((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT 		((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY 		((volatile signed short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY 		((volatile signed short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-
-
-
-/* Parallel Peripheral Interface (PPI) */
-#define pPPI_CONTROL 	((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS 	((volatile unsigned short *)PPI_STATUS)
-#define pPPI_COUNT 		((volatile unsigned short *)PPI_COUNT)
-#define pPPI_DELAY 		((volatile unsigned short *)PPI_DELAY)
-#define pPPI_FRAME 		((volatile unsigned short *)PPI_FRAME)
-
-#endif /* _CDEF_BF532_H */
diff --git a/libgloss/bfin/include/cdefBF533.h b/libgloss/bfin/include/cdefBF533.h
deleted file mode 100644
index 5910e1714..000000000
--- a/libgloss/bfin/include/cdefBF533.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF533.h
- *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF533_H
-#define _CDEFBF533_H
-
-#include <cdefBF532.h>
-
-#endif /* _CDEFBF533_H */
diff --git a/libgloss/bfin/include/cdefBF534.h b/libgloss/bfin/include/cdefBF534.h
deleted file mode 100644
index c40720aa6..000000000
--- a/libgloss/bfin/include/cdefBF534.h
+++ /dev/null
@@ -1,1007 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2005-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access.
-**
-**/
-
-/**********************************************************************************
-** System MMR Register Map
-***********************************************************************************/
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#endif /* _MISRA_RULES */
-
-/* Include all Core registers and bit definitions 									*/
-#include <defBF534.h>
-
-/* Include core specific register pointer definitions 								*/
-#include <cdef_LPBlackfin.h>
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-
-/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
-#define pPLL_CTL 		((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 		((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 		((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 		((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID      ((volatile unsigned long*)CHIPID)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
-#define pSWRST 			((volatile unsigned short *)SWRST)
-#define pSYSCR 			((volatile unsigned short *)SYSCR)
-#define pSIC_IMASK 		((volatile unsigned long  *)SIC_IMASK)
-#define pSIC_IAR0 		((volatile unsigned long  *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile unsigned long  *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile unsigned long  *)SIC_IAR2)
-#define pSIC_IAR3 		((volatile unsigned long  *)SIC_IAR3)
-#define pSIC_ISR 		((volatile unsigned long  *)SIC_ISR)
-#define pSIC_IWR 		((volatile unsigned long  *)SIC_IWR)
-
-
-/* Watchdog Timer		(0xFFC00200 - 0xFFC002FF)									*/
-#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile unsigned long  *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile unsigned long  *)WDOG_STAT)
-
-
-/* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
-#define pRTC_STAT 		((volatile unsigned long  *)RTC_STAT)
-#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM 		((volatile unsigned long  *)RTC_ALARM)
-#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
-
-
-/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
-#define pUART0_THR 		((volatile unsigned short *)UART0_THR)
-#define pUART0_RBR 		((volatile unsigned short *)UART0_RBR)
-#define pUART0_DLL 		((volatile unsigned short *)UART0_DLL)
-#define pUART0_IER 		((volatile unsigned short *)UART0_IER)
-#define pUART0_DLH 		((volatile unsigned short *)UART0_DLH)
-#define pUART0_IIR 		((volatile unsigned short *)UART0_IIR)
-#define pUART0_LCR 		((volatile unsigned short *)UART0_LCR)
-#define pUART0_MCR 		((volatile unsigned short *)UART0_MCR)
-#define pUART0_LSR 		((volatile unsigned short *)UART0_LSR)
-#define pUART0_SCR 		((volatile unsigned short *)UART0_SCR)
-#define pUART0_GCTL 		((volatile unsigned short *)UART0_GCTL)
-
-
-/* SPI Controller		(0xFFC00500 - 0xFFC005FF)									*/
-#define pSPI_CTL 		((volatile unsigned short *)SPI_CTL)
-#define pSPI_FLG 		((volatile unsigned short *)SPI_FLG)
-#define pSPI_STAT 		((volatile unsigned short *)SPI_STAT)
-#define pSPI_TDBR 		((volatile unsigned short *)SPI_TDBR)
-#define pSPI_RDBR 		((volatile unsigned short *)SPI_RDBR)
-#define pSPI_BAUD 		((volatile unsigned short *)SPI_BAUD)
-#define pSPI_SHADOW 		((volatile unsigned short *)SPI_SHADOW)
-
-
-/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
-#define pTIMER0_CONFIG 		((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER 	((volatile unsigned long  *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 		((volatile unsigned long  *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 		((volatile unsigned long  *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 		((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER 	((volatile unsigned long  *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 		((volatile unsigned long  *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 		((volatile unsigned long  *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 		((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER 	((volatile unsigned long  *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 		((volatile unsigned long  *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 		((volatile unsigned long  *)TIMER2_WIDTH)
-
-#define pTIMER3_CONFIG 		((volatile unsigned short *)TIMER3_CONFIG)
-#define pTIMER3_COUNTER 	((volatile unsigned long  *)TIMER3_COUNTER)
-#define pTIMER3_PERIOD 		((volatile unsigned long  *)TIMER3_PERIOD)
-#define pTIMER3_WIDTH 		((volatile unsigned long  *)TIMER3_WIDTH)
-
-#define pTIMER4_CONFIG 		((volatile unsigned short *)TIMER4_CONFIG)
-#define pTIMER4_COUNTER 	((volatile unsigned long  *)TIMER4_COUNTER)
-#define pTIMER4_PERIOD 		((volatile unsigned long  *)TIMER4_PERIOD)
-#define pTIMER4_WIDTH 		((volatile unsigned long  *)TIMER4_WIDTH)
-
-#define pTIMER5_CONFIG 		((volatile unsigned short *)TIMER5_CONFIG)
-#define pTIMER5_COUNTER 	((volatile unsigned long  *)TIMER5_COUNTER)
-#define pTIMER5_PERIOD 		((volatile unsigned long  *)TIMER5_PERIOD)
-#define pTIMER5_WIDTH 		((volatile unsigned long  *)TIMER5_WIDTH)
-
-#define pTIMER6_CONFIG 		((volatile unsigned short *)TIMER6_CONFIG)
-#define pTIMER6_COUNTER 	((volatile unsigned long  *)TIMER6_COUNTER)
-#define pTIMER6_PERIOD 		((volatile unsigned long  *)TIMER6_PERIOD)
-#define pTIMER6_WIDTH 		((volatile unsigned long  *)TIMER6_WIDTH)
-
-#define pTIMER7_CONFIG 		((volatile unsigned short *)TIMER7_CONFIG)
-#define pTIMER7_COUNTER 	((volatile unsigned long  *)TIMER7_COUNTER)
-#define pTIMER7_PERIOD 		((volatile unsigned long  *)TIMER7_PERIOD)
-#define pTIMER7_WIDTH 		((volatile unsigned long  *)TIMER7_WIDTH)
-
-#define pTIMER_ENABLE 		((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE 		((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS		((volatile unsigned long  *)TIMER_STATUS)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)								*/
-#define pPORTFIO	 	((volatile unsigned short *)PORTFIO)
-#define pPORTFIO_CLEAR	 	((volatile unsigned short *)PORTFIO_CLEAR)
-#define pPORTFIO_SET	 	((volatile unsigned short *)PORTFIO_SET)
-#define pPORTFIO_TOGGLE 	((volatile unsigned short *)PORTFIO_TOGGLE)
-#define pPORTFIO_MASKA 		((volatile unsigned short *)PORTFIO_MASKA)
-#define pPORTFIO_MASKA_CLEAR 	((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
-#define pPORTFIO_MASKA_SET 	((volatile unsigned short *)PORTFIO_MASKA_SET)
-#define pPORTFIO_MASKA_TOGGLE 	((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
-#define pPORTFIO_MASKB	 	((volatile unsigned short *)PORTFIO_MASKB)
-#define pPORTFIO_MASKB_CLEAR 	((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
-#define pPORTFIO_MASKB_SET 	((volatile unsigned short *)PORTFIO_MASKB_SET)
-#define pPORTFIO_MASKB_TOGGLE 	((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
-#define pPORTFIO_DIR 		((volatile unsigned short *)PORTFIO_DIR)
-#define pPORTFIO_POLAR 		((volatile unsigned short *)PORTFIO_POLAR)
-#define pPORTFIO_EDGE 		((volatile unsigned short *)PORTFIO_EDGE)
-#define pPORTFIO_BOTH 		((volatile unsigned short *)PORTFIO_BOTH)
-#define pPORTFIO_INEN 		((volatile unsigned short *)PORTFIO_INEN)
-
-
-/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)								*/
-#define pSPORT0_TCR1 		((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 		((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV 	((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 		((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX32 		((volatile unsigned long  *)SPORT0_TX)
-#define pSPORT0_RX32 		((volatile unsigned long  *)SPORT0_RX)
-#define pSPORT0_TX16 		((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 		((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 		((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 		((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV 	((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 		((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 		((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 		((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 		((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 		((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 		((volatile unsigned long  *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 		((volatile unsigned long  *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 		((volatile unsigned long  *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 		((volatile unsigned long  *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 		((volatile unsigned long  *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 		((volatile unsigned long  *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 		((volatile unsigned long  *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 		((volatile unsigned long  *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)								*/
-#define pSPORT1_TCR1 		((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 		((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV 	((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 		((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX32 		((volatile unsigned long  *)SPORT1_TX)
-#define pSPORT1_RX32 		((volatile unsigned long  *)SPORT1_RX)
-#define pSPORT1_TX16 		((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 		((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 		((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 		((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV 	((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 		((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 		((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 		((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 		((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 		((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 		((volatile unsigned long  *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 		((volatile unsigned long  *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 		((volatile unsigned long  *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 		((volatile unsigned long  *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 		((volatile unsigned long  *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 		((volatile unsigned long  *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 		((volatile unsigned long  *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 		((volatile unsigned long  *)SPORT1_MRCS3)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)							*/
-#define pEBIU_AMGCTL 		((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 		((volatile unsigned long  *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 		((volatile unsigned long  *)EBIU_AMBCTL1)
-#define pEBIU_SDGCTL 		((volatile unsigned long  *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 		((volatile unsigned short *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 		((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 		((volatile unsigned short *)EBIU_SDSTAT)
-
-
-/* DMA Traffic Control Registers													*/
-#define	pDMA_TC_PER		((volatile unsigned short *)DMA_TC_PER)
-#define	pDMA_TC_CNT		((volatile unsigned short *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define	pDMA_TCPER		((volatile unsigned short *)DMA_TCPER)
-#define	pDMA_TCCNT		((volatile unsigned short *)DMA_TCCNT)
-
-/* DMA Controller																	*/
-#define pDMA0_CONFIG 		((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 		((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 		((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 		((volatile signed   short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 		((volatile signed   short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 	((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 	((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 	((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 		((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 		((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 		((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 		((volatile signed   short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 		((volatile signed   short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 	((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 	((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 		((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 		((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 		((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 		((volatile signed   short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 		((volatile signed   short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 	((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 	((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 		((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 		((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 		((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 		((volatile signed   short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 		((volatile signed   short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 	((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 	((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 	((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 		((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 		((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 		((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 		((volatile signed   short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 		((volatile signed   short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 	((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 	((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 	((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 		((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 		((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 		((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 		((volatile signed   short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 		((volatile signed   short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 	((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 	((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 	((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 		((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 		((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 		((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 		((volatile signed   short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 		((volatile signed   short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 	((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 	((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 	((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 		((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 		((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 		((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 		((volatile signed   short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 		((volatile signed   short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 	((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 	((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 	((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pDMA8_CONFIG 		((volatile unsigned short *)DMA8_CONFIG)
-#define pDMA8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
-#define pDMA8_X_COUNT 		((volatile unsigned short *)DMA8_X_COUNT)
-#define pDMA8_Y_COUNT 		((volatile unsigned short *)DMA8_Y_COUNT)
-#define pDMA8_X_MODIFY 		((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_MODIFY 		((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
-#define pDMA8_CURR_X_COUNT 	((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 	((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-#define pDMA8_IRQ_STATUS 	((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 	((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-
-#define pDMA9_CONFIG 		((volatile unsigned short *)DMA9_CONFIG)
-#define pDMA9_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
-#define pDMA9_X_COUNT 		((volatile unsigned short *)DMA9_X_COUNT)
-#define pDMA9_Y_COUNT 		((volatile unsigned short *)DMA9_Y_COUNT)
-#define pDMA9_X_MODIFY 		((volatile signed   short *)DMA9_X_MODIFY)
-#define pDMA9_Y_MODIFY 		((volatile signed   short *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
-#define pDMA9_CURR_X_COUNT 	((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT 	((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-#define pDMA9_IRQ_STATUS 	((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP 	((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-
-#define pDMA10_CONFIG 		((volatile unsigned short *)DMA10_CONFIG)
-#define pDMA10_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
-#define pDMA10_X_COUNT 		((volatile unsigned short *)DMA10_X_COUNT)
-#define pDMA10_Y_COUNT 		((volatile unsigned short *)DMA10_Y_COUNT)
-#define pDMA10_X_MODIFY 	((volatile signed   short *)DMA10_X_MODIFY)
-#define pDMA10_Y_MODIFY 	((volatile signed   short *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
-#define pDMA10_CURR_X_COUNT 	((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT 	((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-#define pDMA10_IRQ_STATUS 	((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP 	((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-
-#define pDMA11_CONFIG 		((volatile unsigned short *)DMA11_CONFIG)
-#define pDMA11_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
-#define pDMA11_X_COUNT 		((volatile unsigned short *)DMA11_X_COUNT)
-#define pDMA11_Y_COUNT 		((volatile unsigned short *)DMA11_Y_COUNT)
-#define pDMA11_X_MODIFY 	((volatile signed   short *)DMA11_X_MODIFY)
-#define pDMA11_Y_MODIFY 	((volatile signed   short *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
-#define pDMA11_CURR_X_COUNT 	((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT 	((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-#define pDMA11_IRQ_STATUS 	((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP 	((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG 	((volatile unsigned short *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT 	((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT 	((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY 	((volatile signed   short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY 	((volatile signed   short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG 	((volatile unsigned short *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT 	((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT 	((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY 	((volatile signed   short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY 	((volatile signed   short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG 	((volatile unsigned short *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT 	((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT 	((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY 	((volatile signed   short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY 	((volatile signed   short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG 	((volatile unsigned short *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT 	((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT 	((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY 	((volatile signed   short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY 	((volatile signed   short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)							*/
-#define pPPI_CONTROL 		((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS 		((volatile unsigned short *)PPI_STATUS)
-#define pPPI_DELAY 		((volatile unsigned short *)PPI_DELAY)
-#define pPPI_COUNT 		((volatile unsigned short *)PPI_COUNT)
-#define pPPI_FRAME 		((volatile unsigned short *)PPI_FRAME)
-
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
-#define pTWI_CLKDIV		((volatile unsigned short *)TWI_CLKDIV)
-#define pTWI_CONTROL		((volatile unsigned short *)TWI_CONTROL)
-#define pTWI_SLAVE_CTL		((volatile unsigned short *)TWI_SLAVE_CTL)
-#define pTWI_SLAVE_STAT		((volatile unsigned short *)TWI_SLAVE_STAT)
-#define pTWI_SLAVE_ADDR		((volatile unsigned short *)TWI_SLAVE_ADDR)
-#define pTWI_MASTER_CTL		((volatile unsigned short *)TWI_MASTER_CTL)
-#define pTWI_MASTER_STAT	((volatile unsigned short *)TWI_MASTER_STAT)
-#define pTWI_MASTER_ADDR	((volatile unsigned short *)TWI_MASTER_ADDR)
-#define pTWI_INT_STAT		((volatile unsigned short *)TWI_INT_STAT)
-#define pTWI_INT_MASK		((volatile unsigned short *)TWI_INT_MASK)
-#define pTWI_FIFO_CTL		((volatile unsigned short *)TWI_FIFO_CTL)
-#define pTWI_FIFO_STAT		((volatile unsigned short *)TWI_FIFO_STAT)
-#define pTWI_XMT_DATA8		((volatile unsigned short *)TWI_XMT_DATA8)
-#define pTWI_XMT_DATA16		((volatile unsigned short *)TWI_XMT_DATA16)
-#define pTWI_RCV_DATA8		((volatile unsigned short *)TWI_RCV_DATA8)
-#define pTWI_RCV_DATA16		((volatile unsigned short *)TWI_RCV_DATA16)
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)								*/
-#define pPORTGIO	 	((volatile unsigned short *)PORTGIO)
-#define pPORTGIO_CLEAR	 	((volatile unsigned short *)PORTGIO_CLEAR)
-#define pPORTGIO_SET	 	((volatile unsigned short *)PORTGIO_SET)
-#define pPORTGIO_TOGGLE 	((volatile unsigned short *)PORTGIO_TOGGLE)
-#define pPORTGIO_MASKA		((volatile unsigned short *)PORTGIO_MASKA)
-#define pPORTGIO_MASKA_CLEAR	((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
-#define pPORTGIO_MASKA_SET	((volatile unsigned short *)PORTGIO_MASKA_SET)
-#define pPORTGIO_MASKA_TOGGLE	((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
-#define pPORTGIO_MASKB		((volatile unsigned short *)PORTGIO_MASKB)
-#define pPORTGIO_MASKB_CLEAR	((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
-#define pPORTGIO_MASKB_SET	((volatile unsigned short *)PORTGIO_MASKB_SET)
-#define pPORTGIO_MASKB_TOGGLE	((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
-#define pPORTGIO_DIR 		((volatile unsigned short *)PORTGIO_DIR)
-#define pPORTGIO_POLAR 		((volatile unsigned short *)PORTGIO_POLAR)
-#define pPORTGIO_EDGE 		((volatile unsigned short *)PORTGIO_EDGE)
-#define pPORTGIO_BOTH 		((volatile unsigned short *)PORTGIO_BOTH)
-#define pPORTGIO_INEN 		((volatile unsigned short *)PORTGIO_INEN)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)								*/
-#define pPORTHIO	 	((volatile unsigned short *)PORTHIO)
-#define pPORTHIO_CLEAR	 	((volatile unsigned short *)PORTHIO_CLEAR)
-#define pPORTHIO_SET	 	((volatile unsigned short *)PORTHIO_SET)
-#define pPORTHIO_TOGGLE 	((volatile unsigned short *)PORTHIO_TOGGLE)
-#define pPORTHIO_MASKA		((volatile unsigned short *)PORTHIO_MASKA)
-#define pPORTHIO_MASKA_CLEAR	((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
-#define pPORTHIO_MASKA_SET	((volatile unsigned short *)PORTHIO_MASKA_SET)
-#define pPORTHIO_MASKA_TOGGLE	((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
-#define pPORTHIO_MASKB		((volatile unsigned short *)PORTHIO_MASKB)
-#define pPORTHIO_MASKB_CLEAR	((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
-#define pPORTHIO_MASKB_SET	((volatile unsigned short *)PORTHIO_MASKB_SET)
-#define pPORTHIO_MASKB_TOGGLE	((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
-#define pPORTHIO_DIR 		((volatile unsigned short *)PORTHIO_DIR)
-#define pPORTHIO_POLAR 		((volatile unsigned short *)PORTHIO_POLAR)
-#define pPORTHIO_EDGE 		((volatile unsigned short *)PORTHIO_EDGE)
-#define pPORTHIO_BOTH 		((volatile unsigned short *)PORTHIO_BOTH)
-#define pPORTHIO_INEN 		((volatile unsigned short *)PORTHIO_INEN)
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define pUART1_THR 		((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR 		((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL 		((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER 		((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH 		((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR 		((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR 		((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR 		((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR 		((volatile unsigned short *)UART1_LSR)
-#define pUART1_SCR 		((volatile unsigned short *)UART1_SCR)
-#define pUART1_GCTL 		((volatile unsigned short *)UART1_GCTL)
-
-
-/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)								*/
-/* For Mailboxes 0-15 */
-#define pCAN_MC1		((volatile unsigned short *)CAN_MC1)
-#define pCAN_MD1		((volatile unsigned short *)CAN_MD1)
-#define pCAN_TRS1		((volatile unsigned short *)CAN_TRS1)
-#define pCAN_TRR1		((volatile unsigned short *)CAN_TRR1)
-#define pCAN_TA1		((volatile unsigned short *)CAN_TA1)
-#define pCAN_AA1		((volatile unsigned short *)CAN_AA1)
-#define pCAN_RMP1		((volatile unsigned short *)CAN_RMP1)
-#define pCAN_RML1		((volatile unsigned short *)CAN_RML1)
-#define pCAN_MBTIF1		((volatile unsigned short *)CAN_MBTIF1)
-#define pCAN_MBRIF1		((volatile unsigned short *)CAN_MBRIF1)
-#define pCAN_MBIM1		((volatile unsigned short *)CAN_MBIM1)
-#define pCAN_RFH1		((volatile unsigned short *)CAN_RFH1)
-#define pCAN_OPSS1		((volatile unsigned short *)CAN_OPSS1)
-
-/* For Mailboxes 16-31 */
-#define pCAN_MC2		((volatile unsigned short *)CAN_MC2)
-#define pCAN_MD2		((volatile unsigned short *)CAN_MD2)
-#define pCAN_TRS2		((volatile unsigned short *)CAN_TRS2)
-#define pCAN_TRR2		((volatile unsigned short *)CAN_TRR2)
-#define pCAN_TA2		((volatile unsigned short *)CAN_TA2)
-#define pCAN_AA2		((volatile unsigned short *)CAN_AA2)
-#define pCAN_RMP2		((volatile unsigned short *)CAN_RMP2)
-#define pCAN_RML2		((volatile unsigned short *)CAN_RML2)
-#define pCAN_MBTIF2		((volatile unsigned short *)CAN_MBTIF2)
-#define pCAN_MBRIF2		((volatile unsigned short *)CAN_MBRIF2)
-#define pCAN_MBIM2		((volatile unsigned short *)CAN_MBIM2)
-#define pCAN_RFH2		((volatile unsigned short *)CAN_RFH2)
-#define pCAN_OPSS2		((volatile unsigned short *)CAN_OPSS2)
-
-#define pCAN_CLOCK		((volatile unsigned short *)CAN_CLOCK)
-#define pCAN_TIMING		((volatile unsigned short *)CAN_TIMING)
-#define pCAN_DEBUG		((volatile unsigned short *)CAN_DEBUG)
-#define pCAN_STATUS		((volatile unsigned short *)CAN_STATUS)
-#define pCAN_CEC		((volatile unsigned short *)CAN_CEC)
-#define pCAN_GIS		((volatile unsigned short *)CAN_GIS)
-#define pCAN_GIM		((volatile unsigned short *)CAN_GIM)
-#define pCAN_GIF		((volatile unsigned short *)CAN_GIF)
-#define pCAN_CONTROL		((volatile unsigned short *)CAN_CONTROL)
-#define pCAN_INTR		((volatile unsigned short *)CAN_INTR)
-#define pCAN_MBTD		((volatile unsigned short *)CAN_MBTD)
-#define pCAN_EWR		((volatile unsigned short *)CAN_EWR)
-#define pCAN_ESR		((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCCNT		((volatile unsigned short *)CAN_UCCNT)
-#define pCAN_UCRC		((volatile unsigned short *)CAN_UCRC)
-#define pCAN_UCCNF		((volatile unsigned short *)CAN_UCCNF)
-
-/* Mailbox Acceptance Masks */
-#define pCAN_AM00L		((volatile unsigned short *)CAN_AM00L)
-#define pCAN_AM00H		((volatile unsigned short *)CAN_AM00H)
-#define pCAN_AM01L		((volatile unsigned short *)CAN_AM01L)
-#define pCAN_AM01H		((volatile unsigned short *)CAN_AM01H)
-#define pCAN_AM02L		((volatile unsigned short *)CAN_AM02L)
-#define pCAN_AM02H		((volatile unsigned short *)CAN_AM02H)
-#define pCAN_AM03L		((volatile unsigned short *)CAN_AM03L)
-#define pCAN_AM03H		((volatile unsigned short *)CAN_AM03H)
-#define pCAN_AM04L		((volatile unsigned short *)CAN_AM04L)
-#define pCAN_AM04H		((volatile unsigned short *)CAN_AM04H)
-#define pCAN_AM05L		((volatile unsigned short *)CAN_AM05L)
-#define pCAN_AM05H		((volatile unsigned short *)CAN_AM05H)
-#define pCAN_AM06L		((volatile unsigned short *)CAN_AM06L)
-#define pCAN_AM06H		((volatile unsigned short *)CAN_AM06H)
-#define pCAN_AM07L		((volatile unsigned short *)CAN_AM07L)
-#define pCAN_AM07H		((volatile unsigned short *)CAN_AM07H)
-#define pCAN_AM08L		((volatile unsigned short *)CAN_AM08L)
-#define pCAN_AM08H		((volatile unsigned short *)CAN_AM08H)
-#define pCAN_AM09L		((volatile unsigned short *)CAN_AM09L)
-#define pCAN_AM09H		((volatile unsigned short *)CAN_AM09H)
-#define pCAN_AM10L		((volatile unsigned short *)CAN_AM10L)
-#define pCAN_AM10H		((volatile unsigned short *)CAN_AM10H)
-#define pCAN_AM11L		((volatile unsigned short *)CAN_AM11L)
-#define pCAN_AM11H		((volatile unsigned short *)CAN_AM11H)
-#define pCAN_AM12L		((volatile unsigned short *)CAN_AM12L)
-#define pCAN_AM12H		((volatile unsigned short *)CAN_AM12H)
-#define pCAN_AM13L		((volatile unsigned short *)CAN_AM13L)
-#define pCAN_AM13H		((volatile unsigned short *)CAN_AM13H)
-#define pCAN_AM14L		((volatile unsigned short *)CAN_AM14L)
-#define pCAN_AM14H		((volatile unsigned short *)CAN_AM14H)
-#define pCAN_AM15L		((volatile unsigned short *)CAN_AM15L)
-#define pCAN_AM15H		((volatile unsigned short *)CAN_AM15H)
-
-#define pCAN_AM16L		((volatile unsigned short *)CAN_AM16L)
-#define pCAN_AM16H		((volatile unsigned short *)CAN_AM16H)
-#define pCAN_AM17L		((volatile unsigned short *)CAN_AM17L)
-#define pCAN_AM17H		((volatile unsigned short *)CAN_AM17H)
-#define pCAN_AM18L		((volatile unsigned short *)CAN_AM18L)
-#define pCAN_AM18H		((volatile unsigned short *)CAN_AM18H)
-#define pCAN_AM19L		((volatile unsigned short *)CAN_AM19L)
-#define pCAN_AM19H		((volatile unsigned short *)CAN_AM19H)
-#define pCAN_AM20L		((volatile unsigned short *)CAN_AM20L)
-#define pCAN_AM20H		((volatile unsigned short *)CAN_AM20H)
-#define pCAN_AM21L		((volatile unsigned short *)CAN_AM21L)
-#define pCAN_AM21H		((volatile unsigned short *)CAN_AM21H)
-#define pCAN_AM22L		((volatile unsigned short *)CAN_AM22L)
-#define pCAN_AM22H		((volatile unsigned short *)CAN_AM22H)
-#define pCAN_AM23L		((volatile unsigned short *)CAN_AM23L)
-#define pCAN_AM23H		((volatile unsigned short *)CAN_AM23H)
-#define pCAN_AM24L		((volatile unsigned short *)CAN_AM24L)
-#define pCAN_AM24H		((volatile unsigned short *)CAN_AM24H)
-#define pCAN_AM25L		((volatile unsigned short *)CAN_AM25L)
-#define pCAN_AM25H		((volatile unsigned short *)CAN_AM25H)
-#define pCAN_AM26L		((volatile unsigned short *)CAN_AM26L)
-#define pCAN_AM26H		((volatile unsigned short *)CAN_AM26H)
-#define pCAN_AM27L		((volatile unsigned short *)CAN_AM27L)
-#define pCAN_AM27H		((volatile unsigned short *)CAN_AM27H)
-#define pCAN_AM28L		((volatile unsigned short *)CAN_AM28L)
-#define pCAN_AM28H		((volatile unsigned short *)CAN_AM28H)
-#define pCAN_AM29L		((volatile unsigned short *)CAN_AM29L)
-#define pCAN_AM29H		((volatile unsigned short *)CAN_AM29H)
-#define pCAN_AM30L		((volatile unsigned short *)CAN_AM30L)
-#define pCAN_AM30H		((volatile unsigned short *)CAN_AM30H)
-#define pCAN_AM31L		((volatile unsigned short *)CAN_AM31L)
-#define pCAN_AM31H		((volatile unsigned short *)CAN_AM31H)
-
-/* CAN Acceptance Mask Area Macros	*/
-#define pCAN_AM_L(x)		((volatile unsigned short *)CAN_AM_L(x))
-#define pCAN_AM_H(x)		((volatile unsigned short *)CAN_AM_H(x))
-
-/* Mailbox Registers */
-#define pCAN_MB00_ID1		((volatile unsigned short *)CAN_MB00_ID1)
-#define pCAN_MB00_ID0		((volatile unsigned short *)CAN_MB00_ID0)
-#define pCAN_MB00_TIMESTAMP	((volatile unsigned short *)CAN_MB00_TIMESTAMP)
-#define pCAN_MB00_LENGTH	((volatile unsigned short *)CAN_MB00_LENGTH)
-#define pCAN_MB00_DATA3		((volatile unsigned short *)CAN_MB00_DATA3)
-#define pCAN_MB00_DATA2		((volatile unsigned short *)CAN_MB00_DATA2)
-#define pCAN_MB00_DATA1		((volatile unsigned short *)CAN_MB00_DATA1)
-#define pCAN_MB00_DATA0		((volatile unsigned short *)CAN_MB00_DATA0)
-
-#define pCAN_MB01_ID1		((volatile unsigned short *)CAN_MB01_ID1)
-#define pCAN_MB01_ID0		((volatile unsigned short *)CAN_MB01_ID0)
-#define pCAN_MB01_TIMESTAMP	((volatile unsigned short *)CAN_MB01_TIMESTAMP)
-#define pCAN_MB01_LENGTH	((volatile unsigned short *)CAN_MB01_LENGTH)
-#define pCAN_MB01_DATA3		((volatile unsigned short *)CAN_MB01_DATA3)
-#define pCAN_MB01_DATA2		((volatile unsigned short *)CAN_MB01_DATA2)
-#define pCAN_MB01_DATA1		((volatile unsigned short *)CAN_MB01_DATA1)
-#define pCAN_MB01_DATA0		((volatile unsigned short *)CAN_MB01_DATA0)
-
-#define pCAN_MB02_ID1		((volatile unsigned short *)CAN_MB02_ID1)
-#define pCAN_MB02_ID0		((volatile unsigned short *)CAN_MB02_ID0)
-#define pCAN_MB02_TIMESTAMP	((volatile unsigned short *)CAN_MB02_TIMESTAMP)
-#define pCAN_MB02_LENGTH	((volatile unsigned short *)CAN_MB02_LENGTH)
-#define pCAN_MB02_DATA3		((volatile unsigned short *)CAN_MB02_DATA3)
-#define pCAN_MB02_DATA2		((volatile unsigned short *)CAN_MB02_DATA2)
-#define pCAN_MB02_DATA1		((volatile unsigned short *)CAN_MB02_DATA1)
-#define pCAN_MB02_DATA0		((volatile unsigned short *)CAN_MB02_DATA0)
-
-#define pCAN_MB03_ID1		((volatile unsigned short *)CAN_MB03_ID1)
-#define pCAN_MB03_ID0		((volatile unsigned short *)CAN_MB03_ID0)
-#define pCAN_MB03_TIMESTAMP	((volatile unsigned short *)CAN_MB03_TIMESTAMP)
-#define pCAN_MB03_LENGTH	((volatile unsigned short *)CAN_MB03_LENGTH)
-#define pCAN_MB03_DATA3		((volatile unsigned short *)CAN_MB03_DATA3)
-#define pCAN_MB03_DATA2		((volatile unsigned short *)CAN_MB03_DATA2)
-#define pCAN_MB03_DATA1		((volatile unsigned short *)CAN_MB03_DATA1)
-#define pCAN_MB03_DATA0		((volatile unsigned short *)CAN_MB03_DATA0)
-
-#define pCAN_MB04_ID1		((volatile unsigned short *)CAN_MB04_ID1)
-#define pCAN_MB04_ID0		((volatile unsigned short *)CAN_MB04_ID0)
-#define pCAN_MB04_TIMESTAMP	((volatile unsigned short *)CAN_MB04_TIMESTAMP)
-#define pCAN_MB04_LENGTH	((volatile unsigned short *)CAN_MB04_LENGTH)
-#define pCAN_MB04_DATA3		((volatile unsigned short *)CAN_MB04_DATA3)
-#define pCAN_MB04_DATA2		((volatile unsigned short *)CAN_MB04_DATA2)
-#define pCAN_MB04_DATA1		((volatile unsigned short *)CAN_MB04_DATA1)
-#define pCAN_MB04_DATA0		((volatile unsigned short *)CAN_MB04_DATA0)
-
-#define pCAN_MB05_ID1		((volatile unsigned short *)CAN_MB05_ID1)
-#define pCAN_MB05_ID0		((volatile unsigned short *)CAN_MB05_ID0)
-#define pCAN_MB05_TIMESTAMP	((volatile unsigned short *)CAN_MB05_TIMESTAMP)
-#define pCAN_MB05_LENGTH	((volatile unsigned short *)CAN_MB05_LENGTH)
-#define pCAN_MB05_DATA3		((volatile unsigned short *)CAN_MB05_DATA3)
-#define pCAN_MB05_DATA2		((volatile unsigned short *)CAN_MB05_DATA2)
-#define pCAN_MB05_DATA1		((volatile unsigned short *)CAN_MB05_DATA1)
-#define pCAN_MB05_DATA0		((volatile unsigned short *)CAN_MB05_DATA0)
-
-#define pCAN_MB06_ID1		((volatile unsigned short *)CAN_MB06_ID1)
-#define pCAN_MB06_ID0		((volatile unsigned short *)CAN_MB06_ID0)
-#define pCAN_MB06_TIMESTAMP	((volatile unsigned short *)CAN_MB06_TIMESTAMP)
-#define pCAN_MB06_LENGTH	((volatile unsigned short *)CAN_MB06_LENGTH)
-#define pCAN_MB06_DATA3		((volatile unsigned short *)CAN_MB06_DATA3)
-#define pCAN_MB06_DATA2		((volatile unsigned short *)CAN_MB06_DATA2)
-#define pCAN_MB06_DATA1		((volatile unsigned short *)CAN_MB06_DATA1)
-#define pCAN_MB06_DATA0		((volatile unsigned short *)CAN_MB06_DATA0)
-
-#define pCAN_MB07_ID1		((volatile unsigned short *)CAN_MB07_ID1)
-#define pCAN_MB07_ID0		((volatile unsigned short *)CAN_MB07_ID0)
-#define pCAN_MB07_TIMESTAMP	((volatile unsigned short *)CAN_MB07_TIMESTAMP)
-#define pCAN_MB07_LENGTH	((volatile unsigned short *)CAN_MB07_LENGTH)
-#define pCAN_MB07_DATA3		((volatile unsigned short *)CAN_MB07_DATA3)
-#define pCAN_MB07_DATA2		((volatile unsigned short *)CAN_MB07_DATA2)
-#define pCAN_MB07_DATA1		((volatile unsigned short *)CAN_MB07_DATA1)
-#define pCAN_MB07_DATA0		((volatile unsigned short *)CAN_MB07_DATA0)
-
-#define pCAN_MB08_ID1		((volatile unsigned short *)CAN_MB08_ID1)
-#define pCAN_MB08_ID0		((volatile unsigned short *)CAN_MB08_ID0)
-#define pCAN_MB08_TIMESTAMP	((volatile unsigned short *)CAN_MB08_TIMESTAMP)
-#define pCAN_MB08_LENGTH	((volatile unsigned short *)CAN_MB08_LENGTH)
-#define pCAN_MB08_DATA3		((volatile unsigned short *)CAN_MB08_DATA3)
-#define pCAN_MB08_DATA2		((volatile unsigned short *)CAN_MB08_DATA2)
-#define pCAN_MB08_DATA1		((volatile unsigned short *)CAN_MB08_DATA1)
-#define pCAN_MB08_DATA0		((volatile unsigned short *)CAN_MB08_DATA0)
-
-#define pCAN_MB09_ID1		((volatile unsigned short *)CAN_MB09_ID1)
-#define pCAN_MB09_ID0		((volatile unsigned short *)CAN_MB09_ID0)
-#define pCAN_MB09_TIMESTAMP	((volatile unsigned short *)CAN_MB09_TIMESTAMP)
-#define pCAN_MB09_LENGTH	((volatile unsigned short *)CAN_MB09_LENGTH)
-#define pCAN_MB09_DATA3		((volatile unsigned short *)CAN_MB09_DATA3)
-#define pCAN_MB09_DATA2		((volatile unsigned short *)CAN_MB09_DATA2)
-#define pCAN_MB09_DATA1		((volatile unsigned short *)CAN_MB09_DATA1)
-#define pCAN_MB09_DATA0		((volatile unsigned short *)CAN_MB09_DATA0)
-
-#define pCAN_MB10_ID1		((volatile unsigned short *)CAN_MB10_ID1)
-#define pCAN_MB10_ID0		((volatile unsigned short *)CAN_MB10_ID0)
-#define pCAN_MB10_TIMESTAMP	((volatile unsigned short *)CAN_MB10_TIMESTAMP)
-#define pCAN_MB10_LENGTH	((volatile unsigned short *)CAN_MB10_LENGTH)
-#define pCAN_MB10_DATA3		((volatile unsigned short *)CAN_MB10_DATA3)
-#define pCAN_MB10_DATA2		((volatile unsigned short *)CAN_MB10_DATA2)
-#define pCAN_MB10_DATA1		((volatile unsigned short *)CAN_MB10_DATA1)
-#define pCAN_MB10_DATA0		((volatile unsigned short *)CAN_MB10_DATA0)
-
-#define pCAN_MB11_ID1		((volatile unsigned short *)CAN_MB11_ID1)
-#define pCAN_MB11_ID0		((volatile unsigned short *)CAN_MB11_ID0)
-#define pCAN_MB11_TIMESTAMP	((volatile unsigned short *)CAN_MB11_TIMESTAMP)
-#define pCAN_MB11_LENGTH	((volatile unsigned short *)CAN_MB11_LENGTH)
-#define pCAN_MB11_DATA3		((volatile unsigned short *)CAN_MB11_DATA3)
-#define pCAN_MB11_DATA2		((volatile unsigned short *)CAN_MB11_DATA2)
-#define pCAN_MB11_DATA1		((volatile unsigned short *)CAN_MB11_DATA1)
-#define pCAN_MB11_DATA0		((volatile unsigned short *)CAN_MB11_DATA0)
-
-#define pCAN_MB12_ID1		((volatile unsigned short *)CAN_MB12_ID1)
-#define pCAN_MB12_ID0		((volatile unsigned short *)CAN_MB12_ID0)
-#define pCAN_MB12_TIMESTAMP	((volatile unsigned short *)CAN_MB12_TIMESTAMP)
-#define pCAN_MB12_LENGTH	((volatile unsigned short *)CAN_MB12_LENGTH)
-#define pCAN_MB12_DATA3		((volatile unsigned short *)CAN_MB12_DATA3)
-#define pCAN_MB12_DATA2		((volatile unsigned short *)CAN_MB12_DATA2)
-#define pCAN_MB12_DATA1		((volatile unsigned short *)CAN_MB12_DATA1)
-#define pCAN_MB12_DATA0		((volatile unsigned short *)CAN_MB12_DATA0)
-
-#define pCAN_MB13_ID1		((volatile unsigned short *)CAN_MB13_ID1)
-#define pCAN_MB13_ID0		((volatile unsigned short *)CAN_MB13_ID0)
-#define pCAN_MB13_TIMESTAMP	((volatile unsigned short *)CAN_MB13_TIMESTAMP)
-#define pCAN_MB13_LENGTH	((volatile unsigned short *)CAN_MB13_LENGTH)
-#define pCAN_MB13_DATA3		((volatile unsigned short *)CAN_MB13_DATA3)
-#define pCAN_MB13_DATA2		((volatile unsigned short *)CAN_MB13_DATA2)
-#define pCAN_MB13_DATA1		((volatile unsigned short *)CAN_MB13_DATA1)
-#define pCAN_MB13_DATA0		((volatile unsigned short *)CAN_MB13_DATA0)
-
-#define pCAN_MB14_ID1		((volatile unsigned short *)CAN_MB14_ID1)
-#define pCAN_MB14_ID0		((volatile unsigned short *)CAN_MB14_ID0)
-#define pCAN_MB14_TIMESTAMP	((volatile unsigned short *)CAN_MB14_TIMESTAMP)
-#define pCAN_MB14_LENGTH	((volatile unsigned short *)CAN_MB14_LENGTH)
-#define pCAN_MB14_DATA3		((volatile unsigned short *)CAN_MB14_DATA3)
-#define pCAN_MB14_DATA2		((volatile unsigned short *)CAN_MB14_DATA2)
-#define pCAN_MB14_DATA1		((volatile unsigned short *)CAN_MB14_DATA1)
-#define pCAN_MB14_DATA0		((volatile unsigned short *)CAN_MB14_DATA0)
-
-#define pCAN_MB15_ID1		((volatile unsigned short *)CAN_MB15_ID1)
-#define pCAN_MB15_ID0		((volatile unsigned short *)CAN_MB15_ID0)
-#define pCAN_MB15_TIMESTAMP	((volatile unsigned short *)CAN_MB15_TIMESTAMP)
-#define pCAN_MB15_LENGTH	((volatile unsigned short *)CAN_MB15_LENGTH)
-#define pCAN_MB15_DATA3		((volatile unsigned short *)CAN_MB15_DATA3)
-#define pCAN_MB15_DATA2		((volatile unsigned short *)CAN_MB15_DATA2)
-#define pCAN_MB15_DATA1		((volatile unsigned short *)CAN_MB15_DATA1)
-#define pCAN_MB15_DATA0		((volatile unsigned short *)CAN_MB15_DATA0)
-
-#define pCAN_MB16_ID1		((volatile unsigned short *)CAN_MB16_ID1)
-#define pCAN_MB16_ID0		((volatile unsigned short *)CAN_MB16_ID0)
-#define pCAN_MB16_TIMESTAMP	((volatile unsigned short *)CAN_MB16_TIMESTAMP)
-#define pCAN_MB16_LENGTH	((volatile unsigned short *)CAN_MB16_LENGTH)
-#define pCAN_MB16_DATA3		((volatile unsigned short *)CAN_MB16_DATA3)
-#define pCAN_MB16_DATA2		((volatile unsigned short *)CAN_MB16_DATA2)
-#define pCAN_MB16_DATA1		((volatile unsigned short *)CAN_MB16_DATA1)
-#define pCAN_MB16_DATA0		((volatile unsigned short *)CAN_MB16_DATA0)
-
-#define pCAN_MB17_ID1		((volatile unsigned short *)CAN_MB17_ID1)
-#define pCAN_MB17_ID0		((volatile unsigned short *)CAN_MB17_ID0)
-#define pCAN_MB17_TIMESTAMP	((volatile unsigned short *)CAN_MB17_TIMESTAMP)
-#define pCAN_MB17_LENGTH	((volatile unsigned short *)CAN_MB17_LENGTH)
-#define pCAN_MB17_DATA3		((volatile unsigned short *)CAN_MB17_DATA3)
-#define pCAN_MB17_DATA2		((volatile unsigned short *)CAN_MB17_DATA2)
-#define pCAN_MB17_DATA1		((volatile unsigned short *)CAN_MB17_DATA1)
-#define pCAN_MB17_DATA0		((volatile unsigned short *)CAN_MB17_DATA0)
-
-#define pCAN_MB18_ID1		((volatile unsigned short *)CAN_MB18_ID1)
-#define pCAN_MB18_ID0		((volatile unsigned short *)CAN_MB18_ID0)
-#define pCAN_MB18_TIMESTAMP	((volatile unsigned short *)CAN_MB18_TIMESTAMP)
-#define pCAN_MB18_LENGTH	((volatile unsigned short *)CAN_MB18_LENGTH)
-#define pCAN_MB18_DATA3		((volatile unsigned short *)CAN_MB18_DATA3)
-#define pCAN_MB18_DATA2		((volatile unsigned short *)CAN_MB18_DATA2)
-#define pCAN_MB18_DATA1		((volatile unsigned short *)CAN_MB18_DATA1)
-#define pCAN_MB18_DATA0		((volatile unsigned short *)CAN_MB18_DATA0)
-
-#define pCAN_MB19_ID1		((volatile unsigned short *)CAN_MB19_ID1)
-#define pCAN_MB19_ID0		((volatile unsigned short *)CAN_MB19_ID0)
-#define pCAN_MB19_TIMESTAMP	((volatile unsigned short *)CAN_MB19_TIMESTAMP)
-#define pCAN_MB19_LENGTH	((volatile unsigned short *)CAN_MB19_LENGTH)
-#define pCAN_MB19_DATA3		((volatile unsigned short *)CAN_MB19_DATA3)
-#define pCAN_MB19_DATA2		((volatile unsigned short *)CAN_MB19_DATA2)
-#define pCAN_MB19_DATA1		((volatile unsigned short *)CAN_MB19_DATA1)
-#define pCAN_MB19_DATA0		((volatile unsigned short *)CAN_MB19_DATA0)
-
-#define pCAN_MB20_ID1		((volatile unsigned short *)CAN_MB20_ID1)
-#define pCAN_MB20_ID0		((volatile unsigned short *)CAN_MB20_ID0)
-#define pCAN_MB20_TIMESTAMP	((volatile unsigned short *)CAN_MB20_TIMESTAMP)
-#define pCAN_MB20_LENGTH	((volatile unsigned short *)CAN_MB20_LENGTH)
-#define pCAN_MB20_DATA3		((volatile unsigned short *)CAN_MB20_DATA3)
-#define pCAN_MB20_DATA2		((volatile unsigned short *)CAN_MB20_DATA2)
-#define pCAN_MB20_DATA1		((volatile unsigned short *)CAN_MB20_DATA1)
-#define pCAN_MB20_DATA0		((volatile unsigned short *)CAN_MB20_DATA0)
-
-#define pCAN_MB21_ID1		((volatile unsigned short *)CAN_MB21_ID1)
-#define pCAN_MB21_ID0		((volatile unsigned short *)CAN_MB21_ID0)
-#define pCAN_MB21_TIMESTAMP	((volatile unsigned short *)CAN_MB21_TIMESTAMP)
-#define pCAN_MB21_LENGTH	((volatile unsigned short *)CAN_MB21_LENGTH)
-#define pCAN_MB21_DATA3		((volatile unsigned short *)CAN_MB21_DATA3)
-#define pCAN_MB21_DATA2		((volatile unsigned short *)CAN_MB21_DATA2)
-#define pCAN_MB21_DATA1		((volatile unsigned short *)CAN_MB21_DATA1)
-#define pCAN_MB21_DATA0		((volatile unsigned short *)CAN_MB21_DATA0)
-
-#define pCAN_MB22_ID1		((volatile unsigned short *)CAN_MB22_ID1)
-#define pCAN_MB22_ID0		((volatile unsigned short *)CAN_MB22_ID0)
-#define pCAN_MB22_TIMESTAMP	((volatile unsigned short *)CAN_MB22_TIMESTAMP)
-#define pCAN_MB22_LENGTH	((volatile unsigned short *)CAN_MB22_LENGTH)
-#define pCAN_MB22_DATA3		((volatile unsigned short *)CAN_MB22_DATA3)
-#define pCAN_MB22_DATA2		((volatile unsigned short *)CAN_MB22_DATA2)
-#define pCAN_MB22_DATA1		((volatile unsigned short *)CAN_MB22_DATA1)
-#define pCAN_MB22_DATA0		((volatile unsigned short *)CAN_MB22_DATA0)
-
-#define pCAN_MB23_ID1		((volatile unsigned short *)CAN_MB23_ID1)
-#define pCAN_MB23_ID0		((volatile unsigned short *)CAN_MB23_ID0)
-#define pCAN_MB23_TIMESTAMP	((volatile unsigned short *)CAN_MB23_TIMESTAMP)
-#define pCAN_MB23_LENGTH	((volatile unsigned short *)CAN_MB23_LENGTH)
-#define pCAN_MB23_DATA3		((volatile unsigned short *)CAN_MB23_DATA3)
-#define pCAN_MB23_DATA2		((volatile unsigned short *)CAN_MB23_DATA2)
-#define pCAN_MB23_DATA1		((volatile unsigned short *)CAN_MB23_DATA1)
-#define pCAN_MB23_DATA0		((volatile unsigned short *)CAN_MB23_DATA0)
-
-#define pCAN_MB24_ID1		((volatile unsigned short *)CAN_MB24_ID1)
-#define pCAN_MB24_ID0		((volatile unsigned short *)CAN_MB24_ID0)
-#define pCAN_MB24_TIMESTAMP	((volatile unsigned short *)CAN_MB24_TIMESTAMP)
-#define pCAN_MB24_LENGTH	((volatile unsigned short *)CAN_MB24_LENGTH)
-#define pCAN_MB24_DATA3		((volatile unsigned short *)CAN_MB24_DATA3)
-#define pCAN_MB24_DATA2		((volatile unsigned short *)CAN_MB24_DATA2)
-#define pCAN_MB24_DATA1		((volatile unsigned short *)CAN_MB24_DATA1)
-#define pCAN_MB24_DATA0		((volatile unsigned short *)CAN_MB24_DATA0)
-
-#define pCAN_MB25_ID1		((volatile unsigned short *)CAN_MB25_ID1)
-#define pCAN_MB25_ID0		((volatile unsigned short *)CAN_MB25_ID0)
-#define pCAN_MB25_TIMESTAMP	((volatile unsigned short *)CAN_MB25_TIMESTAMP)
-#define pCAN_MB25_LENGTH	((volatile unsigned short *)CAN_MB25_LENGTH)
-#define pCAN_MB25_DATA3		((volatile unsigned short *)CAN_MB25_DATA3)
-#define pCAN_MB25_DATA2		((volatile unsigned short *)CAN_MB25_DATA2)
-#define pCAN_MB25_DATA1		((volatile unsigned short *)CAN_MB25_DATA1)
-#define pCAN_MB25_DATA0		((volatile unsigned short *)CAN_MB25_DATA0)
-
-#define pCAN_MB26_ID1		((volatile unsigned short *)CAN_MB26_ID1)
-#define pCAN_MB26_ID0		((volatile unsigned short *)CAN_MB26_ID0)
-#define pCAN_MB26_TIMESTAMP	((volatile unsigned short *)CAN_MB26_TIMESTAMP)
-#define pCAN_MB26_LENGTH	((volatile unsigned short *)CAN_MB26_LENGTH)
-#define pCAN_MB26_DATA3		((volatile unsigned short *)CAN_MB26_DATA3)
-#define pCAN_MB26_DATA2		((volatile unsigned short *)CAN_MB26_DATA2)
-#define pCAN_MB26_DATA1		((volatile unsigned short *)CAN_MB26_DATA1)
-#define pCAN_MB26_DATA0		((volatile unsigned short *)CAN_MB26_DATA0)
-
-#define pCAN_MB27_ID1		((volatile unsigned short *)CAN_MB27_ID1)
-#define pCAN_MB27_ID0		((volatile unsigned short *)CAN_MB27_ID0)
-#define pCAN_MB27_TIMESTAMP	((volatile unsigned short *)CAN_MB27_TIMESTAMP)
-#define pCAN_MB27_LENGTH	((volatile unsigned short *)CAN_MB27_LENGTH)
-#define pCAN_MB27_DATA3		((volatile unsigned short *)CAN_MB27_DATA3)
-#define pCAN_MB27_DATA2		((volatile unsigned short *)CAN_MB27_DATA2)
-#define pCAN_MB27_DATA1		((volatile unsigned short *)CAN_MB27_DATA1)
-#define pCAN_MB27_DATA0		((volatile unsigned short *)CAN_MB27_DATA0)
-
-#define pCAN_MB28_ID1		((volatile unsigned short *)CAN_MB28_ID1)
-#define pCAN_MB28_ID0		((volatile unsigned short *)CAN_MB28_ID0)
-#define pCAN_MB28_TIMESTAMP	((volatile unsigned short *)CAN_MB28_TIMESTAMP)
-#define pCAN_MB28_LENGTH	((volatile unsigned short *)CAN_MB28_LENGTH)
-#define pCAN_MB28_DATA3		((volatile unsigned short *)CAN_MB28_DATA3)
-#define pCAN_MB28_DATA2		((volatile unsigned short *)CAN_MB28_DATA2)
-#define pCAN_MB28_DATA1		((volatile unsigned short *)CAN_MB28_DATA1)
-#define pCAN_MB28_DATA0		((volatile unsigned short *)CAN_MB28_DATA0)
-
-#define pCAN_MB29_ID1		((volatile unsigned short *)CAN_MB29_ID1)
-#define pCAN_MB29_ID0		((volatile unsigned short *)CAN_MB29_ID0)
-#define pCAN_MB29_TIMESTAMP	((volatile unsigned short *)CAN_MB29_TIMESTAMP)
-#define pCAN_MB29_LENGTH	((volatile unsigned short *)CAN_MB29_LENGTH)
-#define pCAN_MB29_DATA3		((volatile unsigned short *)CAN_MB29_DATA3)
-#define pCAN_MB29_DATA2		((volatile unsigned short *)CAN_MB29_DATA2)
-#define pCAN_MB29_DATA1		((volatile unsigned short *)CAN_MB29_DATA1)
-#define pCAN_MB29_DATA0		((volatile unsigned short *)CAN_MB29_DATA0)
-
-#define pCAN_MB30_ID1		((volatile unsigned short *)CAN_MB30_ID1)
-#define pCAN_MB30_ID0		((volatile unsigned short *)CAN_MB30_ID0)
-#define pCAN_MB30_TIMESTAMP	((volatile unsigned short *)CAN_MB30_TIMESTAMP)
-#define pCAN_MB30_LENGTH	((volatile unsigned short *)CAN_MB30_LENGTH)
-#define pCAN_MB30_DATA3		((volatile unsigned short *)CAN_MB30_DATA3)
-#define pCAN_MB30_DATA2		((volatile unsigned short *)CAN_MB30_DATA2)
-#define pCAN_MB30_DATA1		((volatile unsigned short *)CAN_MB30_DATA1)
-#define pCAN_MB30_DATA0		((volatile unsigned short *)CAN_MB30_DATA0)
-
-#define pCAN_MB31_ID1		((volatile unsigned short *)CAN_MB31_ID1)
-#define pCAN_MB31_ID0		((volatile unsigned short *)CAN_MB31_ID0)
-#define pCAN_MB31_TIMESTAMP	((volatile unsigned short *)CAN_MB31_TIMESTAMP)
-#define pCAN_MB31_LENGTH	((volatile unsigned short *)CAN_MB31_LENGTH)
-#define pCAN_MB31_DATA3		((volatile unsigned short *)CAN_MB31_DATA3)
-#define pCAN_MB31_DATA2		((volatile unsigned short *)CAN_MB31_DATA2)
-#define pCAN_MB31_DATA1		((volatile unsigned short *)CAN_MB31_DATA1)
-#define pCAN_MB31_DATA0		((volatile unsigned short *)CAN_MB31_DATA0)
-
-/* CAN Mailbox Area Macros		*/
-#define pCAN_MB_ID1(x)		((volatile unsigned short *)CAN_MB_ID1(x))
-#define pCAN_MB_ID0(x)		((volatile unsigned short *)CAN_MB_ID0(x))
-#define pCAN_MB_TIMESTAMP(x)	((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
-#define pCAN_MB_LENGTH(x)	((volatile unsigned short *)CAN_MB_LENGTH(x))
-#define pCAN_MB_DATA3(x)	((volatile unsigned short *)CAN_MB_DATA3(x))
-#define pCAN_MB_DATA2(x)	((volatile unsigned short *)CAN_MB_DATA2(x))
-#define pCAN_MB_DATA1(x)	((volatile unsigned short *)CAN_MB_DATA1(x))
-#define pCAN_MB_DATA0(x)	((volatile unsigned short *)CAN_MB_DATA0(x))
-
-
-/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)								*/
-#define pPORTF_FER		((volatile unsigned short *)PORTF_FER)
-#define pPORTG_FER		((volatile unsigned short *)PORTG_FER)
-#define pPORTH_FER		((volatile unsigned short *)PORTH_FER)
-#define pPORT_MUX		((volatile unsigned short *)PORT_MUX)
-
-
-/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)								*/
-#define pHMDMA0_CONTROL		((volatile unsigned short *)HMDMA0_CONTROL)
-#define pHMDMA0_ECINIT		((volatile unsigned short *)HMDMA0_ECINIT)
-#define pHMDMA0_BCINIT		((volatile unsigned short *)HMDMA0_BCINIT)
-#define pHMDMA0_ECURGENT	((volatile unsigned short *)HMDMA0_ECURGENT)
-#define pHMDMA0_ECOVERFLOW	((volatile unsigned short *)HMDMA0_ECOVERFLOW)
-#define pHMDMA0_ECOUNT		((volatile unsigned short *)HMDMA0_ECOUNT)
-#define pHMDMA0_BCOUNT		((volatile unsigned short *)HMDMA0_BCOUNT)
-
-#define pHMDMA1_CONTROL		((volatile unsigned short *)HMDMA1_CONTROL)
-#define pHMDMA1_ECINIT		((volatile unsigned short *)HMDMA1_ECINIT)
-#define pHMDMA1_BCINIT		((volatile unsigned short *)HMDMA1_BCINIT)
-#define pHMDMA1_ECURGENT	((volatile unsigned short *)HMDMA1_ECURGENT)
-#define pHMDMA1_ECOVERFLOW	((volatile unsigned short *)HMDMA1_ECOVERFLOW)
-#define pHMDMA1_ECOUNT		((volatile unsigned short *)HMDMA1_ECOUNT)
-#define pHMDMA1_BCOUNT		((volatile unsigned short *)HMDMA1_BCOUNT)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF534_H */
diff --git a/libgloss/bfin/include/cdefBF535.h b/libgloss/bfin/include/cdefBF535.h
deleted file mode 100644
index cd991d069..000000000
--- a/libgloss/bfin/include/cdefBF535.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF535.h
- *
- * (c) Copyright 2002-2005 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEF_BF535_H
-#define _CDEF_BF535_H
-
-/* include all Core registers and bit definitions */
-#if defined(__ADSPLPBLACKFIN__)
-#warning cdefBF535.h should only be included for 535 compatible chips.
-#endif
-#include <defBF535.h>
-
-/* include core specific register pointer definitions */
-#include <cdefblackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define pPLL_CTL ((volatile unsigned long *)PLL_CTL)
-#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
-#define pSWRST ((volatile unsigned short *)SWRST)
-#define pSYSCR ((volatile unsigned short *)SYSCR)
-#define pPLL_IOCKR ((volatile unsigned short *)PLL_IOCKR)
-#define pPLL_IOCK ((volatile unsigned short *)PLL_IOCK)
-
-/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
-#define pCHIPID ((volatile unsigned long *)CHIPID)
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
-#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
-#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
-#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
-#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
-#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
-#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
-#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
-#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
-#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
-#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
-#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
-#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
-#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
-#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
-#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
-#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
-#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
-
-/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
-#define pUSBD_ID ((volatile unsigned short *)USBD_ID)
-#define pUSBD_FRM ((volatile unsigned short *)USBD_FRM)
-#define pUSBD_FRMAT ((volatile unsigned short *)USBD_FRMAT)
-#define pUSBD_EPBUF ((volatile unsigned short *)USBD_EPBUF)
-#define pUSBD_STAT ((volatile unsigned short *)USBD_STAT)
-#define pUSBD_CTRL ((volatile unsigned short *)USBD_CTRL)
-#define pUSBD_GINTR ((volatile unsigned short *)USBD_GINTR)
-#define pUSBD_GMASK ((volatile unsigned short *)USBD_GMASK)
-#define pUSBD_DMACFG ((volatile unsigned short *)USBD_DMACFG)
-#define pUSBD_DMABL ((volatile unsigned short *)USBD_DMABL)
-#define pUSBD_DMABH ((volatile unsigned short *)USBD_DMABH)
-#define pUSBD_DMACT ((volatile unsigned short *)USBD_DMACT)
-#define pUSBD_DMAIRQ ((volatile unsigned short *)USBD_DMAIRQ)
-#define pUSBD_INTR0 ((volatile unsigned short *)USBD_INTR0)
-#define pUSBD_MASK0 ((volatile unsigned short *)USBD_MASK0)
-#define pUSBD_EPCFG0 ((volatile unsigned short *)USBD_EPCFG0)
-#define pUSBD_EPADR0 ((volatile unsigned short *)USBD_EPADR0)
-#define pUSBD_EPLEN0 ((volatile unsigned short *)USBD_EPLEN0)
-#define pUSBD_INTR1 ((volatile unsigned short *)USBD_INTR1)
-#define pUSBD_MASK1 ((volatile unsigned short *)USBD_MASK1)
-#define pUSBD_EPCFG1 ((volatile unsigned short *)USBD_EPCFG1)
-#define pUSBD_EPADR1 ((volatile unsigned short *)USBD_EPADR1)
-#define pUSBD_EPLEN1 ((volatile unsigned short *)USBD_EPLEN1)
-#define pUSBD_INTR2 ((volatile unsigned short *)USBD_INTR2)
-#define pUSBD_MASK2 ((volatile unsigned short *)USBD_MASK2)
-#define pUSBD_EPCFG2 ((volatile unsigned short *)USBD_EPCFG2)
-#define pUSBD_EPADR2 ((volatile unsigned short *)USBD_EPADR2)
-#define pUSBD_EPLEN2 ((volatile unsigned short *)USBD_EPLEN2)
-#define pUSBD_INTR3 ((volatile unsigned short *)USBD_INTR3)
-#define pUSBD_MASK3 ((volatile unsigned short *)USBD_MASK3)
-#define pUSBD_EPCFG3 ((volatile unsigned short *)USBD_EPCFG3)
-#define pUSBD_EPADR3 ((volatile unsigned short *)USBD_EPADR3)
-#define pUSBD_EPLEN3 ((volatile unsigned short *)USBD_EPLEN3)
-#define pUSBD_INTR4 ((volatile unsigned short *)USBD_INTR4)
-#define pUSBD_MASK4 ((volatile unsigned short *)USBD_MASK4)
-#define pUSBD_EPCFG4 ((volatile unsigned short *)USBD_EPCFG4)
-#define pUSBD_EPADR4 ((volatile unsigned short *)USBD_EPADR4)
-#define pUSBD_EPLEN4 ((volatile unsigned short *)USBD_EPLEN4)
-#define pUSBD_INTR5 ((volatile unsigned short *)USBD_INTR5)
-#define pUSBD_MASK5 ((volatile unsigned short *)USBD_MASK5)
-#define pUSBD_EPCFG5 ((volatile unsigned short *)USBD_EPCFG5)
-#define pUSBD_EPADR5 ((volatile unsigned short *)USBD_EPADR5)
-#define pUSBD_EPLEN5 ((volatile unsigned short *)USBD_EPLEN5)
-#define pUSBD_INTR6 ((volatile unsigned short *)USBD_INTR6)
-#define pUSBD_MASK6 ((volatile unsigned short *)USBD_MASK6)
-#define pUSBD_EPCFG6 ((volatile unsigned short *)USBD_EPCFG6)
-#define pUSBD_EPADR6 ((volatile unsigned short *)USBD_EPADR6)
-#define pUSBD_EPLEN6 ((volatile unsigned short *)USBD_EPLEN6)
-#define pUSBD_INTR7 ((volatile unsigned short *)USBD_INTR7)
-#define pUSBD_MASK7 ((volatile unsigned short *)USBD_MASK7)
-#define pUSBD_EPCFG7 ((volatile unsigned short *)USBD_EPCFG7)
-#define pUSBD_EPADR7 ((volatile unsigned short *)USBD_EPADR7)
-#define pUSBD_EPLEN7 ((volatile unsigned short *)USBD_EPLEN7)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
-#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
-#define pEBIU_SDBCTL ((volatile unsigned long *)EBIU_SDBCTL)
-
-/* Memory Map */
-
-/* Core MMRs */
-#define pCOREMMR_BASE ((volatile void *)COREMMR_BASE)
-
-/* System MMRs */
-#define pSYSMMR_BASE ((volatile void *)SYSMMR_BASE)
-
-/* L1 cache/SRAM internal memory */
-#define pL1_DATA_A ((void *)L1_DATA_A)
-#define pL1_DATA_B ((void *)L1_DATA_B)
-#define pL1_CODE ((void *)L1_CODE)
-#define pL1_SCRATCH ((void *)L1_SCRATCH)
-
-/* L2 SRAM external memory */
-#define pL2_BASE ((void *)L2_BASE)
-
-/* PCI Spaces */
-#define pPCI_CONFIG_SPACE_PORT ((volatile void *)PCI_CONFIG_SPACE_PORT)
-#define pPCI_CONFIG_BASE ((volatile void *)PCI_CONFIG_BASE)
-#define pPCI_IO_BASE ((volatile void *)PCI_IO_BASE)
-#define pPCI_MEM_BASE ((volatile void *)PCI_MEM_BASE)
-
-/* Async Memory Banks */
-#define pASYNC_BANK3_BASE ((void *)ASYNC_BANK3_BASE)
-#define pASYNC_BANK2_BASE ((void *)ASYNC_BANK2_BASE)
-#define pASYNC_BANK1_BASE ((void *)ASYNC_BANK1_BASE)
-#define pASYNC_BANK0_BASE ((void *)ASYNC_BANK0_BASE)
-
-/* Sync DRAM Banks */
-#define pSDRAM_BANK3_BASE ((void *)SDRAM_BANK3_BASE)
-#define pSDRAM_BANK2_BASE ((void *)SDRAM_BANK2_BASE)
-#define pSDRAM_BANK1_BASE ((void *)SDRAM_BANK1_BASE)
-#define pSDRAM_BANK0_BASE ((void *)SDRAM_BANK0_BASE)
-
-/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
-#define pUART0_THR ((volatile unsigned short *)UART0_THR)
-#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
-#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
-#define pUART0_IER ((volatile unsigned short *)UART0_IER)
-#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
-#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
-#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
-#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
-#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
-#define pUART0_MSR ((volatile unsigned short *)UART0_MSR)
-#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
-#define pUART0_IRCR ((volatile unsigned short *)UART0_IRCR)
-#define pUART0_CURR_PTR_RX ((volatile unsigned short *)UART0_CURR_PTR_RX)
-#define pUART0_CONFIG_RX ((volatile unsigned short *)UART0_CONFIG_RX)
-#define pUART0_START_ADDR_HI_RX ((volatile unsigned short *)UART0_START_ADDR_HI_RX)
-#define pUART0_START_ADDR_LO_RX ((volatile unsigned short *)UART0_START_ADDR_LO_RX)
-#define pUART0_COUNT_RX ((volatile unsigned short *)UART0_COUNT_RX)
-#define pUART0_NEXT_DESCR_RX ((volatile unsigned short *)UART0_NEXT_DESCR_RX)
-#define pUART0_DESCR_RDY_RX ((volatile unsigned short *)UART0_DESCR_RDY_RX)
-#define pUART0_IRQSTAT_RX ((volatile unsigned short *)UART0_IRQSTAT_RX)
-#define pUART0_CURR_PTR_TX ((volatile unsigned short *)UART0_CURR_PTR_TX)
-#define pUART0_CONFIG_TX ((volatile unsigned short *)UART0_CONFIG_TX)
-#define pUART0_START_ADDR_HI_TX ((volatile unsigned short *)UART0_START_ADDR_HI_TX)
-#define pUART0_START_ADDR_LO_TX ((volatile unsigned short *)UART0_START_ADDR_LO_TX)
-#define pUART0_COUNT_TX ((volatile unsigned short *)UART0_COUNT_TX)
-#define pUART0_NEXT_DESCR_TX ((volatile unsigned short *)UART0_NEXT_DESCR_TX)
-#define pUART0_DESCR_RDY_TX ((volatile unsigned short *)UART0_DESCR_RDY_TX)
-#define pUART0_IRQSTAT_TX ((volatile unsigned short *)UART0_IRQSTAT_TX)
-
-/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
-#define pUART1_THR ((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER ((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
-#define pUART1_MSR ((volatile unsigned short *)UART1_MSR)
-#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
-#define pUART1_CURR_PTR_RX ((volatile unsigned short *)UART1_CURR_PTR_RX)
-#define pUART1_CONFIG_RX ((volatile unsigned short *)UART1_CONFIG_RX)
-#define pUART1_START_ADDR_HI_RX ((volatile unsigned short *)UART1_START_ADDR_HI_RX)
-#define pUART1_START_ADDR_LO_RX ((volatile unsigned short *)UART1_START_ADDR_LO_RX)
-#define pUART1_COUNT_RX ((volatile unsigned short *)UART1_COUNT_RX)
-#define pUART1_NEXT_DESCR_RX ((volatile unsigned short *)UART1_NEXT_DESCR_RX)
-#define pUART1_DESCR_RDY_RX ((volatile unsigned short *)UART1_DESCR_RDY_RX)
-#define pUART1_IRQSTAT_RX ((volatile unsigned short *)UART1_IRQSTAT_RX)
-#define pUART1_CURR_PTR_TX ((volatile unsigned short *)UART1_CURR_PTR_TX)
-#define pUART1_CONFIG_TX ((volatile unsigned short *)UART1_CONFIG_TX)
-#define pUART1_START_ADDR_HI_TX ((volatile unsigned short *)UART1_START_ADDR_HI_TX)
-#define pUART1_START_ADDR_LO_TX ((volatile unsigned short *)UART1_START_ADDR_LO_TX)
-#define pUART1_COUNT_TX ((volatile unsigned short *)UART1_COUNT_TX)
-#define pUART1_NEXT_DESCR_TX ((volatile unsigned short *)UART1_NEXT_DESCR_TX)
-#define pUART1_DESCR_RDY_TX ((volatile unsigned short *)UART1_DESCR_RDY_TX)
-#define pUART1_IRQSTAT_TX ((volatile unsigned short *)UART1_IRQSTAT_TX)
-
-/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
-#define pTIMER0_STATUS ((volatile unsigned short *)TIMER0_STATUS)
-#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER_LO ((volatile unsigned short *)TIMER0_COUNTER_LO)
-#define pTIMER0_COUNTER_HI ((volatile unsigned short *)TIMER0_COUNTER_HI)
-#define pTIMER0_PERIOD_LO ((volatile unsigned short *)TIMER0_PERIOD_LO)
-#define pTIMER0_PERIOD_HI ((volatile unsigned short *)TIMER0_PERIOD_HI)
-#define pTIMER0_WIDTH_LO ((volatile unsigned short *)TIMER0_WIDTH_LO)
-#define pTIMER0_WIDTH_HI ((volatile unsigned short *)TIMER0_WIDTH_HI)
-#define pTIMER1_STATUS ((volatile unsigned short *)TIMER1_STATUS)
-#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER_LO ((volatile unsigned short *)TIMER1_COUNTER_LO)
-#define pTIMER1_COUNTER_HI ((volatile unsigned short *)TIMER1_COUNTER_HI)
-#define pTIMER1_PERIOD_LO ((volatile unsigned short *)TIMER1_PERIOD_LO)
-#define pTIMER1_PERIOD_HI ((volatile unsigned short *)TIMER1_PERIOD_HI)
-#define pTIMER1_WIDTH_LO ((volatile unsigned short *)TIMER1_WIDTH_LO)
-#define pTIMER1_WIDTH_HI ((volatile unsigned short *)TIMER1_WIDTH_HI)
-#define pTIMER2_STATUS ((volatile unsigned short *)TIMER2_STATUS)
-#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER_LO ((volatile unsigned short *)TIMER2_COUNTER_LO)
-#define pTIMER2_COUNTER_HI ((volatile unsigned short *)TIMER2_COUNTER_HI)
-#define pTIMER2_PERIOD_LO ((volatile unsigned short *)TIMER2_PERIOD_LO)
-#define pTIMER2_PERIOD_HI ((volatile unsigned short *)TIMER2_PERIOD_HI)
-#define pTIMER2_WIDTH_LO ((volatile unsigned short *)TIMER2_WIDTH_LO)
-#define pTIMER2_WIDTH_HI ((volatile unsigned short *)TIMER2_WIDTH_HI)
-
-/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
-#define pSPORT0_TX_CONFIG ((volatile unsigned short *)SPORT0_TX_CONFIG)
-#define pSPORT0_RX_CONFIG ((volatile unsigned short *)SPORT0_RX_CONFIG)
-#define pSPORT0_TX ((volatile short *)SPORT0_TX)
-#define pSPORT0_RX ((volatile short *)SPORT0_RX)
-#define pSPORT0_TSCLKDIV ((volatile unsigned short *)SPORT0_TSCLKDIV)
-#define pSPORT0_RSCLKDIV ((volatile unsigned short *)SPORT0_RSCLKDIV)
-#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_MTCS0 ((volatile unsigned short *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 ((volatile unsigned short *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 ((volatile unsigned short *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 ((volatile unsigned short *)SPORT0_MTCS3)
-#define pSPORT0_MTCS4 ((volatile unsigned short *)SPORT0_MTCS4)
-#define pSPORT0_MTCS5 ((volatile unsigned short *)SPORT0_MTCS5)
-#define pSPORT0_MTCS6 ((volatile unsigned short *)SPORT0_MTCS6)
-#define pSPORT0_MTCS7 ((volatile unsigned short *)SPORT0_MTCS7)
-#define pSPORT0_MRCS0 ((volatile unsigned short *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 ((volatile unsigned short *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 ((volatile unsigned short *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 ((volatile unsigned short *)SPORT0_MRCS3)
-#define pSPORT0_MRCS4 ((volatile unsigned short *)SPORT0_MRCS4)
-#define pSPORT0_MRCS5 ((volatile unsigned short *)SPORT0_MRCS5)
-#define pSPORT0_MRCS6 ((volatile unsigned short *)SPORT0_MRCS6)
-#define pSPORT0_MRCS7 ((volatile unsigned short *)SPORT0_MRCS7)
-#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_CURR_PTR_RX ((volatile unsigned short *)SPORT0_CURR_PTR_RX)
-#define pSPORT0_CONFIG_DMA_RX ((volatile unsigned short *)SPORT0_CONFIG_DMA_RX)
-#define pSPORT0_START_ADDR_HI_RX ((volatile unsigned short *)SPORT0_START_ADDR_HI_RX)
-#define pSPORT0_START_ADDR_LO_RX ((volatile unsigned short *)SPORT0_START_ADDR_LO_RX)
-#define pSPORT0_COUNT_RX ((volatile unsigned short *)SPORT0_COUNT_RX)
-#define pSPORT0_NEXT_DESCR_RX ((volatile unsigned short *)SPORT0_NEXT_DESCR_RX)
-#define pSPORT0_DESCR_RDY_RX ((volatile unsigned short *)SPORT0_DESCR_RDY_RX)
-#define pSPORT0_IRQSTAT_RX ((volatile unsigned short *)SPORT0_IRQSTAT_RX)
-#define pSPORT0_CURR_PTR_TX ((volatile unsigned short *)SPORT0_CURR_PTR_TX)
-#define pSPORT0_CONFIG_DMA_TX ((volatile unsigned short *)SPORT0_CONFIG_DMA_TX)
-#define pSPORT0_START_ADDR_HI_TX ((volatile unsigned short *)SPORT0_START_ADDR_HI_TX)
-#define pSPORT0_START_ADDR_LO_TX ((volatile unsigned short *)SPORT0_START_ADDR_LO_TX)
-#define pSPORT0_COUNT_TX ((volatile unsigned short *)SPORT0_COUNT_TX)
-#define pSPORT0_NEXT_DESCR_TX ((volatile unsigned short *)SPORT0_NEXT_DESCR_TX)
-#define pSPORT0_DESCR_RDY_TX ((volatile unsigned short *)SPORT0_DESCR_RDY_TX)
-#define pSPORT0_IRQSTAT_TX ((volatile unsigned short *)SPORT0_IRQSTAT_TX)
-
-/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
-#define pSPORT1_TX_CONFIG ((volatile unsigned short *)SPORT1_TX_CONFIG)
-#define pSPORT1_RX_CONFIG ((volatile unsigned short *)SPORT1_RX_CONFIG)
-#define pSPORT1_TX ((volatile short *)SPORT1_TX)
-#define pSPORT1_RX ((volatile short *)SPORT1_RX)
-#define pSPORT1_TSCLKDIV ((volatile unsigned short *)SPORT1_TSCLKDIV)
-#define pSPORT1_RSCLKDIV ((volatile unsigned short *)SPORT1_RSCLKDIV)
-#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_MTCS0 ((volatile unsigned short *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 ((volatile unsigned short *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 ((volatile unsigned short *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 ((volatile unsigned short *)SPORT1_MTCS3)
-#define pSPORT1_MTCS4 ((volatile unsigned short *)SPORT1_MTCS4)
-#define pSPORT1_MTCS5 ((volatile unsigned short *)SPORT1_MTCS5)
-#define pSPORT1_MTCS6 ((volatile unsigned short *)SPORT1_MTCS6)
-#define pSPORT1_MTCS7 ((volatile unsigned short *)SPORT1_MTCS7)
-#define pSPORT1_MRCS0 ((volatile unsigned short *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 ((volatile unsigned short *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 ((volatile unsigned short *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 ((volatile unsigned short *)SPORT1_MRCS3)
-#define pSPORT1_MRCS4 ((volatile unsigned short *)SPORT1_MRCS4)
-#define pSPORT1_MRCS5 ((volatile unsigned short *)SPORT1_MRCS5)
-#define pSPORT1_MRCS6 ((volatile unsigned short *)SPORT1_MRCS6)
-#define pSPORT1_MRCS7 ((volatile unsigned short *)SPORT1_MRCS7)
-#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_CURR_PTR_RX ((volatile unsigned short *)SPORT1_CURR_PTR_RX)
-#define pSPORT1_CONFIG_DMA_RX ((volatile unsigned short *)SPORT1_CONFIG_DMA_RX)
-#define pSPORT1_START_ADDR_HI_RX ((volatile unsigned short *)SPORT1_START_ADDR_HI_RX)
-#define pSPORT1_START_ADDR_LO_RX ((volatile unsigned short *)SPORT1_START_ADDR_LO_RX)
-#define pSPORT1_COUNT_RX ((volatile unsigned short *)SPORT1_COUNT_RX)
-#define pSPORT1_NEXT_DESCR_RX ((volatile unsigned short *)SPORT1_NEXT_DESCR_RX)
-#define pSPORT1_DESCR_RDY_RX ((volatile unsigned short *)SPORT1_DESCR_RDY_RX)
-#define pSPORT1_IRQSTAT_RX ((volatile unsigned short *)SPORT1_IRQSTAT_RX)
-#define pSPORT1_CURR_PTR_TX ((volatile unsigned short *)SPORT1_CURR_PTR_TX)
-#define pSPORT1_CONFIG_DMA_TX ((volatile unsigned short *)SPORT1_CONFIG_DMA_TX)
-#define pSPORT1_START_ADDR_HI_TX ((volatile unsigned short *)SPORT1_START_ADDR_HI_TX)
-#define pSPORT1_START_ADDR_LO_TX ((volatile unsigned short *)SPORT1_START_ADDR_LO_TX)
-#define pSPORT1_COUNT_TX ((volatile unsigned short *)SPORT1_COUNT_TX)
-#define pSPORT1_NEXT_DESCR_TX ((volatile unsigned short *)SPORT1_NEXT_DESCR_TX)
-#define pSPORT1_DESCR_RDY_TX ((volatile unsigned short *)SPORT1_DESCR_RDY_TX)
-#define pSPORT1_IRQSTAT_TX ((volatile unsigned short *)SPORT1_IRQSTAT_TX)
-
-/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
-#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
-#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
-#define pSPI0_ST ((volatile unsigned short *)SPI0_ST)
-#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
-#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
-#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
-#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
-#define pSPI0_CURR_PTR ((volatile unsigned short *)SPI0_CURR_PTR)
-#define pSPI0_CONFIG ((volatile unsigned short *)SPI0_CONFIG)
-#define pSPI0_START_ADDR_HI ((volatile unsigned short *)SPI0_START_ADDR_HI)
-#define pSPI0_START_ADDR_LO ((volatile unsigned short *)SPI0_START_ADDR_LO)
-#define pSPI0_COUNT ((volatile unsigned short *)SPI0_COUNT)
-#define pSPI0_NEXT_DESCR ((volatile unsigned short *)SPI0_NEXT_DESCR)
-#define pSPI0_DESCR_RDY ((volatile unsigned short *)SPI0_DESCR_RDY)
-#define pSPI0_DMA_INT ((volatile unsigned short *)SPI0_DMA_INT)
-
-/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
-#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
-#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
-#define pSPI1_ST ((volatile unsigned short *)SPI1_ST)
-#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
-#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
-#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
-#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
-#define pSPI1_CURR_PTR ((volatile unsigned short *)SPI1_CURR_PTR)
-#define pSPI1_CONFIG ((volatile unsigned short *)SPI1_CONFIG)
-#define pSPI1_START_ADDR_HI ((volatile unsigned short *)SPI1_START_ADDR_HI)
-#define pSPI1_START_ADDR_LO ((volatile unsigned short *)SPI1_START_ADDR_LO)
-#define pSPI1_COUNT ((volatile unsigned short *)SPI1_COUNT)
-#define pSPI1_NEXT_DESCR ((volatile unsigned short *)SPI1_NEXT_DESCR)
-#define pSPI1_DESCR_RDY ((volatile unsigned short *)SPI1_DESCR_RDY)
-#define pSPI1_DMA_INT ((volatile unsigned short *)SPI1_DMA_INT)
-
-/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
-#define pMDD_DCP ((volatile unsigned short *)MDD_DCP)
-#define pMDD_DCFG ((volatile unsigned short *)MDD_DCFG)
-#define pMDD_DSAH ((volatile unsigned short *)MDD_DSAH)
-#define pMDD_DSAL ((volatile unsigned short *)MDD_DSAL)
-#define pMDD_DCT ((volatile unsigned short *)MDD_DCT)
-#define pMDD_DND ((volatile unsigned short *)MDD_DND)
-#define pMDD_DDR ((volatile unsigned short *)MDD_DDR)
-#define pMDD_DI ((volatile unsigned short *)MDD_DI)
-#define pMDS_DCP ((volatile unsigned short *)MDS_DCP)
-#define pMDS_DCFG ((volatile unsigned short *)MDS_DCFG)
-#define pMDS_DSAH ((volatile unsigned short *)MDS_DSAH)
-#define pMDS_DSAL ((volatile unsigned short *)MDS_DSAL)
-#define pMDS_DCT ((volatile unsigned short *)MDS_DCT)
-#define pMDS_DND ((volatile unsigned short *)MDS_DND)
-#define pMDS_DDR ((volatile unsigned short *)MDS_DDR)
-#define pMDS_DI ((volatile unsigned short *)MDS_DI)
-
-/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
-#define pPCI_CTL ((volatile unsigned short *)PCI_CTL)
-#define pPCI_STAT ((volatile unsigned long *)PCI_STAT)
-#define pPCI_ICTL ((volatile unsigned long *)PCI_ICTL)
-#define pPCI_MBAP (_PTR_TO_VOL_VOID_PTR PCI_MBAP)
-#define pPCI_IBAP (_PTR_TO_VOL_VOID_PTR PCI_IBAP)
-#define pPCI_CBAP (_PTR_TO_VOL_VOID_PTR PCI_CBAP)
-#define pPCI_TMBAP (_PTR_TO_VOL_VOID_PTR PCI_TMBAP)
-#define pPCI_TIBAP (_PTR_TO_VOL_VOID_PTR PCI_TIBAP)
-
-/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
-#define pPCI_DMBARM ((volatile unsigned long *)PCI_DMBARM)
-#define pPCI_DIBARM ((volatile unsigned long *)PCI_DIBARM)
-#define pPCI_CFG_DIC ((volatile unsigned long *)PCI_CFG_DIC)
-#define pPCI_CFG_VIC ((volatile unsigned long *)PCI_CFG_VIC)
-#define pPCI_CFG_STAT ((volatile unsigned long *)PCI_CFG_STAT)
-#define pPCI_CFG_CMD ((volatile unsigned long *)PCI_CFG_CMD)
-#define pPCI_CFG_CC ((volatile unsigned long *)PCI_CFG_CC)
-#define pPCI_CFG_RID ((volatile unsigned long *)PCI_CFG_RID)
-#define pPCI_CFG_BIST ((volatile unsigned long *)PCI_CFG_BIST)
-#define pPCI_CFG_HT ((volatile unsigned long *)PCI_CFG_HT)
-#define pPCI_CFG_MLT ((volatile unsigned long *)PCI_CFG_MLT)
-#define pPCI_CFG_CLS ((volatile unsigned long *)PCI_CFG_CLS)
-#define pPCI_CFG_MBAR ((volatile unsigned long *)PCI_CFG_MBAR)
-#define pPCI_CFG_IBAR ((volatile unsigned long *)PCI_CFG_IBAR)
-#define pPCI_CFG_SID ((volatile unsigned long *)PCI_CFG_SID)
-#define pPCI_CFG_SVID ((volatile unsigned long *)PCI_CFG_SVID)
-#define pPCI_CFG_MAXL ((volatile unsigned long *)PCI_CFG_MAXL)
-#define pPCI_CFG_MING ((volatile unsigned long *)PCI_CFG_MING)
-#define pPCI_CFG_IP ((volatile unsigned long *)PCI_CFG_IP)
-#define pPCI_CFG_IL ((volatile unsigned long *)PCI_CFG_IL)
-#define pPCI_HMCTL ((volatile unsigned long *)PCI_HMCTL)
-
-/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
-#define pDMA_DBP ((volatile unsigned short *)DMA_DBP)
-#define pDB_ACOMP (_PTR_TO_VOL_VOID_PTR DB_ACOMP)
-#define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF535_H */
diff --git a/libgloss/bfin/include/cdefBF536.h b/libgloss/bfin/include/cdefBF536.h
deleted file mode 100644
index fbb186cb0..000000000
--- a/libgloss/bfin/include/cdefBF536.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access.
-**
-**/
-/**********************************************************************************
-** System MMR Register Map
-***********************************************************************************/
-
-#ifndef _CDEF_BF536_H
-#define _CDEF_BF536_H
-
-/* MMR Space Identical to BF537 Processor 								*/
-#include <cdefBF537.h>
-
-#endif /* _CDEF_BF536_H */
-
diff --git a/libgloss/bfin/include/cdefBF537.h b/libgloss/bfin/include/cdefBF537.h
deleted file mode 100644
index f3b468d0c..000000000
--- a/libgloss/bfin/include/cdefBF537.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access.
-**
-**/
-
-/**********************************************************************************
-** System MMR Register Map
-***********************************************************************************/
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534 								*/
-#include <cdefBF534.h>
-
-/* Include all Core registers and bit definitions 									*/
-#include <defBF537.h>
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537		*/
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) 						*/
-#define	pEMAC_OPMODE		((volatile unsigned long  *)EMAC_OPMODE)
-#define pEMAC_ADDRLO		((volatile unsigned long  *)EMAC_ADDRLO)
-#define pEMAC_ADDRHI		((volatile unsigned long  *)EMAC_ADDRHI)
-#define pEMAC_HASHLO		((volatile unsigned long  *)EMAC_HASHLO)
-#define pEMAC_HASHHI		((volatile unsigned long  *)EMAC_HASHHI)
-#define pEMAC_STAADD		((volatile unsigned long  *)EMAC_STAADD)
-#define pEMAC_STADAT		((volatile unsigned long  *)EMAC_STADAT)
-#define pEMAC_FLC			((volatile unsigned long  *)EMAC_FLC)
-#define pEMAC_VLAN1			((volatile unsigned long  *)EMAC_VLAN1)
-#define pEMAC_VLAN2			((volatile unsigned long  *)EMAC_VLAN2)
-#define pEMAC_WKUP_CTL		((volatile unsigned long  *)EMAC_WKUP_CTL)
-#define pEMAC_WKUP_FFMSK0	((volatile unsigned long  *)EMAC_WKUP_FFMSK0)
-#define pEMAC_WKUP_FFMSK1	((volatile unsigned long  *)EMAC_WKUP_FFMSK1)
-#define pEMAC_WKUP_FFMSK2	((volatile unsigned long  *)EMAC_WKUP_FFMSK2)
-#define pEMAC_WKUP_FFMSK3	((volatile unsigned long  *)EMAC_WKUP_FFMSK3)
-#define pEMAC_WKUP_FFCMD	((volatile unsigned long  *)EMAC_WKUP_FFCMD)
-#define pEMAC_WKUP_FFOFF	((volatile unsigned long  *)EMAC_WKUP_FFOFF)
-#define pEMAC_WKUP_FFCRC0	((volatile unsigned long  *)EMAC_WKUP_FFCRC0)
-#define pEMAC_WKUP_FFCRC1	((volatile unsigned long  *)EMAC_WKUP_FFCRC1)
-
-#define	pEMAC_SYSCTL		((volatile unsigned long  *)EMAC_SYSCTL)
-#define pEMAC_SYSTAT		((volatile unsigned long  *)EMAC_SYSTAT)
-#define pEMAC_RX_STAT		((volatile unsigned long  *)EMAC_RX_STAT)
-#define pEMAC_RX_STKY		((volatile unsigned long  *)EMAC_RX_STKY)
-#define pEMAC_RX_IRQE		((volatile unsigned long  *)EMAC_RX_IRQE)
-#define pEMAC_TX_STAT		((volatile unsigned long  *)EMAC_TX_STAT)
-#define pEMAC_TX_STKY		((volatile unsigned long  *)EMAC_TX_STKY)
-#define pEMAC_TX_IRQE		((volatile unsigned long  *)EMAC_TX_IRQE)
-
-#define pEMAC_MMC_CTL		((volatile unsigned long  *)EMAC_MMC_CTL)
-#define pEMAC_MMC_RIRQS		((volatile unsigned long  *)EMAC_MMC_RIRQS)
-#define pEMAC_MMC_RIRQE		((volatile unsigned long  *)EMAC_MMC_RIRQE)
-#define pEMAC_MMC_TIRQS		((volatile unsigned long  *)EMAC_MMC_TIRQS)
-#define pEMAC_MMC_TIRQE		((volatile unsigned long  *)EMAC_MMC_TIRQE)
-
-#define pEMAC_RXC_OK		((volatile unsigned long  *)EMAC_RXC_OK)
-#define pEMAC_RXC_FCS		((volatile unsigned long  *)EMAC_RXC_FCS)
-#define pEMAC_RXC_ALIGN		((volatile unsigned long  *)EMAC_RXC_ALIGN)
-#define pEMAC_RXC_OCTET		((volatile unsigned long  *)EMAC_RXC_OCTET)
-#define pEMAC_RXC_DMAOVF	((volatile unsigned long  *)EMAC_RXC_DMAOVF)
-#define pEMAC_RXC_UNICST	((volatile unsigned long  *)EMAC_RXC_UNICST)
-#define pEMAC_RXC_MULTI		((volatile unsigned long  *)EMAC_RXC_MULTI)
-#define pEMAC_RXC_BROAD		((volatile unsigned long  *)EMAC_RXC_BROAD)
-#define pEMAC_RXC_LNERRI	((volatile unsigned long  *)EMAC_RXC_LNERRI)
-#define pEMAC_RXC_LNERRO	((volatile unsigned long  *)EMAC_RXC_LNERRO)
-#define pEMAC_RXC_LONG		((volatile unsigned long  *)EMAC_RXC_LONG)
-#define pEMAC_RXC_MACCTL	((volatile unsigned long  *)EMAC_RXC_MACCTL)
-#define pEMAC_RXC_OPCODE	((volatile unsigned long  *)EMAC_RXC_OPCODE)
-#define pEMAC_RXC_PAUSE		((volatile unsigned long  *)EMAC_RXC_PAUSE)
-#define pEMAC_RXC_ALLFRM	((volatile unsigned long  *)EMAC_RXC_ALLFRM)
-#define pEMAC_RXC_ALLOCT	((volatile unsigned long  *)EMAC_RXC_ALLOCT)
-#define pEMAC_RXC_TYPED		((volatile unsigned long  *)EMAC_RXC_TYPED)
-#define pEMAC_RXC_SHORT		((volatile unsigned long  *)EMAC_RXC_SHORT)
-#define pEMAC_RXC_EQ64		((volatile unsigned long  *)EMAC_RXC_EQ64)
-#define	pEMAC_RXC_LT128		((volatile unsigned long  *)EMAC_RXC_LT128)
-#define pEMAC_RXC_LT256		((volatile unsigned long  *)EMAC_RXC_LT256)
-#define pEMAC_RXC_LT512		((volatile unsigned long  *)EMAC_RXC_LT512)
-#define pEMAC_RXC_LT1024	((volatile unsigned long  *)EMAC_RXC_LT1024)
-#define pEMAC_RXC_GE1024	((volatile unsigned long  *)EMAC_RXC_GE1024)
-
-#define pEMAC_TXC_OK		((volatile unsigned long  *)EMAC_TXC_OK)
-#define pEMAC_TXC_1COL		((volatile unsigned long  *)EMAC_TXC_1COL)
-#define pEMAC_TXC_GT1COL	((volatile unsigned long  *)EMAC_TXC_GT1COL)
-#define pEMAC_TXC_OCTET		((volatile unsigned long  *)EMAC_TXC_OCTET)
-#define pEMAC_TXC_DEFER		((volatile unsigned long  *)EMAC_TXC_DEFER)
-#define pEMAC_TXC_LATECL	((volatile unsigned long  *)EMAC_TXC_LATECL)
-#define pEMAC_TXC_XS_COL	((volatile unsigned long  *)EMAC_TXC_XS_COL)
-#define pEMAC_TXC_DMAUND	((volatile unsigned long  *)EMAC_TXC_DMAUND)
-#define pEMAC_TXC_CRSERR	((volatile unsigned long  *)EMAC_TXC_CRSERR)
-#define pEMAC_TXC_UNICST	((volatile unsigned long  *)EMAC_TXC_UNICST)
-#define pEMAC_TXC_MULTI		((volatile unsigned long  *)EMAC_TXC_MULTI)
-#define pEMAC_TXC_BROAD		((volatile unsigned long  *)EMAC_TXC_BROAD)
-#define pEMAC_TXC_XS_DFR	((volatile unsigned long  *)EMAC_TXC_XS_DFR)
-#define pEMAC_TXC_MACCTL	((volatile unsigned long  *)EMAC_TXC_MACCTL)
-#define pEMAC_TXC_ALLFRM	((volatile unsigned long  *)EMAC_TXC_ALLFRM)
-#define pEMAC_TXC_ALLOCT	((volatile unsigned long  *)EMAC_TXC_ALLOCT)
-#define pEMAC_TXC_EQ64		((volatile unsigned long  *)EMAC_TXC_EQ64)
-#define pEMAC_TXC_LT128		((volatile unsigned long  *)EMAC_TXC_LT128)
-#define pEMAC_TXC_LT256		((volatile unsigned long  *)EMAC_TXC_LT256)
-#define pEMAC_TXC_LT512		((volatile unsigned long  *)EMAC_TXC_LT512)
-#define pEMAC_TXC_LT1024	((volatile unsigned long  *)EMAC_TXC_LT1024)
-#define pEMAC_TXC_GE1024	((volatile unsigned long  *)EMAC_TXC_GE1024)
-#define pEMAC_TXC_ABORT		((volatile unsigned long  *)EMAC_TXC_ABORT)
-
-#endif /* _CDEF_BF537_H */
diff --git a/libgloss/bfin/include/cdefBF538.h b/libgloss/bfin/include/cdefBF538.h
deleted file mode 100644
index 3f6e71f03..000000000
--- a/libgloss/bfin/include/cdefBF538.h
+++ /dev/null
@@ -1,1014 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF538.h
- *
- * (c) Copyright 2006-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538 */
-
-#ifndef _CDEF_BF538_H
-#define _CDEF_BF538_H
-
-/* include all Core registers and bit definitions */
-#include <defBF538.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* include common system register pointer definitions from ADSP-BF532 */
-#include <cdefBF532.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#endif /* _MISRA_RULES */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)				*/
-/* ADSP-BF538 SIC0 is same as SIC on ADSP-BF532 */
-#define pSIC_IMASK0				pSIC_IMASK
-#define pSIC_ISR0 				pSIC_ISR
-#define pSIC_IWR0 				pSIC_IWR
-/* ADSP-BF538 SIC1 Registers */
-#define pSIC_IMASK1				((volatile unsigned long  *)SIC_IMASK1)
-#define pSIC_ISR1 				((volatile unsigned long  *)SIC_ISR1)
-#define pSIC_IWR1 				((volatile unsigned long  *)SIC_IWR1)
-#define pSIC_IAR3 				((volatile unsigned long  *)SIC_IAR3)
-#define pSIC_IAR4 				((volatile unsigned long  *)SIC_IAR4)
-#define pSIC_IAR5 				((volatile unsigned long  *)SIC_IAR5)
-#define pSIC_IAR6 				((volatile unsigned long  *)SIC_IAR6)
-
-
-/* UART0 Controller								*/
-/* ADSP-BF538 UART0 is same as UART on ADSP-BF532 */
-#define pUART0_THR 				pUART_THR
-#define pUART0_RBR 				pUART_RBR
-#define pUART0_DLL 				pUART_DLL
-#define pUART0_IER 				pUART_IER
-#define pUART0_DLH 				pUART_DLH
-#define pUART0_IIR 				pUART_IIR
-#define pUART0_LCR 				pUART_LCR
-#define pUART0_MCR 				pUART_MCR
-#define pUART0_LSR 				pUART_LSR
-#define pUART0_SCR 				pUART_SCR
-#define pUART0_GCTL 			pUART_GCTL
-
-
-/* SPI0 Controller						*/
-/* ADSP-BF538 SPI0 is same as SPI on ADSP-BF532 */
-#define pSPI0_CTL 				pSPI_CTL
-#define pSPI0_FLG 				pSPI_FLG
-#define pSPI0_STAT 				pSPI_STAT
-#define pSPI0_TDBR 				pSPI_TDBR
-#define pSPI0_RDBR 				pSPI_RDBR
-#define pSPI0_BAUD 				pSPI_BAUD
-#define pSPI0_SHADOW 			pSPI_SHADOW
-
-
-/* General-Purpose Input/Output Ports (GPIO)					*/
-/* ADSP-BF538 Refers to FIO as GPIO Port F */
-#define pPORTFIO 				pFIO_FLAG_D
-#define pPORTFIO_CLEAR 			pFIO_FLAG_C
-#define pPORTFIO_SET 			pFIO_FLAG_S
-#define pPORTFIO_TOGGLE 		pFIO_FLAG_T
-#define pPORTFIO_MASKA 			pFIO_MASKA_D
-#define pPORTFIO_MASKA_CLEAR 	pFIO_MASKA_C
-#define pPORTFIO_MASKA_SET 		pFIO_MASKA_S
-#define pPORTFIO_MASKA_TOGGLE 	pFIO_MASKA_T
-#define pPORTFIO_MASKB 			pFIO_MASKB_D
-#define pPORTFIO_MASKB_CLEAR 	pFIO_MASKB_C
-#define pPORTFIO_MASKB_SET 		pFIO_MASKB_S
-#define pPORTFIO_MASKB_TOGGLE 	pFIO_MASKB_T
-#define pPORTFIO_DIR 			pFIO_DIR
-#define pPORTFIO_POLAR	 		pFIO_POLAR
-#define pPORTFIO_EDGE 			pFIO_EDGE
-#define pPORTFIO_BOTH 			pFIO_BOTH
-#define pPORTFIO_INEN 			pFIO_INEN
-
-
-/* DMA0 Traffic Control Registers											*/
-/* ADSP-BF538 DMA0 Controller is same as DMA Controller on ADSP-BF532 */
-#define	pDMAC0_TC_PER				pDMA_TC_PER
-#define	pDMAC0_TC_CNT				pDMA_TC_CNT
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define	pDMA0_TC_PER				pDMAC0_TC_PER
-#define	pDMA0_TC_CNT				pDMAC0_TC_CNT
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA0_TCPER					pDMA0_TC_PER	/* Traffic Control Periods Register			*/
-#define pDMA0_TCCNT					pDMA0_TC_CNT	/* Traffic Control Current Counts Register	*/
-
-/* Must Enumerate MemDMA Controllers As Well */
-#define pMDMA0_D0_NEXT_DESC_PTR 	pMDMA_D0_NEXT_DESC_PTR
-#define pMDMA0_D0_START_ADDR 		pMDMA_D0_START_ADDR
-#define pMDMA0_D0_CONFIG 			pMDMA_D0_CONFIG
-#define pMDMA0_D0_X_COUNT 			pMDMA_D0_X_COUNT
-#define pMDMA0_D0_X_MODIFY 			pMDMA_D0_X_MODIFY
-#define pMDMA0_D0_Y_COUNT 			pMDMA_D0_Y_COUNT
-#define pMDMA0_D0_Y_MODIFY 			pMDMA_D0_Y_MODIFY
-#define pMDMA0_D0_CURR_DESC_PTR 	pMDMA_D0_CURR_DESC_PTR
-#define pMDMA0_D0_CURR_ADDR 		pMDMA_D0_CURR_ADDR
-#define pMDMA0_D0_IRQ_STATUS 		pMDMA_D0_IRQ_STATUS
-#define pMDMA0_D0_PERIPHERAL_MAP 	pMDMA_D0_PERIPHERAL_MAP
-#define pMDMA0_D0_CURR_X_COUNT 		pMDMA_D0_CURR_X_COUNT
-#define pMDMA0_D0_CURR_Y_COUNT 		pMDMA_D0_CURR_Y_COUNT
-
-#define pMDMA0_S0_NEXT_DESC_PTR 	pMDMA_S0_NEXT_DESC_PTR
-#define pMDMA0_S0_START_ADDR 		pMDMA_S0_START_ADDR
-#define pMDMA0_S0_CONFIG 			pMDMA_S0_CONFIG
-#define pMDMA0_S0_X_COUNT 			pMDMA_S0_X_COUNT
-#define pMDMA0_S0_X_MODIFY 			pMDMA_S0_X_MODIFY
-#define pMDMA0_S0_Y_COUNT 			pMDMA_S0_Y_COUNT
-#define pMDMA0_S0_Y_MODIFY 			pMDMA_S0_Y_MODIFY
-#define pMDMA0_S0_CURR_DESC_PTR 	pMDMA_S0_CURR_DESC_PTR
-#define pMDMA0_S0_CURR_ADDR 		pMDMA_S0_CURR_ADDR
-#define pMDMA0_S0_IRQ_STATUS 		pMDMA_S0_IRQ_STATUS
-#define pMDMA0_S0_PERIPHERAL_MAP	pMDMA_S0_PERIPHERAL_MAP
-#define pMDMA0_S0_CURR_X_COUNT 		pMDMA_S0_CURR_X_COUNT
-#define pMDMA0_S0_CURR_Y_COUNT 		pMDMA_S0_CURR_Y_COUNT
-
-#define pMDMA0_D1_NEXT_DESC_PTR 	pMDMA_D1_NEXT_DESC_PTR
-#define pMDMA0_D1_START_ADDR 		pMDMA_D1_START_ADDR
-#define pMDMA0_D1_CONFIG 			pMDMA_D1_CONFIG
-#define pMDMA0_D1_X_COUNT 			pMDMA_D1_X_COUNT
-#define pMDMA0_D1_X_MODIFY 			pMDMA_D1_X_MODIFY
-#define pMDMA0_D1_Y_COUNT 			pMDMA_D1_Y_COUNT
-#define pMDMA0_D1_Y_MODIFY 			pMDMA_D1_Y_MODIFY
-#define pMDMA0_D1_CURR_DESC_PTR 	pMDMA_D1_CURR_DESC_PTR
-#define pMDMA0_D1_CURR_ADDR 		pMDMA_D1_CURR_ADDR
-#define pMDMA0_D1_IRQ_STATUS 		pMDMA_D1_IRQ_STATUS
-#define pMDMA0_D1_PERIPHERAL_MAP 	pMDMA_D1_PERIPHERAL_MAP
-#define pMDMA0_D1_CURR_X_COUNT 		pMDMA_D1_CURR_X_COUNT
-#define pMDMA0_D1_CURR_Y_COUNT 		pMDMA_D1_CURR_Y_COUNT
-
-#define pMDMA0_S1_NEXT_DESC_PTR 	pMDMA_S1_NEXT_DESC_PTR
-#define pMDMA0_S1_START_ADDR 		pMDMA_S1_START_ADDR
-#define pMDMA0_S1_CONFIG 			pMDMA_S1_CONFIG
-#define pMDMA0_S1_X_COUNT 			pMDMA_S1_X_COUNT
-#define pMDMA0_S1_X_MODIFY 			pMDMA_S1_X_MODIFY
-#define pMDMA0_S1_Y_COUNT 			pMDMA_S1_Y_COUNT
-#define pMDMA0_S1_Y_MODIFY 			pMDMA_S1_Y_MODIFY
-#define pMDMA0_S1_CURR_DESC_PTR 	pMDMA_S1_CURR_DESC_PTR
-#define pMDMA0_S1_CURR_ADDR 		pMDMA_S1_CURR_ADDR
-#define pMDMA0_S1_IRQ_STATUS 		pMDMA_S1_IRQ_STATUS
-#define pMDMA0_S1_PERIPHERAL_MAP 	pMDMA_S1_PERIPHERAL_MAP
-#define pMDMA0_S1_CURR_X_COUNT 		pMDMA_S1_CURR_X_COUNT
-#define pMDMA0_S1_CURR_Y_COUNT 		pMDMA_S1_CURR_Y_COUNT
-
-
-/* Two-Wire Interface 0						*/
-#define pTWI0_CLKDIV		((volatile unsigned short *)TWI0_CLKDIV)
-#define pTWI0_CONTROL		((volatile unsigned short *)TWI0_CONTROL)
-#define pTWI0_SLAVE_CTRL	((volatile unsigned short *)TWI0_SLAVE_CTRL)
-#define pTWI0_SLAVE_STAT	((volatile unsigned short *)TWI0_SLAVE_STAT)
-#define pTWI0_SLAVE_ADDR	((volatile unsigned short *)TWI0_SLAVE_ADDR)
-#define pTWI0_MASTER_CTRL	((volatile unsigned short *)TWI0_MASTER_CTRL)
-#define pTWI0_MASTER_STAT	((volatile unsigned short *)TWI0_MASTER_STAT)
-#define pTWI0_MASTER_ADDR	((volatile unsigned short *)TWI0_MASTER_ADDR)
-#define pTWI0_INT_STAT		((volatile unsigned short *)TWI0_INT_STAT)
-#define pTWI0_INT_MASK		((volatile unsigned short *)TWI0_INT_MASK)
-#define pTWI0_FIFO_CTRL		((volatile unsigned short *)TWI0_FIFO_CTRL)
-#define pTWI0_FIFO_STAT		((volatile unsigned short *)TWI0_FIFO_STAT)
-#define pTWI0_XMT_DATA8		((volatile unsigned short *)TWI0_XMT_DATA8)
-#define pTWI0_XMT_DATA16	((volatile unsigned short *)TWI0_XMT_DATA16)
-#define pTWI0_RCV_DATA8		((volatile unsigned short *)TWI0_RCV_DATA8)
-#define pTWI0_RCV_DATA16	((volatile unsigned short *)TWI0_RCV_DATA16)
-
-
-/* General Purpose IO Ports C, D, and E						*/
-#define pPORTCIO_FER		((volatile unsigned short *)PORTCIO_FER)
-#define pPORTCIO			((volatile unsigned short *)PORTCIO)
-#define pPORTCIO_CLEAR		((volatile unsigned short *)PORTCIO_CLEAR)
-#define pPORTCIO_SET		((volatile unsigned short *)PORTCIO_SET)
-#define pPORTCIO_TOGGLE		((volatile unsigned short *)PORTCIO_TOGGLE)
-#define pPORTCIO_DIR		((volatile unsigned short *)PORTCIO_DIR)
-#define pPORTCIO_INEN		((volatile unsigned short *)PORTCIO_INEN)
-
-#define pPORTDIO_FER		((volatile unsigned short *)PORTDIO_FER)
-#define pPORTDIO			((volatile unsigned short *)PORTDIO)
-#define pPORTDIO_CLEAR		((volatile unsigned short *)PORTDIO_CLEAR)
-#define pPORTDIO_SET		((volatile unsigned short *)PORTDIO_SET)
-#define pPORTDIO_TOGGLE		((volatile unsigned short *)PORTDIO_TOGGLE)
-#define pPORTDIO_DIR		((volatile unsigned short *)PORTDIO_DIR)
-#define pPORTDIO_INEN		((volatile unsigned short *)PORTDIO_INEN)
-
-#define pPORTEIO_FER		((volatile unsigned short *)PORTEIO_FER)
-#define pPORTEIO			((volatile unsigned short *)PORTEIO)
-#define pPORTEIO_CLEAR		((volatile unsigned short *)PORTEIO_CLEAR)
-#define pPORTEIO_SET		((volatile unsigned short *)PORTEIO_SET)
-#define pPORTEIO_TOGGLE		((volatile unsigned short *)PORTEIO_TOGGLE)
-#define pPORTEIO_DIR		((volatile unsigned short *)PORTEIO_DIR)
-#define pPORTEIO_INEN		((volatile unsigned short *)PORTEIO_INEN)
-
-
-/* DMA1 Traffic Control Registers											*/
-#define	pDMAC1_TC_PER				((volatile unsigned short *)DMAC1_TC_PER)
-#define	pDMAC1_TC_CNT				((volatile unsigned short *)DMAC1_TC_CNT)
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA1_TC_PER					pDMAC1_TC_PER	/* Traffic Control Periods Register			*/
-#define pDMA1_TC_CNT					pDMAC1_TC_CNT	/* Traffic Control Current Counts Register	*/
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA1_TCPER					pDMA1_TC_PER	/* Traffic Control Periods Register			*/
-#define pDMA1_TCCNT					pDMA1_TC_CNT	/* Traffic Control Current Counts Register	*/
-
-/* DMA Controller 1 						*/
-#define pDMA8_NEXT_DESC_PTR 		((void * volatile *)DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 			((void * volatile *)DMA8_START_ADDR)
-#define pDMA8_CONFIG 				((volatile unsigned short *)DMA8_CONFIG)
-#define pDMA8_X_COUNT 				((volatile unsigned short *)DMA8_X_COUNT)
-#define pDMA8_X_MODIFY 				((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_COUNT 				((volatile unsigned short *)DMA8_Y_COUNT)
-#define pDMA8_Y_MODIFY 				((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 		((void * volatile *)DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 			((void * volatile *)DMA8_CURR_ADDR)
-#define pDMA8_IRQ_STATUS 			((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 		((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-#define pDMA8_CURR_X_COUNT 			((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 			((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-
-#define pDMA9_NEXT_DESC_PTR 		((void * volatile *)DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR 			((void * volatile *)DMA9_START_ADDR)
-#define pDMA9_CONFIG 				((volatile unsigned short *)DMA9_CONFIG)
-#define pDMA9_X_COUNT 				((volatile unsigned short *)DMA9_X_COUNT)
-#define pDMA9_X_MODIFY 				((volatile signed   short *)DMA9_X_MODIFY)
-#define pDMA9_Y_COUNT 				((volatile unsigned short *)DMA9_Y_COUNT)
-#define pDMA9_Y_MODIFY 				((volatile signed   short *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR 		((void * volatile *)DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR 			((void * volatile *)DMA9_CURR_ADDR)
-#define pDMA9_IRQ_STATUS 			((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP 		((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-#define pDMA9_CURR_X_COUNT 			((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT 			((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-
-#define pDMA10_NEXT_DESC_PTR 		((void * volatile *)DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR 			((void * volatile *)DMA10_START_ADDR)
-#define pDMA10_CONFIG 				((volatile unsigned short *)DMA10_CONFIG)
-#define pDMA10_X_COUNT 				((volatile unsigned short *)DMA10_X_COUNT)
-#define pDMA10_X_MODIFY 			((volatile signed   short *)DMA10_X_MODIFY)
-#define pDMA10_Y_COUNT 				((volatile unsigned short *)DMA10_Y_COUNT)
-#define pDMA10_Y_MODIFY 			((volatile signed   short *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR 		((void * volatile *)DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR 			((void * volatile *)DMA10_CURR_ADDR)
-#define pDMA10_IRQ_STATUS 			((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP 		((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-#define pDMA10_CURR_X_COUNT 		((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT 		((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-
-#define pDMA11_NEXT_DESC_PTR 		((void * volatile *)DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR 			((void * volatile *)DMA11_START_ADDR)
-#define pDMA11_CONFIG 				((volatile unsigned short *)DMA11_CONFIG)
-#define pDMA11_X_COUNT 				((volatile unsigned short *)DMA11_X_COUNT)
-#define pDMA11_X_MODIFY 			((volatile signed   short *)DMA11_X_MODIFY)
-#define pDMA11_Y_COUNT 				((volatile unsigned short *)DMA11_Y_COUNT)
-#define pDMA11_Y_MODIFY 			((volatile signed   short *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR 		((void * volatile *)DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR 			((void * volatile *)DMA11_CURR_ADDR)
-#define pDMA11_IRQ_STATUS 			((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP 		((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-#define pDMA11_CURR_X_COUNT 		((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT 		((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-
-#define pDMA12_NEXT_DESC_PTR 		((void * volatile *)DMA12_NEXT_DESC_PTR)
-#define pDMA12_START_ADDR 			((void * volatile *)DMA12_START_ADDR)
-#define pDMA12_CONFIG 				((volatile unsigned short *)DMA12_CONFIG)
-#define pDMA12_X_COUNT 				((volatile unsigned short *)DMA12_X_COUNT)
-#define pDMA12_X_MODIFY 			((volatile signed   short *)DMA12_X_MODIFY)
-#define pDMA12_Y_COUNT 				((volatile unsigned short *)DMA12_Y_COUNT)
-#define pDMA12_Y_MODIFY 			((volatile signed   short *)DMA12_Y_MODIFY)
-#define pDMA12_CURR_DESC_PTR 		((void * volatile *)DMA12_CURR_DESC_PTR)
-#define pDMA12_CURR_ADDR 			((void * volatile *)DMA12_CURR_ADDR)
-#define pDMA12_IRQ_STATUS 			((volatile unsigned short *)DMA12_IRQ_STATUS)
-#define pDMA12_PERIPHERAL_MAP 		((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
-#define pDMA12_CURR_X_COUNT 		((volatile unsigned short *)DMA12_CURR_X_COUNT)
-#define pDMA12_CURR_Y_COUNT 		((volatile unsigned short *)DMA12_CURR_Y_COUNT)
-
-#define pDMA13_NEXT_DESC_PTR 		((void * volatile *)DMA13_NEXT_DESC_PTR)
-#define pDMA13_START_ADDR 			((void * volatile *)DMA13_START_ADDR)
-#define pDMA13_CONFIG 				((volatile unsigned short *)DMA13_CONFIG)
-#define pDMA13_X_COUNT 				((volatile unsigned short *)DMA13_X_COUNT)
-#define pDMA13_X_MODIFY 			((volatile signed   short *)DMA13_X_MODIFY)
-#define pDMA13_Y_COUNT 				((volatile unsigned short *)DMA13_Y_COUNT)
-#define pDMA13_Y_MODIFY 			((volatile signed   short *)DMA13_Y_MODIFY)
-#define pDMA13_CURR_DESC_PTR 		((void * volatile *)DMA13_CURR_DESC_PTR)
-#define pDMA13_CURR_ADDR 			((void * volatile *)DMA13_CURR_ADDR)
-#define pDMA13_IRQ_STATUS 			((volatile unsigned short *)DMA13_IRQ_STATUS)
-#define pDMA13_PERIPHERAL_MAP 		((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
-#define pDMA13_CURR_X_COUNT 		((volatile unsigned short *)DMA13_CURR_X_COUNT)
-#define pDMA13_CURR_Y_COUNT 		((volatile unsigned short *)DMA13_CURR_Y_COUNT)
-
-#define pDMA14_NEXT_DESC_PTR 		((void * volatile *)DMA14_NEXT_DESC_PTR)
-#define pDMA14_START_ADDR 			((void * volatile *)DMA14_START_ADDR)
-#define pDMA14_CONFIG 				((volatile unsigned short *)DMA14_CONFIG)
-#define pDMA14_X_COUNT 				((volatile unsigned short *)DMA14_X_COUNT)
-#define pDMA14_X_MODIFY 			((volatile signed   short *)DMA14_X_MODIFY)
-#define pDMA14_Y_COUNT 				((volatile unsigned short *)DMA14_Y_COUNT)
-#define pDMA14_Y_MODIFY 			((volatile signed   short *)DMA14_Y_MODIFY)
-#define pDMA14_CURR_DESC_PTR 		((void * volatile *)DMA14_CURR_DESC_PTR)
-#define pDMA14_CURR_ADDR 			((void * volatile *)DMA14_CURR_ADDR)
-#define pDMA14_IRQ_STATUS 			((volatile unsigned short *)DMA14_IRQ_STATUS)
-#define pDMA14_PERIPHERAL_MAP 		((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
-#define pDMA14_CURR_X_COUNT 		((volatile unsigned short *)DMA14_CURR_X_COUNT)
-#define pDMA14_CURR_Y_COUNT 		((volatile unsigned short *)DMA14_CURR_Y_COUNT)
-
-#define pDMA15_NEXT_DESC_PTR 		((void * volatile *)DMA15_NEXT_DESC_PTR)
-#define pDMA15_START_ADDR 			((void * volatile *)DMA15_START_ADDR)
-#define pDMA15_CONFIG 				((volatile unsigned short *)DMA15_CONFIG)
-#define pDMA15_X_COUNT 				((volatile unsigned short *)DMA15_X_COUNT)
-#define pDMA15_X_MODIFY 			((volatile signed   short *)DMA15_X_MODIFY)
-#define pDMA15_Y_COUNT 				((volatile unsigned short *)DMA15_Y_COUNT)
-#define pDMA15_Y_MODIFY 			((volatile signed   short *)DMA15_Y_MODIFY)
-#define pDMA15_CURR_DESC_PTR 		((void * volatile *)DMA15_CURR_DESC_PTR)
-#define pDMA15_CURR_ADDR 			((void * volatile *)DMA15_CURR_ADDR)
-#define pDMA15_IRQ_STATUS 			((volatile unsigned short *)DMA15_IRQ_STATUS)
-#define pDMA15_PERIPHERAL_MAP 		((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
-#define pDMA15_CURR_X_COUNT 		((volatile unsigned short *)DMA15_CURR_X_COUNT)
-#define pDMA15_CURR_Y_COUNT 		((volatile unsigned short *)DMA15_CURR_Y_COUNT)
-
-#define pDMA16_NEXT_DESC_PTR 		((void * volatile *)DMA16_NEXT_DESC_PTR)
-#define pDMA16_START_ADDR 			((void * volatile *)DMA16_START_ADDR)
-#define pDMA16_CONFIG 				((volatile unsigned short *)DMA16_CONFIG)
-#define pDMA16_X_COUNT 				((volatile unsigned short *)DMA16_X_COUNT)
-#define pDMA16_X_MODIFY 			((volatile signed   short *)DMA16_X_MODIFY)
-#define pDMA16_Y_COUNT 				((volatile unsigned short *)DMA16_Y_COUNT)
-#define pDMA16_Y_MODIFY 			((volatile signed   short *)DMA16_Y_MODIFY)
-#define pDMA16_CURR_DESC_PTR 		((void * volatile *)DMA16_CURR_DESC_PTR)
-#define pDMA16_CURR_ADDR 			((void * volatile *)DMA16_CURR_ADDR)
-#define pDMA16_IRQ_STATUS 			((volatile unsigned short *)DMA16_IRQ_STATUS)
-#define pDMA16_PERIPHERAL_MAP 		((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
-#define pDMA16_CURR_X_COUNT 		((volatile unsigned short *)DMA16_CURR_X_COUNT)
-#define pDMA16_CURR_Y_COUNT 		((volatile unsigned short *)DMA16_CURR_Y_COUNT)
-
-#define pDMA17_NEXT_DESC_PTR 		((void * volatile *)DMA17_NEXT_DESC_PTR)
-#define pDMA17_START_ADDR 			((void * volatile *)DMA17_START_ADDR)
-#define pDMA17_CONFIG 				((volatile unsigned short *)DMA17_CONFIG)
-#define pDMA17_X_COUNT 				((volatile unsigned short *)DMA17_X_COUNT)
-#define pDMA17_X_MODIFY 			((volatile signed   short *)DMA17_X_MODIFY)
-#define pDMA17_Y_COUNT 				((volatile unsigned short *)DMA17_Y_COUNT)
-#define pDMA17_Y_MODIFY 			((volatile signed   short *)DMA17_Y_MODIFY)
-#define pDMA17_CURR_DESC_PTR 		((void * volatile *)DMA17_CURR_DESC_PTR)
-#define pDMA17_CURR_ADDR 			((void * volatile *)DMA17_CURR_ADDR)
-#define pDMA17_IRQ_STATUS 			((volatile unsigned short *)DMA17_IRQ_STATUS)
-#define pDMA17_PERIPHERAL_MAP 		((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
-#define pDMA17_CURR_X_COUNT 		((volatile unsigned short *)DMA17_CURR_X_COUNT)
-#define pDMA17_CURR_Y_COUNT 		((volatile unsigned short *)DMA17_CURR_Y_COUNT)
-
-#define pDMA18_NEXT_DESC_PTR 		((void * volatile *)DMA18_NEXT_DESC_PTR)
-#define pDMA18_START_ADDR 			((void * volatile *)DMA18_START_ADDR)
-#define pDMA18_CONFIG 				((volatile unsigned short *)DMA18_CONFIG)
-#define pDMA18_X_COUNT 				((volatile unsigned short *)DMA18_X_COUNT)
-#define pDMA18_X_MODIFY 			((volatile signed   short *)DMA18_X_MODIFY)
-#define pDMA18_Y_COUNT 				((volatile unsigned short *)DMA18_Y_COUNT)
-#define pDMA18_Y_MODIFY 			((volatile signed   short *)DMA18_Y_MODIFY)
-#define pDMA18_CURR_DESC_PTR 		((void * volatile *)DMA18_CURR_DESC_PTR)
-#define pDMA18_CURR_ADDR 			((void * volatile *)DMA18_CURR_ADDR)
-#define pDMA18_IRQ_STATUS 			((volatile unsigned short *)DMA18_IRQ_STATUS)
-#define pDMA18_PERIPHERAL_MAP 		((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
-#define pDMA18_CURR_X_COUNT 		((volatile unsigned short *)DMA18_CURR_X_COUNT)
-#define pDMA18_CURR_Y_COUNT 		((volatile unsigned short *)DMA18_CURR_Y_COUNT)
-
-#define pDMA19_NEXT_DESC_PTR 		((void * volatile *)DMA19_NEXT_DESC_PTR)
-#define pDMA19_START_ADDR 			((void * volatile *)DMA19_START_ADDR)
-#define pDMA19_CONFIG 				((volatile unsigned short *)DMA19_CONFIG)
-#define pDMA19_X_COUNT 				((volatile unsigned short *)DMA19_X_COUNT)
-#define pDMA19_X_MODIFY 			((volatile signed   short *)DMA19_X_MODIFY)
-#define pDMA19_Y_COUNT 				((volatile unsigned short *)DMA19_Y_COUNT)
-#define pDMA19_Y_MODIFY 			((volatile signed   short *)DMA19_Y_MODIFY)
-#define pDMA19_CURR_DESC_PTR 		((void * volatile *)DMA19_CURR_DESC_PTR)
-#define pDMA19_CURR_ADDR 			((void * volatile *)DMA19_CURR_ADDR)
-#define pDMA19_IRQ_STATUS 			((volatile unsigned short *)DMA19_IRQ_STATUS)
-#define pDMA19_PERIPHERAL_MAP 		((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
-#define pDMA19_CURR_X_COUNT 		((volatile unsigned short *)DMA19_CURR_X_COUNT)
-#define pDMA19_CURR_Y_COUNT 		((volatile unsigned short *)DMA19_CURR_Y_COUNT)
-
-#define pMDMA1_D0_NEXT_DESC_PTR 	((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
-#define pMDMA1_D0_START_ADDR 		((void * volatile *)MDMA1_D0_START_ADDR)
-#define pMDMA1_D0_CONFIG 			((volatile unsigned short *)MDMA1_D0_CONFIG)
-#define pMDMA1_D0_X_COUNT 			((volatile unsigned short *)MDMA1_D0_X_COUNT)
-#define pMDMA1_D0_X_MODIFY 			((volatile signed   short *)MDMA1_D0_X_MODIFY)
-#define pMDMA1_D0_Y_COUNT 			((volatile unsigned short *)MDMA1_D0_Y_COUNT)
-#define pMDMA1_D0_Y_MODIFY 			((volatile signed   short *)MDMA1_D0_Y_MODIFY)
-#define pMDMA1_D0_CURR_DESC_PTR 	((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
-#define pMDMA1_D0_CURR_ADDR 		((void * volatile *)MDMA1_D0_CURR_ADDR)
-#define pMDMA1_D0_IRQ_STATUS 		((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
-#define pMDMA1_D0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
-#define pMDMA1_D0_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT)
-#define pMDMA1_D0_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
-
-#define pMDMA1_S0_NEXT_DESC_PTR 	((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
-#define pMDMA1_S0_START_ADDR 		((void * volatile *)MDMA1_S0_START_ADDR)
-#define pMDMA1_S0_CONFIG 			((volatile unsigned short *)MDMA1_S0_CONFIG)
-#define pMDMA1_S0_X_COUNT 			((volatile unsigned short *)MDMA1_S0_X_COUNT)
-#define pMDMA1_S0_X_MODIFY 			((volatile signed   short *)MDMA1_S0_X_MODIFY)
-#define pMDMA1_S0_Y_COUNT 			((volatile unsigned short *)MDMA1_S0_Y_COUNT)
-#define pMDMA1_S0_Y_MODIFY 			((volatile signed   short *)MDMA1_S0_Y_MODIFY)
-#define pMDMA1_S0_CURR_DESC_PTR 	((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
-#define pMDMA1_S0_CURR_ADDR 		((void * volatile *)MDMA1_S0_CURR_ADDR)
-#define pMDMA1_S0_IRQ_STATUS 		((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
-#define pMDMA1_S0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
-#define pMDMA1_S0_CURR_X_COUNT		((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
-#define pMDMA1_S0_CURR_Y_COUNT		((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
-
-#define pMDMA1_D1_NEXT_DESC_PTR 	((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
-#define pMDMA1_D1_START_ADDR 		((void * volatile *)MDMA1_D1_START_ADDR)
-#define pMDMA1_D1_CONFIG 			((volatile unsigned short *)MDMA1_D1_CONFIG)
-#define pMDMA1_D1_X_COUNT 			((volatile unsigned short *)MDMA1_D1_X_COUNT)
-#define pMDMA1_D1_X_MODIFY 			((volatile signed   short *)MDMA1_D1_X_MODIFY)
-#define pMDMA1_D1_Y_COUNT 			((volatile unsigned short *)MDMA1_D1_Y_COUNT)
-#define pMDMA1_D1_Y_MODIFY 			((volatile signed   short *)MDMA1_D1_Y_MODIFY)
-#define pMDMA1_D1_CURR_DESC_PTR 	((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
-#define pMDMA1_D1_CURR_ADDR 		((void * volatile *)MDMA1_D1_CURR_ADDR)
-#define pMDMA1_D1_IRQ_STATUS 		((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
-#define pMDMA1_D1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
-#define pMDMA1_D1_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
-#define pMDMA1_D1_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
-
-#define pMDMA1_S1_NEXT_DESC_PTR 	((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
-#define pMDMA1_S1_START_ADDR 		((void * volatile *)MDMA1_S1_START_ADDR)
-#define pMDMA1_S1_CONFIG 			((volatile unsigned short *)MDMA1_S1_CONFIG)
-#define pMDMA1_S1_X_COUNT 			((volatile unsigned short *)MDMA1_S1_X_COUNT)
-#define pMDMA1_S1_X_MODIFY 			((volatile signed   short *)MDMA1_S1_X_MODIFY)
-#define pMDMA1_S1_Y_COUNT 			((volatile unsigned short *)MDMA1_S1_Y_COUNT)
-#define pMDMA1_S1_Y_MODIFY 			((volatile signed   short *)MDMA1_S1_Y_MODIFY)
-#define pMDMA1_S1_CURR_DESC_PTR 	((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
-#define pMDMA1_S1_CURR_ADDR 		((void * volatile *)MDMA1_S1_CURR_ADDR)
-#define pMDMA1_S1_IRQ_STATUS 		((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
-#define pMDMA1_S1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
-#define pMDMA1_S1_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
-#define pMDMA1_S1_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
-
-
-/* UART1 Controller							*/
-#define pUART1_THR 			((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR 			((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL 			((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER 			((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH 			((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR 			((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR 			((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR 			((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR 			((volatile unsigned short *)UART1_LSR)
-#define pUART1_SCR 			((volatile unsigned short *)UART1_SCR)
-#define pUART1_GCTL 		((volatile unsigned short *)UART1_GCTL)
-
-
-/* UART2 Controller						*/
-#define pUART2_THR 			((volatile unsigned short *)UART2_THR)
-#define pUART2_RBR 			((volatile unsigned short *)UART2_RBR)
-#define pUART2_DLL 			((volatile unsigned short *)UART2_DLL)
-#define pUART2_IER 			((volatile unsigned short *)UART2_IER)
-#define pUART2_DLH 			((volatile unsigned short *)UART2_DLH)
-#define pUART2_IIR 			((volatile unsigned short *)UART2_IIR)
-#define pUART2_LCR 			((volatile unsigned short *)UART2_LCR)
-#define pUART2_MCR 			((volatile unsigned short *)UART2_MCR)
-#define pUART2_LSR 			((volatile unsigned short *)UART2_LSR)
-#define pUART2_SCR 			((volatile unsigned short *)UART2_SCR)
-#define pUART2_GCTL 		((volatile unsigned short *)UART2_GCTL)
-
-
-/* Two-Wire Interface 1						*/
-#define pTWI1_CLKDIV		((volatile unsigned short *)TWI1_CLKDIV)
-#define pTWI1_CONTROL		((volatile unsigned short *)TWI1_CONTROL)
-#define pTWI1_SLAVE_CTRL	((volatile unsigned short *)TWI1_SLAVE_CTRL)
-#define pTWI1_SLAVE_STAT	((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define pTWI1_SLAVE_ADDR	((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define pTWI1_MASTER_CTRL	((volatile unsigned short *)TWI1_MASTER_CTRL)
-#define pTWI1_MASTER_STAT	((volatile unsigned short *)TWI1_MASTER_STAT)
-#define pTWI1_MASTER_ADDR	((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define pTWI1_INT_STAT		((volatile unsigned short *)TWI1_INT_STAT)
-#define pTWI1_INT_MASK		((volatile unsigned short *)TWI1_INT_MASK)
-#define pTWI1_FIFO_CTRL		((volatile unsigned short *)TWI1_FIFO_CTRL)
-#define pTWI1_FIFO_STAT		((volatile unsigned short *)TWI1_FIFO_STAT)
-#define pTWI1_XMT_DATA8		((volatile unsigned short *)TWI1_XMT_DATA8)
-#define pTWI1_XMT_DATA16	((volatile unsigned short *)TWI1_XMT_DATA16)
-#define pTWI1_RCV_DATA8		((volatile unsigned short *)TWI1_RCV_DATA8)
-#define pTWI1_RCV_DATA16	((volatile unsigned short *)TWI1_RCV_DATA16)
-
-
-/* SPI1 Controller					*/
-#define pSPI1_CTL 			((volatile unsigned short *)SPI1_CTL)
-#define pSPI1_FLG 			((volatile unsigned short *)SPI1_FLG)
-#define pSPI1_STAT 			((volatile unsigned short *)SPI1_STAT)
-#define pSPI1_TDBR 			((volatile unsigned short *)SPI1_TDBR)
-#define pSPI1_RDBR 			((volatile unsigned short *)SPI1_RDBR)
-#define pSPI1_BAUD 			((volatile unsigned short *)SPI1_BAUD)
-#define pSPI1_SHADOW 		((volatile unsigned short *)SPI1_SHADOW)
-
-
-/* SPI2 Controller								*/
-#define pSPI2_CTL 			((volatile unsigned short *)SPI2_CTL)
-#define pSPI2_FLG 			((volatile unsigned short *)SPI2_FLG)
-#define pSPI2_STAT 			((volatile unsigned short *)SPI2_STAT)
-#define pSPI2_TDBR 			((volatile unsigned short *)SPI2_TDBR)
-#define pSPI2_RDBR 			((volatile unsigned short *)SPI2_RDBR)
-#define pSPI2_BAUD 			((volatile unsigned short *)SPI2_BAUD)
-#define pSPI2_SHADOW 		((volatile unsigned short *)SPI2_SHADOW)
-
-
-/* SPORT2 Controller					*/
-#define pSPORT2_TCR1 		((volatile unsigned short *)SPORT2_TCR1)
-#define pSPORT2_TCR2 		((volatile unsigned short *)SPORT2_TCR2)
-#define pSPORT2_TCLKDIV 	((volatile unsigned short *)SPORT2_TCLKDIV)
-#define pSPORT2_TFSDIV 		((volatile unsigned short *)SPORT2_TFSDIV)
-#define pSPORT2_TX 			((volatile unsigned long  *)SPORT2_TX)
-#define pSPORT2_RX 			((volatile unsigned long  *)SPORT2_RX)
-#define pSPORT2_TX32 		((volatile unsigned long  *)SPORT2_TX)
-#define pSPORT2_RX32 		((volatile unsigned long  *)SPORT2_RX)
-#define pSPORT2_TX16 		((volatile unsigned short *)SPORT2_TX)
-#define pSPORT2_RX16 		((volatile unsigned short *)SPORT2_RX)
-#define pSPORT2_RCR1 		((volatile unsigned short *)SPORT2_RCR1)
-#define pSPORT2_RCR2 		((volatile unsigned short *)SPORT2_RCR2)
-#define pSPORT2_RCLKDIV 	((volatile unsigned short *)SPORT2_RCLKDIV)
-#define pSPORT2_RFSDIV 		((volatile unsigned short *)SPORT2_RFSDIV)
-#define pSPORT2_STAT 		((volatile unsigned short *)SPORT2_STAT)
-#define pSPORT2_CHNL 		((volatile unsigned short *)SPORT2_CHNL)
-#define pSPORT2_MCMC1 		((volatile unsigned short *)SPORT2_MCMC1)
-#define pSPORT2_MCMC2 		((volatile unsigned short *)SPORT2_MCMC2)
-#define pSPORT2_MTCS0 		((volatile unsigned long  *)SPORT2_MTCS0)
-#define pSPORT2_MTCS1 		((volatile unsigned long  *)SPORT2_MTCS1)
-#define pSPORT2_MTCS2 		((volatile unsigned long  *)SPORT2_MTCS2)
-#define pSPORT2_MTCS3 		((volatile unsigned long  *)SPORT2_MTCS3)
-#define pSPORT2_MRCS0 		((volatile unsigned long  *)SPORT2_MRCS0)
-#define pSPORT2_MRCS1 		((volatile unsigned long  *)SPORT2_MRCS1)
-#define pSPORT2_MRCS2 		((volatile unsigned long  *)SPORT2_MRCS2)
-#define pSPORT2_MRCS3 		((volatile unsigned long  *)SPORT2_MRCS3)
-
-
-/* SPORT3 Controller						*/
-#define pSPORT3_TCR1 		((volatile unsigned short *)SPORT3_TCR1)
-#define pSPORT3_TCR2 		((volatile unsigned short *)SPORT3_TCR2)
-#define pSPORT3_TCLKDIV 	((volatile unsigned short *)SPORT3_TCLKDIV)
-#define pSPORT3_TFSDIV 		((volatile unsigned short *)SPORT3_TFSDIV)
-#define pSPORT3_TX 			((volatile unsigned long  *)SPORT3_TX)
-#define pSPORT3_RX 			((volatile unsigned long  *)SPORT3_RX)
-#define pSPORT3_TX32 		((volatile unsigned long  *)SPORT3_TX)
-#define pSPORT3_RX32 		((volatile unsigned long  *)SPORT3_RX)
-#define pSPORT3_TX16 		((volatile unsigned short *)SPORT3_TX)
-#define pSPORT3_RX16 		((volatile unsigned short *)SPORT3_RX)
-#define pSPORT3_RCR1 		((volatile unsigned short *)SPORT3_RCR1)
-#define pSPORT3_RCR2 		((volatile unsigned short *)SPORT3_RCR2)
-#define pSPORT3_RCLKDIV 	((volatile unsigned short *)SPORT3_RCLKDIV)
-#define pSPORT3_RFSDIV 		((volatile unsigned short *)SPORT3_RFSDIV)
-#define pSPORT3_STAT 		((volatile unsigned short *)SPORT3_STAT)
-#define pSPORT3_CHNL 		((volatile unsigned short *)SPORT3_CHNL)
-#define pSPORT3_MCMC1 		((volatile unsigned short *)SPORT3_MCMC1)
-#define pSPORT3_MCMC2 		((volatile unsigned short *)SPORT3_MCMC2)
-#define pSPORT3_MTCS0 		((volatile unsigned long  *)SPORT3_MTCS0)
-#define pSPORT3_MTCS1 		((volatile unsigned long  *)SPORT3_MTCS1)
-#define pSPORT3_MTCS2 		((volatile unsigned long  *)SPORT3_MTCS2)
-#define pSPORT3_MTCS3 		((volatile unsigned long  *)SPORT3_MTCS3)
-#define pSPORT3_MRCS0 		((volatile unsigned long  *)SPORT3_MRCS0)
-#define pSPORT3_MRCS1 		((volatile unsigned long  *)SPORT3_MRCS1)
-#define pSPORT3_MRCS2 		((volatile unsigned long  *)SPORT3_MRCS2)
-#define pSPORT3_MRCS3 		((volatile unsigned long  *)SPORT3_MRCS3)
-
-
-/* CAN Controller						*/
-/* For Mailboxes 0-15													*/
-#define pCAN_MC1			((volatile unsigned short *)CAN_MC1)
-#define pCAN_MD1			((volatile unsigned short *)CAN_MD1)
-#define pCAN_TRS1			((volatile unsigned short *)CAN_TRS1)
-#define pCAN_TRR1			((volatile unsigned short *)CAN_TRR1)
-#define pCAN_TA1			((volatile unsigned short *)CAN_TA1)
-#define pCAN_AA1			((volatile unsigned short *)CAN_AA1)
-#define pCAN_RMP1			((volatile unsigned short *)CAN_RMP1)
-#define pCAN_RML1			((volatile unsigned short *)CAN_RML1)
-#define pCAN_MBTIF1			((volatile unsigned short *)CAN_MBTIF1)
-#define pCAN_MBRIF1			((volatile unsigned short *)CAN_MBRIF1)
-#define pCAN_MBIM1			((volatile unsigned short *)CAN_MBIM1)
-#define pCAN_RFH1			((volatile unsigned short *)CAN_RFH1)
-#define pCAN_OPSS1			((volatile unsigned short *)CAN_OPSS1)
-
-/* For Mailboxes 16-31   												*/
-#define pCAN_MC2			((volatile unsigned short *)CAN_MC2)
-#define pCAN_MD2			((volatile unsigned short *)CAN_MD2)
-#define pCAN_TRS2			((volatile unsigned short *)CAN_TRS2)
-#define pCAN_TRR2			((volatile unsigned short *)CAN_TRR2)
-#define pCAN_TA2			((volatile unsigned short *)CAN_TA2)
-#define pCAN_AA2			((volatile unsigned short *)CAN_AA2)
-#define pCAN_RMP2			((volatile unsigned short *)CAN_RMP2)
-#define pCAN_RML2			((volatile unsigned short *)CAN_RML2)
-#define pCAN_MBTIF2			((volatile unsigned short *)CAN_MBTIF2)
-#define pCAN_MBRIF2			((volatile unsigned short *)CAN_MBRIF2)
-#define pCAN_MBIM2			((volatile unsigned short *)CAN_MBIM2)
-#define pCAN_RFH2			((volatile unsigned short *)CAN_RFH2)
-#define pCAN_OPSS2			((volatile unsigned short *)CAN_OPSS2)
-
-#define pCAN_CLOCK			((volatile unsigned short *)CAN_CLOCK)
-#define pCAN_TIMING			((volatile unsigned short *)CAN_TIMING)
-#define pCAN_DEBUG			((volatile unsigned short *)CAN_DEBUG)
-#define pCAN_STATUS			((volatile unsigned short *)CAN_STATUS)
-#define pCAN_CEC			((volatile unsigned short *)CAN_CEC)
-#define pCAN_GIS			((volatile unsigned short *)CAN_GIS)
-#define pCAN_GIM			((volatile unsigned short *)CAN_GIM)
-#define pCAN_GIF			((volatile unsigned short *)CAN_GIF)
-#define pCAN_CONTROL		((volatile unsigned short *)CAN_CONTROL)
-#define pCAN_INTR			((volatile unsigned short *)CAN_INTR)
-#define pCAN_MBTD			((volatile unsigned short *)CAN_MBTD)
-#define pCAN_EWR			((volatile unsigned short *)CAN_EWR)
-#define pCAN_ESR			((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCCNT			((volatile unsigned short *)CAN_UCCNT)
-#define pCAN_UCRC			((volatile unsigned short *)CAN_UCRC)
-#define pCAN_UCCNF			((volatile unsigned short *)CAN_UCCNF)
-
-/* Mailbox Acceptance Masks 											*/
-#define pCAN_AM00L			((volatile unsigned short *)CAN_AM00L)
-#define pCAN_AM00H			((volatile unsigned short *)CAN_AM00H)
-#define pCAN_AM01L			((volatile unsigned short *)CAN_AM01L)
-#define pCAN_AM01H			((volatile unsigned short *)CAN_AM01H)
-#define pCAN_AM02L			((volatile unsigned short *)CAN_AM02L)
-#define pCAN_AM02H			((volatile unsigned short *)CAN_AM02H)
-#define pCAN_AM03L			((volatile unsigned short *)CAN_AM03L)
-#define pCAN_AM03H			((volatile unsigned short *)CAN_AM03H)
-#define pCAN_AM04L			((volatile unsigned short *)CAN_AM04L)
-#define pCAN_AM04H			((volatile unsigned short *)CAN_AM04H)
-#define pCAN_AM05L			((volatile unsigned short *)CAN_AM05L)
-#define pCAN_AM05H			((volatile unsigned short *)CAN_AM05H)
-#define pCAN_AM06L			((volatile unsigned short *)CAN_AM06L)
-#define pCAN_AM06H			((volatile unsigned short *)CAN_AM06H)
-#define pCAN_AM07L			((volatile unsigned short *)CAN_AM07L)
-#define pCAN_AM07H			((volatile unsigned short *)CAN_AM07H)
-#define pCAN_AM08L			((volatile unsigned short *)CAN_AM08L)
-#define pCAN_AM08H			((volatile unsigned short *)CAN_AM08H)
-#define pCAN_AM09L			((volatile unsigned short *)CAN_AM09L)
-#define pCAN_AM09H			((volatile unsigned short *)CAN_AM09H)
-#define pCAN_AM10L			((volatile unsigned short *)CAN_AM10L)
-#define pCAN_AM10H			((volatile unsigned short *)CAN_AM10H)
-#define pCAN_AM11L			((volatile unsigned short *)CAN_AM11L)
-#define pCAN_AM11H			((volatile unsigned short *)CAN_AM11H)
-#define pCAN_AM12L			((volatile unsigned short *)CAN_AM12L)
-#define pCAN_AM12H			((volatile unsigned short *)CAN_AM12H)
-#define pCAN_AM13L			((volatile unsigned short *)CAN_AM13L)
-#define pCAN_AM13H			((volatile unsigned short *)CAN_AM13H)
-#define pCAN_AM14L			((volatile unsigned short *)CAN_AM14L)
-#define pCAN_AM14H			((volatile unsigned short *)CAN_AM14H)
-#define pCAN_AM15L			((volatile unsigned short *)CAN_AM15L)
-#define pCAN_AM15H			((volatile unsigned short *)CAN_AM15H)
-
-#define pCAN_AM16L			((volatile unsigned short *)CAN_AM16L)
-#define pCAN_AM16H			((volatile unsigned short *)CAN_AM16H)
-#define pCAN_AM17L			((volatile unsigned short *)CAN_AM17L)
-#define pCAN_AM17H			((volatile unsigned short *)CAN_AM17H)
-#define pCAN_AM18L			((volatile unsigned short *)CAN_AM18L)
-#define pCAN_AM18H			((volatile unsigned short *)CAN_AM18H)
-#define pCAN_AM19L			((volatile unsigned short *)CAN_AM19L)
-#define pCAN_AM19H			((volatile unsigned short *)CAN_AM19H)
-#define pCAN_AM20L			((volatile unsigned short *)CAN_AM20L)
-#define pCAN_AM20H			((volatile unsigned short *)CAN_AM20H)
-#define pCAN_AM21L			((volatile unsigned short *)CAN_AM21L)
-#define pCAN_AM21H			((volatile unsigned short *)CAN_AM21H)
-#define pCAN_AM22L			((volatile unsigned short *)CAN_AM22L)
-#define pCAN_AM22H			((volatile unsigned short *)CAN_AM22H)
-#define pCAN_AM23L			((volatile unsigned short *)CAN_AM23L)
-#define pCAN_AM23H			((volatile unsigned short *)CAN_AM23H)
-#define pCAN_AM24L			((volatile unsigned short *)CAN_AM24L)
-#define pCAN_AM24H			((volatile unsigned short *)CAN_AM24H)
-#define pCAN_AM25L			((volatile unsigned short *)CAN_AM25L)
-#define pCAN_AM25H			((volatile unsigned short *)CAN_AM25H)
-#define pCAN_AM26L			((volatile unsigned short *)CAN_AM26L)
-#define pCAN_AM26H			((volatile unsigned short *)CAN_AM26H)
-#define pCAN_AM27L			((volatile unsigned short *)CAN_AM27L)
-#define pCAN_AM27H			((volatile unsigned short *)CAN_AM27H)
-#define pCAN_AM28L			((volatile unsigned short *)CAN_AM28L)
-#define pCAN_AM28H			((volatile unsigned short *)CAN_AM28H)
-#define pCAN_AM29L			((volatile unsigned short *)CAN_AM29L)
-#define pCAN_AM29H			((volatile unsigned short *)CAN_AM29H)
-#define pCAN_AM30L			((volatile unsigned short *)CAN_AM30L)
-#define pCAN_AM30H			((volatile unsigned short *)CAN_AM30H)
-#define pCAN_AM31L			((volatile unsigned short *)CAN_AM31L)
-#define pCAN_AM31H			((volatile unsigned short *)CAN_AM31H)
-
-/* CAN Acceptance Mask Area Macros	*/
-#define pCAN_AM_L(x)		((volatile unsigned short *)CAN_AM_L(x))
-#define pCAN_AM_H(x)		((volatile unsigned short *)CAN_AM_H(x))
-
-/* Mailbox Registers														*/
-#define pCAN_MB00_DATA0		((volatile unsigned short *)CAN_MB00_DATA0)
-#define pCAN_MB00_DATA1		((volatile unsigned short *)CAN_MB00_DATA1)
-#define pCAN_MB00_DATA2		((volatile unsigned short *)CAN_MB00_DATA2)
-#define pCAN_MB00_DATA3		((volatile unsigned short *)CAN_MB00_DATA3)
-#define pCAN_MB00_LENGTH	((volatile unsigned short *)CAN_MB00_LENGTH)
-#define pCAN_MB00_TIMESTAMP	((volatile unsigned short *)CAN_MB00_TIMESTAMP)
-#define pCAN_MB00_ID0		((volatile unsigned short *)CAN_MB00_ID0)
-#define pCAN_MB00_ID1		((volatile unsigned short *)CAN_MB00_ID1)
-
-#define pCAN_MB01_DATA0		((volatile unsigned short *)CAN_MB01_DATA0)
-#define pCAN_MB01_DATA1		((volatile unsigned short *)CAN_MB01_DATA1)
-#define pCAN_MB01_DATA2		((volatile unsigned short *)CAN_MB01_DATA2)
-#define pCAN_MB01_DATA3		((volatile unsigned short *)CAN_MB01_DATA3)
-#define pCAN_MB01_LENGTH	((volatile unsigned short *)CAN_MB01_LENGTH)
-#define pCAN_MB01_TIMESTAMP	((volatile unsigned short *)CAN_MB01_TIMESTAMP)
-#define pCAN_MB01_ID0		((volatile unsigned short *)CAN_MB01_ID0)
-#define pCAN_MB01_ID1		((volatile unsigned short *)CAN_MB01_ID1)
-
-#define pCAN_MB02_DATA0		((volatile unsigned short *)CAN_MB02_DATA0)
-#define pCAN_MB02_DATA1		((volatile unsigned short *)CAN_MB02_DATA1)
-#define pCAN_MB02_DATA2		((volatile unsigned short *)CAN_MB02_DATA2)
-#define pCAN_MB02_DATA3		((volatile unsigned short *)CAN_MB02_DATA3)
-#define pCAN_MB02_LENGTH	((volatile unsigned short *)CAN_MB02_LENGTH)
-#define pCAN_MB02_TIMESTAMP	((volatile unsigned short *)CAN_MB02_TIMESTAMP)
-#define pCAN_MB02_ID0		((volatile unsigned short *)CAN_MB02_ID0)
-#define pCAN_MB02_ID1		((volatile unsigned short *)CAN_MB02_ID1)
-
-#define pCAN_MB03_DATA0		((volatile unsigned short *)CAN_MB03_DATA0)
-#define pCAN_MB03_DATA1		((volatile unsigned short *)CAN_MB03_DATA1)
-#define pCAN_MB03_DATA2		((volatile unsigned short *)CAN_MB03_DATA2)
-#define pCAN_MB03_DATA3		((volatile unsigned short *)CAN_MB03_DATA3)
-#define pCAN_MB03_LENGTH	((volatile unsigned short *)CAN_MB03_LENGTH)
-#define pCAN_MB03_TIMESTAMP	((volatile unsigned short *)CAN_MB03_TIMESTAMP)
-#define pCAN_MB03_ID0		((volatile unsigned short *)CAN_MB03_ID0)
-#define pCAN_MB03_ID1		((volatile unsigned short *)CAN_MB03_ID1)
-
-#define pCAN_MB04_DATA0		((volatile unsigned short *)CAN_MB04_DATA0)
-#define pCAN_MB04_DATA1		((volatile unsigned short *)CAN_MB04_DATA1)
-#define pCAN_MB04_DATA2		((volatile unsigned short *)CAN_MB04_DATA2)
-#define pCAN_MB04_DATA3		((volatile unsigned short *)CAN_MB04_DATA3)
-#define pCAN_MB04_LENGTH	((volatile unsigned short *)CAN_MB04_LENGTH)
-#define pCAN_MB04_TIMESTAMP	((volatile unsigned short *)CAN_MB04_TIMESTAMP)
-#define pCAN_MB04_ID0		((volatile unsigned short *)CAN_MB04_ID0)
-#define pCAN_MB04_ID1		((volatile unsigned short *)CAN_MB04_ID1)
-
-#define pCAN_MB05_DATA0		((volatile unsigned short *)CAN_MB05_DATA0)
-#define pCAN_MB05_DATA1		((volatile unsigned short *)CAN_MB05_DATA1)
-#define pCAN_MB05_DATA2		((volatile unsigned short *)CAN_MB05_DATA2)
-#define pCAN_MB05_DATA3		((volatile unsigned short *)CAN_MB05_DATA3)
-#define pCAN_MB05_LENGTH	((volatile unsigned short *)CAN_MB05_LENGTH)
-#define pCAN_MB05_TIMESTAMP	((volatile unsigned short *)CAN_MB05_TIMESTAMP)
-#define pCAN_MB05_ID0		((volatile unsigned short *)CAN_MB05_ID0)
-#define pCAN_MB05_ID1		((volatile unsigned short *)CAN_MB05_ID1)
-
-#define pCAN_MB06_DATA0		((volatile unsigned short *)CAN_MB06_DATA0)
-#define pCAN_MB06_DATA1		((volatile unsigned short *)CAN_MB06_DATA1)
-#define pCAN_MB06_DATA2		((volatile unsigned short *)CAN_MB06_DATA2)
-#define pCAN_MB06_DATA3		((volatile unsigned short *)CAN_MB06_DATA3)
-#define pCAN_MB06_LENGTH	((volatile unsigned short *)CAN_MB06_LENGTH)
-#define pCAN_MB06_TIMESTAMP	((volatile unsigned short *)CAN_MB06_TIMESTAMP)
-#define pCAN_MB06_ID0		((volatile unsigned short *)CAN_MB06_ID0)
-#define pCAN_MB06_ID1		((volatile unsigned short *)CAN_MB06_ID1)
-
-#define pCAN_MB07_DATA0		((volatile unsigned short *)CAN_MB07_DATA0)
-#define pCAN_MB07_DATA1		((volatile unsigned short *)CAN_MB07_DATA1)
-#define pCAN_MB07_DATA2		((volatile unsigned short *)CAN_MB07_DATA2)
-#define pCAN_MB07_DATA3		((volatile unsigned short *)CAN_MB07_DATA3)
-#define pCAN_MB07_LENGTH	((volatile unsigned short *)CAN_MB07_LENGTH)
-#define pCAN_MB07_TIMESTAMP	((volatile unsigned short *)CAN_MB07_TIMESTAMP)
-#define pCAN_MB07_ID0		((volatile unsigned short *)CAN_MB07_ID0)
-#define pCAN_MB07_ID1		((volatile unsigned short *)CAN_MB07_ID1)
-
-#define pCAN_MB08_DATA0		((volatile unsigned short *)CAN_MB08_DATA0)
-#define pCAN_MB08_DATA1		((volatile unsigned short *)CAN_MB08_DATA1)
-#define pCAN_MB08_DATA2		((volatile unsigned short *)CAN_MB08_DATA2)
-#define pCAN_MB08_DATA3		((volatile unsigned short *)CAN_MB08_DATA3)
-#define pCAN_MB08_LENGTH	((volatile unsigned short *)CAN_MB08_LENGTH)
-#define pCAN_MB08_TIMESTAMP	((volatile unsigned short *)CAN_MB08_TIMESTAMP)
-#define pCAN_MB08_ID0		((volatile unsigned short *)CAN_MB08_ID0)
-#define pCAN_MB08_ID1		((volatile unsigned short *)CAN_MB08_ID1)
-
-#define pCAN_MB09_DATA0		((volatile unsigned short *)CAN_MB09_DATA0)
-#define pCAN_MB09_DATA1		((volatile unsigned short *)CAN_MB09_DATA1)
-#define pCAN_MB09_DATA2		((volatile unsigned short *)CAN_MB09_DATA2)
-#define pCAN_MB09_DATA3		((volatile unsigned short *)CAN_MB09_DATA3)
-#define pCAN_MB09_LENGTH	((volatile unsigned short *)CAN_MB09_LENGTH)
-#define pCAN_MB09_TIMESTAMP	((volatile unsigned short *)CAN_MB09_TIMESTAMP)
-#define pCAN_MB09_ID0		((volatile unsigned short *)CAN_MB09_ID0)
-#define pCAN_MB09_ID1		((volatile unsigned short *)CAN_MB09_ID1)
-
-#define pCAN_MB10_DATA0		((volatile unsigned short *)CAN_MB10_DATA0)
-#define pCAN_MB10_DATA1		((volatile unsigned short *)CAN_MB10_DATA1)
-#define pCAN_MB10_DATA2		((volatile unsigned short *)CAN_MB10_DATA2)
-#define pCAN_MB10_DATA3		((volatile unsigned short *)CAN_MB10_DATA3)
-#define pCAN_MB10_LENGTH	((volatile unsigned short *)CAN_MB10_LENGTH)
-#define pCAN_MB10_TIMESTAMP	((volatile unsigned short *)CAN_MB10_TIMESTAMP)
-#define pCAN_MB10_ID0		((volatile unsigned short *)CAN_MB10_ID0)
-#define pCAN_MB10_ID1		((volatile unsigned short *)CAN_MB10_ID1)
-
-#define pCAN_MB11_DATA0		((volatile unsigned short *)CAN_MB11_DATA0)
-#define pCAN_MB11_DATA1		((volatile unsigned short *)CAN_MB11_DATA1)
-#define pCAN_MB11_DATA2		((volatile unsigned short *)CAN_MB11_DATA2)
-#define pCAN_MB11_DATA3		((volatile unsigned short *)CAN_MB11_DATA3)
-#define pCAN_MB11_LENGTH	((volatile unsigned short *)CAN_MB11_LENGTH)
-#define pCAN_MB11_TIMESTAMP	((volatile unsigned short *)CAN_MB11_TIMESTAMP)
-#define pCAN_MB11_ID0		((volatile unsigned short *)CAN_MB11_ID0)
-#define pCAN_MB11_ID1		((volatile unsigned short *)CAN_MB11_ID1)
-
-#define pCAN_MB12_DATA0		((volatile unsigned short *)CAN_MB12_DATA0)
-#define pCAN_MB12_DATA1		((volatile unsigned short *)CAN_MB12_DATA1)
-#define pCAN_MB12_DATA2		((volatile unsigned short *)CAN_MB12_DATA2)
-#define pCAN_MB12_DATA3		((volatile unsigned short *)CAN_MB12_DATA3)
-#define pCAN_MB12_LENGTH	((volatile unsigned short *)CAN_MB12_LENGTH)
-#define pCAN_MB12_TIMESTAMP	((volatile unsigned short *)CAN_MB12_TIMESTAMP)
-#define pCAN_MB12_ID0		((volatile unsigned short *)CAN_MB12_ID0)
-#define pCAN_MB12_ID1		((volatile unsigned short *)CAN_MB12_ID1)
-
-#define pCAN_MB13_DATA0		((volatile unsigned short *)CAN_MB13_DATA0)
-#define pCAN_MB13_DATA1		((volatile unsigned short *)CAN_MB13_DATA1)
-#define pCAN_MB13_DATA2		((volatile unsigned short *)CAN_MB13_DATA2)
-#define pCAN_MB13_DATA3		((volatile unsigned short *)CAN_MB13_DATA3)
-#define pCAN_MB13_LENGTH	((volatile unsigned short *)CAN_MB13_LENGTH)
-#define pCAN_MB13_TIMESTAMP	((volatile unsigned short *)CAN_MB13_TIMESTAMP)
-#define pCAN_MB13_ID0		((volatile unsigned short *)CAN_MB13_ID0)
-#define pCAN_MB13_ID1		((volatile unsigned short *)CAN_MB13_ID1)
-
-#define pCAN_MB14_DATA0		((volatile unsigned short *)CAN_MB14_DATA0)
-#define pCAN_MB14_DATA1		((volatile unsigned short *)CAN_MB14_DATA1)
-#define pCAN_MB14_DATA2		((volatile unsigned short *)CAN_MB14_DATA2)
-#define pCAN_MB14_DATA3		((volatile unsigned short *)CAN_MB14_DATA3)
-#define pCAN_MB14_LENGTH	((volatile unsigned short *)CAN_MB14_LENGTH)
-#define pCAN_MB14_TIMESTAMP	((volatile unsigned short *)CAN_MB14_TIMESTAMP)
-#define pCAN_MB14_ID0		((volatile unsigned short *)CAN_MB14_ID0)
-#define pCAN_MB14_ID1		((volatile unsigned short *)CAN_MB14_ID1)
-
-#define pCAN_MB15_DATA0		((volatile unsigned short *)CAN_MB15_DATA0)
-#define pCAN_MB15_DATA1		((volatile unsigned short *)CAN_MB15_DATA1)
-#define pCAN_MB15_DATA2		((volatile unsigned short *)CAN_MB15_DATA2)
-#define pCAN_MB15_DATA3		((volatile unsigned short *)CAN_MB15_DATA3)
-#define pCAN_MB15_LENGTH	((volatile unsigned short *)CAN_MB15_LENGTH)
-#define pCAN_MB15_TIMESTAMP	((volatile unsigned short *)CAN_MB15_TIMESTAMP)
-#define pCAN_MB15_ID0		((volatile unsigned short *)CAN_MB15_ID0)
-#define pCAN_MB15_ID1		((volatile unsigned short *)CAN_MB15_ID1)
-
-#define pCAN_MB16_DATA0		((volatile unsigned short *)CAN_MB16_DATA0)
-#define pCAN_MB16_DATA1		((volatile unsigned short *)CAN_MB16_DATA1)
-#define pCAN_MB16_DATA2		((volatile unsigned short *)CAN_MB16_DATA2)
-#define pCAN_MB16_DATA3		((volatile unsigned short *)CAN_MB16_DATA3)
-#define pCAN_MB16_LENGTH	((volatile unsigned short *)CAN_MB16_LENGTH)
-#define pCAN_MB16_TIMESTAMP	((volatile unsigned short *)CAN_MB16_TIMESTAMP)
-#define pCAN_MB16_ID0		((volatile unsigned short *)CAN_MB16_ID0)
-#define pCAN_MB16_ID1		((volatile unsigned short *)CAN_MB16_ID1)
-
-#define pCAN_MB17_DATA0		((volatile unsigned short *)CAN_MB17_DATA0)
-#define pCAN_MB17_DATA1		((volatile unsigned short *)CAN_MB17_DATA1)
-#define pCAN_MB17_DATA2		((volatile unsigned short *)CAN_MB17_DATA2)
-#define pCAN_MB17_DATA3		((volatile unsigned short *)CAN_MB17_DATA3)
-#define pCAN_MB17_LENGTH	((volatile unsigned short *)CAN_MB17_LENGTH)
-#define pCAN_MB17_TIMESTAMP	((volatile unsigned short *)CAN_MB17_TIMESTAMP)
-#define pCAN_MB17_ID0		((volatile unsigned short *)CAN_MB17_ID0)
-#define pCAN_MB17_ID1		((volatile unsigned short *)CAN_MB17_ID1)
-
-#define pCAN_MB18_DATA0		((volatile unsigned short *)CAN_MB18_DATA0)
-#define pCAN_MB18_DATA1		((volatile unsigned short *)CAN_MB18_DATA1)
-#define pCAN_MB18_DATA2		((volatile unsigned short *)CAN_MB18_DATA2)
-#define pCAN_MB18_DATA3		((volatile unsigned short *)CAN_MB18_DATA3)
-#define pCAN_MB18_LENGTH	((volatile unsigned short *)CAN_MB18_LENGTH)
-#define pCAN_MB18_TIMESTAMP	((volatile unsigned short *)CAN_MB18_TIMESTAMP)
-#define pCAN_MB18_ID0		((volatile unsigned short *)CAN_MB18_ID0)
-#define pCAN_MB18_ID1		((volatile unsigned short *)CAN_MB18_ID1)
-
-#define pCAN_MB19_DATA0		((volatile unsigned short *)CAN_MB19_DATA0)
-#define pCAN_MB19_DATA1		((volatile unsigned short *)CAN_MB19_DATA1)
-#define pCAN_MB19_DATA2		((volatile unsigned short *)CAN_MB19_DATA2)
-#define pCAN_MB19_DATA3		((volatile unsigned short *)CAN_MB19_DATA3)
-#define pCAN_MB19_LENGTH	((volatile unsigned short *)CAN_MB19_LENGTH)
-#define pCAN_MB19_TIMESTAMP	((volatile unsigned short *)CAN_MB19_TIMESTAMP)
-#define pCAN_MB19_ID0		((volatile unsigned short *)CAN_MB19_ID0)
-#define pCAN_MB19_ID1		((volatile unsigned short *)CAN_MB19_ID1)
-
-#define pCAN_MB20_DATA0		((volatile unsigned short *)CAN_MB20_DATA0)
-#define pCAN_MB20_DATA1		((volatile unsigned short *)CAN_MB20_DATA1)
-#define pCAN_MB20_DATA2		((volatile unsigned short *)CAN_MB20_DATA2)
-#define pCAN_MB20_DATA3		((volatile unsigned short *)CAN_MB20_DATA3)
-#define pCAN_MB20_LENGTH	((volatile unsigned short *)CAN_MB20_LENGTH)
-#define pCAN_MB20_TIMESTAMP	((volatile unsigned short *)CAN_MB20_TIMESTAMP)
-#define pCAN_MB20_ID0		((volatile unsigned short *)CAN_MB20_ID0)
-#define pCAN_MB20_ID1		((volatile unsigned short *)CAN_MB20_ID1)
-
-#define pCAN_MB21_DATA0		((volatile unsigned short *)CAN_MB21_DATA0)
-#define pCAN_MB21_DATA1		((volatile unsigned short *)CAN_MB21_DATA1)
-#define pCAN_MB21_DATA2		((volatile unsigned short *)CAN_MB21_DATA2)
-#define pCAN_MB21_DATA3		((volatile unsigned short *)CAN_MB21_DATA3)
-#define pCAN_MB21_LENGTH	((volatile unsigned short *)CAN_MB21_LENGTH)
-#define pCAN_MB21_TIMESTAMP	((volatile unsigned short *)CAN_MB21_TIMESTAMP)
-#define pCAN_MB21_ID0		((volatile unsigned short *)CAN_MB21_ID0)
-#define pCAN_MB21_ID1		((volatile unsigned short *)CAN_MB21_ID1)
-
-#define pCAN_MB22_DATA0		((volatile unsigned short *)CAN_MB22_DATA0)
-#define pCAN_MB22_DATA1		((volatile unsigned short *)CAN_MB22_DATA1)
-#define pCAN_MB22_DATA2		((volatile unsigned short *)CAN_MB22_DATA2)
-#define pCAN_MB22_DATA3		((volatile unsigned short *)CAN_MB22_DATA3)
-#define pCAN_MB22_LENGTH	((volatile unsigned short *)CAN_MB22_LENGTH)
-#define pCAN_MB22_TIMESTAMP	((volatile unsigned short *)CAN_MB22_TIMESTAMP)
-#define pCAN_MB22_ID0		((volatile unsigned short *)CAN_MB22_ID0)
-#define pCAN_MB22_ID1		((volatile unsigned short *)CAN_MB22_ID1)
-
-#define pCAN_MB23_DATA0		((volatile unsigned short *)CAN_MB23_DATA0)
-#define pCAN_MB23_DATA1		((volatile unsigned short *)CAN_MB23_DATA1)
-#define pCAN_MB23_DATA2		((volatile unsigned short *)CAN_MB23_DATA2)
-#define pCAN_MB23_DATA3		((volatile unsigned short *)CAN_MB23_DATA3)
-#define pCAN_MB23_LENGTH	((volatile unsigned short *)CAN_MB23_LENGTH)
-#define pCAN_MB23_TIMESTAMP	((volatile unsigned short *)CAN_MB23_TIMESTAMP)
-#define pCAN_MB23_ID0		((volatile unsigned short *)CAN_MB23_ID0)
-#define pCAN_MB23_ID1		((volatile unsigned short *)CAN_MB23_ID1)
-
-#define pCAN_MB24_DATA0		((volatile unsigned short *)CAN_MB24_DATA0)
-#define pCAN_MB24_DATA1		((volatile unsigned short *)CAN_MB24_DATA1)
-#define pCAN_MB24_DATA2		((volatile unsigned short *)CAN_MB24_DATA2)
-#define pCAN_MB24_DATA3		((volatile unsigned short *)CAN_MB24_DATA3)
-#define pCAN_MB24_LENGTH	((volatile unsigned short *)CAN_MB24_LENGTH)
-#define pCAN_MB24_TIMESTAMP	((volatile unsigned short *)CAN_MB24_TIMESTAMP)
-#define pCAN_MB24_ID0		((volatile unsigned short *)CAN_MB24_ID0)
-#define pCAN_MB24_ID1		((volatile unsigned short *)CAN_MB24_ID1)
-
-#define pCAN_MB25_DATA0		((volatile unsigned short *)CAN_MB25_DATA0)
-#define pCAN_MB25_DATA1		((volatile unsigned short *)CAN_MB25_DATA1)
-#define pCAN_MB25_DATA2		((volatile unsigned short *)CAN_MB25_DATA2)
-#define pCAN_MB25_DATA3		((volatile unsigned short *)CAN_MB25_DATA3)
-#define pCAN_MB25_LENGTH	((volatile unsigned short *)CAN_MB25_LENGTH)
-#define pCAN_MB25_TIMESTAMP	((volatile unsigned short *)CAN_MB25_TIMESTAMP)
-#define pCAN_MB25_ID0		((volatile unsigned short *)CAN_MB25_ID0)
-#define pCAN_MB25_ID1		((volatile unsigned short *)CAN_MB25_ID1)
-
-#define pCAN_MB26_DATA0		((volatile unsigned short *)CAN_MB26_DATA0)
-#define pCAN_MB26_DATA1		((volatile unsigned short *)CAN_MB26_DATA1)
-#define pCAN_MB26_DATA2		((volatile unsigned short *)CAN_MB26_DATA2)
-#define pCAN_MB26_DATA3		((volatile unsigned short *)CAN_MB26_DATA3)
-#define pCAN_MB26_LENGTH	((volatile unsigned short *)CAN_MB26_LENGTH)
-#define pCAN_MB26_TIMESTAMP	((volatile unsigned short *)CAN_MB26_TIMESTAMP)
-#define pCAN_MB26_ID0		((volatile unsigned short *)CAN_MB26_ID0)
-#define pCAN_MB26_ID1		((volatile unsigned short *)CAN_MB26_ID1)
-
-#define pCAN_MB27_DATA0		((volatile unsigned short *)CAN_MB27_DATA0)
-#define pCAN_MB27_DATA1		((volatile unsigned short *)CAN_MB27_DATA1)
-#define pCAN_MB27_DATA2		((volatile unsigned short *)CAN_MB27_DATA2)
-#define pCAN_MB27_DATA3		((volatile unsigned short *)CAN_MB27_DATA3)
-#define pCAN_MB27_LENGTH	((volatile unsigned short *)CAN_MB27_LENGTH)
-#define pCAN_MB27_TIMESTAMP	((volatile unsigned short *)CAN_MB27_TIMESTAMP)
-#define pCAN_MB27_ID0		((volatile unsigned short *)CAN_MB27_ID0)
-#define pCAN_MB27_ID1		((volatile unsigned short *)CAN_MB27_ID1)
-
-#define pCAN_MB28_DATA0		((volatile unsigned short *)CAN_MB28_DATA0)
-#define pCAN_MB28_DATA1		((volatile unsigned short *)CAN_MB28_DATA1)
-#define pCAN_MB28_DATA2		((volatile unsigned short *)CAN_MB28_DATA2)
-#define pCAN_MB28_DATA3		((volatile unsigned short *)CAN_MB28_DATA3)
-#define pCAN_MB28_LENGTH	((volatile unsigned short *)CAN_MB28_LENGTH)
-#define pCAN_MB28_TIMESTAMP	((volatile unsigned short *)CAN_MB28_TIMESTAMP)
-#define pCAN_MB28_ID0		((volatile unsigned short *)CAN_MB28_ID0)
-#define pCAN_MB28_ID1		((volatile unsigned short *)CAN_MB28_ID1)
-
-#define pCAN_MB29_DATA0		((volatile unsigned short *)CAN_MB29_DATA0)
-#define pCAN_MB29_DATA1		((volatile unsigned short *)CAN_MB29_DATA1)
-#define pCAN_MB29_DATA2		((volatile unsigned short *)CAN_MB29_DATA2)
-#define pCAN_MB29_DATA3		((volatile unsigned short *)CAN_MB29_DATA3)
-#define pCAN_MB29_LENGTH	((volatile unsigned short *)CAN_MB29_LENGTH)
-#define pCAN_MB29_TIMESTAMP	((volatile unsigned short *)CAN_MB29_TIMESTAMP)
-#define pCAN_MB29_ID0		((volatile unsigned short *)CAN_MB29_ID0)
-#define pCAN_MB29_ID1		((volatile unsigned short *)CAN_MB29_ID1)
-
-#define pCAN_MB30_DATA0		((volatile unsigned short *)CAN_MB30_DATA0)
-#define pCAN_MB30_DATA1		((volatile unsigned short *)CAN_MB30_DATA1)
-#define pCAN_MB30_DATA2		((volatile unsigned short *)CAN_MB30_DATA2)
-#define pCAN_MB30_DATA3		((volatile unsigned short *)CAN_MB30_DATA3)
-#define pCAN_MB30_LENGTH	((volatile unsigned short *)CAN_MB30_LENGTH)
-#define pCAN_MB30_TIMESTAMP	((volatile unsigned short *)CAN_MB30_TIMESTAMP)
-#define pCAN_MB30_ID0		((volatile unsigned short *)CAN_MB30_ID0)
-#define pCAN_MB30_ID1		((volatile unsigned short *)CAN_MB30_ID1)
-
-#define pCAN_MB31_DATA0		((volatile unsigned short *)CAN_MB31_DATA0)
-#define pCAN_MB31_DATA1		((volatile unsigned short *)CAN_MB31_DATA1)
-#define pCAN_MB31_DATA2		((volatile unsigned short *)CAN_MB31_DATA2)
-#define pCAN_MB31_DATA3		((volatile unsigned short *)CAN_MB31_DATA3)
-#define pCAN_MB31_LENGTH	((volatile unsigned short *)CAN_MB31_LENGTH)
-#define pCAN_MB31_TIMESTAMP	((volatile unsigned short *)CAN_MB31_TIMESTAMP)
-#define pCAN_MB31_ID0		((volatile unsigned short *)CAN_MB31_ID0)
-#define pCAN_MB31_ID1		((volatile unsigned short *)CAN_MB31_ID1)
-
-
-/* CAN Mailbox Area Macros		*/
-#define pCAN_MB_ID1(x)			((volatile unsigned short *)CAN_MB_ID1(x))
-#define pCAN_MB_ID0(x)			((volatile unsigned short *)CAN_MB_ID0(x))
-#define pCAN_MB_TIMESTAMP(x)	((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
-#define pCAN_MB_LENGTH(x)		((volatile unsigned short *)CAN_MB_LENGTH(x))
-#define pCAN_MB_DATA3(x)		((volatile unsigned short *)CAN_MB_DATA3(x))
-#define pCAN_MB_DATA2(x)		((volatile unsigned short *)CAN_MB_DATA2(x))
-#define pCAN_MB_DATA1(x)		((volatile unsigned short *)CAN_MB_DATA1(x))
-#define pCAN_MB_DATA0(x)		((volatile unsigned short *)CAN_MB_DATA0(x))
-
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define pCAN_CNF         	pCAN_DEBUG
-#define pTWI0_PRESCALE   	pTWI0_CONTROL
-#define pTWI0_INT_SRC	 	pTWI0_INT_STAT
-#define pTWI0_INT_ENABLE 	pTWI0_INT_MASK
-#define pTWI1_PRESCALE		pTWI1_CONTROL
-#define pTWI1_INT_SRC		pTWI1_INT_STAT
-#define pTWI1_INT_ENABLE	pTWI1_INT_MASK
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF538_H */
-
diff --git a/libgloss/bfin/include/cdefBF539.h b/libgloss/bfin/include/cdefBF539.h
deleted file mode 100644
index 331ebe93e..000000000
--- a/libgloss/bfin/include/cdefBF539.h
+++ /dev/null
@@ -1,1421 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for BF539 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF539_H
-#define _CDEF_BF539_H
-
-/* include all Core registers and bit definitions */
-#include <defBF539.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* include built-in mneumonic macros */
-#include <ccblkfn.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-/* Clock/Regulator Control */
-#define pPLL_CTL 		((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 		((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 		((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 		((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 	((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID			((volatile unsigned long *)CHIPID)
-
-
-/* System Interrupt Controllers */
-#define pSWRST 			((volatile unsigned short *)SWRST)
-#define pSYSCR 			((volatile unsigned short *)SYSCR)
-
-#define pSIC_IMASK0 		((volatile unsigned long *)SIC_IMASK0)
-#define pSIC_IMASK1				((volatile unsigned long  *)SIC_IMASK1)
-
-#define pSIC_ISR0 		((volatile unsigned long *)SIC_ISR0)
-#define pSIC_ISR1 				((volatile unsigned long  *)SIC_ISR1)
-
-#define pSIC_IWR0 		((volatile unsigned long *)SIC_IWR0)
-#define pSIC_IWR1 				((volatile unsigned long  *)SIC_IWR1)
-
-#define pSIC_IAR0 		((volatile unsigned long *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile unsigned long *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile unsigned long *)SIC_IAR2)
-#define pSIC_IAR3 				((volatile unsigned long  *)SIC_IAR3)
-#define pSIC_IAR4 				((volatile unsigned long  *)SIC_IAR4)
-#define pSIC_IAR5 				((volatile unsigned long  *)SIC_IAR5)
-#define pSIC_IAR6 				((volatile unsigned long  *)SIC_IAR6)
-
-
-/* Watchdog Timer */
-#define pWDOG_CTL 		((volatile unsigned short *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile unsigned long *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile unsigned long *)WDOG_STAT)
-
-
-/* Real Time Clock */
-#define pRTC_STAT 		((volatile unsigned long *)RTC_STAT)
-#define pRTC_ICTL 		((volatile unsigned short *)RTC_ICTL)
-#define pRTC_ISTAT 		((volatile unsigned short *)RTC_ISTAT)
-#define pRTC_SWCNT 		((volatile unsigned short *)RTC_SWCNT)
-#define pRTC_ALARM 		((volatile unsigned long *)RTC_ALARM)
-#define pRTC_FAST 		((volatile unsigned short *)RTC_FAST)
-#define pRTC_PREN 		((volatile unsigned short *)RTC_PREN)
-
-
-/* UART0 Controller */
-#define pUART0_THR 		((volatile unsigned short *)UART0_THR)
-#define pUART0_RBR 		((volatile unsigned short *)UART0_RBR)
-#define pUART0_DLL 		((volatile unsigned short *)UART0_DLL)
-#define pUART0_IER 		((volatile unsigned short *)UART0_IER)
-#define pUART0_DLH 		((volatile unsigned short *)UART0_DLH)
-#define pUART0_IIR 		((volatile unsigned short *)UART0_IIR)
-#define pUART0_LCR 		((volatile unsigned short *)UART0_LCR)
-#define pUART0_MCR 		((volatile unsigned short *)UART0_MCR)
-#define pUART0_LSR 		((volatile unsigned short *)UART0_LSR)
-/* #define UART0_MSR */
-#define pUART0_SCR 		((volatile unsigned short *)UART0_SCR)
-#define pUART0_GCTL 		((volatile unsigned short *)UART0_GCTL)
-
-
-/* UART1 Controller							*/
-#define pUART1_THR 			((volatile unsigned short *)UART1_THR)
-#define pUART1_RBR 			((volatile unsigned short *)UART1_RBR)
-#define pUART1_DLL 			((volatile unsigned short *)UART1_DLL)
-#define pUART1_IER 			((volatile unsigned short *)UART1_IER)
-#define pUART1_DLH 			((volatile unsigned short *)UART1_DLH)
-#define pUART1_IIR 			((volatile unsigned short *)UART1_IIR)
-#define pUART1_LCR 			((volatile unsigned short *)UART1_LCR)
-#define pUART1_MCR 			((volatile unsigned short *)UART1_MCR)
-#define pUART1_LSR 			((volatile unsigned short *)UART1_LSR)
-#define pUART1_SCR 			((volatile unsigned short *)UART1_SCR)
-#define pUART1_GCTL 		((volatile unsigned short *)UART1_GCTL)
-
-
-/* UART2 Controller						*/
-#define pUART2_THR 			((volatile unsigned short *)UART2_THR)
-#define pUART2_RBR 			((volatile unsigned short *)UART2_RBR)
-#define pUART2_DLL 			((volatile unsigned short *)UART2_DLL)
-#define pUART2_IER 			((volatile unsigned short *)UART2_IER)
-#define pUART2_DLH 			((volatile unsigned short *)UART2_DLH)
-#define pUART2_IIR 			((volatile unsigned short *)UART2_IIR)
-#define pUART2_LCR 			((volatile unsigned short *)UART2_LCR)
-#define pUART2_MCR 			((volatile unsigned short *)UART2_MCR)
-#define pUART2_LSR 			((volatile unsigned short *)UART2_LSR)
-#define pUART2_SCR 			((volatile unsigned short *)UART2_SCR)
-#define pUART2_GCTL 		((volatile unsigned short *)UART2_GCTL)
-
-
-/* SPI0 Controller */
-#define pSPI0_CTL 		((volatile unsigned short *)SPI0_CTL)
-#define pSPI0_FLG 		((volatile unsigned short *)SPI0_FLG)
-#define pSPI0_STAT 		((volatile unsigned short *)SPI0_STAT)
-#define pSPI0_TDBR 		((volatile unsigned short *)SPI0_TDBR)
-#define pSPI0_RDBR 		((volatile unsigned short *)SPI0_RDBR)
-#define pSPI0_BAUD 		((volatile unsigned short *)SPI0_BAUD)
-#define pSPI0_SHADOW 	((volatile unsigned short *)SPI0_SHADOW)
-
-
-/* SPI1 Controller					*/
-#define pSPI1_CTL 			((volatile unsigned short *)SPI1_CTL)
-#define pSPI1_FLG 			((volatile unsigned short *)SPI1_FLG)
-#define pSPI1_STAT 			((volatile unsigned short *)SPI1_STAT)
-#define pSPI1_TDBR 			((volatile unsigned short *)SPI1_TDBR)
-#define pSPI1_RDBR 			((volatile unsigned short *)SPI1_RDBR)
-#define pSPI1_BAUD 			((volatile unsigned short *)SPI1_BAUD)
-#define pSPI1_SHADOW 		((volatile unsigned short *)SPI1_SHADOW)
-
-
-/* SPI2 Controller								*/
-#define pSPI2_CTL 			((volatile unsigned short *)SPI2_CTL)
-#define pSPI2_FLG 			((volatile unsigned short *)SPI2_FLG)
-#define pSPI2_STAT 			((volatile unsigned short *)SPI2_STAT)
-#define pSPI2_TDBR 			((volatile unsigned short *)SPI2_TDBR)
-#define pSPI2_RDBR 			((volatile unsigned short *)SPI2_RDBR)
-#define pSPI2_BAUD 			((volatile unsigned short *)SPI2_BAUD)
-#define pSPI2_SHADOW 		((volatile unsigned short *)SPI2_SHADOW)
-
-
-/* TIMER 0, 1, 2 Registers */
-#define pTIMER0_CONFIG 	((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 	((volatile unsigned long *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 	((volatile unsigned long *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 	((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 	((volatile unsigned long *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 	((volatile unsigned long *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 	((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 	((volatile unsigned long *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 	((volatile unsigned long *)TIMER2_WIDTH)
-
-#define pTIMER_ENABLE 	((volatile unsigned short *)TIMER_ENABLE)
-#define pTIMER_DISABLE 	((volatile unsigned short *)TIMER_DISABLE)
-#define pTIMER_STATUS 	((volatile unsigned short *)TIMER_STATUS)
-
-
-/* Two-Wire Interface 0						*/
-#define pTWI0_CLKDIV		((volatile unsigned short *)TWI0_CLKDIV)
-#define pTWI0_CONTROL		((volatile unsigned short *)TWI0_CONTROL)
-#define pTWI0_SLAVE_CTRL	((volatile unsigned short *)TWI0_SLAVE_CTRL)
-#define pTWI0_SLAVE_STAT	((volatile unsigned short *)TWI0_SLAVE_STAT)
-#define pTWI0_SLAVE_ADDR	((volatile unsigned short *)TWI0_SLAVE_ADDR)
-#define pTWI0_MASTER_CTRL	((volatile unsigned short *)TWI0_MASTER_CTRL)
-#define pTWI0_MASTER_STAT	((volatile unsigned short *)TWI0_MASTER_STAT)
-#define pTWI0_MASTER_ADDR	((volatile unsigned short *)TWI0_MASTER_ADDR)
-#define pTWI0_INT_STAT		((volatile unsigned short *)TWI0_INT_STAT)
-#define pTWI0_INT_MASK		((volatile unsigned short *)TWI0_INT_MASK)
-#define pTWI0_FIFO_CTRL		((volatile unsigned short *)TWI0_FIFO_CTRL)
-#define pTWI0_FIFO_STAT		((volatile unsigned short *)TWI0_FIFO_STAT)
-#define pTWI0_XMT_DATA8		((volatile unsigned short *)TWI0_XMT_DATA8)
-#define pTWI0_XMT_DATA16	((volatile unsigned short *)TWI0_XMT_DATA16)
-#define pTWI0_RCV_DATA8		((volatile unsigned short *)TWI0_RCV_DATA8)
-#define pTWI0_RCV_DATA16	((volatile unsigned short *)TWI0_RCV_DATA16)
-
-
-/* Two-Wire Interface 1						*/
-#define pTWI1_CLKDIV		((volatile unsigned short *)TWI1_CLKDIV)
-#define pTWI1_CONTROL		((volatile unsigned short *)TWI1_CONTROL)
-#define pTWI1_SLAVE_CTRL	((volatile unsigned short *)TWI1_SLAVE_CTRL)
-#define pTWI1_SLAVE_STAT	((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define pTWI1_SLAVE_ADDR	((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define pTWI1_MASTER_CTRL	((volatile unsigned short *)TWI1_MASTER_CTRL)
-#define pTWI1_MASTER_STAT	((volatile unsigned short *)TWI1_MASTER_STAT)
-#define pTWI1_MASTER_ADDR	((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define pTWI1_INT_STAT		((volatile unsigned short *)TWI1_INT_STAT)
-#define pTWI1_INT_MASK		((volatile unsigned short *)TWI1_INT_MASK)
-#define pTWI1_FIFO_CTRL		((volatile unsigned short *)TWI1_FIFO_CTRL)
-#define pTWI1_FIFO_STAT		((volatile unsigned short *)TWI1_FIFO_STAT)
-#define pTWI1_XMT_DATA8		((volatile unsigned short *)TWI1_XMT_DATA8)
-#define pTWI1_XMT_DATA16	((volatile unsigned short *)TWI1_XMT_DATA16)
-#define pTWI1_RCV_DATA8		((volatile unsigned short *)TWI1_RCV_DATA8)
-#define pTWI1_RCV_DATA16	((volatile unsigned short *)TWI1_RCV_DATA16)
-
-
-/* General Purpose I/O */
-/* Flag I/O (FIO_) */
-#define pFIO_FLAG_D 	((volatile unsigned short *)FIO_FLAG_D)
-#define pFIO_FLAG_C 	((volatile unsigned short *)FIO_FLAG_C)
-#define pFIO_FLAG_S 	((volatile unsigned short *)FIO_FLAG_S)
-#define pFIO_FLAG_T 	((volatile unsigned short *)FIO_FLAG_T)
-#define pFIO_MASKA_D 	((volatile unsigned short *)FIO_MASKA_D)
-#define pFIO_MASKA_C 	((volatile unsigned short *)FIO_MASKA_C)
-#define pFIO_MASKA_S 	((volatile unsigned short *)FIO_MASKA_S)
-#define pFIO_MASKA_T 	((volatile unsigned short *)FIO_MASKA_T)
-#define pFIO_MASKB_D 	((volatile unsigned short *)FIO_MASKB_D)
-#define pFIO_MASKB_C 	((volatile unsigned short *)FIO_MASKB_C)
-#define pFIO_MASKB_S 	((volatile unsigned short *)FIO_MASKB_S)
-#define pFIO_MASKB_T 	((volatile unsigned short *)FIO_MASKB_T)
-#define pFIO_DIR 		((volatile unsigned short *)FIO_DIR)
-#define pFIO_POLAR 		((volatile unsigned short *)FIO_POLAR)
-#define pFIO_EDGE 		((volatile unsigned short *)FIO_EDGE)
-#define pFIO_BOTH 		((volatile unsigned short *)FIO_BOTH)
-#define pFIO_INEN 		((volatile unsigned short *)FIO_INEN)
-
-/* GPIO Registers  (Port C/D/E)						*/
-#define pGPIO_C_CNFG			((volatile unsigned short *)GPIO_C_CNFG)
-#define pGPIO_D_CNFG			((volatile unsigned short *)GPIO_D_CNFG)
-#define pGPIO_E_CNFG			((volatile unsigned short *)GPIO_E_CNFG)
-
-#define pGPIO_C_D				((volatile unsigned short *)GPIO_C_D)
-#define pGPIO_D_D				((volatile unsigned short *)GPIO_D_D)
-#define pGPIO_E_D				((volatile unsigned short *)GPIO_E_D)
-
-#define pGPIO_C_C				((volatile unsigned short *)GPIO_C_C)
-#define pGPIO_D_C				((volatile unsigned short *)GPIO_D_C)
-#define pGPIO_E_C				((volatile unsigned short *)GPIO_E_C)
-
-#define pGPIO_C_S				((volatile unsigned short *)GPIO_C_S)
-#define pGPIO_D_S				((volatile unsigned short *)GPIO_D_S)
-#define pGPIO_E_S				((volatile unsigned short *)GPIO_E_S)
-
-#define pGPIO_C_T				((volatile unsigned short *)GPIO_C_T)
-#define pGPIO_D_T				((volatile unsigned short *)GPIO_D_T)
-#define pGPIO_E_T				((volatile unsigned short *)GPIO_E_T)
-
-#define pGPIO_C_DIR				((volatile unsigned short *)GPIO_C_DIR)
-#define pGPIO_D_DIR				((volatile unsigned short *)GPIO_D_DIR)
-#define pGPIO_E_DIR				((volatile unsigned short *)GPIO_E_DIR)
-
-#define pGPIO_C_INEN			((volatile unsigned short *)GPIO_C_INEN)
-#define pGPIO_D_INEN			((volatile unsigned short *)GPIO_D_INEN)
-#define pGPIO_E_INEN			((volatile unsigned short *)GPIO_E_INEN)
-
-/* Deprecate old macros */
-#define pGPIO_C_DAT pGPIO_C_D
-#define pGPIO_D_DAT pGPIO_D_D
-#define pGPIO_E_DAT pGPIO_E_D
-
-#define pGPIO_C_CLR pGPIO_C_C
-#define pGPIO_D_CLR pGPIO_D_C
-#define pGPIO_E_CLR pGPIO_E_C
-
-#define pGPIO_C_SET pGPIO_C_S
-#define pGPIO_D_SET pGPIO_D_S
-#define pGPIO_E_SET pGPIO_E_S
-
-#define pGPIO_C_TGL pGPIO_C_T
-#define pGPIO_D_TGL pGPIO_D_T
-#define pGPIO_E_TGL pGPIO_E_T
-
-/* SPORT0 Controller */
-#define pSPORT0_TCR1 	((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 	((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 	((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 		((volatile long *)SPORT0_TX)
-#define pSPORT0_RX 		((volatile long *)SPORT0_RX)
-#define pSPORT0_TX32	((volatile long *)SPORT0_TX)
-#define pSPORT0_RX32 	((volatile long *)SPORT0_RX)
-#define pSPORT0_TX16 	((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 	((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 	((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 	((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 	((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 	((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 	((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 	((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 	((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 	((volatile unsigned long *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 	((volatile unsigned long *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 	((volatile unsigned long *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 	((volatile unsigned long *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 	((volatile unsigned long *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 	((volatile unsigned long *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 	((volatile unsigned long *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 	((volatile unsigned long *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller */
-#define pSPORT1_TCR1 	((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 	((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 	((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile long *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile long *)SPORT1_RX)
-#define pSPORT1_TX32 	((volatile long *)SPORT1_TX)
-#define pSPORT1_RX32 	((volatile long *)SPORT1_RX)
-#define pSPORT1_TX16 	((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 	((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 	((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 	((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 	((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 	((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 	((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 	((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 	((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 	((volatile unsigned long *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 	((volatile unsigned long *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 	((volatile unsigned long *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 	((volatile unsigned long *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 	((volatile unsigned long *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 	((volatile unsigned long *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 	((volatile unsigned long *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 	((volatile unsigned long *)SPORT1_MRCS3)
-
-
-/* SPORT2 Controller					*/
-#define pSPORT2_TCR1 		((volatile unsigned short *)SPORT2_TCR1)
-#define pSPORT2_TCR2 		((volatile unsigned short *)SPORT2_TCR2)
-#define pSPORT2_TCLKDIV 	((volatile unsigned short *)SPORT2_TCLKDIV)
-#define pSPORT2_TFSDIV 		((volatile unsigned short *)SPORT2_TFSDIV)
-#define pSPORT2_TX 			((volatile unsigned long  *)SPORT2_TX)
-#define pSPORT2_RX 			((volatile unsigned long  *)SPORT2_RX)
-#define pSPORT2_TX32 		((volatile unsigned long  *)SPORT2_TX)
-#define pSPORT2_RX32 		((volatile unsigned long  *)SPORT2_RX)
-#define pSPORT2_TX16 		((volatile unsigned short *)SPORT2_TX)
-#define pSPORT2_RX16 		((volatile unsigned short *)SPORT2_RX)
-#define pSPORT2_RCR1 		((volatile unsigned short *)SPORT2_RCR1)
-#define pSPORT2_RCR2 		((volatile unsigned short *)SPORT2_RCR2)
-#define pSPORT2_RCLKDIV 	((volatile unsigned short *)SPORT2_RCLKDIV)
-#define pSPORT2_RFSDIV 		((volatile unsigned short *)SPORT2_RFSDIV)
-#define pSPORT2_STAT 		((volatile unsigned short *)SPORT2_STAT)
-#define pSPORT2_CHNL 		((volatile unsigned short *)SPORT2_CHNL)
-#define pSPORT2_MCMC1 		((volatile unsigned short *)SPORT2_MCMC1)
-#define pSPORT2_MCMC2 		((volatile unsigned short *)SPORT2_MCMC2)
-#define pSPORT2_MTCS0 		((volatile unsigned long  *)SPORT2_MTCS0)
-#define pSPORT2_MTCS1 		((volatile unsigned long  *)SPORT2_MTCS1)
-#define pSPORT2_MTCS2 		((volatile unsigned long  *)SPORT2_MTCS2)
-#define pSPORT2_MTCS3 		((volatile unsigned long  *)SPORT2_MTCS3)
-#define pSPORT2_MRCS0 		((volatile unsigned long  *)SPORT2_MRCS0)
-#define pSPORT2_MRCS1 		((volatile unsigned long  *)SPORT2_MRCS1)
-#define pSPORT2_MRCS2 		((volatile unsigned long  *)SPORT2_MRCS2)
-#define pSPORT2_MRCS3 		((volatile unsigned long  *)SPORT2_MRCS3)
-
-
-/* SPORT3 Controller						*/
-#define pSPORT3_TCR1 		((volatile unsigned short *)SPORT3_TCR1)
-#define pSPORT3_TCR2 		((volatile unsigned short *)SPORT3_TCR2)
-#define pSPORT3_TCLKDIV 	((volatile unsigned short *)SPORT3_TCLKDIV)
-#define pSPORT3_TFSDIV 		((volatile unsigned short *)SPORT3_TFSDIV)
-#define pSPORT3_TX 			((volatile unsigned long  *)SPORT3_TX)
-#define pSPORT3_RX 			((volatile unsigned long  *)SPORT3_RX)
-#define pSPORT3_TX32 		((volatile unsigned long  *)SPORT3_TX)
-#define pSPORT3_RX32 		((volatile unsigned long  *)SPORT3_RX)
-#define pSPORT3_TX16 		((volatile unsigned short *)SPORT3_TX)
-#define pSPORT3_RX16 		((volatile unsigned short *)SPORT3_RX)
-#define pSPORT3_RCR1 		((volatile unsigned short *)SPORT3_RCR1)
-#define pSPORT3_RCR2 		((volatile unsigned short *)SPORT3_RCR2)
-#define pSPORT3_RCLKDIV 	((volatile unsigned short *)SPORT3_RCLKDIV)
-#define pSPORT3_RFSDIV 		((volatile unsigned short *)SPORT3_RFSDIV)
-#define pSPORT3_STAT 		((volatile unsigned short *)SPORT3_STAT)
-#define pSPORT3_CHNL 		((volatile unsigned short *)SPORT3_CHNL)
-#define pSPORT3_MCMC1 		((volatile unsigned short *)SPORT3_MCMC1)
-#define pSPORT3_MCMC2 		((volatile unsigned short *)SPORT3_MCMC2)
-#define pSPORT3_MTCS0 		((volatile unsigned long  *)SPORT3_MTCS0)
-#define pSPORT3_MTCS1 		((volatile unsigned long  *)SPORT3_MTCS1)
-#define pSPORT3_MTCS2 		((volatile unsigned long  *)SPORT3_MTCS2)
-#define pSPORT3_MTCS3 		((volatile unsigned long  *)SPORT3_MTCS3)
-#define pSPORT3_MRCS0 		((volatile unsigned long  *)SPORT3_MRCS0)
-#define pSPORT3_MRCS1 		((volatile unsigned long  *)SPORT3_MRCS1)
-#define pSPORT3_MRCS2 		((volatile unsigned long  *)SPORT3_MRCS2)
-#define pSPORT3_MRCS3 		((volatile unsigned long  *)SPORT3_MRCS3)
-
-
-/* External Bus Interface Unit */
-/* Aysnchronous Memory Controller */
-#define pEBIU_AMGCTL 	((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 	((volatile unsigned long *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 	((volatile unsigned long *)EBIU_AMBCTL1)
-
-/* SDRAM Controller */
-#define pEBIU_SDGCTL 	((volatile unsigned long *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 	((volatile unsigned short *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 	((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 	((volatile unsigned short *)EBIU_SDSTAT)
-
-
-/* DMA Controller 0 Traffic controls */
-#define pDMAC0_TC_PER 	((volatile unsigned short *)DMAC0_TC_PER)
-#define pDMAC0_TC_CNT 	((volatile unsigned short *)DMAC0_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA0_TCPER 		((volatile unsigned short *)DMA0_TCPER)
-#define pDMA0_TCCNT 		((volatile unsigned short *)DMA0_TCCNT)
-
-
-/* DMA Controller 0 */
-#define pDMA0_CONFIG 			((volatile unsigned short *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 			((volatile unsigned short *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 			((volatile unsigned short *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 			((volatile signed short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 			((volatile signed short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 		((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 		((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 		((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 			((volatile unsigned short *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 			((volatile unsigned short *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 			((volatile unsigned short *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 			((volatile signed short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 			((volatile signed short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 		((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 		((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 		((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 			((volatile unsigned short *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 			((volatile unsigned short *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 			((volatile unsigned short *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 			((volatile signed short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 			((volatile signed short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 		((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 		((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 		((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 			((volatile unsigned short *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 			((volatile unsigned short *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 			((volatile unsigned short *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 			((volatile signed short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 			((volatile signed short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 		((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 		((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 		((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 			((volatile unsigned short *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 			((volatile unsigned short *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 			((volatile unsigned short *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 			((volatile signed short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 			((volatile signed short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 		((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 		((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 		((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 			((volatile unsigned short *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 			((volatile unsigned short *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 			((volatile unsigned short *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 			((volatile signed short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 			((volatile signed short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 		((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 		((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 		((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 			((volatile unsigned short *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 			((volatile unsigned short *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 			((volatile unsigned short *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 			((volatile signed short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 			((volatile signed short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 		((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 		((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 		((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 			((volatile unsigned short *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 			((volatile unsigned short *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 			((volatile unsigned short *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 			((volatile signed short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 			((volatile signed short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 		((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 		((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 		((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-
-#define pMDMA0_D1_CONFIG 		((volatile unsigned short *)MDMA0_D1_CONFIG)
-#define pMDMA0_D1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D1_NEXT_DESC_PTR)
-#define pMDMA0_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D1_START_ADDR)
-#define pMDMA0_D1_X_COUNT 		((volatile unsigned short *)MDMA0_D1_X_COUNT)
-#define pMDMA0_D1_Y_COUNT 		((volatile unsigned short *)MDMA0_D1_Y_COUNT)
-#define pMDMA0_D1_X_MODIFY 		((volatile signed short *)MDMA0_D1_X_MODIFY)
-#define pMDMA0_D1_Y_MODIFY 		((volatile signed short *)MDMA0_D1_Y_MODIFY)
-#define pMDMA0_D1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D1_CURR_DESC_PTR)
-#define pMDMA0_D1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA0_D1_CURR_ADDR)
-#define pMDMA0_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA0_D1_CURR_X_COUNT)
-#define pMDMA0_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA0_D1_CURR_Y_COUNT)
-#define pMDMA0_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA0_D1_IRQ_STATUS)
-#define pMDMA0_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_D1_PERIPHERAL_MAP)
-
-#define pMDMA0_S1_CONFIG 		((volatile unsigned short *)MDMA0_S1_CONFIG)
-#define pMDMA0_S1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S1_NEXT_DESC_PTR)
-#define pMDMA0_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S1_START_ADDR)
-#define pMDMA0_S1_X_COUNT 		((volatile unsigned short *)MDMA0_S1_X_COUNT)
-#define pMDMA0_S1_Y_COUNT 		((volatile unsigned short *)MDMA0_S1_Y_COUNT)
-#define pMDMA0_S1_X_MODIFY 		((volatile signed short *)MDMA0_S1_X_MODIFY)
-#define pMDMA0_S1_Y_MODIFY 		((volatile signed short *)MDMA0_S1_Y_MODIFY)
-#define pMDMA0_S1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S1_CURR_DESC_PTR)
-#define pMDMA0_S1_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA0_S1_CURR_ADDR)
-#define pMDMA0_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA0_S1_CURR_X_COUNT)
-#define pMDMA0_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA0_S1_CURR_Y_COUNT)
-#define pMDMA0_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA0_S1_IRQ_STATUS)
-#define pMDMA0_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_S1_PERIPHERAL_MAP)
-
-#define pMDMA0_D0_CONFIG 		((volatile unsigned short *)MDMA0_D0_CONFIG)
-#define pMDMA0_D0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D0_NEXT_DESC_PTR)
-#define pMDMA0_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D0_START_ADDR)
-#define pMDMA0_D0_X_COUNT 		((volatile unsigned short *)MDMA0_D0_X_COUNT)
-#define pMDMA0_D0_Y_COUNT 		((volatile unsigned short *)MDMA0_D0_Y_COUNT)
-#define pMDMA0_D0_X_MODIFY 		((volatile signed short *)MDMA0_D0_X_MODIFY)
-#define pMDMA0_D0_Y_MODIFY 		((volatile signed short *)MDMA0_D0_Y_MODIFY)
-#define pMDMA0_D0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_D0_CURR_DESC_PTR)
-#define pMDMA0_D0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA0_D0_CURR_ADDR)
-#define pMDMA0_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA0_D0_CURR_X_COUNT)
-#define pMDMA0_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA0_D0_CURR_Y_COUNT)
-#define pMDMA0_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA0_D0_IRQ_STATUS)
-#define pMDMA0_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_D0_PERIPHERAL_MAP)
-
-#define pMDMA0_S0_CONFIG 		((volatile unsigned short *)MDMA0_S0_CONFIG)
-#define pMDMA0_S0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S0_NEXT_DESC_PTR)
-#define pMDMA0_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S0_START_ADDR)
-#define pMDMA0_S0_X_COUNT 		((volatile unsigned short *)MDMA0_S0_X_COUNT)
-#define pMDMA0_S0_Y_COUNT 		((volatile unsigned short *)MDMA0_S0_Y_COUNT)
-#define pMDMA0_S0_X_MODIFY 		((volatile signed short *)MDMA0_S0_X_MODIFY)
-#define pMDMA0_S0_Y_MODIFY 		((volatile signed short *)MDMA0_S0_Y_MODIFY)
-#define pMDMA0_S0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR MDMA0_S0_CURR_DESC_PTR)
-#define pMDMA0_S0_CURR_ADDR 		(_PTR_TO_VOL_VOID_PTR MDMA0_S0_CURR_ADDR)
-#define pMDMA0_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA0_S0_CURR_X_COUNT)
-#define pMDMA0_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA0_S0_CURR_Y_COUNT)
-#define pMDMA0_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA0_S0_IRQ_STATUS)
-#define pMDMA0_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_S0_PERIPHERAL_MAP)
-
-
-/* DMA Controller 1 Traffic Control Registers											*/
-#define	pDMAC1_TC_PER				((volatile unsigned short *)DMAC1_TC_PER)
-#define	pDMAC1_TC_CNT				((volatile unsigned short *)DMAC1_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define pDMA1_TCPER					pDMA1_TCPER	/* Traffic Control Periods Register			*/
-#define pDMA1_TCCNT					pDMA1_TCCNT	/* Traffic Control Current Counts Register	*/
-
-/* DMA Controller 1 						*/
-#define pDMA8_NEXT_DESC_PTR 		((void * volatile *)DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 			((void * volatile *)DMA8_START_ADDR)
-#define pDMA8_CONFIG 				((volatile unsigned short *)DMA8_CONFIG)
-#define pDMA8_X_COUNT 				((volatile unsigned short *)DMA8_X_COUNT)
-#define pDMA8_X_MODIFY 				((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_COUNT 				((volatile unsigned short *)DMA8_Y_COUNT)
-#define pDMA8_Y_MODIFY 				((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 		((void * volatile *)DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 			((void * volatile *)DMA8_CURR_ADDR)
-#define pDMA8_IRQ_STATUS 			((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 		((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-#define pDMA8_CURR_X_COUNT 			((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 			((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-
-#define pDMA9_NEXT_DESC_PTR 		((void * volatile *)DMA9_NEXT_DESC_PTR)
-#define pDMA9_START_ADDR 			((void * volatile *)DMA9_START_ADDR)
-#define pDMA9_CONFIG 				((volatile unsigned short *)DMA9_CONFIG)
-#define pDMA9_X_COUNT 				((volatile unsigned short *)DMA9_X_COUNT)
-#define pDMA9_X_MODIFY 				((volatile signed   short *)DMA9_X_MODIFY)
-#define pDMA9_Y_COUNT 				((volatile unsigned short *)DMA9_Y_COUNT)
-#define pDMA9_Y_MODIFY 				((volatile signed   short *)DMA9_Y_MODIFY)
-#define pDMA9_CURR_DESC_PTR 		((void * volatile *)DMA9_CURR_DESC_PTR)
-#define pDMA9_CURR_ADDR 			((void * volatile *)DMA9_CURR_ADDR)
-#define pDMA9_IRQ_STATUS 			((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define pDMA9_PERIPHERAL_MAP 		((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-#define pDMA9_CURR_X_COUNT 			((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define pDMA9_CURR_Y_COUNT 			((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-
-#define pDMA10_NEXT_DESC_PTR 		((void * volatile *)DMA10_NEXT_DESC_PTR)
-#define pDMA10_START_ADDR 			((void * volatile *)DMA10_START_ADDR)
-#define pDMA10_CONFIG 				((volatile unsigned short *)DMA10_CONFIG)
-#define pDMA10_X_COUNT 				((volatile unsigned short *)DMA10_X_COUNT)
-#define pDMA10_X_MODIFY 			((volatile signed   short *)DMA10_X_MODIFY)
-#define pDMA10_Y_COUNT 				((volatile unsigned short *)DMA10_Y_COUNT)
-#define pDMA10_Y_MODIFY 			((volatile signed   short *)DMA10_Y_MODIFY)
-#define pDMA10_CURR_DESC_PTR 		((void * volatile *)DMA10_CURR_DESC_PTR)
-#define pDMA10_CURR_ADDR 			((void * volatile *)DMA10_CURR_ADDR)
-#define pDMA10_IRQ_STATUS 			((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define pDMA10_PERIPHERAL_MAP 		((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-#define pDMA10_CURR_X_COUNT 		((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define pDMA10_CURR_Y_COUNT 		((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-
-#define pDMA11_NEXT_DESC_PTR 		((void * volatile *)DMA11_NEXT_DESC_PTR)
-#define pDMA11_START_ADDR 			((void * volatile *)DMA11_START_ADDR)
-#define pDMA11_CONFIG 				((volatile unsigned short *)DMA11_CONFIG)
-#define pDMA11_X_COUNT 				((volatile unsigned short *)DMA11_X_COUNT)
-#define pDMA11_X_MODIFY 			((volatile signed   short *)DMA11_X_MODIFY)
-#define pDMA11_Y_COUNT 				((volatile unsigned short *)DMA11_Y_COUNT)
-#define pDMA11_Y_MODIFY 			((volatile signed   short *)DMA11_Y_MODIFY)
-#define pDMA11_CURR_DESC_PTR 		((void * volatile *)DMA11_CURR_DESC_PTR)
-#define pDMA11_CURR_ADDR 			((void * volatile *)DMA11_CURR_ADDR)
-#define pDMA11_IRQ_STATUS 			((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define pDMA11_PERIPHERAL_MAP 		((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-#define pDMA11_CURR_X_COUNT 		((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define pDMA11_CURR_Y_COUNT 		((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-
-#define pDMA12_NEXT_DESC_PTR 		((void * volatile *)DMA12_NEXT_DESC_PTR)
-#define pDMA12_START_ADDR 			((void * volatile *)DMA12_START_ADDR)
-#define pDMA12_CONFIG 				((volatile unsigned short *)DMA12_CONFIG)
-#define pDMA12_X_COUNT 				((volatile unsigned short *)DMA12_X_COUNT)
-#define pDMA12_X_MODIFY 			((volatile signed   short *)DMA12_X_MODIFY)
-#define pDMA12_Y_COUNT 				((volatile unsigned short *)DMA12_Y_COUNT)
-#define pDMA12_Y_MODIFY 			((volatile signed   short *)DMA12_Y_MODIFY)
-#define pDMA12_CURR_DESC_PTR 		((void * volatile *)DMA12_CURR_DESC_PTR)
-#define pDMA12_CURR_ADDR 			((void * volatile *)DMA12_CURR_ADDR)
-#define pDMA12_IRQ_STATUS 			((volatile unsigned short *)DMA12_IRQ_STATUS)
-#define pDMA12_PERIPHERAL_MAP 		((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
-#define pDMA12_CURR_X_COUNT 		((volatile unsigned short *)DMA12_CURR_X_COUNT)
-#define pDMA12_CURR_Y_COUNT 		((volatile unsigned short *)DMA12_CURR_Y_COUNT)
-
-#define pDMA13_NEXT_DESC_PTR 		((void * volatile *)DMA13_NEXT_DESC_PTR)
-#define pDMA13_START_ADDR 			((void * volatile *)DMA13_START_ADDR)
-#define pDMA13_CONFIG 				((volatile unsigned short *)DMA13_CONFIG)
-#define pDMA13_X_COUNT 				((volatile unsigned short *)DMA13_X_COUNT)
-#define pDMA13_X_MODIFY 			((volatile signed   short *)DMA13_X_MODIFY)
-#define pDMA13_Y_COUNT 				((volatile unsigned short *)DMA13_Y_COUNT)
-#define pDMA13_Y_MODIFY 			((volatile signed   short *)DMA13_Y_MODIFY)
-#define pDMA13_CURR_DESC_PTR 		((void * volatile *)DMA13_CURR_DESC_PTR)
-#define pDMA13_CURR_ADDR 			((void * volatile *)DMA13_CURR_ADDR)
-#define pDMA13_IRQ_STATUS 			((volatile unsigned short *)DMA13_IRQ_STATUS)
-#define pDMA13_PERIPHERAL_MAP 		((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
-#define pDMA13_CURR_X_COUNT 		((volatile unsigned short *)DMA13_CURR_X_COUNT)
-#define pDMA13_CURR_Y_COUNT 		((volatile unsigned short *)DMA13_CURR_Y_COUNT)
-
-#define pDMA14_NEXT_DESC_PTR 		((void * volatile *)DMA14_NEXT_DESC_PTR)
-#define pDMA14_START_ADDR 			((void * volatile *)DMA14_START_ADDR)
-#define pDMA14_CONFIG 				((volatile unsigned short *)DMA14_CONFIG)
-#define pDMA14_X_COUNT 				((volatile unsigned short *)DMA14_X_COUNT)
-#define pDMA14_X_MODIFY 			((volatile signed   short *)DMA14_X_MODIFY)
-#define pDMA14_Y_COUNT 				((volatile unsigned short *)DMA14_Y_COUNT)
-#define pDMA14_Y_MODIFY 			((volatile signed   short *)DMA14_Y_MODIFY)
-#define pDMA14_CURR_DESC_PTR 		((void * volatile *)DMA14_CURR_DESC_PTR)
-#define pDMA14_CURR_ADDR 			((void * volatile *)DMA14_CURR_ADDR)
-#define pDMA14_IRQ_STATUS 			((volatile unsigned short *)DMA14_IRQ_STATUS)
-#define pDMA14_PERIPHERAL_MAP 		((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
-#define pDMA14_CURR_X_COUNT 		((volatile unsigned short *)DMA14_CURR_X_COUNT)
-#define pDMA14_CURR_Y_COUNT 		((volatile unsigned short *)DMA14_CURR_Y_COUNT)
-
-#define pDMA15_NEXT_DESC_PTR 		((void * volatile *)DMA15_NEXT_DESC_PTR)
-#define pDMA15_START_ADDR 			((void * volatile *)DMA15_START_ADDR)
-#define pDMA15_CONFIG 				((volatile unsigned short *)DMA15_CONFIG)
-#define pDMA15_X_COUNT 				((volatile unsigned short *)DMA15_X_COUNT)
-#define pDMA15_X_MODIFY 			((volatile signed   short *)DMA15_X_MODIFY)
-#define pDMA15_Y_COUNT 				((volatile unsigned short *)DMA15_Y_COUNT)
-#define pDMA15_Y_MODIFY 			((volatile signed   short *)DMA15_Y_MODIFY)
-#define pDMA15_CURR_DESC_PTR 		((void * volatile *)DMA15_CURR_DESC_PTR)
-#define pDMA15_CURR_ADDR 			((void * volatile *)DMA15_CURR_ADDR)
-#define pDMA15_IRQ_STATUS 			((volatile unsigned short *)DMA15_IRQ_STATUS)
-#define pDMA15_PERIPHERAL_MAP 		((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
-#define pDMA15_CURR_X_COUNT 		((volatile unsigned short *)DMA15_CURR_X_COUNT)
-#define pDMA15_CURR_Y_COUNT 		((volatile unsigned short *)DMA15_CURR_Y_COUNT)
-
-#define pDMA16_NEXT_DESC_PTR 		((void * volatile *)DMA16_NEXT_DESC_PTR)
-#define pDMA16_START_ADDR 			((void * volatile *)DMA16_START_ADDR)
-#define pDMA16_CONFIG 				((volatile unsigned short *)DMA16_CONFIG)
-#define pDMA16_X_COUNT 				((volatile unsigned short *)DMA16_X_COUNT)
-#define pDMA16_X_MODIFY 			((volatile signed   short *)DMA16_X_MODIFY)
-#define pDMA16_Y_COUNT 				((volatile unsigned short *)DMA16_Y_COUNT)
-#define pDMA16_Y_MODIFY 			((volatile signed   short *)DMA16_Y_MODIFY)
-#define pDMA16_CURR_DESC_PTR 		((void * volatile *)DMA16_CURR_DESC_PTR)
-#define pDMA16_CURR_ADDR 			((void * volatile *)DMA16_CURR_ADDR)
-#define pDMA16_IRQ_STATUS 			((volatile unsigned short *)DMA16_IRQ_STATUS)
-#define pDMA16_PERIPHERAL_MAP 		((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
-#define pDMA16_CURR_X_COUNT 		((volatile unsigned short *)DMA16_CURR_X_COUNT)
-#define pDMA16_CURR_Y_COUNT 		((volatile unsigned short *)DMA16_CURR_Y_COUNT)
-
-#define pDMA17_NEXT_DESC_PTR 		((void * volatile *)DMA17_NEXT_DESC_PTR)
-#define pDMA17_START_ADDR 			((void * volatile *)DMA17_START_ADDR)
-#define pDMA17_CONFIG 				((volatile unsigned short *)DMA17_CONFIG)
-#define pDMA17_X_COUNT 				((volatile unsigned short *)DMA17_X_COUNT)
-#define pDMA17_X_MODIFY 			((volatile signed   short *)DMA17_X_MODIFY)
-#define pDMA17_Y_COUNT 				((volatile unsigned short *)DMA17_Y_COUNT)
-#define pDMA17_Y_MODIFY 			((volatile signed   short *)DMA17_Y_MODIFY)
-#define pDMA17_CURR_DESC_PTR 		((void * volatile *)DMA17_CURR_DESC_PTR)
-#define pDMA17_CURR_ADDR 			((void * volatile *)DMA17_CURR_ADDR)
-#define pDMA17_IRQ_STATUS 			((volatile unsigned short *)DMA17_IRQ_STATUS)
-#define pDMA17_PERIPHERAL_MAP 		((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
-#define pDMA17_CURR_X_COUNT 		((volatile unsigned short *)DMA17_CURR_X_COUNT)
-#define pDMA17_CURR_Y_COUNT 		((volatile unsigned short *)DMA17_CURR_Y_COUNT)
-
-#define pDMA18_NEXT_DESC_PTR 		((void * volatile *)DMA18_NEXT_DESC_PTR)
-#define pDMA18_START_ADDR 			((void * volatile *)DMA18_START_ADDR)
-#define pDMA18_CONFIG 				((volatile unsigned short *)DMA18_CONFIG)
-#define pDMA18_X_COUNT 				((volatile unsigned short *)DMA18_X_COUNT)
-#define pDMA18_X_MODIFY 			((volatile signed   short *)DMA18_X_MODIFY)
-#define pDMA18_Y_COUNT 				((volatile unsigned short *)DMA18_Y_COUNT)
-#define pDMA18_Y_MODIFY 			((volatile signed   short *)DMA18_Y_MODIFY)
-#define pDMA18_CURR_DESC_PTR 		((void * volatile *)DMA18_CURR_DESC_PTR)
-#define pDMA18_CURR_ADDR 			((void * volatile *)DMA18_CURR_ADDR)
-#define pDMA18_IRQ_STATUS 			((volatile unsigned short *)DMA18_IRQ_STATUS)
-#define pDMA18_PERIPHERAL_MAP 		((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
-#define pDMA18_CURR_X_COUNT 		((volatile unsigned short *)DMA18_CURR_X_COUNT)
-#define pDMA18_CURR_Y_COUNT 		((volatile unsigned short *)DMA18_CURR_Y_COUNT)
-
-#define pDMA19_NEXT_DESC_PTR 		((void * volatile *)DMA19_NEXT_DESC_PTR)
-#define pDMA19_START_ADDR 			((void * volatile *)DMA19_START_ADDR)
-#define pDMA19_CONFIG 				((volatile unsigned short *)DMA19_CONFIG)
-#define pDMA19_X_COUNT 				((volatile unsigned short *)DMA19_X_COUNT)
-#define pDMA19_X_MODIFY 			((volatile signed   short *)DMA19_X_MODIFY)
-#define pDMA19_Y_COUNT 				((volatile unsigned short *)DMA19_Y_COUNT)
-#define pDMA19_Y_MODIFY 			((volatile signed   short *)DMA19_Y_MODIFY)
-#define pDMA19_CURR_DESC_PTR 		((void * volatile *)DMA19_CURR_DESC_PTR)
-#define pDMA19_CURR_ADDR 			((void * volatile *)DMA19_CURR_ADDR)
-#define pDMA19_IRQ_STATUS 			((volatile unsigned short *)DMA19_IRQ_STATUS)
-#define pDMA19_PERIPHERAL_MAP 		((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
-#define pDMA19_CURR_X_COUNT 		((volatile unsigned short *)DMA19_CURR_X_COUNT)
-#define pDMA19_CURR_Y_COUNT 		((volatile unsigned short *)DMA19_CURR_Y_COUNT)
-
-#define pMDMA1_D0_NEXT_DESC_PTR 	((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
-#define pMDMA1_D0_START_ADDR 		((void * volatile *)MDMA1_D0_START_ADDR)
-#define pMDMA1_D0_CONFIG 			((volatile unsigned short *)MDMA1_D0_CONFIG)
-#define pMDMA1_D0_X_COUNT 			((volatile unsigned short *)MDMA1_D0_X_COUNT)
-#define pMDMA1_D0_X_MODIFY 			((volatile signed   short *)MDMA1_D0_X_MODIFY)
-#define pMDMA1_D0_Y_COUNT 			((volatile unsigned short *)MDMA1_D0_Y_COUNT)
-#define pMDMA1_D0_Y_MODIFY 			((volatile signed   short *)MDMA1_D0_Y_MODIFY)
-#define pMDMA1_D0_CURR_DESC_PTR 	((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
-#define pMDMA1_D0_CURR_ADDR 		((void * volatile *)MDMA1_D0_CURR_ADDR)
-#define pMDMA1_D0_IRQ_STATUS 		((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
-#define pMDMA1_D0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
-#define pMDMA1_D0_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT)
-#define pMDMA1_D0_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
-
-#define pMDMA1_S0_NEXT_DESC_PTR 	((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
-#define pMDMA1_S0_START_ADDR 		((void * volatile *)MDMA1_S0_START_ADDR)
-#define pMDMA1_S0_CONFIG 			((volatile unsigned short *)MDMA1_S0_CONFIG)
-#define pMDMA1_S0_X_COUNT 			((volatile unsigned short *)MDMA1_S0_X_COUNT)
-#define pMDMA1_S0_X_MODIFY 			((volatile signed   short *)MDMA1_S0_X_MODIFY)
-#define pMDMA1_S0_Y_COUNT 			((volatile unsigned short *)MDMA1_S0_Y_COUNT)
-#define pMDMA1_S0_Y_MODIFY 			((volatile signed   short *)MDMA1_S0_Y_MODIFY)
-#define pMDMA1_S0_CURR_DESC_PTR 	((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
-#define pMDMA1_S0_CURR_ADDR 		((void * volatile *)MDMA1_S0_CURR_ADDR)
-#define pMDMA1_S0_IRQ_STATUS 		((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
-#define pMDMA1_S0_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
-#define pMDMA1_S0_CURR_X_COUNT		((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
-#define pMDMA1_S0_CURR_Y_COUNT		((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
-
-#define pMDMA1_D1_NEXT_DESC_PTR 	((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
-#define pMDMA1_D1_START_ADDR 		((void * volatile *)MDMA1_D1_START_ADDR)
-#define pMDMA1_D1_CONFIG 			((volatile unsigned short *)MDMA1_D1_CONFIG)
-#define pMDMA1_D1_X_COUNT 			((volatile unsigned short *)MDMA1_D1_X_COUNT)
-#define pMDMA1_D1_X_MODIFY 			((volatile signed   short *)MDMA1_D1_X_MODIFY)
-#define pMDMA1_D1_Y_COUNT 			((volatile unsigned short *)MDMA1_D1_Y_COUNT)
-#define pMDMA1_D1_Y_MODIFY 			((volatile signed   short *)MDMA1_D1_Y_MODIFY)
-#define pMDMA1_D1_CURR_DESC_PTR 	((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
-#define pMDMA1_D1_CURR_ADDR 		((void * volatile *)MDMA1_D1_CURR_ADDR)
-#define pMDMA1_D1_IRQ_STATUS 		((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
-#define pMDMA1_D1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
-#define pMDMA1_D1_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
-#define pMDMA1_D1_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
-
-#define pMDMA1_S1_NEXT_DESC_PTR 	((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
-#define pMDMA1_S1_START_ADDR 		((void * volatile *)MDMA1_S1_START_ADDR)
-#define pMDMA1_S1_CONFIG 			((volatile unsigned short *)MDMA1_S1_CONFIG)
-#define pMDMA1_S1_X_COUNT 			((volatile unsigned short *)MDMA1_S1_X_COUNT)
-#define pMDMA1_S1_X_MODIFY 			((volatile signed   short *)MDMA1_S1_X_MODIFY)
-#define pMDMA1_S1_Y_COUNT 			((volatile unsigned short *)MDMA1_S1_Y_COUNT)
-#define pMDMA1_S1_Y_MODIFY 			((volatile signed   short *)MDMA1_S1_Y_MODIFY)
-#define pMDMA1_S1_CURR_DESC_PTR 	((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
-#define pMDMA1_S1_CURR_ADDR 		((void * volatile *)MDMA1_S1_CURR_ADDR)
-#define pMDMA1_S1_IRQ_STATUS 		((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
-#define pMDMA1_S1_PERIPHERAL_MAP	((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
-#define pMDMA1_S1_CURR_X_COUNT 		((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
-#define pMDMA1_S1_CURR_Y_COUNT 		((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
-
-
-/* Parallel Peripheral Interface (PPI) */
-#define pPPI_CONTROL 	((volatile unsigned short *)PPI_CONTROL)
-#define pPPI_STATUS 	((volatile unsigned short *)PPI_STATUS)
-#define pPPI_COUNT 		((volatile unsigned short *)PPI_COUNT)
-#define pPPI_DELAY 		((volatile unsigned short *)PPI_DELAY)
-#define pPPI_FRAME 		((volatile unsigned short *)PPI_FRAME)
-
-
-/* Media Transceiver (MXVR)		(0xFFC02700 - 0xFFC028FF) */
-#define pMXVR_CONFIG			((volatile unsigned short *)MXVR_CONFIG)
-#define pMXVR_PLL_CTL_0			((volatile unsigned long  *)MXVR_PLL_CTL_0)
-
-#define pMXVR_STATE_0			((volatile unsigned long  *)MXVR_STATE_0)
-#define pMXVR_STATE_1			((volatile unsigned long  *)MXVR_STATE_1)
-
-#define pMXVR_INT_STAT_0		((volatile unsigned long  *)MXVR_INT_STAT_0)
-#define pMXVR_INT_STAT_1		((volatile unsigned long  *)MXVR_INT_STAT_1)
-
-#define pMXVR_INT_EN_0			((volatile unsigned long  *)MXVR_INT_EN_0)
-#define pMXVR_INT_EN_1			((volatile unsigned long  *)MXVR_INT_EN_1)
-
-#define pMXVR_POSITION			((volatile unsigned short *)MXVR_POSITION)
-#define pMXVR_MAX_POSITION		((volatile unsigned short *)MXVR_MAX_POSITION)
-
-#define pMXVR_DELAY				((volatile unsigned short *)MXVR_DELAY)
-#define pMXVR_MAX_DELAY			((volatile unsigned short *)MXVR_MAX_DELAY)
-
-#define pMXVR_LADDR	 			((volatile unsigned long  *)MXVR_LADDR)
-#define pMXVR_GADDR				((volatile unsigned short *)MXVR_GADDR)
-#define pMXVR_AADDR				((volatile unsigned long  *)MXVR_AADDR)
-
-#define pMXVR_ALLOC_0			((volatile unsigned long  *)MXVR_ALLOC_0)
-#define pMXVR_ALLOC_1			((volatile unsigned long  *)MXVR_ALLOC_1)
-#define pMXVR_ALLOC_2			((volatile unsigned long  *)MXVR_ALLOC_2)
-#define pMXVR_ALLOC_3			((volatile unsigned long  *)MXVR_ALLOC_3)
-#define pMXVR_ALLOC_4			((volatile unsigned long  *)MXVR_ALLOC_4)
-#define pMXVR_ALLOC_5			((volatile unsigned long  *)MXVR_ALLOC_5)
-#define pMXVR_ALLOC_6			((volatile unsigned long  *)MXVR_ALLOC_6)
-#define pMXVR_ALLOC_7			((volatile unsigned long  *)MXVR_ALLOC_7)
-#define pMXVR_ALLOC_8			((volatile unsigned long  *)MXVR_ALLOC_8)
-#define pMXVR_ALLOC_9			((volatile unsigned long  *)MXVR_ALLOC_9)
-#define pMXVR_ALLOC_10			((volatile unsigned long  *)MXVR_ALLOC_10)
-#define pMXVR_ALLOC_11			((volatile unsigned long  *)MXVR_ALLOC_11)
-#define pMXVR_ALLOC_12			((volatile unsigned long  *)MXVR_ALLOC_12)
-#define pMXVR_ALLOC_13			((volatile unsigned long  *)MXVR_ALLOC_13)
-#define pMXVR_ALLOC_14			((volatile unsigned long  *)MXVR_ALLOC_14)
-
-#define pMXVR_SYNC_LCHAN_0		((volatile unsigned long  *)MXVR_SYNC_LCHAN_0)
-#define pMXVR_SYNC_LCHAN_1		((volatile unsigned long  *)MXVR_SYNC_LCHAN_1)
-#define pMXVR_SYNC_LCHAN_2		((volatile unsigned long  *)MXVR_SYNC_LCHAN_2)
-#define pMXVR_SYNC_LCHAN_3		((volatile unsigned long  *)MXVR_SYNC_LCHAN_3)
-#define pMXVR_SYNC_LCHAN_4		((volatile unsigned long  *)MXVR_SYNC_LCHAN_4)
-#define pMXVR_SYNC_LCHAN_5		((volatile unsigned long  *)MXVR_SYNC_LCHAN_5)
-#define pMXVR_SYNC_LCHAN_6		((volatile unsigned long  *)MXVR_SYNC_LCHAN_6)
-#define pMXVR_SYNC_LCHAN_7		((volatile unsigned long  *)MXVR_SYNC_LCHAN_7)
-
-#define pMXVR_DMA0_CONFIG		((volatile unsigned long  *)MXVR_DMA0_CONFIG)
-#define pMXVR_DMA0_START_ADDR	((void * volatile *)MXVR_DMA0_START_ADDR)
-#define pMXVR_DMA0_COUNT		((volatile unsigned short *)MXVR_DMA0_COUNT)
-#define pMXVR_DMA0_CURR_ADDR	((void * volatile *)MXVR_DMA0_CURR_ADDR)
-#define pMXVR_DMA0_CURR_COUNT	((volatile unsigned short *)MXVR_DMA0_CURR_COUNT)
-
-#define pMXVR_DMA1_CONFIG		((volatile unsigned long  *)MXVR_DMA1_CONFIG)
-#define pMXVR_DMA1_START_ADDR	((void * volatile *)MXVR_DMA1_START_ADDR)
-#define pMXVR_DMA1_COUNT		((volatile unsigned short *)MXVR_DMA1_COUNT)
-#define pMXVR_DMA1_CURR_ADDR	((void * volatile *)MXVR_DMA1_CURR_ADDR)
-#define pMXVR_DMA1_CURR_COUNT	((volatile unsigned short *)MXVR_DMA1_CURR_COUNT)
-
-#define pMXVR_DMA2_CONFIG		((volatile unsigned long  *)MXVR_DMA2_CONFIG)
-#define pMXVR_DMA2_START_ADDR	((void * volatile *)MXVR_DMA2_START_ADDR)
-#define pMXVR_DMA2_COUNT		((volatile unsigned short *)MXVR_DMA2_COUNT)
-#define pMXVR_DMA2_CURR_ADDR	((void * volatile *)MXVR_DMA2_CURR_ADDR)
-#define pMXVR_DMA2_CURR_COUNT	((volatile unsigned short *)MXVR_DMA2_CURR_COUNT)
-
-#define pMXVR_DMA3_CONFIG		((volatile unsigned long  *)MXVR_DMA3_CONFIG)
-#define pMXVR_DMA3_START_ADDR	((void * volatile *)MXVR_DMA3_START_ADDR)
-#define pMXVR_DMA3_COUNT		((volatile unsigned short *)MXVR_DMA3_COUNT)
-#define pMXVR_DMA3_CURR_ADDR	((void * volatile *)MXVR_DMA3_CURR_ADDR)
-#define pMXVR_DMA3_CURR_COUNT	((volatile unsigned short *)MXVR_DMA3_CURR_COUNT)
-
-#define pMXVR_DMA4_CONFIG		((volatile unsigned long  *)MXVR_DMA4_CONFIG)
-#define pMXVR_DMA4_START_ADDR	((void * volatile *)MXVR_DMA4_START_ADDR)
-#define pMXVR_DMA4_COUNT		((volatile unsigned short *)MXVR_DMA4_COUNT)
-#define pMXVR_DMA4_CURR_ADDR	((void * volatile *)MXVR_DMA4_CURR_ADDR)
-#define pMXVR_DMA4_CURR_COUNT	((volatile unsigned short *)MXVR_DMA4_CURR_COUNT)
-
-#define pMXVR_DMA5_CONFIG		((volatile unsigned long  *)MXVR_DMA5_CONFIG)
-#define pMXVR_DMA5_START_ADDR	((void * volatile *)MXVR_DMA5_START_ADDR)
-#define pMXVR_DMA5_COUNT		((volatile unsigned short *)MXVR_DMA5_COUNT)
-#define pMXVR_DMA5_CURR_ADDR	((void * volatile *)MXVR_DMA5_CURR_ADDR)
-#define pMXVR_DMA5_CURR_COUNT	((volatile unsigned short *)MXVR_DMA5_CURR_COUNT)
-
-#define pMXVR_DMA6_CONFIG		((volatile unsigned long  *)MXVR_DMA6_CONFIG)
-#define pMXVR_DMA6_START_ADDR	((void * volatile *)MXVR_DMA6_START_ADDR)
-#define pMXVR_DMA6_COUNT		((volatile unsigned short *)MXVR_DMA6_COUNT)
-#define pMXVR_DMA6_CURR_ADDR	((void * volatile *)MXVR_DMA6_CURR_ADDR)
-#define pMXVR_DMA6_CURR_COUNT	((volatile unsigned short *)MXVR_DMA6_CURR_COUNT)
-
-#define pMXVR_DMA7_CONFIG		((volatile unsigned long  *)MXVR_DMA7_CONFIG)
-#define pMXVR_DMA7_START_ADDR	((void * volatile *)MXVR_DMA7_START_ADDR)
-#define pMXVR_DMA7_COUNT		((volatile unsigned short *)MXVR_DMA7_COUNT)
-#define pMXVR_DMA7_CURR_ADDR	((void * volatile *)MXVR_DMA7_CURR_ADDR)
-#define pMXVR_DMA7_CURR_COUNT	((volatile unsigned short *)MXVR_DMA7_CURR_COUNT)
-
-#define pMXVR_AP_CTL			((volatile unsigned short *)MXVR_AP_CTL)
-#define pMXVR_APRB_START_ADDR	((void * volatile *)MXVR_APRB_START_ADDR)
-#define pMXVR_APRB_CURR_ADDR	((void * volatile *)MXVR_APRB_CURR_ADDR)
-#define pMXVR_APTB_START_ADDR	((void * volatile *)MXVR_APTB_START_ADDR)
-#define pMXVR_APTB_CURR_ADDR	((void * volatile *)MXVR_APTB_CURR_ADDR)
-
-#define pMXVR_CM_CTL			((volatile unsigned long  *)MXVR_CM_CTL)
-#define pMXVR_CMRB_START_ADDR	((void * volatile *)MXVR_CMRB_START_ADDR)
-#define pMXVR_CMRB_CURR_ADDR	((void * volatile *)MXVR_CMRB_CURR_ADDR)
-#define pMXVR_CMTB_START_ADDR	((void * volatile *)MXVR_CMTB_START_ADDR)
-#define pMXVR_CMTB_CURR_ADDR	((void * volatile *)MXVR_CMTB_CURR_ADDR)
-
-#define pMXVR_RRDB_START_ADDR	((void * volatile *)MXVR_RRDB_START_ADDR)
-#define pMXVR_RRDB_CURR_ADDR	((void * volatile *)MXVR_RRDB_CURR_ADDR)
-
-#define pMXVR_PAT_DATA_0		((volatile unsigned long  *)MXVR_PAT_DATA_0)
-#define pMXVR_PAT_EN_0			((volatile unsigned long  *)MXVR_PAT_EN_0)
-#define pMXVR_PAT_DATA_1		((volatile unsigned long  *)MXVR_PAT_DATA_1)
-#define pMXVR_PAT_EN_1			((volatile unsigned long  *)MXVR_PAT_EN_1)
-
-#define pMXVR_FRAME_CNT_0		((volatile unsigned short *)MXVR_FRAME_CNT_0)
-#define pMXVR_FRAME_CNT_1		((volatile unsigned short *)MXVR_FRAME_CNT_1)
-
-#define pMXVR_ROUTING_0			((volatile unsigned long  *)MXVR_ROUTING_0)
-#define pMXVR_ROUTING_1			((volatile unsigned long  *)MXVR_ROUTING_1)
-#define pMXVR_ROUTING_2			((volatile unsigned long  *)MXVR_ROUTING_2)
-#define pMXVR_ROUTING_3			((volatile unsigned long  *)MXVR_ROUTING_3)
-#define pMXVR_ROUTING_4			((volatile unsigned long  *)MXVR_ROUTING_4)
-#define pMXVR_ROUTING_5			((volatile unsigned long  *)MXVR_ROUTING_5)
-#define pMXVR_ROUTING_6			((volatile unsigned long  *)MXVR_ROUTING_6)
-#define pMXVR_ROUTING_7			((volatile unsigned long  *)MXVR_ROUTING_7)
-#define pMXVR_ROUTING_8			((volatile unsigned long  *)MXVR_ROUTING_8)
-#define pMXVR_ROUTING_9			((volatile unsigned long  *)MXVR_ROUTING_9)
-#define pMXVR_ROUTING_10		((volatile unsigned long  *)MXVR_ROUTING_10)
-#define pMXVR_ROUTING_11		((volatile unsigned long  *)MXVR_ROUTING_11)
-#define pMXVR_ROUTING_12		((volatile unsigned long  *)MXVR_ROUTING_12)
-#define pMXVR_ROUTING_13		((volatile unsigned long  *)MXVR_ROUTING_13)
-#define pMXVR_ROUTING_14		((volatile unsigned long  *)MXVR_ROUTING_14)
-
-#define pMXVR_PLL_CTL_1			((volatile unsigned long  *)MXVR_PLL_CTL_1)
-#define pMXVR_PLL_CTL_2			((volatile unsigned short *)MXVR_PLL_CTL_2)
-
-#define pMXVR_BLOCK_CNT			((volatile unsigned short *)MXVR_BLOCK_CNT)
-
-
-/* CAN Controller						*/
-/* For Mailboxes 0-15													*/
-#define pCAN_MC1			((volatile unsigned short *)CAN_MC1)
-#define pCAN_MD1			((volatile unsigned short *)CAN_MD1)
-#define pCAN_TRS1			((volatile unsigned short *)CAN_TRS1)
-#define pCAN_TRR1			((volatile unsigned short *)CAN_TRR1)
-#define pCAN_TA1			((volatile unsigned short *)CAN_TA1)
-#define pCAN_AA1			((volatile unsigned short *)CAN_AA1)
-#define pCAN_RMP1			((volatile unsigned short *)CAN_RMP1)
-#define pCAN_RML1			((volatile unsigned short *)CAN_RML1)
-#define pCAN_MBTIF1			((volatile unsigned short *)CAN_MBTIF1)
-#define pCAN_MBRIF1			((volatile unsigned short *)CAN_MBRIF1)
-#define pCAN_MBIM1			((volatile unsigned short *)CAN_MBIM1)
-#define pCAN_RFH1			((volatile unsigned short *)CAN_RFH1)
-#define pCAN_OPSS1			((volatile unsigned short *)CAN_OPSS1)
-
-/* For Mailboxes 16-31   												*/
-#define pCAN_MC2			((volatile unsigned short *)CAN_MC2)
-#define pCAN_MD2			((volatile unsigned short *)CAN_MD2)
-#define pCAN_TRS2			((volatile unsigned short *)CAN_TRS2)
-#define pCAN_TRR2			((volatile unsigned short *)CAN_TRR2)
-#define pCAN_TA2			((volatile unsigned short *)CAN_TA2)
-#define pCAN_AA2			((volatile unsigned short *)CAN_AA2)
-#define pCAN_RMP2			((volatile unsigned short *)CAN_RMP2)
-#define pCAN_RML2			((volatile unsigned short *)CAN_RML2)
-#define pCAN_MBTIF2			((volatile unsigned short *)CAN_MBTIF2)
-#define pCAN_MBRIF2			((volatile unsigned short *)CAN_MBRIF2)
-#define pCAN_MBIM2			((volatile unsigned short *)CAN_MBIM2)
-#define pCAN_RFH2			((volatile unsigned short *)CAN_RFH2)
-#define pCAN_OPSS2			((volatile unsigned short *)CAN_OPSS2)
-
-#define pCAN_CLOCK			((volatile unsigned short *)CAN_CLOCK)
-#define pCAN_TIMING			((volatile unsigned short *)CAN_TIMING)
-#define pCAN_DEBUG			((volatile unsigned short *)CAN_DEBUG)
-#define pCAN_STATUS			((volatile unsigned short *)CAN_STATUS)
-#define pCAN_CEC			((volatile unsigned short *)CAN_CEC)
-#define pCAN_GIS			((volatile unsigned short *)CAN_GIS)
-#define pCAN_GIM			((volatile unsigned short *)CAN_GIM)
-#define pCAN_GIF			((volatile unsigned short *)CAN_GIF)
-#define pCAN_CONTROL		((volatile unsigned short *)CAN_CONTROL)
-#define pCAN_INTR			((volatile unsigned short *)CAN_INTR)
-#define pCAN_MBTD			((volatile unsigned short *)CAN_MBTD)
-#define pCAN_EWR			((volatile unsigned short *)CAN_EWR)
-#define pCAN_ESR			((volatile unsigned short *)CAN_ESR)
-#define pCAN_UCCNT			((volatile unsigned short *)CAN_UCCNT)
-#define pCAN_UCRC			((volatile unsigned short *)CAN_UCRC)
-#define pCAN_UCCNF			((volatile unsigned short *)CAN_UCCNF)
-
-/* Mailbox Acceptance Masks 											*/
-#define pCAN_AM00L			((volatile unsigned short *)CAN_AM00L)
-#define pCAN_AM00H			((volatile unsigned short *)CAN_AM00H)
-#define pCAN_AM01L			((volatile unsigned short *)CAN_AM01L)
-#define pCAN_AM01H			((volatile unsigned short *)CAN_AM01H)
-#define pCAN_AM02L			((volatile unsigned short *)CAN_AM02L)
-#define pCAN_AM02H			((volatile unsigned short *)CAN_AM02H)
-#define pCAN_AM03L			((volatile unsigned short *)CAN_AM03L)
-#define pCAN_AM03H			((volatile unsigned short *)CAN_AM03H)
-#define pCAN_AM04L			((volatile unsigned short *)CAN_AM04L)
-#define pCAN_AM04H			((volatile unsigned short *)CAN_AM04H)
-#define pCAN_AM05L			((volatile unsigned short *)CAN_AM05L)
-#define pCAN_AM05H			((volatile unsigned short *)CAN_AM05H)
-#define pCAN_AM06L			((volatile unsigned short *)CAN_AM06L)
-#define pCAN_AM06H			((volatile unsigned short *)CAN_AM06H)
-#define pCAN_AM07L			((volatile unsigned short *)CAN_AM07L)
-#define pCAN_AM07H			((volatile unsigned short *)CAN_AM07H)
-#define pCAN_AM08L			((volatile unsigned short *)CAN_AM08L)
-#define pCAN_AM08H			((volatile unsigned short *)CAN_AM08H)
-#define pCAN_AM09L			((volatile unsigned short *)CAN_AM09L)
-#define pCAN_AM09H			((volatile unsigned short *)CAN_AM09H)
-#define pCAN_AM10L			((volatile unsigned short *)CAN_AM10L)
-#define pCAN_AM10H			((volatile unsigned short *)CAN_AM10H)
-#define pCAN_AM11L			((volatile unsigned short *)CAN_AM11L)
-#define pCAN_AM11H			((volatile unsigned short *)CAN_AM11H)
-#define pCAN_AM12L			((volatile unsigned short *)CAN_AM12L)
-#define pCAN_AM12H			((volatile unsigned short *)CAN_AM12H)
-#define pCAN_AM13L			((volatile unsigned short *)CAN_AM13L)
-#define pCAN_AM13H			((volatile unsigned short *)CAN_AM13H)
-#define pCAN_AM14L			((volatile unsigned short *)CAN_AM14L)
-#define pCAN_AM14H			((volatile unsigned short *)CAN_AM14H)
-#define pCAN_AM15L			((volatile unsigned short *)CAN_AM15L)
-#define pCAN_AM15H			((volatile unsigned short *)CAN_AM15H)
-
-#define pCAN_AM16L			((volatile unsigned short *)CAN_AM16L)
-#define pCAN_AM16H			((volatile unsigned short *)CAN_AM16H)
-#define pCAN_AM17L			((volatile unsigned short *)CAN_AM17L)
-#define pCAN_AM17H			((volatile unsigned short *)CAN_AM17H)
-#define pCAN_AM18L			((volatile unsigned short *)CAN_AM18L)
-#define pCAN_AM18H			((volatile unsigned short *)CAN_AM18H)
-#define pCAN_AM19L			((volatile unsigned short *)CAN_AM19L)
-#define pCAN_AM19H			((volatile unsigned short *)CAN_AM19H)
-#define pCAN_AM20L			((volatile unsigned short *)CAN_AM20L)
-#define pCAN_AM20H			((volatile unsigned short *)CAN_AM20H)
-#define pCAN_AM21L			((volatile unsigned short *)CAN_AM21L)
-#define pCAN_AM21H			((volatile unsigned short *)CAN_AM21H)
-#define pCAN_AM22L			((volatile unsigned short *)CAN_AM22L)
-#define pCAN_AM22H			((volatile unsigned short *)CAN_AM22H)
-#define pCAN_AM23L			((volatile unsigned short *)CAN_AM23L)
-#define pCAN_AM23H			((volatile unsigned short *)CAN_AM23H)
-#define pCAN_AM24L			((volatile unsigned short *)CAN_AM24L)
-#define pCAN_AM24H			((volatile unsigned short *)CAN_AM24H)
-#define pCAN_AM25L			((volatile unsigned short *)CAN_AM25L)
-#define pCAN_AM25H			((volatile unsigned short *)CAN_AM25H)
-#define pCAN_AM26L			((volatile unsigned short *)CAN_AM26L)
-#define pCAN_AM26H			((volatile unsigned short *)CAN_AM26H)
-#define pCAN_AM27L			((volatile unsigned short *)CAN_AM27L)
-#define pCAN_AM27H			((volatile unsigned short *)CAN_AM27H)
-#define pCAN_AM28L			((volatile unsigned short *)CAN_AM28L)
-#define pCAN_AM28H			((volatile unsigned short *)CAN_AM28H)
-#define pCAN_AM29L			((volatile unsigned short *)CAN_AM29L)
-#define pCAN_AM29H			((volatile unsigned short *)CAN_AM29H)
-#define pCAN_AM30L			((volatile unsigned short *)CAN_AM30L)
-#define pCAN_AM30H			((volatile unsigned short *)CAN_AM30H)
-#define pCAN_AM31L			((volatile unsigned short *)CAN_AM31L)
-#define pCAN_AM31H			((volatile unsigned short *)CAN_AM31H)
-
-/* CAN Acceptance Mask Area Macros	*/
-#define pCAN_AM_L(x)		((volatile unsigned short *)CAN_AM_L(x))
-#define pCAN_AM_H(x)		((volatile unsigned short *)CAN_AM_H(x))
-
-/* Mailbox Registers														*/
-#define pCAN_MB00_DATA0		((volatile unsigned short *)CAN_MB00_DATA0)
-#define pCAN_MB00_DATA1		((volatile unsigned short *)CAN_MB00_DATA1)
-#define pCAN_MB00_DATA2		((volatile unsigned short *)CAN_MB00_DATA2)
-#define pCAN_MB00_DATA3		((volatile unsigned short *)CAN_MB00_DATA3)
-#define pCAN_MB00_LENGTH	((volatile unsigned short *)CAN_MB00_LENGTH)
-#define pCAN_MB00_TIMESTAMP	((volatile unsigned short *)CAN_MB00_TIMESTAMP)
-#define pCAN_MB00_ID0		((volatile unsigned short *)CAN_MB00_ID0)
-#define pCAN_MB00_ID1		((volatile unsigned short *)CAN_MB00_ID1)
-
-#define pCAN_MB01_DATA0		((volatile unsigned short *)CAN_MB01_DATA0)
-#define pCAN_MB01_DATA1		((volatile unsigned short *)CAN_MB01_DATA1)
-#define pCAN_MB01_DATA2		((volatile unsigned short *)CAN_MB01_DATA2)
-#define pCAN_MB01_DATA3		((volatile unsigned short *)CAN_MB01_DATA3)
-#define pCAN_MB01_LENGTH	((volatile unsigned short *)CAN_MB01_LENGTH)
-#define pCAN_MB01_TIMESTAMP	((volatile unsigned short *)CAN_MB01_TIMESTAMP)
-#define pCAN_MB01_ID0		((volatile unsigned short *)CAN_MB01_ID0)
-#define pCAN_MB01_ID1		((volatile unsigned short *)CAN_MB01_ID1)
-
-#define pCAN_MB02_DATA0		((volatile unsigned short *)CAN_MB02_DATA0)
-#define pCAN_MB02_DATA1		((volatile unsigned short *)CAN_MB02_DATA1)
-#define pCAN_MB02_DATA2		((volatile unsigned short *)CAN_MB02_DATA2)
-#define pCAN_MB02_DATA3		((volatile unsigned short *)CAN_MB02_DATA3)
-#define pCAN_MB02_LENGTH	((volatile unsigned short *)CAN_MB02_LENGTH)
-#define pCAN_MB02_TIMESTAMP	((volatile unsigned short *)CAN_MB02_TIMESTAMP)
-#define pCAN_MB02_ID0		((volatile unsigned short *)CAN_MB02_ID0)
-#define pCAN_MB02_ID1		((volatile unsigned short *)CAN_MB02_ID1)
-
-#define pCAN_MB03_DATA0		((volatile unsigned short *)CAN_MB03_DATA0)
-#define pCAN_MB03_DATA1		((volatile unsigned short *)CAN_MB03_DATA1)
-#define pCAN_MB03_DATA2		((volatile unsigned short *)CAN_MB03_DATA2)
-#define pCAN_MB03_DATA3		((volatile unsigned short *)CAN_MB03_DATA3)
-#define pCAN_MB03_LENGTH	((volatile unsigned short *)CAN_MB03_LENGTH)
-#define pCAN_MB03_TIMESTAMP	((volatile unsigned short *)CAN_MB03_TIMESTAMP)
-#define pCAN_MB03_ID0		((volatile unsigned short *)CAN_MB03_ID0)
-#define pCAN_MB03_ID1		((volatile unsigned short *)CAN_MB03_ID1)
-
-#define pCAN_MB04_DATA0		((volatile unsigned short *)CAN_MB04_DATA0)
-#define pCAN_MB04_DATA1		((volatile unsigned short *)CAN_MB04_DATA1)
-#define pCAN_MB04_DATA2		((volatile unsigned short *)CAN_MB04_DATA2)
-#define pCAN_MB04_DATA3		((volatile unsigned short *)CAN_MB04_DATA3)
-#define pCAN_MB04_LENGTH	((volatile unsigned short *)CAN_MB04_LENGTH)
-#define pCAN_MB04_TIMESTAMP	((volatile unsigned short *)CAN_MB04_TIMESTAMP)
-#define pCAN_MB04_ID0		((volatile unsigned short *)CAN_MB04_ID0)
-#define pCAN_MB04_ID1		((volatile unsigned short *)CAN_MB04_ID1)
-
-#define pCAN_MB05_DATA0		((volatile unsigned short *)CAN_MB05_DATA0)
-#define pCAN_MB05_DATA1		((volatile unsigned short *)CAN_MB05_DATA1)
-#define pCAN_MB05_DATA2		((volatile unsigned short *)CAN_MB05_DATA2)
-#define pCAN_MB05_DATA3		((volatile unsigned short *)CAN_MB05_DATA3)
-#define pCAN_MB05_LENGTH	((volatile unsigned short *)CAN_MB05_LENGTH)
-#define pCAN_MB05_TIMESTAMP	((volatile unsigned short *)CAN_MB05_TIMESTAMP)
-#define pCAN_MB05_ID0		((volatile unsigned short *)CAN_MB05_ID0)
-#define pCAN_MB05_ID1		((volatile unsigned short *)CAN_MB05_ID1)
-
-#define pCAN_MB06_DATA0		((volatile unsigned short *)CAN_MB06_DATA0)
-#define pCAN_MB06_DATA1		((volatile unsigned short *)CAN_MB06_DATA1)
-#define pCAN_MB06_DATA2		((volatile unsigned short *)CAN_MB06_DATA2)
-#define pCAN_MB06_DATA3		((volatile unsigned short *)CAN_MB06_DATA3)
-#define pCAN_MB06_LENGTH	((volatile unsigned short *)CAN_MB06_LENGTH)
-#define pCAN_MB06_TIMESTAMP	((volatile unsigned short *)CAN_MB06_TIMESTAMP)
-#define pCAN_MB06_ID0		((volatile unsigned short *)CAN_MB06_ID0)
-#define pCAN_MB06_ID1		((volatile unsigned short *)CAN_MB06_ID1)
-
-#define pCAN_MB07_DATA0		((volatile unsigned short *)CAN_MB07_DATA0)
-#define pCAN_MB07_DATA1		((volatile unsigned short *)CAN_MB07_DATA1)
-#define pCAN_MB07_DATA2		((volatile unsigned short *)CAN_MB07_DATA2)
-#define pCAN_MB07_DATA3		((volatile unsigned short *)CAN_MB07_DATA3)
-#define pCAN_MB07_LENGTH	((volatile unsigned short *)CAN_MB07_LENGTH)
-#define pCAN_MB07_TIMESTAMP	((volatile unsigned short *)CAN_MB07_TIMESTAMP)
-#define pCAN_MB07_ID0		((volatile unsigned short *)CAN_MB07_ID0)
-#define pCAN_MB07_ID1		((volatile unsigned short *)CAN_MB07_ID1)
-
-#define pCAN_MB08_DATA0		((volatile unsigned short *)CAN_MB08_DATA0)
-#define pCAN_MB08_DATA1		((volatile unsigned short *)CAN_MB08_DATA1)
-#define pCAN_MB08_DATA2		((volatile unsigned short *)CAN_MB08_DATA2)
-#define pCAN_MB08_DATA3		((volatile unsigned short *)CAN_MB08_DATA3)
-#define pCAN_MB08_LENGTH	((volatile unsigned short *)CAN_MB08_LENGTH)
-#define pCAN_MB08_TIMESTAMP	((volatile unsigned short *)CAN_MB08_TIMESTAMP)
-#define pCAN_MB08_ID0		((volatile unsigned short *)CAN_MB08_ID0)
-#define pCAN_MB08_ID1		((volatile unsigned short *)CAN_MB08_ID1)
-
-#define pCAN_MB09_DATA0		((volatile unsigned short *)CAN_MB09_DATA0)
-#define pCAN_MB09_DATA1		((volatile unsigned short *)CAN_MB09_DATA1)
-#define pCAN_MB09_DATA2		((volatile unsigned short *)CAN_MB09_DATA2)
-#define pCAN_MB09_DATA3		((volatile unsigned short *)CAN_MB09_DATA3)
-#define pCAN_MB09_LENGTH	((volatile unsigned short *)CAN_MB09_LENGTH)
-#define pCAN_MB09_TIMESTAMP	((volatile unsigned short *)CAN_MB09_TIMESTAMP)
-#define pCAN_MB09_ID0		((volatile unsigned short *)CAN_MB09_ID0)
-#define pCAN_MB09_ID1		((volatile unsigned short *)CAN_MB09_ID1)
-
-#define pCAN_MB10_DATA0		((volatile unsigned short *)CAN_MB10_DATA0)
-#define pCAN_MB10_DATA1		((volatile unsigned short *)CAN_MB10_DATA1)
-#define pCAN_MB10_DATA2		((volatile unsigned short *)CAN_MB10_DATA2)
-#define pCAN_MB10_DATA3		((volatile unsigned short *)CAN_MB10_DATA3)
-#define pCAN_MB10_LENGTH	((volatile unsigned short *)CAN_MB10_LENGTH)
-#define pCAN_MB10_TIMESTAMP	((volatile unsigned short *)CAN_MB10_TIMESTAMP)
-#define pCAN_MB10_ID0		((volatile unsigned short *)CAN_MB10_ID0)
-#define pCAN_MB10_ID1		((volatile unsigned short *)CAN_MB10_ID1)
-
-#define pCAN_MB11_DATA0		((volatile unsigned short *)CAN_MB11_DATA0)
-#define pCAN_MB11_DATA1		((volatile unsigned short *)CAN_MB11_DATA1)
-#define pCAN_MB11_DATA2		((volatile unsigned short *)CAN_MB11_DATA2)
-#define pCAN_MB11_DATA3		((volatile unsigned short *)CAN_MB11_DATA3)
-#define pCAN_MB11_LENGTH	((volatile unsigned short *)CAN_MB11_LENGTH)
-#define pCAN_MB11_TIMESTAMP	((volatile unsigned short *)CAN_MB11_TIMESTAMP)
-#define pCAN_MB11_ID0		((volatile unsigned short *)CAN_MB11_ID0)
-#define pCAN_MB11_ID1		((volatile unsigned short *)CAN_MB11_ID1)
-
-#define pCAN_MB12_DATA0		((volatile unsigned short *)CAN_MB12_DATA0)
-#define pCAN_MB12_DATA1		((volatile unsigned short *)CAN_MB12_DATA1)
-#define pCAN_MB12_DATA2		((volatile unsigned short *)CAN_MB12_DATA2)
-#define pCAN_MB12_DATA3		((volatile unsigned short *)CAN_MB12_DATA3)
-#define pCAN_MB12_LENGTH	((volatile unsigned short *)CAN_MB12_LENGTH)
-#define pCAN_MB12_TIMESTAMP	((volatile unsigned short *)CAN_MB12_TIMESTAMP)
-#define pCAN_MB12_ID0		((volatile unsigned short *)CAN_MB12_ID0)
-#define pCAN_MB12_ID1		((volatile unsigned short *)CAN_MB12_ID1)
-
-#define pCAN_MB13_DATA0		((volatile unsigned short *)CAN_MB13_DATA0)
-#define pCAN_MB13_DATA1		((volatile unsigned short *)CAN_MB13_DATA1)
-#define pCAN_MB13_DATA2		((volatile unsigned short *)CAN_MB13_DATA2)
-#define pCAN_MB13_DATA3		((volatile unsigned short *)CAN_MB13_DATA3)
-#define pCAN_MB13_LENGTH	((volatile unsigned short *)CAN_MB13_LENGTH)
-#define pCAN_MB13_TIMESTAMP	((volatile unsigned short *)CAN_MB13_TIMESTAMP)
-#define pCAN_MB13_ID0		((volatile unsigned short *)CAN_MB13_ID0)
-#define pCAN_MB13_ID1		((volatile unsigned short *)CAN_MB13_ID1)
-
-#define pCAN_MB14_DATA0		((volatile unsigned short *)CAN_MB14_DATA0)
-#define pCAN_MB14_DATA1		((volatile unsigned short *)CAN_MB14_DATA1)
-#define pCAN_MB14_DATA2		((volatile unsigned short *)CAN_MB14_DATA2)
-#define pCAN_MB14_DATA3		((volatile unsigned short *)CAN_MB14_DATA3)
-#define pCAN_MB14_LENGTH	((volatile unsigned short *)CAN_MB14_LENGTH)
-#define pCAN_MB14_TIMESTAMP	((volatile unsigned short *)CAN_MB14_TIMESTAMP)
-#define pCAN_MB14_ID0		((volatile unsigned short *)CAN_MB14_ID0)
-#define pCAN_MB14_ID1		((volatile unsigned short *)CAN_MB14_ID1)
-
-#define pCAN_MB15_DATA0		((volatile unsigned short *)CAN_MB15_DATA0)
-#define pCAN_MB15_DATA1		((volatile unsigned short *)CAN_MB15_DATA1)
-#define pCAN_MB15_DATA2		((volatile unsigned short *)CAN_MB15_DATA2)
-#define pCAN_MB15_DATA3		((volatile unsigned short *)CAN_MB15_DATA3)
-#define pCAN_MB15_LENGTH	((volatile unsigned short *)CAN_MB15_LENGTH)
-#define pCAN_MB15_TIMESTAMP	((volatile unsigned short *)CAN_MB15_TIMESTAMP)
-#define pCAN_MB15_ID0		((volatile unsigned short *)CAN_MB15_ID0)
-#define pCAN_MB15_ID1		((volatile unsigned short *)CAN_MB15_ID1)
-
-#define pCAN_MB16_DATA0		((volatile unsigned short *)CAN_MB16_DATA0)
-#define pCAN_MB16_DATA1		((volatile unsigned short *)CAN_MB16_DATA1)
-#define pCAN_MB16_DATA2		((volatile unsigned short *)CAN_MB16_DATA2)
-#define pCAN_MB16_DATA3		((volatile unsigned short *)CAN_MB16_DATA3)
-#define pCAN_MB16_LENGTH	((volatile unsigned short *)CAN_MB16_LENGTH)
-#define pCAN_MB16_TIMESTAMP	((volatile unsigned short *)CAN_MB16_TIMESTAMP)
-#define pCAN_MB16_ID0		((volatile unsigned short *)CAN_MB16_ID0)
-#define pCAN_MB16_ID1		((volatile unsigned short *)CAN_MB16_ID1)
-
-#define pCAN_MB17_DATA0		((volatile unsigned short *)CAN_MB17_DATA0)
-#define pCAN_MB17_DATA1		((volatile unsigned short *)CAN_MB17_DATA1)
-#define pCAN_MB17_DATA2		((volatile unsigned short *)CAN_MB17_DATA2)
-#define pCAN_MB17_DATA3		((volatile unsigned short *)CAN_MB17_DATA3)
-#define pCAN_MB17_LENGTH	((volatile unsigned short *)CAN_MB17_LENGTH)
-#define pCAN_MB17_TIMESTAMP	((volatile unsigned short *)CAN_MB17_TIMESTAMP)
-#define pCAN_MB17_ID0		((volatile unsigned short *)CAN_MB17_ID0)
-#define pCAN_MB17_ID1		((volatile unsigned short *)CAN_MB17_ID1)
-
-#define pCAN_MB18_DATA0		((volatile unsigned short *)CAN_MB18_DATA0)
-#define pCAN_MB18_DATA1		((volatile unsigned short *)CAN_MB18_DATA1)
-#define pCAN_MB18_DATA2		((volatile unsigned short *)CAN_MB18_DATA2)
-#define pCAN_MB18_DATA3		((volatile unsigned short *)CAN_MB18_DATA3)
-#define pCAN_MB18_LENGTH	((volatile unsigned short *)CAN_MB18_LENGTH)
-#define pCAN_MB18_TIMESTAMP	((volatile unsigned short *)CAN_MB18_TIMESTAMP)
-#define pCAN_MB18_ID0		((volatile unsigned short *)CAN_MB18_ID0)
-#define pCAN_MB18_ID1		((volatile unsigned short *)CAN_MB18_ID1)
-
-#define pCAN_MB19_DATA0		((volatile unsigned short *)CAN_MB19_DATA0)
-#define pCAN_MB19_DATA1		((volatile unsigned short *)CAN_MB19_DATA1)
-#define pCAN_MB19_DATA2		((volatile unsigned short *)CAN_MB19_DATA2)
-#define pCAN_MB19_DATA3		((volatile unsigned short *)CAN_MB19_DATA3)
-#define pCAN_MB19_LENGTH	((volatile unsigned short *)CAN_MB19_LENGTH)
-#define pCAN_MB19_TIMESTAMP	((volatile unsigned short *)CAN_MB19_TIMESTAMP)
-#define pCAN_MB19_ID0		((volatile unsigned short *)CAN_MB19_ID0)
-#define pCAN_MB19_ID1		((volatile unsigned short *)CAN_MB19_ID1)
-
-#define pCAN_MB20_DATA0		((volatile unsigned short *)CAN_MB20_DATA0)
-#define pCAN_MB20_DATA1		((volatile unsigned short *)CAN_MB20_DATA1)
-#define pCAN_MB20_DATA2		((volatile unsigned short *)CAN_MB20_DATA2)
-#define pCAN_MB20_DATA3		((volatile unsigned short *)CAN_MB20_DATA3)
-#define pCAN_MB20_LENGTH	((volatile unsigned short *)CAN_MB20_LENGTH)
-#define pCAN_MB20_TIMESTAMP	((volatile unsigned short *)CAN_MB20_TIMESTAMP)
-#define pCAN_MB20_ID0		((volatile unsigned short *)CAN_MB20_ID0)
-#define pCAN_MB20_ID1		((volatile unsigned short *)CAN_MB20_ID1)
-
-#define pCAN_MB21_DATA0		((volatile unsigned short *)CAN_MB21_DATA0)
-#define pCAN_MB21_DATA1		((volatile unsigned short *)CAN_MB21_DATA1)
-#define pCAN_MB21_DATA2		((volatile unsigned short *)CAN_MB21_DATA2)
-#define pCAN_MB21_DATA3		((volatile unsigned short *)CAN_MB21_DATA3)
-#define pCAN_MB21_LENGTH	((volatile unsigned short *)CAN_MB21_LENGTH)
-#define pCAN_MB21_TIMESTAMP	((volatile unsigned short *)CAN_MB21_TIMESTAMP)
-#define pCAN_MB21_ID0		((volatile unsigned short *)CAN_MB21_ID0)
-#define pCAN_MB21_ID1		((volatile unsigned short *)CAN_MB21_ID1)
-
-#define pCAN_MB22_DATA0		((volatile unsigned short *)CAN_MB22_DATA0)
-#define pCAN_MB22_DATA1		((volatile unsigned short *)CAN_MB22_DATA1)
-#define pCAN_MB22_DATA2		((volatile unsigned short *)CAN_MB22_DATA2)
-#define pCAN_MB22_DATA3		((volatile unsigned short *)CAN_MB22_DATA3)
-#define pCAN_MB22_LENGTH	((volatile unsigned short *)CAN_MB22_LENGTH)
-#define pCAN_MB22_TIMESTAMP	((volatile unsigned short *)CAN_MB22_TIMESTAMP)
-#define pCAN_MB22_ID0		((volatile unsigned short *)CAN_MB22_ID0)
-#define pCAN_MB22_ID1		((volatile unsigned short *)CAN_MB22_ID1)
-
-#define pCAN_MB23_DATA0		((volatile unsigned short *)CAN_MB23_DATA0)
-#define pCAN_MB23_DATA1		((volatile unsigned short *)CAN_MB23_DATA1)
-#define pCAN_MB23_DATA2		((volatile unsigned short *)CAN_MB23_DATA2)
-#define pCAN_MB23_DATA3		((volatile unsigned short *)CAN_MB23_DATA3)
-#define pCAN_MB23_LENGTH	((volatile unsigned short *)CAN_MB23_LENGTH)
-#define pCAN_MB23_TIMESTAMP	((volatile unsigned short *)CAN_MB23_TIMESTAMP)
-#define pCAN_MB23_ID0		((volatile unsigned short *)CAN_MB23_ID0)
-#define pCAN_MB23_ID1		((volatile unsigned short *)CAN_MB23_ID1)
-
-#define pCAN_MB24_DATA0		((volatile unsigned short *)CAN_MB24_DATA0)
-#define pCAN_MB24_DATA1		((volatile unsigned short *)CAN_MB24_DATA1)
-#define pCAN_MB24_DATA2		((volatile unsigned short *)CAN_MB24_DATA2)
-#define pCAN_MB24_DATA3		((volatile unsigned short *)CAN_MB24_DATA3)
-#define pCAN_MB24_LENGTH	((volatile unsigned short *)CAN_MB24_LENGTH)
-#define pCAN_MB24_TIMESTAMP	((volatile unsigned short *)CAN_MB24_TIMESTAMP)
-#define pCAN_MB24_ID0		((volatile unsigned short *)CAN_MB24_ID0)
-#define pCAN_MB24_ID1		((volatile unsigned short *)CAN_MB24_ID1)
-
-#define pCAN_MB25_DATA0		((volatile unsigned short *)CAN_MB25_DATA0)
-#define pCAN_MB25_DATA1		((volatile unsigned short *)CAN_MB25_DATA1)
-#define pCAN_MB25_DATA2		((volatile unsigned short *)CAN_MB25_DATA2)
-#define pCAN_MB25_DATA3		((volatile unsigned short *)CAN_MB25_DATA3)
-#define pCAN_MB25_LENGTH	((volatile unsigned short *)CAN_MB25_LENGTH)
-#define pCAN_MB25_TIMESTAMP	((volatile unsigned short *)CAN_MB25_TIMESTAMP)
-#define pCAN_MB25_ID0		((volatile unsigned short *)CAN_MB25_ID0)
-#define pCAN_MB25_ID1		((volatile unsigned short *)CAN_MB25_ID1)
-
-#define pCAN_MB26_DATA0		((volatile unsigned short *)CAN_MB26_DATA0)
-#define pCAN_MB26_DATA1		((volatile unsigned short *)CAN_MB26_DATA1)
-#define pCAN_MB26_DATA2		((volatile unsigned short *)CAN_MB26_DATA2)
-#define pCAN_MB26_DATA3		((volatile unsigned short *)CAN_MB26_DATA3)
-#define pCAN_MB26_LENGTH	((volatile unsigned short *)CAN_MB26_LENGTH)
-#define pCAN_MB26_TIMESTAMP	((volatile unsigned short *)CAN_MB26_TIMESTAMP)
-#define pCAN_MB26_ID0		((volatile unsigned short *)CAN_MB26_ID0)
-#define pCAN_MB26_ID1		((volatile unsigned short *)CAN_MB26_ID1)
-
-#define pCAN_MB27_DATA0		((volatile unsigned short *)CAN_MB27_DATA0)
-#define pCAN_MB27_DATA1		((volatile unsigned short *)CAN_MB27_DATA1)
-#define pCAN_MB27_DATA2		((volatile unsigned short *)CAN_MB27_DATA2)
-#define pCAN_MB27_DATA3		((volatile unsigned short *)CAN_MB27_DATA3)
-#define pCAN_MB27_LENGTH	((volatile unsigned short *)CAN_MB27_LENGTH)
-#define pCAN_MB27_TIMESTAMP	((volatile unsigned short *)CAN_MB27_TIMESTAMP)
-#define pCAN_MB27_ID0		((volatile unsigned short *)CAN_MB27_ID0)
-#define pCAN_MB27_ID1		((volatile unsigned short *)CAN_MB27_ID1)
-
-#define pCAN_MB28_DATA0		((volatile unsigned short *)CAN_MB28_DATA0)
-#define pCAN_MB28_DATA1		((volatile unsigned short *)CAN_MB28_DATA1)
-#define pCAN_MB28_DATA2		((volatile unsigned short *)CAN_MB28_DATA2)
-#define pCAN_MB28_DATA3		((volatile unsigned short *)CAN_MB28_DATA3)
-#define pCAN_MB28_LENGTH	((volatile unsigned short *)CAN_MB28_LENGTH)
-#define pCAN_MB28_TIMESTAMP	((volatile unsigned short *)CAN_MB28_TIMESTAMP)
-#define pCAN_MB28_ID0		((volatile unsigned short *)CAN_MB28_ID0)
-#define pCAN_MB28_ID1		((volatile unsigned short *)CAN_MB28_ID1)
-
-#define pCAN_MB29_DATA0		((volatile unsigned short *)CAN_MB29_DATA0)
-#define pCAN_MB29_DATA1		((volatile unsigned short *)CAN_MB29_DATA1)
-#define pCAN_MB29_DATA2		((volatile unsigned short *)CAN_MB29_DATA2)
-#define pCAN_MB29_DATA3		((volatile unsigned short *)CAN_MB29_DATA3)
-#define pCAN_MB29_LENGTH	((volatile unsigned short *)CAN_MB29_LENGTH)
-#define pCAN_MB29_TIMESTAMP	((volatile unsigned short *)CAN_MB29_TIMESTAMP)
-#define pCAN_MB29_ID0		((volatile unsigned short *)CAN_MB29_ID0)
-#define pCAN_MB29_ID1		((volatile unsigned short *)CAN_MB29_ID1)
-
-#define pCAN_MB30_DATA0		((volatile unsigned short *)CAN_MB30_DATA0)
-#define pCAN_MB30_DATA1		((volatile unsigned short *)CAN_MB30_DATA1)
-#define pCAN_MB30_DATA2		((volatile unsigned short *)CAN_MB30_DATA2)
-#define pCAN_MB30_DATA3		((volatile unsigned short *)CAN_MB30_DATA3)
-#define pCAN_MB30_LENGTH	((volatile unsigned short *)CAN_MB30_LENGTH)
-#define pCAN_MB30_TIMESTAMP	((volatile unsigned short *)CAN_MB30_TIMESTAMP)
-#define pCAN_MB30_ID0		((volatile unsigned short *)CAN_MB30_ID0)
-#define pCAN_MB30_ID1		((volatile unsigned short *)CAN_MB30_ID1)
-
-#define pCAN_MB31_DATA0		((volatile unsigned short *)CAN_MB31_DATA0)
-#define pCAN_MB31_DATA1		((volatile unsigned short *)CAN_MB31_DATA1)
-#define pCAN_MB31_DATA2		((volatile unsigned short *)CAN_MB31_DATA2)
-#define pCAN_MB31_DATA3		((volatile unsigned short *)CAN_MB31_DATA3)
-#define pCAN_MB31_LENGTH	((volatile unsigned short *)CAN_MB31_LENGTH)
-#define pCAN_MB31_TIMESTAMP	((volatile unsigned short *)CAN_MB31_TIMESTAMP)
-#define pCAN_MB31_ID0		((volatile unsigned short *)CAN_MB31_ID0)
-#define pCAN_MB31_ID1		((volatile unsigned short *)CAN_MB31_ID1)
-
-
-/* CAN Mailbox Area Macros		*/
-#define pCAN_MB_ID1(x)			((volatile unsigned short *)CAN_MB_ID1(x))
-#define pCAN_MB_ID0(x)			((volatile unsigned short *)CAN_MB_ID0(x))
-#define pCAN_MB_TIMESTAMP(x)	((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
-#define pCAN_MB_LENGTH(x)		((volatile unsigned short *)CAN_MB_LENGTH(x))
-#define pCAN_MB_DATA3(x)		((volatile unsigned short *)CAN_MB_DATA3(x))
-#define pCAN_MB_DATA2(x)		((volatile unsigned short *)CAN_MB_DATA2(x))
-#define pCAN_MB_DATA1(x)		((volatile unsigned short *)CAN_MB_DATA1(x))
-#define pCAN_MB_DATA0(x)		((volatile unsigned short *)CAN_MB_DATA0(x))
-
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define pCAN_CNF         	pCAN_DEBUG
-#define pTWI0_PRESCALE   	pTWI0_CONTROL
-#define pTWI0_INT_SRC	 	pTWI0_INT_STAT
-#define pTWI0_INT_ENABLE 	pTWI0_INT_MASK
-#define pTWI1_PRESCALE		pTWI1_CONTROL
-#define pTWI1_INT_SRC		pTWI1_INT_STAT
-#define pTWI1_INT_ENABLE	pTWI1_INT_MASK
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF539_H */
-
diff --git a/libgloss/bfin/include/cdefBF53x.h b/libgloss/bfin/include/cdefBF53x.h
deleted file mode 100644
index f147a5d2c..000000000
--- a/libgloss/bfin/include/cdefBF53x.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF53x.h
- *
- * (c) Copyright 2002-2006 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEFBF53x_H
-#define _CDEFBF53x_H
-
-#include <sys/platform.h>
-
-#endif /* _CDEFBF53x_H */
diff --git a/libgloss/bfin/include/cdefBF542.h b/libgloss/bfin/include/cdefBF542.h
deleted file mode 100644
index 5e111918d..000000000
--- a/libgloss/bfin/include/cdefBF542.h
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF542.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF542 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include all Core registers and bit definitions */
-#include <defBF542.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <cdefBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define                    pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
-#define                     pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
-#define                   pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
-#define                  pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
-#define                  pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
-#define                   pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
-#define                 pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
-#define                   pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
-#define                pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
-#define                   pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
-#define                  pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
-#define                 pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
-#define                 pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
-#define               pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
-#define             pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
-#define                  pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
-#define                  pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
-#define                  pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
-#define                pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
-#define                pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
-#define                pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
-#define                pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
-#define                pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
-#define                pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
-#define                pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
-
-/* SDH Registers */
-
-#define                      pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
-#define                      pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
-#define                     pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
-#define                      pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
-#define                     pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
-#define                    pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
-#define                    pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
-#define                    pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
-#define                    pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
-#define                   pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
-#define                    pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
-#define                     pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
-#define                     pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
-#define                       pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
-#define                   pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
-#define                        pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
-#define                        pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
-#define                     pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
-#define                         pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
-#define                     pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
-#define                       pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
-#define                          pSDH_CFG ((volatile unsigned short *)SDH_CFG)
-#define                   pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define                         pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
-#define                         pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
-#define                         pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
-#define                         pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
-#define                         pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
-#define                         pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
-#define                         pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
-#define                         pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-
-/* USB Endpoint 1 Control Registers */
-
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-
-/* USB Endpoint 2 Control Registers */
-
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-
-/* USB Endpoint 3 Control Registers */
-
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-
-/* USB Endpoint 4 Control Registers */
-
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-
-/* USB Endpoint 5 Control Registers */
-
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-
-/* USB Endpoint 6 Control Registers */
-
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-
-/* USB Endpoint 7 Control Registers */
-
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-/* Keypad Registers */
-
-#define                         pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
-#define                    pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
-#define                        pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
-#define                      pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
-#define                        pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
-#define                    pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF542_H */
diff --git a/libgloss/bfin/include/cdefBF542M.h b/libgloss/bfin/include/cdefBF542M.h
deleted file mode 100644
index 060b21387..000000000
--- a/libgloss/bfin/include/cdefBF542M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF542M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps to the cdef for BF542 unless anything
-** is required to change.
-**
-************************************************************************************/
-
-#ifndef _CDEF_BF542M_H
-#define _CDEF_BF542M_H
-
-#include <cdefBF542.h>
-
-#endif /* _CDEF_BF542M_H */
diff --git a/libgloss/bfin/include/cdefBF544.h b/libgloss/bfin/include/cdefBF544.h
deleted file mode 100644
index d16468289..000000000
--- a/libgloss/bfin/include/cdefBF544.h
+++ /dev/null
@@ -1,520 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF544.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF544 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include all Core registers and bit definitions */
-#include <defBF544.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <cdefBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
-#define                   pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
-#define                    pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
-#define                     pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
-#define                    pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
-#define                   pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
-#define                    pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
-#define                     pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
-#define                   pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
-#define                  pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
-#define                   pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
-#define                    pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
-
-/* Timer Group of 3 */
-
-#define                    pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
-#define                   pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
-#define                    pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
-
-/* EPPI0 Registers */
-
-#define                     pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
-#define                     pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
-#define                     pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
-#define                     pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
-#define                     pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
-#define                      pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
-#define                       pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
-#define                     pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
-#define                    pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
-#define                   pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
-#define                  pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
-#define                   pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
-#define                  pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
-#define                       pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
-#define                     pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
-#define                   pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
-#define                  pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define                  pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define                  pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
-#define                 pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
-#define                 pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define                    pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
-#define                    pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
-#define                    pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
-#define                   pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
-#define                   pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
-#define                  pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
-#define                   pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
-#define                  pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
-#define                         pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
-#define                        pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
-#define                        pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
-#define                         pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
-#define                         pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
-#define                        pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
-#define                        pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
-#define                      pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
-#define                      pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
-#define                       pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
-#define                        pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
-#define                       pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
-#define                         pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
-#define                        pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
-#define                        pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
-#define                         pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
-#define                         pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
-#define                        pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
-#define                        pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
-#define                      pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
-#define                      pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
-#define                       pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
-#define                        pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
-#define                       pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
-#define                      pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
-#define                       pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
-#define                      pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
-#define                         pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
-#define                         pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
-#define                         pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
-#define                         pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
-#define                     pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
-#define                        pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
-#define                        pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
-#define                         pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
-#define                         pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
-#define                       pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
-#define                        pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
-#define                       pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
-#define                       pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
-#define                       pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
-#define                       pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
-#define                       pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
-#define                       pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
-#define                       pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
-#define                       pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
-#define                       pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
-#define                       pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
-#define                       pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
-#define                       pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
-#define                       pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
-#define                       pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
-#define                       pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
-#define                       pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
-#define                       pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
-#define                       pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
-#define                       pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
-#define                       pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
-#define                       pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
-#define                       pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
-#define                       pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
-#define                       pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
-#define                       pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
-#define                       pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
-#define                       pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
-#define                       pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
-#define                       pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
-#define                       pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
-#define                       pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
-#define                       pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
-#define                       pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
-#define                       pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
-#define                       pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
-#define                       pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
-#define                       pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
-#define                       pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
-#define                       pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
-#define                       pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
-#define                       pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
-#define                       pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
-#define                       pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
-#define                       pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
-#define                       pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
-#define                       pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
-#define                       pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
-#define                       pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
-#define                       pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
-#define                       pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
-#define                       pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
-#define                       pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
-#define                       pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
-#define                       pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
-#define                       pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
-#define                       pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
-#define                       pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
-#define                       pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
-#define                       pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
-#define                       pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
-#define                       pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
-#define                       pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
-#define                       pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
-#define                  pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
-#define                  pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
-#define                  pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
-#define                 pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
-#define              pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
-#define                    pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
-#define                    pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
-#define                  pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
-#define                  pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
-#define                  pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
-#define                  pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
-#define                 pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
-#define              pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
-#define                    pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
-#define                    pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
-#define                  pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
-#define                  pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
-#define                  pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
-#define                  pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
-#define                 pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
-#define              pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
-#define                    pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
-#define                    pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
-#define                  pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
-#define                  pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
-#define                  pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
-#define                  pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
-#define                 pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
-#define              pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
-#define                    pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
-#define                    pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
-#define                  pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
-#define                  pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
-#define                  pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
-#define                  pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
-#define                 pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
-#define              pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
-#define                    pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
-#define                    pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
-#define                  pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
-#define                  pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
-#define                  pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
-#define                  pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
-#define                 pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
-#define              pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
-#define                    pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
-#define                    pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
-#define                  pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
-#define                  pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
-#define                  pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
-#define                  pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
-#define                 pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
-#define              pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
-#define                    pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
-#define                    pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
-#define                  pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
-#define                  pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
-#define                  pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
-#define                  pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
-#define                 pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
-#define              pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
-#define                    pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
-#define                    pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
-#define                  pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
-#define                  pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
-#define                  pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
-#define                  pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
-#define                 pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
-#define              pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
-#define                    pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
-#define                    pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
-#define                  pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
-#define                  pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
-#define                  pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
-#define                  pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
-#define                 pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
-#define              pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
-#define                    pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
-#define                    pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
-#define                  pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
-#define                  pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
-#define                  pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
-#define                  pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
-#define                 pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
-#define              pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
-#define                    pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
-#define                    pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
-#define                  pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
-#define                  pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
-#define                  pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
-#define                  pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
-#define                 pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
-#define              pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
-#define                    pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
-#define                    pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
-#define                  pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
-#define                  pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
-#define                  pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
-#define                  pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
-#define                 pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
-#define              pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
-#define                    pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
-#define                    pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
-#define                  pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
-#define                  pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
-#define                  pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
-#define                  pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
-#define                 pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
-#define              pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
-#define                    pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
-#define                    pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
-#define                  pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
-#define                  pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
-#define                  pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
-#define                  pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
-#define                 pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
-#define              pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
-#define                    pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
-#define                    pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
-#define                  pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
-#define                  pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
-#define                  pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
-#define                  pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
-#define                 pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
-#define              pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
-#define                    pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
-#define                    pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
-#define                  pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
-#define                  pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
-#define                  pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
-#define                 pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
-#define              pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
-#define                    pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
-#define                    pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
-#define                  pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
-#define                  pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
-#define                  pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
-#define                  pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
-#define                 pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
-#define              pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
-#define                    pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
-#define                    pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
-#define                  pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
-#define                  pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
-#define                  pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
-#define                  pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
-#define                 pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
-#define              pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
-#define                    pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
-#define                    pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
-#define                  pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
-#define                  pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
-#define                  pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
-#define                  pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
-#define                 pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
-#define              pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
-#define                    pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
-#define                    pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
-#define                  pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
-#define                  pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
-#define                  pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
-#define                  pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
-#define                 pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
-#define              pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
-#define                    pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
-#define                    pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
-#define                  pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
-#define                  pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
-#define                  pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
-#define                  pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
-#define                 pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
-#define              pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
-#define                    pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
-#define                    pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
-#define                  pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
-#define                  pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
-#define                  pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
-#define                  pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
-#define                 pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
-#define              pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
-#define                    pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
-#define                    pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
-#define                  pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
-#define                  pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
-#define                  pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
-#define                  pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
-#define                 pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
-#define              pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
-#define                    pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
-#define                    pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
-#define                  pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
-#define                  pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
-#define                  pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
-#define                  pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
-#define                 pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
-#define              pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
-#define                    pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
-#define                    pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
-#define                  pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
-#define                  pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
-#define                  pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
-#define                  pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
-#define                 pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
-#define              pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
-#define                    pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
-#define                    pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
-#define                  pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
-#define                  pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
-#define                  pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
-#define                  pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
-#define                 pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
-#define              pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
-#define                    pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
-#define                    pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
-#define                  pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
-#define                  pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
-#define                  pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
-#define                  pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
-#define                 pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
-#define              pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
-#define                    pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
-#define                    pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
-#define                  pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
-#define                  pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
-#define                  pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
-#define                  pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
-#define                 pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
-#define              pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
-#define                    pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
-#define                    pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
-#define                  pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
-#define                  pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
-#define                  pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
-#define                  pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
-#define                 pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
-#define              pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
-#define                    pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
-#define                    pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
-#define                  pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
-#define                  pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
-#define                  pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
-#define                  pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
-#define                 pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
-#define              pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
-#define                    pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
-#define                    pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
-#define                  pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
-#define                  pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
-#define                  pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
-#define                  pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
-#define                 pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
-#define              pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
-#define                    pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
-#define                    pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
-
-/* HOST Port Registers */
-
-#define                     pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
-#define                      pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
-#define                     pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
-#define                         pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
-#define                         pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
-#define                     pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
-#define                       pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
-#define                     pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
-#define                       pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
-#define                     pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
-#define                     pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
-#define                       pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
-#define                     pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
-#define                       pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
-#define                     pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
-#define                    pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
-#define                       pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
-#define                       pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
-#define                       pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
-#define                      pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
-#define                          pPIXC_TC ((volatile unsigned long *)PIXC_TC)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF544_H */
diff --git a/libgloss/bfin/include/cdefBF544M.h b/libgloss/bfin/include/cdefBF544M.h
deleted file mode 100644
index c2a9bb1b4..000000000
--- a/libgloss/bfin/include/cdefBF544M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF544M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps to the cdef for BF544 unless anything
-** is required to change.
-**
-************************************************************************************/
-
-#ifndef _CDEF_BF544M_H
-#define _CDEF_BF544M_H
-
-#include <cdefBF544.h>
-
-#endif /* _CDEF_BF544M_H */
diff --git a/libgloss/bfin/include/cdefBF547.h b/libgloss/bfin/include/cdefBF547.h
deleted file mode 100644
index cd7bfdf7f..000000000
--- a/libgloss/bfin/include/cdefBF547.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF547.h
-**
-** Copyright (C) 2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF547 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF547_H
-#define _CDEF_BF547_H
-
-/* include all Core registers and bit definitions */
-#include <defBF547.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <cdefBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
-#define                   pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
-#define                    pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
-#define                     pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
-#define                    pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
-#define                   pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
-#define                    pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
-#define                     pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
-#define                   pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
-#define                  pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
-#define                   pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
-#define                    pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
-
-/* Timer Group of 3 */
-
-#define                    pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
-#define                   pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
-#define                    pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
-
-/* SPORT0 Registers */
-
-#define                      pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
-#define                      pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
-#define                   pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define                    pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
-#define                        pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
-#define                        pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
-#define                      pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
-#define                      pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
-#define                   pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define                    pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
-#define                      pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
-#define                      pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
-#define                     pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
-#define                     pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
-#define                     pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
-#define                     pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
-#define                     pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
-#define                     pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
-#define                     pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
-#define                     pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
-#define                     pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
-#define                     pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
-
-/* EPPI0 Registers */
-
-#define                     pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
-#define                     pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
-#define                     pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
-#define                     pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
-#define                     pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
-#define                      pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
-#define                       pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
-#define                     pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
-#define                    pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
-#define                   pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
-#define                  pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
-#define                   pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
-#define                  pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
-#define                       pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
-
-/* UART2 Registers */
-
-#define                        pUART2_DLL ((volatile unsigned short *)UART2_DLL)
-#define                        pUART2_DLH ((volatile unsigned short *)UART2_DLH)
-#define                       pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
-#define                        pUART2_LCR ((volatile unsigned short *)UART2_LCR)
-#define                        pUART2_MCR ((volatile unsigned short *)UART2_MCR)
-#define                        pUART2_LSR ((volatile unsigned short *)UART2_LSR)
-#define                        pUART2_MSR ((volatile unsigned short *)UART2_MSR)
-#define                        pUART2_SCR ((volatile unsigned short *)UART2_SCR)
-#define                    pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
-#define                  pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
-#define                        pUART2_THR ((volatile unsigned short *)UART2_THR)
-#define                        pUART2_RBR ((volatile unsigned short *)UART2_RBR)
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
-#define                     pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
-#define                   pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
-#define                  pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define                  pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define                  pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
-#define                 pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
-#define                 pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define                    pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
-#define                    pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
-#define                    pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
-#define                   pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
-#define                   pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
-#define                  pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
-#define                   pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
-#define                  pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
-
-/* SPI2  Registers */
-
-#define                         pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
-#define                         pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
-#define                        pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
-#define                        pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
-#define                        pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
-#define                        pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
-#define                      pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
-
-/* ATAPI Registers */
-
-#define                    pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
-#define                     pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
-#define                   pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
-#define                  pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
-#define                  pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
-#define                   pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
-#define                 pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
-#define                   pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
-#define                pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
-#define                   pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
-#define                  pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
-#define                 pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
-#define                 pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
-#define               pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
-#define             pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
-#define                  pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
-#define                  pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
-#define                  pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
-#define                pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
-#define                pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
-#define                pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
-#define                pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
-#define                pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
-#define                pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
-#define                pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
-
-/* SDH Registers */
-
-#define                      pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
-#define                      pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
-#define                     pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
-#define                      pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
-#define                     pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
-#define                    pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
-#define                    pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
-#define                    pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
-#define                    pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
-#define                   pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
-#define                    pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
-#define                     pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
-#define                     pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
-#define                       pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
-#define                   pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
-#define                        pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
-#define                        pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
-#define                     pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
-#define                         pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
-#define                     pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
-#define                       pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
-#define                          pSDH_CFG ((volatile unsigned short *)SDH_CFG)
-#define                   pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define                         pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
-#define                         pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
-#define                         pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
-#define                         pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
-#define                         pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
-#define                         pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
-#define                         pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
-#define                         pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
-
-/* HOST Port Registers */
-
-#define                     pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
-#define                      pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
-#define                     pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-
-/* USB Endpoint 1 Control Registers */
-
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-
-/* USB Endpoint 2 Control Registers */
-
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-
-/* USB Endpoint 3 Control Registers */
-
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-
-/* USB Endpoint 4 Control Registers */
-
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-
-/* USB Endpoint 5 Control Registers */
-
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-
-/* USB Endpoint 6 Control Registers */
-
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-
-/* USB Endpoint 7 Control Registers */
-
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-/* Keypad Registers */
-
-#define                         pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
-#define                    pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
-#define                        pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
-#define                      pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
-#define                        pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
-#define                    pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
-#define                         pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
-#define                         pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
-#define                     pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
-#define                       pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
-#define                     pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
-#define                       pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
-#define                     pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
-#define                     pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
-#define                       pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
-#define                     pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
-#define                       pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
-#define                     pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
-#define                    pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
-#define                       pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
-#define                       pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
-#define                       pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
-#define                      pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
-#define                          pPIXC_TC ((volatile unsigned long *)PIXC_TC)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF547_H */
diff --git a/libgloss/bfin/include/cdefBF547M.h b/libgloss/bfin/include/cdefBF547M.h
deleted file mode 100644
index 14e2db0c0..000000000
--- a/libgloss/bfin/include/cdefBF547M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF547M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps to the cdef for BF547 unless anything
-** is required to change.
-**
-************************************************************************************/
-
-#ifndef _CDEF_BF547M_H
-#define _CDEF_BF547M_H
-
-#include <cdefBF547.h>
-
-#endif /* _CDEF_BF547M_H */
diff --git a/libgloss/bfin/include/cdefBF548.h b/libgloss/bfin/include/cdefBF548.h
deleted file mode 100644
index 062446825..000000000
--- a/libgloss/bfin/include/cdefBF548.h
+++ /dev/null
@@ -1,882 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF548.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF548 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include all Core registers and bit definitions */
-#include <defBF548.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <cdefBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
-#define                   pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
-#define                    pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
-#define                     pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
-#define                    pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
-#define                   pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
-#define                    pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
-#define                     pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
-#define                   pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
-#define                  pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
-#define                   pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
-#define                    pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
-
-/* Timer Group of 3 */
-
-#define                    pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
-#define                   pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
-#define                    pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
-
-/* SPORT0 Registers */
-
-#define                      pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
-#define                      pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
-#define                   pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define                    pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
-#define                        pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
-#define                        pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
-#define                      pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
-#define                      pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
-#define                   pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define                    pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
-#define                      pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
-#define                      pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
-#define                     pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
-#define                     pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
-#define                     pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
-#define                     pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
-#define                     pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
-#define                     pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
-#define                     pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
-#define                     pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
-#define                     pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
-#define                     pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
-
-/* EPPI0 Registers */
-
-#define                     pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
-#define                     pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
-#define                     pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
-#define                     pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
-#define                     pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
-#define                      pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
-#define                       pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
-#define                     pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
-#define                    pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
-#define                   pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
-#define                  pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
-#define                   pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
-#define                  pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
-#define                       pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
-
-/* UART2 Registers */
-
-#define                        pUART2_DLL ((volatile unsigned short *)UART2_DLL)
-#define                        pUART2_DLH ((volatile unsigned short *)UART2_DLH)
-#define                       pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
-#define                        pUART2_LCR ((volatile unsigned short *)UART2_LCR)
-#define                        pUART2_MCR ((volatile unsigned short *)UART2_MCR)
-#define                        pUART2_LSR ((volatile unsigned short *)UART2_LSR)
-#define                        pUART2_MSR ((volatile unsigned short *)UART2_MSR)
-#define                        pUART2_SCR ((volatile unsigned short *)UART2_SCR)
-#define                    pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
-#define                  pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
-#define                        pUART2_THR ((volatile unsigned short *)UART2_THR)
-#define                        pUART2_RBR ((volatile unsigned short *)UART2_RBR)
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
-#define                     pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
-#define                   pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
-#define                  pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define                  pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define                  pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
-#define                 pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
-#define                 pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define                    pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
-#define                    pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
-#define                    pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
-#define                   pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
-#define                   pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
-#define                  pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
-#define                   pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
-#define                  pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
-
-/* SPI2  Registers */
-
-#define                         pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
-#define                         pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
-#define                        pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
-#define                        pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
-#define                        pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
-#define                        pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
-#define                      pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
-#define                         pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
-#define                        pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
-#define                        pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
-#define                         pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
-#define                         pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
-#define                        pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
-#define                        pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
-#define                      pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
-#define                      pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
-#define                       pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
-#define                        pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
-#define                       pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
-#define                         pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
-#define                        pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
-#define                        pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
-#define                         pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
-#define                         pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
-#define                        pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
-#define                        pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
-#define                      pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
-#define                      pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
-#define                       pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
-#define                        pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
-#define                       pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
-#define                      pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
-#define                       pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
-#define                      pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
-#define                         pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
-#define                         pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
-#define                         pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
-#define                         pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
-#define                     pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
-#define                        pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
-#define                        pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
-#define                         pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
-#define                         pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
-#define                       pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
-#define                        pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
-#define                       pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
-#define                       pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
-#define                       pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
-#define                       pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
-#define                       pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
-#define                       pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
-#define                       pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
-#define                       pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
-#define                       pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
-#define                       pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
-#define                       pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
-#define                       pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
-#define                       pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
-#define                       pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
-#define                       pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
-#define                       pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
-#define                       pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
-#define                       pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
-#define                       pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
-#define                       pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
-#define                       pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
-#define                       pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
-#define                       pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
-#define                       pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
-#define                       pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
-#define                       pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
-#define                       pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
-#define                       pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
-#define                       pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
-#define                       pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
-#define                       pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
-#define                       pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
-#define                       pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
-#define                       pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
-#define                       pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
-#define                       pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
-#define                       pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
-#define                       pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
-#define                       pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
-#define                       pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
-#define                       pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
-#define                       pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
-#define                       pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
-#define                       pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
-#define                       pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
-#define                       pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
-#define                       pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
-#define                       pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
-#define                       pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
-#define                       pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
-#define                       pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
-#define                       pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
-#define                       pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
-#define                       pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
-#define                       pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
-#define                       pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
-#define                       pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
-#define                       pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
-#define                       pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
-#define                       pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
-#define                       pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
-#define                       pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
-#define                       pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
-#define                  pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
-#define                  pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
-#define                  pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
-#define                 pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
-#define              pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
-#define                    pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
-#define                    pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
-#define                  pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
-#define                  pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
-#define                  pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
-#define                  pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
-#define                 pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
-#define              pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
-#define                    pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
-#define                    pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
-#define                  pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
-#define                  pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
-#define                  pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
-#define                  pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
-#define                 pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
-#define              pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
-#define                    pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
-#define                    pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
-#define                  pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
-#define                  pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
-#define                  pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
-#define                  pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
-#define                 pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
-#define              pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
-#define                    pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
-#define                    pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
-#define                  pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
-#define                  pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
-#define                  pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
-#define                  pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
-#define                 pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
-#define              pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
-#define                    pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
-#define                    pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
-#define                  pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
-#define                  pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
-#define                  pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
-#define                  pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
-#define                 pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
-#define              pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
-#define                    pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
-#define                    pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
-#define                  pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
-#define                  pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
-#define                  pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
-#define                  pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
-#define                 pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
-#define              pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
-#define                    pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
-#define                    pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
-#define                  pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
-#define                  pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
-#define                  pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
-#define                  pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
-#define                 pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
-#define              pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
-#define                    pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
-#define                    pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
-#define                  pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
-#define                  pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
-#define                  pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
-#define                  pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
-#define                 pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
-#define              pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
-#define                    pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
-#define                    pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
-#define                  pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
-#define                  pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
-#define                  pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
-#define                  pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
-#define                 pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
-#define              pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
-#define                    pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
-#define                    pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
-#define                  pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
-#define                  pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
-#define                  pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
-#define                  pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
-#define                 pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
-#define              pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
-#define                    pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
-#define                    pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
-#define                  pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
-#define                  pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
-#define                  pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
-#define                  pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
-#define                 pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
-#define              pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
-#define                    pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
-#define                    pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
-#define                  pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
-#define                  pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
-#define                  pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
-#define                  pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
-#define                 pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
-#define              pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
-#define                    pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
-#define                    pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
-#define                  pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
-#define                  pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
-#define                  pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
-#define                  pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
-#define                 pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
-#define              pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
-#define                    pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
-#define                    pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
-#define                  pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
-#define                  pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
-#define                  pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
-#define                  pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
-#define                 pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
-#define              pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
-#define                    pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
-#define                    pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
-#define                  pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
-#define                  pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
-#define                  pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
-#define                  pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
-#define                 pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
-#define              pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
-#define                    pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
-#define                    pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
-#define                  pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
-#define                  pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
-#define                  pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
-#define                 pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
-#define              pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
-#define                    pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
-#define                    pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
-#define                  pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
-#define                  pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
-#define                  pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
-#define                  pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
-#define                 pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
-#define              pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
-#define                    pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
-#define                    pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
-#define                  pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
-#define                  pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
-#define                  pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
-#define                  pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
-#define                 pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
-#define              pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
-#define                    pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
-#define                    pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
-#define                  pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
-#define                  pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
-#define                  pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
-#define                  pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
-#define                 pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
-#define              pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
-#define                    pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
-#define                    pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
-#define                  pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
-#define                  pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
-#define                  pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
-#define                  pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
-#define                 pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
-#define              pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
-#define                    pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
-#define                    pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
-#define                  pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
-#define                  pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
-#define                  pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
-#define                  pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
-#define                 pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
-#define              pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
-#define                    pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
-#define                    pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
-#define                  pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
-#define                  pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
-#define                  pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
-#define                  pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
-#define                 pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
-#define              pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
-#define                    pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
-#define                    pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
-#define                  pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
-#define                  pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
-#define                  pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
-#define                  pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
-#define                 pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
-#define              pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
-#define                    pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
-#define                    pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
-#define                  pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
-#define                  pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
-#define                  pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
-#define                  pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
-#define                 pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
-#define              pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
-#define                    pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
-#define                    pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
-#define                  pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
-#define                  pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
-#define                  pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
-#define                  pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
-#define                 pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
-#define              pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
-#define                    pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
-#define                    pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
-#define                  pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
-#define                  pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
-#define                  pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
-#define                  pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
-#define                 pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
-#define              pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
-#define                    pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
-#define                    pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
-#define                  pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
-#define                  pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
-#define                  pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
-#define                  pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
-#define                 pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
-#define              pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
-#define                    pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
-#define                    pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
-#define                  pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
-#define                  pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
-#define                  pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
-#define                  pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
-#define                 pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
-#define              pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
-#define                    pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
-#define                    pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
-#define                  pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
-#define                  pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
-#define                  pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
-#define                  pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
-#define                 pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
-#define              pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
-#define                    pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
-#define                    pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
-#define                  pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
-#define                  pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
-#define                  pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
-#define                  pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
-#define                 pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
-#define              pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
-#define                    pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
-#define                    pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
-#define                  pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
-#define                  pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
-#define                  pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
-#define                  pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
-#define                 pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
-#define              pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
-#define                    pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
-#define                    pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
-
-/* ATAPI Registers */
-
-#define                    pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
-#define                     pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
-#define                   pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
-#define                  pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
-#define                  pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
-#define                   pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
-#define                 pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
-#define                   pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
-#define                pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
-#define                   pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
-#define                  pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
-#define                 pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
-#define                 pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
-#define               pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
-#define             pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
-#define                  pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
-#define                  pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
-#define                  pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
-#define                pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
-#define                pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
-#define                pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
-#define                pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
-#define                pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
-#define                pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
-#define                pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
-
-/* SDH Registers */
-
-#define                      pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
-#define                      pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
-#define                     pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
-#define                      pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
-#define                     pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
-#define                    pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
-#define                    pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
-#define                    pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
-#define                    pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
-#define                   pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
-#define                    pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
-#define                     pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
-#define                     pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
-#define                       pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
-#define                   pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
-#define                        pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
-#define                        pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
-#define                     pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
-#define                         pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
-#define                     pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
-#define                       pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
-#define                          pSDH_CFG ((volatile unsigned short *)SDH_CFG)
-#define                   pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define                         pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
-#define                         pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
-#define                         pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
-#define                         pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
-#define                         pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
-#define                         pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
-#define                         pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
-#define                         pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
-
-/* HOST Port Registers */
-
-#define                     pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
-#define                      pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
-#define                     pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-
-/* USB Endpoint 1 Control Registers */
-
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-
-/* USB Endpoint 2 Control Registers */
-
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-
-/* USB Endpoint 3 Control Registers */
-
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-
-/* USB Endpoint 4 Control Registers */
-
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-
-/* USB Endpoint 5 Control Registers */
-
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-
-/* USB Endpoint 6 Control Registers */
-
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-
-/* USB Endpoint 7 Control Registers */
-
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-/* Keypad Registers */
-
-#define                         pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
-#define                    pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
-#define                        pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
-#define                      pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
-#define                        pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
-#define                    pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
-#define                         pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
-#define                         pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
-#define                     pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
-#define                       pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
-#define                     pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
-#define                       pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
-#define                     pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
-#define                     pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
-#define                       pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
-#define                     pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
-#define                       pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
-#define                     pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
-#define                    pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
-#define                       pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
-#define                       pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
-#define                       pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
-#define                      pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
-#define                          pPIXC_TC ((volatile unsigned long *)PIXC_TC)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF548_H */
diff --git a/libgloss/bfin/include/cdefBF548M.h b/libgloss/bfin/include/cdefBF548M.h
deleted file mode 100644
index a0bee15e3..000000000
--- a/libgloss/bfin/include/cdefBF548M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF548M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps to the cdef for BF548 unless anything
-** is required to change.
-**
-************************************************************************************/
-
-#ifndef _CDEF_BF548M_H
-#define _CDEF_BF548M_H
-
-#include <cdefBF548.h>
-
-#endif /* _CDEF_BF548M_H */
diff --git a/libgloss/bfin/include/cdefBF549.h b/libgloss/bfin/include/cdefBF549.h
deleted file mode 100644
index 7dadd6b17..000000000
--- a/libgloss/bfin/include/cdefBF549.h
+++ /dev/null
@@ -1,1052 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF549.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF549 peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include all Core registers and bit definitions */
-#include <defBF549.h>
-
-/* include core specific register pointer definitions */
-#include <cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <cdefBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
-#define                   pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
-#define                    pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
-#define                     pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
-#define                    pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
-#define                   pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
-#define                    pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
-#define                     pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
-#define                   pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
-#define                  pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
-#define                   pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
-#define                    pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
-
-/* Timer Group of 3 */
-
-#define                    pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
-#define                   pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
-#define                    pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
-
-/* SPORT0 Registers */
-
-#define                      pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
-#define                      pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
-#define                   pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define                    pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
-#define                        pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
-#define                        pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
-#define                      pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
-#define                      pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
-#define                   pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define                    pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
-#define                      pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
-#define                      pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
-#define                     pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
-#define                     pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
-#define                     pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
-#define                     pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
-#define                     pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
-#define                     pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
-#define                     pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
-#define                     pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
-#define                     pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
-#define                     pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
-
-/* EPPI0 Registers */
-
-#define                     pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
-#define                     pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
-#define                     pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
-#define                     pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
-#define                     pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
-#define                      pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
-#define                       pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
-#define                     pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
-#define                    pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
-#define                   pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
-#define                  pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
-#define                   pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
-#define                  pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
-#define                       pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
-
-/* UART2 Registers */
-
-#define                        pUART2_DLL ((volatile unsigned short *)UART2_DLL)
-#define                        pUART2_DLH ((volatile unsigned short *)UART2_DLH)
-#define                       pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
-#define                        pUART2_LCR ((volatile unsigned short *)UART2_LCR)
-#define                        pUART2_MCR ((volatile unsigned short *)UART2_MCR)
-#define                        pUART2_LSR ((volatile unsigned short *)UART2_LSR)
-#define                        pUART2_MSR ((volatile unsigned short *)UART2_MSR)
-#define                        pUART2_SCR ((volatile unsigned short *)UART2_SCR)
-#define                    pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
-#define                  pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
-#define                        pUART2_THR ((volatile unsigned short *)UART2_THR)
-#define                        pUART2_RBR ((volatile unsigned short *)UART2_RBR)
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
-#define                     pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
-#define                   pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
-#define                  pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
-#define                  pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
-#define                  pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
-#define                 pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
-#define                 pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
-#define                    pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
-#define                    pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
-#define                    pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
-#define                   pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
-#define                   pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
-#define                  pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
-#define                   pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
-#define                  pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
-
-/* SPI2 Registers */
-
-#define                         pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
-#define                         pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
-#define                        pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
-#define                        pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
-#define                        pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
-#define                        pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
-#define                      pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
-
-/* MXVR Registers */
-
-#define                      pMXVR_CONFIG ((volatile unsigned short *)MXVR_CONFIG)
-#define                     pMXVR_STATE_0 ((volatile unsigned long *)MXVR_STATE_0)
-#define                     pMXVR_STATE_1 ((volatile unsigned long *)MXVR_STATE_1)
-#define                  pMXVR_INT_STAT_0 ((volatile unsigned long *)MXVR_INT_STAT_0)
-#define                  pMXVR_INT_STAT_1 ((volatile unsigned long *)MXVR_INT_STAT_1)
-#define                    pMXVR_INT_EN_0 ((volatile unsigned long *)MXVR_INT_EN_0)
-#define                    pMXVR_INT_EN_1 ((volatile unsigned long *)MXVR_INT_EN_1)
-#define                    pMXVR_POSITION ((volatile unsigned short *)MXVR_POSITION)
-#define                pMXVR_MAX_POSITION ((volatile unsigned short *)MXVR_MAX_POSITION)
-#define                       pMXVR_DELAY ((volatile unsigned short *)MXVR_DELAY)
-#define                   pMXVR_MAX_DELAY ((volatile unsigned short *)MXVR_MAX_DELAY)
-#define                       pMXVR_LADDR ((volatile unsigned long *)MXVR_LADDR)
-#define                       pMXVR_GADDR ((volatile unsigned short *)MXVR_GADDR)
-#define                       pMXVR_AADDR ((volatile unsigned long *)MXVR_AADDR)
-
-/* MXVR Allocation Table Registers */
-
-#define                     pMXVR_ALLOC_0 ((volatile unsigned long *)MXVR_ALLOC_0)
-#define                     pMXVR_ALLOC_1 ((volatile unsigned long *)MXVR_ALLOC_1)
-#define                     pMXVR_ALLOC_2 ((volatile unsigned long *)MXVR_ALLOC_2)
-#define                     pMXVR_ALLOC_3 ((volatile unsigned long *)MXVR_ALLOC_3)
-#define                     pMXVR_ALLOC_4 ((volatile unsigned long *)MXVR_ALLOC_4)
-#define                     pMXVR_ALLOC_5 ((volatile unsigned long *)MXVR_ALLOC_5)
-#define                     pMXVR_ALLOC_6 ((volatile unsigned long *)MXVR_ALLOC_6)
-#define                     pMXVR_ALLOC_7 ((volatile unsigned long *)MXVR_ALLOC_7)
-#define                     pMXVR_ALLOC_8 ((volatile unsigned long *)MXVR_ALLOC_8)
-#define                     pMXVR_ALLOC_9 ((volatile unsigned long *)MXVR_ALLOC_9)
-#define                    pMXVR_ALLOC_10 ((volatile unsigned long *)MXVR_ALLOC_10)
-#define                    pMXVR_ALLOC_11 ((volatile unsigned long *)MXVR_ALLOC_11)
-#define                    pMXVR_ALLOC_12 ((volatile unsigned long *)MXVR_ALLOC_12)
-#define                    pMXVR_ALLOC_13 ((volatile unsigned long *)MXVR_ALLOC_13)
-#define                    pMXVR_ALLOC_14 ((volatile unsigned long *)MXVR_ALLOC_14)
-
-/* MXVR Channel Assign Registers */
-
-#define                pMXVR_SYNC_LCHAN_0 ((volatile unsigned long *)MXVR_SYNC_LCHAN_0)
-#define                pMXVR_SYNC_LCHAN_1 ((volatile unsigned long *)MXVR_SYNC_LCHAN_1)
-#define                pMXVR_SYNC_LCHAN_2 ((volatile unsigned long *)MXVR_SYNC_LCHAN_2)
-#define                pMXVR_SYNC_LCHAN_3 ((volatile unsigned long *)MXVR_SYNC_LCHAN_3)
-#define                pMXVR_SYNC_LCHAN_4 ((volatile unsigned long *)MXVR_SYNC_LCHAN_4)
-#define                pMXVR_SYNC_LCHAN_5 ((volatile unsigned long *)MXVR_SYNC_LCHAN_5)
-#define                pMXVR_SYNC_LCHAN_6 ((volatile unsigned long *)MXVR_SYNC_LCHAN_6)
-#define                pMXVR_SYNC_LCHAN_7 ((volatile unsigned long *)MXVR_SYNC_LCHAN_7)
-
-/* MXVR DMA0 Registers */
-
-#define                 pMXVR_DMA0_CONFIG ((volatile unsigned long *)MXVR_DMA0_CONFIG)
-#define             pMXVR_DMA0_START_ADDR ((void *volatile *)MXVR_DMA0_START_ADDR)
-#define                  pMXVR_DMA0_COUNT ((volatile unsigned short *)MXVR_DMA0_COUNT)
-#define              pMXVR_DMA0_CURR_ADDR ((void *volatile *)MXVR_DMA0_CURR_ADDR)
-#define             pMXVR_DMA0_CURR_COUNT ((volatile unsigned short *)MXVR_DMA0_CURR_COUNT)
-
-/* MXVR DMA1 Registers */
-
-#define                 pMXVR_DMA1_CONFIG ((volatile unsigned long *)MXVR_DMA1_CONFIG)
-#define             pMXVR_DMA1_START_ADDR ((void *volatile *)MXVR_DMA1_START_ADDR)
-#define                  pMXVR_DMA1_COUNT ((volatile unsigned short *)MXVR_DMA1_COUNT)
-#define              pMXVR_DMA1_CURR_ADDR ((void *volatile *)MXVR_DMA1_CURR_ADDR)
-#define             pMXVR_DMA1_CURR_COUNT ((volatile unsigned short *)MXVR_DMA1_CURR_COUNT)
-
-/* MXVR DMA2 Registers */
-
-#define                 pMXVR_DMA2_CONFIG ((volatile unsigned long *)MXVR_DMA2_CONFIG)
-#define             pMXVR_DMA2_START_ADDR ((void *volatile *)MXVR_DMA2_START_ADDR)
-#define                  pMXVR_DMA2_COUNT ((volatile unsigned short *)MXVR_DMA2_COUNT)
-#define              pMXVR_DMA2_CURR_ADDR ((void *volatile *)MXVR_DMA2_CURR_ADDR)
-#define             pMXVR_DMA2_CURR_COUNT ((volatile unsigned short *)MXVR_DMA2_CURR_COUNT)
-
-/* MXVR DMA3 Registers */
-
-#define                 pMXVR_DMA3_CONFIG ((volatile unsigned long *)MXVR_DMA3_CONFIG)
-#define             pMXVR_DMA3_START_ADDR ((void *volatile *)MXVR_DMA3_START_ADDR)
-#define                  pMXVR_DMA3_COUNT ((volatile unsigned short *)MXVR_DMA3_COUNT)
-#define              pMXVR_DMA3_CURR_ADDR ((void *volatile *)MXVR_DMA3_CURR_ADDR)
-#define             pMXVR_DMA3_CURR_COUNT ((volatile unsigned short *)MXVR_DMA3_CURR_COUNT)
-
-/* MXVR DMA4 Registers */
-
-#define                 pMXVR_DMA4_CONFIG ((volatile unsigned long *)MXVR_DMA4_CONFIG)
-#define             pMXVR_DMA4_START_ADDR ((void *volatile *)MXVR_DMA4_START_ADDR)
-#define                  pMXVR_DMA4_COUNT ((volatile unsigned short *)MXVR_DMA4_COUNT)
-#define              pMXVR_DMA4_CURR_ADDR ((void *volatile *)MXVR_DMA4_CURR_ADDR)
-#define             pMXVR_DMA4_CURR_COUNT ((volatile unsigned short *)MXVR_DMA4_CURR_COUNT)
-
-/* MXVR DMA5 Registers */
-
-#define                 pMXVR_DMA5_CONFIG ((volatile unsigned long *)MXVR_DMA5_CONFIG)
-#define             pMXVR_DMA5_START_ADDR ((void *volatile *)MXVR_DMA5_START_ADDR)
-#define                  pMXVR_DMA5_COUNT ((volatile unsigned short *)MXVR_DMA5_COUNT)
-#define              pMXVR_DMA5_CURR_ADDR ((void *volatile *)MXVR_DMA5_CURR_ADDR)
-#define             pMXVR_DMA5_CURR_COUNT ((volatile unsigned short *)MXVR_DMA5_CURR_COUNT)
-
-/* MXVR DMA6 Registers */
-
-#define                 pMXVR_DMA6_CONFIG ((volatile unsigned long *)MXVR_DMA6_CONFIG)
-#define             pMXVR_DMA6_START_ADDR ((void *volatile *)MXVR_DMA6_START_ADDR)
-#define                  pMXVR_DMA6_COUNT ((volatile unsigned short *)MXVR_DMA6_COUNT)
-#define              pMXVR_DMA6_CURR_ADDR ((void *volatile *)MXVR_DMA6_CURR_ADDR)
-#define             pMXVR_DMA6_CURR_COUNT ((volatile unsigned short *)MXVR_DMA6_CURR_COUNT)
-
-/* MXVR DMA7 Registers */
-
-#define                 pMXVR_DMA7_CONFIG ((volatile unsigned long *)MXVR_DMA7_CONFIG)
-#define             pMXVR_DMA7_START_ADDR ((void *volatile *)MXVR_DMA7_START_ADDR)
-#define                  pMXVR_DMA7_COUNT ((volatile unsigned short *)MXVR_DMA7_COUNT)
-#define              pMXVR_DMA7_CURR_ADDR ((void *volatile *)MXVR_DMA7_CURR_ADDR)
-#define             pMXVR_DMA7_CURR_COUNT ((volatile unsigned short *)MXVR_DMA7_CURR_COUNT)
-
-/* MXVR Asynch Packet Registers */
-
-#define                      pMXVR_AP_CTL ((volatile unsigned short *)MXVR_AP_CTL)
-#define             pMXVR_APRB_START_ADDR ((void *volatile *)MXVR_APRB_START_ADDR)
-#define              pMXVR_APRB_CURR_ADDR ((void *volatile *)MXVR_APRB_CURR_ADDR)
-#define             pMXVR_APTB_START_ADDR ((void *volatile *)MXVR_APTB_START_ADDR)
-#define              pMXVR_APTB_CURR_ADDR ((void *volatile *)MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define                      pMXVR_CM_CTL ((volatile unsigned long *)MXVR_CM_CTL)
-#define             pMXVR_CMRB_START_ADDR ((void *volatile *)MXVR_CMRB_START_ADDR)
-#define              pMXVR_CMRB_CURR_ADDR ((void *volatile *)MXVR_CMRB_CURR_ADDR)
-#define             pMXVR_CMTB_START_ADDR ((void *volatile *)MXVR_CMTB_START_ADDR)
-#define              pMXVR_CMTB_CURR_ADDR ((void *volatile *)MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define             pMXVR_RRDB_START_ADDR ((void *volatile *)MXVR_RRDB_START_ADDR)
-#define              pMXVR_RRDB_CURR_ADDR ((void *volatile *)MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define                  pMXVR_PAT_DATA_0 ((volatile unsigned long *)MXVR_PAT_DATA_0)
-#define                    pMXVR_PAT_EN_0 ((volatile unsigned long *)MXVR_PAT_EN_0)
-#define                  pMXVR_PAT_DATA_1 ((volatile unsigned long *)MXVR_PAT_DATA_1)
-#define                    pMXVR_PAT_EN_1 ((volatile unsigned long *)MXVR_PAT_EN_1)
-
-/* MXVR Frame Counter Registers */
-
-#define                 pMXVR_FRAME_CNT_0 ((volatile unsigned short *)MXVR_FRAME_CNT_0)
-#define                 pMXVR_FRAME_CNT_1 ((volatile unsigned short *)MXVR_FRAME_CNT_1)
-
-/* MXVR Routing Table Registers */
-
-#define                   pMXVR_ROUTING_0 ((volatile unsigned long *)MXVR_ROUTING_0)
-#define                   pMXVR_ROUTING_1 ((volatile unsigned long *)MXVR_ROUTING_1)
-#define                   pMXVR_ROUTING_2 ((volatile unsigned long *)MXVR_ROUTING_2)
-#define                   pMXVR_ROUTING_3 ((volatile unsigned long *)MXVR_ROUTING_3)
-#define                   pMXVR_ROUTING_4 ((volatile unsigned long *)MXVR_ROUTING_4)
-#define                   pMXVR_ROUTING_5 ((volatile unsigned long *)MXVR_ROUTING_5)
-#define                   pMXVR_ROUTING_6 ((volatile unsigned long *)MXVR_ROUTING_6)
-#define                   pMXVR_ROUTING_7 ((volatile unsigned long *)MXVR_ROUTING_7)
-#define                   pMXVR_ROUTING_8 ((volatile unsigned long *)MXVR_ROUTING_8)
-#define                   pMXVR_ROUTING_9 ((volatile unsigned long *)MXVR_ROUTING_9)
-#define                  pMXVR_ROUTING_10 ((volatile unsigned long *)MXVR_ROUTING_10)
-#define                  pMXVR_ROUTING_11 ((volatile unsigned long *)MXVR_ROUTING_11)
-#define                  pMXVR_ROUTING_12 ((volatile unsigned long *)MXVR_ROUTING_12)
-#define                  pMXVR_ROUTING_13 ((volatile unsigned long *)MXVR_ROUTING_13)
-#define                  pMXVR_ROUTING_14 ((volatile unsigned long *)MXVR_ROUTING_14)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define                   pMXVR_BLOCK_CNT ((volatile unsigned short *)MXVR_BLOCK_CNT)
-#define                     pMXVR_CLK_CTL ((volatile unsigned long *)MXVR_CLK_CTL)
-#define                  pMXVR_CDRPLL_CTL ((volatile unsigned long *)MXVR_CDRPLL_CTL)
-#define                   pMXVR_FMPLL_CTL ((volatile unsigned long *)MXVR_FMPLL_CTL)
-#define                     pMXVR_PIN_CTL ((volatile unsigned short *)MXVR_PIN_CTL)
-#define                    pMXVR_SCLK_CNT ((volatile unsigned short *)MXVR_SCLK_CNT)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
-#define                         pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
-#define                        pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
-#define                        pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
-#define                         pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
-#define                         pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
-#define                        pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
-#define                        pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
-#define                      pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
-#define                      pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
-#define                       pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
-#define                        pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
-#define                       pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
-#define                         pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
-#define                        pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
-#define                        pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
-#define                         pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
-#define                         pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
-#define                        pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
-#define                        pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
-#define                      pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
-#define                      pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
-#define                       pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
-#define                        pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
-#define                       pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
-#define                      pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
-#define                       pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
-#define                      pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
-#define                         pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
-#define                         pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
-#define                         pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
-#define                         pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
-#define                     pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
-#define                        pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
-#define                        pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
-#define                         pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
-#define                         pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
-#define                       pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
-#define                        pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
-#define                       pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
-#define                       pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
-#define                       pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
-#define                       pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
-#define                       pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
-#define                       pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
-#define                       pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
-#define                       pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
-#define                       pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
-#define                       pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
-#define                       pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
-#define                       pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
-#define                       pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
-#define                       pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
-#define                       pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
-#define                       pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
-#define                       pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
-#define                       pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
-#define                       pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
-#define                       pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
-#define                       pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
-#define                       pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
-#define                       pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
-#define                       pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
-#define                       pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
-#define                       pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
-#define                       pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
-#define                       pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
-#define                       pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
-#define                       pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
-#define                       pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
-#define                       pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
-#define                       pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
-#define                       pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
-#define                       pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
-#define                       pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
-#define                       pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
-#define                       pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
-#define                       pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
-#define                       pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
-#define                       pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
-#define                       pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
-#define                       pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
-#define                       pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
-#define                       pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
-#define                       pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
-#define                       pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
-#define                       pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
-#define                       pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
-#define                       pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
-#define                       pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
-#define                       pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
-#define                       pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
-#define                       pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
-#define                       pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
-#define                       pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
-#define                       pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
-#define                       pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
-#define                       pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
-#define                       pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
-#define                       pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
-#define                       pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
-#define                       pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
-#define                  pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
-#define                  pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
-#define                  pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
-#define                 pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
-#define              pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
-#define                    pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
-#define                    pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
-#define                  pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
-#define                  pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
-#define                  pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
-#define                  pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
-#define                 pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
-#define              pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
-#define                    pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
-#define                    pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
-#define                  pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
-#define                  pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
-#define                  pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
-#define                  pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
-#define                 pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
-#define              pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
-#define                    pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
-#define                    pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
-#define                  pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
-#define                  pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
-#define                  pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
-#define                  pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
-#define                 pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
-#define              pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
-#define                    pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
-#define                    pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
-#define                  pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
-#define                  pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
-#define                  pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
-#define                  pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
-#define                 pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
-#define              pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
-#define                    pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
-#define                    pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
-#define                  pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
-#define                  pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
-#define                  pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
-#define                  pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
-#define                 pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
-#define              pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
-#define                    pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
-#define                    pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
-#define                  pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
-#define                  pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
-#define                  pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
-#define                  pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
-#define                 pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
-#define              pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
-#define                    pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
-#define                    pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
-#define                  pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
-#define                  pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
-#define                  pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
-#define                  pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
-#define                 pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
-#define              pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
-#define                    pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
-#define                    pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
-#define                  pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
-#define                  pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
-#define                  pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
-#define                  pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
-#define                 pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
-#define              pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
-#define                    pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
-#define                    pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
-#define                  pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
-#define                  pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
-#define                  pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
-#define                  pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
-#define                 pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
-#define              pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
-#define                    pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
-#define                    pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
-#define                  pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
-#define                  pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
-#define                  pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
-#define                  pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
-#define                 pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
-#define              pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
-#define                    pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
-#define                    pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
-#define                  pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
-#define                  pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
-#define                  pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
-#define                  pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
-#define                 pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
-#define              pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
-#define                    pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
-#define                    pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
-#define                  pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
-#define                  pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
-#define                  pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
-#define                  pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
-#define                 pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
-#define              pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
-#define                    pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
-#define                    pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
-#define                  pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
-#define                  pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
-#define                  pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
-#define                  pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
-#define                 pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
-#define              pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
-#define                    pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
-#define                    pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
-#define                  pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
-#define                  pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
-#define                  pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
-#define                  pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
-#define                 pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
-#define              pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
-#define                    pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
-#define                    pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
-#define                  pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
-#define                  pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
-#define                  pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
-#define                  pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
-#define                 pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
-#define              pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
-#define                    pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
-#define                    pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
-#define                  pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
-#define                  pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
-#define                  pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
-#define                 pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
-#define              pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
-#define                    pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
-#define                    pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
-#define                  pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
-#define                  pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
-#define                  pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
-#define                  pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
-#define                 pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
-#define              pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
-#define                    pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
-#define                    pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
-#define                  pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
-#define                  pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
-#define                  pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
-#define                  pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
-#define                 pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
-#define              pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
-#define                    pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
-#define                    pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
-#define                  pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
-#define                  pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
-#define                  pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
-#define                  pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
-#define                 pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
-#define              pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
-#define                    pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
-#define                    pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
-#define                  pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
-#define                  pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
-#define                  pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
-#define                  pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
-#define                 pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
-#define              pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
-#define                    pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
-#define                    pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
-#define                  pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
-#define                  pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
-#define                  pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
-#define                  pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
-#define                 pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
-#define              pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
-#define                    pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
-#define                    pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
-#define                  pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
-#define                  pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
-#define                  pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
-#define                  pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
-#define                 pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
-#define              pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
-#define                    pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
-#define                    pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
-#define                  pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
-#define                  pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
-#define                  pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
-#define                  pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
-#define                 pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
-#define              pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
-#define                    pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
-#define                    pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
-#define                  pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
-#define                  pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
-#define                  pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
-#define                  pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
-#define                 pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
-#define              pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
-#define                    pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
-#define                    pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
-#define                  pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
-#define                  pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
-#define                  pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
-#define                  pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
-#define                 pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
-#define              pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
-#define                    pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
-#define                    pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
-#define                  pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
-#define                  pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
-#define                  pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
-#define                  pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
-#define                 pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
-#define              pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
-#define                    pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
-#define                    pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
-#define                  pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
-#define                  pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
-#define                  pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
-#define                  pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
-#define                 pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
-#define              pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
-#define                    pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
-#define                    pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
-#define                  pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
-#define                  pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
-#define                  pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
-#define                  pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
-#define                 pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
-#define              pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
-#define                    pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
-#define                    pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
-#define                  pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
-#define                  pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
-#define                  pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
-#define                  pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
-#define                 pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
-#define              pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
-#define                    pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
-#define                    pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
-#define                  pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
-#define                  pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
-#define                  pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
-#define                  pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
-#define                 pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
-#define              pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
-#define                    pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
-#define                    pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
-#define                  pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
-#define                  pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
-#define                  pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
-#define                  pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
-#define                 pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
-#define              pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
-#define                    pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
-#define                    pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
-
-/* ATAPI Registers */
-
-#define                    pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
-#define                     pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
-#define                   pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
-#define                  pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
-#define                  pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
-#define                   pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
-#define                 pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
-#define                   pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
-#define                pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
-#define                   pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
-#define                  pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
-#define                 pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
-#define                 pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
-#define               pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
-#define             pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
-#define                  pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
-#define                  pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
-#define                  pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
-#define                pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
-#define                pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
-#define                pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
-#define                pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
-#define                pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
-#define                pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
-#define                pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
-
-/* SDH Registers */
-
-#define                      pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
-#define                      pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
-#define                     pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
-#define                      pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
-#define                     pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
-#define                    pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
-#define                    pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
-#define                    pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
-#define                    pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
-#define                   pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
-#define                    pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
-#define                     pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
-#define                     pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
-#define                       pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
-#define                   pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
-#define                        pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
-#define                        pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
-#define                     pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
-#define                         pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
-#define                     pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
-#define                       pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
-#define                          pSDH_CFG ((volatile unsigned short *)SDH_CFG)
-#define                   pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
-#define                         pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
-#define                         pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
-#define                         pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
-#define                         pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
-#define                         pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
-#define                         pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
-#define                         pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
-#define                         pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
-
-/* HOST Port Registers */
-
-#define                     pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
-#define                      pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
-#define                     pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
-
-/* USB Control Registers */
-
-#define                        pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
-#define                        pUSB_POWER ((volatile unsigned short *)USB_POWER)
-#define                       pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
-#define                       pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
-#define                      pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
-#define                      pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
-#define                      pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
-#define                     pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
-#define                        pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
-#define                        pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
-#define                     pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
-#define                     pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
-#define                   pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
-
-/* USB Packet Control Registers */
-
-#define                pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
-#define                         pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
-#define                        pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
-#define                pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
-#define                        pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
-#define                       pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
-#define                      pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
-#define                       pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
-#define                    pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
-#define                   pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
-#define                       pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
-#define                   pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
-#define                      pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
-
-/* USB Endpoint FIFO Registers */
-
-#define                     pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
-#define                     pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
-#define                     pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
-#define                     pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
-#define                     pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
-#define                     pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
-#define                     pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
-#define                     pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
-
-/* USB OTG Control Registers */
-
-#define                  pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
-#define                 pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
-#define                pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
-
-/* USB Phy Control Registers */
-
-#define                     pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
-#define                        pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
-#define                      pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
-#define                      pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
-#define                      pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
-#define                  pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
-#define                  pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
-#define                   pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
-
-/* USB Endpoint 0 Control Registers */
-
-#define                pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
-#define                 pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
-#define                pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
-#define                 pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
-#define               pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
-#define                pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
-#define            pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
-#define                pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
-#define            pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
-
-/* USB Endpoint 1 Control Registers */
-
-#define               pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
-#define                pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
-#define                 pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
-#define                pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
-#define                 pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
-#define               pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
-#define                pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
-#define            pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
-#define                pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
-#define            pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
-
-/* USB Endpoint 2 Control Registers */
-
-#define               pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
-#define                pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
-#define                 pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
-#define                pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
-#define                 pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
-#define               pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
-#define                pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
-#define            pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
-#define                pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
-#define            pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
-
-/* USB Endpoint 3 Control Registers */
-
-#define               pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
-#define                pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
-#define                 pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
-#define                pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
-#define                 pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
-#define               pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
-#define                pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
-#define            pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
-#define                pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
-#define            pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
-
-/* USB Endpoint 4 Control Registers */
-
-#define               pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
-#define                pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
-#define                 pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
-#define                pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
-#define                 pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
-#define               pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
-#define                pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
-#define            pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
-#define                pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
-#define            pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
-
-/* USB Endpoint 5 Control Registers */
-
-#define               pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
-#define                pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
-#define                 pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
-#define                pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
-#define                 pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
-#define               pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
-#define                pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
-#define            pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
-#define                pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
-#define            pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
-
-/* USB Endpoint 6 Control Registers */
-
-#define               pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
-#define                pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
-#define                 pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
-#define                pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
-#define                 pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
-#define               pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
-#define                pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
-#define            pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
-#define                pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
-#define            pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
-
-/* USB Endpoint 7 Control Registers */
-
-#define               pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
-#define                pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
-#define                 pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
-#define                pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
-#define                 pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
-#define               pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
-#define                pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
-#define            pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
-#define                pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
-#define            pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
-#define               pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
-#define                pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
-
-/* USB Channel 0 Config Registers */
-
-#define                  pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
-#define                  pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
-#define                 pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
-#define                 pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
-#define                pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
-
-/* USB Channel 1 Config Registers */
-
-#define                  pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
-#define                  pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
-#define                 pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
-#define                 pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
-#define                pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
-
-/* USB Channel 2 Config Registers */
-
-#define                  pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
-#define                  pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
-#define                 pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
-#define                 pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
-#define                pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
-
-/* USB Channel 3 Config Registers */
-
-#define                  pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
-#define                  pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
-#define                 pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
-#define                 pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
-#define                pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
-
-/* USB Channel 4 Config Registers */
-
-#define                  pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
-#define                  pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
-#define                 pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
-#define                 pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
-#define                pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
-
-/* USB Channel 5 Config Registers */
-
-#define                  pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
-#define                  pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
-#define                 pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
-#define                 pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
-#define                pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
-
-/* USB Channel 6 Config Registers */
-
-#define                  pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
-#define                  pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
-#define                 pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
-#define                 pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
-#define                pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
-
-/* USB Channel 7 Config Registers */
-
-#define                  pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
-#define                  pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
-#define                 pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
-#define                 pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
-#define                pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
-
-/* Keypad Registers */
-
-#define                         pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
-#define                    pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
-#define                        pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
-#define                      pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
-#define                        pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
-#define                    pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
-#define                         pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
-#define                         pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
-#define                     pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
-#define                       pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
-#define                     pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
-#define                       pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
-#define                     pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
-#define                     pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
-#define                       pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
-#define                     pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
-#define                       pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
-#define                     pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
-#define                    pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
-#define                       pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
-#define                       pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
-#define                       pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
-#define                      pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
-#define                          pPIXC_TC ((volatile unsigned long *)PIXC_TC)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF549_H */
diff --git a/libgloss/bfin/include/cdefBF549M.h b/libgloss/bfin/include/cdefBF549M.h
deleted file mode 100644
index c378ce36a..000000000
--- a/libgloss/bfin/include/cdefBF549M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF549M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps to the cdef for BF549 unless anything
-** is required to change.
-**
-************************************************************************************/
-
-#ifndef _CDEF_BF549M_H
-#define _CDEF_BF549M_H
-
-#include <cdefBF549.h>
-
-#endif /* _CDEF_BF549M_H */
diff --git a/libgloss/bfin/include/cdefBF54x_base.h b/libgloss/bfin/include/cdefBF54x_base.h
deleted file mode 100644
index 62388b99d..000000000
--- a/libgloss/bfin/include/cdefBF54x_base.h
+++ /dev/null
@@ -1,1519 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF54x_base.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF54x peripherals.
-**
-***************************************************************/
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-#include <defBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define                          pPLL_CTL ((volatile unsigned short *)PLL_CTL)
-#define                          pPLL_DIV ((volatile unsigned short *)PLL_DIV)
-#define                           pVR_CTL ((volatile unsigned short *)VR_CTL)
-#define                         pPLL_STAT ((volatile unsigned short *)PLL_STAT)
-#define                      pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define                           pCHIPID ((volatile unsigned long *)CHIPID)
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define                            pSWRST ((volatile unsigned short *)SWRST)
-#define                            pSYSCR ((volatile unsigned short *)SYSCR)
-
-/* SIC Registers */
-
-#define                       pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
-#define                       pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
-#define                       pSIC_IMASK2 ((volatile unsigned long *)SIC_IMASK2)
-#define                         pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0)
-#define                         pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
-#define                         pSIC_ISR2 ((volatile unsigned long *)SIC_ISR2)
-#define                         pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0)
-#define                         pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
-#define                         pSIC_IWR2 ((volatile unsigned long *)SIC_IWR2)
-#define                         pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
-#define                         pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
-#define                         pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
-#define                         pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
-#define                         pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
-#define                         pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
-#define                         pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
-#define                         pSIC_IAR7 ((volatile unsigned long *)SIC_IAR7)
-#define                         pSIC_IAR8 ((volatile unsigned long *)SIC_IAR8)
-#define                         pSIC_IAR9 ((volatile unsigned long *)SIC_IAR9)
-#define                        pSIC_IAR10 ((volatile unsigned long *)SIC_IAR10)
-#define                        pSIC_IAR11 ((volatile unsigned long *)SIC_IAR11)
-
-/* Watchdog Timer Registers */
-
-#define                         pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
-#define                         pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
-#define                        pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
-
-/* RTC Registers */
-
-#define                         pRTC_STAT ((volatile unsigned long *)RTC_STAT)
-#define                         pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
-#define                        pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
-#define                        pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
-#define                        pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
-#define                         pRTC_PREN ((volatile unsigned short *)RTC_PREN)
-
-/* UART0 Registers */
-
-#define                        pUART0_DLL ((volatile unsigned short *)UART0_DLL)
-#define                        pUART0_DLH ((volatile unsigned short *)UART0_DLH)
-#define                       pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
-#define                        pUART0_LCR ((volatile unsigned short *)UART0_LCR)
-#define                        pUART0_MCR ((volatile unsigned short *)UART0_MCR)
-#define                        pUART0_LSR ((volatile unsigned short *)UART0_LSR)
-#define                        pUART0_MSR ((volatile unsigned short *)UART0_MSR)
-#define                        pUART0_SCR ((volatile unsigned short *)UART0_SCR)
-#define                    pUART0_IER_SET ((volatile unsigned short *)UART0_IER_SET)
-#define                  pUART0_IER_CLEAR ((volatile unsigned short *)UART0_IER_CLEAR)
-#define                        pUART0_THR ((volatile unsigned short *)UART0_THR)
-#define                        pUART0_RBR ((volatile unsigned short *)UART0_RBR)
-
-/* SPI0 Registers */
-
-#define                         pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
-#define                         pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
-#define                        pSPI0_STAT ((volatile unsigned short *)SPI0_STAT)
-#define                        pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
-#define                        pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
-#define                        pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
-#define                      pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define                      pTWI0_CLKDIV ((volatile unsigned short *)TWI0_CLKDIV)
-#define                     pTWI0_CONTROL ((volatile unsigned short *)TWI0_CONTROL)
-#define                   pTWI0_SLAVE_CTL ((volatile unsigned short *)TWI0_SLAVE_CTL)
-#define                  pTWI0_SLAVE_STAT ((volatile unsigned short *)TWI0_SLAVE_STAT)
-#define                  pTWI0_SLAVE_ADDR ((volatile unsigned short *)TWI0_SLAVE_ADDR)
-#define                  pTWI0_MASTER_CTL ((volatile unsigned short *)TWI0_MASTER_CTL)
-#define                 pTWI0_MASTER_STAT ((volatile unsigned short *)TWI0_MASTER_STAT)
-#define                 pTWI0_MASTER_ADDR ((volatile unsigned short *)TWI0_MASTER_ADDR)
-#define                    pTWI0_INT_STAT ((volatile unsigned short *)TWI0_INT_STAT)
-#define                    pTWI0_INT_MASK ((volatile unsigned short *)TWI0_INT_MASK)
-#define                    pTWI0_FIFO_CTL ((volatile unsigned short *)TWI0_FIFO_CTL)
-#define                   pTWI0_FIFO_STAT ((volatile unsigned short *)TWI0_FIFO_STAT)
-#define                   pTWI0_XMT_DATA8 ((volatile unsigned short *)TWI0_XMT_DATA8)
-#define                  pTWI0_XMT_DATA16 ((volatile unsigned short *)TWI0_XMT_DATA16)
-#define                   pTWI0_RCV_DATA8 ((volatile unsigned short *)TWI0_RCV_DATA8)
-#define                  pTWI0_RCV_DATA16 ((volatile unsigned short *)TWI0_RCV_DATA16)
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define                      pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
-#define                      pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
-#define                   pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
-#define                    pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
-#define                        pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
-#define                        pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
-#define                      pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
-#define                      pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
-#define                   pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
-#define                    pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
-#define                      pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
-#define                      pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
-#define                     pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
-#define                     pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
-#define                     pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
-#define                     pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
-#define                     pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
-#define                     pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
-#define                     pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
-#define                     pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
-#define                     pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
-#define                     pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
-
-/* Asynchronous Memory Control Registers */
-
-#define                      pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
-#define                     pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
-#define                     pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
-#define                      pEBIU_MBSCTL ((volatile unsigned long *)EBIU_MBSCTL)
-#define                     pEBIU_ARBSTAT ((volatile unsigned long *)EBIU_ARBSTAT)
-#define                        pEBIU_MODE ((volatile unsigned long *)EBIU_MODE)
-#define                        pEBIU_FCTL ((volatile unsigned long *)EBIU_FCTL)
-
-/* DDR Memory Control Registers */
-
-#define                     pEBIU_DDRCTL0 ((volatile unsigned long *)EBIU_DDRCTL0)
-#define                     pEBIU_DDRCTL1 ((volatile unsigned long *)EBIU_DDRCTL1)
-#define                     pEBIU_DDRCTL2 ((volatile unsigned long *)EBIU_DDRCTL2)
-#define                     pEBIU_DDRCTL3 ((volatile unsigned long *)EBIU_DDRCTL3)
-#define                      pEBIU_DDRQUE ((volatile unsigned long *)EBIU_DDRQUE)
-#define                      pEBIU_ERRADD ((void *volatile *)EBIU_ERRADD)
-#define                      pEBIU_ERRMST ((volatile unsigned short *)EBIU_ERRMST)
-#define                      pEBIU_RSTCTL ((volatile unsigned short *)EBIU_RSTCTL)
-
-/* DDR BankRead and Write Count Registers */
-
-#define                     pEBIU_DDRBRC0 ((volatile unsigned long *)EBIU_DDRBRC0)
-#define                     pEBIU_DDRBRC1 ((volatile unsigned long *)EBIU_DDRBRC1)
-#define                     pEBIU_DDRBRC2 ((volatile unsigned long *)EBIU_DDRBRC2)
-#define                     pEBIU_DDRBRC3 ((volatile unsigned long *)EBIU_DDRBRC3)
-#define                     pEBIU_DDRBRC4 ((volatile unsigned long *)EBIU_DDRBRC4)
-#define                     pEBIU_DDRBRC5 ((volatile unsigned long *)EBIU_DDRBRC5)
-#define                     pEBIU_DDRBRC6 ((volatile unsigned long *)EBIU_DDRBRC6)
-#define                     pEBIU_DDRBRC7 ((volatile unsigned long *)EBIU_DDRBRC7)
-#define                     pEBIU_DDRBWC0 ((volatile unsigned long *)EBIU_DDRBWC0)
-#define                     pEBIU_DDRBWC1 ((volatile unsigned long *)EBIU_DDRBWC1)
-#define                     pEBIU_DDRBWC2 ((volatile unsigned long *)EBIU_DDRBWC2)
-#define                     pEBIU_DDRBWC3 ((volatile unsigned long *)EBIU_DDRBWC3)
-#define                     pEBIU_DDRBWC4 ((volatile unsigned long *)EBIU_DDRBWC4)
-#define                     pEBIU_DDRBWC5 ((volatile unsigned long *)EBIU_DDRBWC5)
-#define                     pEBIU_DDRBWC6 ((volatile unsigned long *)EBIU_DDRBWC6)
-#define                     pEBIU_DDRBWC7 ((volatile unsigned long *)EBIU_DDRBWC7)
-#define                     pEBIU_DDRACCT ((volatile unsigned long *)EBIU_DDRACCT)
-#define                     pEBIU_DDRTACT ((volatile unsigned long *)EBIU_DDRTACT)
-#define                     pEBIU_DDRARCT ((volatile unsigned long *)EBIU_DDRARCT)
-#define                      pEBIU_DDRGC0 ((volatile unsigned long *)EBIU_DDRGC0)
-#define                      pEBIU_DDRGC1 ((volatile unsigned long *)EBIU_DDRGC1)
-#define                      pEBIU_DDRGC2 ((volatile unsigned long *)EBIU_DDRGC2)
-#define                      pEBIU_DDRGC3 ((volatile unsigned long *)EBIU_DDRGC3)
-#define                     pEBIU_DDRMCEN ((volatile unsigned long *)EBIU_DDRMCEN)
-#define                     pEBIU_DDRMCCL ((volatile unsigned long *)EBIU_DDRMCCL)
-
-/* DMAC0 Registers */
-
-#define                      pDMAC0_TCPER ((volatile unsigned short *)DMAC0_TCPER)
-#define                      pDMAC0_TCCNT ((volatile unsigned short *)DMAC0_TCCNT)
-
-/* DMA Channel 0 Registers */
-
-#define               pDMA0_NEXT_DESC_PTR ((void *volatile *)DMA0_NEXT_DESC_PTR)
-#define                  pDMA0_START_ADDR ((void *volatile *)DMA0_START_ADDR)
-#define                      pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
-#define                     pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
-#define                    pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
-#define                     pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
-#define                    pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
-#define               pDMA0_CURR_DESC_PTR ((void *volatile *)DMA0_CURR_DESC_PTR)
-#define                   pDMA0_CURR_ADDR ((void *volatile *)DMA0_CURR_ADDR)
-#define                  pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
-#define              pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
-#define                pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
-#define                pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
-
-/* DMA Channel 1 Registers */
-
-#define               pDMA1_NEXT_DESC_PTR ((void *volatile *)DMA1_NEXT_DESC_PTR)
-#define                  pDMA1_START_ADDR ((void *volatile *)DMA1_START_ADDR)
-#define                      pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
-#define                     pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
-#define                    pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
-#define                     pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
-#define                    pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
-#define               pDMA1_CURR_DESC_PTR ((void *volatile *)DMA1_CURR_DESC_PTR)
-#define                   pDMA1_CURR_ADDR ((void *volatile *)DMA1_CURR_ADDR)
-#define                  pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
-#define              pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
-#define                pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
-#define                pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
-
-/* DMA Channel 2 Registers */
-
-#define               pDMA2_NEXT_DESC_PTR ((void *volatile *)DMA2_NEXT_DESC_PTR)
-#define                  pDMA2_START_ADDR ((void *volatile *)DMA2_START_ADDR)
-#define                      pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
-#define                     pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
-#define                    pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
-#define                     pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
-#define                    pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
-#define               pDMA2_CURR_DESC_PTR ((void *volatile *)DMA2_CURR_DESC_PTR)
-#define                   pDMA2_CURR_ADDR ((void *volatile *)DMA2_CURR_ADDR)
-#define                  pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
-#define              pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
-#define                pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
-#define                pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
-
-/* DMA Channel 3 Registers */
-
-#define               pDMA3_NEXT_DESC_PTR ((void *volatile *)DMA3_NEXT_DESC_PTR)
-#define                  pDMA3_START_ADDR ((void *volatile *)DMA3_START_ADDR)
-#define                      pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
-#define                     pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
-#define                    pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
-#define                     pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
-#define                    pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
-#define               pDMA3_CURR_DESC_PTR ((void *volatile *)DMA3_CURR_DESC_PTR)
-#define                   pDMA3_CURR_ADDR ((void *volatile *)DMA3_CURR_ADDR)
-#define                  pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
-#define              pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
-#define                pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
-#define                pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
-
-/* DMA Channel 4 Registers */
-
-#define               pDMA4_NEXT_DESC_PTR ((void *volatile *)DMA4_NEXT_DESC_PTR)
-#define                  pDMA4_START_ADDR ((void *volatile *)DMA4_START_ADDR)
-#define                      pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
-#define                     pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
-#define                    pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
-#define                     pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
-#define                    pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
-#define               pDMA4_CURR_DESC_PTR ((void *volatile *)DMA4_CURR_DESC_PTR)
-#define                   pDMA4_CURR_ADDR ((void *volatile *)DMA4_CURR_ADDR)
-#define                  pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
-#define              pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
-#define                pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
-#define                pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
-
-/* DMA Channel 5 Registers */
-
-#define               pDMA5_NEXT_DESC_PTR ((void *volatile *)DMA5_NEXT_DESC_PTR)
-#define                  pDMA5_START_ADDR ((void *volatile *)DMA5_START_ADDR)
-#define                      pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
-#define                     pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
-#define                    pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
-#define                     pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
-#define                    pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
-#define               pDMA5_CURR_DESC_PTR ((void *volatile *)DMA5_CURR_DESC_PTR)
-#define                   pDMA5_CURR_ADDR ((void *volatile *)DMA5_CURR_ADDR)
-#define                  pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
-#define              pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
-#define                pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
-#define                pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
-
-/* DMA Channel 6 Registers */
-
-#define               pDMA6_NEXT_DESC_PTR ((void *volatile *)DMA6_NEXT_DESC_PTR)
-#define                  pDMA6_START_ADDR ((void *volatile *)DMA6_START_ADDR)
-#define                      pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
-#define                     pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
-#define                    pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
-#define                     pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
-#define                    pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
-#define               pDMA6_CURR_DESC_PTR ((void *volatile *)DMA6_CURR_DESC_PTR)
-#define                   pDMA6_CURR_ADDR ((void *volatile *)DMA6_CURR_ADDR)
-#define                  pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
-#define              pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
-#define                pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
-#define                pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
-
-/* DMA Channel 7 Registers */
-
-#define               pDMA7_NEXT_DESC_PTR ((void *volatile *)DMA7_NEXT_DESC_PTR)
-#define                  pDMA7_START_ADDR ((void *volatile *)DMA7_START_ADDR)
-#define                      pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
-#define                     pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
-#define                    pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
-#define                     pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
-#define                    pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
-#define               pDMA7_CURR_DESC_PTR ((void *volatile *)DMA7_CURR_DESC_PTR)
-#define                   pDMA7_CURR_ADDR ((void *volatile *)DMA7_CURR_ADDR)
-#define                  pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
-#define              pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
-#define                pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
-#define                pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
-
-/* DMA Channel 8 Registers */
-
-#define               pDMA8_NEXT_DESC_PTR ((void *volatile *)DMA8_NEXT_DESC_PTR)
-#define                  pDMA8_START_ADDR ((void *volatile *)DMA8_START_ADDR)
-#define                      pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
-#define                     pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
-#define                    pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
-#define                     pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
-#define                    pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
-#define               pDMA8_CURR_DESC_PTR ((void *volatile *)DMA8_CURR_DESC_PTR)
-#define                   pDMA8_CURR_ADDR ((void *volatile *)DMA8_CURR_ADDR)
-#define                  pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
-#define              pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
-#define                pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
-#define                pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
-
-/* DMA Channel 9 Registers */
-
-#define               pDMA9_NEXT_DESC_PTR ((void *volatile *)DMA9_NEXT_DESC_PTR)
-#define                  pDMA9_START_ADDR ((void *volatile *)DMA9_START_ADDR)
-#define                      pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
-#define                     pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
-#define                    pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
-#define                     pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
-#define                    pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
-#define               pDMA9_CURR_DESC_PTR ((void *volatile *)DMA9_CURR_DESC_PTR)
-#define                   pDMA9_CURR_ADDR ((void *volatile *)DMA9_CURR_ADDR)
-#define                  pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
-#define              pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
-#define                pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
-#define                pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
-
-/* DMA Channel 10 Registers */
-
-#define              pDMA10_NEXT_DESC_PTR ((void *volatile *)DMA10_NEXT_DESC_PTR)
-#define                 pDMA10_START_ADDR ((void *volatile *)DMA10_START_ADDR)
-#define                     pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
-#define                    pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
-#define                   pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
-#define                    pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
-#define                   pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
-#define              pDMA10_CURR_DESC_PTR ((void *volatile *)DMA10_CURR_DESC_PTR)
-#define                  pDMA10_CURR_ADDR ((void *volatile *)DMA10_CURR_ADDR)
-#define                 pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
-#define             pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
-#define               pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
-#define               pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
-
-/* DMA Channel 11 Registers */
-
-#define              pDMA11_NEXT_DESC_PTR ((void *volatile *)DMA11_NEXT_DESC_PTR)
-#define                 pDMA11_START_ADDR ((void *volatile *)DMA11_START_ADDR)
-#define                     pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
-#define                    pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
-#define                   pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
-#define                    pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
-#define                   pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
-#define              pDMA11_CURR_DESC_PTR ((void *volatile *)DMA11_CURR_DESC_PTR)
-#define                  pDMA11_CURR_ADDR ((void *volatile *)DMA11_CURR_ADDR)
-#define                 pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
-#define             pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
-#define               pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
-#define               pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
-
-/* MDMA Stream 0 Registers */
-
-#define            pMDMA_D0_NEXT_DESC_PTR ((void *volatile *)MDMA_D0_NEXT_DESC_PTR)
-#define               pMDMA_D0_START_ADDR ((void *volatile *)MDMA_D0_START_ADDR)
-#define                   pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
-#define                  pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
-#define                 pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
-#define                  pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
-#define                 pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
-#define            pMDMA_D0_CURR_DESC_PTR ((void *volatile *)MDMA_D0_CURR_DESC_PTR)
-#define                pMDMA_D0_CURR_ADDR ((void *volatile *)MDMA_D0_CURR_ADDR)
-#define               pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
-#define           pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
-#define             pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
-#define             pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
-#define            pMDMA_S0_NEXT_DESC_PTR ((void *volatile *)MDMA_S0_NEXT_DESC_PTR)
-#define               pMDMA_S0_START_ADDR ((void *volatile *)MDMA_S0_START_ADDR)
-#define                   pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
-#define                  pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
-#define                 pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
-#define                  pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
-#define                 pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
-#define            pMDMA_S0_CURR_DESC_PTR ((void *volatile *)MDMA_S0_CURR_DESC_PTR)
-#define                pMDMA_S0_CURR_ADDR ((void *volatile *)MDMA_S0_CURR_ADDR)
-#define               pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
-#define           pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
-#define             pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
-#define             pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
-
-/* MDMA Stream 1 Registers */
-
-#define            pMDMA_D1_NEXT_DESC_PTR ((void *volatile *)MDMA_D1_NEXT_DESC_PTR)
-#define               pMDMA_D1_START_ADDR ((void *volatile *)MDMA_D1_START_ADDR)
-#define                   pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
-#define                  pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
-#define                 pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
-#define                  pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
-#define                 pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
-#define            pMDMA_D1_CURR_DESC_PTR ((void *volatile *)MDMA_D1_CURR_DESC_PTR)
-#define                pMDMA_D1_CURR_ADDR ((void *volatile *)MDMA_D1_CURR_ADDR)
-#define               pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
-#define           pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
-#define             pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
-#define             pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
-#define            pMDMA_S1_NEXT_DESC_PTR ((void *volatile *)MDMA_S1_NEXT_DESC_PTR)
-#define               pMDMA_S1_START_ADDR ((void *volatile *)MDMA_S1_START_ADDR)
-#define                   pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
-#define                  pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
-#define                 pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
-#define                  pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
-#define                 pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
-#define            pMDMA_S1_CURR_DESC_PTR ((void *volatile *)MDMA_S1_CURR_DESC_PTR)
-#define                pMDMA_S1_CURR_ADDR ((void *volatile *)MDMA_S1_CURR_ADDR)
-#define               pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
-#define           pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
-#define             pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
-#define             pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
-
-/* EPPI1 Registers */
-
-#define                     pEPPI1_STATUS ((volatile unsigned short *)EPPI1_STATUS)
-#define                     pEPPI1_HCOUNT ((volatile unsigned short *)EPPI1_HCOUNT)
-#define                     pEPPI1_HDELAY ((volatile unsigned short *)EPPI1_HDELAY)
-#define                     pEPPI1_VCOUNT ((volatile unsigned short *)EPPI1_VCOUNT)
-#define                     pEPPI1_VDELAY ((volatile unsigned short *)EPPI1_VDELAY)
-#define                      pEPPI1_FRAME ((volatile unsigned short *)EPPI1_FRAME)
-#define                       pEPPI1_LINE ((volatile unsigned short *)EPPI1_LINE)
-#define                     pEPPI1_CLKDIV ((volatile unsigned short *)EPPI1_CLKDIV)
-#define                    pEPPI1_CONTROL ((volatile unsigned long *)EPPI1_CONTROL)
-#define                   pEPPI1_FS1W_HBL ((volatile unsigned long *)EPPI1_FS1W_HBL)
-#define                  pEPPI1_FS1P_AVPL ((volatile unsigned long *)EPPI1_FS1P_AVPL)
-#define                   pEPPI1_FS2W_LVB ((volatile unsigned long *)EPPI1_FS2W_LVB)
-#define                  pEPPI1_FS2P_LAVF ((volatile unsigned long *)EPPI1_FS2P_LAVF)
-#define                       pEPPI1_CLIP ((volatile unsigned long *)EPPI1_CLIP)
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define                   pPINT0_MASK_SET ((volatile unsigned long *)PINT0_MASK_SET)
-#define                 pPINT0_MASK_CLEAR ((volatile unsigned long *)PINT0_MASK_CLEAR)
-#define                    pPINT0_REQUEST ((volatile unsigned long *)PINT0_REQUEST)
-#define                     pPINT0_ASSIGN ((volatile unsigned long *)PINT0_ASSIGN)
-#define                   pPINT0_EDGE_SET ((volatile unsigned long *)PINT0_EDGE_SET)
-#define                 pPINT0_EDGE_CLEAR ((volatile unsigned long *)PINT0_EDGE_CLEAR)
-#define                 pPINT0_INVERT_SET ((volatile unsigned long *)PINT0_INVERT_SET)
-#define               pPINT0_INVERT_CLEAR ((volatile unsigned long *)PINT0_INVERT_CLEAR)
-#define                   pPINT0_PINSTATE ((volatile unsigned long *)PINT0_PINSTATE)
-#define                      pPINT0_LATCH ((volatile unsigned long *)PINT0_LATCH)
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define                   pPINT1_MASK_SET ((volatile unsigned long *)PINT1_MASK_SET)
-#define                 pPINT1_MASK_CLEAR ((volatile unsigned long *)PINT1_MASK_CLEAR)
-#define                    pPINT1_REQUEST ((volatile unsigned long *)PINT1_REQUEST)
-#define                     pPINT1_ASSIGN ((volatile unsigned long *)PINT1_ASSIGN)
-#define                   pPINT1_EDGE_SET ((volatile unsigned long *)PINT1_EDGE_SET)
-#define                 pPINT1_EDGE_CLEAR ((volatile unsigned long *)PINT1_EDGE_CLEAR)
-#define                 pPINT1_INVERT_SET ((volatile unsigned long *)PINT1_INVERT_SET)
-#define               pPINT1_INVERT_CLEAR ((volatile unsigned long *)PINT1_INVERT_CLEAR)
-#define                   pPINT1_PINSTATE ((volatile unsigned long *)PINT1_PINSTATE)
-#define                      pPINT1_LATCH ((volatile unsigned long *)PINT1_LATCH)
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define                   pPINT2_MASK_SET ((volatile unsigned long *)PINT2_MASK_SET)
-#define                 pPINT2_MASK_CLEAR ((volatile unsigned long *)PINT2_MASK_CLEAR)
-#define                    pPINT2_REQUEST ((volatile unsigned long *)PINT2_REQUEST)
-#define                     pPINT2_ASSIGN ((volatile unsigned long *)PINT2_ASSIGN)
-#define                   pPINT2_EDGE_SET ((volatile unsigned long *)PINT2_EDGE_SET)
-#define                 pPINT2_EDGE_CLEAR ((volatile unsigned long *)PINT2_EDGE_CLEAR)
-#define                 pPINT2_INVERT_SET ((volatile unsigned long *)PINT2_INVERT_SET)
-#define               pPINT2_INVERT_CLEAR ((volatile unsigned long *)PINT2_INVERT_CLEAR)
-#define                   pPINT2_PINSTATE ((volatile unsigned long *)PINT2_PINSTATE)
-#define                      pPINT2_LATCH ((volatile unsigned long *)PINT2_LATCH)
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define                   pPINT3_MASK_SET ((volatile unsigned long *)PINT3_MASK_SET)
-#define                 pPINT3_MASK_CLEAR ((volatile unsigned long *)PINT3_MASK_CLEAR)
-#define                    pPINT3_REQUEST ((volatile unsigned long *)PINT3_REQUEST)
-#define                     pPINT3_ASSIGN ((volatile unsigned long *)PINT3_ASSIGN)
-#define                   pPINT3_EDGE_SET ((volatile unsigned long *)PINT3_EDGE_SET)
-#define                 pPINT3_EDGE_CLEAR ((volatile unsigned long *)PINT3_EDGE_CLEAR)
-#define                 pPINT3_INVERT_SET ((volatile unsigned long *)PINT3_INVERT_SET)
-#define               pPINT3_INVERT_CLEAR ((volatile unsigned long *)PINT3_INVERT_CLEAR)
-#define                   pPINT3_PINSTATE ((volatile unsigned long *)PINT3_PINSTATE)
-#define                      pPINT3_LATCH ((volatile unsigned long *)PINT3_LATCH)
-
-/* Port A Registers */
-
-#define                        pPORTA_FER ((volatile unsigned short *)PORTA_FER)
-#define                            pPORTA ((volatile unsigned short *)PORTA)
-#define                        pPORTA_SET ((volatile unsigned short *)PORTA_SET)
-#define                      pPORTA_CLEAR ((volatile unsigned short *)PORTA_CLEAR)
-#define                    pPORTA_DIR_SET ((volatile unsigned short *)PORTA_DIR_SET)
-#define                  pPORTA_DIR_CLEAR ((volatile unsigned short *)PORTA_DIR_CLEAR)
-#define                       pPORTA_INEN ((volatile unsigned short *)PORTA_INEN)
-#define                        pPORTA_MUX ((volatile unsigned long *)PORTA_MUX)
-
-/* Port B Registers */
-
-#define                        pPORTB_FER ((volatile unsigned short *)PORTB_FER)
-#define                            pPORTB ((volatile unsigned short *)PORTB)
-#define                        pPORTB_SET ((volatile unsigned short *)PORTB_SET)
-#define                      pPORTB_CLEAR ((volatile unsigned short *)PORTB_CLEAR)
-#define                    pPORTB_DIR_SET ((volatile unsigned short *)PORTB_DIR_SET)
-#define                  pPORTB_DIR_CLEAR ((volatile unsigned short *)PORTB_DIR_CLEAR)
-#define                       pPORTB_INEN ((volatile unsigned short *)PORTB_INEN)
-#define                        pPORTB_MUX ((volatile unsigned long *)PORTB_MUX)
-
-/* Port C Registers */
-
-#define                        pPORTC_FER ((volatile unsigned short *)PORTC_FER)
-#define                            pPORTC ((volatile unsigned short *)PORTC)
-#define                        pPORTC_SET ((volatile unsigned short *)PORTC_SET)
-#define                      pPORTC_CLEAR ((volatile unsigned short *)PORTC_CLEAR)
-#define                    pPORTC_DIR_SET ((volatile unsigned short *)PORTC_DIR_SET)
-#define                  pPORTC_DIR_CLEAR ((volatile unsigned short *)PORTC_DIR_CLEAR)
-#define                       pPORTC_INEN ((volatile unsigned short *)PORTC_INEN)
-#define                        pPORTC_MUX ((volatile unsigned long *)PORTC_MUX)
-
-/* Port D Registers */
-
-#define                        pPORTD_FER ((volatile unsigned short *)PORTD_FER)
-#define                            pPORTD ((volatile unsigned short *)PORTD)
-#define                        pPORTD_SET ((volatile unsigned short *)PORTD_SET)
-#define                      pPORTD_CLEAR ((volatile unsigned short *)PORTD_CLEAR)
-#define                    pPORTD_DIR_SET ((volatile unsigned short *)PORTD_DIR_SET)
-#define                  pPORTD_DIR_CLEAR ((volatile unsigned short *)PORTD_DIR_CLEAR)
-#define                       pPORTD_INEN ((volatile unsigned short *)PORTD_INEN)
-#define                        pPORTD_MUX ((volatile unsigned long *)PORTD_MUX)
-
-/* Port E Registers */
-
-#define                        pPORTE_FER ((volatile unsigned short *)PORTE_FER)
-#define                            pPORTE ((volatile unsigned short *)PORTE)
-#define                        pPORTE_SET ((volatile unsigned short *)PORTE_SET)
-#define                      pPORTE_CLEAR ((volatile unsigned short *)PORTE_CLEAR)
-#define                    pPORTE_DIR_SET ((volatile unsigned short *)PORTE_DIR_SET)
-#define                  pPORTE_DIR_CLEAR ((volatile unsigned short *)PORTE_DIR_CLEAR)
-#define                       pPORTE_INEN ((volatile unsigned short *)PORTE_INEN)
-#define                        pPORTE_MUX ((volatile unsigned long *)PORTE_MUX)
-
-/* Port F Registers */
-
-#define                        pPORTF_FER ((volatile unsigned short *)PORTF_FER)
-#define                            pPORTF ((volatile unsigned short *)PORTF)
-#define                        pPORTF_SET ((volatile unsigned short *)PORTF_SET)
-#define                      pPORTF_CLEAR ((volatile unsigned short *)PORTF_CLEAR)
-#define                    pPORTF_DIR_SET ((volatile unsigned short *)PORTF_DIR_SET)
-#define                  pPORTF_DIR_CLEAR ((volatile unsigned short *)PORTF_DIR_CLEAR)
-#define                       pPORTF_INEN ((volatile unsigned short *)PORTF_INEN)
-#define                        pPORTF_MUX ((volatile unsigned long *)PORTF_MUX)
-
-/* Port G Registers */
-
-#define                        pPORTG_FER ((volatile unsigned short *)PORTG_FER)
-#define                            pPORTG ((volatile unsigned short *)PORTG)
-#define                        pPORTG_SET ((volatile unsigned short *)PORTG_SET)
-#define                      pPORTG_CLEAR ((volatile unsigned short *)PORTG_CLEAR)
-#define                    pPORTG_DIR_SET ((volatile unsigned short *)PORTG_DIR_SET)
-#define                  pPORTG_DIR_CLEAR ((volatile unsigned short *)PORTG_DIR_CLEAR)
-#define                       pPORTG_INEN ((volatile unsigned short *)PORTG_INEN)
-#define                        pPORTG_MUX ((volatile unsigned long *)PORTG_MUX)
-
-/* Port H Registers */
-
-#define                        pPORTH_FER ((volatile unsigned short *)PORTH_FER)
-#define                            pPORTH ((volatile unsigned short *)PORTH)
-#define                        pPORTH_SET ((volatile unsigned short *)PORTH_SET)
-#define                      pPORTH_CLEAR ((volatile unsigned short *)PORTH_CLEAR)
-#define                    pPORTH_DIR_SET ((volatile unsigned short *)PORTH_DIR_SET)
-#define                  pPORTH_DIR_CLEAR ((volatile unsigned short *)PORTH_DIR_CLEAR)
-#define                       pPORTH_INEN ((volatile unsigned short *)PORTH_INEN)
-#define                        pPORTH_MUX ((volatile unsigned long *)PORTH_MUX)
-
-/* Port I Registers */
-
-#define                        pPORTI_FER ((volatile unsigned short *)PORTI_FER)
-#define                            pPORTI ((volatile unsigned short *)PORTI)
-#define                        pPORTI_SET ((volatile unsigned short *)PORTI_SET)
-#define                      pPORTI_CLEAR ((volatile unsigned short *)PORTI_CLEAR)
-#define                    pPORTI_DIR_SET ((volatile unsigned short *)PORTI_DIR_SET)
-#define                  pPORTI_DIR_CLEAR ((volatile unsigned short *)PORTI_DIR_CLEAR)
-#define                       pPORTI_INEN ((volatile unsigned short *)PORTI_INEN)
-#define                        pPORTI_MUX ((volatile unsigned long *)PORTI_MUX)
-
-/* Port J Registers */
-
-#define                        pPORTJ_FER ((volatile unsigned short *)PORTJ_FER)
-#define                            pPORTJ ((volatile unsigned short *)PORTJ)
-#define                        pPORTJ_SET ((volatile unsigned short *)PORTJ_SET)
-#define                      pPORTJ_CLEAR ((volatile unsigned short *)PORTJ_CLEAR)
-#define                    pPORTJ_DIR_SET ((volatile unsigned short *)PORTJ_DIR_SET)
-#define                  pPORTJ_DIR_CLEAR ((volatile unsigned short *)PORTJ_DIR_CLEAR)
-#define                       pPORTJ_INEN ((volatile unsigned short *)PORTJ_INEN)
-#define                        pPORTJ_MUX ((volatile unsigned long *)PORTJ_MUX)
-
-/* PWM Timer Registers */
-
-#define                    pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
-#define                   pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
-#define                    pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
-#define                     pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
-#define                    pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
-#define                   pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
-#define                    pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
-#define                     pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
-#define                    pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
-#define                   pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
-#define                    pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
-#define                     pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
-#define                    pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
-#define                   pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
-#define                    pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
-#define                     pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
-#define                    pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
-#define                   pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
-#define                    pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
-#define                     pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
-#define                    pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
-#define                   pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
-#define                    pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
-#define                     pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
-#define                    pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
-#define                   pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
-#define                    pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
-#define                     pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
-#define                    pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
-#define                   pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
-#define                    pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
-#define                     pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
-
-/* Timer Group of 8 */
-
-#define                    pTIMER_ENABLE0 ((volatile unsigned short *)TIMER_ENABLE0)
-#define                   pTIMER_DISABLE0 ((volatile unsigned short *)TIMER_DISABLE0)
-#define                    pTIMER_STATUS0 ((volatile unsigned long *)TIMER_STATUS0)
-
-/* DMAC1 Registers */
-
-#define                      pDMAC1_TCPER ((volatile unsigned short *)DMAC1_TCPER)
-#define                      pDMAC1_TCCNT ((volatile unsigned short *)DMAC1_TCCNT)
-
-/* DMA Channel 12 Registers */
-
-#define              pDMA12_NEXT_DESC_PTR ((void *volatile *)DMA12_NEXT_DESC_PTR)
-#define                 pDMA12_START_ADDR ((void *volatile *)DMA12_START_ADDR)
-#define                     pDMA12_CONFIG ((volatile unsigned short *)DMA12_CONFIG)
-#define                    pDMA12_X_COUNT ((volatile unsigned short *)DMA12_X_COUNT)
-#define                   pDMA12_X_MODIFY ((volatile signed short *)DMA12_X_MODIFY)
-#define                    pDMA12_Y_COUNT ((volatile unsigned short *)DMA12_Y_COUNT)
-#define                   pDMA12_Y_MODIFY ((volatile signed short *)DMA12_Y_MODIFY)
-#define              pDMA12_CURR_DESC_PTR ((void *volatile *)DMA12_CURR_DESC_PTR)
-#define                  pDMA12_CURR_ADDR ((void *volatile *)DMA12_CURR_ADDR)
-#define                 pDMA12_IRQ_STATUS ((volatile unsigned short *)DMA12_IRQ_STATUS)
-#define             pDMA12_PERIPHERAL_MAP ((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
-#define               pDMA12_CURR_X_COUNT ((volatile unsigned short *)DMA12_CURR_X_COUNT)
-#define               pDMA12_CURR_Y_COUNT ((volatile unsigned short *)DMA12_CURR_Y_COUNT)
-
-/* DMA Channel 13 Registers */
-
-#define              pDMA13_NEXT_DESC_PTR ((void *volatile *)DMA13_NEXT_DESC_PTR)
-#define                 pDMA13_START_ADDR ((void *volatile *)DMA13_START_ADDR)
-#define                     pDMA13_CONFIG ((volatile unsigned short *)DMA13_CONFIG)
-#define                    pDMA13_X_COUNT ((volatile unsigned short *)DMA13_X_COUNT)
-#define                   pDMA13_X_MODIFY ((volatile signed short *)DMA13_X_MODIFY)
-#define                    pDMA13_Y_COUNT ((volatile unsigned short *)DMA13_Y_COUNT)
-#define                   pDMA13_Y_MODIFY ((volatile signed short *)DMA13_Y_MODIFY)
-#define              pDMA13_CURR_DESC_PTR ((void *volatile *)DMA13_CURR_DESC_PTR)
-#define                  pDMA13_CURR_ADDR ((void *volatile *)DMA13_CURR_ADDR)
-#define                 pDMA13_IRQ_STATUS ((volatile unsigned short *)DMA13_IRQ_STATUS)
-#define             pDMA13_PERIPHERAL_MAP ((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
-#define               pDMA13_CURR_X_COUNT ((volatile unsigned short *)DMA13_CURR_X_COUNT)
-#define               pDMA13_CURR_Y_COUNT ((volatile unsigned short *)DMA13_CURR_Y_COUNT)
-
-/* DMA Channel 14 Registers */
-
-#define              pDMA14_NEXT_DESC_PTR ((void *volatile *)DMA14_NEXT_DESC_PTR)
-#define                 pDMA14_START_ADDR ((void *volatile *)DMA14_START_ADDR)
-#define                     pDMA14_CONFIG ((volatile unsigned short *)DMA14_CONFIG)
-#define                    pDMA14_X_COUNT ((volatile unsigned short *)DMA14_X_COUNT)
-#define                   pDMA14_X_MODIFY ((volatile signed short *)DMA14_X_MODIFY)
-#define                    pDMA14_Y_COUNT ((volatile unsigned short *)DMA14_Y_COUNT)
-#define                   pDMA14_Y_MODIFY ((volatile signed short *)DMA14_Y_MODIFY)
-#define              pDMA14_CURR_DESC_PTR ((void *volatile *)DMA14_CURR_DESC_PTR)
-#define                  pDMA14_CURR_ADDR ((void *volatile *)DMA14_CURR_ADDR)
-#define                 pDMA14_IRQ_STATUS ((volatile unsigned short *)DMA14_IRQ_STATUS)
-#define             pDMA14_PERIPHERAL_MAP ((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
-#define               pDMA14_CURR_X_COUNT ((volatile unsigned short *)DMA14_CURR_X_COUNT)
-#define               pDMA14_CURR_Y_COUNT ((volatile unsigned short *)DMA14_CURR_Y_COUNT)
-
-/* DMA Channel 15 Registers */
-
-#define              pDMA15_NEXT_DESC_PTR ((void *volatile *)DMA15_NEXT_DESC_PTR)
-#define                 pDMA15_START_ADDR ((void *volatile *)DMA15_START_ADDR)
-#define                     pDMA15_CONFIG ((volatile unsigned short *)DMA15_CONFIG)
-#define                    pDMA15_X_COUNT ((volatile unsigned short *)DMA15_X_COUNT)
-#define                   pDMA15_X_MODIFY ((volatile signed short *)DMA15_X_MODIFY)
-#define                    pDMA15_Y_COUNT ((volatile unsigned short *)DMA15_Y_COUNT)
-#define                   pDMA15_Y_MODIFY ((volatile signed short *)DMA15_Y_MODIFY)
-#define              pDMA15_CURR_DESC_PTR ((void *volatile *)DMA15_CURR_DESC_PTR)
-#define                  pDMA15_CURR_ADDR ((void *volatile *)DMA15_CURR_ADDR)
-#define                 pDMA15_IRQ_STATUS ((volatile unsigned short *)DMA15_IRQ_STATUS)
-#define             pDMA15_PERIPHERAL_MAP ((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
-#define               pDMA15_CURR_X_COUNT ((volatile unsigned short *)DMA15_CURR_X_COUNT)
-#define               pDMA15_CURR_Y_COUNT ((volatile unsigned short *)DMA15_CURR_Y_COUNT)
-
-/* DMA Channel 16 Registers */
-
-#define              pDMA16_NEXT_DESC_PTR ((void *volatile *)DMA16_NEXT_DESC_PTR)
-#define                 pDMA16_START_ADDR ((void *volatile *)DMA16_START_ADDR)
-#define                     pDMA16_CONFIG ((volatile unsigned short *)DMA16_CONFIG)
-#define                    pDMA16_X_COUNT ((volatile unsigned short *)DMA16_X_COUNT)
-#define                   pDMA16_X_MODIFY ((volatile signed short *)DMA16_X_MODIFY)
-#define                    pDMA16_Y_COUNT ((volatile unsigned short *)DMA16_Y_COUNT)
-#define                   pDMA16_Y_MODIFY ((volatile signed short *)DMA16_Y_MODIFY)
-#define              pDMA16_CURR_DESC_PTR ((void *volatile *)DMA16_CURR_DESC_PTR)
-#define                  pDMA16_CURR_ADDR ((void *volatile *)DMA16_CURR_ADDR)
-#define                 pDMA16_IRQ_STATUS ((volatile unsigned short *)DMA16_IRQ_STATUS)
-#define             pDMA16_PERIPHERAL_MAP ((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
-#define               pDMA16_CURR_X_COUNT ((volatile unsigned short *)DMA16_CURR_X_COUNT)
-#define               pDMA16_CURR_Y_COUNT ((volatile unsigned short *)DMA16_CURR_Y_COUNT)
-
-/* DMA Channel 17 Registers */
-
-#define              pDMA17_NEXT_DESC_PTR ((void *volatile *)DMA17_NEXT_DESC_PTR)
-#define                 pDMA17_START_ADDR ((void *volatile *)DMA17_START_ADDR)
-#define                     pDMA17_CONFIG ((volatile unsigned short *)DMA17_CONFIG)
-#define                    pDMA17_X_COUNT ((volatile unsigned short *)DMA17_X_COUNT)
-#define                   pDMA17_X_MODIFY ((volatile signed short *)DMA17_X_MODIFY)
-#define                    pDMA17_Y_COUNT ((volatile unsigned short *)DMA17_Y_COUNT)
-#define                   pDMA17_Y_MODIFY ((volatile signed short *)DMA17_Y_MODIFY)
-#define              pDMA17_CURR_DESC_PTR ((void *volatile *)DMA17_CURR_DESC_PTR)
-#define                  pDMA17_CURR_ADDR ((void *volatile *)DMA17_CURR_ADDR)
-#define                 pDMA17_IRQ_STATUS ((volatile unsigned short *)DMA17_IRQ_STATUS)
-#define             pDMA17_PERIPHERAL_MAP ((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
-#define               pDMA17_CURR_X_COUNT ((volatile unsigned short *)DMA17_CURR_X_COUNT)
-#define               pDMA17_CURR_Y_COUNT ((volatile unsigned short *)DMA17_CURR_Y_COUNT)
-
-/* DMA Channel 18 Registers */
-
-#define              pDMA18_NEXT_DESC_PTR ((void *volatile *)DMA18_NEXT_DESC_PTR)
-#define                 pDMA18_START_ADDR ((void *volatile *)DMA18_START_ADDR)
-#define                     pDMA18_CONFIG ((volatile unsigned short *)DMA18_CONFIG)
-#define                    pDMA18_X_COUNT ((volatile unsigned short *)DMA18_X_COUNT)
-#define                   pDMA18_X_MODIFY ((volatile signed short *)DMA18_X_MODIFY)
-#define                    pDMA18_Y_COUNT ((volatile unsigned short *)DMA18_Y_COUNT)
-#define                   pDMA18_Y_MODIFY ((volatile signed short *)DMA18_Y_MODIFY)
-#define              pDMA18_CURR_DESC_PTR ((void *volatile *)DMA18_CURR_DESC_PTR)
-#define                  pDMA18_CURR_ADDR ((void *volatile *)DMA18_CURR_ADDR)
-#define                 pDMA18_IRQ_STATUS ((volatile unsigned short *)DMA18_IRQ_STATUS)
-#define             pDMA18_PERIPHERAL_MAP ((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
-#define               pDMA18_CURR_X_COUNT ((volatile unsigned short *)DMA18_CURR_X_COUNT)
-#define               pDMA18_CURR_Y_COUNT ((volatile unsigned short *)DMA18_CURR_Y_COUNT)
-
-/* DMA Channel 19 Registers */
-
-#define              pDMA19_NEXT_DESC_PTR ((void *volatile *)DMA19_NEXT_DESC_PTR)
-#define                 pDMA19_START_ADDR ((void *volatile *)DMA19_START_ADDR)
-#define                     pDMA19_CONFIG ((volatile unsigned short *)DMA19_CONFIG)
-#define                    pDMA19_X_COUNT ((volatile unsigned short *)DMA19_X_COUNT)
-#define                   pDMA19_X_MODIFY ((volatile signed short *)DMA19_X_MODIFY)
-#define                    pDMA19_Y_COUNT ((volatile unsigned short *)DMA19_Y_COUNT)
-#define                   pDMA19_Y_MODIFY ((volatile signed short *)DMA19_Y_MODIFY)
-#define              pDMA19_CURR_DESC_PTR ((void *volatile *)DMA19_CURR_DESC_PTR)
-#define                  pDMA19_CURR_ADDR ((void *volatile *)DMA19_CURR_ADDR)
-#define                 pDMA19_IRQ_STATUS ((volatile unsigned short *)DMA19_IRQ_STATUS)
-#define             pDMA19_PERIPHERAL_MAP ((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
-#define               pDMA19_CURR_X_COUNT ((volatile unsigned short *)DMA19_CURR_X_COUNT)
-#define               pDMA19_CURR_Y_COUNT ((volatile unsigned short *)DMA19_CURR_Y_COUNT)
-
-/* DMA Channel 20 Registers */
-
-#define              pDMA20_NEXT_DESC_PTR ((void *volatile *)DMA20_NEXT_DESC_PTR)
-#define                 pDMA20_START_ADDR ((void *volatile *)DMA20_START_ADDR)
-#define                     pDMA20_CONFIG ((volatile unsigned short *)DMA20_CONFIG)
-#define                    pDMA20_X_COUNT ((volatile unsigned short *)DMA20_X_COUNT)
-#define                   pDMA20_X_MODIFY ((volatile signed short *)DMA20_X_MODIFY)
-#define                    pDMA20_Y_COUNT ((volatile unsigned short *)DMA20_Y_COUNT)
-#define                   pDMA20_Y_MODIFY ((volatile signed short *)DMA20_Y_MODIFY)
-#define              pDMA20_CURR_DESC_PTR ((void *volatile *)DMA20_CURR_DESC_PTR)
-#define                  pDMA20_CURR_ADDR ((void *volatile *)DMA20_CURR_ADDR)
-#define                 pDMA20_IRQ_STATUS ((volatile unsigned short *)DMA20_IRQ_STATUS)
-#define             pDMA20_PERIPHERAL_MAP ((volatile unsigned short *)DMA20_PERIPHERAL_MAP)
-#define               pDMA20_CURR_X_COUNT ((volatile unsigned short *)DMA20_CURR_X_COUNT)
-#define               pDMA20_CURR_Y_COUNT ((volatile unsigned short *)DMA20_CURR_Y_COUNT)
-
-/* DMA Channel 21 Registers */
-
-#define              pDMA21_NEXT_DESC_PTR ((void *volatile *)DMA21_NEXT_DESC_PTR)
-#define                 pDMA21_START_ADDR ((void *volatile *)DMA21_START_ADDR)
-#define                     pDMA21_CONFIG ((volatile unsigned short *)DMA21_CONFIG)
-#define                    pDMA21_X_COUNT ((volatile unsigned short *)DMA21_X_COUNT)
-#define                   pDMA21_X_MODIFY ((volatile signed short *)DMA21_X_MODIFY)
-#define                    pDMA21_Y_COUNT ((volatile unsigned short *)DMA21_Y_COUNT)
-#define                   pDMA21_Y_MODIFY ((volatile signed short *)DMA21_Y_MODIFY)
-#define              pDMA21_CURR_DESC_PTR ((void *volatile *)DMA21_CURR_DESC_PTR)
-#define                  pDMA21_CURR_ADDR ((void *volatile *)DMA21_CURR_ADDR)
-#define                 pDMA21_IRQ_STATUS ((volatile unsigned short *)DMA21_IRQ_STATUS)
-#define             pDMA21_PERIPHERAL_MAP ((volatile unsigned short *)DMA21_PERIPHERAL_MAP)
-#define               pDMA21_CURR_X_COUNT ((volatile unsigned short *)DMA21_CURR_X_COUNT)
-#define               pDMA21_CURR_Y_COUNT ((volatile unsigned short *)DMA21_CURR_Y_COUNT)
-
-/* DMA Channel 22 Registers */
-
-#define              pDMA22_NEXT_DESC_PTR ((void *volatile *)DMA22_NEXT_DESC_PTR)
-#define                 pDMA22_START_ADDR ((void *volatile *)DMA22_START_ADDR)
-#define                     pDMA22_CONFIG ((volatile unsigned short *)DMA22_CONFIG)
-#define                    pDMA22_X_COUNT ((volatile unsigned short *)DMA22_X_COUNT)
-#define                   pDMA22_X_MODIFY ((volatile signed short *)DMA22_X_MODIFY)
-#define                    pDMA22_Y_COUNT ((volatile unsigned short *)DMA22_Y_COUNT)
-#define                   pDMA22_Y_MODIFY ((volatile signed short *)DMA22_Y_MODIFY)
-#define              pDMA22_CURR_DESC_PTR ((void *volatile *)DMA22_CURR_DESC_PTR)
-#define                  pDMA22_CURR_ADDR ((void *volatile *)DMA22_CURR_ADDR)
-#define                 pDMA22_IRQ_STATUS ((volatile unsigned short *)DMA22_IRQ_STATUS)
-#define             pDMA22_PERIPHERAL_MAP ((volatile unsigned short *)DMA22_PERIPHERAL_MAP)
-#define               pDMA22_CURR_X_COUNT ((volatile unsigned short *)DMA22_CURR_X_COUNT)
-#define               pDMA22_CURR_Y_COUNT ((volatile unsigned short *)DMA22_CURR_Y_COUNT)
-
-/* DMA Channel 23 Registers */
-
-#define              pDMA23_NEXT_DESC_PTR ((void *volatile *)DMA23_NEXT_DESC_PTR)
-#define                 pDMA23_START_ADDR ((void *volatile *)DMA23_START_ADDR)
-#define                     pDMA23_CONFIG ((volatile unsigned short *)DMA23_CONFIG)
-#define                    pDMA23_X_COUNT ((volatile unsigned short *)DMA23_X_COUNT)
-#define                   pDMA23_X_MODIFY ((volatile signed short *)DMA23_X_MODIFY)
-#define                    pDMA23_Y_COUNT ((volatile unsigned short *)DMA23_Y_COUNT)
-#define                   pDMA23_Y_MODIFY ((volatile signed short *)DMA23_Y_MODIFY)
-#define              pDMA23_CURR_DESC_PTR ((void *volatile *)DMA23_CURR_DESC_PTR)
-#define                  pDMA23_CURR_ADDR ((void *volatile *)DMA23_CURR_ADDR)
-#define                 pDMA23_IRQ_STATUS ((volatile unsigned short *)DMA23_IRQ_STATUS)
-#define             pDMA23_PERIPHERAL_MAP ((volatile unsigned short *)DMA23_PERIPHERAL_MAP)
-#define               pDMA23_CURR_X_COUNT ((volatile unsigned short *)DMA23_CURR_X_COUNT)
-#define               pDMA23_CURR_Y_COUNT ((volatile unsigned short *)DMA23_CURR_Y_COUNT)
-
-/* MDMA Stream 2 Registers */
-
-#define            pMDMA_D2_NEXT_DESC_PTR ((void *volatile *)MDMA_D2_NEXT_DESC_PTR)
-#define               pMDMA_D2_START_ADDR ((void *volatile *)MDMA_D2_START_ADDR)
-#define                   pMDMA_D2_CONFIG ((volatile unsigned short *)MDMA_D2_CONFIG)
-#define                  pMDMA_D2_X_COUNT ((volatile unsigned short *)MDMA_D2_X_COUNT)
-#define                 pMDMA_D2_X_MODIFY ((volatile signed short *)MDMA_D2_X_MODIFY)
-#define                  pMDMA_D2_Y_COUNT ((volatile unsigned short *)MDMA_D2_Y_COUNT)
-#define                 pMDMA_D2_Y_MODIFY ((volatile signed short *)MDMA_D2_Y_MODIFY)
-#define            pMDMA_D2_CURR_DESC_PTR ((void *volatile *)MDMA_D2_CURR_DESC_PTR)
-#define                pMDMA_D2_CURR_ADDR ((void *volatile *)MDMA_D2_CURR_ADDR)
-#define               pMDMA_D2_IRQ_STATUS ((volatile unsigned short *)MDMA_D2_IRQ_STATUS)
-#define           pMDMA_D2_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D2_PERIPHERAL_MAP)
-#define             pMDMA_D2_CURR_X_COUNT ((volatile unsigned short *)MDMA_D2_CURR_X_COUNT)
-#define             pMDMA_D2_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D2_CURR_Y_COUNT)
-#define            pMDMA_S2_NEXT_DESC_PTR ((void *volatile *)MDMA_S2_NEXT_DESC_PTR)
-#define               pMDMA_S2_START_ADDR ((void *volatile *)MDMA_S2_START_ADDR)
-#define                   pMDMA_S2_CONFIG ((volatile unsigned short *)MDMA_S2_CONFIG)
-#define                  pMDMA_S2_X_COUNT ((volatile unsigned short *)MDMA_S2_X_COUNT)
-#define                 pMDMA_S2_X_MODIFY ((volatile signed short *)MDMA_S2_X_MODIFY)
-#define                  pMDMA_S2_Y_COUNT ((volatile unsigned short *)MDMA_S2_Y_COUNT)
-#define                 pMDMA_S2_Y_MODIFY ((volatile signed short *)MDMA_S2_Y_MODIFY)
-#define            pMDMA_S2_CURR_DESC_PTR ((void *volatile *)MDMA_S2_CURR_DESC_PTR)
-#define                pMDMA_S2_CURR_ADDR ((void *volatile *)MDMA_S2_CURR_ADDR)
-#define               pMDMA_S2_IRQ_STATUS ((volatile unsigned short *)MDMA_S2_IRQ_STATUS)
-#define           pMDMA_S2_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S2_PERIPHERAL_MAP)
-#define             pMDMA_S2_CURR_X_COUNT ((volatile unsigned short *)MDMA_S2_CURR_X_COUNT)
-#define             pMDMA_S2_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S2_CURR_Y_COUNT)
-
-/* MDMA Stream 3 Registers */
-
-#define            pMDMA_D3_NEXT_DESC_PTR ((void *volatile *)MDMA_D3_NEXT_DESC_PTR)
-#define               pMDMA_D3_START_ADDR ((void *volatile *)MDMA_D3_START_ADDR)
-#define                   pMDMA_D3_CONFIG ((volatile unsigned short *)MDMA_D3_CONFIG)
-#define                  pMDMA_D3_X_COUNT ((volatile unsigned short *)MDMA_D3_X_COUNT)
-#define                 pMDMA_D3_X_MODIFY ((volatile signed short *)MDMA_D3_X_MODIFY)
-#define                  pMDMA_D3_Y_COUNT ((volatile unsigned short *)MDMA_D3_Y_COUNT)
-#define                 pMDMA_D3_Y_MODIFY ((volatile signed short *)MDMA_D3_Y_MODIFY)
-#define            pMDMA_D3_CURR_DESC_PTR ((void *volatile *)MDMA_D3_CURR_DESC_PTR)
-#define                pMDMA_D3_CURR_ADDR ((void *volatile *)MDMA_D3_CURR_ADDR)
-#define               pMDMA_D3_IRQ_STATUS ((volatile unsigned short *)MDMA_D3_IRQ_STATUS)
-#define           pMDMA_D3_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D3_PERIPHERAL_MAP)
-#define             pMDMA_D3_CURR_X_COUNT ((volatile unsigned short *)MDMA_D3_CURR_X_COUNT)
-#define             pMDMA_D3_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D3_CURR_Y_COUNT)
-#define            pMDMA_S3_NEXT_DESC_PTR ((void *volatile *)MDMA_S3_NEXT_DESC_PTR)
-#define               pMDMA_S3_START_ADDR ((void *volatile *)MDMA_S3_START_ADDR)
-#define                   pMDMA_S3_CONFIG ((volatile unsigned short *)MDMA_S3_CONFIG)
-#define                  pMDMA_S3_X_COUNT ((volatile unsigned short *)MDMA_S3_X_COUNT)
-#define                 pMDMA_S3_X_MODIFY ((volatile signed short *)MDMA_S3_X_MODIFY)
-#define                  pMDMA_S3_Y_COUNT ((volatile unsigned short *)MDMA_S3_Y_COUNT)
-#define                 pMDMA_S3_Y_MODIFY ((volatile signed short *)MDMA_S3_Y_MODIFY)
-#define            pMDMA_S3_CURR_DESC_PTR ((void *volatile *)MDMA_S3_CURR_DESC_PTR)
-#define                pMDMA_S3_CURR_ADDR ((void *volatile *)MDMA_S3_CURR_ADDR)
-#define               pMDMA_S3_IRQ_STATUS ((volatile unsigned short *)MDMA_S3_IRQ_STATUS)
-#define           pMDMA_S3_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S3_PERIPHERAL_MAP)
-#define             pMDMA_S3_CURR_X_COUNT ((volatile unsigned short *)MDMA_S3_CURR_X_COUNT)
-#define             pMDMA_S3_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S3_CURR_Y_COUNT)
-
-/* UART1 Registers */
-
-#define                        pUART1_DLL ((volatile unsigned short *)UART1_DLL)
-#define                        pUART1_DLH ((volatile unsigned short *)UART1_DLH)
-#define                       pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
-#define                        pUART1_LCR ((volatile unsigned short *)UART1_LCR)
-#define                        pUART1_MCR ((volatile unsigned short *)UART1_MCR)
-#define                        pUART1_LSR ((volatile unsigned short *)UART1_LSR)
-#define                        pUART1_MSR ((volatile unsigned short *)UART1_MSR)
-#define                        pUART1_SCR ((volatile unsigned short *)UART1_SCR)
-#define                    pUART1_IER_SET ((volatile unsigned short *)UART1_IER_SET)
-#define                  pUART1_IER_CLEAR ((volatile unsigned short *)UART1_IER_CLEAR)
-#define                        pUART1_THR ((volatile unsigned short *)UART1_THR)
-#define                        pUART1_RBR ((volatile unsigned short *)UART1_RBR)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define                         pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
-#define                         pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
-#define                        pSPI1_STAT ((volatile unsigned short *)SPI1_STAT)
-#define                        pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
-#define                        pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
-#define                        pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
-#define                      pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
-
-/* SPORT2 Registers */
-
-#define                      pSPORT2_TCR1 ((volatile unsigned short *)SPORT2_TCR1)
-#define                      pSPORT2_TCR2 ((volatile unsigned short *)SPORT2_TCR2)
-#define                   pSPORT2_TCLKDIV ((volatile unsigned short *)SPORT2_TCLKDIV)
-#define                    pSPORT2_TFSDIV ((volatile unsigned short *)SPORT2_TFSDIV)
-#define                        pSPORT2_TX ((volatile unsigned long *)SPORT2_TX)
-#define                        pSPORT2_RX ((volatile unsigned long *)SPORT2_RX)
-#define                      pSPORT2_RCR1 ((volatile unsigned short *)SPORT2_RCR1)
-#define                      pSPORT2_RCR2 ((volatile unsigned short *)SPORT2_RCR2)
-#define                   pSPORT2_RCLKDIV ((volatile unsigned short *)SPORT2_RCLKDIV)
-#define                    pSPORT2_RFSDIV ((volatile unsigned short *)SPORT2_RFSDIV)
-#define                      pSPORT2_STAT ((volatile unsigned short *)SPORT2_STAT)
-#define                      pSPORT2_CHNL ((volatile unsigned short *)SPORT2_CHNL)
-#define                     pSPORT2_MCMC1 ((volatile unsigned short *)SPORT2_MCMC1)
-#define                     pSPORT2_MCMC2 ((volatile unsigned short *)SPORT2_MCMC2)
-#define                     pSPORT2_MTCS0 ((volatile unsigned long *)SPORT2_MTCS0)
-#define                     pSPORT2_MTCS1 ((volatile unsigned long *)SPORT2_MTCS1)
-#define                     pSPORT2_MTCS2 ((volatile unsigned long *)SPORT2_MTCS2)
-#define                     pSPORT2_MTCS3 ((volatile unsigned long *)SPORT2_MTCS3)
-#define                     pSPORT2_MRCS0 ((volatile unsigned long *)SPORT2_MRCS0)
-#define                     pSPORT2_MRCS1 ((volatile unsigned long *)SPORT2_MRCS1)
-#define                     pSPORT2_MRCS2 ((volatile unsigned long *)SPORT2_MRCS2)
-#define                     pSPORT2_MRCS3 ((volatile unsigned long *)SPORT2_MRCS3)
-
-/* SPORT3 Registers */
-
-#define                      pSPORT3_TCR1 ((volatile unsigned short *)SPORT3_TCR1)
-#define                      pSPORT3_TCR2 ((volatile unsigned short *)SPORT3_TCR2)
-#define                   pSPORT3_TCLKDIV ((volatile unsigned short *)SPORT3_TCLKDIV)
-#define                    pSPORT3_TFSDIV ((volatile unsigned short *)SPORT3_TFSDIV)
-#define                        pSPORT3_TX ((volatile unsigned long *)SPORT3_TX)
-#define                        pSPORT3_RX ((volatile unsigned long *)SPORT3_RX)
-#define                      pSPORT3_RCR1 ((volatile unsigned short *)SPORT3_RCR1)
-#define                      pSPORT3_RCR2 ((volatile unsigned short *)SPORT3_RCR2)
-#define                   pSPORT3_RCLKDIV ((volatile unsigned short *)SPORT3_RCLKDIV)
-#define                    pSPORT3_RFSDIV ((volatile unsigned short *)SPORT3_RFSDIV)
-#define                      pSPORT3_STAT ((volatile unsigned short *)SPORT3_STAT)
-#define                      pSPORT3_CHNL ((volatile unsigned short *)SPORT3_CHNL)
-#define                     pSPORT3_MCMC1 ((volatile unsigned short *)SPORT3_MCMC1)
-#define                     pSPORT3_MCMC2 ((volatile unsigned short *)SPORT3_MCMC2)
-#define                     pSPORT3_MTCS0 ((volatile unsigned long *)SPORT3_MTCS0)
-#define                     pSPORT3_MTCS1 ((volatile unsigned long *)SPORT3_MTCS1)
-#define                     pSPORT3_MTCS2 ((volatile unsigned long *)SPORT3_MTCS2)
-#define                     pSPORT3_MTCS3 ((volatile unsigned long *)SPORT3_MTCS3)
-#define                     pSPORT3_MRCS0 ((volatile unsigned long *)SPORT3_MRCS0)
-#define                     pSPORT3_MRCS1 ((volatile unsigned long *)SPORT3_MRCS1)
-#define                     pSPORT3_MRCS2 ((volatile unsigned long *)SPORT3_MRCS2)
-#define                     pSPORT3_MRCS3 ((volatile unsigned long *)SPORT3_MRCS3)
-
-/* EPPI2 Registers */
-
-#define                     pEPPI2_STATUS ((volatile unsigned short *)EPPI2_STATUS)
-#define                     pEPPI2_HCOUNT ((volatile unsigned short *)EPPI2_HCOUNT)
-#define                     pEPPI2_HDELAY ((volatile unsigned short *)EPPI2_HDELAY)
-#define                     pEPPI2_VCOUNT ((volatile unsigned short *)EPPI2_VCOUNT)
-#define                     pEPPI2_VDELAY ((volatile unsigned short *)EPPI2_VDELAY)
-#define                      pEPPI2_FRAME ((volatile unsigned short *)EPPI2_FRAME)
-#define                       pEPPI2_LINE ((volatile unsigned short *)EPPI2_LINE)
-#define                     pEPPI2_CLKDIV ((volatile unsigned short *)EPPI2_CLKDIV)
-#define                    pEPPI2_CONTROL ((volatile unsigned long *)EPPI2_CONTROL)
-#define                   pEPPI2_FS1W_HBL ((volatile unsigned long *)EPPI2_FS1W_HBL)
-#define                  pEPPI2_FS1P_AVPL ((volatile unsigned long *)EPPI2_FS1P_AVPL)
-#define                   pEPPI2_FS2W_LVB ((volatile unsigned long *)EPPI2_FS2W_LVB)
-#define                  pEPPI2_FS2P_LAVF ((volatile unsigned long *)EPPI2_FS2P_LAVF)
-#define                       pEPPI2_CLIP ((volatile unsigned long *)EPPI2_CLIP)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define                         pCAN0_MC1 ((volatile unsigned short *)CAN0_MC1)
-#define                         pCAN0_MD1 ((volatile unsigned short *)CAN0_MD1)
-#define                        pCAN0_TRS1 ((volatile unsigned short *)CAN0_TRS1)
-#define                        pCAN0_TRR1 ((volatile unsigned short *)CAN0_TRR1)
-#define                         pCAN0_TA1 ((volatile unsigned short *)CAN0_TA1)
-#define                         pCAN0_AA1 ((volatile unsigned short *)CAN0_AA1)
-#define                        pCAN0_RMP1 ((volatile unsigned short *)CAN0_RMP1)
-#define                        pCAN0_RML1 ((volatile unsigned short *)CAN0_RML1)
-#define                      pCAN0_MBTIF1 ((volatile unsigned short *)CAN0_MBTIF1)
-#define                      pCAN0_MBRIF1 ((volatile unsigned short *)CAN0_MBRIF1)
-#define                       pCAN0_MBIM1 ((volatile unsigned short *)CAN0_MBIM1)
-#define                        pCAN0_RFH1 ((volatile unsigned short *)CAN0_RFH1)
-#define                       pCAN0_OPSS1 ((volatile unsigned short *)CAN0_OPSS1)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define                         pCAN0_MC2 ((volatile unsigned short *)CAN0_MC2)
-#define                         pCAN0_MD2 ((volatile unsigned short *)CAN0_MD2)
-#define                        pCAN0_TRS2 ((volatile unsigned short *)CAN0_TRS2)
-#define                        pCAN0_TRR2 ((volatile unsigned short *)CAN0_TRR2)
-#define                         pCAN0_TA2 ((volatile unsigned short *)CAN0_TA2)
-#define                         pCAN0_AA2 ((volatile unsigned short *)CAN0_AA2)
-#define                        pCAN0_RMP2 ((volatile unsigned short *)CAN0_RMP2)
-#define                        pCAN0_RML2 ((volatile unsigned short *)CAN0_RML2)
-#define                      pCAN0_MBTIF2 ((volatile unsigned short *)CAN0_MBTIF2)
-#define                      pCAN0_MBRIF2 ((volatile unsigned short *)CAN0_MBRIF2)
-#define                       pCAN0_MBIM2 ((volatile unsigned short *)CAN0_MBIM2)
-#define                        pCAN0_RFH2 ((volatile unsigned short *)CAN0_RFH2)
-#define                       pCAN0_OPSS2 ((volatile unsigned short *)CAN0_OPSS2)
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define                       pCAN0_CLOCK ((volatile unsigned short *)CAN0_CLOCK)
-#define                      pCAN0_TIMING ((volatile unsigned short *)CAN0_TIMING)
-#define                       pCAN0_DEBUG ((volatile unsigned short *)CAN0_DEBUG)
-#define                      pCAN0_STATUS ((volatile unsigned short *)CAN0_STATUS)
-#define                         pCAN0_CEC ((volatile unsigned short *)CAN0_CEC)
-#define                         pCAN0_GIS ((volatile unsigned short *)CAN0_GIS)
-#define                         pCAN0_GIM ((volatile unsigned short *)CAN0_GIM)
-#define                         pCAN0_GIF ((volatile unsigned short *)CAN0_GIF)
-#define                     pCAN0_CONTROL ((volatile unsigned short *)CAN0_CONTROL)
-#define                        pCAN0_INTR ((volatile unsigned short *)CAN0_INTR)
-#define                        pCAN0_MBTD ((volatile unsigned short *)CAN0_MBTD)
-#define                         pCAN0_EWR ((volatile unsigned short *)CAN0_EWR)
-#define                         pCAN0_ESR ((volatile unsigned short *)CAN0_ESR)
-#define                       pCAN0_UCCNT ((volatile unsigned short *)CAN0_UCCNT)
-#define                        pCAN0_UCRC ((volatile unsigned short *)CAN0_UCRC)
-#define                       pCAN0_UCCNF ((volatile unsigned short *)CAN0_UCCNF)
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       pCAN0_AM00L ((volatile unsigned short *)CAN0_AM00L)
-#define                       pCAN0_AM00H ((volatile unsigned short *)CAN0_AM00H)
-#define                       pCAN0_AM01L ((volatile unsigned short *)CAN0_AM01L)
-#define                       pCAN0_AM01H ((volatile unsigned short *)CAN0_AM01H)
-#define                       pCAN0_AM02L ((volatile unsigned short *)CAN0_AM02L)
-#define                       pCAN0_AM02H ((volatile unsigned short *)CAN0_AM02H)
-#define                       pCAN0_AM03L ((volatile unsigned short *)CAN0_AM03L)
-#define                       pCAN0_AM03H ((volatile unsigned short *)CAN0_AM03H)
-#define                       pCAN0_AM04L ((volatile unsigned short *)CAN0_AM04L)
-#define                       pCAN0_AM04H ((volatile unsigned short *)CAN0_AM04H)
-#define                       pCAN0_AM05L ((volatile unsigned short *)CAN0_AM05L)
-#define                       pCAN0_AM05H ((volatile unsigned short *)CAN0_AM05H)
-#define                       pCAN0_AM06L ((volatile unsigned short *)CAN0_AM06L)
-#define                       pCAN0_AM06H ((volatile unsigned short *)CAN0_AM06H)
-#define                       pCAN0_AM07L ((volatile unsigned short *)CAN0_AM07L)
-#define                       pCAN0_AM07H ((volatile unsigned short *)CAN0_AM07H)
-#define                       pCAN0_AM08L ((volatile unsigned short *)CAN0_AM08L)
-#define                       pCAN0_AM08H ((volatile unsigned short *)CAN0_AM08H)
-#define                       pCAN0_AM09L ((volatile unsigned short *)CAN0_AM09L)
-#define                       pCAN0_AM09H ((volatile unsigned short *)CAN0_AM09H)
-#define                       pCAN0_AM10L ((volatile unsigned short *)CAN0_AM10L)
-#define                       pCAN0_AM10H ((volatile unsigned short *)CAN0_AM10H)
-#define                       pCAN0_AM11L ((volatile unsigned short *)CAN0_AM11L)
-#define                       pCAN0_AM11H ((volatile unsigned short *)CAN0_AM11H)
-#define                       pCAN0_AM12L ((volatile unsigned short *)CAN0_AM12L)
-#define                       pCAN0_AM12H ((volatile unsigned short *)CAN0_AM12H)
-#define                       pCAN0_AM13L ((volatile unsigned short *)CAN0_AM13L)
-#define                       pCAN0_AM13H ((volatile unsigned short *)CAN0_AM13H)
-#define                       pCAN0_AM14L ((volatile unsigned short *)CAN0_AM14L)
-#define                       pCAN0_AM14H ((volatile unsigned short *)CAN0_AM14H)
-#define                       pCAN0_AM15L ((volatile unsigned short *)CAN0_AM15L)
-#define                       pCAN0_AM15H ((volatile unsigned short *)CAN0_AM15H)
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       pCAN0_AM16L ((volatile unsigned short *)CAN0_AM16L)
-#define                       pCAN0_AM16H ((volatile unsigned short *)CAN0_AM16H)
-#define                       pCAN0_AM17L ((volatile unsigned short *)CAN0_AM17L)
-#define                       pCAN0_AM17H ((volatile unsigned short *)CAN0_AM17H)
-#define                       pCAN0_AM18L ((volatile unsigned short *)CAN0_AM18L)
-#define                       pCAN0_AM18H ((volatile unsigned short *)CAN0_AM18H)
-#define                       pCAN0_AM19L ((volatile unsigned short *)CAN0_AM19L)
-#define                       pCAN0_AM19H ((volatile unsigned short *)CAN0_AM19H)
-#define                       pCAN0_AM20L ((volatile unsigned short *)CAN0_AM20L)
-#define                       pCAN0_AM20H ((volatile unsigned short *)CAN0_AM20H)
-#define                       pCAN0_AM21L ((volatile unsigned short *)CAN0_AM21L)
-#define                       pCAN0_AM21H ((volatile unsigned short *)CAN0_AM21H)
-#define                       pCAN0_AM22L ((volatile unsigned short *)CAN0_AM22L)
-#define                       pCAN0_AM22H ((volatile unsigned short *)CAN0_AM22H)
-#define                       pCAN0_AM23L ((volatile unsigned short *)CAN0_AM23L)
-#define                       pCAN0_AM23H ((volatile unsigned short *)CAN0_AM23H)
-#define                       pCAN0_AM24L ((volatile unsigned short *)CAN0_AM24L)
-#define                       pCAN0_AM24H ((volatile unsigned short *)CAN0_AM24H)
-#define                       pCAN0_AM25L ((volatile unsigned short *)CAN0_AM25L)
-#define                       pCAN0_AM25H ((volatile unsigned short *)CAN0_AM25H)
-#define                       pCAN0_AM26L ((volatile unsigned short *)CAN0_AM26L)
-#define                       pCAN0_AM26H ((volatile unsigned short *)CAN0_AM26H)
-#define                       pCAN0_AM27L ((volatile unsigned short *)CAN0_AM27L)
-#define                       pCAN0_AM27H ((volatile unsigned short *)CAN0_AM27H)
-#define                       pCAN0_AM28L ((volatile unsigned short *)CAN0_AM28L)
-#define                       pCAN0_AM28H ((volatile unsigned short *)CAN0_AM28H)
-#define                       pCAN0_AM29L ((volatile unsigned short *)CAN0_AM29L)
-#define                       pCAN0_AM29H ((volatile unsigned short *)CAN0_AM29H)
-#define                       pCAN0_AM30L ((volatile unsigned short *)CAN0_AM30L)
-#define                       pCAN0_AM30H ((volatile unsigned short *)CAN0_AM30H)
-#define                       pCAN0_AM31L ((volatile unsigned short *)CAN0_AM31L)
-#define                       pCAN0_AM31H ((volatile unsigned short *)CAN0_AM31H)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  pCAN0_MB00_DATA0 ((volatile unsigned short *)CAN0_MB00_DATA0)
-#define                  pCAN0_MB00_DATA1 ((volatile unsigned short *)CAN0_MB00_DATA1)
-#define                  pCAN0_MB00_DATA2 ((volatile unsigned short *)CAN0_MB00_DATA2)
-#define                  pCAN0_MB00_DATA3 ((volatile unsigned short *)CAN0_MB00_DATA3)
-#define                 pCAN0_MB00_LENGTH ((volatile unsigned short *)CAN0_MB00_LENGTH)
-#define              pCAN0_MB00_TIMESTAMP ((volatile unsigned short *)CAN0_MB00_TIMESTAMP)
-#define                    pCAN0_MB00_ID0 ((volatile unsigned short *)CAN0_MB00_ID0)
-#define                    pCAN0_MB00_ID1 ((volatile unsigned short *)CAN0_MB00_ID1)
-#define                  pCAN0_MB01_DATA0 ((volatile unsigned short *)CAN0_MB01_DATA0)
-#define                  pCAN0_MB01_DATA1 ((volatile unsigned short *)CAN0_MB01_DATA1)
-#define                  pCAN0_MB01_DATA2 ((volatile unsigned short *)CAN0_MB01_DATA2)
-#define                  pCAN0_MB01_DATA3 ((volatile unsigned short *)CAN0_MB01_DATA3)
-#define                 pCAN0_MB01_LENGTH ((volatile unsigned short *)CAN0_MB01_LENGTH)
-#define              pCAN0_MB01_TIMESTAMP ((volatile unsigned short *)CAN0_MB01_TIMESTAMP)
-#define                    pCAN0_MB01_ID0 ((volatile unsigned short *)CAN0_MB01_ID0)
-#define                    pCAN0_MB01_ID1 ((volatile unsigned short *)CAN0_MB01_ID1)
-#define                  pCAN0_MB02_DATA0 ((volatile unsigned short *)CAN0_MB02_DATA0)
-#define                  pCAN0_MB02_DATA1 ((volatile unsigned short *)CAN0_MB02_DATA1)
-#define                  pCAN0_MB02_DATA2 ((volatile unsigned short *)CAN0_MB02_DATA2)
-#define                  pCAN0_MB02_DATA3 ((volatile unsigned short *)CAN0_MB02_DATA3)
-#define                 pCAN0_MB02_LENGTH ((volatile unsigned short *)CAN0_MB02_LENGTH)
-#define              pCAN0_MB02_TIMESTAMP ((volatile unsigned short *)CAN0_MB02_TIMESTAMP)
-#define                    pCAN0_MB02_ID0 ((volatile unsigned short *)CAN0_MB02_ID0)
-#define                    pCAN0_MB02_ID1 ((volatile unsigned short *)CAN0_MB02_ID1)
-#define                  pCAN0_MB03_DATA0 ((volatile unsigned short *)CAN0_MB03_DATA0)
-#define                  pCAN0_MB03_DATA1 ((volatile unsigned short *)CAN0_MB03_DATA1)
-#define                  pCAN0_MB03_DATA2 ((volatile unsigned short *)CAN0_MB03_DATA2)
-#define                  pCAN0_MB03_DATA3 ((volatile unsigned short *)CAN0_MB03_DATA3)
-#define                 pCAN0_MB03_LENGTH ((volatile unsigned short *)CAN0_MB03_LENGTH)
-#define              pCAN0_MB03_TIMESTAMP ((volatile unsigned short *)CAN0_MB03_TIMESTAMP)
-#define                    pCAN0_MB03_ID0 ((volatile unsigned short *)CAN0_MB03_ID0)
-#define                    pCAN0_MB03_ID1 ((volatile unsigned short *)CAN0_MB03_ID1)
-#define                  pCAN0_MB04_DATA0 ((volatile unsigned short *)CAN0_MB04_DATA0)
-#define                  pCAN0_MB04_DATA1 ((volatile unsigned short *)CAN0_MB04_DATA1)
-#define                  pCAN0_MB04_DATA2 ((volatile unsigned short *)CAN0_MB04_DATA2)
-#define                  pCAN0_MB04_DATA3 ((volatile unsigned short *)CAN0_MB04_DATA3)
-#define                 pCAN0_MB04_LENGTH ((volatile unsigned short *)CAN0_MB04_LENGTH)
-#define              pCAN0_MB04_TIMESTAMP ((volatile unsigned short *)CAN0_MB04_TIMESTAMP)
-#define                    pCAN0_MB04_ID0 ((volatile unsigned short *)CAN0_MB04_ID0)
-#define                    pCAN0_MB04_ID1 ((volatile unsigned short *)CAN0_MB04_ID1)
-#define                  pCAN0_MB05_DATA0 ((volatile unsigned short *)CAN0_MB05_DATA0)
-#define                  pCAN0_MB05_DATA1 ((volatile unsigned short *)CAN0_MB05_DATA1)
-#define                  pCAN0_MB05_DATA2 ((volatile unsigned short *)CAN0_MB05_DATA2)
-#define                  pCAN0_MB05_DATA3 ((volatile unsigned short *)CAN0_MB05_DATA3)
-#define                 pCAN0_MB05_LENGTH ((volatile unsigned short *)CAN0_MB05_LENGTH)
-#define              pCAN0_MB05_TIMESTAMP ((volatile unsigned short *)CAN0_MB05_TIMESTAMP)
-#define                    pCAN0_MB05_ID0 ((volatile unsigned short *)CAN0_MB05_ID0)
-#define                    pCAN0_MB05_ID1 ((volatile unsigned short *)CAN0_MB05_ID1)
-#define                  pCAN0_MB06_DATA0 ((volatile unsigned short *)CAN0_MB06_DATA0)
-#define                  pCAN0_MB06_DATA1 ((volatile unsigned short *)CAN0_MB06_DATA1)
-#define                  pCAN0_MB06_DATA2 ((volatile unsigned short *)CAN0_MB06_DATA2)
-#define                  pCAN0_MB06_DATA3 ((volatile unsigned short *)CAN0_MB06_DATA3)
-#define                 pCAN0_MB06_LENGTH ((volatile unsigned short *)CAN0_MB06_LENGTH)
-#define              pCAN0_MB06_TIMESTAMP ((volatile unsigned short *)CAN0_MB06_TIMESTAMP)
-#define                    pCAN0_MB06_ID0 ((volatile unsigned short *)CAN0_MB06_ID0)
-#define                    pCAN0_MB06_ID1 ((volatile unsigned short *)CAN0_MB06_ID1)
-#define                  pCAN0_MB07_DATA0 ((volatile unsigned short *)CAN0_MB07_DATA0)
-#define                  pCAN0_MB07_DATA1 ((volatile unsigned short *)CAN0_MB07_DATA1)
-#define                  pCAN0_MB07_DATA2 ((volatile unsigned short *)CAN0_MB07_DATA2)
-#define                  pCAN0_MB07_DATA3 ((volatile unsigned short *)CAN0_MB07_DATA3)
-#define                 pCAN0_MB07_LENGTH ((volatile unsigned short *)CAN0_MB07_LENGTH)
-#define              pCAN0_MB07_TIMESTAMP ((volatile unsigned short *)CAN0_MB07_TIMESTAMP)
-#define                    pCAN0_MB07_ID0 ((volatile unsigned short *)CAN0_MB07_ID0)
-#define                    pCAN0_MB07_ID1 ((volatile unsigned short *)CAN0_MB07_ID1)
-#define                  pCAN0_MB08_DATA0 ((volatile unsigned short *)CAN0_MB08_DATA0)
-#define                  pCAN0_MB08_DATA1 ((volatile unsigned short *)CAN0_MB08_DATA1)
-#define                  pCAN0_MB08_DATA2 ((volatile unsigned short *)CAN0_MB08_DATA2)
-#define                  pCAN0_MB08_DATA3 ((volatile unsigned short *)CAN0_MB08_DATA3)
-#define                 pCAN0_MB08_LENGTH ((volatile unsigned short *)CAN0_MB08_LENGTH)
-#define              pCAN0_MB08_TIMESTAMP ((volatile unsigned short *)CAN0_MB08_TIMESTAMP)
-#define                    pCAN0_MB08_ID0 ((volatile unsigned short *)CAN0_MB08_ID0)
-#define                    pCAN0_MB08_ID1 ((volatile unsigned short *)CAN0_MB08_ID1)
-#define                  pCAN0_MB09_DATA0 ((volatile unsigned short *)CAN0_MB09_DATA0)
-#define                  pCAN0_MB09_DATA1 ((volatile unsigned short *)CAN0_MB09_DATA1)
-#define                  pCAN0_MB09_DATA2 ((volatile unsigned short *)CAN0_MB09_DATA2)
-#define                  pCAN0_MB09_DATA3 ((volatile unsigned short *)CAN0_MB09_DATA3)
-#define                 pCAN0_MB09_LENGTH ((volatile unsigned short *)CAN0_MB09_LENGTH)
-#define              pCAN0_MB09_TIMESTAMP ((volatile unsigned short *)CAN0_MB09_TIMESTAMP)
-#define                    pCAN0_MB09_ID0 ((volatile unsigned short *)CAN0_MB09_ID0)
-#define                    pCAN0_MB09_ID1 ((volatile unsigned short *)CAN0_MB09_ID1)
-#define                  pCAN0_MB10_DATA0 ((volatile unsigned short *)CAN0_MB10_DATA0)
-#define                  pCAN0_MB10_DATA1 ((volatile unsigned short *)CAN0_MB10_DATA1)
-#define                  pCAN0_MB10_DATA2 ((volatile unsigned short *)CAN0_MB10_DATA2)
-#define                  pCAN0_MB10_DATA3 ((volatile unsigned short *)CAN0_MB10_DATA3)
-#define                 pCAN0_MB10_LENGTH ((volatile unsigned short *)CAN0_MB10_LENGTH)
-#define              pCAN0_MB10_TIMESTAMP ((volatile unsigned short *)CAN0_MB10_TIMESTAMP)
-#define                    pCAN0_MB10_ID0 ((volatile unsigned short *)CAN0_MB10_ID0)
-#define                    pCAN0_MB10_ID1 ((volatile unsigned short *)CAN0_MB10_ID1)
-#define                  pCAN0_MB11_DATA0 ((volatile unsigned short *)CAN0_MB11_DATA0)
-#define                  pCAN0_MB11_DATA1 ((volatile unsigned short *)CAN0_MB11_DATA1)
-#define                  pCAN0_MB11_DATA2 ((volatile unsigned short *)CAN0_MB11_DATA2)
-#define                  pCAN0_MB11_DATA3 ((volatile unsigned short *)CAN0_MB11_DATA3)
-#define                 pCAN0_MB11_LENGTH ((volatile unsigned short *)CAN0_MB11_LENGTH)
-#define              pCAN0_MB11_TIMESTAMP ((volatile unsigned short *)CAN0_MB11_TIMESTAMP)
-#define                    pCAN0_MB11_ID0 ((volatile unsigned short *)CAN0_MB11_ID0)
-#define                    pCAN0_MB11_ID1 ((volatile unsigned short *)CAN0_MB11_ID1)
-#define                  pCAN0_MB12_DATA0 ((volatile unsigned short *)CAN0_MB12_DATA0)
-#define                  pCAN0_MB12_DATA1 ((volatile unsigned short *)CAN0_MB12_DATA1)
-#define                  pCAN0_MB12_DATA2 ((volatile unsigned short *)CAN0_MB12_DATA2)
-#define                  pCAN0_MB12_DATA3 ((volatile unsigned short *)CAN0_MB12_DATA3)
-#define                 pCAN0_MB12_LENGTH ((volatile unsigned short *)CAN0_MB12_LENGTH)
-#define              pCAN0_MB12_TIMESTAMP ((volatile unsigned short *)CAN0_MB12_TIMESTAMP)
-#define                    pCAN0_MB12_ID0 ((volatile unsigned short *)CAN0_MB12_ID0)
-#define                    pCAN0_MB12_ID1 ((volatile unsigned short *)CAN0_MB12_ID1)
-#define                  pCAN0_MB13_DATA0 ((volatile unsigned short *)CAN0_MB13_DATA0)
-#define                  pCAN0_MB13_DATA1 ((volatile unsigned short *)CAN0_MB13_DATA1)
-#define                  pCAN0_MB13_DATA2 ((volatile unsigned short *)CAN0_MB13_DATA2)
-#define                  pCAN0_MB13_DATA3 ((volatile unsigned short *)CAN0_MB13_DATA3)
-#define                 pCAN0_MB13_LENGTH ((volatile unsigned short *)CAN0_MB13_LENGTH)
-#define              pCAN0_MB13_TIMESTAMP ((volatile unsigned short *)CAN0_MB13_TIMESTAMP)
-#define                    pCAN0_MB13_ID0 ((volatile unsigned short *)CAN0_MB13_ID0)
-#define                    pCAN0_MB13_ID1 ((volatile unsigned short *)CAN0_MB13_ID1)
-#define                  pCAN0_MB14_DATA0 ((volatile unsigned short *)CAN0_MB14_DATA0)
-#define                  pCAN0_MB14_DATA1 ((volatile unsigned short *)CAN0_MB14_DATA1)
-#define                  pCAN0_MB14_DATA2 ((volatile unsigned short *)CAN0_MB14_DATA2)
-#define                  pCAN0_MB14_DATA3 ((volatile unsigned short *)CAN0_MB14_DATA3)
-#define                 pCAN0_MB14_LENGTH ((volatile unsigned short *)CAN0_MB14_LENGTH)
-#define              pCAN0_MB14_TIMESTAMP ((volatile unsigned short *)CAN0_MB14_TIMESTAMP)
-#define                    pCAN0_MB14_ID0 ((volatile unsigned short *)CAN0_MB14_ID0)
-#define                    pCAN0_MB14_ID1 ((volatile unsigned short *)CAN0_MB14_ID1)
-#define                  pCAN0_MB15_DATA0 ((volatile unsigned short *)CAN0_MB15_DATA0)
-#define                  pCAN0_MB15_DATA1 ((volatile unsigned short *)CAN0_MB15_DATA1)
-#define                  pCAN0_MB15_DATA2 ((volatile unsigned short *)CAN0_MB15_DATA2)
-#define                  pCAN0_MB15_DATA3 ((volatile unsigned short *)CAN0_MB15_DATA3)
-#define                 pCAN0_MB15_LENGTH ((volatile unsigned short *)CAN0_MB15_LENGTH)
-#define              pCAN0_MB15_TIMESTAMP ((volatile unsigned short *)CAN0_MB15_TIMESTAMP)
-#define                    pCAN0_MB15_ID0 ((volatile unsigned short *)CAN0_MB15_ID0)
-#define                    pCAN0_MB15_ID1 ((volatile unsigned short *)CAN0_MB15_ID1)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  pCAN0_MB16_DATA0 ((volatile unsigned short *)CAN0_MB16_DATA0)
-#define                  pCAN0_MB16_DATA1 ((volatile unsigned short *)CAN0_MB16_DATA1)
-#define                  pCAN0_MB16_DATA2 ((volatile unsigned short *)CAN0_MB16_DATA2)
-#define                  pCAN0_MB16_DATA3 ((volatile unsigned short *)CAN0_MB16_DATA3)
-#define                 pCAN0_MB16_LENGTH ((volatile unsigned short *)CAN0_MB16_LENGTH)
-#define              pCAN0_MB16_TIMESTAMP ((volatile unsigned short *)CAN0_MB16_TIMESTAMP)
-#define                    pCAN0_MB16_ID0 ((volatile unsigned short *)CAN0_MB16_ID0)
-#define                    pCAN0_MB16_ID1 ((volatile unsigned short *)CAN0_MB16_ID1)
-#define                  pCAN0_MB17_DATA0 ((volatile unsigned short *)CAN0_MB17_DATA0)
-#define                  pCAN0_MB17_DATA1 ((volatile unsigned short *)CAN0_MB17_DATA1)
-#define                  pCAN0_MB17_DATA2 ((volatile unsigned short *)CAN0_MB17_DATA2)
-#define                  pCAN0_MB17_DATA3 ((volatile unsigned short *)CAN0_MB17_DATA3)
-#define                 pCAN0_MB17_LENGTH ((volatile unsigned short *)CAN0_MB17_LENGTH)
-#define              pCAN0_MB17_TIMESTAMP ((volatile unsigned short *)CAN0_MB17_TIMESTAMP)
-#define                    pCAN0_MB17_ID0 ((volatile unsigned short *)CAN0_MB17_ID0)
-#define                    pCAN0_MB17_ID1 ((volatile unsigned short *)CAN0_MB17_ID1)
-#define                  pCAN0_MB18_DATA0 ((volatile unsigned short *)CAN0_MB18_DATA0)
-#define                  pCAN0_MB18_DATA1 ((volatile unsigned short *)CAN0_MB18_DATA1)
-#define                  pCAN0_MB18_DATA2 ((volatile unsigned short *)CAN0_MB18_DATA2)
-#define                  pCAN0_MB18_DATA3 ((volatile unsigned short *)CAN0_MB18_DATA3)
-#define                 pCAN0_MB18_LENGTH ((volatile unsigned short *)CAN0_MB18_LENGTH)
-#define              pCAN0_MB18_TIMESTAMP ((volatile unsigned short *)CAN0_MB18_TIMESTAMP)
-#define                    pCAN0_MB18_ID0 ((volatile unsigned short *)CAN0_MB18_ID0)
-#define                    pCAN0_MB18_ID1 ((volatile unsigned short *)CAN0_MB18_ID1)
-#define                  pCAN0_MB19_DATA0 ((volatile unsigned short *)CAN0_MB19_DATA0)
-#define                  pCAN0_MB19_DATA1 ((volatile unsigned short *)CAN0_MB19_DATA1)
-#define                  pCAN0_MB19_DATA2 ((volatile unsigned short *)CAN0_MB19_DATA2)
-#define                  pCAN0_MB19_DATA3 ((volatile unsigned short *)CAN0_MB19_DATA3)
-#define                 pCAN0_MB19_LENGTH ((volatile unsigned short *)CAN0_MB19_LENGTH)
-#define              pCAN0_MB19_TIMESTAMP ((volatile unsigned short *)CAN0_MB19_TIMESTAMP)
-#define                    pCAN0_MB19_ID0 ((volatile unsigned short *)CAN0_MB19_ID0)
-#define                    pCAN0_MB19_ID1 ((volatile unsigned short *)CAN0_MB19_ID1)
-#define                  pCAN0_MB20_DATA0 ((volatile unsigned short *)CAN0_MB20_DATA0)
-#define                  pCAN0_MB20_DATA1 ((volatile unsigned short *)CAN0_MB20_DATA1)
-#define                  pCAN0_MB20_DATA2 ((volatile unsigned short *)CAN0_MB20_DATA2)
-#define                  pCAN0_MB20_DATA3 ((volatile unsigned short *)CAN0_MB20_DATA3)
-#define                 pCAN0_MB20_LENGTH ((volatile unsigned short *)CAN0_MB20_LENGTH)
-#define              pCAN0_MB20_TIMESTAMP ((volatile unsigned short *)CAN0_MB20_TIMESTAMP)
-#define                    pCAN0_MB20_ID0 ((volatile unsigned short *)CAN0_MB20_ID0)
-#define                    pCAN0_MB20_ID1 ((volatile unsigned short *)CAN0_MB20_ID1)
-#define                  pCAN0_MB21_DATA0 ((volatile unsigned short *)CAN0_MB21_DATA0)
-#define                  pCAN0_MB21_DATA1 ((volatile unsigned short *)CAN0_MB21_DATA1)
-#define                  pCAN0_MB21_DATA2 ((volatile unsigned short *)CAN0_MB21_DATA2)
-#define                  pCAN0_MB21_DATA3 ((volatile unsigned short *)CAN0_MB21_DATA3)
-#define                 pCAN0_MB21_LENGTH ((volatile unsigned short *)CAN0_MB21_LENGTH)
-#define              pCAN0_MB21_TIMESTAMP ((volatile unsigned short *)CAN0_MB21_TIMESTAMP)
-#define                    pCAN0_MB21_ID0 ((volatile unsigned short *)CAN0_MB21_ID0)
-#define                    pCAN0_MB21_ID1 ((volatile unsigned short *)CAN0_MB21_ID1)
-#define                  pCAN0_MB22_DATA0 ((volatile unsigned short *)CAN0_MB22_DATA0)
-#define                  pCAN0_MB22_DATA1 ((volatile unsigned short *)CAN0_MB22_DATA1)
-#define                  pCAN0_MB22_DATA2 ((volatile unsigned short *)CAN0_MB22_DATA2)
-#define                  pCAN0_MB22_DATA3 ((volatile unsigned short *)CAN0_MB22_DATA3)
-#define                 pCAN0_MB22_LENGTH ((volatile unsigned short *)CAN0_MB22_LENGTH)
-#define              pCAN0_MB22_TIMESTAMP ((volatile unsigned short *)CAN0_MB22_TIMESTAMP)
-#define                    pCAN0_MB22_ID0 ((volatile unsigned short *)CAN0_MB22_ID0)
-#define                    pCAN0_MB22_ID1 ((volatile unsigned short *)CAN0_MB22_ID1)
-#define                  pCAN0_MB23_DATA0 ((volatile unsigned short *)CAN0_MB23_DATA0)
-#define                  pCAN0_MB23_DATA1 ((volatile unsigned short *)CAN0_MB23_DATA1)
-#define                  pCAN0_MB23_DATA2 ((volatile unsigned short *)CAN0_MB23_DATA2)
-#define                  pCAN0_MB23_DATA3 ((volatile unsigned short *)CAN0_MB23_DATA3)
-#define                 pCAN0_MB23_LENGTH ((volatile unsigned short *)CAN0_MB23_LENGTH)
-#define              pCAN0_MB23_TIMESTAMP ((volatile unsigned short *)CAN0_MB23_TIMESTAMP)
-#define                    pCAN0_MB23_ID0 ((volatile unsigned short *)CAN0_MB23_ID0)
-#define                    pCAN0_MB23_ID1 ((volatile unsigned short *)CAN0_MB23_ID1)
-#define                  pCAN0_MB24_DATA0 ((volatile unsigned short *)CAN0_MB24_DATA0)
-#define                  pCAN0_MB24_DATA1 ((volatile unsigned short *)CAN0_MB24_DATA1)
-#define                  pCAN0_MB24_DATA2 ((volatile unsigned short *)CAN0_MB24_DATA2)
-#define                  pCAN0_MB24_DATA3 ((volatile unsigned short *)CAN0_MB24_DATA3)
-#define                 pCAN0_MB24_LENGTH ((volatile unsigned short *)CAN0_MB24_LENGTH)
-#define              pCAN0_MB24_TIMESTAMP ((volatile unsigned short *)CAN0_MB24_TIMESTAMP)
-#define                    pCAN0_MB24_ID0 ((volatile unsigned short *)CAN0_MB24_ID0)
-#define                    pCAN0_MB24_ID1 ((volatile unsigned short *)CAN0_MB24_ID1)
-#define                  pCAN0_MB25_DATA0 ((volatile unsigned short *)CAN0_MB25_DATA0)
-#define                  pCAN0_MB25_DATA1 ((volatile unsigned short *)CAN0_MB25_DATA1)
-#define                  pCAN0_MB25_DATA2 ((volatile unsigned short *)CAN0_MB25_DATA2)
-#define                  pCAN0_MB25_DATA3 ((volatile unsigned short *)CAN0_MB25_DATA3)
-#define                 pCAN0_MB25_LENGTH ((volatile unsigned short *)CAN0_MB25_LENGTH)
-#define              pCAN0_MB25_TIMESTAMP ((volatile unsigned short *)CAN0_MB25_TIMESTAMP)
-#define                    pCAN0_MB25_ID0 ((volatile unsigned short *)CAN0_MB25_ID0)
-#define                    pCAN0_MB25_ID1 ((volatile unsigned short *)CAN0_MB25_ID1)
-#define                  pCAN0_MB26_DATA0 ((volatile unsigned short *)CAN0_MB26_DATA0)
-#define                  pCAN0_MB26_DATA1 ((volatile unsigned short *)CAN0_MB26_DATA1)
-#define                  pCAN0_MB26_DATA2 ((volatile unsigned short *)CAN0_MB26_DATA2)
-#define                  pCAN0_MB26_DATA3 ((volatile unsigned short *)CAN0_MB26_DATA3)
-#define                 pCAN0_MB26_LENGTH ((volatile unsigned short *)CAN0_MB26_LENGTH)
-#define              pCAN0_MB26_TIMESTAMP ((volatile unsigned short *)CAN0_MB26_TIMESTAMP)
-#define                    pCAN0_MB26_ID0 ((volatile unsigned short *)CAN0_MB26_ID0)
-#define                    pCAN0_MB26_ID1 ((volatile unsigned short *)CAN0_MB26_ID1)
-#define                  pCAN0_MB27_DATA0 ((volatile unsigned short *)CAN0_MB27_DATA0)
-#define                  pCAN0_MB27_DATA1 ((volatile unsigned short *)CAN0_MB27_DATA1)
-#define                  pCAN0_MB27_DATA2 ((volatile unsigned short *)CAN0_MB27_DATA2)
-#define                  pCAN0_MB27_DATA3 ((volatile unsigned short *)CAN0_MB27_DATA3)
-#define                 pCAN0_MB27_LENGTH ((volatile unsigned short *)CAN0_MB27_LENGTH)
-#define              pCAN0_MB27_TIMESTAMP ((volatile unsigned short *)CAN0_MB27_TIMESTAMP)
-#define                    pCAN0_MB27_ID0 ((volatile unsigned short *)CAN0_MB27_ID0)
-#define                    pCAN0_MB27_ID1 ((volatile unsigned short *)CAN0_MB27_ID1)
-#define                  pCAN0_MB28_DATA0 ((volatile unsigned short *)CAN0_MB28_DATA0)
-#define                  pCAN0_MB28_DATA1 ((volatile unsigned short *)CAN0_MB28_DATA1)
-#define                  pCAN0_MB28_DATA2 ((volatile unsigned short *)CAN0_MB28_DATA2)
-#define                  pCAN0_MB28_DATA3 ((volatile unsigned short *)CAN0_MB28_DATA3)
-#define                 pCAN0_MB28_LENGTH ((volatile unsigned short *)CAN0_MB28_LENGTH)
-#define              pCAN0_MB28_TIMESTAMP ((volatile unsigned short *)CAN0_MB28_TIMESTAMP)
-#define                    pCAN0_MB28_ID0 ((volatile unsigned short *)CAN0_MB28_ID0)
-#define                    pCAN0_MB28_ID1 ((volatile unsigned short *)CAN0_MB28_ID1)
-#define                  pCAN0_MB29_DATA0 ((volatile unsigned short *)CAN0_MB29_DATA0)
-#define                  pCAN0_MB29_DATA1 ((volatile unsigned short *)CAN0_MB29_DATA1)
-#define                  pCAN0_MB29_DATA2 ((volatile unsigned short *)CAN0_MB29_DATA2)
-#define                  pCAN0_MB29_DATA3 ((volatile unsigned short *)CAN0_MB29_DATA3)
-#define                 pCAN0_MB29_LENGTH ((volatile unsigned short *)CAN0_MB29_LENGTH)
-#define              pCAN0_MB29_TIMESTAMP ((volatile unsigned short *)CAN0_MB29_TIMESTAMP)
-#define                    pCAN0_MB29_ID0 ((volatile unsigned short *)CAN0_MB29_ID0)
-#define                    pCAN0_MB29_ID1 ((volatile unsigned short *)CAN0_MB29_ID1)
-#define                  pCAN0_MB30_DATA0 ((volatile unsigned short *)CAN0_MB30_DATA0)
-#define                  pCAN0_MB30_DATA1 ((volatile unsigned short *)CAN0_MB30_DATA1)
-#define                  pCAN0_MB30_DATA2 ((volatile unsigned short *)CAN0_MB30_DATA2)
-#define                  pCAN0_MB30_DATA3 ((volatile unsigned short *)CAN0_MB30_DATA3)
-#define                 pCAN0_MB30_LENGTH ((volatile unsigned short *)CAN0_MB30_LENGTH)
-#define              pCAN0_MB30_TIMESTAMP ((volatile unsigned short *)CAN0_MB30_TIMESTAMP)
-#define                    pCAN0_MB30_ID0 ((volatile unsigned short *)CAN0_MB30_ID0)
-#define                    pCAN0_MB30_ID1 ((volatile unsigned short *)CAN0_MB30_ID1)
-#define                  pCAN0_MB31_DATA0 ((volatile unsigned short *)CAN0_MB31_DATA0)
-#define                  pCAN0_MB31_DATA1 ((volatile unsigned short *)CAN0_MB31_DATA1)
-#define                  pCAN0_MB31_DATA2 ((volatile unsigned short *)CAN0_MB31_DATA2)
-#define                  pCAN0_MB31_DATA3 ((volatile unsigned short *)CAN0_MB31_DATA3)
-#define                 pCAN0_MB31_LENGTH ((volatile unsigned short *)CAN0_MB31_LENGTH)
-#define              pCAN0_MB31_TIMESTAMP ((volatile unsigned short *)CAN0_MB31_TIMESTAMP)
-#define                    pCAN0_MB31_ID0 ((volatile unsigned short *)CAN0_MB31_ID0)
-#define                    pCAN0_MB31_ID1 ((volatile unsigned short *)CAN0_MB31_ID1)
-
-/* UART3 Registers */
-
-#define                        pUART3_DLL ((volatile unsigned short *)UART3_DLL)
-#define                        pUART3_DLH ((volatile unsigned short *)UART3_DLH)
-#define                       pUART3_GCTL ((volatile unsigned short *)UART3_GCTL)
-#define                        pUART3_LCR ((volatile unsigned short *)UART3_LCR)
-#define                        pUART3_MCR ((volatile unsigned short *)UART3_MCR)
-#define                        pUART3_LSR ((volatile unsigned short *)UART3_LSR)
-#define                        pUART3_MSR ((volatile unsigned short *)UART3_MSR)
-#define                        pUART3_SCR ((volatile unsigned short *)UART3_SCR)
-#define                    pUART3_IER_SET ((volatile unsigned short *)UART3_IER_SET)
-#define                  pUART3_IER_CLEAR ((volatile unsigned short *)UART3_IER_CLEAR)
-#define                        pUART3_THR ((volatile unsigned short *)UART3_THR)
-#define                        pUART3_RBR ((volatile unsigned short *)UART3_RBR)
-
-/* NFC Registers */
-
-#define                          pNFC_CTL ((volatile unsigned short *)NFC_CTL)
-#define                         pNFC_STAT ((volatile unsigned short *)NFC_STAT)
-#define                      pNFC_IRQSTAT ((volatile unsigned short *)NFC_IRQSTAT)
-#define                      pNFC_IRQMASK ((volatile unsigned short *)NFC_IRQMASK)
-#define                         pNFC_ECC0 ((volatile unsigned short *)NFC_ECC0)
-#define                         pNFC_ECC1 ((volatile unsigned short *)NFC_ECC1)
-#define                         pNFC_ECC2 ((volatile unsigned short *)NFC_ECC2)
-#define                         pNFC_ECC3 ((volatile unsigned short *)NFC_ECC3)
-#define                        pNFC_COUNT ((volatile unsigned short *)NFC_COUNT)
-#define                          pNFC_RST ((volatile unsigned short *)NFC_RST)
-#define                        pNFC_PGCTL ((volatile unsigned short *)NFC_PGCTL)
-#define                         pNFC_READ ((volatile unsigned short *)NFC_READ)
-#define                         pNFC_ADDR ((volatile unsigned short *)NFC_ADDR)
-#define                          pNFC_CMD ((volatile unsigned short *)NFC_CMD)
-#define                      pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
-#define                      pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
-
-/* Counter Registers */
-
-#define                       pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
-#define                        pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
-#define                       pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
-#define                      pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
-#define                     pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
-#define                      pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
-#define                          pCNT_MAX ((volatile unsigned long *)CNT_MAX)
-#define                          pCNT_MIN ((volatile unsigned long *)CNT_MIN)
-
-/* Security Registers */
-
-#define                    pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
-#define                   pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
-#define                    pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
-
-/* DMA Peripheral Mux Register */
-
-#define                    pDMAC1_PERIMUX ((volatile unsigned short *)DMAC1_PERIMUX)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
-#define                        pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
-#define                        pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
-#define                        pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
-
-/* Handshake MDMA 0 Registers */
-
-#define                   pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
-#define                    pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
-#define                    pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
-#define                  pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
-#define                pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
-#define                    pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
-#define                    pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
-
-/* Handshake MDMA 1 Registers */
-
-#define                   pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
-#define                    pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
-#define                    pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
-#define                  pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
-#define                pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
-#define                    pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
-#define                    pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
-
-/* legacy definitions */
-#define pEBIU_AMCBCTL0 pEBIU_AMBCTL0
-#define pEBIU_AMCBCTL1 pEBIU_AMBCTL1
-#define pPINT0_IRQ pPINT0_REQUEST
-#define pPINT1_IRQ pPINT1_REQUEST
-#define pPINT2_IRQ pPINT2_REQUEST
-#define pPINT3_IRQ pPINT3_REQUEST
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/libgloss/bfin/include/cdefBF561.h b/libgloss/bfin/include/cdefBF561.h
deleted file mode 100644
index dc2c6b534..000000000
--- a/libgloss/bfin/include/cdefBF561.h
+++ /dev/null
@@ -1,795 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefBF561.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-#if !defined(__ADSPBF561__)
-#warning cdefBF561.h should only be included for BF561 chip.
-#endif
-/* include all Core registers and bit definitions */
-#include <defBF561.h>
-#include <cdef_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL 	((volatile unsigned short *)PLL_CTL)
-#define pPLL_DIV 	((volatile unsigned short *)PLL_DIV)
-#define pVR_CTL 	((volatile unsigned short *)VR_CTL)
-#define pPLL_STAT 	((volatile unsigned short *)PLL_STAT)
-#define pPLL_LOCKCNT 	((volatile unsigned short *)PLL_LOCKCNT)
-#define pCHIPID ((volatile unsigned long*)CHIPID)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define pSICA_SWRST 	((volatile unsigned short *)SICA_SWRST)
-#define pSICA_SYSCR 	((volatile unsigned short *)SICA_SYSCR)
-#define pSICA_RVECT 	((volatile unsigned short *)SICA_RVECT)
-#define pSICA_IMASK 	((volatile unsigned long *)SICA_IMASK)
-#define pSICA_IMASK0 	((volatile unsigned long *)SICA_IMASK0)
-#define pSICA_IMASK1 	((volatile unsigned long *)SICA_IMASK1)
-#define pSICA_IAR0 	((volatile unsigned long *)SICA_IAR0)
-#define pSICA_IAR1 	((volatile unsigned long *)SICA_IAR1)
-#define pSICA_IAR2 	((volatile unsigned long *)SICA_IAR2)
-#define pSICA_IAR3 	((volatile unsigned long *)SICA_IAR3)
-#define pSICA_IAR4 	((volatile unsigned long *)SICA_IAR4)
-#define pSICA_IAR5 	((volatile unsigned long *)SICA_IAR5)
-#define pSICA_IAR6 	((volatile unsigned long *)SICA_IAR6)
-#define pSICA_IAR7 	((volatile unsigned long *)SICA_IAR7)
-#define pSICA_ISR0 	((volatile unsigned long *)SICA_ISR0)
-#define pSICA_ISR1 	((volatile unsigned long *)SICA_ISR1)
-#define pSICA_IWR0 	((volatile unsigned long *)SICA_IWR0)
-#define pSICA_IWR1 	((volatile unsigned long *)SICA_IWR1)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define pSICB_SWRST 	((volatile unsigned short *)SICB_SWRST)
-#define pSICB_SYSCR 	((volatile unsigned short *)SICB_SYSCR)
-#define pSICB_RVECT 	((volatile unsigned short *)SICB_RVECT)
-#define pSICB_IMASK0 	((volatile unsigned long *)SICB_IMASK0)
-#define pSICB_IMASK1	((volatile unsigned long *)SICB_IMASK1)
-#define pSICB_IAR0 	((volatile unsigned long *)SICB_IAR0)
-#define pSICB_IAR1	((volatile unsigned long *)SICB_IAR1)
-#define pSICB_IAR2	((volatile unsigned long *)SICB_IAR2)
-#define pSICB_IAR3	((volatile unsigned long *)SICB_IAR3)
-#define pSICB_IAR4	((volatile unsigned long *)SICB_IAR4)
-#define pSICB_IAR5	((volatile unsigned long *)SICB_IAR5)
-#define pSICB_IAR6	((volatile unsigned long *)SICB_IAR6)
-#define pSICB_IAR7 	((volatile unsigned long *)SICB_IAR7)
-#define pSICB_ISR0	((volatile unsigned long *)SICB_ISR0)
-#define pSICB_ISR1 	((volatile unsigned long *)SICB_ISR1)
-#define pSICB_IWR0 	((volatile unsigned long *)SICB_IWR0)
-#define pSICB_IWR1 	((volatile unsigned long *)SICB_IWR1)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define pWDOGA_CTL 	((volatile unsigned short *)WDOGA_CTL)
-#define pWDOGA_CNT 	((volatile unsigned long *)WDOGA_CNT)
-#define pWDOGA_STAT 	((volatile unsigned long *)WDOGA_STAT)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define pWDOGB_CTL 	((volatile unsigned short *)WDOGB_CTL)
-#define pWDOGB_CNT 	((volatile unsigned long *)WDOGB_CNT)
-#define pWDOGB_STAT 	((volatile unsigned long *)WDOGB_STAT)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define pUART_THR 	((volatile unsigned short *)UART_THR)
-#define pUART_RBR 	((volatile unsigned short *)UART_RBR)
-#define pUART_DLL 	((volatile unsigned short *)UART_DLL)
-#define pUART_IER 	((volatile unsigned short *)UART_IER)
-#define pUART_DLH 	((volatile unsigned short *)UART_DLH)
-#define pUART_IIR 	((volatile unsigned short *)UART_IIR)
-#define pUART_LCR 	((volatile unsigned short *)UART_LCR)
-#define pUART_MCR 	((volatile unsigned short *)UART_MCR)
-#define pUART_LSR 	((volatile unsigned short *)UART_LSR)
-#define pUART_SCR 	((volatile unsigned short *)UART_SCR)
-#define pUART_GCTL 	((volatile unsigned short *)UART_GCTL)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define pSPI_CTL 	((volatile unsigned short *)SPI_CTL)
-#define pSPI_FLG 	((volatile unsigned short *)SPI_FLG)
-#define pSPI_STAT 	((volatile unsigned short *)SPI_STAT)
-#define pSPI_TDBR 	((volatile unsigned short *)SPI_TDBR)
-#define pSPI_RDBR 	((volatile unsigned short *)SPI_RDBR)
-#define pSPI_BAUD 	((volatile unsigned short *)SPI_BAUD)
-#define pSPI_SHADOW 	((volatile unsigned short *)SPI_SHADOW)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define pTIMER0_CONFIG 	((volatile unsigned short *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 	((volatile unsigned long *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 	((volatile unsigned long *)TIMER0_WIDTH)
-#define pTIMER1_CONFIG 	((volatile unsigned short *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 	((volatile unsigned long *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 	((volatile unsigned long *)TIMER1_WIDTH)
-#define pTIMER2_CONFIG 	((volatile unsigned short *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 	((volatile unsigned long *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 	((volatile unsigned long *)TIMER2_WIDTH)
-#define pTIMER3_CONFIG 	((volatile unsigned short *)TIMER3_CONFIG)
-#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
-#define pTIMER3_PERIOD 	((volatile unsigned long *)TIMER3_PERIOD)
-#define pTIMER3_WIDTH 	((volatile unsigned long *)TIMER3_WIDTH)
-#define pTIMER4_CONFIG 	((volatile unsigned short *)TIMER4_CONFIG)
-#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
-#define pTIMER4_PERIOD 	((volatile unsigned long *)TIMER4_PERIOD)
-#define pTIMER4_WIDTH 	((volatile unsigned long *)TIMER4_WIDTH)
-#define pTIMER5_CONFIG 	((volatile unsigned short *)TIMER5_CONFIG)
-#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
-#define pTIMER5_PERIOD 	((volatile unsigned long *)TIMER5_PERIOD)
-#define pTIMER5_WIDTH 	((volatile unsigned long *)TIMER5_WIDTH)
-#define pTIMER6_CONFIG 	((volatile unsigned short *)TIMER6_CONFIG)
-#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
-#define pTIMER6_PERIOD 	((volatile unsigned long *)TIMER6_PERIOD)
-#define pTIMER6_WIDTH 	((volatile unsigned long *)TIMER6_WIDTH)
-#define pTIMER7_CONFIG 	((volatile unsigned short *)TIMER7_CONFIG)
-#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
-#define pTIMER7_PERIOD 	((volatile unsigned long *)TIMER7_PERIOD)
-#define pTIMER7_WIDTH 	((volatile unsigned long *)TIMER7_WIDTH)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define pTMRS8_ENABLE 	((volatile unsigned short *)TMRS8_ENABLE)
-#define pTMRS8_DISABLE 	((volatile unsigned short *)TMRS8_DISABLE)
-#define pTMRS8_STATUS 	((volatile unsigned long *)TMRS8_STATUS)
-#define pTIMER8_CONFIG 	((volatile unsigned short *)TIMER8_CONFIG)
-#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
-#define pTIMER8_PERIOD 	((volatile unsigned long *)TIMER8_PERIOD)
-#define pTIMER8_WIDTH 	((volatile unsigned long *)TIMER8_WIDTH)
-#define pTIMER9_CONFIG 	((volatile unsigned short *)TIMER9_CONFIG)
-#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
-#define pTIMER9_PERIOD 	((volatile unsigned long *)TIMER9_PERIOD)
-#define pTIMER9_WIDTH 	((volatile unsigned long *)TIMER9_WIDTH)
-#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
-#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
-#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
-#define pTIMER10_WIDTH 	((volatile unsigned long *)TIMER10_WIDTH)
-#define pTIMER11_CONFIG ((volatile unsigned short *)TIMER11_CONFIG)
-#define pTIMER11_COUNTER ((volatile unsigned long *)TIMER11_COUNTER)
-#define pTIMER11_PERIOD ((volatile unsigned long *)TIMER11_PERIOD)
-#define pTIMER11_WIDTH 	((volatile unsigned long *)TIMER11_WIDTH)
-#define pTMRS4_ENABLE 	((volatile unsigned short *)TMRS4_ENABLE)
-#define pTMRS4_DISABLE 	((volatile unsigned short *)TMRS4_DISABLE)
-#define pTMRS4_STATUS 	((volatile unsigned long *)TMRS4_STATUS)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define pFIO0_FLAG_D 	((volatile unsigned short *)FIO0_FLAG_D)
-#define pFIO0_FLAG_C 	((volatile unsigned short *)FIO0_FLAG_C)
-#define pFIO0_FLAG_S 	((volatile unsigned short *)FIO0_FLAG_S)
-#define pFIO0_FLAG_T 	((volatile unsigned short *)FIO0_FLAG_T)
-#define pFIO0_MASKA_D 	((volatile unsigned short *)FIO0_MASKA_D)
-#define pFIO0_MASKA_C 	((volatile unsigned short *)FIO0_MASKA_C)
-#define pFIO0_MASKA_S 	((volatile unsigned short *)FIO0_MASKA_S)
-#define pFIO0_MASKA_T 	((volatile unsigned short *)FIO0_MASKA_T)
-#define pFIO0_MASKB_D 	((volatile unsigned short *)FIO0_MASKB_D)
-#define pFIO0_MASKB_C 	((volatile unsigned short *)FIO0_MASKB_C)
-#define pFIO0_MASKB_S 	((volatile unsigned short *)FIO0_MASKB_S)
-#define pFIO0_MASKB_T 	((volatile unsigned short *)FIO0_MASKB_T)
-#define pFIO0_DIR 	((volatile unsigned short *)FIO0_DIR)
-#define pFIO0_POLAR 	((volatile unsigned short *)FIO0_POLAR)
-#define pFIO0_EDGE 	((volatile unsigned short *)FIO0_EDGE)
-#define pFIO0_BOTH 	((volatile unsigned short *)FIO0_BOTH)
-#define pFIO0_INEN 	((volatile unsigned short *)FIO0_INEN)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define pFIO1_FLAG_D 	((volatile unsigned short *)FIO1_FLAG_D)
-#define pFIO1_FLAG_C 	((volatile unsigned short *)FIO1_FLAG_C)
-#define pFIO1_FLAG_S 	((volatile unsigned short *)FIO1_FLAG_S)
-#define pFIO1_FLAG_T 	((volatile unsigned short *)FIO1_FLAG_T)
-#define pFIO1_MASKA_D 	((volatile unsigned short *)FIO1_MASKA_D)
-#define pFIO1_MASKA_C 	((volatile unsigned short *)FIO1_MASKA_C)
-#define pFIO1_MASKA_S 	((volatile unsigned short *)FIO1_MASKA_S)
-#define pFIO1_MASKA_T 	((volatile unsigned short *)FIO1_MASKA_T)
-#define pFIO1_MASKB_D 	((volatile unsigned short *)FIO1_MASKB_D)
-#define pFIO1_MASKB_C 	((volatile unsigned short *)FIO1_MASKB_C)
-#define pFIO1_MASKB_S 	((volatile unsigned short *)FIO1_MASKB_S)
-#define pFIO1_MASKB_T 	((volatile unsigned short *)FIO1_MASKB_T)
-#define pFIO1_DIR 	((volatile unsigned short *)FIO1_DIR)
-#define pFIO1_POLAR 	((volatile unsigned short *)FIO1_POLAR)
-#define pFIO1_EDGE 	((volatile unsigned short *)FIO1_EDGE)
-#define pFIO1_BOTH 	((volatile unsigned short *)FIO1_BOTH)
-#define pFIO1_INEN 	((volatile unsigned short *)FIO1_INEN)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define pFIO2_FLAG_D 	((volatile unsigned short *)FIO2_FLAG_D)
-#define pFIO2_FLAG_C 	((volatile unsigned short *)FIO2_FLAG_C)
-#define pFIO2_FLAG_S 	((volatile unsigned short *)FIO2_FLAG_S)
-#define pFIO2_FLAG_T 	((volatile unsigned short *)FIO2_FLAG_T)
-#define pFIO2_MASKA_D 	((volatile unsigned short *)FIO2_MASKA_D)
-#define pFIO2_MASKA_C 	((volatile unsigned short *)FIO2_MASKA_C)
-#define pFIO2_MASKA_S 	((volatile unsigned short *)FIO2_MASKA_S)
-#define pFIO2_MASKA_T 	((volatile unsigned short *)FIO2_MASKA_T)
-#define pFIO2_MASKB_D 	((volatile unsigned short *)FIO2_MASKB_D)
-#define pFIO2_MASKB_C 	((volatile unsigned short *)FIO2_MASKB_C)
-#define pFIO2_MASKB_S 	((volatile unsigned short *)FIO2_MASKB_S)
-#define pFIO2_MASKB_T 	((volatile unsigned short *)FIO2_MASKB_T)
-#define pFIO2_DIR 	((volatile unsigned short *)FIO2_DIR)
-#define pFIO2_POLAR 	((volatile unsigned short *)FIO2_POLAR)
-#define pFIO2_EDGE 	((volatile unsigned short *)FIO2_EDGE)
-#define pFIO2_BOTH 	((volatile unsigned short *)FIO2_BOTH)
-#define pFIO2_INEN 	((volatile unsigned short *)FIO2_INEN)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1 	((volatile unsigned short *)SPORT0_TCR1)
-#define pSPORT0_TCR2 	((volatile unsigned short *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 	((volatile unsigned short *)SPORT0_TFSDIV)
-#define pSPORT0_TX 	((volatile unsigned long *)SPORT0_TX)
-#define pSPORT0_RX 	((volatile unsigned long *)SPORT0_RX)
-#define pSPORT0_TX32 	((volatile long *)SPORT0_TX)
-#define pSPORT0_RX32 	((volatile long *)SPORT0_RX)
-#define pSPORT0_TX16 	((volatile unsigned short *)SPORT0_TX)
-#define pSPORT0_RX16 	((volatile unsigned short *)SPORT0_RX)
-#define pSPORT0_RCR1 	((volatile unsigned short *)SPORT0_RCR1)
-#define pSPORT0_RCR2 	((volatile unsigned short *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 	((volatile unsigned short *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 	((volatile unsigned short *)SPORT0_STAT)
-#define pSPORT0_CHNL 	((volatile unsigned short *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 	((volatile unsigned short *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 	((volatile unsigned short *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 	((volatile unsigned long *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 	((volatile unsigned long *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 	((volatile unsigned long *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3	((volatile unsigned long *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0	((volatile unsigned long *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1	((volatile unsigned long *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 	((volatile unsigned long *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 	((volatile unsigned long *)SPORT0_MRCS3)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1 	((volatile unsigned short *)SPORT1_TCR1)
-#define pSPORT1_TCR2 	((volatile unsigned short *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 	((volatile unsigned short *)SPORT1_TFSDIV)
-#define pSPORT1_TX 	((volatile unsigned long *)SPORT1_TX)
-#define pSPORT1_RX 	((volatile unsigned long *)SPORT1_RX)
-#define pSPORT1_TX32 	((volatile long *)SPORT1_TX)
-#define pSPORT1_RX32 	((volatile long *)SPORT1_RX)
-#define pSPORT1_TX16 	((volatile unsigned short *)SPORT1_TX)
-#define pSPORT1_RX16 	((volatile unsigned short *)SPORT1_RX)
-#define pSPORT1_RCR1 	((volatile unsigned short *)SPORT1_RCR1)
-#define pSPORT1_RCR2 	((volatile unsigned short *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 	((volatile unsigned short *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 	((volatile unsigned short *)SPORT1_STAT)
-#define pSPORT1_CHNL 	((volatile unsigned short *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 	((volatile unsigned short *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 	((volatile unsigned short *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 	((volatile unsigned long *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 	((volatile unsigned long *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 	((volatile unsigned long *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 	((volatile unsigned long *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 	((volatile unsigned long *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 	((volatile unsigned long *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 	((volatile unsigned long *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 	((volatile unsigned long *)SPORT1_MRCS3)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define pEBIU_AMGCTL 	((volatile unsigned short *)EBIU_AMGCTL)
-#define pEBIU_AMBCTL0 	((volatile unsigned long *)EBIU_AMBCTL0)
-#define pEBIU_AMBCTL1 	((volatile unsigned long *)EBIU_AMBCTL1)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define pEBIU_SDGCTL 	((volatile unsigned long *)EBIU_SDGCTL)
-#define pEBIU_SDBCTL 	((volatile unsigned long *)EBIU_SDBCTL)
-#define pEBIU_SDRRC 	((volatile unsigned short *)EBIU_SDRRC)
-#define pEBIU_SDSTAT 	((volatile unsigned short *)EBIU_SDSTAT)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define pPPI0_CONTROL 	((volatile unsigned short *)PPI0_CONTROL)
-#define pPPI0_STATUS 	((volatile unsigned short *)PPI0_STATUS)
-#define pPPI0_COUNT 	((volatile unsigned short *)PPI0_COUNT)
-#define pPPI0_DELAY 	((volatile unsigned short *)PPI0_DELAY)
-#define pPPI0_FRAME 	((volatile unsigned short *)PPI0_FRAME)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define pPPI1_CONTROL 	((volatile unsigned short *)PPI1_CONTROL)
-#define pPPI1_STATUS	((volatile unsigned short *)PPI1_STATUS)
-#define pPPI1_COUNT 	((volatile unsigned short *)PPI1_COUNT)
-#define pPPI1_DELAY 	((volatile unsigned short *)PPI1_DELAY)
-#define pPPI1_FRAME 	((volatile unsigned short *)PPI1_FRAME)
-/*DMA traffic control registers */
-#define pDMA1_TC_PER 	((volatile unsigned short *)DMA1_TC_PER)
-#define pDMA1_TC_CNT 	((volatile unsigned short *)DMA1_TC_CNT)
-#define pDMA2_TC_PER 	((volatile unsigned short *)DMA2_TC_PER)
-#define pDMA2_TC_CNT 	((volatile unsigned short *)DMA2_TC_CNT)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define pDMA1_0_CONFIG 		((volatile unsigned short *)DMA1_0_CONFIG)
-#define pDMA1_0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_0_NEXT_DESC_PTR)
-#define pDMA1_0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_0_START_ADDR)
-#define pDMA1_0_X_COUNT 	((volatile unsigned short *)DMA1_0_X_COUNT)
-#define pDMA1_0_Y_COUNT 	((volatile unsigned short *)DMA1_0_Y_COUNT)
-#define pDMA1_0_X_MODIFY 	(volatile signed short *)DMA1_0_X_MODIFY
-#define pDMA1_0_Y_MODIFY 	(volatile signed short *)DMA1_0_Y_MODIFY
-#define pDMA1_0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_0_CURR_DESC_PTR)
-#define pDMA1_0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_0_CURR_ADDR)
-#define pDMA1_0_CURR_X_COUNT 	((volatile unsigned short *)DMA1_0_CURR_X_COUNT)
-#define pDMA1_0_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_0_CURR_Y_COUNT)
-#define pDMA1_0_IRQ_STATUS 	((volatile unsigned short *)DMA1_0_IRQ_STATUS)
-#define pDMA1_0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_0_PERIPHERAL_MAP)
-#define pDMA1_1_CONFIG 		((volatile unsigned short *)DMA1_1_CONFIG)
-#define pDMA1_1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_1_NEXT_DESC_PTR)
-#define pDMA1_1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_1_START_ADDR)
-#define pDMA1_1_X_COUNT 	((volatile unsigned short *)DMA1_1_X_COUNT)
-#define pDMA1_1_Y_COUNT 	((volatile unsigned short *)DMA1_1_Y_COUNT)
-#define pDMA1_1_X_MODIFY 	(volatile signed short *)DMA1_1_X_MODIFY
-#define pDMA1_1_Y_MODIFY 	(volatile signed short *)DMA1_1_Y_MODIFY
-#define pDMA1_1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_1_CURR_DESC_PTR)
-#define pDMA1_1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_1_CURR_ADDR)
-#define pDMA1_1_CURR_X_COUNT 	((volatile unsigned short *)DMA1_1_CURR_X_COUNT)
-#define pDMA1_1_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_1_CURR_Y_COUNT)
-#define pDMA1_1_IRQ_STATUS 	((volatile unsigned short *)DMA1_1_IRQ_STATUS)
-#define pDMA1_1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_1_PERIPHERAL_MAP)
-#define pDMA1_2_CONFIG 		((volatile unsigned short *)DMA1_2_CONFIG)
-#define pDMA1_2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_2_NEXT_DESC_PTR)
-#define pDMA1_2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_2_START_ADDR)
-#define pDMA1_2_X_COUNT 	((volatile unsigned short *)DMA1_2_X_COUNT)
-#define pDMA1_2_Y_COUNT 	((volatile unsigned short *)DMA1_2_Y_COUNT)
-#define pDMA1_2_X_MODIFY 	(volatile signed short *)DMA1_2_X_MODIFY
-#define pDMA1_2_Y_MODIFY 	(volatile signed short *)DMA1_2_Y_MODIFY
-#define pDMA1_2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_2_CURR_DESC_PTR)
-#define pDMA1_2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_2_CURR_ADDR)
-#define pDMA1_2_CURR_X_COUNT 	((volatile unsigned short *)DMA1_2_CURR_X_COUNT)
-#define pDMA1_2_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_2_CURR_Y_COUNT)
-#define pDMA1_2_IRQ_STATUS 	((volatile unsigned short *)DMA1_2_IRQ_STATUS)
-#define pDMA1_2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_2_PERIPHERAL_MAP)
-#define pDMA1_3_CONFIG 		((volatile unsigned short *)DMA1_3_CONFIG)
-#define pDMA1_3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_3_NEXT_DESC_PTR)
-#define pDMA1_3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_3_START_ADDR)
-#define pDMA1_3_X_COUNT 	((volatile unsigned short *)DMA1_3_X_COUNT)
-#define pDMA1_3_Y_COUNT 	((volatile unsigned short *)DMA1_3_Y_COUNT)
-#define pDMA1_3_X_MODIFY 	(volatile signed short *)DMA1_3_X_MODIFY
-#define pDMA1_3_Y_MODIFY 	(volatile signed short *)DMA1_3_Y_MODIFY
-#define pDMA1_3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_3_CURR_DESC_PTR)
-#define pDMA1_3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_3_CURR_ADDR)
-#define pDMA1_3_CURR_X_COUNT 	((volatile unsigned short *)DMA1_3_CURR_X_COUNT)
-#define pDMA1_3_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_3_CURR_Y_COUNT)
-#define pDMA1_3_IRQ_STATUS 	((volatile unsigned short *)DMA1_3_IRQ_STATUS)
-#define pDMA1_3_PERIPHERAL_MAP	((volatile unsigned short *)DMA1_3_PERIPHERAL_MAP)
-#define pDMA1_4_CONFIG 		((volatile unsigned short *)DMA1_4_CONFIG)
-#define pDMA1_4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_4_NEXT_DESC_PTR)
-#define pDMA1_4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_4_START_ADDR)
-#define pDMA1_4_X_COUNT 	((volatile unsigned short *)DMA1_4_X_COUNT)
-#define pDMA1_4_Y_COUNT 	((volatile unsigned short *)DMA1_4_Y_COUNT)
-#define pDMA1_4_X_MODIFY 	(volatile signed short *)DMA1_4_X_MODIFY
-#define pDMA1_4_Y_MODIFY 	(volatile signed short *)DMA1_4_Y_MODIFY
-#define pDMA1_4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_4_CURR_DESC_PTR)
-#define pDMA1_4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_4_CURR_ADDR)
-#define pDMA1_4_CURR_X_COUNT 	((volatile unsigned short *)DMA1_4_CURR_X_COUNT)
-#define pDMA1_4_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_4_CURR_Y_COUNT)
-#define pDMA1_4_IRQ_STATUS 	((volatile unsigned short *)DMA1_4_IRQ_STATUS)
-#define pDMA1_4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_4_PERIPHERAL_MAP)
-#define pDMA1_5_CONFIG 		((volatile unsigned short *)DMA1_5_CONFIG)
-#define pDMA1_5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_5_NEXT_DESC_PTR)
-#define pDMA1_5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_5_START_ADDR)
-#define pDMA1_5_X_COUNT 	((volatile unsigned short *)DMA1_5_X_COUNT)
-#define pDMA1_5_Y_COUNT 	((volatile unsigned short *)DMA1_5_Y_COUNT)
-#define pDMA1_5_X_MODIFY 	(volatile signed short *)DMA1_5_X_MODIFY
-#define pDMA1_5_Y_MODIFY 	(volatile signed short *)DMA1_5_Y_MODIFY
-#define pDMA1_5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_5_CURR_DESC_PTR)
-#define pDMA1_5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_5_CURR_ADDR)
-#define pDMA1_5_CURR_X_COUNT 	((volatile unsigned short *)DMA1_5_CURR_X_COUNT)
-#define pDMA1_5_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_5_CURR_Y_COUNT)
-#define pDMA1_5_IRQ_STATUS 	((volatile unsigned short *)DMA1_5_IRQ_STATUS)
-#define pDMA1_5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_5_PERIPHERAL_MAP)
-#define pDMA1_6_CONFIG 		((volatile unsigned short *)DMA1_6_CONFIG)
-#define pDMA1_6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_6_NEXT_DESC_PTR)
-#define pDMA1_6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_6_START_ADDR)
-#define pDMA1_6_X_COUNT 	((volatile unsigned short *)DMA1_6_X_COUNT)
-#define pDMA1_6_Y_COUNT 	((volatile unsigned short *)DMA1_6_Y_COUNT)
-#define pDMA1_6_X_MODIFY 	(volatile signed short *)DMA1_6_X_MODIFY
-#define pDMA1_6_Y_MODIFY 	(volatile signed short *)DMA1_6_Y_MODIFY
-#define pDMA1_6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_6_CURR_DESC_PTR)
-#define pDMA1_6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_6_CURR_ADDR)
-#define pDMA1_6_CURR_X_COUNT 	((volatile unsigned short *)DMA1_6_CURR_X_COUNT)
-#define pDMA1_6_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_6_CURR_Y_COUNT)
-#define pDMA1_6_IRQ_STATUS 	((volatile unsigned short *)DMA1_6_IRQ_STATUS)
-#define pDMA1_6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_6_PERIPHERAL_MAP)
-#define pDMA1_7_CONFIG 		((volatile unsigned short *)DMA1_7_CONFIG)
-#define pDMA1_7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_7_NEXT_DESC_PTR)
-#define pDMA1_7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_7_START_ADDR)
-#define pDMA1_7_X_COUNT 	((volatile unsigned short *)DMA1_7_X_COUNT)
-#define pDMA1_7_Y_COUNT 	((volatile unsigned short *)DMA1_7_Y_COUNT)
-#define pDMA1_7_X_MODIFY 	(volatile signed short *)DMA1_7_X_MODIFY
-#define pDMA1_7_Y_MODIFY 	(volatile signed short *)DMA1_7_Y_MODIFY
-#define pDMA1_7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_7_CURR_DESC_PTR)
-#define pDMA1_7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_7_CURR_ADDR)
-#define pDMA1_7_CURR_X_COUNT 	((volatile unsigned short *)DMA1_7_CURR_X_COUNT)
-#define pDMA1_7_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_7_CURR_Y_COUNT)
-#define pDMA1_7_IRQ_STATUS 	((volatile unsigned short *)DMA1_7_IRQ_STATUS)
-#define pDMA1_7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_7_PERIPHERAL_MAP)
-#define pDMA1_8_CONFIG 		((volatile unsigned short *)DMA1_8_CONFIG)
-#define pDMA1_8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_8_NEXT_DESC_PTR)
-#define pDMA1_8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_8_START_ADDR)
-#define pDMA1_8_X_COUNT 	((volatile unsigned short *)DMA1_8_X_COUNT)
-#define pDMA1_8_Y_COUNT 	((volatile unsigned short *)DMA1_8_Y_COUNT)
-#define pDMA1_8_X_MODIFY 	(volatile signed short *)DMA1_8_X_MODIFY
-#define pDMA1_8_Y_MODIFY 	(volatile signed short *)DMA1_8_Y_MODIFY
-#define pDMA1_8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_8_CURR_DESC_PTR)
-#define pDMA1_8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_8_CURR_ADDR)
-#define pDMA1_8_CURR_X_COUNT 	((volatile unsigned short *)DMA1_8_CURR_X_COUNT)
-#define pDMA1_8_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_8_CURR_Y_COUNT)
-#define pDMA1_8_IRQ_STATUS 	((volatile unsigned short *)DMA1_8_IRQ_STATUS)
-#define pDMA1_8_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_8_PERIPHERAL_MAP)
-#define pDMA1_9_CONFIG 		((volatile unsigned short *)DMA1_9_CONFIG)
-#define pDMA1_9_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_9_NEXT_DESC_PTR)
-#define pDMA1_9_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_9_START_ADDR)
-#define pDMA1_9_X_COUNT 	((volatile unsigned short *)DMA1_9_X_COUNT)
-#define pDMA1_9_Y_COUNT 	((volatile unsigned short *)DMA1_9_Y_COUNT)
-#define pDMA1_9_X_MODIFY 	(volatile signed short *)DMA1_9_X_MODIFY
-#define pDMA1_9_Y_MODIFY 	(volatile signed short *)DMA1_9_Y_MODIFY
-#define pDMA1_9_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_9_CURR_DESC_PTR)
-#define pDMA1_9_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_9_CURR_ADDR)
-#define pDMA1_9_CURR_X_COUNT 	((volatile unsigned short *)DMA1_9_CURR_X_COUNT)
-#define pDMA1_9_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_9_CURR_Y_COUNT)
-#define pDMA1_9_IRQ_STATUS 	((volatile unsigned short *)DMA1_9_IRQ_STATUS)
-#define pDMA1_9_PERIPHERAL_MAP 	((volatile unsigned short *)DMA1_9_PERIPHERAL_MAP)
-#define pDMA1_10_CONFIG 	((volatile unsigned short *)DMA1_10_CONFIG)
-#define pDMA1_10_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_10_NEXT_DESC_PTR)
-#define pDMA1_10_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_10_START_ADDR)
-#define pDMA1_10_X_COUNT 	((volatile unsigned short *)DMA1_10_X_COUNT)
-#define pDMA1_10_Y_COUNT 	((volatile unsigned short *)DMA1_10_Y_COUNT)
-#define pDMA1_10_X_MODIFY 	(volatile signed short *)DMA1_10_X_MODIFY
-#define pDMA1_10_Y_MODIFY 	(volatile signed short *)DMA1_10_Y_MODIFY
-#define pDMA1_10_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_10_CURR_DESC_PTR)
-#define pDMA1_10_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_10_CURR_ADDR)
-#define pDMA1_10_CURR_X_COUNT 	((volatile unsigned short *)DMA1_10_CURR_X_COUNT)
-#define pDMA1_10_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_10_CURR_Y_COUNT)
-#define pDMA1_10_IRQ_STATUS 	((volatile unsigned short *)DMA1_10_IRQ_STATUS)
-#define pDMA1_10_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_10_PERIPHERAL_MAP)
-#define pDMA1_11_CONFIG 	((volatile unsigned short *)DMA1_11_CONFIG)
-#define pDMA1_11_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_11_NEXT_DESC_PTR)
-#define pDMA1_11_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_11_START_ADDR)
-#define pDMA1_11_X_COUNT 	((volatile unsigned short *)DMA1_11_X_COUNT)
-#define pDMA1_11_Y_COUNT 	((volatile unsigned short *)DMA1_11_Y_COUNT)
-#define pDMA1_11_X_MODIFY 	(volatile signed short *)DMA1_11_X_MODIFY
-#define pDMA1_11_Y_MODIFY 	(volatile signed short *)DMA1_11_Y_MODIFY
-#define pDMA1_11_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_11_CURR_DESC_PTR)
-#define pDMA1_11_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_11_CURR_ADDR)
-#define pDMA1_11_CURR_X_COUNT 	((volatile unsigned short *)DMA1_11_CURR_X_COUNT)
-#define pDMA1_11_CURR_Y_COUNT 	((volatile unsigned short *)DMA1_11_CURR_Y_COUNT)
-#define pDMA1_11_IRQ_STATUS 	((volatile unsigned short *)DMA1_11_IRQ_STATUS)
-#define pDMA1_11_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_11_PERIPHERAL_MAP)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define pMDMA1_D0_CONFIG 	((volatile unsigned short *)MDMA1_D0_CONFIG)
-#define pMDMA1_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_NEXT_DESC_PTR)
-#define pMDMA1_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_D0_START_ADDR)
-#define pMDMA1_D0_X_COUNT 	((volatile unsigned short *)MDMA1_D0_X_COUNT)
-#define pMDMA1_D0_Y_COUNT 	((volatile unsigned short *)MDMA1_D0_Y_COUNT)
-#define pMDMA1_D0_X_MODIFY 	(volatile signed short *)MDMA1_D0_X_MODIFY
-#define pMDMA1_D0_Y_MODIFY 	(volatile signed short *)MDMA1_D0_Y_MODIFY
-#define pMDMA1_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_DESC_PTR)
-#define pMDMA1_D0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_ADDR)
-#define pMDMA1_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT	)
-#define pMDMA1_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
-#define pMDMA1_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
-#define pMDMA1_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
-#define pMDMA1_S0_CONFIG 	((volatile unsigned short *)MDMA1_S0_CONFIG)
-#define pMDMA1_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_NEXT_DESC_PTR)
-#define pMDMA1_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_S0_START_ADDR)
-#define pMDMA1_S0_X_COUNT 	((volatile unsigned short *)MDMA1_S0_X_COUNT)
-#define pMDMA1_S0_Y_COUNT 	((volatile unsigned short *)MDMA1_S0_Y_COUNT)
-#define pMDMA1_S0_X_MODIFY 	(volatile signed short *)MDMA1_S0_X_MODIFY
-#define pMDMA1_S0_Y_MODIFY 	(volatile signed short *)MDMA1_S0_Y_MODIFY
-#define pMDMA1_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_DESC_PTR)
-#define pMDMA1_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_ADDR)
-#define pMDMA1_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
-#define pMDMA1_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
-#define pMDMA1_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
-#define pMDMA1_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
-#define pMDMA1_D1_CONFIG 	((volatile unsigned short *)MDMA1_D1_CONFIG)
-#define pMDMA1_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_NEXT_DESC_PTR)
-#define pMDMA1_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_D1_START_ADDR)
-#define pMDMA1_D1_X_COUNT 	((volatile unsigned short *)MDMA1_D1_X_COUNT)
-#define pMDMA1_D1_Y_COUNT 	((volatile unsigned short *)MDMA1_D1_Y_COUNT)
-#define pMDMA1_D1_X_MODIFY 	(volatile signed short *)MDMA1_D1_X_MODIFY
-#define pMDMA1_D1_Y_MODIFY 	(volatile signed short *)MDMA1_D1_Y_MODIFY
-#define pMDMA1_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_DESC_PTR)
-#define pMDMA1_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_ADDR)
-#define pMDMA1_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
-#define pMDMA1_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
-#define pMDMA1_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
-#define pMDMA1_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
-#define pMDMA1_S1_CONFIG 	((volatile unsigned short *)MDMA1_S1_CONFIG)
-#define pMDMA1_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_NEXT_DESC_PTR)
-#define pMDMA1_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_S1_START_ADDR)
-#define pMDMA1_S1_X_COUNT 	((volatile unsigned short *)MDMA1_S1_X_COUNT)
-#define pMDMA1_S1_Y_COUNT 	((volatile unsigned short *)MDMA1_S1_Y_COUNT)
-#define pMDMA1_S1_X_MODIFY 	(volatile signed short *)MDMA1_S1_X_MODIFY
-#define pMDMA1_S1_Y_MODIFY 	(volatile signed short *)MDMA1_S1_Y_MODIFY
-#define pMDMA1_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_DESC_PTR)
-#define pMDMA1_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_ADDR)
-#define pMDMA1_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
-#define pMDMA1_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
-#define pMDMA1_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
-#define pMDMA1_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define pDMA2_0_CONFIG 		((volatile unsigned short *)DMA2_0_CONFIG)
-#define pDMA2_0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_0_NEXT_DESC_PTR)
-#define pDMA2_0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_0_START_ADDR)
-#define pDMA2_0_X_COUNT 	((volatile unsigned short *)DMA2_0_X_COUNT)
-#define pDMA2_0_Y_COUNT 	((volatile unsigned short *)DMA2_0_Y_COUNT)
-#define pDMA2_0_X_MODIFY 	(volatile signed short *)DMA2_0_X_MODIFY
-#define pDMA2_0_Y_MODIFY 	(volatile signed short *)DMA2_0_Y_MODIFY
-#define pDMA2_0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_0_CURR_DESC_PTR)
-#define pDMA2_0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_0_CURR_ADDR)
-#define pDMA2_0_CURR_X_COUNT 	((volatile unsigned short *)DMA2_0_CURR_X_COUNT)
-#define pDMA2_0_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_0_CURR_Y_COUNT)
-#define pDMA2_0_IRQ_STATUS 	((volatile unsigned short *)DMA2_0_IRQ_STATUS)
-#define pDMA2_0_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_0_PERIPHERAL_MAP)
-#define pDMA2_1_CONFIG 		((volatile unsigned short *)DMA2_1_CONFIG)
-#define pDMA2_1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_1_NEXT_DESC_PTR)
-#define pDMA2_1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_1_START_ADDR)
-#define pDMA2_1_X_COUNT 	((volatile unsigned short *)DMA2_1_X_COUNT)
-#define pDMA2_1_Y_COUNT 	((volatile unsigned short *)DMA2_1_Y_COUNT)
-#define pDMA2_1_X_MODIFY 	(volatile signed short *)DMA2_1_X_MODIFY
-#define pDMA2_1_Y_MODIFY 	(volatile signed short *)DMA2_1_Y_MODIFY
-#define pDMA2_1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_1_CURR_DESC_PTR)
-#define pDMA2_1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_1_CURR_ADDR)
-#define pDMA2_1_CURR_X_COUNT 	((volatile unsigned short *)DMA2_1_CURR_X_COUNT)
-#define pDMA2_1_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_1_CURR_Y_COUNT)
-#define pDMA2_1_IRQ_STATUS 	((volatile unsigned short *)DMA2_1_IRQ_STATUS)
-#define pDMA2_1_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_1_PERIPHERAL_MAP)
-#define pDMA2_2_CONFIG 		((volatile unsigned short *)DMA2_2_CONFIG)
-#define pDMA2_2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_2_NEXT_DESC_PTR)
-#define pDMA2_2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_2_START_ADDR)
-#define pDMA2_2_X_COUNT 	((volatile unsigned short *)DMA2_2_X_COUNT)
-#define pDMA2_2_Y_COUNT 	((volatile unsigned short *)DMA2_2_Y_COUNT)
-#define pDMA2_2_X_MODIFY 	(volatile signed short *)DMA2_2_X_MODIFY
-#define pDMA2_2_Y_MODIFY 	(volatile signed short *)DMA2_2_Y_MODIFY
-#define pDMA2_2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_2_CURR_DESC_PTR)
-#define pDMA2_2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_2_CURR_ADDR)
-#define pDMA2_2_CURR_X_COUNT 	((volatile unsigned short *)DMA2_2_CURR_X_COUNT)
-#define pDMA2_2_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_2_CURR_Y_COUNT)
-#define pDMA2_2_IRQ_STATUS 	((volatile unsigned short *)DMA2_2_IRQ_STATUS)
-#define pDMA2_2_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_2_PERIPHERAL_MAP)
-#define pDMA2_3_CONFIG 		((volatile unsigned short *)DMA2_3_CONFIG)
-#define pDMA2_3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_3_NEXT_DESC_PTR)
-#define pDMA2_3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_3_START_ADDR)
-#define pDMA2_3_X_COUNT 	((volatile unsigned short *)DMA2_3_X_COUNT)
-#define pDMA2_3_Y_COUNT 	((volatile unsigned short *)DMA2_3_Y_COUNT)
-#define pDMA2_3_X_MODIFY 	(volatile signed short *)DMA2_3_X_MODIFY
-#define pDMA2_3_Y_MODIFY 	(volatile signed short *)DMA2_3_Y_MODIFY
-#define pDMA2_3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_3_CURR_DESC_PTR)
-#define pDMA2_3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_3_CURR_ADDR)
-#define pDMA2_3_CURR_X_COUNT 	((volatile unsigned short *)DMA2_3_CURR_X_COUNT)
-#define pDMA2_3_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_3_CURR_Y_COUNT)
-#define pDMA2_3_IRQ_STATUS 	((volatile unsigned short *)DMA2_3_IRQ_STATUS)
-#define pDMA2_3_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_3_PERIPHERAL_MAP)
-#define pDMA2_4_CONFIG 		((volatile unsigned short *)DMA2_4_CONFIG)
-#define pDMA2_4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_4_NEXT_DESC_PTR)
-#define pDMA2_4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_4_START_ADDR)
-#define pDMA2_4_X_COUNT 	((volatile unsigned short *)DMA2_4_X_COUNT)
-#define pDMA2_4_Y_COUNT 	((volatile unsigned short *)DMA2_4_Y_COUNT)
-#define pDMA2_4_X_MODIFY 	(volatile signed short *)DMA2_4_X_MODIFY
-#define pDMA2_4_Y_MODIFY 	(volatile signed short *)DMA2_4_Y_MODIFY
-#define pDMA2_4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_4_CURR_DESC_PTR)
-#define pDMA2_4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_4_CURR_ADDR)
-#define pDMA2_4_CURR_X_COUNT 	((volatile unsigned short *)DMA2_4_CURR_X_COUNT)
-#define pDMA2_4_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_4_CURR_Y_COUNT)
-#define pDMA2_4_IRQ_STATUS 	((volatile unsigned short *)DMA2_4_IRQ_STATUS)
-#define pDMA2_4_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_4_PERIPHERAL_MAP)
-#define pDMA2_5_CONFIG 		((volatile unsigned short *)DMA2_5_CONFIG)
-#define pDMA2_5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_5_NEXT_DESC_PTR)
-#define pDMA2_5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_5_START_ADDR)
-#define pDMA2_5_X_COUNT 	((volatile unsigned short *)DMA2_5_X_COUNT)
-#define pDMA2_5_Y_COUNT 	((volatile unsigned short *)DMA2_5_Y_COUNT)
-#define pDMA2_5_X_MODIFY 	(volatile signed short *)DMA2_5_X_MODIFY
-#define pDMA2_5_Y_MODIFY 	(volatile signed short *)DMA2_5_Y_MODIFY
-#define pDMA2_5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_5_CURR_DESC_PTR)
-#define pDMA2_5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_5_CURR_ADDR)
-#define pDMA2_5_CURR_X_COUNT 	((volatile unsigned short *)DMA2_5_CURR_X_COUNT)
-#define pDMA2_5_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_5_CURR_Y_COUNT)
-#define pDMA2_5_IRQ_STATUS 	((volatile unsigned short *)DMA2_5_IRQ_STATUS)
-#define pDMA2_5_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_5_PERIPHERAL_MAP)
-#define pDMA2_6_CONFIG 		((volatile unsigned short *)DMA2_6_CONFIG)
-#define pDMA2_6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_6_NEXT_DESC_PTR)
-#define pDMA2_6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_6_START_ADDR)
-#define pDMA2_6_X_COUNT 	((volatile unsigned short *)DMA2_6_X_COUNT)
-#define pDMA2_6_Y_COUNT 	((volatile unsigned short *)DMA2_6_Y_COUNT)
-#define pDMA2_6_X_MODIFY 	(volatile signed short *)DMA2_6_X_MODIFY
-#define pDMA2_6_Y_MODIFY 	(volatile signed short *)DMA2_6_Y_MODIFY
-#define pDMA2_6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_6_CURR_DESC_PTR)
-#define pDMA2_6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_6_CURR_ADDR)
-#define pDMA2_6_CURR_X_COUNT 	((volatile unsigned short *)DMA2_6_CURR_X_COUNT)
-#define pDMA2_6_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_6_CURR_Y_COUNT)
-#define pDMA2_6_IRQ_STATUS 	((volatile unsigned short *)DMA2_6_IRQ_STATUS)
-#define pDMA2_6_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_6_PERIPHERAL_MAP)
-#define pDMA2_7_CONFIG 		((volatile unsigned short *)DMA2_7_CONFIG)
-#define pDMA2_7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_7_NEXT_DESC_PTR)
-#define pDMA2_7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_7_START_ADDR)
-#define pDMA2_7_X_COUNT 	((volatile unsigned short *)DMA2_7_X_COUNT)
-#define pDMA2_7_Y_COUNT 	((volatile unsigned short *)DMA2_7_Y_COUNT)
-#define pDMA2_7_X_MODIFY 	(volatile signed short *)DMA2_7_X_MODIFY
-#define pDMA2_7_Y_MODIFY 	(volatile signed short *)DMA2_7_Y_MODIFY
-#define pDMA2_7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_7_CURR_DESC_PTR)
-#define pDMA2_7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_7_CURR_ADDR)
-#define pDMA2_7_CURR_X_COUNT 	((volatile unsigned short *)DMA2_7_CURR_X_COUNT)
-#define pDMA2_7_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_7_CURR_Y_COUNT)
-#define pDMA2_7_IRQ_STATUS 	((volatile unsigned short *)DMA2_7_IRQ_STATUS)
-#define pDMA2_7_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_7_PERIPHERAL_MAP)
-#define pDMA2_8_CONFIG 		((volatile unsigned short *)DMA2_8_CONFIG)
-#define pDMA2_8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_8_NEXT_DESC_PTR)
-#define pDMA2_8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_8_START_ADDR)
-#define pDMA2_8_X_COUNT 	((volatile unsigned short *)DMA2_8_X_COUNT)
-#define pDMA2_8_Y_COUNT 	((volatile unsigned short *)DMA2_8_Y_COUNT)
-#define pDMA2_8_X_MODIFY 	(volatile signed short *)DMA2_8_X_MODIFY
-#define pDMA2_8_Y_MODIFY 	(volatile signed short *)DMA2_8_Y_MODIFY
-#define pDMA2_8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_8_CURR_DESC_PTR)
-#define pDMA2_8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_8_CURR_ADDR)
-#define pDMA2_8_CURR_X_COUNT 	((volatile unsigned short *)DMA2_8_CURR_X_COUNT)
-#define pDMA2_8_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_8_CURR_Y_COUNT)
-#define pDMA2_8_IRQ_STATUS 	((volatile unsigned short *)DMA2_8_IRQ_STATUS)
-#define pDMA2_8_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_8_PERIPHERAL_MAP)
-#define pDMA2_9_CONFIG 		((volatile unsigned short *)DMA2_9_CONFIG)
-#define pDMA2_9_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_9_NEXT_DESC_PTR)
-#define pDMA2_9_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_9_START_ADDR)
-#define pDMA2_9_X_COUNT 	((volatile unsigned short *)DMA2_9_X_COUNT)
-#define pDMA2_9_Y_COUNT 	((volatile unsigned short *)DMA2_9_Y_COUNT)
-#define pDMA2_9_X_MODIFY 	(volatile signed short *)DMA2_9_X_MODIFY
-#define pDMA2_9_Y_MODIFY 	(volatile signed short *)DMA2_9_Y_MODIFY
-#define pDMA2_9_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_9_CURR_DESC_PTR)
-#define pDMA2_9_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_9_CURR_ADDR)
-#define pDMA2_9_CURR_X_COUNT 	((volatile unsigned short *)DMA2_9_CURR_X_COUNT)
-#define pDMA2_9_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_9_CURR_Y_COUNT)
-#define pDMA2_9_IRQ_STATUS 	((volatile unsigned short *)DMA2_9_IRQ_STATUS)
-#define pDMA2_9_PERIPHERAL_MAP 	((volatile unsigned short *)DMA2_9_PERIPHERAL_MAP)
-#define pDMA2_10_CONFIG		((volatile unsigned short *)DMA2_10_CONFIG)
-#define pDMA2_10_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_10_NEXT_DESC_PTR)
-#define pDMA2_10_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_10_START_ADDR)
-#define pDMA2_10_X_COUNT 	((volatile unsigned short *)DMA2_10_X_COUNT)
-#define pDMA2_10_Y_COUNT 	((volatile unsigned short *)DMA2_10_Y_COUNT)
-#define pDMA2_10_X_MODIFY 	(volatile signed short *)DMA2_10_X_MODIFY
-#define pDMA2_10_Y_MODIFY 	(volatile signed short *)DMA2_10_Y_MODIFY
-#define pDMA2_10_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_10_CURR_DESC_PTR)
-#define pDMA2_10_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_10_CURR_ADDR)
-#define pDMA2_10_CURR_X_COUNT 	((volatile unsigned short *)DMA2_10_CURR_X_COUNT)
-#define pDMA2_10_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_10_CURR_Y_COUNT)
-#define pDMA2_10_IRQ_STATUS 	((volatile unsigned short *)DMA2_10_IRQ_STATUS)
-#define pDMA2_10_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_10_PERIPHERAL_MAP)
-#define pDMA2_11_CONFIG 	((volatile unsigned short *)DMA2_11_CONFIG)
-#define pDMA2_11_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_11_NEXT_DESC_PTR)
-#define pDMA2_11_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_11_START_ADDR)
-#define pDMA2_11_X_COUNT 	((volatile unsigned short *)DMA2_11_X_COUNT)
-#define pDMA2_11_Y_COUNT 	((volatile unsigned short *)DMA2_11_Y_COUNT)
-#define pDMA2_11_X_MODIFY 	(volatile signed short *)DMA2_11_X_MODIFY
-#define pDMA2_11_Y_MODIFY 	(volatile signed short *)DMA2_11_Y_MODIFY
-#define pDMA2_11_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_11_CURR_DESC_PTR)
-#define pDMA2_11_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_11_CURR_ADDR)
-#define pDMA2_11_CURR_X_COUNT 	((volatile unsigned short *)DMA2_11_CURR_X_COUNT)
-#define pDMA2_11_CURR_Y_COUNT 	((volatile unsigned short *)DMA2_11_CURR_Y_COUNT)
-#define pDMA2_11_IRQ_STATUS 	((volatile unsigned short *)DMA2_11_IRQ_STATUS)
-#define pDMA2_11_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_11_PERIPHERAL_MAP)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define pMDMA2_D0_CONFIG 	((volatile unsigned short *)MDMA2_D0_CONFIG)
-#define pMDMA2_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_NEXT_DESC_PTR)
-#define pMDMA2_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_D0_START_ADDR)
-#define pMDMA2_D0_X_COUNT 	((volatile unsigned short *)MDMA2_D0_X_COUNT)
-#define pMDMA2_D0_Y_COUNT 	((volatile unsigned short *)MDMA2_D0_Y_COUNT)
-#define pMDMA2_D0_X_MODIFY 	(volatile signed short *)MDMA2_D0_X_MODIFY
-#define pMDMA2_D0_Y_MODIFY 	(volatile signed short *)MDMA2_D0_Y_MODIFY
-#define pMDMA2_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_DESC_PTR)
-#define pMDMA2_D0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_ADDR)
-#define pMDMA2_D0_CURR_X_COUNT 	((volatile unsigned short *)MDMA2_D0_CURR_X_COUNT)
-#define pMDMA2_D0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT)
-#define pMDMA2_D0_IRQ_STATUS 	((volatile unsigned short *)MDMA2_D0_IRQ_STATUS)
-#define pMDMA2_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP)
-#define pMDMA2_S0_CONFIG 	((volatile unsigned short *)MDMA2_S0_CONFIG)
-#define pMDMA2_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_NEXT_DESC_PTR)
-#define pMDMA2_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_S0_START_ADDR)
-#define pMDMA2_S0_X_COUNT 	((volatile unsigned short *)MDMA2_S0_X_COUNT)
-#define pMDMA2_S0_Y_COUNT 	((volatile unsigned short *)MDMA2_S0_Y_COUNT)
-#define pMDMA2_S0_X_MODIFY 	(volatile signed short *)MDMA2_S0_X_MODIFY
-#define pMDMA2_S0_Y_MODIFY 	(volatile signed short *)MDMA2_S0_Y_MODIFY
-#define pMDMA2_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_DESC_PTR)
-#define pMDMA2_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_ADDR)
-#define pMDMA2_S0_CURR_X_COUNT 	((volatile unsigned short *)MDMA2_S0_CURR_X_COUNT)
-#define pMDMA2_S0_CURR_Y_COUNT 	((volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT)
-#define pMDMA2_S0_IRQ_STATUS 	((volatile unsigned short *)MDMA2_S0_IRQ_STATUS)
-#define pMDMA2_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP)
-#define pMDMA2_D1_CONFIG 	((volatile unsigned short *)MDMA2_D1_CONFIG)
-#define pMDMA2_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_NEXT_DESC_PTR)
-#define pMDMA2_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_D1_START_ADDR)
-#define pMDMA2_D1_X_COUNT 	((volatile unsigned short *)MDMA2_D1_X_COUNT)
-#define pMDMA2_D1_Y_COUNT 	((volatile unsigned short *)MDMA2_D1_Y_COUNT)
-#define pMDMA2_D1_X_MODIFY 	(volatile signed short *)MDMA2_D1_X_MODIFY
-#define pMDMA2_D1_Y_MODIFY 	(volatile signed short *)MDMA2_D1_Y_MODIFY
-#define pMDMA2_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_DESC_PTR)
-#define pMDMA2_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_ADDR)
-#define pMDMA2_D1_CURR_X_COUNT 	((volatile unsigned short *)MDMA2_D1_CURR_X_COUNT)
-#define pMDMA2_D1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT)
-#define pMDMA2_D1_IRQ_STATUS 	((volatile unsigned short *)MDMA2_D1_IRQ_STATUS)
-#define pMDMA2_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP)
-#define pMDMA2_S1_CONFIG 	((volatile unsigned short *)MDMA2_S1_CONFIG)
-#define pMDMA2_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_NEXT_DESC_PTR)
-#define pMDMA2_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_S1_START_ADDR)
-#define pMDMA2_S1_X_COUNT 	((volatile unsigned short *)MDMA2_S1_X_COUNT)
-#define pMDMA2_S1_Y_COUNT 	((volatile unsigned short *)MDMA2_S1_Y_COUNT)
-#define pMDMA2_S1_X_MODIFY 	(volatile signed short *)MDMA2_S1_X_MODIFY
-#define pMDMA2_S1_Y_MODIFY 	(volatile signed short *)MDMA2_S1_Y_MODIFY
-#define pMDMA2_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_DESC_PTR)
-#define pMDMA2_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_ADDR)
-#define pMDMA2_S1_CURR_X_COUNT 	((volatile unsigned short *)MDMA2_S1_CURR_X_COUNT)
-#define pMDMA2_S1_CURR_Y_COUNT 	((volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT)
-#define pMDMA2_S1_IRQ_STATUS 	((volatile unsigned short *)MDMA2_S1_IRQ_STATUS)
-#define pMDMA2_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define pIMDMA_D0_CONFIG 	((volatile unsigned short *)IMDMA_D0_CONFIG)
-#define pIMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_NEXT_DESC_PTR)
-#define pIMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_D0_START_ADDR)
-#define pIMDMA_D0_X_COUNT 	((volatile unsigned short *)IMDMA_D0_X_COUNT)
-#define pIMDMA_D0_Y_COUNT 	((volatile unsigned short *)IMDMA_D0_Y_COUNT)
-#define pIMDMA_D0_X_MODIFY 	(volatile signed short *)IMDMA_D0_X_MODIFY
-#define pIMDMA_D0_Y_MODIFY 	(volatile signed short *)IMDMA_D0_Y_MODIFY
-#define pIMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_DESC_PTR)
-#define pIMDMA_D0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_ADDR)
-#define pIMDMA_D0_CURR_X_COUNT 	((volatile unsigned short *)IMDMA_D0_CURR_X_COUNT)
-#define pIMDMA_D0_CURR_Y_COUNT 	((volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT)
-#define pIMDMA_D0_IRQ_STATUS 	((volatile unsigned short *)IMDMA_D0_IRQ_STATUS)
-#define pIMDMA_S0_CONFIG 	((volatile unsigned short *)IMDMA_S0_CONFIG)
-#define pIMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_NEXT_DESC_PTR)
-#define pIMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_S0_START_ADDR)
-#define pIMDMA_S0_X_COUNT 	((volatile unsigned short *)IMDMA_S0_X_COUNT)
-#define pIMDMA_S0_Y_COUNT 	((volatile unsigned short *)IMDMA_S0_Y_COUNT)
-#define pIMDMA_S0_X_MODIFY 	(volatile signed short *)IMDMA_S0_X_MODIFY
-#define pIMDMA_S0_Y_MODIFY 	(volatile signed short *)IMDMA_S0_Y_MODIFY
-#define pIMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_DESC_PTR)
-#define pIMDMA_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_ADDR)
-#define pIMDMA_S0_CURR_X_COUNT 	((volatile unsigned short *)IMDMA_S0_CURR_X_COUNT)
-#define pIMDMA_S0_CURR_Y_COUNT 	((volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT)
-#define pIMDMA_S0_IRQ_STATUS 	((volatile unsigned short *)IMDMA_S0_IRQ_STATUS)
-#define pIMDMA_D1_CONFIG 	((volatile unsigned short *)IMDMA_D1_CONFIG)
-#define pIMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_NEXT_DESC_PTR)
-#define pIMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_D1_START_ADDR)
-#define pIMDMA_D1_X_COUNT 	((volatile unsigned short *)IMDMA_D1_X_COUNT)
-#define pIMDMA_D1_Y_COUNT 	((volatile unsigned short *)IMDMA_D1_Y_COUNT)
-#define pIMDMA_D1_X_MODIFY 	(volatile signed short *)IMDMA_D1_X_MODIFY
-#define pIMDMA_D1_Y_MODIFY 	(volatile signed short *)IMDMA_D1_Y_MODIFY
-#define pIMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_DESC_PTR)
-#define pIMDMA_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_ADDR)
-#define pIMDMA_D1_CURR_X_COUNT 	((volatile unsigned short *)IMDMA_D1_CURR_X_COUNT)
-#define pIMDMA_D1_CURR_Y_COUNT 	((volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT)
-#define pIMDMA_D1_IRQ_STATUS 	((volatile unsigned short *)IMDMA_D1_IRQ_STATUS)
-#define pIMDMA_S1_CONFIG 	((volatile unsigned short *)IMDMA_S1_CONFIG)
-#define pIMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_NEXT_DESC_PTR)
-#define pIMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_S1_START_ADDR)
-#define pIMDMA_S1_X_COUNT 	((volatile unsigned short *)IMDMA_S1_X_COUNT)
-#define pIMDMA_S1_Y_COUNT 	((volatile unsigned short *)IMDMA_S1_Y_COUNT)
-#define pIMDMA_S1_X_MODIFY 	(volatile signed short *)IMDMA_S1_X_MODIFY
-#define pIMDMA_S1_Y_MODIFY 	(volatile signed short *)IMDMA_S1_Y_MODIFY
-#define pIMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_DESC_PTR)
-#define pIMDMA_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_ADDR)
-#define pIMDMA_S1_CURR_X_COUNT 	((volatile unsigned short *)IMDMA_S1_CURR_X_COUNT)
-#define pIMDMA_S1_CURR_Y_COUNT 	((volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT)
-#define pIMDMA_S1_IRQ_STATUS 	((volatile unsigned short *)IMDMA_S1_IRQ_STATUS)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BF561_H */
diff --git a/libgloss/bfin/include/cdefBF592-A.h b/libgloss/bfin/include/cdefBF592-A.h
deleted file mode 100644
index ba78c119d..000000000
--- a/libgloss/bfin/include/cdefBF592-A.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF592-A peripherals.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _CDEF_BF592A_H
-#define _CDEF_BF592A_H
-
-/* include parts registers and bit definitions */
-#include <defBF592-A.h>
-
-/* include the core specific definitions */
-#include <cdef_LPBlackfin.h>
-
-/* include the family common definitions */
-#include <cdefBF59x_base.h>
-
-#endif /* _CDEF_BF592A_H */
diff --git a/libgloss/bfin/include/cdefBF59x_base.h b/libgloss/bfin/include/cdefBF59x_base.h
deleted file mode 100644
index 3dbfaa3a6..000000000
--- a/libgloss/bfin/include/cdefBF59x_base.h
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** cdefBF59x_base.h
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF59x peripherals.
-**
-***************************************************************/
-
-#ifndef _CDEF_BF59x_H
-#define _CDEF_BF59x_H
-
-#include <defBF59x_base.h>
-#include <stdint.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-
-/* Clock and System Control 	(0xFFC00000 - 0xFFC000FF) */
-#define pPLL_CTL 			((volatile uint16_t *)PLL_CTL)
-#define pPLL_DIV 			((volatile uint16_t *)PLL_DIV)
-#define pVR_CTL 			((volatile uint16_t *)VR_CTL)
-#define pPLL_STAT 		((volatile uint16_t *)PLL_STAT)
-#define pPLL_LOCKCNT 		((volatile uint16_t *)PLL_LOCKCNT)
-#define pCHIPID			((volatile uint32_t *)CHIPID)
-#define pAUX_REVID			((volatile uint32_t *)AUX_REVID)
-
-
-/* System Interrupt Controller(0xFFC00100 - 0xFFC001FF) */
-#define pSWRST 			((volatile uint16_t *)SWRST)
-#define pSYSCR 			((volatile uint16_t *)SYSCR)
-
-#define pSIC_IMASK0 	((volatile uint32_t *)SIC_IMASK0)
-#define pSIC_IAR0 		((volatile uint32_t *)SIC_IAR0)
-#define pSIC_IAR1 		((volatile uint32_t *)SIC_IAR1)
-#define pSIC_IAR2 		((volatile uint32_t *)SIC_IAR2)
-#define pSIC_IAR3 		((volatile uint32_t *)SIC_IAR3)
-#define pSIC_ISR0 		((volatile uint32_t *)SIC_ISR0)
-#define pSIC_IWR0 		((volatile uint32_t *)SIC_IWR0)
-
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IMASK 		((volatile uint32_t *)SIC_IMASK0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_ISR 		((volatile uint32_t *)SIC_ISR0)
-/* legacy register name (below) provided for backwards code compatibility */
-#define pSIC_IWR 		((volatile uint32_t *)SIC_IWR0)
-
-
-/* Watchdog Timer 		(0xFFC00200 - 0xFFC002FF) */
-#define pWDOG_CTL 		((volatile uint16_t *)WDOG_CTL)
-#define pWDOG_CNT 		((volatile uint32_t *)WDOG_CNT)
-#define pWDOG_STAT 		((volatile uint32_t *)WDOG_STAT)
-
-
-/* UART0 Controller 		(0xFFC00400 - 0xFFC004FF) */
-#define pUART0_THR 		((volatile uint16_t *)UART0_THR)
-#define pUART0_RBR 		((volatile uint16_t *)UART0_RBR)
-#define pUART0_DLL 		((volatile uint16_t *)UART0_DLL)
-#define pUART0_IER 		((volatile uint16_t *)UART0_IER)
-#define pUART0_DLH 		((volatile uint16_t *)UART0_DLH)
-#define pUART0_IIR 		((volatile uint16_t *)UART0_IIR)
-#define pUART0_LCR 		((volatile uint16_t *)UART0_LCR)
-#define pUART0_MCR 		((volatile uint16_t *)UART0_MCR)
-#define pUART0_LSR 		((volatile uint16_t *)UART0_LSR)
-#define pUART0_SCR 		((volatile uint16_t *)UART0_SCR)
-#define pUART0_GCTL 	((volatile uint16_t *)UART0_GCTL)
-
-
-/* SPI0 Controller  		(0xFFC00500 - 0xFFC005FF)*/
-#define pSPI0_CTL 		((volatile uint16_t *)SPI0_CTL)
-#define pSPI0_FLG 		((volatile uint16_t *)SPI0_FLG)
-#define pSPI0_STAT 		((volatile uint16_t *)SPI0_STAT)
-#define pSPI0_TDBR 		((volatile uint16_t *)SPI0_TDBR)
-#define pSPI0_RDBR 		((volatile uint16_t *)SPI0_RDBR)
-#define pSPI0_BAUD 		((volatile uint16_t *)SPI0_BAUD)
-#define pSPI0_SHADOW 	((volatile uint16_t *)SPI0_SHADOW)
-
-
-/* SPI1 Controller 		(0xFFC01300 - 0xFFC013FF)*/
-#define pSPI1_CTL 		((volatile uint16_t *)SPI1_CTL)
-#define pSPI1_FLG 		((volatile uint16_t *)SPI1_FLG)
-#define pSPI1_STAT 		((volatile uint16_t *)SPI1_STAT)
-#define pSPI1_TDBR 		((volatile uint16_t *)SPI1_TDBR)
-#define pSPI1_RDBR 		((volatile uint16_t *)SPI1_RDBR)
-#define pSPI1_BAUD 		((volatile uint16_t *)SPI1_BAUD)
-#define pSPI1_SHADOW 	((volatile uint16_t *)SPI1_SHADOW)
-
-
-/* TIMER0-2 Registers 		(0xFFC00600 - 0xFFC006FF) */
-#define pTIMER0_CONFIG 		((volatile uint16_t *)TIMER0_CONFIG)
-#define pTIMER0_COUNTER 	((volatile uint32_t *)TIMER0_COUNTER)
-#define pTIMER0_PERIOD 		((volatile uint32_t *)TIMER0_PERIOD)
-#define pTIMER0_WIDTH 		((volatile uint32_t *)TIMER0_WIDTH)
-
-#define pTIMER1_CONFIG 		((volatile uint16_t *)TIMER1_CONFIG)
-#define pTIMER1_COUNTER 	((volatile uint32_t *)TIMER1_COUNTER)
-#define pTIMER1_PERIOD 		((volatile uint32_t *)TIMER1_PERIOD)
-#define pTIMER1_WIDTH 		((volatile uint32_t *)TIMER1_WIDTH)
-
-#define pTIMER2_CONFIG 		((volatile uint16_t *)TIMER2_CONFIG)
-#define pTIMER2_COUNTER 	((volatile uint32_t *)TIMER2_COUNTER)
-#define pTIMER2_PERIOD 		((volatile uint32_t *)TIMER2_PERIOD)
-#define pTIMER2_WIDTH 		((volatile uint32_t *)TIMER2_WIDTH)
-
-#define pTIMER_ENABLE 		((volatile uint16_t *)TIMER_ENABLE)
-#define pTIMER_DISABLE 		((volatile uint16_t *)TIMER_DISABLE)
-#define pTIMER_STATUS		((volatile uint16_t *)TIMER_STATUS)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
-#define pPORTFIO 			((volatile uint16_t *)PORTFIO)
-#define pPORTFIO_CLEAR	 	((volatile uint16_t *)PORTFIO_CLEAR)
-#define pPORTFIO_SET	 	((volatile uint16_t *)PORTFIO_SET)
-#define pPORTFIO_TOGGLE 	((volatile uint16_t *)PORTFIO_TOGGLE)
-#define pPORTFIO_MASKA 		((volatile uint16_t *)PORTFIO_MASKA)
-#define pPORTFIO_MASKA_CLEAR 	((volatile uint16_t *)PORTFIO_MASKA_CLEAR)
-#define pPORTFIO_MASKA_SET 	((volatile uint16_t *)PORTFIO_MASKA_SET)
-#define pPORTFIO_MASKA_TOGGLE ((volatile uint16_t *)PORTFIO_MASKA_TOGGLE)
-#define pPORTFIO_MASKB	 	((volatile uint16_t *)PORTFIO_MASKB)
-#define pPORTFIO_MASKB_CLEAR 	((volatile uint16_t *)PORTFIO_MASKB_CLEAR)
-#define pPORTFIO_MASKB_SET 	((volatile uint16_t *)PORTFIO_MASKB_SET)
-#define pPORTFIO_MASKB_TOGGLE ((volatile uint16_t *)PORTFIO_MASKB_TOGGLE)
-#define pPORTFIO_DIR 		((volatile uint16_t *)PORTFIO_DIR)
-#define pPORTFIO_POLAR 		((volatile uint16_t *)PORTFIO_POLAR)
-#define pPORTFIO_EDGE 		((volatile uint16_t *)PORTFIO_EDGE)
-#define pPORTFIO_BOTH 		((volatile uint16_t *)PORTFIO_BOTH)
-#define pPORTFIO_INEN 		((volatile uint16_t *)PORTFIO_INEN)
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
-#define pPORTGIO	 		((volatile uint16_t *)PORTGIO)
-#define pPORTGIO_CLEAR	 	((volatile uint16_t *)PORTGIO_CLEAR)
-#define pPORTGIO_SET	 	((volatile uint16_t *)PORTGIO_SET)
-#define pPORTGIO_TOGGLE 	((volatile uint16_t *)PORTGIO_TOGGLE)
-#define pPORTGIO_MASKA		((volatile uint16_t *)PORTGIO_MASKA)
-#define pPORTGIO_MASKA_CLEAR	((volatile uint16_t *)PORTGIO_MASKA_CLEAR)
-#define pPORTGIO_MASKA_SET	((volatile uint16_t *)PORTGIO_MASKA_SET)
-#define pPORTGIO_MASKA_TOGGLE	((volatile uint16_t *)PORTGIO_MASKA_TOGGLE)
-#define pPORTGIO_MASKB		((volatile uint16_t *)PORTGIO_MASKB)
-#define pPORTGIO_MASKB_CLEAR	((volatile uint16_t *)PORTGIO_MASKB_CLEAR)
-#define pPORTGIO_MASKB_SET	((volatile uint16_t *)PORTGIO_MASKB_SET)
-#define pPORTGIO_MASKB_TOGGLE	((volatile uint16_t *)PORTGIO_MASKB_TOGGLE)
-#define pPORTGIO_DIR 		((volatile uint16_t *)PORTGIO_DIR)
-#define pPORTGIO_POLAR 		((volatile uint16_t *)PORTGIO_POLAR)
-#define pPORTGIO_EDGE 		((volatile uint16_t *)PORTGIO_EDGE)
-#define pPORTGIO_BOTH 		((volatile uint16_t *)PORTGIO_BOTH)
-#define pPORTGIO_INEN 		((volatile uint16_t *)PORTGIO_INEN)
-
-
-/* Pin Control Registers 	(0xFFC01100 - 0xFFC012FF) */
-#define pPORTF_FER			((volatile uint16_t *)PORTF_FER)
-#define pPORTF_MUX 			((volatile uint16_t *)PORTF_MUX)
-#define pPORTF_PADCTL 		((volatile uint16_t *)PORTF_PADCTL)
-#define pPORTG_FER			((volatile uint16_t *)PORTG_FER)
-#define pPORTG_MUX 			((volatile uint16_t *)PORTG_MUX)
-#define pPORTG_PADCTL 		((volatile uint16_t *)PORTG_PADCTL)
-
-/* SPORT Clock Gating			(0xFFC0120C) */
-#define pSPORT_GATECLK 		((volatile uint16_t *)SPORT_GATECLK)
-
-/* SPORT0 Controller 		(0xFFC00800 - 0xFFC008FF) */
-#define pSPORT0_TCR1 		((volatile uint16_t *)SPORT0_TCR1)
-#define pSPORT0_TCR2 		((volatile uint16_t *)SPORT0_TCR2)
-#define pSPORT0_TCLKDIV 	((volatile uint16_t *)SPORT0_TCLKDIV)
-#define pSPORT0_TFSDIV 		((volatile uint16_t *)SPORT0_TFSDIV)
-#define pSPORT0_TX 			((volatile uint32_t *)SPORT0_TX)
-#define pSPORT0_RX 			((volatile uint32_t *)SPORT0_RX)
-#define pSPORT0_TX32 		((volatile uint32_t *)SPORT0_TX)
-#define pSPORT0_RX32 		((volatile uint32_t *)SPORT0_RX)
-#define pSPORT0_TX16 		((volatile uint16_t *)SPORT0_TX)
-#define pSPORT0_RX16 		((volatile uint16_t *)SPORT0_RX)
-#define pSPORT0_RCR1 		((volatile uint16_t *)SPORT0_RCR1)
-#define pSPORT0_RCR2 		((volatile uint16_t *)SPORT0_RCR2)
-#define pSPORT0_RCLKDIV 	((volatile uint16_t *)SPORT0_RCLKDIV)
-#define pSPORT0_RFSDIV 		((volatile uint16_t *)SPORT0_RFSDIV)
-#define pSPORT0_STAT 		((volatile uint16_t *)SPORT0_STAT)
-#define pSPORT0_CHNL 		((volatile uint16_t *)SPORT0_CHNL)
-#define pSPORT0_MCMC1 		((volatile uint16_t *)SPORT0_MCMC1)
-#define pSPORT0_MCMC2 		((volatile uint16_t *)SPORT0_MCMC2)
-#define pSPORT0_MTCS0 		((volatile uint32_t *)SPORT0_MTCS0)
-#define pSPORT0_MTCS1 		((volatile uint32_t *)SPORT0_MTCS1)
-#define pSPORT0_MTCS2 		((volatile uint32_t *)SPORT0_MTCS2)
-#define pSPORT0_MTCS3 		((volatile uint32_t *)SPORT0_MTCS3)
-#define pSPORT0_MRCS0 		((volatile uint32_t *)SPORT0_MRCS0)
-#define pSPORT0_MRCS1 		((volatile uint32_t *)SPORT0_MRCS1)
-#define pSPORT0_MRCS2 		((volatile uint32_t *)SPORT0_MRCS2)
-#define pSPORT0_MRCS3 		((volatile uint32_t *)SPORT0_MRCS3)
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF) */
-#define pSPORT1_TCR1 		((volatile uint16_t *)SPORT1_TCR1)
-#define pSPORT1_TCR2 		((volatile uint16_t *)SPORT1_TCR2)
-#define pSPORT1_TCLKDIV 	((volatile uint16_t *)SPORT1_TCLKDIV)
-#define pSPORT1_TFSDIV 		((volatile uint16_t *)SPORT1_TFSDIV)
-#define pSPORT1_TX 		((volatile uint32_t *)SPORT1_TX)
-#define pSPORT1_RX 		((volatile uint32_t *)SPORT1_RX)
-#define pSPORT1_TX32 		((volatile uint32_t *)SPORT1_TX)
-#define pSPORT1_RX32 		((volatile uint32_t *)SPORT1_RX)
-#define pSPORT1_TX16 		((volatile uint16_t *)SPORT1_TX)
-#define pSPORT1_RX16 		((volatile uint16_t *)SPORT1_RX)
-#define pSPORT1_RCR1 		((volatile uint16_t *)SPORT1_RCR1)
-#define pSPORT1_RCR2 		((volatile uint16_t *)SPORT1_RCR2)
-#define pSPORT1_RCLKDIV 	((volatile uint16_t *)SPORT1_RCLKDIV)
-#define pSPORT1_RFSDIV 		((volatile uint16_t *)SPORT1_RFSDIV)
-#define pSPORT1_STAT 		((volatile uint16_t *)SPORT1_STAT)
-#define pSPORT1_CHNL 		((volatile uint16_t *)SPORT1_CHNL)
-#define pSPORT1_MCMC1 		((volatile uint16_t *)SPORT1_MCMC1)
-#define pSPORT1_MCMC2 		((volatile uint16_t *)SPORT1_MCMC2)
-#define pSPORT1_MTCS0 		((volatile uint32_t *)SPORT1_MTCS0)
-#define pSPORT1_MTCS1 		((volatile uint32_t *)SPORT1_MTCS1)
-#define pSPORT1_MTCS2 		((volatile uint32_t *)SPORT1_MTCS2)
-#define pSPORT1_MTCS3 		((volatile uint32_t *)SPORT1_MTCS3)
-#define pSPORT1_MRCS0 		((volatile uint32_t *)SPORT1_MRCS0)
-#define pSPORT1_MRCS1 		((volatile uint32_t *)SPORT1_MRCS1)
-#define pSPORT1_MRCS2 		((volatile uint32_t *)SPORT1_MRCS2)
-#define pSPORT1_MRCS3 		((volatile uint32_t *)SPORT1_MRCS3)
-
-
-/* DMA Traffic Control Registers	(0xFFC00B00 - 0xFFC00BFF) */
-#define	pDMA_TC_PER		((volatile uint16_t *)DMA_TC_PER)
-#define	pDMA_TC_CNT		((volatile uint16_t *)DMA_TC_CNT)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define	pDMA_TCPER		((volatile uint16_t *)DMA_TCPER)
-#define	pDMA_TCCNT		((volatile uint16_t *)DMA_TCCNT)
-
-/* DMA Controller			(0xFFC00C00 - FFC00FFF)*/
-#define pDMA0_CONFIG 		((volatile uint16_t *)DMA0_CONFIG)
-#define pDMA0_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
-#define pDMA0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
-#define pDMA0_X_COUNT 		((volatile uint16_t *)DMA0_X_COUNT)
-#define pDMA0_Y_COUNT 		((volatile uint16_t *)DMA0_Y_COUNT)
-#define pDMA0_X_MODIFY 		((volatile signed   short *)DMA0_X_MODIFY)
-#define pDMA0_Y_MODIFY 		((volatile signed   short *)DMA0_Y_MODIFY)
-#define pDMA0_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
-#define pDMA0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
-#define pDMA0_CURR_X_COUNT 	((volatile uint16_t *)DMA0_CURR_X_COUNT)
-#define pDMA0_CURR_Y_COUNT 	((volatile uint16_t *)DMA0_CURR_Y_COUNT)
-#define pDMA0_IRQ_STATUS 	((volatile uint16_t *)DMA0_IRQ_STATUS)
-#define pDMA0_PERIPHERAL_MAP 	((volatile uint16_t *)DMA0_PERIPHERAL_MAP)
-
-#define pDMA1_CONFIG 		((volatile uint16_t *)DMA1_CONFIG)
-#define pDMA1_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
-#define pDMA1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
-#define pDMA1_X_COUNT 		((volatile uint16_t *)DMA1_X_COUNT)
-#define pDMA1_Y_COUNT 		((volatile uint16_t *)DMA1_Y_COUNT)
-#define pDMA1_X_MODIFY 		((volatile signed   short *)DMA1_X_MODIFY)
-#define pDMA1_Y_MODIFY 		((volatile signed   short *)DMA1_Y_MODIFY)
-#define pDMA1_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
-#define pDMA1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
-#define pDMA1_CURR_X_COUNT 	((volatile uint16_t *)DMA1_CURR_X_COUNT)
-#define pDMA1_CURR_Y_COUNT 	((volatile uint16_t *)DMA1_CURR_Y_COUNT)
-#define pDMA1_IRQ_STATUS 	((volatile uint16_t *)DMA1_IRQ_STATUS)
-#define pDMA1_PERIPHERAL_MAP 	((volatile uint16_t *)DMA1_PERIPHERAL_MAP)
-
-#define pDMA2_CONFIG 		((volatile uint16_t *)DMA2_CONFIG)
-#define pDMA2_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
-#define pDMA2_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
-#define pDMA2_X_COUNT 		((volatile uint16_t *)DMA2_X_COUNT)
-#define pDMA2_Y_COUNT 		((volatile uint16_t *)DMA2_Y_COUNT)
-#define pDMA2_X_MODIFY 		((volatile signed   short *)DMA2_X_MODIFY)
-#define pDMA2_Y_MODIFY 		((volatile signed   short *)DMA2_Y_MODIFY)
-#define pDMA2_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
-#define pDMA2_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
-#define pDMA2_CURR_X_COUNT 	((volatile uint16_t *)DMA2_CURR_X_COUNT)
-#define pDMA2_CURR_Y_COUNT 	((volatile uint16_t *)DMA2_CURR_Y_COUNT)
-#define pDMA2_IRQ_STATUS 	((volatile uint16_t *)DMA2_IRQ_STATUS)
-#define pDMA2_PERIPHERAL_MAP 	((volatile uint16_t *)DMA2_PERIPHERAL_MAP)
-
-#define pDMA3_CONFIG 		((volatile uint16_t *)DMA3_CONFIG)
-#define pDMA3_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
-#define pDMA3_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
-#define pDMA3_X_COUNT 		((volatile uint16_t *)DMA3_X_COUNT)
-#define pDMA3_Y_COUNT 		((volatile uint16_t *)DMA3_Y_COUNT)
-#define pDMA3_X_MODIFY 		((volatile signed   short *)DMA3_X_MODIFY)
-#define pDMA3_Y_MODIFY 		((volatile signed   short *)DMA3_Y_MODIFY)
-#define pDMA3_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
-#define pDMA3_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
-#define pDMA3_CURR_X_COUNT 	((volatile uint16_t *)DMA3_CURR_X_COUNT)
-#define pDMA3_CURR_Y_COUNT 	((volatile uint16_t *)DMA3_CURR_Y_COUNT)
-#define pDMA3_IRQ_STATUS 	((volatile uint16_t *)DMA3_IRQ_STATUS)
-#define pDMA3_PERIPHERAL_MAP 	((volatile uint16_t *)DMA3_PERIPHERAL_MAP)
-
-#define pDMA4_CONFIG 		((volatile uint16_t *)DMA4_CONFIG)
-#define pDMA4_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
-#define pDMA4_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
-#define pDMA4_X_COUNT 		((volatile uint16_t *)DMA4_X_COUNT)
-#define pDMA4_Y_COUNT 		((volatile uint16_t *)DMA4_Y_COUNT)
-#define pDMA4_X_MODIFY 		((volatile signed   short *)DMA4_X_MODIFY)
-#define pDMA4_Y_MODIFY 		((volatile signed   short *)DMA4_Y_MODIFY)
-#define pDMA4_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
-#define pDMA4_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
-#define pDMA4_CURR_X_COUNT 	((volatile uint16_t *)DMA4_CURR_X_COUNT)
-#define pDMA4_CURR_Y_COUNT 	((volatile uint16_t *)DMA4_CURR_Y_COUNT)
-#define pDMA4_IRQ_STATUS 	((volatile uint16_t *)DMA4_IRQ_STATUS)
-#define pDMA4_PERIPHERAL_MAP 	((volatile uint16_t *)DMA4_PERIPHERAL_MAP)
-
-#define pDMA5_CONFIG 		((volatile uint16_t *)DMA5_CONFIG)
-#define pDMA5_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
-#define pDMA5_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
-#define pDMA5_X_COUNT 		((volatile uint16_t *)DMA5_X_COUNT)
-#define pDMA5_Y_COUNT 		((volatile uint16_t *)DMA5_Y_COUNT)
-#define pDMA5_X_MODIFY 		((volatile signed   short *)DMA5_X_MODIFY)
-#define pDMA5_Y_MODIFY 		((volatile signed   short *)DMA5_Y_MODIFY)
-#define pDMA5_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
-#define pDMA5_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
-#define pDMA5_CURR_X_COUNT 	((volatile uint16_t *)DMA5_CURR_X_COUNT)
-#define pDMA5_CURR_Y_COUNT 	((volatile uint16_t *)DMA5_CURR_Y_COUNT)
-#define pDMA5_IRQ_STATUS 	((volatile uint16_t *)DMA5_IRQ_STATUS)
-#define pDMA5_PERIPHERAL_MAP 	((volatile uint16_t *)DMA5_PERIPHERAL_MAP)
-
-#define pDMA6_CONFIG 		((volatile uint16_t *)DMA6_CONFIG)
-#define pDMA6_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
-#define pDMA6_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
-#define pDMA6_X_COUNT 		((volatile uint16_t *)DMA6_X_COUNT)
-#define pDMA6_Y_COUNT 		((volatile uint16_t *)DMA6_Y_COUNT)
-#define pDMA6_X_MODIFY 		((volatile signed   short *)DMA6_X_MODIFY)
-#define pDMA6_Y_MODIFY 		((volatile signed   short *)DMA6_Y_MODIFY)
-#define pDMA6_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
-#define pDMA6_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
-#define pDMA6_CURR_X_COUNT 	((volatile uint16_t *)DMA6_CURR_X_COUNT)
-#define pDMA6_CURR_Y_COUNT 	((volatile uint16_t *)DMA6_CURR_Y_COUNT)
-#define pDMA6_IRQ_STATUS 	((volatile uint16_t *)DMA6_IRQ_STATUS)
-#define pDMA6_PERIPHERAL_MAP 	((volatile uint16_t *)DMA6_PERIPHERAL_MAP)
-
-#define pDMA7_CONFIG 		((volatile uint16_t *)DMA7_CONFIG)
-#define pDMA7_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
-#define pDMA7_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
-#define pDMA7_X_COUNT 		((volatile uint16_t *)DMA7_X_COUNT)
-#define pDMA7_Y_COUNT 		((volatile uint16_t *)DMA7_Y_COUNT)
-#define pDMA7_X_MODIFY 		((volatile signed   short *)DMA7_X_MODIFY)
-#define pDMA7_Y_MODIFY 		((volatile signed   short *)DMA7_Y_MODIFY)
-#define pDMA7_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
-#define pDMA7_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
-#define pDMA7_CURR_X_COUNT 	((volatile uint16_t *)DMA7_CURR_X_COUNT)
-#define pDMA7_CURR_Y_COUNT 	((volatile uint16_t *)DMA7_CURR_Y_COUNT)
-#define pDMA7_IRQ_STATUS 	((volatile uint16_t *)DMA7_IRQ_STATUS)
-#define pDMA7_PERIPHERAL_MAP 	((volatile uint16_t *)DMA7_PERIPHERAL_MAP)
-
-#define pDMA8_CONFIG 		((volatile uint16_t *)DMA8_CONFIG)
-#define pDMA8_NEXT_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
-#define pDMA8_START_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
-#define pDMA8_X_COUNT 		((volatile uint16_t *)DMA8_X_COUNT)
-#define pDMA8_Y_COUNT 		((volatile uint16_t *)DMA8_Y_COUNT)
-#define pDMA8_X_MODIFY 		((volatile signed   short *)DMA8_X_MODIFY)
-#define pDMA8_Y_MODIFY 		((volatile signed   short *)DMA8_Y_MODIFY)
-#define pDMA8_CURR_DESC_PTR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
-#define pDMA8_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
-#define pDMA8_CURR_X_COUNT 	((volatile uint16_t *)DMA8_CURR_X_COUNT)
-#define pDMA8_CURR_Y_COUNT 	((volatile uint16_t *)DMA8_CURR_Y_COUNT)
-#define pDMA8_IRQ_STATUS 	((volatile uint16_t *)DMA8_IRQ_STATUS)
-#define pDMA8_PERIPHERAL_MAP 	((volatile uint16_t *)DMA8_PERIPHERAL_MAP)
-
-#define pMDMA_D0_CONFIG 	((volatile uint16_t *)MDMA_D0_CONFIG)
-#define pMDMA_D0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
-#define pMDMA_D0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
-#define pMDMA_D0_X_COUNT 	((volatile uint16_t *)MDMA_D0_X_COUNT)
-#define pMDMA_D0_Y_COUNT 	((volatile uint16_t *)MDMA_D0_Y_COUNT)
-#define pMDMA_D0_X_MODIFY 	((volatile signed   short *)MDMA_D0_X_MODIFY)
-#define pMDMA_D0_Y_MODIFY 	((volatile signed   short *)MDMA_D0_Y_MODIFY)
-#define pMDMA_D0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
-#define pMDMA_D0_CURR_ADDR 	  (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
-#define pMDMA_D0_CURR_X_COUNT ((volatile uint16_t *)MDMA_D0_CURR_X_COUNT)
-#define pMDMA_D0_CURR_Y_COUNT ((volatile uint16_t *)MDMA_D0_CURR_Y_COUNT)
-#define pMDMA_D0_IRQ_STATUS 	((volatile uint16_t *)MDMA_D0_IRQ_STATUS)
-#define pMDMA_D0_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_D0_PERIPHERAL_MAP)
-
-#define pMDMA_S0_CONFIG 	((volatile uint16_t *)MDMA_S0_CONFIG)
-#define pMDMA_S0_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
-#define pMDMA_S0_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
-#define pMDMA_S0_X_COUNT 	((volatile uint16_t *)MDMA_S0_X_COUNT)
-#define pMDMA_S0_Y_COUNT 	((volatile uint16_t *)MDMA_S0_Y_COUNT)
-#define pMDMA_S0_X_MODIFY 	((volatile signed   short *)MDMA_S0_X_MODIFY)
-#define pMDMA_S0_Y_MODIFY 	((volatile signed   short *)MDMA_S0_Y_MODIFY)
-#define pMDMA_S0_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
-#define pMDMA_S0_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
-#define pMDMA_S0_CURR_X_COUNT ((volatile uint16_t *)MDMA_S0_CURR_X_COUNT)
-#define pMDMA_S0_CURR_Y_COUNT ((volatile uint16_t *)MDMA_S0_CURR_Y_COUNT)
-#define pMDMA_S0_IRQ_STATUS 	((volatile uint16_t *)MDMA_S0_IRQ_STATUS)
-#define pMDMA_S0_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_S0_PERIPHERAL_MAP)
-
-#define pMDMA_D1_CONFIG 	((volatile uint16_t *)MDMA_D1_CONFIG)
-#define pMDMA_D1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
-#define pMDMA_D1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
-#define pMDMA_D1_X_COUNT 	((volatile uint16_t *)MDMA_D1_X_COUNT)
-#define pMDMA_D1_Y_COUNT 	((volatile uint16_t *)MDMA_D1_Y_COUNT)
-#define pMDMA_D1_X_MODIFY 	((volatile signed   short *)MDMA_D1_X_MODIFY)
-#define pMDMA_D1_Y_MODIFY 	((volatile signed   short *)MDMA_D1_Y_MODIFY)
-#define pMDMA_D1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
-#define pMDMA_D1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
-#define pMDMA_D1_CURR_X_COUNT ((volatile uint16_t *)MDMA_D1_CURR_X_COUNT)
-#define pMDMA_D1_CURR_Y_COUNT ((volatile uint16_t *)MDMA_D1_CURR_Y_COUNT)
-#define pMDMA_D1_IRQ_STATUS 	((volatile uint16_t *)MDMA_D1_IRQ_STATUS)
-#define pMDMA_D1_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_D1_PERIPHERAL_MAP)
-
-#define pMDMA_S1_CONFIG 	((volatile uint16_t *)MDMA_S1_CONFIG)
-#define pMDMA_S1_NEXT_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
-#define pMDMA_S1_START_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
-#define pMDMA_S1_X_COUNT 	((volatile uint16_t *)MDMA_S1_X_COUNT)
-#define pMDMA_S1_Y_COUNT 	((volatile uint16_t *)MDMA_S1_Y_COUNT)
-#define pMDMA_S1_X_MODIFY 	((volatile signed   short *)MDMA_S1_X_MODIFY)
-#define pMDMA_S1_Y_MODIFY 	((volatile signed   short *)MDMA_S1_Y_MODIFY)
-#define pMDMA_S1_CURR_DESC_PTR  (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
-#define pMDMA_S1_CURR_ADDR 	(_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
-#define pMDMA_S1_CURR_X_COUNT ((volatile uint16_t *)MDMA_S1_CURR_X_COUNT)
-#define pMDMA_S1_CURR_Y_COUNT ((volatile uint16_t *)MDMA_S1_CURR_Y_COUNT)
-#define pMDMA_S1_IRQ_STATUS 	((volatile uint16_t *)MDMA_S1_IRQ_STATUS)
-#define pMDMA_S1_PERIPHERAL_MAP ((volatile uint16_t *)MDMA_S1_PERIPHERAL_MAP)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
-#define pPPI_CONTROL 		((volatile uint16_t *)PPI_CONTROL)
-#define pPPI_STATUS 		((volatile uint16_t *)PPI_STATUS)
-#define pPPI_DELAY 		((volatile uint16_t *)PPI_DELAY)
-#define pPPI_COUNT 		((volatile uint16_t *)PPI_COUNT)
-#define pPPI_FRAME 		((volatile uint16_t *)PPI_FRAME)
-
-
-/* Two-Wire Interface 		(0xFFC01400 - 0xFFC014FF) */
-#define pTWI_CLKDIV		((volatile uint16_t *)TWI_CLKDIV)
-#define pTWI_CONTROL		((volatile uint16_t *)TWI_CONTROL)
-#define pTWI_SLAVE_CTL		((volatile uint16_t *)TWI_SLAVE_CTL)
-#define pTWI_SLAVE_STAT		((volatile uint16_t *)TWI_SLAVE_STAT)
-#define pTWI_SLAVE_ADDR		((volatile uint16_t *)TWI_SLAVE_ADDR)
-#define pTWI_MASTER_CTL		((volatile uint16_t *)TWI_MASTER_CTL)
-#define pTWI_MASTER_STAT	((volatile uint16_t *)TWI_MASTER_STAT)
-#define pTWI_MASTER_ADDR	((volatile uint16_t *)TWI_MASTER_ADDR)
-#define pTWI_INT_STAT		((volatile uint16_t *)TWI_INT_STAT)
-#define pTWI_INT_MASK		((volatile uint16_t *)TWI_INT_MASK)
-#define pTWI_FIFO_CTL		((volatile uint16_t *)TWI_FIFO_CTL)
-#define pTWI_FIFO_STAT		((volatile uint16_t *)TWI_FIFO_STAT)
-#define pTWI_XMT_DATA8		((volatile uint16_t *)TWI_XMT_DATA8)
-#define pTWI_XMT_DATA16		((volatile uint16_t *)TWI_XMT_DATA16)
-#define pTWI_RCV_DATA8		((volatile uint16_t *)TWI_RCV_DATA8)
-#define pTWI_RCV_DATA16		((volatile uint16_t *)TWI_RCV_DATA16)
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-
-#endif  /*_CDEF_BF59x_H*/
diff --git a/libgloss/bfin/include/cdefBF606.h b/libgloss/bfin/include/cdefBF606.h
deleted file mode 100644
index c8c1eee34..000000000
--- a/libgloss/bfin/include/cdefBF606.h
+++ /dev/null
@@ -1,4153 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* =========================================================================
-
-     Project      :   ADSP-BF606
-     File         :   cdefBF606.h
-     Description  :   C register and bitfield definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ========================================================================= */
-#ifndef _CDEF_BF606_H
-#define _CDEF_BF606_H
-
-#include <stdint.h>
-#include <defBF606.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_7:"ADI header will re-use identifiers")
-#pragma diag(suppress:misra_rule_6_3:"ADI header allows use of basic types")
-#endif /* _MISRA_RULES */
-
-
-
-
-/* =========================================================================
-       CNT0
-   ========================================================================= */
-#define pREG_CNT0_CFG                    ((volatile uint16_t *)REG_CNT0_CFG)                     /* CNT0 Configuration Register */
-#define pREG_CNT0_IMSK                   ((volatile uint16_t *)REG_CNT0_IMSK)                    /* CNT0 Interrupt Mask Register */
-#define pREG_CNT0_STAT                   ((volatile uint16_t *)REG_CNT0_STAT)                    /* CNT0 Status Register */
-#define pREG_CNT0_CMD                    ((volatile uint16_t *)REG_CNT0_CMD)                     /* CNT0 Command Register */
-#define pREG_CNT0_DEBNCE                 ((volatile uint16_t *)REG_CNT0_DEBNCE)                  /* CNT0 Debounce Register */
-#define pREG_CNT0_CNTR                   ((volatile uint32_t *)REG_CNT0_CNTR)                    /* CNT0 Counter Register */
-#define pREG_CNT0_MAX                    ((volatile uint32_t *)REG_CNT0_MAX)                     /* CNT0 Maximum Count Register */
-#define pREG_CNT0_MIN                    ((volatile uint32_t *)REG_CNT0_MIN)                     /* CNT0 Minimum Count Register */
-
-
-/* =========================================================================
-       RSI0
-   ========================================================================= */
-#define pREG_RSI0_CTL                    ((volatile uint16_t *)REG_RSI0_CTL)                     /* RSI0 Control Register */
-#define pREG_RSI0_ARG                    ((volatile uint32_t *)REG_RSI0_ARG)                     /* RSI0 Argument Register */
-#define pREG_RSI0_CMD                    ((volatile uint16_t *)REG_RSI0_CMD)                     /* RSI0 Command Register */
-#define pREG_RSI0_RESP_CMD               ((volatile uint16_t *)REG_RSI0_RESP_CMD)                /* RSI0 Response Command Register */
-#define pREG_RSI0_RESP0                  ((volatile uint32_t *)REG_RSI0_RESP0)                   /* RSI0 Response 0 Register */
-#define pREG_RSI0_RESP1                  ((volatile uint32_t *)REG_RSI0_RESP1)                   /* RSI0 Response 1 Register */
-#define pREG_RSI0_RESP2                  ((volatile uint32_t *)REG_RSI0_RESP2)                   /* RSI0 Response 2 Register */
-#define pREG_RSI0_RESP3                  ((volatile uint32_t *)REG_RSI0_RESP3)                   /* RSI0 Response 3 Register */
-#define pREG_RSI0_DATA_TMR               ((volatile uint32_t *)REG_RSI0_DATA_TMR)                /* RSI0 Data Timer Register */
-#define pREG_RSI0_DATA_LEN               ((volatile uint16_t *)REG_RSI0_DATA_LEN)                /* RSI0 Data Length Register */
-#define pREG_RSI0_DATA_CTL               ((volatile uint16_t *)REG_RSI0_DATA_CTL)                /* RSI0 Data Control Register */
-#define pREG_RSI0_DATA_CNT               ((volatile uint16_t *)REG_RSI0_DATA_CNT)                /* RSI0 Data Count Register */
-#define pREG_RSI0_XFRSTAT                ((volatile uint32_t *)REG_RSI0_XFRSTAT)                 /* RSI0 Status Register */
-#define pREG_RSI0_XFRSTAT_CLR            ((volatile uint16_t *)REG_RSI0_XFRSTAT_CLR)             /* RSI0 Status Clear Register */
-#define pREG_RSI0_XFR_IMSK0              ((volatile uint32_t *)REG_RSI0_XFR_IMSK0)               /* RSI0 Interrupt 0 Mask Register */
-#define pREG_RSI0_XFR_IMSK1              ((volatile uint32_t *)REG_RSI0_XFR_IMSK1)               /* RSI0 Interrupt 1 Mask Register */
-#define pREG_RSI0_FIFO_CNT               ((volatile uint16_t *)REG_RSI0_FIFO_CNT)                /* RSI0 FIFO Counter Register */
-#define pREG_RSI0_CEATA                  ((volatile uint32_t *)REG_RSI0_CEATA)                   /* RSI0 This register contains bit to dis CCS gen */
-#define pREG_RSI0_BOOT_TCNTR             ((volatile uint16_t *)REG_RSI0_BOOT_TCNTR)              /* RSI0 Boot Timing Counter Register */
-#define pREG_RSI0_BACK_TOUT              ((volatile uint32_t *)REG_RSI0_BACK_TOUT)               /* RSI0 Boot Acknowledge Timeout Register */
-#define pREG_RSI0_SLP_WKUP_TOUT          ((volatile uint32_t *)REG_RSI0_SLP_WKUP_TOUT)           /* RSI0 Sleep Wakeup Timeout Register */
-#define pREG_RSI0_BLKSZ                  ((volatile uint16_t *)REG_RSI0_BLKSZ)                   /* RSI0 Block Size Register */
-#define pREG_RSI0_FIFO                   ((volatile uint32_t *)REG_RSI0_FIFO)                    /* RSI0 Data FIFO Register */
-#define pREG_RSI0_STAT0                  ((volatile uint32_t *)REG_RSI0_STAT0)                   /* RSI0 Exception Status Register */
-#define pREG_RSI0_IMSK0                  ((volatile uint32_t *)REG_RSI0_IMSK0)                   /* RSI0 Exception Mask Register */
-#define pREG_RSI0_CFG                    ((volatile uint16_t *)REG_RSI0_CFG)                     /* RSI0 Configuration Register */
-#define pREG_RSI0_RD_WAIT                ((volatile uint16_t *)REG_RSI0_RD_WAIT)                 /* RSI0 Read Wait Enable Register */
-#define pREG_RSI0_PID0                   ((volatile uint32_t *)REG_RSI0_PID0)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID1                   ((volatile uint32_t *)REG_RSI0_PID1)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID2                   ((volatile uint32_t *)REG_RSI0_PID2)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID3                   ((volatile uint32_t *)REG_RSI0_PID3)                    /* RSI0 Peripheral Identification Register */
-
-
-/* =========================================================================
-       CAN0
-   ========================================================================= */
-#define pREG_CAN0_MC1                    ((volatile uint16_t *)REG_CAN0_MC1)                     /* CAN0 Mailbox Configuration 1 Register */
-#define pREG_CAN0_MD1                    ((volatile uint16_t *)REG_CAN0_MD1)                     /* CAN0 Mailbox Direction 1 Register */
-#define pREG_CAN0_TRS1                   ((volatile uint16_t *)REG_CAN0_TRS1)                    /* CAN0 Transmission Request Set 1 Register */
-#define pREG_CAN0_TRR1                   ((volatile uint16_t *)REG_CAN0_TRR1)                    /* CAN0 Transmission Request Reset 1 Register */
-#define pREG_CAN0_TA1                    ((volatile uint16_t *)REG_CAN0_TA1)                     /* CAN0 Transmission Acknowledge 1 Register */
-#define pREG_CAN0_AA1                    ((volatile uint16_t *)REG_CAN0_AA1)                     /* CAN0 Abort Acknowledge 1 Register */
-#define pREG_CAN0_RMP1                   ((volatile uint16_t *)REG_CAN0_RMP1)                    /* CAN0 Receive Message Pending 1 Register */
-#define pREG_CAN0_RML1                   ((volatile uint16_t *)REG_CAN0_RML1)                    /* CAN0 Receive Message Lost 1 Register */
-#define pREG_CAN0_MBTIF1                 ((volatile uint16_t *)REG_CAN0_MBTIF1)                  /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define pREG_CAN0_MBRIF1                 ((volatile uint16_t *)REG_CAN0_MBRIF1)                  /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define pREG_CAN0_MBIM1                  ((volatile uint16_t *)REG_CAN0_MBIM1)                   /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define pREG_CAN0_RFH1                   ((volatile uint16_t *)REG_CAN0_RFH1)                    /* CAN0 Remote Frame Handling 1 Register */
-#define pREG_CAN0_OPSS1                  ((volatile uint16_t *)REG_CAN0_OPSS1)                   /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define pREG_CAN0_MC2                    ((volatile uint16_t *)REG_CAN0_MC2)                     /* CAN0 Mailbox Configuration 2 Register */
-#define pREG_CAN0_MD2                    ((volatile uint16_t *)REG_CAN0_MD2)                     /* CAN0 Mailbox Direction 2 Register */
-#define pREG_CAN0_TRS2                   ((volatile uint16_t *)REG_CAN0_TRS2)                    /* CAN0 Transmission Request Set 2 Register */
-#define pREG_CAN0_TRR2                   ((volatile uint16_t *)REG_CAN0_TRR2)                    /* CAN0 Transmission Request Reset 2 Register */
-#define pREG_CAN0_TA2                    ((volatile uint16_t *)REG_CAN0_TA2)                     /* CAN0 Transmission Acknowledge 2 Register */
-#define pREG_CAN0_AA2                    ((volatile uint16_t *)REG_CAN0_AA2)                     /* CAN0 Abort Acknowledge 2 Register */
-#define pREG_CAN0_RMP2                   ((volatile uint16_t *)REG_CAN0_RMP2)                    /* CAN0 Receive Message Pending 2 Register */
-#define pREG_CAN0_RML2                   ((volatile uint16_t *)REG_CAN0_RML2)                    /* CAN0 Receive Message Lost 2 Register */
-#define pREG_CAN0_MBTIF2                 ((volatile uint16_t *)REG_CAN0_MBTIF2)                  /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define pREG_CAN0_MBRIF2                 ((volatile uint16_t *)REG_CAN0_MBRIF2)                  /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define pREG_CAN0_MBIM2                  ((volatile uint16_t *)REG_CAN0_MBIM2)                   /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define pREG_CAN0_RFH2                   ((volatile uint16_t *)REG_CAN0_RFH2)                    /* CAN0 Remote Frame Handling 2 Register */
-#define pREG_CAN0_OPSS2                  ((volatile uint16_t *)REG_CAN0_OPSS2)                   /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define pREG_CAN0_CLK                    ((volatile uint16_t *)REG_CAN0_CLK)                     /* CAN0 Clock Register */
-#define pREG_CAN0_TIMING                 ((volatile uint16_t *)REG_CAN0_TIMING)                  /* CAN0 Timing Register */
-#define pREG_CAN0_DBG                    ((volatile uint16_t *)REG_CAN0_DBG)                     /* CAN0 Debug Register */
-#define pREG_CAN0_STAT                   ((volatile uint16_t *)REG_CAN0_STAT)                    /* CAN0 Status Register */
-#define pREG_CAN0_CEC                    ((volatile uint16_t *)REG_CAN0_CEC)                     /* CAN0 Error Counter Register */
-#define pREG_CAN0_GIS                    ((volatile uint16_t *)REG_CAN0_GIS)                     /* CAN0 Global CAN Interrupt Status Register */
-#define pREG_CAN0_GIM                    ((volatile uint16_t *)REG_CAN0_GIM)                     /* CAN0 Global CAN Interrupt Mask Register */
-#define pREG_CAN0_GIF                    ((volatile uint16_t *)REG_CAN0_GIF)                     /* CAN0 Global CAN Interrupt Flag Register */
-#define pREG_CAN0_CTL                    ((volatile uint16_t *)REG_CAN0_CTL)                     /* CAN0 CAN Master Control Register */
-#define pREG_CAN0_INT                    ((volatile uint16_t *)REG_CAN0_INT)                     /* CAN0 Interrupt Pending Register */
-#define pREG_CAN0_MBTD                   ((volatile uint16_t *)REG_CAN0_MBTD)                    /* CAN0 Temporary Mailbox Disable Register */
-#define pREG_CAN0_EWR                    ((volatile uint16_t *)REG_CAN0_EWR)                     /* CAN0 Error Counter Warning Level Register */
-#define pREG_CAN0_ESR                    ((volatile uint16_t *)REG_CAN0_ESR)                     /* CAN0 Error Status Register */
-#define pREG_CAN0_UCCNT                  ((volatile uint16_t *)REG_CAN0_UCCNT)                   /* CAN0 Universal Counter Register */
-#define pREG_CAN0_UCRC                   ((volatile uint16_t *)REG_CAN0_UCRC)                    /* CAN0 Universal Counter Reload/Capture Register */
-#define pREG_CAN0_UCCNF                  ((volatile uint16_t *)REG_CAN0_UCCNF)                   /* CAN0 Universal Counter Configuration Mode Register */
-#define pREG_CAN0_AM00L                  ((volatile uint16_t *)REG_CAN0_AM00L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM01L                  ((volatile uint16_t *)REG_CAN0_AM01L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM02L                  ((volatile uint16_t *)REG_CAN0_AM02L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM03L                  ((volatile uint16_t *)REG_CAN0_AM03L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM04L                  ((volatile uint16_t *)REG_CAN0_AM04L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM05L                  ((volatile uint16_t *)REG_CAN0_AM05L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM06L                  ((volatile uint16_t *)REG_CAN0_AM06L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM07L                  ((volatile uint16_t *)REG_CAN0_AM07L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM08L                  ((volatile uint16_t *)REG_CAN0_AM08L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM09L                  ((volatile uint16_t *)REG_CAN0_AM09L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM10L                  ((volatile uint16_t *)REG_CAN0_AM10L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM11L                  ((volatile uint16_t *)REG_CAN0_AM11L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM12L                  ((volatile uint16_t *)REG_CAN0_AM12L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM13L                  ((volatile uint16_t *)REG_CAN0_AM13L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM14L                  ((volatile uint16_t *)REG_CAN0_AM14L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM15L                  ((volatile uint16_t *)REG_CAN0_AM15L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM16L                  ((volatile uint16_t *)REG_CAN0_AM16L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM17L                  ((volatile uint16_t *)REG_CAN0_AM17L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM18L                  ((volatile uint16_t *)REG_CAN0_AM18L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM19L                  ((volatile uint16_t *)REG_CAN0_AM19L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM20L                  ((volatile uint16_t *)REG_CAN0_AM20L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM21L                  ((volatile uint16_t *)REG_CAN0_AM21L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM22L                  ((volatile uint16_t *)REG_CAN0_AM22L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM23L                  ((volatile uint16_t *)REG_CAN0_AM23L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM24L                  ((volatile uint16_t *)REG_CAN0_AM24L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM25L                  ((volatile uint16_t *)REG_CAN0_AM25L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM26L                  ((volatile uint16_t *)REG_CAN0_AM26L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM27L                  ((volatile uint16_t *)REG_CAN0_AM27L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM28L                  ((volatile uint16_t *)REG_CAN0_AM28L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM29L                  ((volatile uint16_t *)REG_CAN0_AM29L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM30L                  ((volatile uint16_t *)REG_CAN0_AM30L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM31L                  ((volatile uint16_t *)REG_CAN0_AM31L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM00H                  ((volatile uint16_t *)REG_CAN0_AM00H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM01H                  ((volatile uint16_t *)REG_CAN0_AM01H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM02H                  ((volatile uint16_t *)REG_CAN0_AM02H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM03H                  ((volatile uint16_t *)REG_CAN0_AM03H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM04H                  ((volatile uint16_t *)REG_CAN0_AM04H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM05H                  ((volatile uint16_t *)REG_CAN0_AM05H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM06H                  ((volatile uint16_t *)REG_CAN0_AM06H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM07H                  ((volatile uint16_t *)REG_CAN0_AM07H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM08H                  ((volatile uint16_t *)REG_CAN0_AM08H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM09H                  ((volatile uint16_t *)REG_CAN0_AM09H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM10H                  ((volatile uint16_t *)REG_CAN0_AM10H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM11H                  ((volatile uint16_t *)REG_CAN0_AM11H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM12H                  ((volatile uint16_t *)REG_CAN0_AM12H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM13H                  ((volatile uint16_t *)REG_CAN0_AM13H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM14H                  ((volatile uint16_t *)REG_CAN0_AM14H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM15H                  ((volatile uint16_t *)REG_CAN0_AM15H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM16H                  ((volatile uint16_t *)REG_CAN0_AM16H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM17H                  ((volatile uint16_t *)REG_CAN0_AM17H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM18H                  ((volatile uint16_t *)REG_CAN0_AM18H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM19H                  ((volatile uint16_t *)REG_CAN0_AM19H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM20H                  ((volatile uint16_t *)REG_CAN0_AM20H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM21H                  ((volatile uint16_t *)REG_CAN0_AM21H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM22H                  ((volatile uint16_t *)REG_CAN0_AM22H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM23H                  ((volatile uint16_t *)REG_CAN0_AM23H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM24H                  ((volatile uint16_t *)REG_CAN0_AM24H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM25H                  ((volatile uint16_t *)REG_CAN0_AM25H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM26H                  ((volatile uint16_t *)REG_CAN0_AM26H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM27H                  ((volatile uint16_t *)REG_CAN0_AM27H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM28H                  ((volatile uint16_t *)REG_CAN0_AM28H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM29H                  ((volatile uint16_t *)REG_CAN0_AM29H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM30H                  ((volatile uint16_t *)REG_CAN0_AM30H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM31H                  ((volatile uint16_t *)REG_CAN0_AM31H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_MB00_DATA0             ((volatile uint16_t *)REG_CAN0_MB00_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB01_DATA0             ((volatile uint16_t *)REG_CAN0_MB01_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB02_DATA0             ((volatile uint16_t *)REG_CAN0_MB02_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB03_DATA0             ((volatile uint16_t *)REG_CAN0_MB03_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB04_DATA0             ((volatile uint16_t *)REG_CAN0_MB04_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB05_DATA0             ((volatile uint16_t *)REG_CAN0_MB05_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB06_DATA0             ((volatile uint16_t *)REG_CAN0_MB06_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB07_DATA0             ((volatile uint16_t *)REG_CAN0_MB07_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB08_DATA0             ((volatile uint16_t *)REG_CAN0_MB08_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB09_DATA0             ((volatile uint16_t *)REG_CAN0_MB09_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB10_DATA0             ((volatile uint16_t *)REG_CAN0_MB10_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB11_DATA0             ((volatile uint16_t *)REG_CAN0_MB11_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB12_DATA0             ((volatile uint16_t *)REG_CAN0_MB12_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB13_DATA0             ((volatile uint16_t *)REG_CAN0_MB13_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB14_DATA0             ((volatile uint16_t *)REG_CAN0_MB14_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB15_DATA0             ((volatile uint16_t *)REG_CAN0_MB15_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB16_DATA0             ((volatile uint16_t *)REG_CAN0_MB16_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB17_DATA0             ((volatile uint16_t *)REG_CAN0_MB17_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB18_DATA0             ((volatile uint16_t *)REG_CAN0_MB18_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB19_DATA0             ((volatile uint16_t *)REG_CAN0_MB19_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB20_DATA0             ((volatile uint16_t *)REG_CAN0_MB20_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB21_DATA0             ((volatile uint16_t *)REG_CAN0_MB21_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB22_DATA0             ((volatile uint16_t *)REG_CAN0_MB22_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB23_DATA0             ((volatile uint16_t *)REG_CAN0_MB23_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB24_DATA0             ((volatile uint16_t *)REG_CAN0_MB24_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB25_DATA0             ((volatile uint16_t *)REG_CAN0_MB25_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB26_DATA0             ((volatile uint16_t *)REG_CAN0_MB26_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB27_DATA0             ((volatile uint16_t *)REG_CAN0_MB27_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB28_DATA0             ((volatile uint16_t *)REG_CAN0_MB28_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB29_DATA0             ((volatile uint16_t *)REG_CAN0_MB29_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB30_DATA0             ((volatile uint16_t *)REG_CAN0_MB30_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB31_DATA0             ((volatile uint16_t *)REG_CAN0_MB31_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB00_DATA1             ((volatile uint16_t *)REG_CAN0_MB00_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB01_DATA1             ((volatile uint16_t *)REG_CAN0_MB01_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB02_DATA1             ((volatile uint16_t *)REG_CAN0_MB02_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB03_DATA1             ((volatile uint16_t *)REG_CAN0_MB03_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB04_DATA1             ((volatile uint16_t *)REG_CAN0_MB04_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB05_DATA1             ((volatile uint16_t *)REG_CAN0_MB05_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB06_DATA1             ((volatile uint16_t *)REG_CAN0_MB06_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB07_DATA1             ((volatile uint16_t *)REG_CAN0_MB07_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB08_DATA1             ((volatile uint16_t *)REG_CAN0_MB08_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB09_DATA1             ((volatile uint16_t *)REG_CAN0_MB09_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB10_DATA1             ((volatile uint16_t *)REG_CAN0_MB10_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB11_DATA1             ((volatile uint16_t *)REG_CAN0_MB11_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB12_DATA1             ((volatile uint16_t *)REG_CAN0_MB12_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB13_DATA1             ((volatile uint16_t *)REG_CAN0_MB13_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB14_DATA1             ((volatile uint16_t *)REG_CAN0_MB14_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB15_DATA1             ((volatile uint16_t *)REG_CAN0_MB15_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB16_DATA1             ((volatile uint16_t *)REG_CAN0_MB16_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB17_DATA1             ((volatile uint16_t *)REG_CAN0_MB17_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB18_DATA1             ((volatile uint16_t *)REG_CAN0_MB18_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB19_DATA1             ((volatile uint16_t *)REG_CAN0_MB19_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB20_DATA1             ((volatile uint16_t *)REG_CAN0_MB20_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB21_DATA1             ((volatile uint16_t *)REG_CAN0_MB21_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB22_DATA1             ((volatile uint16_t *)REG_CAN0_MB22_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB23_DATA1             ((volatile uint16_t *)REG_CAN0_MB23_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB24_DATA1             ((volatile uint16_t *)REG_CAN0_MB24_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB25_DATA1             ((volatile uint16_t *)REG_CAN0_MB25_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB26_DATA1             ((volatile uint16_t *)REG_CAN0_MB26_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB27_DATA1             ((volatile uint16_t *)REG_CAN0_MB27_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB28_DATA1             ((volatile uint16_t *)REG_CAN0_MB28_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB29_DATA1             ((volatile uint16_t *)REG_CAN0_MB29_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB30_DATA1             ((volatile uint16_t *)REG_CAN0_MB30_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB31_DATA1             ((volatile uint16_t *)REG_CAN0_MB31_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB00_DATA2             ((volatile uint16_t *)REG_CAN0_MB00_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB01_DATA2             ((volatile uint16_t *)REG_CAN0_MB01_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB02_DATA2             ((volatile uint16_t *)REG_CAN0_MB02_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB03_DATA2             ((volatile uint16_t *)REG_CAN0_MB03_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB04_DATA2             ((volatile uint16_t *)REG_CAN0_MB04_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB05_DATA2             ((volatile uint16_t *)REG_CAN0_MB05_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB06_DATA2             ((volatile uint16_t *)REG_CAN0_MB06_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB07_DATA2             ((volatile uint16_t *)REG_CAN0_MB07_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB08_DATA2             ((volatile uint16_t *)REG_CAN0_MB08_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB09_DATA2             ((volatile uint16_t *)REG_CAN0_MB09_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB10_DATA2             ((volatile uint16_t *)REG_CAN0_MB10_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB11_DATA2             ((volatile uint16_t *)REG_CAN0_MB11_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB12_DATA2             ((volatile uint16_t *)REG_CAN0_MB12_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB13_DATA2             ((volatile uint16_t *)REG_CAN0_MB13_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB14_DATA2             ((volatile uint16_t *)REG_CAN0_MB14_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB15_DATA2             ((volatile uint16_t *)REG_CAN0_MB15_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB16_DATA2             ((volatile uint16_t *)REG_CAN0_MB16_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB17_DATA2             ((volatile uint16_t *)REG_CAN0_MB17_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB18_DATA2             ((volatile uint16_t *)REG_CAN0_MB18_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB19_DATA2             ((volatile uint16_t *)REG_CAN0_MB19_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB20_DATA2             ((volatile uint16_t *)REG_CAN0_MB20_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB21_DATA2             ((volatile uint16_t *)REG_CAN0_MB21_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB22_DATA2             ((volatile uint16_t *)REG_CAN0_MB22_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB23_DATA2             ((volatile uint16_t *)REG_CAN0_MB23_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB24_DATA2             ((volatile uint16_t *)REG_CAN0_MB24_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB25_DATA2             ((volatile uint16_t *)REG_CAN0_MB25_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB26_DATA2             ((volatile uint16_t *)REG_CAN0_MB26_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB27_DATA2             ((volatile uint16_t *)REG_CAN0_MB27_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB28_DATA2             ((volatile uint16_t *)REG_CAN0_MB28_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB29_DATA2             ((volatile uint16_t *)REG_CAN0_MB29_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB30_DATA2             ((volatile uint16_t *)REG_CAN0_MB30_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB31_DATA2             ((volatile uint16_t *)REG_CAN0_MB31_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB00_DATA3             ((volatile uint16_t *)REG_CAN0_MB00_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB01_DATA3             ((volatile uint16_t *)REG_CAN0_MB01_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB02_DATA3             ((volatile uint16_t *)REG_CAN0_MB02_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB03_DATA3             ((volatile uint16_t *)REG_CAN0_MB03_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB04_DATA3             ((volatile uint16_t *)REG_CAN0_MB04_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB05_DATA3             ((volatile uint16_t *)REG_CAN0_MB05_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB06_DATA3             ((volatile uint16_t *)REG_CAN0_MB06_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB07_DATA3             ((volatile uint16_t *)REG_CAN0_MB07_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB08_DATA3             ((volatile uint16_t *)REG_CAN0_MB08_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB09_DATA3             ((volatile uint16_t *)REG_CAN0_MB09_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB10_DATA3             ((volatile uint16_t *)REG_CAN0_MB10_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB11_DATA3             ((volatile uint16_t *)REG_CAN0_MB11_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB12_DATA3             ((volatile uint16_t *)REG_CAN0_MB12_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB13_DATA3             ((volatile uint16_t *)REG_CAN0_MB13_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB14_DATA3             ((volatile uint16_t *)REG_CAN0_MB14_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB15_DATA3             ((volatile uint16_t *)REG_CAN0_MB15_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB16_DATA3             ((volatile uint16_t *)REG_CAN0_MB16_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB17_DATA3             ((volatile uint16_t *)REG_CAN0_MB17_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB18_DATA3             ((volatile uint16_t *)REG_CAN0_MB18_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB19_DATA3             ((volatile uint16_t *)REG_CAN0_MB19_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB20_DATA3             ((volatile uint16_t *)REG_CAN0_MB20_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB21_DATA3             ((volatile uint16_t *)REG_CAN0_MB21_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB22_DATA3             ((volatile uint16_t *)REG_CAN0_MB22_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB23_DATA3             ((volatile uint16_t *)REG_CAN0_MB23_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB24_DATA3             ((volatile uint16_t *)REG_CAN0_MB24_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB25_DATA3             ((volatile uint16_t *)REG_CAN0_MB25_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB26_DATA3             ((volatile uint16_t *)REG_CAN0_MB26_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB27_DATA3             ((volatile uint16_t *)REG_CAN0_MB27_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB28_DATA3             ((volatile uint16_t *)REG_CAN0_MB28_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB29_DATA3             ((volatile uint16_t *)REG_CAN0_MB29_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB30_DATA3             ((volatile uint16_t *)REG_CAN0_MB30_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB31_DATA3             ((volatile uint16_t *)REG_CAN0_MB31_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB00_LENGTH            ((volatile uint16_t *)REG_CAN0_MB00_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB01_LENGTH            ((volatile uint16_t *)REG_CAN0_MB01_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB02_LENGTH            ((volatile uint16_t *)REG_CAN0_MB02_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB03_LENGTH            ((volatile uint16_t *)REG_CAN0_MB03_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB04_LENGTH            ((volatile uint16_t *)REG_CAN0_MB04_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB05_LENGTH            ((volatile uint16_t *)REG_CAN0_MB05_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB06_LENGTH            ((volatile uint16_t *)REG_CAN0_MB06_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB07_LENGTH            ((volatile uint16_t *)REG_CAN0_MB07_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB08_LENGTH            ((volatile uint16_t *)REG_CAN0_MB08_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB09_LENGTH            ((volatile uint16_t *)REG_CAN0_MB09_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB10_LENGTH            ((volatile uint16_t *)REG_CAN0_MB10_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB11_LENGTH            ((volatile uint16_t *)REG_CAN0_MB11_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB12_LENGTH            ((volatile uint16_t *)REG_CAN0_MB12_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB13_LENGTH            ((volatile uint16_t *)REG_CAN0_MB13_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB14_LENGTH            ((volatile uint16_t *)REG_CAN0_MB14_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB15_LENGTH            ((volatile uint16_t *)REG_CAN0_MB15_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB16_LENGTH            ((volatile uint16_t *)REG_CAN0_MB16_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB17_LENGTH            ((volatile uint16_t *)REG_CAN0_MB17_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB18_LENGTH            ((volatile uint16_t *)REG_CAN0_MB18_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB19_LENGTH            ((volatile uint16_t *)REG_CAN0_MB19_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB20_LENGTH            ((volatile uint16_t *)REG_CAN0_MB20_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB21_LENGTH            ((volatile uint16_t *)REG_CAN0_MB21_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB22_LENGTH            ((volatile uint16_t *)REG_CAN0_MB22_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB23_LENGTH            ((volatile uint16_t *)REG_CAN0_MB23_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB24_LENGTH            ((volatile uint16_t *)REG_CAN0_MB24_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB25_LENGTH            ((volatile uint16_t *)REG_CAN0_MB25_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB26_LENGTH            ((volatile uint16_t *)REG_CAN0_MB26_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB27_LENGTH            ((volatile uint16_t *)REG_CAN0_MB27_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB28_LENGTH            ((volatile uint16_t *)REG_CAN0_MB28_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB29_LENGTH            ((volatile uint16_t *)REG_CAN0_MB29_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB30_LENGTH            ((volatile uint16_t *)REG_CAN0_MB30_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB31_LENGTH            ((volatile uint16_t *)REG_CAN0_MB31_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB00_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB00_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB01_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB01_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB02_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB02_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB03_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB03_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB04_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB04_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB05_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB05_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB06_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB06_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB07_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB07_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB08_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB08_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB09_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB09_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB10_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB10_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB11_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB11_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB12_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB12_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB13_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB13_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB14_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB14_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB15_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB15_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB16_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB16_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB17_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB17_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB18_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB18_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB19_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB19_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB20_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB20_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB21_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB21_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB22_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB22_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB23_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB23_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB24_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB24_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB25_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB25_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB26_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB26_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB27_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB27_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB28_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB28_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB29_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB29_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB30_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB30_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB31_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB31_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB00_ID0               ((volatile uint16_t *)REG_CAN0_MB00_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB01_ID0               ((volatile uint16_t *)REG_CAN0_MB01_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB02_ID0               ((volatile uint16_t *)REG_CAN0_MB02_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB03_ID0               ((volatile uint16_t *)REG_CAN0_MB03_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB04_ID0               ((volatile uint16_t *)REG_CAN0_MB04_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB05_ID0               ((volatile uint16_t *)REG_CAN0_MB05_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB06_ID0               ((volatile uint16_t *)REG_CAN0_MB06_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB07_ID0               ((volatile uint16_t *)REG_CAN0_MB07_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB08_ID0               ((volatile uint16_t *)REG_CAN0_MB08_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB09_ID0               ((volatile uint16_t *)REG_CAN0_MB09_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB10_ID0               ((volatile uint16_t *)REG_CAN0_MB10_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB11_ID0               ((volatile uint16_t *)REG_CAN0_MB11_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB12_ID0               ((volatile uint16_t *)REG_CAN0_MB12_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB13_ID0               ((volatile uint16_t *)REG_CAN0_MB13_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB14_ID0               ((volatile uint16_t *)REG_CAN0_MB14_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB15_ID0               ((volatile uint16_t *)REG_CAN0_MB15_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB16_ID0               ((volatile uint16_t *)REG_CAN0_MB16_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB17_ID0               ((volatile uint16_t *)REG_CAN0_MB17_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB18_ID0               ((volatile uint16_t *)REG_CAN0_MB18_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB19_ID0               ((volatile uint16_t *)REG_CAN0_MB19_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB20_ID0               ((volatile uint16_t *)REG_CAN0_MB20_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB21_ID0               ((volatile uint16_t *)REG_CAN0_MB21_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB22_ID0               ((volatile uint16_t *)REG_CAN0_MB22_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB23_ID0               ((volatile uint16_t *)REG_CAN0_MB23_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB24_ID0               ((volatile uint16_t *)REG_CAN0_MB24_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB25_ID0               ((volatile uint16_t *)REG_CAN0_MB25_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB26_ID0               ((volatile uint16_t *)REG_CAN0_MB26_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB27_ID0               ((volatile uint16_t *)REG_CAN0_MB27_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB28_ID0               ((volatile uint16_t *)REG_CAN0_MB28_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB29_ID0               ((volatile uint16_t *)REG_CAN0_MB29_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB30_ID0               ((volatile uint16_t *)REG_CAN0_MB30_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB31_ID0               ((volatile uint16_t *)REG_CAN0_MB31_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB00_ID1               ((volatile uint16_t *)REG_CAN0_MB00_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB01_ID1               ((volatile uint16_t *)REG_CAN0_MB01_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB02_ID1               ((volatile uint16_t *)REG_CAN0_MB02_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB03_ID1               ((volatile uint16_t *)REG_CAN0_MB03_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB04_ID1               ((volatile uint16_t *)REG_CAN0_MB04_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB05_ID1               ((volatile uint16_t *)REG_CAN0_MB05_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB06_ID1               ((volatile uint16_t *)REG_CAN0_MB06_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB07_ID1               ((volatile uint16_t *)REG_CAN0_MB07_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB08_ID1               ((volatile uint16_t *)REG_CAN0_MB08_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB09_ID1               ((volatile uint16_t *)REG_CAN0_MB09_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB10_ID1               ((volatile uint16_t *)REG_CAN0_MB10_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB11_ID1               ((volatile uint16_t *)REG_CAN0_MB11_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB12_ID1               ((volatile uint16_t *)REG_CAN0_MB12_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB13_ID1               ((volatile uint16_t *)REG_CAN0_MB13_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB14_ID1               ((volatile uint16_t *)REG_CAN0_MB14_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB15_ID1               ((volatile uint16_t *)REG_CAN0_MB15_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB16_ID1               ((volatile uint16_t *)REG_CAN0_MB16_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB17_ID1               ((volatile uint16_t *)REG_CAN0_MB17_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB18_ID1               ((volatile uint16_t *)REG_CAN0_MB18_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB19_ID1               ((volatile uint16_t *)REG_CAN0_MB19_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB20_ID1               ((volatile uint16_t *)REG_CAN0_MB20_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB21_ID1               ((volatile uint16_t *)REG_CAN0_MB21_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB22_ID1               ((volatile uint16_t *)REG_CAN0_MB22_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB23_ID1               ((volatile uint16_t *)REG_CAN0_MB23_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB24_ID1               ((volatile uint16_t *)REG_CAN0_MB24_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB25_ID1               ((volatile uint16_t *)REG_CAN0_MB25_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB26_ID1               ((volatile uint16_t *)REG_CAN0_MB26_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB27_ID1               ((volatile uint16_t *)REG_CAN0_MB27_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB28_ID1               ((volatile uint16_t *)REG_CAN0_MB28_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB29_ID1               ((volatile uint16_t *)REG_CAN0_MB29_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB30_ID1               ((volatile uint16_t *)REG_CAN0_MB30_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB31_ID1               ((volatile uint16_t *)REG_CAN0_MB31_ID1)                /* CAN0 Mailbox ID 1 Register */
-
-
-/* =========================================================================
-       LP0
-   ========================================================================= */
-#define pREG_LP0_CTL                     ((volatile uint32_t *)REG_LP0_CTL)                      /* LP0 Control Register */
-#define pREG_LP0_STAT                    ((volatile uint32_t *)REG_LP0_STAT)                     /* LP0 Status Register */
-#define pREG_LP0_DIV                     ((volatile uint32_t *)REG_LP0_DIV)                      /* LP0 Clock Divider Value */
-#define pREG_LP0_TX                      ((volatile uint32_t *)REG_LP0_TX)                       /* LP0 Transmit Buffer */
-#define pREG_LP0_RX                      ((volatile uint32_t *)REG_LP0_RX)                       /* LP0 Receive Buffer */
-#define pREG_LP0_TXIN_SHDW               ((volatile uint32_t *)REG_LP0_TXIN_SHDW)                /* LP0 Shadow Input Transmit Buffer */
-#define pREG_LP0_TXOUT_SHDW              ((volatile uint32_t *)REG_LP0_TXOUT_SHDW)               /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP1
-   ========================================================================= */
-#define pREG_LP1_CTL                     ((volatile uint32_t *)REG_LP1_CTL)                      /* LP1 Control Register */
-#define pREG_LP1_STAT                    ((volatile uint32_t *)REG_LP1_STAT)                     /* LP1 Status Register */
-#define pREG_LP1_DIV                     ((volatile uint32_t *)REG_LP1_DIV)                      /* LP1 Clock Divider Value */
-#define pREG_LP1_TX                      ((volatile uint32_t *)REG_LP1_TX)                       /* LP1 Transmit Buffer */
-#define pREG_LP1_RX                      ((volatile uint32_t *)REG_LP1_RX)                       /* LP1 Receive Buffer */
-#define pREG_LP1_TXIN_SHDW               ((volatile uint32_t *)REG_LP1_TXIN_SHDW)                /* LP1 Shadow Input Transmit Buffer */
-#define pREG_LP1_TXOUT_SHDW              ((volatile uint32_t *)REG_LP1_TXOUT_SHDW)               /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP2
-   ========================================================================= */
-#define pREG_LP2_CTL                     ((volatile uint32_t *)REG_LP2_CTL)                      /* LP2 Control Register */
-#define pREG_LP2_STAT                    ((volatile uint32_t *)REG_LP2_STAT)                     /* LP2 Status Register */
-#define pREG_LP2_DIV                     ((volatile uint32_t *)REG_LP2_DIV)                      /* LP2 Clock Divider Value */
-#define pREG_LP2_TX                      ((volatile uint32_t *)REG_LP2_TX)                       /* LP2 Transmit Buffer */
-#define pREG_LP2_RX                      ((volatile uint32_t *)REG_LP2_RX)                       /* LP2 Receive Buffer */
-#define pREG_LP2_TXIN_SHDW               ((volatile uint32_t *)REG_LP2_TXIN_SHDW)                /* LP2 Shadow Input Transmit Buffer */
-#define pREG_LP2_TXOUT_SHDW              ((volatile uint32_t *)REG_LP2_TXOUT_SHDW)               /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP3
-   ========================================================================= */
-#define pREG_LP3_CTL                     ((volatile uint32_t *)REG_LP3_CTL)                      /* LP3 Control Register */
-#define pREG_LP3_STAT                    ((volatile uint32_t *)REG_LP3_STAT)                     /* LP3 Status Register */
-#define pREG_LP3_DIV                     ((volatile uint32_t *)REG_LP3_DIV)                      /* LP3 Clock Divider Value */
-#define pREG_LP3_TX                      ((volatile uint32_t *)REG_LP3_TX)                       /* LP3 Transmit Buffer */
-#define pREG_LP3_RX                      ((volatile uint32_t *)REG_LP3_RX)                       /* LP3 Receive Buffer */
-#define pREG_LP3_TXIN_SHDW               ((volatile uint32_t *)REG_LP3_TXIN_SHDW)                /* LP3 Shadow Input Transmit Buffer */
-#define pREG_LP3_TXOUT_SHDW              ((volatile uint32_t *)REG_LP3_TXOUT_SHDW)               /* LP3 Shadow Output Transmit Buffer */
-
-
-/* =========================================================================
-       TIMER0
-   ========================================================================= */
-#define pREG_TIMER0_REVID                ((volatile uint16_t *)REG_TIMER0_REVID)                 /* TIMER0 Revision ID Register */
-#define pREG_TIMER0_RUN                  ((volatile uint16_t *)REG_TIMER0_RUN)                   /* TIMER0 Run Register */
-#define pREG_TIMER0_RUN_SET              ((volatile uint16_t *)REG_TIMER0_RUN_SET)               /* TIMER0 Run Set Register */
-#define pREG_TIMER0_RUN_CLR              ((volatile uint16_t *)REG_TIMER0_RUN_CLR)               /* TIMER0 Run Clear Register */
-#define pREG_TIMER0_STOP_CFG             ((volatile uint16_t *)REG_TIMER0_STOP_CFG)              /* TIMER0 Stop Configuration Register */
-#define pREG_TIMER0_STOP_CFG_SET         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_SET)          /* TIMER0 Stop Configuration Set Register */
-#define pREG_TIMER0_STOP_CFG_CLR         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_CLR)          /* TIMER0 Stop Configuration Clear Register */
-#define pREG_TIMER0_DATA_IMSK            ((volatile uint16_t *)REG_TIMER0_DATA_IMSK)             /* TIMER0 Data Interrupt Mask Register */
-#define pREG_TIMER0_STAT_IMSK            ((volatile uint16_t *)REG_TIMER0_STAT_IMSK)             /* TIMER0 Status Interrupt Mask Register */
-#define pREG_TIMER0_TRG_MSK              ((volatile uint16_t *)REG_TIMER0_TRG_MSK)               /* TIMER0 Trigger Master Mask Register */
-#define pREG_TIMER0_TRG_IE               ((volatile uint16_t *)REG_TIMER0_TRG_IE)                /* TIMER0 Trigger Slave Enable Register */
-#define pREG_TIMER0_DATA_ILAT            ((volatile uint16_t *)REG_TIMER0_DATA_ILAT)             /* TIMER0 Data Interrupt Latch Register */
-#define pREG_TIMER0_STAT_ILAT            ((volatile uint16_t *)REG_TIMER0_STAT_ILAT)             /* TIMER0 Status Interrupt Latch Register */
-#define pREG_TIMER0_ERR_TYPE             ((volatile uint32_t *)REG_TIMER0_ERR_TYPE)              /* TIMER0 Error Type Status Register */
-#define pREG_TIMER0_BCAST_PER            ((volatile uint32_t *)REG_TIMER0_BCAST_PER)             /* TIMER0 Broadcast Period Register */
-#define pREG_TIMER0_BCAST_WID            ((volatile uint32_t *)REG_TIMER0_BCAST_WID)             /* TIMER0 Broadcast Width Register */
-#define pREG_TIMER0_BCAST_DLY            ((volatile uint32_t *)REG_TIMER0_BCAST_DLY)             /* TIMER0 Broadcast Delay Register */
-#define pREG_TIMER0_TMR0_CFG             ((volatile uint16_t *)REG_TIMER0_TMR0_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR1_CFG             ((volatile uint16_t *)REG_TIMER0_TMR1_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR2_CFG             ((volatile uint16_t *)REG_TIMER0_TMR2_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR3_CFG             ((volatile uint16_t *)REG_TIMER0_TMR3_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR4_CFG             ((volatile uint16_t *)REG_TIMER0_TMR4_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR5_CFG             ((volatile uint16_t *)REG_TIMER0_TMR5_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR6_CFG             ((volatile uint16_t *)REG_TIMER0_TMR6_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR7_CFG             ((volatile uint16_t *)REG_TIMER0_TMR7_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR0_CNT             ((volatile uint32_t *)REG_TIMER0_TMR0_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR1_CNT             ((volatile uint32_t *)REG_TIMER0_TMR1_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR2_CNT             ((volatile uint32_t *)REG_TIMER0_TMR2_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR3_CNT             ((volatile uint32_t *)REG_TIMER0_TMR3_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR4_CNT             ((volatile uint32_t *)REG_TIMER0_TMR4_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR5_CNT             ((volatile uint32_t *)REG_TIMER0_TMR5_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR6_CNT             ((volatile uint32_t *)REG_TIMER0_TMR6_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR7_CNT             ((volatile uint32_t *)REG_TIMER0_TMR7_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR0_PER             ((volatile uint32_t *)REG_TIMER0_TMR0_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR1_PER             ((volatile uint32_t *)REG_TIMER0_TMR1_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR2_PER             ((volatile uint32_t *)REG_TIMER0_TMR2_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR3_PER             ((volatile uint32_t *)REG_TIMER0_TMR3_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR4_PER             ((volatile uint32_t *)REG_TIMER0_TMR4_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR5_PER             ((volatile uint32_t *)REG_TIMER0_TMR5_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR6_PER             ((volatile uint32_t *)REG_TIMER0_TMR6_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR7_PER             ((volatile uint32_t *)REG_TIMER0_TMR7_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR0_WID             ((volatile uint32_t *)REG_TIMER0_TMR0_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR1_WID             ((volatile uint32_t *)REG_TIMER0_TMR1_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR2_WID             ((volatile uint32_t *)REG_TIMER0_TMR2_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR3_WID             ((volatile uint32_t *)REG_TIMER0_TMR3_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR4_WID             ((volatile uint32_t *)REG_TIMER0_TMR4_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR5_WID             ((volatile uint32_t *)REG_TIMER0_TMR5_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR6_WID             ((volatile uint32_t *)REG_TIMER0_TMR6_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR7_WID             ((volatile uint32_t *)REG_TIMER0_TMR7_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR0_DLY             ((volatile uint32_t *)REG_TIMER0_TMR0_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR1_DLY             ((volatile uint32_t *)REG_TIMER0_TMR1_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR2_DLY             ((volatile uint32_t *)REG_TIMER0_TMR2_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR3_DLY             ((volatile uint32_t *)REG_TIMER0_TMR3_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR4_DLY             ((volatile uint32_t *)REG_TIMER0_TMR4_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR5_DLY             ((volatile uint32_t *)REG_TIMER0_TMR5_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR6_DLY             ((volatile uint32_t *)REG_TIMER0_TMR6_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR7_DLY             ((volatile uint32_t *)REG_TIMER0_TMR7_DLY)              /* TIMER0 Timer n Delay Register */
-
-
-/* =========================================================================
-       CRC0
-   ========================================================================= */
-#define pREG_CRC0_CTL                    ((volatile uint32_t *)REG_CRC0_CTL)                     /* CRC0 Control Register */
-#define pREG_CRC0_DCNT                   ((volatile uint32_t *)REG_CRC0_DCNT)                    /* CRC0 Data Word Count Register */
-#define pREG_CRC0_DCNTRLD                ((volatile uint32_t *)REG_CRC0_DCNTRLD)                 /* CRC0 Data Word Count Reload Register */
-#define pREG_CRC0_COMP                   ((volatile uint32_t *)REG_CRC0_COMP)                    /* CRC0 Data Compare Register */
-#define pREG_CRC0_FILLVAL                ((volatile uint32_t *)REG_CRC0_FILLVAL)                 /* CRC0 Fill Value Register */
-#define pREG_CRC0_DFIFO                  ((volatile uint32_t *)REG_CRC0_DFIFO)                   /* CRC0 Data FIFO Register */
-#define pREG_CRC0_INEN                   ((volatile uint32_t *)REG_CRC0_INEN)                    /* CRC0 Interrupt Enable Register */
-#define pREG_CRC0_INEN_SET               ((volatile uint32_t *)REG_CRC0_INEN_SET)                /* CRC0 Interrupt Enable Set Register */
-#define pREG_CRC0_INEN_CLR               ((volatile uint32_t *)REG_CRC0_INEN_CLR)                /* CRC0 Interrupt Enable Clear Register */
-#define pREG_CRC0_POLY                   ((volatile uint32_t *)REG_CRC0_POLY)                    /* CRC0 Polynomial Register */
-#define pREG_CRC0_STAT                   ((volatile uint32_t *)REG_CRC0_STAT)                    /* CRC0 Status Register */
-#define pREG_CRC0_DCNTCAP                ((volatile uint32_t *)REG_CRC0_DCNTCAP)                 /* CRC0 Data Count Capture Register */
-#define pREG_CRC0_RESULT_FIN             ((volatile uint32_t *)REG_CRC0_RESULT_FIN)              /* CRC0 CRC Final Result Register */
-#define pREG_CRC0_RESULT_CUR             ((volatile uint32_t *)REG_CRC0_RESULT_CUR)              /* CRC0 CRC Current Result Register */
-#define pREG_CRC0_REVID                  ((volatile uint32_t *)REG_CRC0_REVID)                   /* CRC0 Revision ID Register */
-
-/* =========================================================================
-       CRC1
-   ========================================================================= */
-#define pREG_CRC1_CTL                    ((volatile uint32_t *)REG_CRC1_CTL)                     /* CRC1 Control Register */
-#define pREG_CRC1_DCNT                   ((volatile uint32_t *)REG_CRC1_DCNT)                    /* CRC1 Data Word Count Register */
-#define pREG_CRC1_DCNTRLD                ((volatile uint32_t *)REG_CRC1_DCNTRLD)                 /* CRC1 Data Word Count Reload Register */
-#define pREG_CRC1_COMP                   ((volatile uint32_t *)REG_CRC1_COMP)                    /* CRC1 Data Compare Register */
-#define pREG_CRC1_FILLVAL                ((volatile uint32_t *)REG_CRC1_FILLVAL)                 /* CRC1 Fill Value Register */
-#define pREG_CRC1_DFIFO                  ((volatile uint32_t *)REG_CRC1_DFIFO)                   /* CRC1 Data FIFO Register */
-#define pREG_CRC1_INEN                   ((volatile uint32_t *)REG_CRC1_INEN)                    /* CRC1 Interrupt Enable Register */
-#define pREG_CRC1_INEN_SET               ((volatile uint32_t *)REG_CRC1_INEN_SET)                /* CRC1 Interrupt Enable Set Register */
-#define pREG_CRC1_INEN_CLR               ((volatile uint32_t *)REG_CRC1_INEN_CLR)                /* CRC1 Interrupt Enable Clear Register */
-#define pREG_CRC1_POLY                   ((volatile uint32_t *)REG_CRC1_POLY)                    /* CRC1 Polynomial Register */
-#define pREG_CRC1_STAT                   ((volatile uint32_t *)REG_CRC1_STAT)                    /* CRC1 Status Register */
-#define pREG_CRC1_DCNTCAP                ((volatile uint32_t *)REG_CRC1_DCNTCAP)                 /* CRC1 Data Count Capture Register */
-#define pREG_CRC1_RESULT_FIN             ((volatile uint32_t *)REG_CRC1_RESULT_FIN)              /* CRC1 CRC Final Result Register */
-#define pREG_CRC1_RESULT_CUR             ((volatile uint32_t *)REG_CRC1_RESULT_CUR)              /* CRC1 CRC Current Result Register */
-#define pREG_CRC1_REVID                  ((volatile uint32_t *)REG_CRC1_REVID)                   /* CRC1 Revision ID Register */
-
-
-/* =========================================================================
-       TWI0
-   ========================================================================= */
-#define pREG_TWI0_CLKDIV                 ((volatile uint16_t *)REG_TWI0_CLKDIV)                  /* TWI0 SCL Clock Divider Register */
-#define pREG_TWI0_CTL                    ((volatile uint16_t *)REG_TWI0_CTL)                     /* TWI0 Control Register */
-#define pREG_TWI0_SLVCTL                 ((volatile uint16_t *)REG_TWI0_SLVCTL)                  /* TWI0 Slave Mode Control Register */
-#define pREG_TWI0_SLVSTAT                ((volatile uint16_t *)REG_TWI0_SLVSTAT)                 /* TWI0 Slave Mode Status Register */
-#define pREG_TWI0_SLVADDR                ((volatile uint16_t *)REG_TWI0_SLVADDR)                 /* TWI0 Slave Mode Address Register */
-#define pREG_TWI0_MSTRCTL                ((volatile uint16_t *)REG_TWI0_MSTRCTL)                 /* TWI0 Master Mode Control Registers */
-#define pREG_TWI0_MSTRSTAT               ((volatile uint16_t *)REG_TWI0_MSTRSTAT)                /* TWI0 Master Mode Status Register */
-#define pREG_TWI0_MSTRADDR               ((volatile uint16_t *)REG_TWI0_MSTRADDR)                /* TWI0 Master Mode Address Register */
-#define pREG_TWI0_ISTAT                  ((volatile uint16_t *)REG_TWI0_ISTAT)                   /* TWI0 Interrupt Status Register */
-#define pREG_TWI0_IMSK                   ((volatile uint16_t *)REG_TWI0_IMSK)                    /* TWI0 Interrupt Mask Register */
-#define pREG_TWI0_FIFOCTL                ((volatile uint16_t *)REG_TWI0_FIFOCTL)                 /* TWI0 FIFO Control Register */
-#define pREG_TWI0_FIFOSTAT               ((volatile uint16_t *)REG_TWI0_FIFOSTAT)                /* TWI0 FIFO Status Register */
-#define pREG_TWI0_TXDATA8                ((volatile uint16_t *)REG_TWI0_TXDATA8)                 /* TWI0 Tx Data Single-Byte Register */
-#define pREG_TWI0_TXDATA16               ((volatile uint16_t *)REG_TWI0_TXDATA16)                /* TWI0 Tx Data Double-Byte Register */
-#define pREG_TWI0_RXDATA8                ((volatile uint16_t *)REG_TWI0_RXDATA8)                 /* TWI0 Rx Data Single-Byte Register */
-#define pREG_TWI0_RXDATA16               ((volatile uint16_t *)REG_TWI0_RXDATA16)                /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================================================================
-       TWI1
-   ========================================================================= */
-#define pREG_TWI1_CLKDIV                 ((volatile uint16_t *)REG_TWI1_CLKDIV)                  /* TWI1 SCL Clock Divider Register */
-#define pREG_TWI1_CTL                    ((volatile uint16_t *)REG_TWI1_CTL)                     /* TWI1 Control Register */
-#define pREG_TWI1_SLVCTL                 ((volatile uint16_t *)REG_TWI1_SLVCTL)                  /* TWI1 Slave Mode Control Register */
-#define pREG_TWI1_SLVSTAT                ((volatile uint16_t *)REG_TWI1_SLVSTAT)                 /* TWI1 Slave Mode Status Register */
-#define pREG_TWI1_SLVADDR                ((volatile uint16_t *)REG_TWI1_SLVADDR)                 /* TWI1 Slave Mode Address Register */
-#define pREG_TWI1_MSTRCTL                ((volatile uint16_t *)REG_TWI1_MSTRCTL)                 /* TWI1 Master Mode Control Registers */
-#define pREG_TWI1_MSTRSTAT               ((volatile uint16_t *)REG_TWI1_MSTRSTAT)                /* TWI1 Master Mode Status Register */
-#define pREG_TWI1_MSTRADDR               ((volatile uint16_t *)REG_TWI1_MSTRADDR)                /* TWI1 Master Mode Address Register */
-#define pREG_TWI1_ISTAT                  ((volatile uint16_t *)REG_TWI1_ISTAT)                   /* TWI1 Interrupt Status Register */
-#define pREG_TWI1_IMSK                   ((volatile uint16_t *)REG_TWI1_IMSK)                    /* TWI1 Interrupt Mask Register */
-#define pREG_TWI1_FIFOCTL                ((volatile uint16_t *)REG_TWI1_FIFOCTL)                 /* TWI1 FIFO Control Register */
-#define pREG_TWI1_FIFOSTAT               ((volatile uint16_t *)REG_TWI1_FIFOSTAT)                /* TWI1 FIFO Status Register */
-#define pREG_TWI1_TXDATA8                ((volatile uint16_t *)REG_TWI1_TXDATA8)                 /* TWI1 Tx Data Single-Byte Register */
-#define pREG_TWI1_TXDATA16               ((volatile uint16_t *)REG_TWI1_TXDATA16)                /* TWI1 Tx Data Double-Byte Register */
-#define pREG_TWI1_RXDATA8                ((volatile uint16_t *)REG_TWI1_RXDATA8)                 /* TWI1 Rx Data Single-Byte Register */
-#define pREG_TWI1_RXDATA16               ((volatile uint16_t *)REG_TWI1_RXDATA16)                /* TWI1 Rx Data Double-Byte Register */
-
-
-/* =========================================================================
-       UART0
-   ========================================================================= */
-#define pREG_UART0_REVID                 ((volatile uint32_t *)REG_UART0_REVID)                  /* UART0 Revision ID Register */
-#define pREG_UART0_CTL                   ((volatile uint32_t *)REG_UART0_CTL)                    /* UART0 Control Register */
-#define pREG_UART0_STAT                  ((volatile uint32_t *)REG_UART0_STAT)                   /* UART0 Status Register */
-#define pREG_UART0_SCR                   ((volatile uint32_t *)REG_UART0_SCR)                    /* UART0 Scratch Register */
-#define pREG_UART0_CLK                   ((volatile uint32_t *)REG_UART0_CLK)                    /* UART0 Clock Rate Register */
-#define pREG_UART0_IMSK                  ((volatile uint32_t *)REG_UART0_IMSK)                   /* UART0 Interrupt Mask Register */
-#define pREG_UART0_IMSK_SET              ((volatile uint32_t *)REG_UART0_IMSK_SET)               /* UART0 Interrupt Mask Set Register */
-#define pREG_UART0_IMSK_CLR              ((volatile uint32_t *)REG_UART0_IMSK_CLR)               /* UART0 Interrupt Mask Clear Register */
-#define pREG_UART0_RBR                   ((volatile uint32_t *)REG_UART0_RBR)                    /* UART0 Receive Buffer Register */
-#define pREG_UART0_THR                   ((volatile uint32_t *)REG_UART0_THR)                    /* UART0 Transmit Hold Register */
-#define pREG_UART0_TAIP                  ((volatile uint32_t *)REG_UART0_TAIP)                   /* UART0 Transmit Address/Insert Pulse Register */
-#define pREG_UART0_TSR                   ((volatile uint32_t *)REG_UART0_TSR)                    /* UART0 Transmit Shift Register */
-#define pREG_UART0_RSR                   ((volatile uint32_t *)REG_UART0_RSR)                    /* UART0 Receive Shift Register */
-#define pREG_UART0_TXCNT                 ((volatile uint32_t *)REG_UART0_TXCNT)                  /* UART0 Transmit Counter Register */
-#define pREG_UART0_RXCNT                 ((volatile uint32_t *)REG_UART0_RXCNT)                  /* UART0 Receive Counter Register */
-
-/* =========================================================================
-       UART1
-   ========================================================================= */
-#define pREG_UART1_REVID                 ((volatile uint32_t *)REG_UART1_REVID)                  /* UART1 Revision ID Register */
-#define pREG_UART1_CTL                   ((volatile uint32_t *)REG_UART1_CTL)                    /* UART1 Control Register */
-#define pREG_UART1_STAT                  ((volatile uint32_t *)REG_UART1_STAT)                   /* UART1 Status Register */
-#define pREG_UART1_SCR                   ((volatile uint32_t *)REG_UART1_SCR)                    /* UART1 Scratch Register */
-#define pREG_UART1_CLK                   ((volatile uint32_t *)REG_UART1_CLK)                    /* UART1 Clock Rate Register */
-#define pREG_UART1_IMSK                  ((volatile uint32_t *)REG_UART1_IMSK)                   /* UART1 Interrupt Mask Register */
-#define pREG_UART1_IMSK_SET              ((volatile uint32_t *)REG_UART1_IMSK_SET)               /* UART1 Interrupt Mask Set Register */
-#define pREG_UART1_IMSK_CLR              ((volatile uint32_t *)REG_UART1_IMSK_CLR)               /* UART1 Interrupt Mask Clear Register */
-#define pREG_UART1_RBR                   ((volatile uint32_t *)REG_UART1_RBR)                    /* UART1 Receive Buffer Register */
-#define pREG_UART1_THR                   ((volatile uint32_t *)REG_UART1_THR)                    /* UART1 Transmit Hold Register */
-#define pREG_UART1_TAIP                  ((volatile uint32_t *)REG_UART1_TAIP)                   /* UART1 Transmit Address/Insert Pulse Register */
-#define pREG_UART1_TSR                   ((volatile uint32_t *)REG_UART1_TSR)                    /* UART1 Transmit Shift Register */
-#define pREG_UART1_RSR                   ((volatile uint32_t *)REG_UART1_RSR)                    /* UART1 Receive Shift Register */
-#define pREG_UART1_TXCNT                 ((volatile uint32_t *)REG_UART1_TXCNT)                  /* UART1 Transmit Counter Register */
-#define pREG_UART1_RXCNT                 ((volatile uint32_t *)REG_UART1_RXCNT)                  /* UART1 Receive Counter Register */
-
-
-/* =========================================================================
-       PORTA
-   ========================================================================= */
-#define pREG_PORTA_FER                   ((volatile uint32_t *)REG_PORTA_FER)                    /* PORTA Port x Function Enable Register */
-#define pREG_PORTA_FER_SET               ((volatile uint32_t *)REG_PORTA_FER_SET)                /* PORTA Port x Function Enable Set Register */
-#define pREG_PORTA_FER_CLR               ((volatile uint32_t *)REG_PORTA_FER_CLR)                /* PORTA Port x Function Enable Clear Register */
-#define pREG_PORTA_DATA                  ((volatile uint32_t *)REG_PORTA_DATA)                   /* PORTA Port x GPIO Data Register */
-#define pREG_PORTA_DATA_SET              ((volatile uint32_t *)REG_PORTA_DATA_SET)               /* PORTA Port x GPIO Data Set Register */
-#define pREG_PORTA_DATA_CLR              ((volatile uint32_t *)REG_PORTA_DATA_CLR)               /* PORTA Port x GPIO Data Clear Register */
-#define pREG_PORTA_DIR                   ((volatile uint32_t *)REG_PORTA_DIR)                    /* PORTA Port x GPIO Direction Register */
-#define pREG_PORTA_DIR_SET               ((volatile uint32_t *)REG_PORTA_DIR_SET)                /* PORTA Port x GPIO Direction Set Register */
-#define pREG_PORTA_DIR_CLR               ((volatile uint32_t *)REG_PORTA_DIR_CLR)                /* PORTA Port x GPIO Direction Clear Register */
-#define pREG_PORTA_INEN                  ((volatile uint32_t *)REG_PORTA_INEN)                   /* PORTA Port x GPIO Input Enable Register */
-#define pREG_PORTA_INEN_SET              ((volatile uint32_t *)REG_PORTA_INEN_SET)               /* PORTA Port x GPIO Input Enable Set Register */
-#define pREG_PORTA_INEN_CLR              ((volatile uint32_t *)REG_PORTA_INEN_CLR)               /* PORTA Port x GPIO Input Enable Clear Register */
-#define pREG_PORTA_MUX                   ((volatile uint32_t *)REG_PORTA_MUX)                    /* PORTA Port x Multiplexer Control Register */
-#define pREG_PORTA_DATA_TGL              ((volatile uint32_t *)REG_PORTA_DATA_TGL)               /* PORTA Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTA_POL                   ((volatile uint32_t *)REG_PORTA_POL)                    /* PORTA Port x GPIO Polarity Invert Register */
-#define pREG_PORTA_POL_SET               ((volatile uint32_t *)REG_PORTA_POL_SET)                /* PORTA Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTA_POL_CLR               ((volatile uint32_t *)REG_PORTA_POL_CLR)                /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTA_LOCK                  ((volatile uint32_t *)REG_PORTA_LOCK)                   /* PORTA Port x GPIO Lock Register */
-#define pREG_PORTA_REVID                 ((volatile uint32_t *)REG_PORTA_REVID)                  /* PORTA Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTB
-   ========================================================================= */
-#define pREG_PORTB_FER                   ((volatile uint32_t *)REG_PORTB_FER)                    /* PORTB Port x Function Enable Register */
-#define pREG_PORTB_FER_SET               ((volatile uint32_t *)REG_PORTB_FER_SET)                /* PORTB Port x Function Enable Set Register */
-#define pREG_PORTB_FER_CLR               ((volatile uint32_t *)REG_PORTB_FER_CLR)                /* PORTB Port x Function Enable Clear Register */
-#define pREG_PORTB_DATA                  ((volatile uint32_t *)REG_PORTB_DATA)                   /* PORTB Port x GPIO Data Register */
-#define pREG_PORTB_DATA_SET              ((volatile uint32_t *)REG_PORTB_DATA_SET)               /* PORTB Port x GPIO Data Set Register */
-#define pREG_PORTB_DATA_CLR              ((volatile uint32_t *)REG_PORTB_DATA_CLR)               /* PORTB Port x GPIO Data Clear Register */
-#define pREG_PORTB_DIR                   ((volatile uint32_t *)REG_PORTB_DIR)                    /* PORTB Port x GPIO Direction Register */
-#define pREG_PORTB_DIR_SET               ((volatile uint32_t *)REG_PORTB_DIR_SET)                /* PORTB Port x GPIO Direction Set Register */
-#define pREG_PORTB_DIR_CLR               ((volatile uint32_t *)REG_PORTB_DIR_CLR)                /* PORTB Port x GPIO Direction Clear Register */
-#define pREG_PORTB_INEN                  ((volatile uint32_t *)REG_PORTB_INEN)                   /* PORTB Port x GPIO Input Enable Register */
-#define pREG_PORTB_INEN_SET              ((volatile uint32_t *)REG_PORTB_INEN_SET)               /* PORTB Port x GPIO Input Enable Set Register */
-#define pREG_PORTB_INEN_CLR              ((volatile uint32_t *)REG_PORTB_INEN_CLR)               /* PORTB Port x GPIO Input Enable Clear Register */
-#define pREG_PORTB_MUX                   ((volatile uint32_t *)REG_PORTB_MUX)                    /* PORTB Port x Multiplexer Control Register */
-#define pREG_PORTB_DATA_TGL              ((volatile uint32_t *)REG_PORTB_DATA_TGL)               /* PORTB Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTB_POL                   ((volatile uint32_t *)REG_PORTB_POL)                    /* PORTB Port x GPIO Polarity Invert Register */
-#define pREG_PORTB_POL_SET               ((volatile uint32_t *)REG_PORTB_POL_SET)                /* PORTB Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTB_POL_CLR               ((volatile uint32_t *)REG_PORTB_POL_CLR)                /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTB_LOCK                  ((volatile uint32_t *)REG_PORTB_LOCK)                   /* PORTB Port x GPIO Lock Register */
-#define pREG_PORTB_REVID                 ((volatile uint32_t *)REG_PORTB_REVID)                  /* PORTB Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTC
-   ========================================================================= */
-#define pREG_PORTC_FER                   ((volatile uint32_t *)REG_PORTC_FER)                    /* PORTC Port x Function Enable Register */
-#define pREG_PORTC_FER_SET               ((volatile uint32_t *)REG_PORTC_FER_SET)                /* PORTC Port x Function Enable Set Register */
-#define pREG_PORTC_FER_CLR               ((volatile uint32_t *)REG_PORTC_FER_CLR)                /* PORTC Port x Function Enable Clear Register */
-#define pREG_PORTC_DATA                  ((volatile uint32_t *)REG_PORTC_DATA)                   /* PORTC Port x GPIO Data Register */
-#define pREG_PORTC_DATA_SET              ((volatile uint32_t *)REG_PORTC_DATA_SET)               /* PORTC Port x GPIO Data Set Register */
-#define pREG_PORTC_DATA_CLR              ((volatile uint32_t *)REG_PORTC_DATA_CLR)               /* PORTC Port x GPIO Data Clear Register */
-#define pREG_PORTC_DIR                   ((volatile uint32_t *)REG_PORTC_DIR)                    /* PORTC Port x GPIO Direction Register */
-#define pREG_PORTC_DIR_SET               ((volatile uint32_t *)REG_PORTC_DIR_SET)                /* PORTC Port x GPIO Direction Set Register */
-#define pREG_PORTC_DIR_CLR               ((volatile uint32_t *)REG_PORTC_DIR_CLR)                /* PORTC Port x GPIO Direction Clear Register */
-#define pREG_PORTC_INEN                  ((volatile uint32_t *)REG_PORTC_INEN)                   /* PORTC Port x GPIO Input Enable Register */
-#define pREG_PORTC_INEN_SET              ((volatile uint32_t *)REG_PORTC_INEN_SET)               /* PORTC Port x GPIO Input Enable Set Register */
-#define pREG_PORTC_INEN_CLR              ((volatile uint32_t *)REG_PORTC_INEN_CLR)               /* PORTC Port x GPIO Input Enable Clear Register */
-#define pREG_PORTC_MUX                   ((volatile uint32_t *)REG_PORTC_MUX)                    /* PORTC Port x Multiplexer Control Register */
-#define pREG_PORTC_DATA_TGL              ((volatile uint32_t *)REG_PORTC_DATA_TGL)               /* PORTC Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTC_POL                   ((volatile uint32_t *)REG_PORTC_POL)                    /* PORTC Port x GPIO Polarity Invert Register */
-#define pREG_PORTC_POL_SET               ((volatile uint32_t *)REG_PORTC_POL_SET)                /* PORTC Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTC_POL_CLR               ((volatile uint32_t *)REG_PORTC_POL_CLR)                /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTC_LOCK                  ((volatile uint32_t *)REG_PORTC_LOCK)                   /* PORTC Port x GPIO Lock Register */
-#define pREG_PORTC_REVID                 ((volatile uint32_t *)REG_PORTC_REVID)                  /* PORTC Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTD
-   ========================================================================= */
-#define pREG_PORTD_FER                   ((volatile uint32_t *)REG_PORTD_FER)                    /* PORTD Port x Function Enable Register */
-#define pREG_PORTD_FER_SET               ((volatile uint32_t *)REG_PORTD_FER_SET)                /* PORTD Port x Function Enable Set Register */
-#define pREG_PORTD_FER_CLR               ((volatile uint32_t *)REG_PORTD_FER_CLR)                /* PORTD Port x Function Enable Clear Register */
-#define pREG_PORTD_DATA                  ((volatile uint32_t *)REG_PORTD_DATA)                   /* PORTD Port x GPIO Data Register */
-#define pREG_PORTD_DATA_SET              ((volatile uint32_t *)REG_PORTD_DATA_SET)               /* PORTD Port x GPIO Data Set Register */
-#define pREG_PORTD_DATA_CLR              ((volatile uint32_t *)REG_PORTD_DATA_CLR)               /* PORTD Port x GPIO Data Clear Register */
-#define pREG_PORTD_DIR                   ((volatile uint32_t *)REG_PORTD_DIR)                    /* PORTD Port x GPIO Direction Register */
-#define pREG_PORTD_DIR_SET               ((volatile uint32_t *)REG_PORTD_DIR_SET)                /* PORTD Port x GPIO Direction Set Register */
-#define pREG_PORTD_DIR_CLR               ((volatile uint32_t *)REG_PORTD_DIR_CLR)                /* PORTD Port x GPIO Direction Clear Register */
-#define pREG_PORTD_INEN                  ((volatile uint32_t *)REG_PORTD_INEN)                   /* PORTD Port x GPIO Input Enable Register */
-#define pREG_PORTD_INEN_SET              ((volatile uint32_t *)REG_PORTD_INEN_SET)               /* PORTD Port x GPIO Input Enable Set Register */
-#define pREG_PORTD_INEN_CLR              ((volatile uint32_t *)REG_PORTD_INEN_CLR)               /* PORTD Port x GPIO Input Enable Clear Register */
-#define pREG_PORTD_MUX                   ((volatile uint32_t *)REG_PORTD_MUX)                    /* PORTD Port x Multiplexer Control Register */
-#define pREG_PORTD_DATA_TGL              ((volatile uint32_t *)REG_PORTD_DATA_TGL)               /* PORTD Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTD_POL                   ((volatile uint32_t *)REG_PORTD_POL)                    /* PORTD Port x GPIO Polarity Invert Register */
-#define pREG_PORTD_POL_SET               ((volatile uint32_t *)REG_PORTD_POL_SET)                /* PORTD Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTD_POL_CLR               ((volatile uint32_t *)REG_PORTD_POL_CLR)                /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTD_LOCK                  ((volatile uint32_t *)REG_PORTD_LOCK)                   /* PORTD Port x GPIO Lock Register */
-#define pREG_PORTD_REVID                 ((volatile uint32_t *)REG_PORTD_REVID)                  /* PORTD Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTE
-   ========================================================================= */
-#define pREG_PORTE_FER                   ((volatile uint32_t *)REG_PORTE_FER)                    /* PORTE Port x Function Enable Register */
-#define pREG_PORTE_FER_SET               ((volatile uint32_t *)REG_PORTE_FER_SET)                /* PORTE Port x Function Enable Set Register */
-#define pREG_PORTE_FER_CLR               ((volatile uint32_t *)REG_PORTE_FER_CLR)                /* PORTE Port x Function Enable Clear Register */
-#define pREG_PORTE_DATA                  ((volatile uint32_t *)REG_PORTE_DATA)                   /* PORTE Port x GPIO Data Register */
-#define pREG_PORTE_DATA_SET              ((volatile uint32_t *)REG_PORTE_DATA_SET)               /* PORTE Port x GPIO Data Set Register */
-#define pREG_PORTE_DATA_CLR              ((volatile uint32_t *)REG_PORTE_DATA_CLR)               /* PORTE Port x GPIO Data Clear Register */
-#define pREG_PORTE_DIR                   ((volatile uint32_t *)REG_PORTE_DIR)                    /* PORTE Port x GPIO Direction Register */
-#define pREG_PORTE_DIR_SET               ((volatile uint32_t *)REG_PORTE_DIR_SET)                /* PORTE Port x GPIO Direction Set Register */
-#define pREG_PORTE_DIR_CLR               ((volatile uint32_t *)REG_PORTE_DIR_CLR)                /* PORTE Port x GPIO Direction Clear Register */
-#define pREG_PORTE_INEN                  ((volatile uint32_t *)REG_PORTE_INEN)                   /* PORTE Port x GPIO Input Enable Register */
-#define pREG_PORTE_INEN_SET              ((volatile uint32_t *)REG_PORTE_INEN_SET)               /* PORTE Port x GPIO Input Enable Set Register */
-#define pREG_PORTE_INEN_CLR              ((volatile uint32_t *)REG_PORTE_INEN_CLR)               /* PORTE Port x GPIO Input Enable Clear Register */
-#define pREG_PORTE_MUX                   ((volatile uint32_t *)REG_PORTE_MUX)                    /* PORTE Port x Multiplexer Control Register */
-#define pREG_PORTE_DATA_TGL              ((volatile uint32_t *)REG_PORTE_DATA_TGL)               /* PORTE Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTE_POL                   ((volatile uint32_t *)REG_PORTE_POL)                    /* PORTE Port x GPIO Polarity Invert Register */
-#define pREG_PORTE_POL_SET               ((volatile uint32_t *)REG_PORTE_POL_SET)                /* PORTE Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTE_POL_CLR               ((volatile uint32_t *)REG_PORTE_POL_CLR)                /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTE_LOCK                  ((volatile uint32_t *)REG_PORTE_LOCK)                   /* PORTE Port x GPIO Lock Register */
-#define pREG_PORTE_REVID                 ((volatile uint32_t *)REG_PORTE_REVID)                  /* PORTE Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTF
-   ========================================================================= */
-#define pREG_PORTF_FER                   ((volatile uint32_t *)REG_PORTF_FER)                    /* PORTF Port x Function Enable Register */
-#define pREG_PORTF_FER_SET               ((volatile uint32_t *)REG_PORTF_FER_SET)                /* PORTF Port x Function Enable Set Register */
-#define pREG_PORTF_FER_CLR               ((volatile uint32_t *)REG_PORTF_FER_CLR)                /* PORTF Port x Function Enable Clear Register */
-#define pREG_PORTF_DATA                  ((volatile uint32_t *)REG_PORTF_DATA)                   /* PORTF Port x GPIO Data Register */
-#define pREG_PORTF_DATA_SET              ((volatile uint32_t *)REG_PORTF_DATA_SET)               /* PORTF Port x GPIO Data Set Register */
-#define pREG_PORTF_DATA_CLR              ((volatile uint32_t *)REG_PORTF_DATA_CLR)               /* PORTF Port x GPIO Data Clear Register */
-#define pREG_PORTF_DIR                   ((volatile uint32_t *)REG_PORTF_DIR)                    /* PORTF Port x GPIO Direction Register */
-#define pREG_PORTF_DIR_SET               ((volatile uint32_t *)REG_PORTF_DIR_SET)                /* PORTF Port x GPIO Direction Set Register */
-#define pREG_PORTF_DIR_CLR               ((volatile uint32_t *)REG_PORTF_DIR_CLR)                /* PORTF Port x GPIO Direction Clear Register */
-#define pREG_PORTF_INEN                  ((volatile uint32_t *)REG_PORTF_INEN)                   /* PORTF Port x GPIO Input Enable Register */
-#define pREG_PORTF_INEN_SET              ((volatile uint32_t *)REG_PORTF_INEN_SET)               /* PORTF Port x GPIO Input Enable Set Register */
-#define pREG_PORTF_INEN_CLR              ((volatile uint32_t *)REG_PORTF_INEN_CLR)               /* PORTF Port x GPIO Input Enable Clear Register */
-#define pREG_PORTF_MUX                   ((volatile uint32_t *)REG_PORTF_MUX)                    /* PORTF Port x Multiplexer Control Register */
-#define pREG_PORTF_DATA_TGL              ((volatile uint32_t *)REG_PORTF_DATA_TGL)               /* PORTF Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTF_POL                   ((volatile uint32_t *)REG_PORTF_POL)                    /* PORTF Port x GPIO Polarity Invert Register */
-#define pREG_PORTF_POL_SET               ((volatile uint32_t *)REG_PORTF_POL_SET)                /* PORTF Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTF_POL_CLR               ((volatile uint32_t *)REG_PORTF_POL_CLR)                /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTF_LOCK                  ((volatile uint32_t *)REG_PORTF_LOCK)                   /* PORTF Port x GPIO Lock Register */
-#define pREG_PORTF_REVID                 ((volatile uint32_t *)REG_PORTF_REVID)                  /* PORTF Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTG
-   ========================================================================= */
-#define pREG_PORTG_FER                   ((volatile uint32_t *)REG_PORTG_FER)                    /* PORTG Port x Function Enable Register */
-#define pREG_PORTG_FER_SET               ((volatile uint32_t *)REG_PORTG_FER_SET)                /* PORTG Port x Function Enable Set Register */
-#define pREG_PORTG_FER_CLR               ((volatile uint32_t *)REG_PORTG_FER_CLR)                /* PORTG Port x Function Enable Clear Register */
-#define pREG_PORTG_DATA                  ((volatile uint32_t *)REG_PORTG_DATA)                   /* PORTG Port x GPIO Data Register */
-#define pREG_PORTG_DATA_SET              ((volatile uint32_t *)REG_PORTG_DATA_SET)               /* PORTG Port x GPIO Data Set Register */
-#define pREG_PORTG_DATA_CLR              ((volatile uint32_t *)REG_PORTG_DATA_CLR)               /* PORTG Port x GPIO Data Clear Register */
-#define pREG_PORTG_DIR                   ((volatile uint32_t *)REG_PORTG_DIR)                    /* PORTG Port x GPIO Direction Register */
-#define pREG_PORTG_DIR_SET               ((volatile uint32_t *)REG_PORTG_DIR_SET)                /* PORTG Port x GPIO Direction Set Register */
-#define pREG_PORTG_DIR_CLR               ((volatile uint32_t *)REG_PORTG_DIR_CLR)                /* PORTG Port x GPIO Direction Clear Register */
-#define pREG_PORTG_INEN                  ((volatile uint32_t *)REG_PORTG_INEN)                   /* PORTG Port x GPIO Input Enable Register */
-#define pREG_PORTG_INEN_SET              ((volatile uint32_t *)REG_PORTG_INEN_SET)               /* PORTG Port x GPIO Input Enable Set Register */
-#define pREG_PORTG_INEN_CLR              ((volatile uint32_t *)REG_PORTG_INEN_CLR)               /* PORTG Port x GPIO Input Enable Clear Register */
-#define pREG_PORTG_MUX                   ((volatile uint32_t *)REG_PORTG_MUX)                    /* PORTG Port x Multiplexer Control Register */
-#define pREG_PORTG_DATA_TGL              ((volatile uint32_t *)REG_PORTG_DATA_TGL)               /* PORTG Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTG_POL                   ((volatile uint32_t *)REG_PORTG_POL)                    /* PORTG Port x GPIO Polarity Invert Register */
-#define pREG_PORTG_POL_SET               ((volatile uint32_t *)REG_PORTG_POL_SET)                /* PORTG Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTG_POL_CLR               ((volatile uint32_t *)REG_PORTG_POL_CLR)                /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTG_LOCK                  ((volatile uint32_t *)REG_PORTG_LOCK)                   /* PORTG Port x GPIO Lock Register */
-#define pREG_PORTG_REVID                 ((volatile uint32_t *)REG_PORTG_REVID)                  /* PORTG Port x GPIO Revision ID */
-
-
-/* =========================================================================
-       PADS0
-   ========================================================================= */
-#define pREG_PADS0_EMAC_PTP_CLKSEL       ((volatile uint32_t *)REG_PADS0_EMAC_PTP_CLKSEL)        /* PADS0 Clock Selection for EMAC and PTP */
-#define pREG_PADS0_TWI_VSEL              ((volatile uint32_t *)REG_PADS0_TWI_VSEL)               /* PADS0 TWI Voltage Selection */
-#define pREG_PADS0_PORTS_HYST            ((volatile uint32_t *)REG_PADS0_PORTS_HYST)             /* PADS0 Hysteresis Enable Register */
-
-
-/* =========================================================================
-       PINT0
-   ========================================================================= */
-#define pREG_PINT0_MSK_SET               ((volatile uint32_t *)REG_PINT0_MSK_SET)                /* PINT0 Pint Mask Set Register */
-#define pREG_PINT0_MSK_CLR               ((volatile uint32_t *)REG_PINT0_MSK_CLR)                /* PINT0 Pint Mask Clear Register */
-#define pREG_PINT0_REQ                   ((volatile uint32_t *)REG_PINT0_REQ)                    /* PINT0 Pint Request Register */
-#define pREG_PINT0_ASSIGN                ((volatile uint32_t *)REG_PINT0_ASSIGN)                 /* PINT0 Pint Assign Register */
-#define pREG_PINT0_EDGE_SET              ((volatile uint32_t *)REG_PINT0_EDGE_SET)               /* PINT0 Pint Edge Set Register */
-#define pREG_PINT0_EDGE_CLR              ((volatile uint32_t *)REG_PINT0_EDGE_CLR)               /* PINT0 Pint Edge Clear Register */
-#define pREG_PINT0_INV_SET               ((volatile uint32_t *)REG_PINT0_INV_SET)                /* PINT0 Pint Invert Set Register */
-#define pREG_PINT0_INV_CLR               ((volatile uint32_t *)REG_PINT0_INV_CLR)                /* PINT0 Pint Invert Clear Register */
-#define pREG_PINT0_PINSTATE              ((volatile uint32_t *)REG_PINT0_PINSTATE)               /* PINT0 Pint Pinstate Register */
-#define pREG_PINT0_LATCH                 ((volatile uint32_t *)REG_PINT0_LATCH)                  /* PINT0 Pint Latch Register */
-
-/* =========================================================================
-       PINT1
-   ========================================================================= */
-#define pREG_PINT1_MSK_SET               ((volatile uint32_t *)REG_PINT1_MSK_SET)                /* PINT1 Pint Mask Set Register */
-#define pREG_PINT1_MSK_CLR               ((volatile uint32_t *)REG_PINT1_MSK_CLR)                /* PINT1 Pint Mask Clear Register */
-#define pREG_PINT1_REQ                   ((volatile uint32_t *)REG_PINT1_REQ)                    /* PINT1 Pint Request Register */
-#define pREG_PINT1_ASSIGN                ((volatile uint32_t *)REG_PINT1_ASSIGN)                 /* PINT1 Pint Assign Register */
-#define pREG_PINT1_EDGE_SET              ((volatile uint32_t *)REG_PINT1_EDGE_SET)               /* PINT1 Pint Edge Set Register */
-#define pREG_PINT1_EDGE_CLR              ((volatile uint32_t *)REG_PINT1_EDGE_CLR)               /* PINT1 Pint Edge Clear Register */
-#define pREG_PINT1_INV_SET               ((volatile uint32_t *)REG_PINT1_INV_SET)                /* PINT1 Pint Invert Set Register */
-#define pREG_PINT1_INV_CLR               ((volatile uint32_t *)REG_PINT1_INV_CLR)                /* PINT1 Pint Invert Clear Register */
-#define pREG_PINT1_PINSTATE              ((volatile uint32_t *)REG_PINT1_PINSTATE)               /* PINT1 Pint Pinstate Register */
-#define pREG_PINT1_LATCH                 ((volatile uint32_t *)REG_PINT1_LATCH)                  /* PINT1 Pint Latch Register */
-
-/* =========================================================================
-       PINT2
-   ========================================================================= */
-#define pREG_PINT2_MSK_SET               ((volatile uint32_t *)REG_PINT2_MSK_SET)                /* PINT2 Pint Mask Set Register */
-#define pREG_PINT2_MSK_CLR               ((volatile uint32_t *)REG_PINT2_MSK_CLR)                /* PINT2 Pint Mask Clear Register */
-#define pREG_PINT2_REQ                   ((volatile uint32_t *)REG_PINT2_REQ)                    /* PINT2 Pint Request Register */
-#define pREG_PINT2_ASSIGN                ((volatile uint32_t *)REG_PINT2_ASSIGN)                 /* PINT2 Pint Assign Register */
-#define pREG_PINT2_EDGE_SET              ((volatile uint32_t *)REG_PINT2_EDGE_SET)               /* PINT2 Pint Edge Set Register */
-#define pREG_PINT2_EDGE_CLR              ((volatile uint32_t *)REG_PINT2_EDGE_CLR)               /* PINT2 Pint Edge Clear Register */
-#define pREG_PINT2_INV_SET               ((volatile uint32_t *)REG_PINT2_INV_SET)                /* PINT2 Pint Invert Set Register */
-#define pREG_PINT2_INV_CLR               ((volatile uint32_t *)REG_PINT2_INV_CLR)                /* PINT2 Pint Invert Clear Register */
-#define pREG_PINT2_PINSTATE              ((volatile uint32_t *)REG_PINT2_PINSTATE)               /* PINT2 Pint Pinstate Register */
-#define pREG_PINT2_LATCH                 ((volatile uint32_t *)REG_PINT2_LATCH)                  /* PINT2 Pint Latch Register */
-
-/* =========================================================================
-       PINT3
-   ========================================================================= */
-#define pREG_PINT3_MSK_SET               ((volatile uint32_t *)REG_PINT3_MSK_SET)                /* PINT3 Pint Mask Set Register */
-#define pREG_PINT3_MSK_CLR               ((volatile uint32_t *)REG_PINT3_MSK_CLR)                /* PINT3 Pint Mask Clear Register */
-#define pREG_PINT3_REQ                   ((volatile uint32_t *)REG_PINT3_REQ)                    /* PINT3 Pint Request Register */
-#define pREG_PINT3_ASSIGN                ((volatile uint32_t *)REG_PINT3_ASSIGN)                 /* PINT3 Pint Assign Register */
-#define pREG_PINT3_EDGE_SET              ((volatile uint32_t *)REG_PINT3_EDGE_SET)               /* PINT3 Pint Edge Set Register */
-#define pREG_PINT3_EDGE_CLR              ((volatile uint32_t *)REG_PINT3_EDGE_CLR)               /* PINT3 Pint Edge Clear Register */
-#define pREG_PINT3_INV_SET               ((volatile uint32_t *)REG_PINT3_INV_SET)                /* PINT3 Pint Invert Set Register */
-#define pREG_PINT3_INV_CLR               ((volatile uint32_t *)REG_PINT3_INV_CLR)                /* PINT3 Pint Invert Clear Register */
-#define pREG_PINT3_PINSTATE              ((volatile uint32_t *)REG_PINT3_PINSTATE)               /* PINT3 Pint Pinstate Register */
-#define pREG_PINT3_LATCH                 ((volatile uint32_t *)REG_PINT3_LATCH)                  /* PINT3 Pint Latch Register */
-
-/* =========================================================================
-       PINT4
-   ========================================================================= */
-#define pREG_PINT4_MSK_SET               ((volatile uint32_t *)REG_PINT4_MSK_SET)                /* PINT4 Pint Mask Set Register */
-#define pREG_PINT4_MSK_CLR               ((volatile uint32_t *)REG_PINT4_MSK_CLR)                /* PINT4 Pint Mask Clear Register */
-#define pREG_PINT4_REQ                   ((volatile uint32_t *)REG_PINT4_REQ)                    /* PINT4 Pint Request Register */
-#define pREG_PINT4_ASSIGN                ((volatile uint32_t *)REG_PINT4_ASSIGN)                 /* PINT4 Pint Assign Register */
-#define pREG_PINT4_EDGE_SET              ((volatile uint32_t *)REG_PINT4_EDGE_SET)               /* PINT4 Pint Edge Set Register */
-#define pREG_PINT4_EDGE_CLR              ((volatile uint32_t *)REG_PINT4_EDGE_CLR)               /* PINT4 Pint Edge Clear Register */
-#define pREG_PINT4_INV_SET               ((volatile uint32_t *)REG_PINT4_INV_SET)                /* PINT4 Pint Invert Set Register */
-#define pREG_PINT4_INV_CLR               ((volatile uint32_t *)REG_PINT4_INV_CLR)                /* PINT4 Pint Invert Clear Register */
-#define pREG_PINT4_PINSTATE              ((volatile uint32_t *)REG_PINT4_PINSTATE)               /* PINT4 Pint Pinstate Register */
-#define pREG_PINT4_LATCH                 ((volatile uint32_t *)REG_PINT4_LATCH)                  /* PINT4 Pint Latch Register */
-
-/* =========================================================================
-       PINT5
-   ========================================================================= */
-#define pREG_PINT5_MSK_SET               ((volatile uint32_t *)REG_PINT5_MSK_SET)                /* PINT5 Pint Mask Set Register */
-#define pREG_PINT5_MSK_CLR               ((volatile uint32_t *)REG_PINT5_MSK_CLR)                /* PINT5 Pint Mask Clear Register */
-#define pREG_PINT5_REQ                   ((volatile uint32_t *)REG_PINT5_REQ)                    /* PINT5 Pint Request Register */
-#define pREG_PINT5_ASSIGN                ((volatile uint32_t *)REG_PINT5_ASSIGN)                 /* PINT5 Pint Assign Register */
-#define pREG_PINT5_EDGE_SET              ((volatile uint32_t *)REG_PINT5_EDGE_SET)               /* PINT5 Pint Edge Set Register */
-#define pREG_PINT5_EDGE_CLR              ((volatile uint32_t *)REG_PINT5_EDGE_CLR)               /* PINT5 Pint Edge Clear Register */
-#define pREG_PINT5_INV_SET               ((volatile uint32_t *)REG_PINT5_INV_SET)                /* PINT5 Pint Invert Set Register */
-#define pREG_PINT5_INV_CLR               ((volatile uint32_t *)REG_PINT5_INV_CLR)                /* PINT5 Pint Invert Clear Register */
-#define pREG_PINT5_PINSTATE              ((volatile uint32_t *)REG_PINT5_PINSTATE)               /* PINT5 Pint Pinstate Register */
-#define pREG_PINT5_LATCH                 ((volatile uint32_t *)REG_PINT5_LATCH)                  /* PINT5 Pint Latch Register */
-
-
-/* =========================================================================
-       SMC0
-   ========================================================================= */
-#define pREG_SMC0_GCTL                   ((volatile uint32_t *)REG_SMC0_GCTL)                    /* SMC0 Grant Control Register */
-#define pREG_SMC0_GSTAT                  ((volatile uint32_t *)REG_SMC0_GSTAT)                   /* SMC0 Grant Status Register */
-#define pREG_SMC0_B0CTL                  ((volatile uint32_t *)REG_SMC0_B0CTL)                   /* SMC0 Bank 0 Control Register */
-#define pREG_SMC0_B0TIM                  ((volatile uint32_t *)REG_SMC0_B0TIM)                   /* SMC0 Bank 0 Timing Register */
-#define pREG_SMC0_B0ETIM                 ((volatile uint32_t *)REG_SMC0_B0ETIM)                  /* SMC0 Bank 0 Extended Timing Register */
-#define pREG_SMC0_B1CTL                  ((volatile uint32_t *)REG_SMC0_B1CTL)                   /* SMC0 Bank 1 Control Register */
-#define pREG_SMC0_B1TIM                  ((volatile uint32_t *)REG_SMC0_B1TIM)                   /* SMC0 Bank 1 Timing Register */
-#define pREG_SMC0_B1ETIM                 ((volatile uint32_t *)REG_SMC0_B1ETIM)                  /* SMC0 Bank 1 Extended Timing Register */
-#define pREG_SMC0_B2CTL                  ((volatile uint32_t *)REG_SMC0_B2CTL)                   /* SMC0 Bank 2 Control Register */
-#define pREG_SMC0_B2TIM                  ((volatile uint32_t *)REG_SMC0_B2TIM)                   /* SMC0 Bank 2 Timing Register */
-#define pREG_SMC0_B2ETIM                 ((volatile uint32_t *)REG_SMC0_B2ETIM)                  /* SMC0 Bank 2 Extended Timing Register */
-#define pREG_SMC0_B3CTL                  ((volatile uint32_t *)REG_SMC0_B3CTL)                   /* SMC0 Bank 3 Control Register */
-#define pREG_SMC0_B3TIM                  ((volatile uint32_t *)REG_SMC0_B3TIM)                   /* SMC0 Bank 3 Timing Register */
-#define pREG_SMC0_B3ETIM                 ((volatile uint32_t *)REG_SMC0_B3ETIM)                  /* SMC0 Bank 3 Extended Timing Register */
-
-
-/* =========================================================================
-       WDOG0
-   ========================================================================= */
-#define pREG_WDOG0_CTL                   ((volatile uint32_t *)REG_WDOG0_CTL)                    /* WDOG0 Control Register */
-#define pREG_WDOG0_CNT                   ((volatile uint32_t *)REG_WDOG0_CNT)                    /* WDOG0 Count Register */
-#define pREG_WDOG0_STAT                  ((volatile uint32_t *)REG_WDOG0_STAT)                   /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================================================================
-       WDOG1
-   ========================================================================= */
-#define pREG_WDOG1_CTL                   ((volatile uint32_t *)REG_WDOG1_CTL)                    /* WDOG1 Control Register */
-#define pREG_WDOG1_CNT                   ((volatile uint32_t *)REG_WDOG1_CNT)                    /* WDOG1 Count Register */
-#define pREG_WDOG1_STAT                  ((volatile uint32_t *)REG_WDOG1_STAT)                   /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================================================================
-       EPPI0
-   ========================================================================= */
-#define pREG_EPPI0_STAT                  ((volatile uint32_t *)REG_EPPI0_STAT)                   /* EPPI0 Status Register */
-#define pREG_EPPI0_HCNT                  ((volatile uint32_t *)REG_EPPI0_HCNT)                   /* EPPI0 Horizontal Transfer Count Register */
-#define pREG_EPPI0_HDLY                  ((volatile uint32_t *)REG_EPPI0_HDLY)                   /* EPPI0 Horizontal Delay Count Register */
-#define pREG_EPPI0_VCNT                  ((volatile uint32_t *)REG_EPPI0_VCNT)                   /* EPPI0 Vertical Transfer Count Register */
-#define pREG_EPPI0_VDLY                  ((volatile uint32_t *)REG_EPPI0_VDLY)                   /* EPPI0 Vertical Delay Count Register */
-#define pREG_EPPI0_FRAME                 ((volatile uint32_t *)REG_EPPI0_FRAME)                  /* EPPI0 Lines Per Frame Register */
-#define pREG_EPPI0_LINE                  ((volatile uint32_t *)REG_EPPI0_LINE)                   /* EPPI0 Samples Per Line Register */
-#define pREG_EPPI0_CLKDIV                ((volatile uint32_t *)REG_EPPI0_CLKDIV)                 /* EPPI0 Clock Divide Register */
-#define pREG_EPPI0_CTL                   ((volatile uint32_t *)REG_EPPI0_CTL)                    /* EPPI0 Control Register */
-#define pREG_EPPI0_FS1_WLHB              ((volatile uint32_t *)REG_EPPI0_FS1_WLHB)               /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI0_FS1_PASPL             ((volatile uint32_t *)REG_EPPI0_FS1_PASPL)              /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI0_FS2_WLVB              ((volatile uint32_t *)REG_EPPI0_FS2_WLVB)               /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI0_FS2_PALPF             ((volatile uint32_t *)REG_EPPI0_FS2_PALPF)              /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI0_IMSK                  ((volatile uint32_t *)REG_EPPI0_IMSK)                   /* EPPI0 Interrupt Mask Register */
-#define pREG_EPPI0_ODDCLIP               ((volatile uint32_t *)REG_EPPI0_ODDCLIP)                /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI0_EVENCLIP              ((volatile uint32_t *)REG_EPPI0_EVENCLIP)               /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI0_FS1_DLY               ((volatile uint32_t *)REG_EPPI0_FS1_DLY)                /* EPPI0 Frame Sync 1 Delay Value */
-#define pREG_EPPI0_FS2_DLY               ((volatile uint32_t *)REG_EPPI0_FS2_DLY)                /* EPPI0 Frame Sync 2 Delay Value */
-#define pREG_EPPI0_CTL2                  ((volatile uint32_t *)REG_EPPI0_CTL2)                   /* EPPI0 Control Register 2 */
-
-/* =========================================================================
-       EPPI1
-   ========================================================================= */
-#define pREG_EPPI1_STAT                  ((volatile uint32_t *)REG_EPPI1_STAT)                   /* EPPI1 Status Register */
-#define pREG_EPPI1_HCNT                  ((volatile uint32_t *)REG_EPPI1_HCNT)                   /* EPPI1 Horizontal Transfer Count Register */
-#define pREG_EPPI1_HDLY                  ((volatile uint32_t *)REG_EPPI1_HDLY)                   /* EPPI1 Horizontal Delay Count Register */
-#define pREG_EPPI1_VCNT                  ((volatile uint32_t *)REG_EPPI1_VCNT)                   /* EPPI1 Vertical Transfer Count Register */
-#define pREG_EPPI1_VDLY                  ((volatile uint32_t *)REG_EPPI1_VDLY)                   /* EPPI1 Vertical Delay Count Register */
-#define pREG_EPPI1_FRAME                 ((volatile uint32_t *)REG_EPPI1_FRAME)                  /* EPPI1 Lines Per Frame Register */
-#define pREG_EPPI1_LINE                  ((volatile uint32_t *)REG_EPPI1_LINE)                   /* EPPI1 Samples Per Line Register */
-#define pREG_EPPI1_CLKDIV                ((volatile uint32_t *)REG_EPPI1_CLKDIV)                 /* EPPI1 Clock Divide Register */
-#define pREG_EPPI1_CTL                   ((volatile uint32_t *)REG_EPPI1_CTL)                    /* EPPI1 Control Register */
-#define pREG_EPPI1_FS1_WLHB              ((volatile uint32_t *)REG_EPPI1_FS1_WLHB)               /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI1_FS1_PASPL             ((volatile uint32_t *)REG_EPPI1_FS1_PASPL)              /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI1_FS2_WLVB              ((volatile uint32_t *)REG_EPPI1_FS2_WLVB)               /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI1_FS2_PALPF             ((volatile uint32_t *)REG_EPPI1_FS2_PALPF)              /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI1_IMSK                  ((volatile uint32_t *)REG_EPPI1_IMSK)                   /* EPPI1 Interrupt Mask Register */
-#define pREG_EPPI1_ODDCLIP               ((volatile uint32_t *)REG_EPPI1_ODDCLIP)                /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI1_EVENCLIP              ((volatile uint32_t *)REG_EPPI1_EVENCLIP)               /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI1_FS1_DLY               ((volatile uint32_t *)REG_EPPI1_FS1_DLY)                /* EPPI1 Frame Sync 1 Delay Value */
-#define pREG_EPPI1_FS2_DLY               ((volatile uint32_t *)REG_EPPI1_FS2_DLY)                /* EPPI1 Frame Sync 2 Delay Value */
-#define pREG_EPPI1_CTL2                  ((volatile uint32_t *)REG_EPPI1_CTL2)                   /* EPPI1 Control Register 2 */
-
-/* =========================================================================
-       EPPI2
-   ========================================================================= */
-#define pREG_EPPI2_STAT                  ((volatile uint32_t *)REG_EPPI2_STAT)                   /* EPPI2 Status Register */
-#define pREG_EPPI2_HCNT                  ((volatile uint32_t *)REG_EPPI2_HCNT)                   /* EPPI2 Horizontal Transfer Count Register */
-#define pREG_EPPI2_HDLY                  ((volatile uint32_t *)REG_EPPI2_HDLY)                   /* EPPI2 Horizontal Delay Count Register */
-#define pREG_EPPI2_VCNT                  ((volatile uint32_t *)REG_EPPI2_VCNT)                   /* EPPI2 Vertical Transfer Count Register */
-#define pREG_EPPI2_VDLY                  ((volatile uint32_t *)REG_EPPI2_VDLY)                   /* EPPI2 Vertical Delay Count Register */
-#define pREG_EPPI2_FRAME                 ((volatile uint32_t *)REG_EPPI2_FRAME)                  /* EPPI2 Lines Per Frame Register */
-#define pREG_EPPI2_LINE                  ((volatile uint32_t *)REG_EPPI2_LINE)                   /* EPPI2 Samples Per Line Register */
-#define pREG_EPPI2_CLKDIV                ((volatile uint32_t *)REG_EPPI2_CLKDIV)                 /* EPPI2 Clock Divide Register */
-#define pREG_EPPI2_CTL                   ((volatile uint32_t *)REG_EPPI2_CTL)                    /* EPPI2 Control Register */
-#define pREG_EPPI2_FS1_WLHB              ((volatile uint32_t *)REG_EPPI2_FS1_WLHB)               /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI2_FS1_PASPL             ((volatile uint32_t *)REG_EPPI2_FS1_PASPL)              /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI2_FS2_WLVB              ((volatile uint32_t *)REG_EPPI2_FS2_WLVB)               /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI2_FS2_PALPF             ((volatile uint32_t *)REG_EPPI2_FS2_PALPF)              /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI2_IMSK                  ((volatile uint32_t *)REG_EPPI2_IMSK)                   /* EPPI2 Interrupt Mask Register */
-#define pREG_EPPI2_ODDCLIP               ((volatile uint32_t *)REG_EPPI2_ODDCLIP)                /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI2_EVENCLIP              ((volatile uint32_t *)REG_EPPI2_EVENCLIP)               /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI2_FS1_DLY               ((volatile uint32_t *)REG_EPPI2_FS1_DLY)                /* EPPI2 Frame Sync 1 Delay Value */
-#define pREG_EPPI2_FS2_DLY               ((volatile uint32_t *)REG_EPPI2_FS2_DLY)                /* EPPI2 Frame Sync 2 Delay Value */
-#define pREG_EPPI2_CTL2                  ((volatile uint32_t *)REG_EPPI2_CTL2)                   /* EPPI2 Control Register 2 */
-
-
-/* =========================================================================
-       PWM0
-   ========================================================================= */
-#define pREG_PWM0_CTL                    ((volatile uint32_t *)REG_PWM0_CTL)                     /* PWM0 Control Register */
-#define pREG_PWM0_CHANCFG                ((volatile uint32_t *)REG_PWM0_CHANCFG)                 /* PWM0 Channel Config Register */
-#define pREG_PWM0_TRIPCFG                ((volatile uint32_t *)REG_PWM0_TRIPCFG)                 /* PWM0 Trip Config Register */
-#define pREG_PWM0_STAT                   ((volatile uint32_t *)REG_PWM0_STAT)                    /* PWM0 Status Register */
-#define pREG_PWM0_IMSK                   ((volatile uint32_t *)REG_PWM0_IMSK)                    /* PWM0 Interrupt Mask Register */
-#define pREG_PWM0_ILAT                   ((volatile uint32_t *)REG_PWM0_ILAT)                    /* PWM0 Interrupt Latch Register */
-#define pREG_PWM0_CHOPCFG                ((volatile uint32_t *)REG_PWM0_CHOPCFG)                 /* PWM0 Chop Configuration Register */
-#define pREG_PWM0_DT                     ((volatile uint32_t *)REG_PWM0_DT)                      /* PWM0 Dead Time Register */
-#define pREG_PWM0_SYNC_WID               ((volatile uint32_t *)REG_PWM0_SYNC_WID)                /* PWM0 Sync Pulse Width Register */
-#define pREG_PWM0_TM0                    ((volatile uint32_t *)REG_PWM0_TM0)                     /* PWM0 Timer 0 Period Register */
-#define pREG_PWM0_TM1                    ((volatile uint32_t *)REG_PWM0_TM1)                     /* PWM0 Timer 1 Period Register */
-#define pREG_PWM0_TM2                    ((volatile uint32_t *)REG_PWM0_TM2)                     /* PWM0 Timer 2 Period Register */
-#define pREG_PWM0_TM3                    ((volatile uint32_t *)REG_PWM0_TM3)                     /* PWM0 Timer 3 Period Register */
-#define pREG_PWM0_TM4                    ((volatile uint32_t *)REG_PWM0_TM4)                     /* PWM0 Timer 4 Period Register */
-#define pREG_PWM0_DLYA                   ((volatile uint32_t *)REG_PWM0_DLYA)                    /* PWM0 Channel A Delay Register */
-#define pREG_PWM0_DLYB                   ((volatile uint32_t *)REG_PWM0_DLYB)                    /* PWM0 Channel B Delay Register */
-#define pREG_PWM0_DLYC                   ((volatile uint32_t *)REG_PWM0_DLYC)                    /* PWM0 Channel C Delay Register */
-#define pREG_PWM0_DLYD                   ((volatile uint32_t *)REG_PWM0_DLYD)                    /* PWM0 Channel D Delay Register */
-#define pREG_PWM0_ACTL                   ((volatile uint32_t *)REG_PWM0_ACTL)                    /* PWM0 Channel A Control Register */
-#define pREG_PWM0_AH0                    ((volatile uint32_t *)REG_PWM0_AH0)                     /* PWM0 Channel A-High Duty-0 Register */
-#define pREG_PWM0_AH1                    ((volatile uint32_t *)REG_PWM0_AH1)                     /* PWM0 Channel A-High Duty-1 Register */
-#define pREG_PWM0_AL0                    ((volatile uint32_t *)REG_PWM0_AL0)                     /* PWM0 Channel A-Low Duty-0 Register */
-#define pREG_PWM0_AL1                    ((volatile uint32_t *)REG_PWM0_AL1)                     /* PWM0 Channel A-Low Duty-1 Register */
-#define pREG_PWM0_BCTL                   ((volatile uint32_t *)REG_PWM0_BCTL)                    /* PWM0 Channel B Control Register */
-#define pREG_PWM0_BH0                    ((volatile uint32_t *)REG_PWM0_BH0)                     /* PWM0 Channel B-High Duty-0 Register */
-#define pREG_PWM0_BH1                    ((volatile uint32_t *)REG_PWM0_BH1)                     /* PWM0 Channel B-High Duty-1 Register */
-#define pREG_PWM0_BL0                    ((volatile uint32_t *)REG_PWM0_BL0)                     /* PWM0 Channel B-Low Duty-0 Register */
-#define pREG_PWM0_BL1                    ((volatile uint32_t *)REG_PWM0_BL1)                     /* PWM0 Channel B-Low Duty-1 Register */
-#define pREG_PWM0_CCTL                   ((volatile uint32_t *)REG_PWM0_CCTL)                    /* PWM0 Channel C Control Register */
-#define pREG_PWM0_CH0                    ((volatile uint32_t *)REG_PWM0_CH0)                     /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM0_CH1                    ((volatile uint32_t *)REG_PWM0_CH1)                     /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM0_CL0                    ((volatile uint32_t *)REG_PWM0_CL0)                     /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM0_CL1                    ((volatile uint32_t *)REG_PWM0_CL1)                     /* PWM0 Channel C-Low Duty-1 Register */
-#define pREG_PWM0_DCTL                   ((volatile uint32_t *)REG_PWM0_DCTL)                    /* PWM0 Channel D Control Register */
-#define pREG_PWM0_DH0                    ((volatile uint32_t *)REG_PWM0_DH0)                     /* PWM0 Channel D-High Duty-0 Register */
-#define pREG_PWM0_DH1                    ((volatile uint32_t *)REG_PWM0_DH1)                     /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM0_DL0                    ((volatile uint32_t *)REG_PWM0_DL0)                     /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM0_DL1                    ((volatile uint32_t *)REG_PWM0_DL1)                     /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================================================================
-       PWM1
-   ========================================================================= */
-#define pREG_PWM1_CTL                    ((volatile uint32_t *)REG_PWM1_CTL)                     /* PWM1 Control Register */
-#define pREG_PWM1_CHANCFG                ((volatile uint32_t *)REG_PWM1_CHANCFG)                 /* PWM1 Channel Config Register */
-#define pREG_PWM1_TRIPCFG                ((volatile uint32_t *)REG_PWM1_TRIPCFG)                 /* PWM1 Trip Config Register */
-#define pREG_PWM1_STAT                   ((volatile uint32_t *)REG_PWM1_STAT)                    /* PWM1 Status Register */
-#define pREG_PWM1_IMSK                   ((volatile uint32_t *)REG_PWM1_IMSK)                    /* PWM1 Interrupt Mask Register */
-#define pREG_PWM1_ILAT                   ((volatile uint32_t *)REG_PWM1_ILAT)                    /* PWM1 Interrupt Latch Register */
-#define pREG_PWM1_CHOPCFG                ((volatile uint32_t *)REG_PWM1_CHOPCFG)                 /* PWM1 Chop Configuration Register */
-#define pREG_PWM1_DT                     ((volatile uint32_t *)REG_PWM1_DT)                      /* PWM1 Dead Time Register */
-#define pREG_PWM1_SYNC_WID               ((volatile uint32_t *)REG_PWM1_SYNC_WID)                /* PWM1 Sync Pulse Width Register */
-#define pREG_PWM1_TM0                    ((volatile uint32_t *)REG_PWM1_TM0)                     /* PWM1 Timer 0 Period Register */
-#define pREG_PWM1_TM1                    ((volatile uint32_t *)REG_PWM1_TM1)                     /* PWM1 Timer 1 Period Register */
-#define pREG_PWM1_TM2                    ((volatile uint32_t *)REG_PWM1_TM2)                     /* PWM1 Timer 2 Period Register */
-#define pREG_PWM1_TM3                    ((volatile uint32_t *)REG_PWM1_TM3)                     /* PWM1 Timer 3 Period Register */
-#define pREG_PWM1_TM4                    ((volatile uint32_t *)REG_PWM1_TM4)                     /* PWM1 Timer 4 Period Register */
-#define pREG_PWM1_DLYA                   ((volatile uint32_t *)REG_PWM1_DLYA)                    /* PWM1 Channel A Delay Register */
-#define pREG_PWM1_DLYB                   ((volatile uint32_t *)REG_PWM1_DLYB)                    /* PWM1 Channel B Delay Register */
-#define pREG_PWM1_DLYC                   ((volatile uint32_t *)REG_PWM1_DLYC)                    /* PWM1 Channel C Delay Register */
-#define pREG_PWM1_DLYD                   ((volatile uint32_t *)REG_PWM1_DLYD)                    /* PWM1 Channel D Delay Register */
-#define pREG_PWM1_ACTL                   ((volatile uint32_t *)REG_PWM1_ACTL)                    /* PWM1 Channel A Control Register */
-#define pREG_PWM1_AH0                    ((volatile uint32_t *)REG_PWM1_AH0)                     /* PWM1 Channel A-High Duty-0 Register */
-#define pREG_PWM1_AH1                    ((volatile uint32_t *)REG_PWM1_AH1)                     /* PWM1 Channel A-High Duty-1 Register */
-#define pREG_PWM1_AL0                    ((volatile uint32_t *)REG_PWM1_AL0)                     /* PWM1 Channel A-Low Duty-0 Register */
-#define pREG_PWM1_AL1                    ((volatile uint32_t *)REG_PWM1_AL1)                     /* PWM1 Channel A-Low Duty-1 Register */
-#define pREG_PWM1_BCTL                   ((volatile uint32_t *)REG_PWM1_BCTL)                    /* PWM1 Channel B Control Register */
-#define pREG_PWM1_BH0                    ((volatile uint32_t *)REG_PWM1_BH0)                     /* PWM1 Channel B-High Duty-0 Register */
-#define pREG_PWM1_BH1                    ((volatile uint32_t *)REG_PWM1_BH1)                     /* PWM1 Channel B-High Duty-1 Register */
-#define pREG_PWM1_BL0                    ((volatile uint32_t *)REG_PWM1_BL0)                     /* PWM1 Channel B-Low Duty-0 Register */
-#define pREG_PWM1_BL1                    ((volatile uint32_t *)REG_PWM1_BL1)                     /* PWM1 Channel B-Low Duty-1 Register */
-#define pREG_PWM1_CCTL                   ((volatile uint32_t *)REG_PWM1_CCTL)                    /* PWM1 Channel C Control Register */
-#define pREG_PWM1_CH0                    ((volatile uint32_t *)REG_PWM1_CH0)                     /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM1_CH1                    ((volatile uint32_t *)REG_PWM1_CH1)                     /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM1_CL0                    ((volatile uint32_t *)REG_PWM1_CL0)                     /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM1_CL1                    ((volatile uint32_t *)REG_PWM1_CL1)                     /* PWM1 Channel C-Low Duty-1 Register */
-#define pREG_PWM1_DCTL                   ((volatile uint32_t *)REG_PWM1_DCTL)                    /* PWM1 Channel D Control Register */
-#define pREG_PWM1_DH0                    ((volatile uint32_t *)REG_PWM1_DH0)                     /* PWM1 Channel D-High Duty-0 Register */
-#define pREG_PWM1_DH1                    ((volatile uint32_t *)REG_PWM1_DH1)                     /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM1_DL0                    ((volatile uint32_t *)REG_PWM1_DL0)                     /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM1_DL1                    ((volatile uint32_t *)REG_PWM1_DL1)                     /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-
-/* =========================================================================
-       VID0
-   ========================================================================= */
-#define pREG_VID0_CONN                   ((volatile uint32_t *)REG_VID0_CONN)                    /* VID0 Video Subsystem Connect Register */
-
-
-/* =========================================================================
-       SWU0
-   ========================================================================= */
-#define pREG_SWU0_GCTL                   ((volatile uint32_t *)REG_SWU0_GCTL)                    /* SWU0 Global Control Register */
-#define pREG_SWU0_GSTAT                  ((volatile uint32_t *)REG_SWU0_GSTAT)                   /* SWU0 Global Status Register */
-#define pREG_SWU0_CTL0                   ((volatile uint32_t *)REG_SWU0_CTL0)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL1                   ((volatile uint32_t *)REG_SWU0_CTL1)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL2                   ((volatile uint32_t *)REG_SWU0_CTL2)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL3                   ((volatile uint32_t *)REG_SWU0_CTL3)                    /* SWU0 Control Register n */
-#define pREG_SWU0_LA0                    ((void * volatile *)REG_SWU0_LA0)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA1                    ((void * volatile *)REG_SWU0_LA1)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA2                    ((void * volatile *)REG_SWU0_LA2)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA3                    ((void * volatile *)REG_SWU0_LA3)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_UA0                    ((void * volatile *)REG_SWU0_UA0)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA1                    ((void * volatile *)REG_SWU0_UA1)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA2                    ((void * volatile *)REG_SWU0_UA2)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA3                    ((void * volatile *)REG_SWU0_UA3)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_ID0                    ((volatile uint32_t *)REG_SWU0_ID0)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID1                    ((volatile uint32_t *)REG_SWU0_ID1)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID2                    ((volatile uint32_t *)REG_SWU0_ID2)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID3                    ((volatile uint32_t *)REG_SWU0_ID3)                     /* SWU0 ID Register n */
-#define pREG_SWU0_CNT0                   ((volatile uint32_t *)REG_SWU0_CNT0)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT1                   ((volatile uint32_t *)REG_SWU0_CNT1)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT2                   ((volatile uint32_t *)REG_SWU0_CNT2)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT3                   ((volatile uint32_t *)REG_SWU0_CNT3)                    /* SWU0 Count Register n */
-#define pREG_SWU0_TARG0                  ((volatile uint32_t *)REG_SWU0_TARG0)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG1                  ((volatile uint32_t *)REG_SWU0_TARG1)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG2                  ((volatile uint32_t *)REG_SWU0_TARG2)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG3                  ((volatile uint32_t *)REG_SWU0_TARG3)                   /* SWU0 Target Register n */
-#define pREG_SWU0_HIST0                  ((volatile uint32_t *)REG_SWU0_HIST0)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST1                  ((volatile uint32_t *)REG_SWU0_HIST1)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST2                  ((volatile uint32_t *)REG_SWU0_HIST2)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST3                  ((volatile uint32_t *)REG_SWU0_HIST3)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_CUR0                   ((volatile uint32_t *)REG_SWU0_CUR0)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR1                   ((volatile uint32_t *)REG_SWU0_CUR1)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR2                   ((volatile uint32_t *)REG_SWU0_CUR2)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR3                   ((volatile uint32_t *)REG_SWU0_CUR3)                    /* SWU0 Current Register n */
-
-/* =========================================================================
-       SWU1
-   ========================================================================= */
-#define pREG_SWU1_GCTL                   ((volatile uint32_t *)REG_SWU1_GCTL)                    /* SWU1 Global Control Register */
-#define pREG_SWU1_GSTAT                  ((volatile uint32_t *)REG_SWU1_GSTAT)                   /* SWU1 Global Status Register */
-#define pREG_SWU1_CTL0                   ((volatile uint32_t *)REG_SWU1_CTL0)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL1                   ((volatile uint32_t *)REG_SWU1_CTL1)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL2                   ((volatile uint32_t *)REG_SWU1_CTL2)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL3                   ((volatile uint32_t *)REG_SWU1_CTL3)                    /* SWU1 Control Register n */
-#define pREG_SWU1_LA0                    ((void * volatile *)REG_SWU1_LA0)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA1                    ((void * volatile *)REG_SWU1_LA1)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA2                    ((void * volatile *)REG_SWU1_LA2)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA3                    ((void * volatile *)REG_SWU1_LA3)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_UA0                    ((void * volatile *)REG_SWU1_UA0)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA1                    ((void * volatile *)REG_SWU1_UA1)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA2                    ((void * volatile *)REG_SWU1_UA2)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA3                    ((void * volatile *)REG_SWU1_UA3)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_ID0                    ((volatile uint32_t *)REG_SWU1_ID0)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID1                    ((volatile uint32_t *)REG_SWU1_ID1)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID2                    ((volatile uint32_t *)REG_SWU1_ID2)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID3                    ((volatile uint32_t *)REG_SWU1_ID3)                     /* SWU1 ID Register n */
-#define pREG_SWU1_CNT0                   ((volatile uint32_t *)REG_SWU1_CNT0)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT1                   ((volatile uint32_t *)REG_SWU1_CNT1)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT2                   ((volatile uint32_t *)REG_SWU1_CNT2)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT3                   ((volatile uint32_t *)REG_SWU1_CNT3)                    /* SWU1 Count Register n */
-#define pREG_SWU1_TARG0                  ((volatile uint32_t *)REG_SWU1_TARG0)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG1                  ((volatile uint32_t *)REG_SWU1_TARG1)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG2                  ((volatile uint32_t *)REG_SWU1_TARG2)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG3                  ((volatile uint32_t *)REG_SWU1_TARG3)                   /* SWU1 Target Register n */
-#define pREG_SWU1_HIST0                  ((volatile uint32_t *)REG_SWU1_HIST0)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST1                  ((volatile uint32_t *)REG_SWU1_HIST1)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST2                  ((volatile uint32_t *)REG_SWU1_HIST2)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST3                  ((volatile uint32_t *)REG_SWU1_HIST3)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_CUR0                   ((volatile uint32_t *)REG_SWU1_CUR0)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR1                   ((volatile uint32_t *)REG_SWU1_CUR1)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR2                   ((volatile uint32_t *)REG_SWU1_CUR2)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR3                   ((volatile uint32_t *)REG_SWU1_CUR3)                    /* SWU1 Current Register n */
-
-/* =========================================================================
-       SWU2
-   ========================================================================= */
-#define pREG_SWU2_GCTL                   ((volatile uint32_t *)REG_SWU2_GCTL)                    /* SWU2 Global Control Register */
-#define pREG_SWU2_GSTAT                  ((volatile uint32_t *)REG_SWU2_GSTAT)                   /* SWU2 Global Status Register */
-#define pREG_SWU2_CTL0                   ((volatile uint32_t *)REG_SWU2_CTL0)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL1                   ((volatile uint32_t *)REG_SWU2_CTL1)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL2                   ((volatile uint32_t *)REG_SWU2_CTL2)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL3                   ((volatile uint32_t *)REG_SWU2_CTL3)                    /* SWU2 Control Register n */
-#define pREG_SWU2_LA0                    ((void * volatile *)REG_SWU2_LA0)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA1                    ((void * volatile *)REG_SWU2_LA1)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA2                    ((void * volatile *)REG_SWU2_LA2)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA3                    ((void * volatile *)REG_SWU2_LA3)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_UA0                    ((void * volatile *)REG_SWU2_UA0)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA1                    ((void * volatile *)REG_SWU2_UA1)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA2                    ((void * volatile *)REG_SWU2_UA2)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA3                    ((void * volatile *)REG_SWU2_UA3)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_ID0                    ((volatile uint32_t *)REG_SWU2_ID0)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID1                    ((volatile uint32_t *)REG_SWU2_ID1)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID2                    ((volatile uint32_t *)REG_SWU2_ID2)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID3                    ((volatile uint32_t *)REG_SWU2_ID3)                     /* SWU2 ID Register n */
-#define pREG_SWU2_CNT0                   ((volatile uint32_t *)REG_SWU2_CNT0)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT1                   ((volatile uint32_t *)REG_SWU2_CNT1)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT2                   ((volatile uint32_t *)REG_SWU2_CNT2)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT3                   ((volatile uint32_t *)REG_SWU2_CNT3)                    /* SWU2 Count Register n */
-#define pREG_SWU2_TARG0                  ((volatile uint32_t *)REG_SWU2_TARG0)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG1                  ((volatile uint32_t *)REG_SWU2_TARG1)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG2                  ((volatile uint32_t *)REG_SWU2_TARG2)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG3                  ((volatile uint32_t *)REG_SWU2_TARG3)                   /* SWU2 Target Register n */
-#define pREG_SWU2_HIST0                  ((volatile uint32_t *)REG_SWU2_HIST0)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST1                  ((volatile uint32_t *)REG_SWU2_HIST1)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST2                  ((volatile uint32_t *)REG_SWU2_HIST2)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST3                  ((volatile uint32_t *)REG_SWU2_HIST3)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_CUR0                   ((volatile uint32_t *)REG_SWU2_CUR0)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR1                   ((volatile uint32_t *)REG_SWU2_CUR1)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR2                   ((volatile uint32_t *)REG_SWU2_CUR2)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR3                   ((volatile uint32_t *)REG_SWU2_CUR3)                    /* SWU2 Current Register n */
-
-/* =========================================================================
-       SWU3
-   ========================================================================= */
-#define pREG_SWU3_GCTL                   ((volatile uint32_t *)REG_SWU3_GCTL)                    /* SWU3 Global Control Register */
-#define pREG_SWU3_GSTAT                  ((volatile uint32_t *)REG_SWU3_GSTAT)                   /* SWU3 Global Status Register */
-#define pREG_SWU3_CTL0                   ((volatile uint32_t *)REG_SWU3_CTL0)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL1                   ((volatile uint32_t *)REG_SWU3_CTL1)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL2                   ((volatile uint32_t *)REG_SWU3_CTL2)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL3                   ((volatile uint32_t *)REG_SWU3_CTL3)                    /* SWU3 Control Register n */
-#define pREG_SWU3_LA0                    ((void * volatile *)REG_SWU3_LA0)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA1                    ((void * volatile *)REG_SWU3_LA1)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA2                    ((void * volatile *)REG_SWU3_LA2)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA3                    ((void * volatile *)REG_SWU3_LA3)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_UA0                    ((void * volatile *)REG_SWU3_UA0)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA1                    ((void * volatile *)REG_SWU3_UA1)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA2                    ((void * volatile *)REG_SWU3_UA2)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA3                    ((void * volatile *)REG_SWU3_UA3)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_ID0                    ((volatile uint32_t *)REG_SWU3_ID0)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID1                    ((volatile uint32_t *)REG_SWU3_ID1)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID2                    ((volatile uint32_t *)REG_SWU3_ID2)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID3                    ((volatile uint32_t *)REG_SWU3_ID3)                     /* SWU3 ID Register n */
-#define pREG_SWU3_CNT0                   ((volatile uint32_t *)REG_SWU3_CNT0)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT1                   ((volatile uint32_t *)REG_SWU3_CNT1)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT2                   ((volatile uint32_t *)REG_SWU3_CNT2)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT3                   ((volatile uint32_t *)REG_SWU3_CNT3)                    /* SWU3 Count Register n */
-#define pREG_SWU3_TARG0                  ((volatile uint32_t *)REG_SWU3_TARG0)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG1                  ((volatile uint32_t *)REG_SWU3_TARG1)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG2                  ((volatile uint32_t *)REG_SWU3_TARG2)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG3                  ((volatile uint32_t *)REG_SWU3_TARG3)                   /* SWU3 Target Register n */
-#define pREG_SWU3_HIST0                  ((volatile uint32_t *)REG_SWU3_HIST0)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST1                  ((volatile uint32_t *)REG_SWU3_HIST1)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST2                  ((volatile uint32_t *)REG_SWU3_HIST2)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST3                  ((volatile uint32_t *)REG_SWU3_HIST3)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_CUR0                   ((volatile uint32_t *)REG_SWU3_CUR0)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR1                   ((volatile uint32_t *)REG_SWU3_CUR1)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR2                   ((volatile uint32_t *)REG_SWU3_CUR2)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR3                   ((volatile uint32_t *)REG_SWU3_CUR3)                    /* SWU3 Current Register n */
-
-/* =========================================================================
-       SWU4
-   ========================================================================= */
-#define pREG_SWU4_GCTL                   ((volatile uint32_t *)REG_SWU4_GCTL)                    /* SWU4 Global Control Register */
-#define pREG_SWU4_GSTAT                  ((volatile uint32_t *)REG_SWU4_GSTAT)                   /* SWU4 Global Status Register */
-#define pREG_SWU4_CTL0                   ((volatile uint32_t *)REG_SWU4_CTL0)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL1                   ((volatile uint32_t *)REG_SWU4_CTL1)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL2                   ((volatile uint32_t *)REG_SWU4_CTL2)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL3                   ((volatile uint32_t *)REG_SWU4_CTL3)                    /* SWU4 Control Register n */
-#define pREG_SWU4_LA0                    ((void * volatile *)REG_SWU4_LA0)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA1                    ((void * volatile *)REG_SWU4_LA1)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA2                    ((void * volatile *)REG_SWU4_LA2)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA3                    ((void * volatile *)REG_SWU4_LA3)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_UA0                    ((void * volatile *)REG_SWU4_UA0)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA1                    ((void * volatile *)REG_SWU4_UA1)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA2                    ((void * volatile *)REG_SWU4_UA2)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA3                    ((void * volatile *)REG_SWU4_UA3)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_ID0                    ((volatile uint32_t *)REG_SWU4_ID0)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID1                    ((volatile uint32_t *)REG_SWU4_ID1)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID2                    ((volatile uint32_t *)REG_SWU4_ID2)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID3                    ((volatile uint32_t *)REG_SWU4_ID3)                     /* SWU4 ID Register n */
-#define pREG_SWU4_CNT0                   ((volatile uint32_t *)REG_SWU4_CNT0)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT1                   ((volatile uint32_t *)REG_SWU4_CNT1)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT2                   ((volatile uint32_t *)REG_SWU4_CNT2)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT3                   ((volatile uint32_t *)REG_SWU4_CNT3)                    /* SWU4 Count Register n */
-#define pREG_SWU4_TARG0                  ((volatile uint32_t *)REG_SWU4_TARG0)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG1                  ((volatile uint32_t *)REG_SWU4_TARG1)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG2                  ((volatile uint32_t *)REG_SWU4_TARG2)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG3                  ((volatile uint32_t *)REG_SWU4_TARG3)                   /* SWU4 Target Register n */
-#define pREG_SWU4_HIST0                  ((volatile uint32_t *)REG_SWU4_HIST0)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST1                  ((volatile uint32_t *)REG_SWU4_HIST1)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST2                  ((volatile uint32_t *)REG_SWU4_HIST2)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST3                  ((volatile uint32_t *)REG_SWU4_HIST3)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_CUR0                   ((volatile uint32_t *)REG_SWU4_CUR0)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR1                   ((volatile uint32_t *)REG_SWU4_CUR1)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR2                   ((volatile uint32_t *)REG_SWU4_CUR2)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR3                   ((volatile uint32_t *)REG_SWU4_CUR3)                    /* SWU4 Current Register n */
-
-/* =========================================================================
-       SWU5
-   ========================================================================= */
-#define pREG_SWU5_GCTL                   ((volatile uint32_t *)REG_SWU5_GCTL)                    /* SWU5 Global Control Register */
-#define pREG_SWU5_GSTAT                  ((volatile uint32_t *)REG_SWU5_GSTAT)                   /* SWU5 Global Status Register */
-#define pREG_SWU5_CTL0                   ((volatile uint32_t *)REG_SWU5_CTL0)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL1                   ((volatile uint32_t *)REG_SWU5_CTL1)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL2                   ((volatile uint32_t *)REG_SWU5_CTL2)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL3                   ((volatile uint32_t *)REG_SWU5_CTL3)                    /* SWU5 Control Register n */
-#define pREG_SWU5_LA0                    ((void * volatile *)REG_SWU5_LA0)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA1                    ((void * volatile *)REG_SWU5_LA1)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA2                    ((void * volatile *)REG_SWU5_LA2)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA3                    ((void * volatile *)REG_SWU5_LA3)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_UA0                    ((void * volatile *)REG_SWU5_UA0)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA1                    ((void * volatile *)REG_SWU5_UA1)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA2                    ((void * volatile *)REG_SWU5_UA2)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA3                    ((void * volatile *)REG_SWU5_UA3)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_ID0                    ((volatile uint32_t *)REG_SWU5_ID0)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID1                    ((volatile uint32_t *)REG_SWU5_ID1)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID2                    ((volatile uint32_t *)REG_SWU5_ID2)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID3                    ((volatile uint32_t *)REG_SWU5_ID3)                     /* SWU5 ID Register n */
-#define pREG_SWU5_CNT0                   ((volatile uint32_t *)REG_SWU5_CNT0)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT1                   ((volatile uint32_t *)REG_SWU5_CNT1)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT2                   ((volatile uint32_t *)REG_SWU5_CNT2)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT3                   ((volatile uint32_t *)REG_SWU5_CNT3)                    /* SWU5 Count Register n */
-#define pREG_SWU5_TARG0                  ((volatile uint32_t *)REG_SWU5_TARG0)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG1                  ((volatile uint32_t *)REG_SWU5_TARG1)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG2                  ((volatile uint32_t *)REG_SWU5_TARG2)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG3                  ((volatile uint32_t *)REG_SWU5_TARG3)                   /* SWU5 Target Register n */
-#define pREG_SWU5_HIST0                  ((volatile uint32_t *)REG_SWU5_HIST0)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST1                  ((volatile uint32_t *)REG_SWU5_HIST1)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST2                  ((volatile uint32_t *)REG_SWU5_HIST2)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST3                  ((volatile uint32_t *)REG_SWU5_HIST3)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_CUR0                   ((volatile uint32_t *)REG_SWU5_CUR0)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR1                   ((volatile uint32_t *)REG_SWU5_CUR1)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR2                   ((volatile uint32_t *)REG_SWU5_CUR2)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR3                   ((volatile uint32_t *)REG_SWU5_CUR3)                    /* SWU5 Current Register n */
-
-/* =========================================================================
-       SWU6
-   ========================================================================= */
-#define pREG_SWU6_GCTL                   ((volatile uint32_t *)REG_SWU6_GCTL)                    /* SWU6 Global Control Register */
-#define pREG_SWU6_GSTAT                  ((volatile uint32_t *)REG_SWU6_GSTAT)                   /* SWU6 Global Status Register */
-#define pREG_SWU6_CTL0                   ((volatile uint32_t *)REG_SWU6_CTL0)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL1                   ((volatile uint32_t *)REG_SWU6_CTL1)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL2                   ((volatile uint32_t *)REG_SWU6_CTL2)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL3                   ((volatile uint32_t *)REG_SWU6_CTL3)                    /* SWU6 Control Register n */
-#define pREG_SWU6_LA0                    ((void * volatile *)REG_SWU6_LA0)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA1                    ((void * volatile *)REG_SWU6_LA1)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA2                    ((void * volatile *)REG_SWU6_LA2)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA3                    ((void * volatile *)REG_SWU6_LA3)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_UA0                    ((void * volatile *)REG_SWU6_UA0)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA1                    ((void * volatile *)REG_SWU6_UA1)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA2                    ((void * volatile *)REG_SWU6_UA2)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA3                    ((void * volatile *)REG_SWU6_UA3)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_ID0                    ((volatile uint32_t *)REG_SWU6_ID0)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID1                    ((volatile uint32_t *)REG_SWU6_ID1)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID2                    ((volatile uint32_t *)REG_SWU6_ID2)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID3                    ((volatile uint32_t *)REG_SWU6_ID3)                     /* SWU6 ID Register n */
-#define pREG_SWU6_CNT0                   ((volatile uint32_t *)REG_SWU6_CNT0)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT1                   ((volatile uint32_t *)REG_SWU6_CNT1)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT2                   ((volatile uint32_t *)REG_SWU6_CNT2)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT3                   ((volatile uint32_t *)REG_SWU6_CNT3)                    /* SWU6 Count Register n */
-#define pREG_SWU6_TARG0                  ((volatile uint32_t *)REG_SWU6_TARG0)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG1                  ((volatile uint32_t *)REG_SWU6_TARG1)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG2                  ((volatile uint32_t *)REG_SWU6_TARG2)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG3                  ((volatile uint32_t *)REG_SWU6_TARG3)                   /* SWU6 Target Register n */
-#define pREG_SWU6_HIST0                  ((volatile uint32_t *)REG_SWU6_HIST0)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST1                  ((volatile uint32_t *)REG_SWU6_HIST1)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST2                  ((volatile uint32_t *)REG_SWU6_HIST2)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST3                  ((volatile uint32_t *)REG_SWU6_HIST3)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_CUR0                   ((volatile uint32_t *)REG_SWU6_CUR0)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR1                   ((volatile uint32_t *)REG_SWU6_CUR1)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR2                   ((volatile uint32_t *)REG_SWU6_CUR2)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR3                   ((volatile uint32_t *)REG_SWU6_CUR3)                    /* SWU6 Current Register n */
-
-
-/* =========================================================================
-       SDU0
-   ========================================================================= */
-#define pREG_SDU0_IDCODE                 ((volatile uint32_t *)REG_SDU0_IDCODE)                  /* SDU0 ID Code Register */
-#define pREG_SDU0_CTL                    ((volatile uint32_t *)REG_SDU0_CTL)                     /* SDU0 Control Register */
-#define pREG_SDU0_STAT                   ((volatile uint32_t *)REG_SDU0_STAT)                    /* SDU0 Status Register */
-#define pREG_SDU0_MACCTL                 ((volatile uint32_t *)REG_SDU0_MACCTL)                  /* SDU0 Memory Access Control Register */
-#define pREG_SDU0_MACADDR                ((void * volatile *)REG_SDU0_MACADDR)                   /* SDU0 Memory Access Address Register */
-#define pREG_SDU0_MACDATA                ((volatile uint32_t *)REG_SDU0_MACDATA)                 /* SDU0 Memory Access Data Register */
-#define pREG_SDU0_DMARD                  ((volatile uint32_t *)REG_SDU0_DMARD)                   /* SDU0 DMA Read Data Register */
-#define pREG_SDU0_DMAWD                  ((volatile uint32_t *)REG_SDU0_DMAWD)                   /* SDU0 DMA Write Data Register */
-#define pREG_SDU0_MSG                    ((volatile uint32_t *)REG_SDU0_MSG)                     /* SDU0 Message Register */
-#define pREG_SDU0_MSG_SET                ((volatile uint32_t *)REG_SDU0_MSG_SET)                 /* SDU0 Message Set Register */
-#define pREG_SDU0_MSG_CLR                ((volatile uint32_t *)REG_SDU0_MSG_CLR)                 /* SDU0 Message Clear Register */
-#define pREG_SDU0_GHLT                   ((volatile uint32_t *)REG_SDU0_GHLT)                    /* SDU0 Group Halt Register */
-
-
-/* =========================================================================
-       EMAC0
-   ========================================================================= */
-#define pREG_EMAC0_MACCFG                ((volatile uint32_t *)REG_EMAC0_MACCFG)                 /* EMAC0 MAC Configuration Register */
-#define pREG_EMAC0_MACFRMFILT            ((volatile uint32_t *)REG_EMAC0_MACFRMFILT)             /* EMAC0 MAC Rx Frame Filter Register */
-#define pREG_EMAC0_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC0_HASHTBL_HI)             /* EMAC0 Hash Table High Register */
-#define pREG_EMAC0_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC0_HASHTBL_LO)             /* EMAC0 Hash Table Low Register */
-#define pREG_EMAC0_SMI_ADDR              ((volatile uint32_t *)REG_EMAC0_SMI_ADDR)               /* EMAC0 SMI Address Register */
-#define pREG_EMAC0_SMI_DATA              ((volatile uint32_t *)REG_EMAC0_SMI_DATA)               /* EMAC0 SMI Data Register */
-#define pREG_EMAC0_FLOWCTL               ((volatile uint32_t *)REG_EMAC0_FLOWCTL)                /* EMAC0 FLow Control Register */
-#define pREG_EMAC0_VLANTAG               ((volatile uint32_t *)REG_EMAC0_VLANTAG)                /* EMAC0 VLAN Tag Register */
-#define pREG_EMAC0_DBG                   ((volatile uint32_t *)REG_EMAC0_DBG)                    /* EMAC0 Debug Register */
-#define pREG_EMAC0_ISTAT                 ((volatile uint32_t *)REG_EMAC0_ISTAT)                  /* EMAC0 Interrupt Status Register */
-#define pREG_EMAC0_IMSK                  ((volatile uint32_t *)REG_EMAC0_IMSK)                   /* EMAC0 Interrupt Mask Register */
-#define pREG_EMAC0_ADDR0_HI              ((volatile uint32_t *)REG_EMAC0_ADDR0_HI)               /* EMAC0 MAC Address 0 High Register */
-#define pREG_EMAC0_ADDR0_LO              ((volatile uint32_t *)REG_EMAC0_ADDR0_LO)               /* EMAC0 MAC Address 0 Low Register */
-#define pREG_EMAC0_MMC_CTL               ((volatile uint32_t *)REG_EMAC0_MMC_CTL)                /* EMAC0 MMC Control Register */
-#define pREG_EMAC0_MMC_RXINT             ((volatile uint32_t *)REG_EMAC0_MMC_RXINT)              /* EMAC0 MMC Rx Interrupt Register */
-#define pREG_EMAC0_MMC_TXINT             ((volatile uint32_t *)REG_EMAC0_MMC_TXINT)              /* EMAC0 MMC Tx Interrupt Register */
-#define pREG_EMAC0_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_RXIMSK)             /* EMAC0 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC0_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_TXIMSK)             /* EMAC0 MMC TX Interrupt Mask Register */
-#define pREG_EMAC0_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_GB)            /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC0_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_GB)            /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_G)           /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_G)           /* EMAC0 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC0_TX64_GB               ((volatile uint32_t *)REG_EMAC0_TX64_GB)                /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_TX65TO127_GB)           /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_TX128TO255_GB)          /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_TX256TO511_GB)          /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_TX512TO1023_GB)         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_TX1024TOMAX_GB)         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXUCASTFRM_GB)          /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_GB)          /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_GB)          /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC0_TXUNDR_ERR)             /* EMAC0 Tx Underflow Error Register */
-#define pREG_EMAC0_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC0_TXSNGCOL_G)             /* EMAC0 Tx Single Collision (Good) Register */
-#define pREG_EMAC0_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC0_TXMULTCOL_G)            /* EMAC0 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC0_TXDEFERRED            ((volatile uint32_t *)REG_EMAC0_TXDEFERRED)             /* EMAC0 Tx Deferred Register */
-#define pREG_EMAC0_TXLATECOL             ((volatile uint32_t *)REG_EMAC0_TXLATECOL)              /* EMAC0 Tx Late Collision Register */
-#define pREG_EMAC0_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC0_TXEXCESSCOL)            /* EMAC0 Tx Excess Collision Register */
-#define pREG_EMAC0_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC0_TXCARR_ERR)             /* EMAC0 Tx Carrier Error Register */
-#define pREG_EMAC0_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_G)             /* EMAC0 Tx Octet Count (Good) Register */
-#define pREG_EMAC0_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_G)             /* EMAC0 Tx Frame Count (Good) Register */
-#define pREG_EMAC0_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC0_TXEXCESSDEF)            /* EMAC0 Tx Excess Deferral Register */
-#define pREG_EMAC0_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_TXPAUSEFRM)             /* EMAC0 Tx Pause Frame Register */
-#define pREG_EMAC0_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC0_TXVLANFRM_G)            /* EMAC0 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC0_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXFRMCNT_GB)            /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_GB)            /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_G)             /* EMAC0 Rx Octet Count (Good) Register */
-#define pREG_EMAC0_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXBCASTFRM_G)           /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXMCASTFRM_G)           /* EMAC0 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC0_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC0_RXCRC_ERR)              /* EMAC0 Rx CRC Error Register */
-#define pREG_EMAC0_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC0_RXALIGN_ERR)            /* EMAC0 Rx alignment Error Register */
-#define pREG_EMAC0_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC0_RXRUNT_ERR)             /* EMAC0 Rx Runt Error Register */
-#define pREG_EMAC0_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC0_RXJAB_ERR)              /* EMAC0 Rx Jab Error Register */
-#define pREG_EMAC0_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXUSIZE_G)              /* EMAC0 Rx Undersize (Good) Register */
-#define pREG_EMAC0_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXOSIZE_G)              /* EMAC0 Rx Oversize (Good) Register */
-#define pREG_EMAC0_RX64_GB               ((volatile uint32_t *)REG_EMAC0_RX64_GB)                /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_RX65TO127_GB)           /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_RX128TO255_GB)          /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_RX256TO511_GB)          /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_RX512TO1023_GB)         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_RX1024TOMAX_GB)         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXUCASTFRM_G)           /* EMAC0 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC0_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC0_RXLEN_ERR)              /* EMAC0 Rx Length Error Register */
-#define pREG_EMAC0_RXOORTYPE             ((volatile uint32_t *)REG_EMAC0_RXOORTYPE)              /* EMAC0 Rx Out Of Range Type Register */
-#define pREG_EMAC0_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_RXPAUSEFRM)             /* EMAC0 Rx Pause Frames Register */
-#define pREG_EMAC0_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC0_RXFIFO_OVF)             /* EMAC0 Rx FIFO Overflow Register */
-#define pREG_EMAC0_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC0_RXVLANFRM_GB)           /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC0_RXWDOG_ERR)             /* EMAC0 Rx Watch Dog Error Register */
-#define pREG_EMAC0_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_IPC_RXIMSK)             /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC0_IPC_RXINT             ((volatile uint32_t *)REG_EMAC0_IPC_RXINT)              /* EMAC0 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC0_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_FRM)          /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_FRM)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_FRM)       /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC0_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_FRM)        /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_FRM)       /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC0_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_FRM)          /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_FRM)     /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_FRM)       /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC0_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_FRM)           /* EMAC0 Rx UDP Good Frames Register */
-#define pREG_EMAC0_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_FRM)          /* EMAC0 Rx UDP Error Frames Register */
-#define pREG_EMAC0_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_FRM)           /* EMAC0 Rx TCP Good Frames Register */
-#define pREG_EMAC0_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_FRM)          /* EMAC0 Rx TCP Error Frames Register */
-#define pREG_EMAC0_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_FRM)          /* EMAC0 Rx ICMP Good Frames Register */
-#define pREG_EMAC0_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_FRM)         /* EMAC0 Rx ICMP Error Frames Register */
-#define pREG_EMAC0_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_OCT)          /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_OCT)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_OCT)       /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC0_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_OCT)        /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_OCT)       /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC0_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_OCT)          /* EMAC0 Rx IPv6 Good Octets Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_OCT)     /* EMAC0 Rx IPv6 Header Errors Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_OCT)       /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC0_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_OCT)           /* EMAC0 Rx UDP Good Octets Register */
-#define pREG_EMAC0_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_OCT)          /* EMAC0 Rx UDP Error Octets Register */
-#define pREG_EMAC0_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_OCT)           /* EMAC0 Rx TCP Good Octets Register */
-#define pREG_EMAC0_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_OCT)          /* EMAC0 Rx TCP Error Octets Register */
-#define pREG_EMAC0_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_OCT)          /* EMAC0 Rx ICMP Good Octets Register */
-#define pREG_EMAC0_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_OCT)         /* EMAC0 Rx ICMP Error Octets Register */
-#define pREG_EMAC0_TM_CTL                ((volatile uint32_t *)REG_EMAC0_TM_CTL)                 /* EMAC0 Time Stamp Control Register */
-#define pREG_EMAC0_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC0_TM_SUBSEC)              /* EMAC0 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC0_TM_SEC                ((volatile uint32_t *)REG_EMAC0_TM_SEC)                 /* EMAC0 Time Stamp Low Seconds Register */
-#define pREG_EMAC0_TM_NSEC               ((volatile uint32_t *)REG_EMAC0_TM_NSEC)                /* EMAC0 Time Stamp Nano Seconds Register */
-#define pREG_EMAC0_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC0_TM_SECUPDT)             /* EMAC0 Time Stamp Seconds Update Register */
-#define pREG_EMAC0_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC0_TM_NSECUPDT)            /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC0_TM_ADDEND             ((volatile uint32_t *)REG_EMAC0_TM_ADDEND)              /* EMAC0 Time Stamp Addend Register */
-#define pREG_EMAC0_TM_TGTM               ((volatile uint32_t *)REG_EMAC0_TM_TGTM)                /* EMAC0 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC0_TM_NTGTM              ((volatile uint32_t *)REG_EMAC0_TM_NTGTM)               /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC0_TM_HISEC              ((volatile uint32_t *)REG_EMAC0_TM_HISEC)               /* EMAC0 Time Stamp High Second Register */
-#define pREG_EMAC0_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC0_TM_STMPSTAT)            /* EMAC0 Time Stamp Status Register */
-#define pREG_EMAC0_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC0_TM_PPSCTL)              /* EMAC0 PPS Control Register */
-#define pREG_EMAC0_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_NSEC)        /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC0_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_SEC)         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC0_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC0_TM_PPSINTVL)            /* EMAC0 Time Stamp PPS Interval Register */
-#define pREG_EMAC0_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC0_TM_PPSWIDTH)            /* EMAC0 PPS Width Register */
-#define pREG_EMAC0_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC0_DMA_BUSMODE)            /* EMAC0 DMA Bus Mode Register */
-#define pREG_EMAC0_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_TXPOLL)             /* EMAC0 DMA Tx Poll Demand Register */
-#define pREG_EMAC0_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_RXPOLL)             /* EMAC0 DMA Rx Poll Demand register */
-#define pREG_EMAC0_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_ADDR)         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_ADDR)         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_STAT              ((volatile uint32_t *)REG_EMAC0_DMA_STAT)               /* EMAC0 DMA Status Register */
-#define pREG_EMAC0_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC0_DMA_OPMODE)             /* EMAC0 DMA Operation Mode Register */
-#define pREG_EMAC0_DMA_IEN               ((volatile uint32_t *)REG_EMAC0_DMA_IEN)                /* EMAC0 DMA Interrupt Enable Register */
-#define pREG_EMAC0_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC0_DMA_MISS_FRM)           /* EMAC0 DMA Missed Frame Register */
-#define pREG_EMAC0_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC0_DMA_RXIWDOG)            /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC0_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC0_DMA_BMMODE)             /* EMAC0 DMA SCB Bus Mode Register */
-#define pREG_EMAC0_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC0_DMA_BMSTAT)             /* EMAC0 DMA SCB Status Register */
-#define pREG_EMAC0_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_CUR)          /* EMAC0 DMA Tx Descriptor Current Register */
-#define pREG_EMAC0_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_CUR)          /* EMAC0 DMA Rx Descriptor Current Register */
-#define pREG_EMAC0_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXBUF_CUR)          /* EMAC0 DMA Tx Buffer Current Register */
-#define pREG_EMAC0_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXBUF_CUR)          /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================================================================
-       EMAC1
-   ========================================================================= */
-#define pREG_EMAC1_MACCFG                ((volatile uint32_t *)REG_EMAC1_MACCFG)                 /* EMAC1 MAC Configuration Register */
-#define pREG_EMAC1_MACFRMFILT            ((volatile uint32_t *)REG_EMAC1_MACFRMFILT)             /* EMAC1 MAC Rx Frame Filter Register */
-#define pREG_EMAC1_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC1_HASHTBL_HI)             /* EMAC1 Hash Table High Register */
-#define pREG_EMAC1_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC1_HASHTBL_LO)             /* EMAC1 Hash Table Low Register */
-#define pREG_EMAC1_SMI_ADDR              ((volatile uint32_t *)REG_EMAC1_SMI_ADDR)               /* EMAC1 SMI Address Register */
-#define pREG_EMAC1_SMI_DATA              ((volatile uint32_t *)REG_EMAC1_SMI_DATA)               /* EMAC1 SMI Data Register */
-#define pREG_EMAC1_FLOWCTL               ((volatile uint32_t *)REG_EMAC1_FLOWCTL)                /* EMAC1 FLow Control Register */
-#define pREG_EMAC1_VLANTAG               ((volatile uint32_t *)REG_EMAC1_VLANTAG)                /* EMAC1 VLAN Tag Register */
-#define pREG_EMAC1_DBG                   ((volatile uint32_t *)REG_EMAC1_DBG)                    /* EMAC1 Debug Register */
-#define pREG_EMAC1_ISTAT                 ((volatile uint32_t *)REG_EMAC1_ISTAT)                  /* EMAC1 Interrupt Status Register */
-#define pREG_EMAC1_IMSK                  ((volatile uint32_t *)REG_EMAC1_IMSK)                   /* EMAC1 Interrupt Mask Register */
-#define pREG_EMAC1_ADDR0_HI              ((volatile uint32_t *)REG_EMAC1_ADDR0_HI)               /* EMAC1 MAC Address 0 High Register */
-#define pREG_EMAC1_ADDR0_LO              ((volatile uint32_t *)REG_EMAC1_ADDR0_LO)               /* EMAC1 MAC Address 0 Low Register */
-#define pREG_EMAC1_MMC_CTL               ((volatile uint32_t *)REG_EMAC1_MMC_CTL)                /* EMAC1 MMC Control Register */
-#define pREG_EMAC1_MMC_RXINT             ((volatile uint32_t *)REG_EMAC1_MMC_RXINT)              /* EMAC1 MMC Rx Interrupt Register */
-#define pREG_EMAC1_MMC_TXINT             ((volatile uint32_t *)REG_EMAC1_MMC_TXINT)              /* EMAC1 MMC Tx Interrupt Register */
-#define pREG_EMAC1_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_RXIMSK)             /* EMAC1 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC1_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_TXIMSK)             /* EMAC1 MMC TX Interrupt Mask Register */
-#define pREG_EMAC1_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_GB)            /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC1_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_GB)            /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_G)           /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_G)           /* EMAC1 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC1_TX64_GB               ((volatile uint32_t *)REG_EMAC1_TX64_GB)                /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_TX65TO127_GB)           /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_TX128TO255_GB)          /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_TX256TO511_GB)          /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_TX512TO1023_GB)         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_TX1024TOMAX_GB)         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXUCASTFRM_GB)          /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_GB)          /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_GB)          /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC1_TXUNDR_ERR)             /* EMAC1 Tx Underflow Error Register */
-#define pREG_EMAC1_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC1_TXSNGCOL_G)             /* EMAC1 Tx Single Collision (Good) Register */
-#define pREG_EMAC1_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC1_TXMULTCOL_G)            /* EMAC1 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC1_TXDEFERRED            ((volatile uint32_t *)REG_EMAC1_TXDEFERRED)             /* EMAC1 Tx Deferred Register */
-#define pREG_EMAC1_TXLATECOL             ((volatile uint32_t *)REG_EMAC1_TXLATECOL)              /* EMAC1 Tx Late Collision Register */
-#define pREG_EMAC1_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC1_TXEXCESSCOL)            /* EMAC1 Tx Excess Collision Register */
-#define pREG_EMAC1_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC1_TXCARR_ERR)             /* EMAC1 Tx Carrier Error Register */
-#define pREG_EMAC1_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_G)             /* EMAC1 Tx Octet Count (Good) Register */
-#define pREG_EMAC1_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_G)             /* EMAC1 Tx Frame Count (Good) Register */
-#define pREG_EMAC1_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC1_TXEXCESSDEF)            /* EMAC1 Tx Excess Deferral Register */
-#define pREG_EMAC1_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_TXPAUSEFRM)             /* EMAC1 Tx Pause Frame Register */
-#define pREG_EMAC1_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC1_TXVLANFRM_G)            /* EMAC1 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC1_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXFRMCNT_GB)            /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_GB)            /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_G)             /* EMAC1 Rx Octet Count (Good) Register */
-#define pREG_EMAC1_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXBCASTFRM_G)           /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXMCASTFRM_G)           /* EMAC1 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC1_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC1_RXCRC_ERR)              /* EMAC1 Rx CRC Error Register */
-#define pREG_EMAC1_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC1_RXALIGN_ERR)            /* EMAC1 Rx alignment Error Register */
-#define pREG_EMAC1_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC1_RXRUNT_ERR)             /* EMAC1 Rx Runt Error Register */
-#define pREG_EMAC1_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC1_RXJAB_ERR)              /* EMAC1 Rx Jab Error Register */
-#define pREG_EMAC1_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXUSIZE_G)              /* EMAC1 Rx Undersize (Good) Register */
-#define pREG_EMAC1_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXOSIZE_G)              /* EMAC1 Rx Oversize (Good) Register */
-#define pREG_EMAC1_RX64_GB               ((volatile uint32_t *)REG_EMAC1_RX64_GB)                /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_RX65TO127_GB)           /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_RX128TO255_GB)          /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_RX256TO511_GB)          /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_RX512TO1023_GB)         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_RX1024TOMAX_GB)         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXUCASTFRM_G)           /* EMAC1 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC1_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC1_RXLEN_ERR)              /* EMAC1 Rx Length Error Register */
-#define pREG_EMAC1_RXOORTYPE             ((volatile uint32_t *)REG_EMAC1_RXOORTYPE)              /* EMAC1 Rx Out Of Range Type Register */
-#define pREG_EMAC1_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_RXPAUSEFRM)             /* EMAC1 Rx Pause Frames Register */
-#define pREG_EMAC1_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC1_RXFIFO_OVF)             /* EMAC1 Rx FIFO Overflow Register */
-#define pREG_EMAC1_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC1_RXVLANFRM_GB)           /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC1_RXWDOG_ERR)             /* EMAC1 Rx Watch Dog Error Register */
-#define pREG_EMAC1_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_IPC_RXIMSK)             /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC1_IPC_RXINT             ((volatile uint32_t *)REG_EMAC1_IPC_RXINT)              /* EMAC1 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC1_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_FRM)          /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_FRM)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_FRM)       /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC1_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_FRM)        /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_FRM)       /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC1_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_FRM)          /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_FRM)     /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_FRM)       /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC1_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_FRM)           /* EMAC1 Rx UDP Good Frames Register */
-#define pREG_EMAC1_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_FRM)          /* EMAC1 Rx UDP Error Frames Register */
-#define pREG_EMAC1_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_FRM)           /* EMAC1 Rx TCP Good Frames Register */
-#define pREG_EMAC1_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_FRM)          /* EMAC1 Rx TCP Error Frames Register */
-#define pREG_EMAC1_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_FRM)          /* EMAC1 Rx ICMP Good Frames Register */
-#define pREG_EMAC1_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_FRM)         /* EMAC1 Rx ICMP Error Frames Register */
-#define pREG_EMAC1_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_OCT)          /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_OCT)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_OCT)       /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC1_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_OCT)        /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_OCT)       /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC1_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_OCT)          /* EMAC1 Rx IPv6 Good Octets Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_OCT)     /* EMAC1 Rx IPv6 Header Errors Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_OCT)       /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC1_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_OCT)           /* EMAC1 Rx UDP Good Octets Register */
-#define pREG_EMAC1_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_OCT)          /* EMAC1 Rx UDP Error Octets Register */
-#define pREG_EMAC1_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_OCT)           /* EMAC1 Rx TCP Good Octets Register */
-#define pREG_EMAC1_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_OCT)          /* EMAC1 Rx TCP Error Octets Register */
-#define pREG_EMAC1_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_OCT)          /* EMAC1 Rx ICMP Good Octets Register */
-#define pREG_EMAC1_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_OCT)         /* EMAC1 Rx ICMP Error Octets Register */
-#define pREG_EMAC1_TM_CTL                ((volatile uint32_t *)REG_EMAC1_TM_CTL)                 /* EMAC1 Time Stamp Control Register */
-#define pREG_EMAC1_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC1_TM_SUBSEC)              /* EMAC1 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC1_TM_SEC                ((volatile uint32_t *)REG_EMAC1_TM_SEC)                 /* EMAC1 Time Stamp Low Seconds Register */
-#define pREG_EMAC1_TM_NSEC               ((volatile uint32_t *)REG_EMAC1_TM_NSEC)                /* EMAC1 Time Stamp Nano Seconds Register */
-#define pREG_EMAC1_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC1_TM_SECUPDT)             /* EMAC1 Time Stamp Seconds Update Register */
-#define pREG_EMAC1_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC1_TM_NSECUPDT)            /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC1_TM_ADDEND             ((volatile uint32_t *)REG_EMAC1_TM_ADDEND)              /* EMAC1 Time Stamp Addend Register */
-#define pREG_EMAC1_TM_TGTM               ((volatile uint32_t *)REG_EMAC1_TM_TGTM)                /* EMAC1 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC1_TM_NTGTM              ((volatile uint32_t *)REG_EMAC1_TM_NTGTM)               /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC1_TM_HISEC              ((volatile uint32_t *)REG_EMAC1_TM_HISEC)               /* EMAC1 Time Stamp High Second Register */
-#define pREG_EMAC1_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC1_TM_STMPSTAT)            /* EMAC1 Time Stamp Status Register */
-#define pREG_EMAC1_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC1_TM_PPSCTL)              /* EMAC1 PPS Control Register */
-#define pREG_EMAC1_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_NSEC)        /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC1_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_SEC)         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC1_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC1_TM_PPSINTVL)            /* EMAC1 Time Stamp PPS Interval Register */
-#define pREG_EMAC1_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC1_TM_PPSWIDTH)            /* EMAC1 PPS Width Register */
-#define pREG_EMAC1_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC1_DMA_BUSMODE)            /* EMAC1 DMA Bus Mode Register */
-#define pREG_EMAC1_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_TXPOLL)             /* EMAC1 DMA Tx Poll Demand Register */
-#define pREG_EMAC1_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_RXPOLL)             /* EMAC1 DMA Rx Poll Demand register */
-#define pREG_EMAC1_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_ADDR)         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_ADDR)         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_STAT              ((volatile uint32_t *)REG_EMAC1_DMA_STAT)               /* EMAC1 DMA Status Register */
-#define pREG_EMAC1_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC1_DMA_OPMODE)             /* EMAC1 DMA Operation Mode Register */
-#define pREG_EMAC1_DMA_IEN               ((volatile uint32_t *)REG_EMAC1_DMA_IEN)                /* EMAC1 DMA Interrupt Enable Register */
-#define pREG_EMAC1_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC1_DMA_MISS_FRM)           /* EMAC1 DMA Missed Frame Register */
-#define pREG_EMAC1_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC1_DMA_RXIWDOG)            /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC1_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC1_DMA_BMMODE)             /* EMAC1 DMA SCB Bus Mode Register */
-#define pREG_EMAC1_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC1_DMA_BMSTAT)             /* EMAC1 DMA SCB Status Register */
-#define pREG_EMAC1_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_CUR)          /* EMAC1 DMA Tx Descriptor Current Register */
-#define pREG_EMAC1_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_CUR)          /* EMAC1 DMA Rx Descriptor Current Register */
-#define pREG_EMAC1_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXBUF_CUR)          /* EMAC1 DMA Tx Buffer Current Register */
-#define pREG_EMAC1_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXBUF_CUR)          /* EMAC1 DMA Rx Buffer Current Register */
-
-
-/* =========================================================================
-       SPORT0
-   ========================================================================= */
-#define pREG_SPORT0_CTL_A                ((volatile uint32_t *)REG_SPORT0_CTL_A)                 /* SPORT0 Half SPORT 'A' Control Register */
-#define pREG_SPORT0_DIV_A                ((volatile uint32_t *)REG_SPORT0_DIV_A)                 /* SPORT0 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT0_MCTL_A               ((volatile uint32_t *)REG_SPORT0_MCTL_A)                /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_A                ((volatile uint32_t *)REG_SPORT0_CS0_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_A                ((volatile uint32_t *)REG_SPORT0_CS1_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_A                ((volatile uint32_t *)REG_SPORT0_CS2_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT0_CS3_A                ((volatile uint32_t *)REG_SPORT0_CS3_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT0_ERR_A                ((volatile uint32_t *)REG_SPORT0_ERR_A)                 /* SPORT0 Half SPORT 'A' Error Register */
-#define pREG_SPORT0_MSTAT_A              ((volatile uint32_t *)REG_SPORT0_MSTAT_A)               /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_A               ((volatile uint32_t *)REG_SPORT0_CTL2_A)                /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT0_TXPRI_A              ((volatile uint32_t *)REG_SPORT0_TXPRI_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_A              ((volatile uint32_t *)REG_SPORT0_RXPRI_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_A              ((volatile uint32_t *)REG_SPORT0_TXSEC_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_A              ((volatile uint32_t *)REG_SPORT0_RXSEC_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT0_CTL_B                ((volatile uint32_t *)REG_SPORT0_CTL_B)                 /* SPORT0 Half SPORT 'B' Control Register */
-#define pREG_SPORT0_DIV_B                ((volatile uint32_t *)REG_SPORT0_DIV_B)                 /* SPORT0 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT0_MCTL_B               ((volatile uint32_t *)REG_SPORT0_MCTL_B)                /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_B                ((volatile uint32_t *)REG_SPORT0_CS0_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_B                ((volatile uint32_t *)REG_SPORT0_CS1_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_B                ((volatile uint32_t *)REG_SPORT0_CS2_B)                 /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT0_CS3_B                ((volatile uint32_t *)REG_SPORT0_CS3_B)                 /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT0_ERR_B                ((volatile uint32_t *)REG_SPORT0_ERR_B)                 /* SPORT0 Half SPORT 'B' Error Register */
-#define pREG_SPORT0_MSTAT_B              ((volatile uint32_t *)REG_SPORT0_MSTAT_B)               /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_B               ((volatile uint32_t *)REG_SPORT0_CTL2_B)                /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT0_TXPRI_B              ((volatile uint32_t *)REG_SPORT0_TXPRI_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_B              ((volatile uint32_t *)REG_SPORT0_RXPRI_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_B              ((volatile uint32_t *)REG_SPORT0_TXSEC_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_B              ((volatile uint32_t *)REG_SPORT0_RXSEC_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT1
-   ========================================================================= */
-#define pREG_SPORT1_CTL_A                ((volatile uint32_t *)REG_SPORT1_CTL_A)                 /* SPORT1 Half SPORT 'A' Control Register */
-#define pREG_SPORT1_DIV_A                ((volatile uint32_t *)REG_SPORT1_DIV_A)                 /* SPORT1 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT1_MCTL_A               ((volatile uint32_t *)REG_SPORT1_MCTL_A)                /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_A                ((volatile uint32_t *)REG_SPORT1_CS0_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_A                ((volatile uint32_t *)REG_SPORT1_CS1_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_A                ((volatile uint32_t *)REG_SPORT1_CS2_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT1_CS3_A                ((volatile uint32_t *)REG_SPORT1_CS3_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT1_ERR_A                ((volatile uint32_t *)REG_SPORT1_ERR_A)                 /* SPORT1 Half SPORT 'A' Error Register */
-#define pREG_SPORT1_MSTAT_A              ((volatile uint32_t *)REG_SPORT1_MSTAT_A)               /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_A               ((volatile uint32_t *)REG_SPORT1_CTL2_A)                /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT1_TXPRI_A              ((volatile uint32_t *)REG_SPORT1_TXPRI_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_A              ((volatile uint32_t *)REG_SPORT1_RXPRI_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_A              ((volatile uint32_t *)REG_SPORT1_TXSEC_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_A              ((volatile uint32_t *)REG_SPORT1_RXSEC_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT1_CTL_B                ((volatile uint32_t *)REG_SPORT1_CTL_B)                 /* SPORT1 Half SPORT 'B' Control Register */
-#define pREG_SPORT1_DIV_B                ((volatile uint32_t *)REG_SPORT1_DIV_B)                 /* SPORT1 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT1_MCTL_B               ((volatile uint32_t *)REG_SPORT1_MCTL_B)                /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_B                ((volatile uint32_t *)REG_SPORT1_CS0_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_B                ((volatile uint32_t *)REG_SPORT1_CS1_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_B                ((volatile uint32_t *)REG_SPORT1_CS2_B)                 /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT1_CS3_B                ((volatile uint32_t *)REG_SPORT1_CS3_B)                 /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT1_ERR_B                ((volatile uint32_t *)REG_SPORT1_ERR_B)                 /* SPORT1 Half SPORT 'B' Error Register */
-#define pREG_SPORT1_MSTAT_B              ((volatile uint32_t *)REG_SPORT1_MSTAT_B)               /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_B               ((volatile uint32_t *)REG_SPORT1_CTL2_B)                /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT1_TXPRI_B              ((volatile uint32_t *)REG_SPORT1_TXPRI_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_B              ((volatile uint32_t *)REG_SPORT1_RXPRI_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_B              ((volatile uint32_t *)REG_SPORT1_TXSEC_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_B              ((volatile uint32_t *)REG_SPORT1_RXSEC_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT2
-   ========================================================================= */
-#define pREG_SPORT2_CTL_A                ((volatile uint32_t *)REG_SPORT2_CTL_A)                 /* SPORT2 Half SPORT 'A' Control Register */
-#define pREG_SPORT2_DIV_A                ((volatile uint32_t *)REG_SPORT2_DIV_A)                 /* SPORT2 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT2_MCTL_A               ((volatile uint32_t *)REG_SPORT2_MCTL_A)                /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_A                ((volatile uint32_t *)REG_SPORT2_CS0_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_A                ((volatile uint32_t *)REG_SPORT2_CS1_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_A                ((volatile uint32_t *)REG_SPORT2_CS2_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT2_CS3_A                ((volatile uint32_t *)REG_SPORT2_CS3_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT2_ERR_A                ((volatile uint32_t *)REG_SPORT2_ERR_A)                 /* SPORT2 Half SPORT 'A' Error Register */
-#define pREG_SPORT2_MSTAT_A              ((volatile uint32_t *)REG_SPORT2_MSTAT_A)               /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_A               ((volatile uint32_t *)REG_SPORT2_CTL2_A)                /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT2_TXPRI_A              ((volatile uint32_t *)REG_SPORT2_TXPRI_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_A              ((volatile uint32_t *)REG_SPORT2_RXPRI_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_A              ((volatile uint32_t *)REG_SPORT2_TXSEC_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_A              ((volatile uint32_t *)REG_SPORT2_RXSEC_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT2_CTL_B                ((volatile uint32_t *)REG_SPORT2_CTL_B)                 /* SPORT2 Half SPORT 'B' Control Register */
-#define pREG_SPORT2_DIV_B                ((volatile uint32_t *)REG_SPORT2_DIV_B)                 /* SPORT2 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT2_MCTL_B               ((volatile uint32_t *)REG_SPORT2_MCTL_B)                /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_B                ((volatile uint32_t *)REG_SPORT2_CS0_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_B                ((volatile uint32_t *)REG_SPORT2_CS1_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_B                ((volatile uint32_t *)REG_SPORT2_CS2_B)                 /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT2_CS3_B                ((volatile uint32_t *)REG_SPORT2_CS3_B)                 /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT2_ERR_B                ((volatile uint32_t *)REG_SPORT2_ERR_B)                 /* SPORT2 Half SPORT 'B' Error Register */
-#define pREG_SPORT2_MSTAT_B              ((volatile uint32_t *)REG_SPORT2_MSTAT_B)               /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_B               ((volatile uint32_t *)REG_SPORT2_CTL2_B)                /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT2_TXPRI_B              ((volatile uint32_t *)REG_SPORT2_TXPRI_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_B              ((volatile uint32_t *)REG_SPORT2_RXPRI_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_B              ((volatile uint32_t *)REG_SPORT2_TXSEC_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_B              ((volatile uint32_t *)REG_SPORT2_RXSEC_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-
-/* =========================================================================
-       SPI0
-   ========================================================================= */
-#define pREG_SPI0_CTL                    ((volatile uint32_t *)REG_SPI0_CTL)                     /* SPI0 Control Register */
-#define pREG_SPI0_RXCTL                  ((volatile uint32_t *)REG_SPI0_RXCTL)                   /* SPI0 Receive Control Register */
-#define pREG_SPI0_TXCTL                  ((volatile uint32_t *)REG_SPI0_TXCTL)                   /* SPI0 Transmit Control Register */
-#define pREG_SPI0_CLK                    ((volatile uint32_t *)REG_SPI0_CLK)                     /* SPI0 Clock Rate Register */
-#define pREG_SPI0_DLY                    ((volatile uint32_t *)REG_SPI0_DLY)                     /* SPI0 Delay Register */
-#define pREG_SPI0_SLVSEL                 ((volatile uint32_t *)REG_SPI0_SLVSEL)                  /* SPI0 Slave Select Register */
-#define pREG_SPI0_RWC                    ((volatile uint32_t *)REG_SPI0_RWC)                     /* SPI0 Received Word Count Register */
-#define pREG_SPI0_RWCR                   ((volatile uint32_t *)REG_SPI0_RWCR)                    /* SPI0 Received Word Count Reload Register */
-#define pREG_SPI0_TWC                    ((volatile uint32_t *)REG_SPI0_TWC)                     /* SPI0 Transmitted Word Count Register */
-#define pREG_SPI0_TWCR                   ((volatile uint32_t *)REG_SPI0_TWCR)                    /* SPI0 Transmitted Word Count Reload Register */
-#define pREG_SPI0_IMSK                   ((volatile uint32_t *)REG_SPI0_IMSK)                    /* SPI0 Interrupt Mask Register */
-#define pREG_SPI0_IMSK_CLR               ((volatile uint32_t *)REG_SPI0_IMSK_CLR)                /* SPI0 Interrupt Mask Clear Register */
-#define pREG_SPI0_IMSK_SET               ((volatile uint32_t *)REG_SPI0_IMSK_SET)                /* SPI0 Interrupt Mask Set Register */
-#define pREG_SPI0_STAT                   ((volatile uint32_t *)REG_SPI0_STAT)                    /* SPI0 Status Register */
-#define pREG_SPI0_ILAT                   ((volatile uint32_t *)REG_SPI0_ILAT)                    /* SPI0 Masked Interrupt Condition Register */
-#define pREG_SPI0_ILAT_CLR               ((volatile uint32_t *)REG_SPI0_ILAT_CLR)                /* SPI0 Masked Interrupt Clear Register */
-#define pREG_SPI0_RFIFO                  ((volatile uint32_t *)REG_SPI0_RFIFO)                   /* SPI0 Receive FIFO Data Register */
-#define pREG_SPI0_TFIFO                  ((volatile uint32_t *)REG_SPI0_TFIFO)                   /* SPI0 Transmit FIFO Data Register */
-
-/* =========================================================================
-       SPI1
-   ========================================================================= */
-#define pREG_SPI1_CTL                    ((volatile uint32_t *)REG_SPI1_CTL)                     /* SPI1 Control Register */
-#define pREG_SPI1_RXCTL                  ((volatile uint32_t *)REG_SPI1_RXCTL)                   /* SPI1 Receive Control Register */
-#define pREG_SPI1_TXCTL                  ((volatile uint32_t *)REG_SPI1_TXCTL)                   /* SPI1 Transmit Control Register */
-#define pREG_SPI1_CLK                    ((volatile uint32_t *)REG_SPI1_CLK)                     /* SPI1 Clock Rate Register */
-#define pREG_SPI1_DLY                    ((volatile uint32_t *)REG_SPI1_DLY)                     /* SPI1 Delay Register */
-#define pREG_SPI1_SLVSEL                 ((volatile uint32_t *)REG_SPI1_SLVSEL)                  /* SPI1 Slave Select Register */
-#define pREG_SPI1_RWC                    ((volatile uint32_t *)REG_SPI1_RWC)                     /* SPI1 Received Word Count Register */
-#define pREG_SPI1_RWCR                   ((volatile uint32_t *)REG_SPI1_RWCR)                    /* SPI1 Received Word Count Reload Register */
-#define pREG_SPI1_TWC                    ((volatile uint32_t *)REG_SPI1_TWC)                     /* SPI1 Transmitted Word Count Register */
-#define pREG_SPI1_TWCR                   ((volatile uint32_t *)REG_SPI1_TWCR)                    /* SPI1 Transmitted Word Count Reload Register */
-#define pREG_SPI1_IMSK                   ((volatile uint32_t *)REG_SPI1_IMSK)                    /* SPI1 Interrupt Mask Register */
-#define pREG_SPI1_IMSK_CLR               ((volatile uint32_t *)REG_SPI1_IMSK_CLR)                /* SPI1 Interrupt Mask Clear Register */
-#define pREG_SPI1_IMSK_SET               ((volatile uint32_t *)REG_SPI1_IMSK_SET)                /* SPI1 Interrupt Mask Set Register */
-#define pREG_SPI1_STAT                   ((volatile uint32_t *)REG_SPI1_STAT)                    /* SPI1 Status Register */
-#define pREG_SPI1_ILAT                   ((volatile uint32_t *)REG_SPI1_ILAT)                    /* SPI1 Masked Interrupt Condition Register */
-#define pREG_SPI1_ILAT_CLR               ((volatile uint32_t *)REG_SPI1_ILAT_CLR)                /* SPI1 Masked Interrupt Clear Register */
-#define pREG_SPI1_RFIFO                  ((volatile uint32_t *)REG_SPI1_RFIFO)                   /* SPI1 Receive FIFO Data Register */
-#define pREG_SPI1_TFIFO                  ((volatile uint32_t *)REG_SPI1_TFIFO)                   /* SPI1 Transmit FIFO Data Register */
-
-
-/* =========================================================================
-       DMA0
-   ========================================================================= */
-#define pREG_DMA0_DSCPTR_NXT             ((void * volatile *)REG_DMA0_DSCPTR_NXT)                /* DMA0 Pointer to Next Initial Descriptor */
-#define pREG_DMA0_ADDRSTART              ((void * volatile *)REG_DMA0_ADDRSTART)                 /* DMA0 Start Address of Current Buffer */
-#define pREG_DMA0_CFG                    ((volatile uint32_t *)REG_DMA0_CFG)                     /* DMA0 Configuration Register */
-#define pREG_DMA0_XCNT                   ((volatile uint32_t *)REG_DMA0_XCNT)                    /* DMA0 Inner Loop Count Start Value */
-#define pREG_DMA0_XMOD                   ((volatile  int32_t *)REG_DMA0_XMOD)                    /* DMA0 Inner Loop Address Increment */
-#define pREG_DMA0_YCNT                   ((volatile uint32_t *)REG_DMA0_YCNT)                    /* DMA0 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA0_YMOD                   ((volatile  int32_t *)REG_DMA0_YMOD)                    /* DMA0 Outer Loop Address Increment (2D only) */
-#define pREG_DMA0_DSCPTR_CUR             ((void * volatile *)REG_DMA0_DSCPTR_CUR)                /* DMA0 Current Descriptor Pointer */
-#define pREG_DMA0_DSCPTR_PRV             ((void * volatile *)REG_DMA0_DSCPTR_PRV)                /* DMA0 Previous Initial Descriptor Pointer */
-#define pREG_DMA0_ADDR_CUR               ((void * volatile *)REG_DMA0_ADDR_CUR)                  /* DMA0 Current Address */
-#define pREG_DMA0_STAT                   ((volatile uint32_t *)REG_DMA0_STAT)                    /* DMA0 Status Register */
-#define pREG_DMA0_XCNT_CUR               ((volatile uint32_t *)REG_DMA0_XCNT_CUR)                /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA0_YCNT_CUR               ((volatile uint32_t *)REG_DMA0_YCNT_CUR)                /* DMA0 Current Row Count (2D only) */
-#define pREG_DMA0_BWLCNT                 ((volatile uint32_t *)REG_DMA0_BWLCNT)                  /* DMA0 Bandwidth Limit Count */
-#define pREG_DMA0_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWLCNT_CUR)              /* DMA0 Bandwidth Limit Count Current */
-#define pREG_DMA0_BWMCNT                 ((volatile uint32_t *)REG_DMA0_BWMCNT)                  /* DMA0 Bandwidth Monitor Count */
-#define pREG_DMA0_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWMCNT_CUR)              /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA1
-   ========================================================================= */
-#define pREG_DMA1_DSCPTR_NXT             ((void * volatile *)REG_DMA1_DSCPTR_NXT)                /* DMA1 Pointer to Next Initial Descriptor */
-#define pREG_DMA1_ADDRSTART              ((void * volatile *)REG_DMA1_ADDRSTART)                 /* DMA1 Start Address of Current Buffer */
-#define pREG_DMA1_CFG                    ((volatile uint32_t *)REG_DMA1_CFG)                     /* DMA1 Configuration Register */
-#define pREG_DMA1_XCNT                   ((volatile uint32_t *)REG_DMA1_XCNT)                    /* DMA1 Inner Loop Count Start Value */
-#define pREG_DMA1_XMOD                   ((volatile  int32_t *)REG_DMA1_XMOD)                    /* DMA1 Inner Loop Address Increment */
-#define pREG_DMA1_YCNT                   ((volatile uint32_t *)REG_DMA1_YCNT)                    /* DMA1 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA1_YMOD                   ((volatile  int32_t *)REG_DMA1_YMOD)                    /* DMA1 Outer Loop Address Increment (2D only) */
-#define pREG_DMA1_DSCPTR_CUR             ((void * volatile *)REG_DMA1_DSCPTR_CUR)                /* DMA1 Current Descriptor Pointer */
-#define pREG_DMA1_DSCPTR_PRV             ((void * volatile *)REG_DMA1_DSCPTR_PRV)                /* DMA1 Previous Initial Descriptor Pointer */
-#define pREG_DMA1_ADDR_CUR               ((void * volatile *)REG_DMA1_ADDR_CUR)                  /* DMA1 Current Address */
-#define pREG_DMA1_STAT                   ((volatile uint32_t *)REG_DMA1_STAT)                    /* DMA1 Status Register */
-#define pREG_DMA1_XCNT_CUR               ((volatile uint32_t *)REG_DMA1_XCNT_CUR)                /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA1_YCNT_CUR               ((volatile uint32_t *)REG_DMA1_YCNT_CUR)                /* DMA1 Current Row Count (2D only) */
-#define pREG_DMA1_BWLCNT                 ((volatile uint32_t *)REG_DMA1_BWLCNT)                  /* DMA1 Bandwidth Limit Count */
-#define pREG_DMA1_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWLCNT_CUR)              /* DMA1 Bandwidth Limit Count Current */
-#define pREG_DMA1_BWMCNT                 ((volatile uint32_t *)REG_DMA1_BWMCNT)                  /* DMA1 Bandwidth Monitor Count */
-#define pREG_DMA1_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWMCNT_CUR)              /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA2
-   ========================================================================= */
-#define pREG_DMA2_DSCPTR_NXT             ((void * volatile *)REG_DMA2_DSCPTR_NXT)                /* DMA2 Pointer to Next Initial Descriptor */
-#define pREG_DMA2_ADDRSTART              ((void * volatile *)REG_DMA2_ADDRSTART)                 /* DMA2 Start Address of Current Buffer */
-#define pREG_DMA2_CFG                    ((volatile uint32_t *)REG_DMA2_CFG)                     /* DMA2 Configuration Register */
-#define pREG_DMA2_XCNT                   ((volatile uint32_t *)REG_DMA2_XCNT)                    /* DMA2 Inner Loop Count Start Value */
-#define pREG_DMA2_XMOD                   ((volatile  int32_t *)REG_DMA2_XMOD)                    /* DMA2 Inner Loop Address Increment */
-#define pREG_DMA2_YCNT                   ((volatile uint32_t *)REG_DMA2_YCNT)                    /* DMA2 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA2_YMOD                   ((volatile  int32_t *)REG_DMA2_YMOD)                    /* DMA2 Outer Loop Address Increment (2D only) */
-#define pREG_DMA2_DSCPTR_CUR             ((void * volatile *)REG_DMA2_DSCPTR_CUR)                /* DMA2 Current Descriptor Pointer */
-#define pREG_DMA2_DSCPTR_PRV             ((void * volatile *)REG_DMA2_DSCPTR_PRV)                /* DMA2 Previous Initial Descriptor Pointer */
-#define pREG_DMA2_ADDR_CUR               ((void * volatile *)REG_DMA2_ADDR_CUR)                  /* DMA2 Current Address */
-#define pREG_DMA2_STAT                   ((volatile uint32_t *)REG_DMA2_STAT)                    /* DMA2 Status Register */
-#define pREG_DMA2_XCNT_CUR               ((volatile uint32_t *)REG_DMA2_XCNT_CUR)                /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA2_YCNT_CUR               ((volatile uint32_t *)REG_DMA2_YCNT_CUR)                /* DMA2 Current Row Count (2D only) */
-#define pREG_DMA2_BWLCNT                 ((volatile uint32_t *)REG_DMA2_BWLCNT)                  /* DMA2 Bandwidth Limit Count */
-#define pREG_DMA2_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWLCNT_CUR)              /* DMA2 Bandwidth Limit Count Current */
-#define pREG_DMA2_BWMCNT                 ((volatile uint32_t *)REG_DMA2_BWMCNT)                  /* DMA2 Bandwidth Monitor Count */
-#define pREG_DMA2_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWMCNT_CUR)              /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA3
-   ========================================================================= */
-#define pREG_DMA3_DSCPTR_NXT             ((void * volatile *)REG_DMA3_DSCPTR_NXT)                /* DMA3 Pointer to Next Initial Descriptor */
-#define pREG_DMA3_ADDRSTART              ((void * volatile *)REG_DMA3_ADDRSTART)                 /* DMA3 Start Address of Current Buffer */
-#define pREG_DMA3_CFG                    ((volatile uint32_t *)REG_DMA3_CFG)                     /* DMA3 Configuration Register */
-#define pREG_DMA3_XCNT                   ((volatile uint32_t *)REG_DMA3_XCNT)                    /* DMA3 Inner Loop Count Start Value */
-#define pREG_DMA3_XMOD                   ((volatile  int32_t *)REG_DMA3_XMOD)                    /* DMA3 Inner Loop Address Increment */
-#define pREG_DMA3_YCNT                   ((volatile uint32_t *)REG_DMA3_YCNT)                    /* DMA3 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA3_YMOD                   ((volatile  int32_t *)REG_DMA3_YMOD)                    /* DMA3 Outer Loop Address Increment (2D only) */
-#define pREG_DMA3_DSCPTR_CUR             ((void * volatile *)REG_DMA3_DSCPTR_CUR)                /* DMA3 Current Descriptor Pointer */
-#define pREG_DMA3_DSCPTR_PRV             ((void * volatile *)REG_DMA3_DSCPTR_PRV)                /* DMA3 Previous Initial Descriptor Pointer */
-#define pREG_DMA3_ADDR_CUR               ((void * volatile *)REG_DMA3_ADDR_CUR)                  /* DMA3 Current Address */
-#define pREG_DMA3_STAT                   ((volatile uint32_t *)REG_DMA3_STAT)                    /* DMA3 Status Register */
-#define pREG_DMA3_XCNT_CUR               ((volatile uint32_t *)REG_DMA3_XCNT_CUR)                /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA3_YCNT_CUR               ((volatile uint32_t *)REG_DMA3_YCNT_CUR)                /* DMA3 Current Row Count (2D only) */
-#define pREG_DMA3_BWLCNT                 ((volatile uint32_t *)REG_DMA3_BWLCNT)                  /* DMA3 Bandwidth Limit Count */
-#define pREG_DMA3_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWLCNT_CUR)              /* DMA3 Bandwidth Limit Count Current */
-#define pREG_DMA3_BWMCNT                 ((volatile uint32_t *)REG_DMA3_BWMCNT)                  /* DMA3 Bandwidth Monitor Count */
-#define pREG_DMA3_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWMCNT_CUR)              /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA4
-   ========================================================================= */
-#define pREG_DMA4_DSCPTR_NXT             ((void * volatile *)REG_DMA4_DSCPTR_NXT)                /* DMA4 Pointer to Next Initial Descriptor */
-#define pREG_DMA4_ADDRSTART              ((void * volatile *)REG_DMA4_ADDRSTART)                 /* DMA4 Start Address of Current Buffer */
-#define pREG_DMA4_CFG                    ((volatile uint32_t *)REG_DMA4_CFG)                     /* DMA4 Configuration Register */
-#define pREG_DMA4_XCNT                   ((volatile uint32_t *)REG_DMA4_XCNT)                    /* DMA4 Inner Loop Count Start Value */
-#define pREG_DMA4_XMOD                   ((volatile  int32_t *)REG_DMA4_XMOD)                    /* DMA4 Inner Loop Address Increment */
-#define pREG_DMA4_YCNT                   ((volatile uint32_t *)REG_DMA4_YCNT)                    /* DMA4 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA4_YMOD                   ((volatile  int32_t *)REG_DMA4_YMOD)                    /* DMA4 Outer Loop Address Increment (2D only) */
-#define pREG_DMA4_DSCPTR_CUR             ((void * volatile *)REG_DMA4_DSCPTR_CUR)                /* DMA4 Current Descriptor Pointer */
-#define pREG_DMA4_DSCPTR_PRV             ((void * volatile *)REG_DMA4_DSCPTR_PRV)                /* DMA4 Previous Initial Descriptor Pointer */
-#define pREG_DMA4_ADDR_CUR               ((void * volatile *)REG_DMA4_ADDR_CUR)                  /* DMA4 Current Address */
-#define pREG_DMA4_STAT                   ((volatile uint32_t *)REG_DMA4_STAT)                    /* DMA4 Status Register */
-#define pREG_DMA4_XCNT_CUR               ((volatile uint32_t *)REG_DMA4_XCNT_CUR)                /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA4_YCNT_CUR               ((volatile uint32_t *)REG_DMA4_YCNT_CUR)                /* DMA4 Current Row Count (2D only) */
-#define pREG_DMA4_BWLCNT                 ((volatile uint32_t *)REG_DMA4_BWLCNT)                  /* DMA4 Bandwidth Limit Count */
-#define pREG_DMA4_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWLCNT_CUR)              /* DMA4 Bandwidth Limit Count Current */
-#define pREG_DMA4_BWMCNT                 ((volatile uint32_t *)REG_DMA4_BWMCNT)                  /* DMA4 Bandwidth Monitor Count */
-#define pREG_DMA4_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWMCNT_CUR)              /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA5
-   ========================================================================= */
-#define pREG_DMA5_DSCPTR_NXT             ((void * volatile *)REG_DMA5_DSCPTR_NXT)                /* DMA5 Pointer to Next Initial Descriptor */
-#define pREG_DMA5_ADDRSTART              ((void * volatile *)REG_DMA5_ADDRSTART)                 /* DMA5 Start Address of Current Buffer */
-#define pREG_DMA5_CFG                    ((volatile uint32_t *)REG_DMA5_CFG)                     /* DMA5 Configuration Register */
-#define pREG_DMA5_XCNT                   ((volatile uint32_t *)REG_DMA5_XCNT)                    /* DMA5 Inner Loop Count Start Value */
-#define pREG_DMA5_XMOD                   ((volatile  int32_t *)REG_DMA5_XMOD)                    /* DMA5 Inner Loop Address Increment */
-#define pREG_DMA5_YCNT                   ((volatile uint32_t *)REG_DMA5_YCNT)                    /* DMA5 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA5_YMOD                   ((volatile  int32_t *)REG_DMA5_YMOD)                    /* DMA5 Outer Loop Address Increment (2D only) */
-#define pREG_DMA5_DSCPTR_CUR             ((void * volatile *)REG_DMA5_DSCPTR_CUR)                /* DMA5 Current Descriptor Pointer */
-#define pREG_DMA5_DSCPTR_PRV             ((void * volatile *)REG_DMA5_DSCPTR_PRV)                /* DMA5 Previous Initial Descriptor Pointer */
-#define pREG_DMA5_ADDR_CUR               ((void * volatile *)REG_DMA5_ADDR_CUR)                  /* DMA5 Current Address */
-#define pREG_DMA5_STAT                   ((volatile uint32_t *)REG_DMA5_STAT)                    /* DMA5 Status Register */
-#define pREG_DMA5_XCNT_CUR               ((volatile uint32_t *)REG_DMA5_XCNT_CUR)                /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA5_YCNT_CUR               ((volatile uint32_t *)REG_DMA5_YCNT_CUR)                /* DMA5 Current Row Count (2D only) */
-#define pREG_DMA5_BWLCNT                 ((volatile uint32_t *)REG_DMA5_BWLCNT)                  /* DMA5 Bandwidth Limit Count */
-#define pREG_DMA5_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWLCNT_CUR)              /* DMA5 Bandwidth Limit Count Current */
-#define pREG_DMA5_BWMCNT                 ((volatile uint32_t *)REG_DMA5_BWMCNT)                  /* DMA5 Bandwidth Monitor Count */
-#define pREG_DMA5_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWMCNT_CUR)              /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA6
-   ========================================================================= */
-#define pREG_DMA6_DSCPTR_NXT             ((void * volatile *)REG_DMA6_DSCPTR_NXT)                /* DMA6 Pointer to Next Initial Descriptor */
-#define pREG_DMA6_ADDRSTART              ((void * volatile *)REG_DMA6_ADDRSTART)                 /* DMA6 Start Address of Current Buffer */
-#define pREG_DMA6_CFG                    ((volatile uint32_t *)REG_DMA6_CFG)                     /* DMA6 Configuration Register */
-#define pREG_DMA6_XCNT                   ((volatile uint32_t *)REG_DMA6_XCNT)                    /* DMA6 Inner Loop Count Start Value */
-#define pREG_DMA6_XMOD                   ((volatile  int32_t *)REG_DMA6_XMOD)                    /* DMA6 Inner Loop Address Increment */
-#define pREG_DMA6_YCNT                   ((volatile uint32_t *)REG_DMA6_YCNT)                    /* DMA6 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA6_YMOD                   ((volatile  int32_t *)REG_DMA6_YMOD)                    /* DMA6 Outer Loop Address Increment (2D only) */
-#define pREG_DMA6_DSCPTR_CUR             ((void * volatile *)REG_DMA6_DSCPTR_CUR)                /* DMA6 Current Descriptor Pointer */
-#define pREG_DMA6_DSCPTR_PRV             ((void * volatile *)REG_DMA6_DSCPTR_PRV)                /* DMA6 Previous Initial Descriptor Pointer */
-#define pREG_DMA6_ADDR_CUR               ((void * volatile *)REG_DMA6_ADDR_CUR)                  /* DMA6 Current Address */
-#define pREG_DMA6_STAT                   ((volatile uint32_t *)REG_DMA6_STAT)                    /* DMA6 Status Register */
-#define pREG_DMA6_XCNT_CUR               ((volatile uint32_t *)REG_DMA6_XCNT_CUR)                /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA6_YCNT_CUR               ((volatile uint32_t *)REG_DMA6_YCNT_CUR)                /* DMA6 Current Row Count (2D only) */
-#define pREG_DMA6_BWLCNT                 ((volatile uint32_t *)REG_DMA6_BWLCNT)                  /* DMA6 Bandwidth Limit Count */
-#define pREG_DMA6_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWLCNT_CUR)              /* DMA6 Bandwidth Limit Count Current */
-#define pREG_DMA6_BWMCNT                 ((volatile uint32_t *)REG_DMA6_BWMCNT)                  /* DMA6 Bandwidth Monitor Count */
-#define pREG_DMA6_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWMCNT_CUR)              /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA7
-   ========================================================================= */
-#define pREG_DMA7_DSCPTR_NXT             ((void * volatile *)REG_DMA7_DSCPTR_NXT)                /* DMA7 Pointer to Next Initial Descriptor */
-#define pREG_DMA7_ADDRSTART              ((void * volatile *)REG_DMA7_ADDRSTART)                 /* DMA7 Start Address of Current Buffer */
-#define pREG_DMA7_CFG                    ((volatile uint32_t *)REG_DMA7_CFG)                     /* DMA7 Configuration Register */
-#define pREG_DMA7_XCNT                   ((volatile uint32_t *)REG_DMA7_XCNT)                    /* DMA7 Inner Loop Count Start Value */
-#define pREG_DMA7_XMOD                   ((volatile  int32_t *)REG_DMA7_XMOD)                    /* DMA7 Inner Loop Address Increment */
-#define pREG_DMA7_YCNT                   ((volatile uint32_t *)REG_DMA7_YCNT)                    /* DMA7 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA7_YMOD                   ((volatile  int32_t *)REG_DMA7_YMOD)                    /* DMA7 Outer Loop Address Increment (2D only) */
-#define pREG_DMA7_DSCPTR_CUR             ((void * volatile *)REG_DMA7_DSCPTR_CUR)                /* DMA7 Current Descriptor Pointer */
-#define pREG_DMA7_DSCPTR_PRV             ((void * volatile *)REG_DMA7_DSCPTR_PRV)                /* DMA7 Previous Initial Descriptor Pointer */
-#define pREG_DMA7_ADDR_CUR               ((void * volatile *)REG_DMA7_ADDR_CUR)                  /* DMA7 Current Address */
-#define pREG_DMA7_STAT                   ((volatile uint32_t *)REG_DMA7_STAT)                    /* DMA7 Status Register */
-#define pREG_DMA7_XCNT_CUR               ((volatile uint32_t *)REG_DMA7_XCNT_CUR)                /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA7_YCNT_CUR               ((volatile uint32_t *)REG_DMA7_YCNT_CUR)                /* DMA7 Current Row Count (2D only) */
-#define pREG_DMA7_BWLCNT                 ((volatile uint32_t *)REG_DMA7_BWLCNT)                  /* DMA7 Bandwidth Limit Count */
-#define pREG_DMA7_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWLCNT_CUR)              /* DMA7 Bandwidth Limit Count Current */
-#define pREG_DMA7_BWMCNT                 ((volatile uint32_t *)REG_DMA7_BWMCNT)                  /* DMA7 Bandwidth Monitor Count */
-#define pREG_DMA7_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWMCNT_CUR)              /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA8
-   ========================================================================= */
-#define pREG_DMA8_DSCPTR_NXT             ((void * volatile *)REG_DMA8_DSCPTR_NXT)                /* DMA8 Pointer to Next Initial Descriptor */
-#define pREG_DMA8_ADDRSTART              ((void * volatile *)REG_DMA8_ADDRSTART)                 /* DMA8 Start Address of Current Buffer */
-#define pREG_DMA8_CFG                    ((volatile uint32_t *)REG_DMA8_CFG)                     /* DMA8 Configuration Register */
-#define pREG_DMA8_XCNT                   ((volatile uint32_t *)REG_DMA8_XCNT)                    /* DMA8 Inner Loop Count Start Value */
-#define pREG_DMA8_XMOD                   ((volatile  int32_t *)REG_DMA8_XMOD)                    /* DMA8 Inner Loop Address Increment */
-#define pREG_DMA8_YCNT                   ((volatile uint32_t *)REG_DMA8_YCNT)                    /* DMA8 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA8_YMOD                   ((volatile  int32_t *)REG_DMA8_YMOD)                    /* DMA8 Outer Loop Address Increment (2D only) */
-#define pREG_DMA8_DSCPTR_CUR             ((void * volatile *)REG_DMA8_DSCPTR_CUR)                /* DMA8 Current Descriptor Pointer */
-#define pREG_DMA8_DSCPTR_PRV             ((void * volatile *)REG_DMA8_DSCPTR_PRV)                /* DMA8 Previous Initial Descriptor Pointer */
-#define pREG_DMA8_ADDR_CUR               ((void * volatile *)REG_DMA8_ADDR_CUR)                  /* DMA8 Current Address */
-#define pREG_DMA8_STAT                   ((volatile uint32_t *)REG_DMA8_STAT)                    /* DMA8 Status Register */
-#define pREG_DMA8_XCNT_CUR               ((volatile uint32_t *)REG_DMA8_XCNT_CUR)                /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA8_YCNT_CUR               ((volatile uint32_t *)REG_DMA8_YCNT_CUR)                /* DMA8 Current Row Count (2D only) */
-#define pREG_DMA8_BWLCNT                 ((volatile uint32_t *)REG_DMA8_BWLCNT)                  /* DMA8 Bandwidth Limit Count */
-#define pREG_DMA8_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWLCNT_CUR)              /* DMA8 Bandwidth Limit Count Current */
-#define pREG_DMA8_BWMCNT                 ((volatile uint32_t *)REG_DMA8_BWMCNT)                  /* DMA8 Bandwidth Monitor Count */
-#define pREG_DMA8_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWMCNT_CUR)              /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA9
-   ========================================================================= */
-#define pREG_DMA9_DSCPTR_NXT             ((void * volatile *)REG_DMA9_DSCPTR_NXT)                /* DMA9 Pointer to Next Initial Descriptor */
-#define pREG_DMA9_ADDRSTART              ((void * volatile *)REG_DMA9_ADDRSTART)                 /* DMA9 Start Address of Current Buffer */
-#define pREG_DMA9_CFG                    ((volatile uint32_t *)REG_DMA9_CFG)                     /* DMA9 Configuration Register */
-#define pREG_DMA9_XCNT                   ((volatile uint32_t *)REG_DMA9_XCNT)                    /* DMA9 Inner Loop Count Start Value */
-#define pREG_DMA9_XMOD                   ((volatile  int32_t *)REG_DMA9_XMOD)                    /* DMA9 Inner Loop Address Increment */
-#define pREG_DMA9_YCNT                   ((volatile uint32_t *)REG_DMA9_YCNT)                    /* DMA9 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA9_YMOD                   ((volatile  int32_t *)REG_DMA9_YMOD)                    /* DMA9 Outer Loop Address Increment (2D only) */
-#define pREG_DMA9_DSCPTR_CUR             ((void * volatile *)REG_DMA9_DSCPTR_CUR)                /* DMA9 Current Descriptor Pointer */
-#define pREG_DMA9_DSCPTR_PRV             ((void * volatile *)REG_DMA9_DSCPTR_PRV)                /* DMA9 Previous Initial Descriptor Pointer */
-#define pREG_DMA9_ADDR_CUR               ((void * volatile *)REG_DMA9_ADDR_CUR)                  /* DMA9 Current Address */
-#define pREG_DMA9_STAT                   ((volatile uint32_t *)REG_DMA9_STAT)                    /* DMA9 Status Register */
-#define pREG_DMA9_XCNT_CUR               ((volatile uint32_t *)REG_DMA9_XCNT_CUR)                /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA9_YCNT_CUR               ((volatile uint32_t *)REG_DMA9_YCNT_CUR)                /* DMA9 Current Row Count (2D only) */
-#define pREG_DMA9_BWLCNT                 ((volatile uint32_t *)REG_DMA9_BWLCNT)                  /* DMA9 Bandwidth Limit Count */
-#define pREG_DMA9_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWLCNT_CUR)              /* DMA9 Bandwidth Limit Count Current */
-#define pREG_DMA9_BWMCNT                 ((volatile uint32_t *)REG_DMA9_BWMCNT)                  /* DMA9 Bandwidth Monitor Count */
-#define pREG_DMA9_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWMCNT_CUR)              /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA10
-   ========================================================================= */
-#define pREG_DMA10_DSCPTR_NXT            ((void * volatile *)REG_DMA10_DSCPTR_NXT)               /* DMA10 Pointer to Next Initial Descriptor */
-#define pREG_DMA10_ADDRSTART             ((void * volatile *)REG_DMA10_ADDRSTART)                /* DMA10 Start Address of Current Buffer */
-#define pREG_DMA10_CFG                   ((volatile uint32_t *)REG_DMA10_CFG)                    /* DMA10 Configuration Register */
-#define pREG_DMA10_XCNT                  ((volatile uint32_t *)REG_DMA10_XCNT)                   /* DMA10 Inner Loop Count Start Value */
-#define pREG_DMA10_XMOD                  ((volatile  int32_t *)REG_DMA10_XMOD)                   /* DMA10 Inner Loop Address Increment */
-#define pREG_DMA10_YCNT                  ((volatile uint32_t *)REG_DMA10_YCNT)                   /* DMA10 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA10_YMOD                  ((volatile  int32_t *)REG_DMA10_YMOD)                   /* DMA10 Outer Loop Address Increment (2D only) */
-#define pREG_DMA10_DSCPTR_CUR            ((void * volatile *)REG_DMA10_DSCPTR_CUR)               /* DMA10 Current Descriptor Pointer */
-#define pREG_DMA10_DSCPTR_PRV            ((void * volatile *)REG_DMA10_DSCPTR_PRV)               /* DMA10 Previous Initial Descriptor Pointer */
-#define pREG_DMA10_ADDR_CUR              ((void * volatile *)REG_DMA10_ADDR_CUR)                 /* DMA10 Current Address */
-#define pREG_DMA10_STAT                  ((volatile uint32_t *)REG_DMA10_STAT)                   /* DMA10 Status Register */
-#define pREG_DMA10_XCNT_CUR              ((volatile uint32_t *)REG_DMA10_XCNT_CUR)               /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA10_YCNT_CUR              ((volatile uint32_t *)REG_DMA10_YCNT_CUR)               /* DMA10 Current Row Count (2D only) */
-#define pREG_DMA10_BWLCNT                ((volatile uint32_t *)REG_DMA10_BWLCNT)                 /* DMA10 Bandwidth Limit Count */
-#define pREG_DMA10_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWLCNT_CUR)             /* DMA10 Bandwidth Limit Count Current */
-#define pREG_DMA10_BWMCNT                ((volatile uint32_t *)REG_DMA10_BWMCNT)                 /* DMA10 Bandwidth Monitor Count */
-#define pREG_DMA10_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWMCNT_CUR)             /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA11
-   ========================================================================= */
-#define pREG_DMA11_DSCPTR_NXT            ((void * volatile *)REG_DMA11_DSCPTR_NXT)               /* DMA11 Pointer to Next Initial Descriptor */
-#define pREG_DMA11_ADDRSTART             ((void * volatile *)REG_DMA11_ADDRSTART)                /* DMA11 Start Address of Current Buffer */
-#define pREG_DMA11_CFG                   ((volatile uint32_t *)REG_DMA11_CFG)                    /* DMA11 Configuration Register */
-#define pREG_DMA11_XCNT                  ((volatile uint32_t *)REG_DMA11_XCNT)                   /* DMA11 Inner Loop Count Start Value */
-#define pREG_DMA11_XMOD                  ((volatile  int32_t *)REG_DMA11_XMOD)                   /* DMA11 Inner Loop Address Increment */
-#define pREG_DMA11_YCNT                  ((volatile uint32_t *)REG_DMA11_YCNT)                   /* DMA11 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA11_YMOD                  ((volatile  int32_t *)REG_DMA11_YMOD)                   /* DMA11 Outer Loop Address Increment (2D only) */
-#define pREG_DMA11_DSCPTR_CUR            ((void * volatile *)REG_DMA11_DSCPTR_CUR)               /* DMA11 Current Descriptor Pointer */
-#define pREG_DMA11_DSCPTR_PRV            ((void * volatile *)REG_DMA11_DSCPTR_PRV)               /* DMA11 Previous Initial Descriptor Pointer */
-#define pREG_DMA11_ADDR_CUR              ((void * volatile *)REG_DMA11_ADDR_CUR)                 /* DMA11 Current Address */
-#define pREG_DMA11_STAT                  ((volatile uint32_t *)REG_DMA11_STAT)                   /* DMA11 Status Register */
-#define pREG_DMA11_XCNT_CUR              ((volatile uint32_t *)REG_DMA11_XCNT_CUR)               /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA11_YCNT_CUR              ((volatile uint32_t *)REG_DMA11_YCNT_CUR)               /* DMA11 Current Row Count (2D only) */
-#define pREG_DMA11_BWLCNT                ((volatile uint32_t *)REG_DMA11_BWLCNT)                 /* DMA11 Bandwidth Limit Count */
-#define pREG_DMA11_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWLCNT_CUR)             /* DMA11 Bandwidth Limit Count Current */
-#define pREG_DMA11_BWMCNT                ((volatile uint32_t *)REG_DMA11_BWMCNT)                 /* DMA11 Bandwidth Monitor Count */
-#define pREG_DMA11_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWMCNT_CUR)             /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA12
-   ========================================================================= */
-#define pREG_DMA12_DSCPTR_NXT            ((void * volatile *)REG_DMA12_DSCPTR_NXT)               /* DMA12 Pointer to Next Initial Descriptor */
-#define pREG_DMA12_ADDRSTART             ((void * volatile *)REG_DMA12_ADDRSTART)                /* DMA12 Start Address of Current Buffer */
-#define pREG_DMA12_CFG                   ((volatile uint32_t *)REG_DMA12_CFG)                    /* DMA12 Configuration Register */
-#define pREG_DMA12_XCNT                  ((volatile uint32_t *)REG_DMA12_XCNT)                   /* DMA12 Inner Loop Count Start Value */
-#define pREG_DMA12_XMOD                  ((volatile  int32_t *)REG_DMA12_XMOD)                   /* DMA12 Inner Loop Address Increment */
-#define pREG_DMA12_YCNT                  ((volatile uint32_t *)REG_DMA12_YCNT)                   /* DMA12 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA12_YMOD                  ((volatile  int32_t *)REG_DMA12_YMOD)                   /* DMA12 Outer Loop Address Increment (2D only) */
-#define pREG_DMA12_DSCPTR_CUR            ((void * volatile *)REG_DMA12_DSCPTR_CUR)               /* DMA12 Current Descriptor Pointer */
-#define pREG_DMA12_DSCPTR_PRV            ((void * volatile *)REG_DMA12_DSCPTR_PRV)               /* DMA12 Previous Initial Descriptor Pointer */
-#define pREG_DMA12_ADDR_CUR              ((void * volatile *)REG_DMA12_ADDR_CUR)                 /* DMA12 Current Address */
-#define pREG_DMA12_STAT                  ((volatile uint32_t *)REG_DMA12_STAT)                   /* DMA12 Status Register */
-#define pREG_DMA12_XCNT_CUR              ((volatile uint32_t *)REG_DMA12_XCNT_CUR)               /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA12_YCNT_CUR              ((volatile uint32_t *)REG_DMA12_YCNT_CUR)               /* DMA12 Current Row Count (2D only) */
-#define pREG_DMA12_BWLCNT                ((volatile uint32_t *)REG_DMA12_BWLCNT)                 /* DMA12 Bandwidth Limit Count */
-#define pREG_DMA12_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWLCNT_CUR)             /* DMA12 Bandwidth Limit Count Current */
-#define pREG_DMA12_BWMCNT                ((volatile uint32_t *)REG_DMA12_BWMCNT)                 /* DMA12 Bandwidth Monitor Count */
-#define pREG_DMA12_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWMCNT_CUR)             /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA13
-   ========================================================================= */
-#define pREG_DMA13_DSCPTR_NXT            ((void * volatile *)REG_DMA13_DSCPTR_NXT)               /* DMA13 Pointer to Next Initial Descriptor */
-#define pREG_DMA13_ADDRSTART             ((void * volatile *)REG_DMA13_ADDRSTART)                /* DMA13 Start Address of Current Buffer */
-#define pREG_DMA13_CFG                   ((volatile uint32_t *)REG_DMA13_CFG)                    /* DMA13 Configuration Register */
-#define pREG_DMA13_XCNT                  ((volatile uint32_t *)REG_DMA13_XCNT)                   /* DMA13 Inner Loop Count Start Value */
-#define pREG_DMA13_XMOD                  ((volatile  int32_t *)REG_DMA13_XMOD)                   /* DMA13 Inner Loop Address Increment */
-#define pREG_DMA13_YCNT                  ((volatile uint32_t *)REG_DMA13_YCNT)                   /* DMA13 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA13_YMOD                  ((volatile  int32_t *)REG_DMA13_YMOD)                   /* DMA13 Outer Loop Address Increment (2D only) */
-#define pREG_DMA13_DSCPTR_CUR            ((void * volatile *)REG_DMA13_DSCPTR_CUR)               /* DMA13 Current Descriptor Pointer */
-#define pREG_DMA13_DSCPTR_PRV            ((void * volatile *)REG_DMA13_DSCPTR_PRV)               /* DMA13 Previous Initial Descriptor Pointer */
-#define pREG_DMA13_ADDR_CUR              ((void * volatile *)REG_DMA13_ADDR_CUR)                 /* DMA13 Current Address */
-#define pREG_DMA13_STAT                  ((volatile uint32_t *)REG_DMA13_STAT)                   /* DMA13 Status Register */
-#define pREG_DMA13_XCNT_CUR              ((volatile uint32_t *)REG_DMA13_XCNT_CUR)               /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA13_YCNT_CUR              ((volatile uint32_t *)REG_DMA13_YCNT_CUR)               /* DMA13 Current Row Count (2D only) */
-#define pREG_DMA13_BWLCNT                ((volatile uint32_t *)REG_DMA13_BWLCNT)                 /* DMA13 Bandwidth Limit Count */
-#define pREG_DMA13_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWLCNT_CUR)             /* DMA13 Bandwidth Limit Count Current */
-#define pREG_DMA13_BWMCNT                ((volatile uint32_t *)REG_DMA13_BWMCNT)                 /* DMA13 Bandwidth Monitor Count */
-#define pREG_DMA13_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWMCNT_CUR)             /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA14
-   ========================================================================= */
-#define pREG_DMA14_DSCPTR_NXT            ((void * volatile *)REG_DMA14_DSCPTR_NXT)               /* DMA14 Pointer to Next Initial Descriptor */
-#define pREG_DMA14_ADDRSTART             ((void * volatile *)REG_DMA14_ADDRSTART)                /* DMA14 Start Address of Current Buffer */
-#define pREG_DMA14_CFG                   ((volatile uint32_t *)REG_DMA14_CFG)                    /* DMA14 Configuration Register */
-#define pREG_DMA14_XCNT                  ((volatile uint32_t *)REG_DMA14_XCNT)                   /* DMA14 Inner Loop Count Start Value */
-#define pREG_DMA14_XMOD                  ((volatile  int32_t *)REG_DMA14_XMOD)                   /* DMA14 Inner Loop Address Increment */
-#define pREG_DMA14_YCNT                  ((volatile uint32_t *)REG_DMA14_YCNT)                   /* DMA14 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA14_YMOD                  ((volatile  int32_t *)REG_DMA14_YMOD)                   /* DMA14 Outer Loop Address Increment (2D only) */
-#define pREG_DMA14_DSCPTR_CUR            ((void * volatile *)REG_DMA14_DSCPTR_CUR)               /* DMA14 Current Descriptor Pointer */
-#define pREG_DMA14_DSCPTR_PRV            ((void * volatile *)REG_DMA14_DSCPTR_PRV)               /* DMA14 Previous Initial Descriptor Pointer */
-#define pREG_DMA14_ADDR_CUR              ((void * volatile *)REG_DMA14_ADDR_CUR)                 /* DMA14 Current Address */
-#define pREG_DMA14_STAT                  ((volatile uint32_t *)REG_DMA14_STAT)                   /* DMA14 Status Register */
-#define pREG_DMA14_XCNT_CUR              ((volatile uint32_t *)REG_DMA14_XCNT_CUR)               /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA14_YCNT_CUR              ((volatile uint32_t *)REG_DMA14_YCNT_CUR)               /* DMA14 Current Row Count (2D only) */
-#define pREG_DMA14_BWLCNT                ((volatile uint32_t *)REG_DMA14_BWLCNT)                 /* DMA14 Bandwidth Limit Count */
-#define pREG_DMA14_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWLCNT_CUR)             /* DMA14 Bandwidth Limit Count Current */
-#define pREG_DMA14_BWMCNT                ((volatile uint32_t *)REG_DMA14_BWMCNT)                 /* DMA14 Bandwidth Monitor Count */
-#define pREG_DMA14_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWMCNT_CUR)             /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA15
-   ========================================================================= */
-#define pREG_DMA15_DSCPTR_NXT            ((void * volatile *)REG_DMA15_DSCPTR_NXT)               /* DMA15 Pointer to Next Initial Descriptor */
-#define pREG_DMA15_ADDRSTART             ((void * volatile *)REG_DMA15_ADDRSTART)                /* DMA15 Start Address of Current Buffer */
-#define pREG_DMA15_CFG                   ((volatile uint32_t *)REG_DMA15_CFG)                    /* DMA15 Configuration Register */
-#define pREG_DMA15_XCNT                  ((volatile uint32_t *)REG_DMA15_XCNT)                   /* DMA15 Inner Loop Count Start Value */
-#define pREG_DMA15_XMOD                  ((volatile  int32_t *)REG_DMA15_XMOD)                   /* DMA15 Inner Loop Address Increment */
-#define pREG_DMA15_YCNT                  ((volatile uint32_t *)REG_DMA15_YCNT)                   /* DMA15 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA15_YMOD                  ((volatile  int32_t *)REG_DMA15_YMOD)                   /* DMA15 Outer Loop Address Increment (2D only) */
-#define pREG_DMA15_DSCPTR_CUR            ((void * volatile *)REG_DMA15_DSCPTR_CUR)               /* DMA15 Current Descriptor Pointer */
-#define pREG_DMA15_DSCPTR_PRV            ((void * volatile *)REG_DMA15_DSCPTR_PRV)               /* DMA15 Previous Initial Descriptor Pointer */
-#define pREG_DMA15_ADDR_CUR              ((void * volatile *)REG_DMA15_ADDR_CUR)                 /* DMA15 Current Address */
-#define pREG_DMA15_STAT                  ((volatile uint32_t *)REG_DMA15_STAT)                   /* DMA15 Status Register */
-#define pREG_DMA15_XCNT_CUR              ((volatile uint32_t *)REG_DMA15_XCNT_CUR)               /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA15_YCNT_CUR              ((volatile uint32_t *)REG_DMA15_YCNT_CUR)               /* DMA15 Current Row Count (2D only) */
-#define pREG_DMA15_BWLCNT                ((volatile uint32_t *)REG_DMA15_BWLCNT)                 /* DMA15 Bandwidth Limit Count */
-#define pREG_DMA15_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWLCNT_CUR)             /* DMA15 Bandwidth Limit Count Current */
-#define pREG_DMA15_BWMCNT                ((volatile uint32_t *)REG_DMA15_BWMCNT)                 /* DMA15 Bandwidth Monitor Count */
-#define pREG_DMA15_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWMCNT_CUR)             /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA16
-   ========================================================================= */
-#define pREG_DMA16_DSCPTR_NXT            ((void * volatile *)REG_DMA16_DSCPTR_NXT)               /* DMA16 Pointer to Next Initial Descriptor */
-#define pREG_DMA16_ADDRSTART             ((void * volatile *)REG_DMA16_ADDRSTART)                /* DMA16 Start Address of Current Buffer */
-#define pREG_DMA16_CFG                   ((volatile uint32_t *)REG_DMA16_CFG)                    /* DMA16 Configuration Register */
-#define pREG_DMA16_XCNT                  ((volatile uint32_t *)REG_DMA16_XCNT)                   /* DMA16 Inner Loop Count Start Value */
-#define pREG_DMA16_XMOD                  ((volatile  int32_t *)REG_DMA16_XMOD)                   /* DMA16 Inner Loop Address Increment */
-#define pREG_DMA16_YCNT                  ((volatile uint32_t *)REG_DMA16_YCNT)                   /* DMA16 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA16_YMOD                  ((volatile  int32_t *)REG_DMA16_YMOD)                   /* DMA16 Outer Loop Address Increment (2D only) */
-#define pREG_DMA16_DSCPTR_CUR            ((void * volatile *)REG_DMA16_DSCPTR_CUR)               /* DMA16 Current Descriptor Pointer */
-#define pREG_DMA16_DSCPTR_PRV            ((void * volatile *)REG_DMA16_DSCPTR_PRV)               /* DMA16 Previous Initial Descriptor Pointer */
-#define pREG_DMA16_ADDR_CUR              ((void * volatile *)REG_DMA16_ADDR_CUR)                 /* DMA16 Current Address */
-#define pREG_DMA16_STAT                  ((volatile uint32_t *)REG_DMA16_STAT)                   /* DMA16 Status Register */
-#define pREG_DMA16_XCNT_CUR              ((volatile uint32_t *)REG_DMA16_XCNT_CUR)               /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA16_YCNT_CUR              ((volatile uint32_t *)REG_DMA16_YCNT_CUR)               /* DMA16 Current Row Count (2D only) */
-#define pREG_DMA16_BWLCNT                ((volatile uint32_t *)REG_DMA16_BWLCNT)                 /* DMA16 Bandwidth Limit Count */
-#define pREG_DMA16_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWLCNT_CUR)             /* DMA16 Bandwidth Limit Count Current */
-#define pREG_DMA16_BWMCNT                ((volatile uint32_t *)REG_DMA16_BWMCNT)                 /* DMA16 Bandwidth Monitor Count */
-#define pREG_DMA16_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWMCNT_CUR)             /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA17
-   ========================================================================= */
-#define pREG_DMA17_DSCPTR_NXT            ((void * volatile *)REG_DMA17_DSCPTR_NXT)               /* DMA17 Pointer to Next Initial Descriptor */
-#define pREG_DMA17_ADDRSTART             ((void * volatile *)REG_DMA17_ADDRSTART)                /* DMA17 Start Address of Current Buffer */
-#define pREG_DMA17_CFG                   ((volatile uint32_t *)REG_DMA17_CFG)                    /* DMA17 Configuration Register */
-#define pREG_DMA17_XCNT                  ((volatile uint32_t *)REG_DMA17_XCNT)                   /* DMA17 Inner Loop Count Start Value */
-#define pREG_DMA17_XMOD                  ((volatile  int32_t *)REG_DMA17_XMOD)                   /* DMA17 Inner Loop Address Increment */
-#define pREG_DMA17_YCNT                  ((volatile uint32_t *)REG_DMA17_YCNT)                   /* DMA17 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA17_YMOD                  ((volatile  int32_t *)REG_DMA17_YMOD)                   /* DMA17 Outer Loop Address Increment (2D only) */
-#define pREG_DMA17_DSCPTR_CUR            ((void * volatile *)REG_DMA17_DSCPTR_CUR)               /* DMA17 Current Descriptor Pointer */
-#define pREG_DMA17_DSCPTR_PRV            ((void * volatile *)REG_DMA17_DSCPTR_PRV)               /* DMA17 Previous Initial Descriptor Pointer */
-#define pREG_DMA17_ADDR_CUR              ((void * volatile *)REG_DMA17_ADDR_CUR)                 /* DMA17 Current Address */
-#define pREG_DMA17_STAT                  ((volatile uint32_t *)REG_DMA17_STAT)                   /* DMA17 Status Register */
-#define pREG_DMA17_XCNT_CUR              ((volatile uint32_t *)REG_DMA17_XCNT_CUR)               /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA17_YCNT_CUR              ((volatile uint32_t *)REG_DMA17_YCNT_CUR)               /* DMA17 Current Row Count (2D only) */
-#define pREG_DMA17_BWLCNT                ((volatile uint32_t *)REG_DMA17_BWLCNT)                 /* DMA17 Bandwidth Limit Count */
-#define pREG_DMA17_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWLCNT_CUR)             /* DMA17 Bandwidth Limit Count Current */
-#define pREG_DMA17_BWMCNT                ((volatile uint32_t *)REG_DMA17_BWMCNT)                 /* DMA17 Bandwidth Monitor Count */
-#define pREG_DMA17_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWMCNT_CUR)             /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA18
-   ========================================================================= */
-#define pREG_DMA18_DSCPTR_NXT            ((void * volatile *)REG_DMA18_DSCPTR_NXT)               /* DMA18 Pointer to Next Initial Descriptor */
-#define pREG_DMA18_ADDRSTART             ((void * volatile *)REG_DMA18_ADDRSTART)                /* DMA18 Start Address of Current Buffer */
-#define pREG_DMA18_CFG                   ((volatile uint32_t *)REG_DMA18_CFG)                    /* DMA18 Configuration Register */
-#define pREG_DMA18_XCNT                  ((volatile uint32_t *)REG_DMA18_XCNT)                   /* DMA18 Inner Loop Count Start Value */
-#define pREG_DMA18_XMOD                  ((volatile  int32_t *)REG_DMA18_XMOD)                   /* DMA18 Inner Loop Address Increment */
-#define pREG_DMA18_YCNT                  ((volatile uint32_t *)REG_DMA18_YCNT)                   /* DMA18 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA18_YMOD                  ((volatile  int32_t *)REG_DMA18_YMOD)                   /* DMA18 Outer Loop Address Increment (2D only) */
-#define pREG_DMA18_DSCPTR_CUR            ((void * volatile *)REG_DMA18_DSCPTR_CUR)               /* DMA18 Current Descriptor Pointer */
-#define pREG_DMA18_DSCPTR_PRV            ((void * volatile *)REG_DMA18_DSCPTR_PRV)               /* DMA18 Previous Initial Descriptor Pointer */
-#define pREG_DMA18_ADDR_CUR              ((void * volatile *)REG_DMA18_ADDR_CUR)                 /* DMA18 Current Address */
-#define pREG_DMA18_STAT                  ((volatile uint32_t *)REG_DMA18_STAT)                   /* DMA18 Status Register */
-#define pREG_DMA18_XCNT_CUR              ((volatile uint32_t *)REG_DMA18_XCNT_CUR)               /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA18_YCNT_CUR              ((volatile uint32_t *)REG_DMA18_YCNT_CUR)               /* DMA18 Current Row Count (2D only) */
-#define pREG_DMA18_BWLCNT                ((volatile uint32_t *)REG_DMA18_BWLCNT)                 /* DMA18 Bandwidth Limit Count */
-#define pREG_DMA18_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWLCNT_CUR)             /* DMA18 Bandwidth Limit Count Current */
-#define pREG_DMA18_BWMCNT                ((volatile uint32_t *)REG_DMA18_BWMCNT)                 /* DMA18 Bandwidth Monitor Count */
-#define pREG_DMA18_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWMCNT_CUR)             /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA19
-   ========================================================================= */
-#define pREG_DMA19_DSCPTR_NXT            ((void * volatile *)REG_DMA19_DSCPTR_NXT)               /* DMA19 Pointer to Next Initial Descriptor */
-#define pREG_DMA19_ADDRSTART             ((void * volatile *)REG_DMA19_ADDRSTART)                /* DMA19 Start Address of Current Buffer */
-#define pREG_DMA19_CFG                   ((volatile uint32_t *)REG_DMA19_CFG)                    /* DMA19 Configuration Register */
-#define pREG_DMA19_XCNT                  ((volatile uint32_t *)REG_DMA19_XCNT)                   /* DMA19 Inner Loop Count Start Value */
-#define pREG_DMA19_XMOD                  ((volatile  int32_t *)REG_DMA19_XMOD)                   /* DMA19 Inner Loop Address Increment */
-#define pREG_DMA19_YCNT                  ((volatile uint32_t *)REG_DMA19_YCNT)                   /* DMA19 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA19_YMOD                  ((volatile  int32_t *)REG_DMA19_YMOD)                   /* DMA19 Outer Loop Address Increment (2D only) */
-#define pREG_DMA19_DSCPTR_CUR            ((void * volatile *)REG_DMA19_DSCPTR_CUR)               /* DMA19 Current Descriptor Pointer */
-#define pREG_DMA19_DSCPTR_PRV            ((void * volatile *)REG_DMA19_DSCPTR_PRV)               /* DMA19 Previous Initial Descriptor Pointer */
-#define pREG_DMA19_ADDR_CUR              ((void * volatile *)REG_DMA19_ADDR_CUR)                 /* DMA19 Current Address */
-#define pREG_DMA19_STAT                  ((volatile uint32_t *)REG_DMA19_STAT)                   /* DMA19 Status Register */
-#define pREG_DMA19_XCNT_CUR              ((volatile uint32_t *)REG_DMA19_XCNT_CUR)               /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA19_YCNT_CUR              ((volatile uint32_t *)REG_DMA19_YCNT_CUR)               /* DMA19 Current Row Count (2D only) */
-#define pREG_DMA19_BWLCNT                ((volatile uint32_t *)REG_DMA19_BWLCNT)                 /* DMA19 Bandwidth Limit Count */
-#define pREG_DMA19_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWLCNT_CUR)             /* DMA19 Bandwidth Limit Count Current */
-#define pREG_DMA19_BWMCNT                ((volatile uint32_t *)REG_DMA19_BWMCNT)                 /* DMA19 Bandwidth Monitor Count */
-#define pREG_DMA19_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWMCNT_CUR)             /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA20
-   ========================================================================= */
-#define pREG_DMA20_DSCPTR_NXT            ((void * volatile *)REG_DMA20_DSCPTR_NXT)               /* DMA20 Pointer to Next Initial Descriptor */
-#define pREG_DMA20_ADDRSTART             ((void * volatile *)REG_DMA20_ADDRSTART)                /* DMA20 Start Address of Current Buffer */
-#define pREG_DMA20_CFG                   ((volatile uint32_t *)REG_DMA20_CFG)                    /* DMA20 Configuration Register */
-#define pREG_DMA20_XCNT                  ((volatile uint32_t *)REG_DMA20_XCNT)                   /* DMA20 Inner Loop Count Start Value */
-#define pREG_DMA20_XMOD                  ((volatile  int32_t *)REG_DMA20_XMOD)                   /* DMA20 Inner Loop Address Increment */
-#define pREG_DMA20_YCNT                  ((volatile uint32_t *)REG_DMA20_YCNT)                   /* DMA20 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA20_YMOD                  ((volatile  int32_t *)REG_DMA20_YMOD)                   /* DMA20 Outer Loop Address Increment (2D only) */
-#define pREG_DMA20_DSCPTR_CUR            ((void * volatile *)REG_DMA20_DSCPTR_CUR)               /* DMA20 Current Descriptor Pointer */
-#define pREG_DMA20_DSCPTR_PRV            ((void * volatile *)REG_DMA20_DSCPTR_PRV)               /* DMA20 Previous Initial Descriptor Pointer */
-#define pREG_DMA20_ADDR_CUR              ((void * volatile *)REG_DMA20_ADDR_CUR)                 /* DMA20 Current Address */
-#define pREG_DMA20_STAT                  ((volatile uint32_t *)REG_DMA20_STAT)                   /* DMA20 Status Register */
-#define pREG_DMA20_XCNT_CUR              ((volatile uint32_t *)REG_DMA20_XCNT_CUR)               /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA20_YCNT_CUR              ((volatile uint32_t *)REG_DMA20_YCNT_CUR)               /* DMA20 Current Row Count (2D only) */
-#define pREG_DMA20_BWLCNT                ((volatile uint32_t *)REG_DMA20_BWLCNT)                 /* DMA20 Bandwidth Limit Count */
-#define pREG_DMA20_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWLCNT_CUR)             /* DMA20 Bandwidth Limit Count Current */
-#define pREG_DMA20_BWMCNT                ((volatile uint32_t *)REG_DMA20_BWMCNT)                 /* DMA20 Bandwidth Monitor Count */
-#define pREG_DMA20_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWMCNT_CUR)             /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA21
-   ========================================================================= */
-#define pREG_DMA21_DSCPTR_NXT            ((void * volatile *)REG_DMA21_DSCPTR_NXT)               /* DMA21 Pointer to Next Initial Descriptor */
-#define pREG_DMA21_ADDRSTART             ((void * volatile *)REG_DMA21_ADDRSTART)                /* DMA21 Start Address of Current Buffer */
-#define pREG_DMA21_CFG                   ((volatile uint32_t *)REG_DMA21_CFG)                    /* DMA21 Configuration Register */
-#define pREG_DMA21_XCNT                  ((volatile uint32_t *)REG_DMA21_XCNT)                   /* DMA21 Inner Loop Count Start Value */
-#define pREG_DMA21_XMOD                  ((volatile  int32_t *)REG_DMA21_XMOD)                   /* DMA21 Inner Loop Address Increment */
-#define pREG_DMA21_YCNT                  ((volatile uint32_t *)REG_DMA21_YCNT)                   /* DMA21 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA21_YMOD                  ((volatile  int32_t *)REG_DMA21_YMOD)                   /* DMA21 Outer Loop Address Increment (2D only) */
-#define pREG_DMA21_DSCPTR_CUR            ((void * volatile *)REG_DMA21_DSCPTR_CUR)               /* DMA21 Current Descriptor Pointer */
-#define pREG_DMA21_DSCPTR_PRV            ((void * volatile *)REG_DMA21_DSCPTR_PRV)               /* DMA21 Previous Initial Descriptor Pointer */
-#define pREG_DMA21_ADDR_CUR              ((void * volatile *)REG_DMA21_ADDR_CUR)                 /* DMA21 Current Address */
-#define pREG_DMA21_STAT                  ((volatile uint32_t *)REG_DMA21_STAT)                   /* DMA21 Status Register */
-#define pREG_DMA21_XCNT_CUR              ((volatile uint32_t *)REG_DMA21_XCNT_CUR)               /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA21_YCNT_CUR              ((volatile uint32_t *)REG_DMA21_YCNT_CUR)               /* DMA21 Current Row Count (2D only) */
-#define pREG_DMA21_BWLCNT                ((volatile uint32_t *)REG_DMA21_BWLCNT)                 /* DMA21 Bandwidth Limit Count */
-#define pREG_DMA21_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWLCNT_CUR)             /* DMA21 Bandwidth Limit Count Current */
-#define pREG_DMA21_BWMCNT                ((volatile uint32_t *)REG_DMA21_BWMCNT)                 /* DMA21 Bandwidth Monitor Count */
-#define pREG_DMA21_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWMCNT_CUR)             /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA22
-   ========================================================================= */
-#define pREG_DMA22_DSCPTR_NXT            ((void * volatile *)REG_DMA22_DSCPTR_NXT)               /* DMA22 Pointer to Next Initial Descriptor */
-#define pREG_DMA22_ADDRSTART             ((void * volatile *)REG_DMA22_ADDRSTART)                /* DMA22 Start Address of Current Buffer */
-#define pREG_DMA22_CFG                   ((volatile uint32_t *)REG_DMA22_CFG)                    /* DMA22 Configuration Register */
-#define pREG_DMA22_XCNT                  ((volatile uint32_t *)REG_DMA22_XCNT)                   /* DMA22 Inner Loop Count Start Value */
-#define pREG_DMA22_XMOD                  ((volatile  int32_t *)REG_DMA22_XMOD)                   /* DMA22 Inner Loop Address Increment */
-#define pREG_DMA22_YCNT                  ((volatile uint32_t *)REG_DMA22_YCNT)                   /* DMA22 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA22_YMOD                  ((volatile  int32_t *)REG_DMA22_YMOD)                   /* DMA22 Outer Loop Address Increment (2D only) */
-#define pREG_DMA22_DSCPTR_CUR            ((void * volatile *)REG_DMA22_DSCPTR_CUR)               /* DMA22 Current Descriptor Pointer */
-#define pREG_DMA22_DSCPTR_PRV            ((void * volatile *)REG_DMA22_DSCPTR_PRV)               /* DMA22 Previous Initial Descriptor Pointer */
-#define pREG_DMA22_ADDR_CUR              ((void * volatile *)REG_DMA22_ADDR_CUR)                 /* DMA22 Current Address */
-#define pREG_DMA22_STAT                  ((volatile uint32_t *)REG_DMA22_STAT)                   /* DMA22 Status Register */
-#define pREG_DMA22_XCNT_CUR              ((volatile uint32_t *)REG_DMA22_XCNT_CUR)               /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA22_YCNT_CUR              ((volatile uint32_t *)REG_DMA22_YCNT_CUR)               /* DMA22 Current Row Count (2D only) */
-#define pREG_DMA22_BWLCNT                ((volatile uint32_t *)REG_DMA22_BWLCNT)                 /* DMA22 Bandwidth Limit Count */
-#define pREG_DMA22_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWLCNT_CUR)             /* DMA22 Bandwidth Limit Count Current */
-#define pREG_DMA22_BWMCNT                ((volatile uint32_t *)REG_DMA22_BWMCNT)                 /* DMA22 Bandwidth Monitor Count */
-#define pREG_DMA22_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWMCNT_CUR)             /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA23
-   ========================================================================= */
-#define pREG_DMA23_DSCPTR_NXT            ((void * volatile *)REG_DMA23_DSCPTR_NXT)               /* DMA23 Pointer to Next Initial Descriptor */
-#define pREG_DMA23_ADDRSTART             ((void * volatile *)REG_DMA23_ADDRSTART)                /* DMA23 Start Address of Current Buffer */
-#define pREG_DMA23_CFG                   ((volatile uint32_t *)REG_DMA23_CFG)                    /* DMA23 Configuration Register */
-#define pREG_DMA23_XCNT                  ((volatile uint32_t *)REG_DMA23_XCNT)                   /* DMA23 Inner Loop Count Start Value */
-#define pREG_DMA23_XMOD                  ((volatile  int32_t *)REG_DMA23_XMOD)                   /* DMA23 Inner Loop Address Increment */
-#define pREG_DMA23_YCNT                  ((volatile uint32_t *)REG_DMA23_YCNT)                   /* DMA23 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA23_YMOD                  ((volatile  int32_t *)REG_DMA23_YMOD)                   /* DMA23 Outer Loop Address Increment (2D only) */
-#define pREG_DMA23_DSCPTR_CUR            ((void * volatile *)REG_DMA23_DSCPTR_CUR)               /* DMA23 Current Descriptor Pointer */
-#define pREG_DMA23_DSCPTR_PRV            ((void * volatile *)REG_DMA23_DSCPTR_PRV)               /* DMA23 Previous Initial Descriptor Pointer */
-#define pREG_DMA23_ADDR_CUR              ((void * volatile *)REG_DMA23_ADDR_CUR)                 /* DMA23 Current Address */
-#define pREG_DMA23_STAT                  ((volatile uint32_t *)REG_DMA23_STAT)                   /* DMA23 Status Register */
-#define pREG_DMA23_XCNT_CUR              ((volatile uint32_t *)REG_DMA23_XCNT_CUR)               /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA23_YCNT_CUR              ((volatile uint32_t *)REG_DMA23_YCNT_CUR)               /* DMA23 Current Row Count (2D only) */
-#define pREG_DMA23_BWLCNT                ((volatile uint32_t *)REG_DMA23_BWLCNT)                 /* DMA23 Bandwidth Limit Count */
-#define pREG_DMA23_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWLCNT_CUR)             /* DMA23 Bandwidth Limit Count Current */
-#define pREG_DMA23_BWMCNT                ((volatile uint32_t *)REG_DMA23_BWMCNT)                 /* DMA23 Bandwidth Monitor Count */
-#define pREG_DMA23_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWMCNT_CUR)             /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA24
-   ========================================================================= */
-#define pREG_DMA24_DSCPTR_NXT            ((void * volatile *)REG_DMA24_DSCPTR_NXT)               /* DMA24 Pointer to Next Initial Descriptor */
-#define pREG_DMA24_ADDRSTART             ((void * volatile *)REG_DMA24_ADDRSTART)                /* DMA24 Start Address of Current Buffer */
-#define pREG_DMA24_CFG                   ((volatile uint32_t *)REG_DMA24_CFG)                    /* DMA24 Configuration Register */
-#define pREG_DMA24_XCNT                  ((volatile uint32_t *)REG_DMA24_XCNT)                   /* DMA24 Inner Loop Count Start Value */
-#define pREG_DMA24_XMOD                  ((volatile  int32_t *)REG_DMA24_XMOD)                   /* DMA24 Inner Loop Address Increment */
-#define pREG_DMA24_YCNT                  ((volatile uint32_t *)REG_DMA24_YCNT)                   /* DMA24 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA24_YMOD                  ((volatile  int32_t *)REG_DMA24_YMOD)                   /* DMA24 Outer Loop Address Increment (2D only) */
-#define pREG_DMA24_DSCPTR_CUR            ((void * volatile *)REG_DMA24_DSCPTR_CUR)               /* DMA24 Current Descriptor Pointer */
-#define pREG_DMA24_DSCPTR_PRV            ((void * volatile *)REG_DMA24_DSCPTR_PRV)               /* DMA24 Previous Initial Descriptor Pointer */
-#define pREG_DMA24_ADDR_CUR              ((void * volatile *)REG_DMA24_ADDR_CUR)                 /* DMA24 Current Address */
-#define pREG_DMA24_STAT                  ((volatile uint32_t *)REG_DMA24_STAT)                   /* DMA24 Status Register */
-#define pREG_DMA24_XCNT_CUR              ((volatile uint32_t *)REG_DMA24_XCNT_CUR)               /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA24_YCNT_CUR              ((volatile uint32_t *)REG_DMA24_YCNT_CUR)               /* DMA24 Current Row Count (2D only) */
-#define pREG_DMA24_BWLCNT                ((volatile uint32_t *)REG_DMA24_BWLCNT)                 /* DMA24 Bandwidth Limit Count */
-#define pREG_DMA24_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWLCNT_CUR)             /* DMA24 Bandwidth Limit Count Current */
-#define pREG_DMA24_BWMCNT                ((volatile uint32_t *)REG_DMA24_BWMCNT)                 /* DMA24 Bandwidth Monitor Count */
-#define pREG_DMA24_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWMCNT_CUR)             /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA25
-   ========================================================================= */
-#define pREG_DMA25_DSCPTR_NXT            ((void * volatile *)REG_DMA25_DSCPTR_NXT)               /* DMA25 Pointer to Next Initial Descriptor */
-#define pREG_DMA25_ADDRSTART             ((void * volatile *)REG_DMA25_ADDRSTART)                /* DMA25 Start Address of Current Buffer */
-#define pREG_DMA25_CFG                   ((volatile uint32_t *)REG_DMA25_CFG)                    /* DMA25 Configuration Register */
-#define pREG_DMA25_XCNT                  ((volatile uint32_t *)REG_DMA25_XCNT)                   /* DMA25 Inner Loop Count Start Value */
-#define pREG_DMA25_XMOD                  ((volatile  int32_t *)REG_DMA25_XMOD)                   /* DMA25 Inner Loop Address Increment */
-#define pREG_DMA25_YCNT                  ((volatile uint32_t *)REG_DMA25_YCNT)                   /* DMA25 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA25_YMOD                  ((volatile  int32_t *)REG_DMA25_YMOD)                   /* DMA25 Outer Loop Address Increment (2D only) */
-#define pREG_DMA25_DSCPTR_CUR            ((void * volatile *)REG_DMA25_DSCPTR_CUR)               /* DMA25 Current Descriptor Pointer */
-#define pREG_DMA25_DSCPTR_PRV            ((void * volatile *)REG_DMA25_DSCPTR_PRV)               /* DMA25 Previous Initial Descriptor Pointer */
-#define pREG_DMA25_ADDR_CUR              ((void * volatile *)REG_DMA25_ADDR_CUR)                 /* DMA25 Current Address */
-#define pREG_DMA25_STAT                  ((volatile uint32_t *)REG_DMA25_STAT)                   /* DMA25 Status Register */
-#define pREG_DMA25_XCNT_CUR              ((volatile uint32_t *)REG_DMA25_XCNT_CUR)               /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA25_YCNT_CUR              ((volatile uint32_t *)REG_DMA25_YCNT_CUR)               /* DMA25 Current Row Count (2D only) */
-#define pREG_DMA25_BWLCNT                ((volatile uint32_t *)REG_DMA25_BWLCNT)                 /* DMA25 Bandwidth Limit Count */
-#define pREG_DMA25_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWLCNT_CUR)             /* DMA25 Bandwidth Limit Count Current */
-#define pREG_DMA25_BWMCNT                ((volatile uint32_t *)REG_DMA25_BWMCNT)                 /* DMA25 Bandwidth Monitor Count */
-#define pREG_DMA25_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWMCNT_CUR)             /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA26
-   ========================================================================= */
-#define pREG_DMA26_DSCPTR_NXT            ((void * volatile *)REG_DMA26_DSCPTR_NXT)               /* DMA26 Pointer to Next Initial Descriptor */
-#define pREG_DMA26_ADDRSTART             ((void * volatile *)REG_DMA26_ADDRSTART)                /* DMA26 Start Address of Current Buffer */
-#define pREG_DMA26_CFG                   ((volatile uint32_t *)REG_DMA26_CFG)                    /* DMA26 Configuration Register */
-#define pREG_DMA26_XCNT                  ((volatile uint32_t *)REG_DMA26_XCNT)                   /* DMA26 Inner Loop Count Start Value */
-#define pREG_DMA26_XMOD                  ((volatile  int32_t *)REG_DMA26_XMOD)                   /* DMA26 Inner Loop Address Increment */
-#define pREG_DMA26_YCNT                  ((volatile uint32_t *)REG_DMA26_YCNT)                   /* DMA26 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA26_YMOD                  ((volatile  int32_t *)REG_DMA26_YMOD)                   /* DMA26 Outer Loop Address Increment (2D only) */
-#define pREG_DMA26_DSCPTR_CUR            ((void * volatile *)REG_DMA26_DSCPTR_CUR)               /* DMA26 Current Descriptor Pointer */
-#define pREG_DMA26_DSCPTR_PRV            ((void * volatile *)REG_DMA26_DSCPTR_PRV)               /* DMA26 Previous Initial Descriptor Pointer */
-#define pREG_DMA26_ADDR_CUR              ((void * volatile *)REG_DMA26_ADDR_CUR)                 /* DMA26 Current Address */
-#define pREG_DMA26_STAT                  ((volatile uint32_t *)REG_DMA26_STAT)                   /* DMA26 Status Register */
-#define pREG_DMA26_XCNT_CUR              ((volatile uint32_t *)REG_DMA26_XCNT_CUR)               /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA26_YCNT_CUR              ((volatile uint32_t *)REG_DMA26_YCNT_CUR)               /* DMA26 Current Row Count (2D only) */
-#define pREG_DMA26_BWLCNT                ((volatile uint32_t *)REG_DMA26_BWLCNT)                 /* DMA26 Bandwidth Limit Count */
-#define pREG_DMA26_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWLCNT_CUR)             /* DMA26 Bandwidth Limit Count Current */
-#define pREG_DMA26_BWMCNT                ((volatile uint32_t *)REG_DMA26_BWMCNT)                 /* DMA26 Bandwidth Monitor Count */
-#define pREG_DMA26_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWMCNT_CUR)             /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA27
-   ========================================================================= */
-#define pREG_DMA27_DSCPTR_NXT            ((void * volatile *)REG_DMA27_DSCPTR_NXT)               /* DMA27 Pointer to Next Initial Descriptor */
-#define pREG_DMA27_ADDRSTART             ((void * volatile *)REG_DMA27_ADDRSTART)                /* DMA27 Start Address of Current Buffer */
-#define pREG_DMA27_CFG                   ((volatile uint32_t *)REG_DMA27_CFG)                    /* DMA27 Configuration Register */
-#define pREG_DMA27_XCNT                  ((volatile uint32_t *)REG_DMA27_XCNT)                   /* DMA27 Inner Loop Count Start Value */
-#define pREG_DMA27_XMOD                  ((volatile  int32_t *)REG_DMA27_XMOD)                   /* DMA27 Inner Loop Address Increment */
-#define pREG_DMA27_YCNT                  ((volatile uint32_t *)REG_DMA27_YCNT)                   /* DMA27 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA27_YMOD                  ((volatile  int32_t *)REG_DMA27_YMOD)                   /* DMA27 Outer Loop Address Increment (2D only) */
-#define pREG_DMA27_DSCPTR_CUR            ((void * volatile *)REG_DMA27_DSCPTR_CUR)               /* DMA27 Current Descriptor Pointer */
-#define pREG_DMA27_DSCPTR_PRV            ((void * volatile *)REG_DMA27_DSCPTR_PRV)               /* DMA27 Previous Initial Descriptor Pointer */
-#define pREG_DMA27_ADDR_CUR              ((void * volatile *)REG_DMA27_ADDR_CUR)                 /* DMA27 Current Address */
-#define pREG_DMA27_STAT                  ((volatile uint32_t *)REG_DMA27_STAT)                   /* DMA27 Status Register */
-#define pREG_DMA27_XCNT_CUR              ((volatile uint32_t *)REG_DMA27_XCNT_CUR)               /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA27_YCNT_CUR              ((volatile uint32_t *)REG_DMA27_YCNT_CUR)               /* DMA27 Current Row Count (2D only) */
-#define pREG_DMA27_BWLCNT                ((volatile uint32_t *)REG_DMA27_BWLCNT)                 /* DMA27 Bandwidth Limit Count */
-#define pREG_DMA27_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWLCNT_CUR)             /* DMA27 Bandwidth Limit Count Current */
-#define pREG_DMA27_BWMCNT                ((volatile uint32_t *)REG_DMA27_BWMCNT)                 /* DMA27 Bandwidth Monitor Count */
-#define pREG_DMA27_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWMCNT_CUR)             /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA28
-   ========================================================================= */
-#define pREG_DMA28_DSCPTR_NXT            ((void * volatile *)REG_DMA28_DSCPTR_NXT)               /* DMA28 Pointer to Next Initial Descriptor */
-#define pREG_DMA28_ADDRSTART             ((void * volatile *)REG_DMA28_ADDRSTART)                /* DMA28 Start Address of Current Buffer */
-#define pREG_DMA28_CFG                   ((volatile uint32_t *)REG_DMA28_CFG)                    /* DMA28 Configuration Register */
-#define pREG_DMA28_XCNT                  ((volatile uint32_t *)REG_DMA28_XCNT)                   /* DMA28 Inner Loop Count Start Value */
-#define pREG_DMA28_XMOD                  ((volatile  int32_t *)REG_DMA28_XMOD)                   /* DMA28 Inner Loop Address Increment */
-#define pREG_DMA28_YCNT                  ((volatile uint32_t *)REG_DMA28_YCNT)                   /* DMA28 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA28_YMOD                  ((volatile  int32_t *)REG_DMA28_YMOD)                   /* DMA28 Outer Loop Address Increment (2D only) */
-#define pREG_DMA28_DSCPTR_CUR            ((void * volatile *)REG_DMA28_DSCPTR_CUR)               /* DMA28 Current Descriptor Pointer */
-#define pREG_DMA28_DSCPTR_PRV            ((void * volatile *)REG_DMA28_DSCPTR_PRV)               /* DMA28 Previous Initial Descriptor Pointer */
-#define pREG_DMA28_ADDR_CUR              ((void * volatile *)REG_DMA28_ADDR_CUR)                 /* DMA28 Current Address */
-#define pREG_DMA28_STAT                  ((volatile uint32_t *)REG_DMA28_STAT)                   /* DMA28 Status Register */
-#define pREG_DMA28_XCNT_CUR              ((volatile uint32_t *)REG_DMA28_XCNT_CUR)               /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA28_YCNT_CUR              ((volatile uint32_t *)REG_DMA28_YCNT_CUR)               /* DMA28 Current Row Count (2D only) */
-#define pREG_DMA28_BWLCNT                ((volatile uint32_t *)REG_DMA28_BWLCNT)                 /* DMA28 Bandwidth Limit Count */
-#define pREG_DMA28_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWLCNT_CUR)             /* DMA28 Bandwidth Limit Count Current */
-#define pREG_DMA28_BWMCNT                ((volatile uint32_t *)REG_DMA28_BWMCNT)                 /* DMA28 Bandwidth Monitor Count */
-#define pREG_DMA28_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWMCNT_CUR)             /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA29
-   ========================================================================= */
-#define pREG_DMA29_DSCPTR_NXT            ((void * volatile *)REG_DMA29_DSCPTR_NXT)               /* DMA29 Pointer to Next Initial Descriptor */
-#define pREG_DMA29_ADDRSTART             ((void * volatile *)REG_DMA29_ADDRSTART)                /* DMA29 Start Address of Current Buffer */
-#define pREG_DMA29_CFG                   ((volatile uint32_t *)REG_DMA29_CFG)                    /* DMA29 Configuration Register */
-#define pREG_DMA29_XCNT                  ((volatile uint32_t *)REG_DMA29_XCNT)                   /* DMA29 Inner Loop Count Start Value */
-#define pREG_DMA29_XMOD                  ((volatile  int32_t *)REG_DMA29_XMOD)                   /* DMA29 Inner Loop Address Increment */
-#define pREG_DMA29_YCNT                  ((volatile uint32_t *)REG_DMA29_YCNT)                   /* DMA29 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA29_YMOD                  ((volatile  int32_t *)REG_DMA29_YMOD)                   /* DMA29 Outer Loop Address Increment (2D only) */
-#define pREG_DMA29_DSCPTR_CUR            ((void * volatile *)REG_DMA29_DSCPTR_CUR)               /* DMA29 Current Descriptor Pointer */
-#define pREG_DMA29_DSCPTR_PRV            ((void * volatile *)REG_DMA29_DSCPTR_PRV)               /* DMA29 Previous Initial Descriptor Pointer */
-#define pREG_DMA29_ADDR_CUR              ((void * volatile *)REG_DMA29_ADDR_CUR)                 /* DMA29 Current Address */
-#define pREG_DMA29_STAT                  ((volatile uint32_t *)REG_DMA29_STAT)                   /* DMA29 Status Register */
-#define pREG_DMA29_XCNT_CUR              ((volatile uint32_t *)REG_DMA29_XCNT_CUR)               /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA29_YCNT_CUR              ((volatile uint32_t *)REG_DMA29_YCNT_CUR)               /* DMA29 Current Row Count (2D only) */
-#define pREG_DMA29_BWLCNT                ((volatile uint32_t *)REG_DMA29_BWLCNT)                 /* DMA29 Bandwidth Limit Count */
-#define pREG_DMA29_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWLCNT_CUR)             /* DMA29 Bandwidth Limit Count Current */
-#define pREG_DMA29_BWMCNT                ((volatile uint32_t *)REG_DMA29_BWMCNT)                 /* DMA29 Bandwidth Monitor Count */
-#define pREG_DMA29_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWMCNT_CUR)             /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA30
-   ========================================================================= */
-#define pREG_DMA30_DSCPTR_NXT            ((void * volatile *)REG_DMA30_DSCPTR_NXT)               /* DMA30 Pointer to Next Initial Descriptor */
-#define pREG_DMA30_ADDRSTART             ((void * volatile *)REG_DMA30_ADDRSTART)                /* DMA30 Start Address of Current Buffer */
-#define pREG_DMA30_CFG                   ((volatile uint32_t *)REG_DMA30_CFG)                    /* DMA30 Configuration Register */
-#define pREG_DMA30_XCNT                  ((volatile uint32_t *)REG_DMA30_XCNT)                   /* DMA30 Inner Loop Count Start Value */
-#define pREG_DMA30_XMOD                  ((volatile  int32_t *)REG_DMA30_XMOD)                   /* DMA30 Inner Loop Address Increment */
-#define pREG_DMA30_YCNT                  ((volatile uint32_t *)REG_DMA30_YCNT)                   /* DMA30 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA30_YMOD                  ((volatile  int32_t *)REG_DMA30_YMOD)                   /* DMA30 Outer Loop Address Increment (2D only) */
-#define pREG_DMA30_DSCPTR_CUR            ((void * volatile *)REG_DMA30_DSCPTR_CUR)               /* DMA30 Current Descriptor Pointer */
-#define pREG_DMA30_DSCPTR_PRV            ((void * volatile *)REG_DMA30_DSCPTR_PRV)               /* DMA30 Previous Initial Descriptor Pointer */
-#define pREG_DMA30_ADDR_CUR              ((void * volatile *)REG_DMA30_ADDR_CUR)                 /* DMA30 Current Address */
-#define pREG_DMA30_STAT                  ((volatile uint32_t *)REG_DMA30_STAT)                   /* DMA30 Status Register */
-#define pREG_DMA30_XCNT_CUR              ((volatile uint32_t *)REG_DMA30_XCNT_CUR)               /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA30_YCNT_CUR              ((volatile uint32_t *)REG_DMA30_YCNT_CUR)               /* DMA30 Current Row Count (2D only) */
-#define pREG_DMA30_BWLCNT                ((volatile uint32_t *)REG_DMA30_BWLCNT)                 /* DMA30 Bandwidth Limit Count */
-#define pREG_DMA30_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWLCNT_CUR)             /* DMA30 Bandwidth Limit Count Current */
-#define pREG_DMA30_BWMCNT                ((volatile uint32_t *)REG_DMA30_BWMCNT)                 /* DMA30 Bandwidth Monitor Count */
-#define pREG_DMA30_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWMCNT_CUR)             /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA31
-   ========================================================================= */
-#define pREG_DMA31_DSCPTR_NXT            ((void * volatile *)REG_DMA31_DSCPTR_NXT)               /* DMA31 Pointer to Next Initial Descriptor */
-#define pREG_DMA31_ADDRSTART             ((void * volatile *)REG_DMA31_ADDRSTART)                /* DMA31 Start Address of Current Buffer */
-#define pREG_DMA31_CFG                   ((volatile uint32_t *)REG_DMA31_CFG)                    /* DMA31 Configuration Register */
-#define pREG_DMA31_XCNT                  ((volatile uint32_t *)REG_DMA31_XCNT)                   /* DMA31 Inner Loop Count Start Value */
-#define pREG_DMA31_XMOD                  ((volatile  int32_t *)REG_DMA31_XMOD)                   /* DMA31 Inner Loop Address Increment */
-#define pREG_DMA31_YCNT                  ((volatile uint32_t *)REG_DMA31_YCNT)                   /* DMA31 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA31_YMOD                  ((volatile  int32_t *)REG_DMA31_YMOD)                   /* DMA31 Outer Loop Address Increment (2D only) */
-#define pREG_DMA31_DSCPTR_CUR            ((void * volatile *)REG_DMA31_DSCPTR_CUR)               /* DMA31 Current Descriptor Pointer */
-#define pREG_DMA31_DSCPTR_PRV            ((void * volatile *)REG_DMA31_DSCPTR_PRV)               /* DMA31 Previous Initial Descriptor Pointer */
-#define pREG_DMA31_ADDR_CUR              ((void * volatile *)REG_DMA31_ADDR_CUR)                 /* DMA31 Current Address */
-#define pREG_DMA31_STAT                  ((volatile uint32_t *)REG_DMA31_STAT)                   /* DMA31 Status Register */
-#define pREG_DMA31_XCNT_CUR              ((volatile uint32_t *)REG_DMA31_XCNT_CUR)               /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA31_YCNT_CUR              ((volatile uint32_t *)REG_DMA31_YCNT_CUR)               /* DMA31 Current Row Count (2D only) */
-#define pREG_DMA31_BWLCNT                ((volatile uint32_t *)REG_DMA31_BWLCNT)                 /* DMA31 Bandwidth Limit Count */
-#define pREG_DMA31_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWLCNT_CUR)             /* DMA31 Bandwidth Limit Count Current */
-#define pREG_DMA31_BWMCNT                ((volatile uint32_t *)REG_DMA31_BWMCNT)                 /* DMA31 Bandwidth Monitor Count */
-#define pREG_DMA31_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWMCNT_CUR)             /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA32
-   ========================================================================= */
-#define pREG_DMA32_DSCPTR_NXT            ((void * volatile *)REG_DMA32_DSCPTR_NXT)               /* DMA32 Pointer to Next Initial Descriptor */
-#define pREG_DMA32_ADDRSTART             ((void * volatile *)REG_DMA32_ADDRSTART)                /* DMA32 Start Address of Current Buffer */
-#define pREG_DMA32_CFG                   ((volatile uint32_t *)REG_DMA32_CFG)                    /* DMA32 Configuration Register */
-#define pREG_DMA32_XCNT                  ((volatile uint32_t *)REG_DMA32_XCNT)                   /* DMA32 Inner Loop Count Start Value */
-#define pREG_DMA32_XMOD                  ((volatile  int32_t *)REG_DMA32_XMOD)                   /* DMA32 Inner Loop Address Increment */
-#define pREG_DMA32_YCNT                  ((volatile uint32_t *)REG_DMA32_YCNT)                   /* DMA32 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA32_YMOD                  ((volatile  int32_t *)REG_DMA32_YMOD)                   /* DMA32 Outer Loop Address Increment (2D only) */
-#define pREG_DMA32_DSCPTR_CUR            ((void * volatile *)REG_DMA32_DSCPTR_CUR)               /* DMA32 Current Descriptor Pointer */
-#define pREG_DMA32_DSCPTR_PRV            ((void * volatile *)REG_DMA32_DSCPTR_PRV)               /* DMA32 Previous Initial Descriptor Pointer */
-#define pREG_DMA32_ADDR_CUR              ((void * volatile *)REG_DMA32_ADDR_CUR)                 /* DMA32 Current Address */
-#define pREG_DMA32_STAT                  ((volatile uint32_t *)REG_DMA32_STAT)                   /* DMA32 Status Register */
-#define pREG_DMA32_XCNT_CUR              ((volatile uint32_t *)REG_DMA32_XCNT_CUR)               /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA32_YCNT_CUR              ((volatile uint32_t *)REG_DMA32_YCNT_CUR)               /* DMA32 Current Row Count (2D only) */
-#define pREG_DMA32_BWLCNT                ((volatile uint32_t *)REG_DMA32_BWLCNT)                 /* DMA32 Bandwidth Limit Count */
-#define pREG_DMA32_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWLCNT_CUR)             /* DMA32 Bandwidth Limit Count Current */
-#define pREG_DMA32_BWMCNT                ((volatile uint32_t *)REG_DMA32_BWMCNT)                 /* DMA32 Bandwidth Monitor Count */
-#define pREG_DMA32_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWMCNT_CUR)             /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA33
-   ========================================================================= */
-#define pREG_DMA33_DSCPTR_NXT            ((void * volatile *)REG_DMA33_DSCPTR_NXT)               /* DMA33 Pointer to Next Initial Descriptor */
-#define pREG_DMA33_ADDRSTART             ((void * volatile *)REG_DMA33_ADDRSTART)                /* DMA33 Start Address of Current Buffer */
-#define pREG_DMA33_CFG                   ((volatile uint32_t *)REG_DMA33_CFG)                    /* DMA33 Configuration Register */
-#define pREG_DMA33_XCNT                  ((volatile uint32_t *)REG_DMA33_XCNT)                   /* DMA33 Inner Loop Count Start Value */
-#define pREG_DMA33_XMOD                  ((volatile  int32_t *)REG_DMA33_XMOD)                   /* DMA33 Inner Loop Address Increment */
-#define pREG_DMA33_YCNT                  ((volatile uint32_t *)REG_DMA33_YCNT)                   /* DMA33 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA33_YMOD                  ((volatile  int32_t *)REG_DMA33_YMOD)                   /* DMA33 Outer Loop Address Increment (2D only) */
-#define pREG_DMA33_DSCPTR_CUR            ((void * volatile *)REG_DMA33_DSCPTR_CUR)               /* DMA33 Current Descriptor Pointer */
-#define pREG_DMA33_DSCPTR_PRV            ((void * volatile *)REG_DMA33_DSCPTR_PRV)               /* DMA33 Previous Initial Descriptor Pointer */
-#define pREG_DMA33_ADDR_CUR              ((void * volatile *)REG_DMA33_ADDR_CUR)                 /* DMA33 Current Address */
-#define pREG_DMA33_STAT                  ((volatile uint32_t *)REG_DMA33_STAT)                   /* DMA33 Status Register */
-#define pREG_DMA33_XCNT_CUR              ((volatile uint32_t *)REG_DMA33_XCNT_CUR)               /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA33_YCNT_CUR              ((volatile uint32_t *)REG_DMA33_YCNT_CUR)               /* DMA33 Current Row Count (2D only) */
-#define pREG_DMA33_BWLCNT                ((volatile uint32_t *)REG_DMA33_BWLCNT)                 /* DMA33 Bandwidth Limit Count */
-#define pREG_DMA33_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWLCNT_CUR)             /* DMA33 Bandwidth Limit Count Current */
-#define pREG_DMA33_BWMCNT                ((volatile uint32_t *)REG_DMA33_BWMCNT)                 /* DMA33 Bandwidth Monitor Count */
-#define pREG_DMA33_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWMCNT_CUR)             /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA34
-   ========================================================================= */
-#define pREG_DMA34_DSCPTR_NXT            ((void * volatile *)REG_DMA34_DSCPTR_NXT)               /* DMA34 Pointer to Next Initial Descriptor */
-#define pREG_DMA34_ADDRSTART             ((void * volatile *)REG_DMA34_ADDRSTART)                /* DMA34 Start Address of Current Buffer */
-#define pREG_DMA34_CFG                   ((volatile uint32_t *)REG_DMA34_CFG)                    /* DMA34 Configuration Register */
-#define pREG_DMA34_XCNT                  ((volatile uint32_t *)REG_DMA34_XCNT)                   /* DMA34 Inner Loop Count Start Value */
-#define pREG_DMA34_XMOD                  ((volatile  int32_t *)REG_DMA34_XMOD)                   /* DMA34 Inner Loop Address Increment */
-#define pREG_DMA34_YCNT                  ((volatile uint32_t *)REG_DMA34_YCNT)                   /* DMA34 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA34_YMOD                  ((volatile  int32_t *)REG_DMA34_YMOD)                   /* DMA34 Outer Loop Address Increment (2D only) */
-#define pREG_DMA34_DSCPTR_CUR            ((void * volatile *)REG_DMA34_DSCPTR_CUR)               /* DMA34 Current Descriptor Pointer */
-#define pREG_DMA34_DSCPTR_PRV            ((void * volatile *)REG_DMA34_DSCPTR_PRV)               /* DMA34 Previous Initial Descriptor Pointer */
-#define pREG_DMA34_ADDR_CUR              ((void * volatile *)REG_DMA34_ADDR_CUR)                 /* DMA34 Current Address */
-#define pREG_DMA34_STAT                  ((volatile uint32_t *)REG_DMA34_STAT)                   /* DMA34 Status Register */
-#define pREG_DMA34_XCNT_CUR              ((volatile uint32_t *)REG_DMA34_XCNT_CUR)               /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA34_YCNT_CUR              ((volatile uint32_t *)REG_DMA34_YCNT_CUR)               /* DMA34 Current Row Count (2D only) */
-#define pREG_DMA34_BWLCNT                ((volatile uint32_t *)REG_DMA34_BWLCNT)                 /* DMA34 Bandwidth Limit Count */
-#define pREG_DMA34_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWLCNT_CUR)             /* DMA34 Bandwidth Limit Count Current */
-#define pREG_DMA34_BWMCNT                ((volatile uint32_t *)REG_DMA34_BWMCNT)                 /* DMA34 Bandwidth Monitor Count */
-#define pREG_DMA34_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWMCNT_CUR)             /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA35
-   ========================================================================= */
-#define pREG_DMA35_DSCPTR_NXT            ((void * volatile *)REG_DMA35_DSCPTR_NXT)               /* DMA35 Pointer to Next Initial Descriptor */
-#define pREG_DMA35_ADDRSTART             ((void * volatile *)REG_DMA35_ADDRSTART)                /* DMA35 Start Address of Current Buffer */
-#define pREG_DMA35_CFG                   ((volatile uint32_t *)REG_DMA35_CFG)                    /* DMA35 Configuration Register */
-#define pREG_DMA35_XCNT                  ((volatile uint32_t *)REG_DMA35_XCNT)                   /* DMA35 Inner Loop Count Start Value */
-#define pREG_DMA35_XMOD                  ((volatile  int32_t *)REG_DMA35_XMOD)                   /* DMA35 Inner Loop Address Increment */
-#define pREG_DMA35_YCNT                  ((volatile uint32_t *)REG_DMA35_YCNT)                   /* DMA35 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA35_YMOD                  ((volatile  int32_t *)REG_DMA35_YMOD)                   /* DMA35 Outer Loop Address Increment (2D only) */
-#define pREG_DMA35_DSCPTR_CUR            ((void * volatile *)REG_DMA35_DSCPTR_CUR)               /* DMA35 Current Descriptor Pointer */
-#define pREG_DMA35_DSCPTR_PRV            ((void * volatile *)REG_DMA35_DSCPTR_PRV)               /* DMA35 Previous Initial Descriptor Pointer */
-#define pREG_DMA35_ADDR_CUR              ((void * volatile *)REG_DMA35_ADDR_CUR)                 /* DMA35 Current Address */
-#define pREG_DMA35_STAT                  ((volatile uint32_t *)REG_DMA35_STAT)                   /* DMA35 Status Register */
-#define pREG_DMA35_XCNT_CUR              ((volatile uint32_t *)REG_DMA35_XCNT_CUR)               /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA35_YCNT_CUR              ((volatile uint32_t *)REG_DMA35_YCNT_CUR)               /* DMA35 Current Row Count (2D only) */
-#define pREG_DMA35_BWLCNT                ((volatile uint32_t *)REG_DMA35_BWLCNT)                 /* DMA35 Bandwidth Limit Count */
-#define pREG_DMA35_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWLCNT_CUR)             /* DMA35 Bandwidth Limit Count Current */
-#define pREG_DMA35_BWMCNT                ((volatile uint32_t *)REG_DMA35_BWMCNT)                 /* DMA35 Bandwidth Monitor Count */
-#define pREG_DMA35_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWMCNT_CUR)             /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA36
-   ========================================================================= */
-#define pREG_DMA36_DSCPTR_NXT            ((void * volatile *)REG_DMA36_DSCPTR_NXT)               /* DMA36 Pointer to Next Initial Descriptor */
-#define pREG_DMA36_ADDRSTART             ((void * volatile *)REG_DMA36_ADDRSTART)                /* DMA36 Start Address of Current Buffer */
-#define pREG_DMA36_CFG                   ((volatile uint32_t *)REG_DMA36_CFG)                    /* DMA36 Configuration Register */
-#define pREG_DMA36_XCNT                  ((volatile uint32_t *)REG_DMA36_XCNT)                   /* DMA36 Inner Loop Count Start Value */
-#define pREG_DMA36_XMOD                  ((volatile  int32_t *)REG_DMA36_XMOD)                   /* DMA36 Inner Loop Address Increment */
-#define pREG_DMA36_YCNT                  ((volatile uint32_t *)REG_DMA36_YCNT)                   /* DMA36 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA36_YMOD                  ((volatile  int32_t *)REG_DMA36_YMOD)                   /* DMA36 Outer Loop Address Increment (2D only) */
-#define pREG_DMA36_DSCPTR_CUR            ((void * volatile *)REG_DMA36_DSCPTR_CUR)               /* DMA36 Current Descriptor Pointer */
-#define pREG_DMA36_DSCPTR_PRV            ((void * volatile *)REG_DMA36_DSCPTR_PRV)               /* DMA36 Previous Initial Descriptor Pointer */
-#define pREG_DMA36_ADDR_CUR              ((void * volatile *)REG_DMA36_ADDR_CUR)                 /* DMA36 Current Address */
-#define pREG_DMA36_STAT                  ((volatile uint32_t *)REG_DMA36_STAT)                   /* DMA36 Status Register */
-#define pREG_DMA36_XCNT_CUR              ((volatile uint32_t *)REG_DMA36_XCNT_CUR)               /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA36_YCNT_CUR              ((volatile uint32_t *)REG_DMA36_YCNT_CUR)               /* DMA36 Current Row Count (2D only) */
-#define pREG_DMA36_BWLCNT                ((volatile uint32_t *)REG_DMA36_BWLCNT)                 /* DMA36 Bandwidth Limit Count */
-#define pREG_DMA36_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWLCNT_CUR)             /* DMA36 Bandwidth Limit Count Current */
-#define pREG_DMA36_BWMCNT                ((volatile uint32_t *)REG_DMA36_BWMCNT)                 /* DMA36 Bandwidth Monitor Count */
-#define pREG_DMA36_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWMCNT_CUR)             /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA37
-   ========================================================================= */
-#define pREG_DMA37_DSCPTR_NXT            ((void * volatile *)REG_DMA37_DSCPTR_NXT)               /* DMA37 Pointer to Next Initial Descriptor */
-#define pREG_DMA37_ADDRSTART             ((void * volatile *)REG_DMA37_ADDRSTART)                /* DMA37 Start Address of Current Buffer */
-#define pREG_DMA37_CFG                   ((volatile uint32_t *)REG_DMA37_CFG)                    /* DMA37 Configuration Register */
-#define pREG_DMA37_XCNT                  ((volatile uint32_t *)REG_DMA37_XCNT)                   /* DMA37 Inner Loop Count Start Value */
-#define pREG_DMA37_XMOD                  ((volatile  int32_t *)REG_DMA37_XMOD)                   /* DMA37 Inner Loop Address Increment */
-#define pREG_DMA37_YCNT                  ((volatile uint32_t *)REG_DMA37_YCNT)                   /* DMA37 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA37_YMOD                  ((volatile  int32_t *)REG_DMA37_YMOD)                   /* DMA37 Outer Loop Address Increment (2D only) */
-#define pREG_DMA37_DSCPTR_CUR            ((void * volatile *)REG_DMA37_DSCPTR_CUR)               /* DMA37 Current Descriptor Pointer */
-#define pREG_DMA37_DSCPTR_PRV            ((void * volatile *)REG_DMA37_DSCPTR_PRV)               /* DMA37 Previous Initial Descriptor Pointer */
-#define pREG_DMA37_ADDR_CUR              ((void * volatile *)REG_DMA37_ADDR_CUR)                 /* DMA37 Current Address */
-#define pREG_DMA37_STAT                  ((volatile uint32_t *)REG_DMA37_STAT)                   /* DMA37 Status Register */
-#define pREG_DMA37_XCNT_CUR              ((volatile uint32_t *)REG_DMA37_XCNT_CUR)               /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA37_YCNT_CUR              ((volatile uint32_t *)REG_DMA37_YCNT_CUR)               /* DMA37 Current Row Count (2D only) */
-#define pREG_DMA37_BWLCNT                ((volatile uint32_t *)REG_DMA37_BWLCNT)                 /* DMA37 Bandwidth Limit Count */
-#define pREG_DMA37_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWLCNT_CUR)             /* DMA37 Bandwidth Limit Count Current */
-#define pREG_DMA37_BWMCNT                ((volatile uint32_t *)REG_DMA37_BWMCNT)                 /* DMA37 Bandwidth Monitor Count */
-#define pREG_DMA37_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWMCNT_CUR)             /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA38
-   ========================================================================= */
-#define pREG_DMA38_DSCPTR_NXT            ((void * volatile *)REG_DMA38_DSCPTR_NXT)               /* DMA38 Pointer to Next Initial Descriptor */
-#define pREG_DMA38_ADDRSTART             ((void * volatile *)REG_DMA38_ADDRSTART)                /* DMA38 Start Address of Current Buffer */
-#define pREG_DMA38_CFG                   ((volatile uint32_t *)REG_DMA38_CFG)                    /* DMA38 Configuration Register */
-#define pREG_DMA38_XCNT                  ((volatile uint32_t *)REG_DMA38_XCNT)                   /* DMA38 Inner Loop Count Start Value */
-#define pREG_DMA38_XMOD                  ((volatile  int32_t *)REG_DMA38_XMOD)                   /* DMA38 Inner Loop Address Increment */
-#define pREG_DMA38_YCNT                  ((volatile uint32_t *)REG_DMA38_YCNT)                   /* DMA38 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA38_YMOD                  ((volatile  int32_t *)REG_DMA38_YMOD)                   /* DMA38 Outer Loop Address Increment (2D only) */
-#define pREG_DMA38_DSCPTR_CUR            ((void * volatile *)REG_DMA38_DSCPTR_CUR)               /* DMA38 Current Descriptor Pointer */
-#define pREG_DMA38_DSCPTR_PRV            ((void * volatile *)REG_DMA38_DSCPTR_PRV)               /* DMA38 Previous Initial Descriptor Pointer */
-#define pREG_DMA38_ADDR_CUR              ((void * volatile *)REG_DMA38_ADDR_CUR)                 /* DMA38 Current Address */
-#define pREG_DMA38_STAT                  ((volatile uint32_t *)REG_DMA38_STAT)                   /* DMA38 Status Register */
-#define pREG_DMA38_XCNT_CUR              ((volatile uint32_t *)REG_DMA38_XCNT_CUR)               /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA38_YCNT_CUR              ((volatile uint32_t *)REG_DMA38_YCNT_CUR)               /* DMA38 Current Row Count (2D only) */
-#define pREG_DMA38_BWLCNT                ((volatile uint32_t *)REG_DMA38_BWLCNT)                 /* DMA38 Bandwidth Limit Count */
-#define pREG_DMA38_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWLCNT_CUR)             /* DMA38 Bandwidth Limit Count Current */
-#define pREG_DMA38_BWMCNT                ((volatile uint32_t *)REG_DMA38_BWMCNT)                 /* DMA38 Bandwidth Monitor Count */
-#define pREG_DMA38_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWMCNT_CUR)             /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA39
-   ========================================================================= */
-#define pREG_DMA39_DSCPTR_NXT            ((void * volatile *)REG_DMA39_DSCPTR_NXT)               /* DMA39 Pointer to Next Initial Descriptor */
-#define pREG_DMA39_ADDRSTART             ((void * volatile *)REG_DMA39_ADDRSTART)                /* DMA39 Start Address of Current Buffer */
-#define pREG_DMA39_CFG                   ((volatile uint32_t *)REG_DMA39_CFG)                    /* DMA39 Configuration Register */
-#define pREG_DMA39_XCNT                  ((volatile uint32_t *)REG_DMA39_XCNT)                   /* DMA39 Inner Loop Count Start Value */
-#define pREG_DMA39_XMOD                  ((volatile  int32_t *)REG_DMA39_XMOD)                   /* DMA39 Inner Loop Address Increment */
-#define pREG_DMA39_YCNT                  ((volatile uint32_t *)REG_DMA39_YCNT)                   /* DMA39 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA39_YMOD                  ((volatile  int32_t *)REG_DMA39_YMOD)                   /* DMA39 Outer Loop Address Increment (2D only) */
-#define pREG_DMA39_DSCPTR_CUR            ((void * volatile *)REG_DMA39_DSCPTR_CUR)               /* DMA39 Current Descriptor Pointer */
-#define pREG_DMA39_DSCPTR_PRV            ((void * volatile *)REG_DMA39_DSCPTR_PRV)               /* DMA39 Previous Initial Descriptor Pointer */
-#define pREG_DMA39_ADDR_CUR              ((void * volatile *)REG_DMA39_ADDR_CUR)                 /* DMA39 Current Address */
-#define pREG_DMA39_STAT                  ((volatile uint32_t *)REG_DMA39_STAT)                   /* DMA39 Status Register */
-#define pREG_DMA39_XCNT_CUR              ((volatile uint32_t *)REG_DMA39_XCNT_CUR)               /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA39_YCNT_CUR              ((volatile uint32_t *)REG_DMA39_YCNT_CUR)               /* DMA39 Current Row Count (2D only) */
-#define pREG_DMA39_BWLCNT                ((volatile uint32_t *)REG_DMA39_BWLCNT)                 /* DMA39 Bandwidth Limit Count */
-#define pREG_DMA39_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWLCNT_CUR)             /* DMA39 Bandwidth Limit Count Current */
-#define pREG_DMA39_BWMCNT                ((volatile uint32_t *)REG_DMA39_BWMCNT)                 /* DMA39 Bandwidth Monitor Count */
-#define pREG_DMA39_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWMCNT_CUR)             /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA40
-   ========================================================================= */
-#define pREG_DMA40_DSCPTR_NXT            ((void * volatile *)REG_DMA40_DSCPTR_NXT)               /* DMA40 Pointer to Next Initial Descriptor */
-#define pREG_DMA40_ADDRSTART             ((void * volatile *)REG_DMA40_ADDRSTART)                /* DMA40 Start Address of Current Buffer */
-#define pREG_DMA40_CFG                   ((volatile uint32_t *)REG_DMA40_CFG)                    /* DMA40 Configuration Register */
-#define pREG_DMA40_XCNT                  ((volatile uint32_t *)REG_DMA40_XCNT)                   /* DMA40 Inner Loop Count Start Value */
-#define pREG_DMA40_XMOD                  ((volatile  int32_t *)REG_DMA40_XMOD)                   /* DMA40 Inner Loop Address Increment */
-#define pREG_DMA40_YCNT                  ((volatile uint32_t *)REG_DMA40_YCNT)                   /* DMA40 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA40_YMOD                  ((volatile  int32_t *)REG_DMA40_YMOD)                   /* DMA40 Outer Loop Address Increment (2D only) */
-#define pREG_DMA40_DSCPTR_CUR            ((void * volatile *)REG_DMA40_DSCPTR_CUR)               /* DMA40 Current Descriptor Pointer */
-#define pREG_DMA40_DSCPTR_PRV            ((void * volatile *)REG_DMA40_DSCPTR_PRV)               /* DMA40 Previous Initial Descriptor Pointer */
-#define pREG_DMA40_ADDR_CUR              ((void * volatile *)REG_DMA40_ADDR_CUR)                 /* DMA40 Current Address */
-#define pREG_DMA40_STAT                  ((volatile uint32_t *)REG_DMA40_STAT)                   /* DMA40 Status Register */
-#define pREG_DMA40_XCNT_CUR              ((volatile uint32_t *)REG_DMA40_XCNT_CUR)               /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA40_YCNT_CUR              ((volatile uint32_t *)REG_DMA40_YCNT_CUR)               /* DMA40 Current Row Count (2D only) */
-#define pREG_DMA40_BWLCNT                ((volatile uint32_t *)REG_DMA40_BWLCNT)                 /* DMA40 Bandwidth Limit Count */
-#define pREG_DMA40_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWLCNT_CUR)             /* DMA40 Bandwidth Limit Count Current */
-#define pREG_DMA40_BWMCNT                ((volatile uint32_t *)REG_DMA40_BWMCNT)                 /* DMA40 Bandwidth Monitor Count */
-#define pREG_DMA40_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWMCNT_CUR)             /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA41
-   ========================================================================= */
-#define pREG_DMA41_DSCPTR_NXT            ((void * volatile *)REG_DMA41_DSCPTR_NXT)               /* DMA41 Pointer to Next Initial Descriptor */
-#define pREG_DMA41_ADDRSTART             ((void * volatile *)REG_DMA41_ADDRSTART)                /* DMA41 Start Address of Current Buffer */
-#define pREG_DMA41_CFG                   ((volatile uint32_t *)REG_DMA41_CFG)                    /* DMA41 Configuration Register */
-#define pREG_DMA41_XCNT                  ((volatile uint32_t *)REG_DMA41_XCNT)                   /* DMA41 Inner Loop Count Start Value */
-#define pREG_DMA41_XMOD                  ((volatile  int32_t *)REG_DMA41_XMOD)                   /* DMA41 Inner Loop Address Increment */
-#define pREG_DMA41_YCNT                  ((volatile uint32_t *)REG_DMA41_YCNT)                   /* DMA41 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA41_YMOD                  ((volatile  int32_t *)REG_DMA41_YMOD)                   /* DMA41 Outer Loop Address Increment (2D only) */
-#define pREG_DMA41_DSCPTR_CUR            ((void * volatile *)REG_DMA41_DSCPTR_CUR)               /* DMA41 Current Descriptor Pointer */
-#define pREG_DMA41_DSCPTR_PRV            ((void * volatile *)REG_DMA41_DSCPTR_PRV)               /* DMA41 Previous Initial Descriptor Pointer */
-#define pREG_DMA41_ADDR_CUR              ((void * volatile *)REG_DMA41_ADDR_CUR)                 /* DMA41 Current Address */
-#define pREG_DMA41_STAT                  ((volatile uint32_t *)REG_DMA41_STAT)                   /* DMA41 Status Register */
-#define pREG_DMA41_XCNT_CUR              ((volatile uint32_t *)REG_DMA41_XCNT_CUR)               /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA41_YCNT_CUR              ((volatile uint32_t *)REG_DMA41_YCNT_CUR)               /* DMA41 Current Row Count (2D only) */
-#define pREG_DMA41_BWLCNT                ((volatile uint32_t *)REG_DMA41_BWLCNT)                 /* DMA41 Bandwidth Limit Count */
-#define pREG_DMA41_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWLCNT_CUR)             /* DMA41 Bandwidth Limit Count Current */
-#define pREG_DMA41_BWMCNT                ((volatile uint32_t *)REG_DMA41_BWMCNT)                 /* DMA41 Bandwidth Monitor Count */
-#define pREG_DMA41_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWMCNT_CUR)             /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA42
-   ========================================================================= */
-#define pREG_DMA42_DSCPTR_NXT            ((void * volatile *)REG_DMA42_DSCPTR_NXT)               /* DMA42 Pointer to Next Initial Descriptor */
-#define pREG_DMA42_ADDRSTART             ((void * volatile *)REG_DMA42_ADDRSTART)                /* DMA42 Start Address of Current Buffer */
-#define pREG_DMA42_CFG                   ((volatile uint32_t *)REG_DMA42_CFG)                    /* DMA42 Configuration Register */
-#define pREG_DMA42_XCNT                  ((volatile uint32_t *)REG_DMA42_XCNT)                   /* DMA42 Inner Loop Count Start Value */
-#define pREG_DMA42_XMOD                  ((volatile  int32_t *)REG_DMA42_XMOD)                   /* DMA42 Inner Loop Address Increment */
-#define pREG_DMA42_YCNT                  ((volatile uint32_t *)REG_DMA42_YCNT)                   /* DMA42 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA42_YMOD                  ((volatile  int32_t *)REG_DMA42_YMOD)                   /* DMA42 Outer Loop Address Increment (2D only) */
-#define pREG_DMA42_DSCPTR_CUR            ((void * volatile *)REG_DMA42_DSCPTR_CUR)               /* DMA42 Current Descriptor Pointer */
-#define pREG_DMA42_DSCPTR_PRV            ((void * volatile *)REG_DMA42_DSCPTR_PRV)               /* DMA42 Previous Initial Descriptor Pointer */
-#define pREG_DMA42_ADDR_CUR              ((void * volatile *)REG_DMA42_ADDR_CUR)                 /* DMA42 Current Address */
-#define pREG_DMA42_STAT                  ((volatile uint32_t *)REG_DMA42_STAT)                   /* DMA42 Status Register */
-#define pREG_DMA42_XCNT_CUR              ((volatile uint32_t *)REG_DMA42_XCNT_CUR)               /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA42_YCNT_CUR              ((volatile uint32_t *)REG_DMA42_YCNT_CUR)               /* DMA42 Current Row Count (2D only) */
-#define pREG_DMA42_BWLCNT                ((volatile uint32_t *)REG_DMA42_BWLCNT)                 /* DMA42 Bandwidth Limit Count */
-#define pREG_DMA42_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWLCNT_CUR)             /* DMA42 Bandwidth Limit Count Current */
-#define pREG_DMA42_BWMCNT                ((volatile uint32_t *)REG_DMA42_BWMCNT)                 /* DMA42 Bandwidth Monitor Count */
-#define pREG_DMA42_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWMCNT_CUR)             /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA43
-   ========================================================================= */
-#define pREG_DMA43_DSCPTR_NXT            ((void * volatile *)REG_DMA43_DSCPTR_NXT)               /* DMA43 Pointer to Next Initial Descriptor */
-#define pREG_DMA43_ADDRSTART             ((void * volatile *)REG_DMA43_ADDRSTART)                /* DMA43 Start Address of Current Buffer */
-#define pREG_DMA43_CFG                   ((volatile uint32_t *)REG_DMA43_CFG)                    /* DMA43 Configuration Register */
-#define pREG_DMA43_XCNT                  ((volatile uint32_t *)REG_DMA43_XCNT)                   /* DMA43 Inner Loop Count Start Value */
-#define pREG_DMA43_XMOD                  ((volatile  int32_t *)REG_DMA43_XMOD)                   /* DMA43 Inner Loop Address Increment */
-#define pREG_DMA43_YCNT                  ((volatile uint32_t *)REG_DMA43_YCNT)                   /* DMA43 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA43_YMOD                  ((volatile  int32_t *)REG_DMA43_YMOD)                   /* DMA43 Outer Loop Address Increment (2D only) */
-#define pREG_DMA43_DSCPTR_CUR            ((void * volatile *)REG_DMA43_DSCPTR_CUR)               /* DMA43 Current Descriptor Pointer */
-#define pREG_DMA43_DSCPTR_PRV            ((void * volatile *)REG_DMA43_DSCPTR_PRV)               /* DMA43 Previous Initial Descriptor Pointer */
-#define pREG_DMA43_ADDR_CUR              ((void * volatile *)REG_DMA43_ADDR_CUR)                 /* DMA43 Current Address */
-#define pREG_DMA43_STAT                  ((volatile uint32_t *)REG_DMA43_STAT)                   /* DMA43 Status Register */
-#define pREG_DMA43_XCNT_CUR              ((volatile uint32_t *)REG_DMA43_XCNT_CUR)               /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA43_YCNT_CUR              ((volatile uint32_t *)REG_DMA43_YCNT_CUR)               /* DMA43 Current Row Count (2D only) */
-#define pREG_DMA43_BWLCNT                ((volatile uint32_t *)REG_DMA43_BWLCNT)                 /* DMA43 Bandwidth Limit Count */
-#define pREG_DMA43_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWLCNT_CUR)             /* DMA43 Bandwidth Limit Count Current */
-#define pREG_DMA43_BWMCNT                ((volatile uint32_t *)REG_DMA43_BWMCNT)                 /* DMA43 Bandwidth Monitor Count */
-#define pREG_DMA43_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWMCNT_CUR)             /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA44
-   ========================================================================= */
-#define pREG_DMA44_DSCPTR_NXT            ((void * volatile *)REG_DMA44_DSCPTR_NXT)               /* DMA44 Pointer to Next Initial Descriptor */
-#define pREG_DMA44_ADDRSTART             ((void * volatile *)REG_DMA44_ADDRSTART)                /* DMA44 Start Address of Current Buffer */
-#define pREG_DMA44_CFG                   ((volatile uint32_t *)REG_DMA44_CFG)                    /* DMA44 Configuration Register */
-#define pREG_DMA44_XCNT                  ((volatile uint32_t *)REG_DMA44_XCNT)                   /* DMA44 Inner Loop Count Start Value */
-#define pREG_DMA44_XMOD                  ((volatile  int32_t *)REG_DMA44_XMOD)                   /* DMA44 Inner Loop Address Increment */
-#define pREG_DMA44_YCNT                  ((volatile uint32_t *)REG_DMA44_YCNT)                   /* DMA44 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA44_YMOD                  ((volatile  int32_t *)REG_DMA44_YMOD)                   /* DMA44 Outer Loop Address Increment (2D only) */
-#define pREG_DMA44_DSCPTR_CUR            ((void * volatile *)REG_DMA44_DSCPTR_CUR)               /* DMA44 Current Descriptor Pointer */
-#define pREG_DMA44_DSCPTR_PRV            ((void * volatile *)REG_DMA44_DSCPTR_PRV)               /* DMA44 Previous Initial Descriptor Pointer */
-#define pREG_DMA44_ADDR_CUR              ((void * volatile *)REG_DMA44_ADDR_CUR)                 /* DMA44 Current Address */
-#define pREG_DMA44_STAT                  ((volatile uint32_t *)REG_DMA44_STAT)                   /* DMA44 Status Register */
-#define pREG_DMA44_XCNT_CUR              ((volatile uint32_t *)REG_DMA44_XCNT_CUR)               /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA44_YCNT_CUR              ((volatile uint32_t *)REG_DMA44_YCNT_CUR)               /* DMA44 Current Row Count (2D only) */
-#define pREG_DMA44_BWLCNT                ((volatile uint32_t *)REG_DMA44_BWLCNT)                 /* DMA44 Bandwidth Limit Count */
-#define pREG_DMA44_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWLCNT_CUR)             /* DMA44 Bandwidth Limit Count Current */
-#define pREG_DMA44_BWMCNT                ((volatile uint32_t *)REG_DMA44_BWMCNT)                 /* DMA44 Bandwidth Monitor Count */
-#define pREG_DMA44_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWMCNT_CUR)             /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA45
-   ========================================================================= */
-#define pREG_DMA45_DSCPTR_NXT            ((void * volatile *)REG_DMA45_DSCPTR_NXT)               /* DMA45 Pointer to Next Initial Descriptor */
-#define pREG_DMA45_ADDRSTART             ((void * volatile *)REG_DMA45_ADDRSTART)                /* DMA45 Start Address of Current Buffer */
-#define pREG_DMA45_CFG                   ((volatile uint32_t *)REG_DMA45_CFG)                    /* DMA45 Configuration Register */
-#define pREG_DMA45_XCNT                  ((volatile uint32_t *)REG_DMA45_XCNT)                   /* DMA45 Inner Loop Count Start Value */
-#define pREG_DMA45_XMOD                  ((volatile  int32_t *)REG_DMA45_XMOD)                   /* DMA45 Inner Loop Address Increment */
-#define pREG_DMA45_YCNT                  ((volatile uint32_t *)REG_DMA45_YCNT)                   /* DMA45 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA45_YMOD                  ((volatile  int32_t *)REG_DMA45_YMOD)                   /* DMA45 Outer Loop Address Increment (2D only) */
-#define pREG_DMA45_DSCPTR_CUR            ((void * volatile *)REG_DMA45_DSCPTR_CUR)               /* DMA45 Current Descriptor Pointer */
-#define pREG_DMA45_DSCPTR_PRV            ((void * volatile *)REG_DMA45_DSCPTR_PRV)               /* DMA45 Previous Initial Descriptor Pointer */
-#define pREG_DMA45_ADDR_CUR              ((void * volatile *)REG_DMA45_ADDR_CUR)                 /* DMA45 Current Address */
-#define pREG_DMA45_STAT                  ((volatile uint32_t *)REG_DMA45_STAT)                   /* DMA45 Status Register */
-#define pREG_DMA45_XCNT_CUR              ((volatile uint32_t *)REG_DMA45_XCNT_CUR)               /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA45_YCNT_CUR              ((volatile uint32_t *)REG_DMA45_YCNT_CUR)               /* DMA45 Current Row Count (2D only) */
-#define pREG_DMA45_BWLCNT                ((volatile uint32_t *)REG_DMA45_BWLCNT)                 /* DMA45 Bandwidth Limit Count */
-#define pREG_DMA45_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWLCNT_CUR)             /* DMA45 Bandwidth Limit Count Current */
-#define pREG_DMA45_BWMCNT                ((volatile uint32_t *)REG_DMA45_BWMCNT)                 /* DMA45 Bandwidth Monitor Count */
-#define pREG_DMA45_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWMCNT_CUR)             /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA46
-   ========================================================================= */
-#define pREG_DMA46_DSCPTR_NXT            ((void * volatile *)REG_DMA46_DSCPTR_NXT)               /* DMA46 Pointer to Next Initial Descriptor */
-#define pREG_DMA46_ADDRSTART             ((void * volatile *)REG_DMA46_ADDRSTART)                /* DMA46 Start Address of Current Buffer */
-#define pREG_DMA46_CFG                   ((volatile uint32_t *)REG_DMA46_CFG)                    /* DMA46 Configuration Register */
-#define pREG_DMA46_XCNT                  ((volatile uint32_t *)REG_DMA46_XCNT)                   /* DMA46 Inner Loop Count Start Value */
-#define pREG_DMA46_XMOD                  ((volatile  int32_t *)REG_DMA46_XMOD)                   /* DMA46 Inner Loop Address Increment */
-#define pREG_DMA46_YCNT                  ((volatile uint32_t *)REG_DMA46_YCNT)                   /* DMA46 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA46_YMOD                  ((volatile  int32_t *)REG_DMA46_YMOD)                   /* DMA46 Outer Loop Address Increment (2D only) */
-#define pREG_DMA46_DSCPTR_CUR            ((void * volatile *)REG_DMA46_DSCPTR_CUR)               /* DMA46 Current Descriptor Pointer */
-#define pREG_DMA46_DSCPTR_PRV            ((void * volatile *)REG_DMA46_DSCPTR_PRV)               /* DMA46 Previous Initial Descriptor Pointer */
-#define pREG_DMA46_ADDR_CUR              ((void * volatile *)REG_DMA46_ADDR_CUR)                 /* DMA46 Current Address */
-#define pREG_DMA46_STAT                  ((volatile uint32_t *)REG_DMA46_STAT)                   /* DMA46 Status Register */
-#define pREG_DMA46_XCNT_CUR              ((volatile uint32_t *)REG_DMA46_XCNT_CUR)               /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA46_YCNT_CUR              ((volatile uint32_t *)REG_DMA46_YCNT_CUR)               /* DMA46 Current Row Count (2D only) */
-#define pREG_DMA46_BWLCNT                ((volatile uint32_t *)REG_DMA46_BWLCNT)                 /* DMA46 Bandwidth Limit Count */
-#define pREG_DMA46_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWLCNT_CUR)             /* DMA46 Bandwidth Limit Count Current */
-#define pREG_DMA46_BWMCNT                ((volatile uint32_t *)REG_DMA46_BWMCNT)                 /* DMA46 Bandwidth Monitor Count */
-#define pREG_DMA46_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWMCNT_CUR)             /* DMA46 Bandwidth Monitor Count Current */
-
-
-/* =========================================================================
-       ACM0
-   ========================================================================= */
-#define pREG_ACM0_CTL                    ((volatile uint32_t *)REG_ACM0_CTL)                     /* ACM0 ACM Control Register */
-#define pREG_ACM0_TC0                    ((volatile uint32_t *)REG_ACM0_TC0)                     /* ACM0 ACM Timing Configuration 0 Register */
-#define pREG_ACM0_TC1                    ((volatile uint32_t *)REG_ACM0_TC1)                     /* ACM0 ACM Timing Configuration 1 Register */
-#define pREG_ACM0_STAT                   ((volatile uint32_t *)REG_ACM0_STAT)                    /* ACM0 ACM Status Register */
-#define pREG_ACM0_EVSTAT                 ((volatile uint32_t *)REG_ACM0_EVSTAT)                  /* ACM0 ACM Event Status Register */
-#define pREG_ACM0_EVMSK                  ((volatile uint32_t *)REG_ACM0_EVMSK)                   /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define pREG_ACM0_MEVSTAT                ((volatile uint32_t *)REG_ACM0_MEVSTAT)                 /* ACM0 ACM Missed Event Status Register */
-#define pREG_ACM0_MEVMSK                 ((volatile uint32_t *)REG_ACM0_MEVMSK)                  /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define pREG_ACM0_EVCTL0                 ((volatile uint32_t *)REG_ACM0_EVCTL0)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL1                 ((volatile uint32_t *)REG_ACM0_EVCTL1)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL2                 ((volatile uint32_t *)REG_ACM0_EVCTL2)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL3                 ((volatile uint32_t *)REG_ACM0_EVCTL3)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL4                 ((volatile uint32_t *)REG_ACM0_EVCTL4)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL5                 ((volatile uint32_t *)REG_ACM0_EVCTL5)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL6                 ((volatile uint32_t *)REG_ACM0_EVCTL6)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL7                 ((volatile uint32_t *)REG_ACM0_EVCTL7)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL8                 ((volatile uint32_t *)REG_ACM0_EVCTL8)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL9                 ((volatile uint32_t *)REG_ACM0_EVCTL9)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL10                ((volatile uint32_t *)REG_ACM0_EVCTL10)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL11                ((volatile uint32_t *)REG_ACM0_EVCTL11)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL12                ((volatile uint32_t *)REG_ACM0_EVCTL12)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL13                ((volatile uint32_t *)REG_ACM0_EVCTL13)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL14                ((volatile uint32_t *)REG_ACM0_EVCTL14)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL15                ((volatile uint32_t *)REG_ACM0_EVCTL15)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVTIME0                ((volatile uint32_t *)REG_ACM0_EVTIME0)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME1                ((volatile uint32_t *)REG_ACM0_EVTIME1)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME2                ((volatile uint32_t *)REG_ACM0_EVTIME2)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME3                ((volatile uint32_t *)REG_ACM0_EVTIME3)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME4                ((volatile uint32_t *)REG_ACM0_EVTIME4)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME5                ((volatile uint32_t *)REG_ACM0_EVTIME5)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME6                ((volatile uint32_t *)REG_ACM0_EVTIME6)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME7                ((volatile uint32_t *)REG_ACM0_EVTIME7)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME8                ((volatile uint32_t *)REG_ACM0_EVTIME8)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME9                ((volatile uint32_t *)REG_ACM0_EVTIME9)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME10               ((volatile uint32_t *)REG_ACM0_EVTIME10)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME11               ((volatile uint32_t *)REG_ACM0_EVTIME11)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME12               ((volatile uint32_t *)REG_ACM0_EVTIME12)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME13               ((volatile uint32_t *)REG_ACM0_EVTIME13)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME14               ((volatile uint32_t *)REG_ACM0_EVTIME14)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME15               ((volatile uint32_t *)REG_ACM0_EVTIME15)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVORD0                 ((volatile uint32_t *)REG_ACM0_EVORD0)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD1                 ((volatile uint32_t *)REG_ACM0_EVORD1)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD2                 ((volatile uint32_t *)REG_ACM0_EVORD2)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD3                 ((volatile uint32_t *)REG_ACM0_EVORD3)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD4                 ((volatile uint32_t *)REG_ACM0_EVORD4)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD5                 ((volatile uint32_t *)REG_ACM0_EVORD5)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD6                 ((volatile uint32_t *)REG_ACM0_EVORD6)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD7                 ((volatile uint32_t *)REG_ACM0_EVORD7)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD8                 ((volatile uint32_t *)REG_ACM0_EVORD8)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD9                 ((volatile uint32_t *)REG_ACM0_EVORD9)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD10                ((volatile uint32_t *)REG_ACM0_EVORD10)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD11                ((volatile uint32_t *)REG_ACM0_EVORD11)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD12                ((volatile uint32_t *)REG_ACM0_EVORD12)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD13                ((volatile uint32_t *)REG_ACM0_EVORD13)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD14                ((volatile uint32_t *)REG_ACM0_EVORD14)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD15                ((volatile uint32_t *)REG_ACM0_EVORD15)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_TMR0                   ((volatile uint32_t *)REG_ACM0_TMR0)                    /* ACM0 ACM Timer 0 Register */
-#define pREG_ACM0_TMR1                   ((volatile uint32_t *)REG_ACM0_TMR1)                    /* ACM0 ACM Timer 1 Register */
-
-
-/* =========================================================================
-       DMC0
-   ========================================================================= */
-#define pREG_DMC0_CTL                    ((volatile uint32_t *)REG_DMC0_CTL)                     /* DMC0 Control Register */
-#define pREG_DMC0_STAT                   ((volatile uint32_t *)REG_DMC0_STAT)                    /* DMC0 Status Register */
-#define pREG_DMC0_EFFCTL                 ((volatile uint32_t *)REG_DMC0_EFFCTL)                  /* DMC0 Efficiency Control Register */
-#define pREG_DMC0_PRIO                   ((volatile uint32_t *)REG_DMC0_PRIO)                    /* DMC0 Priority ID Register */
-#define pREG_DMC0_PRIOMSK                ((volatile uint32_t *)REG_DMC0_PRIOMSK)                 /* DMC0 Priority ID Mask Register */
-#define pREG_DMC0_CFG                    ((volatile uint32_t *)REG_DMC0_CFG)                     /* DMC0 Configuration Register */
-#define pREG_DMC0_TR0                    ((volatile uint32_t *)REG_DMC0_TR0)                     /* DMC0 Timing 0 Register */
-#define pREG_DMC0_TR1                    ((volatile uint32_t *)REG_DMC0_TR1)                     /* DMC0 Timing 1 Register */
-#define pREG_DMC0_TR2                    ((volatile uint32_t *)REG_DMC0_TR2)                     /* DMC0 Timing 2 Register */
-#define pREG_DMC0_MSK                    ((volatile uint32_t *)REG_DMC0_MSK)                     /* DMC0 Mask (Mode Register Shadow) Register */
-#define pREG_DMC0_MR                     ((volatile uint32_t *)REG_DMC0_MR)                      /* DMC0 Shadow MR Register */
-#define pREG_DMC0_EMR1                   ((volatile uint32_t *)REG_DMC0_EMR1)                    /* DMC0 Shadow EMR1 Register */
-#define pREG_DMC0_EMR2                   ((volatile uint32_t *)REG_DMC0_EMR2)                    /* DMC0 Shadow EMR2 Register */
-#define pREG_DMC0_EMR3                   ((volatile uint32_t *)REG_DMC0_EMR3)                    /* DMC0 Shadow EMR3 Register */
-#define pREG_DMC0_DLLCTL                 ((volatile uint32_t *)REG_DMC0_DLLCTL)                  /* DMC0 DLL Control Register */
-#define pREG_DMC0_PHY_CTL0               ((volatile uint32_t *)REG_DMC0_PHY_CTL0)                /* DMC0 PHY Control 0 Register */
-#define pREG_DMC0_PHY_CTL1               ((volatile uint32_t *)REG_DMC0_PHY_CTL1)                /* DMC0 PHY Control 1 Register */
-#define pREG_DMC0_PHY_CTL2               ((volatile uint32_t *)REG_DMC0_PHY_CTL2)                /* DMC0 PHY Control 2 Register */
-#define pREG_DMC0_PHY_CTL3               ((volatile uint32_t *)REG_DMC0_PHY_CTL3)                /* DMC0 PHY Control 3 Register */
-#define pREG_DMC0_PADCTL                 ((volatile uint32_t *)REG_DMC0_PADCTL)                  /* DMC0 PAD Control Register */
-
-
-/* =========================================================================
-       SCB0
-   ========================================================================= */
-#define pREG_SCB0_ARBR0                  ((volatile uint32_t *)REG_SCB0_ARBR0)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR1                  ((volatile uint32_t *)REG_SCB0_ARBR1)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR2                  ((volatile uint32_t *)REG_SCB0_ARBR2)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR3                  ((volatile uint32_t *)REG_SCB0_ARBR3)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR4                  ((volatile uint32_t *)REG_SCB0_ARBR4)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR5                  ((volatile uint32_t *)REG_SCB0_ARBR5)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBW0                  ((volatile uint32_t *)REG_SCB0_ARBW0)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW1                  ((volatile uint32_t *)REG_SCB0_ARBW1)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW2                  ((volatile uint32_t *)REG_SCB0_ARBW2)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW3                  ((volatile uint32_t *)REG_SCB0_ARBW3)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW4                  ((volatile uint32_t *)REG_SCB0_ARBW4)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW5                  ((volatile uint32_t *)REG_SCB0_ARBW5)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_SLAVES                 ((volatile uint32_t *)REG_SCB0_SLAVES)                  /* SCB0 Slave Interfaces Number Register */
-#define pREG_SCB0_MASTERS                ((volatile uint32_t *)REG_SCB0_MASTERS)                 /* SCB0 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB1
-   ========================================================================= */
-#define pREG_SCB1_ARBR0                  ((volatile uint32_t *)REG_SCB1_ARBR0)                   /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB1_ARBW0                  ((volatile uint32_t *)REG_SCB1_ARBW0)                   /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB1_SLAVES                 ((volatile uint32_t *)REG_SCB1_SLAVES)                  /* SCB1 Slave Interfaces Number Register */
-#define pREG_SCB1_MASTERS                ((volatile uint32_t *)REG_SCB1_MASTERS)                 /* SCB1 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB2
-   ========================================================================= */
-#define pREG_SCB2_ARBR0                  ((volatile uint32_t *)REG_SCB2_ARBR0)                   /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB2_ARBW0                  ((volatile uint32_t *)REG_SCB2_ARBW0)                   /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB2_SLAVES                 ((volatile uint32_t *)REG_SCB2_SLAVES)                  /* SCB2 Slave Interfaces Number Register */
-#define pREG_SCB2_MASTERS                ((volatile uint32_t *)REG_SCB2_MASTERS)                 /* SCB2 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB3
-   ========================================================================= */
-#define pREG_SCB3_ARBR0                  ((volatile uint32_t *)REG_SCB3_ARBR0)                   /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB3_ARBW0                  ((volatile uint32_t *)REG_SCB3_ARBW0)                   /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB3_SLAVES                 ((volatile uint32_t *)REG_SCB3_SLAVES)                  /* SCB3 Slave Interfaces Number Register */
-#define pREG_SCB3_MASTERS                ((volatile uint32_t *)REG_SCB3_MASTERS)                 /* SCB3 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB4
-   ========================================================================= */
-#define pREG_SCB4_ARBR0                  ((volatile uint32_t *)REG_SCB4_ARBR0)                   /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB4_ARBW0                  ((volatile uint32_t *)REG_SCB4_ARBW0)                   /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB4_SLAVES                 ((volatile uint32_t *)REG_SCB4_SLAVES)                  /* SCB4 Slave Interfaces Number Register */
-#define pREG_SCB4_MASTERS                ((volatile uint32_t *)REG_SCB4_MASTERS)                 /* SCB4 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB5
-   ========================================================================= */
-#define pREG_SCB5_ARBR0                  ((volatile uint32_t *)REG_SCB5_ARBR0)                   /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB5_ARBW0                  ((volatile uint32_t *)REG_SCB5_ARBW0)                   /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB5_SLAVES                 ((volatile uint32_t *)REG_SCB5_SLAVES)                  /* SCB5 Slave Interfaces Number Register */
-#define pREG_SCB5_MASTERS                ((volatile uint32_t *)REG_SCB5_MASTERS)                 /* SCB5 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB6
-   ========================================================================= */
-#define pREG_SCB6_ARBR0                  ((volatile uint32_t *)REG_SCB6_ARBR0)                   /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB6_ARBW0                  ((volatile uint32_t *)REG_SCB6_ARBW0)                   /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB6_SLAVES                 ((volatile uint32_t *)REG_SCB6_SLAVES)                  /* SCB6 Slave Interfaces Number Register */
-#define pREG_SCB6_MASTERS                ((volatile uint32_t *)REG_SCB6_MASTERS)                 /* SCB6 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB7
-   ========================================================================= */
-#define pREG_SCB7_ARBR0                  ((volatile uint32_t *)REG_SCB7_ARBR0)                   /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB7_ARBW0                  ((volatile uint32_t *)REG_SCB7_ARBW0)                   /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB7_SLAVES                 ((volatile uint32_t *)REG_SCB7_SLAVES)                  /* SCB7 Slave Interfaces Number Register */
-#define pREG_SCB7_MASTERS                ((volatile uint32_t *)REG_SCB7_MASTERS)                 /* SCB7 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB8
-   ========================================================================= */
-#define pREG_SCB8_ARBR0                  ((volatile uint32_t *)REG_SCB8_ARBR0)                   /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB8_ARBW0                  ((volatile uint32_t *)REG_SCB8_ARBW0)                   /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB8_SLAVES                 ((volatile uint32_t *)REG_SCB8_SLAVES)                  /* SCB8 Slave Interfaces Number Register */
-#define pREG_SCB8_MASTERS                ((volatile uint32_t *)REG_SCB8_MASTERS)                 /* SCB8 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB9
-   ========================================================================= */
-#define pREG_SCB9_ARBR0                  ((volatile uint32_t *)REG_SCB9_ARBR0)                   /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB9_ARBW0                  ((volatile uint32_t *)REG_SCB9_ARBW0)                   /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB9_SLAVES                 ((volatile uint32_t *)REG_SCB9_SLAVES)                  /* SCB9 Slave Interfaces Number Register */
-#define pREG_SCB9_MASTERS                ((volatile uint32_t *)REG_SCB9_MASTERS)                 /* SCB9 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB10
-   ========================================================================= */
-#define pREG_SCB10_ARBR0                 ((volatile uint32_t *)REG_SCB10_ARBR0)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR1                 ((volatile uint32_t *)REG_SCB10_ARBR1)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR2                 ((volatile uint32_t *)REG_SCB10_ARBR2)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBW0                 ((volatile uint32_t *)REG_SCB10_ARBW0)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW1                 ((volatile uint32_t *)REG_SCB10_ARBW1)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW2                 ((volatile uint32_t *)REG_SCB10_ARBW2)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_SLAVES                ((volatile uint32_t *)REG_SCB10_SLAVES)                 /* SCB10 Slave Interfaces Number Register */
-#define pREG_SCB10_MASTERS               ((volatile uint32_t *)REG_SCB10_MASTERS)                /* SCB10 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB11
-   ========================================================================= */
-#define pREG_SCB11_ARBR0                 ((volatile uint32_t *)REG_SCB11_ARBR0)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR1                 ((volatile uint32_t *)REG_SCB11_ARBR1)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR2                 ((volatile uint32_t *)REG_SCB11_ARBR2)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR3                 ((volatile uint32_t *)REG_SCB11_ARBR3)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR4                 ((volatile uint32_t *)REG_SCB11_ARBR4)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR5                 ((volatile uint32_t *)REG_SCB11_ARBR5)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR6                 ((volatile uint32_t *)REG_SCB11_ARBR6)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBW0                 ((volatile uint32_t *)REG_SCB11_ARBW0)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW1                 ((volatile uint32_t *)REG_SCB11_ARBW1)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW2                 ((volatile uint32_t *)REG_SCB11_ARBW2)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW3                 ((volatile uint32_t *)REG_SCB11_ARBW3)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW4                 ((volatile uint32_t *)REG_SCB11_ARBW4)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW5                 ((volatile uint32_t *)REG_SCB11_ARBW5)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW6                 ((volatile uint32_t *)REG_SCB11_ARBW6)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_SLAVES                ((volatile uint32_t *)REG_SCB11_SLAVES)                 /* SCB11 Slave Interfaces Number Register */
-#define pREG_SCB11_MASTERS               ((volatile uint32_t *)REG_SCB11_MASTERS)                /* SCB11 Master Interfaces Number Register */
-
-
-/* =========================================================================
-       L2CTL0
-   ========================================================================= */
-#define pREG_L2CTL0_CTL                  ((volatile uint32_t *)REG_L2CTL0_CTL)                   /* L2CTL0 Control Register */
-#define pREG_L2CTL0_ACTL_C0              ((volatile uint32_t *)REG_L2CTL0_ACTL_C0)               /* L2CTL0 Access Control Core 0 Register */
-#define pREG_L2CTL0_ACTL_C1              ((volatile uint32_t *)REG_L2CTL0_ACTL_C1)               /* L2CTL0 Access Control Core 1 Register */
-#define pREG_L2CTL0_ACTL_SYS             ((volatile uint32_t *)REG_L2CTL0_ACTL_SYS)              /* L2CTL0 Access Control System Register */
-#define pREG_L2CTL0_STAT                 ((volatile uint32_t *)REG_L2CTL0_STAT)                  /* L2CTL0 Status Register */
-#define pREG_L2CTL0_RPCR                 ((volatile uint32_t *)REG_L2CTL0_RPCR)                  /* L2CTL0 Read Priority Count Register */
-#define pREG_L2CTL0_WPCR                 ((volatile uint32_t *)REG_L2CTL0_WPCR)                  /* L2CTL0 Write Priority Count Register */
-#define pREG_L2CTL0_RFA                  ((void * volatile *)REG_L2CTL0_RFA)                     /* L2CTL0 Refresh Address Register */
-#define pREG_L2CTL0_ERRADDR0             ((void * volatile *)REG_L2CTL0_ERRADDR0)                /* L2CTL0 ECC Error Address 0 Register */
-#define pREG_L2CTL0_ERRADDR1             ((void * volatile *)REG_L2CTL0_ERRADDR1)                /* L2CTL0 ECC Error Address 1 Register */
-#define pREG_L2CTL0_ERRADDR2             ((void * volatile *)REG_L2CTL0_ERRADDR2)                /* L2CTL0 ECC Error Address 2 Register */
-#define pREG_L2CTL0_ERRADDR3             ((void * volatile *)REG_L2CTL0_ERRADDR3)                /* L2CTL0 ECC Error Address 3 Register */
-#define pREG_L2CTL0_ERRADDR4             ((void * volatile *)REG_L2CTL0_ERRADDR4)                /* L2CTL0 ECC Error Address 4 Register */
-#define pREG_L2CTL0_ERRADDR5             ((void * volatile *)REG_L2CTL0_ERRADDR5)                /* L2CTL0 ECC Error Address 5 Register */
-#define pREG_L2CTL0_ERRADDR6             ((void * volatile *)REG_L2CTL0_ERRADDR6)                /* L2CTL0 ECC Error Address 6 Register */
-#define pREG_L2CTL0_ERRADDR7             ((void * volatile *)REG_L2CTL0_ERRADDR7)                /* L2CTL0 ECC Error Address 7 Register */
-#define pREG_L2CTL0_ET0                  ((volatile uint32_t *)REG_L2CTL0_ET0)                   /* L2CTL0 Error Type 0 Register */
-#define pREG_L2CTL0_EADDR0               ((void * volatile *)REG_L2CTL0_EADDR0)                  /* L2CTL0 Error Type 0 Address Register */
-#define pREG_L2CTL0_ET1                  ((volatile uint32_t *)REG_L2CTL0_ET1)                   /* L2CTL0 Error Type 1 Register */
-#define pREG_L2CTL0_EADDR1               ((void * volatile *)REG_L2CTL0_EADDR1)                  /* L2CTL0 Error Type 1 Address Register */
-
-
-/* =========================================================================
-       SEC0
-   ========================================================================= */
-
-/*    SEC Core Interface (SCI) Registers    */
-#define pREG_SEC0_CCTL0                  ((volatile uint32_t *)REG_SEC0_CCTL0)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CCTL1                  ((volatile uint32_t *)REG_SEC0_CCTL1)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CSTAT0                 ((volatile uint32_t *)REG_SEC0_CSTAT0)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CSTAT1                 ((volatile uint32_t *)REG_SEC0_CSTAT1)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CPND0                  ((volatile uint32_t *)REG_SEC0_CPND0)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CPND1                  ((volatile uint32_t *)REG_SEC0_CPND1)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CACT0                  ((volatile uint32_t *)REG_SEC0_CACT0)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CACT1                  ((volatile uint32_t *)REG_SEC0_CACT1)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CPMSK0                 ((volatile uint32_t *)REG_SEC0_CPMSK0)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CPMSK1                 ((volatile uint32_t *)REG_SEC0_CPMSK1)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CGMSK0                 ((volatile uint32_t *)REG_SEC0_CGMSK0)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CGMSK1                 ((volatile uint32_t *)REG_SEC0_CGMSK1)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CPLVL0                 ((volatile uint32_t *)REG_SEC0_CPLVL0)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CPLVL1                 ((volatile uint32_t *)REG_SEC0_CPLVL1)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CSID0                  ((volatile uint32_t *)REG_SEC0_CSID0)                   /* SEC0 SCI Source ID Register n */
-#define pREG_SEC0_CSID1                  ((volatile uint32_t *)REG_SEC0_CSID1)                   /* SEC0 SCI Source ID Register n */
-
-/*    SEC Fault Management Interface (SFI) Registers    */
-#define pREG_SEC0_FCTL                   ((volatile uint32_t *)REG_SEC0_FCTL)                    /* SEC0 Fault Control Register */
-#define pREG_SEC0_FSTAT                  ((volatile uint32_t *)REG_SEC0_FSTAT)                   /* SEC0 Fault Status Register */
-#define pREG_SEC0_FSID                   ((volatile uint32_t *)REG_SEC0_FSID)                    /* SEC0 Fault Source ID Register */
-#define pREG_SEC0_FEND                   ((volatile uint32_t *)REG_SEC0_FEND)                    /* SEC0 Fault End Register */
-#define pREG_SEC0_FDLY                   ((volatile uint32_t *)REG_SEC0_FDLY)                    /* SEC0 Fault Delay Register */
-#define pREG_SEC0_FDLY_CUR               ((volatile uint32_t *)REG_SEC0_FDLY_CUR)                /* SEC0 Fault Delay Current Register */
-#define pREG_SEC0_FSRDLY                 ((volatile uint32_t *)REG_SEC0_FSRDLY)                  /* SEC0 Fault System Reset Delay Register */
-#define pREG_SEC0_FSRDLY_CUR             ((volatile uint32_t *)REG_SEC0_FSRDLY_CUR)              /* SEC0 Fault System Reset Delay Current Register */
-#define pREG_SEC0_FCOPP                  ((volatile uint32_t *)REG_SEC0_FCOPP)                   /* SEC0 Fault COP Period Register */
-#define pREG_SEC0_FCOPP_CUR              ((volatile uint32_t *)REG_SEC0_FCOPP_CUR)               /* SEC0 Fault COP Period Current Register */
-
-/*    SEC Global Registers    */
-#define pREG_SEC0_GCTL                   ((volatile uint32_t *)REG_SEC0_GCTL)                    /* SEC0 Global Control Register */
-#define pREG_SEC0_GSTAT                  ((volatile uint32_t *)REG_SEC0_GSTAT)                   /* SEC0 Global Status Register */
-#define pREG_SEC0_RAISE                  ((volatile uint32_t *)REG_SEC0_RAISE)                   /* SEC0 Global Raise Register */
-#define pREG_SEC0_END                    ((volatile uint32_t *)REG_SEC0_END)                     /* SEC0 Global End Register */
-
-/*    SEC Source Interface (SSI) Registers    */
-#define pREG_SEC0_SCTL0                  ((volatile uint32_t *)REG_SEC0_SCTL0)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL1                  ((volatile uint32_t *)REG_SEC0_SCTL1)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL2                  ((volatile uint32_t *)REG_SEC0_SCTL2)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL3                  ((volatile uint32_t *)REG_SEC0_SCTL3)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL4                  ((volatile uint32_t *)REG_SEC0_SCTL4)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL5                  ((volatile uint32_t *)REG_SEC0_SCTL5)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL6                  ((volatile uint32_t *)REG_SEC0_SCTL6)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL7                  ((volatile uint32_t *)REG_SEC0_SCTL7)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL8                  ((volatile uint32_t *)REG_SEC0_SCTL8)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL9                  ((volatile uint32_t *)REG_SEC0_SCTL9)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL10                 ((volatile uint32_t *)REG_SEC0_SCTL10)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL11                 ((volatile uint32_t *)REG_SEC0_SCTL11)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL12                 ((volatile uint32_t *)REG_SEC0_SCTL12)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL13                 ((volatile uint32_t *)REG_SEC0_SCTL13)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL14                 ((volatile uint32_t *)REG_SEC0_SCTL14)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL15                 ((volatile uint32_t *)REG_SEC0_SCTL15)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL16                 ((volatile uint32_t *)REG_SEC0_SCTL16)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL17                 ((volatile uint32_t *)REG_SEC0_SCTL17)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL18                 ((volatile uint32_t *)REG_SEC0_SCTL18)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL19                 ((volatile uint32_t *)REG_SEC0_SCTL19)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL20                 ((volatile uint32_t *)REG_SEC0_SCTL20)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL21                 ((volatile uint32_t *)REG_SEC0_SCTL21)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL22                 ((volatile uint32_t *)REG_SEC0_SCTL22)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL23                 ((volatile uint32_t *)REG_SEC0_SCTL23)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL24                 ((volatile uint32_t *)REG_SEC0_SCTL24)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL25                 ((volatile uint32_t *)REG_SEC0_SCTL25)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL26                 ((volatile uint32_t *)REG_SEC0_SCTL26)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL27                 ((volatile uint32_t *)REG_SEC0_SCTL27)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL28                 ((volatile uint32_t *)REG_SEC0_SCTL28)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL29                 ((volatile uint32_t *)REG_SEC0_SCTL29)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL30                 ((volatile uint32_t *)REG_SEC0_SCTL30)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL31                 ((volatile uint32_t *)REG_SEC0_SCTL31)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL32                 ((volatile uint32_t *)REG_SEC0_SCTL32)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL33                 ((volatile uint32_t *)REG_SEC0_SCTL33)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL34                 ((volatile uint32_t *)REG_SEC0_SCTL34)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL35                 ((volatile uint32_t *)REG_SEC0_SCTL35)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL36                 ((volatile uint32_t *)REG_SEC0_SCTL36)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL37                 ((volatile uint32_t *)REG_SEC0_SCTL37)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL38                 ((volatile uint32_t *)REG_SEC0_SCTL38)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL39                 ((volatile uint32_t *)REG_SEC0_SCTL39)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL40                 ((volatile uint32_t *)REG_SEC0_SCTL40)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL41                 ((volatile uint32_t *)REG_SEC0_SCTL41)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL42                 ((volatile uint32_t *)REG_SEC0_SCTL42)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL43                 ((volatile uint32_t *)REG_SEC0_SCTL43)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL44                 ((volatile uint32_t *)REG_SEC0_SCTL44)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL45                 ((volatile uint32_t *)REG_SEC0_SCTL45)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL46                 ((volatile uint32_t *)REG_SEC0_SCTL46)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL47                 ((volatile uint32_t *)REG_SEC0_SCTL47)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL48                 ((volatile uint32_t *)REG_SEC0_SCTL48)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL49                 ((volatile uint32_t *)REG_SEC0_SCTL49)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL50                 ((volatile uint32_t *)REG_SEC0_SCTL50)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL51                 ((volatile uint32_t *)REG_SEC0_SCTL51)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL52                 ((volatile uint32_t *)REG_SEC0_SCTL52)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL53                 ((volatile uint32_t *)REG_SEC0_SCTL53)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL54                 ((volatile uint32_t *)REG_SEC0_SCTL54)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL55                 ((volatile uint32_t *)REG_SEC0_SCTL55)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL56                 ((volatile uint32_t *)REG_SEC0_SCTL56)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL57                 ((volatile uint32_t *)REG_SEC0_SCTL57)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL58                 ((volatile uint32_t *)REG_SEC0_SCTL58)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL59                 ((volatile uint32_t *)REG_SEC0_SCTL59)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL60                 ((volatile uint32_t *)REG_SEC0_SCTL60)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL61                 ((volatile uint32_t *)REG_SEC0_SCTL61)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL62                 ((volatile uint32_t *)REG_SEC0_SCTL62)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL63                 ((volatile uint32_t *)REG_SEC0_SCTL63)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL64                 ((volatile uint32_t *)REG_SEC0_SCTL64)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL65                 ((volatile uint32_t *)REG_SEC0_SCTL65)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL66                 ((volatile uint32_t *)REG_SEC0_SCTL66)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL67                 ((volatile uint32_t *)REG_SEC0_SCTL67)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL68                 ((volatile uint32_t *)REG_SEC0_SCTL68)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL69                 ((volatile uint32_t *)REG_SEC0_SCTL69)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL70                 ((volatile uint32_t *)REG_SEC0_SCTL70)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL71                 ((volatile uint32_t *)REG_SEC0_SCTL71)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL72                 ((volatile uint32_t *)REG_SEC0_SCTL72)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL73                 ((volatile uint32_t *)REG_SEC0_SCTL73)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL74                 ((volatile uint32_t *)REG_SEC0_SCTL74)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL75                 ((volatile uint32_t *)REG_SEC0_SCTL75)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL76                 ((volatile uint32_t *)REG_SEC0_SCTL76)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL77                 ((volatile uint32_t *)REG_SEC0_SCTL77)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL78                 ((volatile uint32_t *)REG_SEC0_SCTL78)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL79                 ((volatile uint32_t *)REG_SEC0_SCTL79)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL80                 ((volatile uint32_t *)REG_SEC0_SCTL80)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL81                 ((volatile uint32_t *)REG_SEC0_SCTL81)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL82                 ((volatile uint32_t *)REG_SEC0_SCTL82)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL83                 ((volatile uint32_t *)REG_SEC0_SCTL83)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL84                 ((volatile uint32_t *)REG_SEC0_SCTL84)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL85                 ((volatile uint32_t *)REG_SEC0_SCTL85)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL86                 ((volatile uint32_t *)REG_SEC0_SCTL86)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL87                 ((volatile uint32_t *)REG_SEC0_SCTL87)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL88                 ((volatile uint32_t *)REG_SEC0_SCTL88)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL89                 ((volatile uint32_t *)REG_SEC0_SCTL89)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL90                 ((volatile uint32_t *)REG_SEC0_SCTL90)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL91                 ((volatile uint32_t *)REG_SEC0_SCTL91)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL92                 ((volatile uint32_t *)REG_SEC0_SCTL92)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL93                 ((volatile uint32_t *)REG_SEC0_SCTL93)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL94                 ((volatile uint32_t *)REG_SEC0_SCTL94)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL95                 ((volatile uint32_t *)REG_SEC0_SCTL95)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL96                 ((volatile uint32_t *)REG_SEC0_SCTL96)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL97                 ((volatile uint32_t *)REG_SEC0_SCTL97)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL98                 ((volatile uint32_t *)REG_SEC0_SCTL98)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL99                 ((volatile uint32_t *)REG_SEC0_SCTL99)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL100                ((volatile uint32_t *)REG_SEC0_SCTL100)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL101                ((volatile uint32_t *)REG_SEC0_SCTL101)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL102                ((volatile uint32_t *)REG_SEC0_SCTL102)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL103                ((volatile uint32_t *)REG_SEC0_SCTL103)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL104                ((volatile uint32_t *)REG_SEC0_SCTL104)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL105                ((volatile uint32_t *)REG_SEC0_SCTL105)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL106                ((volatile uint32_t *)REG_SEC0_SCTL106)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL107                ((volatile uint32_t *)REG_SEC0_SCTL107)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL108                ((volatile uint32_t *)REG_SEC0_SCTL108)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL109                ((volatile uint32_t *)REG_SEC0_SCTL109)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL110                ((volatile uint32_t *)REG_SEC0_SCTL110)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL111                ((volatile uint32_t *)REG_SEC0_SCTL111)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL112                ((volatile uint32_t *)REG_SEC0_SCTL112)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL113                ((volatile uint32_t *)REG_SEC0_SCTL113)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL114                ((volatile uint32_t *)REG_SEC0_SCTL114)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL115                ((volatile uint32_t *)REG_SEC0_SCTL115)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL116                ((volatile uint32_t *)REG_SEC0_SCTL116)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL117                ((volatile uint32_t *)REG_SEC0_SCTL117)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL118                ((volatile uint32_t *)REG_SEC0_SCTL118)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL119                ((volatile uint32_t *)REG_SEC0_SCTL119)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL120                ((volatile uint32_t *)REG_SEC0_SCTL120)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL121                ((volatile uint32_t *)REG_SEC0_SCTL121)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL122                ((volatile uint32_t *)REG_SEC0_SCTL122)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL123                ((volatile uint32_t *)REG_SEC0_SCTL123)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL124                ((volatile uint32_t *)REG_SEC0_SCTL124)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL125                ((volatile uint32_t *)REG_SEC0_SCTL125)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL126                ((volatile uint32_t *)REG_SEC0_SCTL126)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL127                ((volatile uint32_t *)REG_SEC0_SCTL127)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL128                ((volatile uint32_t *)REG_SEC0_SCTL128)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL129                ((volatile uint32_t *)REG_SEC0_SCTL129)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL130                ((volatile uint32_t *)REG_SEC0_SCTL130)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL131                ((volatile uint32_t *)REG_SEC0_SCTL131)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL132                ((volatile uint32_t *)REG_SEC0_SCTL132)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL133                ((volatile uint32_t *)REG_SEC0_SCTL133)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL134                ((volatile uint32_t *)REG_SEC0_SCTL134)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL135                ((volatile uint32_t *)REG_SEC0_SCTL135)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL136                ((volatile uint32_t *)REG_SEC0_SCTL136)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL137                ((volatile uint32_t *)REG_SEC0_SCTL137)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL138                ((volatile uint32_t *)REG_SEC0_SCTL138)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL139                ((volatile uint32_t *)REG_SEC0_SCTL139)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SSTAT0                 ((volatile uint32_t *)REG_SEC0_SSTAT0)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT1                 ((volatile uint32_t *)REG_SEC0_SSTAT1)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT2                 ((volatile uint32_t *)REG_SEC0_SSTAT2)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT3                 ((volatile uint32_t *)REG_SEC0_SSTAT3)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT4                 ((volatile uint32_t *)REG_SEC0_SSTAT4)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT5                 ((volatile uint32_t *)REG_SEC0_SSTAT5)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT6                 ((volatile uint32_t *)REG_SEC0_SSTAT6)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT7                 ((volatile uint32_t *)REG_SEC0_SSTAT7)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT8                 ((volatile uint32_t *)REG_SEC0_SSTAT8)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT9                 ((volatile uint32_t *)REG_SEC0_SSTAT9)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT10                ((volatile uint32_t *)REG_SEC0_SSTAT10)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT11                ((volatile uint32_t *)REG_SEC0_SSTAT11)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT12                ((volatile uint32_t *)REG_SEC0_SSTAT12)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT13                ((volatile uint32_t *)REG_SEC0_SSTAT13)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT14                ((volatile uint32_t *)REG_SEC0_SSTAT14)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT15                ((volatile uint32_t *)REG_SEC0_SSTAT15)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT16                ((volatile uint32_t *)REG_SEC0_SSTAT16)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT17                ((volatile uint32_t *)REG_SEC0_SSTAT17)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT18                ((volatile uint32_t *)REG_SEC0_SSTAT18)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT19                ((volatile uint32_t *)REG_SEC0_SSTAT19)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT20                ((volatile uint32_t *)REG_SEC0_SSTAT20)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT21                ((volatile uint32_t *)REG_SEC0_SSTAT21)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT22                ((volatile uint32_t *)REG_SEC0_SSTAT22)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT23                ((volatile uint32_t *)REG_SEC0_SSTAT23)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT24                ((volatile uint32_t *)REG_SEC0_SSTAT24)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT25                ((volatile uint32_t *)REG_SEC0_SSTAT25)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT26                ((volatile uint32_t *)REG_SEC0_SSTAT26)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT27                ((volatile uint32_t *)REG_SEC0_SSTAT27)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT28                ((volatile uint32_t *)REG_SEC0_SSTAT28)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT29                ((volatile uint32_t *)REG_SEC0_SSTAT29)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT30                ((volatile uint32_t *)REG_SEC0_SSTAT30)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT31                ((volatile uint32_t *)REG_SEC0_SSTAT31)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT32                ((volatile uint32_t *)REG_SEC0_SSTAT32)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT33                ((volatile uint32_t *)REG_SEC0_SSTAT33)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT34                ((volatile uint32_t *)REG_SEC0_SSTAT34)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT35                ((volatile uint32_t *)REG_SEC0_SSTAT35)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT36                ((volatile uint32_t *)REG_SEC0_SSTAT36)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT37                ((volatile uint32_t *)REG_SEC0_SSTAT37)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT38                ((volatile uint32_t *)REG_SEC0_SSTAT38)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT39                ((volatile uint32_t *)REG_SEC0_SSTAT39)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT40                ((volatile uint32_t *)REG_SEC0_SSTAT40)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT41                ((volatile uint32_t *)REG_SEC0_SSTAT41)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT42                ((volatile uint32_t *)REG_SEC0_SSTAT42)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT43                ((volatile uint32_t *)REG_SEC0_SSTAT43)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT44                ((volatile uint32_t *)REG_SEC0_SSTAT44)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT45                ((volatile uint32_t *)REG_SEC0_SSTAT45)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT46                ((volatile uint32_t *)REG_SEC0_SSTAT46)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT47                ((volatile uint32_t *)REG_SEC0_SSTAT47)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT48                ((volatile uint32_t *)REG_SEC0_SSTAT48)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT49                ((volatile uint32_t *)REG_SEC0_SSTAT49)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT50                ((volatile uint32_t *)REG_SEC0_SSTAT50)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT51                ((volatile uint32_t *)REG_SEC0_SSTAT51)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT52                ((volatile uint32_t *)REG_SEC0_SSTAT52)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT53                ((volatile uint32_t *)REG_SEC0_SSTAT53)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT54                ((volatile uint32_t *)REG_SEC0_SSTAT54)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT55                ((volatile uint32_t *)REG_SEC0_SSTAT55)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT56                ((volatile uint32_t *)REG_SEC0_SSTAT56)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT57                ((volatile uint32_t *)REG_SEC0_SSTAT57)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT58                ((volatile uint32_t *)REG_SEC0_SSTAT58)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT59                ((volatile uint32_t *)REG_SEC0_SSTAT59)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT60                ((volatile uint32_t *)REG_SEC0_SSTAT60)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT61                ((volatile uint32_t *)REG_SEC0_SSTAT61)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT62                ((volatile uint32_t *)REG_SEC0_SSTAT62)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT63                ((volatile uint32_t *)REG_SEC0_SSTAT63)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT64                ((volatile uint32_t *)REG_SEC0_SSTAT64)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT65                ((volatile uint32_t *)REG_SEC0_SSTAT65)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT66                ((volatile uint32_t *)REG_SEC0_SSTAT66)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT67                ((volatile uint32_t *)REG_SEC0_SSTAT67)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT68                ((volatile uint32_t *)REG_SEC0_SSTAT68)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT69                ((volatile uint32_t *)REG_SEC0_SSTAT69)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT70                ((volatile uint32_t *)REG_SEC0_SSTAT70)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT71                ((volatile uint32_t *)REG_SEC0_SSTAT71)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT72                ((volatile uint32_t *)REG_SEC0_SSTAT72)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT73                ((volatile uint32_t *)REG_SEC0_SSTAT73)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT74                ((volatile uint32_t *)REG_SEC0_SSTAT74)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT75                ((volatile uint32_t *)REG_SEC0_SSTAT75)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT76                ((volatile uint32_t *)REG_SEC0_SSTAT76)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT77                ((volatile uint32_t *)REG_SEC0_SSTAT77)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT78                ((volatile uint32_t *)REG_SEC0_SSTAT78)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT79                ((volatile uint32_t *)REG_SEC0_SSTAT79)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT80                ((volatile uint32_t *)REG_SEC0_SSTAT80)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT81                ((volatile uint32_t *)REG_SEC0_SSTAT81)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT82                ((volatile uint32_t *)REG_SEC0_SSTAT82)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT83                ((volatile uint32_t *)REG_SEC0_SSTAT83)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT84                ((volatile uint32_t *)REG_SEC0_SSTAT84)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT85                ((volatile uint32_t *)REG_SEC0_SSTAT85)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT86                ((volatile uint32_t *)REG_SEC0_SSTAT86)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT87                ((volatile uint32_t *)REG_SEC0_SSTAT87)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT88                ((volatile uint32_t *)REG_SEC0_SSTAT88)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT89                ((volatile uint32_t *)REG_SEC0_SSTAT89)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT90                ((volatile uint32_t *)REG_SEC0_SSTAT90)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT91                ((volatile uint32_t *)REG_SEC0_SSTAT91)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT92                ((volatile uint32_t *)REG_SEC0_SSTAT92)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT93                ((volatile uint32_t *)REG_SEC0_SSTAT93)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT94                ((volatile uint32_t *)REG_SEC0_SSTAT94)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT95                ((volatile uint32_t *)REG_SEC0_SSTAT95)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT96                ((volatile uint32_t *)REG_SEC0_SSTAT96)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT97                ((volatile uint32_t *)REG_SEC0_SSTAT97)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT98                ((volatile uint32_t *)REG_SEC0_SSTAT98)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT99                ((volatile uint32_t *)REG_SEC0_SSTAT99)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT100               ((volatile uint32_t *)REG_SEC0_SSTAT100)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT101               ((volatile uint32_t *)REG_SEC0_SSTAT101)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT102               ((volatile uint32_t *)REG_SEC0_SSTAT102)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT103               ((volatile uint32_t *)REG_SEC0_SSTAT103)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT104               ((volatile uint32_t *)REG_SEC0_SSTAT104)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT105               ((volatile uint32_t *)REG_SEC0_SSTAT105)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT106               ((volatile uint32_t *)REG_SEC0_SSTAT106)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT107               ((volatile uint32_t *)REG_SEC0_SSTAT107)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT108               ((volatile uint32_t *)REG_SEC0_SSTAT108)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT109               ((volatile uint32_t *)REG_SEC0_SSTAT109)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT110               ((volatile uint32_t *)REG_SEC0_SSTAT110)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT111               ((volatile uint32_t *)REG_SEC0_SSTAT111)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT112               ((volatile uint32_t *)REG_SEC0_SSTAT112)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT113               ((volatile uint32_t *)REG_SEC0_SSTAT113)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT114               ((volatile uint32_t *)REG_SEC0_SSTAT114)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT115               ((volatile uint32_t *)REG_SEC0_SSTAT115)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT116               ((volatile uint32_t *)REG_SEC0_SSTAT116)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT117               ((volatile uint32_t *)REG_SEC0_SSTAT117)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT118               ((volatile uint32_t *)REG_SEC0_SSTAT118)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT119               ((volatile uint32_t *)REG_SEC0_SSTAT119)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT120               ((volatile uint32_t *)REG_SEC0_SSTAT120)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT121               ((volatile uint32_t *)REG_SEC0_SSTAT121)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT122               ((volatile uint32_t *)REG_SEC0_SSTAT122)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT123               ((volatile uint32_t *)REG_SEC0_SSTAT123)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT124               ((volatile uint32_t *)REG_SEC0_SSTAT124)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT125               ((volatile uint32_t *)REG_SEC0_SSTAT125)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT126               ((volatile uint32_t *)REG_SEC0_SSTAT126)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT127               ((volatile uint32_t *)REG_SEC0_SSTAT127)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT128               ((volatile uint32_t *)REG_SEC0_SSTAT128)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT129               ((volatile uint32_t *)REG_SEC0_SSTAT129)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT130               ((volatile uint32_t *)REG_SEC0_SSTAT130)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT131               ((volatile uint32_t *)REG_SEC0_SSTAT131)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT132               ((volatile uint32_t *)REG_SEC0_SSTAT132)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT133               ((volatile uint32_t *)REG_SEC0_SSTAT133)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT134               ((volatile uint32_t *)REG_SEC0_SSTAT134)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT135               ((volatile uint32_t *)REG_SEC0_SSTAT135)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT136               ((volatile uint32_t *)REG_SEC0_SSTAT136)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT137               ((volatile uint32_t *)REG_SEC0_SSTAT137)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT138               ((volatile uint32_t *)REG_SEC0_SSTAT138)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT139               ((volatile uint32_t *)REG_SEC0_SSTAT139)                /* SEC0 Source Status Register n */
-
-
-/* =========================================================================
-       TRU0
-   ========================================================================= */
-#define pREG_TRU0_SSR0                   ((volatile uint32_t *)REG_TRU0_SSR0)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR1                   ((volatile uint32_t *)REG_TRU0_SSR1)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR2                   ((volatile uint32_t *)REG_TRU0_SSR2)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR3                   ((volatile uint32_t *)REG_TRU0_SSR3)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR4                   ((volatile uint32_t *)REG_TRU0_SSR4)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR5                   ((volatile uint32_t *)REG_TRU0_SSR5)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR6                   ((volatile uint32_t *)REG_TRU0_SSR6)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR7                   ((volatile uint32_t *)REG_TRU0_SSR7)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR8                   ((volatile uint32_t *)REG_TRU0_SSR8)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR9                   ((volatile uint32_t *)REG_TRU0_SSR9)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR10                  ((volatile uint32_t *)REG_TRU0_SSR10)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR11                  ((volatile uint32_t *)REG_TRU0_SSR11)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR12                  ((volatile uint32_t *)REG_TRU0_SSR12)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR13                  ((volatile uint32_t *)REG_TRU0_SSR13)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR14                  ((volatile uint32_t *)REG_TRU0_SSR14)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR15                  ((volatile uint32_t *)REG_TRU0_SSR15)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR16                  ((volatile uint32_t *)REG_TRU0_SSR16)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR17                  ((volatile uint32_t *)REG_TRU0_SSR17)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR18                  ((volatile uint32_t *)REG_TRU0_SSR18)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR19                  ((volatile uint32_t *)REG_TRU0_SSR19)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR20                  ((volatile uint32_t *)REG_TRU0_SSR20)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR21                  ((volatile uint32_t *)REG_TRU0_SSR21)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR22                  ((volatile uint32_t *)REG_TRU0_SSR22)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR23                  ((volatile uint32_t *)REG_TRU0_SSR23)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR24                  ((volatile uint32_t *)REG_TRU0_SSR24)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR25                  ((volatile uint32_t *)REG_TRU0_SSR25)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR26                  ((volatile uint32_t *)REG_TRU0_SSR26)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR27                  ((volatile uint32_t *)REG_TRU0_SSR27)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR28                  ((volatile uint32_t *)REG_TRU0_SSR28)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR29                  ((volatile uint32_t *)REG_TRU0_SSR29)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR30                  ((volatile uint32_t *)REG_TRU0_SSR30)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR31                  ((volatile uint32_t *)REG_TRU0_SSR31)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR32                  ((volatile uint32_t *)REG_TRU0_SSR32)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR33                  ((volatile uint32_t *)REG_TRU0_SSR33)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR34                  ((volatile uint32_t *)REG_TRU0_SSR34)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR35                  ((volatile uint32_t *)REG_TRU0_SSR35)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR36                  ((volatile uint32_t *)REG_TRU0_SSR36)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR37                  ((volatile uint32_t *)REG_TRU0_SSR37)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR38                  ((volatile uint32_t *)REG_TRU0_SSR38)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR39                  ((volatile uint32_t *)REG_TRU0_SSR39)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR40                  ((volatile uint32_t *)REG_TRU0_SSR40)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR41                  ((volatile uint32_t *)REG_TRU0_SSR41)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR42                  ((volatile uint32_t *)REG_TRU0_SSR42)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR43                  ((volatile uint32_t *)REG_TRU0_SSR43)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR44                  ((volatile uint32_t *)REG_TRU0_SSR44)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR45                  ((volatile uint32_t *)REG_TRU0_SSR45)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR46                  ((volatile uint32_t *)REG_TRU0_SSR46)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR47                  ((volatile uint32_t *)REG_TRU0_SSR47)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR48                  ((volatile uint32_t *)REG_TRU0_SSR48)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR49                  ((volatile uint32_t *)REG_TRU0_SSR49)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR50                  ((volatile uint32_t *)REG_TRU0_SSR50)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR51                  ((volatile uint32_t *)REG_TRU0_SSR51)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR52                  ((volatile uint32_t *)REG_TRU0_SSR52)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR53                  ((volatile uint32_t *)REG_TRU0_SSR53)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR54                  ((volatile uint32_t *)REG_TRU0_SSR54)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR55                  ((volatile uint32_t *)REG_TRU0_SSR55)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR56                  ((volatile uint32_t *)REG_TRU0_SSR56)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR57                  ((volatile uint32_t *)REG_TRU0_SSR57)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR58                  ((volatile uint32_t *)REG_TRU0_SSR58)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR59                  ((volatile uint32_t *)REG_TRU0_SSR59)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR60                  ((volatile uint32_t *)REG_TRU0_SSR60)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR61                  ((volatile uint32_t *)REG_TRU0_SSR61)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR62                  ((volatile uint32_t *)REG_TRU0_SSR62)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR63                  ((volatile uint32_t *)REG_TRU0_SSR63)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR64                  ((volatile uint32_t *)REG_TRU0_SSR64)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR65                  ((volatile uint32_t *)REG_TRU0_SSR65)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR66                  ((volatile uint32_t *)REG_TRU0_SSR66)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR67                  ((volatile uint32_t *)REG_TRU0_SSR67)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR68                  ((volatile uint32_t *)REG_TRU0_SSR68)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR69                  ((volatile uint32_t *)REG_TRU0_SSR69)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR70                  ((volatile uint32_t *)REG_TRU0_SSR70)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR71                  ((volatile uint32_t *)REG_TRU0_SSR71)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR72                  ((volatile uint32_t *)REG_TRU0_SSR72)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR73                  ((volatile uint32_t *)REG_TRU0_SSR73)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR74                  ((volatile uint32_t *)REG_TRU0_SSR74)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR75                  ((volatile uint32_t *)REG_TRU0_SSR75)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR76                  ((volatile uint32_t *)REG_TRU0_SSR76)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR77                  ((volatile uint32_t *)REG_TRU0_SSR77)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR78                  ((volatile uint32_t *)REG_TRU0_SSR78)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR79                  ((volatile uint32_t *)REG_TRU0_SSR79)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR80                  ((volatile uint32_t *)REG_TRU0_SSR80)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR81                  ((volatile uint32_t *)REG_TRU0_SSR81)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR82                  ((volatile uint32_t *)REG_TRU0_SSR82)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR83                  ((volatile uint32_t *)REG_TRU0_SSR83)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR84                  ((volatile uint32_t *)REG_TRU0_SSR84)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR85                  ((volatile uint32_t *)REG_TRU0_SSR85)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR86                  ((volatile uint32_t *)REG_TRU0_SSR86)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_MTR                    ((volatile uint32_t *)REG_TRU0_MTR)                     /* TRU0 Master Trigger Register */
-#define pREG_TRU0_ERRADDR                ((volatile uint32_t *)REG_TRU0_ERRADDR)                 /* TRU0 Error Address Register */
-#define pREG_TRU0_STAT                   ((volatile uint32_t *)REG_TRU0_STAT)                    /* TRU0 Status Information Register */
-#define pREG_TRU0_REVID                  ((volatile uint32_t *)REG_TRU0_REVID)                   /* TRU0 Revision ID Register */
-#define pREG_TRU0_GCTL                   ((volatile uint32_t *)REG_TRU0_GCTL)                    /* TRU0 Global Control Register */
-
-
-/* =========================================================================
-       RCU0
-   ========================================================================= */
-#define pREG_RCU0_CTL                    ((volatile uint32_t *)REG_RCU0_CTL)                     /* RCU0 Control Register */
-#define pREG_RCU0_STAT                   ((volatile uint32_t *)REG_RCU0_STAT)                    /* RCU0 Status Register */
-#define pREG_RCU0_CRCTL                  ((volatile uint32_t *)REG_RCU0_CRCTL)                   /* RCU0 Core Reset Control Register */
-#define pREG_RCU0_CRSTAT                 ((volatile uint32_t *)REG_RCU0_CRSTAT)                  /* RCU0 Core Reset Status Register */
-#define pREG_RCU0_SIDIS                  ((volatile uint32_t *)REG_RCU0_SIDIS)                   /* RCU0 System Interface Disable Register */
-#define pREG_RCU0_SISTAT                 ((volatile uint32_t *)REG_RCU0_SISTAT)                  /* RCU0 System Interface Status Register */
-#define pREG_RCU0_SVECT_LCK              ((volatile uint32_t *)REG_RCU0_SVECT_LCK)               /* RCU0 SVECT Lock Register */
-#define pREG_RCU0_BCODE                  ((volatile uint32_t *)REG_RCU0_BCODE)                   /* RCU0 Boot Code Register */
-#define pREG_RCU0_SVECT0                 ((void * volatile *)REG_RCU0_SVECT0)                    /* RCU0 Software Vector Register n */
-#define pREG_RCU0_SVECT1                 ((void * volatile *)REG_RCU0_SVECT1)                    /* RCU0 Software Vector Register n */
-
-
-/* =========================================================================
-       SPU0
-   ========================================================================= */
-#define pREG_SPU0_CTL                    ((volatile uint32_t *)REG_SPU0_CTL)                     /* SPU0 Control Register */
-#define pREG_SPU0_STAT                   ((volatile uint32_t *)REG_SPU0_STAT)                    /* SPU0 Status Register */
-#define pREG_SPU0_WP0                    ((volatile uint32_t *)REG_SPU0_WP0)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP1                    ((volatile uint32_t *)REG_SPU0_WP1)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP2                    ((volatile uint32_t *)REG_SPU0_WP2)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP3                    ((volatile uint32_t *)REG_SPU0_WP3)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP4                    ((volatile uint32_t *)REG_SPU0_WP4)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP5                    ((volatile uint32_t *)REG_SPU0_WP5)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP6                    ((volatile uint32_t *)REG_SPU0_WP6)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP7                    ((volatile uint32_t *)REG_SPU0_WP7)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP8                    ((volatile uint32_t *)REG_SPU0_WP8)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP9                    ((volatile uint32_t *)REG_SPU0_WP9)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP10                   ((volatile uint32_t *)REG_SPU0_WP10)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP11                   ((volatile uint32_t *)REG_SPU0_WP11)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP12                   ((volatile uint32_t *)REG_SPU0_WP12)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP13                   ((volatile uint32_t *)REG_SPU0_WP13)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP14                   ((volatile uint32_t *)REG_SPU0_WP14)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP15                   ((volatile uint32_t *)REG_SPU0_WP15)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP16                   ((volatile uint32_t *)REG_SPU0_WP16)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP17                   ((volatile uint32_t *)REG_SPU0_WP17)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP18                   ((volatile uint32_t *)REG_SPU0_WP18)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP19                   ((volatile uint32_t *)REG_SPU0_WP19)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP20                   ((volatile uint32_t *)REG_SPU0_WP20)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP21                   ((volatile uint32_t *)REG_SPU0_WP21)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP22                   ((volatile uint32_t *)REG_SPU0_WP22)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP23                   ((volatile uint32_t *)REG_SPU0_WP23)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP24                   ((volatile uint32_t *)REG_SPU0_WP24)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP25                   ((volatile uint32_t *)REG_SPU0_WP25)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP26                   ((volatile uint32_t *)REG_SPU0_WP26)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP27                   ((volatile uint32_t *)REG_SPU0_WP27)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP28                   ((volatile uint32_t *)REG_SPU0_WP28)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP29                   ((volatile uint32_t *)REG_SPU0_WP29)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP30                   ((volatile uint32_t *)REG_SPU0_WP30)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP31                   ((volatile uint32_t *)REG_SPU0_WP31)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP32                   ((volatile uint32_t *)REG_SPU0_WP32)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP33                   ((volatile uint32_t *)REG_SPU0_WP33)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP34                   ((volatile uint32_t *)REG_SPU0_WP34)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP35                   ((volatile uint32_t *)REG_SPU0_WP35)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP36                   ((volatile uint32_t *)REG_SPU0_WP36)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP37                   ((volatile uint32_t *)REG_SPU0_WP37)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP38                   ((volatile uint32_t *)REG_SPU0_WP38)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP39                   ((volatile uint32_t *)REG_SPU0_WP39)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP40                   ((volatile uint32_t *)REG_SPU0_WP40)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP41                   ((volatile uint32_t *)REG_SPU0_WP41)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP42                   ((volatile uint32_t *)REG_SPU0_WP42)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP43                   ((volatile uint32_t *)REG_SPU0_WP43)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP44                   ((volatile uint32_t *)REG_SPU0_WP44)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP45                   ((volatile uint32_t *)REG_SPU0_WP45)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP46                   ((volatile uint32_t *)REG_SPU0_WP46)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP47                   ((volatile uint32_t *)REG_SPU0_WP47)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP48                   ((volatile uint32_t *)REG_SPU0_WP48)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP49                   ((volatile uint32_t *)REG_SPU0_WP49)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP50                   ((volatile uint32_t *)REG_SPU0_WP50)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP51                   ((volatile uint32_t *)REG_SPU0_WP51)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP52                   ((volatile uint32_t *)REG_SPU0_WP52)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP53                   ((volatile uint32_t *)REG_SPU0_WP53)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP54                   ((volatile uint32_t *)REG_SPU0_WP54)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP55                   ((volatile uint32_t *)REG_SPU0_WP55)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP56                   ((volatile uint32_t *)REG_SPU0_WP56)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP57                   ((volatile uint32_t *)REG_SPU0_WP57)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP58                   ((volatile uint32_t *)REG_SPU0_WP58)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP59                   ((volatile uint32_t *)REG_SPU0_WP59)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP60                   ((volatile uint32_t *)REG_SPU0_WP60)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP61                   ((volatile uint32_t *)REG_SPU0_WP61)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP62                   ((volatile uint32_t *)REG_SPU0_WP62)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP63                   ((volatile uint32_t *)REG_SPU0_WP63)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP64                   ((volatile uint32_t *)REG_SPU0_WP64)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP65                   ((volatile uint32_t *)REG_SPU0_WP65)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP66                   ((volatile uint32_t *)REG_SPU0_WP66)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP67                   ((volatile uint32_t *)REG_SPU0_WP67)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP68                   ((volatile uint32_t *)REG_SPU0_WP68)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP69                   ((volatile uint32_t *)REG_SPU0_WP69)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP70                   ((volatile uint32_t *)REG_SPU0_WP70)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP71                   ((volatile uint32_t *)REG_SPU0_WP71)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP72                   ((volatile uint32_t *)REG_SPU0_WP72)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP73                   ((volatile uint32_t *)REG_SPU0_WP73)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP74                   ((volatile uint32_t *)REG_SPU0_WP74)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP75                   ((volatile uint32_t *)REG_SPU0_WP75)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP76                   ((volatile uint32_t *)REG_SPU0_WP76)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP77                   ((volatile uint32_t *)REG_SPU0_WP77)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP78                   ((volatile uint32_t *)REG_SPU0_WP78)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP79                   ((volatile uint32_t *)REG_SPU0_WP79)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP80                   ((volatile uint32_t *)REG_SPU0_WP80)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP81                   ((volatile uint32_t *)REG_SPU0_WP81)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP82                   ((volatile uint32_t *)REG_SPU0_WP82)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP83                   ((volatile uint32_t *)REG_SPU0_WP83)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP84                   ((volatile uint32_t *)REG_SPU0_WP84)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP85                   ((volatile uint32_t *)REG_SPU0_WP85)                    /* SPU0 Write Protect Register n */
-
-
-/* =========================================================================
-       CGU0
-   ========================================================================= */
-#define pREG_CGU0_CTL                    ((volatile uint32_t *)REG_CGU0_CTL)                     /* CGU0 Control Register */
-#define pREG_CGU0_STAT                   ((volatile uint32_t *)REG_CGU0_STAT)                    /* CGU0 Status Register */
-#define pREG_CGU0_DIV                    ((volatile uint32_t *)REG_CGU0_DIV)                     /* CGU0 Divisor Register */
-#define pREG_CGU0_CLKOUTSEL              ((volatile uint32_t *)REG_CGU0_CLKOUTSEL)               /* CGU0 CLKOUT Select Register */
-
-
-/* =========================================================================
-       DPM0
-   ========================================================================= */
-#define pREG_DPM0_CTL                    ((volatile uint32_t *)REG_DPM0_CTL)                     /* DPM0 Control Register */
-#define pREG_DPM0_STAT                   ((volatile uint32_t *)REG_DPM0_STAT)                    /* DPM0 Status Register */
-#define pREG_DPM0_CCBF_DIS               ((volatile uint32_t *)REG_DPM0_CCBF_DIS)                /* DPM0 Core Clock Buffer Disable Register */
-#define pREG_DPM0_CCBF_EN                ((volatile uint32_t *)REG_DPM0_CCBF_EN)                 /* DPM0 Core Clock Buffer Enable Register */
-#define pREG_DPM0_CCBF_STAT              ((volatile uint32_t *)REG_DPM0_CCBF_STAT)               /* DPM0 Core Clock Buffer Status Register */
-#define pREG_DPM0_CCBF_STAT_STKY         ((volatile uint32_t *)REG_DPM0_CCBF_STAT_STKY)          /* DPM0 Core Clock Buffer Status Sticky Register */
-#define pREG_DPM0_SCBF_DIS               ((volatile uint32_t *)REG_DPM0_SCBF_DIS)                /* DPM0 System Clock Buffer Disable Register */
-#define pREG_DPM0_WAKE_EN                ((volatile uint32_t *)REG_DPM0_WAKE_EN)                 /* DPM0 Wakeup Enable Register */
-#define pREG_DPM0_WAKE_POL               ((volatile uint32_t *)REG_DPM0_WAKE_POL)                /* DPM0 Wakeup Polarity Register */
-#define pREG_DPM0_WAKE_STAT              ((volatile uint32_t *)REG_DPM0_WAKE_STAT)               /* DPM0 Wakeup Status Register */
-#define pREG_DPM0_HIB_DIS                ((volatile uint32_t *)REG_DPM0_HIB_DIS)                 /* DPM0 Hibernate Disable Register */
-#define pREG_DPM0_PGCNTR                 ((volatile uint32_t *)REG_DPM0_PGCNTR)                  /* DPM0 Power Good Counter Register */
-#define pREG_DPM0_RESTORE0               ((volatile uint32_t *)REG_DPM0_RESTORE0)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE1               ((volatile uint32_t *)REG_DPM0_RESTORE1)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE2               ((volatile uint32_t *)REG_DPM0_RESTORE2)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE3               ((volatile uint32_t *)REG_DPM0_RESTORE3)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE4               ((volatile uint32_t *)REG_DPM0_RESTORE4)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE5               ((volatile uint32_t *)REG_DPM0_RESTORE5)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE6               ((volatile uint32_t *)REG_DPM0_RESTORE6)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE7               ((volatile uint32_t *)REG_DPM0_RESTORE7)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE8               ((volatile uint32_t *)REG_DPM0_RESTORE8)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE9               ((volatile uint32_t *)REG_DPM0_RESTORE9)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE10              ((volatile uint32_t *)REG_DPM0_RESTORE10)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE11              ((volatile uint32_t *)REG_DPM0_RESTORE11)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE12              ((volatile uint32_t *)REG_DPM0_RESTORE12)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE13              ((volatile uint32_t *)REG_DPM0_RESTORE13)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE14              ((volatile uint32_t *)REG_DPM0_RESTORE14)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE15              ((volatile uint32_t *)REG_DPM0_RESTORE15)               /* DPM0 Restore n Register */
-
-
-/* =========================================================================
-       EFS0
-   ========================================================================= */
-#define pREG_EFS0_CTL                    ((volatile uint32_t *)REG_EFS0_CTL)                     /* EFS0 Control Register */
-#define pREG_EFS0_DAT0                   ((volatile uint32_t *)REG_EFS0_DAT0)                    /* EFS0 Data Register 0 */
-#define pREG_EFS0_DAT1                   ((volatile uint32_t *)REG_EFS0_DAT1)                    /* EFS0 Data Register 1 */
-#define pREG_EFS0_DAT2                   ((volatile uint32_t *)REG_EFS0_DAT2)                    /* EFS0 Data Register 2 */
-#define pREG_EFS0_DAT3                   ((volatile uint32_t *)REG_EFS0_DAT3)                    /* EFS0 Data Register 3 */
-#define pREG_EFS0_DAT4                   ((volatile uint32_t *)REG_EFS0_DAT4)                    /* EFS0 Data Register 4 */
-#define pREG_EFS0_DAT5                   ((volatile uint32_t *)REG_EFS0_DAT5)                    /* EFS0 Data Register 5 */
-#define pREG_EFS0_DAT6                   ((volatile uint32_t *)REG_EFS0_DAT6)                    /* EFS0 Data Register 6 */
-#define pREG_EFS0_DAT7                   ((volatile uint32_t *)REG_EFS0_DAT7)                    /* EFS0 Data Register 7 */
-
-
-/* =========================================================================
-       USB0
-   ========================================================================= */
-#define pREG_USB0_FADDR                  ((volatile  uint8_t *)REG_USB0_FADDR)                   /* USB0 Function Address Register */
-#define pREG_USB0_POWER                  ((volatile  uint8_t *)REG_USB0_POWER)                   /* USB0 Power and Device Control Register */
-#define pREG_USB0_INTRTX                 ((volatile uint16_t *)REG_USB0_INTRTX)                  /* USB0 Transmit Interrupt Register */
-#define pREG_USB0_INTRRX                 ((volatile uint16_t *)REG_USB0_INTRRX)                  /* USB0 Receive Interrupt Register */
-#define pREG_USB0_INTRTXE                ((volatile uint16_t *)REG_USB0_INTRTXE)                 /* USB0 Transmit Interrupt Enable Register */
-#define pREG_USB0_INTRRXE                ((volatile uint16_t *)REG_USB0_INTRRXE)                 /* USB0 Receive Interrupt Enable Register */
-#define pREG_USB0_IRQ                    ((volatile  uint8_t *)REG_USB0_IRQ)                     /* USB0 Common Interrupts Register */
-#define pREG_USB0_IEN                    ((volatile  uint8_t *)REG_USB0_IEN)                     /* USB0 Common Interrupts Enable Register */
-#define pREG_USB0_FRAME                  ((volatile uint16_t *)REG_USB0_FRAME)                   /* USB0 Frame Number Register */
-#define pREG_USB0_INDEX                  ((volatile  uint8_t *)REG_USB0_INDEX)                   /* USB0 Index Register */
-#define pREG_USB0_TESTMODE               ((volatile  uint8_t *)REG_USB0_TESTMODE)                /* USB0 Testmode Register */
-#define pREG_USB0_EPI_TXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_TXMAXP0)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EPI_TXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_P0)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EPI_TXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_H0)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0I_CSR0_P            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_P)             /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CSR0_H            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_H)             /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_RXMAXP0)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EPI_RXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_H0)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_P0)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CNT0              ((volatile uint16_t *)REG_USB0_EP0I_CNT0)               /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EPI_RXCNT0             ((volatile uint16_t *)REG_USB0_EPI_RXCNT0)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EPI_TXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_TXTYPE0)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0I_TYPE0             ((volatile  uint8_t *)REG_USB0_EP0I_TYPE0)              /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EPI_TXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_TXINTERVAL0)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0I_NAKLIMIT0         ((volatile  uint8_t *)REG_USB0_EP0I_NAKLIMIT0)          /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EPI_RXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_RXTYPE0)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EPI_RXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_RXINTERVAL0)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0I_CFGDATA0          ((volatile  uint8_t *)REG_USB0_EP0I_CFGDATA0)           /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_FIFOB0                 ((volatile  uint8_t *)REG_USB0_FIFOB0)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB1                 ((volatile  uint8_t *)REG_USB0_FIFOB1)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB2                 ((volatile  uint8_t *)REG_USB0_FIFOB2)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB3                 ((volatile  uint8_t *)REG_USB0_FIFOB3)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB4                 ((volatile  uint8_t *)REG_USB0_FIFOB4)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB5                 ((volatile  uint8_t *)REG_USB0_FIFOB5)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB6                 ((volatile  uint8_t *)REG_USB0_FIFOB6)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB7                 ((volatile  uint8_t *)REG_USB0_FIFOB7)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB8                 ((volatile  uint8_t *)REG_USB0_FIFOB8)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB9                 ((volatile  uint8_t *)REG_USB0_FIFOB9)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB10                ((volatile  uint8_t *)REG_USB0_FIFOB10)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB11                ((volatile  uint8_t *)REG_USB0_FIFOB11)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOH0                 ((volatile uint16_t *)REG_USB0_FIFOH0)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH1                 ((volatile uint16_t *)REG_USB0_FIFOH1)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH2                 ((volatile uint16_t *)REG_USB0_FIFOH2)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH3                 ((volatile uint16_t *)REG_USB0_FIFOH3)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH4                 ((volatile uint16_t *)REG_USB0_FIFOH4)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH5                 ((volatile uint16_t *)REG_USB0_FIFOH5)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH6                 ((volatile uint16_t *)REG_USB0_FIFOH6)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH7                 ((volatile uint16_t *)REG_USB0_FIFOH7)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH8                 ((volatile uint16_t *)REG_USB0_FIFOH8)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH9                 ((volatile uint16_t *)REG_USB0_FIFOH9)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH10                ((volatile uint16_t *)REG_USB0_FIFOH10)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH11                ((volatile uint16_t *)REG_USB0_FIFOH11)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFO0                  ((volatile uint32_t *)REG_USB0_FIFO0)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO1                  ((volatile uint32_t *)REG_USB0_FIFO1)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO2                  ((volatile uint32_t *)REG_USB0_FIFO2)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO3                  ((volatile uint32_t *)REG_USB0_FIFO3)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO4                  ((volatile uint32_t *)REG_USB0_FIFO4)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO5                  ((volatile uint32_t *)REG_USB0_FIFO5)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO6                  ((volatile uint32_t *)REG_USB0_FIFO6)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO7                  ((volatile uint32_t *)REG_USB0_FIFO7)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO8                  ((volatile uint32_t *)REG_USB0_FIFO8)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO9                  ((volatile uint32_t *)REG_USB0_FIFO9)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO10                 ((volatile uint32_t *)REG_USB0_FIFO10)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO11                 ((volatile uint32_t *)REG_USB0_FIFO11)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_DEV_CTL                ((volatile  uint8_t *)REG_USB0_DEV_CTL)                 /* USB0 Device Control Register */
-#define pREG_USB0_TXFIFOSZ               ((volatile  uint8_t *)REG_USB0_TXFIFOSZ)                /* USB0 Transmit FIFO Size Register */
-#define pREG_USB0_RXFIFOSZ               ((volatile  uint8_t *)REG_USB0_RXFIFOSZ)                /* USB0 Receive FIFO Size Register */
-#define pREG_USB0_TXFIFOADDR             ((volatile uint16_t *)REG_USB0_TXFIFOADDR)              /* USB0 Transmit FIFO Address Register */
-#define pREG_USB0_RXFIFOADDR             ((volatile uint16_t *)REG_USB0_RXFIFOADDR)              /* USB0 Receive FIFO Address Register */
-#define pREG_USB0_EPINFO                 ((volatile  uint8_t *)REG_USB0_EPINFO)                  /* USB0 Endpoint Information Register */
-#define pREG_USB0_RAMINFO                ((volatile  uint8_t *)REG_USB0_RAMINFO)                 /* USB0 RAM Information Register */
-#define pREG_USB0_LINKINFO               ((volatile  uint8_t *)REG_USB0_LINKINFO)                /* USB0 Link Information Register */
-#define pREG_USB0_VPLEN                  ((volatile  uint8_t *)REG_USB0_VPLEN)                   /* USB0 VBUS Pulse Length Register */
-#define pREG_USB0_HS_EOF1                ((volatile  uint8_t *)REG_USB0_HS_EOF1)                 /* USB0 High-Speed EOF 1 Register */
-#define pREG_USB0_FS_EOF1                ((volatile  uint8_t *)REG_USB0_FS_EOF1)                 /* USB0 Full-Speed EOF 1 Register */
-#define pREG_USB0_LS_EOF1                ((volatile  uint8_t *)REG_USB0_LS_EOF1)                 /* USB0 Low-Speed EOF 1 Register */
-#define pREG_USB0_SOFT_RST               ((volatile  uint8_t *)REG_USB0_SOFT_RST)                /* USB0 Software Reset Register */
-#define pREG_USB0_MP0_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP1_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP2_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP3_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP4_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP5_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP6_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP7_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP8_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP9_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP10_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP11_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP0_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP1_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP2_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP3_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP4_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP5_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP6_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP7_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP8_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP9_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP10_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP11_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP0_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP1_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP2_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP3_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP4_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP5_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP6_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP7_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP8_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP9_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP10_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP11_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP0_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP1_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP2_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP3_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP4_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP5_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP6_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP7_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP8_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP9_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP10_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP11_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP0_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP1_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP2_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP3_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP4_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP5_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP6_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP7_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP8_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP9_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP10_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP11_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP0_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP1_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP2_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP3_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP4_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP5_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP6_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP7_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP8_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP9_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP10_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP11_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_EP0_TXMAXP             ((volatile uint16_t *)REG_USB0_EP0_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP1_TXMAXP             ((volatile uint16_t *)REG_USB0_EP1_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP2_TXMAXP             ((volatile uint16_t *)REG_USB0_EP2_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP3_TXMAXP             ((volatile uint16_t *)REG_USB0_EP3_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP4_TXMAXP             ((volatile uint16_t *)REG_USB0_EP4_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP5_TXMAXP             ((volatile uint16_t *)REG_USB0_EP5_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP6_TXMAXP             ((volatile uint16_t *)REG_USB0_EP6_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP7_TXMAXP             ((volatile uint16_t *)REG_USB0_EP7_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP8_TXMAXP             ((volatile uint16_t *)REG_USB0_EP8_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP9_TXMAXP             ((volatile uint16_t *)REG_USB0_EP9_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP10_TXMAXP            ((volatile uint16_t *)REG_USB0_EP10_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP11_TXMAXP            ((volatile uint16_t *)REG_USB0_EP11_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP0_CSR0_H             ((volatile uint16_t *)REG_USB0_EP0_CSR0_H)              /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_CSR0_P             ((volatile uint16_t *)REG_USB0_EP0_CSR0_P)              /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_RXMAXP             ((volatile uint16_t *)REG_USB0_EP0_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP1_RXMAXP             ((volatile uint16_t *)REG_USB0_EP1_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP2_RXMAXP             ((volatile uint16_t *)REG_USB0_EP2_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP3_RXMAXP             ((volatile uint16_t *)REG_USB0_EP3_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP4_RXMAXP             ((volatile uint16_t *)REG_USB0_EP4_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP5_RXMAXP             ((volatile uint16_t *)REG_USB0_EP5_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP6_RXMAXP             ((volatile uint16_t *)REG_USB0_EP6_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP7_RXMAXP             ((volatile uint16_t *)REG_USB0_EP7_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP8_RXMAXP             ((volatile uint16_t *)REG_USB0_EP8_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP9_RXMAXP             ((volatile uint16_t *)REG_USB0_EP9_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP10_RXMAXP            ((volatile uint16_t *)REG_USB0_EP10_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP11_RXMAXP            ((volatile uint16_t *)REG_USB0_EP11_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP0_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_CNT0               ((volatile uint16_t *)REG_USB0_EP0_CNT0)                /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EP0_RXCNT              ((volatile uint16_t *)REG_USB0_EP0_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP1_RXCNT              ((volatile uint16_t *)REG_USB0_EP1_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP2_RXCNT              ((volatile uint16_t *)REG_USB0_EP2_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP3_RXCNT              ((volatile uint16_t *)REG_USB0_EP3_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP4_RXCNT              ((volatile uint16_t *)REG_USB0_EP4_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP5_RXCNT              ((volatile uint16_t *)REG_USB0_EP5_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP6_RXCNT              ((volatile uint16_t *)REG_USB0_EP6_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP7_RXCNT              ((volatile uint16_t *)REG_USB0_EP7_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP8_RXCNT              ((volatile uint16_t *)REG_USB0_EP8_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP9_RXCNT              ((volatile uint16_t *)REG_USB0_EP9_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP10_RXCNT             ((volatile uint16_t *)REG_USB0_EP10_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP11_RXCNT             ((volatile uint16_t *)REG_USB0_EP11_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP0_TYPE0              ((volatile  uint8_t *)REG_USB0_EP0_TYPE0)               /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EP0_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP1_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP2_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP3_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP4_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP5_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP6_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP7_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP8_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP9_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP10_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP11_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0_NAKLIMIT0          ((volatile  uint8_t *)REG_USB0_EP0_NAKLIMIT0)           /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EP0_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP1_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP2_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP3_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP4_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP5_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP6_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP7_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP8_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP9_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP10_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP11_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP1_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP2_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP3_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP4_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP5_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP6_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP7_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP8_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP9_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP10_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP11_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP0_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP1_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP2_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP3_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP4_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP5_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP6_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP7_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP8_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP9_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP10_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP11_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0_CFGDATA0           ((volatile  uint8_t *)REG_USB0_EP0_CFGDATA0)            /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_DMA_IRQ                ((volatile  uint8_t *)REG_USB0_DMA_IRQ)                 /* USB0 DMA Interrupt Register */
-#define pREG_USB0_DMA0_CTL               ((volatile uint16_t *)REG_USB0_DMA0_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA1_CTL               ((volatile uint16_t *)REG_USB0_DMA1_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA2_CTL               ((volatile uint16_t *)REG_USB0_DMA2_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA3_CTL               ((volatile uint16_t *)REG_USB0_DMA3_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA4_CTL               ((volatile uint16_t *)REG_USB0_DMA4_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA5_CTL               ((volatile uint16_t *)REG_USB0_DMA5_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA6_CTL               ((volatile uint16_t *)REG_USB0_DMA6_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA7_CTL               ((volatile uint16_t *)REG_USB0_DMA7_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA0_ADDR              ((void * volatile *)REG_USB0_DMA0_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA1_ADDR              ((void * volatile *)REG_USB0_DMA1_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA2_ADDR              ((void * volatile *)REG_USB0_DMA2_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA3_ADDR              ((void * volatile *)REG_USB0_DMA3_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA4_ADDR              ((void * volatile *)REG_USB0_DMA4_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA5_ADDR              ((void * volatile *)REG_USB0_DMA5_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA6_ADDR              ((void * volatile *)REG_USB0_DMA6_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA7_ADDR              ((void * volatile *)REG_USB0_DMA7_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA0_CNT               ((volatile uint32_t *)REG_USB0_DMA0_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA1_CNT               ((volatile uint32_t *)REG_USB0_DMA1_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA2_CNT               ((volatile uint32_t *)REG_USB0_DMA2_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA3_CNT               ((volatile uint32_t *)REG_USB0_DMA3_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA4_CNT               ((volatile uint32_t *)REG_USB0_DMA4_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA5_CNT               ((volatile uint32_t *)REG_USB0_DMA5_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA6_CNT               ((volatile uint32_t *)REG_USB0_DMA6_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA7_CNT               ((volatile uint32_t *)REG_USB0_DMA7_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_RQPKTCNT0              ((volatile uint16_t *)REG_USB0_RQPKTCNT0)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT1              ((volatile uint16_t *)REG_USB0_RQPKTCNT1)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT2              ((volatile uint16_t *)REG_USB0_RQPKTCNT2)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT3              ((volatile uint16_t *)REG_USB0_RQPKTCNT3)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT4              ((volatile uint16_t *)REG_USB0_RQPKTCNT4)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT5              ((volatile uint16_t *)REG_USB0_RQPKTCNT5)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT6              ((volatile uint16_t *)REG_USB0_RQPKTCNT6)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT7              ((volatile uint16_t *)REG_USB0_RQPKTCNT7)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT8              ((volatile uint16_t *)REG_USB0_RQPKTCNT8)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT9              ((volatile uint16_t *)REG_USB0_RQPKTCNT9)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT10             ((volatile uint16_t *)REG_USB0_RQPKTCNT10)              /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_CT_UCH                 ((volatile uint16_t *)REG_USB0_CT_UCH)                  /* USB0 Chirp Timeout Register */
-#define pREG_USB0_CT_HHSRTN              ((volatile uint16_t *)REG_USB0_CT_HHSRTN)               /* USB0 Host High Speed Return to Normal Register */
-#define pREG_USB0_CT_HSBT                ((volatile uint16_t *)REG_USB0_CT_HSBT)                 /* USB0 High Speed Timeout Register */
-#define pREG_USB0_LPM_ATTR               ((volatile uint16_t *)REG_USB0_LPM_ATTR)                /* USB0 LPM Attribute Register */
-#define pREG_USB0_LPM_CTL                ((volatile  uint8_t *)REG_USB0_LPM_CTL)                 /* USB0 LPM Control Register */
-#define pREG_USB0_LPM_IEN                ((volatile  uint8_t *)REG_USB0_LPM_IEN)                 /* USB0 LPM Interrupt Enable Register */
-#define pREG_USB0_LPM_IRQ                ((volatile  uint8_t *)REG_USB0_LPM_IRQ)                 /* USB0 LPM Interrupt Status Register */
-#define pREG_USB0_LPM_FADDR              ((volatile  uint8_t *)REG_USB0_LPM_FADDR)               /* USB0 LPM Function Address Register */
-#define pREG_USB0_VBUS_CTL               ((volatile  uint8_t *)REG_USB0_VBUS_CTL)                /* USB0 VBUS Control Register */
-#define pREG_USB0_BAT_CHG                ((volatile  uint8_t *)REG_USB0_BAT_CHG)                 /* USB0 Battery Charging Control Register */
-#define pREG_USB0_PHY_CTL                ((volatile  uint8_t *)REG_USB0_PHY_CTL)                 /* USB0 PHY Control Register */
-#define pREG_USB0_PLL_OSC                ((volatile uint16_t *)REG_USB0_PLL_OSC)                 /* USB0 PLL and Oscillator Control Register */
-
-
-/* =========================================================================
-       L1DM0
-   ========================================================================= */
-#define pSRAM_BASE_ADDRESS               ((void * volatile *)SRAM_BASE_ADDRESS)                  /* SRAM Base Address */
-#define pDMEM_CONTROL                    ((volatile uint32_t *)DMEM_CONTROL)                     /* Data memory control */
-#define pDCPLB_STATUS                    ((volatile uint32_t *)DCPLB_STATUS)                     /* Data Cacheability Protection Lookaside Buffer Status */
-#define pDCPLB_FAULT_ADDR                ((void * volatile *)DCPLB_FAULT_ADDR)                   /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define pDCPLB_ADDR0                     ((void * volatile *)DCPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR1                     ((void * volatile *)DCPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR2                     ((void * volatile *)DCPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR3                     ((void * volatile *)DCPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR4                     ((void * volatile *)DCPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR5                     ((void * volatile *)DCPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR6                     ((void * volatile *)DCPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR7                     ((void * volatile *)DCPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR8                     ((void * volatile *)DCPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR9                     ((void * volatile *)DCPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR10                    ((void * volatile *)DCPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR11                    ((void * volatile *)DCPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR12                    ((void * volatile *)DCPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR13                    ((void * volatile *)DCPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR14                    ((void * volatile *)DCPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR15                    ((void * volatile *)DCPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_DATA0                     ((volatile uint32_t *)DCPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA1                     ((volatile uint32_t *)DCPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA2                     ((volatile uint32_t *)DCPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA3                     ((volatile uint32_t *)DCPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA4                     ((volatile uint32_t *)DCPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA5                     ((volatile uint32_t *)DCPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA6                     ((volatile uint32_t *)DCPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA7                     ((volatile uint32_t *)DCPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA8                     ((volatile uint32_t *)DCPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA9                     ((volatile uint32_t *)DCPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA10                    ((volatile uint32_t *)DCPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA11                    ((volatile uint32_t *)DCPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA12                    ((volatile uint32_t *)DCPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA13                    ((volatile uint32_t *)DCPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA14                    ((volatile uint32_t *)DCPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA15                    ((volatile uint32_t *)DCPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDTEST_COMMAND                   ((volatile uint32_t *)DTEST_COMMAND)                    /* Data Test Command Register */
-#define pDTEST_DATA0                     ((volatile uint32_t *)DTEST_DATA0)                      /* Data Test Data Register */
-#define pDTEST_DATA1                     ((volatile uint32_t *)DTEST_DATA1)                      /* Data Test Data Register */
-#define pL1DBNKA_PELOC                   ((volatile uint32_t *)L1DBNKA_PELOC)                    /* Data Bank A Parity Error Location */
-#define pL1DBNKB_PELOC                   ((volatile uint32_t *)L1DBNKB_PELOC)                    /* Data Bank B Parity Error Location */
-
-
-/* =========================================================================
-       L1IM0
-   ========================================================================= */
-#define pIMEM_CONTROL                    ((volatile uint32_t *)IMEM_CONTROL)                     /* Instruction memory control */
-#define pICPLB_STATUS                    ((volatile uint32_t *)ICPLB_STATUS)                     /* Cacheability Protection Lookaside Buffer Status */
-#define pICPLB_FAULT_ADDR                ((void * volatile *)ICPLB_FAULT_ADDR)                   /* Cacheability Protection Lookaside Buffer Fault Address */
-#define pICPLB_ADDR0                     ((void * volatile *)ICPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR1                     ((void * volatile *)ICPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR2                     ((void * volatile *)ICPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR3                     ((void * volatile *)ICPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR4                     ((void * volatile *)ICPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR5                     ((void * volatile *)ICPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR6                     ((void * volatile *)ICPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR7                     ((void * volatile *)ICPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR8                     ((void * volatile *)ICPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR9                     ((void * volatile *)ICPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR10                    ((void * volatile *)ICPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR11                    ((void * volatile *)ICPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR12                    ((void * volatile *)ICPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR13                    ((void * volatile *)ICPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR14                    ((void * volatile *)ICPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR15                    ((void * volatile *)ICPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_DATA0                     ((volatile uint32_t *)ICPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA1                     ((volatile uint32_t *)ICPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA2                     ((volatile uint32_t *)ICPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA3                     ((volatile uint32_t *)ICPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA4                     ((volatile uint32_t *)ICPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA5                     ((volatile uint32_t *)ICPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA6                     ((volatile uint32_t *)ICPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA7                     ((volatile uint32_t *)ICPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA8                     ((volatile uint32_t *)ICPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA9                     ((volatile uint32_t *)ICPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA10                    ((volatile uint32_t *)ICPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA11                    ((volatile uint32_t *)ICPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA12                    ((volatile uint32_t *)ICPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA13                    ((volatile uint32_t *)ICPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA14                    ((volatile uint32_t *)ICPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA15                    ((volatile uint32_t *)ICPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pITEST_COMMAND                   ((volatile uint32_t *)ITEST_COMMAND)                    /* Instruction Test Command Register */
-#define pITEST_DATA0                     ((volatile uint32_t *)ITEST_DATA0)                      /* Instruction Test Data Register */
-#define pITEST_DATA1                     ((volatile uint32_t *)ITEST_DATA1)                      /* Instruction Test Data Register */
-#define pL1IBNKA_PELOC                   ((volatile uint32_t *)L1IBNKA_PELOC)                    /* Instruction Bank A Parity Error Location */
-#define pL1IBNKB_PELOC                   ((volatile uint32_t *)L1IBNKB_PELOC)                    /* Instruction Bank B Parity Error Location */
-#define pL1IBNKC_PELOC                   ((volatile uint32_t *)L1IBNKC_PELOC)                    /* Instruction Bank C Parity Error Location */
-
-
-/* =========================================================================
-       ICU0
-   ========================================================================= */
-#define pEVT0                            ((void * volatile *)EVT0)                               /* Event Vector */
-#define pEVT1                            ((void * volatile *)EVT1)                               /* Event Vector */
-#define pEVT2                            ((void * volatile *)EVT2)                               /* Event Vector */
-#define pEVT3                            ((void * volatile *)EVT3)                               /* Event Vector */
-#define pEVT4                            ((void * volatile *)EVT4)                               /* Event Vector */
-#define pEVT5                            ((void * volatile *)EVT5)                               /* Event Vector */
-#define pEVT6                            ((void * volatile *)EVT6)                               /* Event Vector */
-#define pEVT7                            ((void * volatile *)EVT7)                               /* Event Vector */
-#define pEVT8                            ((void * volatile *)EVT8)                               /* Event Vector */
-#define pEVT9                            ((void * volatile *)EVT9)                               /* Event Vector */
-#define pEVT10                           ((void * volatile *)EVT10)                              /* Event Vector */
-#define pEVT11                           ((void * volatile *)EVT11)                              /* Event Vector */
-#define pEVT12                           ((void * volatile *)EVT12)                              /* Event Vector */
-#define pEVT13                           ((void * volatile *)EVT13)                              /* Event Vector */
-#define pEVT14                           ((void * volatile *)EVT14)                              /* Event Vector */
-#define pEVT15                           ((void * volatile *)EVT15)                              /* Event Vector */
-#define pIMASK                           ((volatile uint32_t *)IMASK)                            /* Interrupt Mask Register */
-#define pIPEND                           ((volatile uint32_t *)IPEND)                            /* Interrupts Pending Register */
-#define pILAT                            ((volatile uint32_t *)ILAT)                             /* Interrupt Latch Register */
-#define pIPRIO                           ((volatile uint32_t *)IPRIO)                            /* Interrupt Priority Register */
-#define pCEC_SID                         ((volatile uint32_t *)CEC_SID)                          /* Core System Interrupt ID */
-
-
-/* =========================================================================
-       TMR0
-   ========================================================================= */
-#define pTCNTL                           ((volatile uint32_t *)TCNTL)                            /* Timer Control Register */
-#define pTPERIOD                         ((volatile uint32_t *)TPERIOD)                          /* Timer Period Register */
-#define pTSCALE                          ((volatile uint32_t *)TSCALE)                           /* Timer Scale Register */
-#define pTCOUNT                          ((volatile uint32_t *)TCOUNT)                           /* Timer Count Register */
-
-
-/* =========================================================================
-       DBG0
-   ========================================================================= */
-#define pDSPID                           ((volatile uint32_t *)DSPID)                            /* DSP Identification Register */
-
-
-/* =========================================================================
-       TB0
-   ========================================================================= */
-#define pTBUFCTL                         ((volatile uint32_t *)TBUFCTL)                          /* Trace Buffer Control Register */
-#define pTBUFSTAT                        ((volatile uint32_t *)TBUFSTAT)                         /* Trace Buffer Status Register */
-#define pTBUF                            ((void * volatile *)TBUF)                               /* Trace Buffer */
-
-
-/* =========================================================================
-       WP0
-   ========================================================================= */
-#define pWPIACTL                         ((volatile uint32_t *)WPIACTL)                          /* Watchpoint Instruction Address Control Register 01 */
-#define pWPIA0                           ((void * volatile *)WPIA0)                              /* Watchpoint Instruction Address Register */
-#define pWPIA1                           ((void * volatile *)WPIA1)                              /* Watchpoint Instruction Address Register */
-#define pWPIA2                           ((void * volatile *)WPIA2)                              /* Watchpoint Instruction Address Register */
-#define pWPIA3                           ((void * volatile *)WPIA3)                              /* Watchpoint Instruction Address Register */
-#define pWPIA4                           ((void * volatile *)WPIA4)                              /* Watchpoint Instruction Address Register */
-#define pWPIA5                           ((void * volatile *)WPIA5)                              /* Watchpoint Instruction Address Register */
-#define pWPIACNT0                        ((volatile uint32_t *)WPIACNT0)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT1                        ((volatile uint32_t *)WPIACNT1)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT2                        ((volatile uint32_t *)WPIACNT2)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT3                        ((volatile uint32_t *)WPIACNT3)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT4                        ((volatile uint32_t *)WPIACNT4)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT5                        ((volatile uint32_t *)WPIACNT5)                         /* Watchpoint Instruction Address Count Register */
-#define pWPDACTL                         ((volatile uint32_t *)WPDACTL)                          /* Watchpoint Data Address Control Register */
-#define pWPDA0                           ((void * volatile *)WPDA0)                              /* Watchpoint Data Address Register */
-#define pWPDA1                           ((void * volatile *)WPDA1)                              /* Watchpoint Data Address Register */
-#define pWPDACNT0                        ((volatile uint32_t *)WPDACNT0)                         /* Watchpoint Data Address Count Value Register */
-#define pWPDACNT1                        ((volatile uint32_t *)WPDACNT1)                         /* Watchpoint Data Address Count Value Register */
-#define pWPSTAT                          ((volatile uint32_t *)WPSTAT)                           /* Watchpoint Status Register */
-
-
-/* =========================================================================
-       PF0
-   ========================================================================= */
-#define pPFCTL                           ((volatile uint32_t *)PFCTL)                            /* Performance Monitor Control Register */
-#define pPFCNTR0                         ((volatile uint32_t *)PFCNTR0)                          /* Performance Monitor Counter 0 */
-#define pPFCNTR1                         ((volatile uint32_t *)PFCNTR1)                          /* Performance Monitor Counter 1 */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif	/* end ifndef _CDEF_BF606_H */
diff --git a/libgloss/bfin/include/cdefBF607.h b/libgloss/bfin/include/cdefBF607.h
deleted file mode 100644
index 3ed6b8a0a..000000000
--- a/libgloss/bfin/include/cdefBF607.h
+++ /dev/null
@@ -1,4153 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* =========================================================================
-
-     Project      :   ADSP-BF607
-     File         :   cdefBF607.h
-     Description  :   C register and bitfield definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ========================================================================= */
-#ifndef _CDEF_BF607_H
-#define _CDEF_BF607_H
-
-#include <stdint.h>
-#include <defBF607.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_7:"ADI header will re-use identifiers")
-#pragma diag(suppress:misra_rule_6_3:"ADI header allows use of basic types")
-#endif /* _MISRA_RULES */
-
-
-
-
-/* =========================================================================
-       CNT0
-   ========================================================================= */
-#define pREG_CNT0_CFG                    ((volatile uint16_t *)REG_CNT0_CFG)                     /* CNT0 Configuration Register */
-#define pREG_CNT0_IMSK                   ((volatile uint16_t *)REG_CNT0_IMSK)                    /* CNT0 Interrupt Mask Register */
-#define pREG_CNT0_STAT                   ((volatile uint16_t *)REG_CNT0_STAT)                    /* CNT0 Status Register */
-#define pREG_CNT0_CMD                    ((volatile uint16_t *)REG_CNT0_CMD)                     /* CNT0 Command Register */
-#define pREG_CNT0_DEBNCE                 ((volatile uint16_t *)REG_CNT0_DEBNCE)                  /* CNT0 Debounce Register */
-#define pREG_CNT0_CNTR                   ((volatile uint32_t *)REG_CNT0_CNTR)                    /* CNT0 Counter Register */
-#define pREG_CNT0_MAX                    ((volatile uint32_t *)REG_CNT0_MAX)                     /* CNT0 Maximum Count Register */
-#define pREG_CNT0_MIN                    ((volatile uint32_t *)REG_CNT0_MIN)                     /* CNT0 Minimum Count Register */
-
-
-/* =========================================================================
-       RSI0
-   ========================================================================= */
-#define pREG_RSI0_CTL                    ((volatile uint16_t *)REG_RSI0_CTL)                     /* RSI0 Control Register */
-#define pREG_RSI0_ARG                    ((volatile uint32_t *)REG_RSI0_ARG)                     /* RSI0 Argument Register */
-#define pREG_RSI0_CMD                    ((volatile uint16_t *)REG_RSI0_CMD)                     /* RSI0 Command Register */
-#define pREG_RSI0_RESP_CMD               ((volatile uint16_t *)REG_RSI0_RESP_CMD)                /* RSI0 Response Command Register */
-#define pREG_RSI0_RESP0                  ((volatile uint32_t *)REG_RSI0_RESP0)                   /* RSI0 Response 0 Register */
-#define pREG_RSI0_RESP1                  ((volatile uint32_t *)REG_RSI0_RESP1)                   /* RSI0 Response 1 Register */
-#define pREG_RSI0_RESP2                  ((volatile uint32_t *)REG_RSI0_RESP2)                   /* RSI0 Response 2 Register */
-#define pREG_RSI0_RESP3                  ((volatile uint32_t *)REG_RSI0_RESP3)                   /* RSI0 Response 3 Register */
-#define pREG_RSI0_DATA_TMR               ((volatile uint32_t *)REG_RSI0_DATA_TMR)                /* RSI0 Data Timer Register */
-#define pREG_RSI0_DATA_LEN               ((volatile uint16_t *)REG_RSI0_DATA_LEN)                /* RSI0 Data Length Register */
-#define pREG_RSI0_DATA_CTL               ((volatile uint16_t *)REG_RSI0_DATA_CTL)                /* RSI0 Data Control Register */
-#define pREG_RSI0_DATA_CNT               ((volatile uint16_t *)REG_RSI0_DATA_CNT)                /* RSI0 Data Count Register */
-#define pREG_RSI0_XFRSTAT                ((volatile uint32_t *)REG_RSI0_XFRSTAT)                 /* RSI0 Status Register */
-#define pREG_RSI0_XFRSTAT_CLR            ((volatile uint16_t *)REG_RSI0_XFRSTAT_CLR)             /* RSI0 Status Clear Register */
-#define pREG_RSI0_XFR_IMSK0              ((volatile uint32_t *)REG_RSI0_XFR_IMSK0)               /* RSI0 Interrupt 0 Mask Register */
-#define pREG_RSI0_XFR_IMSK1              ((volatile uint32_t *)REG_RSI0_XFR_IMSK1)               /* RSI0 Interrupt 1 Mask Register */
-#define pREG_RSI0_FIFO_CNT               ((volatile uint16_t *)REG_RSI0_FIFO_CNT)                /* RSI0 FIFO Counter Register */
-#define pREG_RSI0_CEATA                  ((volatile uint32_t *)REG_RSI0_CEATA)                   /* RSI0 This register contains bit to dis CCS gen */
-#define pREG_RSI0_BOOT_TCNTR             ((volatile uint16_t *)REG_RSI0_BOOT_TCNTR)              /* RSI0 Boot Timing Counter Register */
-#define pREG_RSI0_BACK_TOUT              ((volatile uint32_t *)REG_RSI0_BACK_TOUT)               /* RSI0 Boot Acknowledge Timeout Register */
-#define pREG_RSI0_SLP_WKUP_TOUT          ((volatile uint32_t *)REG_RSI0_SLP_WKUP_TOUT)           /* RSI0 Sleep Wakeup Timeout Register */
-#define pREG_RSI0_BLKSZ                  ((volatile uint16_t *)REG_RSI0_BLKSZ)                   /* RSI0 Block Size Register */
-#define pREG_RSI0_FIFO                   ((volatile uint32_t *)REG_RSI0_FIFO)                    /* RSI0 Data FIFO Register */
-#define pREG_RSI0_STAT0                  ((volatile uint32_t *)REG_RSI0_STAT0)                   /* RSI0 Exception Status Register */
-#define pREG_RSI0_IMSK0                  ((volatile uint32_t *)REG_RSI0_IMSK0)                   /* RSI0 Exception Mask Register */
-#define pREG_RSI0_CFG                    ((volatile uint16_t *)REG_RSI0_CFG)                     /* RSI0 Configuration Register */
-#define pREG_RSI0_RD_WAIT                ((volatile uint16_t *)REG_RSI0_RD_WAIT)                 /* RSI0 Read Wait Enable Register */
-#define pREG_RSI0_PID0                   ((volatile uint32_t *)REG_RSI0_PID0)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID1                   ((volatile uint32_t *)REG_RSI0_PID1)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID2                   ((volatile uint32_t *)REG_RSI0_PID2)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID3                   ((volatile uint32_t *)REG_RSI0_PID3)                    /* RSI0 Peripheral Identification Register */
-
-
-/* =========================================================================
-       CAN0
-   ========================================================================= */
-#define pREG_CAN0_MC1                    ((volatile uint16_t *)REG_CAN0_MC1)                     /* CAN0 Mailbox Configuration 1 Register */
-#define pREG_CAN0_MD1                    ((volatile uint16_t *)REG_CAN0_MD1)                     /* CAN0 Mailbox Direction 1 Register */
-#define pREG_CAN0_TRS1                   ((volatile uint16_t *)REG_CAN0_TRS1)                    /* CAN0 Transmission Request Set 1 Register */
-#define pREG_CAN0_TRR1                   ((volatile uint16_t *)REG_CAN0_TRR1)                    /* CAN0 Transmission Request Reset 1 Register */
-#define pREG_CAN0_TA1                    ((volatile uint16_t *)REG_CAN0_TA1)                     /* CAN0 Transmission Acknowledge 1 Register */
-#define pREG_CAN0_AA1                    ((volatile uint16_t *)REG_CAN0_AA1)                     /* CAN0 Abort Acknowledge 1 Register */
-#define pREG_CAN0_RMP1                   ((volatile uint16_t *)REG_CAN0_RMP1)                    /* CAN0 Receive Message Pending 1 Register */
-#define pREG_CAN0_RML1                   ((volatile uint16_t *)REG_CAN0_RML1)                    /* CAN0 Receive Message Lost 1 Register */
-#define pREG_CAN0_MBTIF1                 ((volatile uint16_t *)REG_CAN0_MBTIF1)                  /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define pREG_CAN0_MBRIF1                 ((volatile uint16_t *)REG_CAN0_MBRIF1)                  /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define pREG_CAN0_MBIM1                  ((volatile uint16_t *)REG_CAN0_MBIM1)                   /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define pREG_CAN0_RFH1                   ((volatile uint16_t *)REG_CAN0_RFH1)                    /* CAN0 Remote Frame Handling 1 Register */
-#define pREG_CAN0_OPSS1                  ((volatile uint16_t *)REG_CAN0_OPSS1)                   /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define pREG_CAN0_MC2                    ((volatile uint16_t *)REG_CAN0_MC2)                     /* CAN0 Mailbox Configuration 2 Register */
-#define pREG_CAN0_MD2                    ((volatile uint16_t *)REG_CAN0_MD2)                     /* CAN0 Mailbox Direction 2 Register */
-#define pREG_CAN0_TRS2                   ((volatile uint16_t *)REG_CAN0_TRS2)                    /* CAN0 Transmission Request Set 2 Register */
-#define pREG_CAN0_TRR2                   ((volatile uint16_t *)REG_CAN0_TRR2)                    /* CAN0 Transmission Request Reset 2 Register */
-#define pREG_CAN0_TA2                    ((volatile uint16_t *)REG_CAN0_TA2)                     /* CAN0 Transmission Acknowledge 2 Register */
-#define pREG_CAN0_AA2                    ((volatile uint16_t *)REG_CAN0_AA2)                     /* CAN0 Abort Acknowledge 2 Register */
-#define pREG_CAN0_RMP2                   ((volatile uint16_t *)REG_CAN0_RMP2)                    /* CAN0 Receive Message Pending 2 Register */
-#define pREG_CAN0_RML2                   ((volatile uint16_t *)REG_CAN0_RML2)                    /* CAN0 Receive Message Lost 2 Register */
-#define pREG_CAN0_MBTIF2                 ((volatile uint16_t *)REG_CAN0_MBTIF2)                  /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define pREG_CAN0_MBRIF2                 ((volatile uint16_t *)REG_CAN0_MBRIF2)                  /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define pREG_CAN0_MBIM2                  ((volatile uint16_t *)REG_CAN0_MBIM2)                   /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define pREG_CAN0_RFH2                   ((volatile uint16_t *)REG_CAN0_RFH2)                    /* CAN0 Remote Frame Handling 2 Register */
-#define pREG_CAN0_OPSS2                  ((volatile uint16_t *)REG_CAN0_OPSS2)                   /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define pREG_CAN0_CLK                    ((volatile uint16_t *)REG_CAN0_CLK)                     /* CAN0 Clock Register */
-#define pREG_CAN0_TIMING                 ((volatile uint16_t *)REG_CAN0_TIMING)                  /* CAN0 Timing Register */
-#define pREG_CAN0_DBG                    ((volatile uint16_t *)REG_CAN0_DBG)                     /* CAN0 Debug Register */
-#define pREG_CAN0_STAT                   ((volatile uint16_t *)REG_CAN0_STAT)                    /* CAN0 Status Register */
-#define pREG_CAN0_CEC                    ((volatile uint16_t *)REG_CAN0_CEC)                     /* CAN0 Error Counter Register */
-#define pREG_CAN0_GIS                    ((volatile uint16_t *)REG_CAN0_GIS)                     /* CAN0 Global CAN Interrupt Status Register */
-#define pREG_CAN0_GIM                    ((volatile uint16_t *)REG_CAN0_GIM)                     /* CAN0 Global CAN Interrupt Mask Register */
-#define pREG_CAN0_GIF                    ((volatile uint16_t *)REG_CAN0_GIF)                     /* CAN0 Global CAN Interrupt Flag Register */
-#define pREG_CAN0_CTL                    ((volatile uint16_t *)REG_CAN0_CTL)                     /* CAN0 CAN Master Control Register */
-#define pREG_CAN0_INT                    ((volatile uint16_t *)REG_CAN0_INT)                     /* CAN0 Interrupt Pending Register */
-#define pREG_CAN0_MBTD                   ((volatile uint16_t *)REG_CAN0_MBTD)                    /* CAN0 Temporary Mailbox Disable Register */
-#define pREG_CAN0_EWR                    ((volatile uint16_t *)REG_CAN0_EWR)                     /* CAN0 Error Counter Warning Level Register */
-#define pREG_CAN0_ESR                    ((volatile uint16_t *)REG_CAN0_ESR)                     /* CAN0 Error Status Register */
-#define pREG_CAN0_UCCNT                  ((volatile uint16_t *)REG_CAN0_UCCNT)                   /* CAN0 Universal Counter Register */
-#define pREG_CAN0_UCRC                   ((volatile uint16_t *)REG_CAN0_UCRC)                    /* CAN0 Universal Counter Reload/Capture Register */
-#define pREG_CAN0_UCCNF                  ((volatile uint16_t *)REG_CAN0_UCCNF)                   /* CAN0 Universal Counter Configuration Mode Register */
-#define pREG_CAN0_AM00L                  ((volatile uint16_t *)REG_CAN0_AM00L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM01L                  ((volatile uint16_t *)REG_CAN0_AM01L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM02L                  ((volatile uint16_t *)REG_CAN0_AM02L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM03L                  ((volatile uint16_t *)REG_CAN0_AM03L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM04L                  ((volatile uint16_t *)REG_CAN0_AM04L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM05L                  ((volatile uint16_t *)REG_CAN0_AM05L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM06L                  ((volatile uint16_t *)REG_CAN0_AM06L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM07L                  ((volatile uint16_t *)REG_CAN0_AM07L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM08L                  ((volatile uint16_t *)REG_CAN0_AM08L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM09L                  ((volatile uint16_t *)REG_CAN0_AM09L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM10L                  ((volatile uint16_t *)REG_CAN0_AM10L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM11L                  ((volatile uint16_t *)REG_CAN0_AM11L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM12L                  ((volatile uint16_t *)REG_CAN0_AM12L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM13L                  ((volatile uint16_t *)REG_CAN0_AM13L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM14L                  ((volatile uint16_t *)REG_CAN0_AM14L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM15L                  ((volatile uint16_t *)REG_CAN0_AM15L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM16L                  ((volatile uint16_t *)REG_CAN0_AM16L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM17L                  ((volatile uint16_t *)REG_CAN0_AM17L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM18L                  ((volatile uint16_t *)REG_CAN0_AM18L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM19L                  ((volatile uint16_t *)REG_CAN0_AM19L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM20L                  ((volatile uint16_t *)REG_CAN0_AM20L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM21L                  ((volatile uint16_t *)REG_CAN0_AM21L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM22L                  ((volatile uint16_t *)REG_CAN0_AM22L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM23L                  ((volatile uint16_t *)REG_CAN0_AM23L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM24L                  ((volatile uint16_t *)REG_CAN0_AM24L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM25L                  ((volatile uint16_t *)REG_CAN0_AM25L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM26L                  ((volatile uint16_t *)REG_CAN0_AM26L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM27L                  ((volatile uint16_t *)REG_CAN0_AM27L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM28L                  ((volatile uint16_t *)REG_CAN0_AM28L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM29L                  ((volatile uint16_t *)REG_CAN0_AM29L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM30L                  ((volatile uint16_t *)REG_CAN0_AM30L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM31L                  ((volatile uint16_t *)REG_CAN0_AM31L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM00H                  ((volatile uint16_t *)REG_CAN0_AM00H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM01H                  ((volatile uint16_t *)REG_CAN0_AM01H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM02H                  ((volatile uint16_t *)REG_CAN0_AM02H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM03H                  ((volatile uint16_t *)REG_CAN0_AM03H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM04H                  ((volatile uint16_t *)REG_CAN0_AM04H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM05H                  ((volatile uint16_t *)REG_CAN0_AM05H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM06H                  ((volatile uint16_t *)REG_CAN0_AM06H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM07H                  ((volatile uint16_t *)REG_CAN0_AM07H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM08H                  ((volatile uint16_t *)REG_CAN0_AM08H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM09H                  ((volatile uint16_t *)REG_CAN0_AM09H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM10H                  ((volatile uint16_t *)REG_CAN0_AM10H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM11H                  ((volatile uint16_t *)REG_CAN0_AM11H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM12H                  ((volatile uint16_t *)REG_CAN0_AM12H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM13H                  ((volatile uint16_t *)REG_CAN0_AM13H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM14H                  ((volatile uint16_t *)REG_CAN0_AM14H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM15H                  ((volatile uint16_t *)REG_CAN0_AM15H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM16H                  ((volatile uint16_t *)REG_CAN0_AM16H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM17H                  ((volatile uint16_t *)REG_CAN0_AM17H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM18H                  ((volatile uint16_t *)REG_CAN0_AM18H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM19H                  ((volatile uint16_t *)REG_CAN0_AM19H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM20H                  ((volatile uint16_t *)REG_CAN0_AM20H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM21H                  ((volatile uint16_t *)REG_CAN0_AM21H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM22H                  ((volatile uint16_t *)REG_CAN0_AM22H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM23H                  ((volatile uint16_t *)REG_CAN0_AM23H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM24H                  ((volatile uint16_t *)REG_CAN0_AM24H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM25H                  ((volatile uint16_t *)REG_CAN0_AM25H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM26H                  ((volatile uint16_t *)REG_CAN0_AM26H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM27H                  ((volatile uint16_t *)REG_CAN0_AM27H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM28H                  ((volatile uint16_t *)REG_CAN0_AM28H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM29H                  ((volatile uint16_t *)REG_CAN0_AM29H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM30H                  ((volatile uint16_t *)REG_CAN0_AM30H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM31H                  ((volatile uint16_t *)REG_CAN0_AM31H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_MB00_DATA0             ((volatile uint16_t *)REG_CAN0_MB00_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB01_DATA0             ((volatile uint16_t *)REG_CAN0_MB01_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB02_DATA0             ((volatile uint16_t *)REG_CAN0_MB02_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB03_DATA0             ((volatile uint16_t *)REG_CAN0_MB03_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB04_DATA0             ((volatile uint16_t *)REG_CAN0_MB04_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB05_DATA0             ((volatile uint16_t *)REG_CAN0_MB05_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB06_DATA0             ((volatile uint16_t *)REG_CAN0_MB06_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB07_DATA0             ((volatile uint16_t *)REG_CAN0_MB07_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB08_DATA0             ((volatile uint16_t *)REG_CAN0_MB08_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB09_DATA0             ((volatile uint16_t *)REG_CAN0_MB09_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB10_DATA0             ((volatile uint16_t *)REG_CAN0_MB10_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB11_DATA0             ((volatile uint16_t *)REG_CAN0_MB11_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB12_DATA0             ((volatile uint16_t *)REG_CAN0_MB12_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB13_DATA0             ((volatile uint16_t *)REG_CAN0_MB13_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB14_DATA0             ((volatile uint16_t *)REG_CAN0_MB14_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB15_DATA0             ((volatile uint16_t *)REG_CAN0_MB15_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB16_DATA0             ((volatile uint16_t *)REG_CAN0_MB16_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB17_DATA0             ((volatile uint16_t *)REG_CAN0_MB17_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB18_DATA0             ((volatile uint16_t *)REG_CAN0_MB18_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB19_DATA0             ((volatile uint16_t *)REG_CAN0_MB19_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB20_DATA0             ((volatile uint16_t *)REG_CAN0_MB20_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB21_DATA0             ((volatile uint16_t *)REG_CAN0_MB21_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB22_DATA0             ((volatile uint16_t *)REG_CAN0_MB22_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB23_DATA0             ((volatile uint16_t *)REG_CAN0_MB23_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB24_DATA0             ((volatile uint16_t *)REG_CAN0_MB24_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB25_DATA0             ((volatile uint16_t *)REG_CAN0_MB25_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB26_DATA0             ((volatile uint16_t *)REG_CAN0_MB26_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB27_DATA0             ((volatile uint16_t *)REG_CAN0_MB27_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB28_DATA0             ((volatile uint16_t *)REG_CAN0_MB28_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB29_DATA0             ((volatile uint16_t *)REG_CAN0_MB29_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB30_DATA0             ((volatile uint16_t *)REG_CAN0_MB30_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB31_DATA0             ((volatile uint16_t *)REG_CAN0_MB31_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB00_DATA1             ((volatile uint16_t *)REG_CAN0_MB00_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB01_DATA1             ((volatile uint16_t *)REG_CAN0_MB01_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB02_DATA1             ((volatile uint16_t *)REG_CAN0_MB02_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB03_DATA1             ((volatile uint16_t *)REG_CAN0_MB03_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB04_DATA1             ((volatile uint16_t *)REG_CAN0_MB04_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB05_DATA1             ((volatile uint16_t *)REG_CAN0_MB05_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB06_DATA1             ((volatile uint16_t *)REG_CAN0_MB06_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB07_DATA1             ((volatile uint16_t *)REG_CAN0_MB07_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB08_DATA1             ((volatile uint16_t *)REG_CAN0_MB08_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB09_DATA1             ((volatile uint16_t *)REG_CAN0_MB09_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB10_DATA1             ((volatile uint16_t *)REG_CAN0_MB10_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB11_DATA1             ((volatile uint16_t *)REG_CAN0_MB11_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB12_DATA1             ((volatile uint16_t *)REG_CAN0_MB12_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB13_DATA1             ((volatile uint16_t *)REG_CAN0_MB13_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB14_DATA1             ((volatile uint16_t *)REG_CAN0_MB14_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB15_DATA1             ((volatile uint16_t *)REG_CAN0_MB15_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB16_DATA1             ((volatile uint16_t *)REG_CAN0_MB16_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB17_DATA1             ((volatile uint16_t *)REG_CAN0_MB17_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB18_DATA1             ((volatile uint16_t *)REG_CAN0_MB18_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB19_DATA1             ((volatile uint16_t *)REG_CAN0_MB19_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB20_DATA1             ((volatile uint16_t *)REG_CAN0_MB20_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB21_DATA1             ((volatile uint16_t *)REG_CAN0_MB21_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB22_DATA1             ((volatile uint16_t *)REG_CAN0_MB22_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB23_DATA1             ((volatile uint16_t *)REG_CAN0_MB23_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB24_DATA1             ((volatile uint16_t *)REG_CAN0_MB24_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB25_DATA1             ((volatile uint16_t *)REG_CAN0_MB25_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB26_DATA1             ((volatile uint16_t *)REG_CAN0_MB26_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB27_DATA1             ((volatile uint16_t *)REG_CAN0_MB27_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB28_DATA1             ((volatile uint16_t *)REG_CAN0_MB28_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB29_DATA1             ((volatile uint16_t *)REG_CAN0_MB29_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB30_DATA1             ((volatile uint16_t *)REG_CAN0_MB30_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB31_DATA1             ((volatile uint16_t *)REG_CAN0_MB31_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB00_DATA2             ((volatile uint16_t *)REG_CAN0_MB00_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB01_DATA2             ((volatile uint16_t *)REG_CAN0_MB01_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB02_DATA2             ((volatile uint16_t *)REG_CAN0_MB02_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB03_DATA2             ((volatile uint16_t *)REG_CAN0_MB03_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB04_DATA2             ((volatile uint16_t *)REG_CAN0_MB04_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB05_DATA2             ((volatile uint16_t *)REG_CAN0_MB05_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB06_DATA2             ((volatile uint16_t *)REG_CAN0_MB06_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB07_DATA2             ((volatile uint16_t *)REG_CAN0_MB07_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB08_DATA2             ((volatile uint16_t *)REG_CAN0_MB08_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB09_DATA2             ((volatile uint16_t *)REG_CAN0_MB09_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB10_DATA2             ((volatile uint16_t *)REG_CAN0_MB10_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB11_DATA2             ((volatile uint16_t *)REG_CAN0_MB11_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB12_DATA2             ((volatile uint16_t *)REG_CAN0_MB12_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB13_DATA2             ((volatile uint16_t *)REG_CAN0_MB13_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB14_DATA2             ((volatile uint16_t *)REG_CAN0_MB14_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB15_DATA2             ((volatile uint16_t *)REG_CAN0_MB15_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB16_DATA2             ((volatile uint16_t *)REG_CAN0_MB16_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB17_DATA2             ((volatile uint16_t *)REG_CAN0_MB17_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB18_DATA2             ((volatile uint16_t *)REG_CAN0_MB18_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB19_DATA2             ((volatile uint16_t *)REG_CAN0_MB19_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB20_DATA2             ((volatile uint16_t *)REG_CAN0_MB20_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB21_DATA2             ((volatile uint16_t *)REG_CAN0_MB21_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB22_DATA2             ((volatile uint16_t *)REG_CAN0_MB22_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB23_DATA2             ((volatile uint16_t *)REG_CAN0_MB23_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB24_DATA2             ((volatile uint16_t *)REG_CAN0_MB24_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB25_DATA2             ((volatile uint16_t *)REG_CAN0_MB25_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB26_DATA2             ((volatile uint16_t *)REG_CAN0_MB26_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB27_DATA2             ((volatile uint16_t *)REG_CAN0_MB27_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB28_DATA2             ((volatile uint16_t *)REG_CAN0_MB28_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB29_DATA2             ((volatile uint16_t *)REG_CAN0_MB29_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB30_DATA2             ((volatile uint16_t *)REG_CAN0_MB30_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB31_DATA2             ((volatile uint16_t *)REG_CAN0_MB31_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB00_DATA3             ((volatile uint16_t *)REG_CAN0_MB00_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB01_DATA3             ((volatile uint16_t *)REG_CAN0_MB01_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB02_DATA3             ((volatile uint16_t *)REG_CAN0_MB02_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB03_DATA3             ((volatile uint16_t *)REG_CAN0_MB03_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB04_DATA3             ((volatile uint16_t *)REG_CAN0_MB04_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB05_DATA3             ((volatile uint16_t *)REG_CAN0_MB05_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB06_DATA3             ((volatile uint16_t *)REG_CAN0_MB06_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB07_DATA3             ((volatile uint16_t *)REG_CAN0_MB07_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB08_DATA3             ((volatile uint16_t *)REG_CAN0_MB08_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB09_DATA3             ((volatile uint16_t *)REG_CAN0_MB09_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB10_DATA3             ((volatile uint16_t *)REG_CAN0_MB10_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB11_DATA3             ((volatile uint16_t *)REG_CAN0_MB11_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB12_DATA3             ((volatile uint16_t *)REG_CAN0_MB12_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB13_DATA3             ((volatile uint16_t *)REG_CAN0_MB13_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB14_DATA3             ((volatile uint16_t *)REG_CAN0_MB14_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB15_DATA3             ((volatile uint16_t *)REG_CAN0_MB15_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB16_DATA3             ((volatile uint16_t *)REG_CAN0_MB16_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB17_DATA3             ((volatile uint16_t *)REG_CAN0_MB17_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB18_DATA3             ((volatile uint16_t *)REG_CAN0_MB18_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB19_DATA3             ((volatile uint16_t *)REG_CAN0_MB19_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB20_DATA3             ((volatile uint16_t *)REG_CAN0_MB20_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB21_DATA3             ((volatile uint16_t *)REG_CAN0_MB21_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB22_DATA3             ((volatile uint16_t *)REG_CAN0_MB22_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB23_DATA3             ((volatile uint16_t *)REG_CAN0_MB23_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB24_DATA3             ((volatile uint16_t *)REG_CAN0_MB24_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB25_DATA3             ((volatile uint16_t *)REG_CAN0_MB25_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB26_DATA3             ((volatile uint16_t *)REG_CAN0_MB26_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB27_DATA3             ((volatile uint16_t *)REG_CAN0_MB27_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB28_DATA3             ((volatile uint16_t *)REG_CAN0_MB28_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB29_DATA3             ((volatile uint16_t *)REG_CAN0_MB29_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB30_DATA3             ((volatile uint16_t *)REG_CAN0_MB30_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB31_DATA3             ((volatile uint16_t *)REG_CAN0_MB31_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB00_LENGTH            ((volatile uint16_t *)REG_CAN0_MB00_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB01_LENGTH            ((volatile uint16_t *)REG_CAN0_MB01_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB02_LENGTH            ((volatile uint16_t *)REG_CAN0_MB02_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB03_LENGTH            ((volatile uint16_t *)REG_CAN0_MB03_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB04_LENGTH            ((volatile uint16_t *)REG_CAN0_MB04_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB05_LENGTH            ((volatile uint16_t *)REG_CAN0_MB05_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB06_LENGTH            ((volatile uint16_t *)REG_CAN0_MB06_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB07_LENGTH            ((volatile uint16_t *)REG_CAN0_MB07_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB08_LENGTH            ((volatile uint16_t *)REG_CAN0_MB08_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB09_LENGTH            ((volatile uint16_t *)REG_CAN0_MB09_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB10_LENGTH            ((volatile uint16_t *)REG_CAN0_MB10_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB11_LENGTH            ((volatile uint16_t *)REG_CAN0_MB11_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB12_LENGTH            ((volatile uint16_t *)REG_CAN0_MB12_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB13_LENGTH            ((volatile uint16_t *)REG_CAN0_MB13_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB14_LENGTH            ((volatile uint16_t *)REG_CAN0_MB14_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB15_LENGTH            ((volatile uint16_t *)REG_CAN0_MB15_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB16_LENGTH            ((volatile uint16_t *)REG_CAN0_MB16_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB17_LENGTH            ((volatile uint16_t *)REG_CAN0_MB17_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB18_LENGTH            ((volatile uint16_t *)REG_CAN0_MB18_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB19_LENGTH            ((volatile uint16_t *)REG_CAN0_MB19_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB20_LENGTH            ((volatile uint16_t *)REG_CAN0_MB20_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB21_LENGTH            ((volatile uint16_t *)REG_CAN0_MB21_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB22_LENGTH            ((volatile uint16_t *)REG_CAN0_MB22_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB23_LENGTH            ((volatile uint16_t *)REG_CAN0_MB23_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB24_LENGTH            ((volatile uint16_t *)REG_CAN0_MB24_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB25_LENGTH            ((volatile uint16_t *)REG_CAN0_MB25_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB26_LENGTH            ((volatile uint16_t *)REG_CAN0_MB26_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB27_LENGTH            ((volatile uint16_t *)REG_CAN0_MB27_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB28_LENGTH            ((volatile uint16_t *)REG_CAN0_MB28_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB29_LENGTH            ((volatile uint16_t *)REG_CAN0_MB29_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB30_LENGTH            ((volatile uint16_t *)REG_CAN0_MB30_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB31_LENGTH            ((volatile uint16_t *)REG_CAN0_MB31_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB00_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB00_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB01_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB01_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB02_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB02_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB03_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB03_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB04_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB04_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB05_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB05_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB06_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB06_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB07_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB07_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB08_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB08_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB09_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB09_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB10_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB10_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB11_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB11_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB12_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB12_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB13_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB13_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB14_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB14_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB15_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB15_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB16_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB16_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB17_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB17_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB18_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB18_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB19_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB19_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB20_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB20_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB21_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB21_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB22_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB22_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB23_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB23_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB24_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB24_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB25_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB25_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB26_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB26_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB27_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB27_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB28_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB28_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB29_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB29_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB30_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB30_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB31_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB31_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB00_ID0               ((volatile uint16_t *)REG_CAN0_MB00_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB01_ID0               ((volatile uint16_t *)REG_CAN0_MB01_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB02_ID0               ((volatile uint16_t *)REG_CAN0_MB02_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB03_ID0               ((volatile uint16_t *)REG_CAN0_MB03_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB04_ID0               ((volatile uint16_t *)REG_CAN0_MB04_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB05_ID0               ((volatile uint16_t *)REG_CAN0_MB05_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB06_ID0               ((volatile uint16_t *)REG_CAN0_MB06_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB07_ID0               ((volatile uint16_t *)REG_CAN0_MB07_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB08_ID0               ((volatile uint16_t *)REG_CAN0_MB08_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB09_ID0               ((volatile uint16_t *)REG_CAN0_MB09_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB10_ID0               ((volatile uint16_t *)REG_CAN0_MB10_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB11_ID0               ((volatile uint16_t *)REG_CAN0_MB11_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB12_ID0               ((volatile uint16_t *)REG_CAN0_MB12_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB13_ID0               ((volatile uint16_t *)REG_CAN0_MB13_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB14_ID0               ((volatile uint16_t *)REG_CAN0_MB14_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB15_ID0               ((volatile uint16_t *)REG_CAN0_MB15_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB16_ID0               ((volatile uint16_t *)REG_CAN0_MB16_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB17_ID0               ((volatile uint16_t *)REG_CAN0_MB17_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB18_ID0               ((volatile uint16_t *)REG_CAN0_MB18_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB19_ID0               ((volatile uint16_t *)REG_CAN0_MB19_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB20_ID0               ((volatile uint16_t *)REG_CAN0_MB20_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB21_ID0               ((volatile uint16_t *)REG_CAN0_MB21_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB22_ID0               ((volatile uint16_t *)REG_CAN0_MB22_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB23_ID0               ((volatile uint16_t *)REG_CAN0_MB23_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB24_ID0               ((volatile uint16_t *)REG_CAN0_MB24_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB25_ID0               ((volatile uint16_t *)REG_CAN0_MB25_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB26_ID0               ((volatile uint16_t *)REG_CAN0_MB26_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB27_ID0               ((volatile uint16_t *)REG_CAN0_MB27_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB28_ID0               ((volatile uint16_t *)REG_CAN0_MB28_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB29_ID0               ((volatile uint16_t *)REG_CAN0_MB29_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB30_ID0               ((volatile uint16_t *)REG_CAN0_MB30_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB31_ID0               ((volatile uint16_t *)REG_CAN0_MB31_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB00_ID1               ((volatile uint16_t *)REG_CAN0_MB00_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB01_ID1               ((volatile uint16_t *)REG_CAN0_MB01_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB02_ID1               ((volatile uint16_t *)REG_CAN0_MB02_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB03_ID1               ((volatile uint16_t *)REG_CAN0_MB03_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB04_ID1               ((volatile uint16_t *)REG_CAN0_MB04_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB05_ID1               ((volatile uint16_t *)REG_CAN0_MB05_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB06_ID1               ((volatile uint16_t *)REG_CAN0_MB06_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB07_ID1               ((volatile uint16_t *)REG_CAN0_MB07_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB08_ID1               ((volatile uint16_t *)REG_CAN0_MB08_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB09_ID1               ((volatile uint16_t *)REG_CAN0_MB09_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB10_ID1               ((volatile uint16_t *)REG_CAN0_MB10_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB11_ID1               ((volatile uint16_t *)REG_CAN0_MB11_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB12_ID1               ((volatile uint16_t *)REG_CAN0_MB12_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB13_ID1               ((volatile uint16_t *)REG_CAN0_MB13_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB14_ID1               ((volatile uint16_t *)REG_CAN0_MB14_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB15_ID1               ((volatile uint16_t *)REG_CAN0_MB15_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB16_ID1               ((volatile uint16_t *)REG_CAN0_MB16_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB17_ID1               ((volatile uint16_t *)REG_CAN0_MB17_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB18_ID1               ((volatile uint16_t *)REG_CAN0_MB18_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB19_ID1               ((volatile uint16_t *)REG_CAN0_MB19_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB20_ID1               ((volatile uint16_t *)REG_CAN0_MB20_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB21_ID1               ((volatile uint16_t *)REG_CAN0_MB21_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB22_ID1               ((volatile uint16_t *)REG_CAN0_MB22_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB23_ID1               ((volatile uint16_t *)REG_CAN0_MB23_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB24_ID1               ((volatile uint16_t *)REG_CAN0_MB24_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB25_ID1               ((volatile uint16_t *)REG_CAN0_MB25_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB26_ID1               ((volatile uint16_t *)REG_CAN0_MB26_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB27_ID1               ((volatile uint16_t *)REG_CAN0_MB27_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB28_ID1               ((volatile uint16_t *)REG_CAN0_MB28_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB29_ID1               ((volatile uint16_t *)REG_CAN0_MB29_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB30_ID1               ((volatile uint16_t *)REG_CAN0_MB30_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB31_ID1               ((volatile uint16_t *)REG_CAN0_MB31_ID1)                /* CAN0 Mailbox ID 1 Register */
-
-
-/* =========================================================================
-       LP0
-   ========================================================================= */
-#define pREG_LP0_CTL                     ((volatile uint32_t *)REG_LP0_CTL)                      /* LP0 Control Register */
-#define pREG_LP0_STAT                    ((volatile uint32_t *)REG_LP0_STAT)                     /* LP0 Status Register */
-#define pREG_LP0_DIV                     ((volatile uint32_t *)REG_LP0_DIV)                      /* LP0 Clock Divider Value */
-#define pREG_LP0_TX                      ((volatile uint32_t *)REG_LP0_TX)                       /* LP0 Transmit Buffer */
-#define pREG_LP0_RX                      ((volatile uint32_t *)REG_LP0_RX)                       /* LP0 Receive Buffer */
-#define pREG_LP0_TXIN_SHDW               ((volatile uint32_t *)REG_LP0_TXIN_SHDW)                /* LP0 Shadow Input Transmit Buffer */
-#define pREG_LP0_TXOUT_SHDW              ((volatile uint32_t *)REG_LP0_TXOUT_SHDW)               /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP1
-   ========================================================================= */
-#define pREG_LP1_CTL                     ((volatile uint32_t *)REG_LP1_CTL)                      /* LP1 Control Register */
-#define pREG_LP1_STAT                    ((volatile uint32_t *)REG_LP1_STAT)                     /* LP1 Status Register */
-#define pREG_LP1_DIV                     ((volatile uint32_t *)REG_LP1_DIV)                      /* LP1 Clock Divider Value */
-#define pREG_LP1_TX                      ((volatile uint32_t *)REG_LP1_TX)                       /* LP1 Transmit Buffer */
-#define pREG_LP1_RX                      ((volatile uint32_t *)REG_LP1_RX)                       /* LP1 Receive Buffer */
-#define pREG_LP1_TXIN_SHDW               ((volatile uint32_t *)REG_LP1_TXIN_SHDW)                /* LP1 Shadow Input Transmit Buffer */
-#define pREG_LP1_TXOUT_SHDW              ((volatile uint32_t *)REG_LP1_TXOUT_SHDW)               /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP2
-   ========================================================================= */
-#define pREG_LP2_CTL                     ((volatile uint32_t *)REG_LP2_CTL)                      /* LP2 Control Register */
-#define pREG_LP2_STAT                    ((volatile uint32_t *)REG_LP2_STAT)                     /* LP2 Status Register */
-#define pREG_LP2_DIV                     ((volatile uint32_t *)REG_LP2_DIV)                      /* LP2 Clock Divider Value */
-#define pREG_LP2_TX                      ((volatile uint32_t *)REG_LP2_TX)                       /* LP2 Transmit Buffer */
-#define pREG_LP2_RX                      ((volatile uint32_t *)REG_LP2_RX)                       /* LP2 Receive Buffer */
-#define pREG_LP2_TXIN_SHDW               ((volatile uint32_t *)REG_LP2_TXIN_SHDW)                /* LP2 Shadow Input Transmit Buffer */
-#define pREG_LP2_TXOUT_SHDW              ((volatile uint32_t *)REG_LP2_TXOUT_SHDW)               /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP3
-   ========================================================================= */
-#define pREG_LP3_CTL                     ((volatile uint32_t *)REG_LP3_CTL)                      /* LP3 Control Register */
-#define pREG_LP3_STAT                    ((volatile uint32_t *)REG_LP3_STAT)                     /* LP3 Status Register */
-#define pREG_LP3_DIV                     ((volatile uint32_t *)REG_LP3_DIV)                      /* LP3 Clock Divider Value */
-#define pREG_LP3_TX                      ((volatile uint32_t *)REG_LP3_TX)                       /* LP3 Transmit Buffer */
-#define pREG_LP3_RX                      ((volatile uint32_t *)REG_LP3_RX)                       /* LP3 Receive Buffer */
-#define pREG_LP3_TXIN_SHDW               ((volatile uint32_t *)REG_LP3_TXIN_SHDW)                /* LP3 Shadow Input Transmit Buffer */
-#define pREG_LP3_TXOUT_SHDW              ((volatile uint32_t *)REG_LP3_TXOUT_SHDW)               /* LP3 Shadow Output Transmit Buffer */
-
-
-/* =========================================================================
-       TIMER0
-   ========================================================================= */
-#define pREG_TIMER0_REVID                ((volatile uint16_t *)REG_TIMER0_REVID)                 /* TIMER0 Revision ID Register */
-#define pREG_TIMER0_RUN                  ((volatile uint16_t *)REG_TIMER0_RUN)                   /* TIMER0 Run Register */
-#define pREG_TIMER0_RUN_SET              ((volatile uint16_t *)REG_TIMER0_RUN_SET)               /* TIMER0 Run Set Register */
-#define pREG_TIMER0_RUN_CLR              ((volatile uint16_t *)REG_TIMER0_RUN_CLR)               /* TIMER0 Run Clear Register */
-#define pREG_TIMER0_STOP_CFG             ((volatile uint16_t *)REG_TIMER0_STOP_CFG)              /* TIMER0 Stop Configuration Register */
-#define pREG_TIMER0_STOP_CFG_SET         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_SET)          /* TIMER0 Stop Configuration Set Register */
-#define pREG_TIMER0_STOP_CFG_CLR         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_CLR)          /* TIMER0 Stop Configuration Clear Register */
-#define pREG_TIMER0_DATA_IMSK            ((volatile uint16_t *)REG_TIMER0_DATA_IMSK)             /* TIMER0 Data Interrupt Mask Register */
-#define pREG_TIMER0_STAT_IMSK            ((volatile uint16_t *)REG_TIMER0_STAT_IMSK)             /* TIMER0 Status Interrupt Mask Register */
-#define pREG_TIMER0_TRG_MSK              ((volatile uint16_t *)REG_TIMER0_TRG_MSK)               /* TIMER0 Trigger Master Mask Register */
-#define pREG_TIMER0_TRG_IE               ((volatile uint16_t *)REG_TIMER0_TRG_IE)                /* TIMER0 Trigger Slave Enable Register */
-#define pREG_TIMER0_DATA_ILAT            ((volatile uint16_t *)REG_TIMER0_DATA_ILAT)             /* TIMER0 Data Interrupt Latch Register */
-#define pREG_TIMER0_STAT_ILAT            ((volatile uint16_t *)REG_TIMER0_STAT_ILAT)             /* TIMER0 Status Interrupt Latch Register */
-#define pREG_TIMER0_ERR_TYPE             ((volatile uint32_t *)REG_TIMER0_ERR_TYPE)              /* TIMER0 Error Type Status Register */
-#define pREG_TIMER0_BCAST_PER            ((volatile uint32_t *)REG_TIMER0_BCAST_PER)             /* TIMER0 Broadcast Period Register */
-#define pREG_TIMER0_BCAST_WID            ((volatile uint32_t *)REG_TIMER0_BCAST_WID)             /* TIMER0 Broadcast Width Register */
-#define pREG_TIMER0_BCAST_DLY            ((volatile uint32_t *)REG_TIMER0_BCAST_DLY)             /* TIMER0 Broadcast Delay Register */
-#define pREG_TIMER0_TMR0_CFG             ((volatile uint16_t *)REG_TIMER0_TMR0_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR1_CFG             ((volatile uint16_t *)REG_TIMER0_TMR1_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR2_CFG             ((volatile uint16_t *)REG_TIMER0_TMR2_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR3_CFG             ((volatile uint16_t *)REG_TIMER0_TMR3_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR4_CFG             ((volatile uint16_t *)REG_TIMER0_TMR4_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR5_CFG             ((volatile uint16_t *)REG_TIMER0_TMR5_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR6_CFG             ((volatile uint16_t *)REG_TIMER0_TMR6_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR7_CFG             ((volatile uint16_t *)REG_TIMER0_TMR7_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR0_CNT             ((volatile uint32_t *)REG_TIMER0_TMR0_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR1_CNT             ((volatile uint32_t *)REG_TIMER0_TMR1_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR2_CNT             ((volatile uint32_t *)REG_TIMER0_TMR2_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR3_CNT             ((volatile uint32_t *)REG_TIMER0_TMR3_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR4_CNT             ((volatile uint32_t *)REG_TIMER0_TMR4_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR5_CNT             ((volatile uint32_t *)REG_TIMER0_TMR5_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR6_CNT             ((volatile uint32_t *)REG_TIMER0_TMR6_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR7_CNT             ((volatile uint32_t *)REG_TIMER0_TMR7_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR0_PER             ((volatile uint32_t *)REG_TIMER0_TMR0_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR1_PER             ((volatile uint32_t *)REG_TIMER0_TMR1_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR2_PER             ((volatile uint32_t *)REG_TIMER0_TMR2_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR3_PER             ((volatile uint32_t *)REG_TIMER0_TMR3_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR4_PER             ((volatile uint32_t *)REG_TIMER0_TMR4_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR5_PER             ((volatile uint32_t *)REG_TIMER0_TMR5_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR6_PER             ((volatile uint32_t *)REG_TIMER0_TMR6_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR7_PER             ((volatile uint32_t *)REG_TIMER0_TMR7_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR0_WID             ((volatile uint32_t *)REG_TIMER0_TMR0_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR1_WID             ((volatile uint32_t *)REG_TIMER0_TMR1_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR2_WID             ((volatile uint32_t *)REG_TIMER0_TMR2_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR3_WID             ((volatile uint32_t *)REG_TIMER0_TMR3_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR4_WID             ((volatile uint32_t *)REG_TIMER0_TMR4_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR5_WID             ((volatile uint32_t *)REG_TIMER0_TMR5_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR6_WID             ((volatile uint32_t *)REG_TIMER0_TMR6_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR7_WID             ((volatile uint32_t *)REG_TIMER0_TMR7_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR0_DLY             ((volatile uint32_t *)REG_TIMER0_TMR0_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR1_DLY             ((volatile uint32_t *)REG_TIMER0_TMR1_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR2_DLY             ((volatile uint32_t *)REG_TIMER0_TMR2_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR3_DLY             ((volatile uint32_t *)REG_TIMER0_TMR3_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR4_DLY             ((volatile uint32_t *)REG_TIMER0_TMR4_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR5_DLY             ((volatile uint32_t *)REG_TIMER0_TMR5_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR6_DLY             ((volatile uint32_t *)REG_TIMER0_TMR6_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR7_DLY             ((volatile uint32_t *)REG_TIMER0_TMR7_DLY)              /* TIMER0 Timer n Delay Register */
-
-
-/* =========================================================================
-       CRC0
-   ========================================================================= */
-#define pREG_CRC0_CTL                    ((volatile uint32_t *)REG_CRC0_CTL)                     /* CRC0 Control Register */
-#define pREG_CRC0_DCNT                   ((volatile uint32_t *)REG_CRC0_DCNT)                    /* CRC0 Data Word Count Register */
-#define pREG_CRC0_DCNTRLD                ((volatile uint32_t *)REG_CRC0_DCNTRLD)                 /* CRC0 Data Word Count Reload Register */
-#define pREG_CRC0_COMP                   ((volatile uint32_t *)REG_CRC0_COMP)                    /* CRC0 Data Compare Register */
-#define pREG_CRC0_FILLVAL                ((volatile uint32_t *)REG_CRC0_FILLVAL)                 /* CRC0 Fill Value Register */
-#define pREG_CRC0_DFIFO                  ((volatile uint32_t *)REG_CRC0_DFIFO)                   /* CRC0 Data FIFO Register */
-#define pREG_CRC0_INEN                   ((volatile uint32_t *)REG_CRC0_INEN)                    /* CRC0 Interrupt Enable Register */
-#define pREG_CRC0_INEN_SET               ((volatile uint32_t *)REG_CRC0_INEN_SET)                /* CRC0 Interrupt Enable Set Register */
-#define pREG_CRC0_INEN_CLR               ((volatile uint32_t *)REG_CRC0_INEN_CLR)                /* CRC0 Interrupt Enable Clear Register */
-#define pREG_CRC0_POLY                   ((volatile uint32_t *)REG_CRC0_POLY)                    /* CRC0 Polynomial Register */
-#define pREG_CRC0_STAT                   ((volatile uint32_t *)REG_CRC0_STAT)                    /* CRC0 Status Register */
-#define pREG_CRC0_DCNTCAP                ((volatile uint32_t *)REG_CRC0_DCNTCAP)                 /* CRC0 Data Count Capture Register */
-#define pREG_CRC0_RESULT_FIN             ((volatile uint32_t *)REG_CRC0_RESULT_FIN)              /* CRC0 CRC Final Result Register */
-#define pREG_CRC0_RESULT_CUR             ((volatile uint32_t *)REG_CRC0_RESULT_CUR)              /* CRC0 CRC Current Result Register */
-#define pREG_CRC0_REVID                  ((volatile uint32_t *)REG_CRC0_REVID)                   /* CRC0 Revision ID Register */
-
-/* =========================================================================
-       CRC1
-   ========================================================================= */
-#define pREG_CRC1_CTL                    ((volatile uint32_t *)REG_CRC1_CTL)                     /* CRC1 Control Register */
-#define pREG_CRC1_DCNT                   ((volatile uint32_t *)REG_CRC1_DCNT)                    /* CRC1 Data Word Count Register */
-#define pREG_CRC1_DCNTRLD                ((volatile uint32_t *)REG_CRC1_DCNTRLD)                 /* CRC1 Data Word Count Reload Register */
-#define pREG_CRC1_COMP                   ((volatile uint32_t *)REG_CRC1_COMP)                    /* CRC1 Data Compare Register */
-#define pREG_CRC1_FILLVAL                ((volatile uint32_t *)REG_CRC1_FILLVAL)                 /* CRC1 Fill Value Register */
-#define pREG_CRC1_DFIFO                  ((volatile uint32_t *)REG_CRC1_DFIFO)                   /* CRC1 Data FIFO Register */
-#define pREG_CRC1_INEN                   ((volatile uint32_t *)REG_CRC1_INEN)                    /* CRC1 Interrupt Enable Register */
-#define pREG_CRC1_INEN_SET               ((volatile uint32_t *)REG_CRC1_INEN_SET)                /* CRC1 Interrupt Enable Set Register */
-#define pREG_CRC1_INEN_CLR               ((volatile uint32_t *)REG_CRC1_INEN_CLR)                /* CRC1 Interrupt Enable Clear Register */
-#define pREG_CRC1_POLY                   ((volatile uint32_t *)REG_CRC1_POLY)                    /* CRC1 Polynomial Register */
-#define pREG_CRC1_STAT                   ((volatile uint32_t *)REG_CRC1_STAT)                    /* CRC1 Status Register */
-#define pREG_CRC1_DCNTCAP                ((volatile uint32_t *)REG_CRC1_DCNTCAP)                 /* CRC1 Data Count Capture Register */
-#define pREG_CRC1_RESULT_FIN             ((volatile uint32_t *)REG_CRC1_RESULT_FIN)              /* CRC1 CRC Final Result Register */
-#define pREG_CRC1_RESULT_CUR             ((volatile uint32_t *)REG_CRC1_RESULT_CUR)              /* CRC1 CRC Current Result Register */
-#define pREG_CRC1_REVID                  ((volatile uint32_t *)REG_CRC1_REVID)                   /* CRC1 Revision ID Register */
-
-
-/* =========================================================================
-       TWI0
-   ========================================================================= */
-#define pREG_TWI0_CLKDIV                 ((volatile uint16_t *)REG_TWI0_CLKDIV)                  /* TWI0 SCL Clock Divider Register */
-#define pREG_TWI0_CTL                    ((volatile uint16_t *)REG_TWI0_CTL)                     /* TWI0 Control Register */
-#define pREG_TWI0_SLVCTL                 ((volatile uint16_t *)REG_TWI0_SLVCTL)                  /* TWI0 Slave Mode Control Register */
-#define pREG_TWI0_SLVSTAT                ((volatile uint16_t *)REG_TWI0_SLVSTAT)                 /* TWI0 Slave Mode Status Register */
-#define pREG_TWI0_SLVADDR                ((volatile uint16_t *)REG_TWI0_SLVADDR)                 /* TWI0 Slave Mode Address Register */
-#define pREG_TWI0_MSTRCTL                ((volatile uint16_t *)REG_TWI0_MSTRCTL)                 /* TWI0 Master Mode Control Registers */
-#define pREG_TWI0_MSTRSTAT               ((volatile uint16_t *)REG_TWI0_MSTRSTAT)                /* TWI0 Master Mode Status Register */
-#define pREG_TWI0_MSTRADDR               ((volatile uint16_t *)REG_TWI0_MSTRADDR)                /* TWI0 Master Mode Address Register */
-#define pREG_TWI0_ISTAT                  ((volatile uint16_t *)REG_TWI0_ISTAT)                   /* TWI0 Interrupt Status Register */
-#define pREG_TWI0_IMSK                   ((volatile uint16_t *)REG_TWI0_IMSK)                    /* TWI0 Interrupt Mask Register */
-#define pREG_TWI0_FIFOCTL                ((volatile uint16_t *)REG_TWI0_FIFOCTL)                 /* TWI0 FIFO Control Register */
-#define pREG_TWI0_FIFOSTAT               ((volatile uint16_t *)REG_TWI0_FIFOSTAT)                /* TWI0 FIFO Status Register */
-#define pREG_TWI0_TXDATA8                ((volatile uint16_t *)REG_TWI0_TXDATA8)                 /* TWI0 Tx Data Single-Byte Register */
-#define pREG_TWI0_TXDATA16               ((volatile uint16_t *)REG_TWI0_TXDATA16)                /* TWI0 Tx Data Double-Byte Register */
-#define pREG_TWI0_RXDATA8                ((volatile uint16_t *)REG_TWI0_RXDATA8)                 /* TWI0 Rx Data Single-Byte Register */
-#define pREG_TWI0_RXDATA16               ((volatile uint16_t *)REG_TWI0_RXDATA16)                /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================================================================
-       TWI1
-   ========================================================================= */
-#define pREG_TWI1_CLKDIV                 ((volatile uint16_t *)REG_TWI1_CLKDIV)                  /* TWI1 SCL Clock Divider Register */
-#define pREG_TWI1_CTL                    ((volatile uint16_t *)REG_TWI1_CTL)                     /* TWI1 Control Register */
-#define pREG_TWI1_SLVCTL                 ((volatile uint16_t *)REG_TWI1_SLVCTL)                  /* TWI1 Slave Mode Control Register */
-#define pREG_TWI1_SLVSTAT                ((volatile uint16_t *)REG_TWI1_SLVSTAT)                 /* TWI1 Slave Mode Status Register */
-#define pREG_TWI1_SLVADDR                ((volatile uint16_t *)REG_TWI1_SLVADDR)                 /* TWI1 Slave Mode Address Register */
-#define pREG_TWI1_MSTRCTL                ((volatile uint16_t *)REG_TWI1_MSTRCTL)                 /* TWI1 Master Mode Control Registers */
-#define pREG_TWI1_MSTRSTAT               ((volatile uint16_t *)REG_TWI1_MSTRSTAT)                /* TWI1 Master Mode Status Register */
-#define pREG_TWI1_MSTRADDR               ((volatile uint16_t *)REG_TWI1_MSTRADDR)                /* TWI1 Master Mode Address Register */
-#define pREG_TWI1_ISTAT                  ((volatile uint16_t *)REG_TWI1_ISTAT)                   /* TWI1 Interrupt Status Register */
-#define pREG_TWI1_IMSK                   ((volatile uint16_t *)REG_TWI1_IMSK)                    /* TWI1 Interrupt Mask Register */
-#define pREG_TWI1_FIFOCTL                ((volatile uint16_t *)REG_TWI1_FIFOCTL)                 /* TWI1 FIFO Control Register */
-#define pREG_TWI1_FIFOSTAT               ((volatile uint16_t *)REG_TWI1_FIFOSTAT)                /* TWI1 FIFO Status Register */
-#define pREG_TWI1_TXDATA8                ((volatile uint16_t *)REG_TWI1_TXDATA8)                 /* TWI1 Tx Data Single-Byte Register */
-#define pREG_TWI1_TXDATA16               ((volatile uint16_t *)REG_TWI1_TXDATA16)                /* TWI1 Tx Data Double-Byte Register */
-#define pREG_TWI1_RXDATA8                ((volatile uint16_t *)REG_TWI1_RXDATA8)                 /* TWI1 Rx Data Single-Byte Register */
-#define pREG_TWI1_RXDATA16               ((volatile uint16_t *)REG_TWI1_RXDATA16)                /* TWI1 Rx Data Double-Byte Register */
-
-
-/* =========================================================================
-       UART0
-   ========================================================================= */
-#define pREG_UART0_REVID                 ((volatile uint32_t *)REG_UART0_REVID)                  /* UART0 Revision ID Register */
-#define pREG_UART0_CTL                   ((volatile uint32_t *)REG_UART0_CTL)                    /* UART0 Control Register */
-#define pREG_UART0_STAT                  ((volatile uint32_t *)REG_UART0_STAT)                   /* UART0 Status Register */
-#define pREG_UART0_SCR                   ((volatile uint32_t *)REG_UART0_SCR)                    /* UART0 Scratch Register */
-#define pREG_UART0_CLK                   ((volatile uint32_t *)REG_UART0_CLK)                    /* UART0 Clock Rate Register */
-#define pREG_UART0_IMSK                  ((volatile uint32_t *)REG_UART0_IMSK)                   /* UART0 Interrupt Mask Register */
-#define pREG_UART0_IMSK_SET              ((volatile uint32_t *)REG_UART0_IMSK_SET)               /* UART0 Interrupt Mask Set Register */
-#define pREG_UART0_IMSK_CLR              ((volatile uint32_t *)REG_UART0_IMSK_CLR)               /* UART0 Interrupt Mask Clear Register */
-#define pREG_UART0_RBR                   ((volatile uint32_t *)REG_UART0_RBR)                    /* UART0 Receive Buffer Register */
-#define pREG_UART0_THR                   ((volatile uint32_t *)REG_UART0_THR)                    /* UART0 Transmit Hold Register */
-#define pREG_UART0_TAIP                  ((volatile uint32_t *)REG_UART0_TAIP)                   /* UART0 Transmit Address/Insert Pulse Register */
-#define pREG_UART0_TSR                   ((volatile uint32_t *)REG_UART0_TSR)                    /* UART0 Transmit Shift Register */
-#define pREG_UART0_RSR                   ((volatile uint32_t *)REG_UART0_RSR)                    /* UART0 Receive Shift Register */
-#define pREG_UART0_TXCNT                 ((volatile uint32_t *)REG_UART0_TXCNT)                  /* UART0 Transmit Counter Register */
-#define pREG_UART0_RXCNT                 ((volatile uint32_t *)REG_UART0_RXCNT)                  /* UART0 Receive Counter Register */
-
-/* =========================================================================
-       UART1
-   ========================================================================= */
-#define pREG_UART1_REVID                 ((volatile uint32_t *)REG_UART1_REVID)                  /* UART1 Revision ID Register */
-#define pREG_UART1_CTL                   ((volatile uint32_t *)REG_UART1_CTL)                    /* UART1 Control Register */
-#define pREG_UART1_STAT                  ((volatile uint32_t *)REG_UART1_STAT)                   /* UART1 Status Register */
-#define pREG_UART1_SCR                   ((volatile uint32_t *)REG_UART1_SCR)                    /* UART1 Scratch Register */
-#define pREG_UART1_CLK                   ((volatile uint32_t *)REG_UART1_CLK)                    /* UART1 Clock Rate Register */
-#define pREG_UART1_IMSK                  ((volatile uint32_t *)REG_UART1_IMSK)                   /* UART1 Interrupt Mask Register */
-#define pREG_UART1_IMSK_SET              ((volatile uint32_t *)REG_UART1_IMSK_SET)               /* UART1 Interrupt Mask Set Register */
-#define pREG_UART1_IMSK_CLR              ((volatile uint32_t *)REG_UART1_IMSK_CLR)               /* UART1 Interrupt Mask Clear Register */
-#define pREG_UART1_RBR                   ((volatile uint32_t *)REG_UART1_RBR)                    /* UART1 Receive Buffer Register */
-#define pREG_UART1_THR                   ((volatile uint32_t *)REG_UART1_THR)                    /* UART1 Transmit Hold Register */
-#define pREG_UART1_TAIP                  ((volatile uint32_t *)REG_UART1_TAIP)                   /* UART1 Transmit Address/Insert Pulse Register */
-#define pREG_UART1_TSR                   ((volatile uint32_t *)REG_UART1_TSR)                    /* UART1 Transmit Shift Register */
-#define pREG_UART1_RSR                   ((volatile uint32_t *)REG_UART1_RSR)                    /* UART1 Receive Shift Register */
-#define pREG_UART1_TXCNT                 ((volatile uint32_t *)REG_UART1_TXCNT)                  /* UART1 Transmit Counter Register */
-#define pREG_UART1_RXCNT                 ((volatile uint32_t *)REG_UART1_RXCNT)                  /* UART1 Receive Counter Register */
-
-
-/* =========================================================================
-       PORTA
-   ========================================================================= */
-#define pREG_PORTA_FER                   ((volatile uint32_t *)REG_PORTA_FER)                    /* PORTA Port x Function Enable Register */
-#define pREG_PORTA_FER_SET               ((volatile uint32_t *)REG_PORTA_FER_SET)                /* PORTA Port x Function Enable Set Register */
-#define pREG_PORTA_FER_CLR               ((volatile uint32_t *)REG_PORTA_FER_CLR)                /* PORTA Port x Function Enable Clear Register */
-#define pREG_PORTA_DATA                  ((volatile uint32_t *)REG_PORTA_DATA)                   /* PORTA Port x GPIO Data Register */
-#define pREG_PORTA_DATA_SET              ((volatile uint32_t *)REG_PORTA_DATA_SET)               /* PORTA Port x GPIO Data Set Register */
-#define pREG_PORTA_DATA_CLR              ((volatile uint32_t *)REG_PORTA_DATA_CLR)               /* PORTA Port x GPIO Data Clear Register */
-#define pREG_PORTA_DIR                   ((volatile uint32_t *)REG_PORTA_DIR)                    /* PORTA Port x GPIO Direction Register */
-#define pREG_PORTA_DIR_SET               ((volatile uint32_t *)REG_PORTA_DIR_SET)                /* PORTA Port x GPIO Direction Set Register */
-#define pREG_PORTA_DIR_CLR               ((volatile uint32_t *)REG_PORTA_DIR_CLR)                /* PORTA Port x GPIO Direction Clear Register */
-#define pREG_PORTA_INEN                  ((volatile uint32_t *)REG_PORTA_INEN)                   /* PORTA Port x GPIO Input Enable Register */
-#define pREG_PORTA_INEN_SET              ((volatile uint32_t *)REG_PORTA_INEN_SET)               /* PORTA Port x GPIO Input Enable Set Register */
-#define pREG_PORTA_INEN_CLR              ((volatile uint32_t *)REG_PORTA_INEN_CLR)               /* PORTA Port x GPIO Input Enable Clear Register */
-#define pREG_PORTA_MUX                   ((volatile uint32_t *)REG_PORTA_MUX)                    /* PORTA Port x Multiplexer Control Register */
-#define pREG_PORTA_DATA_TGL              ((volatile uint32_t *)REG_PORTA_DATA_TGL)               /* PORTA Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTA_POL                   ((volatile uint32_t *)REG_PORTA_POL)                    /* PORTA Port x GPIO Polarity Invert Register */
-#define pREG_PORTA_POL_SET               ((volatile uint32_t *)REG_PORTA_POL_SET)                /* PORTA Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTA_POL_CLR               ((volatile uint32_t *)REG_PORTA_POL_CLR)                /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTA_LOCK                  ((volatile uint32_t *)REG_PORTA_LOCK)                   /* PORTA Port x GPIO Lock Register */
-#define pREG_PORTA_REVID                 ((volatile uint32_t *)REG_PORTA_REVID)                  /* PORTA Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTB
-   ========================================================================= */
-#define pREG_PORTB_FER                   ((volatile uint32_t *)REG_PORTB_FER)                    /* PORTB Port x Function Enable Register */
-#define pREG_PORTB_FER_SET               ((volatile uint32_t *)REG_PORTB_FER_SET)                /* PORTB Port x Function Enable Set Register */
-#define pREG_PORTB_FER_CLR               ((volatile uint32_t *)REG_PORTB_FER_CLR)                /* PORTB Port x Function Enable Clear Register */
-#define pREG_PORTB_DATA                  ((volatile uint32_t *)REG_PORTB_DATA)                   /* PORTB Port x GPIO Data Register */
-#define pREG_PORTB_DATA_SET              ((volatile uint32_t *)REG_PORTB_DATA_SET)               /* PORTB Port x GPIO Data Set Register */
-#define pREG_PORTB_DATA_CLR              ((volatile uint32_t *)REG_PORTB_DATA_CLR)               /* PORTB Port x GPIO Data Clear Register */
-#define pREG_PORTB_DIR                   ((volatile uint32_t *)REG_PORTB_DIR)                    /* PORTB Port x GPIO Direction Register */
-#define pREG_PORTB_DIR_SET               ((volatile uint32_t *)REG_PORTB_DIR_SET)                /* PORTB Port x GPIO Direction Set Register */
-#define pREG_PORTB_DIR_CLR               ((volatile uint32_t *)REG_PORTB_DIR_CLR)                /* PORTB Port x GPIO Direction Clear Register */
-#define pREG_PORTB_INEN                  ((volatile uint32_t *)REG_PORTB_INEN)                   /* PORTB Port x GPIO Input Enable Register */
-#define pREG_PORTB_INEN_SET              ((volatile uint32_t *)REG_PORTB_INEN_SET)               /* PORTB Port x GPIO Input Enable Set Register */
-#define pREG_PORTB_INEN_CLR              ((volatile uint32_t *)REG_PORTB_INEN_CLR)               /* PORTB Port x GPIO Input Enable Clear Register */
-#define pREG_PORTB_MUX                   ((volatile uint32_t *)REG_PORTB_MUX)                    /* PORTB Port x Multiplexer Control Register */
-#define pREG_PORTB_DATA_TGL              ((volatile uint32_t *)REG_PORTB_DATA_TGL)               /* PORTB Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTB_POL                   ((volatile uint32_t *)REG_PORTB_POL)                    /* PORTB Port x GPIO Polarity Invert Register */
-#define pREG_PORTB_POL_SET               ((volatile uint32_t *)REG_PORTB_POL_SET)                /* PORTB Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTB_POL_CLR               ((volatile uint32_t *)REG_PORTB_POL_CLR)                /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTB_LOCK                  ((volatile uint32_t *)REG_PORTB_LOCK)                   /* PORTB Port x GPIO Lock Register */
-#define pREG_PORTB_REVID                 ((volatile uint32_t *)REG_PORTB_REVID)                  /* PORTB Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTC
-   ========================================================================= */
-#define pREG_PORTC_FER                   ((volatile uint32_t *)REG_PORTC_FER)                    /* PORTC Port x Function Enable Register */
-#define pREG_PORTC_FER_SET               ((volatile uint32_t *)REG_PORTC_FER_SET)                /* PORTC Port x Function Enable Set Register */
-#define pREG_PORTC_FER_CLR               ((volatile uint32_t *)REG_PORTC_FER_CLR)                /* PORTC Port x Function Enable Clear Register */
-#define pREG_PORTC_DATA                  ((volatile uint32_t *)REG_PORTC_DATA)                   /* PORTC Port x GPIO Data Register */
-#define pREG_PORTC_DATA_SET              ((volatile uint32_t *)REG_PORTC_DATA_SET)               /* PORTC Port x GPIO Data Set Register */
-#define pREG_PORTC_DATA_CLR              ((volatile uint32_t *)REG_PORTC_DATA_CLR)               /* PORTC Port x GPIO Data Clear Register */
-#define pREG_PORTC_DIR                   ((volatile uint32_t *)REG_PORTC_DIR)                    /* PORTC Port x GPIO Direction Register */
-#define pREG_PORTC_DIR_SET               ((volatile uint32_t *)REG_PORTC_DIR_SET)                /* PORTC Port x GPIO Direction Set Register */
-#define pREG_PORTC_DIR_CLR               ((volatile uint32_t *)REG_PORTC_DIR_CLR)                /* PORTC Port x GPIO Direction Clear Register */
-#define pREG_PORTC_INEN                  ((volatile uint32_t *)REG_PORTC_INEN)                   /* PORTC Port x GPIO Input Enable Register */
-#define pREG_PORTC_INEN_SET              ((volatile uint32_t *)REG_PORTC_INEN_SET)               /* PORTC Port x GPIO Input Enable Set Register */
-#define pREG_PORTC_INEN_CLR              ((volatile uint32_t *)REG_PORTC_INEN_CLR)               /* PORTC Port x GPIO Input Enable Clear Register */
-#define pREG_PORTC_MUX                   ((volatile uint32_t *)REG_PORTC_MUX)                    /* PORTC Port x Multiplexer Control Register */
-#define pREG_PORTC_DATA_TGL              ((volatile uint32_t *)REG_PORTC_DATA_TGL)               /* PORTC Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTC_POL                   ((volatile uint32_t *)REG_PORTC_POL)                    /* PORTC Port x GPIO Polarity Invert Register */
-#define pREG_PORTC_POL_SET               ((volatile uint32_t *)REG_PORTC_POL_SET)                /* PORTC Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTC_POL_CLR               ((volatile uint32_t *)REG_PORTC_POL_CLR)                /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTC_LOCK                  ((volatile uint32_t *)REG_PORTC_LOCK)                   /* PORTC Port x GPIO Lock Register */
-#define pREG_PORTC_REVID                 ((volatile uint32_t *)REG_PORTC_REVID)                  /* PORTC Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTD
-   ========================================================================= */
-#define pREG_PORTD_FER                   ((volatile uint32_t *)REG_PORTD_FER)                    /* PORTD Port x Function Enable Register */
-#define pREG_PORTD_FER_SET               ((volatile uint32_t *)REG_PORTD_FER_SET)                /* PORTD Port x Function Enable Set Register */
-#define pREG_PORTD_FER_CLR               ((volatile uint32_t *)REG_PORTD_FER_CLR)                /* PORTD Port x Function Enable Clear Register */
-#define pREG_PORTD_DATA                  ((volatile uint32_t *)REG_PORTD_DATA)                   /* PORTD Port x GPIO Data Register */
-#define pREG_PORTD_DATA_SET              ((volatile uint32_t *)REG_PORTD_DATA_SET)               /* PORTD Port x GPIO Data Set Register */
-#define pREG_PORTD_DATA_CLR              ((volatile uint32_t *)REG_PORTD_DATA_CLR)               /* PORTD Port x GPIO Data Clear Register */
-#define pREG_PORTD_DIR                   ((volatile uint32_t *)REG_PORTD_DIR)                    /* PORTD Port x GPIO Direction Register */
-#define pREG_PORTD_DIR_SET               ((volatile uint32_t *)REG_PORTD_DIR_SET)                /* PORTD Port x GPIO Direction Set Register */
-#define pREG_PORTD_DIR_CLR               ((volatile uint32_t *)REG_PORTD_DIR_CLR)                /* PORTD Port x GPIO Direction Clear Register */
-#define pREG_PORTD_INEN                  ((volatile uint32_t *)REG_PORTD_INEN)                   /* PORTD Port x GPIO Input Enable Register */
-#define pREG_PORTD_INEN_SET              ((volatile uint32_t *)REG_PORTD_INEN_SET)               /* PORTD Port x GPIO Input Enable Set Register */
-#define pREG_PORTD_INEN_CLR              ((volatile uint32_t *)REG_PORTD_INEN_CLR)               /* PORTD Port x GPIO Input Enable Clear Register */
-#define pREG_PORTD_MUX                   ((volatile uint32_t *)REG_PORTD_MUX)                    /* PORTD Port x Multiplexer Control Register */
-#define pREG_PORTD_DATA_TGL              ((volatile uint32_t *)REG_PORTD_DATA_TGL)               /* PORTD Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTD_POL                   ((volatile uint32_t *)REG_PORTD_POL)                    /* PORTD Port x GPIO Polarity Invert Register */
-#define pREG_PORTD_POL_SET               ((volatile uint32_t *)REG_PORTD_POL_SET)                /* PORTD Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTD_POL_CLR               ((volatile uint32_t *)REG_PORTD_POL_CLR)                /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTD_LOCK                  ((volatile uint32_t *)REG_PORTD_LOCK)                   /* PORTD Port x GPIO Lock Register */
-#define pREG_PORTD_REVID                 ((volatile uint32_t *)REG_PORTD_REVID)                  /* PORTD Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTE
-   ========================================================================= */
-#define pREG_PORTE_FER                   ((volatile uint32_t *)REG_PORTE_FER)                    /* PORTE Port x Function Enable Register */
-#define pREG_PORTE_FER_SET               ((volatile uint32_t *)REG_PORTE_FER_SET)                /* PORTE Port x Function Enable Set Register */
-#define pREG_PORTE_FER_CLR               ((volatile uint32_t *)REG_PORTE_FER_CLR)                /* PORTE Port x Function Enable Clear Register */
-#define pREG_PORTE_DATA                  ((volatile uint32_t *)REG_PORTE_DATA)                   /* PORTE Port x GPIO Data Register */
-#define pREG_PORTE_DATA_SET              ((volatile uint32_t *)REG_PORTE_DATA_SET)               /* PORTE Port x GPIO Data Set Register */
-#define pREG_PORTE_DATA_CLR              ((volatile uint32_t *)REG_PORTE_DATA_CLR)               /* PORTE Port x GPIO Data Clear Register */
-#define pREG_PORTE_DIR                   ((volatile uint32_t *)REG_PORTE_DIR)                    /* PORTE Port x GPIO Direction Register */
-#define pREG_PORTE_DIR_SET               ((volatile uint32_t *)REG_PORTE_DIR_SET)                /* PORTE Port x GPIO Direction Set Register */
-#define pREG_PORTE_DIR_CLR               ((volatile uint32_t *)REG_PORTE_DIR_CLR)                /* PORTE Port x GPIO Direction Clear Register */
-#define pREG_PORTE_INEN                  ((volatile uint32_t *)REG_PORTE_INEN)                   /* PORTE Port x GPIO Input Enable Register */
-#define pREG_PORTE_INEN_SET              ((volatile uint32_t *)REG_PORTE_INEN_SET)               /* PORTE Port x GPIO Input Enable Set Register */
-#define pREG_PORTE_INEN_CLR              ((volatile uint32_t *)REG_PORTE_INEN_CLR)               /* PORTE Port x GPIO Input Enable Clear Register */
-#define pREG_PORTE_MUX                   ((volatile uint32_t *)REG_PORTE_MUX)                    /* PORTE Port x Multiplexer Control Register */
-#define pREG_PORTE_DATA_TGL              ((volatile uint32_t *)REG_PORTE_DATA_TGL)               /* PORTE Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTE_POL                   ((volatile uint32_t *)REG_PORTE_POL)                    /* PORTE Port x GPIO Polarity Invert Register */
-#define pREG_PORTE_POL_SET               ((volatile uint32_t *)REG_PORTE_POL_SET)                /* PORTE Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTE_POL_CLR               ((volatile uint32_t *)REG_PORTE_POL_CLR)                /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTE_LOCK                  ((volatile uint32_t *)REG_PORTE_LOCK)                   /* PORTE Port x GPIO Lock Register */
-#define pREG_PORTE_REVID                 ((volatile uint32_t *)REG_PORTE_REVID)                  /* PORTE Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTF
-   ========================================================================= */
-#define pREG_PORTF_FER                   ((volatile uint32_t *)REG_PORTF_FER)                    /* PORTF Port x Function Enable Register */
-#define pREG_PORTF_FER_SET               ((volatile uint32_t *)REG_PORTF_FER_SET)                /* PORTF Port x Function Enable Set Register */
-#define pREG_PORTF_FER_CLR               ((volatile uint32_t *)REG_PORTF_FER_CLR)                /* PORTF Port x Function Enable Clear Register */
-#define pREG_PORTF_DATA                  ((volatile uint32_t *)REG_PORTF_DATA)                   /* PORTF Port x GPIO Data Register */
-#define pREG_PORTF_DATA_SET              ((volatile uint32_t *)REG_PORTF_DATA_SET)               /* PORTF Port x GPIO Data Set Register */
-#define pREG_PORTF_DATA_CLR              ((volatile uint32_t *)REG_PORTF_DATA_CLR)               /* PORTF Port x GPIO Data Clear Register */
-#define pREG_PORTF_DIR                   ((volatile uint32_t *)REG_PORTF_DIR)                    /* PORTF Port x GPIO Direction Register */
-#define pREG_PORTF_DIR_SET               ((volatile uint32_t *)REG_PORTF_DIR_SET)                /* PORTF Port x GPIO Direction Set Register */
-#define pREG_PORTF_DIR_CLR               ((volatile uint32_t *)REG_PORTF_DIR_CLR)                /* PORTF Port x GPIO Direction Clear Register */
-#define pREG_PORTF_INEN                  ((volatile uint32_t *)REG_PORTF_INEN)                   /* PORTF Port x GPIO Input Enable Register */
-#define pREG_PORTF_INEN_SET              ((volatile uint32_t *)REG_PORTF_INEN_SET)               /* PORTF Port x GPIO Input Enable Set Register */
-#define pREG_PORTF_INEN_CLR              ((volatile uint32_t *)REG_PORTF_INEN_CLR)               /* PORTF Port x GPIO Input Enable Clear Register */
-#define pREG_PORTF_MUX                   ((volatile uint32_t *)REG_PORTF_MUX)                    /* PORTF Port x Multiplexer Control Register */
-#define pREG_PORTF_DATA_TGL              ((volatile uint32_t *)REG_PORTF_DATA_TGL)               /* PORTF Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTF_POL                   ((volatile uint32_t *)REG_PORTF_POL)                    /* PORTF Port x GPIO Polarity Invert Register */
-#define pREG_PORTF_POL_SET               ((volatile uint32_t *)REG_PORTF_POL_SET)                /* PORTF Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTF_POL_CLR               ((volatile uint32_t *)REG_PORTF_POL_CLR)                /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTF_LOCK                  ((volatile uint32_t *)REG_PORTF_LOCK)                   /* PORTF Port x GPIO Lock Register */
-#define pREG_PORTF_REVID                 ((volatile uint32_t *)REG_PORTF_REVID)                  /* PORTF Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTG
-   ========================================================================= */
-#define pREG_PORTG_FER                   ((volatile uint32_t *)REG_PORTG_FER)                    /* PORTG Port x Function Enable Register */
-#define pREG_PORTG_FER_SET               ((volatile uint32_t *)REG_PORTG_FER_SET)                /* PORTG Port x Function Enable Set Register */
-#define pREG_PORTG_FER_CLR               ((volatile uint32_t *)REG_PORTG_FER_CLR)                /* PORTG Port x Function Enable Clear Register */
-#define pREG_PORTG_DATA                  ((volatile uint32_t *)REG_PORTG_DATA)                   /* PORTG Port x GPIO Data Register */
-#define pREG_PORTG_DATA_SET              ((volatile uint32_t *)REG_PORTG_DATA_SET)               /* PORTG Port x GPIO Data Set Register */
-#define pREG_PORTG_DATA_CLR              ((volatile uint32_t *)REG_PORTG_DATA_CLR)               /* PORTG Port x GPIO Data Clear Register */
-#define pREG_PORTG_DIR                   ((volatile uint32_t *)REG_PORTG_DIR)                    /* PORTG Port x GPIO Direction Register */
-#define pREG_PORTG_DIR_SET               ((volatile uint32_t *)REG_PORTG_DIR_SET)                /* PORTG Port x GPIO Direction Set Register */
-#define pREG_PORTG_DIR_CLR               ((volatile uint32_t *)REG_PORTG_DIR_CLR)                /* PORTG Port x GPIO Direction Clear Register */
-#define pREG_PORTG_INEN                  ((volatile uint32_t *)REG_PORTG_INEN)                   /* PORTG Port x GPIO Input Enable Register */
-#define pREG_PORTG_INEN_SET              ((volatile uint32_t *)REG_PORTG_INEN_SET)               /* PORTG Port x GPIO Input Enable Set Register */
-#define pREG_PORTG_INEN_CLR              ((volatile uint32_t *)REG_PORTG_INEN_CLR)               /* PORTG Port x GPIO Input Enable Clear Register */
-#define pREG_PORTG_MUX                   ((volatile uint32_t *)REG_PORTG_MUX)                    /* PORTG Port x Multiplexer Control Register */
-#define pREG_PORTG_DATA_TGL              ((volatile uint32_t *)REG_PORTG_DATA_TGL)               /* PORTG Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTG_POL                   ((volatile uint32_t *)REG_PORTG_POL)                    /* PORTG Port x GPIO Polarity Invert Register */
-#define pREG_PORTG_POL_SET               ((volatile uint32_t *)REG_PORTG_POL_SET)                /* PORTG Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTG_POL_CLR               ((volatile uint32_t *)REG_PORTG_POL_CLR)                /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTG_LOCK                  ((volatile uint32_t *)REG_PORTG_LOCK)                   /* PORTG Port x GPIO Lock Register */
-#define pREG_PORTG_REVID                 ((volatile uint32_t *)REG_PORTG_REVID)                  /* PORTG Port x GPIO Revision ID */
-
-
-/* =========================================================================
-       PADS0
-   ========================================================================= */
-#define pREG_PADS0_EMAC_PTP_CLKSEL       ((volatile uint32_t *)REG_PADS0_EMAC_PTP_CLKSEL)        /* PADS0 Clock Selection for EMAC and PTP */
-#define pREG_PADS0_TWI_VSEL              ((volatile uint32_t *)REG_PADS0_TWI_VSEL)               /* PADS0 TWI Voltage Selection */
-#define pREG_PADS0_PORTS_HYST            ((volatile uint32_t *)REG_PADS0_PORTS_HYST)             /* PADS0 Hysteresis Enable Register */
-
-
-/* =========================================================================
-       PINT0
-   ========================================================================= */
-#define pREG_PINT0_MSK_SET               ((volatile uint32_t *)REG_PINT0_MSK_SET)                /* PINT0 Pint Mask Set Register */
-#define pREG_PINT0_MSK_CLR               ((volatile uint32_t *)REG_PINT0_MSK_CLR)                /* PINT0 Pint Mask Clear Register */
-#define pREG_PINT0_REQ                   ((volatile uint32_t *)REG_PINT0_REQ)                    /* PINT0 Pint Request Register */
-#define pREG_PINT0_ASSIGN                ((volatile uint32_t *)REG_PINT0_ASSIGN)                 /* PINT0 Pint Assign Register */
-#define pREG_PINT0_EDGE_SET              ((volatile uint32_t *)REG_PINT0_EDGE_SET)               /* PINT0 Pint Edge Set Register */
-#define pREG_PINT0_EDGE_CLR              ((volatile uint32_t *)REG_PINT0_EDGE_CLR)               /* PINT0 Pint Edge Clear Register */
-#define pREG_PINT0_INV_SET               ((volatile uint32_t *)REG_PINT0_INV_SET)                /* PINT0 Pint Invert Set Register */
-#define pREG_PINT0_INV_CLR               ((volatile uint32_t *)REG_PINT0_INV_CLR)                /* PINT0 Pint Invert Clear Register */
-#define pREG_PINT0_PINSTATE              ((volatile uint32_t *)REG_PINT0_PINSTATE)               /* PINT0 Pint Pinstate Register */
-#define pREG_PINT0_LATCH                 ((volatile uint32_t *)REG_PINT0_LATCH)                  /* PINT0 Pint Latch Register */
-
-/* =========================================================================
-       PINT1
-   ========================================================================= */
-#define pREG_PINT1_MSK_SET               ((volatile uint32_t *)REG_PINT1_MSK_SET)                /* PINT1 Pint Mask Set Register */
-#define pREG_PINT1_MSK_CLR               ((volatile uint32_t *)REG_PINT1_MSK_CLR)                /* PINT1 Pint Mask Clear Register */
-#define pREG_PINT1_REQ                   ((volatile uint32_t *)REG_PINT1_REQ)                    /* PINT1 Pint Request Register */
-#define pREG_PINT1_ASSIGN                ((volatile uint32_t *)REG_PINT1_ASSIGN)                 /* PINT1 Pint Assign Register */
-#define pREG_PINT1_EDGE_SET              ((volatile uint32_t *)REG_PINT1_EDGE_SET)               /* PINT1 Pint Edge Set Register */
-#define pREG_PINT1_EDGE_CLR              ((volatile uint32_t *)REG_PINT1_EDGE_CLR)               /* PINT1 Pint Edge Clear Register */
-#define pREG_PINT1_INV_SET               ((volatile uint32_t *)REG_PINT1_INV_SET)                /* PINT1 Pint Invert Set Register */
-#define pREG_PINT1_INV_CLR               ((volatile uint32_t *)REG_PINT1_INV_CLR)                /* PINT1 Pint Invert Clear Register */
-#define pREG_PINT1_PINSTATE              ((volatile uint32_t *)REG_PINT1_PINSTATE)               /* PINT1 Pint Pinstate Register */
-#define pREG_PINT1_LATCH                 ((volatile uint32_t *)REG_PINT1_LATCH)                  /* PINT1 Pint Latch Register */
-
-/* =========================================================================
-       PINT2
-   ========================================================================= */
-#define pREG_PINT2_MSK_SET               ((volatile uint32_t *)REG_PINT2_MSK_SET)                /* PINT2 Pint Mask Set Register */
-#define pREG_PINT2_MSK_CLR               ((volatile uint32_t *)REG_PINT2_MSK_CLR)                /* PINT2 Pint Mask Clear Register */
-#define pREG_PINT2_REQ                   ((volatile uint32_t *)REG_PINT2_REQ)                    /* PINT2 Pint Request Register */
-#define pREG_PINT2_ASSIGN                ((volatile uint32_t *)REG_PINT2_ASSIGN)                 /* PINT2 Pint Assign Register */
-#define pREG_PINT2_EDGE_SET              ((volatile uint32_t *)REG_PINT2_EDGE_SET)               /* PINT2 Pint Edge Set Register */
-#define pREG_PINT2_EDGE_CLR              ((volatile uint32_t *)REG_PINT2_EDGE_CLR)               /* PINT2 Pint Edge Clear Register */
-#define pREG_PINT2_INV_SET               ((volatile uint32_t *)REG_PINT2_INV_SET)                /* PINT2 Pint Invert Set Register */
-#define pREG_PINT2_INV_CLR               ((volatile uint32_t *)REG_PINT2_INV_CLR)                /* PINT2 Pint Invert Clear Register */
-#define pREG_PINT2_PINSTATE              ((volatile uint32_t *)REG_PINT2_PINSTATE)               /* PINT2 Pint Pinstate Register */
-#define pREG_PINT2_LATCH                 ((volatile uint32_t *)REG_PINT2_LATCH)                  /* PINT2 Pint Latch Register */
-
-/* =========================================================================
-       PINT3
-   ========================================================================= */
-#define pREG_PINT3_MSK_SET               ((volatile uint32_t *)REG_PINT3_MSK_SET)                /* PINT3 Pint Mask Set Register */
-#define pREG_PINT3_MSK_CLR               ((volatile uint32_t *)REG_PINT3_MSK_CLR)                /* PINT3 Pint Mask Clear Register */
-#define pREG_PINT3_REQ                   ((volatile uint32_t *)REG_PINT3_REQ)                    /* PINT3 Pint Request Register */
-#define pREG_PINT3_ASSIGN                ((volatile uint32_t *)REG_PINT3_ASSIGN)                 /* PINT3 Pint Assign Register */
-#define pREG_PINT3_EDGE_SET              ((volatile uint32_t *)REG_PINT3_EDGE_SET)               /* PINT3 Pint Edge Set Register */
-#define pREG_PINT3_EDGE_CLR              ((volatile uint32_t *)REG_PINT3_EDGE_CLR)               /* PINT3 Pint Edge Clear Register */
-#define pREG_PINT3_INV_SET               ((volatile uint32_t *)REG_PINT3_INV_SET)                /* PINT3 Pint Invert Set Register */
-#define pREG_PINT3_INV_CLR               ((volatile uint32_t *)REG_PINT3_INV_CLR)                /* PINT3 Pint Invert Clear Register */
-#define pREG_PINT3_PINSTATE              ((volatile uint32_t *)REG_PINT3_PINSTATE)               /* PINT3 Pint Pinstate Register */
-#define pREG_PINT3_LATCH                 ((volatile uint32_t *)REG_PINT3_LATCH)                  /* PINT3 Pint Latch Register */
-
-/* =========================================================================
-       PINT4
-   ========================================================================= */
-#define pREG_PINT4_MSK_SET               ((volatile uint32_t *)REG_PINT4_MSK_SET)                /* PINT4 Pint Mask Set Register */
-#define pREG_PINT4_MSK_CLR               ((volatile uint32_t *)REG_PINT4_MSK_CLR)                /* PINT4 Pint Mask Clear Register */
-#define pREG_PINT4_REQ                   ((volatile uint32_t *)REG_PINT4_REQ)                    /* PINT4 Pint Request Register */
-#define pREG_PINT4_ASSIGN                ((volatile uint32_t *)REG_PINT4_ASSIGN)                 /* PINT4 Pint Assign Register */
-#define pREG_PINT4_EDGE_SET              ((volatile uint32_t *)REG_PINT4_EDGE_SET)               /* PINT4 Pint Edge Set Register */
-#define pREG_PINT4_EDGE_CLR              ((volatile uint32_t *)REG_PINT4_EDGE_CLR)               /* PINT4 Pint Edge Clear Register */
-#define pREG_PINT4_INV_SET               ((volatile uint32_t *)REG_PINT4_INV_SET)                /* PINT4 Pint Invert Set Register */
-#define pREG_PINT4_INV_CLR               ((volatile uint32_t *)REG_PINT4_INV_CLR)                /* PINT4 Pint Invert Clear Register */
-#define pREG_PINT4_PINSTATE              ((volatile uint32_t *)REG_PINT4_PINSTATE)               /* PINT4 Pint Pinstate Register */
-#define pREG_PINT4_LATCH                 ((volatile uint32_t *)REG_PINT4_LATCH)                  /* PINT4 Pint Latch Register */
-
-/* =========================================================================
-       PINT5
-   ========================================================================= */
-#define pREG_PINT5_MSK_SET               ((volatile uint32_t *)REG_PINT5_MSK_SET)                /* PINT5 Pint Mask Set Register */
-#define pREG_PINT5_MSK_CLR               ((volatile uint32_t *)REG_PINT5_MSK_CLR)                /* PINT5 Pint Mask Clear Register */
-#define pREG_PINT5_REQ                   ((volatile uint32_t *)REG_PINT5_REQ)                    /* PINT5 Pint Request Register */
-#define pREG_PINT5_ASSIGN                ((volatile uint32_t *)REG_PINT5_ASSIGN)                 /* PINT5 Pint Assign Register */
-#define pREG_PINT5_EDGE_SET              ((volatile uint32_t *)REG_PINT5_EDGE_SET)               /* PINT5 Pint Edge Set Register */
-#define pREG_PINT5_EDGE_CLR              ((volatile uint32_t *)REG_PINT5_EDGE_CLR)               /* PINT5 Pint Edge Clear Register */
-#define pREG_PINT5_INV_SET               ((volatile uint32_t *)REG_PINT5_INV_SET)                /* PINT5 Pint Invert Set Register */
-#define pREG_PINT5_INV_CLR               ((volatile uint32_t *)REG_PINT5_INV_CLR)                /* PINT5 Pint Invert Clear Register */
-#define pREG_PINT5_PINSTATE              ((volatile uint32_t *)REG_PINT5_PINSTATE)               /* PINT5 Pint Pinstate Register */
-#define pREG_PINT5_LATCH                 ((volatile uint32_t *)REG_PINT5_LATCH)                  /* PINT5 Pint Latch Register */
-
-
-/* =========================================================================
-       SMC0
-   ========================================================================= */
-#define pREG_SMC0_GCTL                   ((volatile uint32_t *)REG_SMC0_GCTL)                    /* SMC0 Grant Control Register */
-#define pREG_SMC0_GSTAT                  ((volatile uint32_t *)REG_SMC0_GSTAT)                   /* SMC0 Grant Status Register */
-#define pREG_SMC0_B0CTL                  ((volatile uint32_t *)REG_SMC0_B0CTL)                   /* SMC0 Bank 0 Control Register */
-#define pREG_SMC0_B0TIM                  ((volatile uint32_t *)REG_SMC0_B0TIM)                   /* SMC0 Bank 0 Timing Register */
-#define pREG_SMC0_B0ETIM                 ((volatile uint32_t *)REG_SMC0_B0ETIM)                  /* SMC0 Bank 0 Extended Timing Register */
-#define pREG_SMC0_B1CTL                  ((volatile uint32_t *)REG_SMC0_B1CTL)                   /* SMC0 Bank 1 Control Register */
-#define pREG_SMC0_B1TIM                  ((volatile uint32_t *)REG_SMC0_B1TIM)                   /* SMC0 Bank 1 Timing Register */
-#define pREG_SMC0_B1ETIM                 ((volatile uint32_t *)REG_SMC0_B1ETIM)                  /* SMC0 Bank 1 Extended Timing Register */
-#define pREG_SMC0_B2CTL                  ((volatile uint32_t *)REG_SMC0_B2CTL)                   /* SMC0 Bank 2 Control Register */
-#define pREG_SMC0_B2TIM                  ((volatile uint32_t *)REG_SMC0_B2TIM)                   /* SMC0 Bank 2 Timing Register */
-#define pREG_SMC0_B2ETIM                 ((volatile uint32_t *)REG_SMC0_B2ETIM)                  /* SMC0 Bank 2 Extended Timing Register */
-#define pREG_SMC0_B3CTL                  ((volatile uint32_t *)REG_SMC0_B3CTL)                   /* SMC0 Bank 3 Control Register */
-#define pREG_SMC0_B3TIM                  ((volatile uint32_t *)REG_SMC0_B3TIM)                   /* SMC0 Bank 3 Timing Register */
-#define pREG_SMC0_B3ETIM                 ((volatile uint32_t *)REG_SMC0_B3ETIM)                  /* SMC0 Bank 3 Extended Timing Register */
-
-
-/* =========================================================================
-       WDOG0
-   ========================================================================= */
-#define pREG_WDOG0_CTL                   ((volatile uint32_t *)REG_WDOG0_CTL)                    /* WDOG0 Control Register */
-#define pREG_WDOG0_CNT                   ((volatile uint32_t *)REG_WDOG0_CNT)                    /* WDOG0 Count Register */
-#define pREG_WDOG0_STAT                  ((volatile uint32_t *)REG_WDOG0_STAT)                   /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================================================================
-       WDOG1
-   ========================================================================= */
-#define pREG_WDOG1_CTL                   ((volatile uint32_t *)REG_WDOG1_CTL)                    /* WDOG1 Control Register */
-#define pREG_WDOG1_CNT                   ((volatile uint32_t *)REG_WDOG1_CNT)                    /* WDOG1 Count Register */
-#define pREG_WDOG1_STAT                  ((volatile uint32_t *)REG_WDOG1_STAT)                   /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================================================================
-       EPPI0
-   ========================================================================= */
-#define pREG_EPPI0_STAT                  ((volatile uint32_t *)REG_EPPI0_STAT)                   /* EPPI0 Status Register */
-#define pREG_EPPI0_HCNT                  ((volatile uint32_t *)REG_EPPI0_HCNT)                   /* EPPI0 Horizontal Transfer Count Register */
-#define pREG_EPPI0_HDLY                  ((volatile uint32_t *)REG_EPPI0_HDLY)                   /* EPPI0 Horizontal Delay Count Register */
-#define pREG_EPPI0_VCNT                  ((volatile uint32_t *)REG_EPPI0_VCNT)                   /* EPPI0 Vertical Transfer Count Register */
-#define pREG_EPPI0_VDLY                  ((volatile uint32_t *)REG_EPPI0_VDLY)                   /* EPPI0 Vertical Delay Count Register */
-#define pREG_EPPI0_FRAME                 ((volatile uint32_t *)REG_EPPI0_FRAME)                  /* EPPI0 Lines Per Frame Register */
-#define pREG_EPPI0_LINE                  ((volatile uint32_t *)REG_EPPI0_LINE)                   /* EPPI0 Samples Per Line Register */
-#define pREG_EPPI0_CLKDIV                ((volatile uint32_t *)REG_EPPI0_CLKDIV)                 /* EPPI0 Clock Divide Register */
-#define pREG_EPPI0_CTL                   ((volatile uint32_t *)REG_EPPI0_CTL)                    /* EPPI0 Control Register */
-#define pREG_EPPI0_FS1_WLHB              ((volatile uint32_t *)REG_EPPI0_FS1_WLHB)               /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI0_FS1_PASPL             ((volatile uint32_t *)REG_EPPI0_FS1_PASPL)              /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI0_FS2_WLVB              ((volatile uint32_t *)REG_EPPI0_FS2_WLVB)               /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI0_FS2_PALPF             ((volatile uint32_t *)REG_EPPI0_FS2_PALPF)              /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI0_IMSK                  ((volatile uint32_t *)REG_EPPI0_IMSK)                   /* EPPI0 Interrupt Mask Register */
-#define pREG_EPPI0_ODDCLIP               ((volatile uint32_t *)REG_EPPI0_ODDCLIP)                /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI0_EVENCLIP              ((volatile uint32_t *)REG_EPPI0_EVENCLIP)               /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI0_FS1_DLY               ((volatile uint32_t *)REG_EPPI0_FS1_DLY)                /* EPPI0 Frame Sync 1 Delay Value */
-#define pREG_EPPI0_FS2_DLY               ((volatile uint32_t *)REG_EPPI0_FS2_DLY)                /* EPPI0 Frame Sync 2 Delay Value */
-#define pREG_EPPI0_CTL2                  ((volatile uint32_t *)REG_EPPI0_CTL2)                   /* EPPI0 Control Register 2 */
-
-/* =========================================================================
-       EPPI1
-   ========================================================================= */
-#define pREG_EPPI1_STAT                  ((volatile uint32_t *)REG_EPPI1_STAT)                   /* EPPI1 Status Register */
-#define pREG_EPPI1_HCNT                  ((volatile uint32_t *)REG_EPPI1_HCNT)                   /* EPPI1 Horizontal Transfer Count Register */
-#define pREG_EPPI1_HDLY                  ((volatile uint32_t *)REG_EPPI1_HDLY)                   /* EPPI1 Horizontal Delay Count Register */
-#define pREG_EPPI1_VCNT                  ((volatile uint32_t *)REG_EPPI1_VCNT)                   /* EPPI1 Vertical Transfer Count Register */
-#define pREG_EPPI1_VDLY                  ((volatile uint32_t *)REG_EPPI1_VDLY)                   /* EPPI1 Vertical Delay Count Register */
-#define pREG_EPPI1_FRAME                 ((volatile uint32_t *)REG_EPPI1_FRAME)                  /* EPPI1 Lines Per Frame Register */
-#define pREG_EPPI1_LINE                  ((volatile uint32_t *)REG_EPPI1_LINE)                   /* EPPI1 Samples Per Line Register */
-#define pREG_EPPI1_CLKDIV                ((volatile uint32_t *)REG_EPPI1_CLKDIV)                 /* EPPI1 Clock Divide Register */
-#define pREG_EPPI1_CTL                   ((volatile uint32_t *)REG_EPPI1_CTL)                    /* EPPI1 Control Register */
-#define pREG_EPPI1_FS1_WLHB              ((volatile uint32_t *)REG_EPPI1_FS1_WLHB)               /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI1_FS1_PASPL             ((volatile uint32_t *)REG_EPPI1_FS1_PASPL)              /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI1_FS2_WLVB              ((volatile uint32_t *)REG_EPPI1_FS2_WLVB)               /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI1_FS2_PALPF             ((volatile uint32_t *)REG_EPPI1_FS2_PALPF)              /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI1_IMSK                  ((volatile uint32_t *)REG_EPPI1_IMSK)                   /* EPPI1 Interrupt Mask Register */
-#define pREG_EPPI1_ODDCLIP               ((volatile uint32_t *)REG_EPPI1_ODDCLIP)                /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI1_EVENCLIP              ((volatile uint32_t *)REG_EPPI1_EVENCLIP)               /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI1_FS1_DLY               ((volatile uint32_t *)REG_EPPI1_FS1_DLY)                /* EPPI1 Frame Sync 1 Delay Value */
-#define pREG_EPPI1_FS2_DLY               ((volatile uint32_t *)REG_EPPI1_FS2_DLY)                /* EPPI1 Frame Sync 2 Delay Value */
-#define pREG_EPPI1_CTL2                  ((volatile uint32_t *)REG_EPPI1_CTL2)                   /* EPPI1 Control Register 2 */
-
-/* =========================================================================
-       EPPI2
-   ========================================================================= */
-#define pREG_EPPI2_STAT                  ((volatile uint32_t *)REG_EPPI2_STAT)                   /* EPPI2 Status Register */
-#define pREG_EPPI2_HCNT                  ((volatile uint32_t *)REG_EPPI2_HCNT)                   /* EPPI2 Horizontal Transfer Count Register */
-#define pREG_EPPI2_HDLY                  ((volatile uint32_t *)REG_EPPI2_HDLY)                   /* EPPI2 Horizontal Delay Count Register */
-#define pREG_EPPI2_VCNT                  ((volatile uint32_t *)REG_EPPI2_VCNT)                   /* EPPI2 Vertical Transfer Count Register */
-#define pREG_EPPI2_VDLY                  ((volatile uint32_t *)REG_EPPI2_VDLY)                   /* EPPI2 Vertical Delay Count Register */
-#define pREG_EPPI2_FRAME                 ((volatile uint32_t *)REG_EPPI2_FRAME)                  /* EPPI2 Lines Per Frame Register */
-#define pREG_EPPI2_LINE                  ((volatile uint32_t *)REG_EPPI2_LINE)                   /* EPPI2 Samples Per Line Register */
-#define pREG_EPPI2_CLKDIV                ((volatile uint32_t *)REG_EPPI2_CLKDIV)                 /* EPPI2 Clock Divide Register */
-#define pREG_EPPI2_CTL                   ((volatile uint32_t *)REG_EPPI2_CTL)                    /* EPPI2 Control Register */
-#define pREG_EPPI2_FS1_WLHB              ((volatile uint32_t *)REG_EPPI2_FS1_WLHB)               /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI2_FS1_PASPL             ((volatile uint32_t *)REG_EPPI2_FS1_PASPL)              /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI2_FS2_WLVB              ((volatile uint32_t *)REG_EPPI2_FS2_WLVB)               /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI2_FS2_PALPF             ((volatile uint32_t *)REG_EPPI2_FS2_PALPF)              /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI2_IMSK                  ((volatile uint32_t *)REG_EPPI2_IMSK)                   /* EPPI2 Interrupt Mask Register */
-#define pREG_EPPI2_ODDCLIP               ((volatile uint32_t *)REG_EPPI2_ODDCLIP)                /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI2_EVENCLIP              ((volatile uint32_t *)REG_EPPI2_EVENCLIP)               /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI2_FS1_DLY               ((volatile uint32_t *)REG_EPPI2_FS1_DLY)                /* EPPI2 Frame Sync 1 Delay Value */
-#define pREG_EPPI2_FS2_DLY               ((volatile uint32_t *)REG_EPPI2_FS2_DLY)                /* EPPI2 Frame Sync 2 Delay Value */
-#define pREG_EPPI2_CTL2                  ((volatile uint32_t *)REG_EPPI2_CTL2)                   /* EPPI2 Control Register 2 */
-
-
-/* =========================================================================
-       PWM0
-   ========================================================================= */
-#define pREG_PWM0_CTL                    ((volatile uint32_t *)REG_PWM0_CTL)                     /* PWM0 Control Register */
-#define pREG_PWM0_CHANCFG                ((volatile uint32_t *)REG_PWM0_CHANCFG)                 /* PWM0 Channel Config Register */
-#define pREG_PWM0_TRIPCFG                ((volatile uint32_t *)REG_PWM0_TRIPCFG)                 /* PWM0 Trip Config Register */
-#define pREG_PWM0_STAT                   ((volatile uint32_t *)REG_PWM0_STAT)                    /* PWM0 Status Register */
-#define pREG_PWM0_IMSK                   ((volatile uint32_t *)REG_PWM0_IMSK)                    /* PWM0 Interrupt Mask Register */
-#define pREG_PWM0_ILAT                   ((volatile uint32_t *)REG_PWM0_ILAT)                    /* PWM0 Interrupt Latch Register */
-#define pREG_PWM0_CHOPCFG                ((volatile uint32_t *)REG_PWM0_CHOPCFG)                 /* PWM0 Chop Configuration Register */
-#define pREG_PWM0_DT                     ((volatile uint32_t *)REG_PWM0_DT)                      /* PWM0 Dead Time Register */
-#define pREG_PWM0_SYNC_WID               ((volatile uint32_t *)REG_PWM0_SYNC_WID)                /* PWM0 Sync Pulse Width Register */
-#define pREG_PWM0_TM0                    ((volatile uint32_t *)REG_PWM0_TM0)                     /* PWM0 Timer 0 Period Register */
-#define pREG_PWM0_TM1                    ((volatile uint32_t *)REG_PWM0_TM1)                     /* PWM0 Timer 1 Period Register */
-#define pREG_PWM0_TM2                    ((volatile uint32_t *)REG_PWM0_TM2)                     /* PWM0 Timer 2 Period Register */
-#define pREG_PWM0_TM3                    ((volatile uint32_t *)REG_PWM0_TM3)                     /* PWM0 Timer 3 Period Register */
-#define pREG_PWM0_TM4                    ((volatile uint32_t *)REG_PWM0_TM4)                     /* PWM0 Timer 4 Period Register */
-#define pREG_PWM0_DLYA                   ((volatile uint32_t *)REG_PWM0_DLYA)                    /* PWM0 Channel A Delay Register */
-#define pREG_PWM0_DLYB                   ((volatile uint32_t *)REG_PWM0_DLYB)                    /* PWM0 Channel B Delay Register */
-#define pREG_PWM0_DLYC                   ((volatile uint32_t *)REG_PWM0_DLYC)                    /* PWM0 Channel C Delay Register */
-#define pREG_PWM0_DLYD                   ((volatile uint32_t *)REG_PWM0_DLYD)                    /* PWM0 Channel D Delay Register */
-#define pREG_PWM0_ACTL                   ((volatile uint32_t *)REG_PWM0_ACTL)                    /* PWM0 Channel A Control Register */
-#define pREG_PWM0_AH0                    ((volatile uint32_t *)REG_PWM0_AH0)                     /* PWM0 Channel A-High Duty-0 Register */
-#define pREG_PWM0_AH1                    ((volatile uint32_t *)REG_PWM0_AH1)                     /* PWM0 Channel A-High Duty-1 Register */
-#define pREG_PWM0_AL0                    ((volatile uint32_t *)REG_PWM0_AL0)                     /* PWM0 Channel A-Low Duty-0 Register */
-#define pREG_PWM0_AL1                    ((volatile uint32_t *)REG_PWM0_AL1)                     /* PWM0 Channel A-Low Duty-1 Register */
-#define pREG_PWM0_BCTL                   ((volatile uint32_t *)REG_PWM0_BCTL)                    /* PWM0 Channel B Control Register */
-#define pREG_PWM0_BH0                    ((volatile uint32_t *)REG_PWM0_BH0)                     /* PWM0 Channel B-High Duty-0 Register */
-#define pREG_PWM0_BH1                    ((volatile uint32_t *)REG_PWM0_BH1)                     /* PWM0 Channel B-High Duty-1 Register */
-#define pREG_PWM0_BL0                    ((volatile uint32_t *)REG_PWM0_BL0)                     /* PWM0 Channel B-Low Duty-0 Register */
-#define pREG_PWM0_BL1                    ((volatile uint32_t *)REG_PWM0_BL1)                     /* PWM0 Channel B-Low Duty-1 Register */
-#define pREG_PWM0_CCTL                   ((volatile uint32_t *)REG_PWM0_CCTL)                    /* PWM0 Channel C Control Register */
-#define pREG_PWM0_CH0                    ((volatile uint32_t *)REG_PWM0_CH0)                     /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM0_CH1                    ((volatile uint32_t *)REG_PWM0_CH1)                     /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM0_CL0                    ((volatile uint32_t *)REG_PWM0_CL0)                     /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM0_CL1                    ((volatile uint32_t *)REG_PWM0_CL1)                     /* PWM0 Channel C-Low Duty-1 Register */
-#define pREG_PWM0_DCTL                   ((volatile uint32_t *)REG_PWM0_DCTL)                    /* PWM0 Channel D Control Register */
-#define pREG_PWM0_DH0                    ((volatile uint32_t *)REG_PWM0_DH0)                     /* PWM0 Channel D-High Duty-0 Register */
-#define pREG_PWM0_DH1                    ((volatile uint32_t *)REG_PWM0_DH1)                     /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM0_DL0                    ((volatile uint32_t *)REG_PWM0_DL0)                     /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM0_DL1                    ((volatile uint32_t *)REG_PWM0_DL1)                     /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================================================================
-       PWM1
-   ========================================================================= */
-#define pREG_PWM1_CTL                    ((volatile uint32_t *)REG_PWM1_CTL)                     /* PWM1 Control Register */
-#define pREG_PWM1_CHANCFG                ((volatile uint32_t *)REG_PWM1_CHANCFG)                 /* PWM1 Channel Config Register */
-#define pREG_PWM1_TRIPCFG                ((volatile uint32_t *)REG_PWM1_TRIPCFG)                 /* PWM1 Trip Config Register */
-#define pREG_PWM1_STAT                   ((volatile uint32_t *)REG_PWM1_STAT)                    /* PWM1 Status Register */
-#define pREG_PWM1_IMSK                   ((volatile uint32_t *)REG_PWM1_IMSK)                    /* PWM1 Interrupt Mask Register */
-#define pREG_PWM1_ILAT                   ((volatile uint32_t *)REG_PWM1_ILAT)                    /* PWM1 Interrupt Latch Register */
-#define pREG_PWM1_CHOPCFG                ((volatile uint32_t *)REG_PWM1_CHOPCFG)                 /* PWM1 Chop Configuration Register */
-#define pREG_PWM1_DT                     ((volatile uint32_t *)REG_PWM1_DT)                      /* PWM1 Dead Time Register */
-#define pREG_PWM1_SYNC_WID               ((volatile uint32_t *)REG_PWM1_SYNC_WID)                /* PWM1 Sync Pulse Width Register */
-#define pREG_PWM1_TM0                    ((volatile uint32_t *)REG_PWM1_TM0)                     /* PWM1 Timer 0 Period Register */
-#define pREG_PWM1_TM1                    ((volatile uint32_t *)REG_PWM1_TM1)                     /* PWM1 Timer 1 Period Register */
-#define pREG_PWM1_TM2                    ((volatile uint32_t *)REG_PWM1_TM2)                     /* PWM1 Timer 2 Period Register */
-#define pREG_PWM1_TM3                    ((volatile uint32_t *)REG_PWM1_TM3)                     /* PWM1 Timer 3 Period Register */
-#define pREG_PWM1_TM4                    ((volatile uint32_t *)REG_PWM1_TM4)                     /* PWM1 Timer 4 Period Register */
-#define pREG_PWM1_DLYA                   ((volatile uint32_t *)REG_PWM1_DLYA)                    /* PWM1 Channel A Delay Register */
-#define pREG_PWM1_DLYB                   ((volatile uint32_t *)REG_PWM1_DLYB)                    /* PWM1 Channel B Delay Register */
-#define pREG_PWM1_DLYC                   ((volatile uint32_t *)REG_PWM1_DLYC)                    /* PWM1 Channel C Delay Register */
-#define pREG_PWM1_DLYD                   ((volatile uint32_t *)REG_PWM1_DLYD)                    /* PWM1 Channel D Delay Register */
-#define pREG_PWM1_ACTL                   ((volatile uint32_t *)REG_PWM1_ACTL)                    /* PWM1 Channel A Control Register */
-#define pREG_PWM1_AH0                    ((volatile uint32_t *)REG_PWM1_AH0)                     /* PWM1 Channel A-High Duty-0 Register */
-#define pREG_PWM1_AH1                    ((volatile uint32_t *)REG_PWM1_AH1)                     /* PWM1 Channel A-High Duty-1 Register */
-#define pREG_PWM1_AL0                    ((volatile uint32_t *)REG_PWM1_AL0)                     /* PWM1 Channel A-Low Duty-0 Register */
-#define pREG_PWM1_AL1                    ((volatile uint32_t *)REG_PWM1_AL1)                     /* PWM1 Channel A-Low Duty-1 Register */
-#define pREG_PWM1_BCTL                   ((volatile uint32_t *)REG_PWM1_BCTL)                    /* PWM1 Channel B Control Register */
-#define pREG_PWM1_BH0                    ((volatile uint32_t *)REG_PWM1_BH0)                     /* PWM1 Channel B-High Duty-0 Register */
-#define pREG_PWM1_BH1                    ((volatile uint32_t *)REG_PWM1_BH1)                     /* PWM1 Channel B-High Duty-1 Register */
-#define pREG_PWM1_BL0                    ((volatile uint32_t *)REG_PWM1_BL0)                     /* PWM1 Channel B-Low Duty-0 Register */
-#define pREG_PWM1_BL1                    ((volatile uint32_t *)REG_PWM1_BL1)                     /* PWM1 Channel B-Low Duty-1 Register */
-#define pREG_PWM1_CCTL                   ((volatile uint32_t *)REG_PWM1_CCTL)                    /* PWM1 Channel C Control Register */
-#define pREG_PWM1_CH0                    ((volatile uint32_t *)REG_PWM1_CH0)                     /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM1_CH1                    ((volatile uint32_t *)REG_PWM1_CH1)                     /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM1_CL0                    ((volatile uint32_t *)REG_PWM1_CL0)                     /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM1_CL1                    ((volatile uint32_t *)REG_PWM1_CL1)                     /* PWM1 Channel C-Low Duty-1 Register */
-#define pREG_PWM1_DCTL                   ((volatile uint32_t *)REG_PWM1_DCTL)                    /* PWM1 Channel D Control Register */
-#define pREG_PWM1_DH0                    ((volatile uint32_t *)REG_PWM1_DH0)                     /* PWM1 Channel D-High Duty-0 Register */
-#define pREG_PWM1_DH1                    ((volatile uint32_t *)REG_PWM1_DH1)                     /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM1_DL0                    ((volatile uint32_t *)REG_PWM1_DL0)                     /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM1_DL1                    ((volatile uint32_t *)REG_PWM1_DL1)                     /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-
-/* =========================================================================
-       VID0
-   ========================================================================= */
-#define pREG_VID0_CONN                   ((volatile uint32_t *)REG_VID0_CONN)                    /* VID0 Video Subsystem Connect Register */
-
-
-/* =========================================================================
-       SWU0
-   ========================================================================= */
-#define pREG_SWU0_GCTL                   ((volatile uint32_t *)REG_SWU0_GCTL)                    /* SWU0 Global Control Register */
-#define pREG_SWU0_GSTAT                  ((volatile uint32_t *)REG_SWU0_GSTAT)                   /* SWU0 Global Status Register */
-#define pREG_SWU0_CTL0                   ((volatile uint32_t *)REG_SWU0_CTL0)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL1                   ((volatile uint32_t *)REG_SWU0_CTL1)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL2                   ((volatile uint32_t *)REG_SWU0_CTL2)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL3                   ((volatile uint32_t *)REG_SWU0_CTL3)                    /* SWU0 Control Register n */
-#define pREG_SWU0_LA0                    ((void * volatile *)REG_SWU0_LA0)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA1                    ((void * volatile *)REG_SWU0_LA1)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA2                    ((void * volatile *)REG_SWU0_LA2)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA3                    ((void * volatile *)REG_SWU0_LA3)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_UA0                    ((void * volatile *)REG_SWU0_UA0)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA1                    ((void * volatile *)REG_SWU0_UA1)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA2                    ((void * volatile *)REG_SWU0_UA2)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA3                    ((void * volatile *)REG_SWU0_UA3)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_ID0                    ((volatile uint32_t *)REG_SWU0_ID0)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID1                    ((volatile uint32_t *)REG_SWU0_ID1)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID2                    ((volatile uint32_t *)REG_SWU0_ID2)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID3                    ((volatile uint32_t *)REG_SWU0_ID3)                     /* SWU0 ID Register n */
-#define pREG_SWU0_CNT0                   ((volatile uint32_t *)REG_SWU0_CNT0)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT1                   ((volatile uint32_t *)REG_SWU0_CNT1)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT2                   ((volatile uint32_t *)REG_SWU0_CNT2)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT3                   ((volatile uint32_t *)REG_SWU0_CNT3)                    /* SWU0 Count Register n */
-#define pREG_SWU0_TARG0                  ((volatile uint32_t *)REG_SWU0_TARG0)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG1                  ((volatile uint32_t *)REG_SWU0_TARG1)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG2                  ((volatile uint32_t *)REG_SWU0_TARG2)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG3                  ((volatile uint32_t *)REG_SWU0_TARG3)                   /* SWU0 Target Register n */
-#define pREG_SWU0_HIST0                  ((volatile uint32_t *)REG_SWU0_HIST0)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST1                  ((volatile uint32_t *)REG_SWU0_HIST1)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST2                  ((volatile uint32_t *)REG_SWU0_HIST2)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST3                  ((volatile uint32_t *)REG_SWU0_HIST3)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_CUR0                   ((volatile uint32_t *)REG_SWU0_CUR0)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR1                   ((volatile uint32_t *)REG_SWU0_CUR1)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR2                   ((volatile uint32_t *)REG_SWU0_CUR2)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR3                   ((volatile uint32_t *)REG_SWU0_CUR3)                    /* SWU0 Current Register n */
-
-/* =========================================================================
-       SWU1
-   ========================================================================= */
-#define pREG_SWU1_GCTL                   ((volatile uint32_t *)REG_SWU1_GCTL)                    /* SWU1 Global Control Register */
-#define pREG_SWU1_GSTAT                  ((volatile uint32_t *)REG_SWU1_GSTAT)                   /* SWU1 Global Status Register */
-#define pREG_SWU1_CTL0                   ((volatile uint32_t *)REG_SWU1_CTL0)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL1                   ((volatile uint32_t *)REG_SWU1_CTL1)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL2                   ((volatile uint32_t *)REG_SWU1_CTL2)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL3                   ((volatile uint32_t *)REG_SWU1_CTL3)                    /* SWU1 Control Register n */
-#define pREG_SWU1_LA0                    ((void * volatile *)REG_SWU1_LA0)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA1                    ((void * volatile *)REG_SWU1_LA1)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA2                    ((void * volatile *)REG_SWU1_LA2)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA3                    ((void * volatile *)REG_SWU1_LA3)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_UA0                    ((void * volatile *)REG_SWU1_UA0)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA1                    ((void * volatile *)REG_SWU1_UA1)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA2                    ((void * volatile *)REG_SWU1_UA2)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA3                    ((void * volatile *)REG_SWU1_UA3)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_ID0                    ((volatile uint32_t *)REG_SWU1_ID0)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID1                    ((volatile uint32_t *)REG_SWU1_ID1)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID2                    ((volatile uint32_t *)REG_SWU1_ID2)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID3                    ((volatile uint32_t *)REG_SWU1_ID3)                     /* SWU1 ID Register n */
-#define pREG_SWU1_CNT0                   ((volatile uint32_t *)REG_SWU1_CNT0)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT1                   ((volatile uint32_t *)REG_SWU1_CNT1)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT2                   ((volatile uint32_t *)REG_SWU1_CNT2)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT3                   ((volatile uint32_t *)REG_SWU1_CNT3)                    /* SWU1 Count Register n */
-#define pREG_SWU1_TARG0                  ((volatile uint32_t *)REG_SWU1_TARG0)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG1                  ((volatile uint32_t *)REG_SWU1_TARG1)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG2                  ((volatile uint32_t *)REG_SWU1_TARG2)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG3                  ((volatile uint32_t *)REG_SWU1_TARG3)                   /* SWU1 Target Register n */
-#define pREG_SWU1_HIST0                  ((volatile uint32_t *)REG_SWU1_HIST0)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST1                  ((volatile uint32_t *)REG_SWU1_HIST1)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST2                  ((volatile uint32_t *)REG_SWU1_HIST2)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST3                  ((volatile uint32_t *)REG_SWU1_HIST3)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_CUR0                   ((volatile uint32_t *)REG_SWU1_CUR0)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR1                   ((volatile uint32_t *)REG_SWU1_CUR1)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR2                   ((volatile uint32_t *)REG_SWU1_CUR2)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR3                   ((volatile uint32_t *)REG_SWU1_CUR3)                    /* SWU1 Current Register n */
-
-/* =========================================================================
-       SWU2
-   ========================================================================= */
-#define pREG_SWU2_GCTL                   ((volatile uint32_t *)REG_SWU2_GCTL)                    /* SWU2 Global Control Register */
-#define pREG_SWU2_GSTAT                  ((volatile uint32_t *)REG_SWU2_GSTAT)                   /* SWU2 Global Status Register */
-#define pREG_SWU2_CTL0                   ((volatile uint32_t *)REG_SWU2_CTL0)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL1                   ((volatile uint32_t *)REG_SWU2_CTL1)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL2                   ((volatile uint32_t *)REG_SWU2_CTL2)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL3                   ((volatile uint32_t *)REG_SWU2_CTL3)                    /* SWU2 Control Register n */
-#define pREG_SWU2_LA0                    ((void * volatile *)REG_SWU2_LA0)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA1                    ((void * volatile *)REG_SWU2_LA1)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA2                    ((void * volatile *)REG_SWU2_LA2)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA3                    ((void * volatile *)REG_SWU2_LA3)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_UA0                    ((void * volatile *)REG_SWU2_UA0)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA1                    ((void * volatile *)REG_SWU2_UA1)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA2                    ((void * volatile *)REG_SWU2_UA2)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA3                    ((void * volatile *)REG_SWU2_UA3)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_ID0                    ((volatile uint32_t *)REG_SWU2_ID0)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID1                    ((volatile uint32_t *)REG_SWU2_ID1)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID2                    ((volatile uint32_t *)REG_SWU2_ID2)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID3                    ((volatile uint32_t *)REG_SWU2_ID3)                     /* SWU2 ID Register n */
-#define pREG_SWU2_CNT0                   ((volatile uint32_t *)REG_SWU2_CNT0)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT1                   ((volatile uint32_t *)REG_SWU2_CNT1)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT2                   ((volatile uint32_t *)REG_SWU2_CNT2)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT3                   ((volatile uint32_t *)REG_SWU2_CNT3)                    /* SWU2 Count Register n */
-#define pREG_SWU2_TARG0                  ((volatile uint32_t *)REG_SWU2_TARG0)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG1                  ((volatile uint32_t *)REG_SWU2_TARG1)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG2                  ((volatile uint32_t *)REG_SWU2_TARG2)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG3                  ((volatile uint32_t *)REG_SWU2_TARG3)                   /* SWU2 Target Register n */
-#define pREG_SWU2_HIST0                  ((volatile uint32_t *)REG_SWU2_HIST0)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST1                  ((volatile uint32_t *)REG_SWU2_HIST1)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST2                  ((volatile uint32_t *)REG_SWU2_HIST2)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST3                  ((volatile uint32_t *)REG_SWU2_HIST3)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_CUR0                   ((volatile uint32_t *)REG_SWU2_CUR0)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR1                   ((volatile uint32_t *)REG_SWU2_CUR1)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR2                   ((volatile uint32_t *)REG_SWU2_CUR2)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR3                   ((volatile uint32_t *)REG_SWU2_CUR3)                    /* SWU2 Current Register n */
-
-/* =========================================================================
-       SWU3
-   ========================================================================= */
-#define pREG_SWU3_GCTL                   ((volatile uint32_t *)REG_SWU3_GCTL)                    /* SWU3 Global Control Register */
-#define pREG_SWU3_GSTAT                  ((volatile uint32_t *)REG_SWU3_GSTAT)                   /* SWU3 Global Status Register */
-#define pREG_SWU3_CTL0                   ((volatile uint32_t *)REG_SWU3_CTL0)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL1                   ((volatile uint32_t *)REG_SWU3_CTL1)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL2                   ((volatile uint32_t *)REG_SWU3_CTL2)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL3                   ((volatile uint32_t *)REG_SWU3_CTL3)                    /* SWU3 Control Register n */
-#define pREG_SWU3_LA0                    ((void * volatile *)REG_SWU3_LA0)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA1                    ((void * volatile *)REG_SWU3_LA1)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA2                    ((void * volatile *)REG_SWU3_LA2)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA3                    ((void * volatile *)REG_SWU3_LA3)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_UA0                    ((void * volatile *)REG_SWU3_UA0)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA1                    ((void * volatile *)REG_SWU3_UA1)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA2                    ((void * volatile *)REG_SWU3_UA2)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA3                    ((void * volatile *)REG_SWU3_UA3)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_ID0                    ((volatile uint32_t *)REG_SWU3_ID0)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID1                    ((volatile uint32_t *)REG_SWU3_ID1)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID2                    ((volatile uint32_t *)REG_SWU3_ID2)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID3                    ((volatile uint32_t *)REG_SWU3_ID3)                     /* SWU3 ID Register n */
-#define pREG_SWU3_CNT0                   ((volatile uint32_t *)REG_SWU3_CNT0)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT1                   ((volatile uint32_t *)REG_SWU3_CNT1)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT2                   ((volatile uint32_t *)REG_SWU3_CNT2)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT3                   ((volatile uint32_t *)REG_SWU3_CNT3)                    /* SWU3 Count Register n */
-#define pREG_SWU3_TARG0                  ((volatile uint32_t *)REG_SWU3_TARG0)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG1                  ((volatile uint32_t *)REG_SWU3_TARG1)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG2                  ((volatile uint32_t *)REG_SWU3_TARG2)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG3                  ((volatile uint32_t *)REG_SWU3_TARG3)                   /* SWU3 Target Register n */
-#define pREG_SWU3_HIST0                  ((volatile uint32_t *)REG_SWU3_HIST0)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST1                  ((volatile uint32_t *)REG_SWU3_HIST1)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST2                  ((volatile uint32_t *)REG_SWU3_HIST2)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST3                  ((volatile uint32_t *)REG_SWU3_HIST3)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_CUR0                   ((volatile uint32_t *)REG_SWU3_CUR0)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR1                   ((volatile uint32_t *)REG_SWU3_CUR1)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR2                   ((volatile uint32_t *)REG_SWU3_CUR2)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR3                   ((volatile uint32_t *)REG_SWU3_CUR3)                    /* SWU3 Current Register n */
-
-/* =========================================================================
-       SWU4
-   ========================================================================= */
-#define pREG_SWU4_GCTL                   ((volatile uint32_t *)REG_SWU4_GCTL)                    /* SWU4 Global Control Register */
-#define pREG_SWU4_GSTAT                  ((volatile uint32_t *)REG_SWU4_GSTAT)                   /* SWU4 Global Status Register */
-#define pREG_SWU4_CTL0                   ((volatile uint32_t *)REG_SWU4_CTL0)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL1                   ((volatile uint32_t *)REG_SWU4_CTL1)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL2                   ((volatile uint32_t *)REG_SWU4_CTL2)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL3                   ((volatile uint32_t *)REG_SWU4_CTL3)                    /* SWU4 Control Register n */
-#define pREG_SWU4_LA0                    ((void * volatile *)REG_SWU4_LA0)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA1                    ((void * volatile *)REG_SWU4_LA1)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA2                    ((void * volatile *)REG_SWU4_LA2)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA3                    ((void * volatile *)REG_SWU4_LA3)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_UA0                    ((void * volatile *)REG_SWU4_UA0)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA1                    ((void * volatile *)REG_SWU4_UA1)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA2                    ((void * volatile *)REG_SWU4_UA2)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA3                    ((void * volatile *)REG_SWU4_UA3)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_ID0                    ((volatile uint32_t *)REG_SWU4_ID0)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID1                    ((volatile uint32_t *)REG_SWU4_ID1)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID2                    ((volatile uint32_t *)REG_SWU4_ID2)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID3                    ((volatile uint32_t *)REG_SWU4_ID3)                     /* SWU4 ID Register n */
-#define pREG_SWU4_CNT0                   ((volatile uint32_t *)REG_SWU4_CNT0)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT1                   ((volatile uint32_t *)REG_SWU4_CNT1)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT2                   ((volatile uint32_t *)REG_SWU4_CNT2)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT3                   ((volatile uint32_t *)REG_SWU4_CNT3)                    /* SWU4 Count Register n */
-#define pREG_SWU4_TARG0                  ((volatile uint32_t *)REG_SWU4_TARG0)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG1                  ((volatile uint32_t *)REG_SWU4_TARG1)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG2                  ((volatile uint32_t *)REG_SWU4_TARG2)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG3                  ((volatile uint32_t *)REG_SWU4_TARG3)                   /* SWU4 Target Register n */
-#define pREG_SWU4_HIST0                  ((volatile uint32_t *)REG_SWU4_HIST0)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST1                  ((volatile uint32_t *)REG_SWU4_HIST1)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST2                  ((volatile uint32_t *)REG_SWU4_HIST2)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST3                  ((volatile uint32_t *)REG_SWU4_HIST3)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_CUR0                   ((volatile uint32_t *)REG_SWU4_CUR0)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR1                   ((volatile uint32_t *)REG_SWU4_CUR1)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR2                   ((volatile uint32_t *)REG_SWU4_CUR2)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR3                   ((volatile uint32_t *)REG_SWU4_CUR3)                    /* SWU4 Current Register n */
-
-/* =========================================================================
-       SWU5
-   ========================================================================= */
-#define pREG_SWU5_GCTL                   ((volatile uint32_t *)REG_SWU5_GCTL)                    /* SWU5 Global Control Register */
-#define pREG_SWU5_GSTAT                  ((volatile uint32_t *)REG_SWU5_GSTAT)                   /* SWU5 Global Status Register */
-#define pREG_SWU5_CTL0                   ((volatile uint32_t *)REG_SWU5_CTL0)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL1                   ((volatile uint32_t *)REG_SWU5_CTL1)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL2                   ((volatile uint32_t *)REG_SWU5_CTL2)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL3                   ((volatile uint32_t *)REG_SWU5_CTL3)                    /* SWU5 Control Register n */
-#define pREG_SWU5_LA0                    ((void * volatile *)REG_SWU5_LA0)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA1                    ((void * volatile *)REG_SWU5_LA1)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA2                    ((void * volatile *)REG_SWU5_LA2)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA3                    ((void * volatile *)REG_SWU5_LA3)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_UA0                    ((void * volatile *)REG_SWU5_UA0)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA1                    ((void * volatile *)REG_SWU5_UA1)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA2                    ((void * volatile *)REG_SWU5_UA2)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA3                    ((void * volatile *)REG_SWU5_UA3)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_ID0                    ((volatile uint32_t *)REG_SWU5_ID0)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID1                    ((volatile uint32_t *)REG_SWU5_ID1)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID2                    ((volatile uint32_t *)REG_SWU5_ID2)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID3                    ((volatile uint32_t *)REG_SWU5_ID3)                     /* SWU5 ID Register n */
-#define pREG_SWU5_CNT0                   ((volatile uint32_t *)REG_SWU5_CNT0)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT1                   ((volatile uint32_t *)REG_SWU5_CNT1)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT2                   ((volatile uint32_t *)REG_SWU5_CNT2)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT3                   ((volatile uint32_t *)REG_SWU5_CNT3)                    /* SWU5 Count Register n */
-#define pREG_SWU5_TARG0                  ((volatile uint32_t *)REG_SWU5_TARG0)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG1                  ((volatile uint32_t *)REG_SWU5_TARG1)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG2                  ((volatile uint32_t *)REG_SWU5_TARG2)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG3                  ((volatile uint32_t *)REG_SWU5_TARG3)                   /* SWU5 Target Register n */
-#define pREG_SWU5_HIST0                  ((volatile uint32_t *)REG_SWU5_HIST0)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST1                  ((volatile uint32_t *)REG_SWU5_HIST1)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST2                  ((volatile uint32_t *)REG_SWU5_HIST2)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST3                  ((volatile uint32_t *)REG_SWU5_HIST3)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_CUR0                   ((volatile uint32_t *)REG_SWU5_CUR0)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR1                   ((volatile uint32_t *)REG_SWU5_CUR1)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR2                   ((volatile uint32_t *)REG_SWU5_CUR2)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR3                   ((volatile uint32_t *)REG_SWU5_CUR3)                    /* SWU5 Current Register n */
-
-/* =========================================================================
-       SWU6
-   ========================================================================= */
-#define pREG_SWU6_GCTL                   ((volatile uint32_t *)REG_SWU6_GCTL)                    /* SWU6 Global Control Register */
-#define pREG_SWU6_GSTAT                  ((volatile uint32_t *)REG_SWU6_GSTAT)                   /* SWU6 Global Status Register */
-#define pREG_SWU6_CTL0                   ((volatile uint32_t *)REG_SWU6_CTL0)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL1                   ((volatile uint32_t *)REG_SWU6_CTL1)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL2                   ((volatile uint32_t *)REG_SWU6_CTL2)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL3                   ((volatile uint32_t *)REG_SWU6_CTL3)                    /* SWU6 Control Register n */
-#define pREG_SWU6_LA0                    ((void * volatile *)REG_SWU6_LA0)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA1                    ((void * volatile *)REG_SWU6_LA1)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA2                    ((void * volatile *)REG_SWU6_LA2)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA3                    ((void * volatile *)REG_SWU6_LA3)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_UA0                    ((void * volatile *)REG_SWU6_UA0)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA1                    ((void * volatile *)REG_SWU6_UA1)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA2                    ((void * volatile *)REG_SWU6_UA2)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA3                    ((void * volatile *)REG_SWU6_UA3)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_ID0                    ((volatile uint32_t *)REG_SWU6_ID0)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID1                    ((volatile uint32_t *)REG_SWU6_ID1)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID2                    ((volatile uint32_t *)REG_SWU6_ID2)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID3                    ((volatile uint32_t *)REG_SWU6_ID3)                     /* SWU6 ID Register n */
-#define pREG_SWU6_CNT0                   ((volatile uint32_t *)REG_SWU6_CNT0)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT1                   ((volatile uint32_t *)REG_SWU6_CNT1)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT2                   ((volatile uint32_t *)REG_SWU6_CNT2)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT3                   ((volatile uint32_t *)REG_SWU6_CNT3)                    /* SWU6 Count Register n */
-#define pREG_SWU6_TARG0                  ((volatile uint32_t *)REG_SWU6_TARG0)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG1                  ((volatile uint32_t *)REG_SWU6_TARG1)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG2                  ((volatile uint32_t *)REG_SWU6_TARG2)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG3                  ((volatile uint32_t *)REG_SWU6_TARG3)                   /* SWU6 Target Register n */
-#define pREG_SWU6_HIST0                  ((volatile uint32_t *)REG_SWU6_HIST0)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST1                  ((volatile uint32_t *)REG_SWU6_HIST1)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST2                  ((volatile uint32_t *)REG_SWU6_HIST2)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST3                  ((volatile uint32_t *)REG_SWU6_HIST3)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_CUR0                   ((volatile uint32_t *)REG_SWU6_CUR0)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR1                   ((volatile uint32_t *)REG_SWU6_CUR1)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR2                   ((volatile uint32_t *)REG_SWU6_CUR2)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR3                   ((volatile uint32_t *)REG_SWU6_CUR3)                    /* SWU6 Current Register n */
-
-
-/* =========================================================================
-       SDU0
-   ========================================================================= */
-#define pREG_SDU0_IDCODE                 ((volatile uint32_t *)REG_SDU0_IDCODE)                  /* SDU0 ID Code Register */
-#define pREG_SDU0_CTL                    ((volatile uint32_t *)REG_SDU0_CTL)                     /* SDU0 Control Register */
-#define pREG_SDU0_STAT                   ((volatile uint32_t *)REG_SDU0_STAT)                    /* SDU0 Status Register */
-#define pREG_SDU0_MACCTL                 ((volatile uint32_t *)REG_SDU0_MACCTL)                  /* SDU0 Memory Access Control Register */
-#define pREG_SDU0_MACADDR                ((void * volatile *)REG_SDU0_MACADDR)                   /* SDU0 Memory Access Address Register */
-#define pREG_SDU0_MACDATA                ((volatile uint32_t *)REG_SDU0_MACDATA)                 /* SDU0 Memory Access Data Register */
-#define pREG_SDU0_DMARD                  ((volatile uint32_t *)REG_SDU0_DMARD)                   /* SDU0 DMA Read Data Register */
-#define pREG_SDU0_DMAWD                  ((volatile uint32_t *)REG_SDU0_DMAWD)                   /* SDU0 DMA Write Data Register */
-#define pREG_SDU0_MSG                    ((volatile uint32_t *)REG_SDU0_MSG)                     /* SDU0 Message Register */
-#define pREG_SDU0_MSG_SET                ((volatile uint32_t *)REG_SDU0_MSG_SET)                 /* SDU0 Message Set Register */
-#define pREG_SDU0_MSG_CLR                ((volatile uint32_t *)REG_SDU0_MSG_CLR)                 /* SDU0 Message Clear Register */
-#define pREG_SDU0_GHLT                   ((volatile uint32_t *)REG_SDU0_GHLT)                    /* SDU0 Group Halt Register */
-
-
-/* =========================================================================
-       EMAC0
-   ========================================================================= */
-#define pREG_EMAC0_MACCFG                ((volatile uint32_t *)REG_EMAC0_MACCFG)                 /* EMAC0 MAC Configuration Register */
-#define pREG_EMAC0_MACFRMFILT            ((volatile uint32_t *)REG_EMAC0_MACFRMFILT)             /* EMAC0 MAC Rx Frame Filter Register */
-#define pREG_EMAC0_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC0_HASHTBL_HI)             /* EMAC0 Hash Table High Register */
-#define pREG_EMAC0_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC0_HASHTBL_LO)             /* EMAC0 Hash Table Low Register */
-#define pREG_EMAC0_SMI_ADDR              ((volatile uint32_t *)REG_EMAC0_SMI_ADDR)               /* EMAC0 SMI Address Register */
-#define pREG_EMAC0_SMI_DATA              ((volatile uint32_t *)REG_EMAC0_SMI_DATA)               /* EMAC0 SMI Data Register */
-#define pREG_EMAC0_FLOWCTL               ((volatile uint32_t *)REG_EMAC0_FLOWCTL)                /* EMAC0 FLow Control Register */
-#define pREG_EMAC0_VLANTAG               ((volatile uint32_t *)REG_EMAC0_VLANTAG)                /* EMAC0 VLAN Tag Register */
-#define pREG_EMAC0_DBG                   ((volatile uint32_t *)REG_EMAC0_DBG)                    /* EMAC0 Debug Register */
-#define pREG_EMAC0_ISTAT                 ((volatile uint32_t *)REG_EMAC0_ISTAT)                  /* EMAC0 Interrupt Status Register */
-#define pREG_EMAC0_IMSK                  ((volatile uint32_t *)REG_EMAC0_IMSK)                   /* EMAC0 Interrupt Mask Register */
-#define pREG_EMAC0_ADDR0_HI              ((volatile uint32_t *)REG_EMAC0_ADDR0_HI)               /* EMAC0 MAC Address 0 High Register */
-#define pREG_EMAC0_ADDR0_LO              ((volatile uint32_t *)REG_EMAC0_ADDR0_LO)               /* EMAC0 MAC Address 0 Low Register */
-#define pREG_EMAC0_MMC_CTL               ((volatile uint32_t *)REG_EMAC0_MMC_CTL)                /* EMAC0 MMC Control Register */
-#define pREG_EMAC0_MMC_RXINT             ((volatile uint32_t *)REG_EMAC0_MMC_RXINT)              /* EMAC0 MMC Rx Interrupt Register */
-#define pREG_EMAC0_MMC_TXINT             ((volatile uint32_t *)REG_EMAC0_MMC_TXINT)              /* EMAC0 MMC Tx Interrupt Register */
-#define pREG_EMAC0_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_RXIMSK)             /* EMAC0 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC0_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_TXIMSK)             /* EMAC0 MMC TX Interrupt Mask Register */
-#define pREG_EMAC0_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_GB)            /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC0_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_GB)            /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_G)           /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_G)           /* EMAC0 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC0_TX64_GB               ((volatile uint32_t *)REG_EMAC0_TX64_GB)                /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_TX65TO127_GB)           /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_TX128TO255_GB)          /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_TX256TO511_GB)          /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_TX512TO1023_GB)         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_TX1024TOMAX_GB)         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXUCASTFRM_GB)          /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_GB)          /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_GB)          /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC0_TXUNDR_ERR)             /* EMAC0 Tx Underflow Error Register */
-#define pREG_EMAC0_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC0_TXSNGCOL_G)             /* EMAC0 Tx Single Collision (Good) Register */
-#define pREG_EMAC0_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC0_TXMULTCOL_G)            /* EMAC0 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC0_TXDEFERRED            ((volatile uint32_t *)REG_EMAC0_TXDEFERRED)             /* EMAC0 Tx Deferred Register */
-#define pREG_EMAC0_TXLATECOL             ((volatile uint32_t *)REG_EMAC0_TXLATECOL)              /* EMAC0 Tx Late Collision Register */
-#define pREG_EMAC0_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC0_TXEXCESSCOL)            /* EMAC0 Tx Excess Collision Register */
-#define pREG_EMAC0_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC0_TXCARR_ERR)             /* EMAC0 Tx Carrier Error Register */
-#define pREG_EMAC0_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_G)             /* EMAC0 Tx Octet Count (Good) Register */
-#define pREG_EMAC0_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_G)             /* EMAC0 Tx Frame Count (Good) Register */
-#define pREG_EMAC0_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC0_TXEXCESSDEF)            /* EMAC0 Tx Excess Deferral Register */
-#define pREG_EMAC0_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_TXPAUSEFRM)             /* EMAC0 Tx Pause Frame Register */
-#define pREG_EMAC0_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC0_TXVLANFRM_G)            /* EMAC0 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC0_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXFRMCNT_GB)            /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_GB)            /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_G)             /* EMAC0 Rx Octet Count (Good) Register */
-#define pREG_EMAC0_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXBCASTFRM_G)           /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXMCASTFRM_G)           /* EMAC0 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC0_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC0_RXCRC_ERR)              /* EMAC0 Rx CRC Error Register */
-#define pREG_EMAC0_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC0_RXALIGN_ERR)            /* EMAC0 Rx alignment Error Register */
-#define pREG_EMAC0_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC0_RXRUNT_ERR)             /* EMAC0 Rx Runt Error Register */
-#define pREG_EMAC0_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC0_RXJAB_ERR)              /* EMAC0 Rx Jab Error Register */
-#define pREG_EMAC0_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXUSIZE_G)              /* EMAC0 Rx Undersize (Good) Register */
-#define pREG_EMAC0_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXOSIZE_G)              /* EMAC0 Rx Oversize (Good) Register */
-#define pREG_EMAC0_RX64_GB               ((volatile uint32_t *)REG_EMAC0_RX64_GB)                /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_RX65TO127_GB)           /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_RX128TO255_GB)          /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_RX256TO511_GB)          /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_RX512TO1023_GB)         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_RX1024TOMAX_GB)         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXUCASTFRM_G)           /* EMAC0 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC0_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC0_RXLEN_ERR)              /* EMAC0 Rx Length Error Register */
-#define pREG_EMAC0_RXOORTYPE             ((volatile uint32_t *)REG_EMAC0_RXOORTYPE)              /* EMAC0 Rx Out Of Range Type Register */
-#define pREG_EMAC0_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_RXPAUSEFRM)             /* EMAC0 Rx Pause Frames Register */
-#define pREG_EMAC0_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC0_RXFIFO_OVF)             /* EMAC0 Rx FIFO Overflow Register */
-#define pREG_EMAC0_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC0_RXVLANFRM_GB)           /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC0_RXWDOG_ERR)             /* EMAC0 Rx Watch Dog Error Register */
-#define pREG_EMAC0_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_IPC_RXIMSK)             /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC0_IPC_RXINT             ((volatile uint32_t *)REG_EMAC0_IPC_RXINT)              /* EMAC0 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC0_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_FRM)          /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_FRM)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_FRM)       /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC0_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_FRM)        /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_FRM)       /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC0_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_FRM)          /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_FRM)     /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_FRM)       /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC0_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_FRM)           /* EMAC0 Rx UDP Good Frames Register */
-#define pREG_EMAC0_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_FRM)          /* EMAC0 Rx UDP Error Frames Register */
-#define pREG_EMAC0_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_FRM)           /* EMAC0 Rx TCP Good Frames Register */
-#define pREG_EMAC0_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_FRM)          /* EMAC0 Rx TCP Error Frames Register */
-#define pREG_EMAC0_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_FRM)          /* EMAC0 Rx ICMP Good Frames Register */
-#define pREG_EMAC0_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_FRM)         /* EMAC0 Rx ICMP Error Frames Register */
-#define pREG_EMAC0_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_OCT)          /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_OCT)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_OCT)       /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC0_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_OCT)        /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_OCT)       /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC0_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_OCT)          /* EMAC0 Rx IPv6 Good Octets Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_OCT)     /* EMAC0 Rx IPv6 Header Errors Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_OCT)       /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC0_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_OCT)           /* EMAC0 Rx UDP Good Octets Register */
-#define pREG_EMAC0_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_OCT)          /* EMAC0 Rx UDP Error Octets Register */
-#define pREG_EMAC0_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_OCT)           /* EMAC0 Rx TCP Good Octets Register */
-#define pREG_EMAC0_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_OCT)          /* EMAC0 Rx TCP Error Octets Register */
-#define pREG_EMAC0_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_OCT)          /* EMAC0 Rx ICMP Good Octets Register */
-#define pREG_EMAC0_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_OCT)         /* EMAC0 Rx ICMP Error Octets Register */
-#define pREG_EMAC0_TM_CTL                ((volatile uint32_t *)REG_EMAC0_TM_CTL)                 /* EMAC0 Time Stamp Control Register */
-#define pREG_EMAC0_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC0_TM_SUBSEC)              /* EMAC0 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC0_TM_SEC                ((volatile uint32_t *)REG_EMAC0_TM_SEC)                 /* EMAC0 Time Stamp Low Seconds Register */
-#define pREG_EMAC0_TM_NSEC               ((volatile uint32_t *)REG_EMAC0_TM_NSEC)                /* EMAC0 Time Stamp Nano Seconds Register */
-#define pREG_EMAC0_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC0_TM_SECUPDT)             /* EMAC0 Time Stamp Seconds Update Register */
-#define pREG_EMAC0_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC0_TM_NSECUPDT)            /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC0_TM_ADDEND             ((volatile uint32_t *)REG_EMAC0_TM_ADDEND)              /* EMAC0 Time Stamp Addend Register */
-#define pREG_EMAC0_TM_TGTM               ((volatile uint32_t *)REG_EMAC0_TM_TGTM)                /* EMAC0 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC0_TM_NTGTM              ((volatile uint32_t *)REG_EMAC0_TM_NTGTM)               /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC0_TM_HISEC              ((volatile uint32_t *)REG_EMAC0_TM_HISEC)               /* EMAC0 Time Stamp High Second Register */
-#define pREG_EMAC0_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC0_TM_STMPSTAT)            /* EMAC0 Time Stamp Status Register */
-#define pREG_EMAC0_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC0_TM_PPSCTL)              /* EMAC0 PPS Control Register */
-#define pREG_EMAC0_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_NSEC)        /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC0_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_SEC)         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC0_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC0_TM_PPSINTVL)            /* EMAC0 Time Stamp PPS Interval Register */
-#define pREG_EMAC0_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC0_TM_PPSWIDTH)            /* EMAC0 PPS Width Register */
-#define pREG_EMAC0_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC0_DMA_BUSMODE)            /* EMAC0 DMA Bus Mode Register */
-#define pREG_EMAC0_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_TXPOLL)             /* EMAC0 DMA Tx Poll Demand Register */
-#define pREG_EMAC0_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_RXPOLL)             /* EMAC0 DMA Rx Poll Demand register */
-#define pREG_EMAC0_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_ADDR)         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_ADDR)         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_STAT              ((volatile uint32_t *)REG_EMAC0_DMA_STAT)               /* EMAC0 DMA Status Register */
-#define pREG_EMAC0_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC0_DMA_OPMODE)             /* EMAC0 DMA Operation Mode Register */
-#define pREG_EMAC0_DMA_IEN               ((volatile uint32_t *)REG_EMAC0_DMA_IEN)                /* EMAC0 DMA Interrupt Enable Register */
-#define pREG_EMAC0_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC0_DMA_MISS_FRM)           /* EMAC0 DMA Missed Frame Register */
-#define pREG_EMAC0_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC0_DMA_RXIWDOG)            /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC0_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC0_DMA_BMMODE)             /* EMAC0 DMA SCB Bus Mode Register */
-#define pREG_EMAC0_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC0_DMA_BMSTAT)             /* EMAC0 DMA SCB Status Register */
-#define pREG_EMAC0_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_CUR)          /* EMAC0 DMA Tx Descriptor Current Register */
-#define pREG_EMAC0_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_CUR)          /* EMAC0 DMA Rx Descriptor Current Register */
-#define pREG_EMAC0_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXBUF_CUR)          /* EMAC0 DMA Tx Buffer Current Register */
-#define pREG_EMAC0_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXBUF_CUR)          /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================================================================
-       EMAC1
-   ========================================================================= */
-#define pREG_EMAC1_MACCFG                ((volatile uint32_t *)REG_EMAC1_MACCFG)                 /* EMAC1 MAC Configuration Register */
-#define pREG_EMAC1_MACFRMFILT            ((volatile uint32_t *)REG_EMAC1_MACFRMFILT)             /* EMAC1 MAC Rx Frame Filter Register */
-#define pREG_EMAC1_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC1_HASHTBL_HI)             /* EMAC1 Hash Table High Register */
-#define pREG_EMAC1_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC1_HASHTBL_LO)             /* EMAC1 Hash Table Low Register */
-#define pREG_EMAC1_SMI_ADDR              ((volatile uint32_t *)REG_EMAC1_SMI_ADDR)               /* EMAC1 SMI Address Register */
-#define pREG_EMAC1_SMI_DATA              ((volatile uint32_t *)REG_EMAC1_SMI_DATA)               /* EMAC1 SMI Data Register */
-#define pREG_EMAC1_FLOWCTL               ((volatile uint32_t *)REG_EMAC1_FLOWCTL)                /* EMAC1 FLow Control Register */
-#define pREG_EMAC1_VLANTAG               ((volatile uint32_t *)REG_EMAC1_VLANTAG)                /* EMAC1 VLAN Tag Register */
-#define pREG_EMAC1_DBG                   ((volatile uint32_t *)REG_EMAC1_DBG)                    /* EMAC1 Debug Register */
-#define pREG_EMAC1_ISTAT                 ((volatile uint32_t *)REG_EMAC1_ISTAT)                  /* EMAC1 Interrupt Status Register */
-#define pREG_EMAC1_IMSK                  ((volatile uint32_t *)REG_EMAC1_IMSK)                   /* EMAC1 Interrupt Mask Register */
-#define pREG_EMAC1_ADDR0_HI              ((volatile uint32_t *)REG_EMAC1_ADDR0_HI)               /* EMAC1 MAC Address 0 High Register */
-#define pREG_EMAC1_ADDR0_LO              ((volatile uint32_t *)REG_EMAC1_ADDR0_LO)               /* EMAC1 MAC Address 0 Low Register */
-#define pREG_EMAC1_MMC_CTL               ((volatile uint32_t *)REG_EMAC1_MMC_CTL)                /* EMAC1 MMC Control Register */
-#define pREG_EMAC1_MMC_RXINT             ((volatile uint32_t *)REG_EMAC1_MMC_RXINT)              /* EMAC1 MMC Rx Interrupt Register */
-#define pREG_EMAC1_MMC_TXINT             ((volatile uint32_t *)REG_EMAC1_MMC_TXINT)              /* EMAC1 MMC Tx Interrupt Register */
-#define pREG_EMAC1_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_RXIMSK)             /* EMAC1 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC1_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_TXIMSK)             /* EMAC1 MMC TX Interrupt Mask Register */
-#define pREG_EMAC1_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_GB)            /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC1_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_GB)            /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_G)           /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_G)           /* EMAC1 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC1_TX64_GB               ((volatile uint32_t *)REG_EMAC1_TX64_GB)                /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_TX65TO127_GB)           /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_TX128TO255_GB)          /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_TX256TO511_GB)          /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_TX512TO1023_GB)         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_TX1024TOMAX_GB)         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXUCASTFRM_GB)          /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_GB)          /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_GB)          /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC1_TXUNDR_ERR)             /* EMAC1 Tx Underflow Error Register */
-#define pREG_EMAC1_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC1_TXSNGCOL_G)             /* EMAC1 Tx Single Collision (Good) Register */
-#define pREG_EMAC1_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC1_TXMULTCOL_G)            /* EMAC1 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC1_TXDEFERRED            ((volatile uint32_t *)REG_EMAC1_TXDEFERRED)             /* EMAC1 Tx Deferred Register */
-#define pREG_EMAC1_TXLATECOL             ((volatile uint32_t *)REG_EMAC1_TXLATECOL)              /* EMAC1 Tx Late Collision Register */
-#define pREG_EMAC1_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC1_TXEXCESSCOL)            /* EMAC1 Tx Excess Collision Register */
-#define pREG_EMAC1_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC1_TXCARR_ERR)             /* EMAC1 Tx Carrier Error Register */
-#define pREG_EMAC1_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_G)             /* EMAC1 Tx Octet Count (Good) Register */
-#define pREG_EMAC1_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_G)             /* EMAC1 Tx Frame Count (Good) Register */
-#define pREG_EMAC1_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC1_TXEXCESSDEF)            /* EMAC1 Tx Excess Deferral Register */
-#define pREG_EMAC1_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_TXPAUSEFRM)             /* EMAC1 Tx Pause Frame Register */
-#define pREG_EMAC1_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC1_TXVLANFRM_G)            /* EMAC1 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC1_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXFRMCNT_GB)            /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_GB)            /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_G)             /* EMAC1 Rx Octet Count (Good) Register */
-#define pREG_EMAC1_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXBCASTFRM_G)           /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXMCASTFRM_G)           /* EMAC1 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC1_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC1_RXCRC_ERR)              /* EMAC1 Rx CRC Error Register */
-#define pREG_EMAC1_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC1_RXALIGN_ERR)            /* EMAC1 Rx alignment Error Register */
-#define pREG_EMAC1_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC1_RXRUNT_ERR)             /* EMAC1 Rx Runt Error Register */
-#define pREG_EMAC1_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC1_RXJAB_ERR)              /* EMAC1 Rx Jab Error Register */
-#define pREG_EMAC1_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXUSIZE_G)              /* EMAC1 Rx Undersize (Good) Register */
-#define pREG_EMAC1_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXOSIZE_G)              /* EMAC1 Rx Oversize (Good) Register */
-#define pREG_EMAC1_RX64_GB               ((volatile uint32_t *)REG_EMAC1_RX64_GB)                /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_RX65TO127_GB)           /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_RX128TO255_GB)          /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_RX256TO511_GB)          /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_RX512TO1023_GB)         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_RX1024TOMAX_GB)         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXUCASTFRM_G)           /* EMAC1 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC1_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC1_RXLEN_ERR)              /* EMAC1 Rx Length Error Register */
-#define pREG_EMAC1_RXOORTYPE             ((volatile uint32_t *)REG_EMAC1_RXOORTYPE)              /* EMAC1 Rx Out Of Range Type Register */
-#define pREG_EMAC1_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_RXPAUSEFRM)             /* EMAC1 Rx Pause Frames Register */
-#define pREG_EMAC1_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC1_RXFIFO_OVF)             /* EMAC1 Rx FIFO Overflow Register */
-#define pREG_EMAC1_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC1_RXVLANFRM_GB)           /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC1_RXWDOG_ERR)             /* EMAC1 Rx Watch Dog Error Register */
-#define pREG_EMAC1_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_IPC_RXIMSK)             /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC1_IPC_RXINT             ((volatile uint32_t *)REG_EMAC1_IPC_RXINT)              /* EMAC1 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC1_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_FRM)          /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_FRM)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_FRM)       /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC1_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_FRM)        /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_FRM)       /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC1_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_FRM)          /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_FRM)     /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_FRM)       /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC1_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_FRM)           /* EMAC1 Rx UDP Good Frames Register */
-#define pREG_EMAC1_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_FRM)          /* EMAC1 Rx UDP Error Frames Register */
-#define pREG_EMAC1_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_FRM)           /* EMAC1 Rx TCP Good Frames Register */
-#define pREG_EMAC1_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_FRM)          /* EMAC1 Rx TCP Error Frames Register */
-#define pREG_EMAC1_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_FRM)          /* EMAC1 Rx ICMP Good Frames Register */
-#define pREG_EMAC1_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_FRM)         /* EMAC1 Rx ICMP Error Frames Register */
-#define pREG_EMAC1_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_OCT)          /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_OCT)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_OCT)       /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC1_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_OCT)        /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_OCT)       /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC1_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_OCT)          /* EMAC1 Rx IPv6 Good Octets Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_OCT)     /* EMAC1 Rx IPv6 Header Errors Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_OCT)       /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC1_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_OCT)           /* EMAC1 Rx UDP Good Octets Register */
-#define pREG_EMAC1_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_OCT)          /* EMAC1 Rx UDP Error Octets Register */
-#define pREG_EMAC1_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_OCT)           /* EMAC1 Rx TCP Good Octets Register */
-#define pREG_EMAC1_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_OCT)          /* EMAC1 Rx TCP Error Octets Register */
-#define pREG_EMAC1_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_OCT)          /* EMAC1 Rx ICMP Good Octets Register */
-#define pREG_EMAC1_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_OCT)         /* EMAC1 Rx ICMP Error Octets Register */
-#define pREG_EMAC1_TM_CTL                ((volatile uint32_t *)REG_EMAC1_TM_CTL)                 /* EMAC1 Time Stamp Control Register */
-#define pREG_EMAC1_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC1_TM_SUBSEC)              /* EMAC1 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC1_TM_SEC                ((volatile uint32_t *)REG_EMAC1_TM_SEC)                 /* EMAC1 Time Stamp Low Seconds Register */
-#define pREG_EMAC1_TM_NSEC               ((volatile uint32_t *)REG_EMAC1_TM_NSEC)                /* EMAC1 Time Stamp Nano Seconds Register */
-#define pREG_EMAC1_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC1_TM_SECUPDT)             /* EMAC1 Time Stamp Seconds Update Register */
-#define pREG_EMAC1_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC1_TM_NSECUPDT)            /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC1_TM_ADDEND             ((volatile uint32_t *)REG_EMAC1_TM_ADDEND)              /* EMAC1 Time Stamp Addend Register */
-#define pREG_EMAC1_TM_TGTM               ((volatile uint32_t *)REG_EMAC1_TM_TGTM)                /* EMAC1 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC1_TM_NTGTM              ((volatile uint32_t *)REG_EMAC1_TM_NTGTM)               /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC1_TM_HISEC              ((volatile uint32_t *)REG_EMAC1_TM_HISEC)               /* EMAC1 Time Stamp High Second Register */
-#define pREG_EMAC1_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC1_TM_STMPSTAT)            /* EMAC1 Time Stamp Status Register */
-#define pREG_EMAC1_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC1_TM_PPSCTL)              /* EMAC1 PPS Control Register */
-#define pREG_EMAC1_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_NSEC)        /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC1_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_SEC)         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC1_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC1_TM_PPSINTVL)            /* EMAC1 Time Stamp PPS Interval Register */
-#define pREG_EMAC1_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC1_TM_PPSWIDTH)            /* EMAC1 PPS Width Register */
-#define pREG_EMAC1_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC1_DMA_BUSMODE)            /* EMAC1 DMA Bus Mode Register */
-#define pREG_EMAC1_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_TXPOLL)             /* EMAC1 DMA Tx Poll Demand Register */
-#define pREG_EMAC1_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_RXPOLL)             /* EMAC1 DMA Rx Poll Demand register */
-#define pREG_EMAC1_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_ADDR)         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_ADDR)         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_STAT              ((volatile uint32_t *)REG_EMAC1_DMA_STAT)               /* EMAC1 DMA Status Register */
-#define pREG_EMAC1_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC1_DMA_OPMODE)             /* EMAC1 DMA Operation Mode Register */
-#define pREG_EMAC1_DMA_IEN               ((volatile uint32_t *)REG_EMAC1_DMA_IEN)                /* EMAC1 DMA Interrupt Enable Register */
-#define pREG_EMAC1_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC1_DMA_MISS_FRM)           /* EMAC1 DMA Missed Frame Register */
-#define pREG_EMAC1_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC1_DMA_RXIWDOG)            /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC1_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC1_DMA_BMMODE)             /* EMAC1 DMA SCB Bus Mode Register */
-#define pREG_EMAC1_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC1_DMA_BMSTAT)             /* EMAC1 DMA SCB Status Register */
-#define pREG_EMAC1_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_CUR)          /* EMAC1 DMA Tx Descriptor Current Register */
-#define pREG_EMAC1_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_CUR)          /* EMAC1 DMA Rx Descriptor Current Register */
-#define pREG_EMAC1_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXBUF_CUR)          /* EMAC1 DMA Tx Buffer Current Register */
-#define pREG_EMAC1_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXBUF_CUR)          /* EMAC1 DMA Rx Buffer Current Register */
-
-
-/* =========================================================================
-       SPORT0
-   ========================================================================= */
-#define pREG_SPORT0_CTL_A                ((volatile uint32_t *)REG_SPORT0_CTL_A)                 /* SPORT0 Half SPORT 'A' Control Register */
-#define pREG_SPORT0_DIV_A                ((volatile uint32_t *)REG_SPORT0_DIV_A)                 /* SPORT0 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT0_MCTL_A               ((volatile uint32_t *)REG_SPORT0_MCTL_A)                /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_A                ((volatile uint32_t *)REG_SPORT0_CS0_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_A                ((volatile uint32_t *)REG_SPORT0_CS1_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_A                ((volatile uint32_t *)REG_SPORT0_CS2_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT0_CS3_A                ((volatile uint32_t *)REG_SPORT0_CS3_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT0_ERR_A                ((volatile uint32_t *)REG_SPORT0_ERR_A)                 /* SPORT0 Half SPORT 'A' Error Register */
-#define pREG_SPORT0_MSTAT_A              ((volatile uint32_t *)REG_SPORT0_MSTAT_A)               /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_A               ((volatile uint32_t *)REG_SPORT0_CTL2_A)                /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT0_TXPRI_A              ((volatile uint32_t *)REG_SPORT0_TXPRI_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_A              ((volatile uint32_t *)REG_SPORT0_RXPRI_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_A              ((volatile uint32_t *)REG_SPORT0_TXSEC_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_A              ((volatile uint32_t *)REG_SPORT0_RXSEC_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT0_CTL_B                ((volatile uint32_t *)REG_SPORT0_CTL_B)                 /* SPORT0 Half SPORT 'B' Control Register */
-#define pREG_SPORT0_DIV_B                ((volatile uint32_t *)REG_SPORT0_DIV_B)                 /* SPORT0 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT0_MCTL_B               ((volatile uint32_t *)REG_SPORT0_MCTL_B)                /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_B                ((volatile uint32_t *)REG_SPORT0_CS0_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_B                ((volatile uint32_t *)REG_SPORT0_CS1_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_B                ((volatile uint32_t *)REG_SPORT0_CS2_B)                 /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT0_CS3_B                ((volatile uint32_t *)REG_SPORT0_CS3_B)                 /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT0_ERR_B                ((volatile uint32_t *)REG_SPORT0_ERR_B)                 /* SPORT0 Half SPORT 'B' Error Register */
-#define pREG_SPORT0_MSTAT_B              ((volatile uint32_t *)REG_SPORT0_MSTAT_B)               /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_B               ((volatile uint32_t *)REG_SPORT0_CTL2_B)                /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT0_TXPRI_B              ((volatile uint32_t *)REG_SPORT0_TXPRI_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_B              ((volatile uint32_t *)REG_SPORT0_RXPRI_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_B              ((volatile uint32_t *)REG_SPORT0_TXSEC_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_B              ((volatile uint32_t *)REG_SPORT0_RXSEC_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT1
-   ========================================================================= */
-#define pREG_SPORT1_CTL_A                ((volatile uint32_t *)REG_SPORT1_CTL_A)                 /* SPORT1 Half SPORT 'A' Control Register */
-#define pREG_SPORT1_DIV_A                ((volatile uint32_t *)REG_SPORT1_DIV_A)                 /* SPORT1 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT1_MCTL_A               ((volatile uint32_t *)REG_SPORT1_MCTL_A)                /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_A                ((volatile uint32_t *)REG_SPORT1_CS0_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_A                ((volatile uint32_t *)REG_SPORT1_CS1_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_A                ((volatile uint32_t *)REG_SPORT1_CS2_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT1_CS3_A                ((volatile uint32_t *)REG_SPORT1_CS3_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT1_ERR_A                ((volatile uint32_t *)REG_SPORT1_ERR_A)                 /* SPORT1 Half SPORT 'A' Error Register */
-#define pREG_SPORT1_MSTAT_A              ((volatile uint32_t *)REG_SPORT1_MSTAT_A)               /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_A               ((volatile uint32_t *)REG_SPORT1_CTL2_A)                /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT1_TXPRI_A              ((volatile uint32_t *)REG_SPORT1_TXPRI_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_A              ((volatile uint32_t *)REG_SPORT1_RXPRI_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_A              ((volatile uint32_t *)REG_SPORT1_TXSEC_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_A              ((volatile uint32_t *)REG_SPORT1_RXSEC_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT1_CTL_B                ((volatile uint32_t *)REG_SPORT1_CTL_B)                 /* SPORT1 Half SPORT 'B' Control Register */
-#define pREG_SPORT1_DIV_B                ((volatile uint32_t *)REG_SPORT1_DIV_B)                 /* SPORT1 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT1_MCTL_B               ((volatile uint32_t *)REG_SPORT1_MCTL_B)                /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_B                ((volatile uint32_t *)REG_SPORT1_CS0_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_B                ((volatile uint32_t *)REG_SPORT1_CS1_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_B                ((volatile uint32_t *)REG_SPORT1_CS2_B)                 /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT1_CS3_B                ((volatile uint32_t *)REG_SPORT1_CS3_B)                 /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT1_ERR_B                ((volatile uint32_t *)REG_SPORT1_ERR_B)                 /* SPORT1 Half SPORT 'B' Error Register */
-#define pREG_SPORT1_MSTAT_B              ((volatile uint32_t *)REG_SPORT1_MSTAT_B)               /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_B               ((volatile uint32_t *)REG_SPORT1_CTL2_B)                /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT1_TXPRI_B              ((volatile uint32_t *)REG_SPORT1_TXPRI_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_B              ((volatile uint32_t *)REG_SPORT1_RXPRI_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_B              ((volatile uint32_t *)REG_SPORT1_TXSEC_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_B              ((volatile uint32_t *)REG_SPORT1_RXSEC_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT2
-   ========================================================================= */
-#define pREG_SPORT2_CTL_A                ((volatile uint32_t *)REG_SPORT2_CTL_A)                 /* SPORT2 Half SPORT 'A' Control Register */
-#define pREG_SPORT2_DIV_A                ((volatile uint32_t *)REG_SPORT2_DIV_A)                 /* SPORT2 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT2_MCTL_A               ((volatile uint32_t *)REG_SPORT2_MCTL_A)                /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_A                ((volatile uint32_t *)REG_SPORT2_CS0_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_A                ((volatile uint32_t *)REG_SPORT2_CS1_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_A                ((volatile uint32_t *)REG_SPORT2_CS2_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT2_CS3_A                ((volatile uint32_t *)REG_SPORT2_CS3_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT2_ERR_A                ((volatile uint32_t *)REG_SPORT2_ERR_A)                 /* SPORT2 Half SPORT 'A' Error Register */
-#define pREG_SPORT2_MSTAT_A              ((volatile uint32_t *)REG_SPORT2_MSTAT_A)               /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_A               ((volatile uint32_t *)REG_SPORT2_CTL2_A)                /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT2_TXPRI_A              ((volatile uint32_t *)REG_SPORT2_TXPRI_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_A              ((volatile uint32_t *)REG_SPORT2_RXPRI_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_A              ((volatile uint32_t *)REG_SPORT2_TXSEC_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_A              ((volatile uint32_t *)REG_SPORT2_RXSEC_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT2_CTL_B                ((volatile uint32_t *)REG_SPORT2_CTL_B)                 /* SPORT2 Half SPORT 'B' Control Register */
-#define pREG_SPORT2_DIV_B                ((volatile uint32_t *)REG_SPORT2_DIV_B)                 /* SPORT2 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT2_MCTL_B               ((volatile uint32_t *)REG_SPORT2_MCTL_B)                /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_B                ((volatile uint32_t *)REG_SPORT2_CS0_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_B                ((volatile uint32_t *)REG_SPORT2_CS1_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_B                ((volatile uint32_t *)REG_SPORT2_CS2_B)                 /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT2_CS3_B                ((volatile uint32_t *)REG_SPORT2_CS3_B)                 /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT2_ERR_B                ((volatile uint32_t *)REG_SPORT2_ERR_B)                 /* SPORT2 Half SPORT 'B' Error Register */
-#define pREG_SPORT2_MSTAT_B              ((volatile uint32_t *)REG_SPORT2_MSTAT_B)               /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_B               ((volatile uint32_t *)REG_SPORT2_CTL2_B)                /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT2_TXPRI_B              ((volatile uint32_t *)REG_SPORT2_TXPRI_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_B              ((volatile uint32_t *)REG_SPORT2_RXPRI_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_B              ((volatile uint32_t *)REG_SPORT2_TXSEC_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_B              ((volatile uint32_t *)REG_SPORT2_RXSEC_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-
-/* =========================================================================
-       SPI0
-   ========================================================================= */
-#define pREG_SPI0_CTL                    ((volatile uint32_t *)REG_SPI0_CTL)                     /* SPI0 Control Register */
-#define pREG_SPI0_RXCTL                  ((volatile uint32_t *)REG_SPI0_RXCTL)                   /* SPI0 Receive Control Register */
-#define pREG_SPI0_TXCTL                  ((volatile uint32_t *)REG_SPI0_TXCTL)                   /* SPI0 Transmit Control Register */
-#define pREG_SPI0_CLK                    ((volatile uint32_t *)REG_SPI0_CLK)                     /* SPI0 Clock Rate Register */
-#define pREG_SPI0_DLY                    ((volatile uint32_t *)REG_SPI0_DLY)                     /* SPI0 Delay Register */
-#define pREG_SPI0_SLVSEL                 ((volatile uint32_t *)REG_SPI0_SLVSEL)                  /* SPI0 Slave Select Register */
-#define pREG_SPI0_RWC                    ((volatile uint32_t *)REG_SPI0_RWC)                     /* SPI0 Received Word Count Register */
-#define pREG_SPI0_RWCR                   ((volatile uint32_t *)REG_SPI0_RWCR)                    /* SPI0 Received Word Count Reload Register */
-#define pREG_SPI0_TWC                    ((volatile uint32_t *)REG_SPI0_TWC)                     /* SPI0 Transmitted Word Count Register */
-#define pREG_SPI0_TWCR                   ((volatile uint32_t *)REG_SPI0_TWCR)                    /* SPI0 Transmitted Word Count Reload Register */
-#define pREG_SPI0_IMSK                   ((volatile uint32_t *)REG_SPI0_IMSK)                    /* SPI0 Interrupt Mask Register */
-#define pREG_SPI0_IMSK_CLR               ((volatile uint32_t *)REG_SPI0_IMSK_CLR)                /* SPI0 Interrupt Mask Clear Register */
-#define pREG_SPI0_IMSK_SET               ((volatile uint32_t *)REG_SPI0_IMSK_SET)                /* SPI0 Interrupt Mask Set Register */
-#define pREG_SPI0_STAT                   ((volatile uint32_t *)REG_SPI0_STAT)                    /* SPI0 Status Register */
-#define pREG_SPI0_ILAT                   ((volatile uint32_t *)REG_SPI0_ILAT)                    /* SPI0 Masked Interrupt Condition Register */
-#define pREG_SPI0_ILAT_CLR               ((volatile uint32_t *)REG_SPI0_ILAT_CLR)                /* SPI0 Masked Interrupt Clear Register */
-#define pREG_SPI0_RFIFO                  ((volatile uint32_t *)REG_SPI0_RFIFO)                   /* SPI0 Receive FIFO Data Register */
-#define pREG_SPI0_TFIFO                  ((volatile uint32_t *)REG_SPI0_TFIFO)                   /* SPI0 Transmit FIFO Data Register */
-
-/* =========================================================================
-       SPI1
-   ========================================================================= */
-#define pREG_SPI1_CTL                    ((volatile uint32_t *)REG_SPI1_CTL)                     /* SPI1 Control Register */
-#define pREG_SPI1_RXCTL                  ((volatile uint32_t *)REG_SPI1_RXCTL)                   /* SPI1 Receive Control Register */
-#define pREG_SPI1_TXCTL                  ((volatile uint32_t *)REG_SPI1_TXCTL)                   /* SPI1 Transmit Control Register */
-#define pREG_SPI1_CLK                    ((volatile uint32_t *)REG_SPI1_CLK)                     /* SPI1 Clock Rate Register */
-#define pREG_SPI1_DLY                    ((volatile uint32_t *)REG_SPI1_DLY)                     /* SPI1 Delay Register */
-#define pREG_SPI1_SLVSEL                 ((volatile uint32_t *)REG_SPI1_SLVSEL)                  /* SPI1 Slave Select Register */
-#define pREG_SPI1_RWC                    ((volatile uint32_t *)REG_SPI1_RWC)                     /* SPI1 Received Word Count Register */
-#define pREG_SPI1_RWCR                   ((volatile uint32_t *)REG_SPI1_RWCR)                    /* SPI1 Received Word Count Reload Register */
-#define pREG_SPI1_TWC                    ((volatile uint32_t *)REG_SPI1_TWC)                     /* SPI1 Transmitted Word Count Register */
-#define pREG_SPI1_TWCR                   ((volatile uint32_t *)REG_SPI1_TWCR)                    /* SPI1 Transmitted Word Count Reload Register */
-#define pREG_SPI1_IMSK                   ((volatile uint32_t *)REG_SPI1_IMSK)                    /* SPI1 Interrupt Mask Register */
-#define pREG_SPI1_IMSK_CLR               ((volatile uint32_t *)REG_SPI1_IMSK_CLR)                /* SPI1 Interrupt Mask Clear Register */
-#define pREG_SPI1_IMSK_SET               ((volatile uint32_t *)REG_SPI1_IMSK_SET)                /* SPI1 Interrupt Mask Set Register */
-#define pREG_SPI1_STAT                   ((volatile uint32_t *)REG_SPI1_STAT)                    /* SPI1 Status Register */
-#define pREG_SPI1_ILAT                   ((volatile uint32_t *)REG_SPI1_ILAT)                    /* SPI1 Masked Interrupt Condition Register */
-#define pREG_SPI1_ILAT_CLR               ((volatile uint32_t *)REG_SPI1_ILAT_CLR)                /* SPI1 Masked Interrupt Clear Register */
-#define pREG_SPI1_RFIFO                  ((volatile uint32_t *)REG_SPI1_RFIFO)                   /* SPI1 Receive FIFO Data Register */
-#define pREG_SPI1_TFIFO                  ((volatile uint32_t *)REG_SPI1_TFIFO)                   /* SPI1 Transmit FIFO Data Register */
-
-
-/* =========================================================================
-       DMA0
-   ========================================================================= */
-#define pREG_DMA0_DSCPTR_NXT             ((void * volatile *)REG_DMA0_DSCPTR_NXT)                /* DMA0 Pointer to Next Initial Descriptor */
-#define pREG_DMA0_ADDRSTART              ((void * volatile *)REG_DMA0_ADDRSTART)                 /* DMA0 Start Address of Current Buffer */
-#define pREG_DMA0_CFG                    ((volatile uint32_t *)REG_DMA0_CFG)                     /* DMA0 Configuration Register */
-#define pREG_DMA0_XCNT                   ((volatile uint32_t *)REG_DMA0_XCNT)                    /* DMA0 Inner Loop Count Start Value */
-#define pREG_DMA0_XMOD                   ((volatile  int32_t *)REG_DMA0_XMOD)                    /* DMA0 Inner Loop Address Increment */
-#define pREG_DMA0_YCNT                   ((volatile uint32_t *)REG_DMA0_YCNT)                    /* DMA0 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA0_YMOD                   ((volatile  int32_t *)REG_DMA0_YMOD)                    /* DMA0 Outer Loop Address Increment (2D only) */
-#define pREG_DMA0_DSCPTR_CUR             ((void * volatile *)REG_DMA0_DSCPTR_CUR)                /* DMA0 Current Descriptor Pointer */
-#define pREG_DMA0_DSCPTR_PRV             ((void * volatile *)REG_DMA0_DSCPTR_PRV)                /* DMA0 Previous Initial Descriptor Pointer */
-#define pREG_DMA0_ADDR_CUR               ((void * volatile *)REG_DMA0_ADDR_CUR)                  /* DMA0 Current Address */
-#define pREG_DMA0_STAT                   ((volatile uint32_t *)REG_DMA0_STAT)                    /* DMA0 Status Register */
-#define pREG_DMA0_XCNT_CUR               ((volatile uint32_t *)REG_DMA0_XCNT_CUR)                /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA0_YCNT_CUR               ((volatile uint32_t *)REG_DMA0_YCNT_CUR)                /* DMA0 Current Row Count (2D only) */
-#define pREG_DMA0_BWLCNT                 ((volatile uint32_t *)REG_DMA0_BWLCNT)                  /* DMA0 Bandwidth Limit Count */
-#define pREG_DMA0_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWLCNT_CUR)              /* DMA0 Bandwidth Limit Count Current */
-#define pREG_DMA0_BWMCNT                 ((volatile uint32_t *)REG_DMA0_BWMCNT)                  /* DMA0 Bandwidth Monitor Count */
-#define pREG_DMA0_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWMCNT_CUR)              /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA1
-   ========================================================================= */
-#define pREG_DMA1_DSCPTR_NXT             ((void * volatile *)REG_DMA1_DSCPTR_NXT)                /* DMA1 Pointer to Next Initial Descriptor */
-#define pREG_DMA1_ADDRSTART              ((void * volatile *)REG_DMA1_ADDRSTART)                 /* DMA1 Start Address of Current Buffer */
-#define pREG_DMA1_CFG                    ((volatile uint32_t *)REG_DMA1_CFG)                     /* DMA1 Configuration Register */
-#define pREG_DMA1_XCNT                   ((volatile uint32_t *)REG_DMA1_XCNT)                    /* DMA1 Inner Loop Count Start Value */
-#define pREG_DMA1_XMOD                   ((volatile  int32_t *)REG_DMA1_XMOD)                    /* DMA1 Inner Loop Address Increment */
-#define pREG_DMA1_YCNT                   ((volatile uint32_t *)REG_DMA1_YCNT)                    /* DMA1 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA1_YMOD                   ((volatile  int32_t *)REG_DMA1_YMOD)                    /* DMA1 Outer Loop Address Increment (2D only) */
-#define pREG_DMA1_DSCPTR_CUR             ((void * volatile *)REG_DMA1_DSCPTR_CUR)                /* DMA1 Current Descriptor Pointer */
-#define pREG_DMA1_DSCPTR_PRV             ((void * volatile *)REG_DMA1_DSCPTR_PRV)                /* DMA1 Previous Initial Descriptor Pointer */
-#define pREG_DMA1_ADDR_CUR               ((void * volatile *)REG_DMA1_ADDR_CUR)                  /* DMA1 Current Address */
-#define pREG_DMA1_STAT                   ((volatile uint32_t *)REG_DMA1_STAT)                    /* DMA1 Status Register */
-#define pREG_DMA1_XCNT_CUR               ((volatile uint32_t *)REG_DMA1_XCNT_CUR)                /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA1_YCNT_CUR               ((volatile uint32_t *)REG_DMA1_YCNT_CUR)                /* DMA1 Current Row Count (2D only) */
-#define pREG_DMA1_BWLCNT                 ((volatile uint32_t *)REG_DMA1_BWLCNT)                  /* DMA1 Bandwidth Limit Count */
-#define pREG_DMA1_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWLCNT_CUR)              /* DMA1 Bandwidth Limit Count Current */
-#define pREG_DMA1_BWMCNT                 ((volatile uint32_t *)REG_DMA1_BWMCNT)                  /* DMA1 Bandwidth Monitor Count */
-#define pREG_DMA1_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWMCNT_CUR)              /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA2
-   ========================================================================= */
-#define pREG_DMA2_DSCPTR_NXT             ((void * volatile *)REG_DMA2_DSCPTR_NXT)                /* DMA2 Pointer to Next Initial Descriptor */
-#define pREG_DMA2_ADDRSTART              ((void * volatile *)REG_DMA2_ADDRSTART)                 /* DMA2 Start Address of Current Buffer */
-#define pREG_DMA2_CFG                    ((volatile uint32_t *)REG_DMA2_CFG)                     /* DMA2 Configuration Register */
-#define pREG_DMA2_XCNT                   ((volatile uint32_t *)REG_DMA2_XCNT)                    /* DMA2 Inner Loop Count Start Value */
-#define pREG_DMA2_XMOD                   ((volatile  int32_t *)REG_DMA2_XMOD)                    /* DMA2 Inner Loop Address Increment */
-#define pREG_DMA2_YCNT                   ((volatile uint32_t *)REG_DMA2_YCNT)                    /* DMA2 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA2_YMOD                   ((volatile  int32_t *)REG_DMA2_YMOD)                    /* DMA2 Outer Loop Address Increment (2D only) */
-#define pREG_DMA2_DSCPTR_CUR             ((void * volatile *)REG_DMA2_DSCPTR_CUR)                /* DMA2 Current Descriptor Pointer */
-#define pREG_DMA2_DSCPTR_PRV             ((void * volatile *)REG_DMA2_DSCPTR_PRV)                /* DMA2 Previous Initial Descriptor Pointer */
-#define pREG_DMA2_ADDR_CUR               ((void * volatile *)REG_DMA2_ADDR_CUR)                  /* DMA2 Current Address */
-#define pREG_DMA2_STAT                   ((volatile uint32_t *)REG_DMA2_STAT)                    /* DMA2 Status Register */
-#define pREG_DMA2_XCNT_CUR               ((volatile uint32_t *)REG_DMA2_XCNT_CUR)                /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA2_YCNT_CUR               ((volatile uint32_t *)REG_DMA2_YCNT_CUR)                /* DMA2 Current Row Count (2D only) */
-#define pREG_DMA2_BWLCNT                 ((volatile uint32_t *)REG_DMA2_BWLCNT)                  /* DMA2 Bandwidth Limit Count */
-#define pREG_DMA2_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWLCNT_CUR)              /* DMA2 Bandwidth Limit Count Current */
-#define pREG_DMA2_BWMCNT                 ((volatile uint32_t *)REG_DMA2_BWMCNT)                  /* DMA2 Bandwidth Monitor Count */
-#define pREG_DMA2_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWMCNT_CUR)              /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA3
-   ========================================================================= */
-#define pREG_DMA3_DSCPTR_NXT             ((void * volatile *)REG_DMA3_DSCPTR_NXT)                /* DMA3 Pointer to Next Initial Descriptor */
-#define pREG_DMA3_ADDRSTART              ((void * volatile *)REG_DMA3_ADDRSTART)                 /* DMA3 Start Address of Current Buffer */
-#define pREG_DMA3_CFG                    ((volatile uint32_t *)REG_DMA3_CFG)                     /* DMA3 Configuration Register */
-#define pREG_DMA3_XCNT                   ((volatile uint32_t *)REG_DMA3_XCNT)                    /* DMA3 Inner Loop Count Start Value */
-#define pREG_DMA3_XMOD                   ((volatile  int32_t *)REG_DMA3_XMOD)                    /* DMA3 Inner Loop Address Increment */
-#define pREG_DMA3_YCNT                   ((volatile uint32_t *)REG_DMA3_YCNT)                    /* DMA3 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA3_YMOD                   ((volatile  int32_t *)REG_DMA3_YMOD)                    /* DMA3 Outer Loop Address Increment (2D only) */
-#define pREG_DMA3_DSCPTR_CUR             ((void * volatile *)REG_DMA3_DSCPTR_CUR)                /* DMA3 Current Descriptor Pointer */
-#define pREG_DMA3_DSCPTR_PRV             ((void * volatile *)REG_DMA3_DSCPTR_PRV)                /* DMA3 Previous Initial Descriptor Pointer */
-#define pREG_DMA3_ADDR_CUR               ((void * volatile *)REG_DMA3_ADDR_CUR)                  /* DMA3 Current Address */
-#define pREG_DMA3_STAT                   ((volatile uint32_t *)REG_DMA3_STAT)                    /* DMA3 Status Register */
-#define pREG_DMA3_XCNT_CUR               ((volatile uint32_t *)REG_DMA3_XCNT_CUR)                /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA3_YCNT_CUR               ((volatile uint32_t *)REG_DMA3_YCNT_CUR)                /* DMA3 Current Row Count (2D only) */
-#define pREG_DMA3_BWLCNT                 ((volatile uint32_t *)REG_DMA3_BWLCNT)                  /* DMA3 Bandwidth Limit Count */
-#define pREG_DMA3_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWLCNT_CUR)              /* DMA3 Bandwidth Limit Count Current */
-#define pREG_DMA3_BWMCNT                 ((volatile uint32_t *)REG_DMA3_BWMCNT)                  /* DMA3 Bandwidth Monitor Count */
-#define pREG_DMA3_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWMCNT_CUR)              /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA4
-   ========================================================================= */
-#define pREG_DMA4_DSCPTR_NXT             ((void * volatile *)REG_DMA4_DSCPTR_NXT)                /* DMA4 Pointer to Next Initial Descriptor */
-#define pREG_DMA4_ADDRSTART              ((void * volatile *)REG_DMA4_ADDRSTART)                 /* DMA4 Start Address of Current Buffer */
-#define pREG_DMA4_CFG                    ((volatile uint32_t *)REG_DMA4_CFG)                     /* DMA4 Configuration Register */
-#define pREG_DMA4_XCNT                   ((volatile uint32_t *)REG_DMA4_XCNT)                    /* DMA4 Inner Loop Count Start Value */
-#define pREG_DMA4_XMOD                   ((volatile  int32_t *)REG_DMA4_XMOD)                    /* DMA4 Inner Loop Address Increment */
-#define pREG_DMA4_YCNT                   ((volatile uint32_t *)REG_DMA4_YCNT)                    /* DMA4 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA4_YMOD                   ((volatile  int32_t *)REG_DMA4_YMOD)                    /* DMA4 Outer Loop Address Increment (2D only) */
-#define pREG_DMA4_DSCPTR_CUR             ((void * volatile *)REG_DMA4_DSCPTR_CUR)                /* DMA4 Current Descriptor Pointer */
-#define pREG_DMA4_DSCPTR_PRV             ((void * volatile *)REG_DMA4_DSCPTR_PRV)                /* DMA4 Previous Initial Descriptor Pointer */
-#define pREG_DMA4_ADDR_CUR               ((void * volatile *)REG_DMA4_ADDR_CUR)                  /* DMA4 Current Address */
-#define pREG_DMA4_STAT                   ((volatile uint32_t *)REG_DMA4_STAT)                    /* DMA4 Status Register */
-#define pREG_DMA4_XCNT_CUR               ((volatile uint32_t *)REG_DMA4_XCNT_CUR)                /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA4_YCNT_CUR               ((volatile uint32_t *)REG_DMA4_YCNT_CUR)                /* DMA4 Current Row Count (2D only) */
-#define pREG_DMA4_BWLCNT                 ((volatile uint32_t *)REG_DMA4_BWLCNT)                  /* DMA4 Bandwidth Limit Count */
-#define pREG_DMA4_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWLCNT_CUR)              /* DMA4 Bandwidth Limit Count Current */
-#define pREG_DMA4_BWMCNT                 ((volatile uint32_t *)REG_DMA4_BWMCNT)                  /* DMA4 Bandwidth Monitor Count */
-#define pREG_DMA4_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWMCNT_CUR)              /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA5
-   ========================================================================= */
-#define pREG_DMA5_DSCPTR_NXT             ((void * volatile *)REG_DMA5_DSCPTR_NXT)                /* DMA5 Pointer to Next Initial Descriptor */
-#define pREG_DMA5_ADDRSTART              ((void * volatile *)REG_DMA5_ADDRSTART)                 /* DMA5 Start Address of Current Buffer */
-#define pREG_DMA5_CFG                    ((volatile uint32_t *)REG_DMA5_CFG)                     /* DMA5 Configuration Register */
-#define pREG_DMA5_XCNT                   ((volatile uint32_t *)REG_DMA5_XCNT)                    /* DMA5 Inner Loop Count Start Value */
-#define pREG_DMA5_XMOD                   ((volatile  int32_t *)REG_DMA5_XMOD)                    /* DMA5 Inner Loop Address Increment */
-#define pREG_DMA5_YCNT                   ((volatile uint32_t *)REG_DMA5_YCNT)                    /* DMA5 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA5_YMOD                   ((volatile  int32_t *)REG_DMA5_YMOD)                    /* DMA5 Outer Loop Address Increment (2D only) */
-#define pREG_DMA5_DSCPTR_CUR             ((void * volatile *)REG_DMA5_DSCPTR_CUR)                /* DMA5 Current Descriptor Pointer */
-#define pREG_DMA5_DSCPTR_PRV             ((void * volatile *)REG_DMA5_DSCPTR_PRV)                /* DMA5 Previous Initial Descriptor Pointer */
-#define pREG_DMA5_ADDR_CUR               ((void * volatile *)REG_DMA5_ADDR_CUR)                  /* DMA5 Current Address */
-#define pREG_DMA5_STAT                   ((volatile uint32_t *)REG_DMA5_STAT)                    /* DMA5 Status Register */
-#define pREG_DMA5_XCNT_CUR               ((volatile uint32_t *)REG_DMA5_XCNT_CUR)                /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA5_YCNT_CUR               ((volatile uint32_t *)REG_DMA5_YCNT_CUR)                /* DMA5 Current Row Count (2D only) */
-#define pREG_DMA5_BWLCNT                 ((volatile uint32_t *)REG_DMA5_BWLCNT)                  /* DMA5 Bandwidth Limit Count */
-#define pREG_DMA5_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWLCNT_CUR)              /* DMA5 Bandwidth Limit Count Current */
-#define pREG_DMA5_BWMCNT                 ((volatile uint32_t *)REG_DMA5_BWMCNT)                  /* DMA5 Bandwidth Monitor Count */
-#define pREG_DMA5_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWMCNT_CUR)              /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA6
-   ========================================================================= */
-#define pREG_DMA6_DSCPTR_NXT             ((void * volatile *)REG_DMA6_DSCPTR_NXT)                /* DMA6 Pointer to Next Initial Descriptor */
-#define pREG_DMA6_ADDRSTART              ((void * volatile *)REG_DMA6_ADDRSTART)                 /* DMA6 Start Address of Current Buffer */
-#define pREG_DMA6_CFG                    ((volatile uint32_t *)REG_DMA6_CFG)                     /* DMA6 Configuration Register */
-#define pREG_DMA6_XCNT                   ((volatile uint32_t *)REG_DMA6_XCNT)                    /* DMA6 Inner Loop Count Start Value */
-#define pREG_DMA6_XMOD                   ((volatile  int32_t *)REG_DMA6_XMOD)                    /* DMA6 Inner Loop Address Increment */
-#define pREG_DMA6_YCNT                   ((volatile uint32_t *)REG_DMA6_YCNT)                    /* DMA6 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA6_YMOD                   ((volatile  int32_t *)REG_DMA6_YMOD)                    /* DMA6 Outer Loop Address Increment (2D only) */
-#define pREG_DMA6_DSCPTR_CUR             ((void * volatile *)REG_DMA6_DSCPTR_CUR)                /* DMA6 Current Descriptor Pointer */
-#define pREG_DMA6_DSCPTR_PRV             ((void * volatile *)REG_DMA6_DSCPTR_PRV)                /* DMA6 Previous Initial Descriptor Pointer */
-#define pREG_DMA6_ADDR_CUR               ((void * volatile *)REG_DMA6_ADDR_CUR)                  /* DMA6 Current Address */
-#define pREG_DMA6_STAT                   ((volatile uint32_t *)REG_DMA6_STAT)                    /* DMA6 Status Register */
-#define pREG_DMA6_XCNT_CUR               ((volatile uint32_t *)REG_DMA6_XCNT_CUR)                /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA6_YCNT_CUR               ((volatile uint32_t *)REG_DMA6_YCNT_CUR)                /* DMA6 Current Row Count (2D only) */
-#define pREG_DMA6_BWLCNT                 ((volatile uint32_t *)REG_DMA6_BWLCNT)                  /* DMA6 Bandwidth Limit Count */
-#define pREG_DMA6_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWLCNT_CUR)              /* DMA6 Bandwidth Limit Count Current */
-#define pREG_DMA6_BWMCNT                 ((volatile uint32_t *)REG_DMA6_BWMCNT)                  /* DMA6 Bandwidth Monitor Count */
-#define pREG_DMA6_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWMCNT_CUR)              /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA7
-   ========================================================================= */
-#define pREG_DMA7_DSCPTR_NXT             ((void * volatile *)REG_DMA7_DSCPTR_NXT)                /* DMA7 Pointer to Next Initial Descriptor */
-#define pREG_DMA7_ADDRSTART              ((void * volatile *)REG_DMA7_ADDRSTART)                 /* DMA7 Start Address of Current Buffer */
-#define pREG_DMA7_CFG                    ((volatile uint32_t *)REG_DMA7_CFG)                     /* DMA7 Configuration Register */
-#define pREG_DMA7_XCNT                   ((volatile uint32_t *)REG_DMA7_XCNT)                    /* DMA7 Inner Loop Count Start Value */
-#define pREG_DMA7_XMOD                   ((volatile  int32_t *)REG_DMA7_XMOD)                    /* DMA7 Inner Loop Address Increment */
-#define pREG_DMA7_YCNT                   ((volatile uint32_t *)REG_DMA7_YCNT)                    /* DMA7 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA7_YMOD                   ((volatile  int32_t *)REG_DMA7_YMOD)                    /* DMA7 Outer Loop Address Increment (2D only) */
-#define pREG_DMA7_DSCPTR_CUR             ((void * volatile *)REG_DMA7_DSCPTR_CUR)                /* DMA7 Current Descriptor Pointer */
-#define pREG_DMA7_DSCPTR_PRV             ((void * volatile *)REG_DMA7_DSCPTR_PRV)                /* DMA7 Previous Initial Descriptor Pointer */
-#define pREG_DMA7_ADDR_CUR               ((void * volatile *)REG_DMA7_ADDR_CUR)                  /* DMA7 Current Address */
-#define pREG_DMA7_STAT                   ((volatile uint32_t *)REG_DMA7_STAT)                    /* DMA7 Status Register */
-#define pREG_DMA7_XCNT_CUR               ((volatile uint32_t *)REG_DMA7_XCNT_CUR)                /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA7_YCNT_CUR               ((volatile uint32_t *)REG_DMA7_YCNT_CUR)                /* DMA7 Current Row Count (2D only) */
-#define pREG_DMA7_BWLCNT                 ((volatile uint32_t *)REG_DMA7_BWLCNT)                  /* DMA7 Bandwidth Limit Count */
-#define pREG_DMA7_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWLCNT_CUR)              /* DMA7 Bandwidth Limit Count Current */
-#define pREG_DMA7_BWMCNT                 ((volatile uint32_t *)REG_DMA7_BWMCNT)                  /* DMA7 Bandwidth Monitor Count */
-#define pREG_DMA7_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWMCNT_CUR)              /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA8
-   ========================================================================= */
-#define pREG_DMA8_DSCPTR_NXT             ((void * volatile *)REG_DMA8_DSCPTR_NXT)                /* DMA8 Pointer to Next Initial Descriptor */
-#define pREG_DMA8_ADDRSTART              ((void * volatile *)REG_DMA8_ADDRSTART)                 /* DMA8 Start Address of Current Buffer */
-#define pREG_DMA8_CFG                    ((volatile uint32_t *)REG_DMA8_CFG)                     /* DMA8 Configuration Register */
-#define pREG_DMA8_XCNT                   ((volatile uint32_t *)REG_DMA8_XCNT)                    /* DMA8 Inner Loop Count Start Value */
-#define pREG_DMA8_XMOD                   ((volatile  int32_t *)REG_DMA8_XMOD)                    /* DMA8 Inner Loop Address Increment */
-#define pREG_DMA8_YCNT                   ((volatile uint32_t *)REG_DMA8_YCNT)                    /* DMA8 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA8_YMOD                   ((volatile  int32_t *)REG_DMA8_YMOD)                    /* DMA8 Outer Loop Address Increment (2D only) */
-#define pREG_DMA8_DSCPTR_CUR             ((void * volatile *)REG_DMA8_DSCPTR_CUR)                /* DMA8 Current Descriptor Pointer */
-#define pREG_DMA8_DSCPTR_PRV             ((void * volatile *)REG_DMA8_DSCPTR_PRV)                /* DMA8 Previous Initial Descriptor Pointer */
-#define pREG_DMA8_ADDR_CUR               ((void * volatile *)REG_DMA8_ADDR_CUR)                  /* DMA8 Current Address */
-#define pREG_DMA8_STAT                   ((volatile uint32_t *)REG_DMA8_STAT)                    /* DMA8 Status Register */
-#define pREG_DMA8_XCNT_CUR               ((volatile uint32_t *)REG_DMA8_XCNT_CUR)                /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA8_YCNT_CUR               ((volatile uint32_t *)REG_DMA8_YCNT_CUR)                /* DMA8 Current Row Count (2D only) */
-#define pREG_DMA8_BWLCNT                 ((volatile uint32_t *)REG_DMA8_BWLCNT)                  /* DMA8 Bandwidth Limit Count */
-#define pREG_DMA8_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWLCNT_CUR)              /* DMA8 Bandwidth Limit Count Current */
-#define pREG_DMA8_BWMCNT                 ((volatile uint32_t *)REG_DMA8_BWMCNT)                  /* DMA8 Bandwidth Monitor Count */
-#define pREG_DMA8_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWMCNT_CUR)              /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA9
-   ========================================================================= */
-#define pREG_DMA9_DSCPTR_NXT             ((void * volatile *)REG_DMA9_DSCPTR_NXT)                /* DMA9 Pointer to Next Initial Descriptor */
-#define pREG_DMA9_ADDRSTART              ((void * volatile *)REG_DMA9_ADDRSTART)                 /* DMA9 Start Address of Current Buffer */
-#define pREG_DMA9_CFG                    ((volatile uint32_t *)REG_DMA9_CFG)                     /* DMA9 Configuration Register */
-#define pREG_DMA9_XCNT                   ((volatile uint32_t *)REG_DMA9_XCNT)                    /* DMA9 Inner Loop Count Start Value */
-#define pREG_DMA9_XMOD                   ((volatile  int32_t *)REG_DMA9_XMOD)                    /* DMA9 Inner Loop Address Increment */
-#define pREG_DMA9_YCNT                   ((volatile uint32_t *)REG_DMA9_YCNT)                    /* DMA9 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA9_YMOD                   ((volatile  int32_t *)REG_DMA9_YMOD)                    /* DMA9 Outer Loop Address Increment (2D only) */
-#define pREG_DMA9_DSCPTR_CUR             ((void * volatile *)REG_DMA9_DSCPTR_CUR)                /* DMA9 Current Descriptor Pointer */
-#define pREG_DMA9_DSCPTR_PRV             ((void * volatile *)REG_DMA9_DSCPTR_PRV)                /* DMA9 Previous Initial Descriptor Pointer */
-#define pREG_DMA9_ADDR_CUR               ((void * volatile *)REG_DMA9_ADDR_CUR)                  /* DMA9 Current Address */
-#define pREG_DMA9_STAT                   ((volatile uint32_t *)REG_DMA9_STAT)                    /* DMA9 Status Register */
-#define pREG_DMA9_XCNT_CUR               ((volatile uint32_t *)REG_DMA9_XCNT_CUR)                /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA9_YCNT_CUR               ((volatile uint32_t *)REG_DMA9_YCNT_CUR)                /* DMA9 Current Row Count (2D only) */
-#define pREG_DMA9_BWLCNT                 ((volatile uint32_t *)REG_DMA9_BWLCNT)                  /* DMA9 Bandwidth Limit Count */
-#define pREG_DMA9_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWLCNT_CUR)              /* DMA9 Bandwidth Limit Count Current */
-#define pREG_DMA9_BWMCNT                 ((volatile uint32_t *)REG_DMA9_BWMCNT)                  /* DMA9 Bandwidth Monitor Count */
-#define pREG_DMA9_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWMCNT_CUR)              /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA10
-   ========================================================================= */
-#define pREG_DMA10_DSCPTR_NXT            ((void * volatile *)REG_DMA10_DSCPTR_NXT)               /* DMA10 Pointer to Next Initial Descriptor */
-#define pREG_DMA10_ADDRSTART             ((void * volatile *)REG_DMA10_ADDRSTART)                /* DMA10 Start Address of Current Buffer */
-#define pREG_DMA10_CFG                   ((volatile uint32_t *)REG_DMA10_CFG)                    /* DMA10 Configuration Register */
-#define pREG_DMA10_XCNT                  ((volatile uint32_t *)REG_DMA10_XCNT)                   /* DMA10 Inner Loop Count Start Value */
-#define pREG_DMA10_XMOD                  ((volatile  int32_t *)REG_DMA10_XMOD)                   /* DMA10 Inner Loop Address Increment */
-#define pREG_DMA10_YCNT                  ((volatile uint32_t *)REG_DMA10_YCNT)                   /* DMA10 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA10_YMOD                  ((volatile  int32_t *)REG_DMA10_YMOD)                   /* DMA10 Outer Loop Address Increment (2D only) */
-#define pREG_DMA10_DSCPTR_CUR            ((void * volatile *)REG_DMA10_DSCPTR_CUR)               /* DMA10 Current Descriptor Pointer */
-#define pREG_DMA10_DSCPTR_PRV            ((void * volatile *)REG_DMA10_DSCPTR_PRV)               /* DMA10 Previous Initial Descriptor Pointer */
-#define pREG_DMA10_ADDR_CUR              ((void * volatile *)REG_DMA10_ADDR_CUR)                 /* DMA10 Current Address */
-#define pREG_DMA10_STAT                  ((volatile uint32_t *)REG_DMA10_STAT)                   /* DMA10 Status Register */
-#define pREG_DMA10_XCNT_CUR              ((volatile uint32_t *)REG_DMA10_XCNT_CUR)               /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA10_YCNT_CUR              ((volatile uint32_t *)REG_DMA10_YCNT_CUR)               /* DMA10 Current Row Count (2D only) */
-#define pREG_DMA10_BWLCNT                ((volatile uint32_t *)REG_DMA10_BWLCNT)                 /* DMA10 Bandwidth Limit Count */
-#define pREG_DMA10_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWLCNT_CUR)             /* DMA10 Bandwidth Limit Count Current */
-#define pREG_DMA10_BWMCNT                ((volatile uint32_t *)REG_DMA10_BWMCNT)                 /* DMA10 Bandwidth Monitor Count */
-#define pREG_DMA10_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWMCNT_CUR)             /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA11
-   ========================================================================= */
-#define pREG_DMA11_DSCPTR_NXT            ((void * volatile *)REG_DMA11_DSCPTR_NXT)               /* DMA11 Pointer to Next Initial Descriptor */
-#define pREG_DMA11_ADDRSTART             ((void * volatile *)REG_DMA11_ADDRSTART)                /* DMA11 Start Address of Current Buffer */
-#define pREG_DMA11_CFG                   ((volatile uint32_t *)REG_DMA11_CFG)                    /* DMA11 Configuration Register */
-#define pREG_DMA11_XCNT                  ((volatile uint32_t *)REG_DMA11_XCNT)                   /* DMA11 Inner Loop Count Start Value */
-#define pREG_DMA11_XMOD                  ((volatile  int32_t *)REG_DMA11_XMOD)                   /* DMA11 Inner Loop Address Increment */
-#define pREG_DMA11_YCNT                  ((volatile uint32_t *)REG_DMA11_YCNT)                   /* DMA11 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA11_YMOD                  ((volatile  int32_t *)REG_DMA11_YMOD)                   /* DMA11 Outer Loop Address Increment (2D only) */
-#define pREG_DMA11_DSCPTR_CUR            ((void * volatile *)REG_DMA11_DSCPTR_CUR)               /* DMA11 Current Descriptor Pointer */
-#define pREG_DMA11_DSCPTR_PRV            ((void * volatile *)REG_DMA11_DSCPTR_PRV)               /* DMA11 Previous Initial Descriptor Pointer */
-#define pREG_DMA11_ADDR_CUR              ((void * volatile *)REG_DMA11_ADDR_CUR)                 /* DMA11 Current Address */
-#define pREG_DMA11_STAT                  ((volatile uint32_t *)REG_DMA11_STAT)                   /* DMA11 Status Register */
-#define pREG_DMA11_XCNT_CUR              ((volatile uint32_t *)REG_DMA11_XCNT_CUR)               /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA11_YCNT_CUR              ((volatile uint32_t *)REG_DMA11_YCNT_CUR)               /* DMA11 Current Row Count (2D only) */
-#define pREG_DMA11_BWLCNT                ((volatile uint32_t *)REG_DMA11_BWLCNT)                 /* DMA11 Bandwidth Limit Count */
-#define pREG_DMA11_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWLCNT_CUR)             /* DMA11 Bandwidth Limit Count Current */
-#define pREG_DMA11_BWMCNT                ((volatile uint32_t *)REG_DMA11_BWMCNT)                 /* DMA11 Bandwidth Monitor Count */
-#define pREG_DMA11_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWMCNT_CUR)             /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA12
-   ========================================================================= */
-#define pREG_DMA12_DSCPTR_NXT            ((void * volatile *)REG_DMA12_DSCPTR_NXT)               /* DMA12 Pointer to Next Initial Descriptor */
-#define pREG_DMA12_ADDRSTART             ((void * volatile *)REG_DMA12_ADDRSTART)                /* DMA12 Start Address of Current Buffer */
-#define pREG_DMA12_CFG                   ((volatile uint32_t *)REG_DMA12_CFG)                    /* DMA12 Configuration Register */
-#define pREG_DMA12_XCNT                  ((volatile uint32_t *)REG_DMA12_XCNT)                   /* DMA12 Inner Loop Count Start Value */
-#define pREG_DMA12_XMOD                  ((volatile  int32_t *)REG_DMA12_XMOD)                   /* DMA12 Inner Loop Address Increment */
-#define pREG_DMA12_YCNT                  ((volatile uint32_t *)REG_DMA12_YCNT)                   /* DMA12 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA12_YMOD                  ((volatile  int32_t *)REG_DMA12_YMOD)                   /* DMA12 Outer Loop Address Increment (2D only) */
-#define pREG_DMA12_DSCPTR_CUR            ((void * volatile *)REG_DMA12_DSCPTR_CUR)               /* DMA12 Current Descriptor Pointer */
-#define pREG_DMA12_DSCPTR_PRV            ((void * volatile *)REG_DMA12_DSCPTR_PRV)               /* DMA12 Previous Initial Descriptor Pointer */
-#define pREG_DMA12_ADDR_CUR              ((void * volatile *)REG_DMA12_ADDR_CUR)                 /* DMA12 Current Address */
-#define pREG_DMA12_STAT                  ((volatile uint32_t *)REG_DMA12_STAT)                   /* DMA12 Status Register */
-#define pREG_DMA12_XCNT_CUR              ((volatile uint32_t *)REG_DMA12_XCNT_CUR)               /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA12_YCNT_CUR              ((volatile uint32_t *)REG_DMA12_YCNT_CUR)               /* DMA12 Current Row Count (2D only) */
-#define pREG_DMA12_BWLCNT                ((volatile uint32_t *)REG_DMA12_BWLCNT)                 /* DMA12 Bandwidth Limit Count */
-#define pREG_DMA12_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWLCNT_CUR)             /* DMA12 Bandwidth Limit Count Current */
-#define pREG_DMA12_BWMCNT                ((volatile uint32_t *)REG_DMA12_BWMCNT)                 /* DMA12 Bandwidth Monitor Count */
-#define pREG_DMA12_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWMCNT_CUR)             /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA13
-   ========================================================================= */
-#define pREG_DMA13_DSCPTR_NXT            ((void * volatile *)REG_DMA13_DSCPTR_NXT)               /* DMA13 Pointer to Next Initial Descriptor */
-#define pREG_DMA13_ADDRSTART             ((void * volatile *)REG_DMA13_ADDRSTART)                /* DMA13 Start Address of Current Buffer */
-#define pREG_DMA13_CFG                   ((volatile uint32_t *)REG_DMA13_CFG)                    /* DMA13 Configuration Register */
-#define pREG_DMA13_XCNT                  ((volatile uint32_t *)REG_DMA13_XCNT)                   /* DMA13 Inner Loop Count Start Value */
-#define pREG_DMA13_XMOD                  ((volatile  int32_t *)REG_DMA13_XMOD)                   /* DMA13 Inner Loop Address Increment */
-#define pREG_DMA13_YCNT                  ((volatile uint32_t *)REG_DMA13_YCNT)                   /* DMA13 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA13_YMOD                  ((volatile  int32_t *)REG_DMA13_YMOD)                   /* DMA13 Outer Loop Address Increment (2D only) */
-#define pREG_DMA13_DSCPTR_CUR            ((void * volatile *)REG_DMA13_DSCPTR_CUR)               /* DMA13 Current Descriptor Pointer */
-#define pREG_DMA13_DSCPTR_PRV            ((void * volatile *)REG_DMA13_DSCPTR_PRV)               /* DMA13 Previous Initial Descriptor Pointer */
-#define pREG_DMA13_ADDR_CUR              ((void * volatile *)REG_DMA13_ADDR_CUR)                 /* DMA13 Current Address */
-#define pREG_DMA13_STAT                  ((volatile uint32_t *)REG_DMA13_STAT)                   /* DMA13 Status Register */
-#define pREG_DMA13_XCNT_CUR              ((volatile uint32_t *)REG_DMA13_XCNT_CUR)               /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA13_YCNT_CUR              ((volatile uint32_t *)REG_DMA13_YCNT_CUR)               /* DMA13 Current Row Count (2D only) */
-#define pREG_DMA13_BWLCNT                ((volatile uint32_t *)REG_DMA13_BWLCNT)                 /* DMA13 Bandwidth Limit Count */
-#define pREG_DMA13_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWLCNT_CUR)             /* DMA13 Bandwidth Limit Count Current */
-#define pREG_DMA13_BWMCNT                ((volatile uint32_t *)REG_DMA13_BWMCNT)                 /* DMA13 Bandwidth Monitor Count */
-#define pREG_DMA13_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWMCNT_CUR)             /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA14
-   ========================================================================= */
-#define pREG_DMA14_DSCPTR_NXT            ((void * volatile *)REG_DMA14_DSCPTR_NXT)               /* DMA14 Pointer to Next Initial Descriptor */
-#define pREG_DMA14_ADDRSTART             ((void * volatile *)REG_DMA14_ADDRSTART)                /* DMA14 Start Address of Current Buffer */
-#define pREG_DMA14_CFG                   ((volatile uint32_t *)REG_DMA14_CFG)                    /* DMA14 Configuration Register */
-#define pREG_DMA14_XCNT                  ((volatile uint32_t *)REG_DMA14_XCNT)                   /* DMA14 Inner Loop Count Start Value */
-#define pREG_DMA14_XMOD                  ((volatile  int32_t *)REG_DMA14_XMOD)                   /* DMA14 Inner Loop Address Increment */
-#define pREG_DMA14_YCNT                  ((volatile uint32_t *)REG_DMA14_YCNT)                   /* DMA14 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA14_YMOD                  ((volatile  int32_t *)REG_DMA14_YMOD)                   /* DMA14 Outer Loop Address Increment (2D only) */
-#define pREG_DMA14_DSCPTR_CUR            ((void * volatile *)REG_DMA14_DSCPTR_CUR)               /* DMA14 Current Descriptor Pointer */
-#define pREG_DMA14_DSCPTR_PRV            ((void * volatile *)REG_DMA14_DSCPTR_PRV)               /* DMA14 Previous Initial Descriptor Pointer */
-#define pREG_DMA14_ADDR_CUR              ((void * volatile *)REG_DMA14_ADDR_CUR)                 /* DMA14 Current Address */
-#define pREG_DMA14_STAT                  ((volatile uint32_t *)REG_DMA14_STAT)                   /* DMA14 Status Register */
-#define pREG_DMA14_XCNT_CUR              ((volatile uint32_t *)REG_DMA14_XCNT_CUR)               /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA14_YCNT_CUR              ((volatile uint32_t *)REG_DMA14_YCNT_CUR)               /* DMA14 Current Row Count (2D only) */
-#define pREG_DMA14_BWLCNT                ((volatile uint32_t *)REG_DMA14_BWLCNT)                 /* DMA14 Bandwidth Limit Count */
-#define pREG_DMA14_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWLCNT_CUR)             /* DMA14 Bandwidth Limit Count Current */
-#define pREG_DMA14_BWMCNT                ((volatile uint32_t *)REG_DMA14_BWMCNT)                 /* DMA14 Bandwidth Monitor Count */
-#define pREG_DMA14_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWMCNT_CUR)             /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA15
-   ========================================================================= */
-#define pREG_DMA15_DSCPTR_NXT            ((void * volatile *)REG_DMA15_DSCPTR_NXT)               /* DMA15 Pointer to Next Initial Descriptor */
-#define pREG_DMA15_ADDRSTART             ((void * volatile *)REG_DMA15_ADDRSTART)                /* DMA15 Start Address of Current Buffer */
-#define pREG_DMA15_CFG                   ((volatile uint32_t *)REG_DMA15_CFG)                    /* DMA15 Configuration Register */
-#define pREG_DMA15_XCNT                  ((volatile uint32_t *)REG_DMA15_XCNT)                   /* DMA15 Inner Loop Count Start Value */
-#define pREG_DMA15_XMOD                  ((volatile  int32_t *)REG_DMA15_XMOD)                   /* DMA15 Inner Loop Address Increment */
-#define pREG_DMA15_YCNT                  ((volatile uint32_t *)REG_DMA15_YCNT)                   /* DMA15 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA15_YMOD                  ((volatile  int32_t *)REG_DMA15_YMOD)                   /* DMA15 Outer Loop Address Increment (2D only) */
-#define pREG_DMA15_DSCPTR_CUR            ((void * volatile *)REG_DMA15_DSCPTR_CUR)               /* DMA15 Current Descriptor Pointer */
-#define pREG_DMA15_DSCPTR_PRV            ((void * volatile *)REG_DMA15_DSCPTR_PRV)               /* DMA15 Previous Initial Descriptor Pointer */
-#define pREG_DMA15_ADDR_CUR              ((void * volatile *)REG_DMA15_ADDR_CUR)                 /* DMA15 Current Address */
-#define pREG_DMA15_STAT                  ((volatile uint32_t *)REG_DMA15_STAT)                   /* DMA15 Status Register */
-#define pREG_DMA15_XCNT_CUR              ((volatile uint32_t *)REG_DMA15_XCNT_CUR)               /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA15_YCNT_CUR              ((volatile uint32_t *)REG_DMA15_YCNT_CUR)               /* DMA15 Current Row Count (2D only) */
-#define pREG_DMA15_BWLCNT                ((volatile uint32_t *)REG_DMA15_BWLCNT)                 /* DMA15 Bandwidth Limit Count */
-#define pREG_DMA15_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWLCNT_CUR)             /* DMA15 Bandwidth Limit Count Current */
-#define pREG_DMA15_BWMCNT                ((volatile uint32_t *)REG_DMA15_BWMCNT)                 /* DMA15 Bandwidth Monitor Count */
-#define pREG_DMA15_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWMCNT_CUR)             /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA16
-   ========================================================================= */
-#define pREG_DMA16_DSCPTR_NXT            ((void * volatile *)REG_DMA16_DSCPTR_NXT)               /* DMA16 Pointer to Next Initial Descriptor */
-#define pREG_DMA16_ADDRSTART             ((void * volatile *)REG_DMA16_ADDRSTART)                /* DMA16 Start Address of Current Buffer */
-#define pREG_DMA16_CFG                   ((volatile uint32_t *)REG_DMA16_CFG)                    /* DMA16 Configuration Register */
-#define pREG_DMA16_XCNT                  ((volatile uint32_t *)REG_DMA16_XCNT)                   /* DMA16 Inner Loop Count Start Value */
-#define pREG_DMA16_XMOD                  ((volatile  int32_t *)REG_DMA16_XMOD)                   /* DMA16 Inner Loop Address Increment */
-#define pREG_DMA16_YCNT                  ((volatile uint32_t *)REG_DMA16_YCNT)                   /* DMA16 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA16_YMOD                  ((volatile  int32_t *)REG_DMA16_YMOD)                   /* DMA16 Outer Loop Address Increment (2D only) */
-#define pREG_DMA16_DSCPTR_CUR            ((void * volatile *)REG_DMA16_DSCPTR_CUR)               /* DMA16 Current Descriptor Pointer */
-#define pREG_DMA16_DSCPTR_PRV            ((void * volatile *)REG_DMA16_DSCPTR_PRV)               /* DMA16 Previous Initial Descriptor Pointer */
-#define pREG_DMA16_ADDR_CUR              ((void * volatile *)REG_DMA16_ADDR_CUR)                 /* DMA16 Current Address */
-#define pREG_DMA16_STAT                  ((volatile uint32_t *)REG_DMA16_STAT)                   /* DMA16 Status Register */
-#define pREG_DMA16_XCNT_CUR              ((volatile uint32_t *)REG_DMA16_XCNT_CUR)               /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA16_YCNT_CUR              ((volatile uint32_t *)REG_DMA16_YCNT_CUR)               /* DMA16 Current Row Count (2D only) */
-#define pREG_DMA16_BWLCNT                ((volatile uint32_t *)REG_DMA16_BWLCNT)                 /* DMA16 Bandwidth Limit Count */
-#define pREG_DMA16_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWLCNT_CUR)             /* DMA16 Bandwidth Limit Count Current */
-#define pREG_DMA16_BWMCNT                ((volatile uint32_t *)REG_DMA16_BWMCNT)                 /* DMA16 Bandwidth Monitor Count */
-#define pREG_DMA16_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWMCNT_CUR)             /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA17
-   ========================================================================= */
-#define pREG_DMA17_DSCPTR_NXT            ((void * volatile *)REG_DMA17_DSCPTR_NXT)               /* DMA17 Pointer to Next Initial Descriptor */
-#define pREG_DMA17_ADDRSTART             ((void * volatile *)REG_DMA17_ADDRSTART)                /* DMA17 Start Address of Current Buffer */
-#define pREG_DMA17_CFG                   ((volatile uint32_t *)REG_DMA17_CFG)                    /* DMA17 Configuration Register */
-#define pREG_DMA17_XCNT                  ((volatile uint32_t *)REG_DMA17_XCNT)                   /* DMA17 Inner Loop Count Start Value */
-#define pREG_DMA17_XMOD                  ((volatile  int32_t *)REG_DMA17_XMOD)                   /* DMA17 Inner Loop Address Increment */
-#define pREG_DMA17_YCNT                  ((volatile uint32_t *)REG_DMA17_YCNT)                   /* DMA17 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA17_YMOD                  ((volatile  int32_t *)REG_DMA17_YMOD)                   /* DMA17 Outer Loop Address Increment (2D only) */
-#define pREG_DMA17_DSCPTR_CUR            ((void * volatile *)REG_DMA17_DSCPTR_CUR)               /* DMA17 Current Descriptor Pointer */
-#define pREG_DMA17_DSCPTR_PRV            ((void * volatile *)REG_DMA17_DSCPTR_PRV)               /* DMA17 Previous Initial Descriptor Pointer */
-#define pREG_DMA17_ADDR_CUR              ((void * volatile *)REG_DMA17_ADDR_CUR)                 /* DMA17 Current Address */
-#define pREG_DMA17_STAT                  ((volatile uint32_t *)REG_DMA17_STAT)                   /* DMA17 Status Register */
-#define pREG_DMA17_XCNT_CUR              ((volatile uint32_t *)REG_DMA17_XCNT_CUR)               /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA17_YCNT_CUR              ((volatile uint32_t *)REG_DMA17_YCNT_CUR)               /* DMA17 Current Row Count (2D only) */
-#define pREG_DMA17_BWLCNT                ((volatile uint32_t *)REG_DMA17_BWLCNT)                 /* DMA17 Bandwidth Limit Count */
-#define pREG_DMA17_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWLCNT_CUR)             /* DMA17 Bandwidth Limit Count Current */
-#define pREG_DMA17_BWMCNT                ((volatile uint32_t *)REG_DMA17_BWMCNT)                 /* DMA17 Bandwidth Monitor Count */
-#define pREG_DMA17_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWMCNT_CUR)             /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA18
-   ========================================================================= */
-#define pREG_DMA18_DSCPTR_NXT            ((void * volatile *)REG_DMA18_DSCPTR_NXT)               /* DMA18 Pointer to Next Initial Descriptor */
-#define pREG_DMA18_ADDRSTART             ((void * volatile *)REG_DMA18_ADDRSTART)                /* DMA18 Start Address of Current Buffer */
-#define pREG_DMA18_CFG                   ((volatile uint32_t *)REG_DMA18_CFG)                    /* DMA18 Configuration Register */
-#define pREG_DMA18_XCNT                  ((volatile uint32_t *)REG_DMA18_XCNT)                   /* DMA18 Inner Loop Count Start Value */
-#define pREG_DMA18_XMOD                  ((volatile  int32_t *)REG_DMA18_XMOD)                   /* DMA18 Inner Loop Address Increment */
-#define pREG_DMA18_YCNT                  ((volatile uint32_t *)REG_DMA18_YCNT)                   /* DMA18 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA18_YMOD                  ((volatile  int32_t *)REG_DMA18_YMOD)                   /* DMA18 Outer Loop Address Increment (2D only) */
-#define pREG_DMA18_DSCPTR_CUR            ((void * volatile *)REG_DMA18_DSCPTR_CUR)               /* DMA18 Current Descriptor Pointer */
-#define pREG_DMA18_DSCPTR_PRV            ((void * volatile *)REG_DMA18_DSCPTR_PRV)               /* DMA18 Previous Initial Descriptor Pointer */
-#define pREG_DMA18_ADDR_CUR              ((void * volatile *)REG_DMA18_ADDR_CUR)                 /* DMA18 Current Address */
-#define pREG_DMA18_STAT                  ((volatile uint32_t *)REG_DMA18_STAT)                   /* DMA18 Status Register */
-#define pREG_DMA18_XCNT_CUR              ((volatile uint32_t *)REG_DMA18_XCNT_CUR)               /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA18_YCNT_CUR              ((volatile uint32_t *)REG_DMA18_YCNT_CUR)               /* DMA18 Current Row Count (2D only) */
-#define pREG_DMA18_BWLCNT                ((volatile uint32_t *)REG_DMA18_BWLCNT)                 /* DMA18 Bandwidth Limit Count */
-#define pREG_DMA18_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWLCNT_CUR)             /* DMA18 Bandwidth Limit Count Current */
-#define pREG_DMA18_BWMCNT                ((volatile uint32_t *)REG_DMA18_BWMCNT)                 /* DMA18 Bandwidth Monitor Count */
-#define pREG_DMA18_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWMCNT_CUR)             /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA19
-   ========================================================================= */
-#define pREG_DMA19_DSCPTR_NXT            ((void * volatile *)REG_DMA19_DSCPTR_NXT)               /* DMA19 Pointer to Next Initial Descriptor */
-#define pREG_DMA19_ADDRSTART             ((void * volatile *)REG_DMA19_ADDRSTART)                /* DMA19 Start Address of Current Buffer */
-#define pREG_DMA19_CFG                   ((volatile uint32_t *)REG_DMA19_CFG)                    /* DMA19 Configuration Register */
-#define pREG_DMA19_XCNT                  ((volatile uint32_t *)REG_DMA19_XCNT)                   /* DMA19 Inner Loop Count Start Value */
-#define pREG_DMA19_XMOD                  ((volatile  int32_t *)REG_DMA19_XMOD)                   /* DMA19 Inner Loop Address Increment */
-#define pREG_DMA19_YCNT                  ((volatile uint32_t *)REG_DMA19_YCNT)                   /* DMA19 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA19_YMOD                  ((volatile  int32_t *)REG_DMA19_YMOD)                   /* DMA19 Outer Loop Address Increment (2D only) */
-#define pREG_DMA19_DSCPTR_CUR            ((void * volatile *)REG_DMA19_DSCPTR_CUR)               /* DMA19 Current Descriptor Pointer */
-#define pREG_DMA19_DSCPTR_PRV            ((void * volatile *)REG_DMA19_DSCPTR_PRV)               /* DMA19 Previous Initial Descriptor Pointer */
-#define pREG_DMA19_ADDR_CUR              ((void * volatile *)REG_DMA19_ADDR_CUR)                 /* DMA19 Current Address */
-#define pREG_DMA19_STAT                  ((volatile uint32_t *)REG_DMA19_STAT)                   /* DMA19 Status Register */
-#define pREG_DMA19_XCNT_CUR              ((volatile uint32_t *)REG_DMA19_XCNT_CUR)               /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA19_YCNT_CUR              ((volatile uint32_t *)REG_DMA19_YCNT_CUR)               /* DMA19 Current Row Count (2D only) */
-#define pREG_DMA19_BWLCNT                ((volatile uint32_t *)REG_DMA19_BWLCNT)                 /* DMA19 Bandwidth Limit Count */
-#define pREG_DMA19_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWLCNT_CUR)             /* DMA19 Bandwidth Limit Count Current */
-#define pREG_DMA19_BWMCNT                ((volatile uint32_t *)REG_DMA19_BWMCNT)                 /* DMA19 Bandwidth Monitor Count */
-#define pREG_DMA19_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWMCNT_CUR)             /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA20
-   ========================================================================= */
-#define pREG_DMA20_DSCPTR_NXT            ((void * volatile *)REG_DMA20_DSCPTR_NXT)               /* DMA20 Pointer to Next Initial Descriptor */
-#define pREG_DMA20_ADDRSTART             ((void * volatile *)REG_DMA20_ADDRSTART)                /* DMA20 Start Address of Current Buffer */
-#define pREG_DMA20_CFG                   ((volatile uint32_t *)REG_DMA20_CFG)                    /* DMA20 Configuration Register */
-#define pREG_DMA20_XCNT                  ((volatile uint32_t *)REG_DMA20_XCNT)                   /* DMA20 Inner Loop Count Start Value */
-#define pREG_DMA20_XMOD                  ((volatile  int32_t *)REG_DMA20_XMOD)                   /* DMA20 Inner Loop Address Increment */
-#define pREG_DMA20_YCNT                  ((volatile uint32_t *)REG_DMA20_YCNT)                   /* DMA20 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA20_YMOD                  ((volatile  int32_t *)REG_DMA20_YMOD)                   /* DMA20 Outer Loop Address Increment (2D only) */
-#define pREG_DMA20_DSCPTR_CUR            ((void * volatile *)REG_DMA20_DSCPTR_CUR)               /* DMA20 Current Descriptor Pointer */
-#define pREG_DMA20_DSCPTR_PRV            ((void * volatile *)REG_DMA20_DSCPTR_PRV)               /* DMA20 Previous Initial Descriptor Pointer */
-#define pREG_DMA20_ADDR_CUR              ((void * volatile *)REG_DMA20_ADDR_CUR)                 /* DMA20 Current Address */
-#define pREG_DMA20_STAT                  ((volatile uint32_t *)REG_DMA20_STAT)                   /* DMA20 Status Register */
-#define pREG_DMA20_XCNT_CUR              ((volatile uint32_t *)REG_DMA20_XCNT_CUR)               /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA20_YCNT_CUR              ((volatile uint32_t *)REG_DMA20_YCNT_CUR)               /* DMA20 Current Row Count (2D only) */
-#define pREG_DMA20_BWLCNT                ((volatile uint32_t *)REG_DMA20_BWLCNT)                 /* DMA20 Bandwidth Limit Count */
-#define pREG_DMA20_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWLCNT_CUR)             /* DMA20 Bandwidth Limit Count Current */
-#define pREG_DMA20_BWMCNT                ((volatile uint32_t *)REG_DMA20_BWMCNT)                 /* DMA20 Bandwidth Monitor Count */
-#define pREG_DMA20_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWMCNT_CUR)             /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA21
-   ========================================================================= */
-#define pREG_DMA21_DSCPTR_NXT            ((void * volatile *)REG_DMA21_DSCPTR_NXT)               /* DMA21 Pointer to Next Initial Descriptor */
-#define pREG_DMA21_ADDRSTART             ((void * volatile *)REG_DMA21_ADDRSTART)                /* DMA21 Start Address of Current Buffer */
-#define pREG_DMA21_CFG                   ((volatile uint32_t *)REG_DMA21_CFG)                    /* DMA21 Configuration Register */
-#define pREG_DMA21_XCNT                  ((volatile uint32_t *)REG_DMA21_XCNT)                   /* DMA21 Inner Loop Count Start Value */
-#define pREG_DMA21_XMOD                  ((volatile  int32_t *)REG_DMA21_XMOD)                   /* DMA21 Inner Loop Address Increment */
-#define pREG_DMA21_YCNT                  ((volatile uint32_t *)REG_DMA21_YCNT)                   /* DMA21 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA21_YMOD                  ((volatile  int32_t *)REG_DMA21_YMOD)                   /* DMA21 Outer Loop Address Increment (2D only) */
-#define pREG_DMA21_DSCPTR_CUR            ((void * volatile *)REG_DMA21_DSCPTR_CUR)               /* DMA21 Current Descriptor Pointer */
-#define pREG_DMA21_DSCPTR_PRV            ((void * volatile *)REG_DMA21_DSCPTR_PRV)               /* DMA21 Previous Initial Descriptor Pointer */
-#define pREG_DMA21_ADDR_CUR              ((void * volatile *)REG_DMA21_ADDR_CUR)                 /* DMA21 Current Address */
-#define pREG_DMA21_STAT                  ((volatile uint32_t *)REG_DMA21_STAT)                   /* DMA21 Status Register */
-#define pREG_DMA21_XCNT_CUR              ((volatile uint32_t *)REG_DMA21_XCNT_CUR)               /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA21_YCNT_CUR              ((volatile uint32_t *)REG_DMA21_YCNT_CUR)               /* DMA21 Current Row Count (2D only) */
-#define pREG_DMA21_BWLCNT                ((volatile uint32_t *)REG_DMA21_BWLCNT)                 /* DMA21 Bandwidth Limit Count */
-#define pREG_DMA21_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWLCNT_CUR)             /* DMA21 Bandwidth Limit Count Current */
-#define pREG_DMA21_BWMCNT                ((volatile uint32_t *)REG_DMA21_BWMCNT)                 /* DMA21 Bandwidth Monitor Count */
-#define pREG_DMA21_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWMCNT_CUR)             /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA22
-   ========================================================================= */
-#define pREG_DMA22_DSCPTR_NXT            ((void * volatile *)REG_DMA22_DSCPTR_NXT)               /* DMA22 Pointer to Next Initial Descriptor */
-#define pREG_DMA22_ADDRSTART             ((void * volatile *)REG_DMA22_ADDRSTART)                /* DMA22 Start Address of Current Buffer */
-#define pREG_DMA22_CFG                   ((volatile uint32_t *)REG_DMA22_CFG)                    /* DMA22 Configuration Register */
-#define pREG_DMA22_XCNT                  ((volatile uint32_t *)REG_DMA22_XCNT)                   /* DMA22 Inner Loop Count Start Value */
-#define pREG_DMA22_XMOD                  ((volatile  int32_t *)REG_DMA22_XMOD)                   /* DMA22 Inner Loop Address Increment */
-#define pREG_DMA22_YCNT                  ((volatile uint32_t *)REG_DMA22_YCNT)                   /* DMA22 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA22_YMOD                  ((volatile  int32_t *)REG_DMA22_YMOD)                   /* DMA22 Outer Loop Address Increment (2D only) */
-#define pREG_DMA22_DSCPTR_CUR            ((void * volatile *)REG_DMA22_DSCPTR_CUR)               /* DMA22 Current Descriptor Pointer */
-#define pREG_DMA22_DSCPTR_PRV            ((void * volatile *)REG_DMA22_DSCPTR_PRV)               /* DMA22 Previous Initial Descriptor Pointer */
-#define pREG_DMA22_ADDR_CUR              ((void * volatile *)REG_DMA22_ADDR_CUR)                 /* DMA22 Current Address */
-#define pREG_DMA22_STAT                  ((volatile uint32_t *)REG_DMA22_STAT)                   /* DMA22 Status Register */
-#define pREG_DMA22_XCNT_CUR              ((volatile uint32_t *)REG_DMA22_XCNT_CUR)               /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA22_YCNT_CUR              ((volatile uint32_t *)REG_DMA22_YCNT_CUR)               /* DMA22 Current Row Count (2D only) */
-#define pREG_DMA22_BWLCNT                ((volatile uint32_t *)REG_DMA22_BWLCNT)                 /* DMA22 Bandwidth Limit Count */
-#define pREG_DMA22_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWLCNT_CUR)             /* DMA22 Bandwidth Limit Count Current */
-#define pREG_DMA22_BWMCNT                ((volatile uint32_t *)REG_DMA22_BWMCNT)                 /* DMA22 Bandwidth Monitor Count */
-#define pREG_DMA22_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWMCNT_CUR)             /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA23
-   ========================================================================= */
-#define pREG_DMA23_DSCPTR_NXT            ((void * volatile *)REG_DMA23_DSCPTR_NXT)               /* DMA23 Pointer to Next Initial Descriptor */
-#define pREG_DMA23_ADDRSTART             ((void * volatile *)REG_DMA23_ADDRSTART)                /* DMA23 Start Address of Current Buffer */
-#define pREG_DMA23_CFG                   ((volatile uint32_t *)REG_DMA23_CFG)                    /* DMA23 Configuration Register */
-#define pREG_DMA23_XCNT                  ((volatile uint32_t *)REG_DMA23_XCNT)                   /* DMA23 Inner Loop Count Start Value */
-#define pREG_DMA23_XMOD                  ((volatile  int32_t *)REG_DMA23_XMOD)                   /* DMA23 Inner Loop Address Increment */
-#define pREG_DMA23_YCNT                  ((volatile uint32_t *)REG_DMA23_YCNT)                   /* DMA23 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA23_YMOD                  ((volatile  int32_t *)REG_DMA23_YMOD)                   /* DMA23 Outer Loop Address Increment (2D only) */
-#define pREG_DMA23_DSCPTR_CUR            ((void * volatile *)REG_DMA23_DSCPTR_CUR)               /* DMA23 Current Descriptor Pointer */
-#define pREG_DMA23_DSCPTR_PRV            ((void * volatile *)REG_DMA23_DSCPTR_PRV)               /* DMA23 Previous Initial Descriptor Pointer */
-#define pREG_DMA23_ADDR_CUR              ((void * volatile *)REG_DMA23_ADDR_CUR)                 /* DMA23 Current Address */
-#define pREG_DMA23_STAT                  ((volatile uint32_t *)REG_DMA23_STAT)                   /* DMA23 Status Register */
-#define pREG_DMA23_XCNT_CUR              ((volatile uint32_t *)REG_DMA23_XCNT_CUR)               /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA23_YCNT_CUR              ((volatile uint32_t *)REG_DMA23_YCNT_CUR)               /* DMA23 Current Row Count (2D only) */
-#define pREG_DMA23_BWLCNT                ((volatile uint32_t *)REG_DMA23_BWLCNT)                 /* DMA23 Bandwidth Limit Count */
-#define pREG_DMA23_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWLCNT_CUR)             /* DMA23 Bandwidth Limit Count Current */
-#define pREG_DMA23_BWMCNT                ((volatile uint32_t *)REG_DMA23_BWMCNT)                 /* DMA23 Bandwidth Monitor Count */
-#define pREG_DMA23_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWMCNT_CUR)             /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA24
-   ========================================================================= */
-#define pREG_DMA24_DSCPTR_NXT            ((void * volatile *)REG_DMA24_DSCPTR_NXT)               /* DMA24 Pointer to Next Initial Descriptor */
-#define pREG_DMA24_ADDRSTART             ((void * volatile *)REG_DMA24_ADDRSTART)                /* DMA24 Start Address of Current Buffer */
-#define pREG_DMA24_CFG                   ((volatile uint32_t *)REG_DMA24_CFG)                    /* DMA24 Configuration Register */
-#define pREG_DMA24_XCNT                  ((volatile uint32_t *)REG_DMA24_XCNT)                   /* DMA24 Inner Loop Count Start Value */
-#define pREG_DMA24_XMOD                  ((volatile  int32_t *)REG_DMA24_XMOD)                   /* DMA24 Inner Loop Address Increment */
-#define pREG_DMA24_YCNT                  ((volatile uint32_t *)REG_DMA24_YCNT)                   /* DMA24 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA24_YMOD                  ((volatile  int32_t *)REG_DMA24_YMOD)                   /* DMA24 Outer Loop Address Increment (2D only) */
-#define pREG_DMA24_DSCPTR_CUR            ((void * volatile *)REG_DMA24_DSCPTR_CUR)               /* DMA24 Current Descriptor Pointer */
-#define pREG_DMA24_DSCPTR_PRV            ((void * volatile *)REG_DMA24_DSCPTR_PRV)               /* DMA24 Previous Initial Descriptor Pointer */
-#define pREG_DMA24_ADDR_CUR              ((void * volatile *)REG_DMA24_ADDR_CUR)                 /* DMA24 Current Address */
-#define pREG_DMA24_STAT                  ((volatile uint32_t *)REG_DMA24_STAT)                   /* DMA24 Status Register */
-#define pREG_DMA24_XCNT_CUR              ((volatile uint32_t *)REG_DMA24_XCNT_CUR)               /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA24_YCNT_CUR              ((volatile uint32_t *)REG_DMA24_YCNT_CUR)               /* DMA24 Current Row Count (2D only) */
-#define pREG_DMA24_BWLCNT                ((volatile uint32_t *)REG_DMA24_BWLCNT)                 /* DMA24 Bandwidth Limit Count */
-#define pREG_DMA24_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWLCNT_CUR)             /* DMA24 Bandwidth Limit Count Current */
-#define pREG_DMA24_BWMCNT                ((volatile uint32_t *)REG_DMA24_BWMCNT)                 /* DMA24 Bandwidth Monitor Count */
-#define pREG_DMA24_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWMCNT_CUR)             /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA25
-   ========================================================================= */
-#define pREG_DMA25_DSCPTR_NXT            ((void * volatile *)REG_DMA25_DSCPTR_NXT)               /* DMA25 Pointer to Next Initial Descriptor */
-#define pREG_DMA25_ADDRSTART             ((void * volatile *)REG_DMA25_ADDRSTART)                /* DMA25 Start Address of Current Buffer */
-#define pREG_DMA25_CFG                   ((volatile uint32_t *)REG_DMA25_CFG)                    /* DMA25 Configuration Register */
-#define pREG_DMA25_XCNT                  ((volatile uint32_t *)REG_DMA25_XCNT)                   /* DMA25 Inner Loop Count Start Value */
-#define pREG_DMA25_XMOD                  ((volatile  int32_t *)REG_DMA25_XMOD)                   /* DMA25 Inner Loop Address Increment */
-#define pREG_DMA25_YCNT                  ((volatile uint32_t *)REG_DMA25_YCNT)                   /* DMA25 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA25_YMOD                  ((volatile  int32_t *)REG_DMA25_YMOD)                   /* DMA25 Outer Loop Address Increment (2D only) */
-#define pREG_DMA25_DSCPTR_CUR            ((void * volatile *)REG_DMA25_DSCPTR_CUR)               /* DMA25 Current Descriptor Pointer */
-#define pREG_DMA25_DSCPTR_PRV            ((void * volatile *)REG_DMA25_DSCPTR_PRV)               /* DMA25 Previous Initial Descriptor Pointer */
-#define pREG_DMA25_ADDR_CUR              ((void * volatile *)REG_DMA25_ADDR_CUR)                 /* DMA25 Current Address */
-#define pREG_DMA25_STAT                  ((volatile uint32_t *)REG_DMA25_STAT)                   /* DMA25 Status Register */
-#define pREG_DMA25_XCNT_CUR              ((volatile uint32_t *)REG_DMA25_XCNT_CUR)               /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA25_YCNT_CUR              ((volatile uint32_t *)REG_DMA25_YCNT_CUR)               /* DMA25 Current Row Count (2D only) */
-#define pREG_DMA25_BWLCNT                ((volatile uint32_t *)REG_DMA25_BWLCNT)                 /* DMA25 Bandwidth Limit Count */
-#define pREG_DMA25_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWLCNT_CUR)             /* DMA25 Bandwidth Limit Count Current */
-#define pREG_DMA25_BWMCNT                ((volatile uint32_t *)REG_DMA25_BWMCNT)                 /* DMA25 Bandwidth Monitor Count */
-#define pREG_DMA25_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWMCNT_CUR)             /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA26
-   ========================================================================= */
-#define pREG_DMA26_DSCPTR_NXT            ((void * volatile *)REG_DMA26_DSCPTR_NXT)               /* DMA26 Pointer to Next Initial Descriptor */
-#define pREG_DMA26_ADDRSTART             ((void * volatile *)REG_DMA26_ADDRSTART)                /* DMA26 Start Address of Current Buffer */
-#define pREG_DMA26_CFG                   ((volatile uint32_t *)REG_DMA26_CFG)                    /* DMA26 Configuration Register */
-#define pREG_DMA26_XCNT                  ((volatile uint32_t *)REG_DMA26_XCNT)                   /* DMA26 Inner Loop Count Start Value */
-#define pREG_DMA26_XMOD                  ((volatile  int32_t *)REG_DMA26_XMOD)                   /* DMA26 Inner Loop Address Increment */
-#define pREG_DMA26_YCNT                  ((volatile uint32_t *)REG_DMA26_YCNT)                   /* DMA26 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA26_YMOD                  ((volatile  int32_t *)REG_DMA26_YMOD)                   /* DMA26 Outer Loop Address Increment (2D only) */
-#define pREG_DMA26_DSCPTR_CUR            ((void * volatile *)REG_DMA26_DSCPTR_CUR)               /* DMA26 Current Descriptor Pointer */
-#define pREG_DMA26_DSCPTR_PRV            ((void * volatile *)REG_DMA26_DSCPTR_PRV)               /* DMA26 Previous Initial Descriptor Pointer */
-#define pREG_DMA26_ADDR_CUR              ((void * volatile *)REG_DMA26_ADDR_CUR)                 /* DMA26 Current Address */
-#define pREG_DMA26_STAT                  ((volatile uint32_t *)REG_DMA26_STAT)                   /* DMA26 Status Register */
-#define pREG_DMA26_XCNT_CUR              ((volatile uint32_t *)REG_DMA26_XCNT_CUR)               /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA26_YCNT_CUR              ((volatile uint32_t *)REG_DMA26_YCNT_CUR)               /* DMA26 Current Row Count (2D only) */
-#define pREG_DMA26_BWLCNT                ((volatile uint32_t *)REG_DMA26_BWLCNT)                 /* DMA26 Bandwidth Limit Count */
-#define pREG_DMA26_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWLCNT_CUR)             /* DMA26 Bandwidth Limit Count Current */
-#define pREG_DMA26_BWMCNT                ((volatile uint32_t *)REG_DMA26_BWMCNT)                 /* DMA26 Bandwidth Monitor Count */
-#define pREG_DMA26_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWMCNT_CUR)             /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA27
-   ========================================================================= */
-#define pREG_DMA27_DSCPTR_NXT            ((void * volatile *)REG_DMA27_DSCPTR_NXT)               /* DMA27 Pointer to Next Initial Descriptor */
-#define pREG_DMA27_ADDRSTART             ((void * volatile *)REG_DMA27_ADDRSTART)                /* DMA27 Start Address of Current Buffer */
-#define pREG_DMA27_CFG                   ((volatile uint32_t *)REG_DMA27_CFG)                    /* DMA27 Configuration Register */
-#define pREG_DMA27_XCNT                  ((volatile uint32_t *)REG_DMA27_XCNT)                   /* DMA27 Inner Loop Count Start Value */
-#define pREG_DMA27_XMOD                  ((volatile  int32_t *)REG_DMA27_XMOD)                   /* DMA27 Inner Loop Address Increment */
-#define pREG_DMA27_YCNT                  ((volatile uint32_t *)REG_DMA27_YCNT)                   /* DMA27 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA27_YMOD                  ((volatile  int32_t *)REG_DMA27_YMOD)                   /* DMA27 Outer Loop Address Increment (2D only) */
-#define pREG_DMA27_DSCPTR_CUR            ((void * volatile *)REG_DMA27_DSCPTR_CUR)               /* DMA27 Current Descriptor Pointer */
-#define pREG_DMA27_DSCPTR_PRV            ((void * volatile *)REG_DMA27_DSCPTR_PRV)               /* DMA27 Previous Initial Descriptor Pointer */
-#define pREG_DMA27_ADDR_CUR              ((void * volatile *)REG_DMA27_ADDR_CUR)                 /* DMA27 Current Address */
-#define pREG_DMA27_STAT                  ((volatile uint32_t *)REG_DMA27_STAT)                   /* DMA27 Status Register */
-#define pREG_DMA27_XCNT_CUR              ((volatile uint32_t *)REG_DMA27_XCNT_CUR)               /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA27_YCNT_CUR              ((volatile uint32_t *)REG_DMA27_YCNT_CUR)               /* DMA27 Current Row Count (2D only) */
-#define pREG_DMA27_BWLCNT                ((volatile uint32_t *)REG_DMA27_BWLCNT)                 /* DMA27 Bandwidth Limit Count */
-#define pREG_DMA27_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWLCNT_CUR)             /* DMA27 Bandwidth Limit Count Current */
-#define pREG_DMA27_BWMCNT                ((volatile uint32_t *)REG_DMA27_BWMCNT)                 /* DMA27 Bandwidth Monitor Count */
-#define pREG_DMA27_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWMCNT_CUR)             /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA28
-   ========================================================================= */
-#define pREG_DMA28_DSCPTR_NXT            ((void * volatile *)REG_DMA28_DSCPTR_NXT)               /* DMA28 Pointer to Next Initial Descriptor */
-#define pREG_DMA28_ADDRSTART             ((void * volatile *)REG_DMA28_ADDRSTART)                /* DMA28 Start Address of Current Buffer */
-#define pREG_DMA28_CFG                   ((volatile uint32_t *)REG_DMA28_CFG)                    /* DMA28 Configuration Register */
-#define pREG_DMA28_XCNT                  ((volatile uint32_t *)REG_DMA28_XCNT)                   /* DMA28 Inner Loop Count Start Value */
-#define pREG_DMA28_XMOD                  ((volatile  int32_t *)REG_DMA28_XMOD)                   /* DMA28 Inner Loop Address Increment */
-#define pREG_DMA28_YCNT                  ((volatile uint32_t *)REG_DMA28_YCNT)                   /* DMA28 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA28_YMOD                  ((volatile  int32_t *)REG_DMA28_YMOD)                   /* DMA28 Outer Loop Address Increment (2D only) */
-#define pREG_DMA28_DSCPTR_CUR            ((void * volatile *)REG_DMA28_DSCPTR_CUR)               /* DMA28 Current Descriptor Pointer */
-#define pREG_DMA28_DSCPTR_PRV            ((void * volatile *)REG_DMA28_DSCPTR_PRV)               /* DMA28 Previous Initial Descriptor Pointer */
-#define pREG_DMA28_ADDR_CUR              ((void * volatile *)REG_DMA28_ADDR_CUR)                 /* DMA28 Current Address */
-#define pREG_DMA28_STAT                  ((volatile uint32_t *)REG_DMA28_STAT)                   /* DMA28 Status Register */
-#define pREG_DMA28_XCNT_CUR              ((volatile uint32_t *)REG_DMA28_XCNT_CUR)               /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA28_YCNT_CUR              ((volatile uint32_t *)REG_DMA28_YCNT_CUR)               /* DMA28 Current Row Count (2D only) */
-#define pREG_DMA28_BWLCNT                ((volatile uint32_t *)REG_DMA28_BWLCNT)                 /* DMA28 Bandwidth Limit Count */
-#define pREG_DMA28_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWLCNT_CUR)             /* DMA28 Bandwidth Limit Count Current */
-#define pREG_DMA28_BWMCNT                ((volatile uint32_t *)REG_DMA28_BWMCNT)                 /* DMA28 Bandwidth Monitor Count */
-#define pREG_DMA28_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWMCNT_CUR)             /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA29
-   ========================================================================= */
-#define pREG_DMA29_DSCPTR_NXT            ((void * volatile *)REG_DMA29_DSCPTR_NXT)               /* DMA29 Pointer to Next Initial Descriptor */
-#define pREG_DMA29_ADDRSTART             ((void * volatile *)REG_DMA29_ADDRSTART)                /* DMA29 Start Address of Current Buffer */
-#define pREG_DMA29_CFG                   ((volatile uint32_t *)REG_DMA29_CFG)                    /* DMA29 Configuration Register */
-#define pREG_DMA29_XCNT                  ((volatile uint32_t *)REG_DMA29_XCNT)                   /* DMA29 Inner Loop Count Start Value */
-#define pREG_DMA29_XMOD                  ((volatile  int32_t *)REG_DMA29_XMOD)                   /* DMA29 Inner Loop Address Increment */
-#define pREG_DMA29_YCNT                  ((volatile uint32_t *)REG_DMA29_YCNT)                   /* DMA29 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA29_YMOD                  ((volatile  int32_t *)REG_DMA29_YMOD)                   /* DMA29 Outer Loop Address Increment (2D only) */
-#define pREG_DMA29_DSCPTR_CUR            ((void * volatile *)REG_DMA29_DSCPTR_CUR)               /* DMA29 Current Descriptor Pointer */
-#define pREG_DMA29_DSCPTR_PRV            ((void * volatile *)REG_DMA29_DSCPTR_PRV)               /* DMA29 Previous Initial Descriptor Pointer */
-#define pREG_DMA29_ADDR_CUR              ((void * volatile *)REG_DMA29_ADDR_CUR)                 /* DMA29 Current Address */
-#define pREG_DMA29_STAT                  ((volatile uint32_t *)REG_DMA29_STAT)                   /* DMA29 Status Register */
-#define pREG_DMA29_XCNT_CUR              ((volatile uint32_t *)REG_DMA29_XCNT_CUR)               /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA29_YCNT_CUR              ((volatile uint32_t *)REG_DMA29_YCNT_CUR)               /* DMA29 Current Row Count (2D only) */
-#define pREG_DMA29_BWLCNT                ((volatile uint32_t *)REG_DMA29_BWLCNT)                 /* DMA29 Bandwidth Limit Count */
-#define pREG_DMA29_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWLCNT_CUR)             /* DMA29 Bandwidth Limit Count Current */
-#define pREG_DMA29_BWMCNT                ((volatile uint32_t *)REG_DMA29_BWMCNT)                 /* DMA29 Bandwidth Monitor Count */
-#define pREG_DMA29_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWMCNT_CUR)             /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA30
-   ========================================================================= */
-#define pREG_DMA30_DSCPTR_NXT            ((void * volatile *)REG_DMA30_DSCPTR_NXT)               /* DMA30 Pointer to Next Initial Descriptor */
-#define pREG_DMA30_ADDRSTART             ((void * volatile *)REG_DMA30_ADDRSTART)                /* DMA30 Start Address of Current Buffer */
-#define pREG_DMA30_CFG                   ((volatile uint32_t *)REG_DMA30_CFG)                    /* DMA30 Configuration Register */
-#define pREG_DMA30_XCNT                  ((volatile uint32_t *)REG_DMA30_XCNT)                   /* DMA30 Inner Loop Count Start Value */
-#define pREG_DMA30_XMOD                  ((volatile  int32_t *)REG_DMA30_XMOD)                   /* DMA30 Inner Loop Address Increment */
-#define pREG_DMA30_YCNT                  ((volatile uint32_t *)REG_DMA30_YCNT)                   /* DMA30 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA30_YMOD                  ((volatile  int32_t *)REG_DMA30_YMOD)                   /* DMA30 Outer Loop Address Increment (2D only) */
-#define pREG_DMA30_DSCPTR_CUR            ((void * volatile *)REG_DMA30_DSCPTR_CUR)               /* DMA30 Current Descriptor Pointer */
-#define pREG_DMA30_DSCPTR_PRV            ((void * volatile *)REG_DMA30_DSCPTR_PRV)               /* DMA30 Previous Initial Descriptor Pointer */
-#define pREG_DMA30_ADDR_CUR              ((void * volatile *)REG_DMA30_ADDR_CUR)                 /* DMA30 Current Address */
-#define pREG_DMA30_STAT                  ((volatile uint32_t *)REG_DMA30_STAT)                   /* DMA30 Status Register */
-#define pREG_DMA30_XCNT_CUR              ((volatile uint32_t *)REG_DMA30_XCNT_CUR)               /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA30_YCNT_CUR              ((volatile uint32_t *)REG_DMA30_YCNT_CUR)               /* DMA30 Current Row Count (2D only) */
-#define pREG_DMA30_BWLCNT                ((volatile uint32_t *)REG_DMA30_BWLCNT)                 /* DMA30 Bandwidth Limit Count */
-#define pREG_DMA30_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWLCNT_CUR)             /* DMA30 Bandwidth Limit Count Current */
-#define pREG_DMA30_BWMCNT                ((volatile uint32_t *)REG_DMA30_BWMCNT)                 /* DMA30 Bandwidth Monitor Count */
-#define pREG_DMA30_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWMCNT_CUR)             /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA31
-   ========================================================================= */
-#define pREG_DMA31_DSCPTR_NXT            ((void * volatile *)REG_DMA31_DSCPTR_NXT)               /* DMA31 Pointer to Next Initial Descriptor */
-#define pREG_DMA31_ADDRSTART             ((void * volatile *)REG_DMA31_ADDRSTART)                /* DMA31 Start Address of Current Buffer */
-#define pREG_DMA31_CFG                   ((volatile uint32_t *)REG_DMA31_CFG)                    /* DMA31 Configuration Register */
-#define pREG_DMA31_XCNT                  ((volatile uint32_t *)REG_DMA31_XCNT)                   /* DMA31 Inner Loop Count Start Value */
-#define pREG_DMA31_XMOD                  ((volatile  int32_t *)REG_DMA31_XMOD)                   /* DMA31 Inner Loop Address Increment */
-#define pREG_DMA31_YCNT                  ((volatile uint32_t *)REG_DMA31_YCNT)                   /* DMA31 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA31_YMOD                  ((volatile  int32_t *)REG_DMA31_YMOD)                   /* DMA31 Outer Loop Address Increment (2D only) */
-#define pREG_DMA31_DSCPTR_CUR            ((void * volatile *)REG_DMA31_DSCPTR_CUR)               /* DMA31 Current Descriptor Pointer */
-#define pREG_DMA31_DSCPTR_PRV            ((void * volatile *)REG_DMA31_DSCPTR_PRV)               /* DMA31 Previous Initial Descriptor Pointer */
-#define pREG_DMA31_ADDR_CUR              ((void * volatile *)REG_DMA31_ADDR_CUR)                 /* DMA31 Current Address */
-#define pREG_DMA31_STAT                  ((volatile uint32_t *)REG_DMA31_STAT)                   /* DMA31 Status Register */
-#define pREG_DMA31_XCNT_CUR              ((volatile uint32_t *)REG_DMA31_XCNT_CUR)               /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA31_YCNT_CUR              ((volatile uint32_t *)REG_DMA31_YCNT_CUR)               /* DMA31 Current Row Count (2D only) */
-#define pREG_DMA31_BWLCNT                ((volatile uint32_t *)REG_DMA31_BWLCNT)                 /* DMA31 Bandwidth Limit Count */
-#define pREG_DMA31_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWLCNT_CUR)             /* DMA31 Bandwidth Limit Count Current */
-#define pREG_DMA31_BWMCNT                ((volatile uint32_t *)REG_DMA31_BWMCNT)                 /* DMA31 Bandwidth Monitor Count */
-#define pREG_DMA31_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWMCNT_CUR)             /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA32
-   ========================================================================= */
-#define pREG_DMA32_DSCPTR_NXT            ((void * volatile *)REG_DMA32_DSCPTR_NXT)               /* DMA32 Pointer to Next Initial Descriptor */
-#define pREG_DMA32_ADDRSTART             ((void * volatile *)REG_DMA32_ADDRSTART)                /* DMA32 Start Address of Current Buffer */
-#define pREG_DMA32_CFG                   ((volatile uint32_t *)REG_DMA32_CFG)                    /* DMA32 Configuration Register */
-#define pREG_DMA32_XCNT                  ((volatile uint32_t *)REG_DMA32_XCNT)                   /* DMA32 Inner Loop Count Start Value */
-#define pREG_DMA32_XMOD                  ((volatile  int32_t *)REG_DMA32_XMOD)                   /* DMA32 Inner Loop Address Increment */
-#define pREG_DMA32_YCNT                  ((volatile uint32_t *)REG_DMA32_YCNT)                   /* DMA32 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA32_YMOD                  ((volatile  int32_t *)REG_DMA32_YMOD)                   /* DMA32 Outer Loop Address Increment (2D only) */
-#define pREG_DMA32_DSCPTR_CUR            ((void * volatile *)REG_DMA32_DSCPTR_CUR)               /* DMA32 Current Descriptor Pointer */
-#define pREG_DMA32_DSCPTR_PRV            ((void * volatile *)REG_DMA32_DSCPTR_PRV)               /* DMA32 Previous Initial Descriptor Pointer */
-#define pREG_DMA32_ADDR_CUR              ((void * volatile *)REG_DMA32_ADDR_CUR)                 /* DMA32 Current Address */
-#define pREG_DMA32_STAT                  ((volatile uint32_t *)REG_DMA32_STAT)                   /* DMA32 Status Register */
-#define pREG_DMA32_XCNT_CUR              ((volatile uint32_t *)REG_DMA32_XCNT_CUR)               /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA32_YCNT_CUR              ((volatile uint32_t *)REG_DMA32_YCNT_CUR)               /* DMA32 Current Row Count (2D only) */
-#define pREG_DMA32_BWLCNT                ((volatile uint32_t *)REG_DMA32_BWLCNT)                 /* DMA32 Bandwidth Limit Count */
-#define pREG_DMA32_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWLCNT_CUR)             /* DMA32 Bandwidth Limit Count Current */
-#define pREG_DMA32_BWMCNT                ((volatile uint32_t *)REG_DMA32_BWMCNT)                 /* DMA32 Bandwidth Monitor Count */
-#define pREG_DMA32_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWMCNT_CUR)             /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA33
-   ========================================================================= */
-#define pREG_DMA33_DSCPTR_NXT            ((void * volatile *)REG_DMA33_DSCPTR_NXT)               /* DMA33 Pointer to Next Initial Descriptor */
-#define pREG_DMA33_ADDRSTART             ((void * volatile *)REG_DMA33_ADDRSTART)                /* DMA33 Start Address of Current Buffer */
-#define pREG_DMA33_CFG                   ((volatile uint32_t *)REG_DMA33_CFG)                    /* DMA33 Configuration Register */
-#define pREG_DMA33_XCNT                  ((volatile uint32_t *)REG_DMA33_XCNT)                   /* DMA33 Inner Loop Count Start Value */
-#define pREG_DMA33_XMOD                  ((volatile  int32_t *)REG_DMA33_XMOD)                   /* DMA33 Inner Loop Address Increment */
-#define pREG_DMA33_YCNT                  ((volatile uint32_t *)REG_DMA33_YCNT)                   /* DMA33 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA33_YMOD                  ((volatile  int32_t *)REG_DMA33_YMOD)                   /* DMA33 Outer Loop Address Increment (2D only) */
-#define pREG_DMA33_DSCPTR_CUR            ((void * volatile *)REG_DMA33_DSCPTR_CUR)               /* DMA33 Current Descriptor Pointer */
-#define pREG_DMA33_DSCPTR_PRV            ((void * volatile *)REG_DMA33_DSCPTR_PRV)               /* DMA33 Previous Initial Descriptor Pointer */
-#define pREG_DMA33_ADDR_CUR              ((void * volatile *)REG_DMA33_ADDR_CUR)                 /* DMA33 Current Address */
-#define pREG_DMA33_STAT                  ((volatile uint32_t *)REG_DMA33_STAT)                   /* DMA33 Status Register */
-#define pREG_DMA33_XCNT_CUR              ((volatile uint32_t *)REG_DMA33_XCNT_CUR)               /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA33_YCNT_CUR              ((volatile uint32_t *)REG_DMA33_YCNT_CUR)               /* DMA33 Current Row Count (2D only) */
-#define pREG_DMA33_BWLCNT                ((volatile uint32_t *)REG_DMA33_BWLCNT)                 /* DMA33 Bandwidth Limit Count */
-#define pREG_DMA33_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWLCNT_CUR)             /* DMA33 Bandwidth Limit Count Current */
-#define pREG_DMA33_BWMCNT                ((volatile uint32_t *)REG_DMA33_BWMCNT)                 /* DMA33 Bandwidth Monitor Count */
-#define pREG_DMA33_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWMCNT_CUR)             /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA34
-   ========================================================================= */
-#define pREG_DMA34_DSCPTR_NXT            ((void * volatile *)REG_DMA34_DSCPTR_NXT)               /* DMA34 Pointer to Next Initial Descriptor */
-#define pREG_DMA34_ADDRSTART             ((void * volatile *)REG_DMA34_ADDRSTART)                /* DMA34 Start Address of Current Buffer */
-#define pREG_DMA34_CFG                   ((volatile uint32_t *)REG_DMA34_CFG)                    /* DMA34 Configuration Register */
-#define pREG_DMA34_XCNT                  ((volatile uint32_t *)REG_DMA34_XCNT)                   /* DMA34 Inner Loop Count Start Value */
-#define pREG_DMA34_XMOD                  ((volatile  int32_t *)REG_DMA34_XMOD)                   /* DMA34 Inner Loop Address Increment */
-#define pREG_DMA34_YCNT                  ((volatile uint32_t *)REG_DMA34_YCNT)                   /* DMA34 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA34_YMOD                  ((volatile  int32_t *)REG_DMA34_YMOD)                   /* DMA34 Outer Loop Address Increment (2D only) */
-#define pREG_DMA34_DSCPTR_CUR            ((void * volatile *)REG_DMA34_DSCPTR_CUR)               /* DMA34 Current Descriptor Pointer */
-#define pREG_DMA34_DSCPTR_PRV            ((void * volatile *)REG_DMA34_DSCPTR_PRV)               /* DMA34 Previous Initial Descriptor Pointer */
-#define pREG_DMA34_ADDR_CUR              ((void * volatile *)REG_DMA34_ADDR_CUR)                 /* DMA34 Current Address */
-#define pREG_DMA34_STAT                  ((volatile uint32_t *)REG_DMA34_STAT)                   /* DMA34 Status Register */
-#define pREG_DMA34_XCNT_CUR              ((volatile uint32_t *)REG_DMA34_XCNT_CUR)               /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA34_YCNT_CUR              ((volatile uint32_t *)REG_DMA34_YCNT_CUR)               /* DMA34 Current Row Count (2D only) */
-#define pREG_DMA34_BWLCNT                ((volatile uint32_t *)REG_DMA34_BWLCNT)                 /* DMA34 Bandwidth Limit Count */
-#define pREG_DMA34_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWLCNT_CUR)             /* DMA34 Bandwidth Limit Count Current */
-#define pREG_DMA34_BWMCNT                ((volatile uint32_t *)REG_DMA34_BWMCNT)                 /* DMA34 Bandwidth Monitor Count */
-#define pREG_DMA34_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWMCNT_CUR)             /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA35
-   ========================================================================= */
-#define pREG_DMA35_DSCPTR_NXT            ((void * volatile *)REG_DMA35_DSCPTR_NXT)               /* DMA35 Pointer to Next Initial Descriptor */
-#define pREG_DMA35_ADDRSTART             ((void * volatile *)REG_DMA35_ADDRSTART)                /* DMA35 Start Address of Current Buffer */
-#define pREG_DMA35_CFG                   ((volatile uint32_t *)REG_DMA35_CFG)                    /* DMA35 Configuration Register */
-#define pREG_DMA35_XCNT                  ((volatile uint32_t *)REG_DMA35_XCNT)                   /* DMA35 Inner Loop Count Start Value */
-#define pREG_DMA35_XMOD                  ((volatile  int32_t *)REG_DMA35_XMOD)                   /* DMA35 Inner Loop Address Increment */
-#define pREG_DMA35_YCNT                  ((volatile uint32_t *)REG_DMA35_YCNT)                   /* DMA35 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA35_YMOD                  ((volatile  int32_t *)REG_DMA35_YMOD)                   /* DMA35 Outer Loop Address Increment (2D only) */
-#define pREG_DMA35_DSCPTR_CUR            ((void * volatile *)REG_DMA35_DSCPTR_CUR)               /* DMA35 Current Descriptor Pointer */
-#define pREG_DMA35_DSCPTR_PRV            ((void * volatile *)REG_DMA35_DSCPTR_PRV)               /* DMA35 Previous Initial Descriptor Pointer */
-#define pREG_DMA35_ADDR_CUR              ((void * volatile *)REG_DMA35_ADDR_CUR)                 /* DMA35 Current Address */
-#define pREG_DMA35_STAT                  ((volatile uint32_t *)REG_DMA35_STAT)                   /* DMA35 Status Register */
-#define pREG_DMA35_XCNT_CUR              ((volatile uint32_t *)REG_DMA35_XCNT_CUR)               /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA35_YCNT_CUR              ((volatile uint32_t *)REG_DMA35_YCNT_CUR)               /* DMA35 Current Row Count (2D only) */
-#define pREG_DMA35_BWLCNT                ((volatile uint32_t *)REG_DMA35_BWLCNT)                 /* DMA35 Bandwidth Limit Count */
-#define pREG_DMA35_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWLCNT_CUR)             /* DMA35 Bandwidth Limit Count Current */
-#define pREG_DMA35_BWMCNT                ((volatile uint32_t *)REG_DMA35_BWMCNT)                 /* DMA35 Bandwidth Monitor Count */
-#define pREG_DMA35_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWMCNT_CUR)             /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA36
-   ========================================================================= */
-#define pREG_DMA36_DSCPTR_NXT            ((void * volatile *)REG_DMA36_DSCPTR_NXT)               /* DMA36 Pointer to Next Initial Descriptor */
-#define pREG_DMA36_ADDRSTART             ((void * volatile *)REG_DMA36_ADDRSTART)                /* DMA36 Start Address of Current Buffer */
-#define pREG_DMA36_CFG                   ((volatile uint32_t *)REG_DMA36_CFG)                    /* DMA36 Configuration Register */
-#define pREG_DMA36_XCNT                  ((volatile uint32_t *)REG_DMA36_XCNT)                   /* DMA36 Inner Loop Count Start Value */
-#define pREG_DMA36_XMOD                  ((volatile  int32_t *)REG_DMA36_XMOD)                   /* DMA36 Inner Loop Address Increment */
-#define pREG_DMA36_YCNT                  ((volatile uint32_t *)REG_DMA36_YCNT)                   /* DMA36 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA36_YMOD                  ((volatile  int32_t *)REG_DMA36_YMOD)                   /* DMA36 Outer Loop Address Increment (2D only) */
-#define pREG_DMA36_DSCPTR_CUR            ((void * volatile *)REG_DMA36_DSCPTR_CUR)               /* DMA36 Current Descriptor Pointer */
-#define pREG_DMA36_DSCPTR_PRV            ((void * volatile *)REG_DMA36_DSCPTR_PRV)               /* DMA36 Previous Initial Descriptor Pointer */
-#define pREG_DMA36_ADDR_CUR              ((void * volatile *)REG_DMA36_ADDR_CUR)                 /* DMA36 Current Address */
-#define pREG_DMA36_STAT                  ((volatile uint32_t *)REG_DMA36_STAT)                   /* DMA36 Status Register */
-#define pREG_DMA36_XCNT_CUR              ((volatile uint32_t *)REG_DMA36_XCNT_CUR)               /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA36_YCNT_CUR              ((volatile uint32_t *)REG_DMA36_YCNT_CUR)               /* DMA36 Current Row Count (2D only) */
-#define pREG_DMA36_BWLCNT                ((volatile uint32_t *)REG_DMA36_BWLCNT)                 /* DMA36 Bandwidth Limit Count */
-#define pREG_DMA36_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWLCNT_CUR)             /* DMA36 Bandwidth Limit Count Current */
-#define pREG_DMA36_BWMCNT                ((volatile uint32_t *)REG_DMA36_BWMCNT)                 /* DMA36 Bandwidth Monitor Count */
-#define pREG_DMA36_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWMCNT_CUR)             /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA37
-   ========================================================================= */
-#define pREG_DMA37_DSCPTR_NXT            ((void * volatile *)REG_DMA37_DSCPTR_NXT)               /* DMA37 Pointer to Next Initial Descriptor */
-#define pREG_DMA37_ADDRSTART             ((void * volatile *)REG_DMA37_ADDRSTART)                /* DMA37 Start Address of Current Buffer */
-#define pREG_DMA37_CFG                   ((volatile uint32_t *)REG_DMA37_CFG)                    /* DMA37 Configuration Register */
-#define pREG_DMA37_XCNT                  ((volatile uint32_t *)REG_DMA37_XCNT)                   /* DMA37 Inner Loop Count Start Value */
-#define pREG_DMA37_XMOD                  ((volatile  int32_t *)REG_DMA37_XMOD)                   /* DMA37 Inner Loop Address Increment */
-#define pREG_DMA37_YCNT                  ((volatile uint32_t *)REG_DMA37_YCNT)                   /* DMA37 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA37_YMOD                  ((volatile  int32_t *)REG_DMA37_YMOD)                   /* DMA37 Outer Loop Address Increment (2D only) */
-#define pREG_DMA37_DSCPTR_CUR            ((void * volatile *)REG_DMA37_DSCPTR_CUR)               /* DMA37 Current Descriptor Pointer */
-#define pREG_DMA37_DSCPTR_PRV            ((void * volatile *)REG_DMA37_DSCPTR_PRV)               /* DMA37 Previous Initial Descriptor Pointer */
-#define pREG_DMA37_ADDR_CUR              ((void * volatile *)REG_DMA37_ADDR_CUR)                 /* DMA37 Current Address */
-#define pREG_DMA37_STAT                  ((volatile uint32_t *)REG_DMA37_STAT)                   /* DMA37 Status Register */
-#define pREG_DMA37_XCNT_CUR              ((volatile uint32_t *)REG_DMA37_XCNT_CUR)               /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA37_YCNT_CUR              ((volatile uint32_t *)REG_DMA37_YCNT_CUR)               /* DMA37 Current Row Count (2D only) */
-#define pREG_DMA37_BWLCNT                ((volatile uint32_t *)REG_DMA37_BWLCNT)                 /* DMA37 Bandwidth Limit Count */
-#define pREG_DMA37_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWLCNT_CUR)             /* DMA37 Bandwidth Limit Count Current */
-#define pREG_DMA37_BWMCNT                ((volatile uint32_t *)REG_DMA37_BWMCNT)                 /* DMA37 Bandwidth Monitor Count */
-#define pREG_DMA37_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWMCNT_CUR)             /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA38
-   ========================================================================= */
-#define pREG_DMA38_DSCPTR_NXT            ((void * volatile *)REG_DMA38_DSCPTR_NXT)               /* DMA38 Pointer to Next Initial Descriptor */
-#define pREG_DMA38_ADDRSTART             ((void * volatile *)REG_DMA38_ADDRSTART)                /* DMA38 Start Address of Current Buffer */
-#define pREG_DMA38_CFG                   ((volatile uint32_t *)REG_DMA38_CFG)                    /* DMA38 Configuration Register */
-#define pREG_DMA38_XCNT                  ((volatile uint32_t *)REG_DMA38_XCNT)                   /* DMA38 Inner Loop Count Start Value */
-#define pREG_DMA38_XMOD                  ((volatile  int32_t *)REG_DMA38_XMOD)                   /* DMA38 Inner Loop Address Increment */
-#define pREG_DMA38_YCNT                  ((volatile uint32_t *)REG_DMA38_YCNT)                   /* DMA38 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA38_YMOD                  ((volatile  int32_t *)REG_DMA38_YMOD)                   /* DMA38 Outer Loop Address Increment (2D only) */
-#define pREG_DMA38_DSCPTR_CUR            ((void * volatile *)REG_DMA38_DSCPTR_CUR)               /* DMA38 Current Descriptor Pointer */
-#define pREG_DMA38_DSCPTR_PRV            ((void * volatile *)REG_DMA38_DSCPTR_PRV)               /* DMA38 Previous Initial Descriptor Pointer */
-#define pREG_DMA38_ADDR_CUR              ((void * volatile *)REG_DMA38_ADDR_CUR)                 /* DMA38 Current Address */
-#define pREG_DMA38_STAT                  ((volatile uint32_t *)REG_DMA38_STAT)                   /* DMA38 Status Register */
-#define pREG_DMA38_XCNT_CUR              ((volatile uint32_t *)REG_DMA38_XCNT_CUR)               /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA38_YCNT_CUR              ((volatile uint32_t *)REG_DMA38_YCNT_CUR)               /* DMA38 Current Row Count (2D only) */
-#define pREG_DMA38_BWLCNT                ((volatile uint32_t *)REG_DMA38_BWLCNT)                 /* DMA38 Bandwidth Limit Count */
-#define pREG_DMA38_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWLCNT_CUR)             /* DMA38 Bandwidth Limit Count Current */
-#define pREG_DMA38_BWMCNT                ((volatile uint32_t *)REG_DMA38_BWMCNT)                 /* DMA38 Bandwidth Monitor Count */
-#define pREG_DMA38_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWMCNT_CUR)             /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA39
-   ========================================================================= */
-#define pREG_DMA39_DSCPTR_NXT            ((void * volatile *)REG_DMA39_DSCPTR_NXT)               /* DMA39 Pointer to Next Initial Descriptor */
-#define pREG_DMA39_ADDRSTART             ((void * volatile *)REG_DMA39_ADDRSTART)                /* DMA39 Start Address of Current Buffer */
-#define pREG_DMA39_CFG                   ((volatile uint32_t *)REG_DMA39_CFG)                    /* DMA39 Configuration Register */
-#define pREG_DMA39_XCNT                  ((volatile uint32_t *)REG_DMA39_XCNT)                   /* DMA39 Inner Loop Count Start Value */
-#define pREG_DMA39_XMOD                  ((volatile  int32_t *)REG_DMA39_XMOD)                   /* DMA39 Inner Loop Address Increment */
-#define pREG_DMA39_YCNT                  ((volatile uint32_t *)REG_DMA39_YCNT)                   /* DMA39 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA39_YMOD                  ((volatile  int32_t *)REG_DMA39_YMOD)                   /* DMA39 Outer Loop Address Increment (2D only) */
-#define pREG_DMA39_DSCPTR_CUR            ((void * volatile *)REG_DMA39_DSCPTR_CUR)               /* DMA39 Current Descriptor Pointer */
-#define pREG_DMA39_DSCPTR_PRV            ((void * volatile *)REG_DMA39_DSCPTR_PRV)               /* DMA39 Previous Initial Descriptor Pointer */
-#define pREG_DMA39_ADDR_CUR              ((void * volatile *)REG_DMA39_ADDR_CUR)                 /* DMA39 Current Address */
-#define pREG_DMA39_STAT                  ((volatile uint32_t *)REG_DMA39_STAT)                   /* DMA39 Status Register */
-#define pREG_DMA39_XCNT_CUR              ((volatile uint32_t *)REG_DMA39_XCNT_CUR)               /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA39_YCNT_CUR              ((volatile uint32_t *)REG_DMA39_YCNT_CUR)               /* DMA39 Current Row Count (2D only) */
-#define pREG_DMA39_BWLCNT                ((volatile uint32_t *)REG_DMA39_BWLCNT)                 /* DMA39 Bandwidth Limit Count */
-#define pREG_DMA39_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWLCNT_CUR)             /* DMA39 Bandwidth Limit Count Current */
-#define pREG_DMA39_BWMCNT                ((volatile uint32_t *)REG_DMA39_BWMCNT)                 /* DMA39 Bandwidth Monitor Count */
-#define pREG_DMA39_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWMCNT_CUR)             /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA40
-   ========================================================================= */
-#define pREG_DMA40_DSCPTR_NXT            ((void * volatile *)REG_DMA40_DSCPTR_NXT)               /* DMA40 Pointer to Next Initial Descriptor */
-#define pREG_DMA40_ADDRSTART             ((void * volatile *)REG_DMA40_ADDRSTART)                /* DMA40 Start Address of Current Buffer */
-#define pREG_DMA40_CFG                   ((volatile uint32_t *)REG_DMA40_CFG)                    /* DMA40 Configuration Register */
-#define pREG_DMA40_XCNT                  ((volatile uint32_t *)REG_DMA40_XCNT)                   /* DMA40 Inner Loop Count Start Value */
-#define pREG_DMA40_XMOD                  ((volatile  int32_t *)REG_DMA40_XMOD)                   /* DMA40 Inner Loop Address Increment */
-#define pREG_DMA40_YCNT                  ((volatile uint32_t *)REG_DMA40_YCNT)                   /* DMA40 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA40_YMOD                  ((volatile  int32_t *)REG_DMA40_YMOD)                   /* DMA40 Outer Loop Address Increment (2D only) */
-#define pREG_DMA40_DSCPTR_CUR            ((void * volatile *)REG_DMA40_DSCPTR_CUR)               /* DMA40 Current Descriptor Pointer */
-#define pREG_DMA40_DSCPTR_PRV            ((void * volatile *)REG_DMA40_DSCPTR_PRV)               /* DMA40 Previous Initial Descriptor Pointer */
-#define pREG_DMA40_ADDR_CUR              ((void * volatile *)REG_DMA40_ADDR_CUR)                 /* DMA40 Current Address */
-#define pREG_DMA40_STAT                  ((volatile uint32_t *)REG_DMA40_STAT)                   /* DMA40 Status Register */
-#define pREG_DMA40_XCNT_CUR              ((volatile uint32_t *)REG_DMA40_XCNT_CUR)               /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA40_YCNT_CUR              ((volatile uint32_t *)REG_DMA40_YCNT_CUR)               /* DMA40 Current Row Count (2D only) */
-#define pREG_DMA40_BWLCNT                ((volatile uint32_t *)REG_DMA40_BWLCNT)                 /* DMA40 Bandwidth Limit Count */
-#define pREG_DMA40_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWLCNT_CUR)             /* DMA40 Bandwidth Limit Count Current */
-#define pREG_DMA40_BWMCNT                ((volatile uint32_t *)REG_DMA40_BWMCNT)                 /* DMA40 Bandwidth Monitor Count */
-#define pREG_DMA40_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWMCNT_CUR)             /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA41
-   ========================================================================= */
-#define pREG_DMA41_DSCPTR_NXT            ((void * volatile *)REG_DMA41_DSCPTR_NXT)               /* DMA41 Pointer to Next Initial Descriptor */
-#define pREG_DMA41_ADDRSTART             ((void * volatile *)REG_DMA41_ADDRSTART)                /* DMA41 Start Address of Current Buffer */
-#define pREG_DMA41_CFG                   ((volatile uint32_t *)REG_DMA41_CFG)                    /* DMA41 Configuration Register */
-#define pREG_DMA41_XCNT                  ((volatile uint32_t *)REG_DMA41_XCNT)                   /* DMA41 Inner Loop Count Start Value */
-#define pREG_DMA41_XMOD                  ((volatile  int32_t *)REG_DMA41_XMOD)                   /* DMA41 Inner Loop Address Increment */
-#define pREG_DMA41_YCNT                  ((volatile uint32_t *)REG_DMA41_YCNT)                   /* DMA41 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA41_YMOD                  ((volatile  int32_t *)REG_DMA41_YMOD)                   /* DMA41 Outer Loop Address Increment (2D only) */
-#define pREG_DMA41_DSCPTR_CUR            ((void * volatile *)REG_DMA41_DSCPTR_CUR)               /* DMA41 Current Descriptor Pointer */
-#define pREG_DMA41_DSCPTR_PRV            ((void * volatile *)REG_DMA41_DSCPTR_PRV)               /* DMA41 Previous Initial Descriptor Pointer */
-#define pREG_DMA41_ADDR_CUR              ((void * volatile *)REG_DMA41_ADDR_CUR)                 /* DMA41 Current Address */
-#define pREG_DMA41_STAT                  ((volatile uint32_t *)REG_DMA41_STAT)                   /* DMA41 Status Register */
-#define pREG_DMA41_XCNT_CUR              ((volatile uint32_t *)REG_DMA41_XCNT_CUR)               /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA41_YCNT_CUR              ((volatile uint32_t *)REG_DMA41_YCNT_CUR)               /* DMA41 Current Row Count (2D only) */
-#define pREG_DMA41_BWLCNT                ((volatile uint32_t *)REG_DMA41_BWLCNT)                 /* DMA41 Bandwidth Limit Count */
-#define pREG_DMA41_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWLCNT_CUR)             /* DMA41 Bandwidth Limit Count Current */
-#define pREG_DMA41_BWMCNT                ((volatile uint32_t *)REG_DMA41_BWMCNT)                 /* DMA41 Bandwidth Monitor Count */
-#define pREG_DMA41_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWMCNT_CUR)             /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA42
-   ========================================================================= */
-#define pREG_DMA42_DSCPTR_NXT            ((void * volatile *)REG_DMA42_DSCPTR_NXT)               /* DMA42 Pointer to Next Initial Descriptor */
-#define pREG_DMA42_ADDRSTART             ((void * volatile *)REG_DMA42_ADDRSTART)                /* DMA42 Start Address of Current Buffer */
-#define pREG_DMA42_CFG                   ((volatile uint32_t *)REG_DMA42_CFG)                    /* DMA42 Configuration Register */
-#define pREG_DMA42_XCNT                  ((volatile uint32_t *)REG_DMA42_XCNT)                   /* DMA42 Inner Loop Count Start Value */
-#define pREG_DMA42_XMOD                  ((volatile  int32_t *)REG_DMA42_XMOD)                   /* DMA42 Inner Loop Address Increment */
-#define pREG_DMA42_YCNT                  ((volatile uint32_t *)REG_DMA42_YCNT)                   /* DMA42 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA42_YMOD                  ((volatile  int32_t *)REG_DMA42_YMOD)                   /* DMA42 Outer Loop Address Increment (2D only) */
-#define pREG_DMA42_DSCPTR_CUR            ((void * volatile *)REG_DMA42_DSCPTR_CUR)               /* DMA42 Current Descriptor Pointer */
-#define pREG_DMA42_DSCPTR_PRV            ((void * volatile *)REG_DMA42_DSCPTR_PRV)               /* DMA42 Previous Initial Descriptor Pointer */
-#define pREG_DMA42_ADDR_CUR              ((void * volatile *)REG_DMA42_ADDR_CUR)                 /* DMA42 Current Address */
-#define pREG_DMA42_STAT                  ((volatile uint32_t *)REG_DMA42_STAT)                   /* DMA42 Status Register */
-#define pREG_DMA42_XCNT_CUR              ((volatile uint32_t *)REG_DMA42_XCNT_CUR)               /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA42_YCNT_CUR              ((volatile uint32_t *)REG_DMA42_YCNT_CUR)               /* DMA42 Current Row Count (2D only) */
-#define pREG_DMA42_BWLCNT                ((volatile uint32_t *)REG_DMA42_BWLCNT)                 /* DMA42 Bandwidth Limit Count */
-#define pREG_DMA42_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWLCNT_CUR)             /* DMA42 Bandwidth Limit Count Current */
-#define pREG_DMA42_BWMCNT                ((volatile uint32_t *)REG_DMA42_BWMCNT)                 /* DMA42 Bandwidth Monitor Count */
-#define pREG_DMA42_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWMCNT_CUR)             /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA43
-   ========================================================================= */
-#define pREG_DMA43_DSCPTR_NXT            ((void * volatile *)REG_DMA43_DSCPTR_NXT)               /* DMA43 Pointer to Next Initial Descriptor */
-#define pREG_DMA43_ADDRSTART             ((void * volatile *)REG_DMA43_ADDRSTART)                /* DMA43 Start Address of Current Buffer */
-#define pREG_DMA43_CFG                   ((volatile uint32_t *)REG_DMA43_CFG)                    /* DMA43 Configuration Register */
-#define pREG_DMA43_XCNT                  ((volatile uint32_t *)REG_DMA43_XCNT)                   /* DMA43 Inner Loop Count Start Value */
-#define pREG_DMA43_XMOD                  ((volatile  int32_t *)REG_DMA43_XMOD)                   /* DMA43 Inner Loop Address Increment */
-#define pREG_DMA43_YCNT                  ((volatile uint32_t *)REG_DMA43_YCNT)                   /* DMA43 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA43_YMOD                  ((volatile  int32_t *)REG_DMA43_YMOD)                   /* DMA43 Outer Loop Address Increment (2D only) */
-#define pREG_DMA43_DSCPTR_CUR            ((void * volatile *)REG_DMA43_DSCPTR_CUR)               /* DMA43 Current Descriptor Pointer */
-#define pREG_DMA43_DSCPTR_PRV            ((void * volatile *)REG_DMA43_DSCPTR_PRV)               /* DMA43 Previous Initial Descriptor Pointer */
-#define pREG_DMA43_ADDR_CUR              ((void * volatile *)REG_DMA43_ADDR_CUR)                 /* DMA43 Current Address */
-#define pREG_DMA43_STAT                  ((volatile uint32_t *)REG_DMA43_STAT)                   /* DMA43 Status Register */
-#define pREG_DMA43_XCNT_CUR              ((volatile uint32_t *)REG_DMA43_XCNT_CUR)               /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA43_YCNT_CUR              ((volatile uint32_t *)REG_DMA43_YCNT_CUR)               /* DMA43 Current Row Count (2D only) */
-#define pREG_DMA43_BWLCNT                ((volatile uint32_t *)REG_DMA43_BWLCNT)                 /* DMA43 Bandwidth Limit Count */
-#define pREG_DMA43_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWLCNT_CUR)             /* DMA43 Bandwidth Limit Count Current */
-#define pREG_DMA43_BWMCNT                ((volatile uint32_t *)REG_DMA43_BWMCNT)                 /* DMA43 Bandwidth Monitor Count */
-#define pREG_DMA43_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWMCNT_CUR)             /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA44
-   ========================================================================= */
-#define pREG_DMA44_DSCPTR_NXT            ((void * volatile *)REG_DMA44_DSCPTR_NXT)               /* DMA44 Pointer to Next Initial Descriptor */
-#define pREG_DMA44_ADDRSTART             ((void * volatile *)REG_DMA44_ADDRSTART)                /* DMA44 Start Address of Current Buffer */
-#define pREG_DMA44_CFG                   ((volatile uint32_t *)REG_DMA44_CFG)                    /* DMA44 Configuration Register */
-#define pREG_DMA44_XCNT                  ((volatile uint32_t *)REG_DMA44_XCNT)                   /* DMA44 Inner Loop Count Start Value */
-#define pREG_DMA44_XMOD                  ((volatile  int32_t *)REG_DMA44_XMOD)                   /* DMA44 Inner Loop Address Increment */
-#define pREG_DMA44_YCNT                  ((volatile uint32_t *)REG_DMA44_YCNT)                   /* DMA44 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA44_YMOD                  ((volatile  int32_t *)REG_DMA44_YMOD)                   /* DMA44 Outer Loop Address Increment (2D only) */
-#define pREG_DMA44_DSCPTR_CUR            ((void * volatile *)REG_DMA44_DSCPTR_CUR)               /* DMA44 Current Descriptor Pointer */
-#define pREG_DMA44_DSCPTR_PRV            ((void * volatile *)REG_DMA44_DSCPTR_PRV)               /* DMA44 Previous Initial Descriptor Pointer */
-#define pREG_DMA44_ADDR_CUR              ((void * volatile *)REG_DMA44_ADDR_CUR)                 /* DMA44 Current Address */
-#define pREG_DMA44_STAT                  ((volatile uint32_t *)REG_DMA44_STAT)                   /* DMA44 Status Register */
-#define pREG_DMA44_XCNT_CUR              ((volatile uint32_t *)REG_DMA44_XCNT_CUR)               /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA44_YCNT_CUR              ((volatile uint32_t *)REG_DMA44_YCNT_CUR)               /* DMA44 Current Row Count (2D only) */
-#define pREG_DMA44_BWLCNT                ((volatile uint32_t *)REG_DMA44_BWLCNT)                 /* DMA44 Bandwidth Limit Count */
-#define pREG_DMA44_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWLCNT_CUR)             /* DMA44 Bandwidth Limit Count Current */
-#define pREG_DMA44_BWMCNT                ((volatile uint32_t *)REG_DMA44_BWMCNT)                 /* DMA44 Bandwidth Monitor Count */
-#define pREG_DMA44_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWMCNT_CUR)             /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA45
-   ========================================================================= */
-#define pREG_DMA45_DSCPTR_NXT            ((void * volatile *)REG_DMA45_DSCPTR_NXT)               /* DMA45 Pointer to Next Initial Descriptor */
-#define pREG_DMA45_ADDRSTART             ((void * volatile *)REG_DMA45_ADDRSTART)                /* DMA45 Start Address of Current Buffer */
-#define pREG_DMA45_CFG                   ((volatile uint32_t *)REG_DMA45_CFG)                    /* DMA45 Configuration Register */
-#define pREG_DMA45_XCNT                  ((volatile uint32_t *)REG_DMA45_XCNT)                   /* DMA45 Inner Loop Count Start Value */
-#define pREG_DMA45_XMOD                  ((volatile  int32_t *)REG_DMA45_XMOD)                   /* DMA45 Inner Loop Address Increment */
-#define pREG_DMA45_YCNT                  ((volatile uint32_t *)REG_DMA45_YCNT)                   /* DMA45 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA45_YMOD                  ((volatile  int32_t *)REG_DMA45_YMOD)                   /* DMA45 Outer Loop Address Increment (2D only) */
-#define pREG_DMA45_DSCPTR_CUR            ((void * volatile *)REG_DMA45_DSCPTR_CUR)               /* DMA45 Current Descriptor Pointer */
-#define pREG_DMA45_DSCPTR_PRV            ((void * volatile *)REG_DMA45_DSCPTR_PRV)               /* DMA45 Previous Initial Descriptor Pointer */
-#define pREG_DMA45_ADDR_CUR              ((void * volatile *)REG_DMA45_ADDR_CUR)                 /* DMA45 Current Address */
-#define pREG_DMA45_STAT                  ((volatile uint32_t *)REG_DMA45_STAT)                   /* DMA45 Status Register */
-#define pREG_DMA45_XCNT_CUR              ((volatile uint32_t *)REG_DMA45_XCNT_CUR)               /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA45_YCNT_CUR              ((volatile uint32_t *)REG_DMA45_YCNT_CUR)               /* DMA45 Current Row Count (2D only) */
-#define pREG_DMA45_BWLCNT                ((volatile uint32_t *)REG_DMA45_BWLCNT)                 /* DMA45 Bandwidth Limit Count */
-#define pREG_DMA45_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWLCNT_CUR)             /* DMA45 Bandwidth Limit Count Current */
-#define pREG_DMA45_BWMCNT                ((volatile uint32_t *)REG_DMA45_BWMCNT)                 /* DMA45 Bandwidth Monitor Count */
-#define pREG_DMA45_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWMCNT_CUR)             /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA46
-   ========================================================================= */
-#define pREG_DMA46_DSCPTR_NXT            ((void * volatile *)REG_DMA46_DSCPTR_NXT)               /* DMA46 Pointer to Next Initial Descriptor */
-#define pREG_DMA46_ADDRSTART             ((void * volatile *)REG_DMA46_ADDRSTART)                /* DMA46 Start Address of Current Buffer */
-#define pREG_DMA46_CFG                   ((volatile uint32_t *)REG_DMA46_CFG)                    /* DMA46 Configuration Register */
-#define pREG_DMA46_XCNT                  ((volatile uint32_t *)REG_DMA46_XCNT)                   /* DMA46 Inner Loop Count Start Value */
-#define pREG_DMA46_XMOD                  ((volatile  int32_t *)REG_DMA46_XMOD)                   /* DMA46 Inner Loop Address Increment */
-#define pREG_DMA46_YCNT                  ((volatile uint32_t *)REG_DMA46_YCNT)                   /* DMA46 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA46_YMOD                  ((volatile  int32_t *)REG_DMA46_YMOD)                   /* DMA46 Outer Loop Address Increment (2D only) */
-#define pREG_DMA46_DSCPTR_CUR            ((void * volatile *)REG_DMA46_DSCPTR_CUR)               /* DMA46 Current Descriptor Pointer */
-#define pREG_DMA46_DSCPTR_PRV            ((void * volatile *)REG_DMA46_DSCPTR_PRV)               /* DMA46 Previous Initial Descriptor Pointer */
-#define pREG_DMA46_ADDR_CUR              ((void * volatile *)REG_DMA46_ADDR_CUR)                 /* DMA46 Current Address */
-#define pREG_DMA46_STAT                  ((volatile uint32_t *)REG_DMA46_STAT)                   /* DMA46 Status Register */
-#define pREG_DMA46_XCNT_CUR              ((volatile uint32_t *)REG_DMA46_XCNT_CUR)               /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA46_YCNT_CUR              ((volatile uint32_t *)REG_DMA46_YCNT_CUR)               /* DMA46 Current Row Count (2D only) */
-#define pREG_DMA46_BWLCNT                ((volatile uint32_t *)REG_DMA46_BWLCNT)                 /* DMA46 Bandwidth Limit Count */
-#define pREG_DMA46_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWLCNT_CUR)             /* DMA46 Bandwidth Limit Count Current */
-#define pREG_DMA46_BWMCNT                ((volatile uint32_t *)REG_DMA46_BWMCNT)                 /* DMA46 Bandwidth Monitor Count */
-#define pREG_DMA46_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWMCNT_CUR)             /* DMA46 Bandwidth Monitor Count Current */
-
-
-/* =========================================================================
-       ACM0
-   ========================================================================= */
-#define pREG_ACM0_CTL                    ((volatile uint32_t *)REG_ACM0_CTL)                     /* ACM0 ACM Control Register */
-#define pREG_ACM0_TC0                    ((volatile uint32_t *)REG_ACM0_TC0)                     /* ACM0 ACM Timing Configuration 0 Register */
-#define pREG_ACM0_TC1                    ((volatile uint32_t *)REG_ACM0_TC1)                     /* ACM0 ACM Timing Configuration 1 Register */
-#define pREG_ACM0_STAT                   ((volatile uint32_t *)REG_ACM0_STAT)                    /* ACM0 ACM Status Register */
-#define pREG_ACM0_EVSTAT                 ((volatile uint32_t *)REG_ACM0_EVSTAT)                  /* ACM0 ACM Event Status Register */
-#define pREG_ACM0_EVMSK                  ((volatile uint32_t *)REG_ACM0_EVMSK)                   /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define pREG_ACM0_MEVSTAT                ((volatile uint32_t *)REG_ACM0_MEVSTAT)                 /* ACM0 ACM Missed Event Status Register */
-#define pREG_ACM0_MEVMSK                 ((volatile uint32_t *)REG_ACM0_MEVMSK)                  /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define pREG_ACM0_EVCTL0                 ((volatile uint32_t *)REG_ACM0_EVCTL0)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL1                 ((volatile uint32_t *)REG_ACM0_EVCTL1)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL2                 ((volatile uint32_t *)REG_ACM0_EVCTL2)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL3                 ((volatile uint32_t *)REG_ACM0_EVCTL3)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL4                 ((volatile uint32_t *)REG_ACM0_EVCTL4)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL5                 ((volatile uint32_t *)REG_ACM0_EVCTL5)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL6                 ((volatile uint32_t *)REG_ACM0_EVCTL6)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL7                 ((volatile uint32_t *)REG_ACM0_EVCTL7)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL8                 ((volatile uint32_t *)REG_ACM0_EVCTL8)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL9                 ((volatile uint32_t *)REG_ACM0_EVCTL9)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL10                ((volatile uint32_t *)REG_ACM0_EVCTL10)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL11                ((volatile uint32_t *)REG_ACM0_EVCTL11)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL12                ((volatile uint32_t *)REG_ACM0_EVCTL12)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL13                ((volatile uint32_t *)REG_ACM0_EVCTL13)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL14                ((volatile uint32_t *)REG_ACM0_EVCTL14)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL15                ((volatile uint32_t *)REG_ACM0_EVCTL15)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVTIME0                ((volatile uint32_t *)REG_ACM0_EVTIME0)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME1                ((volatile uint32_t *)REG_ACM0_EVTIME1)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME2                ((volatile uint32_t *)REG_ACM0_EVTIME2)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME3                ((volatile uint32_t *)REG_ACM0_EVTIME3)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME4                ((volatile uint32_t *)REG_ACM0_EVTIME4)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME5                ((volatile uint32_t *)REG_ACM0_EVTIME5)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME6                ((volatile uint32_t *)REG_ACM0_EVTIME6)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME7                ((volatile uint32_t *)REG_ACM0_EVTIME7)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME8                ((volatile uint32_t *)REG_ACM0_EVTIME8)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME9                ((volatile uint32_t *)REG_ACM0_EVTIME9)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME10               ((volatile uint32_t *)REG_ACM0_EVTIME10)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME11               ((volatile uint32_t *)REG_ACM0_EVTIME11)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME12               ((volatile uint32_t *)REG_ACM0_EVTIME12)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME13               ((volatile uint32_t *)REG_ACM0_EVTIME13)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME14               ((volatile uint32_t *)REG_ACM0_EVTIME14)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME15               ((volatile uint32_t *)REG_ACM0_EVTIME15)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVORD0                 ((volatile uint32_t *)REG_ACM0_EVORD0)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD1                 ((volatile uint32_t *)REG_ACM0_EVORD1)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD2                 ((volatile uint32_t *)REG_ACM0_EVORD2)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD3                 ((volatile uint32_t *)REG_ACM0_EVORD3)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD4                 ((volatile uint32_t *)REG_ACM0_EVORD4)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD5                 ((volatile uint32_t *)REG_ACM0_EVORD5)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD6                 ((volatile uint32_t *)REG_ACM0_EVORD6)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD7                 ((volatile uint32_t *)REG_ACM0_EVORD7)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD8                 ((volatile uint32_t *)REG_ACM0_EVORD8)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD9                 ((volatile uint32_t *)REG_ACM0_EVORD9)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD10                ((volatile uint32_t *)REG_ACM0_EVORD10)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD11                ((volatile uint32_t *)REG_ACM0_EVORD11)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD12                ((volatile uint32_t *)REG_ACM0_EVORD12)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD13                ((volatile uint32_t *)REG_ACM0_EVORD13)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD14                ((volatile uint32_t *)REG_ACM0_EVORD14)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD15                ((volatile uint32_t *)REG_ACM0_EVORD15)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_TMR0                   ((volatile uint32_t *)REG_ACM0_TMR0)                    /* ACM0 ACM Timer 0 Register */
-#define pREG_ACM0_TMR1                   ((volatile uint32_t *)REG_ACM0_TMR1)                    /* ACM0 ACM Timer 1 Register */
-
-
-/* =========================================================================
-       DMC0
-   ========================================================================= */
-#define pREG_DMC0_CTL                    ((volatile uint32_t *)REG_DMC0_CTL)                     /* DMC0 Control Register */
-#define pREG_DMC0_STAT                   ((volatile uint32_t *)REG_DMC0_STAT)                    /* DMC0 Status Register */
-#define pREG_DMC0_EFFCTL                 ((volatile uint32_t *)REG_DMC0_EFFCTL)                  /* DMC0 Efficiency Control Register */
-#define pREG_DMC0_PRIO                   ((volatile uint32_t *)REG_DMC0_PRIO)                    /* DMC0 Priority ID Register */
-#define pREG_DMC0_PRIOMSK                ((volatile uint32_t *)REG_DMC0_PRIOMSK)                 /* DMC0 Priority ID Mask Register */
-#define pREG_DMC0_CFG                    ((volatile uint32_t *)REG_DMC0_CFG)                     /* DMC0 Configuration Register */
-#define pREG_DMC0_TR0                    ((volatile uint32_t *)REG_DMC0_TR0)                     /* DMC0 Timing 0 Register */
-#define pREG_DMC0_TR1                    ((volatile uint32_t *)REG_DMC0_TR1)                     /* DMC0 Timing 1 Register */
-#define pREG_DMC0_TR2                    ((volatile uint32_t *)REG_DMC0_TR2)                     /* DMC0 Timing 2 Register */
-#define pREG_DMC0_MSK                    ((volatile uint32_t *)REG_DMC0_MSK)                     /* DMC0 Mask (Mode Register Shadow) Register */
-#define pREG_DMC0_MR                     ((volatile uint32_t *)REG_DMC0_MR)                      /* DMC0 Shadow MR Register */
-#define pREG_DMC0_EMR1                   ((volatile uint32_t *)REG_DMC0_EMR1)                    /* DMC0 Shadow EMR1 Register */
-#define pREG_DMC0_EMR2                   ((volatile uint32_t *)REG_DMC0_EMR2)                    /* DMC0 Shadow EMR2 Register */
-#define pREG_DMC0_EMR3                   ((volatile uint32_t *)REG_DMC0_EMR3)                    /* DMC0 Shadow EMR3 Register */
-#define pREG_DMC0_DLLCTL                 ((volatile uint32_t *)REG_DMC0_DLLCTL)                  /* DMC0 DLL Control Register */
-#define pREG_DMC0_PHY_CTL0               ((volatile uint32_t *)REG_DMC0_PHY_CTL0)                /* DMC0 PHY Control 0 Register */
-#define pREG_DMC0_PHY_CTL1               ((volatile uint32_t *)REG_DMC0_PHY_CTL1)                /* DMC0 PHY Control 1 Register */
-#define pREG_DMC0_PHY_CTL2               ((volatile uint32_t *)REG_DMC0_PHY_CTL2)                /* DMC0 PHY Control 2 Register */
-#define pREG_DMC0_PHY_CTL3               ((volatile uint32_t *)REG_DMC0_PHY_CTL3)                /* DMC0 PHY Control 3 Register */
-#define pREG_DMC0_PADCTL                 ((volatile uint32_t *)REG_DMC0_PADCTL)                  /* DMC0 PAD Control Register */
-
-
-/* =========================================================================
-       SCB0
-   ========================================================================= */
-#define pREG_SCB0_ARBR0                  ((volatile uint32_t *)REG_SCB0_ARBR0)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR1                  ((volatile uint32_t *)REG_SCB0_ARBR1)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR2                  ((volatile uint32_t *)REG_SCB0_ARBR2)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR3                  ((volatile uint32_t *)REG_SCB0_ARBR3)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR4                  ((volatile uint32_t *)REG_SCB0_ARBR4)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR5                  ((volatile uint32_t *)REG_SCB0_ARBR5)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBW0                  ((volatile uint32_t *)REG_SCB0_ARBW0)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW1                  ((volatile uint32_t *)REG_SCB0_ARBW1)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW2                  ((volatile uint32_t *)REG_SCB0_ARBW2)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW3                  ((volatile uint32_t *)REG_SCB0_ARBW3)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW4                  ((volatile uint32_t *)REG_SCB0_ARBW4)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW5                  ((volatile uint32_t *)REG_SCB0_ARBW5)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_SLAVES                 ((volatile uint32_t *)REG_SCB0_SLAVES)                  /* SCB0 Slave Interfaces Number Register */
-#define pREG_SCB0_MASTERS                ((volatile uint32_t *)REG_SCB0_MASTERS)                 /* SCB0 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB1
-   ========================================================================= */
-#define pREG_SCB1_ARBR0                  ((volatile uint32_t *)REG_SCB1_ARBR0)                   /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB1_ARBW0                  ((volatile uint32_t *)REG_SCB1_ARBW0)                   /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB1_SLAVES                 ((volatile uint32_t *)REG_SCB1_SLAVES)                  /* SCB1 Slave Interfaces Number Register */
-#define pREG_SCB1_MASTERS                ((volatile uint32_t *)REG_SCB1_MASTERS)                 /* SCB1 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB2
-   ========================================================================= */
-#define pREG_SCB2_ARBR0                  ((volatile uint32_t *)REG_SCB2_ARBR0)                   /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB2_ARBW0                  ((volatile uint32_t *)REG_SCB2_ARBW0)                   /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB2_SLAVES                 ((volatile uint32_t *)REG_SCB2_SLAVES)                  /* SCB2 Slave Interfaces Number Register */
-#define pREG_SCB2_MASTERS                ((volatile uint32_t *)REG_SCB2_MASTERS)                 /* SCB2 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB3
-   ========================================================================= */
-#define pREG_SCB3_ARBR0                  ((volatile uint32_t *)REG_SCB3_ARBR0)                   /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB3_ARBW0                  ((volatile uint32_t *)REG_SCB3_ARBW0)                   /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB3_SLAVES                 ((volatile uint32_t *)REG_SCB3_SLAVES)                  /* SCB3 Slave Interfaces Number Register */
-#define pREG_SCB3_MASTERS                ((volatile uint32_t *)REG_SCB3_MASTERS)                 /* SCB3 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB4
-   ========================================================================= */
-#define pREG_SCB4_ARBR0                  ((volatile uint32_t *)REG_SCB4_ARBR0)                   /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB4_ARBW0                  ((volatile uint32_t *)REG_SCB4_ARBW0)                   /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB4_SLAVES                 ((volatile uint32_t *)REG_SCB4_SLAVES)                  /* SCB4 Slave Interfaces Number Register */
-#define pREG_SCB4_MASTERS                ((volatile uint32_t *)REG_SCB4_MASTERS)                 /* SCB4 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB5
-   ========================================================================= */
-#define pREG_SCB5_ARBR0                  ((volatile uint32_t *)REG_SCB5_ARBR0)                   /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB5_ARBW0                  ((volatile uint32_t *)REG_SCB5_ARBW0)                   /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB5_SLAVES                 ((volatile uint32_t *)REG_SCB5_SLAVES)                  /* SCB5 Slave Interfaces Number Register */
-#define pREG_SCB5_MASTERS                ((volatile uint32_t *)REG_SCB5_MASTERS)                 /* SCB5 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB6
-   ========================================================================= */
-#define pREG_SCB6_ARBR0                  ((volatile uint32_t *)REG_SCB6_ARBR0)                   /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB6_ARBW0                  ((volatile uint32_t *)REG_SCB6_ARBW0)                   /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB6_SLAVES                 ((volatile uint32_t *)REG_SCB6_SLAVES)                  /* SCB6 Slave Interfaces Number Register */
-#define pREG_SCB6_MASTERS                ((volatile uint32_t *)REG_SCB6_MASTERS)                 /* SCB6 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB7
-   ========================================================================= */
-#define pREG_SCB7_ARBR0                  ((volatile uint32_t *)REG_SCB7_ARBR0)                   /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB7_ARBW0                  ((volatile uint32_t *)REG_SCB7_ARBW0)                   /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB7_SLAVES                 ((volatile uint32_t *)REG_SCB7_SLAVES)                  /* SCB7 Slave Interfaces Number Register */
-#define pREG_SCB7_MASTERS                ((volatile uint32_t *)REG_SCB7_MASTERS)                 /* SCB7 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB8
-   ========================================================================= */
-#define pREG_SCB8_ARBR0                  ((volatile uint32_t *)REG_SCB8_ARBR0)                   /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB8_ARBW0                  ((volatile uint32_t *)REG_SCB8_ARBW0)                   /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB8_SLAVES                 ((volatile uint32_t *)REG_SCB8_SLAVES)                  /* SCB8 Slave Interfaces Number Register */
-#define pREG_SCB8_MASTERS                ((volatile uint32_t *)REG_SCB8_MASTERS)                 /* SCB8 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB9
-   ========================================================================= */
-#define pREG_SCB9_ARBR0                  ((volatile uint32_t *)REG_SCB9_ARBR0)                   /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB9_ARBW0                  ((volatile uint32_t *)REG_SCB9_ARBW0)                   /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB9_SLAVES                 ((volatile uint32_t *)REG_SCB9_SLAVES)                  /* SCB9 Slave Interfaces Number Register */
-#define pREG_SCB9_MASTERS                ((volatile uint32_t *)REG_SCB9_MASTERS)                 /* SCB9 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB10
-   ========================================================================= */
-#define pREG_SCB10_ARBR0                 ((volatile uint32_t *)REG_SCB10_ARBR0)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR1                 ((volatile uint32_t *)REG_SCB10_ARBR1)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR2                 ((volatile uint32_t *)REG_SCB10_ARBR2)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBW0                 ((volatile uint32_t *)REG_SCB10_ARBW0)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW1                 ((volatile uint32_t *)REG_SCB10_ARBW1)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW2                 ((volatile uint32_t *)REG_SCB10_ARBW2)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_SLAVES                ((volatile uint32_t *)REG_SCB10_SLAVES)                 /* SCB10 Slave Interfaces Number Register */
-#define pREG_SCB10_MASTERS               ((volatile uint32_t *)REG_SCB10_MASTERS)                /* SCB10 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB11
-   ========================================================================= */
-#define pREG_SCB11_ARBR0                 ((volatile uint32_t *)REG_SCB11_ARBR0)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR1                 ((volatile uint32_t *)REG_SCB11_ARBR1)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR2                 ((volatile uint32_t *)REG_SCB11_ARBR2)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR3                 ((volatile uint32_t *)REG_SCB11_ARBR3)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR4                 ((volatile uint32_t *)REG_SCB11_ARBR4)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR5                 ((volatile uint32_t *)REG_SCB11_ARBR5)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR6                 ((volatile uint32_t *)REG_SCB11_ARBR6)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBW0                 ((volatile uint32_t *)REG_SCB11_ARBW0)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW1                 ((volatile uint32_t *)REG_SCB11_ARBW1)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW2                 ((volatile uint32_t *)REG_SCB11_ARBW2)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW3                 ((volatile uint32_t *)REG_SCB11_ARBW3)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW4                 ((volatile uint32_t *)REG_SCB11_ARBW4)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW5                 ((volatile uint32_t *)REG_SCB11_ARBW5)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW6                 ((volatile uint32_t *)REG_SCB11_ARBW6)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_SLAVES                ((volatile uint32_t *)REG_SCB11_SLAVES)                 /* SCB11 Slave Interfaces Number Register */
-#define pREG_SCB11_MASTERS               ((volatile uint32_t *)REG_SCB11_MASTERS)                /* SCB11 Master Interfaces Number Register */
-
-
-/* =========================================================================
-       L2CTL0
-   ========================================================================= */
-#define pREG_L2CTL0_CTL                  ((volatile uint32_t *)REG_L2CTL0_CTL)                   /* L2CTL0 Control Register */
-#define pREG_L2CTL0_ACTL_C0              ((volatile uint32_t *)REG_L2CTL0_ACTL_C0)               /* L2CTL0 Access Control Core 0 Register */
-#define pREG_L2CTL0_ACTL_C1              ((volatile uint32_t *)REG_L2CTL0_ACTL_C1)               /* L2CTL0 Access Control Core 1 Register */
-#define pREG_L2CTL0_ACTL_SYS             ((volatile uint32_t *)REG_L2CTL0_ACTL_SYS)              /* L2CTL0 Access Control System Register */
-#define pREG_L2CTL0_STAT                 ((volatile uint32_t *)REG_L2CTL0_STAT)                  /* L2CTL0 Status Register */
-#define pREG_L2CTL0_RPCR                 ((volatile uint32_t *)REG_L2CTL0_RPCR)                  /* L2CTL0 Read Priority Count Register */
-#define pREG_L2CTL0_WPCR                 ((volatile uint32_t *)REG_L2CTL0_WPCR)                  /* L2CTL0 Write Priority Count Register */
-#define pREG_L2CTL0_RFA                  ((void * volatile *)REG_L2CTL0_RFA)                     /* L2CTL0 Refresh Address Register */
-#define pREG_L2CTL0_ERRADDR0             ((void * volatile *)REG_L2CTL0_ERRADDR0)                /* L2CTL0 ECC Error Address 0 Register */
-#define pREG_L2CTL0_ERRADDR1             ((void * volatile *)REG_L2CTL0_ERRADDR1)                /* L2CTL0 ECC Error Address 1 Register */
-#define pREG_L2CTL0_ERRADDR2             ((void * volatile *)REG_L2CTL0_ERRADDR2)                /* L2CTL0 ECC Error Address 2 Register */
-#define pREG_L2CTL0_ERRADDR3             ((void * volatile *)REG_L2CTL0_ERRADDR3)                /* L2CTL0 ECC Error Address 3 Register */
-#define pREG_L2CTL0_ERRADDR4             ((void * volatile *)REG_L2CTL0_ERRADDR4)                /* L2CTL0 ECC Error Address 4 Register */
-#define pREG_L2CTL0_ERRADDR5             ((void * volatile *)REG_L2CTL0_ERRADDR5)                /* L2CTL0 ECC Error Address 5 Register */
-#define pREG_L2CTL0_ERRADDR6             ((void * volatile *)REG_L2CTL0_ERRADDR6)                /* L2CTL0 ECC Error Address 6 Register */
-#define pREG_L2CTL0_ERRADDR7             ((void * volatile *)REG_L2CTL0_ERRADDR7)                /* L2CTL0 ECC Error Address 7 Register */
-#define pREG_L2CTL0_ET0                  ((volatile uint32_t *)REG_L2CTL0_ET0)                   /* L2CTL0 Error Type 0 Register */
-#define pREG_L2CTL0_EADDR0               ((void * volatile *)REG_L2CTL0_EADDR0)                  /* L2CTL0 Error Type 0 Address Register */
-#define pREG_L2CTL0_ET1                  ((volatile uint32_t *)REG_L2CTL0_ET1)                   /* L2CTL0 Error Type 1 Register */
-#define pREG_L2CTL0_EADDR1               ((void * volatile *)REG_L2CTL0_EADDR1)                  /* L2CTL0 Error Type 1 Address Register */
-
-
-/* =========================================================================
-       SEC0
-   ========================================================================= */
-
-/*    SEC Core Interface (SCI) Registers    */
-#define pREG_SEC0_CCTL0                  ((volatile uint32_t *)REG_SEC0_CCTL0)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CCTL1                  ((volatile uint32_t *)REG_SEC0_CCTL1)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CSTAT0                 ((volatile uint32_t *)REG_SEC0_CSTAT0)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CSTAT1                 ((volatile uint32_t *)REG_SEC0_CSTAT1)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CPND0                  ((volatile uint32_t *)REG_SEC0_CPND0)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CPND1                  ((volatile uint32_t *)REG_SEC0_CPND1)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CACT0                  ((volatile uint32_t *)REG_SEC0_CACT0)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CACT1                  ((volatile uint32_t *)REG_SEC0_CACT1)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CPMSK0                 ((volatile uint32_t *)REG_SEC0_CPMSK0)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CPMSK1                 ((volatile uint32_t *)REG_SEC0_CPMSK1)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CGMSK0                 ((volatile uint32_t *)REG_SEC0_CGMSK0)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CGMSK1                 ((volatile uint32_t *)REG_SEC0_CGMSK1)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CPLVL0                 ((volatile uint32_t *)REG_SEC0_CPLVL0)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CPLVL1                 ((volatile uint32_t *)REG_SEC0_CPLVL1)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CSID0                  ((volatile uint32_t *)REG_SEC0_CSID0)                   /* SEC0 SCI Source ID Register n */
-#define pREG_SEC0_CSID1                  ((volatile uint32_t *)REG_SEC0_CSID1)                   /* SEC0 SCI Source ID Register n */
-
-/*    SEC Fault Management Interface (SFI) Registers    */
-#define pREG_SEC0_FCTL                   ((volatile uint32_t *)REG_SEC0_FCTL)                    /* SEC0 Fault Control Register */
-#define pREG_SEC0_FSTAT                  ((volatile uint32_t *)REG_SEC0_FSTAT)                   /* SEC0 Fault Status Register */
-#define pREG_SEC0_FSID                   ((volatile uint32_t *)REG_SEC0_FSID)                    /* SEC0 Fault Source ID Register */
-#define pREG_SEC0_FEND                   ((volatile uint32_t *)REG_SEC0_FEND)                    /* SEC0 Fault End Register */
-#define pREG_SEC0_FDLY                   ((volatile uint32_t *)REG_SEC0_FDLY)                    /* SEC0 Fault Delay Register */
-#define pREG_SEC0_FDLY_CUR               ((volatile uint32_t *)REG_SEC0_FDLY_CUR)                /* SEC0 Fault Delay Current Register */
-#define pREG_SEC0_FSRDLY                 ((volatile uint32_t *)REG_SEC0_FSRDLY)                  /* SEC0 Fault System Reset Delay Register */
-#define pREG_SEC0_FSRDLY_CUR             ((volatile uint32_t *)REG_SEC0_FSRDLY_CUR)              /* SEC0 Fault System Reset Delay Current Register */
-#define pREG_SEC0_FCOPP                  ((volatile uint32_t *)REG_SEC0_FCOPP)                   /* SEC0 Fault COP Period Register */
-#define pREG_SEC0_FCOPP_CUR              ((volatile uint32_t *)REG_SEC0_FCOPP_CUR)               /* SEC0 Fault COP Period Current Register */
-
-/*    SEC Global Registers    */
-#define pREG_SEC0_GCTL                   ((volatile uint32_t *)REG_SEC0_GCTL)                    /* SEC0 Global Control Register */
-#define pREG_SEC0_GSTAT                  ((volatile uint32_t *)REG_SEC0_GSTAT)                   /* SEC0 Global Status Register */
-#define pREG_SEC0_RAISE                  ((volatile uint32_t *)REG_SEC0_RAISE)                   /* SEC0 Global Raise Register */
-#define pREG_SEC0_END                    ((volatile uint32_t *)REG_SEC0_END)                     /* SEC0 Global End Register */
-
-/*    SEC Source Interface (SSI) Registers    */
-#define pREG_SEC0_SCTL0                  ((volatile uint32_t *)REG_SEC0_SCTL0)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL1                  ((volatile uint32_t *)REG_SEC0_SCTL1)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL2                  ((volatile uint32_t *)REG_SEC0_SCTL2)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL3                  ((volatile uint32_t *)REG_SEC0_SCTL3)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL4                  ((volatile uint32_t *)REG_SEC0_SCTL4)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL5                  ((volatile uint32_t *)REG_SEC0_SCTL5)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL6                  ((volatile uint32_t *)REG_SEC0_SCTL6)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL7                  ((volatile uint32_t *)REG_SEC0_SCTL7)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL8                  ((volatile uint32_t *)REG_SEC0_SCTL8)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL9                  ((volatile uint32_t *)REG_SEC0_SCTL9)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL10                 ((volatile uint32_t *)REG_SEC0_SCTL10)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL11                 ((volatile uint32_t *)REG_SEC0_SCTL11)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL12                 ((volatile uint32_t *)REG_SEC0_SCTL12)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL13                 ((volatile uint32_t *)REG_SEC0_SCTL13)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL14                 ((volatile uint32_t *)REG_SEC0_SCTL14)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL15                 ((volatile uint32_t *)REG_SEC0_SCTL15)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL16                 ((volatile uint32_t *)REG_SEC0_SCTL16)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL17                 ((volatile uint32_t *)REG_SEC0_SCTL17)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL18                 ((volatile uint32_t *)REG_SEC0_SCTL18)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL19                 ((volatile uint32_t *)REG_SEC0_SCTL19)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL20                 ((volatile uint32_t *)REG_SEC0_SCTL20)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL21                 ((volatile uint32_t *)REG_SEC0_SCTL21)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL22                 ((volatile uint32_t *)REG_SEC0_SCTL22)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL23                 ((volatile uint32_t *)REG_SEC0_SCTL23)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL24                 ((volatile uint32_t *)REG_SEC0_SCTL24)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL25                 ((volatile uint32_t *)REG_SEC0_SCTL25)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL26                 ((volatile uint32_t *)REG_SEC0_SCTL26)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL27                 ((volatile uint32_t *)REG_SEC0_SCTL27)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL28                 ((volatile uint32_t *)REG_SEC0_SCTL28)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL29                 ((volatile uint32_t *)REG_SEC0_SCTL29)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL30                 ((volatile uint32_t *)REG_SEC0_SCTL30)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL31                 ((volatile uint32_t *)REG_SEC0_SCTL31)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL32                 ((volatile uint32_t *)REG_SEC0_SCTL32)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL33                 ((volatile uint32_t *)REG_SEC0_SCTL33)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL34                 ((volatile uint32_t *)REG_SEC0_SCTL34)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL35                 ((volatile uint32_t *)REG_SEC0_SCTL35)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL36                 ((volatile uint32_t *)REG_SEC0_SCTL36)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL37                 ((volatile uint32_t *)REG_SEC0_SCTL37)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL38                 ((volatile uint32_t *)REG_SEC0_SCTL38)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL39                 ((volatile uint32_t *)REG_SEC0_SCTL39)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL40                 ((volatile uint32_t *)REG_SEC0_SCTL40)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL41                 ((volatile uint32_t *)REG_SEC0_SCTL41)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL42                 ((volatile uint32_t *)REG_SEC0_SCTL42)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL43                 ((volatile uint32_t *)REG_SEC0_SCTL43)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL44                 ((volatile uint32_t *)REG_SEC0_SCTL44)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL45                 ((volatile uint32_t *)REG_SEC0_SCTL45)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL46                 ((volatile uint32_t *)REG_SEC0_SCTL46)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL47                 ((volatile uint32_t *)REG_SEC0_SCTL47)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL48                 ((volatile uint32_t *)REG_SEC0_SCTL48)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL49                 ((volatile uint32_t *)REG_SEC0_SCTL49)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL50                 ((volatile uint32_t *)REG_SEC0_SCTL50)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL51                 ((volatile uint32_t *)REG_SEC0_SCTL51)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL52                 ((volatile uint32_t *)REG_SEC0_SCTL52)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL53                 ((volatile uint32_t *)REG_SEC0_SCTL53)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL54                 ((volatile uint32_t *)REG_SEC0_SCTL54)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL55                 ((volatile uint32_t *)REG_SEC0_SCTL55)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL56                 ((volatile uint32_t *)REG_SEC0_SCTL56)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL57                 ((volatile uint32_t *)REG_SEC0_SCTL57)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL58                 ((volatile uint32_t *)REG_SEC0_SCTL58)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL59                 ((volatile uint32_t *)REG_SEC0_SCTL59)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL60                 ((volatile uint32_t *)REG_SEC0_SCTL60)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL61                 ((volatile uint32_t *)REG_SEC0_SCTL61)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL62                 ((volatile uint32_t *)REG_SEC0_SCTL62)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL63                 ((volatile uint32_t *)REG_SEC0_SCTL63)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL64                 ((volatile uint32_t *)REG_SEC0_SCTL64)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL65                 ((volatile uint32_t *)REG_SEC0_SCTL65)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL66                 ((volatile uint32_t *)REG_SEC0_SCTL66)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL67                 ((volatile uint32_t *)REG_SEC0_SCTL67)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL68                 ((volatile uint32_t *)REG_SEC0_SCTL68)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL69                 ((volatile uint32_t *)REG_SEC0_SCTL69)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL70                 ((volatile uint32_t *)REG_SEC0_SCTL70)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL71                 ((volatile uint32_t *)REG_SEC0_SCTL71)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL72                 ((volatile uint32_t *)REG_SEC0_SCTL72)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL73                 ((volatile uint32_t *)REG_SEC0_SCTL73)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL74                 ((volatile uint32_t *)REG_SEC0_SCTL74)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL75                 ((volatile uint32_t *)REG_SEC0_SCTL75)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL76                 ((volatile uint32_t *)REG_SEC0_SCTL76)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL77                 ((volatile uint32_t *)REG_SEC0_SCTL77)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL78                 ((volatile uint32_t *)REG_SEC0_SCTL78)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL79                 ((volatile uint32_t *)REG_SEC0_SCTL79)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL80                 ((volatile uint32_t *)REG_SEC0_SCTL80)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL81                 ((volatile uint32_t *)REG_SEC0_SCTL81)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL82                 ((volatile uint32_t *)REG_SEC0_SCTL82)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL83                 ((volatile uint32_t *)REG_SEC0_SCTL83)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL84                 ((volatile uint32_t *)REG_SEC0_SCTL84)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL85                 ((volatile uint32_t *)REG_SEC0_SCTL85)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL86                 ((volatile uint32_t *)REG_SEC0_SCTL86)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL87                 ((volatile uint32_t *)REG_SEC0_SCTL87)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL88                 ((volatile uint32_t *)REG_SEC0_SCTL88)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL89                 ((volatile uint32_t *)REG_SEC0_SCTL89)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL90                 ((volatile uint32_t *)REG_SEC0_SCTL90)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL91                 ((volatile uint32_t *)REG_SEC0_SCTL91)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL92                 ((volatile uint32_t *)REG_SEC0_SCTL92)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL93                 ((volatile uint32_t *)REG_SEC0_SCTL93)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL94                 ((volatile uint32_t *)REG_SEC0_SCTL94)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL95                 ((volatile uint32_t *)REG_SEC0_SCTL95)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL96                 ((volatile uint32_t *)REG_SEC0_SCTL96)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL97                 ((volatile uint32_t *)REG_SEC0_SCTL97)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL98                 ((volatile uint32_t *)REG_SEC0_SCTL98)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL99                 ((volatile uint32_t *)REG_SEC0_SCTL99)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL100                ((volatile uint32_t *)REG_SEC0_SCTL100)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL101                ((volatile uint32_t *)REG_SEC0_SCTL101)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL102                ((volatile uint32_t *)REG_SEC0_SCTL102)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL103                ((volatile uint32_t *)REG_SEC0_SCTL103)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL104                ((volatile uint32_t *)REG_SEC0_SCTL104)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL105                ((volatile uint32_t *)REG_SEC0_SCTL105)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL106                ((volatile uint32_t *)REG_SEC0_SCTL106)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL107                ((volatile uint32_t *)REG_SEC0_SCTL107)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL108                ((volatile uint32_t *)REG_SEC0_SCTL108)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL109                ((volatile uint32_t *)REG_SEC0_SCTL109)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL110                ((volatile uint32_t *)REG_SEC0_SCTL110)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL111                ((volatile uint32_t *)REG_SEC0_SCTL111)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL112                ((volatile uint32_t *)REG_SEC0_SCTL112)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL113                ((volatile uint32_t *)REG_SEC0_SCTL113)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL114                ((volatile uint32_t *)REG_SEC0_SCTL114)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL115                ((volatile uint32_t *)REG_SEC0_SCTL115)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL116                ((volatile uint32_t *)REG_SEC0_SCTL116)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL117                ((volatile uint32_t *)REG_SEC0_SCTL117)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL118                ((volatile uint32_t *)REG_SEC0_SCTL118)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL119                ((volatile uint32_t *)REG_SEC0_SCTL119)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL120                ((volatile uint32_t *)REG_SEC0_SCTL120)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL121                ((volatile uint32_t *)REG_SEC0_SCTL121)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL122                ((volatile uint32_t *)REG_SEC0_SCTL122)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL123                ((volatile uint32_t *)REG_SEC0_SCTL123)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL124                ((volatile uint32_t *)REG_SEC0_SCTL124)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL125                ((volatile uint32_t *)REG_SEC0_SCTL125)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL126                ((volatile uint32_t *)REG_SEC0_SCTL126)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL127                ((volatile uint32_t *)REG_SEC0_SCTL127)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL128                ((volatile uint32_t *)REG_SEC0_SCTL128)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL129                ((volatile uint32_t *)REG_SEC0_SCTL129)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL130                ((volatile uint32_t *)REG_SEC0_SCTL130)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL131                ((volatile uint32_t *)REG_SEC0_SCTL131)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL132                ((volatile uint32_t *)REG_SEC0_SCTL132)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL133                ((volatile uint32_t *)REG_SEC0_SCTL133)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL134                ((volatile uint32_t *)REG_SEC0_SCTL134)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL135                ((volatile uint32_t *)REG_SEC0_SCTL135)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL136                ((volatile uint32_t *)REG_SEC0_SCTL136)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL137                ((volatile uint32_t *)REG_SEC0_SCTL137)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL138                ((volatile uint32_t *)REG_SEC0_SCTL138)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL139                ((volatile uint32_t *)REG_SEC0_SCTL139)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SSTAT0                 ((volatile uint32_t *)REG_SEC0_SSTAT0)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT1                 ((volatile uint32_t *)REG_SEC0_SSTAT1)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT2                 ((volatile uint32_t *)REG_SEC0_SSTAT2)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT3                 ((volatile uint32_t *)REG_SEC0_SSTAT3)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT4                 ((volatile uint32_t *)REG_SEC0_SSTAT4)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT5                 ((volatile uint32_t *)REG_SEC0_SSTAT5)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT6                 ((volatile uint32_t *)REG_SEC0_SSTAT6)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT7                 ((volatile uint32_t *)REG_SEC0_SSTAT7)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT8                 ((volatile uint32_t *)REG_SEC0_SSTAT8)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT9                 ((volatile uint32_t *)REG_SEC0_SSTAT9)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT10                ((volatile uint32_t *)REG_SEC0_SSTAT10)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT11                ((volatile uint32_t *)REG_SEC0_SSTAT11)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT12                ((volatile uint32_t *)REG_SEC0_SSTAT12)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT13                ((volatile uint32_t *)REG_SEC0_SSTAT13)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT14                ((volatile uint32_t *)REG_SEC0_SSTAT14)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT15                ((volatile uint32_t *)REG_SEC0_SSTAT15)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT16                ((volatile uint32_t *)REG_SEC0_SSTAT16)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT17                ((volatile uint32_t *)REG_SEC0_SSTAT17)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT18                ((volatile uint32_t *)REG_SEC0_SSTAT18)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT19                ((volatile uint32_t *)REG_SEC0_SSTAT19)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT20                ((volatile uint32_t *)REG_SEC0_SSTAT20)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT21                ((volatile uint32_t *)REG_SEC0_SSTAT21)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT22                ((volatile uint32_t *)REG_SEC0_SSTAT22)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT23                ((volatile uint32_t *)REG_SEC0_SSTAT23)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT24                ((volatile uint32_t *)REG_SEC0_SSTAT24)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT25                ((volatile uint32_t *)REG_SEC0_SSTAT25)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT26                ((volatile uint32_t *)REG_SEC0_SSTAT26)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT27                ((volatile uint32_t *)REG_SEC0_SSTAT27)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT28                ((volatile uint32_t *)REG_SEC0_SSTAT28)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT29                ((volatile uint32_t *)REG_SEC0_SSTAT29)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT30                ((volatile uint32_t *)REG_SEC0_SSTAT30)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT31                ((volatile uint32_t *)REG_SEC0_SSTAT31)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT32                ((volatile uint32_t *)REG_SEC0_SSTAT32)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT33                ((volatile uint32_t *)REG_SEC0_SSTAT33)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT34                ((volatile uint32_t *)REG_SEC0_SSTAT34)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT35                ((volatile uint32_t *)REG_SEC0_SSTAT35)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT36                ((volatile uint32_t *)REG_SEC0_SSTAT36)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT37                ((volatile uint32_t *)REG_SEC0_SSTAT37)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT38                ((volatile uint32_t *)REG_SEC0_SSTAT38)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT39                ((volatile uint32_t *)REG_SEC0_SSTAT39)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT40                ((volatile uint32_t *)REG_SEC0_SSTAT40)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT41                ((volatile uint32_t *)REG_SEC0_SSTAT41)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT42                ((volatile uint32_t *)REG_SEC0_SSTAT42)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT43                ((volatile uint32_t *)REG_SEC0_SSTAT43)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT44                ((volatile uint32_t *)REG_SEC0_SSTAT44)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT45                ((volatile uint32_t *)REG_SEC0_SSTAT45)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT46                ((volatile uint32_t *)REG_SEC0_SSTAT46)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT47                ((volatile uint32_t *)REG_SEC0_SSTAT47)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT48                ((volatile uint32_t *)REG_SEC0_SSTAT48)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT49                ((volatile uint32_t *)REG_SEC0_SSTAT49)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT50                ((volatile uint32_t *)REG_SEC0_SSTAT50)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT51                ((volatile uint32_t *)REG_SEC0_SSTAT51)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT52                ((volatile uint32_t *)REG_SEC0_SSTAT52)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT53                ((volatile uint32_t *)REG_SEC0_SSTAT53)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT54                ((volatile uint32_t *)REG_SEC0_SSTAT54)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT55                ((volatile uint32_t *)REG_SEC0_SSTAT55)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT56                ((volatile uint32_t *)REG_SEC0_SSTAT56)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT57                ((volatile uint32_t *)REG_SEC0_SSTAT57)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT58                ((volatile uint32_t *)REG_SEC0_SSTAT58)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT59                ((volatile uint32_t *)REG_SEC0_SSTAT59)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT60                ((volatile uint32_t *)REG_SEC0_SSTAT60)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT61                ((volatile uint32_t *)REG_SEC0_SSTAT61)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT62                ((volatile uint32_t *)REG_SEC0_SSTAT62)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT63                ((volatile uint32_t *)REG_SEC0_SSTAT63)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT64                ((volatile uint32_t *)REG_SEC0_SSTAT64)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT65                ((volatile uint32_t *)REG_SEC0_SSTAT65)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT66                ((volatile uint32_t *)REG_SEC0_SSTAT66)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT67                ((volatile uint32_t *)REG_SEC0_SSTAT67)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT68                ((volatile uint32_t *)REG_SEC0_SSTAT68)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT69                ((volatile uint32_t *)REG_SEC0_SSTAT69)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT70                ((volatile uint32_t *)REG_SEC0_SSTAT70)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT71                ((volatile uint32_t *)REG_SEC0_SSTAT71)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT72                ((volatile uint32_t *)REG_SEC0_SSTAT72)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT73                ((volatile uint32_t *)REG_SEC0_SSTAT73)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT74                ((volatile uint32_t *)REG_SEC0_SSTAT74)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT75                ((volatile uint32_t *)REG_SEC0_SSTAT75)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT76                ((volatile uint32_t *)REG_SEC0_SSTAT76)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT77                ((volatile uint32_t *)REG_SEC0_SSTAT77)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT78                ((volatile uint32_t *)REG_SEC0_SSTAT78)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT79                ((volatile uint32_t *)REG_SEC0_SSTAT79)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT80                ((volatile uint32_t *)REG_SEC0_SSTAT80)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT81                ((volatile uint32_t *)REG_SEC0_SSTAT81)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT82                ((volatile uint32_t *)REG_SEC0_SSTAT82)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT83                ((volatile uint32_t *)REG_SEC0_SSTAT83)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT84                ((volatile uint32_t *)REG_SEC0_SSTAT84)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT85                ((volatile uint32_t *)REG_SEC0_SSTAT85)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT86                ((volatile uint32_t *)REG_SEC0_SSTAT86)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT87                ((volatile uint32_t *)REG_SEC0_SSTAT87)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT88                ((volatile uint32_t *)REG_SEC0_SSTAT88)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT89                ((volatile uint32_t *)REG_SEC0_SSTAT89)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT90                ((volatile uint32_t *)REG_SEC0_SSTAT90)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT91                ((volatile uint32_t *)REG_SEC0_SSTAT91)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT92                ((volatile uint32_t *)REG_SEC0_SSTAT92)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT93                ((volatile uint32_t *)REG_SEC0_SSTAT93)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT94                ((volatile uint32_t *)REG_SEC0_SSTAT94)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT95                ((volatile uint32_t *)REG_SEC0_SSTAT95)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT96                ((volatile uint32_t *)REG_SEC0_SSTAT96)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT97                ((volatile uint32_t *)REG_SEC0_SSTAT97)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT98                ((volatile uint32_t *)REG_SEC0_SSTAT98)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT99                ((volatile uint32_t *)REG_SEC0_SSTAT99)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT100               ((volatile uint32_t *)REG_SEC0_SSTAT100)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT101               ((volatile uint32_t *)REG_SEC0_SSTAT101)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT102               ((volatile uint32_t *)REG_SEC0_SSTAT102)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT103               ((volatile uint32_t *)REG_SEC0_SSTAT103)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT104               ((volatile uint32_t *)REG_SEC0_SSTAT104)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT105               ((volatile uint32_t *)REG_SEC0_SSTAT105)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT106               ((volatile uint32_t *)REG_SEC0_SSTAT106)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT107               ((volatile uint32_t *)REG_SEC0_SSTAT107)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT108               ((volatile uint32_t *)REG_SEC0_SSTAT108)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT109               ((volatile uint32_t *)REG_SEC0_SSTAT109)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT110               ((volatile uint32_t *)REG_SEC0_SSTAT110)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT111               ((volatile uint32_t *)REG_SEC0_SSTAT111)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT112               ((volatile uint32_t *)REG_SEC0_SSTAT112)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT113               ((volatile uint32_t *)REG_SEC0_SSTAT113)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT114               ((volatile uint32_t *)REG_SEC0_SSTAT114)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT115               ((volatile uint32_t *)REG_SEC0_SSTAT115)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT116               ((volatile uint32_t *)REG_SEC0_SSTAT116)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT117               ((volatile uint32_t *)REG_SEC0_SSTAT117)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT118               ((volatile uint32_t *)REG_SEC0_SSTAT118)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT119               ((volatile uint32_t *)REG_SEC0_SSTAT119)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT120               ((volatile uint32_t *)REG_SEC0_SSTAT120)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT121               ((volatile uint32_t *)REG_SEC0_SSTAT121)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT122               ((volatile uint32_t *)REG_SEC0_SSTAT122)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT123               ((volatile uint32_t *)REG_SEC0_SSTAT123)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT124               ((volatile uint32_t *)REG_SEC0_SSTAT124)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT125               ((volatile uint32_t *)REG_SEC0_SSTAT125)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT126               ((volatile uint32_t *)REG_SEC0_SSTAT126)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT127               ((volatile uint32_t *)REG_SEC0_SSTAT127)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT128               ((volatile uint32_t *)REG_SEC0_SSTAT128)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT129               ((volatile uint32_t *)REG_SEC0_SSTAT129)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT130               ((volatile uint32_t *)REG_SEC0_SSTAT130)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT131               ((volatile uint32_t *)REG_SEC0_SSTAT131)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT132               ((volatile uint32_t *)REG_SEC0_SSTAT132)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT133               ((volatile uint32_t *)REG_SEC0_SSTAT133)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT134               ((volatile uint32_t *)REG_SEC0_SSTAT134)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT135               ((volatile uint32_t *)REG_SEC0_SSTAT135)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT136               ((volatile uint32_t *)REG_SEC0_SSTAT136)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT137               ((volatile uint32_t *)REG_SEC0_SSTAT137)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT138               ((volatile uint32_t *)REG_SEC0_SSTAT138)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT139               ((volatile uint32_t *)REG_SEC0_SSTAT139)                /* SEC0 Source Status Register n */
-
-
-/* =========================================================================
-       TRU0
-   ========================================================================= */
-#define pREG_TRU0_SSR0                   ((volatile uint32_t *)REG_TRU0_SSR0)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR1                   ((volatile uint32_t *)REG_TRU0_SSR1)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR2                   ((volatile uint32_t *)REG_TRU0_SSR2)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR3                   ((volatile uint32_t *)REG_TRU0_SSR3)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR4                   ((volatile uint32_t *)REG_TRU0_SSR4)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR5                   ((volatile uint32_t *)REG_TRU0_SSR5)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR6                   ((volatile uint32_t *)REG_TRU0_SSR6)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR7                   ((volatile uint32_t *)REG_TRU0_SSR7)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR8                   ((volatile uint32_t *)REG_TRU0_SSR8)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR9                   ((volatile uint32_t *)REG_TRU0_SSR9)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR10                  ((volatile uint32_t *)REG_TRU0_SSR10)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR11                  ((volatile uint32_t *)REG_TRU0_SSR11)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR12                  ((volatile uint32_t *)REG_TRU0_SSR12)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR13                  ((volatile uint32_t *)REG_TRU0_SSR13)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR14                  ((volatile uint32_t *)REG_TRU0_SSR14)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR15                  ((volatile uint32_t *)REG_TRU0_SSR15)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR16                  ((volatile uint32_t *)REG_TRU0_SSR16)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR17                  ((volatile uint32_t *)REG_TRU0_SSR17)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR18                  ((volatile uint32_t *)REG_TRU0_SSR18)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR19                  ((volatile uint32_t *)REG_TRU0_SSR19)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR20                  ((volatile uint32_t *)REG_TRU0_SSR20)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR21                  ((volatile uint32_t *)REG_TRU0_SSR21)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR22                  ((volatile uint32_t *)REG_TRU0_SSR22)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR23                  ((volatile uint32_t *)REG_TRU0_SSR23)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR24                  ((volatile uint32_t *)REG_TRU0_SSR24)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR25                  ((volatile uint32_t *)REG_TRU0_SSR25)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR26                  ((volatile uint32_t *)REG_TRU0_SSR26)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR27                  ((volatile uint32_t *)REG_TRU0_SSR27)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR28                  ((volatile uint32_t *)REG_TRU0_SSR28)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR29                  ((volatile uint32_t *)REG_TRU0_SSR29)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR30                  ((volatile uint32_t *)REG_TRU0_SSR30)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR31                  ((volatile uint32_t *)REG_TRU0_SSR31)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR32                  ((volatile uint32_t *)REG_TRU0_SSR32)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR33                  ((volatile uint32_t *)REG_TRU0_SSR33)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR34                  ((volatile uint32_t *)REG_TRU0_SSR34)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR35                  ((volatile uint32_t *)REG_TRU0_SSR35)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR36                  ((volatile uint32_t *)REG_TRU0_SSR36)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR37                  ((volatile uint32_t *)REG_TRU0_SSR37)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR38                  ((volatile uint32_t *)REG_TRU0_SSR38)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR39                  ((volatile uint32_t *)REG_TRU0_SSR39)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR40                  ((volatile uint32_t *)REG_TRU0_SSR40)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR41                  ((volatile uint32_t *)REG_TRU0_SSR41)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR42                  ((volatile uint32_t *)REG_TRU0_SSR42)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR43                  ((volatile uint32_t *)REG_TRU0_SSR43)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR44                  ((volatile uint32_t *)REG_TRU0_SSR44)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR45                  ((volatile uint32_t *)REG_TRU0_SSR45)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR46                  ((volatile uint32_t *)REG_TRU0_SSR46)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR47                  ((volatile uint32_t *)REG_TRU0_SSR47)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR48                  ((volatile uint32_t *)REG_TRU0_SSR48)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR49                  ((volatile uint32_t *)REG_TRU0_SSR49)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR50                  ((volatile uint32_t *)REG_TRU0_SSR50)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR51                  ((volatile uint32_t *)REG_TRU0_SSR51)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR52                  ((volatile uint32_t *)REG_TRU0_SSR52)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR53                  ((volatile uint32_t *)REG_TRU0_SSR53)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR54                  ((volatile uint32_t *)REG_TRU0_SSR54)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR55                  ((volatile uint32_t *)REG_TRU0_SSR55)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR56                  ((volatile uint32_t *)REG_TRU0_SSR56)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR57                  ((volatile uint32_t *)REG_TRU0_SSR57)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR58                  ((volatile uint32_t *)REG_TRU0_SSR58)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR59                  ((volatile uint32_t *)REG_TRU0_SSR59)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR60                  ((volatile uint32_t *)REG_TRU0_SSR60)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR61                  ((volatile uint32_t *)REG_TRU0_SSR61)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR62                  ((volatile uint32_t *)REG_TRU0_SSR62)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR63                  ((volatile uint32_t *)REG_TRU0_SSR63)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR64                  ((volatile uint32_t *)REG_TRU0_SSR64)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR65                  ((volatile uint32_t *)REG_TRU0_SSR65)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR66                  ((volatile uint32_t *)REG_TRU0_SSR66)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR67                  ((volatile uint32_t *)REG_TRU0_SSR67)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR68                  ((volatile uint32_t *)REG_TRU0_SSR68)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR69                  ((volatile uint32_t *)REG_TRU0_SSR69)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR70                  ((volatile uint32_t *)REG_TRU0_SSR70)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR71                  ((volatile uint32_t *)REG_TRU0_SSR71)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR72                  ((volatile uint32_t *)REG_TRU0_SSR72)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR73                  ((volatile uint32_t *)REG_TRU0_SSR73)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR74                  ((volatile uint32_t *)REG_TRU0_SSR74)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR75                  ((volatile uint32_t *)REG_TRU0_SSR75)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR76                  ((volatile uint32_t *)REG_TRU0_SSR76)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR77                  ((volatile uint32_t *)REG_TRU0_SSR77)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR78                  ((volatile uint32_t *)REG_TRU0_SSR78)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR79                  ((volatile uint32_t *)REG_TRU0_SSR79)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR80                  ((volatile uint32_t *)REG_TRU0_SSR80)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR81                  ((volatile uint32_t *)REG_TRU0_SSR81)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR82                  ((volatile uint32_t *)REG_TRU0_SSR82)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR83                  ((volatile uint32_t *)REG_TRU0_SSR83)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR84                  ((volatile uint32_t *)REG_TRU0_SSR84)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR85                  ((volatile uint32_t *)REG_TRU0_SSR85)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR86                  ((volatile uint32_t *)REG_TRU0_SSR86)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_MTR                    ((volatile uint32_t *)REG_TRU0_MTR)                     /* TRU0 Master Trigger Register */
-#define pREG_TRU0_ERRADDR                ((volatile uint32_t *)REG_TRU0_ERRADDR)                 /* TRU0 Error Address Register */
-#define pREG_TRU0_STAT                   ((volatile uint32_t *)REG_TRU0_STAT)                    /* TRU0 Status Information Register */
-#define pREG_TRU0_REVID                  ((volatile uint32_t *)REG_TRU0_REVID)                   /* TRU0 Revision ID Register */
-#define pREG_TRU0_GCTL                   ((volatile uint32_t *)REG_TRU0_GCTL)                    /* TRU0 Global Control Register */
-
-
-/* =========================================================================
-       RCU0
-   ========================================================================= */
-#define pREG_RCU0_CTL                    ((volatile uint32_t *)REG_RCU0_CTL)                     /* RCU0 Control Register */
-#define pREG_RCU0_STAT                   ((volatile uint32_t *)REG_RCU0_STAT)                    /* RCU0 Status Register */
-#define pREG_RCU0_CRCTL                  ((volatile uint32_t *)REG_RCU0_CRCTL)                   /* RCU0 Core Reset Control Register */
-#define pREG_RCU0_CRSTAT                 ((volatile uint32_t *)REG_RCU0_CRSTAT)                  /* RCU0 Core Reset Status Register */
-#define pREG_RCU0_SIDIS                  ((volatile uint32_t *)REG_RCU0_SIDIS)                   /* RCU0 System Interface Disable Register */
-#define pREG_RCU0_SISTAT                 ((volatile uint32_t *)REG_RCU0_SISTAT)                  /* RCU0 System Interface Status Register */
-#define pREG_RCU0_SVECT_LCK              ((volatile uint32_t *)REG_RCU0_SVECT_LCK)               /* RCU0 SVECT Lock Register */
-#define pREG_RCU0_BCODE                  ((volatile uint32_t *)REG_RCU0_BCODE)                   /* RCU0 Boot Code Register */
-#define pREG_RCU0_SVECT0                 ((void * volatile *)REG_RCU0_SVECT0)                    /* RCU0 Software Vector Register n */
-#define pREG_RCU0_SVECT1                 ((void * volatile *)REG_RCU0_SVECT1)                    /* RCU0 Software Vector Register n */
-
-
-/* =========================================================================
-       SPU0
-   ========================================================================= */
-#define pREG_SPU0_CTL                    ((volatile uint32_t *)REG_SPU0_CTL)                     /* SPU0 Control Register */
-#define pREG_SPU0_STAT                   ((volatile uint32_t *)REG_SPU0_STAT)                    /* SPU0 Status Register */
-#define pREG_SPU0_WP0                    ((volatile uint32_t *)REG_SPU0_WP0)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP1                    ((volatile uint32_t *)REG_SPU0_WP1)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP2                    ((volatile uint32_t *)REG_SPU0_WP2)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP3                    ((volatile uint32_t *)REG_SPU0_WP3)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP4                    ((volatile uint32_t *)REG_SPU0_WP4)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP5                    ((volatile uint32_t *)REG_SPU0_WP5)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP6                    ((volatile uint32_t *)REG_SPU0_WP6)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP7                    ((volatile uint32_t *)REG_SPU0_WP7)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP8                    ((volatile uint32_t *)REG_SPU0_WP8)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP9                    ((volatile uint32_t *)REG_SPU0_WP9)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP10                   ((volatile uint32_t *)REG_SPU0_WP10)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP11                   ((volatile uint32_t *)REG_SPU0_WP11)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP12                   ((volatile uint32_t *)REG_SPU0_WP12)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP13                   ((volatile uint32_t *)REG_SPU0_WP13)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP14                   ((volatile uint32_t *)REG_SPU0_WP14)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP15                   ((volatile uint32_t *)REG_SPU0_WP15)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP16                   ((volatile uint32_t *)REG_SPU0_WP16)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP17                   ((volatile uint32_t *)REG_SPU0_WP17)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP18                   ((volatile uint32_t *)REG_SPU0_WP18)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP19                   ((volatile uint32_t *)REG_SPU0_WP19)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP20                   ((volatile uint32_t *)REG_SPU0_WP20)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP21                   ((volatile uint32_t *)REG_SPU0_WP21)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP22                   ((volatile uint32_t *)REG_SPU0_WP22)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP23                   ((volatile uint32_t *)REG_SPU0_WP23)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP24                   ((volatile uint32_t *)REG_SPU0_WP24)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP25                   ((volatile uint32_t *)REG_SPU0_WP25)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP26                   ((volatile uint32_t *)REG_SPU0_WP26)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP27                   ((volatile uint32_t *)REG_SPU0_WP27)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP28                   ((volatile uint32_t *)REG_SPU0_WP28)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP29                   ((volatile uint32_t *)REG_SPU0_WP29)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP30                   ((volatile uint32_t *)REG_SPU0_WP30)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP31                   ((volatile uint32_t *)REG_SPU0_WP31)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP32                   ((volatile uint32_t *)REG_SPU0_WP32)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP33                   ((volatile uint32_t *)REG_SPU0_WP33)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP34                   ((volatile uint32_t *)REG_SPU0_WP34)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP35                   ((volatile uint32_t *)REG_SPU0_WP35)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP36                   ((volatile uint32_t *)REG_SPU0_WP36)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP37                   ((volatile uint32_t *)REG_SPU0_WP37)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP38                   ((volatile uint32_t *)REG_SPU0_WP38)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP39                   ((volatile uint32_t *)REG_SPU0_WP39)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP40                   ((volatile uint32_t *)REG_SPU0_WP40)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP41                   ((volatile uint32_t *)REG_SPU0_WP41)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP42                   ((volatile uint32_t *)REG_SPU0_WP42)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP43                   ((volatile uint32_t *)REG_SPU0_WP43)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP44                   ((volatile uint32_t *)REG_SPU0_WP44)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP45                   ((volatile uint32_t *)REG_SPU0_WP45)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP46                   ((volatile uint32_t *)REG_SPU0_WP46)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP47                   ((volatile uint32_t *)REG_SPU0_WP47)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP48                   ((volatile uint32_t *)REG_SPU0_WP48)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP49                   ((volatile uint32_t *)REG_SPU0_WP49)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP50                   ((volatile uint32_t *)REG_SPU0_WP50)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP51                   ((volatile uint32_t *)REG_SPU0_WP51)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP52                   ((volatile uint32_t *)REG_SPU0_WP52)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP53                   ((volatile uint32_t *)REG_SPU0_WP53)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP54                   ((volatile uint32_t *)REG_SPU0_WP54)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP55                   ((volatile uint32_t *)REG_SPU0_WP55)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP56                   ((volatile uint32_t *)REG_SPU0_WP56)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP57                   ((volatile uint32_t *)REG_SPU0_WP57)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP58                   ((volatile uint32_t *)REG_SPU0_WP58)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP59                   ((volatile uint32_t *)REG_SPU0_WP59)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP60                   ((volatile uint32_t *)REG_SPU0_WP60)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP61                   ((volatile uint32_t *)REG_SPU0_WP61)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP62                   ((volatile uint32_t *)REG_SPU0_WP62)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP63                   ((volatile uint32_t *)REG_SPU0_WP63)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP64                   ((volatile uint32_t *)REG_SPU0_WP64)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP65                   ((volatile uint32_t *)REG_SPU0_WP65)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP66                   ((volatile uint32_t *)REG_SPU0_WP66)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP67                   ((volatile uint32_t *)REG_SPU0_WP67)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP68                   ((volatile uint32_t *)REG_SPU0_WP68)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP69                   ((volatile uint32_t *)REG_SPU0_WP69)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP70                   ((volatile uint32_t *)REG_SPU0_WP70)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP71                   ((volatile uint32_t *)REG_SPU0_WP71)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP72                   ((volatile uint32_t *)REG_SPU0_WP72)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP73                   ((volatile uint32_t *)REG_SPU0_WP73)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP74                   ((volatile uint32_t *)REG_SPU0_WP74)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP75                   ((volatile uint32_t *)REG_SPU0_WP75)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP76                   ((volatile uint32_t *)REG_SPU0_WP76)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP77                   ((volatile uint32_t *)REG_SPU0_WP77)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP78                   ((volatile uint32_t *)REG_SPU0_WP78)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP79                   ((volatile uint32_t *)REG_SPU0_WP79)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP80                   ((volatile uint32_t *)REG_SPU0_WP80)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP81                   ((volatile uint32_t *)REG_SPU0_WP81)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP82                   ((volatile uint32_t *)REG_SPU0_WP82)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP83                   ((volatile uint32_t *)REG_SPU0_WP83)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP84                   ((volatile uint32_t *)REG_SPU0_WP84)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP85                   ((volatile uint32_t *)REG_SPU0_WP85)                    /* SPU0 Write Protect Register n */
-
-
-/* =========================================================================
-       CGU0
-   ========================================================================= */
-#define pREG_CGU0_CTL                    ((volatile uint32_t *)REG_CGU0_CTL)                     /* CGU0 Control Register */
-#define pREG_CGU0_STAT                   ((volatile uint32_t *)REG_CGU0_STAT)                    /* CGU0 Status Register */
-#define pREG_CGU0_DIV                    ((volatile uint32_t *)REG_CGU0_DIV)                     /* CGU0 Divisor Register */
-#define pREG_CGU0_CLKOUTSEL              ((volatile uint32_t *)REG_CGU0_CLKOUTSEL)               /* CGU0 CLKOUT Select Register */
-
-
-/* =========================================================================
-       DPM0
-   ========================================================================= */
-#define pREG_DPM0_CTL                    ((volatile uint32_t *)REG_DPM0_CTL)                     /* DPM0 Control Register */
-#define pREG_DPM0_STAT                   ((volatile uint32_t *)REG_DPM0_STAT)                    /* DPM0 Status Register */
-#define pREG_DPM0_CCBF_DIS               ((volatile uint32_t *)REG_DPM0_CCBF_DIS)                /* DPM0 Core Clock Buffer Disable Register */
-#define pREG_DPM0_CCBF_EN                ((volatile uint32_t *)REG_DPM0_CCBF_EN)                 /* DPM0 Core Clock Buffer Enable Register */
-#define pREG_DPM0_CCBF_STAT              ((volatile uint32_t *)REG_DPM0_CCBF_STAT)               /* DPM0 Core Clock Buffer Status Register */
-#define pREG_DPM0_CCBF_STAT_STKY         ((volatile uint32_t *)REG_DPM0_CCBF_STAT_STKY)          /* DPM0 Core Clock Buffer Status Sticky Register */
-#define pREG_DPM0_SCBF_DIS               ((volatile uint32_t *)REG_DPM0_SCBF_DIS)                /* DPM0 System Clock Buffer Disable Register */
-#define pREG_DPM0_WAKE_EN                ((volatile uint32_t *)REG_DPM0_WAKE_EN)                 /* DPM0 Wakeup Enable Register */
-#define pREG_DPM0_WAKE_POL               ((volatile uint32_t *)REG_DPM0_WAKE_POL)                /* DPM0 Wakeup Polarity Register */
-#define pREG_DPM0_WAKE_STAT              ((volatile uint32_t *)REG_DPM0_WAKE_STAT)               /* DPM0 Wakeup Status Register */
-#define pREG_DPM0_HIB_DIS                ((volatile uint32_t *)REG_DPM0_HIB_DIS)                 /* DPM0 Hibernate Disable Register */
-#define pREG_DPM0_PGCNTR                 ((volatile uint32_t *)REG_DPM0_PGCNTR)                  /* DPM0 Power Good Counter Register */
-#define pREG_DPM0_RESTORE0               ((volatile uint32_t *)REG_DPM0_RESTORE0)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE1               ((volatile uint32_t *)REG_DPM0_RESTORE1)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE2               ((volatile uint32_t *)REG_DPM0_RESTORE2)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE3               ((volatile uint32_t *)REG_DPM0_RESTORE3)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE4               ((volatile uint32_t *)REG_DPM0_RESTORE4)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE5               ((volatile uint32_t *)REG_DPM0_RESTORE5)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE6               ((volatile uint32_t *)REG_DPM0_RESTORE6)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE7               ((volatile uint32_t *)REG_DPM0_RESTORE7)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE8               ((volatile uint32_t *)REG_DPM0_RESTORE8)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE9               ((volatile uint32_t *)REG_DPM0_RESTORE9)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE10              ((volatile uint32_t *)REG_DPM0_RESTORE10)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE11              ((volatile uint32_t *)REG_DPM0_RESTORE11)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE12              ((volatile uint32_t *)REG_DPM0_RESTORE12)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE13              ((volatile uint32_t *)REG_DPM0_RESTORE13)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE14              ((volatile uint32_t *)REG_DPM0_RESTORE14)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE15              ((volatile uint32_t *)REG_DPM0_RESTORE15)               /* DPM0 Restore n Register */
-
-
-/* =========================================================================
-       EFS0
-   ========================================================================= */
-#define pREG_EFS0_CTL                    ((volatile uint32_t *)REG_EFS0_CTL)                     /* EFS0 Control Register */
-#define pREG_EFS0_DAT0                   ((volatile uint32_t *)REG_EFS0_DAT0)                    /* EFS0 Data Register 0 */
-#define pREG_EFS0_DAT1                   ((volatile uint32_t *)REG_EFS0_DAT1)                    /* EFS0 Data Register 1 */
-#define pREG_EFS0_DAT2                   ((volatile uint32_t *)REG_EFS0_DAT2)                    /* EFS0 Data Register 2 */
-#define pREG_EFS0_DAT3                   ((volatile uint32_t *)REG_EFS0_DAT3)                    /* EFS0 Data Register 3 */
-#define pREG_EFS0_DAT4                   ((volatile uint32_t *)REG_EFS0_DAT4)                    /* EFS0 Data Register 4 */
-#define pREG_EFS0_DAT5                   ((volatile uint32_t *)REG_EFS0_DAT5)                    /* EFS0 Data Register 5 */
-#define pREG_EFS0_DAT6                   ((volatile uint32_t *)REG_EFS0_DAT6)                    /* EFS0 Data Register 6 */
-#define pREG_EFS0_DAT7                   ((volatile uint32_t *)REG_EFS0_DAT7)                    /* EFS0 Data Register 7 */
-
-
-/* =========================================================================
-       USB0
-   ========================================================================= */
-#define pREG_USB0_FADDR                  ((volatile  uint8_t *)REG_USB0_FADDR)                   /* USB0 Function Address Register */
-#define pREG_USB0_POWER                  ((volatile  uint8_t *)REG_USB0_POWER)                   /* USB0 Power and Device Control Register */
-#define pREG_USB0_INTRTX                 ((volatile uint16_t *)REG_USB0_INTRTX)                  /* USB0 Transmit Interrupt Register */
-#define pREG_USB0_INTRRX                 ((volatile uint16_t *)REG_USB0_INTRRX)                  /* USB0 Receive Interrupt Register */
-#define pREG_USB0_INTRTXE                ((volatile uint16_t *)REG_USB0_INTRTXE)                 /* USB0 Transmit Interrupt Enable Register */
-#define pREG_USB0_INTRRXE                ((volatile uint16_t *)REG_USB0_INTRRXE)                 /* USB0 Receive Interrupt Enable Register */
-#define pREG_USB0_IRQ                    ((volatile  uint8_t *)REG_USB0_IRQ)                     /* USB0 Common Interrupts Register */
-#define pREG_USB0_IEN                    ((volatile  uint8_t *)REG_USB0_IEN)                     /* USB0 Common Interrupts Enable Register */
-#define pREG_USB0_FRAME                  ((volatile uint16_t *)REG_USB0_FRAME)                   /* USB0 Frame Number Register */
-#define pREG_USB0_INDEX                  ((volatile  uint8_t *)REG_USB0_INDEX)                   /* USB0 Index Register */
-#define pREG_USB0_TESTMODE               ((volatile  uint8_t *)REG_USB0_TESTMODE)                /* USB0 Testmode Register */
-#define pREG_USB0_EPI_TXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_TXMAXP0)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EPI_TXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_P0)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EPI_TXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_H0)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0I_CSR0_P            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_P)             /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CSR0_H            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_H)             /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_RXMAXP0)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EPI_RXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_H0)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_P0)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CNT0              ((volatile uint16_t *)REG_USB0_EP0I_CNT0)               /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EPI_RXCNT0             ((volatile uint16_t *)REG_USB0_EPI_RXCNT0)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EPI_TXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_TXTYPE0)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0I_TYPE0             ((volatile  uint8_t *)REG_USB0_EP0I_TYPE0)              /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EPI_TXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_TXINTERVAL0)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0I_NAKLIMIT0         ((volatile  uint8_t *)REG_USB0_EP0I_NAKLIMIT0)          /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EPI_RXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_RXTYPE0)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EPI_RXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_RXINTERVAL0)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0I_CFGDATA0          ((volatile  uint8_t *)REG_USB0_EP0I_CFGDATA0)           /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_FIFOB0                 ((volatile  uint8_t *)REG_USB0_FIFOB0)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB1                 ((volatile  uint8_t *)REG_USB0_FIFOB1)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB2                 ((volatile  uint8_t *)REG_USB0_FIFOB2)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB3                 ((volatile  uint8_t *)REG_USB0_FIFOB3)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB4                 ((volatile  uint8_t *)REG_USB0_FIFOB4)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB5                 ((volatile  uint8_t *)REG_USB0_FIFOB5)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB6                 ((volatile  uint8_t *)REG_USB0_FIFOB6)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB7                 ((volatile  uint8_t *)REG_USB0_FIFOB7)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB8                 ((volatile  uint8_t *)REG_USB0_FIFOB8)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB9                 ((volatile  uint8_t *)REG_USB0_FIFOB9)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB10                ((volatile  uint8_t *)REG_USB0_FIFOB10)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB11                ((volatile  uint8_t *)REG_USB0_FIFOB11)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOH0                 ((volatile uint16_t *)REG_USB0_FIFOH0)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH1                 ((volatile uint16_t *)REG_USB0_FIFOH1)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH2                 ((volatile uint16_t *)REG_USB0_FIFOH2)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH3                 ((volatile uint16_t *)REG_USB0_FIFOH3)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH4                 ((volatile uint16_t *)REG_USB0_FIFOH4)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH5                 ((volatile uint16_t *)REG_USB0_FIFOH5)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH6                 ((volatile uint16_t *)REG_USB0_FIFOH6)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH7                 ((volatile uint16_t *)REG_USB0_FIFOH7)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH8                 ((volatile uint16_t *)REG_USB0_FIFOH8)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH9                 ((volatile uint16_t *)REG_USB0_FIFOH9)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH10                ((volatile uint16_t *)REG_USB0_FIFOH10)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH11                ((volatile uint16_t *)REG_USB0_FIFOH11)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFO0                  ((volatile uint32_t *)REG_USB0_FIFO0)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO1                  ((volatile uint32_t *)REG_USB0_FIFO1)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO2                  ((volatile uint32_t *)REG_USB0_FIFO2)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO3                  ((volatile uint32_t *)REG_USB0_FIFO3)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO4                  ((volatile uint32_t *)REG_USB0_FIFO4)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO5                  ((volatile uint32_t *)REG_USB0_FIFO5)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO6                  ((volatile uint32_t *)REG_USB0_FIFO6)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO7                  ((volatile uint32_t *)REG_USB0_FIFO7)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO8                  ((volatile uint32_t *)REG_USB0_FIFO8)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO9                  ((volatile uint32_t *)REG_USB0_FIFO9)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO10                 ((volatile uint32_t *)REG_USB0_FIFO10)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO11                 ((volatile uint32_t *)REG_USB0_FIFO11)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_DEV_CTL                ((volatile  uint8_t *)REG_USB0_DEV_CTL)                 /* USB0 Device Control Register */
-#define pREG_USB0_TXFIFOSZ               ((volatile  uint8_t *)REG_USB0_TXFIFOSZ)                /* USB0 Transmit FIFO Size Register */
-#define pREG_USB0_RXFIFOSZ               ((volatile  uint8_t *)REG_USB0_RXFIFOSZ)                /* USB0 Receive FIFO Size Register */
-#define pREG_USB0_TXFIFOADDR             ((volatile uint16_t *)REG_USB0_TXFIFOADDR)              /* USB0 Transmit FIFO Address Register */
-#define pREG_USB0_RXFIFOADDR             ((volatile uint16_t *)REG_USB0_RXFIFOADDR)              /* USB0 Receive FIFO Address Register */
-#define pREG_USB0_EPINFO                 ((volatile  uint8_t *)REG_USB0_EPINFO)                  /* USB0 Endpoint Information Register */
-#define pREG_USB0_RAMINFO                ((volatile  uint8_t *)REG_USB0_RAMINFO)                 /* USB0 RAM Information Register */
-#define pREG_USB0_LINKINFO               ((volatile  uint8_t *)REG_USB0_LINKINFO)                /* USB0 Link Information Register */
-#define pREG_USB0_VPLEN                  ((volatile  uint8_t *)REG_USB0_VPLEN)                   /* USB0 VBUS Pulse Length Register */
-#define pREG_USB0_HS_EOF1                ((volatile  uint8_t *)REG_USB0_HS_EOF1)                 /* USB0 High-Speed EOF 1 Register */
-#define pREG_USB0_FS_EOF1                ((volatile  uint8_t *)REG_USB0_FS_EOF1)                 /* USB0 Full-Speed EOF 1 Register */
-#define pREG_USB0_LS_EOF1                ((volatile  uint8_t *)REG_USB0_LS_EOF1)                 /* USB0 Low-Speed EOF 1 Register */
-#define pREG_USB0_SOFT_RST               ((volatile  uint8_t *)REG_USB0_SOFT_RST)                /* USB0 Software Reset Register */
-#define pREG_USB0_MP0_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP1_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP2_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP3_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP4_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP5_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP6_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP7_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP8_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP9_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP10_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP11_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP0_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP1_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP2_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP3_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP4_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP5_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP6_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP7_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP8_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP9_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP10_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP11_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP0_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP1_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP2_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP3_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP4_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP5_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP6_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP7_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP8_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP9_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP10_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP11_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP0_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP1_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP2_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP3_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP4_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP5_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP6_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP7_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP8_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP9_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP10_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP11_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP0_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP1_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP2_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP3_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP4_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP5_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP6_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP7_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP8_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP9_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP10_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP11_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP0_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP1_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP2_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP3_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP4_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP5_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP6_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP7_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP8_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP9_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP10_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP11_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_EP0_TXMAXP             ((volatile uint16_t *)REG_USB0_EP0_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP1_TXMAXP             ((volatile uint16_t *)REG_USB0_EP1_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP2_TXMAXP             ((volatile uint16_t *)REG_USB0_EP2_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP3_TXMAXP             ((volatile uint16_t *)REG_USB0_EP3_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP4_TXMAXP             ((volatile uint16_t *)REG_USB0_EP4_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP5_TXMAXP             ((volatile uint16_t *)REG_USB0_EP5_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP6_TXMAXP             ((volatile uint16_t *)REG_USB0_EP6_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP7_TXMAXP             ((volatile uint16_t *)REG_USB0_EP7_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP8_TXMAXP             ((volatile uint16_t *)REG_USB0_EP8_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP9_TXMAXP             ((volatile uint16_t *)REG_USB0_EP9_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP10_TXMAXP            ((volatile uint16_t *)REG_USB0_EP10_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP11_TXMAXP            ((volatile uint16_t *)REG_USB0_EP11_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP0_CSR0_H             ((volatile uint16_t *)REG_USB0_EP0_CSR0_H)              /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_CSR0_P             ((volatile uint16_t *)REG_USB0_EP0_CSR0_P)              /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_RXMAXP             ((volatile uint16_t *)REG_USB0_EP0_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP1_RXMAXP             ((volatile uint16_t *)REG_USB0_EP1_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP2_RXMAXP             ((volatile uint16_t *)REG_USB0_EP2_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP3_RXMAXP             ((volatile uint16_t *)REG_USB0_EP3_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP4_RXMAXP             ((volatile uint16_t *)REG_USB0_EP4_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP5_RXMAXP             ((volatile uint16_t *)REG_USB0_EP5_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP6_RXMAXP             ((volatile uint16_t *)REG_USB0_EP6_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP7_RXMAXP             ((volatile uint16_t *)REG_USB0_EP7_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP8_RXMAXP             ((volatile uint16_t *)REG_USB0_EP8_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP9_RXMAXP             ((volatile uint16_t *)REG_USB0_EP9_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP10_RXMAXP            ((volatile uint16_t *)REG_USB0_EP10_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP11_RXMAXP            ((volatile uint16_t *)REG_USB0_EP11_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP0_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_CNT0               ((volatile uint16_t *)REG_USB0_EP0_CNT0)                /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EP0_RXCNT              ((volatile uint16_t *)REG_USB0_EP0_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP1_RXCNT              ((volatile uint16_t *)REG_USB0_EP1_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP2_RXCNT              ((volatile uint16_t *)REG_USB0_EP2_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP3_RXCNT              ((volatile uint16_t *)REG_USB0_EP3_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP4_RXCNT              ((volatile uint16_t *)REG_USB0_EP4_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP5_RXCNT              ((volatile uint16_t *)REG_USB0_EP5_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP6_RXCNT              ((volatile uint16_t *)REG_USB0_EP6_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP7_RXCNT              ((volatile uint16_t *)REG_USB0_EP7_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP8_RXCNT              ((volatile uint16_t *)REG_USB0_EP8_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP9_RXCNT              ((volatile uint16_t *)REG_USB0_EP9_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP10_RXCNT             ((volatile uint16_t *)REG_USB0_EP10_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP11_RXCNT             ((volatile uint16_t *)REG_USB0_EP11_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP0_TYPE0              ((volatile  uint8_t *)REG_USB0_EP0_TYPE0)               /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EP0_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP1_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP2_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP3_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP4_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP5_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP6_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP7_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP8_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP9_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP10_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP11_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0_NAKLIMIT0          ((volatile  uint8_t *)REG_USB0_EP0_NAKLIMIT0)           /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EP0_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP1_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP2_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP3_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP4_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP5_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP6_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP7_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP8_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP9_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP10_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP11_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP1_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP2_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP3_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP4_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP5_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP6_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP7_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP8_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP9_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP10_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP11_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP0_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP1_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP2_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP3_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP4_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP5_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP6_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP7_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP8_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP9_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP10_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP11_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0_CFGDATA0           ((volatile  uint8_t *)REG_USB0_EP0_CFGDATA0)            /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_DMA_IRQ                ((volatile  uint8_t *)REG_USB0_DMA_IRQ)                 /* USB0 DMA Interrupt Register */
-#define pREG_USB0_DMA0_CTL               ((volatile uint16_t *)REG_USB0_DMA0_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA1_CTL               ((volatile uint16_t *)REG_USB0_DMA1_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA2_CTL               ((volatile uint16_t *)REG_USB0_DMA2_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA3_CTL               ((volatile uint16_t *)REG_USB0_DMA3_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA4_CTL               ((volatile uint16_t *)REG_USB0_DMA4_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA5_CTL               ((volatile uint16_t *)REG_USB0_DMA5_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA6_CTL               ((volatile uint16_t *)REG_USB0_DMA6_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA7_CTL               ((volatile uint16_t *)REG_USB0_DMA7_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA0_ADDR              ((void * volatile *)REG_USB0_DMA0_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA1_ADDR              ((void * volatile *)REG_USB0_DMA1_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA2_ADDR              ((void * volatile *)REG_USB0_DMA2_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA3_ADDR              ((void * volatile *)REG_USB0_DMA3_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA4_ADDR              ((void * volatile *)REG_USB0_DMA4_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA5_ADDR              ((void * volatile *)REG_USB0_DMA5_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA6_ADDR              ((void * volatile *)REG_USB0_DMA6_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA7_ADDR              ((void * volatile *)REG_USB0_DMA7_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA0_CNT               ((volatile uint32_t *)REG_USB0_DMA0_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA1_CNT               ((volatile uint32_t *)REG_USB0_DMA1_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA2_CNT               ((volatile uint32_t *)REG_USB0_DMA2_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA3_CNT               ((volatile uint32_t *)REG_USB0_DMA3_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA4_CNT               ((volatile uint32_t *)REG_USB0_DMA4_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA5_CNT               ((volatile uint32_t *)REG_USB0_DMA5_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA6_CNT               ((volatile uint32_t *)REG_USB0_DMA6_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA7_CNT               ((volatile uint32_t *)REG_USB0_DMA7_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_RQPKTCNT0              ((volatile uint16_t *)REG_USB0_RQPKTCNT0)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT1              ((volatile uint16_t *)REG_USB0_RQPKTCNT1)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT2              ((volatile uint16_t *)REG_USB0_RQPKTCNT2)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT3              ((volatile uint16_t *)REG_USB0_RQPKTCNT3)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT4              ((volatile uint16_t *)REG_USB0_RQPKTCNT4)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT5              ((volatile uint16_t *)REG_USB0_RQPKTCNT5)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT6              ((volatile uint16_t *)REG_USB0_RQPKTCNT6)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT7              ((volatile uint16_t *)REG_USB0_RQPKTCNT7)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT8              ((volatile uint16_t *)REG_USB0_RQPKTCNT8)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT9              ((volatile uint16_t *)REG_USB0_RQPKTCNT9)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT10             ((volatile uint16_t *)REG_USB0_RQPKTCNT10)              /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_CT_UCH                 ((volatile uint16_t *)REG_USB0_CT_UCH)                  /* USB0 Chirp Timeout Register */
-#define pREG_USB0_CT_HHSRTN              ((volatile uint16_t *)REG_USB0_CT_HHSRTN)               /* USB0 Host High Speed Return to Normal Register */
-#define pREG_USB0_CT_HSBT                ((volatile uint16_t *)REG_USB0_CT_HSBT)                 /* USB0 High Speed Timeout Register */
-#define pREG_USB0_LPM_ATTR               ((volatile uint16_t *)REG_USB0_LPM_ATTR)                /* USB0 LPM Attribute Register */
-#define pREG_USB0_LPM_CTL                ((volatile  uint8_t *)REG_USB0_LPM_CTL)                 /* USB0 LPM Control Register */
-#define pREG_USB0_LPM_IEN                ((volatile  uint8_t *)REG_USB0_LPM_IEN)                 /* USB0 LPM Interrupt Enable Register */
-#define pREG_USB0_LPM_IRQ                ((volatile  uint8_t *)REG_USB0_LPM_IRQ)                 /* USB0 LPM Interrupt Status Register */
-#define pREG_USB0_LPM_FADDR              ((volatile  uint8_t *)REG_USB0_LPM_FADDR)               /* USB0 LPM Function Address Register */
-#define pREG_USB0_VBUS_CTL               ((volatile  uint8_t *)REG_USB0_VBUS_CTL)                /* USB0 VBUS Control Register */
-#define pREG_USB0_BAT_CHG                ((volatile  uint8_t *)REG_USB0_BAT_CHG)                 /* USB0 Battery Charging Control Register */
-#define pREG_USB0_PHY_CTL                ((volatile  uint8_t *)REG_USB0_PHY_CTL)                 /* USB0 PHY Control Register */
-#define pREG_USB0_PLL_OSC                ((volatile uint16_t *)REG_USB0_PLL_OSC)                 /* USB0 PLL and Oscillator Control Register */
-
-
-/* =========================================================================
-       L1DM0
-   ========================================================================= */
-#define pSRAM_BASE_ADDRESS               ((void * volatile *)SRAM_BASE_ADDRESS)                  /* SRAM Base Address */
-#define pDMEM_CONTROL                    ((volatile uint32_t *)DMEM_CONTROL)                     /* Data memory control */
-#define pDCPLB_STATUS                    ((volatile uint32_t *)DCPLB_STATUS)                     /* Data Cacheability Protection Lookaside Buffer Status */
-#define pDCPLB_FAULT_ADDR                ((void * volatile *)DCPLB_FAULT_ADDR)                   /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define pDCPLB_ADDR0                     ((void * volatile *)DCPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR1                     ((void * volatile *)DCPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR2                     ((void * volatile *)DCPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR3                     ((void * volatile *)DCPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR4                     ((void * volatile *)DCPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR5                     ((void * volatile *)DCPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR6                     ((void * volatile *)DCPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR7                     ((void * volatile *)DCPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR8                     ((void * volatile *)DCPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR9                     ((void * volatile *)DCPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR10                    ((void * volatile *)DCPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR11                    ((void * volatile *)DCPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR12                    ((void * volatile *)DCPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR13                    ((void * volatile *)DCPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR14                    ((void * volatile *)DCPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR15                    ((void * volatile *)DCPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_DATA0                     ((volatile uint32_t *)DCPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA1                     ((volatile uint32_t *)DCPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA2                     ((volatile uint32_t *)DCPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA3                     ((volatile uint32_t *)DCPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA4                     ((volatile uint32_t *)DCPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA5                     ((volatile uint32_t *)DCPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA6                     ((volatile uint32_t *)DCPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA7                     ((volatile uint32_t *)DCPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA8                     ((volatile uint32_t *)DCPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA9                     ((volatile uint32_t *)DCPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA10                    ((volatile uint32_t *)DCPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA11                    ((volatile uint32_t *)DCPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA12                    ((volatile uint32_t *)DCPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA13                    ((volatile uint32_t *)DCPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA14                    ((volatile uint32_t *)DCPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA15                    ((volatile uint32_t *)DCPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDTEST_COMMAND                   ((volatile uint32_t *)DTEST_COMMAND)                    /* Data Test Command Register */
-#define pDTEST_DATA0                     ((volatile uint32_t *)DTEST_DATA0)                      /* Data Test Data Register */
-#define pDTEST_DATA1                     ((volatile uint32_t *)DTEST_DATA1)                      /* Data Test Data Register */
-#define pL1DBNKA_PELOC                   ((volatile uint32_t *)L1DBNKA_PELOC)                    /* Data Bank A Parity Error Location */
-#define pL1DBNKB_PELOC                   ((volatile uint32_t *)L1DBNKB_PELOC)                    /* Data Bank B Parity Error Location */
-
-
-/* =========================================================================
-       L1IM0
-   ========================================================================= */
-#define pIMEM_CONTROL                    ((volatile uint32_t *)IMEM_CONTROL)                     /* Instruction memory control */
-#define pICPLB_STATUS                    ((volatile uint32_t *)ICPLB_STATUS)                     /* Cacheability Protection Lookaside Buffer Status */
-#define pICPLB_FAULT_ADDR                ((void * volatile *)ICPLB_FAULT_ADDR)                   /* Cacheability Protection Lookaside Buffer Fault Address */
-#define pICPLB_ADDR0                     ((void * volatile *)ICPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR1                     ((void * volatile *)ICPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR2                     ((void * volatile *)ICPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR3                     ((void * volatile *)ICPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR4                     ((void * volatile *)ICPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR5                     ((void * volatile *)ICPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR6                     ((void * volatile *)ICPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR7                     ((void * volatile *)ICPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR8                     ((void * volatile *)ICPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR9                     ((void * volatile *)ICPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR10                    ((void * volatile *)ICPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR11                    ((void * volatile *)ICPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR12                    ((void * volatile *)ICPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR13                    ((void * volatile *)ICPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR14                    ((void * volatile *)ICPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR15                    ((void * volatile *)ICPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_DATA0                     ((volatile uint32_t *)ICPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA1                     ((volatile uint32_t *)ICPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA2                     ((volatile uint32_t *)ICPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA3                     ((volatile uint32_t *)ICPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA4                     ((volatile uint32_t *)ICPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA5                     ((volatile uint32_t *)ICPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA6                     ((volatile uint32_t *)ICPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA7                     ((volatile uint32_t *)ICPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA8                     ((volatile uint32_t *)ICPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA9                     ((volatile uint32_t *)ICPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA10                    ((volatile uint32_t *)ICPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA11                    ((volatile uint32_t *)ICPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA12                    ((volatile uint32_t *)ICPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA13                    ((volatile uint32_t *)ICPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA14                    ((volatile uint32_t *)ICPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA15                    ((volatile uint32_t *)ICPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pITEST_COMMAND                   ((volatile uint32_t *)ITEST_COMMAND)                    /* Instruction Test Command Register */
-#define pITEST_DATA0                     ((volatile uint32_t *)ITEST_DATA0)                      /* Instruction Test Data Register */
-#define pITEST_DATA1                     ((volatile uint32_t *)ITEST_DATA1)                      /* Instruction Test Data Register */
-#define pL1IBNKA_PELOC                   ((volatile uint32_t *)L1IBNKA_PELOC)                    /* Instruction Bank A Parity Error Location */
-#define pL1IBNKB_PELOC                   ((volatile uint32_t *)L1IBNKB_PELOC)                    /* Instruction Bank B Parity Error Location */
-#define pL1IBNKC_PELOC                   ((volatile uint32_t *)L1IBNKC_PELOC)                    /* Instruction Bank C Parity Error Location */
-
-
-/* =========================================================================
-       ICU0
-   ========================================================================= */
-#define pEVT0                            ((void * volatile *)EVT0)                               /* Event Vector */
-#define pEVT1                            ((void * volatile *)EVT1)                               /* Event Vector */
-#define pEVT2                            ((void * volatile *)EVT2)                               /* Event Vector */
-#define pEVT3                            ((void * volatile *)EVT3)                               /* Event Vector */
-#define pEVT4                            ((void * volatile *)EVT4)                               /* Event Vector */
-#define pEVT5                            ((void * volatile *)EVT5)                               /* Event Vector */
-#define pEVT6                            ((void * volatile *)EVT6)                               /* Event Vector */
-#define pEVT7                            ((void * volatile *)EVT7)                               /* Event Vector */
-#define pEVT8                            ((void * volatile *)EVT8)                               /* Event Vector */
-#define pEVT9                            ((void * volatile *)EVT9)                               /* Event Vector */
-#define pEVT10                           ((void * volatile *)EVT10)                              /* Event Vector */
-#define pEVT11                           ((void * volatile *)EVT11)                              /* Event Vector */
-#define pEVT12                           ((void * volatile *)EVT12)                              /* Event Vector */
-#define pEVT13                           ((void * volatile *)EVT13)                              /* Event Vector */
-#define pEVT14                           ((void * volatile *)EVT14)                              /* Event Vector */
-#define pEVT15                           ((void * volatile *)EVT15)                              /* Event Vector */
-#define pIMASK                           ((volatile uint32_t *)IMASK)                            /* Interrupt Mask Register */
-#define pIPEND                           ((volatile uint32_t *)IPEND)                            /* Interrupts Pending Register */
-#define pILAT                            ((volatile uint32_t *)ILAT)                             /* Interrupt Latch Register */
-#define pIPRIO                           ((volatile uint32_t *)IPRIO)                            /* Interrupt Priority Register */
-#define pCEC_SID                         ((volatile uint32_t *)CEC_SID)                          /* Core System Interrupt ID */
-
-
-/* =========================================================================
-       TMR0
-   ========================================================================= */
-#define pTCNTL                           ((volatile uint32_t *)TCNTL)                            /* Timer Control Register */
-#define pTPERIOD                         ((volatile uint32_t *)TPERIOD)                          /* Timer Period Register */
-#define pTSCALE                          ((volatile uint32_t *)TSCALE)                           /* Timer Scale Register */
-#define pTCOUNT                          ((volatile uint32_t *)TCOUNT)                           /* Timer Count Register */
-
-
-/* =========================================================================
-       DBG0
-   ========================================================================= */
-#define pDSPID                           ((volatile uint32_t *)DSPID)                            /* DSP Identification Register */
-
-
-/* =========================================================================
-       TB0
-   ========================================================================= */
-#define pTBUFCTL                         ((volatile uint32_t *)TBUFCTL)                          /* Trace Buffer Control Register */
-#define pTBUFSTAT                        ((volatile uint32_t *)TBUFSTAT)                         /* Trace Buffer Status Register */
-#define pTBUF                            ((void * volatile *)TBUF)                               /* Trace Buffer */
-
-
-/* =========================================================================
-       WP0
-   ========================================================================= */
-#define pWPIACTL                         ((volatile uint32_t *)WPIACTL)                          /* Watchpoint Instruction Address Control Register 01 */
-#define pWPIA0                           ((void * volatile *)WPIA0)                              /* Watchpoint Instruction Address Register */
-#define pWPIA1                           ((void * volatile *)WPIA1)                              /* Watchpoint Instruction Address Register */
-#define pWPIA2                           ((void * volatile *)WPIA2)                              /* Watchpoint Instruction Address Register */
-#define pWPIA3                           ((void * volatile *)WPIA3)                              /* Watchpoint Instruction Address Register */
-#define pWPIA4                           ((void * volatile *)WPIA4)                              /* Watchpoint Instruction Address Register */
-#define pWPIA5                           ((void * volatile *)WPIA5)                              /* Watchpoint Instruction Address Register */
-#define pWPIACNT0                        ((volatile uint32_t *)WPIACNT0)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT1                        ((volatile uint32_t *)WPIACNT1)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT2                        ((volatile uint32_t *)WPIACNT2)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT3                        ((volatile uint32_t *)WPIACNT3)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT4                        ((volatile uint32_t *)WPIACNT4)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT5                        ((volatile uint32_t *)WPIACNT5)                         /* Watchpoint Instruction Address Count Register */
-#define pWPDACTL                         ((volatile uint32_t *)WPDACTL)                          /* Watchpoint Data Address Control Register */
-#define pWPDA0                           ((void * volatile *)WPDA0)                              /* Watchpoint Data Address Register */
-#define pWPDA1                           ((void * volatile *)WPDA1)                              /* Watchpoint Data Address Register */
-#define pWPDACNT0                        ((volatile uint32_t *)WPDACNT0)                         /* Watchpoint Data Address Count Value Register */
-#define pWPDACNT1                        ((volatile uint32_t *)WPDACNT1)                         /* Watchpoint Data Address Count Value Register */
-#define pWPSTAT                          ((volatile uint32_t *)WPSTAT)                           /* Watchpoint Status Register */
-
-
-/* =========================================================================
-       PF0
-   ========================================================================= */
-#define pPFCTL                           ((volatile uint32_t *)PFCTL)                            /* Performance Monitor Control Register */
-#define pPFCNTR0                         ((volatile uint32_t *)PFCNTR0)                          /* Performance Monitor Counter 0 */
-#define pPFCNTR1                         ((volatile uint32_t *)PFCNTR1)                          /* Performance Monitor Counter 1 */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif	/* end ifndef _CDEF_BF607_H */
diff --git a/libgloss/bfin/include/cdefBF608.h b/libgloss/bfin/include/cdefBF608.h
deleted file mode 100644
index c7d843717..000000000
--- a/libgloss/bfin/include/cdefBF608.h
+++ /dev/null
@@ -1,4419 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* =========================================================================
-
-     Project      :   ADSP-BF608
-     File         :   cdefBF608.h
-     Description  :   C register and bitfield definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ========================================================================= */
-#ifndef _CDEF_BF608_H
-#define _CDEF_BF608_H
-
-#include <stdint.h>
-#include <defBF608.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_7:"ADI header will re-use identifiers")
-#pragma diag(suppress:misra_rule_6_3:"ADI header allows use of basic types")
-#endif /* _MISRA_RULES */
-
-
-
-
-/* =========================================================================
-       CNT0
-   ========================================================================= */
-#define pREG_CNT0_CFG                    ((volatile uint16_t *)REG_CNT0_CFG)                     /* CNT0 Configuration Register */
-#define pREG_CNT0_IMSK                   ((volatile uint16_t *)REG_CNT0_IMSK)                    /* CNT0 Interrupt Mask Register */
-#define pREG_CNT0_STAT                   ((volatile uint16_t *)REG_CNT0_STAT)                    /* CNT0 Status Register */
-#define pREG_CNT0_CMD                    ((volatile uint16_t *)REG_CNT0_CMD)                     /* CNT0 Command Register */
-#define pREG_CNT0_DEBNCE                 ((volatile uint16_t *)REG_CNT0_DEBNCE)                  /* CNT0 Debounce Register */
-#define pREG_CNT0_CNTR                   ((volatile uint32_t *)REG_CNT0_CNTR)                    /* CNT0 Counter Register */
-#define pREG_CNT0_MAX                    ((volatile uint32_t *)REG_CNT0_MAX)                     /* CNT0 Maximum Count Register */
-#define pREG_CNT0_MIN                    ((volatile uint32_t *)REG_CNT0_MIN)                     /* CNT0 Minimum Count Register */
-
-
-/* =========================================================================
-       RSI0
-   ========================================================================= */
-#define pREG_RSI0_CTL                    ((volatile uint16_t *)REG_RSI0_CTL)                     /* RSI0 Control Register */
-#define pREG_RSI0_ARG                    ((volatile uint32_t *)REG_RSI0_ARG)                     /* RSI0 Argument Register */
-#define pREG_RSI0_CMD                    ((volatile uint16_t *)REG_RSI0_CMD)                     /* RSI0 Command Register */
-#define pREG_RSI0_RESP_CMD               ((volatile uint16_t *)REG_RSI0_RESP_CMD)                /* RSI0 Response Command Register */
-#define pREG_RSI0_RESP0                  ((volatile uint32_t *)REG_RSI0_RESP0)                   /* RSI0 Response 0 Register */
-#define pREG_RSI0_RESP1                  ((volatile uint32_t *)REG_RSI0_RESP1)                   /* RSI0 Response 1 Register */
-#define pREG_RSI0_RESP2                  ((volatile uint32_t *)REG_RSI0_RESP2)                   /* RSI0 Response 2 Register */
-#define pREG_RSI0_RESP3                  ((volatile uint32_t *)REG_RSI0_RESP3)                   /* RSI0 Response 3 Register */
-#define pREG_RSI0_DATA_TMR               ((volatile uint32_t *)REG_RSI0_DATA_TMR)                /* RSI0 Data Timer Register */
-#define pREG_RSI0_DATA_LEN               ((volatile uint16_t *)REG_RSI0_DATA_LEN)                /* RSI0 Data Length Register */
-#define pREG_RSI0_DATA_CTL               ((volatile uint16_t *)REG_RSI0_DATA_CTL)                /* RSI0 Data Control Register */
-#define pREG_RSI0_DATA_CNT               ((volatile uint16_t *)REG_RSI0_DATA_CNT)                /* RSI0 Data Count Register */
-#define pREG_RSI0_XFRSTAT                ((volatile uint32_t *)REG_RSI0_XFRSTAT)                 /* RSI0 Status Register */
-#define pREG_RSI0_XFRSTAT_CLR            ((volatile uint16_t *)REG_RSI0_XFRSTAT_CLR)             /* RSI0 Status Clear Register */
-#define pREG_RSI0_XFR_IMSK0              ((volatile uint32_t *)REG_RSI0_XFR_IMSK0)               /* RSI0 Interrupt 0 Mask Register */
-#define pREG_RSI0_XFR_IMSK1              ((volatile uint32_t *)REG_RSI0_XFR_IMSK1)               /* RSI0 Interrupt 1 Mask Register */
-#define pREG_RSI0_FIFO_CNT               ((volatile uint16_t *)REG_RSI0_FIFO_CNT)                /* RSI0 FIFO Counter Register */
-#define pREG_RSI0_CEATA                  ((volatile uint32_t *)REG_RSI0_CEATA)                   /* RSI0 This register contains bit to dis CCS gen */
-#define pREG_RSI0_BOOT_TCNTR             ((volatile uint16_t *)REG_RSI0_BOOT_TCNTR)              /* RSI0 Boot Timing Counter Register */
-#define pREG_RSI0_BACK_TOUT              ((volatile uint32_t *)REG_RSI0_BACK_TOUT)               /* RSI0 Boot Acknowledge Timeout Register */
-#define pREG_RSI0_SLP_WKUP_TOUT          ((volatile uint32_t *)REG_RSI0_SLP_WKUP_TOUT)           /* RSI0 Sleep Wakeup Timeout Register */
-#define pREG_RSI0_BLKSZ                  ((volatile uint16_t *)REG_RSI0_BLKSZ)                   /* RSI0 Block Size Register */
-#define pREG_RSI0_FIFO                   ((volatile uint32_t *)REG_RSI0_FIFO)                    /* RSI0 Data FIFO Register */
-#define pREG_RSI0_STAT0                  ((volatile uint32_t *)REG_RSI0_STAT0)                   /* RSI0 Exception Status Register */
-#define pREG_RSI0_IMSK0                  ((volatile uint32_t *)REG_RSI0_IMSK0)                   /* RSI0 Exception Mask Register */
-#define pREG_RSI0_CFG                    ((volatile uint16_t *)REG_RSI0_CFG)                     /* RSI0 Configuration Register */
-#define pREG_RSI0_RD_WAIT                ((volatile uint16_t *)REG_RSI0_RD_WAIT)                 /* RSI0 Read Wait Enable Register */
-#define pREG_RSI0_PID0                   ((volatile uint32_t *)REG_RSI0_PID0)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID1                   ((volatile uint32_t *)REG_RSI0_PID1)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID2                   ((volatile uint32_t *)REG_RSI0_PID2)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID3                   ((volatile uint32_t *)REG_RSI0_PID3)                    /* RSI0 Peripheral Identification Register */
-
-
-/* =========================================================================
-       CAN0
-   ========================================================================= */
-#define pREG_CAN0_MC1                    ((volatile uint16_t *)REG_CAN0_MC1)                     /* CAN0 Mailbox Configuration 1 Register */
-#define pREG_CAN0_MD1                    ((volatile uint16_t *)REG_CAN0_MD1)                     /* CAN0 Mailbox Direction 1 Register */
-#define pREG_CAN0_TRS1                   ((volatile uint16_t *)REG_CAN0_TRS1)                    /* CAN0 Transmission Request Set 1 Register */
-#define pREG_CAN0_TRR1                   ((volatile uint16_t *)REG_CAN0_TRR1)                    /* CAN0 Transmission Request Reset 1 Register */
-#define pREG_CAN0_TA1                    ((volatile uint16_t *)REG_CAN0_TA1)                     /* CAN0 Transmission Acknowledge 1 Register */
-#define pREG_CAN0_AA1                    ((volatile uint16_t *)REG_CAN0_AA1)                     /* CAN0 Abort Acknowledge 1 Register */
-#define pREG_CAN0_RMP1                   ((volatile uint16_t *)REG_CAN0_RMP1)                    /* CAN0 Receive Message Pending 1 Register */
-#define pREG_CAN0_RML1                   ((volatile uint16_t *)REG_CAN0_RML1)                    /* CAN0 Receive Message Lost 1 Register */
-#define pREG_CAN0_MBTIF1                 ((volatile uint16_t *)REG_CAN0_MBTIF1)                  /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define pREG_CAN0_MBRIF1                 ((volatile uint16_t *)REG_CAN0_MBRIF1)                  /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define pREG_CAN0_MBIM1                  ((volatile uint16_t *)REG_CAN0_MBIM1)                   /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define pREG_CAN0_RFH1                   ((volatile uint16_t *)REG_CAN0_RFH1)                    /* CAN0 Remote Frame Handling 1 Register */
-#define pREG_CAN0_OPSS1                  ((volatile uint16_t *)REG_CAN0_OPSS1)                   /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define pREG_CAN0_MC2                    ((volatile uint16_t *)REG_CAN0_MC2)                     /* CAN0 Mailbox Configuration 2 Register */
-#define pREG_CAN0_MD2                    ((volatile uint16_t *)REG_CAN0_MD2)                     /* CAN0 Mailbox Direction 2 Register */
-#define pREG_CAN0_TRS2                   ((volatile uint16_t *)REG_CAN0_TRS2)                    /* CAN0 Transmission Request Set 2 Register */
-#define pREG_CAN0_TRR2                   ((volatile uint16_t *)REG_CAN0_TRR2)                    /* CAN0 Transmission Request Reset 2 Register */
-#define pREG_CAN0_TA2                    ((volatile uint16_t *)REG_CAN0_TA2)                     /* CAN0 Transmission Acknowledge 2 Register */
-#define pREG_CAN0_AA2                    ((volatile uint16_t *)REG_CAN0_AA2)                     /* CAN0 Abort Acknowledge 2 Register */
-#define pREG_CAN0_RMP2                   ((volatile uint16_t *)REG_CAN0_RMP2)                    /* CAN0 Receive Message Pending 2 Register */
-#define pREG_CAN0_RML2                   ((volatile uint16_t *)REG_CAN0_RML2)                    /* CAN0 Receive Message Lost 2 Register */
-#define pREG_CAN0_MBTIF2                 ((volatile uint16_t *)REG_CAN0_MBTIF2)                  /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define pREG_CAN0_MBRIF2                 ((volatile uint16_t *)REG_CAN0_MBRIF2)                  /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define pREG_CAN0_MBIM2                  ((volatile uint16_t *)REG_CAN0_MBIM2)                   /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define pREG_CAN0_RFH2                   ((volatile uint16_t *)REG_CAN0_RFH2)                    /* CAN0 Remote Frame Handling 2 Register */
-#define pREG_CAN0_OPSS2                  ((volatile uint16_t *)REG_CAN0_OPSS2)                   /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define pREG_CAN0_CLK                    ((volatile uint16_t *)REG_CAN0_CLK)                     /* CAN0 Clock Register */
-#define pREG_CAN0_TIMING                 ((volatile uint16_t *)REG_CAN0_TIMING)                  /* CAN0 Timing Register */
-#define pREG_CAN0_DBG                    ((volatile uint16_t *)REG_CAN0_DBG)                     /* CAN0 Debug Register */
-#define pREG_CAN0_STAT                   ((volatile uint16_t *)REG_CAN0_STAT)                    /* CAN0 Status Register */
-#define pREG_CAN0_CEC                    ((volatile uint16_t *)REG_CAN0_CEC)                     /* CAN0 Error Counter Register */
-#define pREG_CAN0_GIS                    ((volatile uint16_t *)REG_CAN0_GIS)                     /* CAN0 Global CAN Interrupt Status Register */
-#define pREG_CAN0_GIM                    ((volatile uint16_t *)REG_CAN0_GIM)                     /* CAN0 Global CAN Interrupt Mask Register */
-#define pREG_CAN0_GIF                    ((volatile uint16_t *)REG_CAN0_GIF)                     /* CAN0 Global CAN Interrupt Flag Register */
-#define pREG_CAN0_CTL                    ((volatile uint16_t *)REG_CAN0_CTL)                     /* CAN0 CAN Master Control Register */
-#define pREG_CAN0_INT                    ((volatile uint16_t *)REG_CAN0_INT)                     /* CAN0 Interrupt Pending Register */
-#define pREG_CAN0_MBTD                   ((volatile uint16_t *)REG_CAN0_MBTD)                    /* CAN0 Temporary Mailbox Disable Register */
-#define pREG_CAN0_EWR                    ((volatile uint16_t *)REG_CAN0_EWR)                     /* CAN0 Error Counter Warning Level Register */
-#define pREG_CAN0_ESR                    ((volatile uint16_t *)REG_CAN0_ESR)                     /* CAN0 Error Status Register */
-#define pREG_CAN0_UCCNT                  ((volatile uint16_t *)REG_CAN0_UCCNT)                   /* CAN0 Universal Counter Register */
-#define pREG_CAN0_UCRC                   ((volatile uint16_t *)REG_CAN0_UCRC)                    /* CAN0 Universal Counter Reload/Capture Register */
-#define pREG_CAN0_UCCNF                  ((volatile uint16_t *)REG_CAN0_UCCNF)                   /* CAN0 Universal Counter Configuration Mode Register */
-#define pREG_CAN0_AM00L                  ((volatile uint16_t *)REG_CAN0_AM00L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM01L                  ((volatile uint16_t *)REG_CAN0_AM01L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM02L                  ((volatile uint16_t *)REG_CAN0_AM02L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM03L                  ((volatile uint16_t *)REG_CAN0_AM03L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM04L                  ((volatile uint16_t *)REG_CAN0_AM04L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM05L                  ((volatile uint16_t *)REG_CAN0_AM05L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM06L                  ((volatile uint16_t *)REG_CAN0_AM06L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM07L                  ((volatile uint16_t *)REG_CAN0_AM07L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM08L                  ((volatile uint16_t *)REG_CAN0_AM08L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM09L                  ((volatile uint16_t *)REG_CAN0_AM09L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM10L                  ((volatile uint16_t *)REG_CAN0_AM10L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM11L                  ((volatile uint16_t *)REG_CAN0_AM11L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM12L                  ((volatile uint16_t *)REG_CAN0_AM12L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM13L                  ((volatile uint16_t *)REG_CAN0_AM13L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM14L                  ((volatile uint16_t *)REG_CAN0_AM14L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM15L                  ((volatile uint16_t *)REG_CAN0_AM15L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM16L                  ((volatile uint16_t *)REG_CAN0_AM16L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM17L                  ((volatile uint16_t *)REG_CAN0_AM17L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM18L                  ((volatile uint16_t *)REG_CAN0_AM18L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM19L                  ((volatile uint16_t *)REG_CAN0_AM19L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM20L                  ((volatile uint16_t *)REG_CAN0_AM20L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM21L                  ((volatile uint16_t *)REG_CAN0_AM21L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM22L                  ((volatile uint16_t *)REG_CAN0_AM22L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM23L                  ((volatile uint16_t *)REG_CAN0_AM23L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM24L                  ((volatile uint16_t *)REG_CAN0_AM24L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM25L                  ((volatile uint16_t *)REG_CAN0_AM25L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM26L                  ((volatile uint16_t *)REG_CAN0_AM26L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM27L                  ((volatile uint16_t *)REG_CAN0_AM27L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM28L                  ((volatile uint16_t *)REG_CAN0_AM28L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM29L                  ((volatile uint16_t *)REG_CAN0_AM29L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM30L                  ((volatile uint16_t *)REG_CAN0_AM30L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM31L                  ((volatile uint16_t *)REG_CAN0_AM31L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM00H                  ((volatile uint16_t *)REG_CAN0_AM00H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM01H                  ((volatile uint16_t *)REG_CAN0_AM01H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM02H                  ((volatile uint16_t *)REG_CAN0_AM02H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM03H                  ((volatile uint16_t *)REG_CAN0_AM03H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM04H                  ((volatile uint16_t *)REG_CAN0_AM04H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM05H                  ((volatile uint16_t *)REG_CAN0_AM05H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM06H                  ((volatile uint16_t *)REG_CAN0_AM06H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM07H                  ((volatile uint16_t *)REG_CAN0_AM07H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM08H                  ((volatile uint16_t *)REG_CAN0_AM08H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM09H                  ((volatile uint16_t *)REG_CAN0_AM09H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM10H                  ((volatile uint16_t *)REG_CAN0_AM10H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM11H                  ((volatile uint16_t *)REG_CAN0_AM11H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM12H                  ((volatile uint16_t *)REG_CAN0_AM12H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM13H                  ((volatile uint16_t *)REG_CAN0_AM13H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM14H                  ((volatile uint16_t *)REG_CAN0_AM14H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM15H                  ((volatile uint16_t *)REG_CAN0_AM15H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM16H                  ((volatile uint16_t *)REG_CAN0_AM16H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM17H                  ((volatile uint16_t *)REG_CAN0_AM17H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM18H                  ((volatile uint16_t *)REG_CAN0_AM18H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM19H                  ((volatile uint16_t *)REG_CAN0_AM19H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM20H                  ((volatile uint16_t *)REG_CAN0_AM20H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM21H                  ((volatile uint16_t *)REG_CAN0_AM21H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM22H                  ((volatile uint16_t *)REG_CAN0_AM22H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM23H                  ((volatile uint16_t *)REG_CAN0_AM23H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM24H                  ((volatile uint16_t *)REG_CAN0_AM24H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM25H                  ((volatile uint16_t *)REG_CAN0_AM25H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM26H                  ((volatile uint16_t *)REG_CAN0_AM26H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM27H                  ((volatile uint16_t *)REG_CAN0_AM27H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM28H                  ((volatile uint16_t *)REG_CAN0_AM28H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM29H                  ((volatile uint16_t *)REG_CAN0_AM29H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM30H                  ((volatile uint16_t *)REG_CAN0_AM30H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM31H                  ((volatile uint16_t *)REG_CAN0_AM31H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_MB00_DATA0             ((volatile uint16_t *)REG_CAN0_MB00_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB01_DATA0             ((volatile uint16_t *)REG_CAN0_MB01_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB02_DATA0             ((volatile uint16_t *)REG_CAN0_MB02_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB03_DATA0             ((volatile uint16_t *)REG_CAN0_MB03_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB04_DATA0             ((volatile uint16_t *)REG_CAN0_MB04_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB05_DATA0             ((volatile uint16_t *)REG_CAN0_MB05_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB06_DATA0             ((volatile uint16_t *)REG_CAN0_MB06_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB07_DATA0             ((volatile uint16_t *)REG_CAN0_MB07_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB08_DATA0             ((volatile uint16_t *)REG_CAN0_MB08_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB09_DATA0             ((volatile uint16_t *)REG_CAN0_MB09_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB10_DATA0             ((volatile uint16_t *)REG_CAN0_MB10_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB11_DATA0             ((volatile uint16_t *)REG_CAN0_MB11_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB12_DATA0             ((volatile uint16_t *)REG_CAN0_MB12_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB13_DATA0             ((volatile uint16_t *)REG_CAN0_MB13_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB14_DATA0             ((volatile uint16_t *)REG_CAN0_MB14_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB15_DATA0             ((volatile uint16_t *)REG_CAN0_MB15_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB16_DATA0             ((volatile uint16_t *)REG_CAN0_MB16_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB17_DATA0             ((volatile uint16_t *)REG_CAN0_MB17_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB18_DATA0             ((volatile uint16_t *)REG_CAN0_MB18_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB19_DATA0             ((volatile uint16_t *)REG_CAN0_MB19_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB20_DATA0             ((volatile uint16_t *)REG_CAN0_MB20_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB21_DATA0             ((volatile uint16_t *)REG_CAN0_MB21_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB22_DATA0             ((volatile uint16_t *)REG_CAN0_MB22_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB23_DATA0             ((volatile uint16_t *)REG_CAN0_MB23_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB24_DATA0             ((volatile uint16_t *)REG_CAN0_MB24_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB25_DATA0             ((volatile uint16_t *)REG_CAN0_MB25_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB26_DATA0             ((volatile uint16_t *)REG_CAN0_MB26_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB27_DATA0             ((volatile uint16_t *)REG_CAN0_MB27_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB28_DATA0             ((volatile uint16_t *)REG_CAN0_MB28_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB29_DATA0             ((volatile uint16_t *)REG_CAN0_MB29_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB30_DATA0             ((volatile uint16_t *)REG_CAN0_MB30_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB31_DATA0             ((volatile uint16_t *)REG_CAN0_MB31_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB00_DATA1             ((volatile uint16_t *)REG_CAN0_MB00_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB01_DATA1             ((volatile uint16_t *)REG_CAN0_MB01_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB02_DATA1             ((volatile uint16_t *)REG_CAN0_MB02_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB03_DATA1             ((volatile uint16_t *)REG_CAN0_MB03_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB04_DATA1             ((volatile uint16_t *)REG_CAN0_MB04_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB05_DATA1             ((volatile uint16_t *)REG_CAN0_MB05_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB06_DATA1             ((volatile uint16_t *)REG_CAN0_MB06_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB07_DATA1             ((volatile uint16_t *)REG_CAN0_MB07_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB08_DATA1             ((volatile uint16_t *)REG_CAN0_MB08_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB09_DATA1             ((volatile uint16_t *)REG_CAN0_MB09_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB10_DATA1             ((volatile uint16_t *)REG_CAN0_MB10_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB11_DATA1             ((volatile uint16_t *)REG_CAN0_MB11_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB12_DATA1             ((volatile uint16_t *)REG_CAN0_MB12_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB13_DATA1             ((volatile uint16_t *)REG_CAN0_MB13_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB14_DATA1             ((volatile uint16_t *)REG_CAN0_MB14_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB15_DATA1             ((volatile uint16_t *)REG_CAN0_MB15_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB16_DATA1             ((volatile uint16_t *)REG_CAN0_MB16_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB17_DATA1             ((volatile uint16_t *)REG_CAN0_MB17_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB18_DATA1             ((volatile uint16_t *)REG_CAN0_MB18_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB19_DATA1             ((volatile uint16_t *)REG_CAN0_MB19_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB20_DATA1             ((volatile uint16_t *)REG_CAN0_MB20_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB21_DATA1             ((volatile uint16_t *)REG_CAN0_MB21_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB22_DATA1             ((volatile uint16_t *)REG_CAN0_MB22_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB23_DATA1             ((volatile uint16_t *)REG_CAN0_MB23_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB24_DATA1             ((volatile uint16_t *)REG_CAN0_MB24_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB25_DATA1             ((volatile uint16_t *)REG_CAN0_MB25_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB26_DATA1             ((volatile uint16_t *)REG_CAN0_MB26_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB27_DATA1             ((volatile uint16_t *)REG_CAN0_MB27_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB28_DATA1             ((volatile uint16_t *)REG_CAN0_MB28_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB29_DATA1             ((volatile uint16_t *)REG_CAN0_MB29_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB30_DATA1             ((volatile uint16_t *)REG_CAN0_MB30_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB31_DATA1             ((volatile uint16_t *)REG_CAN0_MB31_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB00_DATA2             ((volatile uint16_t *)REG_CAN0_MB00_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB01_DATA2             ((volatile uint16_t *)REG_CAN0_MB01_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB02_DATA2             ((volatile uint16_t *)REG_CAN0_MB02_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB03_DATA2             ((volatile uint16_t *)REG_CAN0_MB03_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB04_DATA2             ((volatile uint16_t *)REG_CAN0_MB04_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB05_DATA2             ((volatile uint16_t *)REG_CAN0_MB05_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB06_DATA2             ((volatile uint16_t *)REG_CAN0_MB06_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB07_DATA2             ((volatile uint16_t *)REG_CAN0_MB07_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB08_DATA2             ((volatile uint16_t *)REG_CAN0_MB08_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB09_DATA2             ((volatile uint16_t *)REG_CAN0_MB09_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB10_DATA2             ((volatile uint16_t *)REG_CAN0_MB10_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB11_DATA2             ((volatile uint16_t *)REG_CAN0_MB11_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB12_DATA2             ((volatile uint16_t *)REG_CAN0_MB12_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB13_DATA2             ((volatile uint16_t *)REG_CAN0_MB13_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB14_DATA2             ((volatile uint16_t *)REG_CAN0_MB14_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB15_DATA2             ((volatile uint16_t *)REG_CAN0_MB15_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB16_DATA2             ((volatile uint16_t *)REG_CAN0_MB16_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB17_DATA2             ((volatile uint16_t *)REG_CAN0_MB17_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB18_DATA2             ((volatile uint16_t *)REG_CAN0_MB18_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB19_DATA2             ((volatile uint16_t *)REG_CAN0_MB19_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB20_DATA2             ((volatile uint16_t *)REG_CAN0_MB20_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB21_DATA2             ((volatile uint16_t *)REG_CAN0_MB21_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB22_DATA2             ((volatile uint16_t *)REG_CAN0_MB22_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB23_DATA2             ((volatile uint16_t *)REG_CAN0_MB23_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB24_DATA2             ((volatile uint16_t *)REG_CAN0_MB24_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB25_DATA2             ((volatile uint16_t *)REG_CAN0_MB25_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB26_DATA2             ((volatile uint16_t *)REG_CAN0_MB26_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB27_DATA2             ((volatile uint16_t *)REG_CAN0_MB27_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB28_DATA2             ((volatile uint16_t *)REG_CAN0_MB28_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB29_DATA2             ((volatile uint16_t *)REG_CAN0_MB29_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB30_DATA2             ((volatile uint16_t *)REG_CAN0_MB30_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB31_DATA2             ((volatile uint16_t *)REG_CAN0_MB31_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB00_DATA3             ((volatile uint16_t *)REG_CAN0_MB00_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB01_DATA3             ((volatile uint16_t *)REG_CAN0_MB01_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB02_DATA3             ((volatile uint16_t *)REG_CAN0_MB02_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB03_DATA3             ((volatile uint16_t *)REG_CAN0_MB03_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB04_DATA3             ((volatile uint16_t *)REG_CAN0_MB04_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB05_DATA3             ((volatile uint16_t *)REG_CAN0_MB05_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB06_DATA3             ((volatile uint16_t *)REG_CAN0_MB06_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB07_DATA3             ((volatile uint16_t *)REG_CAN0_MB07_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB08_DATA3             ((volatile uint16_t *)REG_CAN0_MB08_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB09_DATA3             ((volatile uint16_t *)REG_CAN0_MB09_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB10_DATA3             ((volatile uint16_t *)REG_CAN0_MB10_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB11_DATA3             ((volatile uint16_t *)REG_CAN0_MB11_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB12_DATA3             ((volatile uint16_t *)REG_CAN0_MB12_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB13_DATA3             ((volatile uint16_t *)REG_CAN0_MB13_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB14_DATA3             ((volatile uint16_t *)REG_CAN0_MB14_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB15_DATA3             ((volatile uint16_t *)REG_CAN0_MB15_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB16_DATA3             ((volatile uint16_t *)REG_CAN0_MB16_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB17_DATA3             ((volatile uint16_t *)REG_CAN0_MB17_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB18_DATA3             ((volatile uint16_t *)REG_CAN0_MB18_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB19_DATA3             ((volatile uint16_t *)REG_CAN0_MB19_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB20_DATA3             ((volatile uint16_t *)REG_CAN0_MB20_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB21_DATA3             ((volatile uint16_t *)REG_CAN0_MB21_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB22_DATA3             ((volatile uint16_t *)REG_CAN0_MB22_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB23_DATA3             ((volatile uint16_t *)REG_CAN0_MB23_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB24_DATA3             ((volatile uint16_t *)REG_CAN0_MB24_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB25_DATA3             ((volatile uint16_t *)REG_CAN0_MB25_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB26_DATA3             ((volatile uint16_t *)REG_CAN0_MB26_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB27_DATA3             ((volatile uint16_t *)REG_CAN0_MB27_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB28_DATA3             ((volatile uint16_t *)REG_CAN0_MB28_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB29_DATA3             ((volatile uint16_t *)REG_CAN0_MB29_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB30_DATA3             ((volatile uint16_t *)REG_CAN0_MB30_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB31_DATA3             ((volatile uint16_t *)REG_CAN0_MB31_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB00_LENGTH            ((volatile uint16_t *)REG_CAN0_MB00_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB01_LENGTH            ((volatile uint16_t *)REG_CAN0_MB01_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB02_LENGTH            ((volatile uint16_t *)REG_CAN0_MB02_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB03_LENGTH            ((volatile uint16_t *)REG_CAN0_MB03_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB04_LENGTH            ((volatile uint16_t *)REG_CAN0_MB04_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB05_LENGTH            ((volatile uint16_t *)REG_CAN0_MB05_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB06_LENGTH            ((volatile uint16_t *)REG_CAN0_MB06_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB07_LENGTH            ((volatile uint16_t *)REG_CAN0_MB07_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB08_LENGTH            ((volatile uint16_t *)REG_CAN0_MB08_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB09_LENGTH            ((volatile uint16_t *)REG_CAN0_MB09_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB10_LENGTH            ((volatile uint16_t *)REG_CAN0_MB10_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB11_LENGTH            ((volatile uint16_t *)REG_CAN0_MB11_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB12_LENGTH            ((volatile uint16_t *)REG_CAN0_MB12_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB13_LENGTH            ((volatile uint16_t *)REG_CAN0_MB13_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB14_LENGTH            ((volatile uint16_t *)REG_CAN0_MB14_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB15_LENGTH            ((volatile uint16_t *)REG_CAN0_MB15_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB16_LENGTH            ((volatile uint16_t *)REG_CAN0_MB16_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB17_LENGTH            ((volatile uint16_t *)REG_CAN0_MB17_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB18_LENGTH            ((volatile uint16_t *)REG_CAN0_MB18_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB19_LENGTH            ((volatile uint16_t *)REG_CAN0_MB19_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB20_LENGTH            ((volatile uint16_t *)REG_CAN0_MB20_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB21_LENGTH            ((volatile uint16_t *)REG_CAN0_MB21_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB22_LENGTH            ((volatile uint16_t *)REG_CAN0_MB22_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB23_LENGTH            ((volatile uint16_t *)REG_CAN0_MB23_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB24_LENGTH            ((volatile uint16_t *)REG_CAN0_MB24_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB25_LENGTH            ((volatile uint16_t *)REG_CAN0_MB25_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB26_LENGTH            ((volatile uint16_t *)REG_CAN0_MB26_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB27_LENGTH            ((volatile uint16_t *)REG_CAN0_MB27_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB28_LENGTH            ((volatile uint16_t *)REG_CAN0_MB28_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB29_LENGTH            ((volatile uint16_t *)REG_CAN0_MB29_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB30_LENGTH            ((volatile uint16_t *)REG_CAN0_MB30_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB31_LENGTH            ((volatile uint16_t *)REG_CAN0_MB31_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB00_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB00_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB01_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB01_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB02_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB02_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB03_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB03_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB04_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB04_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB05_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB05_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB06_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB06_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB07_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB07_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB08_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB08_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB09_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB09_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB10_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB10_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB11_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB11_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB12_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB12_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB13_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB13_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB14_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB14_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB15_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB15_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB16_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB16_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB17_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB17_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB18_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB18_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB19_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB19_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB20_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB20_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB21_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB21_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB22_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB22_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB23_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB23_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB24_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB24_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB25_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB25_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB26_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB26_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB27_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB27_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB28_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB28_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB29_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB29_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB30_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB30_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB31_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB31_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB00_ID0               ((volatile uint16_t *)REG_CAN0_MB00_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB01_ID0               ((volatile uint16_t *)REG_CAN0_MB01_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB02_ID0               ((volatile uint16_t *)REG_CAN0_MB02_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB03_ID0               ((volatile uint16_t *)REG_CAN0_MB03_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB04_ID0               ((volatile uint16_t *)REG_CAN0_MB04_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB05_ID0               ((volatile uint16_t *)REG_CAN0_MB05_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB06_ID0               ((volatile uint16_t *)REG_CAN0_MB06_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB07_ID0               ((volatile uint16_t *)REG_CAN0_MB07_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB08_ID0               ((volatile uint16_t *)REG_CAN0_MB08_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB09_ID0               ((volatile uint16_t *)REG_CAN0_MB09_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB10_ID0               ((volatile uint16_t *)REG_CAN0_MB10_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB11_ID0               ((volatile uint16_t *)REG_CAN0_MB11_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB12_ID0               ((volatile uint16_t *)REG_CAN0_MB12_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB13_ID0               ((volatile uint16_t *)REG_CAN0_MB13_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB14_ID0               ((volatile uint16_t *)REG_CAN0_MB14_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB15_ID0               ((volatile uint16_t *)REG_CAN0_MB15_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB16_ID0               ((volatile uint16_t *)REG_CAN0_MB16_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB17_ID0               ((volatile uint16_t *)REG_CAN0_MB17_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB18_ID0               ((volatile uint16_t *)REG_CAN0_MB18_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB19_ID0               ((volatile uint16_t *)REG_CAN0_MB19_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB20_ID0               ((volatile uint16_t *)REG_CAN0_MB20_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB21_ID0               ((volatile uint16_t *)REG_CAN0_MB21_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB22_ID0               ((volatile uint16_t *)REG_CAN0_MB22_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB23_ID0               ((volatile uint16_t *)REG_CAN0_MB23_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB24_ID0               ((volatile uint16_t *)REG_CAN0_MB24_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB25_ID0               ((volatile uint16_t *)REG_CAN0_MB25_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB26_ID0               ((volatile uint16_t *)REG_CAN0_MB26_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB27_ID0               ((volatile uint16_t *)REG_CAN0_MB27_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB28_ID0               ((volatile uint16_t *)REG_CAN0_MB28_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB29_ID0               ((volatile uint16_t *)REG_CAN0_MB29_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB30_ID0               ((volatile uint16_t *)REG_CAN0_MB30_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB31_ID0               ((volatile uint16_t *)REG_CAN0_MB31_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB00_ID1               ((volatile uint16_t *)REG_CAN0_MB00_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB01_ID1               ((volatile uint16_t *)REG_CAN0_MB01_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB02_ID1               ((volatile uint16_t *)REG_CAN0_MB02_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB03_ID1               ((volatile uint16_t *)REG_CAN0_MB03_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB04_ID1               ((volatile uint16_t *)REG_CAN0_MB04_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB05_ID1               ((volatile uint16_t *)REG_CAN0_MB05_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB06_ID1               ((volatile uint16_t *)REG_CAN0_MB06_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB07_ID1               ((volatile uint16_t *)REG_CAN0_MB07_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB08_ID1               ((volatile uint16_t *)REG_CAN0_MB08_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB09_ID1               ((volatile uint16_t *)REG_CAN0_MB09_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB10_ID1               ((volatile uint16_t *)REG_CAN0_MB10_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB11_ID1               ((volatile uint16_t *)REG_CAN0_MB11_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB12_ID1               ((volatile uint16_t *)REG_CAN0_MB12_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB13_ID1               ((volatile uint16_t *)REG_CAN0_MB13_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB14_ID1               ((volatile uint16_t *)REG_CAN0_MB14_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB15_ID1               ((volatile uint16_t *)REG_CAN0_MB15_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB16_ID1               ((volatile uint16_t *)REG_CAN0_MB16_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB17_ID1               ((volatile uint16_t *)REG_CAN0_MB17_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB18_ID1               ((volatile uint16_t *)REG_CAN0_MB18_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB19_ID1               ((volatile uint16_t *)REG_CAN0_MB19_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB20_ID1               ((volatile uint16_t *)REG_CAN0_MB20_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB21_ID1               ((volatile uint16_t *)REG_CAN0_MB21_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB22_ID1               ((volatile uint16_t *)REG_CAN0_MB22_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB23_ID1               ((volatile uint16_t *)REG_CAN0_MB23_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB24_ID1               ((volatile uint16_t *)REG_CAN0_MB24_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB25_ID1               ((volatile uint16_t *)REG_CAN0_MB25_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB26_ID1               ((volatile uint16_t *)REG_CAN0_MB26_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB27_ID1               ((volatile uint16_t *)REG_CAN0_MB27_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB28_ID1               ((volatile uint16_t *)REG_CAN0_MB28_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB29_ID1               ((volatile uint16_t *)REG_CAN0_MB29_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB30_ID1               ((volatile uint16_t *)REG_CAN0_MB30_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB31_ID1               ((volatile uint16_t *)REG_CAN0_MB31_ID1)                /* CAN0 Mailbox ID 1 Register */
-
-
-/* =========================================================================
-       LP0
-   ========================================================================= */
-#define pREG_LP0_CTL                     ((volatile uint32_t *)REG_LP0_CTL)                      /* LP0 Control Register */
-#define pREG_LP0_STAT                    ((volatile uint32_t *)REG_LP0_STAT)                     /* LP0 Status Register */
-#define pREG_LP0_DIV                     ((volatile uint32_t *)REG_LP0_DIV)                      /* LP0 Clock Divider Value */
-#define pREG_LP0_TX                      ((volatile uint32_t *)REG_LP0_TX)                       /* LP0 Transmit Buffer */
-#define pREG_LP0_RX                      ((volatile uint32_t *)REG_LP0_RX)                       /* LP0 Receive Buffer */
-#define pREG_LP0_TXIN_SHDW               ((volatile uint32_t *)REG_LP0_TXIN_SHDW)                /* LP0 Shadow Input Transmit Buffer */
-#define pREG_LP0_TXOUT_SHDW              ((volatile uint32_t *)REG_LP0_TXOUT_SHDW)               /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP1
-   ========================================================================= */
-#define pREG_LP1_CTL                     ((volatile uint32_t *)REG_LP1_CTL)                      /* LP1 Control Register */
-#define pREG_LP1_STAT                    ((volatile uint32_t *)REG_LP1_STAT)                     /* LP1 Status Register */
-#define pREG_LP1_DIV                     ((volatile uint32_t *)REG_LP1_DIV)                      /* LP1 Clock Divider Value */
-#define pREG_LP1_TX                      ((volatile uint32_t *)REG_LP1_TX)                       /* LP1 Transmit Buffer */
-#define pREG_LP1_RX                      ((volatile uint32_t *)REG_LP1_RX)                       /* LP1 Receive Buffer */
-#define pREG_LP1_TXIN_SHDW               ((volatile uint32_t *)REG_LP1_TXIN_SHDW)                /* LP1 Shadow Input Transmit Buffer */
-#define pREG_LP1_TXOUT_SHDW              ((volatile uint32_t *)REG_LP1_TXOUT_SHDW)               /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP2
-   ========================================================================= */
-#define pREG_LP2_CTL                     ((volatile uint32_t *)REG_LP2_CTL)                      /* LP2 Control Register */
-#define pREG_LP2_STAT                    ((volatile uint32_t *)REG_LP2_STAT)                     /* LP2 Status Register */
-#define pREG_LP2_DIV                     ((volatile uint32_t *)REG_LP2_DIV)                      /* LP2 Clock Divider Value */
-#define pREG_LP2_TX                      ((volatile uint32_t *)REG_LP2_TX)                       /* LP2 Transmit Buffer */
-#define pREG_LP2_RX                      ((volatile uint32_t *)REG_LP2_RX)                       /* LP2 Receive Buffer */
-#define pREG_LP2_TXIN_SHDW               ((volatile uint32_t *)REG_LP2_TXIN_SHDW)                /* LP2 Shadow Input Transmit Buffer */
-#define pREG_LP2_TXOUT_SHDW              ((volatile uint32_t *)REG_LP2_TXOUT_SHDW)               /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP3
-   ========================================================================= */
-#define pREG_LP3_CTL                     ((volatile uint32_t *)REG_LP3_CTL)                      /* LP3 Control Register */
-#define pREG_LP3_STAT                    ((volatile uint32_t *)REG_LP3_STAT)                     /* LP3 Status Register */
-#define pREG_LP3_DIV                     ((volatile uint32_t *)REG_LP3_DIV)                      /* LP3 Clock Divider Value */
-#define pREG_LP3_TX                      ((volatile uint32_t *)REG_LP3_TX)                       /* LP3 Transmit Buffer */
-#define pREG_LP3_RX                      ((volatile uint32_t *)REG_LP3_RX)                       /* LP3 Receive Buffer */
-#define pREG_LP3_TXIN_SHDW               ((volatile uint32_t *)REG_LP3_TXIN_SHDW)                /* LP3 Shadow Input Transmit Buffer */
-#define pREG_LP3_TXOUT_SHDW              ((volatile uint32_t *)REG_LP3_TXOUT_SHDW)               /* LP3 Shadow Output Transmit Buffer */
-
-
-/* =========================================================================
-       TIMER0
-   ========================================================================= */
-#define pREG_TIMER0_REVID                ((volatile uint16_t *)REG_TIMER0_REVID)                 /* TIMER0 Revision ID Register */
-#define pREG_TIMER0_RUN                  ((volatile uint16_t *)REG_TIMER0_RUN)                   /* TIMER0 Run Register */
-#define pREG_TIMER0_RUN_SET              ((volatile uint16_t *)REG_TIMER0_RUN_SET)               /* TIMER0 Run Set Register */
-#define pREG_TIMER0_RUN_CLR              ((volatile uint16_t *)REG_TIMER0_RUN_CLR)               /* TIMER0 Run Clear Register */
-#define pREG_TIMER0_STOP_CFG             ((volatile uint16_t *)REG_TIMER0_STOP_CFG)              /* TIMER0 Stop Configuration Register */
-#define pREG_TIMER0_STOP_CFG_SET         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_SET)          /* TIMER0 Stop Configuration Set Register */
-#define pREG_TIMER0_STOP_CFG_CLR         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_CLR)          /* TIMER0 Stop Configuration Clear Register */
-#define pREG_TIMER0_DATA_IMSK            ((volatile uint16_t *)REG_TIMER0_DATA_IMSK)             /* TIMER0 Data Interrupt Mask Register */
-#define pREG_TIMER0_STAT_IMSK            ((volatile uint16_t *)REG_TIMER0_STAT_IMSK)             /* TIMER0 Status Interrupt Mask Register */
-#define pREG_TIMER0_TRG_MSK              ((volatile uint16_t *)REG_TIMER0_TRG_MSK)               /* TIMER0 Trigger Master Mask Register */
-#define pREG_TIMER0_TRG_IE               ((volatile uint16_t *)REG_TIMER0_TRG_IE)                /* TIMER0 Trigger Slave Enable Register */
-#define pREG_TIMER0_DATA_ILAT            ((volatile uint16_t *)REG_TIMER0_DATA_ILAT)             /* TIMER0 Data Interrupt Latch Register */
-#define pREG_TIMER0_STAT_ILAT            ((volatile uint16_t *)REG_TIMER0_STAT_ILAT)             /* TIMER0 Status Interrupt Latch Register */
-#define pREG_TIMER0_ERR_TYPE             ((volatile uint32_t *)REG_TIMER0_ERR_TYPE)              /* TIMER0 Error Type Status Register */
-#define pREG_TIMER0_BCAST_PER            ((volatile uint32_t *)REG_TIMER0_BCAST_PER)             /* TIMER0 Broadcast Period Register */
-#define pREG_TIMER0_BCAST_WID            ((volatile uint32_t *)REG_TIMER0_BCAST_WID)             /* TIMER0 Broadcast Width Register */
-#define pREG_TIMER0_BCAST_DLY            ((volatile uint32_t *)REG_TIMER0_BCAST_DLY)             /* TIMER0 Broadcast Delay Register */
-#define pREG_TIMER0_TMR0_CFG             ((volatile uint16_t *)REG_TIMER0_TMR0_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR1_CFG             ((volatile uint16_t *)REG_TIMER0_TMR1_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR2_CFG             ((volatile uint16_t *)REG_TIMER0_TMR2_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR3_CFG             ((volatile uint16_t *)REG_TIMER0_TMR3_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR4_CFG             ((volatile uint16_t *)REG_TIMER0_TMR4_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR5_CFG             ((volatile uint16_t *)REG_TIMER0_TMR5_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR6_CFG             ((volatile uint16_t *)REG_TIMER0_TMR6_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR7_CFG             ((volatile uint16_t *)REG_TIMER0_TMR7_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR0_CNT             ((volatile uint32_t *)REG_TIMER0_TMR0_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR1_CNT             ((volatile uint32_t *)REG_TIMER0_TMR1_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR2_CNT             ((volatile uint32_t *)REG_TIMER0_TMR2_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR3_CNT             ((volatile uint32_t *)REG_TIMER0_TMR3_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR4_CNT             ((volatile uint32_t *)REG_TIMER0_TMR4_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR5_CNT             ((volatile uint32_t *)REG_TIMER0_TMR5_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR6_CNT             ((volatile uint32_t *)REG_TIMER0_TMR6_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR7_CNT             ((volatile uint32_t *)REG_TIMER0_TMR7_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR0_PER             ((volatile uint32_t *)REG_TIMER0_TMR0_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR1_PER             ((volatile uint32_t *)REG_TIMER0_TMR1_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR2_PER             ((volatile uint32_t *)REG_TIMER0_TMR2_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR3_PER             ((volatile uint32_t *)REG_TIMER0_TMR3_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR4_PER             ((volatile uint32_t *)REG_TIMER0_TMR4_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR5_PER             ((volatile uint32_t *)REG_TIMER0_TMR5_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR6_PER             ((volatile uint32_t *)REG_TIMER0_TMR6_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR7_PER             ((volatile uint32_t *)REG_TIMER0_TMR7_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR0_WID             ((volatile uint32_t *)REG_TIMER0_TMR0_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR1_WID             ((volatile uint32_t *)REG_TIMER0_TMR1_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR2_WID             ((volatile uint32_t *)REG_TIMER0_TMR2_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR3_WID             ((volatile uint32_t *)REG_TIMER0_TMR3_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR4_WID             ((volatile uint32_t *)REG_TIMER0_TMR4_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR5_WID             ((volatile uint32_t *)REG_TIMER0_TMR5_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR6_WID             ((volatile uint32_t *)REG_TIMER0_TMR6_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR7_WID             ((volatile uint32_t *)REG_TIMER0_TMR7_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR0_DLY             ((volatile uint32_t *)REG_TIMER0_TMR0_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR1_DLY             ((volatile uint32_t *)REG_TIMER0_TMR1_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR2_DLY             ((volatile uint32_t *)REG_TIMER0_TMR2_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR3_DLY             ((volatile uint32_t *)REG_TIMER0_TMR3_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR4_DLY             ((volatile uint32_t *)REG_TIMER0_TMR4_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR5_DLY             ((volatile uint32_t *)REG_TIMER0_TMR5_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR6_DLY             ((volatile uint32_t *)REG_TIMER0_TMR6_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR7_DLY             ((volatile uint32_t *)REG_TIMER0_TMR7_DLY)              /* TIMER0 Timer n Delay Register */
-
-
-/* =========================================================================
-       CRC0
-   ========================================================================= */
-#define pREG_CRC0_CTL                    ((volatile uint32_t *)REG_CRC0_CTL)                     /* CRC0 Control Register */
-#define pREG_CRC0_DCNT                   ((volatile uint32_t *)REG_CRC0_DCNT)                    /* CRC0 Data Word Count Register */
-#define pREG_CRC0_DCNTRLD                ((volatile uint32_t *)REG_CRC0_DCNTRLD)                 /* CRC0 Data Word Count Reload Register */
-#define pREG_CRC0_COMP                   ((volatile uint32_t *)REG_CRC0_COMP)                    /* CRC0 Data Compare Register */
-#define pREG_CRC0_FILLVAL                ((volatile uint32_t *)REG_CRC0_FILLVAL)                 /* CRC0 Fill Value Register */
-#define pREG_CRC0_DFIFO                  ((volatile uint32_t *)REG_CRC0_DFIFO)                   /* CRC0 Data FIFO Register */
-#define pREG_CRC0_INEN                   ((volatile uint32_t *)REG_CRC0_INEN)                    /* CRC0 Interrupt Enable Register */
-#define pREG_CRC0_INEN_SET               ((volatile uint32_t *)REG_CRC0_INEN_SET)                /* CRC0 Interrupt Enable Set Register */
-#define pREG_CRC0_INEN_CLR               ((volatile uint32_t *)REG_CRC0_INEN_CLR)                /* CRC0 Interrupt Enable Clear Register */
-#define pREG_CRC0_POLY                   ((volatile uint32_t *)REG_CRC0_POLY)                    /* CRC0 Polynomial Register */
-#define pREG_CRC0_STAT                   ((volatile uint32_t *)REG_CRC0_STAT)                    /* CRC0 Status Register */
-#define pREG_CRC0_DCNTCAP                ((volatile uint32_t *)REG_CRC0_DCNTCAP)                 /* CRC0 Data Count Capture Register */
-#define pREG_CRC0_RESULT_FIN             ((volatile uint32_t *)REG_CRC0_RESULT_FIN)              /* CRC0 CRC Final Result Register */
-#define pREG_CRC0_RESULT_CUR             ((volatile uint32_t *)REG_CRC0_RESULT_CUR)              /* CRC0 CRC Current Result Register */
-#define pREG_CRC0_REVID                  ((volatile uint32_t *)REG_CRC0_REVID)                   /* CRC0 Revision ID Register */
-
-/* =========================================================================
-       CRC1
-   ========================================================================= */
-#define pREG_CRC1_CTL                    ((volatile uint32_t *)REG_CRC1_CTL)                     /* CRC1 Control Register */
-#define pREG_CRC1_DCNT                   ((volatile uint32_t *)REG_CRC1_DCNT)                    /* CRC1 Data Word Count Register */
-#define pREG_CRC1_DCNTRLD                ((volatile uint32_t *)REG_CRC1_DCNTRLD)                 /* CRC1 Data Word Count Reload Register */
-#define pREG_CRC1_COMP                   ((volatile uint32_t *)REG_CRC1_COMP)                    /* CRC1 Data Compare Register */
-#define pREG_CRC1_FILLVAL                ((volatile uint32_t *)REG_CRC1_FILLVAL)                 /* CRC1 Fill Value Register */
-#define pREG_CRC1_DFIFO                  ((volatile uint32_t *)REG_CRC1_DFIFO)                   /* CRC1 Data FIFO Register */
-#define pREG_CRC1_INEN                   ((volatile uint32_t *)REG_CRC1_INEN)                    /* CRC1 Interrupt Enable Register */
-#define pREG_CRC1_INEN_SET               ((volatile uint32_t *)REG_CRC1_INEN_SET)                /* CRC1 Interrupt Enable Set Register */
-#define pREG_CRC1_INEN_CLR               ((volatile uint32_t *)REG_CRC1_INEN_CLR)                /* CRC1 Interrupt Enable Clear Register */
-#define pREG_CRC1_POLY                   ((volatile uint32_t *)REG_CRC1_POLY)                    /* CRC1 Polynomial Register */
-#define pREG_CRC1_STAT                   ((volatile uint32_t *)REG_CRC1_STAT)                    /* CRC1 Status Register */
-#define pREG_CRC1_DCNTCAP                ((volatile uint32_t *)REG_CRC1_DCNTCAP)                 /* CRC1 Data Count Capture Register */
-#define pREG_CRC1_RESULT_FIN             ((volatile uint32_t *)REG_CRC1_RESULT_FIN)              /* CRC1 CRC Final Result Register */
-#define pREG_CRC1_RESULT_CUR             ((volatile uint32_t *)REG_CRC1_RESULT_CUR)              /* CRC1 CRC Current Result Register */
-#define pREG_CRC1_REVID                  ((volatile uint32_t *)REG_CRC1_REVID)                   /* CRC1 Revision ID Register */
-
-
-/* =========================================================================
-       TWI0
-   ========================================================================= */
-#define pREG_TWI0_CLKDIV                 ((volatile uint16_t *)REG_TWI0_CLKDIV)                  /* TWI0 SCL Clock Divider Register */
-#define pREG_TWI0_CTL                    ((volatile uint16_t *)REG_TWI0_CTL)                     /* TWI0 Control Register */
-#define pREG_TWI0_SLVCTL                 ((volatile uint16_t *)REG_TWI0_SLVCTL)                  /* TWI0 Slave Mode Control Register */
-#define pREG_TWI0_SLVSTAT                ((volatile uint16_t *)REG_TWI0_SLVSTAT)                 /* TWI0 Slave Mode Status Register */
-#define pREG_TWI0_SLVADDR                ((volatile uint16_t *)REG_TWI0_SLVADDR)                 /* TWI0 Slave Mode Address Register */
-#define pREG_TWI0_MSTRCTL                ((volatile uint16_t *)REG_TWI0_MSTRCTL)                 /* TWI0 Master Mode Control Registers */
-#define pREG_TWI0_MSTRSTAT               ((volatile uint16_t *)REG_TWI0_MSTRSTAT)                /* TWI0 Master Mode Status Register */
-#define pREG_TWI0_MSTRADDR               ((volatile uint16_t *)REG_TWI0_MSTRADDR)                /* TWI0 Master Mode Address Register */
-#define pREG_TWI0_ISTAT                  ((volatile uint16_t *)REG_TWI0_ISTAT)                   /* TWI0 Interrupt Status Register */
-#define pREG_TWI0_IMSK                   ((volatile uint16_t *)REG_TWI0_IMSK)                    /* TWI0 Interrupt Mask Register */
-#define pREG_TWI0_FIFOCTL                ((volatile uint16_t *)REG_TWI0_FIFOCTL)                 /* TWI0 FIFO Control Register */
-#define pREG_TWI0_FIFOSTAT               ((volatile uint16_t *)REG_TWI0_FIFOSTAT)                /* TWI0 FIFO Status Register */
-#define pREG_TWI0_TXDATA8                ((volatile uint16_t *)REG_TWI0_TXDATA8)                 /* TWI0 Tx Data Single-Byte Register */
-#define pREG_TWI0_TXDATA16               ((volatile uint16_t *)REG_TWI0_TXDATA16)                /* TWI0 Tx Data Double-Byte Register */
-#define pREG_TWI0_RXDATA8                ((volatile uint16_t *)REG_TWI0_RXDATA8)                 /* TWI0 Rx Data Single-Byte Register */
-#define pREG_TWI0_RXDATA16               ((volatile uint16_t *)REG_TWI0_RXDATA16)                /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================================================================
-       TWI1
-   ========================================================================= */
-#define pREG_TWI1_CLKDIV                 ((volatile uint16_t *)REG_TWI1_CLKDIV)                  /* TWI1 SCL Clock Divider Register */
-#define pREG_TWI1_CTL                    ((volatile uint16_t *)REG_TWI1_CTL)                     /* TWI1 Control Register */
-#define pREG_TWI1_SLVCTL                 ((volatile uint16_t *)REG_TWI1_SLVCTL)                  /* TWI1 Slave Mode Control Register */
-#define pREG_TWI1_SLVSTAT                ((volatile uint16_t *)REG_TWI1_SLVSTAT)                 /* TWI1 Slave Mode Status Register */
-#define pREG_TWI1_SLVADDR                ((volatile uint16_t *)REG_TWI1_SLVADDR)                 /* TWI1 Slave Mode Address Register */
-#define pREG_TWI1_MSTRCTL                ((volatile uint16_t *)REG_TWI1_MSTRCTL)                 /* TWI1 Master Mode Control Registers */
-#define pREG_TWI1_MSTRSTAT               ((volatile uint16_t *)REG_TWI1_MSTRSTAT)                /* TWI1 Master Mode Status Register */
-#define pREG_TWI1_MSTRADDR               ((volatile uint16_t *)REG_TWI1_MSTRADDR)                /* TWI1 Master Mode Address Register */
-#define pREG_TWI1_ISTAT                  ((volatile uint16_t *)REG_TWI1_ISTAT)                   /* TWI1 Interrupt Status Register */
-#define pREG_TWI1_IMSK                   ((volatile uint16_t *)REG_TWI1_IMSK)                    /* TWI1 Interrupt Mask Register */
-#define pREG_TWI1_FIFOCTL                ((volatile uint16_t *)REG_TWI1_FIFOCTL)                 /* TWI1 FIFO Control Register */
-#define pREG_TWI1_FIFOSTAT               ((volatile uint16_t *)REG_TWI1_FIFOSTAT)                /* TWI1 FIFO Status Register */
-#define pREG_TWI1_TXDATA8                ((volatile uint16_t *)REG_TWI1_TXDATA8)                 /* TWI1 Tx Data Single-Byte Register */
-#define pREG_TWI1_TXDATA16               ((volatile uint16_t *)REG_TWI1_TXDATA16)                /* TWI1 Tx Data Double-Byte Register */
-#define pREG_TWI1_RXDATA8                ((volatile uint16_t *)REG_TWI1_RXDATA8)                 /* TWI1 Rx Data Single-Byte Register */
-#define pREG_TWI1_RXDATA16               ((volatile uint16_t *)REG_TWI1_RXDATA16)                /* TWI1 Rx Data Double-Byte Register */
-
-
-/* =========================================================================
-       UART0
-   ========================================================================= */
-#define pREG_UART0_REVID                 ((volatile uint32_t *)REG_UART0_REVID)                  /* UART0 Revision ID Register */
-#define pREG_UART0_CTL                   ((volatile uint32_t *)REG_UART0_CTL)                    /* UART0 Control Register */
-#define pREG_UART0_STAT                  ((volatile uint32_t *)REG_UART0_STAT)                   /* UART0 Status Register */
-#define pREG_UART0_SCR                   ((volatile uint32_t *)REG_UART0_SCR)                    /* UART0 Scratch Register */
-#define pREG_UART0_CLK                   ((volatile uint32_t *)REG_UART0_CLK)                    /* UART0 Clock Rate Register */
-#define pREG_UART0_IMSK                  ((volatile uint32_t *)REG_UART0_IMSK)                   /* UART0 Interrupt Mask Register */
-#define pREG_UART0_IMSK_SET              ((volatile uint32_t *)REG_UART0_IMSK_SET)               /* UART0 Interrupt Mask Set Register */
-#define pREG_UART0_IMSK_CLR              ((volatile uint32_t *)REG_UART0_IMSK_CLR)               /* UART0 Interrupt Mask Clear Register */
-#define pREG_UART0_RBR                   ((volatile uint32_t *)REG_UART0_RBR)                    /* UART0 Receive Buffer Register */
-#define pREG_UART0_THR                   ((volatile uint32_t *)REG_UART0_THR)                    /* UART0 Transmit Hold Register */
-#define pREG_UART0_TAIP                  ((volatile uint32_t *)REG_UART0_TAIP)                   /* UART0 Transmit Address/Insert Pulse Register */
-#define pREG_UART0_TSR                   ((volatile uint32_t *)REG_UART0_TSR)                    /* UART0 Transmit Shift Register */
-#define pREG_UART0_RSR                   ((volatile uint32_t *)REG_UART0_RSR)                    /* UART0 Receive Shift Register */
-#define pREG_UART0_TXCNT                 ((volatile uint32_t *)REG_UART0_TXCNT)                  /* UART0 Transmit Counter Register */
-#define pREG_UART0_RXCNT                 ((volatile uint32_t *)REG_UART0_RXCNT)                  /* UART0 Receive Counter Register */
-
-/* =========================================================================
-       UART1
-   ========================================================================= */
-#define pREG_UART1_REVID                 ((volatile uint32_t *)REG_UART1_REVID)                  /* UART1 Revision ID Register */
-#define pREG_UART1_CTL                   ((volatile uint32_t *)REG_UART1_CTL)                    /* UART1 Control Register */
-#define pREG_UART1_STAT                  ((volatile uint32_t *)REG_UART1_STAT)                   /* UART1 Status Register */
-#define pREG_UART1_SCR                   ((volatile uint32_t *)REG_UART1_SCR)                    /* UART1 Scratch Register */
-#define pREG_UART1_CLK                   ((volatile uint32_t *)REG_UART1_CLK)                    /* UART1 Clock Rate Register */
-#define pREG_UART1_IMSK                  ((volatile uint32_t *)REG_UART1_IMSK)                   /* UART1 Interrupt Mask Register */
-#define pREG_UART1_IMSK_SET              ((volatile uint32_t *)REG_UART1_IMSK_SET)               /* UART1 Interrupt Mask Set Register */
-#define pREG_UART1_IMSK_CLR              ((volatile uint32_t *)REG_UART1_IMSK_CLR)               /* UART1 Interrupt Mask Clear Register */
-#define pREG_UART1_RBR                   ((volatile uint32_t *)REG_UART1_RBR)                    /* UART1 Receive Buffer Register */
-#define pREG_UART1_THR                   ((volatile uint32_t *)REG_UART1_THR)                    /* UART1 Transmit Hold Register */
-#define pREG_UART1_TAIP                  ((volatile uint32_t *)REG_UART1_TAIP)                   /* UART1 Transmit Address/Insert Pulse Register */
-#define pREG_UART1_TSR                   ((volatile uint32_t *)REG_UART1_TSR)                    /* UART1 Transmit Shift Register */
-#define pREG_UART1_RSR                   ((volatile uint32_t *)REG_UART1_RSR)                    /* UART1 Receive Shift Register */
-#define pREG_UART1_TXCNT                 ((volatile uint32_t *)REG_UART1_TXCNT)                  /* UART1 Transmit Counter Register */
-#define pREG_UART1_RXCNT                 ((volatile uint32_t *)REG_UART1_RXCNT)                  /* UART1 Receive Counter Register */
-
-
-/* =========================================================================
-       PORTA
-   ========================================================================= */
-#define pREG_PORTA_FER                   ((volatile uint32_t *)REG_PORTA_FER)                    /* PORTA Port x Function Enable Register */
-#define pREG_PORTA_FER_SET               ((volatile uint32_t *)REG_PORTA_FER_SET)                /* PORTA Port x Function Enable Set Register */
-#define pREG_PORTA_FER_CLR               ((volatile uint32_t *)REG_PORTA_FER_CLR)                /* PORTA Port x Function Enable Clear Register */
-#define pREG_PORTA_DATA                  ((volatile uint32_t *)REG_PORTA_DATA)                   /* PORTA Port x GPIO Data Register */
-#define pREG_PORTA_DATA_SET              ((volatile uint32_t *)REG_PORTA_DATA_SET)               /* PORTA Port x GPIO Data Set Register */
-#define pREG_PORTA_DATA_CLR              ((volatile uint32_t *)REG_PORTA_DATA_CLR)               /* PORTA Port x GPIO Data Clear Register */
-#define pREG_PORTA_DIR                   ((volatile uint32_t *)REG_PORTA_DIR)                    /* PORTA Port x GPIO Direction Register */
-#define pREG_PORTA_DIR_SET               ((volatile uint32_t *)REG_PORTA_DIR_SET)                /* PORTA Port x GPIO Direction Set Register */
-#define pREG_PORTA_DIR_CLR               ((volatile uint32_t *)REG_PORTA_DIR_CLR)                /* PORTA Port x GPIO Direction Clear Register */
-#define pREG_PORTA_INEN                  ((volatile uint32_t *)REG_PORTA_INEN)                   /* PORTA Port x GPIO Input Enable Register */
-#define pREG_PORTA_INEN_SET              ((volatile uint32_t *)REG_PORTA_INEN_SET)               /* PORTA Port x GPIO Input Enable Set Register */
-#define pREG_PORTA_INEN_CLR              ((volatile uint32_t *)REG_PORTA_INEN_CLR)               /* PORTA Port x GPIO Input Enable Clear Register */
-#define pREG_PORTA_MUX                   ((volatile uint32_t *)REG_PORTA_MUX)                    /* PORTA Port x Multiplexer Control Register */
-#define pREG_PORTA_DATA_TGL              ((volatile uint32_t *)REG_PORTA_DATA_TGL)               /* PORTA Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTA_POL                   ((volatile uint32_t *)REG_PORTA_POL)                    /* PORTA Port x GPIO Polarity Invert Register */
-#define pREG_PORTA_POL_SET               ((volatile uint32_t *)REG_PORTA_POL_SET)                /* PORTA Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTA_POL_CLR               ((volatile uint32_t *)REG_PORTA_POL_CLR)                /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTA_LOCK                  ((volatile uint32_t *)REG_PORTA_LOCK)                   /* PORTA Port x GPIO Lock Register */
-#define pREG_PORTA_REVID                 ((volatile uint32_t *)REG_PORTA_REVID)                  /* PORTA Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTB
-   ========================================================================= */
-#define pREG_PORTB_FER                   ((volatile uint32_t *)REG_PORTB_FER)                    /* PORTB Port x Function Enable Register */
-#define pREG_PORTB_FER_SET               ((volatile uint32_t *)REG_PORTB_FER_SET)                /* PORTB Port x Function Enable Set Register */
-#define pREG_PORTB_FER_CLR               ((volatile uint32_t *)REG_PORTB_FER_CLR)                /* PORTB Port x Function Enable Clear Register */
-#define pREG_PORTB_DATA                  ((volatile uint32_t *)REG_PORTB_DATA)                   /* PORTB Port x GPIO Data Register */
-#define pREG_PORTB_DATA_SET              ((volatile uint32_t *)REG_PORTB_DATA_SET)               /* PORTB Port x GPIO Data Set Register */
-#define pREG_PORTB_DATA_CLR              ((volatile uint32_t *)REG_PORTB_DATA_CLR)               /* PORTB Port x GPIO Data Clear Register */
-#define pREG_PORTB_DIR                   ((volatile uint32_t *)REG_PORTB_DIR)                    /* PORTB Port x GPIO Direction Register */
-#define pREG_PORTB_DIR_SET               ((volatile uint32_t *)REG_PORTB_DIR_SET)                /* PORTB Port x GPIO Direction Set Register */
-#define pREG_PORTB_DIR_CLR               ((volatile uint32_t *)REG_PORTB_DIR_CLR)                /* PORTB Port x GPIO Direction Clear Register */
-#define pREG_PORTB_INEN                  ((volatile uint32_t *)REG_PORTB_INEN)                   /* PORTB Port x GPIO Input Enable Register */
-#define pREG_PORTB_INEN_SET              ((volatile uint32_t *)REG_PORTB_INEN_SET)               /* PORTB Port x GPIO Input Enable Set Register */
-#define pREG_PORTB_INEN_CLR              ((volatile uint32_t *)REG_PORTB_INEN_CLR)               /* PORTB Port x GPIO Input Enable Clear Register */
-#define pREG_PORTB_MUX                   ((volatile uint32_t *)REG_PORTB_MUX)                    /* PORTB Port x Multiplexer Control Register */
-#define pREG_PORTB_DATA_TGL              ((volatile uint32_t *)REG_PORTB_DATA_TGL)               /* PORTB Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTB_POL                   ((volatile uint32_t *)REG_PORTB_POL)                    /* PORTB Port x GPIO Polarity Invert Register */
-#define pREG_PORTB_POL_SET               ((volatile uint32_t *)REG_PORTB_POL_SET)                /* PORTB Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTB_POL_CLR               ((volatile uint32_t *)REG_PORTB_POL_CLR)                /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTB_LOCK                  ((volatile uint32_t *)REG_PORTB_LOCK)                   /* PORTB Port x GPIO Lock Register */
-#define pREG_PORTB_REVID                 ((volatile uint32_t *)REG_PORTB_REVID)                  /* PORTB Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTC
-   ========================================================================= */
-#define pREG_PORTC_FER                   ((volatile uint32_t *)REG_PORTC_FER)                    /* PORTC Port x Function Enable Register */
-#define pREG_PORTC_FER_SET               ((volatile uint32_t *)REG_PORTC_FER_SET)                /* PORTC Port x Function Enable Set Register */
-#define pREG_PORTC_FER_CLR               ((volatile uint32_t *)REG_PORTC_FER_CLR)                /* PORTC Port x Function Enable Clear Register */
-#define pREG_PORTC_DATA                  ((volatile uint32_t *)REG_PORTC_DATA)                   /* PORTC Port x GPIO Data Register */
-#define pREG_PORTC_DATA_SET              ((volatile uint32_t *)REG_PORTC_DATA_SET)               /* PORTC Port x GPIO Data Set Register */
-#define pREG_PORTC_DATA_CLR              ((volatile uint32_t *)REG_PORTC_DATA_CLR)               /* PORTC Port x GPIO Data Clear Register */
-#define pREG_PORTC_DIR                   ((volatile uint32_t *)REG_PORTC_DIR)                    /* PORTC Port x GPIO Direction Register */
-#define pREG_PORTC_DIR_SET               ((volatile uint32_t *)REG_PORTC_DIR_SET)                /* PORTC Port x GPIO Direction Set Register */
-#define pREG_PORTC_DIR_CLR               ((volatile uint32_t *)REG_PORTC_DIR_CLR)                /* PORTC Port x GPIO Direction Clear Register */
-#define pREG_PORTC_INEN                  ((volatile uint32_t *)REG_PORTC_INEN)                   /* PORTC Port x GPIO Input Enable Register */
-#define pREG_PORTC_INEN_SET              ((volatile uint32_t *)REG_PORTC_INEN_SET)               /* PORTC Port x GPIO Input Enable Set Register */
-#define pREG_PORTC_INEN_CLR              ((volatile uint32_t *)REG_PORTC_INEN_CLR)               /* PORTC Port x GPIO Input Enable Clear Register */
-#define pREG_PORTC_MUX                   ((volatile uint32_t *)REG_PORTC_MUX)                    /* PORTC Port x Multiplexer Control Register */
-#define pREG_PORTC_DATA_TGL              ((volatile uint32_t *)REG_PORTC_DATA_TGL)               /* PORTC Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTC_POL                   ((volatile uint32_t *)REG_PORTC_POL)                    /* PORTC Port x GPIO Polarity Invert Register */
-#define pREG_PORTC_POL_SET               ((volatile uint32_t *)REG_PORTC_POL_SET)                /* PORTC Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTC_POL_CLR               ((volatile uint32_t *)REG_PORTC_POL_CLR)                /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTC_LOCK                  ((volatile uint32_t *)REG_PORTC_LOCK)                   /* PORTC Port x GPIO Lock Register */
-#define pREG_PORTC_REVID                 ((volatile uint32_t *)REG_PORTC_REVID)                  /* PORTC Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTD
-   ========================================================================= */
-#define pREG_PORTD_FER                   ((volatile uint32_t *)REG_PORTD_FER)                    /* PORTD Port x Function Enable Register */
-#define pREG_PORTD_FER_SET               ((volatile uint32_t *)REG_PORTD_FER_SET)                /* PORTD Port x Function Enable Set Register */
-#define pREG_PORTD_FER_CLR               ((volatile uint32_t *)REG_PORTD_FER_CLR)                /* PORTD Port x Function Enable Clear Register */
-#define pREG_PORTD_DATA                  ((volatile uint32_t *)REG_PORTD_DATA)                   /* PORTD Port x GPIO Data Register */
-#define pREG_PORTD_DATA_SET              ((volatile uint32_t *)REG_PORTD_DATA_SET)               /* PORTD Port x GPIO Data Set Register */
-#define pREG_PORTD_DATA_CLR              ((volatile uint32_t *)REG_PORTD_DATA_CLR)               /* PORTD Port x GPIO Data Clear Register */
-#define pREG_PORTD_DIR                   ((volatile uint32_t *)REG_PORTD_DIR)                    /* PORTD Port x GPIO Direction Register */
-#define pREG_PORTD_DIR_SET               ((volatile uint32_t *)REG_PORTD_DIR_SET)                /* PORTD Port x GPIO Direction Set Register */
-#define pREG_PORTD_DIR_CLR               ((volatile uint32_t *)REG_PORTD_DIR_CLR)                /* PORTD Port x GPIO Direction Clear Register */
-#define pREG_PORTD_INEN                  ((volatile uint32_t *)REG_PORTD_INEN)                   /* PORTD Port x GPIO Input Enable Register */
-#define pREG_PORTD_INEN_SET              ((volatile uint32_t *)REG_PORTD_INEN_SET)               /* PORTD Port x GPIO Input Enable Set Register */
-#define pREG_PORTD_INEN_CLR              ((volatile uint32_t *)REG_PORTD_INEN_CLR)               /* PORTD Port x GPIO Input Enable Clear Register */
-#define pREG_PORTD_MUX                   ((volatile uint32_t *)REG_PORTD_MUX)                    /* PORTD Port x Multiplexer Control Register */
-#define pREG_PORTD_DATA_TGL              ((volatile uint32_t *)REG_PORTD_DATA_TGL)               /* PORTD Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTD_POL                   ((volatile uint32_t *)REG_PORTD_POL)                    /* PORTD Port x GPIO Polarity Invert Register */
-#define pREG_PORTD_POL_SET               ((volatile uint32_t *)REG_PORTD_POL_SET)                /* PORTD Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTD_POL_CLR               ((volatile uint32_t *)REG_PORTD_POL_CLR)                /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTD_LOCK                  ((volatile uint32_t *)REG_PORTD_LOCK)                   /* PORTD Port x GPIO Lock Register */
-#define pREG_PORTD_REVID                 ((volatile uint32_t *)REG_PORTD_REVID)                  /* PORTD Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTE
-   ========================================================================= */
-#define pREG_PORTE_FER                   ((volatile uint32_t *)REG_PORTE_FER)                    /* PORTE Port x Function Enable Register */
-#define pREG_PORTE_FER_SET               ((volatile uint32_t *)REG_PORTE_FER_SET)                /* PORTE Port x Function Enable Set Register */
-#define pREG_PORTE_FER_CLR               ((volatile uint32_t *)REG_PORTE_FER_CLR)                /* PORTE Port x Function Enable Clear Register */
-#define pREG_PORTE_DATA                  ((volatile uint32_t *)REG_PORTE_DATA)                   /* PORTE Port x GPIO Data Register */
-#define pREG_PORTE_DATA_SET              ((volatile uint32_t *)REG_PORTE_DATA_SET)               /* PORTE Port x GPIO Data Set Register */
-#define pREG_PORTE_DATA_CLR              ((volatile uint32_t *)REG_PORTE_DATA_CLR)               /* PORTE Port x GPIO Data Clear Register */
-#define pREG_PORTE_DIR                   ((volatile uint32_t *)REG_PORTE_DIR)                    /* PORTE Port x GPIO Direction Register */
-#define pREG_PORTE_DIR_SET               ((volatile uint32_t *)REG_PORTE_DIR_SET)                /* PORTE Port x GPIO Direction Set Register */
-#define pREG_PORTE_DIR_CLR               ((volatile uint32_t *)REG_PORTE_DIR_CLR)                /* PORTE Port x GPIO Direction Clear Register */
-#define pREG_PORTE_INEN                  ((volatile uint32_t *)REG_PORTE_INEN)                   /* PORTE Port x GPIO Input Enable Register */
-#define pREG_PORTE_INEN_SET              ((volatile uint32_t *)REG_PORTE_INEN_SET)               /* PORTE Port x GPIO Input Enable Set Register */
-#define pREG_PORTE_INEN_CLR              ((volatile uint32_t *)REG_PORTE_INEN_CLR)               /* PORTE Port x GPIO Input Enable Clear Register */
-#define pREG_PORTE_MUX                   ((volatile uint32_t *)REG_PORTE_MUX)                    /* PORTE Port x Multiplexer Control Register */
-#define pREG_PORTE_DATA_TGL              ((volatile uint32_t *)REG_PORTE_DATA_TGL)               /* PORTE Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTE_POL                   ((volatile uint32_t *)REG_PORTE_POL)                    /* PORTE Port x GPIO Polarity Invert Register */
-#define pREG_PORTE_POL_SET               ((volatile uint32_t *)REG_PORTE_POL_SET)                /* PORTE Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTE_POL_CLR               ((volatile uint32_t *)REG_PORTE_POL_CLR)                /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTE_LOCK                  ((volatile uint32_t *)REG_PORTE_LOCK)                   /* PORTE Port x GPIO Lock Register */
-#define pREG_PORTE_REVID                 ((volatile uint32_t *)REG_PORTE_REVID)                  /* PORTE Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTF
-   ========================================================================= */
-#define pREG_PORTF_FER                   ((volatile uint32_t *)REG_PORTF_FER)                    /* PORTF Port x Function Enable Register */
-#define pREG_PORTF_FER_SET               ((volatile uint32_t *)REG_PORTF_FER_SET)                /* PORTF Port x Function Enable Set Register */
-#define pREG_PORTF_FER_CLR               ((volatile uint32_t *)REG_PORTF_FER_CLR)                /* PORTF Port x Function Enable Clear Register */
-#define pREG_PORTF_DATA                  ((volatile uint32_t *)REG_PORTF_DATA)                   /* PORTF Port x GPIO Data Register */
-#define pREG_PORTF_DATA_SET              ((volatile uint32_t *)REG_PORTF_DATA_SET)               /* PORTF Port x GPIO Data Set Register */
-#define pREG_PORTF_DATA_CLR              ((volatile uint32_t *)REG_PORTF_DATA_CLR)               /* PORTF Port x GPIO Data Clear Register */
-#define pREG_PORTF_DIR                   ((volatile uint32_t *)REG_PORTF_DIR)                    /* PORTF Port x GPIO Direction Register */
-#define pREG_PORTF_DIR_SET               ((volatile uint32_t *)REG_PORTF_DIR_SET)                /* PORTF Port x GPIO Direction Set Register */
-#define pREG_PORTF_DIR_CLR               ((volatile uint32_t *)REG_PORTF_DIR_CLR)                /* PORTF Port x GPIO Direction Clear Register */
-#define pREG_PORTF_INEN                  ((volatile uint32_t *)REG_PORTF_INEN)                   /* PORTF Port x GPIO Input Enable Register */
-#define pREG_PORTF_INEN_SET              ((volatile uint32_t *)REG_PORTF_INEN_SET)               /* PORTF Port x GPIO Input Enable Set Register */
-#define pREG_PORTF_INEN_CLR              ((volatile uint32_t *)REG_PORTF_INEN_CLR)               /* PORTF Port x GPIO Input Enable Clear Register */
-#define pREG_PORTF_MUX                   ((volatile uint32_t *)REG_PORTF_MUX)                    /* PORTF Port x Multiplexer Control Register */
-#define pREG_PORTF_DATA_TGL              ((volatile uint32_t *)REG_PORTF_DATA_TGL)               /* PORTF Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTF_POL                   ((volatile uint32_t *)REG_PORTF_POL)                    /* PORTF Port x GPIO Polarity Invert Register */
-#define pREG_PORTF_POL_SET               ((volatile uint32_t *)REG_PORTF_POL_SET)                /* PORTF Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTF_POL_CLR               ((volatile uint32_t *)REG_PORTF_POL_CLR)                /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTF_LOCK                  ((volatile uint32_t *)REG_PORTF_LOCK)                   /* PORTF Port x GPIO Lock Register */
-#define pREG_PORTF_REVID                 ((volatile uint32_t *)REG_PORTF_REVID)                  /* PORTF Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTG
-   ========================================================================= */
-#define pREG_PORTG_FER                   ((volatile uint32_t *)REG_PORTG_FER)                    /* PORTG Port x Function Enable Register */
-#define pREG_PORTG_FER_SET               ((volatile uint32_t *)REG_PORTG_FER_SET)                /* PORTG Port x Function Enable Set Register */
-#define pREG_PORTG_FER_CLR               ((volatile uint32_t *)REG_PORTG_FER_CLR)                /* PORTG Port x Function Enable Clear Register */
-#define pREG_PORTG_DATA                  ((volatile uint32_t *)REG_PORTG_DATA)                   /* PORTG Port x GPIO Data Register */
-#define pREG_PORTG_DATA_SET              ((volatile uint32_t *)REG_PORTG_DATA_SET)               /* PORTG Port x GPIO Data Set Register */
-#define pREG_PORTG_DATA_CLR              ((volatile uint32_t *)REG_PORTG_DATA_CLR)               /* PORTG Port x GPIO Data Clear Register */
-#define pREG_PORTG_DIR                   ((volatile uint32_t *)REG_PORTG_DIR)                    /* PORTG Port x GPIO Direction Register */
-#define pREG_PORTG_DIR_SET               ((volatile uint32_t *)REG_PORTG_DIR_SET)                /* PORTG Port x GPIO Direction Set Register */
-#define pREG_PORTG_DIR_CLR               ((volatile uint32_t *)REG_PORTG_DIR_CLR)                /* PORTG Port x GPIO Direction Clear Register */
-#define pREG_PORTG_INEN                  ((volatile uint32_t *)REG_PORTG_INEN)                   /* PORTG Port x GPIO Input Enable Register */
-#define pREG_PORTG_INEN_SET              ((volatile uint32_t *)REG_PORTG_INEN_SET)               /* PORTG Port x GPIO Input Enable Set Register */
-#define pREG_PORTG_INEN_CLR              ((volatile uint32_t *)REG_PORTG_INEN_CLR)               /* PORTG Port x GPIO Input Enable Clear Register */
-#define pREG_PORTG_MUX                   ((volatile uint32_t *)REG_PORTG_MUX)                    /* PORTG Port x Multiplexer Control Register */
-#define pREG_PORTG_DATA_TGL              ((volatile uint32_t *)REG_PORTG_DATA_TGL)               /* PORTG Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTG_POL                   ((volatile uint32_t *)REG_PORTG_POL)                    /* PORTG Port x GPIO Polarity Invert Register */
-#define pREG_PORTG_POL_SET               ((volatile uint32_t *)REG_PORTG_POL_SET)                /* PORTG Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTG_POL_CLR               ((volatile uint32_t *)REG_PORTG_POL_CLR)                /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTG_LOCK                  ((volatile uint32_t *)REG_PORTG_LOCK)                   /* PORTG Port x GPIO Lock Register */
-#define pREG_PORTG_REVID                 ((volatile uint32_t *)REG_PORTG_REVID)                  /* PORTG Port x GPIO Revision ID */
-
-
-/* =========================================================================
-       PADS0
-   ========================================================================= */
-#define pREG_PADS0_EMAC_PTP_CLKSEL       ((volatile uint32_t *)REG_PADS0_EMAC_PTP_CLKSEL)        /* PADS0 Clock Selection for EMAC and PTP */
-#define pREG_PADS0_TWI_VSEL              ((volatile uint32_t *)REG_PADS0_TWI_VSEL)               /* PADS0 TWI Voltage Selection */
-#define pREG_PADS0_PORTS_HYST            ((volatile uint32_t *)REG_PADS0_PORTS_HYST)             /* PADS0 Hysteresis Enable Register */
-
-
-/* =========================================================================
-       PINT0
-   ========================================================================= */
-#define pREG_PINT0_MSK_SET               ((volatile uint32_t *)REG_PINT0_MSK_SET)                /* PINT0 Pint Mask Set Register */
-#define pREG_PINT0_MSK_CLR               ((volatile uint32_t *)REG_PINT0_MSK_CLR)                /* PINT0 Pint Mask Clear Register */
-#define pREG_PINT0_REQ                   ((volatile uint32_t *)REG_PINT0_REQ)                    /* PINT0 Pint Request Register */
-#define pREG_PINT0_ASSIGN                ((volatile uint32_t *)REG_PINT0_ASSIGN)                 /* PINT0 Pint Assign Register */
-#define pREG_PINT0_EDGE_SET              ((volatile uint32_t *)REG_PINT0_EDGE_SET)               /* PINT0 Pint Edge Set Register */
-#define pREG_PINT0_EDGE_CLR              ((volatile uint32_t *)REG_PINT0_EDGE_CLR)               /* PINT0 Pint Edge Clear Register */
-#define pREG_PINT0_INV_SET               ((volatile uint32_t *)REG_PINT0_INV_SET)                /* PINT0 Pint Invert Set Register */
-#define pREG_PINT0_INV_CLR               ((volatile uint32_t *)REG_PINT0_INV_CLR)                /* PINT0 Pint Invert Clear Register */
-#define pREG_PINT0_PINSTATE              ((volatile uint32_t *)REG_PINT0_PINSTATE)               /* PINT0 Pint Pinstate Register */
-#define pREG_PINT0_LATCH                 ((volatile uint32_t *)REG_PINT0_LATCH)                  /* PINT0 Pint Latch Register */
-
-/* =========================================================================
-       PINT1
-   ========================================================================= */
-#define pREG_PINT1_MSK_SET               ((volatile uint32_t *)REG_PINT1_MSK_SET)                /* PINT1 Pint Mask Set Register */
-#define pREG_PINT1_MSK_CLR               ((volatile uint32_t *)REG_PINT1_MSK_CLR)                /* PINT1 Pint Mask Clear Register */
-#define pREG_PINT1_REQ                   ((volatile uint32_t *)REG_PINT1_REQ)                    /* PINT1 Pint Request Register */
-#define pREG_PINT1_ASSIGN                ((volatile uint32_t *)REG_PINT1_ASSIGN)                 /* PINT1 Pint Assign Register */
-#define pREG_PINT1_EDGE_SET              ((volatile uint32_t *)REG_PINT1_EDGE_SET)               /* PINT1 Pint Edge Set Register */
-#define pREG_PINT1_EDGE_CLR              ((volatile uint32_t *)REG_PINT1_EDGE_CLR)               /* PINT1 Pint Edge Clear Register */
-#define pREG_PINT1_INV_SET               ((volatile uint32_t *)REG_PINT1_INV_SET)                /* PINT1 Pint Invert Set Register */
-#define pREG_PINT1_INV_CLR               ((volatile uint32_t *)REG_PINT1_INV_CLR)                /* PINT1 Pint Invert Clear Register */
-#define pREG_PINT1_PINSTATE              ((volatile uint32_t *)REG_PINT1_PINSTATE)               /* PINT1 Pint Pinstate Register */
-#define pREG_PINT1_LATCH                 ((volatile uint32_t *)REG_PINT1_LATCH)                  /* PINT1 Pint Latch Register */
-
-/* =========================================================================
-       PINT2
-   ========================================================================= */
-#define pREG_PINT2_MSK_SET               ((volatile uint32_t *)REG_PINT2_MSK_SET)                /* PINT2 Pint Mask Set Register */
-#define pREG_PINT2_MSK_CLR               ((volatile uint32_t *)REG_PINT2_MSK_CLR)                /* PINT2 Pint Mask Clear Register */
-#define pREG_PINT2_REQ                   ((volatile uint32_t *)REG_PINT2_REQ)                    /* PINT2 Pint Request Register */
-#define pREG_PINT2_ASSIGN                ((volatile uint32_t *)REG_PINT2_ASSIGN)                 /* PINT2 Pint Assign Register */
-#define pREG_PINT2_EDGE_SET              ((volatile uint32_t *)REG_PINT2_EDGE_SET)               /* PINT2 Pint Edge Set Register */
-#define pREG_PINT2_EDGE_CLR              ((volatile uint32_t *)REG_PINT2_EDGE_CLR)               /* PINT2 Pint Edge Clear Register */
-#define pREG_PINT2_INV_SET               ((volatile uint32_t *)REG_PINT2_INV_SET)                /* PINT2 Pint Invert Set Register */
-#define pREG_PINT2_INV_CLR               ((volatile uint32_t *)REG_PINT2_INV_CLR)                /* PINT2 Pint Invert Clear Register */
-#define pREG_PINT2_PINSTATE              ((volatile uint32_t *)REG_PINT2_PINSTATE)               /* PINT2 Pint Pinstate Register */
-#define pREG_PINT2_LATCH                 ((volatile uint32_t *)REG_PINT2_LATCH)                  /* PINT2 Pint Latch Register */
-
-/* =========================================================================
-       PINT3
-   ========================================================================= */
-#define pREG_PINT3_MSK_SET               ((volatile uint32_t *)REG_PINT3_MSK_SET)                /* PINT3 Pint Mask Set Register */
-#define pREG_PINT3_MSK_CLR               ((volatile uint32_t *)REG_PINT3_MSK_CLR)                /* PINT3 Pint Mask Clear Register */
-#define pREG_PINT3_REQ                   ((volatile uint32_t *)REG_PINT3_REQ)                    /* PINT3 Pint Request Register */
-#define pREG_PINT3_ASSIGN                ((volatile uint32_t *)REG_PINT3_ASSIGN)                 /* PINT3 Pint Assign Register */
-#define pREG_PINT3_EDGE_SET              ((volatile uint32_t *)REG_PINT3_EDGE_SET)               /* PINT3 Pint Edge Set Register */
-#define pREG_PINT3_EDGE_CLR              ((volatile uint32_t *)REG_PINT3_EDGE_CLR)               /* PINT3 Pint Edge Clear Register */
-#define pREG_PINT3_INV_SET               ((volatile uint32_t *)REG_PINT3_INV_SET)                /* PINT3 Pint Invert Set Register */
-#define pREG_PINT3_INV_CLR               ((volatile uint32_t *)REG_PINT3_INV_CLR)                /* PINT3 Pint Invert Clear Register */
-#define pREG_PINT3_PINSTATE              ((volatile uint32_t *)REG_PINT3_PINSTATE)               /* PINT3 Pint Pinstate Register */
-#define pREG_PINT3_LATCH                 ((volatile uint32_t *)REG_PINT3_LATCH)                  /* PINT3 Pint Latch Register */
-
-/* =========================================================================
-       PINT4
-   ========================================================================= */
-#define pREG_PINT4_MSK_SET               ((volatile uint32_t *)REG_PINT4_MSK_SET)                /* PINT4 Pint Mask Set Register */
-#define pREG_PINT4_MSK_CLR               ((volatile uint32_t *)REG_PINT4_MSK_CLR)                /* PINT4 Pint Mask Clear Register */
-#define pREG_PINT4_REQ                   ((volatile uint32_t *)REG_PINT4_REQ)                    /* PINT4 Pint Request Register */
-#define pREG_PINT4_ASSIGN                ((volatile uint32_t *)REG_PINT4_ASSIGN)                 /* PINT4 Pint Assign Register */
-#define pREG_PINT4_EDGE_SET              ((volatile uint32_t *)REG_PINT4_EDGE_SET)               /* PINT4 Pint Edge Set Register */
-#define pREG_PINT4_EDGE_CLR              ((volatile uint32_t *)REG_PINT4_EDGE_CLR)               /* PINT4 Pint Edge Clear Register */
-#define pREG_PINT4_INV_SET               ((volatile uint32_t *)REG_PINT4_INV_SET)                /* PINT4 Pint Invert Set Register */
-#define pREG_PINT4_INV_CLR               ((volatile uint32_t *)REG_PINT4_INV_CLR)                /* PINT4 Pint Invert Clear Register */
-#define pREG_PINT4_PINSTATE              ((volatile uint32_t *)REG_PINT4_PINSTATE)               /* PINT4 Pint Pinstate Register */
-#define pREG_PINT4_LATCH                 ((volatile uint32_t *)REG_PINT4_LATCH)                  /* PINT4 Pint Latch Register */
-
-/* =========================================================================
-       PINT5
-   ========================================================================= */
-#define pREG_PINT5_MSK_SET               ((volatile uint32_t *)REG_PINT5_MSK_SET)                /* PINT5 Pint Mask Set Register */
-#define pREG_PINT5_MSK_CLR               ((volatile uint32_t *)REG_PINT5_MSK_CLR)                /* PINT5 Pint Mask Clear Register */
-#define pREG_PINT5_REQ                   ((volatile uint32_t *)REG_PINT5_REQ)                    /* PINT5 Pint Request Register */
-#define pREG_PINT5_ASSIGN                ((volatile uint32_t *)REG_PINT5_ASSIGN)                 /* PINT5 Pint Assign Register */
-#define pREG_PINT5_EDGE_SET              ((volatile uint32_t *)REG_PINT5_EDGE_SET)               /* PINT5 Pint Edge Set Register */
-#define pREG_PINT5_EDGE_CLR              ((volatile uint32_t *)REG_PINT5_EDGE_CLR)               /* PINT5 Pint Edge Clear Register */
-#define pREG_PINT5_INV_SET               ((volatile uint32_t *)REG_PINT5_INV_SET)                /* PINT5 Pint Invert Set Register */
-#define pREG_PINT5_INV_CLR               ((volatile uint32_t *)REG_PINT5_INV_CLR)                /* PINT5 Pint Invert Clear Register */
-#define pREG_PINT5_PINSTATE              ((volatile uint32_t *)REG_PINT5_PINSTATE)               /* PINT5 Pint Pinstate Register */
-#define pREG_PINT5_LATCH                 ((volatile uint32_t *)REG_PINT5_LATCH)                  /* PINT5 Pint Latch Register */
-
-
-/* =========================================================================
-       SMC0
-   ========================================================================= */
-#define pREG_SMC0_GCTL                   ((volatile uint32_t *)REG_SMC0_GCTL)                    /* SMC0 Grant Control Register */
-#define pREG_SMC0_GSTAT                  ((volatile uint32_t *)REG_SMC0_GSTAT)                   /* SMC0 Grant Status Register */
-#define pREG_SMC0_B0CTL                  ((volatile uint32_t *)REG_SMC0_B0CTL)                   /* SMC0 Bank 0 Control Register */
-#define pREG_SMC0_B0TIM                  ((volatile uint32_t *)REG_SMC0_B0TIM)                   /* SMC0 Bank 0 Timing Register */
-#define pREG_SMC0_B0ETIM                 ((volatile uint32_t *)REG_SMC0_B0ETIM)                  /* SMC0 Bank 0 Extended Timing Register */
-#define pREG_SMC0_B1CTL                  ((volatile uint32_t *)REG_SMC0_B1CTL)                   /* SMC0 Bank 1 Control Register */
-#define pREG_SMC0_B1TIM                  ((volatile uint32_t *)REG_SMC0_B1TIM)                   /* SMC0 Bank 1 Timing Register */
-#define pREG_SMC0_B1ETIM                 ((volatile uint32_t *)REG_SMC0_B1ETIM)                  /* SMC0 Bank 1 Extended Timing Register */
-#define pREG_SMC0_B2CTL                  ((volatile uint32_t *)REG_SMC0_B2CTL)                   /* SMC0 Bank 2 Control Register */
-#define pREG_SMC0_B2TIM                  ((volatile uint32_t *)REG_SMC0_B2TIM)                   /* SMC0 Bank 2 Timing Register */
-#define pREG_SMC0_B2ETIM                 ((volatile uint32_t *)REG_SMC0_B2ETIM)                  /* SMC0 Bank 2 Extended Timing Register */
-#define pREG_SMC0_B3CTL                  ((volatile uint32_t *)REG_SMC0_B3CTL)                   /* SMC0 Bank 3 Control Register */
-#define pREG_SMC0_B3TIM                  ((volatile uint32_t *)REG_SMC0_B3TIM)                   /* SMC0 Bank 3 Timing Register */
-#define pREG_SMC0_B3ETIM                 ((volatile uint32_t *)REG_SMC0_B3ETIM)                  /* SMC0 Bank 3 Extended Timing Register */
-
-
-/* =========================================================================
-       WDOG0
-   ========================================================================= */
-#define pREG_WDOG0_CTL                   ((volatile uint32_t *)REG_WDOG0_CTL)                    /* WDOG0 Control Register */
-#define pREG_WDOG0_CNT                   ((volatile uint32_t *)REG_WDOG0_CNT)                    /* WDOG0 Count Register */
-#define pREG_WDOG0_STAT                  ((volatile uint32_t *)REG_WDOG0_STAT)                   /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================================================================
-       WDOG1
-   ========================================================================= */
-#define pREG_WDOG1_CTL                   ((volatile uint32_t *)REG_WDOG1_CTL)                    /* WDOG1 Control Register */
-#define pREG_WDOG1_CNT                   ((volatile uint32_t *)REG_WDOG1_CNT)                    /* WDOG1 Count Register */
-#define pREG_WDOG1_STAT                  ((volatile uint32_t *)REG_WDOG1_STAT)                   /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================================================================
-       EPPI0
-   ========================================================================= */
-#define pREG_EPPI0_STAT                  ((volatile uint32_t *)REG_EPPI0_STAT)                   /* EPPI0 Status Register */
-#define pREG_EPPI0_HCNT                  ((volatile uint32_t *)REG_EPPI0_HCNT)                   /* EPPI0 Horizontal Transfer Count Register */
-#define pREG_EPPI0_HDLY                  ((volatile uint32_t *)REG_EPPI0_HDLY)                   /* EPPI0 Horizontal Delay Count Register */
-#define pREG_EPPI0_VCNT                  ((volatile uint32_t *)REG_EPPI0_VCNT)                   /* EPPI0 Vertical Transfer Count Register */
-#define pREG_EPPI0_VDLY                  ((volatile uint32_t *)REG_EPPI0_VDLY)                   /* EPPI0 Vertical Delay Count Register */
-#define pREG_EPPI0_FRAME                 ((volatile uint32_t *)REG_EPPI0_FRAME)                  /* EPPI0 Lines Per Frame Register */
-#define pREG_EPPI0_LINE                  ((volatile uint32_t *)REG_EPPI0_LINE)                   /* EPPI0 Samples Per Line Register */
-#define pREG_EPPI0_CLKDIV                ((volatile uint32_t *)REG_EPPI0_CLKDIV)                 /* EPPI0 Clock Divide Register */
-#define pREG_EPPI0_CTL                   ((volatile uint32_t *)REG_EPPI0_CTL)                    /* EPPI0 Control Register */
-#define pREG_EPPI0_FS1_WLHB              ((volatile uint32_t *)REG_EPPI0_FS1_WLHB)               /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI0_FS1_PASPL             ((volatile uint32_t *)REG_EPPI0_FS1_PASPL)              /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI0_FS2_WLVB              ((volatile uint32_t *)REG_EPPI0_FS2_WLVB)               /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI0_FS2_PALPF             ((volatile uint32_t *)REG_EPPI0_FS2_PALPF)              /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI0_IMSK                  ((volatile uint32_t *)REG_EPPI0_IMSK)                   /* EPPI0 Interrupt Mask Register */
-#define pREG_EPPI0_ODDCLIP               ((volatile uint32_t *)REG_EPPI0_ODDCLIP)                /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI0_EVENCLIP              ((volatile uint32_t *)REG_EPPI0_EVENCLIP)               /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI0_FS1_DLY               ((volatile uint32_t *)REG_EPPI0_FS1_DLY)                /* EPPI0 Frame Sync 1 Delay Value */
-#define pREG_EPPI0_FS2_DLY               ((volatile uint32_t *)REG_EPPI0_FS2_DLY)                /* EPPI0 Frame Sync 2 Delay Value */
-#define pREG_EPPI0_CTL2                  ((volatile uint32_t *)REG_EPPI0_CTL2)                   /* EPPI0 Control Register 2 */
-
-/* =========================================================================
-       EPPI1
-   ========================================================================= */
-#define pREG_EPPI1_STAT                  ((volatile uint32_t *)REG_EPPI1_STAT)                   /* EPPI1 Status Register */
-#define pREG_EPPI1_HCNT                  ((volatile uint32_t *)REG_EPPI1_HCNT)                   /* EPPI1 Horizontal Transfer Count Register */
-#define pREG_EPPI1_HDLY                  ((volatile uint32_t *)REG_EPPI1_HDLY)                   /* EPPI1 Horizontal Delay Count Register */
-#define pREG_EPPI1_VCNT                  ((volatile uint32_t *)REG_EPPI1_VCNT)                   /* EPPI1 Vertical Transfer Count Register */
-#define pREG_EPPI1_VDLY                  ((volatile uint32_t *)REG_EPPI1_VDLY)                   /* EPPI1 Vertical Delay Count Register */
-#define pREG_EPPI1_FRAME                 ((volatile uint32_t *)REG_EPPI1_FRAME)                  /* EPPI1 Lines Per Frame Register */
-#define pREG_EPPI1_LINE                  ((volatile uint32_t *)REG_EPPI1_LINE)                   /* EPPI1 Samples Per Line Register */
-#define pREG_EPPI1_CLKDIV                ((volatile uint32_t *)REG_EPPI1_CLKDIV)                 /* EPPI1 Clock Divide Register */
-#define pREG_EPPI1_CTL                   ((volatile uint32_t *)REG_EPPI1_CTL)                    /* EPPI1 Control Register */
-#define pREG_EPPI1_FS1_WLHB              ((volatile uint32_t *)REG_EPPI1_FS1_WLHB)               /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI1_FS1_PASPL             ((volatile uint32_t *)REG_EPPI1_FS1_PASPL)              /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI1_FS2_WLVB              ((volatile uint32_t *)REG_EPPI1_FS2_WLVB)               /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI1_FS2_PALPF             ((volatile uint32_t *)REG_EPPI1_FS2_PALPF)              /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI1_IMSK                  ((volatile uint32_t *)REG_EPPI1_IMSK)                   /* EPPI1 Interrupt Mask Register */
-#define pREG_EPPI1_ODDCLIP               ((volatile uint32_t *)REG_EPPI1_ODDCLIP)                /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI1_EVENCLIP              ((volatile uint32_t *)REG_EPPI1_EVENCLIP)               /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI1_FS1_DLY               ((volatile uint32_t *)REG_EPPI1_FS1_DLY)                /* EPPI1 Frame Sync 1 Delay Value */
-#define pREG_EPPI1_FS2_DLY               ((volatile uint32_t *)REG_EPPI1_FS2_DLY)                /* EPPI1 Frame Sync 2 Delay Value */
-#define pREG_EPPI1_CTL2                  ((volatile uint32_t *)REG_EPPI1_CTL2)                   /* EPPI1 Control Register 2 */
-
-/* =========================================================================
-       EPPI2
-   ========================================================================= */
-#define pREG_EPPI2_STAT                  ((volatile uint32_t *)REG_EPPI2_STAT)                   /* EPPI2 Status Register */
-#define pREG_EPPI2_HCNT                  ((volatile uint32_t *)REG_EPPI2_HCNT)                   /* EPPI2 Horizontal Transfer Count Register */
-#define pREG_EPPI2_HDLY                  ((volatile uint32_t *)REG_EPPI2_HDLY)                   /* EPPI2 Horizontal Delay Count Register */
-#define pREG_EPPI2_VCNT                  ((volatile uint32_t *)REG_EPPI2_VCNT)                   /* EPPI2 Vertical Transfer Count Register */
-#define pREG_EPPI2_VDLY                  ((volatile uint32_t *)REG_EPPI2_VDLY)                   /* EPPI2 Vertical Delay Count Register */
-#define pREG_EPPI2_FRAME                 ((volatile uint32_t *)REG_EPPI2_FRAME)                  /* EPPI2 Lines Per Frame Register */
-#define pREG_EPPI2_LINE                  ((volatile uint32_t *)REG_EPPI2_LINE)                   /* EPPI2 Samples Per Line Register */
-#define pREG_EPPI2_CLKDIV                ((volatile uint32_t *)REG_EPPI2_CLKDIV)                 /* EPPI2 Clock Divide Register */
-#define pREG_EPPI2_CTL                   ((volatile uint32_t *)REG_EPPI2_CTL)                    /* EPPI2 Control Register */
-#define pREG_EPPI2_FS1_WLHB              ((volatile uint32_t *)REG_EPPI2_FS1_WLHB)               /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI2_FS1_PASPL             ((volatile uint32_t *)REG_EPPI2_FS1_PASPL)              /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI2_FS2_WLVB              ((volatile uint32_t *)REG_EPPI2_FS2_WLVB)               /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI2_FS2_PALPF             ((volatile uint32_t *)REG_EPPI2_FS2_PALPF)              /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI2_IMSK                  ((volatile uint32_t *)REG_EPPI2_IMSK)                   /* EPPI2 Interrupt Mask Register */
-#define pREG_EPPI2_ODDCLIP               ((volatile uint32_t *)REG_EPPI2_ODDCLIP)                /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI2_EVENCLIP              ((volatile uint32_t *)REG_EPPI2_EVENCLIP)               /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI2_FS1_DLY               ((volatile uint32_t *)REG_EPPI2_FS1_DLY)                /* EPPI2 Frame Sync 1 Delay Value */
-#define pREG_EPPI2_FS2_DLY               ((volatile uint32_t *)REG_EPPI2_FS2_DLY)                /* EPPI2 Frame Sync 2 Delay Value */
-#define pREG_EPPI2_CTL2                  ((volatile uint32_t *)REG_EPPI2_CTL2)                   /* EPPI2 Control Register 2 */
-
-
-/* =========================================================================
-       PIXC0
-   ========================================================================= */
-#define pREG_PIXC0_CTL                   ((volatile uint32_t *)REG_PIXC0_CTL)                    /* PIXC0 Control Register */
-#define pREG_PIXC0_PPL                   ((volatile uint16_t *)REG_PIXC0_PPL)                    /* PIXC0 Pixels Per Line Register */
-#define pREG_PIXC0_LPF                   ((volatile uint16_t *)REG_PIXC0_LPF)                    /* PIXC0 Line Per Frame Register */
-#define pREG_PIXC0_HSTART_A              ((volatile uint16_t *)REG_PIXC0_HSTART_A)               /* PIXC0 Overlay A Horizontal Start Register */
-#define pREG_PIXC0_HEND_A                ((volatile uint16_t *)REG_PIXC0_HEND_A)                 /* PIXC0 Overlay A Horizontal End Register */
-#define pREG_PIXC0_VSTART_A              ((volatile uint16_t *)REG_PIXC0_VSTART_A)               /* PIXC0 Overlay A Vertical Start Register */
-#define pREG_PIXC0_VEND_A                ((volatile uint16_t *)REG_PIXC0_VEND_A)                 /* PIXC0 Overlay A Vertical End Register */
-#define pREG_PIXC0_TRANSP_A              ((volatile uint16_t *)REG_PIXC0_TRANSP_A)               /* PIXC0 Overlay A Transparency Ratio Register */
-#define pREG_PIXC0_HSTART_B              ((volatile uint16_t *)REG_PIXC0_HSTART_B)               /* PIXC0 Overlay B Horizontal Start Register */
-#define pREG_PIXC0_HEND_B                ((volatile uint16_t *)REG_PIXC0_HEND_B)                 /* PIXC0 Overlay B Horizontal End Register */
-#define pREG_PIXC0_VSTART_B              ((volatile uint16_t *)REG_PIXC0_VSTART_B)               /* PIXC0 Overlay B Vertical Start Register */
-#define pREG_PIXC0_VEND_B                ((volatile uint16_t *)REG_PIXC0_VEND_B)                 /* PIXC0 Overlay B Vertical End Register */
-#define pREG_PIXC0_TRANSP_B              ((volatile uint16_t *)REG_PIXC0_TRANSP_B)               /* PIXC0 Overlay B Transparency Ratio Register */
-#define pREG_PIXC0_IRQSTAT               ((volatile uint16_t *)REG_PIXC0_IRQSTAT)                /* PIXC0 Interrupt Status Register */
-#define pREG_PIXC0_CONRY                 ((volatile uint32_t *)REG_PIXC0_CONRY)                  /* PIXC0 RY Conversion Component Register */
-#define pREG_PIXC0_CONGU                 ((volatile uint32_t *)REG_PIXC0_CONGU)                  /* PIXC0 GU Conversion Component Register */
-#define pREG_PIXC0_CONBV                 ((volatile uint32_t *)REG_PIXC0_CONBV)                  /* PIXC0 BV Conversion Component Register */
-#define pREG_PIXC0_CCBIAS                ((volatile uint32_t *)REG_PIXC0_CCBIAS)                 /* PIXC0 Conversion Bias Register */
-#define pREG_PIXC0_TC                    ((volatile uint32_t *)REG_PIXC0_TC)                     /* PIXC0 Transparency Color Register */
-#define pREG_PIXC0_REVID                 ((volatile uint32_t *)REG_PIXC0_REVID)                  /* PIXC0 Revision Id */
-
-
-/* =========================================================================
-       PVP0
-   ========================================================================= */
-#define pREG_PVP0_REVID                  ((volatile uint32_t *)REG_PVP0_REVID)                   /* PVP0 Revision ID */
-#define pREG_PVP0_CTL                    ((volatile uint32_t *)REG_PVP0_CTL)                     /* PVP0 Control */
-#define pREG_PVP0_IMSK0                  ((volatile uint32_t *)REG_PVP0_IMSK0)                   /* PVP0 Interrupt Mask n */
-#define pREG_PVP0_IMSK1                  ((volatile uint32_t *)REG_PVP0_IMSK1)                   /* PVP0 Interrupt Mask n */
-#define pREG_PVP0_STAT                   ((volatile uint32_t *)REG_PVP0_STAT)                    /* PVP0 Status */
-#define pREG_PVP0_ILAT                   ((volatile uint32_t *)REG_PVP0_ILAT)                    /* PVP0 Interrupt Latch Status n */
-#define pREG_PVP0_IREQ0                  ((volatile uint32_t *)REG_PVP0_IREQ0)                   /* PVP0 Interrupt Request n */
-#define pREG_PVP0_IREQ1                  ((volatile uint32_t *)REG_PVP0_IREQ1)                   /* PVP0 Interrupt Request n */
-#define pREG_PVP0_OPF0_CFG               ((volatile uint32_t *)REG_PVP0_OPF0_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF1_CFG               ((volatile uint32_t *)REG_PVP0_OPF1_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF2_CFG               ((volatile uint32_t *)REG_PVP0_OPF2_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF0_CTL               ((volatile uint32_t *)REG_PVP0_OPF0_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF1_CTL               ((volatile uint32_t *)REG_PVP0_OPF1_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF2_CTL               ((volatile uint32_t *)REG_PVP0_OPF2_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF3_CFG               ((volatile uint32_t *)REG_PVP0_OPF3_CFG)                /* PVP0 OPF3 (Memory Pipe) Configuration */
-#define pREG_PVP0_OPF3_CTL               ((volatile uint32_t *)REG_PVP0_OPF3_CTL)                /* PVP0 OPF3 (Memory Pipe) Control */
-#define pREG_PVP0_PEC_CFG                ((volatile uint32_t *)REG_PVP0_PEC_CFG)                 /* PVP0 PEC Configuration */
-#define pREG_PVP0_PEC_CTL                ((volatile uint32_t *)REG_PVP0_PEC_CTL)                 /* PVP0 PEC Control */
-#define pREG_PVP0_PEC_D1TH0              ((volatile uint32_t *)REG_PVP0_PEC_D1TH0)               /* PVP0 PEC Lower Hysteresis Threshold */
-#define pREG_PVP0_PEC_D1TH1              ((volatile uint32_t *)REG_PVP0_PEC_D1TH1)               /* PVP0 PEC Upper Hysteresis Threshold */
-#define pREG_PVP0_PEC_D2TH0              ((volatile uint32_t *)REG_PVP0_PEC_D2TH0)               /* PVP0 PEC Weak Zero Crossing Threshold */
-#define pREG_PVP0_PEC_D2TH1              ((volatile uint32_t *)REG_PVP0_PEC_D2TH1)               /* PVP0 PEC Strong Zero Crossing Threshold */
-#define pREG_PVP0_IIM0_CFG               ((volatile uint32_t *)REG_PVP0_IIM0_CFG)                /* PVP0 IIMn Configuration */
-#define pREG_PVP0_IIM1_CFG               ((volatile uint32_t *)REG_PVP0_IIM1_CFG)                /* PVP0 IIMn Configuration */
-#define pREG_PVP0_IIM0_CTL               ((volatile uint32_t *)REG_PVP0_IIM0_CTL)                /* PVP0 IIMn Control */
-#define pREG_PVP0_IIM1_CTL               ((volatile uint32_t *)REG_PVP0_IIM1_CTL)                /* PVP0 IIMn Control */
-#define pREG_PVP0_IIM0_SCALE             ((volatile uint32_t *)REG_PVP0_IIM0_SCALE)              /* PVP0 IIMn Scaling Values */
-#define pREG_PVP0_IIM1_SCALE             ((volatile uint32_t *)REG_PVP0_IIM1_SCALE)              /* PVP0 IIMn Scaling Values */
-#define pREG_PVP0_IIM0_SOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM0_SOVF_STAT)          /* PVP0 IIMn Signed Overflow Status */
-#define pREG_PVP0_IIM1_SOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM1_SOVF_STAT)          /* PVP0 IIMn Signed Overflow Status */
-#define pREG_PVP0_IIM0_UOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM0_UOVF_STAT)          /* PVP0 IIMn Unsigned Overflow Status */
-#define pREG_PVP0_IIM1_UOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM1_UOVF_STAT)          /* PVP0 IIMn Unsigned Overflow Status */
-#define pREG_PVP0_ACU_CFG                ((volatile uint32_t *)REG_PVP0_ACU_CFG)                 /* PVP0 ACU Configuration */
-#define pREG_PVP0_ACU_CTL                ((volatile uint32_t *)REG_PVP0_ACU_CTL)                 /* PVP0 ACU Control */
-#define pREG_PVP0_ACU_OFFSET             ((volatile uint32_t *)REG_PVP0_ACU_OFFSET)              /* PVP0 ACU SUM Constant */
-#define pREG_PVP0_ACU_FACTOR             ((volatile uint32_t *)REG_PVP0_ACU_FACTOR)              /* PVP0 ACU PROD Constant */
-#define pREG_PVP0_ACU_SHIFT              ((volatile uint32_t *)REG_PVP0_ACU_SHIFT)               /* PVP0 ACU Shift Constant */
-#define pREG_PVP0_ACU_MIN                ((volatile uint32_t *)REG_PVP0_ACU_MIN)                 /* PVP0 ACU Lower Sat Threshold Min */
-#define pREG_PVP0_ACU_MAX                ((volatile uint32_t *)REG_PVP0_ACU_MAX)                 /* PVP0 ACU Upper Sat Threshold Max */
-#define pREG_PVP0_UDS_CFG                ((volatile uint32_t *)REG_PVP0_UDS_CFG)                 /* PVP0 UDS Configuration */
-#define pREG_PVP0_UDS_CTL                ((volatile uint32_t *)REG_PVP0_UDS_CTL)                 /* PVP0 UDS Control */
-#define pREG_PVP0_UDS_OHCNT              ((volatile uint32_t *)REG_PVP0_UDS_OHCNT)               /* PVP0 UDS Output HCNT */
-#define pREG_PVP0_UDS_OVCNT              ((volatile uint32_t *)REG_PVP0_UDS_OVCNT)               /* PVP0 UDS Output VCNT */
-#define pREG_PVP0_UDS_HAVG               ((volatile uint32_t *)REG_PVP0_UDS_HAVG)                /* PVP0 UDS HAVG */
-#define pREG_PVP0_UDS_VAVG               ((volatile uint32_t *)REG_PVP0_UDS_VAVG)                /* PVP0 UDS VAVG */
-#define pREG_PVP0_IPF0_CFG               ((volatile uint32_t *)REG_PVP0_IPF0_CFG)                /* PVP0 IPF0 (Camera Pipe) Configuration */
-#define pREG_PVP0_IPF0_PIPECTL           ((volatile uint32_t *)REG_PVP0_IPF0_PIPECTL)            /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define pREG_PVP0_IPF1_PIPECTL           ((volatile uint32_t *)REG_PVP0_IPF1_PIPECTL)            /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define pREG_PVP0_IPF0_CTL               ((volatile uint32_t *)REG_PVP0_IPF0_CTL)                /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define pREG_PVP0_IPF1_CTL               ((volatile uint32_t *)REG_PVP0_IPF1_CTL)                /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define pREG_PVP0_IPF0_TAG               ((volatile uint32_t *)REG_PVP0_IPF0_TAG)                /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define pREG_PVP0_IPF1_TAG               ((volatile uint32_t *)REG_PVP0_IPF1_TAG)                /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define pREG_PVP0_IPF0_FCNT              ((volatile uint32_t *)REG_PVP0_IPF0_FCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define pREG_PVP0_IPF1_FCNT              ((volatile uint32_t *)REG_PVP0_IPF1_FCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define pREG_PVP0_IPF0_HCNT              ((volatile uint32_t *)REG_PVP0_IPF0_HCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define pREG_PVP0_IPF1_HCNT              ((volatile uint32_t *)REG_PVP0_IPF1_HCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define pREG_PVP0_IPF0_VCNT              ((volatile uint32_t *)REG_PVP0_IPF0_VCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define pREG_PVP0_IPF1_VCNT              ((volatile uint32_t *)REG_PVP0_IPF1_VCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define pREG_PVP0_IPF0_HPOS              ((volatile uint32_t *)REG_PVP0_IPF0_HPOS)               /* PVP0 IPF0 (Camera Pipe) Horizontal Position */
-#define pREG_PVP0_IPF0_VPOS              ((volatile uint32_t *)REG_PVP0_IPF0_VPOS)               /* PVP0 IPF0 (Camera Pipe) Vertical Position */
-#define pREG_PVP0_IPF0_TAG_STAT          ((volatile uint32_t *)REG_PVP0_IPF0_TAG_STAT)           /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define pREG_PVP0_IPF1_TAG_STAT          ((volatile uint32_t *)REG_PVP0_IPF1_TAG_STAT)           /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define pREG_PVP0_IPF1_CFG               ((volatile uint32_t *)REG_PVP0_IPF1_CFG)                /* PVP0 IPF1 (Memory Pipe) Configuration */
-#define pREG_PVP0_CNV0_CFG               ((volatile uint32_t *)REG_PVP0_CNV0_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV1_CFG               ((volatile uint32_t *)REG_PVP0_CNV1_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV2_CFG               ((volatile uint32_t *)REG_PVP0_CNV2_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV3_CFG               ((volatile uint32_t *)REG_PVP0_CNV3_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV0_CTL               ((volatile uint32_t *)REG_PVP0_CNV0_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV1_CTL               ((volatile uint32_t *)REG_PVP0_CNV1_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV2_CTL               ((volatile uint32_t *)REG_PVP0_CNV2_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV3_CTL               ((volatile uint32_t *)REG_PVP0_CNV3_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV0_C00C01            ((volatile uint32_t *)REG_PVP0_CNV0_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV1_C00C01            ((volatile uint32_t *)REG_PVP0_CNV1_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV2_C00C01            ((volatile uint32_t *)REG_PVP0_CNV2_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV3_C00C01            ((volatile uint32_t *)REG_PVP0_CNV3_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV0_C02C03            ((volatile uint32_t *)REG_PVP0_CNV0_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV1_C02C03            ((volatile uint32_t *)REG_PVP0_CNV1_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV2_C02C03            ((volatile uint32_t *)REG_PVP0_CNV2_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV3_C02C03            ((volatile uint32_t *)REG_PVP0_CNV3_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV0_C04               ((volatile uint32_t *)REG_PVP0_CNV0_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV1_C04               ((volatile uint32_t *)REG_PVP0_CNV1_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV2_C04               ((volatile uint32_t *)REG_PVP0_CNV2_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV3_C04               ((volatile uint32_t *)REG_PVP0_CNV3_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV0_C10C11            ((volatile uint32_t *)REG_PVP0_CNV0_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV1_C10C11            ((volatile uint32_t *)REG_PVP0_CNV1_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV2_C10C11            ((volatile uint32_t *)REG_PVP0_CNV2_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV3_C10C11            ((volatile uint32_t *)REG_PVP0_CNV3_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV0_C12C13            ((volatile uint32_t *)REG_PVP0_CNV0_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV1_C12C13            ((volatile uint32_t *)REG_PVP0_CNV1_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV2_C12C13            ((volatile uint32_t *)REG_PVP0_CNV2_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV3_C12C13            ((volatile uint32_t *)REG_PVP0_CNV3_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV0_C14               ((volatile uint32_t *)REG_PVP0_CNV0_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV1_C14               ((volatile uint32_t *)REG_PVP0_CNV1_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV2_C14               ((volatile uint32_t *)REG_PVP0_CNV2_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV3_C14               ((volatile uint32_t *)REG_PVP0_CNV3_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV0_C20C21            ((volatile uint32_t *)REG_PVP0_CNV0_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV1_C20C21            ((volatile uint32_t *)REG_PVP0_CNV1_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV2_C20C21            ((volatile uint32_t *)REG_PVP0_CNV2_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV3_C20C21            ((volatile uint32_t *)REG_PVP0_CNV3_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV0_C22C23            ((volatile uint32_t *)REG_PVP0_CNV0_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV1_C22C23            ((volatile uint32_t *)REG_PVP0_CNV1_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV2_C22C23            ((volatile uint32_t *)REG_PVP0_CNV2_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV3_C22C23            ((volatile uint32_t *)REG_PVP0_CNV3_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV0_C24               ((volatile uint32_t *)REG_PVP0_CNV0_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV1_C24               ((volatile uint32_t *)REG_PVP0_CNV1_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV2_C24               ((volatile uint32_t *)REG_PVP0_CNV2_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV3_C24               ((volatile uint32_t *)REG_PVP0_CNV3_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV0_C30C31            ((volatile uint32_t *)REG_PVP0_CNV0_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV1_C30C31            ((volatile uint32_t *)REG_PVP0_CNV1_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV2_C30C31            ((volatile uint32_t *)REG_PVP0_CNV2_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV3_C30C31            ((volatile uint32_t *)REG_PVP0_CNV3_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV0_C32C33            ((volatile uint32_t *)REG_PVP0_CNV0_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV1_C32C33            ((volatile uint32_t *)REG_PVP0_CNV1_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV2_C32C33            ((volatile uint32_t *)REG_PVP0_CNV2_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV3_C32C33            ((volatile uint32_t *)REG_PVP0_CNV3_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV0_C34               ((volatile uint32_t *)REG_PVP0_CNV0_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV1_C34               ((volatile uint32_t *)REG_PVP0_CNV1_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV2_C34               ((volatile uint32_t *)REG_PVP0_CNV2_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV3_C34               ((volatile uint32_t *)REG_PVP0_CNV3_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV0_C40C41            ((volatile uint32_t *)REG_PVP0_CNV0_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV1_C40C41            ((volatile uint32_t *)REG_PVP0_CNV1_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV2_C40C41            ((volatile uint32_t *)REG_PVP0_CNV2_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV3_C40C41            ((volatile uint32_t *)REG_PVP0_CNV3_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV0_C42C43            ((volatile uint32_t *)REG_PVP0_CNV0_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV1_C42C43            ((volatile uint32_t *)REG_PVP0_CNV1_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV2_C42C43            ((volatile uint32_t *)REG_PVP0_CNV2_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV3_C42C43            ((volatile uint32_t *)REG_PVP0_CNV3_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV0_C44               ((volatile uint32_t *)REG_PVP0_CNV0_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV1_C44               ((volatile uint32_t *)REG_PVP0_CNV1_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV2_C44               ((volatile uint32_t *)REG_PVP0_CNV2_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV3_C44               ((volatile uint32_t *)REG_PVP0_CNV3_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV0_SCALE             ((volatile uint32_t *)REG_PVP0_CNV0_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV1_SCALE             ((volatile uint32_t *)REG_PVP0_CNV1_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV2_SCALE             ((volatile uint32_t *)REG_PVP0_CNV2_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV3_SCALE             ((volatile uint32_t *)REG_PVP0_CNV3_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_THC0_CFG               ((volatile uint32_t *)REG_PVP0_THC0_CFG)                /* PVP0 THCn Configuration */
-#define pREG_PVP0_THC1_CFG               ((volatile uint32_t *)REG_PVP0_THC1_CFG)                /* PVP0 THCn Configuration */
-#define pREG_PVP0_THC0_CTL               ((volatile uint32_t *)REG_PVP0_THC0_CTL)                /* PVP0 THCn Control */
-#define pREG_PVP0_THC1_CTL               ((volatile uint32_t *)REG_PVP0_THC1_CTL)                /* PVP0 THCn Control */
-#define pREG_PVP0_THC0_HFCNT             ((volatile uint32_t *)REG_PVP0_THC0_HFCNT)              /* PVP0 THCn Histogram Frame Count */
-#define pREG_PVP0_THC1_HFCNT             ((volatile uint32_t *)REG_PVP0_THC1_HFCNT)              /* PVP0 THCn Histogram Frame Count */
-#define pREG_PVP0_THC0_RMAXREP           ((volatile uint32_t *)REG_PVP0_THC0_RMAXREP)            /* PVP0 THCn Max RLE Reports */
-#define pREG_PVP0_THC1_RMAXREP           ((volatile uint32_t *)REG_PVP0_THC1_RMAXREP)            /* PVP0 THCn Max RLE Reports */
-#define pREG_PVP0_THC0_CMINVAL           ((volatile  int32_t *)REG_PVP0_THC0_CMINVAL)            /* PVP0 THCn Min Clip Value */
-#define pREG_PVP0_THC1_CMINVAL           ((volatile  int32_t *)REG_PVP0_THC1_CMINVAL)            /* PVP0 THCn Min Clip Value */
-#define pREG_PVP0_THC0_CMINTH            ((volatile  int32_t *)REG_PVP0_THC0_CMINTH)             /* PVP0 THCn Clip Min Threshold */
-#define pREG_PVP0_THC1_CMINTH            ((volatile  int32_t *)REG_PVP0_THC1_CMINTH)             /* PVP0 THCn Clip Min Threshold */
-#define pREG_PVP0_THC0_CMAXTH            ((volatile  int32_t *)REG_PVP0_THC0_CMAXTH)             /* PVP0 THCn Clip Max Threshold */
-#define pREG_PVP0_THC1_CMAXTH            ((volatile  int32_t *)REG_PVP0_THC1_CMAXTH)             /* PVP0 THCn Clip Max Threshold */
-#define pREG_PVP0_THC0_CMAXVAL           ((volatile  int32_t *)REG_PVP0_THC0_CMAXVAL)            /* PVP0 THCn Max Clip Value */
-#define pREG_PVP0_THC1_CMAXVAL           ((volatile  int32_t *)REG_PVP0_THC1_CMAXVAL)            /* PVP0 THCn Max Clip Value */
-#define pREG_PVP0_THC0_TH0               ((volatile  int32_t *)REG_PVP0_THC0_TH0)                /* PVP0 THCn Threshold Value 0 */
-#define pREG_PVP0_THC1_TH0               ((volatile  int32_t *)REG_PVP0_THC1_TH0)                /* PVP0 THCn Threshold Value 0 */
-#define pREG_PVP0_THC0_TH1               ((volatile  int32_t *)REG_PVP0_THC0_TH1)                /* PVP0 THCn Threshold Value 1 */
-#define pREG_PVP0_THC1_TH1               ((volatile  int32_t *)REG_PVP0_THC1_TH1)                /* PVP0 THCn Threshold Value 1 */
-#define pREG_PVP0_THC0_TH2               ((volatile  int32_t *)REG_PVP0_THC0_TH2)                /* PVP0 THCn Threshold Value 2 */
-#define pREG_PVP0_THC1_TH2               ((volatile  int32_t *)REG_PVP0_THC1_TH2)                /* PVP0 THCn Threshold Value 2 */
-#define pREG_PVP0_THC0_TH3               ((volatile  int32_t *)REG_PVP0_THC0_TH3)                /* PVP0 THCn Threshold Value 3 */
-#define pREG_PVP0_THC1_TH3               ((volatile  int32_t *)REG_PVP0_THC1_TH3)                /* PVP0 THCn Threshold Value 3 */
-#define pREG_PVP0_THC0_TH4               ((volatile  int32_t *)REG_PVP0_THC0_TH4)                /* PVP0 THCn Threshold Value 4 */
-#define pREG_PVP0_THC1_TH4               ((volatile  int32_t *)REG_PVP0_THC1_TH4)                /* PVP0 THCn Threshold Value 4 */
-#define pREG_PVP0_THC0_TH5               ((volatile  int32_t *)REG_PVP0_THC0_TH5)                /* PVP0 THCn Threshold Value 5 */
-#define pREG_PVP0_THC1_TH5               ((volatile  int32_t *)REG_PVP0_THC1_TH5)                /* PVP0 THCn Threshold Value 5 */
-#define pREG_PVP0_THC0_TH6               ((volatile  int32_t *)REG_PVP0_THC0_TH6)                /* PVP0 THCn Threshold Value 6 */
-#define pREG_PVP0_THC1_TH6               ((volatile  int32_t *)REG_PVP0_THC1_TH6)                /* PVP0 THCn Threshold Value 6 */
-#define pREG_PVP0_THC0_TH7               ((volatile  int32_t *)REG_PVP0_THC0_TH7)                /* PVP0 THCn Threshold Value 7 */
-#define pREG_PVP0_THC1_TH7               ((volatile  int32_t *)REG_PVP0_THC1_TH7)                /* PVP0 THCn Threshold Value 7 */
-#define pREG_PVP0_THC0_TH8               ((volatile  int32_t *)REG_PVP0_THC0_TH8)                /* PVP0 THCn Threshold Value 8 */
-#define pREG_PVP0_THC1_TH8               ((volatile  int32_t *)REG_PVP0_THC1_TH8)                /* PVP0 THCn Threshold Value 8 */
-#define pREG_PVP0_THC0_TH9               ((volatile  int32_t *)REG_PVP0_THC0_TH9)                /* PVP0 THCn Threshold Value 9 */
-#define pREG_PVP0_THC1_TH9               ((volatile  int32_t *)REG_PVP0_THC1_TH9)                /* PVP0 THCn Threshold Value 9 */
-#define pREG_PVP0_THC0_TH10              ((volatile  int32_t *)REG_PVP0_THC0_TH10)               /* PVP0 THCn Threshold Value 10 */
-#define pREG_PVP0_THC1_TH10              ((volatile  int32_t *)REG_PVP0_THC1_TH10)               /* PVP0 THCn Threshold Value 10 */
-#define pREG_PVP0_THC0_TH11              ((volatile  int32_t *)REG_PVP0_THC0_TH11)               /* PVP0 THCn Threshold Value 11 */
-#define pREG_PVP0_THC1_TH11              ((volatile  int32_t *)REG_PVP0_THC1_TH11)               /* PVP0 THCn Threshold Value 11 */
-#define pREG_PVP0_THC0_TH12              ((volatile  int32_t *)REG_PVP0_THC0_TH12)               /* PVP0 THCn Threshold Value 12 */
-#define pREG_PVP0_THC1_TH12              ((volatile  int32_t *)REG_PVP0_THC1_TH12)               /* PVP0 THCn Threshold Value 12 */
-#define pREG_PVP0_THC0_TH13              ((volatile  int32_t *)REG_PVP0_THC0_TH13)               /* PVP0 THCn Threshold Value 13 */
-#define pREG_PVP0_THC1_TH13              ((volatile  int32_t *)REG_PVP0_THC1_TH13)               /* PVP0 THCn Threshold Value 13 */
-#define pREG_PVP0_THC0_TH14              ((volatile  int32_t *)REG_PVP0_THC0_TH14)               /* PVP0 THCn Threshold Value 14 */
-#define pREG_PVP0_THC1_TH14              ((volatile  int32_t *)REG_PVP0_THC1_TH14)               /* PVP0 THCn Threshold Value 14 */
-#define pREG_PVP0_THC0_TH15              ((volatile  int32_t *)REG_PVP0_THC0_TH15)               /* PVP0 THCn Threshold Value 15 */
-#define pREG_PVP0_THC1_TH15              ((volatile  int32_t *)REG_PVP0_THC1_TH15)               /* PVP0 THCn Threshold Value 15 */
-#define pREG_PVP0_THC0_HHPOS             ((volatile uint32_t *)REG_PVP0_THC0_HHPOS)              /* PVP0 THCn Histogram Horzontal Position */
-#define pREG_PVP0_THC1_HHPOS             ((volatile uint32_t *)REG_PVP0_THC1_HHPOS)              /* PVP0 THCn Histogram Horzontal Position */
-#define pREG_PVP0_THC0_HVPOS             ((volatile uint32_t *)REG_PVP0_THC0_HVPOS)              /* PVP0 THCn Histogram Vertical Position */
-#define pREG_PVP0_THC1_HVPOS             ((volatile uint32_t *)REG_PVP0_THC1_HVPOS)              /* PVP0 THCn Histogram Vertical Position */
-#define pREG_PVP0_THC0_HHCNT             ((volatile uint32_t *)REG_PVP0_THC0_HHCNT)              /* PVP0 THCn Histogram Horizontal Count */
-#define pREG_PVP0_THC1_HHCNT             ((volatile uint32_t *)REG_PVP0_THC1_HHCNT)              /* PVP0 THCn Histogram Horizontal Count */
-#define pREG_PVP0_THC0_HVCNT             ((volatile uint32_t *)REG_PVP0_THC0_HVCNT)              /* PVP0 THCn Histogram Vertical Count */
-#define pREG_PVP0_THC1_HVCNT             ((volatile uint32_t *)REG_PVP0_THC1_HVCNT)              /* PVP0 THCn Histogram Vertical Count */
-#define pREG_PVP0_THC0_RHPOS             ((volatile uint32_t *)REG_PVP0_THC0_RHPOS)              /* PVP0 THCn RLE Horizontal Position */
-#define pREG_PVP0_THC1_RHPOS             ((volatile uint32_t *)REG_PVP0_THC1_RHPOS)              /* PVP0 THCn RLE Horizontal Position */
-#define pREG_PVP0_THC0_RVPOS             ((volatile uint32_t *)REG_PVP0_THC0_RVPOS)              /* PVP0 THCn RLE Vertical Position */
-#define pREG_PVP0_THC1_RVPOS             ((volatile uint32_t *)REG_PVP0_THC1_RVPOS)              /* PVP0 THCn RLE Vertical Position */
-#define pREG_PVP0_THC0_RHCNT             ((volatile uint32_t *)REG_PVP0_THC0_RHCNT)              /* PVP0 THCn RLE Horizontal Count */
-#define pREG_PVP0_THC1_RHCNT             ((volatile uint32_t *)REG_PVP0_THC1_RHCNT)              /* PVP0 THCn RLE Horizontal Count */
-#define pREG_PVP0_THC0_RVCNT             ((volatile uint32_t *)REG_PVP0_THC0_RVCNT)              /* PVP0 THCn RLE Vertical Count */
-#define pREG_PVP0_THC1_RVCNT             ((volatile uint32_t *)REG_PVP0_THC1_RVCNT)              /* PVP0 THCn RLE Vertical Count */
-#define pREG_PVP0_THC0_HFCNT_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HFCNT_STAT)         /* PVP0 THCn Histogram Frame Count Status */
-#define pREG_PVP0_THC1_HFCNT_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HFCNT_STAT)         /* PVP0 THCn Histogram Frame Count Status */
-#define pREG_PVP0_THC0_HCNT0_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT0_STAT)         /* PVP0 THCn Histogram Counter Value 0 */
-#define pREG_PVP0_THC1_HCNT0_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT0_STAT)         /* PVP0 THCn Histogram Counter Value 0 */
-#define pREG_PVP0_THC0_HCNT1_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT1_STAT)         /* PVP0 THCn Histogram Counter Value 1 */
-#define pREG_PVP0_THC1_HCNT1_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT1_STAT)         /* PVP0 THCn Histogram Counter Value 1 */
-#define pREG_PVP0_THC0_HCNT2_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT2_STAT)         /* PVP0 THCn Histogram Counter Value 2 */
-#define pREG_PVP0_THC1_HCNT2_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT2_STAT)         /* PVP0 THCn Histogram Counter Value 2 */
-#define pREG_PVP0_THC0_HCNT3_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT3_STAT)         /* PVP0 THCn Histogram Counter Value 3 */
-#define pREG_PVP0_THC1_HCNT3_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT3_STAT)         /* PVP0 THCn Histogram Counter Value 3 */
-#define pREG_PVP0_THC0_HCNT4_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT4_STAT)         /* PVP0 THCn Histogram Counter Value 4 */
-#define pREG_PVP0_THC1_HCNT4_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT4_STAT)         /* PVP0 THCn Histogram Counter Value 4 */
-#define pREG_PVP0_THC0_HCNT5_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT5_STAT)         /* PVP0 THCn Histogram Counter Value 5 */
-#define pREG_PVP0_THC1_HCNT5_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT5_STAT)         /* PVP0 THCn Histogram Counter Value 5 */
-#define pREG_PVP0_THC0_HCNT6_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT6_STAT)         /* PVP0 THCn Histogram Counter Value 6 */
-#define pREG_PVP0_THC1_HCNT6_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT6_STAT)         /* PVP0 THCn Histogram Counter Value 6 */
-#define pREG_PVP0_THC0_HCNT7_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT7_STAT)         /* PVP0 THCn Histogram Counter Value 7 */
-#define pREG_PVP0_THC1_HCNT7_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT7_STAT)         /* PVP0 THCn Histogram Counter Value 7 */
-#define pREG_PVP0_THC0_HCNT8_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT8_STAT)         /* PVP0 THCn Histogram Counter Value 8 */
-#define pREG_PVP0_THC1_HCNT8_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT8_STAT)         /* PVP0 THCn Histogram Counter Value 8 */
-#define pREG_PVP0_THC0_HCNT9_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT9_STAT)         /* PVP0 THCn Histogram Counter Value 9 */
-#define pREG_PVP0_THC1_HCNT9_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT9_STAT)         /* PVP0 THCn Histogram Counter Value 9 */
-#define pREG_PVP0_THC0_HCNT10_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT10_STAT)        /* PVP0 THCn Histogram Counter Value 10 */
-#define pREG_PVP0_THC1_HCNT10_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT10_STAT)        /* PVP0 THCn Histogram Counter Value 10 */
-#define pREG_PVP0_THC0_HCNT11_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT11_STAT)        /* PVP0 THCn Histogram Counter Value 11 */
-#define pREG_PVP0_THC1_HCNT11_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT11_STAT)        /* PVP0 THCn Histogram Counter Value 11 */
-#define pREG_PVP0_THC0_HCNT12_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT12_STAT)        /* PVP0 THCn Histogram Counter Value 12 */
-#define pREG_PVP0_THC1_HCNT12_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT12_STAT)        /* PVP0 THCn Histogram Counter Value 12 */
-#define pREG_PVP0_THC0_HCNT13_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT13_STAT)        /* PVP0 THCn Histogram Counter Value 13 */
-#define pREG_PVP0_THC1_HCNT13_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT13_STAT)        /* PVP0 THCn Histogram Counter Value 13 */
-#define pREG_PVP0_THC0_HCNT14_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT14_STAT)        /* PVP0 THCn Histogram Counter Value 14 */
-#define pREG_PVP0_THC1_HCNT14_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT14_STAT)        /* PVP0 THCn Histogram Counter Value 14 */
-#define pREG_PVP0_THC0_HCNT15_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT15_STAT)        /* PVP0 THCn Histogram Counter Value 15 */
-#define pREG_PVP0_THC1_HCNT15_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT15_STAT)        /* PVP0 THCn Histogram Counter Value 15 */
-#define pREG_PVP0_THC0_RREP_STAT         ((volatile uint32_t *)REG_PVP0_THC0_RREP_STAT)          /* PVP0 THCn Number of RLE Reports */
-#define pREG_PVP0_THC1_RREP_STAT         ((volatile uint32_t *)REG_PVP0_THC1_RREP_STAT)          /* PVP0 THCn Number of RLE Reports */
-#define pREG_PVP0_PMA_CFG                ((volatile uint32_t *)REG_PVP0_PMA_CFG)                 /* PVP0 PMA Configuration */
-
-
-/* =========================================================================
-       PWM0
-   ========================================================================= */
-#define pREG_PWM0_CTL                    ((volatile uint32_t *)REG_PWM0_CTL)                     /* PWM0 Control Register */
-#define pREG_PWM0_CHANCFG                ((volatile uint32_t *)REG_PWM0_CHANCFG)                 /* PWM0 Channel Config Register */
-#define pREG_PWM0_TRIPCFG                ((volatile uint32_t *)REG_PWM0_TRIPCFG)                 /* PWM0 Trip Config Register */
-#define pREG_PWM0_STAT                   ((volatile uint32_t *)REG_PWM0_STAT)                    /* PWM0 Status Register */
-#define pREG_PWM0_IMSK                   ((volatile uint32_t *)REG_PWM0_IMSK)                    /* PWM0 Interrupt Mask Register */
-#define pREG_PWM0_ILAT                   ((volatile uint32_t *)REG_PWM0_ILAT)                    /* PWM0 Interrupt Latch Register */
-#define pREG_PWM0_CHOPCFG                ((volatile uint32_t *)REG_PWM0_CHOPCFG)                 /* PWM0 Chop Configuration Register */
-#define pREG_PWM0_DT                     ((volatile uint32_t *)REG_PWM0_DT)                      /* PWM0 Dead Time Register */
-#define pREG_PWM0_SYNC_WID               ((volatile uint32_t *)REG_PWM0_SYNC_WID)                /* PWM0 Sync Pulse Width Register */
-#define pREG_PWM0_TM0                    ((volatile uint32_t *)REG_PWM0_TM0)                     /* PWM0 Timer 0 Period Register */
-#define pREG_PWM0_TM1                    ((volatile uint32_t *)REG_PWM0_TM1)                     /* PWM0 Timer 1 Period Register */
-#define pREG_PWM0_TM2                    ((volatile uint32_t *)REG_PWM0_TM2)                     /* PWM0 Timer 2 Period Register */
-#define pREG_PWM0_TM3                    ((volatile uint32_t *)REG_PWM0_TM3)                     /* PWM0 Timer 3 Period Register */
-#define pREG_PWM0_TM4                    ((volatile uint32_t *)REG_PWM0_TM4)                     /* PWM0 Timer 4 Period Register */
-#define pREG_PWM0_DLYA                   ((volatile uint32_t *)REG_PWM0_DLYA)                    /* PWM0 Channel A Delay Register */
-#define pREG_PWM0_DLYB                   ((volatile uint32_t *)REG_PWM0_DLYB)                    /* PWM0 Channel B Delay Register */
-#define pREG_PWM0_DLYC                   ((volatile uint32_t *)REG_PWM0_DLYC)                    /* PWM0 Channel C Delay Register */
-#define pREG_PWM0_DLYD                   ((volatile uint32_t *)REG_PWM0_DLYD)                    /* PWM0 Channel D Delay Register */
-#define pREG_PWM0_ACTL                   ((volatile uint32_t *)REG_PWM0_ACTL)                    /* PWM0 Channel A Control Register */
-#define pREG_PWM0_AH0                    ((volatile uint32_t *)REG_PWM0_AH0)                     /* PWM0 Channel A-High Duty-0 Register */
-#define pREG_PWM0_AH1                    ((volatile uint32_t *)REG_PWM0_AH1)                     /* PWM0 Channel A-High Duty-1 Register */
-#define pREG_PWM0_AL0                    ((volatile uint32_t *)REG_PWM0_AL0)                     /* PWM0 Channel A-Low Duty-0 Register */
-#define pREG_PWM0_AL1                    ((volatile uint32_t *)REG_PWM0_AL1)                     /* PWM0 Channel A-Low Duty-1 Register */
-#define pREG_PWM0_BCTL                   ((volatile uint32_t *)REG_PWM0_BCTL)                    /* PWM0 Channel B Control Register */
-#define pREG_PWM0_BH0                    ((volatile uint32_t *)REG_PWM0_BH0)                     /* PWM0 Channel B-High Duty-0 Register */
-#define pREG_PWM0_BH1                    ((volatile uint32_t *)REG_PWM0_BH1)                     /* PWM0 Channel B-High Duty-1 Register */
-#define pREG_PWM0_BL0                    ((volatile uint32_t *)REG_PWM0_BL0)                     /* PWM0 Channel B-Low Duty-0 Register */
-#define pREG_PWM0_BL1                    ((volatile uint32_t *)REG_PWM0_BL1)                     /* PWM0 Channel B-Low Duty-1 Register */
-#define pREG_PWM0_CCTL                   ((volatile uint32_t *)REG_PWM0_CCTL)                    /* PWM0 Channel C Control Register */
-#define pREG_PWM0_CH0                    ((volatile uint32_t *)REG_PWM0_CH0)                     /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM0_CH1                    ((volatile uint32_t *)REG_PWM0_CH1)                     /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM0_CL0                    ((volatile uint32_t *)REG_PWM0_CL0)                     /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM0_CL1                    ((volatile uint32_t *)REG_PWM0_CL1)                     /* PWM0 Channel C-Low Duty-1 Register */
-#define pREG_PWM0_DCTL                   ((volatile uint32_t *)REG_PWM0_DCTL)                    /* PWM0 Channel D Control Register */
-#define pREG_PWM0_DH0                    ((volatile uint32_t *)REG_PWM0_DH0)                     /* PWM0 Channel D-High Duty-0 Register */
-#define pREG_PWM0_DH1                    ((volatile uint32_t *)REG_PWM0_DH1)                     /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM0_DL0                    ((volatile uint32_t *)REG_PWM0_DL0)                     /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM0_DL1                    ((volatile uint32_t *)REG_PWM0_DL1)                     /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================================================================
-       PWM1
-   ========================================================================= */
-#define pREG_PWM1_CTL                    ((volatile uint32_t *)REG_PWM1_CTL)                     /* PWM1 Control Register */
-#define pREG_PWM1_CHANCFG                ((volatile uint32_t *)REG_PWM1_CHANCFG)                 /* PWM1 Channel Config Register */
-#define pREG_PWM1_TRIPCFG                ((volatile uint32_t *)REG_PWM1_TRIPCFG)                 /* PWM1 Trip Config Register */
-#define pREG_PWM1_STAT                   ((volatile uint32_t *)REG_PWM1_STAT)                    /* PWM1 Status Register */
-#define pREG_PWM1_IMSK                   ((volatile uint32_t *)REG_PWM1_IMSK)                    /* PWM1 Interrupt Mask Register */
-#define pREG_PWM1_ILAT                   ((volatile uint32_t *)REG_PWM1_ILAT)                    /* PWM1 Interrupt Latch Register */
-#define pREG_PWM1_CHOPCFG                ((volatile uint32_t *)REG_PWM1_CHOPCFG)                 /* PWM1 Chop Configuration Register */
-#define pREG_PWM1_DT                     ((volatile uint32_t *)REG_PWM1_DT)                      /* PWM1 Dead Time Register */
-#define pREG_PWM1_SYNC_WID               ((volatile uint32_t *)REG_PWM1_SYNC_WID)                /* PWM1 Sync Pulse Width Register */
-#define pREG_PWM1_TM0                    ((volatile uint32_t *)REG_PWM1_TM0)                     /* PWM1 Timer 0 Period Register */
-#define pREG_PWM1_TM1                    ((volatile uint32_t *)REG_PWM1_TM1)                     /* PWM1 Timer 1 Period Register */
-#define pREG_PWM1_TM2                    ((volatile uint32_t *)REG_PWM1_TM2)                     /* PWM1 Timer 2 Period Register */
-#define pREG_PWM1_TM3                    ((volatile uint32_t *)REG_PWM1_TM3)                     /* PWM1 Timer 3 Period Register */
-#define pREG_PWM1_TM4                    ((volatile uint32_t *)REG_PWM1_TM4)                     /* PWM1 Timer 4 Period Register */
-#define pREG_PWM1_DLYA                   ((volatile uint32_t *)REG_PWM1_DLYA)                    /* PWM1 Channel A Delay Register */
-#define pREG_PWM1_DLYB                   ((volatile uint32_t *)REG_PWM1_DLYB)                    /* PWM1 Channel B Delay Register */
-#define pREG_PWM1_DLYC                   ((volatile uint32_t *)REG_PWM1_DLYC)                    /* PWM1 Channel C Delay Register */
-#define pREG_PWM1_DLYD                   ((volatile uint32_t *)REG_PWM1_DLYD)                    /* PWM1 Channel D Delay Register */
-#define pREG_PWM1_ACTL                   ((volatile uint32_t *)REG_PWM1_ACTL)                    /* PWM1 Channel A Control Register */
-#define pREG_PWM1_AH0                    ((volatile uint32_t *)REG_PWM1_AH0)                     /* PWM1 Channel A-High Duty-0 Register */
-#define pREG_PWM1_AH1                    ((volatile uint32_t *)REG_PWM1_AH1)                     /* PWM1 Channel A-High Duty-1 Register */
-#define pREG_PWM1_AL0                    ((volatile uint32_t *)REG_PWM1_AL0)                     /* PWM1 Channel A-Low Duty-0 Register */
-#define pREG_PWM1_AL1                    ((volatile uint32_t *)REG_PWM1_AL1)                     /* PWM1 Channel A-Low Duty-1 Register */
-#define pREG_PWM1_BCTL                   ((volatile uint32_t *)REG_PWM1_BCTL)                    /* PWM1 Channel B Control Register */
-#define pREG_PWM1_BH0                    ((volatile uint32_t *)REG_PWM1_BH0)                     /* PWM1 Channel B-High Duty-0 Register */
-#define pREG_PWM1_BH1                    ((volatile uint32_t *)REG_PWM1_BH1)                     /* PWM1 Channel B-High Duty-1 Register */
-#define pREG_PWM1_BL0                    ((volatile uint32_t *)REG_PWM1_BL0)                     /* PWM1 Channel B-Low Duty-0 Register */
-#define pREG_PWM1_BL1                    ((volatile uint32_t *)REG_PWM1_BL1)                     /* PWM1 Channel B-Low Duty-1 Register */
-#define pREG_PWM1_CCTL                   ((volatile uint32_t *)REG_PWM1_CCTL)                    /* PWM1 Channel C Control Register */
-#define pREG_PWM1_CH0                    ((volatile uint32_t *)REG_PWM1_CH0)                     /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM1_CH1                    ((volatile uint32_t *)REG_PWM1_CH1)                     /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM1_CL0                    ((volatile uint32_t *)REG_PWM1_CL0)                     /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM1_CL1                    ((volatile uint32_t *)REG_PWM1_CL1)                     /* PWM1 Channel C-Low Duty-1 Register */
-#define pREG_PWM1_DCTL                   ((volatile uint32_t *)REG_PWM1_DCTL)                    /* PWM1 Channel D Control Register */
-#define pREG_PWM1_DH0                    ((volatile uint32_t *)REG_PWM1_DH0)                     /* PWM1 Channel D-High Duty-0 Register */
-#define pREG_PWM1_DH1                    ((volatile uint32_t *)REG_PWM1_DH1)                     /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM1_DL0                    ((volatile uint32_t *)REG_PWM1_DL0)                     /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM1_DL1                    ((volatile uint32_t *)REG_PWM1_DL1)                     /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-
-/* =========================================================================
-       VID0
-   ========================================================================= */
-#define pREG_VID0_CONN                   ((volatile uint32_t *)REG_VID0_CONN)                    /* VID0 Video Subsystem Connect Register */
-
-
-/* =========================================================================
-       SWU0
-   ========================================================================= */
-#define pREG_SWU0_GCTL                   ((volatile uint32_t *)REG_SWU0_GCTL)                    /* SWU0 Global Control Register */
-#define pREG_SWU0_GSTAT                  ((volatile uint32_t *)REG_SWU0_GSTAT)                   /* SWU0 Global Status Register */
-#define pREG_SWU0_CTL0                   ((volatile uint32_t *)REG_SWU0_CTL0)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL1                   ((volatile uint32_t *)REG_SWU0_CTL1)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL2                   ((volatile uint32_t *)REG_SWU0_CTL2)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL3                   ((volatile uint32_t *)REG_SWU0_CTL3)                    /* SWU0 Control Register n */
-#define pREG_SWU0_LA0                    ((void * volatile *)REG_SWU0_LA0)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA1                    ((void * volatile *)REG_SWU0_LA1)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA2                    ((void * volatile *)REG_SWU0_LA2)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA3                    ((void * volatile *)REG_SWU0_LA3)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_UA0                    ((void * volatile *)REG_SWU0_UA0)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA1                    ((void * volatile *)REG_SWU0_UA1)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA2                    ((void * volatile *)REG_SWU0_UA2)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA3                    ((void * volatile *)REG_SWU0_UA3)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_ID0                    ((volatile uint32_t *)REG_SWU0_ID0)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID1                    ((volatile uint32_t *)REG_SWU0_ID1)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID2                    ((volatile uint32_t *)REG_SWU0_ID2)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID3                    ((volatile uint32_t *)REG_SWU0_ID3)                     /* SWU0 ID Register n */
-#define pREG_SWU0_CNT0                   ((volatile uint32_t *)REG_SWU0_CNT0)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT1                   ((volatile uint32_t *)REG_SWU0_CNT1)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT2                   ((volatile uint32_t *)REG_SWU0_CNT2)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT3                   ((volatile uint32_t *)REG_SWU0_CNT3)                    /* SWU0 Count Register n */
-#define pREG_SWU0_TARG0                  ((volatile uint32_t *)REG_SWU0_TARG0)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG1                  ((volatile uint32_t *)REG_SWU0_TARG1)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG2                  ((volatile uint32_t *)REG_SWU0_TARG2)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG3                  ((volatile uint32_t *)REG_SWU0_TARG3)                   /* SWU0 Target Register n */
-#define pREG_SWU0_HIST0                  ((volatile uint32_t *)REG_SWU0_HIST0)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST1                  ((volatile uint32_t *)REG_SWU0_HIST1)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST2                  ((volatile uint32_t *)REG_SWU0_HIST2)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST3                  ((volatile uint32_t *)REG_SWU0_HIST3)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_CUR0                   ((volatile uint32_t *)REG_SWU0_CUR0)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR1                   ((volatile uint32_t *)REG_SWU0_CUR1)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR2                   ((volatile uint32_t *)REG_SWU0_CUR2)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR3                   ((volatile uint32_t *)REG_SWU0_CUR3)                    /* SWU0 Current Register n */
-
-/* =========================================================================
-       SWU1
-   ========================================================================= */
-#define pREG_SWU1_GCTL                   ((volatile uint32_t *)REG_SWU1_GCTL)                    /* SWU1 Global Control Register */
-#define pREG_SWU1_GSTAT                  ((volatile uint32_t *)REG_SWU1_GSTAT)                   /* SWU1 Global Status Register */
-#define pREG_SWU1_CTL0                   ((volatile uint32_t *)REG_SWU1_CTL0)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL1                   ((volatile uint32_t *)REG_SWU1_CTL1)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL2                   ((volatile uint32_t *)REG_SWU1_CTL2)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL3                   ((volatile uint32_t *)REG_SWU1_CTL3)                    /* SWU1 Control Register n */
-#define pREG_SWU1_LA0                    ((void * volatile *)REG_SWU1_LA0)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA1                    ((void * volatile *)REG_SWU1_LA1)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA2                    ((void * volatile *)REG_SWU1_LA2)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA3                    ((void * volatile *)REG_SWU1_LA3)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_UA0                    ((void * volatile *)REG_SWU1_UA0)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA1                    ((void * volatile *)REG_SWU1_UA1)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA2                    ((void * volatile *)REG_SWU1_UA2)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA3                    ((void * volatile *)REG_SWU1_UA3)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_ID0                    ((volatile uint32_t *)REG_SWU1_ID0)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID1                    ((volatile uint32_t *)REG_SWU1_ID1)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID2                    ((volatile uint32_t *)REG_SWU1_ID2)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID3                    ((volatile uint32_t *)REG_SWU1_ID3)                     /* SWU1 ID Register n */
-#define pREG_SWU1_CNT0                   ((volatile uint32_t *)REG_SWU1_CNT0)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT1                   ((volatile uint32_t *)REG_SWU1_CNT1)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT2                   ((volatile uint32_t *)REG_SWU1_CNT2)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT3                   ((volatile uint32_t *)REG_SWU1_CNT3)                    /* SWU1 Count Register n */
-#define pREG_SWU1_TARG0                  ((volatile uint32_t *)REG_SWU1_TARG0)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG1                  ((volatile uint32_t *)REG_SWU1_TARG1)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG2                  ((volatile uint32_t *)REG_SWU1_TARG2)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG3                  ((volatile uint32_t *)REG_SWU1_TARG3)                   /* SWU1 Target Register n */
-#define pREG_SWU1_HIST0                  ((volatile uint32_t *)REG_SWU1_HIST0)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST1                  ((volatile uint32_t *)REG_SWU1_HIST1)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST2                  ((volatile uint32_t *)REG_SWU1_HIST2)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST3                  ((volatile uint32_t *)REG_SWU1_HIST3)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_CUR0                   ((volatile uint32_t *)REG_SWU1_CUR0)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR1                   ((volatile uint32_t *)REG_SWU1_CUR1)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR2                   ((volatile uint32_t *)REG_SWU1_CUR2)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR3                   ((volatile uint32_t *)REG_SWU1_CUR3)                    /* SWU1 Current Register n */
-
-/* =========================================================================
-       SWU2
-   ========================================================================= */
-#define pREG_SWU2_GCTL                   ((volatile uint32_t *)REG_SWU2_GCTL)                    /* SWU2 Global Control Register */
-#define pREG_SWU2_GSTAT                  ((volatile uint32_t *)REG_SWU2_GSTAT)                   /* SWU2 Global Status Register */
-#define pREG_SWU2_CTL0                   ((volatile uint32_t *)REG_SWU2_CTL0)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL1                   ((volatile uint32_t *)REG_SWU2_CTL1)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL2                   ((volatile uint32_t *)REG_SWU2_CTL2)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL3                   ((volatile uint32_t *)REG_SWU2_CTL3)                    /* SWU2 Control Register n */
-#define pREG_SWU2_LA0                    ((void * volatile *)REG_SWU2_LA0)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA1                    ((void * volatile *)REG_SWU2_LA1)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA2                    ((void * volatile *)REG_SWU2_LA2)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA3                    ((void * volatile *)REG_SWU2_LA3)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_UA0                    ((void * volatile *)REG_SWU2_UA0)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA1                    ((void * volatile *)REG_SWU2_UA1)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA2                    ((void * volatile *)REG_SWU2_UA2)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA3                    ((void * volatile *)REG_SWU2_UA3)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_ID0                    ((volatile uint32_t *)REG_SWU2_ID0)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID1                    ((volatile uint32_t *)REG_SWU2_ID1)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID2                    ((volatile uint32_t *)REG_SWU2_ID2)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID3                    ((volatile uint32_t *)REG_SWU2_ID3)                     /* SWU2 ID Register n */
-#define pREG_SWU2_CNT0                   ((volatile uint32_t *)REG_SWU2_CNT0)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT1                   ((volatile uint32_t *)REG_SWU2_CNT1)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT2                   ((volatile uint32_t *)REG_SWU2_CNT2)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT3                   ((volatile uint32_t *)REG_SWU2_CNT3)                    /* SWU2 Count Register n */
-#define pREG_SWU2_TARG0                  ((volatile uint32_t *)REG_SWU2_TARG0)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG1                  ((volatile uint32_t *)REG_SWU2_TARG1)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG2                  ((volatile uint32_t *)REG_SWU2_TARG2)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG3                  ((volatile uint32_t *)REG_SWU2_TARG3)                   /* SWU2 Target Register n */
-#define pREG_SWU2_HIST0                  ((volatile uint32_t *)REG_SWU2_HIST0)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST1                  ((volatile uint32_t *)REG_SWU2_HIST1)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST2                  ((volatile uint32_t *)REG_SWU2_HIST2)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST3                  ((volatile uint32_t *)REG_SWU2_HIST3)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_CUR0                   ((volatile uint32_t *)REG_SWU2_CUR0)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR1                   ((volatile uint32_t *)REG_SWU2_CUR1)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR2                   ((volatile uint32_t *)REG_SWU2_CUR2)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR3                   ((volatile uint32_t *)REG_SWU2_CUR3)                    /* SWU2 Current Register n */
-
-/* =========================================================================
-       SWU3
-   ========================================================================= */
-#define pREG_SWU3_GCTL                   ((volatile uint32_t *)REG_SWU3_GCTL)                    /* SWU3 Global Control Register */
-#define pREG_SWU3_GSTAT                  ((volatile uint32_t *)REG_SWU3_GSTAT)                   /* SWU3 Global Status Register */
-#define pREG_SWU3_CTL0                   ((volatile uint32_t *)REG_SWU3_CTL0)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL1                   ((volatile uint32_t *)REG_SWU3_CTL1)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL2                   ((volatile uint32_t *)REG_SWU3_CTL2)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL3                   ((volatile uint32_t *)REG_SWU3_CTL3)                    /* SWU3 Control Register n */
-#define pREG_SWU3_LA0                    ((void * volatile *)REG_SWU3_LA0)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA1                    ((void * volatile *)REG_SWU3_LA1)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA2                    ((void * volatile *)REG_SWU3_LA2)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA3                    ((void * volatile *)REG_SWU3_LA3)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_UA0                    ((void * volatile *)REG_SWU3_UA0)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA1                    ((void * volatile *)REG_SWU3_UA1)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA2                    ((void * volatile *)REG_SWU3_UA2)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA3                    ((void * volatile *)REG_SWU3_UA3)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_ID0                    ((volatile uint32_t *)REG_SWU3_ID0)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID1                    ((volatile uint32_t *)REG_SWU3_ID1)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID2                    ((volatile uint32_t *)REG_SWU3_ID2)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID3                    ((volatile uint32_t *)REG_SWU3_ID3)                     /* SWU3 ID Register n */
-#define pREG_SWU3_CNT0                   ((volatile uint32_t *)REG_SWU3_CNT0)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT1                   ((volatile uint32_t *)REG_SWU3_CNT1)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT2                   ((volatile uint32_t *)REG_SWU3_CNT2)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT3                   ((volatile uint32_t *)REG_SWU3_CNT3)                    /* SWU3 Count Register n */
-#define pREG_SWU3_TARG0                  ((volatile uint32_t *)REG_SWU3_TARG0)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG1                  ((volatile uint32_t *)REG_SWU3_TARG1)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG2                  ((volatile uint32_t *)REG_SWU3_TARG2)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG3                  ((volatile uint32_t *)REG_SWU3_TARG3)                   /* SWU3 Target Register n */
-#define pREG_SWU3_HIST0                  ((volatile uint32_t *)REG_SWU3_HIST0)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST1                  ((volatile uint32_t *)REG_SWU3_HIST1)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST2                  ((volatile uint32_t *)REG_SWU3_HIST2)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST3                  ((volatile uint32_t *)REG_SWU3_HIST3)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_CUR0                   ((volatile uint32_t *)REG_SWU3_CUR0)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR1                   ((volatile uint32_t *)REG_SWU3_CUR1)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR2                   ((volatile uint32_t *)REG_SWU3_CUR2)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR3                   ((volatile uint32_t *)REG_SWU3_CUR3)                    /* SWU3 Current Register n */
-
-/* =========================================================================
-       SWU4
-   ========================================================================= */
-#define pREG_SWU4_GCTL                   ((volatile uint32_t *)REG_SWU4_GCTL)                    /* SWU4 Global Control Register */
-#define pREG_SWU4_GSTAT                  ((volatile uint32_t *)REG_SWU4_GSTAT)                   /* SWU4 Global Status Register */
-#define pREG_SWU4_CTL0                   ((volatile uint32_t *)REG_SWU4_CTL0)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL1                   ((volatile uint32_t *)REG_SWU4_CTL1)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL2                   ((volatile uint32_t *)REG_SWU4_CTL2)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL3                   ((volatile uint32_t *)REG_SWU4_CTL3)                    /* SWU4 Control Register n */
-#define pREG_SWU4_LA0                    ((void * volatile *)REG_SWU4_LA0)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA1                    ((void * volatile *)REG_SWU4_LA1)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA2                    ((void * volatile *)REG_SWU4_LA2)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA3                    ((void * volatile *)REG_SWU4_LA3)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_UA0                    ((void * volatile *)REG_SWU4_UA0)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA1                    ((void * volatile *)REG_SWU4_UA1)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA2                    ((void * volatile *)REG_SWU4_UA2)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA3                    ((void * volatile *)REG_SWU4_UA3)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_ID0                    ((volatile uint32_t *)REG_SWU4_ID0)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID1                    ((volatile uint32_t *)REG_SWU4_ID1)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID2                    ((volatile uint32_t *)REG_SWU4_ID2)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID3                    ((volatile uint32_t *)REG_SWU4_ID3)                     /* SWU4 ID Register n */
-#define pREG_SWU4_CNT0                   ((volatile uint32_t *)REG_SWU4_CNT0)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT1                   ((volatile uint32_t *)REG_SWU4_CNT1)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT2                   ((volatile uint32_t *)REG_SWU4_CNT2)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT3                   ((volatile uint32_t *)REG_SWU4_CNT3)                    /* SWU4 Count Register n */
-#define pREG_SWU4_TARG0                  ((volatile uint32_t *)REG_SWU4_TARG0)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG1                  ((volatile uint32_t *)REG_SWU4_TARG1)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG2                  ((volatile uint32_t *)REG_SWU4_TARG2)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG3                  ((volatile uint32_t *)REG_SWU4_TARG3)                   /* SWU4 Target Register n */
-#define pREG_SWU4_HIST0                  ((volatile uint32_t *)REG_SWU4_HIST0)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST1                  ((volatile uint32_t *)REG_SWU4_HIST1)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST2                  ((volatile uint32_t *)REG_SWU4_HIST2)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST3                  ((volatile uint32_t *)REG_SWU4_HIST3)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_CUR0                   ((volatile uint32_t *)REG_SWU4_CUR0)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR1                   ((volatile uint32_t *)REG_SWU4_CUR1)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR2                   ((volatile uint32_t *)REG_SWU4_CUR2)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR3                   ((volatile uint32_t *)REG_SWU4_CUR3)                    /* SWU4 Current Register n */
-
-/* =========================================================================
-       SWU5
-   ========================================================================= */
-#define pREG_SWU5_GCTL                   ((volatile uint32_t *)REG_SWU5_GCTL)                    /* SWU5 Global Control Register */
-#define pREG_SWU5_GSTAT                  ((volatile uint32_t *)REG_SWU5_GSTAT)                   /* SWU5 Global Status Register */
-#define pREG_SWU5_CTL0                   ((volatile uint32_t *)REG_SWU5_CTL0)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL1                   ((volatile uint32_t *)REG_SWU5_CTL1)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL2                   ((volatile uint32_t *)REG_SWU5_CTL2)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL3                   ((volatile uint32_t *)REG_SWU5_CTL3)                    /* SWU5 Control Register n */
-#define pREG_SWU5_LA0                    ((void * volatile *)REG_SWU5_LA0)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA1                    ((void * volatile *)REG_SWU5_LA1)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA2                    ((void * volatile *)REG_SWU5_LA2)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA3                    ((void * volatile *)REG_SWU5_LA3)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_UA0                    ((void * volatile *)REG_SWU5_UA0)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA1                    ((void * volatile *)REG_SWU5_UA1)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA2                    ((void * volatile *)REG_SWU5_UA2)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA3                    ((void * volatile *)REG_SWU5_UA3)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_ID0                    ((volatile uint32_t *)REG_SWU5_ID0)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID1                    ((volatile uint32_t *)REG_SWU5_ID1)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID2                    ((volatile uint32_t *)REG_SWU5_ID2)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID3                    ((volatile uint32_t *)REG_SWU5_ID3)                     /* SWU5 ID Register n */
-#define pREG_SWU5_CNT0                   ((volatile uint32_t *)REG_SWU5_CNT0)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT1                   ((volatile uint32_t *)REG_SWU5_CNT1)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT2                   ((volatile uint32_t *)REG_SWU5_CNT2)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT3                   ((volatile uint32_t *)REG_SWU5_CNT3)                    /* SWU5 Count Register n */
-#define pREG_SWU5_TARG0                  ((volatile uint32_t *)REG_SWU5_TARG0)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG1                  ((volatile uint32_t *)REG_SWU5_TARG1)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG2                  ((volatile uint32_t *)REG_SWU5_TARG2)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG3                  ((volatile uint32_t *)REG_SWU5_TARG3)                   /* SWU5 Target Register n */
-#define pREG_SWU5_HIST0                  ((volatile uint32_t *)REG_SWU5_HIST0)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST1                  ((volatile uint32_t *)REG_SWU5_HIST1)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST2                  ((volatile uint32_t *)REG_SWU5_HIST2)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST3                  ((volatile uint32_t *)REG_SWU5_HIST3)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_CUR0                   ((volatile uint32_t *)REG_SWU5_CUR0)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR1                   ((volatile uint32_t *)REG_SWU5_CUR1)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR2                   ((volatile uint32_t *)REG_SWU5_CUR2)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR3                   ((volatile uint32_t *)REG_SWU5_CUR3)                    /* SWU5 Current Register n */
-
-/* =========================================================================
-       SWU6
-   ========================================================================= */
-#define pREG_SWU6_GCTL                   ((volatile uint32_t *)REG_SWU6_GCTL)                    /* SWU6 Global Control Register */
-#define pREG_SWU6_GSTAT                  ((volatile uint32_t *)REG_SWU6_GSTAT)                   /* SWU6 Global Status Register */
-#define pREG_SWU6_CTL0                   ((volatile uint32_t *)REG_SWU6_CTL0)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL1                   ((volatile uint32_t *)REG_SWU6_CTL1)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL2                   ((volatile uint32_t *)REG_SWU6_CTL2)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL3                   ((volatile uint32_t *)REG_SWU6_CTL3)                    /* SWU6 Control Register n */
-#define pREG_SWU6_LA0                    ((void * volatile *)REG_SWU6_LA0)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA1                    ((void * volatile *)REG_SWU6_LA1)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA2                    ((void * volatile *)REG_SWU6_LA2)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA3                    ((void * volatile *)REG_SWU6_LA3)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_UA0                    ((void * volatile *)REG_SWU6_UA0)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA1                    ((void * volatile *)REG_SWU6_UA1)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA2                    ((void * volatile *)REG_SWU6_UA2)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA3                    ((void * volatile *)REG_SWU6_UA3)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_ID0                    ((volatile uint32_t *)REG_SWU6_ID0)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID1                    ((volatile uint32_t *)REG_SWU6_ID1)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID2                    ((volatile uint32_t *)REG_SWU6_ID2)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID3                    ((volatile uint32_t *)REG_SWU6_ID3)                     /* SWU6 ID Register n */
-#define pREG_SWU6_CNT0                   ((volatile uint32_t *)REG_SWU6_CNT0)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT1                   ((volatile uint32_t *)REG_SWU6_CNT1)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT2                   ((volatile uint32_t *)REG_SWU6_CNT2)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT3                   ((volatile uint32_t *)REG_SWU6_CNT3)                    /* SWU6 Count Register n */
-#define pREG_SWU6_TARG0                  ((volatile uint32_t *)REG_SWU6_TARG0)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG1                  ((volatile uint32_t *)REG_SWU6_TARG1)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG2                  ((volatile uint32_t *)REG_SWU6_TARG2)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG3                  ((volatile uint32_t *)REG_SWU6_TARG3)                   /* SWU6 Target Register n */
-#define pREG_SWU6_HIST0                  ((volatile uint32_t *)REG_SWU6_HIST0)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST1                  ((volatile uint32_t *)REG_SWU6_HIST1)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST2                  ((volatile uint32_t *)REG_SWU6_HIST2)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST3                  ((volatile uint32_t *)REG_SWU6_HIST3)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_CUR0                   ((volatile uint32_t *)REG_SWU6_CUR0)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR1                   ((volatile uint32_t *)REG_SWU6_CUR1)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR2                   ((volatile uint32_t *)REG_SWU6_CUR2)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR3                   ((volatile uint32_t *)REG_SWU6_CUR3)                    /* SWU6 Current Register n */
-
-
-/* =========================================================================
-       SDU0
-   ========================================================================= */
-#define pREG_SDU0_IDCODE                 ((volatile uint32_t *)REG_SDU0_IDCODE)                  /* SDU0 ID Code Register */
-#define pREG_SDU0_CTL                    ((volatile uint32_t *)REG_SDU0_CTL)                     /* SDU0 Control Register */
-#define pREG_SDU0_STAT                   ((volatile uint32_t *)REG_SDU0_STAT)                    /* SDU0 Status Register */
-#define pREG_SDU0_MACCTL                 ((volatile uint32_t *)REG_SDU0_MACCTL)                  /* SDU0 Memory Access Control Register */
-#define pREG_SDU0_MACADDR                ((void * volatile *)REG_SDU0_MACADDR)                   /* SDU0 Memory Access Address Register */
-#define pREG_SDU0_MACDATA                ((volatile uint32_t *)REG_SDU0_MACDATA)                 /* SDU0 Memory Access Data Register */
-#define pREG_SDU0_DMARD                  ((volatile uint32_t *)REG_SDU0_DMARD)                   /* SDU0 DMA Read Data Register */
-#define pREG_SDU0_DMAWD                  ((volatile uint32_t *)REG_SDU0_DMAWD)                   /* SDU0 DMA Write Data Register */
-#define pREG_SDU0_MSG                    ((volatile uint32_t *)REG_SDU0_MSG)                     /* SDU0 Message Register */
-#define pREG_SDU0_MSG_SET                ((volatile uint32_t *)REG_SDU0_MSG_SET)                 /* SDU0 Message Set Register */
-#define pREG_SDU0_MSG_CLR                ((volatile uint32_t *)REG_SDU0_MSG_CLR)                 /* SDU0 Message Clear Register */
-#define pREG_SDU0_GHLT                   ((volatile uint32_t *)REG_SDU0_GHLT)                    /* SDU0 Group Halt Register */
-
-
-/* =========================================================================
-       EMAC0
-   ========================================================================= */
-#define pREG_EMAC0_MACCFG                ((volatile uint32_t *)REG_EMAC0_MACCFG)                 /* EMAC0 MAC Configuration Register */
-#define pREG_EMAC0_MACFRMFILT            ((volatile uint32_t *)REG_EMAC0_MACFRMFILT)             /* EMAC0 MAC Rx Frame Filter Register */
-#define pREG_EMAC0_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC0_HASHTBL_HI)             /* EMAC0 Hash Table High Register */
-#define pREG_EMAC0_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC0_HASHTBL_LO)             /* EMAC0 Hash Table Low Register */
-#define pREG_EMAC0_SMI_ADDR              ((volatile uint32_t *)REG_EMAC0_SMI_ADDR)               /* EMAC0 SMI Address Register */
-#define pREG_EMAC0_SMI_DATA              ((volatile uint32_t *)REG_EMAC0_SMI_DATA)               /* EMAC0 SMI Data Register */
-#define pREG_EMAC0_FLOWCTL               ((volatile uint32_t *)REG_EMAC0_FLOWCTL)                /* EMAC0 FLow Control Register */
-#define pREG_EMAC0_VLANTAG               ((volatile uint32_t *)REG_EMAC0_VLANTAG)                /* EMAC0 VLAN Tag Register */
-#define pREG_EMAC0_DBG                   ((volatile uint32_t *)REG_EMAC0_DBG)                    /* EMAC0 Debug Register */
-#define pREG_EMAC0_ISTAT                 ((volatile uint32_t *)REG_EMAC0_ISTAT)                  /* EMAC0 Interrupt Status Register */
-#define pREG_EMAC0_IMSK                  ((volatile uint32_t *)REG_EMAC0_IMSK)                   /* EMAC0 Interrupt Mask Register */
-#define pREG_EMAC0_ADDR0_HI              ((volatile uint32_t *)REG_EMAC0_ADDR0_HI)               /* EMAC0 MAC Address 0 High Register */
-#define pREG_EMAC0_ADDR0_LO              ((volatile uint32_t *)REG_EMAC0_ADDR0_LO)               /* EMAC0 MAC Address 0 Low Register */
-#define pREG_EMAC0_MMC_CTL               ((volatile uint32_t *)REG_EMAC0_MMC_CTL)                /* EMAC0 MMC Control Register */
-#define pREG_EMAC0_MMC_RXINT             ((volatile uint32_t *)REG_EMAC0_MMC_RXINT)              /* EMAC0 MMC Rx Interrupt Register */
-#define pREG_EMAC0_MMC_TXINT             ((volatile uint32_t *)REG_EMAC0_MMC_TXINT)              /* EMAC0 MMC Tx Interrupt Register */
-#define pREG_EMAC0_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_RXIMSK)             /* EMAC0 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC0_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_TXIMSK)             /* EMAC0 MMC TX Interrupt Mask Register */
-#define pREG_EMAC0_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_GB)            /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC0_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_GB)            /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_G)           /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_G)           /* EMAC0 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC0_TX64_GB               ((volatile uint32_t *)REG_EMAC0_TX64_GB)                /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_TX65TO127_GB)           /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_TX128TO255_GB)          /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_TX256TO511_GB)          /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_TX512TO1023_GB)         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_TX1024TOMAX_GB)         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXUCASTFRM_GB)          /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_GB)          /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_GB)          /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC0_TXUNDR_ERR)             /* EMAC0 Tx Underflow Error Register */
-#define pREG_EMAC0_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC0_TXSNGCOL_G)             /* EMAC0 Tx Single Collision (Good) Register */
-#define pREG_EMAC0_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC0_TXMULTCOL_G)            /* EMAC0 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC0_TXDEFERRED            ((volatile uint32_t *)REG_EMAC0_TXDEFERRED)             /* EMAC0 Tx Deferred Register */
-#define pREG_EMAC0_TXLATECOL             ((volatile uint32_t *)REG_EMAC0_TXLATECOL)              /* EMAC0 Tx Late Collision Register */
-#define pREG_EMAC0_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC0_TXEXCESSCOL)            /* EMAC0 Tx Excess Collision Register */
-#define pREG_EMAC0_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC0_TXCARR_ERR)             /* EMAC0 Tx Carrier Error Register */
-#define pREG_EMAC0_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_G)             /* EMAC0 Tx Octet Count (Good) Register */
-#define pREG_EMAC0_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_G)             /* EMAC0 Tx Frame Count (Good) Register */
-#define pREG_EMAC0_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC0_TXEXCESSDEF)            /* EMAC0 Tx Excess Deferral Register */
-#define pREG_EMAC0_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_TXPAUSEFRM)             /* EMAC0 Tx Pause Frame Register */
-#define pREG_EMAC0_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC0_TXVLANFRM_G)            /* EMAC0 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC0_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXFRMCNT_GB)            /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_GB)            /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_G)             /* EMAC0 Rx Octet Count (Good) Register */
-#define pREG_EMAC0_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXBCASTFRM_G)           /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXMCASTFRM_G)           /* EMAC0 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC0_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC0_RXCRC_ERR)              /* EMAC0 Rx CRC Error Register */
-#define pREG_EMAC0_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC0_RXALIGN_ERR)            /* EMAC0 Rx alignment Error Register */
-#define pREG_EMAC0_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC0_RXRUNT_ERR)             /* EMAC0 Rx Runt Error Register */
-#define pREG_EMAC0_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC0_RXJAB_ERR)              /* EMAC0 Rx Jab Error Register */
-#define pREG_EMAC0_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXUSIZE_G)              /* EMAC0 Rx Undersize (Good) Register */
-#define pREG_EMAC0_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXOSIZE_G)              /* EMAC0 Rx Oversize (Good) Register */
-#define pREG_EMAC0_RX64_GB               ((volatile uint32_t *)REG_EMAC0_RX64_GB)                /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_RX65TO127_GB)           /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_RX128TO255_GB)          /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_RX256TO511_GB)          /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_RX512TO1023_GB)         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_RX1024TOMAX_GB)         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXUCASTFRM_G)           /* EMAC0 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC0_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC0_RXLEN_ERR)              /* EMAC0 Rx Length Error Register */
-#define pREG_EMAC0_RXOORTYPE             ((volatile uint32_t *)REG_EMAC0_RXOORTYPE)              /* EMAC0 Rx Out Of Range Type Register */
-#define pREG_EMAC0_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_RXPAUSEFRM)             /* EMAC0 Rx Pause Frames Register */
-#define pREG_EMAC0_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC0_RXFIFO_OVF)             /* EMAC0 Rx FIFO Overflow Register */
-#define pREG_EMAC0_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC0_RXVLANFRM_GB)           /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC0_RXWDOG_ERR)             /* EMAC0 Rx Watch Dog Error Register */
-#define pREG_EMAC0_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_IPC_RXIMSK)             /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC0_IPC_RXINT             ((volatile uint32_t *)REG_EMAC0_IPC_RXINT)              /* EMAC0 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC0_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_FRM)          /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_FRM)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_FRM)       /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC0_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_FRM)        /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_FRM)       /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC0_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_FRM)          /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_FRM)     /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_FRM)       /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC0_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_FRM)           /* EMAC0 Rx UDP Good Frames Register */
-#define pREG_EMAC0_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_FRM)          /* EMAC0 Rx UDP Error Frames Register */
-#define pREG_EMAC0_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_FRM)           /* EMAC0 Rx TCP Good Frames Register */
-#define pREG_EMAC0_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_FRM)          /* EMAC0 Rx TCP Error Frames Register */
-#define pREG_EMAC0_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_FRM)          /* EMAC0 Rx ICMP Good Frames Register */
-#define pREG_EMAC0_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_FRM)         /* EMAC0 Rx ICMP Error Frames Register */
-#define pREG_EMAC0_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_OCT)          /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_OCT)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_OCT)       /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC0_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_OCT)        /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_OCT)       /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC0_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_OCT)          /* EMAC0 Rx IPv6 Good Octets Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_OCT)     /* EMAC0 Rx IPv6 Header Errors Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_OCT)       /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC0_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_OCT)           /* EMAC0 Rx UDP Good Octets Register */
-#define pREG_EMAC0_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_OCT)          /* EMAC0 Rx UDP Error Octets Register */
-#define pREG_EMAC0_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_OCT)           /* EMAC0 Rx TCP Good Octets Register */
-#define pREG_EMAC0_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_OCT)          /* EMAC0 Rx TCP Error Octets Register */
-#define pREG_EMAC0_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_OCT)          /* EMAC0 Rx ICMP Good Octets Register */
-#define pREG_EMAC0_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_OCT)         /* EMAC0 Rx ICMP Error Octets Register */
-#define pREG_EMAC0_TM_CTL                ((volatile uint32_t *)REG_EMAC0_TM_CTL)                 /* EMAC0 Time Stamp Control Register */
-#define pREG_EMAC0_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC0_TM_SUBSEC)              /* EMAC0 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC0_TM_SEC                ((volatile uint32_t *)REG_EMAC0_TM_SEC)                 /* EMAC0 Time Stamp Low Seconds Register */
-#define pREG_EMAC0_TM_NSEC               ((volatile uint32_t *)REG_EMAC0_TM_NSEC)                /* EMAC0 Time Stamp Nano Seconds Register */
-#define pREG_EMAC0_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC0_TM_SECUPDT)             /* EMAC0 Time Stamp Seconds Update Register */
-#define pREG_EMAC0_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC0_TM_NSECUPDT)            /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC0_TM_ADDEND             ((volatile uint32_t *)REG_EMAC0_TM_ADDEND)              /* EMAC0 Time Stamp Addend Register */
-#define pREG_EMAC0_TM_TGTM               ((volatile uint32_t *)REG_EMAC0_TM_TGTM)                /* EMAC0 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC0_TM_NTGTM              ((volatile uint32_t *)REG_EMAC0_TM_NTGTM)               /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC0_TM_HISEC              ((volatile uint32_t *)REG_EMAC0_TM_HISEC)               /* EMAC0 Time Stamp High Second Register */
-#define pREG_EMAC0_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC0_TM_STMPSTAT)            /* EMAC0 Time Stamp Status Register */
-#define pREG_EMAC0_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC0_TM_PPSCTL)              /* EMAC0 PPS Control Register */
-#define pREG_EMAC0_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_NSEC)        /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC0_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_SEC)         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC0_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC0_TM_PPSINTVL)            /* EMAC0 Time Stamp PPS Interval Register */
-#define pREG_EMAC0_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC0_TM_PPSWIDTH)            /* EMAC0 PPS Width Register */
-#define pREG_EMAC0_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC0_DMA_BUSMODE)            /* EMAC0 DMA Bus Mode Register */
-#define pREG_EMAC0_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_TXPOLL)             /* EMAC0 DMA Tx Poll Demand Register */
-#define pREG_EMAC0_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_RXPOLL)             /* EMAC0 DMA Rx Poll Demand register */
-#define pREG_EMAC0_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_ADDR)         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_ADDR)         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_STAT              ((volatile uint32_t *)REG_EMAC0_DMA_STAT)               /* EMAC0 DMA Status Register */
-#define pREG_EMAC0_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC0_DMA_OPMODE)             /* EMAC0 DMA Operation Mode Register */
-#define pREG_EMAC0_DMA_IEN               ((volatile uint32_t *)REG_EMAC0_DMA_IEN)                /* EMAC0 DMA Interrupt Enable Register */
-#define pREG_EMAC0_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC0_DMA_MISS_FRM)           /* EMAC0 DMA Missed Frame Register */
-#define pREG_EMAC0_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC0_DMA_RXIWDOG)            /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC0_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC0_DMA_BMMODE)             /* EMAC0 DMA SCB Bus Mode Register */
-#define pREG_EMAC0_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC0_DMA_BMSTAT)             /* EMAC0 DMA SCB Status Register */
-#define pREG_EMAC0_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_CUR)          /* EMAC0 DMA Tx Descriptor Current Register */
-#define pREG_EMAC0_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_CUR)          /* EMAC0 DMA Rx Descriptor Current Register */
-#define pREG_EMAC0_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXBUF_CUR)          /* EMAC0 DMA Tx Buffer Current Register */
-#define pREG_EMAC0_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXBUF_CUR)          /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================================================================
-       EMAC1
-   ========================================================================= */
-#define pREG_EMAC1_MACCFG                ((volatile uint32_t *)REG_EMAC1_MACCFG)                 /* EMAC1 MAC Configuration Register */
-#define pREG_EMAC1_MACFRMFILT            ((volatile uint32_t *)REG_EMAC1_MACFRMFILT)             /* EMAC1 MAC Rx Frame Filter Register */
-#define pREG_EMAC1_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC1_HASHTBL_HI)             /* EMAC1 Hash Table High Register */
-#define pREG_EMAC1_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC1_HASHTBL_LO)             /* EMAC1 Hash Table Low Register */
-#define pREG_EMAC1_SMI_ADDR              ((volatile uint32_t *)REG_EMAC1_SMI_ADDR)               /* EMAC1 SMI Address Register */
-#define pREG_EMAC1_SMI_DATA              ((volatile uint32_t *)REG_EMAC1_SMI_DATA)               /* EMAC1 SMI Data Register */
-#define pREG_EMAC1_FLOWCTL               ((volatile uint32_t *)REG_EMAC1_FLOWCTL)                /* EMAC1 FLow Control Register */
-#define pREG_EMAC1_VLANTAG               ((volatile uint32_t *)REG_EMAC1_VLANTAG)                /* EMAC1 VLAN Tag Register */
-#define pREG_EMAC1_DBG                   ((volatile uint32_t *)REG_EMAC1_DBG)                    /* EMAC1 Debug Register */
-#define pREG_EMAC1_ISTAT                 ((volatile uint32_t *)REG_EMAC1_ISTAT)                  /* EMAC1 Interrupt Status Register */
-#define pREG_EMAC1_IMSK                  ((volatile uint32_t *)REG_EMAC1_IMSK)                   /* EMAC1 Interrupt Mask Register */
-#define pREG_EMAC1_ADDR0_HI              ((volatile uint32_t *)REG_EMAC1_ADDR0_HI)               /* EMAC1 MAC Address 0 High Register */
-#define pREG_EMAC1_ADDR0_LO              ((volatile uint32_t *)REG_EMAC1_ADDR0_LO)               /* EMAC1 MAC Address 0 Low Register */
-#define pREG_EMAC1_MMC_CTL               ((volatile uint32_t *)REG_EMAC1_MMC_CTL)                /* EMAC1 MMC Control Register */
-#define pREG_EMAC1_MMC_RXINT             ((volatile uint32_t *)REG_EMAC1_MMC_RXINT)              /* EMAC1 MMC Rx Interrupt Register */
-#define pREG_EMAC1_MMC_TXINT             ((volatile uint32_t *)REG_EMAC1_MMC_TXINT)              /* EMAC1 MMC Tx Interrupt Register */
-#define pREG_EMAC1_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_RXIMSK)             /* EMAC1 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC1_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_TXIMSK)             /* EMAC1 MMC TX Interrupt Mask Register */
-#define pREG_EMAC1_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_GB)            /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC1_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_GB)            /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_G)           /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_G)           /* EMAC1 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC1_TX64_GB               ((volatile uint32_t *)REG_EMAC1_TX64_GB)                /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_TX65TO127_GB)           /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_TX128TO255_GB)          /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_TX256TO511_GB)          /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_TX512TO1023_GB)         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_TX1024TOMAX_GB)         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXUCASTFRM_GB)          /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_GB)          /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_GB)          /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC1_TXUNDR_ERR)             /* EMAC1 Tx Underflow Error Register */
-#define pREG_EMAC1_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC1_TXSNGCOL_G)             /* EMAC1 Tx Single Collision (Good) Register */
-#define pREG_EMAC1_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC1_TXMULTCOL_G)            /* EMAC1 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC1_TXDEFERRED            ((volatile uint32_t *)REG_EMAC1_TXDEFERRED)             /* EMAC1 Tx Deferred Register */
-#define pREG_EMAC1_TXLATECOL             ((volatile uint32_t *)REG_EMAC1_TXLATECOL)              /* EMAC1 Tx Late Collision Register */
-#define pREG_EMAC1_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC1_TXEXCESSCOL)            /* EMAC1 Tx Excess Collision Register */
-#define pREG_EMAC1_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC1_TXCARR_ERR)             /* EMAC1 Tx Carrier Error Register */
-#define pREG_EMAC1_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_G)             /* EMAC1 Tx Octet Count (Good) Register */
-#define pREG_EMAC1_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_G)             /* EMAC1 Tx Frame Count (Good) Register */
-#define pREG_EMAC1_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC1_TXEXCESSDEF)            /* EMAC1 Tx Excess Deferral Register */
-#define pREG_EMAC1_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_TXPAUSEFRM)             /* EMAC1 Tx Pause Frame Register */
-#define pREG_EMAC1_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC1_TXVLANFRM_G)            /* EMAC1 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC1_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXFRMCNT_GB)            /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_GB)            /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_G)             /* EMAC1 Rx Octet Count (Good) Register */
-#define pREG_EMAC1_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXBCASTFRM_G)           /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXMCASTFRM_G)           /* EMAC1 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC1_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC1_RXCRC_ERR)              /* EMAC1 Rx CRC Error Register */
-#define pREG_EMAC1_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC1_RXALIGN_ERR)            /* EMAC1 Rx alignment Error Register */
-#define pREG_EMAC1_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC1_RXRUNT_ERR)             /* EMAC1 Rx Runt Error Register */
-#define pREG_EMAC1_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC1_RXJAB_ERR)              /* EMAC1 Rx Jab Error Register */
-#define pREG_EMAC1_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXUSIZE_G)              /* EMAC1 Rx Undersize (Good) Register */
-#define pREG_EMAC1_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXOSIZE_G)              /* EMAC1 Rx Oversize (Good) Register */
-#define pREG_EMAC1_RX64_GB               ((volatile uint32_t *)REG_EMAC1_RX64_GB)                /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_RX65TO127_GB)           /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_RX128TO255_GB)          /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_RX256TO511_GB)          /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_RX512TO1023_GB)         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_RX1024TOMAX_GB)         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXUCASTFRM_G)           /* EMAC1 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC1_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC1_RXLEN_ERR)              /* EMAC1 Rx Length Error Register */
-#define pREG_EMAC1_RXOORTYPE             ((volatile uint32_t *)REG_EMAC1_RXOORTYPE)              /* EMAC1 Rx Out Of Range Type Register */
-#define pREG_EMAC1_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_RXPAUSEFRM)             /* EMAC1 Rx Pause Frames Register */
-#define pREG_EMAC1_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC1_RXFIFO_OVF)             /* EMAC1 Rx FIFO Overflow Register */
-#define pREG_EMAC1_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC1_RXVLANFRM_GB)           /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC1_RXWDOG_ERR)             /* EMAC1 Rx Watch Dog Error Register */
-#define pREG_EMAC1_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_IPC_RXIMSK)             /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC1_IPC_RXINT             ((volatile uint32_t *)REG_EMAC1_IPC_RXINT)              /* EMAC1 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC1_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_FRM)          /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_FRM)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_FRM)       /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC1_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_FRM)        /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_FRM)       /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC1_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_FRM)          /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_FRM)     /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_FRM)       /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC1_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_FRM)           /* EMAC1 Rx UDP Good Frames Register */
-#define pREG_EMAC1_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_FRM)          /* EMAC1 Rx UDP Error Frames Register */
-#define pREG_EMAC1_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_FRM)           /* EMAC1 Rx TCP Good Frames Register */
-#define pREG_EMAC1_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_FRM)          /* EMAC1 Rx TCP Error Frames Register */
-#define pREG_EMAC1_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_FRM)          /* EMAC1 Rx ICMP Good Frames Register */
-#define pREG_EMAC1_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_FRM)         /* EMAC1 Rx ICMP Error Frames Register */
-#define pREG_EMAC1_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_OCT)          /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_OCT)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_OCT)       /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC1_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_OCT)        /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_OCT)       /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC1_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_OCT)          /* EMAC1 Rx IPv6 Good Octets Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_OCT)     /* EMAC1 Rx IPv6 Header Errors Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_OCT)       /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC1_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_OCT)           /* EMAC1 Rx UDP Good Octets Register */
-#define pREG_EMAC1_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_OCT)          /* EMAC1 Rx UDP Error Octets Register */
-#define pREG_EMAC1_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_OCT)           /* EMAC1 Rx TCP Good Octets Register */
-#define pREG_EMAC1_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_OCT)          /* EMAC1 Rx TCP Error Octets Register */
-#define pREG_EMAC1_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_OCT)          /* EMAC1 Rx ICMP Good Octets Register */
-#define pREG_EMAC1_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_OCT)         /* EMAC1 Rx ICMP Error Octets Register */
-#define pREG_EMAC1_TM_CTL                ((volatile uint32_t *)REG_EMAC1_TM_CTL)                 /* EMAC1 Time Stamp Control Register */
-#define pREG_EMAC1_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC1_TM_SUBSEC)              /* EMAC1 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC1_TM_SEC                ((volatile uint32_t *)REG_EMAC1_TM_SEC)                 /* EMAC1 Time Stamp Low Seconds Register */
-#define pREG_EMAC1_TM_NSEC               ((volatile uint32_t *)REG_EMAC1_TM_NSEC)                /* EMAC1 Time Stamp Nano Seconds Register */
-#define pREG_EMAC1_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC1_TM_SECUPDT)             /* EMAC1 Time Stamp Seconds Update Register */
-#define pREG_EMAC1_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC1_TM_NSECUPDT)            /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC1_TM_ADDEND             ((volatile uint32_t *)REG_EMAC1_TM_ADDEND)              /* EMAC1 Time Stamp Addend Register */
-#define pREG_EMAC1_TM_TGTM               ((volatile uint32_t *)REG_EMAC1_TM_TGTM)                /* EMAC1 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC1_TM_NTGTM              ((volatile uint32_t *)REG_EMAC1_TM_NTGTM)               /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC1_TM_HISEC              ((volatile uint32_t *)REG_EMAC1_TM_HISEC)               /* EMAC1 Time Stamp High Second Register */
-#define pREG_EMAC1_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC1_TM_STMPSTAT)            /* EMAC1 Time Stamp Status Register */
-#define pREG_EMAC1_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC1_TM_PPSCTL)              /* EMAC1 PPS Control Register */
-#define pREG_EMAC1_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_NSEC)        /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC1_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_SEC)         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC1_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC1_TM_PPSINTVL)            /* EMAC1 Time Stamp PPS Interval Register */
-#define pREG_EMAC1_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC1_TM_PPSWIDTH)            /* EMAC1 PPS Width Register */
-#define pREG_EMAC1_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC1_DMA_BUSMODE)            /* EMAC1 DMA Bus Mode Register */
-#define pREG_EMAC1_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_TXPOLL)             /* EMAC1 DMA Tx Poll Demand Register */
-#define pREG_EMAC1_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_RXPOLL)             /* EMAC1 DMA Rx Poll Demand register */
-#define pREG_EMAC1_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_ADDR)         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_ADDR)         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_STAT              ((volatile uint32_t *)REG_EMAC1_DMA_STAT)               /* EMAC1 DMA Status Register */
-#define pREG_EMAC1_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC1_DMA_OPMODE)             /* EMAC1 DMA Operation Mode Register */
-#define pREG_EMAC1_DMA_IEN               ((volatile uint32_t *)REG_EMAC1_DMA_IEN)                /* EMAC1 DMA Interrupt Enable Register */
-#define pREG_EMAC1_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC1_DMA_MISS_FRM)           /* EMAC1 DMA Missed Frame Register */
-#define pREG_EMAC1_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC1_DMA_RXIWDOG)            /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC1_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC1_DMA_BMMODE)             /* EMAC1 DMA SCB Bus Mode Register */
-#define pREG_EMAC1_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC1_DMA_BMSTAT)             /* EMAC1 DMA SCB Status Register */
-#define pREG_EMAC1_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_CUR)          /* EMAC1 DMA Tx Descriptor Current Register */
-#define pREG_EMAC1_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_CUR)          /* EMAC1 DMA Rx Descriptor Current Register */
-#define pREG_EMAC1_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXBUF_CUR)          /* EMAC1 DMA Tx Buffer Current Register */
-#define pREG_EMAC1_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXBUF_CUR)          /* EMAC1 DMA Rx Buffer Current Register */
-
-
-/* =========================================================================
-       SPORT0
-   ========================================================================= */
-#define pREG_SPORT0_CTL_A                ((volatile uint32_t *)REG_SPORT0_CTL_A)                 /* SPORT0 Half SPORT 'A' Control Register */
-#define pREG_SPORT0_DIV_A                ((volatile uint32_t *)REG_SPORT0_DIV_A)                 /* SPORT0 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT0_MCTL_A               ((volatile uint32_t *)REG_SPORT0_MCTL_A)                /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_A                ((volatile uint32_t *)REG_SPORT0_CS0_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_A                ((volatile uint32_t *)REG_SPORT0_CS1_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_A                ((volatile uint32_t *)REG_SPORT0_CS2_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT0_CS3_A                ((volatile uint32_t *)REG_SPORT0_CS3_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT0_ERR_A                ((volatile uint32_t *)REG_SPORT0_ERR_A)                 /* SPORT0 Half SPORT 'A' Error Register */
-#define pREG_SPORT0_MSTAT_A              ((volatile uint32_t *)REG_SPORT0_MSTAT_A)               /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_A               ((volatile uint32_t *)REG_SPORT0_CTL2_A)                /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT0_TXPRI_A              ((volatile uint32_t *)REG_SPORT0_TXPRI_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_A              ((volatile uint32_t *)REG_SPORT0_RXPRI_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_A              ((volatile uint32_t *)REG_SPORT0_TXSEC_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_A              ((volatile uint32_t *)REG_SPORT0_RXSEC_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT0_CTL_B                ((volatile uint32_t *)REG_SPORT0_CTL_B)                 /* SPORT0 Half SPORT 'B' Control Register */
-#define pREG_SPORT0_DIV_B                ((volatile uint32_t *)REG_SPORT0_DIV_B)                 /* SPORT0 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT0_MCTL_B               ((volatile uint32_t *)REG_SPORT0_MCTL_B)                /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_B                ((volatile uint32_t *)REG_SPORT0_CS0_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_B                ((volatile uint32_t *)REG_SPORT0_CS1_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_B                ((volatile uint32_t *)REG_SPORT0_CS2_B)                 /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT0_CS3_B                ((volatile uint32_t *)REG_SPORT0_CS3_B)                 /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT0_ERR_B                ((volatile uint32_t *)REG_SPORT0_ERR_B)                 /* SPORT0 Half SPORT 'B' Error Register */
-#define pREG_SPORT0_MSTAT_B              ((volatile uint32_t *)REG_SPORT0_MSTAT_B)               /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_B               ((volatile uint32_t *)REG_SPORT0_CTL2_B)                /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT0_TXPRI_B              ((volatile uint32_t *)REG_SPORT0_TXPRI_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_B              ((volatile uint32_t *)REG_SPORT0_RXPRI_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_B              ((volatile uint32_t *)REG_SPORT0_TXSEC_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_B              ((volatile uint32_t *)REG_SPORT0_RXSEC_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT1
-   ========================================================================= */
-#define pREG_SPORT1_CTL_A                ((volatile uint32_t *)REG_SPORT1_CTL_A)                 /* SPORT1 Half SPORT 'A' Control Register */
-#define pREG_SPORT1_DIV_A                ((volatile uint32_t *)REG_SPORT1_DIV_A)                 /* SPORT1 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT1_MCTL_A               ((volatile uint32_t *)REG_SPORT1_MCTL_A)                /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_A                ((volatile uint32_t *)REG_SPORT1_CS0_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_A                ((volatile uint32_t *)REG_SPORT1_CS1_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_A                ((volatile uint32_t *)REG_SPORT1_CS2_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT1_CS3_A                ((volatile uint32_t *)REG_SPORT1_CS3_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT1_ERR_A                ((volatile uint32_t *)REG_SPORT1_ERR_A)                 /* SPORT1 Half SPORT 'A' Error Register */
-#define pREG_SPORT1_MSTAT_A              ((volatile uint32_t *)REG_SPORT1_MSTAT_A)               /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_A               ((volatile uint32_t *)REG_SPORT1_CTL2_A)                /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT1_TXPRI_A              ((volatile uint32_t *)REG_SPORT1_TXPRI_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_A              ((volatile uint32_t *)REG_SPORT1_RXPRI_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_A              ((volatile uint32_t *)REG_SPORT1_TXSEC_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_A              ((volatile uint32_t *)REG_SPORT1_RXSEC_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT1_CTL_B                ((volatile uint32_t *)REG_SPORT1_CTL_B)                 /* SPORT1 Half SPORT 'B' Control Register */
-#define pREG_SPORT1_DIV_B                ((volatile uint32_t *)REG_SPORT1_DIV_B)                 /* SPORT1 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT1_MCTL_B               ((volatile uint32_t *)REG_SPORT1_MCTL_B)                /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_B                ((volatile uint32_t *)REG_SPORT1_CS0_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_B                ((volatile uint32_t *)REG_SPORT1_CS1_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_B                ((volatile uint32_t *)REG_SPORT1_CS2_B)                 /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT1_CS3_B                ((volatile uint32_t *)REG_SPORT1_CS3_B)                 /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT1_ERR_B                ((volatile uint32_t *)REG_SPORT1_ERR_B)                 /* SPORT1 Half SPORT 'B' Error Register */
-#define pREG_SPORT1_MSTAT_B              ((volatile uint32_t *)REG_SPORT1_MSTAT_B)               /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_B               ((volatile uint32_t *)REG_SPORT1_CTL2_B)                /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT1_TXPRI_B              ((volatile uint32_t *)REG_SPORT1_TXPRI_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_B              ((volatile uint32_t *)REG_SPORT1_RXPRI_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_B              ((volatile uint32_t *)REG_SPORT1_TXSEC_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_B              ((volatile uint32_t *)REG_SPORT1_RXSEC_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT2
-   ========================================================================= */
-#define pREG_SPORT2_CTL_A                ((volatile uint32_t *)REG_SPORT2_CTL_A)                 /* SPORT2 Half SPORT 'A' Control Register */
-#define pREG_SPORT2_DIV_A                ((volatile uint32_t *)REG_SPORT2_DIV_A)                 /* SPORT2 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT2_MCTL_A               ((volatile uint32_t *)REG_SPORT2_MCTL_A)                /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_A                ((volatile uint32_t *)REG_SPORT2_CS0_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_A                ((volatile uint32_t *)REG_SPORT2_CS1_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_A                ((volatile uint32_t *)REG_SPORT2_CS2_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT2_CS3_A                ((volatile uint32_t *)REG_SPORT2_CS3_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT2_ERR_A                ((volatile uint32_t *)REG_SPORT2_ERR_A)                 /* SPORT2 Half SPORT 'A' Error Register */
-#define pREG_SPORT2_MSTAT_A              ((volatile uint32_t *)REG_SPORT2_MSTAT_A)               /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_A               ((volatile uint32_t *)REG_SPORT2_CTL2_A)                /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT2_TXPRI_A              ((volatile uint32_t *)REG_SPORT2_TXPRI_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_A              ((volatile uint32_t *)REG_SPORT2_RXPRI_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_A              ((volatile uint32_t *)REG_SPORT2_TXSEC_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_A              ((volatile uint32_t *)REG_SPORT2_RXSEC_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT2_CTL_B                ((volatile uint32_t *)REG_SPORT2_CTL_B)                 /* SPORT2 Half SPORT 'B' Control Register */
-#define pREG_SPORT2_DIV_B                ((volatile uint32_t *)REG_SPORT2_DIV_B)                 /* SPORT2 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT2_MCTL_B               ((volatile uint32_t *)REG_SPORT2_MCTL_B)                /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_B                ((volatile uint32_t *)REG_SPORT2_CS0_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_B                ((volatile uint32_t *)REG_SPORT2_CS1_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_B                ((volatile uint32_t *)REG_SPORT2_CS2_B)                 /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT2_CS3_B                ((volatile uint32_t *)REG_SPORT2_CS3_B)                 /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT2_ERR_B                ((volatile uint32_t *)REG_SPORT2_ERR_B)                 /* SPORT2 Half SPORT 'B' Error Register */
-#define pREG_SPORT2_MSTAT_B              ((volatile uint32_t *)REG_SPORT2_MSTAT_B)               /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_B               ((volatile uint32_t *)REG_SPORT2_CTL2_B)                /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT2_TXPRI_B              ((volatile uint32_t *)REG_SPORT2_TXPRI_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_B              ((volatile uint32_t *)REG_SPORT2_RXPRI_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_B              ((volatile uint32_t *)REG_SPORT2_TXSEC_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_B              ((volatile uint32_t *)REG_SPORT2_RXSEC_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-
-/* =========================================================================
-       SPI0
-   ========================================================================= */
-#define pREG_SPI0_CTL                    ((volatile uint32_t *)REG_SPI0_CTL)                     /* SPI0 Control Register */
-#define pREG_SPI0_RXCTL                  ((volatile uint32_t *)REG_SPI0_RXCTL)                   /* SPI0 Receive Control Register */
-#define pREG_SPI0_TXCTL                  ((volatile uint32_t *)REG_SPI0_TXCTL)                   /* SPI0 Transmit Control Register */
-#define pREG_SPI0_CLK                    ((volatile uint32_t *)REG_SPI0_CLK)                     /* SPI0 Clock Rate Register */
-#define pREG_SPI0_DLY                    ((volatile uint32_t *)REG_SPI0_DLY)                     /* SPI0 Delay Register */
-#define pREG_SPI0_SLVSEL                 ((volatile uint32_t *)REG_SPI0_SLVSEL)                  /* SPI0 Slave Select Register */
-#define pREG_SPI0_RWC                    ((volatile uint32_t *)REG_SPI0_RWC)                     /* SPI0 Received Word Count Register */
-#define pREG_SPI0_RWCR                   ((volatile uint32_t *)REG_SPI0_RWCR)                    /* SPI0 Received Word Count Reload Register */
-#define pREG_SPI0_TWC                    ((volatile uint32_t *)REG_SPI0_TWC)                     /* SPI0 Transmitted Word Count Register */
-#define pREG_SPI0_TWCR                   ((volatile uint32_t *)REG_SPI0_TWCR)                    /* SPI0 Transmitted Word Count Reload Register */
-#define pREG_SPI0_IMSK                   ((volatile uint32_t *)REG_SPI0_IMSK)                    /* SPI0 Interrupt Mask Register */
-#define pREG_SPI0_IMSK_CLR               ((volatile uint32_t *)REG_SPI0_IMSK_CLR)                /* SPI0 Interrupt Mask Clear Register */
-#define pREG_SPI0_IMSK_SET               ((volatile uint32_t *)REG_SPI0_IMSK_SET)                /* SPI0 Interrupt Mask Set Register */
-#define pREG_SPI0_STAT                   ((volatile uint32_t *)REG_SPI0_STAT)                    /* SPI0 Status Register */
-#define pREG_SPI0_ILAT                   ((volatile uint32_t *)REG_SPI0_ILAT)                    /* SPI0 Masked Interrupt Condition Register */
-#define pREG_SPI0_ILAT_CLR               ((volatile uint32_t *)REG_SPI0_ILAT_CLR)                /* SPI0 Masked Interrupt Clear Register */
-#define pREG_SPI0_RFIFO                  ((volatile uint32_t *)REG_SPI0_RFIFO)                   /* SPI0 Receive FIFO Data Register */
-#define pREG_SPI0_TFIFO                  ((volatile uint32_t *)REG_SPI0_TFIFO)                   /* SPI0 Transmit FIFO Data Register */
-
-/* =========================================================================
-       SPI1
-   ========================================================================= */
-#define pREG_SPI1_CTL                    ((volatile uint32_t *)REG_SPI1_CTL)                     /* SPI1 Control Register */
-#define pREG_SPI1_RXCTL                  ((volatile uint32_t *)REG_SPI1_RXCTL)                   /* SPI1 Receive Control Register */
-#define pREG_SPI1_TXCTL                  ((volatile uint32_t *)REG_SPI1_TXCTL)                   /* SPI1 Transmit Control Register */
-#define pREG_SPI1_CLK                    ((volatile uint32_t *)REG_SPI1_CLK)                     /* SPI1 Clock Rate Register */
-#define pREG_SPI1_DLY                    ((volatile uint32_t *)REG_SPI1_DLY)                     /* SPI1 Delay Register */
-#define pREG_SPI1_SLVSEL                 ((volatile uint32_t *)REG_SPI1_SLVSEL)                  /* SPI1 Slave Select Register */
-#define pREG_SPI1_RWC                    ((volatile uint32_t *)REG_SPI1_RWC)                     /* SPI1 Received Word Count Register */
-#define pREG_SPI1_RWCR                   ((volatile uint32_t *)REG_SPI1_RWCR)                    /* SPI1 Received Word Count Reload Register */
-#define pREG_SPI1_TWC                    ((volatile uint32_t *)REG_SPI1_TWC)                     /* SPI1 Transmitted Word Count Register */
-#define pREG_SPI1_TWCR                   ((volatile uint32_t *)REG_SPI1_TWCR)                    /* SPI1 Transmitted Word Count Reload Register */
-#define pREG_SPI1_IMSK                   ((volatile uint32_t *)REG_SPI1_IMSK)                    /* SPI1 Interrupt Mask Register */
-#define pREG_SPI1_IMSK_CLR               ((volatile uint32_t *)REG_SPI1_IMSK_CLR)                /* SPI1 Interrupt Mask Clear Register */
-#define pREG_SPI1_IMSK_SET               ((volatile uint32_t *)REG_SPI1_IMSK_SET)                /* SPI1 Interrupt Mask Set Register */
-#define pREG_SPI1_STAT                   ((volatile uint32_t *)REG_SPI1_STAT)                    /* SPI1 Status Register */
-#define pREG_SPI1_ILAT                   ((volatile uint32_t *)REG_SPI1_ILAT)                    /* SPI1 Masked Interrupt Condition Register */
-#define pREG_SPI1_ILAT_CLR               ((volatile uint32_t *)REG_SPI1_ILAT_CLR)                /* SPI1 Masked Interrupt Clear Register */
-#define pREG_SPI1_RFIFO                  ((volatile uint32_t *)REG_SPI1_RFIFO)                   /* SPI1 Receive FIFO Data Register */
-#define pREG_SPI1_TFIFO                  ((volatile uint32_t *)REG_SPI1_TFIFO)                   /* SPI1 Transmit FIFO Data Register */
-
-
-/* =========================================================================
-       DMA0
-   ========================================================================= */
-#define pREG_DMA0_DSCPTR_NXT             ((void * volatile *)REG_DMA0_DSCPTR_NXT)                /* DMA0 Pointer to Next Initial Descriptor */
-#define pREG_DMA0_ADDRSTART              ((void * volatile *)REG_DMA0_ADDRSTART)                 /* DMA0 Start Address of Current Buffer */
-#define pREG_DMA0_CFG                    ((volatile uint32_t *)REG_DMA0_CFG)                     /* DMA0 Configuration Register */
-#define pREG_DMA0_XCNT                   ((volatile uint32_t *)REG_DMA0_XCNT)                    /* DMA0 Inner Loop Count Start Value */
-#define pREG_DMA0_XMOD                   ((volatile  int32_t *)REG_DMA0_XMOD)                    /* DMA0 Inner Loop Address Increment */
-#define pREG_DMA0_YCNT                   ((volatile uint32_t *)REG_DMA0_YCNT)                    /* DMA0 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA0_YMOD                   ((volatile  int32_t *)REG_DMA0_YMOD)                    /* DMA0 Outer Loop Address Increment (2D only) */
-#define pREG_DMA0_DSCPTR_CUR             ((void * volatile *)REG_DMA0_DSCPTR_CUR)                /* DMA0 Current Descriptor Pointer */
-#define pREG_DMA0_DSCPTR_PRV             ((void * volatile *)REG_DMA0_DSCPTR_PRV)                /* DMA0 Previous Initial Descriptor Pointer */
-#define pREG_DMA0_ADDR_CUR               ((void * volatile *)REG_DMA0_ADDR_CUR)                  /* DMA0 Current Address */
-#define pREG_DMA0_STAT                   ((volatile uint32_t *)REG_DMA0_STAT)                    /* DMA0 Status Register */
-#define pREG_DMA0_XCNT_CUR               ((volatile uint32_t *)REG_DMA0_XCNT_CUR)                /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA0_YCNT_CUR               ((volatile uint32_t *)REG_DMA0_YCNT_CUR)                /* DMA0 Current Row Count (2D only) */
-#define pREG_DMA0_BWLCNT                 ((volatile uint32_t *)REG_DMA0_BWLCNT)                  /* DMA0 Bandwidth Limit Count */
-#define pREG_DMA0_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWLCNT_CUR)              /* DMA0 Bandwidth Limit Count Current */
-#define pREG_DMA0_BWMCNT                 ((volatile uint32_t *)REG_DMA0_BWMCNT)                  /* DMA0 Bandwidth Monitor Count */
-#define pREG_DMA0_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWMCNT_CUR)              /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA1
-   ========================================================================= */
-#define pREG_DMA1_DSCPTR_NXT             ((void * volatile *)REG_DMA1_DSCPTR_NXT)                /* DMA1 Pointer to Next Initial Descriptor */
-#define pREG_DMA1_ADDRSTART              ((void * volatile *)REG_DMA1_ADDRSTART)                 /* DMA1 Start Address of Current Buffer */
-#define pREG_DMA1_CFG                    ((volatile uint32_t *)REG_DMA1_CFG)                     /* DMA1 Configuration Register */
-#define pREG_DMA1_XCNT                   ((volatile uint32_t *)REG_DMA1_XCNT)                    /* DMA1 Inner Loop Count Start Value */
-#define pREG_DMA1_XMOD                   ((volatile  int32_t *)REG_DMA1_XMOD)                    /* DMA1 Inner Loop Address Increment */
-#define pREG_DMA1_YCNT                   ((volatile uint32_t *)REG_DMA1_YCNT)                    /* DMA1 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA1_YMOD                   ((volatile  int32_t *)REG_DMA1_YMOD)                    /* DMA1 Outer Loop Address Increment (2D only) */
-#define pREG_DMA1_DSCPTR_CUR             ((void * volatile *)REG_DMA1_DSCPTR_CUR)                /* DMA1 Current Descriptor Pointer */
-#define pREG_DMA1_DSCPTR_PRV             ((void * volatile *)REG_DMA1_DSCPTR_PRV)                /* DMA1 Previous Initial Descriptor Pointer */
-#define pREG_DMA1_ADDR_CUR               ((void * volatile *)REG_DMA1_ADDR_CUR)                  /* DMA1 Current Address */
-#define pREG_DMA1_STAT                   ((volatile uint32_t *)REG_DMA1_STAT)                    /* DMA1 Status Register */
-#define pREG_DMA1_XCNT_CUR               ((volatile uint32_t *)REG_DMA1_XCNT_CUR)                /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA1_YCNT_CUR               ((volatile uint32_t *)REG_DMA1_YCNT_CUR)                /* DMA1 Current Row Count (2D only) */
-#define pREG_DMA1_BWLCNT                 ((volatile uint32_t *)REG_DMA1_BWLCNT)                  /* DMA1 Bandwidth Limit Count */
-#define pREG_DMA1_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWLCNT_CUR)              /* DMA1 Bandwidth Limit Count Current */
-#define pREG_DMA1_BWMCNT                 ((volatile uint32_t *)REG_DMA1_BWMCNT)                  /* DMA1 Bandwidth Monitor Count */
-#define pREG_DMA1_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWMCNT_CUR)              /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA2
-   ========================================================================= */
-#define pREG_DMA2_DSCPTR_NXT             ((void * volatile *)REG_DMA2_DSCPTR_NXT)                /* DMA2 Pointer to Next Initial Descriptor */
-#define pREG_DMA2_ADDRSTART              ((void * volatile *)REG_DMA2_ADDRSTART)                 /* DMA2 Start Address of Current Buffer */
-#define pREG_DMA2_CFG                    ((volatile uint32_t *)REG_DMA2_CFG)                     /* DMA2 Configuration Register */
-#define pREG_DMA2_XCNT                   ((volatile uint32_t *)REG_DMA2_XCNT)                    /* DMA2 Inner Loop Count Start Value */
-#define pREG_DMA2_XMOD                   ((volatile  int32_t *)REG_DMA2_XMOD)                    /* DMA2 Inner Loop Address Increment */
-#define pREG_DMA2_YCNT                   ((volatile uint32_t *)REG_DMA2_YCNT)                    /* DMA2 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA2_YMOD                   ((volatile  int32_t *)REG_DMA2_YMOD)                    /* DMA2 Outer Loop Address Increment (2D only) */
-#define pREG_DMA2_DSCPTR_CUR             ((void * volatile *)REG_DMA2_DSCPTR_CUR)                /* DMA2 Current Descriptor Pointer */
-#define pREG_DMA2_DSCPTR_PRV             ((void * volatile *)REG_DMA2_DSCPTR_PRV)                /* DMA2 Previous Initial Descriptor Pointer */
-#define pREG_DMA2_ADDR_CUR               ((void * volatile *)REG_DMA2_ADDR_CUR)                  /* DMA2 Current Address */
-#define pREG_DMA2_STAT                   ((volatile uint32_t *)REG_DMA2_STAT)                    /* DMA2 Status Register */
-#define pREG_DMA2_XCNT_CUR               ((volatile uint32_t *)REG_DMA2_XCNT_CUR)                /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA2_YCNT_CUR               ((volatile uint32_t *)REG_DMA2_YCNT_CUR)                /* DMA2 Current Row Count (2D only) */
-#define pREG_DMA2_BWLCNT                 ((volatile uint32_t *)REG_DMA2_BWLCNT)                  /* DMA2 Bandwidth Limit Count */
-#define pREG_DMA2_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWLCNT_CUR)              /* DMA2 Bandwidth Limit Count Current */
-#define pREG_DMA2_BWMCNT                 ((volatile uint32_t *)REG_DMA2_BWMCNT)                  /* DMA2 Bandwidth Monitor Count */
-#define pREG_DMA2_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWMCNT_CUR)              /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA3
-   ========================================================================= */
-#define pREG_DMA3_DSCPTR_NXT             ((void * volatile *)REG_DMA3_DSCPTR_NXT)                /* DMA3 Pointer to Next Initial Descriptor */
-#define pREG_DMA3_ADDRSTART              ((void * volatile *)REG_DMA3_ADDRSTART)                 /* DMA3 Start Address of Current Buffer */
-#define pREG_DMA3_CFG                    ((volatile uint32_t *)REG_DMA3_CFG)                     /* DMA3 Configuration Register */
-#define pREG_DMA3_XCNT                   ((volatile uint32_t *)REG_DMA3_XCNT)                    /* DMA3 Inner Loop Count Start Value */
-#define pREG_DMA3_XMOD                   ((volatile  int32_t *)REG_DMA3_XMOD)                    /* DMA3 Inner Loop Address Increment */
-#define pREG_DMA3_YCNT                   ((volatile uint32_t *)REG_DMA3_YCNT)                    /* DMA3 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA3_YMOD                   ((volatile  int32_t *)REG_DMA3_YMOD)                    /* DMA3 Outer Loop Address Increment (2D only) */
-#define pREG_DMA3_DSCPTR_CUR             ((void * volatile *)REG_DMA3_DSCPTR_CUR)                /* DMA3 Current Descriptor Pointer */
-#define pREG_DMA3_DSCPTR_PRV             ((void * volatile *)REG_DMA3_DSCPTR_PRV)                /* DMA3 Previous Initial Descriptor Pointer */
-#define pREG_DMA3_ADDR_CUR               ((void * volatile *)REG_DMA3_ADDR_CUR)                  /* DMA3 Current Address */
-#define pREG_DMA3_STAT                   ((volatile uint32_t *)REG_DMA3_STAT)                    /* DMA3 Status Register */
-#define pREG_DMA3_XCNT_CUR               ((volatile uint32_t *)REG_DMA3_XCNT_CUR)                /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA3_YCNT_CUR               ((volatile uint32_t *)REG_DMA3_YCNT_CUR)                /* DMA3 Current Row Count (2D only) */
-#define pREG_DMA3_BWLCNT                 ((volatile uint32_t *)REG_DMA3_BWLCNT)                  /* DMA3 Bandwidth Limit Count */
-#define pREG_DMA3_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWLCNT_CUR)              /* DMA3 Bandwidth Limit Count Current */
-#define pREG_DMA3_BWMCNT                 ((volatile uint32_t *)REG_DMA3_BWMCNT)                  /* DMA3 Bandwidth Monitor Count */
-#define pREG_DMA3_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWMCNT_CUR)              /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA4
-   ========================================================================= */
-#define pREG_DMA4_DSCPTR_NXT             ((void * volatile *)REG_DMA4_DSCPTR_NXT)                /* DMA4 Pointer to Next Initial Descriptor */
-#define pREG_DMA4_ADDRSTART              ((void * volatile *)REG_DMA4_ADDRSTART)                 /* DMA4 Start Address of Current Buffer */
-#define pREG_DMA4_CFG                    ((volatile uint32_t *)REG_DMA4_CFG)                     /* DMA4 Configuration Register */
-#define pREG_DMA4_XCNT                   ((volatile uint32_t *)REG_DMA4_XCNT)                    /* DMA4 Inner Loop Count Start Value */
-#define pREG_DMA4_XMOD                   ((volatile  int32_t *)REG_DMA4_XMOD)                    /* DMA4 Inner Loop Address Increment */
-#define pREG_DMA4_YCNT                   ((volatile uint32_t *)REG_DMA4_YCNT)                    /* DMA4 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA4_YMOD                   ((volatile  int32_t *)REG_DMA4_YMOD)                    /* DMA4 Outer Loop Address Increment (2D only) */
-#define pREG_DMA4_DSCPTR_CUR             ((void * volatile *)REG_DMA4_DSCPTR_CUR)                /* DMA4 Current Descriptor Pointer */
-#define pREG_DMA4_DSCPTR_PRV             ((void * volatile *)REG_DMA4_DSCPTR_PRV)                /* DMA4 Previous Initial Descriptor Pointer */
-#define pREG_DMA4_ADDR_CUR               ((void * volatile *)REG_DMA4_ADDR_CUR)                  /* DMA4 Current Address */
-#define pREG_DMA4_STAT                   ((volatile uint32_t *)REG_DMA4_STAT)                    /* DMA4 Status Register */
-#define pREG_DMA4_XCNT_CUR               ((volatile uint32_t *)REG_DMA4_XCNT_CUR)                /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA4_YCNT_CUR               ((volatile uint32_t *)REG_DMA4_YCNT_CUR)                /* DMA4 Current Row Count (2D only) */
-#define pREG_DMA4_BWLCNT                 ((volatile uint32_t *)REG_DMA4_BWLCNT)                  /* DMA4 Bandwidth Limit Count */
-#define pREG_DMA4_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWLCNT_CUR)              /* DMA4 Bandwidth Limit Count Current */
-#define pREG_DMA4_BWMCNT                 ((volatile uint32_t *)REG_DMA4_BWMCNT)                  /* DMA4 Bandwidth Monitor Count */
-#define pREG_DMA4_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWMCNT_CUR)              /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA5
-   ========================================================================= */
-#define pREG_DMA5_DSCPTR_NXT             ((void * volatile *)REG_DMA5_DSCPTR_NXT)                /* DMA5 Pointer to Next Initial Descriptor */
-#define pREG_DMA5_ADDRSTART              ((void * volatile *)REG_DMA5_ADDRSTART)                 /* DMA5 Start Address of Current Buffer */
-#define pREG_DMA5_CFG                    ((volatile uint32_t *)REG_DMA5_CFG)                     /* DMA5 Configuration Register */
-#define pREG_DMA5_XCNT                   ((volatile uint32_t *)REG_DMA5_XCNT)                    /* DMA5 Inner Loop Count Start Value */
-#define pREG_DMA5_XMOD                   ((volatile  int32_t *)REG_DMA5_XMOD)                    /* DMA5 Inner Loop Address Increment */
-#define pREG_DMA5_YCNT                   ((volatile uint32_t *)REG_DMA5_YCNT)                    /* DMA5 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA5_YMOD                   ((volatile  int32_t *)REG_DMA5_YMOD)                    /* DMA5 Outer Loop Address Increment (2D only) */
-#define pREG_DMA5_DSCPTR_CUR             ((void * volatile *)REG_DMA5_DSCPTR_CUR)                /* DMA5 Current Descriptor Pointer */
-#define pREG_DMA5_DSCPTR_PRV             ((void * volatile *)REG_DMA5_DSCPTR_PRV)                /* DMA5 Previous Initial Descriptor Pointer */
-#define pREG_DMA5_ADDR_CUR               ((void * volatile *)REG_DMA5_ADDR_CUR)                  /* DMA5 Current Address */
-#define pREG_DMA5_STAT                   ((volatile uint32_t *)REG_DMA5_STAT)                    /* DMA5 Status Register */
-#define pREG_DMA5_XCNT_CUR               ((volatile uint32_t *)REG_DMA5_XCNT_CUR)                /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA5_YCNT_CUR               ((volatile uint32_t *)REG_DMA5_YCNT_CUR)                /* DMA5 Current Row Count (2D only) */
-#define pREG_DMA5_BWLCNT                 ((volatile uint32_t *)REG_DMA5_BWLCNT)                  /* DMA5 Bandwidth Limit Count */
-#define pREG_DMA5_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWLCNT_CUR)              /* DMA5 Bandwidth Limit Count Current */
-#define pREG_DMA5_BWMCNT                 ((volatile uint32_t *)REG_DMA5_BWMCNT)                  /* DMA5 Bandwidth Monitor Count */
-#define pREG_DMA5_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWMCNT_CUR)              /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA6
-   ========================================================================= */
-#define pREG_DMA6_DSCPTR_NXT             ((void * volatile *)REG_DMA6_DSCPTR_NXT)                /* DMA6 Pointer to Next Initial Descriptor */
-#define pREG_DMA6_ADDRSTART              ((void * volatile *)REG_DMA6_ADDRSTART)                 /* DMA6 Start Address of Current Buffer */
-#define pREG_DMA6_CFG                    ((volatile uint32_t *)REG_DMA6_CFG)                     /* DMA6 Configuration Register */
-#define pREG_DMA6_XCNT                   ((volatile uint32_t *)REG_DMA6_XCNT)                    /* DMA6 Inner Loop Count Start Value */
-#define pREG_DMA6_XMOD                   ((volatile  int32_t *)REG_DMA6_XMOD)                    /* DMA6 Inner Loop Address Increment */
-#define pREG_DMA6_YCNT                   ((volatile uint32_t *)REG_DMA6_YCNT)                    /* DMA6 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA6_YMOD                   ((volatile  int32_t *)REG_DMA6_YMOD)                    /* DMA6 Outer Loop Address Increment (2D only) */
-#define pREG_DMA6_DSCPTR_CUR             ((void * volatile *)REG_DMA6_DSCPTR_CUR)                /* DMA6 Current Descriptor Pointer */
-#define pREG_DMA6_DSCPTR_PRV             ((void * volatile *)REG_DMA6_DSCPTR_PRV)                /* DMA6 Previous Initial Descriptor Pointer */
-#define pREG_DMA6_ADDR_CUR               ((void * volatile *)REG_DMA6_ADDR_CUR)                  /* DMA6 Current Address */
-#define pREG_DMA6_STAT                   ((volatile uint32_t *)REG_DMA6_STAT)                    /* DMA6 Status Register */
-#define pREG_DMA6_XCNT_CUR               ((volatile uint32_t *)REG_DMA6_XCNT_CUR)                /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA6_YCNT_CUR               ((volatile uint32_t *)REG_DMA6_YCNT_CUR)                /* DMA6 Current Row Count (2D only) */
-#define pREG_DMA6_BWLCNT                 ((volatile uint32_t *)REG_DMA6_BWLCNT)                  /* DMA6 Bandwidth Limit Count */
-#define pREG_DMA6_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWLCNT_CUR)              /* DMA6 Bandwidth Limit Count Current */
-#define pREG_DMA6_BWMCNT                 ((volatile uint32_t *)REG_DMA6_BWMCNT)                  /* DMA6 Bandwidth Monitor Count */
-#define pREG_DMA6_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWMCNT_CUR)              /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA7
-   ========================================================================= */
-#define pREG_DMA7_DSCPTR_NXT             ((void * volatile *)REG_DMA7_DSCPTR_NXT)                /* DMA7 Pointer to Next Initial Descriptor */
-#define pREG_DMA7_ADDRSTART              ((void * volatile *)REG_DMA7_ADDRSTART)                 /* DMA7 Start Address of Current Buffer */
-#define pREG_DMA7_CFG                    ((volatile uint32_t *)REG_DMA7_CFG)                     /* DMA7 Configuration Register */
-#define pREG_DMA7_XCNT                   ((volatile uint32_t *)REG_DMA7_XCNT)                    /* DMA7 Inner Loop Count Start Value */
-#define pREG_DMA7_XMOD                   ((volatile  int32_t *)REG_DMA7_XMOD)                    /* DMA7 Inner Loop Address Increment */
-#define pREG_DMA7_YCNT                   ((volatile uint32_t *)REG_DMA7_YCNT)                    /* DMA7 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA7_YMOD                   ((volatile  int32_t *)REG_DMA7_YMOD)                    /* DMA7 Outer Loop Address Increment (2D only) */
-#define pREG_DMA7_DSCPTR_CUR             ((void * volatile *)REG_DMA7_DSCPTR_CUR)                /* DMA7 Current Descriptor Pointer */
-#define pREG_DMA7_DSCPTR_PRV             ((void * volatile *)REG_DMA7_DSCPTR_PRV)                /* DMA7 Previous Initial Descriptor Pointer */
-#define pREG_DMA7_ADDR_CUR               ((void * volatile *)REG_DMA7_ADDR_CUR)                  /* DMA7 Current Address */
-#define pREG_DMA7_STAT                   ((volatile uint32_t *)REG_DMA7_STAT)                    /* DMA7 Status Register */
-#define pREG_DMA7_XCNT_CUR               ((volatile uint32_t *)REG_DMA7_XCNT_CUR)                /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA7_YCNT_CUR               ((volatile uint32_t *)REG_DMA7_YCNT_CUR)                /* DMA7 Current Row Count (2D only) */
-#define pREG_DMA7_BWLCNT                 ((volatile uint32_t *)REG_DMA7_BWLCNT)                  /* DMA7 Bandwidth Limit Count */
-#define pREG_DMA7_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWLCNT_CUR)              /* DMA7 Bandwidth Limit Count Current */
-#define pREG_DMA7_BWMCNT                 ((volatile uint32_t *)REG_DMA7_BWMCNT)                  /* DMA7 Bandwidth Monitor Count */
-#define pREG_DMA7_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWMCNT_CUR)              /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA8
-   ========================================================================= */
-#define pREG_DMA8_DSCPTR_NXT             ((void * volatile *)REG_DMA8_DSCPTR_NXT)                /* DMA8 Pointer to Next Initial Descriptor */
-#define pREG_DMA8_ADDRSTART              ((void * volatile *)REG_DMA8_ADDRSTART)                 /* DMA8 Start Address of Current Buffer */
-#define pREG_DMA8_CFG                    ((volatile uint32_t *)REG_DMA8_CFG)                     /* DMA8 Configuration Register */
-#define pREG_DMA8_XCNT                   ((volatile uint32_t *)REG_DMA8_XCNT)                    /* DMA8 Inner Loop Count Start Value */
-#define pREG_DMA8_XMOD                   ((volatile  int32_t *)REG_DMA8_XMOD)                    /* DMA8 Inner Loop Address Increment */
-#define pREG_DMA8_YCNT                   ((volatile uint32_t *)REG_DMA8_YCNT)                    /* DMA8 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA8_YMOD                   ((volatile  int32_t *)REG_DMA8_YMOD)                    /* DMA8 Outer Loop Address Increment (2D only) */
-#define pREG_DMA8_DSCPTR_CUR             ((void * volatile *)REG_DMA8_DSCPTR_CUR)                /* DMA8 Current Descriptor Pointer */
-#define pREG_DMA8_DSCPTR_PRV             ((void * volatile *)REG_DMA8_DSCPTR_PRV)                /* DMA8 Previous Initial Descriptor Pointer */
-#define pREG_DMA8_ADDR_CUR               ((void * volatile *)REG_DMA8_ADDR_CUR)                  /* DMA8 Current Address */
-#define pREG_DMA8_STAT                   ((volatile uint32_t *)REG_DMA8_STAT)                    /* DMA8 Status Register */
-#define pREG_DMA8_XCNT_CUR               ((volatile uint32_t *)REG_DMA8_XCNT_CUR)                /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA8_YCNT_CUR               ((volatile uint32_t *)REG_DMA8_YCNT_CUR)                /* DMA8 Current Row Count (2D only) */
-#define pREG_DMA8_BWLCNT                 ((volatile uint32_t *)REG_DMA8_BWLCNT)                  /* DMA8 Bandwidth Limit Count */
-#define pREG_DMA8_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWLCNT_CUR)              /* DMA8 Bandwidth Limit Count Current */
-#define pREG_DMA8_BWMCNT                 ((volatile uint32_t *)REG_DMA8_BWMCNT)                  /* DMA8 Bandwidth Monitor Count */
-#define pREG_DMA8_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWMCNT_CUR)              /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA9
-   ========================================================================= */
-#define pREG_DMA9_DSCPTR_NXT             ((void * volatile *)REG_DMA9_DSCPTR_NXT)                /* DMA9 Pointer to Next Initial Descriptor */
-#define pREG_DMA9_ADDRSTART              ((void * volatile *)REG_DMA9_ADDRSTART)                 /* DMA9 Start Address of Current Buffer */
-#define pREG_DMA9_CFG                    ((volatile uint32_t *)REG_DMA9_CFG)                     /* DMA9 Configuration Register */
-#define pREG_DMA9_XCNT                   ((volatile uint32_t *)REG_DMA9_XCNT)                    /* DMA9 Inner Loop Count Start Value */
-#define pREG_DMA9_XMOD                   ((volatile  int32_t *)REG_DMA9_XMOD)                    /* DMA9 Inner Loop Address Increment */
-#define pREG_DMA9_YCNT                   ((volatile uint32_t *)REG_DMA9_YCNT)                    /* DMA9 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA9_YMOD                   ((volatile  int32_t *)REG_DMA9_YMOD)                    /* DMA9 Outer Loop Address Increment (2D only) */
-#define pREG_DMA9_DSCPTR_CUR             ((void * volatile *)REG_DMA9_DSCPTR_CUR)                /* DMA9 Current Descriptor Pointer */
-#define pREG_DMA9_DSCPTR_PRV             ((void * volatile *)REG_DMA9_DSCPTR_PRV)                /* DMA9 Previous Initial Descriptor Pointer */
-#define pREG_DMA9_ADDR_CUR               ((void * volatile *)REG_DMA9_ADDR_CUR)                  /* DMA9 Current Address */
-#define pREG_DMA9_STAT                   ((volatile uint32_t *)REG_DMA9_STAT)                    /* DMA9 Status Register */
-#define pREG_DMA9_XCNT_CUR               ((volatile uint32_t *)REG_DMA9_XCNT_CUR)                /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA9_YCNT_CUR               ((volatile uint32_t *)REG_DMA9_YCNT_CUR)                /* DMA9 Current Row Count (2D only) */
-#define pREG_DMA9_BWLCNT                 ((volatile uint32_t *)REG_DMA9_BWLCNT)                  /* DMA9 Bandwidth Limit Count */
-#define pREG_DMA9_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWLCNT_CUR)              /* DMA9 Bandwidth Limit Count Current */
-#define pREG_DMA9_BWMCNT                 ((volatile uint32_t *)REG_DMA9_BWMCNT)                  /* DMA9 Bandwidth Monitor Count */
-#define pREG_DMA9_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWMCNT_CUR)              /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA10
-   ========================================================================= */
-#define pREG_DMA10_DSCPTR_NXT            ((void * volatile *)REG_DMA10_DSCPTR_NXT)               /* DMA10 Pointer to Next Initial Descriptor */
-#define pREG_DMA10_ADDRSTART             ((void * volatile *)REG_DMA10_ADDRSTART)                /* DMA10 Start Address of Current Buffer */
-#define pREG_DMA10_CFG                   ((volatile uint32_t *)REG_DMA10_CFG)                    /* DMA10 Configuration Register */
-#define pREG_DMA10_XCNT                  ((volatile uint32_t *)REG_DMA10_XCNT)                   /* DMA10 Inner Loop Count Start Value */
-#define pREG_DMA10_XMOD                  ((volatile  int32_t *)REG_DMA10_XMOD)                   /* DMA10 Inner Loop Address Increment */
-#define pREG_DMA10_YCNT                  ((volatile uint32_t *)REG_DMA10_YCNT)                   /* DMA10 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA10_YMOD                  ((volatile  int32_t *)REG_DMA10_YMOD)                   /* DMA10 Outer Loop Address Increment (2D only) */
-#define pREG_DMA10_DSCPTR_CUR            ((void * volatile *)REG_DMA10_DSCPTR_CUR)               /* DMA10 Current Descriptor Pointer */
-#define pREG_DMA10_DSCPTR_PRV            ((void * volatile *)REG_DMA10_DSCPTR_PRV)               /* DMA10 Previous Initial Descriptor Pointer */
-#define pREG_DMA10_ADDR_CUR              ((void * volatile *)REG_DMA10_ADDR_CUR)                 /* DMA10 Current Address */
-#define pREG_DMA10_STAT                  ((volatile uint32_t *)REG_DMA10_STAT)                   /* DMA10 Status Register */
-#define pREG_DMA10_XCNT_CUR              ((volatile uint32_t *)REG_DMA10_XCNT_CUR)               /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA10_YCNT_CUR              ((volatile uint32_t *)REG_DMA10_YCNT_CUR)               /* DMA10 Current Row Count (2D only) */
-#define pREG_DMA10_BWLCNT                ((volatile uint32_t *)REG_DMA10_BWLCNT)                 /* DMA10 Bandwidth Limit Count */
-#define pREG_DMA10_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWLCNT_CUR)             /* DMA10 Bandwidth Limit Count Current */
-#define pREG_DMA10_BWMCNT                ((volatile uint32_t *)REG_DMA10_BWMCNT)                 /* DMA10 Bandwidth Monitor Count */
-#define pREG_DMA10_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWMCNT_CUR)             /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA11
-   ========================================================================= */
-#define pREG_DMA11_DSCPTR_NXT            ((void * volatile *)REG_DMA11_DSCPTR_NXT)               /* DMA11 Pointer to Next Initial Descriptor */
-#define pREG_DMA11_ADDRSTART             ((void * volatile *)REG_DMA11_ADDRSTART)                /* DMA11 Start Address of Current Buffer */
-#define pREG_DMA11_CFG                   ((volatile uint32_t *)REG_DMA11_CFG)                    /* DMA11 Configuration Register */
-#define pREG_DMA11_XCNT                  ((volatile uint32_t *)REG_DMA11_XCNT)                   /* DMA11 Inner Loop Count Start Value */
-#define pREG_DMA11_XMOD                  ((volatile  int32_t *)REG_DMA11_XMOD)                   /* DMA11 Inner Loop Address Increment */
-#define pREG_DMA11_YCNT                  ((volatile uint32_t *)REG_DMA11_YCNT)                   /* DMA11 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA11_YMOD                  ((volatile  int32_t *)REG_DMA11_YMOD)                   /* DMA11 Outer Loop Address Increment (2D only) */
-#define pREG_DMA11_DSCPTR_CUR            ((void * volatile *)REG_DMA11_DSCPTR_CUR)               /* DMA11 Current Descriptor Pointer */
-#define pREG_DMA11_DSCPTR_PRV            ((void * volatile *)REG_DMA11_DSCPTR_PRV)               /* DMA11 Previous Initial Descriptor Pointer */
-#define pREG_DMA11_ADDR_CUR              ((void * volatile *)REG_DMA11_ADDR_CUR)                 /* DMA11 Current Address */
-#define pREG_DMA11_STAT                  ((volatile uint32_t *)REG_DMA11_STAT)                   /* DMA11 Status Register */
-#define pREG_DMA11_XCNT_CUR              ((volatile uint32_t *)REG_DMA11_XCNT_CUR)               /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA11_YCNT_CUR              ((volatile uint32_t *)REG_DMA11_YCNT_CUR)               /* DMA11 Current Row Count (2D only) */
-#define pREG_DMA11_BWLCNT                ((volatile uint32_t *)REG_DMA11_BWLCNT)                 /* DMA11 Bandwidth Limit Count */
-#define pREG_DMA11_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWLCNT_CUR)             /* DMA11 Bandwidth Limit Count Current */
-#define pREG_DMA11_BWMCNT                ((volatile uint32_t *)REG_DMA11_BWMCNT)                 /* DMA11 Bandwidth Monitor Count */
-#define pREG_DMA11_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWMCNT_CUR)             /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA12
-   ========================================================================= */
-#define pREG_DMA12_DSCPTR_NXT            ((void * volatile *)REG_DMA12_DSCPTR_NXT)               /* DMA12 Pointer to Next Initial Descriptor */
-#define pREG_DMA12_ADDRSTART             ((void * volatile *)REG_DMA12_ADDRSTART)                /* DMA12 Start Address of Current Buffer */
-#define pREG_DMA12_CFG                   ((volatile uint32_t *)REG_DMA12_CFG)                    /* DMA12 Configuration Register */
-#define pREG_DMA12_XCNT                  ((volatile uint32_t *)REG_DMA12_XCNT)                   /* DMA12 Inner Loop Count Start Value */
-#define pREG_DMA12_XMOD                  ((volatile  int32_t *)REG_DMA12_XMOD)                   /* DMA12 Inner Loop Address Increment */
-#define pREG_DMA12_YCNT                  ((volatile uint32_t *)REG_DMA12_YCNT)                   /* DMA12 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA12_YMOD                  ((volatile  int32_t *)REG_DMA12_YMOD)                   /* DMA12 Outer Loop Address Increment (2D only) */
-#define pREG_DMA12_DSCPTR_CUR            ((void * volatile *)REG_DMA12_DSCPTR_CUR)               /* DMA12 Current Descriptor Pointer */
-#define pREG_DMA12_DSCPTR_PRV            ((void * volatile *)REG_DMA12_DSCPTR_PRV)               /* DMA12 Previous Initial Descriptor Pointer */
-#define pREG_DMA12_ADDR_CUR              ((void * volatile *)REG_DMA12_ADDR_CUR)                 /* DMA12 Current Address */
-#define pREG_DMA12_STAT                  ((volatile uint32_t *)REG_DMA12_STAT)                   /* DMA12 Status Register */
-#define pREG_DMA12_XCNT_CUR              ((volatile uint32_t *)REG_DMA12_XCNT_CUR)               /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA12_YCNT_CUR              ((volatile uint32_t *)REG_DMA12_YCNT_CUR)               /* DMA12 Current Row Count (2D only) */
-#define pREG_DMA12_BWLCNT                ((volatile uint32_t *)REG_DMA12_BWLCNT)                 /* DMA12 Bandwidth Limit Count */
-#define pREG_DMA12_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWLCNT_CUR)             /* DMA12 Bandwidth Limit Count Current */
-#define pREG_DMA12_BWMCNT                ((volatile uint32_t *)REG_DMA12_BWMCNT)                 /* DMA12 Bandwidth Monitor Count */
-#define pREG_DMA12_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWMCNT_CUR)             /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA13
-   ========================================================================= */
-#define pREG_DMA13_DSCPTR_NXT            ((void * volatile *)REG_DMA13_DSCPTR_NXT)               /* DMA13 Pointer to Next Initial Descriptor */
-#define pREG_DMA13_ADDRSTART             ((void * volatile *)REG_DMA13_ADDRSTART)                /* DMA13 Start Address of Current Buffer */
-#define pREG_DMA13_CFG                   ((volatile uint32_t *)REG_DMA13_CFG)                    /* DMA13 Configuration Register */
-#define pREG_DMA13_XCNT                  ((volatile uint32_t *)REG_DMA13_XCNT)                   /* DMA13 Inner Loop Count Start Value */
-#define pREG_DMA13_XMOD                  ((volatile  int32_t *)REG_DMA13_XMOD)                   /* DMA13 Inner Loop Address Increment */
-#define pREG_DMA13_YCNT                  ((volatile uint32_t *)REG_DMA13_YCNT)                   /* DMA13 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA13_YMOD                  ((volatile  int32_t *)REG_DMA13_YMOD)                   /* DMA13 Outer Loop Address Increment (2D only) */
-#define pREG_DMA13_DSCPTR_CUR            ((void * volatile *)REG_DMA13_DSCPTR_CUR)               /* DMA13 Current Descriptor Pointer */
-#define pREG_DMA13_DSCPTR_PRV            ((void * volatile *)REG_DMA13_DSCPTR_PRV)               /* DMA13 Previous Initial Descriptor Pointer */
-#define pREG_DMA13_ADDR_CUR              ((void * volatile *)REG_DMA13_ADDR_CUR)                 /* DMA13 Current Address */
-#define pREG_DMA13_STAT                  ((volatile uint32_t *)REG_DMA13_STAT)                   /* DMA13 Status Register */
-#define pREG_DMA13_XCNT_CUR              ((volatile uint32_t *)REG_DMA13_XCNT_CUR)               /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA13_YCNT_CUR              ((volatile uint32_t *)REG_DMA13_YCNT_CUR)               /* DMA13 Current Row Count (2D only) */
-#define pREG_DMA13_BWLCNT                ((volatile uint32_t *)REG_DMA13_BWLCNT)                 /* DMA13 Bandwidth Limit Count */
-#define pREG_DMA13_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWLCNT_CUR)             /* DMA13 Bandwidth Limit Count Current */
-#define pREG_DMA13_BWMCNT                ((volatile uint32_t *)REG_DMA13_BWMCNT)                 /* DMA13 Bandwidth Monitor Count */
-#define pREG_DMA13_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWMCNT_CUR)             /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA14
-   ========================================================================= */
-#define pREG_DMA14_DSCPTR_NXT            ((void * volatile *)REG_DMA14_DSCPTR_NXT)               /* DMA14 Pointer to Next Initial Descriptor */
-#define pREG_DMA14_ADDRSTART             ((void * volatile *)REG_DMA14_ADDRSTART)                /* DMA14 Start Address of Current Buffer */
-#define pREG_DMA14_CFG                   ((volatile uint32_t *)REG_DMA14_CFG)                    /* DMA14 Configuration Register */
-#define pREG_DMA14_XCNT                  ((volatile uint32_t *)REG_DMA14_XCNT)                   /* DMA14 Inner Loop Count Start Value */
-#define pREG_DMA14_XMOD                  ((volatile  int32_t *)REG_DMA14_XMOD)                   /* DMA14 Inner Loop Address Increment */
-#define pREG_DMA14_YCNT                  ((volatile uint32_t *)REG_DMA14_YCNT)                   /* DMA14 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA14_YMOD                  ((volatile  int32_t *)REG_DMA14_YMOD)                   /* DMA14 Outer Loop Address Increment (2D only) */
-#define pREG_DMA14_DSCPTR_CUR            ((void * volatile *)REG_DMA14_DSCPTR_CUR)               /* DMA14 Current Descriptor Pointer */
-#define pREG_DMA14_DSCPTR_PRV            ((void * volatile *)REG_DMA14_DSCPTR_PRV)               /* DMA14 Previous Initial Descriptor Pointer */
-#define pREG_DMA14_ADDR_CUR              ((void * volatile *)REG_DMA14_ADDR_CUR)                 /* DMA14 Current Address */
-#define pREG_DMA14_STAT                  ((volatile uint32_t *)REG_DMA14_STAT)                   /* DMA14 Status Register */
-#define pREG_DMA14_XCNT_CUR              ((volatile uint32_t *)REG_DMA14_XCNT_CUR)               /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA14_YCNT_CUR              ((volatile uint32_t *)REG_DMA14_YCNT_CUR)               /* DMA14 Current Row Count (2D only) */
-#define pREG_DMA14_BWLCNT                ((volatile uint32_t *)REG_DMA14_BWLCNT)                 /* DMA14 Bandwidth Limit Count */
-#define pREG_DMA14_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWLCNT_CUR)             /* DMA14 Bandwidth Limit Count Current */
-#define pREG_DMA14_BWMCNT                ((volatile uint32_t *)REG_DMA14_BWMCNT)                 /* DMA14 Bandwidth Monitor Count */
-#define pREG_DMA14_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWMCNT_CUR)             /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA15
-   ========================================================================= */
-#define pREG_DMA15_DSCPTR_NXT            ((void * volatile *)REG_DMA15_DSCPTR_NXT)               /* DMA15 Pointer to Next Initial Descriptor */
-#define pREG_DMA15_ADDRSTART             ((void * volatile *)REG_DMA15_ADDRSTART)                /* DMA15 Start Address of Current Buffer */
-#define pREG_DMA15_CFG                   ((volatile uint32_t *)REG_DMA15_CFG)                    /* DMA15 Configuration Register */
-#define pREG_DMA15_XCNT                  ((volatile uint32_t *)REG_DMA15_XCNT)                   /* DMA15 Inner Loop Count Start Value */
-#define pREG_DMA15_XMOD                  ((volatile  int32_t *)REG_DMA15_XMOD)                   /* DMA15 Inner Loop Address Increment */
-#define pREG_DMA15_YCNT                  ((volatile uint32_t *)REG_DMA15_YCNT)                   /* DMA15 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA15_YMOD                  ((volatile  int32_t *)REG_DMA15_YMOD)                   /* DMA15 Outer Loop Address Increment (2D only) */
-#define pREG_DMA15_DSCPTR_CUR            ((void * volatile *)REG_DMA15_DSCPTR_CUR)               /* DMA15 Current Descriptor Pointer */
-#define pREG_DMA15_DSCPTR_PRV            ((void * volatile *)REG_DMA15_DSCPTR_PRV)               /* DMA15 Previous Initial Descriptor Pointer */
-#define pREG_DMA15_ADDR_CUR              ((void * volatile *)REG_DMA15_ADDR_CUR)                 /* DMA15 Current Address */
-#define pREG_DMA15_STAT                  ((volatile uint32_t *)REG_DMA15_STAT)                   /* DMA15 Status Register */
-#define pREG_DMA15_XCNT_CUR              ((volatile uint32_t *)REG_DMA15_XCNT_CUR)               /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA15_YCNT_CUR              ((volatile uint32_t *)REG_DMA15_YCNT_CUR)               /* DMA15 Current Row Count (2D only) */
-#define pREG_DMA15_BWLCNT                ((volatile uint32_t *)REG_DMA15_BWLCNT)                 /* DMA15 Bandwidth Limit Count */
-#define pREG_DMA15_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWLCNT_CUR)             /* DMA15 Bandwidth Limit Count Current */
-#define pREG_DMA15_BWMCNT                ((volatile uint32_t *)REG_DMA15_BWMCNT)                 /* DMA15 Bandwidth Monitor Count */
-#define pREG_DMA15_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWMCNT_CUR)             /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA16
-   ========================================================================= */
-#define pREG_DMA16_DSCPTR_NXT            ((void * volatile *)REG_DMA16_DSCPTR_NXT)               /* DMA16 Pointer to Next Initial Descriptor */
-#define pREG_DMA16_ADDRSTART             ((void * volatile *)REG_DMA16_ADDRSTART)                /* DMA16 Start Address of Current Buffer */
-#define pREG_DMA16_CFG                   ((volatile uint32_t *)REG_DMA16_CFG)                    /* DMA16 Configuration Register */
-#define pREG_DMA16_XCNT                  ((volatile uint32_t *)REG_DMA16_XCNT)                   /* DMA16 Inner Loop Count Start Value */
-#define pREG_DMA16_XMOD                  ((volatile  int32_t *)REG_DMA16_XMOD)                   /* DMA16 Inner Loop Address Increment */
-#define pREG_DMA16_YCNT                  ((volatile uint32_t *)REG_DMA16_YCNT)                   /* DMA16 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA16_YMOD                  ((volatile  int32_t *)REG_DMA16_YMOD)                   /* DMA16 Outer Loop Address Increment (2D only) */
-#define pREG_DMA16_DSCPTR_CUR            ((void * volatile *)REG_DMA16_DSCPTR_CUR)               /* DMA16 Current Descriptor Pointer */
-#define pREG_DMA16_DSCPTR_PRV            ((void * volatile *)REG_DMA16_DSCPTR_PRV)               /* DMA16 Previous Initial Descriptor Pointer */
-#define pREG_DMA16_ADDR_CUR              ((void * volatile *)REG_DMA16_ADDR_CUR)                 /* DMA16 Current Address */
-#define pREG_DMA16_STAT                  ((volatile uint32_t *)REG_DMA16_STAT)                   /* DMA16 Status Register */
-#define pREG_DMA16_XCNT_CUR              ((volatile uint32_t *)REG_DMA16_XCNT_CUR)               /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA16_YCNT_CUR              ((volatile uint32_t *)REG_DMA16_YCNT_CUR)               /* DMA16 Current Row Count (2D only) */
-#define pREG_DMA16_BWLCNT                ((volatile uint32_t *)REG_DMA16_BWLCNT)                 /* DMA16 Bandwidth Limit Count */
-#define pREG_DMA16_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWLCNT_CUR)             /* DMA16 Bandwidth Limit Count Current */
-#define pREG_DMA16_BWMCNT                ((volatile uint32_t *)REG_DMA16_BWMCNT)                 /* DMA16 Bandwidth Monitor Count */
-#define pREG_DMA16_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWMCNT_CUR)             /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA17
-   ========================================================================= */
-#define pREG_DMA17_DSCPTR_NXT            ((void * volatile *)REG_DMA17_DSCPTR_NXT)               /* DMA17 Pointer to Next Initial Descriptor */
-#define pREG_DMA17_ADDRSTART             ((void * volatile *)REG_DMA17_ADDRSTART)                /* DMA17 Start Address of Current Buffer */
-#define pREG_DMA17_CFG                   ((volatile uint32_t *)REG_DMA17_CFG)                    /* DMA17 Configuration Register */
-#define pREG_DMA17_XCNT                  ((volatile uint32_t *)REG_DMA17_XCNT)                   /* DMA17 Inner Loop Count Start Value */
-#define pREG_DMA17_XMOD                  ((volatile  int32_t *)REG_DMA17_XMOD)                   /* DMA17 Inner Loop Address Increment */
-#define pREG_DMA17_YCNT                  ((volatile uint32_t *)REG_DMA17_YCNT)                   /* DMA17 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA17_YMOD                  ((volatile  int32_t *)REG_DMA17_YMOD)                   /* DMA17 Outer Loop Address Increment (2D only) */
-#define pREG_DMA17_DSCPTR_CUR            ((void * volatile *)REG_DMA17_DSCPTR_CUR)               /* DMA17 Current Descriptor Pointer */
-#define pREG_DMA17_DSCPTR_PRV            ((void * volatile *)REG_DMA17_DSCPTR_PRV)               /* DMA17 Previous Initial Descriptor Pointer */
-#define pREG_DMA17_ADDR_CUR              ((void * volatile *)REG_DMA17_ADDR_CUR)                 /* DMA17 Current Address */
-#define pREG_DMA17_STAT                  ((volatile uint32_t *)REG_DMA17_STAT)                   /* DMA17 Status Register */
-#define pREG_DMA17_XCNT_CUR              ((volatile uint32_t *)REG_DMA17_XCNT_CUR)               /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA17_YCNT_CUR              ((volatile uint32_t *)REG_DMA17_YCNT_CUR)               /* DMA17 Current Row Count (2D only) */
-#define pREG_DMA17_BWLCNT                ((volatile uint32_t *)REG_DMA17_BWLCNT)                 /* DMA17 Bandwidth Limit Count */
-#define pREG_DMA17_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWLCNT_CUR)             /* DMA17 Bandwidth Limit Count Current */
-#define pREG_DMA17_BWMCNT                ((volatile uint32_t *)REG_DMA17_BWMCNT)                 /* DMA17 Bandwidth Monitor Count */
-#define pREG_DMA17_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWMCNT_CUR)             /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA18
-   ========================================================================= */
-#define pREG_DMA18_DSCPTR_NXT            ((void * volatile *)REG_DMA18_DSCPTR_NXT)               /* DMA18 Pointer to Next Initial Descriptor */
-#define pREG_DMA18_ADDRSTART             ((void * volatile *)REG_DMA18_ADDRSTART)                /* DMA18 Start Address of Current Buffer */
-#define pREG_DMA18_CFG                   ((volatile uint32_t *)REG_DMA18_CFG)                    /* DMA18 Configuration Register */
-#define pREG_DMA18_XCNT                  ((volatile uint32_t *)REG_DMA18_XCNT)                   /* DMA18 Inner Loop Count Start Value */
-#define pREG_DMA18_XMOD                  ((volatile  int32_t *)REG_DMA18_XMOD)                   /* DMA18 Inner Loop Address Increment */
-#define pREG_DMA18_YCNT                  ((volatile uint32_t *)REG_DMA18_YCNT)                   /* DMA18 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA18_YMOD                  ((volatile  int32_t *)REG_DMA18_YMOD)                   /* DMA18 Outer Loop Address Increment (2D only) */
-#define pREG_DMA18_DSCPTR_CUR            ((void * volatile *)REG_DMA18_DSCPTR_CUR)               /* DMA18 Current Descriptor Pointer */
-#define pREG_DMA18_DSCPTR_PRV            ((void * volatile *)REG_DMA18_DSCPTR_PRV)               /* DMA18 Previous Initial Descriptor Pointer */
-#define pREG_DMA18_ADDR_CUR              ((void * volatile *)REG_DMA18_ADDR_CUR)                 /* DMA18 Current Address */
-#define pREG_DMA18_STAT                  ((volatile uint32_t *)REG_DMA18_STAT)                   /* DMA18 Status Register */
-#define pREG_DMA18_XCNT_CUR              ((volatile uint32_t *)REG_DMA18_XCNT_CUR)               /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA18_YCNT_CUR              ((volatile uint32_t *)REG_DMA18_YCNT_CUR)               /* DMA18 Current Row Count (2D only) */
-#define pREG_DMA18_BWLCNT                ((volatile uint32_t *)REG_DMA18_BWLCNT)                 /* DMA18 Bandwidth Limit Count */
-#define pREG_DMA18_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWLCNT_CUR)             /* DMA18 Bandwidth Limit Count Current */
-#define pREG_DMA18_BWMCNT                ((volatile uint32_t *)REG_DMA18_BWMCNT)                 /* DMA18 Bandwidth Monitor Count */
-#define pREG_DMA18_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWMCNT_CUR)             /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA19
-   ========================================================================= */
-#define pREG_DMA19_DSCPTR_NXT            ((void * volatile *)REG_DMA19_DSCPTR_NXT)               /* DMA19 Pointer to Next Initial Descriptor */
-#define pREG_DMA19_ADDRSTART             ((void * volatile *)REG_DMA19_ADDRSTART)                /* DMA19 Start Address of Current Buffer */
-#define pREG_DMA19_CFG                   ((volatile uint32_t *)REG_DMA19_CFG)                    /* DMA19 Configuration Register */
-#define pREG_DMA19_XCNT                  ((volatile uint32_t *)REG_DMA19_XCNT)                   /* DMA19 Inner Loop Count Start Value */
-#define pREG_DMA19_XMOD                  ((volatile  int32_t *)REG_DMA19_XMOD)                   /* DMA19 Inner Loop Address Increment */
-#define pREG_DMA19_YCNT                  ((volatile uint32_t *)REG_DMA19_YCNT)                   /* DMA19 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA19_YMOD                  ((volatile  int32_t *)REG_DMA19_YMOD)                   /* DMA19 Outer Loop Address Increment (2D only) */
-#define pREG_DMA19_DSCPTR_CUR            ((void * volatile *)REG_DMA19_DSCPTR_CUR)               /* DMA19 Current Descriptor Pointer */
-#define pREG_DMA19_DSCPTR_PRV            ((void * volatile *)REG_DMA19_DSCPTR_PRV)               /* DMA19 Previous Initial Descriptor Pointer */
-#define pREG_DMA19_ADDR_CUR              ((void * volatile *)REG_DMA19_ADDR_CUR)                 /* DMA19 Current Address */
-#define pREG_DMA19_STAT                  ((volatile uint32_t *)REG_DMA19_STAT)                   /* DMA19 Status Register */
-#define pREG_DMA19_XCNT_CUR              ((volatile uint32_t *)REG_DMA19_XCNT_CUR)               /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA19_YCNT_CUR              ((volatile uint32_t *)REG_DMA19_YCNT_CUR)               /* DMA19 Current Row Count (2D only) */
-#define pREG_DMA19_BWLCNT                ((volatile uint32_t *)REG_DMA19_BWLCNT)                 /* DMA19 Bandwidth Limit Count */
-#define pREG_DMA19_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWLCNT_CUR)             /* DMA19 Bandwidth Limit Count Current */
-#define pREG_DMA19_BWMCNT                ((volatile uint32_t *)REG_DMA19_BWMCNT)                 /* DMA19 Bandwidth Monitor Count */
-#define pREG_DMA19_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWMCNT_CUR)             /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA20
-   ========================================================================= */
-#define pREG_DMA20_DSCPTR_NXT            ((void * volatile *)REG_DMA20_DSCPTR_NXT)               /* DMA20 Pointer to Next Initial Descriptor */
-#define pREG_DMA20_ADDRSTART             ((void * volatile *)REG_DMA20_ADDRSTART)                /* DMA20 Start Address of Current Buffer */
-#define pREG_DMA20_CFG                   ((volatile uint32_t *)REG_DMA20_CFG)                    /* DMA20 Configuration Register */
-#define pREG_DMA20_XCNT                  ((volatile uint32_t *)REG_DMA20_XCNT)                   /* DMA20 Inner Loop Count Start Value */
-#define pREG_DMA20_XMOD                  ((volatile  int32_t *)REG_DMA20_XMOD)                   /* DMA20 Inner Loop Address Increment */
-#define pREG_DMA20_YCNT                  ((volatile uint32_t *)REG_DMA20_YCNT)                   /* DMA20 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA20_YMOD                  ((volatile  int32_t *)REG_DMA20_YMOD)                   /* DMA20 Outer Loop Address Increment (2D only) */
-#define pREG_DMA20_DSCPTR_CUR            ((void * volatile *)REG_DMA20_DSCPTR_CUR)               /* DMA20 Current Descriptor Pointer */
-#define pREG_DMA20_DSCPTR_PRV            ((void * volatile *)REG_DMA20_DSCPTR_PRV)               /* DMA20 Previous Initial Descriptor Pointer */
-#define pREG_DMA20_ADDR_CUR              ((void * volatile *)REG_DMA20_ADDR_CUR)                 /* DMA20 Current Address */
-#define pREG_DMA20_STAT                  ((volatile uint32_t *)REG_DMA20_STAT)                   /* DMA20 Status Register */
-#define pREG_DMA20_XCNT_CUR              ((volatile uint32_t *)REG_DMA20_XCNT_CUR)               /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA20_YCNT_CUR              ((volatile uint32_t *)REG_DMA20_YCNT_CUR)               /* DMA20 Current Row Count (2D only) */
-#define pREG_DMA20_BWLCNT                ((volatile uint32_t *)REG_DMA20_BWLCNT)                 /* DMA20 Bandwidth Limit Count */
-#define pREG_DMA20_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWLCNT_CUR)             /* DMA20 Bandwidth Limit Count Current */
-#define pREG_DMA20_BWMCNT                ((volatile uint32_t *)REG_DMA20_BWMCNT)                 /* DMA20 Bandwidth Monitor Count */
-#define pREG_DMA20_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWMCNT_CUR)             /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA21
-   ========================================================================= */
-#define pREG_DMA21_DSCPTR_NXT            ((void * volatile *)REG_DMA21_DSCPTR_NXT)               /* DMA21 Pointer to Next Initial Descriptor */
-#define pREG_DMA21_ADDRSTART             ((void * volatile *)REG_DMA21_ADDRSTART)                /* DMA21 Start Address of Current Buffer */
-#define pREG_DMA21_CFG                   ((volatile uint32_t *)REG_DMA21_CFG)                    /* DMA21 Configuration Register */
-#define pREG_DMA21_XCNT                  ((volatile uint32_t *)REG_DMA21_XCNT)                   /* DMA21 Inner Loop Count Start Value */
-#define pREG_DMA21_XMOD                  ((volatile  int32_t *)REG_DMA21_XMOD)                   /* DMA21 Inner Loop Address Increment */
-#define pREG_DMA21_YCNT                  ((volatile uint32_t *)REG_DMA21_YCNT)                   /* DMA21 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA21_YMOD                  ((volatile  int32_t *)REG_DMA21_YMOD)                   /* DMA21 Outer Loop Address Increment (2D only) */
-#define pREG_DMA21_DSCPTR_CUR            ((void * volatile *)REG_DMA21_DSCPTR_CUR)               /* DMA21 Current Descriptor Pointer */
-#define pREG_DMA21_DSCPTR_PRV            ((void * volatile *)REG_DMA21_DSCPTR_PRV)               /* DMA21 Previous Initial Descriptor Pointer */
-#define pREG_DMA21_ADDR_CUR              ((void * volatile *)REG_DMA21_ADDR_CUR)                 /* DMA21 Current Address */
-#define pREG_DMA21_STAT                  ((volatile uint32_t *)REG_DMA21_STAT)                   /* DMA21 Status Register */
-#define pREG_DMA21_XCNT_CUR              ((volatile uint32_t *)REG_DMA21_XCNT_CUR)               /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA21_YCNT_CUR              ((volatile uint32_t *)REG_DMA21_YCNT_CUR)               /* DMA21 Current Row Count (2D only) */
-#define pREG_DMA21_BWLCNT                ((volatile uint32_t *)REG_DMA21_BWLCNT)                 /* DMA21 Bandwidth Limit Count */
-#define pREG_DMA21_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWLCNT_CUR)             /* DMA21 Bandwidth Limit Count Current */
-#define pREG_DMA21_BWMCNT                ((volatile uint32_t *)REG_DMA21_BWMCNT)                 /* DMA21 Bandwidth Monitor Count */
-#define pREG_DMA21_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWMCNT_CUR)             /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA22
-   ========================================================================= */
-#define pREG_DMA22_DSCPTR_NXT            ((void * volatile *)REG_DMA22_DSCPTR_NXT)               /* DMA22 Pointer to Next Initial Descriptor */
-#define pREG_DMA22_ADDRSTART             ((void * volatile *)REG_DMA22_ADDRSTART)                /* DMA22 Start Address of Current Buffer */
-#define pREG_DMA22_CFG                   ((volatile uint32_t *)REG_DMA22_CFG)                    /* DMA22 Configuration Register */
-#define pREG_DMA22_XCNT                  ((volatile uint32_t *)REG_DMA22_XCNT)                   /* DMA22 Inner Loop Count Start Value */
-#define pREG_DMA22_XMOD                  ((volatile  int32_t *)REG_DMA22_XMOD)                   /* DMA22 Inner Loop Address Increment */
-#define pREG_DMA22_YCNT                  ((volatile uint32_t *)REG_DMA22_YCNT)                   /* DMA22 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA22_YMOD                  ((volatile  int32_t *)REG_DMA22_YMOD)                   /* DMA22 Outer Loop Address Increment (2D only) */
-#define pREG_DMA22_DSCPTR_CUR            ((void * volatile *)REG_DMA22_DSCPTR_CUR)               /* DMA22 Current Descriptor Pointer */
-#define pREG_DMA22_DSCPTR_PRV            ((void * volatile *)REG_DMA22_DSCPTR_PRV)               /* DMA22 Previous Initial Descriptor Pointer */
-#define pREG_DMA22_ADDR_CUR              ((void * volatile *)REG_DMA22_ADDR_CUR)                 /* DMA22 Current Address */
-#define pREG_DMA22_STAT                  ((volatile uint32_t *)REG_DMA22_STAT)                   /* DMA22 Status Register */
-#define pREG_DMA22_XCNT_CUR              ((volatile uint32_t *)REG_DMA22_XCNT_CUR)               /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA22_YCNT_CUR              ((volatile uint32_t *)REG_DMA22_YCNT_CUR)               /* DMA22 Current Row Count (2D only) */
-#define pREG_DMA22_BWLCNT                ((volatile uint32_t *)REG_DMA22_BWLCNT)                 /* DMA22 Bandwidth Limit Count */
-#define pREG_DMA22_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWLCNT_CUR)             /* DMA22 Bandwidth Limit Count Current */
-#define pREG_DMA22_BWMCNT                ((volatile uint32_t *)REG_DMA22_BWMCNT)                 /* DMA22 Bandwidth Monitor Count */
-#define pREG_DMA22_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWMCNT_CUR)             /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA23
-   ========================================================================= */
-#define pREG_DMA23_DSCPTR_NXT            ((void * volatile *)REG_DMA23_DSCPTR_NXT)               /* DMA23 Pointer to Next Initial Descriptor */
-#define pREG_DMA23_ADDRSTART             ((void * volatile *)REG_DMA23_ADDRSTART)                /* DMA23 Start Address of Current Buffer */
-#define pREG_DMA23_CFG                   ((volatile uint32_t *)REG_DMA23_CFG)                    /* DMA23 Configuration Register */
-#define pREG_DMA23_XCNT                  ((volatile uint32_t *)REG_DMA23_XCNT)                   /* DMA23 Inner Loop Count Start Value */
-#define pREG_DMA23_XMOD                  ((volatile  int32_t *)REG_DMA23_XMOD)                   /* DMA23 Inner Loop Address Increment */
-#define pREG_DMA23_YCNT                  ((volatile uint32_t *)REG_DMA23_YCNT)                   /* DMA23 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA23_YMOD                  ((volatile  int32_t *)REG_DMA23_YMOD)                   /* DMA23 Outer Loop Address Increment (2D only) */
-#define pREG_DMA23_DSCPTR_CUR            ((void * volatile *)REG_DMA23_DSCPTR_CUR)               /* DMA23 Current Descriptor Pointer */
-#define pREG_DMA23_DSCPTR_PRV            ((void * volatile *)REG_DMA23_DSCPTR_PRV)               /* DMA23 Previous Initial Descriptor Pointer */
-#define pREG_DMA23_ADDR_CUR              ((void * volatile *)REG_DMA23_ADDR_CUR)                 /* DMA23 Current Address */
-#define pREG_DMA23_STAT                  ((volatile uint32_t *)REG_DMA23_STAT)                   /* DMA23 Status Register */
-#define pREG_DMA23_XCNT_CUR              ((volatile uint32_t *)REG_DMA23_XCNT_CUR)               /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA23_YCNT_CUR              ((volatile uint32_t *)REG_DMA23_YCNT_CUR)               /* DMA23 Current Row Count (2D only) */
-#define pREG_DMA23_BWLCNT                ((volatile uint32_t *)REG_DMA23_BWLCNT)                 /* DMA23 Bandwidth Limit Count */
-#define pREG_DMA23_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWLCNT_CUR)             /* DMA23 Bandwidth Limit Count Current */
-#define pREG_DMA23_BWMCNT                ((volatile uint32_t *)REG_DMA23_BWMCNT)                 /* DMA23 Bandwidth Monitor Count */
-#define pREG_DMA23_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWMCNT_CUR)             /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA24
-   ========================================================================= */
-#define pREG_DMA24_DSCPTR_NXT            ((void * volatile *)REG_DMA24_DSCPTR_NXT)               /* DMA24 Pointer to Next Initial Descriptor */
-#define pREG_DMA24_ADDRSTART             ((void * volatile *)REG_DMA24_ADDRSTART)                /* DMA24 Start Address of Current Buffer */
-#define pREG_DMA24_CFG                   ((volatile uint32_t *)REG_DMA24_CFG)                    /* DMA24 Configuration Register */
-#define pREG_DMA24_XCNT                  ((volatile uint32_t *)REG_DMA24_XCNT)                   /* DMA24 Inner Loop Count Start Value */
-#define pREG_DMA24_XMOD                  ((volatile  int32_t *)REG_DMA24_XMOD)                   /* DMA24 Inner Loop Address Increment */
-#define pREG_DMA24_YCNT                  ((volatile uint32_t *)REG_DMA24_YCNT)                   /* DMA24 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA24_YMOD                  ((volatile  int32_t *)REG_DMA24_YMOD)                   /* DMA24 Outer Loop Address Increment (2D only) */
-#define pREG_DMA24_DSCPTR_CUR            ((void * volatile *)REG_DMA24_DSCPTR_CUR)               /* DMA24 Current Descriptor Pointer */
-#define pREG_DMA24_DSCPTR_PRV            ((void * volatile *)REG_DMA24_DSCPTR_PRV)               /* DMA24 Previous Initial Descriptor Pointer */
-#define pREG_DMA24_ADDR_CUR              ((void * volatile *)REG_DMA24_ADDR_CUR)                 /* DMA24 Current Address */
-#define pREG_DMA24_STAT                  ((volatile uint32_t *)REG_DMA24_STAT)                   /* DMA24 Status Register */
-#define pREG_DMA24_XCNT_CUR              ((volatile uint32_t *)REG_DMA24_XCNT_CUR)               /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA24_YCNT_CUR              ((volatile uint32_t *)REG_DMA24_YCNT_CUR)               /* DMA24 Current Row Count (2D only) */
-#define pREG_DMA24_BWLCNT                ((volatile uint32_t *)REG_DMA24_BWLCNT)                 /* DMA24 Bandwidth Limit Count */
-#define pREG_DMA24_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWLCNT_CUR)             /* DMA24 Bandwidth Limit Count Current */
-#define pREG_DMA24_BWMCNT                ((volatile uint32_t *)REG_DMA24_BWMCNT)                 /* DMA24 Bandwidth Monitor Count */
-#define pREG_DMA24_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWMCNT_CUR)             /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA25
-   ========================================================================= */
-#define pREG_DMA25_DSCPTR_NXT            ((void * volatile *)REG_DMA25_DSCPTR_NXT)               /* DMA25 Pointer to Next Initial Descriptor */
-#define pREG_DMA25_ADDRSTART             ((void * volatile *)REG_DMA25_ADDRSTART)                /* DMA25 Start Address of Current Buffer */
-#define pREG_DMA25_CFG                   ((volatile uint32_t *)REG_DMA25_CFG)                    /* DMA25 Configuration Register */
-#define pREG_DMA25_XCNT                  ((volatile uint32_t *)REG_DMA25_XCNT)                   /* DMA25 Inner Loop Count Start Value */
-#define pREG_DMA25_XMOD                  ((volatile  int32_t *)REG_DMA25_XMOD)                   /* DMA25 Inner Loop Address Increment */
-#define pREG_DMA25_YCNT                  ((volatile uint32_t *)REG_DMA25_YCNT)                   /* DMA25 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA25_YMOD                  ((volatile  int32_t *)REG_DMA25_YMOD)                   /* DMA25 Outer Loop Address Increment (2D only) */
-#define pREG_DMA25_DSCPTR_CUR            ((void * volatile *)REG_DMA25_DSCPTR_CUR)               /* DMA25 Current Descriptor Pointer */
-#define pREG_DMA25_DSCPTR_PRV            ((void * volatile *)REG_DMA25_DSCPTR_PRV)               /* DMA25 Previous Initial Descriptor Pointer */
-#define pREG_DMA25_ADDR_CUR              ((void * volatile *)REG_DMA25_ADDR_CUR)                 /* DMA25 Current Address */
-#define pREG_DMA25_STAT                  ((volatile uint32_t *)REG_DMA25_STAT)                   /* DMA25 Status Register */
-#define pREG_DMA25_XCNT_CUR              ((volatile uint32_t *)REG_DMA25_XCNT_CUR)               /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA25_YCNT_CUR              ((volatile uint32_t *)REG_DMA25_YCNT_CUR)               /* DMA25 Current Row Count (2D only) */
-#define pREG_DMA25_BWLCNT                ((volatile uint32_t *)REG_DMA25_BWLCNT)                 /* DMA25 Bandwidth Limit Count */
-#define pREG_DMA25_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWLCNT_CUR)             /* DMA25 Bandwidth Limit Count Current */
-#define pREG_DMA25_BWMCNT                ((volatile uint32_t *)REG_DMA25_BWMCNT)                 /* DMA25 Bandwidth Monitor Count */
-#define pREG_DMA25_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWMCNT_CUR)             /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA26
-   ========================================================================= */
-#define pREG_DMA26_DSCPTR_NXT            ((void * volatile *)REG_DMA26_DSCPTR_NXT)               /* DMA26 Pointer to Next Initial Descriptor */
-#define pREG_DMA26_ADDRSTART             ((void * volatile *)REG_DMA26_ADDRSTART)                /* DMA26 Start Address of Current Buffer */
-#define pREG_DMA26_CFG                   ((volatile uint32_t *)REG_DMA26_CFG)                    /* DMA26 Configuration Register */
-#define pREG_DMA26_XCNT                  ((volatile uint32_t *)REG_DMA26_XCNT)                   /* DMA26 Inner Loop Count Start Value */
-#define pREG_DMA26_XMOD                  ((volatile  int32_t *)REG_DMA26_XMOD)                   /* DMA26 Inner Loop Address Increment */
-#define pREG_DMA26_YCNT                  ((volatile uint32_t *)REG_DMA26_YCNT)                   /* DMA26 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA26_YMOD                  ((volatile  int32_t *)REG_DMA26_YMOD)                   /* DMA26 Outer Loop Address Increment (2D only) */
-#define pREG_DMA26_DSCPTR_CUR            ((void * volatile *)REG_DMA26_DSCPTR_CUR)               /* DMA26 Current Descriptor Pointer */
-#define pREG_DMA26_DSCPTR_PRV            ((void * volatile *)REG_DMA26_DSCPTR_PRV)               /* DMA26 Previous Initial Descriptor Pointer */
-#define pREG_DMA26_ADDR_CUR              ((void * volatile *)REG_DMA26_ADDR_CUR)                 /* DMA26 Current Address */
-#define pREG_DMA26_STAT                  ((volatile uint32_t *)REG_DMA26_STAT)                   /* DMA26 Status Register */
-#define pREG_DMA26_XCNT_CUR              ((volatile uint32_t *)REG_DMA26_XCNT_CUR)               /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA26_YCNT_CUR              ((volatile uint32_t *)REG_DMA26_YCNT_CUR)               /* DMA26 Current Row Count (2D only) */
-#define pREG_DMA26_BWLCNT                ((volatile uint32_t *)REG_DMA26_BWLCNT)                 /* DMA26 Bandwidth Limit Count */
-#define pREG_DMA26_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWLCNT_CUR)             /* DMA26 Bandwidth Limit Count Current */
-#define pREG_DMA26_BWMCNT                ((volatile uint32_t *)REG_DMA26_BWMCNT)                 /* DMA26 Bandwidth Monitor Count */
-#define pREG_DMA26_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWMCNT_CUR)             /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA27
-   ========================================================================= */
-#define pREG_DMA27_DSCPTR_NXT            ((void * volatile *)REG_DMA27_DSCPTR_NXT)               /* DMA27 Pointer to Next Initial Descriptor */
-#define pREG_DMA27_ADDRSTART             ((void * volatile *)REG_DMA27_ADDRSTART)                /* DMA27 Start Address of Current Buffer */
-#define pREG_DMA27_CFG                   ((volatile uint32_t *)REG_DMA27_CFG)                    /* DMA27 Configuration Register */
-#define pREG_DMA27_XCNT                  ((volatile uint32_t *)REG_DMA27_XCNT)                   /* DMA27 Inner Loop Count Start Value */
-#define pREG_DMA27_XMOD                  ((volatile  int32_t *)REG_DMA27_XMOD)                   /* DMA27 Inner Loop Address Increment */
-#define pREG_DMA27_YCNT                  ((volatile uint32_t *)REG_DMA27_YCNT)                   /* DMA27 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA27_YMOD                  ((volatile  int32_t *)REG_DMA27_YMOD)                   /* DMA27 Outer Loop Address Increment (2D only) */
-#define pREG_DMA27_DSCPTR_CUR            ((void * volatile *)REG_DMA27_DSCPTR_CUR)               /* DMA27 Current Descriptor Pointer */
-#define pREG_DMA27_DSCPTR_PRV            ((void * volatile *)REG_DMA27_DSCPTR_PRV)               /* DMA27 Previous Initial Descriptor Pointer */
-#define pREG_DMA27_ADDR_CUR              ((void * volatile *)REG_DMA27_ADDR_CUR)                 /* DMA27 Current Address */
-#define pREG_DMA27_STAT                  ((volatile uint32_t *)REG_DMA27_STAT)                   /* DMA27 Status Register */
-#define pREG_DMA27_XCNT_CUR              ((volatile uint32_t *)REG_DMA27_XCNT_CUR)               /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA27_YCNT_CUR              ((volatile uint32_t *)REG_DMA27_YCNT_CUR)               /* DMA27 Current Row Count (2D only) */
-#define pREG_DMA27_BWLCNT                ((volatile uint32_t *)REG_DMA27_BWLCNT)                 /* DMA27 Bandwidth Limit Count */
-#define pREG_DMA27_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWLCNT_CUR)             /* DMA27 Bandwidth Limit Count Current */
-#define pREG_DMA27_BWMCNT                ((volatile uint32_t *)REG_DMA27_BWMCNT)                 /* DMA27 Bandwidth Monitor Count */
-#define pREG_DMA27_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWMCNT_CUR)             /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA28
-   ========================================================================= */
-#define pREG_DMA28_DSCPTR_NXT            ((void * volatile *)REG_DMA28_DSCPTR_NXT)               /* DMA28 Pointer to Next Initial Descriptor */
-#define pREG_DMA28_ADDRSTART             ((void * volatile *)REG_DMA28_ADDRSTART)                /* DMA28 Start Address of Current Buffer */
-#define pREG_DMA28_CFG                   ((volatile uint32_t *)REG_DMA28_CFG)                    /* DMA28 Configuration Register */
-#define pREG_DMA28_XCNT                  ((volatile uint32_t *)REG_DMA28_XCNT)                   /* DMA28 Inner Loop Count Start Value */
-#define pREG_DMA28_XMOD                  ((volatile  int32_t *)REG_DMA28_XMOD)                   /* DMA28 Inner Loop Address Increment */
-#define pREG_DMA28_YCNT                  ((volatile uint32_t *)REG_DMA28_YCNT)                   /* DMA28 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA28_YMOD                  ((volatile  int32_t *)REG_DMA28_YMOD)                   /* DMA28 Outer Loop Address Increment (2D only) */
-#define pREG_DMA28_DSCPTR_CUR            ((void * volatile *)REG_DMA28_DSCPTR_CUR)               /* DMA28 Current Descriptor Pointer */
-#define pREG_DMA28_DSCPTR_PRV            ((void * volatile *)REG_DMA28_DSCPTR_PRV)               /* DMA28 Previous Initial Descriptor Pointer */
-#define pREG_DMA28_ADDR_CUR              ((void * volatile *)REG_DMA28_ADDR_CUR)                 /* DMA28 Current Address */
-#define pREG_DMA28_STAT                  ((volatile uint32_t *)REG_DMA28_STAT)                   /* DMA28 Status Register */
-#define pREG_DMA28_XCNT_CUR              ((volatile uint32_t *)REG_DMA28_XCNT_CUR)               /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA28_YCNT_CUR              ((volatile uint32_t *)REG_DMA28_YCNT_CUR)               /* DMA28 Current Row Count (2D only) */
-#define pREG_DMA28_BWLCNT                ((volatile uint32_t *)REG_DMA28_BWLCNT)                 /* DMA28 Bandwidth Limit Count */
-#define pREG_DMA28_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWLCNT_CUR)             /* DMA28 Bandwidth Limit Count Current */
-#define pREG_DMA28_BWMCNT                ((volatile uint32_t *)REG_DMA28_BWMCNT)                 /* DMA28 Bandwidth Monitor Count */
-#define pREG_DMA28_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWMCNT_CUR)             /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA29
-   ========================================================================= */
-#define pREG_DMA29_DSCPTR_NXT            ((void * volatile *)REG_DMA29_DSCPTR_NXT)               /* DMA29 Pointer to Next Initial Descriptor */
-#define pREG_DMA29_ADDRSTART             ((void * volatile *)REG_DMA29_ADDRSTART)                /* DMA29 Start Address of Current Buffer */
-#define pREG_DMA29_CFG                   ((volatile uint32_t *)REG_DMA29_CFG)                    /* DMA29 Configuration Register */
-#define pREG_DMA29_XCNT                  ((volatile uint32_t *)REG_DMA29_XCNT)                   /* DMA29 Inner Loop Count Start Value */
-#define pREG_DMA29_XMOD                  ((volatile  int32_t *)REG_DMA29_XMOD)                   /* DMA29 Inner Loop Address Increment */
-#define pREG_DMA29_YCNT                  ((volatile uint32_t *)REG_DMA29_YCNT)                   /* DMA29 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA29_YMOD                  ((volatile  int32_t *)REG_DMA29_YMOD)                   /* DMA29 Outer Loop Address Increment (2D only) */
-#define pREG_DMA29_DSCPTR_CUR            ((void * volatile *)REG_DMA29_DSCPTR_CUR)               /* DMA29 Current Descriptor Pointer */
-#define pREG_DMA29_DSCPTR_PRV            ((void * volatile *)REG_DMA29_DSCPTR_PRV)               /* DMA29 Previous Initial Descriptor Pointer */
-#define pREG_DMA29_ADDR_CUR              ((void * volatile *)REG_DMA29_ADDR_CUR)                 /* DMA29 Current Address */
-#define pREG_DMA29_STAT                  ((volatile uint32_t *)REG_DMA29_STAT)                   /* DMA29 Status Register */
-#define pREG_DMA29_XCNT_CUR              ((volatile uint32_t *)REG_DMA29_XCNT_CUR)               /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA29_YCNT_CUR              ((volatile uint32_t *)REG_DMA29_YCNT_CUR)               /* DMA29 Current Row Count (2D only) */
-#define pREG_DMA29_BWLCNT                ((volatile uint32_t *)REG_DMA29_BWLCNT)                 /* DMA29 Bandwidth Limit Count */
-#define pREG_DMA29_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWLCNT_CUR)             /* DMA29 Bandwidth Limit Count Current */
-#define pREG_DMA29_BWMCNT                ((volatile uint32_t *)REG_DMA29_BWMCNT)                 /* DMA29 Bandwidth Monitor Count */
-#define pREG_DMA29_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWMCNT_CUR)             /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA30
-   ========================================================================= */
-#define pREG_DMA30_DSCPTR_NXT            ((void * volatile *)REG_DMA30_DSCPTR_NXT)               /* DMA30 Pointer to Next Initial Descriptor */
-#define pREG_DMA30_ADDRSTART             ((void * volatile *)REG_DMA30_ADDRSTART)                /* DMA30 Start Address of Current Buffer */
-#define pREG_DMA30_CFG                   ((volatile uint32_t *)REG_DMA30_CFG)                    /* DMA30 Configuration Register */
-#define pREG_DMA30_XCNT                  ((volatile uint32_t *)REG_DMA30_XCNT)                   /* DMA30 Inner Loop Count Start Value */
-#define pREG_DMA30_XMOD                  ((volatile  int32_t *)REG_DMA30_XMOD)                   /* DMA30 Inner Loop Address Increment */
-#define pREG_DMA30_YCNT                  ((volatile uint32_t *)REG_DMA30_YCNT)                   /* DMA30 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA30_YMOD                  ((volatile  int32_t *)REG_DMA30_YMOD)                   /* DMA30 Outer Loop Address Increment (2D only) */
-#define pREG_DMA30_DSCPTR_CUR            ((void * volatile *)REG_DMA30_DSCPTR_CUR)               /* DMA30 Current Descriptor Pointer */
-#define pREG_DMA30_DSCPTR_PRV            ((void * volatile *)REG_DMA30_DSCPTR_PRV)               /* DMA30 Previous Initial Descriptor Pointer */
-#define pREG_DMA30_ADDR_CUR              ((void * volatile *)REG_DMA30_ADDR_CUR)                 /* DMA30 Current Address */
-#define pREG_DMA30_STAT                  ((volatile uint32_t *)REG_DMA30_STAT)                   /* DMA30 Status Register */
-#define pREG_DMA30_XCNT_CUR              ((volatile uint32_t *)REG_DMA30_XCNT_CUR)               /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA30_YCNT_CUR              ((volatile uint32_t *)REG_DMA30_YCNT_CUR)               /* DMA30 Current Row Count (2D only) */
-#define pREG_DMA30_BWLCNT                ((volatile uint32_t *)REG_DMA30_BWLCNT)                 /* DMA30 Bandwidth Limit Count */
-#define pREG_DMA30_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWLCNT_CUR)             /* DMA30 Bandwidth Limit Count Current */
-#define pREG_DMA30_BWMCNT                ((volatile uint32_t *)REG_DMA30_BWMCNT)                 /* DMA30 Bandwidth Monitor Count */
-#define pREG_DMA30_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWMCNT_CUR)             /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA31
-   ========================================================================= */
-#define pREG_DMA31_DSCPTR_NXT            ((void * volatile *)REG_DMA31_DSCPTR_NXT)               /* DMA31 Pointer to Next Initial Descriptor */
-#define pREG_DMA31_ADDRSTART             ((void * volatile *)REG_DMA31_ADDRSTART)                /* DMA31 Start Address of Current Buffer */
-#define pREG_DMA31_CFG                   ((volatile uint32_t *)REG_DMA31_CFG)                    /* DMA31 Configuration Register */
-#define pREG_DMA31_XCNT                  ((volatile uint32_t *)REG_DMA31_XCNT)                   /* DMA31 Inner Loop Count Start Value */
-#define pREG_DMA31_XMOD                  ((volatile  int32_t *)REG_DMA31_XMOD)                   /* DMA31 Inner Loop Address Increment */
-#define pREG_DMA31_YCNT                  ((volatile uint32_t *)REG_DMA31_YCNT)                   /* DMA31 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA31_YMOD                  ((volatile  int32_t *)REG_DMA31_YMOD)                   /* DMA31 Outer Loop Address Increment (2D only) */
-#define pREG_DMA31_DSCPTR_CUR            ((void * volatile *)REG_DMA31_DSCPTR_CUR)               /* DMA31 Current Descriptor Pointer */
-#define pREG_DMA31_DSCPTR_PRV            ((void * volatile *)REG_DMA31_DSCPTR_PRV)               /* DMA31 Previous Initial Descriptor Pointer */
-#define pREG_DMA31_ADDR_CUR              ((void * volatile *)REG_DMA31_ADDR_CUR)                 /* DMA31 Current Address */
-#define pREG_DMA31_STAT                  ((volatile uint32_t *)REG_DMA31_STAT)                   /* DMA31 Status Register */
-#define pREG_DMA31_XCNT_CUR              ((volatile uint32_t *)REG_DMA31_XCNT_CUR)               /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA31_YCNT_CUR              ((volatile uint32_t *)REG_DMA31_YCNT_CUR)               /* DMA31 Current Row Count (2D only) */
-#define pREG_DMA31_BWLCNT                ((volatile uint32_t *)REG_DMA31_BWLCNT)                 /* DMA31 Bandwidth Limit Count */
-#define pREG_DMA31_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWLCNT_CUR)             /* DMA31 Bandwidth Limit Count Current */
-#define pREG_DMA31_BWMCNT                ((volatile uint32_t *)REG_DMA31_BWMCNT)                 /* DMA31 Bandwidth Monitor Count */
-#define pREG_DMA31_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWMCNT_CUR)             /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA32
-   ========================================================================= */
-#define pREG_DMA32_DSCPTR_NXT            ((void * volatile *)REG_DMA32_DSCPTR_NXT)               /* DMA32 Pointer to Next Initial Descriptor */
-#define pREG_DMA32_ADDRSTART             ((void * volatile *)REG_DMA32_ADDRSTART)                /* DMA32 Start Address of Current Buffer */
-#define pREG_DMA32_CFG                   ((volatile uint32_t *)REG_DMA32_CFG)                    /* DMA32 Configuration Register */
-#define pREG_DMA32_XCNT                  ((volatile uint32_t *)REG_DMA32_XCNT)                   /* DMA32 Inner Loop Count Start Value */
-#define pREG_DMA32_XMOD                  ((volatile  int32_t *)REG_DMA32_XMOD)                   /* DMA32 Inner Loop Address Increment */
-#define pREG_DMA32_YCNT                  ((volatile uint32_t *)REG_DMA32_YCNT)                   /* DMA32 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA32_YMOD                  ((volatile  int32_t *)REG_DMA32_YMOD)                   /* DMA32 Outer Loop Address Increment (2D only) */
-#define pREG_DMA32_DSCPTR_CUR            ((void * volatile *)REG_DMA32_DSCPTR_CUR)               /* DMA32 Current Descriptor Pointer */
-#define pREG_DMA32_DSCPTR_PRV            ((void * volatile *)REG_DMA32_DSCPTR_PRV)               /* DMA32 Previous Initial Descriptor Pointer */
-#define pREG_DMA32_ADDR_CUR              ((void * volatile *)REG_DMA32_ADDR_CUR)                 /* DMA32 Current Address */
-#define pREG_DMA32_STAT                  ((volatile uint32_t *)REG_DMA32_STAT)                   /* DMA32 Status Register */
-#define pREG_DMA32_XCNT_CUR              ((volatile uint32_t *)REG_DMA32_XCNT_CUR)               /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA32_YCNT_CUR              ((volatile uint32_t *)REG_DMA32_YCNT_CUR)               /* DMA32 Current Row Count (2D only) */
-#define pREG_DMA32_BWLCNT                ((volatile uint32_t *)REG_DMA32_BWLCNT)                 /* DMA32 Bandwidth Limit Count */
-#define pREG_DMA32_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWLCNT_CUR)             /* DMA32 Bandwidth Limit Count Current */
-#define pREG_DMA32_BWMCNT                ((volatile uint32_t *)REG_DMA32_BWMCNT)                 /* DMA32 Bandwidth Monitor Count */
-#define pREG_DMA32_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWMCNT_CUR)             /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA33
-   ========================================================================= */
-#define pREG_DMA33_DSCPTR_NXT            ((void * volatile *)REG_DMA33_DSCPTR_NXT)               /* DMA33 Pointer to Next Initial Descriptor */
-#define pREG_DMA33_ADDRSTART             ((void * volatile *)REG_DMA33_ADDRSTART)                /* DMA33 Start Address of Current Buffer */
-#define pREG_DMA33_CFG                   ((volatile uint32_t *)REG_DMA33_CFG)                    /* DMA33 Configuration Register */
-#define pREG_DMA33_XCNT                  ((volatile uint32_t *)REG_DMA33_XCNT)                   /* DMA33 Inner Loop Count Start Value */
-#define pREG_DMA33_XMOD                  ((volatile  int32_t *)REG_DMA33_XMOD)                   /* DMA33 Inner Loop Address Increment */
-#define pREG_DMA33_YCNT                  ((volatile uint32_t *)REG_DMA33_YCNT)                   /* DMA33 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA33_YMOD                  ((volatile  int32_t *)REG_DMA33_YMOD)                   /* DMA33 Outer Loop Address Increment (2D only) */
-#define pREG_DMA33_DSCPTR_CUR            ((void * volatile *)REG_DMA33_DSCPTR_CUR)               /* DMA33 Current Descriptor Pointer */
-#define pREG_DMA33_DSCPTR_PRV            ((void * volatile *)REG_DMA33_DSCPTR_PRV)               /* DMA33 Previous Initial Descriptor Pointer */
-#define pREG_DMA33_ADDR_CUR              ((void * volatile *)REG_DMA33_ADDR_CUR)                 /* DMA33 Current Address */
-#define pREG_DMA33_STAT                  ((volatile uint32_t *)REG_DMA33_STAT)                   /* DMA33 Status Register */
-#define pREG_DMA33_XCNT_CUR              ((volatile uint32_t *)REG_DMA33_XCNT_CUR)               /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA33_YCNT_CUR              ((volatile uint32_t *)REG_DMA33_YCNT_CUR)               /* DMA33 Current Row Count (2D only) */
-#define pREG_DMA33_BWLCNT                ((volatile uint32_t *)REG_DMA33_BWLCNT)                 /* DMA33 Bandwidth Limit Count */
-#define pREG_DMA33_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWLCNT_CUR)             /* DMA33 Bandwidth Limit Count Current */
-#define pREG_DMA33_BWMCNT                ((volatile uint32_t *)REG_DMA33_BWMCNT)                 /* DMA33 Bandwidth Monitor Count */
-#define pREG_DMA33_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWMCNT_CUR)             /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA34
-   ========================================================================= */
-#define pREG_DMA34_DSCPTR_NXT            ((void * volatile *)REG_DMA34_DSCPTR_NXT)               /* DMA34 Pointer to Next Initial Descriptor */
-#define pREG_DMA34_ADDRSTART             ((void * volatile *)REG_DMA34_ADDRSTART)                /* DMA34 Start Address of Current Buffer */
-#define pREG_DMA34_CFG                   ((volatile uint32_t *)REG_DMA34_CFG)                    /* DMA34 Configuration Register */
-#define pREG_DMA34_XCNT                  ((volatile uint32_t *)REG_DMA34_XCNT)                   /* DMA34 Inner Loop Count Start Value */
-#define pREG_DMA34_XMOD                  ((volatile  int32_t *)REG_DMA34_XMOD)                   /* DMA34 Inner Loop Address Increment */
-#define pREG_DMA34_YCNT                  ((volatile uint32_t *)REG_DMA34_YCNT)                   /* DMA34 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA34_YMOD                  ((volatile  int32_t *)REG_DMA34_YMOD)                   /* DMA34 Outer Loop Address Increment (2D only) */
-#define pREG_DMA34_DSCPTR_CUR            ((void * volatile *)REG_DMA34_DSCPTR_CUR)               /* DMA34 Current Descriptor Pointer */
-#define pREG_DMA34_DSCPTR_PRV            ((void * volatile *)REG_DMA34_DSCPTR_PRV)               /* DMA34 Previous Initial Descriptor Pointer */
-#define pREG_DMA34_ADDR_CUR              ((void * volatile *)REG_DMA34_ADDR_CUR)                 /* DMA34 Current Address */
-#define pREG_DMA34_STAT                  ((volatile uint32_t *)REG_DMA34_STAT)                   /* DMA34 Status Register */
-#define pREG_DMA34_XCNT_CUR              ((volatile uint32_t *)REG_DMA34_XCNT_CUR)               /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA34_YCNT_CUR              ((volatile uint32_t *)REG_DMA34_YCNT_CUR)               /* DMA34 Current Row Count (2D only) */
-#define pREG_DMA34_BWLCNT                ((volatile uint32_t *)REG_DMA34_BWLCNT)                 /* DMA34 Bandwidth Limit Count */
-#define pREG_DMA34_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWLCNT_CUR)             /* DMA34 Bandwidth Limit Count Current */
-#define pREG_DMA34_BWMCNT                ((volatile uint32_t *)REG_DMA34_BWMCNT)                 /* DMA34 Bandwidth Monitor Count */
-#define pREG_DMA34_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWMCNT_CUR)             /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA35
-   ========================================================================= */
-#define pREG_DMA35_DSCPTR_NXT            ((void * volatile *)REG_DMA35_DSCPTR_NXT)               /* DMA35 Pointer to Next Initial Descriptor */
-#define pREG_DMA35_ADDRSTART             ((void * volatile *)REG_DMA35_ADDRSTART)                /* DMA35 Start Address of Current Buffer */
-#define pREG_DMA35_CFG                   ((volatile uint32_t *)REG_DMA35_CFG)                    /* DMA35 Configuration Register */
-#define pREG_DMA35_XCNT                  ((volatile uint32_t *)REG_DMA35_XCNT)                   /* DMA35 Inner Loop Count Start Value */
-#define pREG_DMA35_XMOD                  ((volatile  int32_t *)REG_DMA35_XMOD)                   /* DMA35 Inner Loop Address Increment */
-#define pREG_DMA35_YCNT                  ((volatile uint32_t *)REG_DMA35_YCNT)                   /* DMA35 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA35_YMOD                  ((volatile  int32_t *)REG_DMA35_YMOD)                   /* DMA35 Outer Loop Address Increment (2D only) */
-#define pREG_DMA35_DSCPTR_CUR            ((void * volatile *)REG_DMA35_DSCPTR_CUR)               /* DMA35 Current Descriptor Pointer */
-#define pREG_DMA35_DSCPTR_PRV            ((void * volatile *)REG_DMA35_DSCPTR_PRV)               /* DMA35 Previous Initial Descriptor Pointer */
-#define pREG_DMA35_ADDR_CUR              ((void * volatile *)REG_DMA35_ADDR_CUR)                 /* DMA35 Current Address */
-#define pREG_DMA35_STAT                  ((volatile uint32_t *)REG_DMA35_STAT)                   /* DMA35 Status Register */
-#define pREG_DMA35_XCNT_CUR              ((volatile uint32_t *)REG_DMA35_XCNT_CUR)               /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA35_YCNT_CUR              ((volatile uint32_t *)REG_DMA35_YCNT_CUR)               /* DMA35 Current Row Count (2D only) */
-#define pREG_DMA35_BWLCNT                ((volatile uint32_t *)REG_DMA35_BWLCNT)                 /* DMA35 Bandwidth Limit Count */
-#define pREG_DMA35_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWLCNT_CUR)             /* DMA35 Bandwidth Limit Count Current */
-#define pREG_DMA35_BWMCNT                ((volatile uint32_t *)REG_DMA35_BWMCNT)                 /* DMA35 Bandwidth Monitor Count */
-#define pREG_DMA35_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWMCNT_CUR)             /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA36
-   ========================================================================= */
-#define pREG_DMA36_DSCPTR_NXT            ((void * volatile *)REG_DMA36_DSCPTR_NXT)               /* DMA36 Pointer to Next Initial Descriptor */
-#define pREG_DMA36_ADDRSTART             ((void * volatile *)REG_DMA36_ADDRSTART)                /* DMA36 Start Address of Current Buffer */
-#define pREG_DMA36_CFG                   ((volatile uint32_t *)REG_DMA36_CFG)                    /* DMA36 Configuration Register */
-#define pREG_DMA36_XCNT                  ((volatile uint32_t *)REG_DMA36_XCNT)                   /* DMA36 Inner Loop Count Start Value */
-#define pREG_DMA36_XMOD                  ((volatile  int32_t *)REG_DMA36_XMOD)                   /* DMA36 Inner Loop Address Increment */
-#define pREG_DMA36_YCNT                  ((volatile uint32_t *)REG_DMA36_YCNT)                   /* DMA36 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA36_YMOD                  ((volatile  int32_t *)REG_DMA36_YMOD)                   /* DMA36 Outer Loop Address Increment (2D only) */
-#define pREG_DMA36_DSCPTR_CUR            ((void * volatile *)REG_DMA36_DSCPTR_CUR)               /* DMA36 Current Descriptor Pointer */
-#define pREG_DMA36_DSCPTR_PRV            ((void * volatile *)REG_DMA36_DSCPTR_PRV)               /* DMA36 Previous Initial Descriptor Pointer */
-#define pREG_DMA36_ADDR_CUR              ((void * volatile *)REG_DMA36_ADDR_CUR)                 /* DMA36 Current Address */
-#define pREG_DMA36_STAT                  ((volatile uint32_t *)REG_DMA36_STAT)                   /* DMA36 Status Register */
-#define pREG_DMA36_XCNT_CUR              ((volatile uint32_t *)REG_DMA36_XCNT_CUR)               /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA36_YCNT_CUR              ((volatile uint32_t *)REG_DMA36_YCNT_CUR)               /* DMA36 Current Row Count (2D only) */
-#define pREG_DMA36_BWLCNT                ((volatile uint32_t *)REG_DMA36_BWLCNT)                 /* DMA36 Bandwidth Limit Count */
-#define pREG_DMA36_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWLCNT_CUR)             /* DMA36 Bandwidth Limit Count Current */
-#define pREG_DMA36_BWMCNT                ((volatile uint32_t *)REG_DMA36_BWMCNT)                 /* DMA36 Bandwidth Monitor Count */
-#define pREG_DMA36_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWMCNT_CUR)             /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA37
-   ========================================================================= */
-#define pREG_DMA37_DSCPTR_NXT            ((void * volatile *)REG_DMA37_DSCPTR_NXT)               /* DMA37 Pointer to Next Initial Descriptor */
-#define pREG_DMA37_ADDRSTART             ((void * volatile *)REG_DMA37_ADDRSTART)                /* DMA37 Start Address of Current Buffer */
-#define pREG_DMA37_CFG                   ((volatile uint32_t *)REG_DMA37_CFG)                    /* DMA37 Configuration Register */
-#define pREG_DMA37_XCNT                  ((volatile uint32_t *)REG_DMA37_XCNT)                   /* DMA37 Inner Loop Count Start Value */
-#define pREG_DMA37_XMOD                  ((volatile  int32_t *)REG_DMA37_XMOD)                   /* DMA37 Inner Loop Address Increment */
-#define pREG_DMA37_YCNT                  ((volatile uint32_t *)REG_DMA37_YCNT)                   /* DMA37 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA37_YMOD                  ((volatile  int32_t *)REG_DMA37_YMOD)                   /* DMA37 Outer Loop Address Increment (2D only) */
-#define pREG_DMA37_DSCPTR_CUR            ((void * volatile *)REG_DMA37_DSCPTR_CUR)               /* DMA37 Current Descriptor Pointer */
-#define pREG_DMA37_DSCPTR_PRV            ((void * volatile *)REG_DMA37_DSCPTR_PRV)               /* DMA37 Previous Initial Descriptor Pointer */
-#define pREG_DMA37_ADDR_CUR              ((void * volatile *)REG_DMA37_ADDR_CUR)                 /* DMA37 Current Address */
-#define pREG_DMA37_STAT                  ((volatile uint32_t *)REG_DMA37_STAT)                   /* DMA37 Status Register */
-#define pREG_DMA37_XCNT_CUR              ((volatile uint32_t *)REG_DMA37_XCNT_CUR)               /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA37_YCNT_CUR              ((volatile uint32_t *)REG_DMA37_YCNT_CUR)               /* DMA37 Current Row Count (2D only) */
-#define pREG_DMA37_BWLCNT                ((volatile uint32_t *)REG_DMA37_BWLCNT)                 /* DMA37 Bandwidth Limit Count */
-#define pREG_DMA37_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWLCNT_CUR)             /* DMA37 Bandwidth Limit Count Current */
-#define pREG_DMA37_BWMCNT                ((volatile uint32_t *)REG_DMA37_BWMCNT)                 /* DMA37 Bandwidth Monitor Count */
-#define pREG_DMA37_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWMCNT_CUR)             /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA38
-   ========================================================================= */
-#define pREG_DMA38_DSCPTR_NXT            ((void * volatile *)REG_DMA38_DSCPTR_NXT)               /* DMA38 Pointer to Next Initial Descriptor */
-#define pREG_DMA38_ADDRSTART             ((void * volatile *)REG_DMA38_ADDRSTART)                /* DMA38 Start Address of Current Buffer */
-#define pREG_DMA38_CFG                   ((volatile uint32_t *)REG_DMA38_CFG)                    /* DMA38 Configuration Register */
-#define pREG_DMA38_XCNT                  ((volatile uint32_t *)REG_DMA38_XCNT)                   /* DMA38 Inner Loop Count Start Value */
-#define pREG_DMA38_XMOD                  ((volatile  int32_t *)REG_DMA38_XMOD)                   /* DMA38 Inner Loop Address Increment */
-#define pREG_DMA38_YCNT                  ((volatile uint32_t *)REG_DMA38_YCNT)                   /* DMA38 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA38_YMOD                  ((volatile  int32_t *)REG_DMA38_YMOD)                   /* DMA38 Outer Loop Address Increment (2D only) */
-#define pREG_DMA38_DSCPTR_CUR            ((void * volatile *)REG_DMA38_DSCPTR_CUR)               /* DMA38 Current Descriptor Pointer */
-#define pREG_DMA38_DSCPTR_PRV            ((void * volatile *)REG_DMA38_DSCPTR_PRV)               /* DMA38 Previous Initial Descriptor Pointer */
-#define pREG_DMA38_ADDR_CUR              ((void * volatile *)REG_DMA38_ADDR_CUR)                 /* DMA38 Current Address */
-#define pREG_DMA38_STAT                  ((volatile uint32_t *)REG_DMA38_STAT)                   /* DMA38 Status Register */
-#define pREG_DMA38_XCNT_CUR              ((volatile uint32_t *)REG_DMA38_XCNT_CUR)               /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA38_YCNT_CUR              ((volatile uint32_t *)REG_DMA38_YCNT_CUR)               /* DMA38 Current Row Count (2D only) */
-#define pREG_DMA38_BWLCNT                ((volatile uint32_t *)REG_DMA38_BWLCNT)                 /* DMA38 Bandwidth Limit Count */
-#define pREG_DMA38_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWLCNT_CUR)             /* DMA38 Bandwidth Limit Count Current */
-#define pREG_DMA38_BWMCNT                ((volatile uint32_t *)REG_DMA38_BWMCNT)                 /* DMA38 Bandwidth Monitor Count */
-#define pREG_DMA38_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWMCNT_CUR)             /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA39
-   ========================================================================= */
-#define pREG_DMA39_DSCPTR_NXT            ((void * volatile *)REG_DMA39_DSCPTR_NXT)               /* DMA39 Pointer to Next Initial Descriptor */
-#define pREG_DMA39_ADDRSTART             ((void * volatile *)REG_DMA39_ADDRSTART)                /* DMA39 Start Address of Current Buffer */
-#define pREG_DMA39_CFG                   ((volatile uint32_t *)REG_DMA39_CFG)                    /* DMA39 Configuration Register */
-#define pREG_DMA39_XCNT                  ((volatile uint32_t *)REG_DMA39_XCNT)                   /* DMA39 Inner Loop Count Start Value */
-#define pREG_DMA39_XMOD                  ((volatile  int32_t *)REG_DMA39_XMOD)                   /* DMA39 Inner Loop Address Increment */
-#define pREG_DMA39_YCNT                  ((volatile uint32_t *)REG_DMA39_YCNT)                   /* DMA39 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA39_YMOD                  ((volatile  int32_t *)REG_DMA39_YMOD)                   /* DMA39 Outer Loop Address Increment (2D only) */
-#define pREG_DMA39_DSCPTR_CUR            ((void * volatile *)REG_DMA39_DSCPTR_CUR)               /* DMA39 Current Descriptor Pointer */
-#define pREG_DMA39_DSCPTR_PRV            ((void * volatile *)REG_DMA39_DSCPTR_PRV)               /* DMA39 Previous Initial Descriptor Pointer */
-#define pREG_DMA39_ADDR_CUR              ((void * volatile *)REG_DMA39_ADDR_CUR)                 /* DMA39 Current Address */
-#define pREG_DMA39_STAT                  ((volatile uint32_t *)REG_DMA39_STAT)                   /* DMA39 Status Register */
-#define pREG_DMA39_XCNT_CUR              ((volatile uint32_t *)REG_DMA39_XCNT_CUR)               /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA39_YCNT_CUR              ((volatile uint32_t *)REG_DMA39_YCNT_CUR)               /* DMA39 Current Row Count (2D only) */
-#define pREG_DMA39_BWLCNT                ((volatile uint32_t *)REG_DMA39_BWLCNT)                 /* DMA39 Bandwidth Limit Count */
-#define pREG_DMA39_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWLCNT_CUR)             /* DMA39 Bandwidth Limit Count Current */
-#define pREG_DMA39_BWMCNT                ((volatile uint32_t *)REG_DMA39_BWMCNT)                 /* DMA39 Bandwidth Monitor Count */
-#define pREG_DMA39_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWMCNT_CUR)             /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA40
-   ========================================================================= */
-#define pREG_DMA40_DSCPTR_NXT            ((void * volatile *)REG_DMA40_DSCPTR_NXT)               /* DMA40 Pointer to Next Initial Descriptor */
-#define pREG_DMA40_ADDRSTART             ((void * volatile *)REG_DMA40_ADDRSTART)                /* DMA40 Start Address of Current Buffer */
-#define pREG_DMA40_CFG                   ((volatile uint32_t *)REG_DMA40_CFG)                    /* DMA40 Configuration Register */
-#define pREG_DMA40_XCNT                  ((volatile uint32_t *)REG_DMA40_XCNT)                   /* DMA40 Inner Loop Count Start Value */
-#define pREG_DMA40_XMOD                  ((volatile  int32_t *)REG_DMA40_XMOD)                   /* DMA40 Inner Loop Address Increment */
-#define pREG_DMA40_YCNT                  ((volatile uint32_t *)REG_DMA40_YCNT)                   /* DMA40 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA40_YMOD                  ((volatile  int32_t *)REG_DMA40_YMOD)                   /* DMA40 Outer Loop Address Increment (2D only) */
-#define pREG_DMA40_DSCPTR_CUR            ((void * volatile *)REG_DMA40_DSCPTR_CUR)               /* DMA40 Current Descriptor Pointer */
-#define pREG_DMA40_DSCPTR_PRV            ((void * volatile *)REG_DMA40_DSCPTR_PRV)               /* DMA40 Previous Initial Descriptor Pointer */
-#define pREG_DMA40_ADDR_CUR              ((void * volatile *)REG_DMA40_ADDR_CUR)                 /* DMA40 Current Address */
-#define pREG_DMA40_STAT                  ((volatile uint32_t *)REG_DMA40_STAT)                   /* DMA40 Status Register */
-#define pREG_DMA40_XCNT_CUR              ((volatile uint32_t *)REG_DMA40_XCNT_CUR)               /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA40_YCNT_CUR              ((volatile uint32_t *)REG_DMA40_YCNT_CUR)               /* DMA40 Current Row Count (2D only) */
-#define pREG_DMA40_BWLCNT                ((volatile uint32_t *)REG_DMA40_BWLCNT)                 /* DMA40 Bandwidth Limit Count */
-#define pREG_DMA40_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWLCNT_CUR)             /* DMA40 Bandwidth Limit Count Current */
-#define pREG_DMA40_BWMCNT                ((volatile uint32_t *)REG_DMA40_BWMCNT)                 /* DMA40 Bandwidth Monitor Count */
-#define pREG_DMA40_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWMCNT_CUR)             /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA41
-   ========================================================================= */
-#define pREG_DMA41_DSCPTR_NXT            ((void * volatile *)REG_DMA41_DSCPTR_NXT)               /* DMA41 Pointer to Next Initial Descriptor */
-#define pREG_DMA41_ADDRSTART             ((void * volatile *)REG_DMA41_ADDRSTART)                /* DMA41 Start Address of Current Buffer */
-#define pREG_DMA41_CFG                   ((volatile uint32_t *)REG_DMA41_CFG)                    /* DMA41 Configuration Register */
-#define pREG_DMA41_XCNT                  ((volatile uint32_t *)REG_DMA41_XCNT)                   /* DMA41 Inner Loop Count Start Value */
-#define pREG_DMA41_XMOD                  ((volatile  int32_t *)REG_DMA41_XMOD)                   /* DMA41 Inner Loop Address Increment */
-#define pREG_DMA41_YCNT                  ((volatile uint32_t *)REG_DMA41_YCNT)                   /* DMA41 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA41_YMOD                  ((volatile  int32_t *)REG_DMA41_YMOD)                   /* DMA41 Outer Loop Address Increment (2D only) */
-#define pREG_DMA41_DSCPTR_CUR            ((void * volatile *)REG_DMA41_DSCPTR_CUR)               /* DMA41 Current Descriptor Pointer */
-#define pREG_DMA41_DSCPTR_PRV            ((void * volatile *)REG_DMA41_DSCPTR_PRV)               /* DMA41 Previous Initial Descriptor Pointer */
-#define pREG_DMA41_ADDR_CUR              ((void * volatile *)REG_DMA41_ADDR_CUR)                 /* DMA41 Current Address */
-#define pREG_DMA41_STAT                  ((volatile uint32_t *)REG_DMA41_STAT)                   /* DMA41 Status Register */
-#define pREG_DMA41_XCNT_CUR              ((volatile uint32_t *)REG_DMA41_XCNT_CUR)               /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA41_YCNT_CUR              ((volatile uint32_t *)REG_DMA41_YCNT_CUR)               /* DMA41 Current Row Count (2D only) */
-#define pREG_DMA41_BWLCNT                ((volatile uint32_t *)REG_DMA41_BWLCNT)                 /* DMA41 Bandwidth Limit Count */
-#define pREG_DMA41_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWLCNT_CUR)             /* DMA41 Bandwidth Limit Count Current */
-#define pREG_DMA41_BWMCNT                ((volatile uint32_t *)REG_DMA41_BWMCNT)                 /* DMA41 Bandwidth Monitor Count */
-#define pREG_DMA41_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWMCNT_CUR)             /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA42
-   ========================================================================= */
-#define pREG_DMA42_DSCPTR_NXT            ((void * volatile *)REG_DMA42_DSCPTR_NXT)               /* DMA42 Pointer to Next Initial Descriptor */
-#define pREG_DMA42_ADDRSTART             ((void * volatile *)REG_DMA42_ADDRSTART)                /* DMA42 Start Address of Current Buffer */
-#define pREG_DMA42_CFG                   ((volatile uint32_t *)REG_DMA42_CFG)                    /* DMA42 Configuration Register */
-#define pREG_DMA42_XCNT                  ((volatile uint32_t *)REG_DMA42_XCNT)                   /* DMA42 Inner Loop Count Start Value */
-#define pREG_DMA42_XMOD                  ((volatile  int32_t *)REG_DMA42_XMOD)                   /* DMA42 Inner Loop Address Increment */
-#define pREG_DMA42_YCNT                  ((volatile uint32_t *)REG_DMA42_YCNT)                   /* DMA42 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA42_YMOD                  ((volatile  int32_t *)REG_DMA42_YMOD)                   /* DMA42 Outer Loop Address Increment (2D only) */
-#define pREG_DMA42_DSCPTR_CUR            ((void * volatile *)REG_DMA42_DSCPTR_CUR)               /* DMA42 Current Descriptor Pointer */
-#define pREG_DMA42_DSCPTR_PRV            ((void * volatile *)REG_DMA42_DSCPTR_PRV)               /* DMA42 Previous Initial Descriptor Pointer */
-#define pREG_DMA42_ADDR_CUR              ((void * volatile *)REG_DMA42_ADDR_CUR)                 /* DMA42 Current Address */
-#define pREG_DMA42_STAT                  ((volatile uint32_t *)REG_DMA42_STAT)                   /* DMA42 Status Register */
-#define pREG_DMA42_XCNT_CUR              ((volatile uint32_t *)REG_DMA42_XCNT_CUR)               /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA42_YCNT_CUR              ((volatile uint32_t *)REG_DMA42_YCNT_CUR)               /* DMA42 Current Row Count (2D only) */
-#define pREG_DMA42_BWLCNT                ((volatile uint32_t *)REG_DMA42_BWLCNT)                 /* DMA42 Bandwidth Limit Count */
-#define pREG_DMA42_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWLCNT_CUR)             /* DMA42 Bandwidth Limit Count Current */
-#define pREG_DMA42_BWMCNT                ((volatile uint32_t *)REG_DMA42_BWMCNT)                 /* DMA42 Bandwidth Monitor Count */
-#define pREG_DMA42_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWMCNT_CUR)             /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA43
-   ========================================================================= */
-#define pREG_DMA43_DSCPTR_NXT            ((void * volatile *)REG_DMA43_DSCPTR_NXT)               /* DMA43 Pointer to Next Initial Descriptor */
-#define pREG_DMA43_ADDRSTART             ((void * volatile *)REG_DMA43_ADDRSTART)                /* DMA43 Start Address of Current Buffer */
-#define pREG_DMA43_CFG                   ((volatile uint32_t *)REG_DMA43_CFG)                    /* DMA43 Configuration Register */
-#define pREG_DMA43_XCNT                  ((volatile uint32_t *)REG_DMA43_XCNT)                   /* DMA43 Inner Loop Count Start Value */
-#define pREG_DMA43_XMOD                  ((volatile  int32_t *)REG_DMA43_XMOD)                   /* DMA43 Inner Loop Address Increment */
-#define pREG_DMA43_YCNT                  ((volatile uint32_t *)REG_DMA43_YCNT)                   /* DMA43 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA43_YMOD                  ((volatile  int32_t *)REG_DMA43_YMOD)                   /* DMA43 Outer Loop Address Increment (2D only) */
-#define pREG_DMA43_DSCPTR_CUR            ((void * volatile *)REG_DMA43_DSCPTR_CUR)               /* DMA43 Current Descriptor Pointer */
-#define pREG_DMA43_DSCPTR_PRV            ((void * volatile *)REG_DMA43_DSCPTR_PRV)               /* DMA43 Previous Initial Descriptor Pointer */
-#define pREG_DMA43_ADDR_CUR              ((void * volatile *)REG_DMA43_ADDR_CUR)                 /* DMA43 Current Address */
-#define pREG_DMA43_STAT                  ((volatile uint32_t *)REG_DMA43_STAT)                   /* DMA43 Status Register */
-#define pREG_DMA43_XCNT_CUR              ((volatile uint32_t *)REG_DMA43_XCNT_CUR)               /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA43_YCNT_CUR              ((volatile uint32_t *)REG_DMA43_YCNT_CUR)               /* DMA43 Current Row Count (2D only) */
-#define pREG_DMA43_BWLCNT                ((volatile uint32_t *)REG_DMA43_BWLCNT)                 /* DMA43 Bandwidth Limit Count */
-#define pREG_DMA43_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWLCNT_CUR)             /* DMA43 Bandwidth Limit Count Current */
-#define pREG_DMA43_BWMCNT                ((volatile uint32_t *)REG_DMA43_BWMCNT)                 /* DMA43 Bandwidth Monitor Count */
-#define pREG_DMA43_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWMCNT_CUR)             /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA44
-   ========================================================================= */
-#define pREG_DMA44_DSCPTR_NXT            ((void * volatile *)REG_DMA44_DSCPTR_NXT)               /* DMA44 Pointer to Next Initial Descriptor */
-#define pREG_DMA44_ADDRSTART             ((void * volatile *)REG_DMA44_ADDRSTART)                /* DMA44 Start Address of Current Buffer */
-#define pREG_DMA44_CFG                   ((volatile uint32_t *)REG_DMA44_CFG)                    /* DMA44 Configuration Register */
-#define pREG_DMA44_XCNT                  ((volatile uint32_t *)REG_DMA44_XCNT)                   /* DMA44 Inner Loop Count Start Value */
-#define pREG_DMA44_XMOD                  ((volatile  int32_t *)REG_DMA44_XMOD)                   /* DMA44 Inner Loop Address Increment */
-#define pREG_DMA44_YCNT                  ((volatile uint32_t *)REG_DMA44_YCNT)                   /* DMA44 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA44_YMOD                  ((volatile  int32_t *)REG_DMA44_YMOD)                   /* DMA44 Outer Loop Address Increment (2D only) */
-#define pREG_DMA44_DSCPTR_CUR            ((void * volatile *)REG_DMA44_DSCPTR_CUR)               /* DMA44 Current Descriptor Pointer */
-#define pREG_DMA44_DSCPTR_PRV            ((void * volatile *)REG_DMA44_DSCPTR_PRV)               /* DMA44 Previous Initial Descriptor Pointer */
-#define pREG_DMA44_ADDR_CUR              ((void * volatile *)REG_DMA44_ADDR_CUR)                 /* DMA44 Current Address */
-#define pREG_DMA44_STAT                  ((volatile uint32_t *)REG_DMA44_STAT)                   /* DMA44 Status Register */
-#define pREG_DMA44_XCNT_CUR              ((volatile uint32_t *)REG_DMA44_XCNT_CUR)               /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA44_YCNT_CUR              ((volatile uint32_t *)REG_DMA44_YCNT_CUR)               /* DMA44 Current Row Count (2D only) */
-#define pREG_DMA44_BWLCNT                ((volatile uint32_t *)REG_DMA44_BWLCNT)                 /* DMA44 Bandwidth Limit Count */
-#define pREG_DMA44_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWLCNT_CUR)             /* DMA44 Bandwidth Limit Count Current */
-#define pREG_DMA44_BWMCNT                ((volatile uint32_t *)REG_DMA44_BWMCNT)                 /* DMA44 Bandwidth Monitor Count */
-#define pREG_DMA44_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWMCNT_CUR)             /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA45
-   ========================================================================= */
-#define pREG_DMA45_DSCPTR_NXT            ((void * volatile *)REG_DMA45_DSCPTR_NXT)               /* DMA45 Pointer to Next Initial Descriptor */
-#define pREG_DMA45_ADDRSTART             ((void * volatile *)REG_DMA45_ADDRSTART)                /* DMA45 Start Address of Current Buffer */
-#define pREG_DMA45_CFG                   ((volatile uint32_t *)REG_DMA45_CFG)                    /* DMA45 Configuration Register */
-#define pREG_DMA45_XCNT                  ((volatile uint32_t *)REG_DMA45_XCNT)                   /* DMA45 Inner Loop Count Start Value */
-#define pREG_DMA45_XMOD                  ((volatile  int32_t *)REG_DMA45_XMOD)                   /* DMA45 Inner Loop Address Increment */
-#define pREG_DMA45_YCNT                  ((volatile uint32_t *)REG_DMA45_YCNT)                   /* DMA45 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA45_YMOD                  ((volatile  int32_t *)REG_DMA45_YMOD)                   /* DMA45 Outer Loop Address Increment (2D only) */
-#define pREG_DMA45_DSCPTR_CUR            ((void * volatile *)REG_DMA45_DSCPTR_CUR)               /* DMA45 Current Descriptor Pointer */
-#define pREG_DMA45_DSCPTR_PRV            ((void * volatile *)REG_DMA45_DSCPTR_PRV)               /* DMA45 Previous Initial Descriptor Pointer */
-#define pREG_DMA45_ADDR_CUR              ((void * volatile *)REG_DMA45_ADDR_CUR)                 /* DMA45 Current Address */
-#define pREG_DMA45_STAT                  ((volatile uint32_t *)REG_DMA45_STAT)                   /* DMA45 Status Register */
-#define pREG_DMA45_XCNT_CUR              ((volatile uint32_t *)REG_DMA45_XCNT_CUR)               /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA45_YCNT_CUR              ((volatile uint32_t *)REG_DMA45_YCNT_CUR)               /* DMA45 Current Row Count (2D only) */
-#define pREG_DMA45_BWLCNT                ((volatile uint32_t *)REG_DMA45_BWLCNT)                 /* DMA45 Bandwidth Limit Count */
-#define pREG_DMA45_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWLCNT_CUR)             /* DMA45 Bandwidth Limit Count Current */
-#define pREG_DMA45_BWMCNT                ((volatile uint32_t *)REG_DMA45_BWMCNT)                 /* DMA45 Bandwidth Monitor Count */
-#define pREG_DMA45_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWMCNT_CUR)             /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA46
-   ========================================================================= */
-#define pREG_DMA46_DSCPTR_NXT            ((void * volatile *)REG_DMA46_DSCPTR_NXT)               /* DMA46 Pointer to Next Initial Descriptor */
-#define pREG_DMA46_ADDRSTART             ((void * volatile *)REG_DMA46_ADDRSTART)                /* DMA46 Start Address of Current Buffer */
-#define pREG_DMA46_CFG                   ((volatile uint32_t *)REG_DMA46_CFG)                    /* DMA46 Configuration Register */
-#define pREG_DMA46_XCNT                  ((volatile uint32_t *)REG_DMA46_XCNT)                   /* DMA46 Inner Loop Count Start Value */
-#define pREG_DMA46_XMOD                  ((volatile  int32_t *)REG_DMA46_XMOD)                   /* DMA46 Inner Loop Address Increment */
-#define pREG_DMA46_YCNT                  ((volatile uint32_t *)REG_DMA46_YCNT)                   /* DMA46 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA46_YMOD                  ((volatile  int32_t *)REG_DMA46_YMOD)                   /* DMA46 Outer Loop Address Increment (2D only) */
-#define pREG_DMA46_DSCPTR_CUR            ((void * volatile *)REG_DMA46_DSCPTR_CUR)               /* DMA46 Current Descriptor Pointer */
-#define pREG_DMA46_DSCPTR_PRV            ((void * volatile *)REG_DMA46_DSCPTR_PRV)               /* DMA46 Previous Initial Descriptor Pointer */
-#define pREG_DMA46_ADDR_CUR              ((void * volatile *)REG_DMA46_ADDR_CUR)                 /* DMA46 Current Address */
-#define pREG_DMA46_STAT                  ((volatile uint32_t *)REG_DMA46_STAT)                   /* DMA46 Status Register */
-#define pREG_DMA46_XCNT_CUR              ((volatile uint32_t *)REG_DMA46_XCNT_CUR)               /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA46_YCNT_CUR              ((volatile uint32_t *)REG_DMA46_YCNT_CUR)               /* DMA46 Current Row Count (2D only) */
-#define pREG_DMA46_BWLCNT                ((volatile uint32_t *)REG_DMA46_BWLCNT)                 /* DMA46 Bandwidth Limit Count */
-#define pREG_DMA46_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWLCNT_CUR)             /* DMA46 Bandwidth Limit Count Current */
-#define pREG_DMA46_BWMCNT                ((volatile uint32_t *)REG_DMA46_BWMCNT)                 /* DMA46 Bandwidth Monitor Count */
-#define pREG_DMA46_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWMCNT_CUR)             /* DMA46 Bandwidth Monitor Count Current */
-
-
-/* =========================================================================
-       ACM0
-   ========================================================================= */
-#define pREG_ACM0_CTL                    ((volatile uint32_t *)REG_ACM0_CTL)                     /* ACM0 ACM Control Register */
-#define pREG_ACM0_TC0                    ((volatile uint32_t *)REG_ACM0_TC0)                     /* ACM0 ACM Timing Configuration 0 Register */
-#define pREG_ACM0_TC1                    ((volatile uint32_t *)REG_ACM0_TC1)                     /* ACM0 ACM Timing Configuration 1 Register */
-#define pREG_ACM0_STAT                   ((volatile uint32_t *)REG_ACM0_STAT)                    /* ACM0 ACM Status Register */
-#define pREG_ACM0_EVSTAT                 ((volatile uint32_t *)REG_ACM0_EVSTAT)                  /* ACM0 ACM Event Status Register */
-#define pREG_ACM0_EVMSK                  ((volatile uint32_t *)REG_ACM0_EVMSK)                   /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define pREG_ACM0_MEVSTAT                ((volatile uint32_t *)REG_ACM0_MEVSTAT)                 /* ACM0 ACM Missed Event Status Register */
-#define pREG_ACM0_MEVMSK                 ((volatile uint32_t *)REG_ACM0_MEVMSK)                  /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define pREG_ACM0_EVCTL0                 ((volatile uint32_t *)REG_ACM0_EVCTL0)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL1                 ((volatile uint32_t *)REG_ACM0_EVCTL1)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL2                 ((volatile uint32_t *)REG_ACM0_EVCTL2)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL3                 ((volatile uint32_t *)REG_ACM0_EVCTL3)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL4                 ((volatile uint32_t *)REG_ACM0_EVCTL4)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL5                 ((volatile uint32_t *)REG_ACM0_EVCTL5)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL6                 ((volatile uint32_t *)REG_ACM0_EVCTL6)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL7                 ((volatile uint32_t *)REG_ACM0_EVCTL7)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL8                 ((volatile uint32_t *)REG_ACM0_EVCTL8)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL9                 ((volatile uint32_t *)REG_ACM0_EVCTL9)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL10                ((volatile uint32_t *)REG_ACM0_EVCTL10)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL11                ((volatile uint32_t *)REG_ACM0_EVCTL11)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL12                ((volatile uint32_t *)REG_ACM0_EVCTL12)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL13                ((volatile uint32_t *)REG_ACM0_EVCTL13)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL14                ((volatile uint32_t *)REG_ACM0_EVCTL14)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL15                ((volatile uint32_t *)REG_ACM0_EVCTL15)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVTIME0                ((volatile uint32_t *)REG_ACM0_EVTIME0)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME1                ((volatile uint32_t *)REG_ACM0_EVTIME1)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME2                ((volatile uint32_t *)REG_ACM0_EVTIME2)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME3                ((volatile uint32_t *)REG_ACM0_EVTIME3)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME4                ((volatile uint32_t *)REG_ACM0_EVTIME4)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME5                ((volatile uint32_t *)REG_ACM0_EVTIME5)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME6                ((volatile uint32_t *)REG_ACM0_EVTIME6)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME7                ((volatile uint32_t *)REG_ACM0_EVTIME7)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME8                ((volatile uint32_t *)REG_ACM0_EVTIME8)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME9                ((volatile uint32_t *)REG_ACM0_EVTIME9)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME10               ((volatile uint32_t *)REG_ACM0_EVTIME10)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME11               ((volatile uint32_t *)REG_ACM0_EVTIME11)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME12               ((volatile uint32_t *)REG_ACM0_EVTIME12)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME13               ((volatile uint32_t *)REG_ACM0_EVTIME13)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME14               ((volatile uint32_t *)REG_ACM0_EVTIME14)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME15               ((volatile uint32_t *)REG_ACM0_EVTIME15)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVORD0                 ((volatile uint32_t *)REG_ACM0_EVORD0)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD1                 ((volatile uint32_t *)REG_ACM0_EVORD1)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD2                 ((volatile uint32_t *)REG_ACM0_EVORD2)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD3                 ((volatile uint32_t *)REG_ACM0_EVORD3)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD4                 ((volatile uint32_t *)REG_ACM0_EVORD4)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD5                 ((volatile uint32_t *)REG_ACM0_EVORD5)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD6                 ((volatile uint32_t *)REG_ACM0_EVORD6)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD7                 ((volatile uint32_t *)REG_ACM0_EVORD7)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD8                 ((volatile uint32_t *)REG_ACM0_EVORD8)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD9                 ((volatile uint32_t *)REG_ACM0_EVORD9)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD10                ((volatile uint32_t *)REG_ACM0_EVORD10)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD11                ((volatile uint32_t *)REG_ACM0_EVORD11)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD12                ((volatile uint32_t *)REG_ACM0_EVORD12)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD13                ((volatile uint32_t *)REG_ACM0_EVORD13)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD14                ((volatile uint32_t *)REG_ACM0_EVORD14)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD15                ((volatile uint32_t *)REG_ACM0_EVORD15)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_TMR0                   ((volatile uint32_t *)REG_ACM0_TMR0)                    /* ACM0 ACM Timer 0 Register */
-#define pREG_ACM0_TMR1                   ((volatile uint32_t *)REG_ACM0_TMR1)                    /* ACM0 ACM Timer 1 Register */
-
-
-/* =========================================================================
-       DMC0
-   ========================================================================= */
-#define pREG_DMC0_CTL                    ((volatile uint32_t *)REG_DMC0_CTL)                     /* DMC0 Control Register */
-#define pREG_DMC0_STAT                   ((volatile uint32_t *)REG_DMC0_STAT)                    /* DMC0 Status Register */
-#define pREG_DMC0_EFFCTL                 ((volatile uint32_t *)REG_DMC0_EFFCTL)                  /* DMC0 Efficiency Control Register */
-#define pREG_DMC0_PRIO                   ((volatile uint32_t *)REG_DMC0_PRIO)                    /* DMC0 Priority ID Register */
-#define pREG_DMC0_PRIOMSK                ((volatile uint32_t *)REG_DMC0_PRIOMSK)                 /* DMC0 Priority ID Mask Register */
-#define pREG_DMC0_CFG                    ((volatile uint32_t *)REG_DMC0_CFG)                     /* DMC0 Configuration Register */
-#define pREG_DMC0_TR0                    ((volatile uint32_t *)REG_DMC0_TR0)                     /* DMC0 Timing 0 Register */
-#define pREG_DMC0_TR1                    ((volatile uint32_t *)REG_DMC0_TR1)                     /* DMC0 Timing 1 Register */
-#define pREG_DMC0_TR2                    ((volatile uint32_t *)REG_DMC0_TR2)                     /* DMC0 Timing 2 Register */
-#define pREG_DMC0_MSK                    ((volatile uint32_t *)REG_DMC0_MSK)                     /* DMC0 Mask (Mode Register Shadow) Register */
-#define pREG_DMC0_MR                     ((volatile uint32_t *)REG_DMC0_MR)                      /* DMC0 Shadow MR Register */
-#define pREG_DMC0_EMR1                   ((volatile uint32_t *)REG_DMC0_EMR1)                    /* DMC0 Shadow EMR1 Register */
-#define pREG_DMC0_EMR2                   ((volatile uint32_t *)REG_DMC0_EMR2)                    /* DMC0 Shadow EMR2 Register */
-#define pREG_DMC0_EMR3                   ((volatile uint32_t *)REG_DMC0_EMR3)                    /* DMC0 Shadow EMR3 Register */
-#define pREG_DMC0_DLLCTL                 ((volatile uint32_t *)REG_DMC0_DLLCTL)                  /* DMC0 DLL Control Register */
-#define pREG_DMC0_PHY_CTL0               ((volatile uint32_t *)REG_DMC0_PHY_CTL0)                /* DMC0 PHY Control 0 Register */
-#define pREG_DMC0_PHY_CTL1               ((volatile uint32_t *)REG_DMC0_PHY_CTL1)                /* DMC0 PHY Control 1 Register */
-#define pREG_DMC0_PHY_CTL2               ((volatile uint32_t *)REG_DMC0_PHY_CTL2)                /* DMC0 PHY Control 2 Register */
-#define pREG_DMC0_PHY_CTL3               ((volatile uint32_t *)REG_DMC0_PHY_CTL3)                /* DMC0 PHY Control 3 Register */
-#define pREG_DMC0_PADCTL                 ((volatile uint32_t *)REG_DMC0_PADCTL)                  /* DMC0 PAD Control Register */
-
-
-/* =========================================================================
-       SCB0
-   ========================================================================= */
-#define pREG_SCB0_ARBR0                  ((volatile uint32_t *)REG_SCB0_ARBR0)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR1                  ((volatile uint32_t *)REG_SCB0_ARBR1)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR2                  ((volatile uint32_t *)REG_SCB0_ARBR2)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR3                  ((volatile uint32_t *)REG_SCB0_ARBR3)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR4                  ((volatile uint32_t *)REG_SCB0_ARBR4)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR5                  ((volatile uint32_t *)REG_SCB0_ARBR5)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBW0                  ((volatile uint32_t *)REG_SCB0_ARBW0)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW1                  ((volatile uint32_t *)REG_SCB0_ARBW1)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW2                  ((volatile uint32_t *)REG_SCB0_ARBW2)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW3                  ((volatile uint32_t *)REG_SCB0_ARBW3)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW4                  ((volatile uint32_t *)REG_SCB0_ARBW4)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW5                  ((volatile uint32_t *)REG_SCB0_ARBW5)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_SLAVES                 ((volatile uint32_t *)REG_SCB0_SLAVES)                  /* SCB0 Slave Interfaces Number Register */
-#define pREG_SCB0_MASTERS                ((volatile uint32_t *)REG_SCB0_MASTERS)                 /* SCB0 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB1
-   ========================================================================= */
-#define pREG_SCB1_ARBR0                  ((volatile uint32_t *)REG_SCB1_ARBR0)                   /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB1_ARBW0                  ((volatile uint32_t *)REG_SCB1_ARBW0)                   /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB1_SLAVES                 ((volatile uint32_t *)REG_SCB1_SLAVES)                  /* SCB1 Slave Interfaces Number Register */
-#define pREG_SCB1_MASTERS                ((volatile uint32_t *)REG_SCB1_MASTERS)                 /* SCB1 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB2
-   ========================================================================= */
-#define pREG_SCB2_ARBR0                  ((volatile uint32_t *)REG_SCB2_ARBR0)                   /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB2_ARBW0                  ((volatile uint32_t *)REG_SCB2_ARBW0)                   /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB2_SLAVES                 ((volatile uint32_t *)REG_SCB2_SLAVES)                  /* SCB2 Slave Interfaces Number Register */
-#define pREG_SCB2_MASTERS                ((volatile uint32_t *)REG_SCB2_MASTERS)                 /* SCB2 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB3
-   ========================================================================= */
-#define pREG_SCB3_ARBR0                  ((volatile uint32_t *)REG_SCB3_ARBR0)                   /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB3_ARBW0                  ((volatile uint32_t *)REG_SCB3_ARBW0)                   /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB3_SLAVES                 ((volatile uint32_t *)REG_SCB3_SLAVES)                  /* SCB3 Slave Interfaces Number Register */
-#define pREG_SCB3_MASTERS                ((volatile uint32_t *)REG_SCB3_MASTERS)                 /* SCB3 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB4
-   ========================================================================= */
-#define pREG_SCB4_ARBR0                  ((volatile uint32_t *)REG_SCB4_ARBR0)                   /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB4_ARBW0                  ((volatile uint32_t *)REG_SCB4_ARBW0)                   /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB4_SLAVES                 ((volatile uint32_t *)REG_SCB4_SLAVES)                  /* SCB4 Slave Interfaces Number Register */
-#define pREG_SCB4_MASTERS                ((volatile uint32_t *)REG_SCB4_MASTERS)                 /* SCB4 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB5
-   ========================================================================= */
-#define pREG_SCB5_ARBR0                  ((volatile uint32_t *)REG_SCB5_ARBR0)                   /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB5_ARBW0                  ((volatile uint32_t *)REG_SCB5_ARBW0)                   /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB5_SLAVES                 ((volatile uint32_t *)REG_SCB5_SLAVES)                  /* SCB5 Slave Interfaces Number Register */
-#define pREG_SCB5_MASTERS                ((volatile uint32_t *)REG_SCB5_MASTERS)                 /* SCB5 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB6
-   ========================================================================= */
-#define pREG_SCB6_ARBR0                  ((volatile uint32_t *)REG_SCB6_ARBR0)                   /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB6_ARBW0                  ((volatile uint32_t *)REG_SCB6_ARBW0)                   /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB6_SLAVES                 ((volatile uint32_t *)REG_SCB6_SLAVES)                  /* SCB6 Slave Interfaces Number Register */
-#define pREG_SCB6_MASTERS                ((volatile uint32_t *)REG_SCB6_MASTERS)                 /* SCB6 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB7
-   ========================================================================= */
-#define pREG_SCB7_ARBR0                  ((volatile uint32_t *)REG_SCB7_ARBR0)                   /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB7_ARBW0                  ((volatile uint32_t *)REG_SCB7_ARBW0)                   /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB7_SLAVES                 ((volatile uint32_t *)REG_SCB7_SLAVES)                  /* SCB7 Slave Interfaces Number Register */
-#define pREG_SCB7_MASTERS                ((volatile uint32_t *)REG_SCB7_MASTERS)                 /* SCB7 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB8
-   ========================================================================= */
-#define pREG_SCB8_ARBR0                  ((volatile uint32_t *)REG_SCB8_ARBR0)                   /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB8_ARBW0                  ((volatile uint32_t *)REG_SCB8_ARBW0)                   /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB8_SLAVES                 ((volatile uint32_t *)REG_SCB8_SLAVES)                  /* SCB8 Slave Interfaces Number Register */
-#define pREG_SCB8_MASTERS                ((volatile uint32_t *)REG_SCB8_MASTERS)                 /* SCB8 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB9
-   ========================================================================= */
-#define pREG_SCB9_ARBR0                  ((volatile uint32_t *)REG_SCB9_ARBR0)                   /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB9_ARBW0                  ((volatile uint32_t *)REG_SCB9_ARBW0)                   /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB9_SLAVES                 ((volatile uint32_t *)REG_SCB9_SLAVES)                  /* SCB9 Slave Interfaces Number Register */
-#define pREG_SCB9_MASTERS                ((volatile uint32_t *)REG_SCB9_MASTERS)                 /* SCB9 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB10
-   ========================================================================= */
-#define pREG_SCB10_ARBR0                 ((volatile uint32_t *)REG_SCB10_ARBR0)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR1                 ((volatile uint32_t *)REG_SCB10_ARBR1)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR2                 ((volatile uint32_t *)REG_SCB10_ARBR2)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBW0                 ((volatile uint32_t *)REG_SCB10_ARBW0)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW1                 ((volatile uint32_t *)REG_SCB10_ARBW1)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW2                 ((volatile uint32_t *)REG_SCB10_ARBW2)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_SLAVES                ((volatile uint32_t *)REG_SCB10_SLAVES)                 /* SCB10 Slave Interfaces Number Register */
-#define pREG_SCB10_MASTERS               ((volatile uint32_t *)REG_SCB10_MASTERS)                /* SCB10 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB11
-   ========================================================================= */
-#define pREG_SCB11_ARBR0                 ((volatile uint32_t *)REG_SCB11_ARBR0)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR1                 ((volatile uint32_t *)REG_SCB11_ARBR1)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR2                 ((volatile uint32_t *)REG_SCB11_ARBR2)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR3                 ((volatile uint32_t *)REG_SCB11_ARBR3)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR4                 ((volatile uint32_t *)REG_SCB11_ARBR4)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR5                 ((volatile uint32_t *)REG_SCB11_ARBR5)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR6                 ((volatile uint32_t *)REG_SCB11_ARBR6)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBW0                 ((volatile uint32_t *)REG_SCB11_ARBW0)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW1                 ((volatile uint32_t *)REG_SCB11_ARBW1)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW2                 ((volatile uint32_t *)REG_SCB11_ARBW2)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW3                 ((volatile uint32_t *)REG_SCB11_ARBW3)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW4                 ((volatile uint32_t *)REG_SCB11_ARBW4)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW5                 ((volatile uint32_t *)REG_SCB11_ARBW5)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW6                 ((volatile uint32_t *)REG_SCB11_ARBW6)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_SLAVES                ((volatile uint32_t *)REG_SCB11_SLAVES)                 /* SCB11 Slave Interfaces Number Register */
-#define pREG_SCB11_MASTERS               ((volatile uint32_t *)REG_SCB11_MASTERS)                /* SCB11 Master Interfaces Number Register */
-
-
-/* =========================================================================
-       L2CTL0
-   ========================================================================= */
-#define pREG_L2CTL0_CTL                  ((volatile uint32_t *)REG_L2CTL0_CTL)                   /* L2CTL0 Control Register */
-#define pREG_L2CTL0_ACTL_C0              ((volatile uint32_t *)REG_L2CTL0_ACTL_C0)               /* L2CTL0 Access Control Core 0 Register */
-#define pREG_L2CTL0_ACTL_C1              ((volatile uint32_t *)REG_L2CTL0_ACTL_C1)               /* L2CTL0 Access Control Core 1 Register */
-#define pREG_L2CTL0_ACTL_SYS             ((volatile uint32_t *)REG_L2CTL0_ACTL_SYS)              /* L2CTL0 Access Control System Register */
-#define pREG_L2CTL0_STAT                 ((volatile uint32_t *)REG_L2CTL0_STAT)                  /* L2CTL0 Status Register */
-#define pREG_L2CTL0_RPCR                 ((volatile uint32_t *)REG_L2CTL0_RPCR)                  /* L2CTL0 Read Priority Count Register */
-#define pREG_L2CTL0_WPCR                 ((volatile uint32_t *)REG_L2CTL0_WPCR)                  /* L2CTL0 Write Priority Count Register */
-#define pREG_L2CTL0_RFA                  ((void * volatile *)REG_L2CTL0_RFA)                     /* L2CTL0 Refresh Address Register */
-#define pREG_L2CTL0_ERRADDR0             ((void * volatile *)REG_L2CTL0_ERRADDR0)                /* L2CTL0 ECC Error Address 0 Register */
-#define pREG_L2CTL0_ERRADDR1             ((void * volatile *)REG_L2CTL0_ERRADDR1)                /* L2CTL0 ECC Error Address 1 Register */
-#define pREG_L2CTL0_ERRADDR2             ((void * volatile *)REG_L2CTL0_ERRADDR2)                /* L2CTL0 ECC Error Address 2 Register */
-#define pREG_L2CTL0_ERRADDR3             ((void * volatile *)REG_L2CTL0_ERRADDR3)                /* L2CTL0 ECC Error Address 3 Register */
-#define pREG_L2CTL0_ERRADDR4             ((void * volatile *)REG_L2CTL0_ERRADDR4)                /* L2CTL0 ECC Error Address 4 Register */
-#define pREG_L2CTL0_ERRADDR5             ((void * volatile *)REG_L2CTL0_ERRADDR5)                /* L2CTL0 ECC Error Address 5 Register */
-#define pREG_L2CTL0_ERRADDR6             ((void * volatile *)REG_L2CTL0_ERRADDR6)                /* L2CTL0 ECC Error Address 6 Register */
-#define pREG_L2CTL0_ERRADDR7             ((void * volatile *)REG_L2CTL0_ERRADDR7)                /* L2CTL0 ECC Error Address 7 Register */
-#define pREG_L2CTL0_ET0                  ((volatile uint32_t *)REG_L2CTL0_ET0)                   /* L2CTL0 Error Type 0 Register */
-#define pREG_L2CTL0_EADDR0               ((void * volatile *)REG_L2CTL0_EADDR0)                  /* L2CTL0 Error Type 0 Address Register */
-#define pREG_L2CTL0_ET1                  ((volatile uint32_t *)REG_L2CTL0_ET1)                   /* L2CTL0 Error Type 1 Register */
-#define pREG_L2CTL0_EADDR1               ((void * volatile *)REG_L2CTL0_EADDR1)                  /* L2CTL0 Error Type 1 Address Register */
-
-
-/* =========================================================================
-       SEC0
-   ========================================================================= */
-
-/*    SEC Core Interface (SCI) Registers    */
-#define pREG_SEC0_CCTL0                  ((volatile uint32_t *)REG_SEC0_CCTL0)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CCTL1                  ((volatile uint32_t *)REG_SEC0_CCTL1)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CSTAT0                 ((volatile uint32_t *)REG_SEC0_CSTAT0)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CSTAT1                 ((volatile uint32_t *)REG_SEC0_CSTAT1)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CPND0                  ((volatile uint32_t *)REG_SEC0_CPND0)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CPND1                  ((volatile uint32_t *)REG_SEC0_CPND1)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CACT0                  ((volatile uint32_t *)REG_SEC0_CACT0)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CACT1                  ((volatile uint32_t *)REG_SEC0_CACT1)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CPMSK0                 ((volatile uint32_t *)REG_SEC0_CPMSK0)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CPMSK1                 ((volatile uint32_t *)REG_SEC0_CPMSK1)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CGMSK0                 ((volatile uint32_t *)REG_SEC0_CGMSK0)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CGMSK1                 ((volatile uint32_t *)REG_SEC0_CGMSK1)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CPLVL0                 ((volatile uint32_t *)REG_SEC0_CPLVL0)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CPLVL1                 ((volatile uint32_t *)REG_SEC0_CPLVL1)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CSID0                  ((volatile uint32_t *)REG_SEC0_CSID0)                   /* SEC0 SCI Source ID Register n */
-#define pREG_SEC0_CSID1                  ((volatile uint32_t *)REG_SEC0_CSID1)                   /* SEC0 SCI Source ID Register n */
-
-/*    SEC Fault Management Interface (SFI) Registers    */
-#define pREG_SEC0_FCTL                   ((volatile uint32_t *)REG_SEC0_FCTL)                    /* SEC0 Fault Control Register */
-#define pREG_SEC0_FSTAT                  ((volatile uint32_t *)REG_SEC0_FSTAT)                   /* SEC0 Fault Status Register */
-#define pREG_SEC0_FSID                   ((volatile uint32_t *)REG_SEC0_FSID)                    /* SEC0 Fault Source ID Register */
-#define pREG_SEC0_FEND                   ((volatile uint32_t *)REG_SEC0_FEND)                    /* SEC0 Fault End Register */
-#define pREG_SEC0_FDLY                   ((volatile uint32_t *)REG_SEC0_FDLY)                    /* SEC0 Fault Delay Register */
-#define pREG_SEC0_FDLY_CUR               ((volatile uint32_t *)REG_SEC0_FDLY_CUR)                /* SEC0 Fault Delay Current Register */
-#define pREG_SEC0_FSRDLY                 ((volatile uint32_t *)REG_SEC0_FSRDLY)                  /* SEC0 Fault System Reset Delay Register */
-#define pREG_SEC0_FSRDLY_CUR             ((volatile uint32_t *)REG_SEC0_FSRDLY_CUR)              /* SEC0 Fault System Reset Delay Current Register */
-#define pREG_SEC0_FCOPP                  ((volatile uint32_t *)REG_SEC0_FCOPP)                   /* SEC0 Fault COP Period Register */
-#define pREG_SEC0_FCOPP_CUR              ((volatile uint32_t *)REG_SEC0_FCOPP_CUR)               /* SEC0 Fault COP Period Current Register */
-
-/*    SEC Global Registers    */
-#define pREG_SEC0_GCTL                   ((volatile uint32_t *)REG_SEC0_GCTL)                    /* SEC0 Global Control Register */
-#define pREG_SEC0_GSTAT                  ((volatile uint32_t *)REG_SEC0_GSTAT)                   /* SEC0 Global Status Register */
-#define pREG_SEC0_RAISE                  ((volatile uint32_t *)REG_SEC0_RAISE)                   /* SEC0 Global Raise Register */
-#define pREG_SEC0_END                    ((volatile uint32_t *)REG_SEC0_END)                     /* SEC0 Global End Register */
-
-/*    SEC Source Interface (SSI) Registers    */
-#define pREG_SEC0_SCTL0                  ((volatile uint32_t *)REG_SEC0_SCTL0)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL1                  ((volatile uint32_t *)REG_SEC0_SCTL1)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL2                  ((volatile uint32_t *)REG_SEC0_SCTL2)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL3                  ((volatile uint32_t *)REG_SEC0_SCTL3)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL4                  ((volatile uint32_t *)REG_SEC0_SCTL4)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL5                  ((volatile uint32_t *)REG_SEC0_SCTL5)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL6                  ((volatile uint32_t *)REG_SEC0_SCTL6)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL7                  ((volatile uint32_t *)REG_SEC0_SCTL7)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL8                  ((volatile uint32_t *)REG_SEC0_SCTL8)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL9                  ((volatile uint32_t *)REG_SEC0_SCTL9)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL10                 ((volatile uint32_t *)REG_SEC0_SCTL10)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL11                 ((volatile uint32_t *)REG_SEC0_SCTL11)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL12                 ((volatile uint32_t *)REG_SEC0_SCTL12)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL13                 ((volatile uint32_t *)REG_SEC0_SCTL13)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL14                 ((volatile uint32_t *)REG_SEC0_SCTL14)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL15                 ((volatile uint32_t *)REG_SEC0_SCTL15)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL16                 ((volatile uint32_t *)REG_SEC0_SCTL16)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL17                 ((volatile uint32_t *)REG_SEC0_SCTL17)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL18                 ((volatile uint32_t *)REG_SEC0_SCTL18)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL19                 ((volatile uint32_t *)REG_SEC0_SCTL19)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL20                 ((volatile uint32_t *)REG_SEC0_SCTL20)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL21                 ((volatile uint32_t *)REG_SEC0_SCTL21)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL22                 ((volatile uint32_t *)REG_SEC0_SCTL22)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL23                 ((volatile uint32_t *)REG_SEC0_SCTL23)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL24                 ((volatile uint32_t *)REG_SEC0_SCTL24)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL25                 ((volatile uint32_t *)REG_SEC0_SCTL25)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL26                 ((volatile uint32_t *)REG_SEC0_SCTL26)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL27                 ((volatile uint32_t *)REG_SEC0_SCTL27)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL28                 ((volatile uint32_t *)REG_SEC0_SCTL28)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL29                 ((volatile uint32_t *)REG_SEC0_SCTL29)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL30                 ((volatile uint32_t *)REG_SEC0_SCTL30)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL31                 ((volatile uint32_t *)REG_SEC0_SCTL31)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL32                 ((volatile uint32_t *)REG_SEC0_SCTL32)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL33                 ((volatile uint32_t *)REG_SEC0_SCTL33)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL34                 ((volatile uint32_t *)REG_SEC0_SCTL34)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL35                 ((volatile uint32_t *)REG_SEC0_SCTL35)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL36                 ((volatile uint32_t *)REG_SEC0_SCTL36)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL37                 ((volatile uint32_t *)REG_SEC0_SCTL37)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL38                 ((volatile uint32_t *)REG_SEC0_SCTL38)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL39                 ((volatile uint32_t *)REG_SEC0_SCTL39)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL40                 ((volatile uint32_t *)REG_SEC0_SCTL40)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL41                 ((volatile uint32_t *)REG_SEC0_SCTL41)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL42                 ((volatile uint32_t *)REG_SEC0_SCTL42)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL43                 ((volatile uint32_t *)REG_SEC0_SCTL43)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL44                 ((volatile uint32_t *)REG_SEC0_SCTL44)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL45                 ((volatile uint32_t *)REG_SEC0_SCTL45)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL46                 ((volatile uint32_t *)REG_SEC0_SCTL46)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL47                 ((volatile uint32_t *)REG_SEC0_SCTL47)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL48                 ((volatile uint32_t *)REG_SEC0_SCTL48)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL49                 ((volatile uint32_t *)REG_SEC0_SCTL49)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL50                 ((volatile uint32_t *)REG_SEC0_SCTL50)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL51                 ((volatile uint32_t *)REG_SEC0_SCTL51)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL52                 ((volatile uint32_t *)REG_SEC0_SCTL52)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL53                 ((volatile uint32_t *)REG_SEC0_SCTL53)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL54                 ((volatile uint32_t *)REG_SEC0_SCTL54)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL55                 ((volatile uint32_t *)REG_SEC0_SCTL55)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL56                 ((volatile uint32_t *)REG_SEC0_SCTL56)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL57                 ((volatile uint32_t *)REG_SEC0_SCTL57)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL58                 ((volatile uint32_t *)REG_SEC0_SCTL58)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL59                 ((volatile uint32_t *)REG_SEC0_SCTL59)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL60                 ((volatile uint32_t *)REG_SEC0_SCTL60)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL61                 ((volatile uint32_t *)REG_SEC0_SCTL61)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL62                 ((volatile uint32_t *)REG_SEC0_SCTL62)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL63                 ((volatile uint32_t *)REG_SEC0_SCTL63)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL64                 ((volatile uint32_t *)REG_SEC0_SCTL64)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL65                 ((volatile uint32_t *)REG_SEC0_SCTL65)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL66                 ((volatile uint32_t *)REG_SEC0_SCTL66)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL67                 ((volatile uint32_t *)REG_SEC0_SCTL67)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL68                 ((volatile uint32_t *)REG_SEC0_SCTL68)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL69                 ((volatile uint32_t *)REG_SEC0_SCTL69)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL70                 ((volatile uint32_t *)REG_SEC0_SCTL70)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL71                 ((volatile uint32_t *)REG_SEC0_SCTL71)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL72                 ((volatile uint32_t *)REG_SEC0_SCTL72)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL73                 ((volatile uint32_t *)REG_SEC0_SCTL73)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL74                 ((volatile uint32_t *)REG_SEC0_SCTL74)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL75                 ((volatile uint32_t *)REG_SEC0_SCTL75)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL76                 ((volatile uint32_t *)REG_SEC0_SCTL76)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL77                 ((volatile uint32_t *)REG_SEC0_SCTL77)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL78                 ((volatile uint32_t *)REG_SEC0_SCTL78)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL79                 ((volatile uint32_t *)REG_SEC0_SCTL79)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL80                 ((volatile uint32_t *)REG_SEC0_SCTL80)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL81                 ((volatile uint32_t *)REG_SEC0_SCTL81)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL82                 ((volatile uint32_t *)REG_SEC0_SCTL82)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL83                 ((volatile uint32_t *)REG_SEC0_SCTL83)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL84                 ((volatile uint32_t *)REG_SEC0_SCTL84)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL85                 ((volatile uint32_t *)REG_SEC0_SCTL85)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL86                 ((volatile uint32_t *)REG_SEC0_SCTL86)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL87                 ((volatile uint32_t *)REG_SEC0_SCTL87)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL88                 ((volatile uint32_t *)REG_SEC0_SCTL88)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL89                 ((volatile uint32_t *)REG_SEC0_SCTL89)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL90                 ((volatile uint32_t *)REG_SEC0_SCTL90)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL91                 ((volatile uint32_t *)REG_SEC0_SCTL91)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL92                 ((volatile uint32_t *)REG_SEC0_SCTL92)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL93                 ((volatile uint32_t *)REG_SEC0_SCTL93)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL94                 ((volatile uint32_t *)REG_SEC0_SCTL94)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL95                 ((volatile uint32_t *)REG_SEC0_SCTL95)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL96                 ((volatile uint32_t *)REG_SEC0_SCTL96)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL97                 ((volatile uint32_t *)REG_SEC0_SCTL97)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL98                 ((volatile uint32_t *)REG_SEC0_SCTL98)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL99                 ((volatile uint32_t *)REG_SEC0_SCTL99)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL100                ((volatile uint32_t *)REG_SEC0_SCTL100)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL101                ((volatile uint32_t *)REG_SEC0_SCTL101)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL102                ((volatile uint32_t *)REG_SEC0_SCTL102)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL103                ((volatile uint32_t *)REG_SEC0_SCTL103)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL104                ((volatile uint32_t *)REG_SEC0_SCTL104)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL105                ((volatile uint32_t *)REG_SEC0_SCTL105)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL106                ((volatile uint32_t *)REG_SEC0_SCTL106)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL107                ((volatile uint32_t *)REG_SEC0_SCTL107)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL108                ((volatile uint32_t *)REG_SEC0_SCTL108)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL109                ((volatile uint32_t *)REG_SEC0_SCTL109)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL110                ((volatile uint32_t *)REG_SEC0_SCTL110)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL111                ((volatile uint32_t *)REG_SEC0_SCTL111)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL112                ((volatile uint32_t *)REG_SEC0_SCTL112)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL113                ((volatile uint32_t *)REG_SEC0_SCTL113)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL114                ((volatile uint32_t *)REG_SEC0_SCTL114)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL115                ((volatile uint32_t *)REG_SEC0_SCTL115)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL116                ((volatile uint32_t *)REG_SEC0_SCTL116)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL117                ((volatile uint32_t *)REG_SEC0_SCTL117)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL118                ((volatile uint32_t *)REG_SEC0_SCTL118)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL119                ((volatile uint32_t *)REG_SEC0_SCTL119)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL120                ((volatile uint32_t *)REG_SEC0_SCTL120)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL121                ((volatile uint32_t *)REG_SEC0_SCTL121)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL122                ((volatile uint32_t *)REG_SEC0_SCTL122)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL123                ((volatile uint32_t *)REG_SEC0_SCTL123)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL124                ((volatile uint32_t *)REG_SEC0_SCTL124)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL125                ((volatile uint32_t *)REG_SEC0_SCTL125)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL126                ((volatile uint32_t *)REG_SEC0_SCTL126)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL127                ((volatile uint32_t *)REG_SEC0_SCTL127)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL128                ((volatile uint32_t *)REG_SEC0_SCTL128)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL129                ((volatile uint32_t *)REG_SEC0_SCTL129)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL130                ((volatile uint32_t *)REG_SEC0_SCTL130)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL131                ((volatile uint32_t *)REG_SEC0_SCTL131)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL132                ((volatile uint32_t *)REG_SEC0_SCTL132)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL133                ((volatile uint32_t *)REG_SEC0_SCTL133)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL134                ((volatile uint32_t *)REG_SEC0_SCTL134)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL135                ((volatile uint32_t *)REG_SEC0_SCTL135)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL136                ((volatile uint32_t *)REG_SEC0_SCTL136)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL137                ((volatile uint32_t *)REG_SEC0_SCTL137)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL138                ((volatile uint32_t *)REG_SEC0_SCTL138)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL139                ((volatile uint32_t *)REG_SEC0_SCTL139)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SSTAT0                 ((volatile uint32_t *)REG_SEC0_SSTAT0)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT1                 ((volatile uint32_t *)REG_SEC0_SSTAT1)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT2                 ((volatile uint32_t *)REG_SEC0_SSTAT2)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT3                 ((volatile uint32_t *)REG_SEC0_SSTAT3)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT4                 ((volatile uint32_t *)REG_SEC0_SSTAT4)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT5                 ((volatile uint32_t *)REG_SEC0_SSTAT5)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT6                 ((volatile uint32_t *)REG_SEC0_SSTAT6)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT7                 ((volatile uint32_t *)REG_SEC0_SSTAT7)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT8                 ((volatile uint32_t *)REG_SEC0_SSTAT8)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT9                 ((volatile uint32_t *)REG_SEC0_SSTAT9)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT10                ((volatile uint32_t *)REG_SEC0_SSTAT10)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT11                ((volatile uint32_t *)REG_SEC0_SSTAT11)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT12                ((volatile uint32_t *)REG_SEC0_SSTAT12)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT13                ((volatile uint32_t *)REG_SEC0_SSTAT13)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT14                ((volatile uint32_t *)REG_SEC0_SSTAT14)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT15                ((volatile uint32_t *)REG_SEC0_SSTAT15)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT16                ((volatile uint32_t *)REG_SEC0_SSTAT16)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT17                ((volatile uint32_t *)REG_SEC0_SSTAT17)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT18                ((volatile uint32_t *)REG_SEC0_SSTAT18)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT19                ((volatile uint32_t *)REG_SEC0_SSTAT19)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT20                ((volatile uint32_t *)REG_SEC0_SSTAT20)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT21                ((volatile uint32_t *)REG_SEC0_SSTAT21)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT22                ((volatile uint32_t *)REG_SEC0_SSTAT22)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT23                ((volatile uint32_t *)REG_SEC0_SSTAT23)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT24                ((volatile uint32_t *)REG_SEC0_SSTAT24)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT25                ((volatile uint32_t *)REG_SEC0_SSTAT25)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT26                ((volatile uint32_t *)REG_SEC0_SSTAT26)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT27                ((volatile uint32_t *)REG_SEC0_SSTAT27)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT28                ((volatile uint32_t *)REG_SEC0_SSTAT28)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT29                ((volatile uint32_t *)REG_SEC0_SSTAT29)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT30                ((volatile uint32_t *)REG_SEC0_SSTAT30)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT31                ((volatile uint32_t *)REG_SEC0_SSTAT31)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT32                ((volatile uint32_t *)REG_SEC0_SSTAT32)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT33                ((volatile uint32_t *)REG_SEC0_SSTAT33)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT34                ((volatile uint32_t *)REG_SEC0_SSTAT34)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT35                ((volatile uint32_t *)REG_SEC0_SSTAT35)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT36                ((volatile uint32_t *)REG_SEC0_SSTAT36)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT37                ((volatile uint32_t *)REG_SEC0_SSTAT37)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT38                ((volatile uint32_t *)REG_SEC0_SSTAT38)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT39                ((volatile uint32_t *)REG_SEC0_SSTAT39)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT40                ((volatile uint32_t *)REG_SEC0_SSTAT40)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT41                ((volatile uint32_t *)REG_SEC0_SSTAT41)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT42                ((volatile uint32_t *)REG_SEC0_SSTAT42)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT43                ((volatile uint32_t *)REG_SEC0_SSTAT43)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT44                ((volatile uint32_t *)REG_SEC0_SSTAT44)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT45                ((volatile uint32_t *)REG_SEC0_SSTAT45)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT46                ((volatile uint32_t *)REG_SEC0_SSTAT46)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT47                ((volatile uint32_t *)REG_SEC0_SSTAT47)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT48                ((volatile uint32_t *)REG_SEC0_SSTAT48)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT49                ((volatile uint32_t *)REG_SEC0_SSTAT49)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT50                ((volatile uint32_t *)REG_SEC0_SSTAT50)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT51                ((volatile uint32_t *)REG_SEC0_SSTAT51)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT52                ((volatile uint32_t *)REG_SEC0_SSTAT52)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT53                ((volatile uint32_t *)REG_SEC0_SSTAT53)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT54                ((volatile uint32_t *)REG_SEC0_SSTAT54)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT55                ((volatile uint32_t *)REG_SEC0_SSTAT55)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT56                ((volatile uint32_t *)REG_SEC0_SSTAT56)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT57                ((volatile uint32_t *)REG_SEC0_SSTAT57)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT58                ((volatile uint32_t *)REG_SEC0_SSTAT58)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT59                ((volatile uint32_t *)REG_SEC0_SSTAT59)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT60                ((volatile uint32_t *)REG_SEC0_SSTAT60)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT61                ((volatile uint32_t *)REG_SEC0_SSTAT61)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT62                ((volatile uint32_t *)REG_SEC0_SSTAT62)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT63                ((volatile uint32_t *)REG_SEC0_SSTAT63)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT64                ((volatile uint32_t *)REG_SEC0_SSTAT64)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT65                ((volatile uint32_t *)REG_SEC0_SSTAT65)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT66                ((volatile uint32_t *)REG_SEC0_SSTAT66)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT67                ((volatile uint32_t *)REG_SEC0_SSTAT67)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT68                ((volatile uint32_t *)REG_SEC0_SSTAT68)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT69                ((volatile uint32_t *)REG_SEC0_SSTAT69)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT70                ((volatile uint32_t *)REG_SEC0_SSTAT70)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT71                ((volatile uint32_t *)REG_SEC0_SSTAT71)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT72                ((volatile uint32_t *)REG_SEC0_SSTAT72)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT73                ((volatile uint32_t *)REG_SEC0_SSTAT73)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT74                ((volatile uint32_t *)REG_SEC0_SSTAT74)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT75                ((volatile uint32_t *)REG_SEC0_SSTAT75)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT76                ((volatile uint32_t *)REG_SEC0_SSTAT76)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT77                ((volatile uint32_t *)REG_SEC0_SSTAT77)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT78                ((volatile uint32_t *)REG_SEC0_SSTAT78)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT79                ((volatile uint32_t *)REG_SEC0_SSTAT79)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT80                ((volatile uint32_t *)REG_SEC0_SSTAT80)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT81                ((volatile uint32_t *)REG_SEC0_SSTAT81)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT82                ((volatile uint32_t *)REG_SEC0_SSTAT82)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT83                ((volatile uint32_t *)REG_SEC0_SSTAT83)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT84                ((volatile uint32_t *)REG_SEC0_SSTAT84)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT85                ((volatile uint32_t *)REG_SEC0_SSTAT85)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT86                ((volatile uint32_t *)REG_SEC0_SSTAT86)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT87                ((volatile uint32_t *)REG_SEC0_SSTAT87)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT88                ((volatile uint32_t *)REG_SEC0_SSTAT88)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT89                ((volatile uint32_t *)REG_SEC0_SSTAT89)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT90                ((volatile uint32_t *)REG_SEC0_SSTAT90)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT91                ((volatile uint32_t *)REG_SEC0_SSTAT91)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT92                ((volatile uint32_t *)REG_SEC0_SSTAT92)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT93                ((volatile uint32_t *)REG_SEC0_SSTAT93)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT94                ((volatile uint32_t *)REG_SEC0_SSTAT94)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT95                ((volatile uint32_t *)REG_SEC0_SSTAT95)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT96                ((volatile uint32_t *)REG_SEC0_SSTAT96)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT97                ((volatile uint32_t *)REG_SEC0_SSTAT97)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT98                ((volatile uint32_t *)REG_SEC0_SSTAT98)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT99                ((volatile uint32_t *)REG_SEC0_SSTAT99)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT100               ((volatile uint32_t *)REG_SEC0_SSTAT100)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT101               ((volatile uint32_t *)REG_SEC0_SSTAT101)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT102               ((volatile uint32_t *)REG_SEC0_SSTAT102)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT103               ((volatile uint32_t *)REG_SEC0_SSTAT103)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT104               ((volatile uint32_t *)REG_SEC0_SSTAT104)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT105               ((volatile uint32_t *)REG_SEC0_SSTAT105)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT106               ((volatile uint32_t *)REG_SEC0_SSTAT106)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT107               ((volatile uint32_t *)REG_SEC0_SSTAT107)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT108               ((volatile uint32_t *)REG_SEC0_SSTAT108)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT109               ((volatile uint32_t *)REG_SEC0_SSTAT109)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT110               ((volatile uint32_t *)REG_SEC0_SSTAT110)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT111               ((volatile uint32_t *)REG_SEC0_SSTAT111)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT112               ((volatile uint32_t *)REG_SEC0_SSTAT112)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT113               ((volatile uint32_t *)REG_SEC0_SSTAT113)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT114               ((volatile uint32_t *)REG_SEC0_SSTAT114)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT115               ((volatile uint32_t *)REG_SEC0_SSTAT115)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT116               ((volatile uint32_t *)REG_SEC0_SSTAT116)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT117               ((volatile uint32_t *)REG_SEC0_SSTAT117)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT118               ((volatile uint32_t *)REG_SEC0_SSTAT118)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT119               ((volatile uint32_t *)REG_SEC0_SSTAT119)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT120               ((volatile uint32_t *)REG_SEC0_SSTAT120)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT121               ((volatile uint32_t *)REG_SEC0_SSTAT121)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT122               ((volatile uint32_t *)REG_SEC0_SSTAT122)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT123               ((volatile uint32_t *)REG_SEC0_SSTAT123)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT124               ((volatile uint32_t *)REG_SEC0_SSTAT124)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT125               ((volatile uint32_t *)REG_SEC0_SSTAT125)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT126               ((volatile uint32_t *)REG_SEC0_SSTAT126)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT127               ((volatile uint32_t *)REG_SEC0_SSTAT127)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT128               ((volatile uint32_t *)REG_SEC0_SSTAT128)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT129               ((volatile uint32_t *)REG_SEC0_SSTAT129)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT130               ((volatile uint32_t *)REG_SEC0_SSTAT130)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT131               ((volatile uint32_t *)REG_SEC0_SSTAT131)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT132               ((volatile uint32_t *)REG_SEC0_SSTAT132)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT133               ((volatile uint32_t *)REG_SEC0_SSTAT133)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT134               ((volatile uint32_t *)REG_SEC0_SSTAT134)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT135               ((volatile uint32_t *)REG_SEC0_SSTAT135)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT136               ((volatile uint32_t *)REG_SEC0_SSTAT136)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT137               ((volatile uint32_t *)REG_SEC0_SSTAT137)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT138               ((volatile uint32_t *)REG_SEC0_SSTAT138)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT139               ((volatile uint32_t *)REG_SEC0_SSTAT139)                /* SEC0 Source Status Register n */
-
-
-/* =========================================================================
-       TRU0
-   ========================================================================= */
-#define pREG_TRU0_SSR0                   ((volatile uint32_t *)REG_TRU0_SSR0)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR1                   ((volatile uint32_t *)REG_TRU0_SSR1)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR2                   ((volatile uint32_t *)REG_TRU0_SSR2)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR3                   ((volatile uint32_t *)REG_TRU0_SSR3)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR4                   ((volatile uint32_t *)REG_TRU0_SSR4)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR5                   ((volatile uint32_t *)REG_TRU0_SSR5)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR6                   ((volatile uint32_t *)REG_TRU0_SSR6)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR7                   ((volatile uint32_t *)REG_TRU0_SSR7)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR8                   ((volatile uint32_t *)REG_TRU0_SSR8)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR9                   ((volatile uint32_t *)REG_TRU0_SSR9)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR10                  ((volatile uint32_t *)REG_TRU0_SSR10)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR11                  ((volatile uint32_t *)REG_TRU0_SSR11)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR12                  ((volatile uint32_t *)REG_TRU0_SSR12)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR13                  ((volatile uint32_t *)REG_TRU0_SSR13)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR14                  ((volatile uint32_t *)REG_TRU0_SSR14)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR15                  ((volatile uint32_t *)REG_TRU0_SSR15)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR16                  ((volatile uint32_t *)REG_TRU0_SSR16)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR17                  ((volatile uint32_t *)REG_TRU0_SSR17)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR18                  ((volatile uint32_t *)REG_TRU0_SSR18)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR19                  ((volatile uint32_t *)REG_TRU0_SSR19)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR20                  ((volatile uint32_t *)REG_TRU0_SSR20)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR21                  ((volatile uint32_t *)REG_TRU0_SSR21)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR22                  ((volatile uint32_t *)REG_TRU0_SSR22)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR23                  ((volatile uint32_t *)REG_TRU0_SSR23)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR24                  ((volatile uint32_t *)REG_TRU0_SSR24)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR25                  ((volatile uint32_t *)REG_TRU0_SSR25)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR26                  ((volatile uint32_t *)REG_TRU0_SSR26)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR27                  ((volatile uint32_t *)REG_TRU0_SSR27)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR28                  ((volatile uint32_t *)REG_TRU0_SSR28)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR29                  ((volatile uint32_t *)REG_TRU0_SSR29)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR30                  ((volatile uint32_t *)REG_TRU0_SSR30)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR31                  ((volatile uint32_t *)REG_TRU0_SSR31)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR32                  ((volatile uint32_t *)REG_TRU0_SSR32)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR33                  ((volatile uint32_t *)REG_TRU0_SSR33)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR34                  ((volatile uint32_t *)REG_TRU0_SSR34)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR35                  ((volatile uint32_t *)REG_TRU0_SSR35)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR36                  ((volatile uint32_t *)REG_TRU0_SSR36)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR37                  ((volatile uint32_t *)REG_TRU0_SSR37)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR38                  ((volatile uint32_t *)REG_TRU0_SSR38)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR39                  ((volatile uint32_t *)REG_TRU0_SSR39)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR40                  ((volatile uint32_t *)REG_TRU0_SSR40)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR41                  ((volatile uint32_t *)REG_TRU0_SSR41)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR42                  ((volatile uint32_t *)REG_TRU0_SSR42)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR43                  ((volatile uint32_t *)REG_TRU0_SSR43)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR44                  ((volatile uint32_t *)REG_TRU0_SSR44)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR45                  ((volatile uint32_t *)REG_TRU0_SSR45)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR46                  ((volatile uint32_t *)REG_TRU0_SSR46)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR47                  ((volatile uint32_t *)REG_TRU0_SSR47)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR48                  ((volatile uint32_t *)REG_TRU0_SSR48)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR49                  ((volatile uint32_t *)REG_TRU0_SSR49)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR50                  ((volatile uint32_t *)REG_TRU0_SSR50)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR51                  ((volatile uint32_t *)REG_TRU0_SSR51)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR52                  ((volatile uint32_t *)REG_TRU0_SSR52)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR53                  ((volatile uint32_t *)REG_TRU0_SSR53)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR54                  ((volatile uint32_t *)REG_TRU0_SSR54)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR55                  ((volatile uint32_t *)REG_TRU0_SSR55)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR56                  ((volatile uint32_t *)REG_TRU0_SSR56)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR57                  ((volatile uint32_t *)REG_TRU0_SSR57)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR58                  ((volatile uint32_t *)REG_TRU0_SSR58)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR59                  ((volatile uint32_t *)REG_TRU0_SSR59)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR60                  ((volatile uint32_t *)REG_TRU0_SSR60)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR61                  ((volatile uint32_t *)REG_TRU0_SSR61)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR62                  ((volatile uint32_t *)REG_TRU0_SSR62)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR63                  ((volatile uint32_t *)REG_TRU0_SSR63)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR64                  ((volatile uint32_t *)REG_TRU0_SSR64)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR65                  ((volatile uint32_t *)REG_TRU0_SSR65)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR66                  ((volatile uint32_t *)REG_TRU0_SSR66)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR67                  ((volatile uint32_t *)REG_TRU0_SSR67)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR68                  ((volatile uint32_t *)REG_TRU0_SSR68)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR69                  ((volatile uint32_t *)REG_TRU0_SSR69)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR70                  ((volatile uint32_t *)REG_TRU0_SSR70)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR71                  ((volatile uint32_t *)REG_TRU0_SSR71)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR72                  ((volatile uint32_t *)REG_TRU0_SSR72)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR73                  ((volatile uint32_t *)REG_TRU0_SSR73)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR74                  ((volatile uint32_t *)REG_TRU0_SSR74)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR75                  ((volatile uint32_t *)REG_TRU0_SSR75)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR76                  ((volatile uint32_t *)REG_TRU0_SSR76)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR77                  ((volatile uint32_t *)REG_TRU0_SSR77)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR78                  ((volatile uint32_t *)REG_TRU0_SSR78)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR79                  ((volatile uint32_t *)REG_TRU0_SSR79)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR80                  ((volatile uint32_t *)REG_TRU0_SSR80)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR81                  ((volatile uint32_t *)REG_TRU0_SSR81)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR82                  ((volatile uint32_t *)REG_TRU0_SSR82)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR83                  ((volatile uint32_t *)REG_TRU0_SSR83)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR84                  ((volatile uint32_t *)REG_TRU0_SSR84)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR85                  ((volatile uint32_t *)REG_TRU0_SSR85)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR86                  ((volatile uint32_t *)REG_TRU0_SSR86)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_MTR                    ((volatile uint32_t *)REG_TRU0_MTR)                     /* TRU0 Master Trigger Register */
-#define pREG_TRU0_ERRADDR                ((volatile uint32_t *)REG_TRU0_ERRADDR)                 /* TRU0 Error Address Register */
-#define pREG_TRU0_STAT                   ((volatile uint32_t *)REG_TRU0_STAT)                    /* TRU0 Status Information Register */
-#define pREG_TRU0_REVID                  ((volatile uint32_t *)REG_TRU0_REVID)                   /* TRU0 Revision ID Register */
-#define pREG_TRU0_GCTL                   ((volatile uint32_t *)REG_TRU0_GCTL)                    /* TRU0 Global Control Register */
-
-
-/* =========================================================================
-       RCU0
-   ========================================================================= */
-#define pREG_RCU0_CTL                    ((volatile uint32_t *)REG_RCU0_CTL)                     /* RCU0 Control Register */
-#define pREG_RCU0_STAT                   ((volatile uint32_t *)REG_RCU0_STAT)                    /* RCU0 Status Register */
-#define pREG_RCU0_CRCTL                  ((volatile uint32_t *)REG_RCU0_CRCTL)                   /* RCU0 Core Reset Control Register */
-#define pREG_RCU0_CRSTAT                 ((volatile uint32_t *)REG_RCU0_CRSTAT)                  /* RCU0 Core Reset Status Register */
-#define pREG_RCU0_SIDIS                  ((volatile uint32_t *)REG_RCU0_SIDIS)                   /* RCU0 System Interface Disable Register */
-#define pREG_RCU0_SISTAT                 ((volatile uint32_t *)REG_RCU0_SISTAT)                  /* RCU0 System Interface Status Register */
-#define pREG_RCU0_SVECT_LCK              ((volatile uint32_t *)REG_RCU0_SVECT_LCK)               /* RCU0 SVECT Lock Register */
-#define pREG_RCU0_BCODE                  ((volatile uint32_t *)REG_RCU0_BCODE)                   /* RCU0 Boot Code Register */
-#define pREG_RCU0_SVECT0                 ((void * volatile *)REG_RCU0_SVECT0)                    /* RCU0 Software Vector Register n */
-#define pREG_RCU0_SVECT1                 ((void * volatile *)REG_RCU0_SVECT1)                    /* RCU0 Software Vector Register n */
-
-
-/* =========================================================================
-       SPU0
-   ========================================================================= */
-#define pREG_SPU0_CTL                    ((volatile uint32_t *)REG_SPU0_CTL)                     /* SPU0 Control Register */
-#define pREG_SPU0_STAT                   ((volatile uint32_t *)REG_SPU0_STAT)                    /* SPU0 Status Register */
-#define pREG_SPU0_WP0                    ((volatile uint32_t *)REG_SPU0_WP0)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP1                    ((volatile uint32_t *)REG_SPU0_WP1)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP2                    ((volatile uint32_t *)REG_SPU0_WP2)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP3                    ((volatile uint32_t *)REG_SPU0_WP3)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP4                    ((volatile uint32_t *)REG_SPU0_WP4)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP5                    ((volatile uint32_t *)REG_SPU0_WP5)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP6                    ((volatile uint32_t *)REG_SPU0_WP6)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP7                    ((volatile uint32_t *)REG_SPU0_WP7)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP8                    ((volatile uint32_t *)REG_SPU0_WP8)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP9                    ((volatile uint32_t *)REG_SPU0_WP9)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP10                   ((volatile uint32_t *)REG_SPU0_WP10)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP11                   ((volatile uint32_t *)REG_SPU0_WP11)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP12                   ((volatile uint32_t *)REG_SPU0_WP12)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP13                   ((volatile uint32_t *)REG_SPU0_WP13)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP14                   ((volatile uint32_t *)REG_SPU0_WP14)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP15                   ((volatile uint32_t *)REG_SPU0_WP15)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP16                   ((volatile uint32_t *)REG_SPU0_WP16)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP17                   ((volatile uint32_t *)REG_SPU0_WP17)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP18                   ((volatile uint32_t *)REG_SPU0_WP18)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP19                   ((volatile uint32_t *)REG_SPU0_WP19)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP20                   ((volatile uint32_t *)REG_SPU0_WP20)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP21                   ((volatile uint32_t *)REG_SPU0_WP21)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP22                   ((volatile uint32_t *)REG_SPU0_WP22)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP23                   ((volatile uint32_t *)REG_SPU0_WP23)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP24                   ((volatile uint32_t *)REG_SPU0_WP24)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP25                   ((volatile uint32_t *)REG_SPU0_WP25)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP26                   ((volatile uint32_t *)REG_SPU0_WP26)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP27                   ((volatile uint32_t *)REG_SPU0_WP27)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP28                   ((volatile uint32_t *)REG_SPU0_WP28)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP29                   ((volatile uint32_t *)REG_SPU0_WP29)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP30                   ((volatile uint32_t *)REG_SPU0_WP30)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP31                   ((volatile uint32_t *)REG_SPU0_WP31)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP32                   ((volatile uint32_t *)REG_SPU0_WP32)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP33                   ((volatile uint32_t *)REG_SPU0_WP33)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP34                   ((volatile uint32_t *)REG_SPU0_WP34)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP35                   ((volatile uint32_t *)REG_SPU0_WP35)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP36                   ((volatile uint32_t *)REG_SPU0_WP36)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP37                   ((volatile uint32_t *)REG_SPU0_WP37)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP38                   ((volatile uint32_t *)REG_SPU0_WP38)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP39                   ((volatile uint32_t *)REG_SPU0_WP39)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP40                   ((volatile uint32_t *)REG_SPU0_WP40)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP41                   ((volatile uint32_t *)REG_SPU0_WP41)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP42                   ((volatile uint32_t *)REG_SPU0_WP42)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP43                   ((volatile uint32_t *)REG_SPU0_WP43)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP44                   ((volatile uint32_t *)REG_SPU0_WP44)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP45                   ((volatile uint32_t *)REG_SPU0_WP45)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP46                   ((volatile uint32_t *)REG_SPU0_WP46)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP47                   ((volatile uint32_t *)REG_SPU0_WP47)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP48                   ((volatile uint32_t *)REG_SPU0_WP48)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP49                   ((volatile uint32_t *)REG_SPU0_WP49)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP50                   ((volatile uint32_t *)REG_SPU0_WP50)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP51                   ((volatile uint32_t *)REG_SPU0_WP51)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP52                   ((volatile uint32_t *)REG_SPU0_WP52)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP53                   ((volatile uint32_t *)REG_SPU0_WP53)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP54                   ((volatile uint32_t *)REG_SPU0_WP54)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP55                   ((volatile uint32_t *)REG_SPU0_WP55)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP56                   ((volatile uint32_t *)REG_SPU0_WP56)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP57                   ((volatile uint32_t *)REG_SPU0_WP57)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP58                   ((volatile uint32_t *)REG_SPU0_WP58)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP59                   ((volatile uint32_t *)REG_SPU0_WP59)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP60                   ((volatile uint32_t *)REG_SPU0_WP60)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP61                   ((volatile uint32_t *)REG_SPU0_WP61)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP62                   ((volatile uint32_t *)REG_SPU0_WP62)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP63                   ((volatile uint32_t *)REG_SPU0_WP63)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP64                   ((volatile uint32_t *)REG_SPU0_WP64)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP65                   ((volatile uint32_t *)REG_SPU0_WP65)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP66                   ((volatile uint32_t *)REG_SPU0_WP66)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP67                   ((volatile uint32_t *)REG_SPU0_WP67)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP68                   ((volatile uint32_t *)REG_SPU0_WP68)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP69                   ((volatile uint32_t *)REG_SPU0_WP69)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP70                   ((volatile uint32_t *)REG_SPU0_WP70)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP71                   ((volatile uint32_t *)REG_SPU0_WP71)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP72                   ((volatile uint32_t *)REG_SPU0_WP72)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP73                   ((volatile uint32_t *)REG_SPU0_WP73)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP74                   ((volatile uint32_t *)REG_SPU0_WP74)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP75                   ((volatile uint32_t *)REG_SPU0_WP75)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP76                   ((volatile uint32_t *)REG_SPU0_WP76)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP77                   ((volatile uint32_t *)REG_SPU0_WP77)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP78                   ((volatile uint32_t *)REG_SPU0_WP78)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP79                   ((volatile uint32_t *)REG_SPU0_WP79)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP80                   ((volatile uint32_t *)REG_SPU0_WP80)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP81                   ((volatile uint32_t *)REG_SPU0_WP81)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP82                   ((volatile uint32_t *)REG_SPU0_WP82)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP83                   ((volatile uint32_t *)REG_SPU0_WP83)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP84                   ((volatile uint32_t *)REG_SPU0_WP84)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP85                   ((volatile uint32_t *)REG_SPU0_WP85)                    /* SPU0 Write Protect Register n */
-
-
-/* =========================================================================
-       CGU0
-   ========================================================================= */
-#define pREG_CGU0_CTL                    ((volatile uint32_t *)REG_CGU0_CTL)                     /* CGU0 Control Register */
-#define pREG_CGU0_STAT                   ((volatile uint32_t *)REG_CGU0_STAT)                    /* CGU0 Status Register */
-#define pREG_CGU0_DIV                    ((volatile uint32_t *)REG_CGU0_DIV)                     /* CGU0 Divisor Register */
-#define pREG_CGU0_CLKOUTSEL              ((volatile uint32_t *)REG_CGU0_CLKOUTSEL)               /* CGU0 CLKOUT Select Register */
-
-
-/* =========================================================================
-       DPM0
-   ========================================================================= */
-#define pREG_DPM0_CTL                    ((volatile uint32_t *)REG_DPM0_CTL)                     /* DPM0 Control Register */
-#define pREG_DPM0_STAT                   ((volatile uint32_t *)REG_DPM0_STAT)                    /* DPM0 Status Register */
-#define pREG_DPM0_CCBF_DIS               ((volatile uint32_t *)REG_DPM0_CCBF_DIS)                /* DPM0 Core Clock Buffer Disable Register */
-#define pREG_DPM0_CCBF_EN                ((volatile uint32_t *)REG_DPM0_CCBF_EN)                 /* DPM0 Core Clock Buffer Enable Register */
-#define pREG_DPM0_CCBF_STAT              ((volatile uint32_t *)REG_DPM0_CCBF_STAT)               /* DPM0 Core Clock Buffer Status Register */
-#define pREG_DPM0_CCBF_STAT_STKY         ((volatile uint32_t *)REG_DPM0_CCBF_STAT_STKY)          /* DPM0 Core Clock Buffer Status Sticky Register */
-#define pREG_DPM0_SCBF_DIS               ((volatile uint32_t *)REG_DPM0_SCBF_DIS)                /* DPM0 System Clock Buffer Disable Register */
-#define pREG_DPM0_WAKE_EN                ((volatile uint32_t *)REG_DPM0_WAKE_EN)                 /* DPM0 Wakeup Enable Register */
-#define pREG_DPM0_WAKE_POL               ((volatile uint32_t *)REG_DPM0_WAKE_POL)                /* DPM0 Wakeup Polarity Register */
-#define pREG_DPM0_WAKE_STAT              ((volatile uint32_t *)REG_DPM0_WAKE_STAT)               /* DPM0 Wakeup Status Register */
-#define pREG_DPM0_HIB_DIS                ((volatile uint32_t *)REG_DPM0_HIB_DIS)                 /* DPM0 Hibernate Disable Register */
-#define pREG_DPM0_PGCNTR                 ((volatile uint32_t *)REG_DPM0_PGCNTR)                  /* DPM0 Power Good Counter Register */
-#define pREG_DPM0_RESTORE0               ((volatile uint32_t *)REG_DPM0_RESTORE0)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE1               ((volatile uint32_t *)REG_DPM0_RESTORE1)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE2               ((volatile uint32_t *)REG_DPM0_RESTORE2)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE3               ((volatile uint32_t *)REG_DPM0_RESTORE3)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE4               ((volatile uint32_t *)REG_DPM0_RESTORE4)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE5               ((volatile uint32_t *)REG_DPM0_RESTORE5)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE6               ((volatile uint32_t *)REG_DPM0_RESTORE6)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE7               ((volatile uint32_t *)REG_DPM0_RESTORE7)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE8               ((volatile uint32_t *)REG_DPM0_RESTORE8)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE9               ((volatile uint32_t *)REG_DPM0_RESTORE9)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE10              ((volatile uint32_t *)REG_DPM0_RESTORE10)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE11              ((volatile uint32_t *)REG_DPM0_RESTORE11)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE12              ((volatile uint32_t *)REG_DPM0_RESTORE12)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE13              ((volatile uint32_t *)REG_DPM0_RESTORE13)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE14              ((volatile uint32_t *)REG_DPM0_RESTORE14)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE15              ((volatile uint32_t *)REG_DPM0_RESTORE15)               /* DPM0 Restore n Register */
-
-
-/* =========================================================================
-       EFS0
-   ========================================================================= */
-#define pREG_EFS0_CTL                    ((volatile uint32_t *)REG_EFS0_CTL)                     /* EFS0 Control Register */
-#define pREG_EFS0_DAT0                   ((volatile uint32_t *)REG_EFS0_DAT0)                    /* EFS0 Data Register 0 */
-#define pREG_EFS0_DAT1                   ((volatile uint32_t *)REG_EFS0_DAT1)                    /* EFS0 Data Register 1 */
-#define pREG_EFS0_DAT2                   ((volatile uint32_t *)REG_EFS0_DAT2)                    /* EFS0 Data Register 2 */
-#define pREG_EFS0_DAT3                   ((volatile uint32_t *)REG_EFS0_DAT3)                    /* EFS0 Data Register 3 */
-#define pREG_EFS0_DAT4                   ((volatile uint32_t *)REG_EFS0_DAT4)                    /* EFS0 Data Register 4 */
-#define pREG_EFS0_DAT5                   ((volatile uint32_t *)REG_EFS0_DAT5)                    /* EFS0 Data Register 5 */
-#define pREG_EFS0_DAT6                   ((volatile uint32_t *)REG_EFS0_DAT6)                    /* EFS0 Data Register 6 */
-#define pREG_EFS0_DAT7                   ((volatile uint32_t *)REG_EFS0_DAT7)                    /* EFS0 Data Register 7 */
-
-
-/* =========================================================================
-       USB0
-   ========================================================================= */
-#define pREG_USB0_FADDR                  ((volatile  uint8_t *)REG_USB0_FADDR)                   /* USB0 Function Address Register */
-#define pREG_USB0_POWER                  ((volatile  uint8_t *)REG_USB0_POWER)                   /* USB0 Power and Device Control Register */
-#define pREG_USB0_INTRTX                 ((volatile uint16_t *)REG_USB0_INTRTX)                  /* USB0 Transmit Interrupt Register */
-#define pREG_USB0_INTRRX                 ((volatile uint16_t *)REG_USB0_INTRRX)                  /* USB0 Receive Interrupt Register */
-#define pREG_USB0_INTRTXE                ((volatile uint16_t *)REG_USB0_INTRTXE)                 /* USB0 Transmit Interrupt Enable Register */
-#define pREG_USB0_INTRRXE                ((volatile uint16_t *)REG_USB0_INTRRXE)                 /* USB0 Receive Interrupt Enable Register */
-#define pREG_USB0_IRQ                    ((volatile  uint8_t *)REG_USB0_IRQ)                     /* USB0 Common Interrupts Register */
-#define pREG_USB0_IEN                    ((volatile  uint8_t *)REG_USB0_IEN)                     /* USB0 Common Interrupts Enable Register */
-#define pREG_USB0_FRAME                  ((volatile uint16_t *)REG_USB0_FRAME)                   /* USB0 Frame Number Register */
-#define pREG_USB0_INDEX                  ((volatile  uint8_t *)REG_USB0_INDEX)                   /* USB0 Index Register */
-#define pREG_USB0_TESTMODE               ((volatile  uint8_t *)REG_USB0_TESTMODE)                /* USB0 Testmode Register */
-#define pREG_USB0_EPI_TXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_TXMAXP0)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EPI_TXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_P0)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EPI_TXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_H0)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0I_CSR0_P            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_P)             /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CSR0_H            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_H)             /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_RXMAXP0)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EPI_RXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_H0)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_P0)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CNT0              ((volatile uint16_t *)REG_USB0_EP0I_CNT0)               /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EPI_RXCNT0             ((volatile uint16_t *)REG_USB0_EPI_RXCNT0)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EPI_TXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_TXTYPE0)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0I_TYPE0             ((volatile  uint8_t *)REG_USB0_EP0I_TYPE0)              /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EPI_TXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_TXINTERVAL0)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0I_NAKLIMIT0         ((volatile  uint8_t *)REG_USB0_EP0I_NAKLIMIT0)          /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EPI_RXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_RXTYPE0)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EPI_RXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_RXINTERVAL0)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0I_CFGDATA0          ((volatile  uint8_t *)REG_USB0_EP0I_CFGDATA0)           /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_FIFOB0                 ((volatile  uint8_t *)REG_USB0_FIFOB0)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB1                 ((volatile  uint8_t *)REG_USB0_FIFOB1)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB2                 ((volatile  uint8_t *)REG_USB0_FIFOB2)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB3                 ((volatile  uint8_t *)REG_USB0_FIFOB3)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB4                 ((volatile  uint8_t *)REG_USB0_FIFOB4)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB5                 ((volatile  uint8_t *)REG_USB0_FIFOB5)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB6                 ((volatile  uint8_t *)REG_USB0_FIFOB6)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB7                 ((volatile  uint8_t *)REG_USB0_FIFOB7)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB8                 ((volatile  uint8_t *)REG_USB0_FIFOB8)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB9                 ((volatile  uint8_t *)REG_USB0_FIFOB9)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB10                ((volatile  uint8_t *)REG_USB0_FIFOB10)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB11                ((volatile  uint8_t *)REG_USB0_FIFOB11)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOH0                 ((volatile uint16_t *)REG_USB0_FIFOH0)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH1                 ((volatile uint16_t *)REG_USB0_FIFOH1)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH2                 ((volatile uint16_t *)REG_USB0_FIFOH2)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH3                 ((volatile uint16_t *)REG_USB0_FIFOH3)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH4                 ((volatile uint16_t *)REG_USB0_FIFOH4)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH5                 ((volatile uint16_t *)REG_USB0_FIFOH5)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH6                 ((volatile uint16_t *)REG_USB0_FIFOH6)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH7                 ((volatile uint16_t *)REG_USB0_FIFOH7)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH8                 ((volatile uint16_t *)REG_USB0_FIFOH8)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH9                 ((volatile uint16_t *)REG_USB0_FIFOH9)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH10                ((volatile uint16_t *)REG_USB0_FIFOH10)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH11                ((volatile uint16_t *)REG_USB0_FIFOH11)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFO0                  ((volatile uint32_t *)REG_USB0_FIFO0)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO1                  ((volatile uint32_t *)REG_USB0_FIFO1)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO2                  ((volatile uint32_t *)REG_USB0_FIFO2)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO3                  ((volatile uint32_t *)REG_USB0_FIFO3)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO4                  ((volatile uint32_t *)REG_USB0_FIFO4)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO5                  ((volatile uint32_t *)REG_USB0_FIFO5)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO6                  ((volatile uint32_t *)REG_USB0_FIFO6)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO7                  ((volatile uint32_t *)REG_USB0_FIFO7)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO8                  ((volatile uint32_t *)REG_USB0_FIFO8)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO9                  ((volatile uint32_t *)REG_USB0_FIFO9)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO10                 ((volatile uint32_t *)REG_USB0_FIFO10)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO11                 ((volatile uint32_t *)REG_USB0_FIFO11)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_DEV_CTL                ((volatile  uint8_t *)REG_USB0_DEV_CTL)                 /* USB0 Device Control Register */
-#define pREG_USB0_TXFIFOSZ               ((volatile  uint8_t *)REG_USB0_TXFIFOSZ)                /* USB0 Transmit FIFO Size Register */
-#define pREG_USB0_RXFIFOSZ               ((volatile  uint8_t *)REG_USB0_RXFIFOSZ)                /* USB0 Receive FIFO Size Register */
-#define pREG_USB0_TXFIFOADDR             ((volatile uint16_t *)REG_USB0_TXFIFOADDR)              /* USB0 Transmit FIFO Address Register */
-#define pREG_USB0_RXFIFOADDR             ((volatile uint16_t *)REG_USB0_RXFIFOADDR)              /* USB0 Receive FIFO Address Register */
-#define pREG_USB0_EPINFO                 ((volatile  uint8_t *)REG_USB0_EPINFO)                  /* USB0 Endpoint Information Register */
-#define pREG_USB0_RAMINFO                ((volatile  uint8_t *)REG_USB0_RAMINFO)                 /* USB0 RAM Information Register */
-#define pREG_USB0_LINKINFO               ((volatile  uint8_t *)REG_USB0_LINKINFO)                /* USB0 Link Information Register */
-#define pREG_USB0_VPLEN                  ((volatile  uint8_t *)REG_USB0_VPLEN)                   /* USB0 VBUS Pulse Length Register */
-#define pREG_USB0_HS_EOF1                ((volatile  uint8_t *)REG_USB0_HS_EOF1)                 /* USB0 High-Speed EOF 1 Register */
-#define pREG_USB0_FS_EOF1                ((volatile  uint8_t *)REG_USB0_FS_EOF1)                 /* USB0 Full-Speed EOF 1 Register */
-#define pREG_USB0_LS_EOF1                ((volatile  uint8_t *)REG_USB0_LS_EOF1)                 /* USB0 Low-Speed EOF 1 Register */
-#define pREG_USB0_SOFT_RST               ((volatile  uint8_t *)REG_USB0_SOFT_RST)                /* USB0 Software Reset Register */
-#define pREG_USB0_MP0_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP1_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP2_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP3_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP4_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP5_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP6_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP7_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP8_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP9_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP10_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP11_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP0_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP1_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP2_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP3_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP4_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP5_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP6_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP7_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP8_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP9_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP10_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP11_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP0_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP1_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP2_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP3_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP4_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP5_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP6_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP7_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP8_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP9_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP10_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP11_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP0_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP1_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP2_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP3_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP4_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP5_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP6_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP7_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP8_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP9_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP10_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP11_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP0_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP1_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP2_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP3_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP4_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP5_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP6_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP7_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP8_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP9_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP10_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP11_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP0_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP1_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP2_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP3_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP4_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP5_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP6_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP7_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP8_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP9_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP10_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP11_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_EP0_TXMAXP             ((volatile uint16_t *)REG_USB0_EP0_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP1_TXMAXP             ((volatile uint16_t *)REG_USB0_EP1_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP2_TXMAXP             ((volatile uint16_t *)REG_USB0_EP2_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP3_TXMAXP             ((volatile uint16_t *)REG_USB0_EP3_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP4_TXMAXP             ((volatile uint16_t *)REG_USB0_EP4_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP5_TXMAXP             ((volatile uint16_t *)REG_USB0_EP5_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP6_TXMAXP             ((volatile uint16_t *)REG_USB0_EP6_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP7_TXMAXP             ((volatile uint16_t *)REG_USB0_EP7_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP8_TXMAXP             ((volatile uint16_t *)REG_USB0_EP8_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP9_TXMAXP             ((volatile uint16_t *)REG_USB0_EP9_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP10_TXMAXP            ((volatile uint16_t *)REG_USB0_EP10_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP11_TXMAXP            ((volatile uint16_t *)REG_USB0_EP11_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP0_CSR0_H             ((volatile uint16_t *)REG_USB0_EP0_CSR0_H)              /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_CSR0_P             ((volatile uint16_t *)REG_USB0_EP0_CSR0_P)              /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_RXMAXP             ((volatile uint16_t *)REG_USB0_EP0_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP1_RXMAXP             ((volatile uint16_t *)REG_USB0_EP1_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP2_RXMAXP             ((volatile uint16_t *)REG_USB0_EP2_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP3_RXMAXP             ((volatile uint16_t *)REG_USB0_EP3_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP4_RXMAXP             ((volatile uint16_t *)REG_USB0_EP4_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP5_RXMAXP             ((volatile uint16_t *)REG_USB0_EP5_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP6_RXMAXP             ((volatile uint16_t *)REG_USB0_EP6_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP7_RXMAXP             ((volatile uint16_t *)REG_USB0_EP7_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP8_RXMAXP             ((volatile uint16_t *)REG_USB0_EP8_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP9_RXMAXP             ((volatile uint16_t *)REG_USB0_EP9_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP10_RXMAXP            ((volatile uint16_t *)REG_USB0_EP10_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP11_RXMAXP            ((volatile uint16_t *)REG_USB0_EP11_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP0_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_CNT0               ((volatile uint16_t *)REG_USB0_EP0_CNT0)                /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EP0_RXCNT              ((volatile uint16_t *)REG_USB0_EP0_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP1_RXCNT              ((volatile uint16_t *)REG_USB0_EP1_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP2_RXCNT              ((volatile uint16_t *)REG_USB0_EP2_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP3_RXCNT              ((volatile uint16_t *)REG_USB0_EP3_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP4_RXCNT              ((volatile uint16_t *)REG_USB0_EP4_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP5_RXCNT              ((volatile uint16_t *)REG_USB0_EP5_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP6_RXCNT              ((volatile uint16_t *)REG_USB0_EP6_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP7_RXCNT              ((volatile uint16_t *)REG_USB0_EP7_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP8_RXCNT              ((volatile uint16_t *)REG_USB0_EP8_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP9_RXCNT              ((volatile uint16_t *)REG_USB0_EP9_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP10_RXCNT             ((volatile uint16_t *)REG_USB0_EP10_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP11_RXCNT             ((volatile uint16_t *)REG_USB0_EP11_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP0_TYPE0              ((volatile  uint8_t *)REG_USB0_EP0_TYPE0)               /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EP0_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP1_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP2_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP3_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP4_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP5_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP6_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP7_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP8_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP9_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP10_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP11_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0_NAKLIMIT0          ((volatile  uint8_t *)REG_USB0_EP0_NAKLIMIT0)           /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EP0_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP1_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP2_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP3_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP4_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP5_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP6_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP7_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP8_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP9_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP10_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP11_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP1_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP2_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP3_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP4_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP5_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP6_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP7_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP8_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP9_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP10_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP11_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP0_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP1_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP2_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP3_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP4_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP5_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP6_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP7_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP8_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP9_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP10_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP11_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0_CFGDATA0           ((volatile  uint8_t *)REG_USB0_EP0_CFGDATA0)            /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_DMA_IRQ                ((volatile  uint8_t *)REG_USB0_DMA_IRQ)                 /* USB0 DMA Interrupt Register */
-#define pREG_USB0_DMA0_CTL               ((volatile uint16_t *)REG_USB0_DMA0_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA1_CTL               ((volatile uint16_t *)REG_USB0_DMA1_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA2_CTL               ((volatile uint16_t *)REG_USB0_DMA2_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA3_CTL               ((volatile uint16_t *)REG_USB0_DMA3_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA4_CTL               ((volatile uint16_t *)REG_USB0_DMA4_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA5_CTL               ((volatile uint16_t *)REG_USB0_DMA5_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA6_CTL               ((volatile uint16_t *)REG_USB0_DMA6_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA7_CTL               ((volatile uint16_t *)REG_USB0_DMA7_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA0_ADDR              ((void * volatile *)REG_USB0_DMA0_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA1_ADDR              ((void * volatile *)REG_USB0_DMA1_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA2_ADDR              ((void * volatile *)REG_USB0_DMA2_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA3_ADDR              ((void * volatile *)REG_USB0_DMA3_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA4_ADDR              ((void * volatile *)REG_USB0_DMA4_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA5_ADDR              ((void * volatile *)REG_USB0_DMA5_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA6_ADDR              ((void * volatile *)REG_USB0_DMA6_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA7_ADDR              ((void * volatile *)REG_USB0_DMA7_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA0_CNT               ((volatile uint32_t *)REG_USB0_DMA0_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA1_CNT               ((volatile uint32_t *)REG_USB0_DMA1_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA2_CNT               ((volatile uint32_t *)REG_USB0_DMA2_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA3_CNT               ((volatile uint32_t *)REG_USB0_DMA3_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA4_CNT               ((volatile uint32_t *)REG_USB0_DMA4_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA5_CNT               ((volatile uint32_t *)REG_USB0_DMA5_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA6_CNT               ((volatile uint32_t *)REG_USB0_DMA6_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA7_CNT               ((volatile uint32_t *)REG_USB0_DMA7_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_RQPKTCNT0              ((volatile uint16_t *)REG_USB0_RQPKTCNT0)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT1              ((volatile uint16_t *)REG_USB0_RQPKTCNT1)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT2              ((volatile uint16_t *)REG_USB0_RQPKTCNT2)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT3              ((volatile uint16_t *)REG_USB0_RQPKTCNT3)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT4              ((volatile uint16_t *)REG_USB0_RQPKTCNT4)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT5              ((volatile uint16_t *)REG_USB0_RQPKTCNT5)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT6              ((volatile uint16_t *)REG_USB0_RQPKTCNT6)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT7              ((volatile uint16_t *)REG_USB0_RQPKTCNT7)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT8              ((volatile uint16_t *)REG_USB0_RQPKTCNT8)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT9              ((volatile uint16_t *)REG_USB0_RQPKTCNT9)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT10             ((volatile uint16_t *)REG_USB0_RQPKTCNT10)              /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_CT_UCH                 ((volatile uint16_t *)REG_USB0_CT_UCH)                  /* USB0 Chirp Timeout Register */
-#define pREG_USB0_CT_HHSRTN              ((volatile uint16_t *)REG_USB0_CT_HHSRTN)               /* USB0 Host High Speed Return to Normal Register */
-#define pREG_USB0_CT_HSBT                ((volatile uint16_t *)REG_USB0_CT_HSBT)                 /* USB0 High Speed Timeout Register */
-#define pREG_USB0_LPM_ATTR               ((volatile uint16_t *)REG_USB0_LPM_ATTR)                /* USB0 LPM Attribute Register */
-#define pREG_USB0_LPM_CTL                ((volatile  uint8_t *)REG_USB0_LPM_CTL)                 /* USB0 LPM Control Register */
-#define pREG_USB0_LPM_IEN                ((volatile  uint8_t *)REG_USB0_LPM_IEN)                 /* USB0 LPM Interrupt Enable Register */
-#define pREG_USB0_LPM_IRQ                ((volatile  uint8_t *)REG_USB0_LPM_IRQ)                 /* USB0 LPM Interrupt Status Register */
-#define pREG_USB0_LPM_FADDR              ((volatile  uint8_t *)REG_USB0_LPM_FADDR)               /* USB0 LPM Function Address Register */
-#define pREG_USB0_VBUS_CTL               ((volatile  uint8_t *)REG_USB0_VBUS_CTL)                /* USB0 VBUS Control Register */
-#define pREG_USB0_BAT_CHG                ((volatile  uint8_t *)REG_USB0_BAT_CHG)                 /* USB0 Battery Charging Control Register */
-#define pREG_USB0_PHY_CTL                ((volatile  uint8_t *)REG_USB0_PHY_CTL)                 /* USB0 PHY Control Register */
-#define pREG_USB0_PLL_OSC                ((volatile uint16_t *)REG_USB0_PLL_OSC)                 /* USB0 PLL and Oscillator Control Register */
-
-
-/* =========================================================================
-       L1DM0
-   ========================================================================= */
-#define pSRAM_BASE_ADDRESS               ((void * volatile *)SRAM_BASE_ADDRESS)                  /* SRAM Base Address */
-#define pDMEM_CONTROL                    ((volatile uint32_t *)DMEM_CONTROL)                     /* Data memory control */
-#define pDCPLB_STATUS                    ((volatile uint32_t *)DCPLB_STATUS)                     /* Data Cacheability Protection Lookaside Buffer Status */
-#define pDCPLB_FAULT_ADDR                ((void * volatile *)DCPLB_FAULT_ADDR)                   /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define pDCPLB_ADDR0                     ((void * volatile *)DCPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR1                     ((void * volatile *)DCPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR2                     ((void * volatile *)DCPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR3                     ((void * volatile *)DCPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR4                     ((void * volatile *)DCPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR5                     ((void * volatile *)DCPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR6                     ((void * volatile *)DCPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR7                     ((void * volatile *)DCPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR8                     ((void * volatile *)DCPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR9                     ((void * volatile *)DCPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR10                    ((void * volatile *)DCPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR11                    ((void * volatile *)DCPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR12                    ((void * volatile *)DCPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR13                    ((void * volatile *)DCPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR14                    ((void * volatile *)DCPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR15                    ((void * volatile *)DCPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_DATA0                     ((volatile uint32_t *)DCPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA1                     ((volatile uint32_t *)DCPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA2                     ((volatile uint32_t *)DCPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA3                     ((volatile uint32_t *)DCPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA4                     ((volatile uint32_t *)DCPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA5                     ((volatile uint32_t *)DCPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA6                     ((volatile uint32_t *)DCPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA7                     ((volatile uint32_t *)DCPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA8                     ((volatile uint32_t *)DCPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA9                     ((volatile uint32_t *)DCPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA10                    ((volatile uint32_t *)DCPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA11                    ((volatile uint32_t *)DCPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA12                    ((volatile uint32_t *)DCPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA13                    ((volatile uint32_t *)DCPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA14                    ((volatile uint32_t *)DCPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA15                    ((volatile uint32_t *)DCPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDTEST_COMMAND                   ((volatile uint32_t *)DTEST_COMMAND)                    /* Data Test Command Register */
-#define pDTEST_DATA0                     ((volatile uint32_t *)DTEST_DATA0)                      /* Data Test Data Register */
-#define pDTEST_DATA1                     ((volatile uint32_t *)DTEST_DATA1)                      /* Data Test Data Register */
-#define pL1DBNKA_PELOC                   ((volatile uint32_t *)L1DBNKA_PELOC)                    /* Data Bank A Parity Error Location */
-#define pL1DBNKB_PELOC                   ((volatile uint32_t *)L1DBNKB_PELOC)                    /* Data Bank B Parity Error Location */
-
-
-/* =========================================================================
-       L1IM0
-   ========================================================================= */
-#define pIMEM_CONTROL                    ((volatile uint32_t *)IMEM_CONTROL)                     /* Instruction memory control */
-#define pICPLB_STATUS                    ((volatile uint32_t *)ICPLB_STATUS)                     /* Cacheability Protection Lookaside Buffer Status */
-#define pICPLB_FAULT_ADDR                ((void * volatile *)ICPLB_FAULT_ADDR)                   /* Cacheability Protection Lookaside Buffer Fault Address */
-#define pICPLB_ADDR0                     ((void * volatile *)ICPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR1                     ((void * volatile *)ICPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR2                     ((void * volatile *)ICPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR3                     ((void * volatile *)ICPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR4                     ((void * volatile *)ICPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR5                     ((void * volatile *)ICPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR6                     ((void * volatile *)ICPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR7                     ((void * volatile *)ICPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR8                     ((void * volatile *)ICPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR9                     ((void * volatile *)ICPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR10                    ((void * volatile *)ICPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR11                    ((void * volatile *)ICPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR12                    ((void * volatile *)ICPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR13                    ((void * volatile *)ICPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR14                    ((void * volatile *)ICPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR15                    ((void * volatile *)ICPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_DATA0                     ((volatile uint32_t *)ICPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA1                     ((volatile uint32_t *)ICPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA2                     ((volatile uint32_t *)ICPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA3                     ((volatile uint32_t *)ICPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA4                     ((volatile uint32_t *)ICPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA5                     ((volatile uint32_t *)ICPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA6                     ((volatile uint32_t *)ICPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA7                     ((volatile uint32_t *)ICPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA8                     ((volatile uint32_t *)ICPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA9                     ((volatile uint32_t *)ICPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA10                    ((volatile uint32_t *)ICPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA11                    ((volatile uint32_t *)ICPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA12                    ((volatile uint32_t *)ICPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA13                    ((volatile uint32_t *)ICPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA14                    ((volatile uint32_t *)ICPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA15                    ((volatile uint32_t *)ICPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pITEST_COMMAND                   ((volatile uint32_t *)ITEST_COMMAND)                    /* Instruction Test Command Register */
-#define pITEST_DATA0                     ((volatile uint32_t *)ITEST_DATA0)                      /* Instruction Test Data Register */
-#define pITEST_DATA1                     ((volatile uint32_t *)ITEST_DATA1)                      /* Instruction Test Data Register */
-#define pL1IBNKA_PELOC                   ((volatile uint32_t *)L1IBNKA_PELOC)                    /* Instruction Bank A Parity Error Location */
-#define pL1IBNKB_PELOC                   ((volatile uint32_t *)L1IBNKB_PELOC)                    /* Instruction Bank B Parity Error Location */
-#define pL1IBNKC_PELOC                   ((volatile uint32_t *)L1IBNKC_PELOC)                    /* Instruction Bank C Parity Error Location */
-
-
-/* =========================================================================
-       ICU0
-   ========================================================================= */
-#define pEVT0                            ((void * volatile *)EVT0)                               /* Event Vector */
-#define pEVT1                            ((void * volatile *)EVT1)                               /* Event Vector */
-#define pEVT2                            ((void * volatile *)EVT2)                               /* Event Vector */
-#define pEVT3                            ((void * volatile *)EVT3)                               /* Event Vector */
-#define pEVT4                            ((void * volatile *)EVT4)                               /* Event Vector */
-#define pEVT5                            ((void * volatile *)EVT5)                               /* Event Vector */
-#define pEVT6                            ((void * volatile *)EVT6)                               /* Event Vector */
-#define pEVT7                            ((void * volatile *)EVT7)                               /* Event Vector */
-#define pEVT8                            ((void * volatile *)EVT8)                               /* Event Vector */
-#define pEVT9                            ((void * volatile *)EVT9)                               /* Event Vector */
-#define pEVT10                           ((void * volatile *)EVT10)                              /* Event Vector */
-#define pEVT11                           ((void * volatile *)EVT11)                              /* Event Vector */
-#define pEVT12                           ((void * volatile *)EVT12)                              /* Event Vector */
-#define pEVT13                           ((void * volatile *)EVT13)                              /* Event Vector */
-#define pEVT14                           ((void * volatile *)EVT14)                              /* Event Vector */
-#define pEVT15                           ((void * volatile *)EVT15)                              /* Event Vector */
-#define pIMASK                           ((volatile uint32_t *)IMASK)                            /* Interrupt Mask Register */
-#define pIPEND                           ((volatile uint32_t *)IPEND)                            /* Interrupts Pending Register */
-#define pILAT                            ((volatile uint32_t *)ILAT)                             /* Interrupt Latch Register */
-#define pIPRIO                           ((volatile uint32_t *)IPRIO)                            /* Interrupt Priority Register */
-#define pCEC_SID                         ((volatile uint32_t *)CEC_SID)                          /* Core System Interrupt ID */
-
-
-/* =========================================================================
-       TMR0
-   ========================================================================= */
-#define pTCNTL                           ((volatile uint32_t *)TCNTL)                            /* Timer Control Register */
-#define pTPERIOD                         ((volatile uint32_t *)TPERIOD)                          /* Timer Period Register */
-#define pTSCALE                          ((volatile uint32_t *)TSCALE)                           /* Timer Scale Register */
-#define pTCOUNT                          ((volatile uint32_t *)TCOUNT)                           /* Timer Count Register */
-
-
-/* =========================================================================
-       DBG0
-   ========================================================================= */
-#define pDSPID                           ((volatile uint32_t *)DSPID)                            /* DSP Identification Register */
-
-
-/* =========================================================================
-       TB0
-   ========================================================================= */
-#define pTBUFCTL                         ((volatile uint32_t *)TBUFCTL)                          /* Trace Buffer Control Register */
-#define pTBUFSTAT                        ((volatile uint32_t *)TBUFSTAT)                         /* Trace Buffer Status Register */
-#define pTBUF                            ((void * volatile *)TBUF)                               /* Trace Buffer */
-
-
-/* =========================================================================
-       WP0
-   ========================================================================= */
-#define pWPIACTL                         ((volatile uint32_t *)WPIACTL)                          /* Watchpoint Instruction Address Control Register 01 */
-#define pWPIA0                           ((void * volatile *)WPIA0)                              /* Watchpoint Instruction Address Register */
-#define pWPIA1                           ((void * volatile *)WPIA1)                              /* Watchpoint Instruction Address Register */
-#define pWPIA2                           ((void * volatile *)WPIA2)                              /* Watchpoint Instruction Address Register */
-#define pWPIA3                           ((void * volatile *)WPIA3)                              /* Watchpoint Instruction Address Register */
-#define pWPIA4                           ((void * volatile *)WPIA4)                              /* Watchpoint Instruction Address Register */
-#define pWPIA5                           ((void * volatile *)WPIA5)                              /* Watchpoint Instruction Address Register */
-#define pWPIACNT0                        ((volatile uint32_t *)WPIACNT0)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT1                        ((volatile uint32_t *)WPIACNT1)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT2                        ((volatile uint32_t *)WPIACNT2)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT3                        ((volatile uint32_t *)WPIACNT3)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT4                        ((volatile uint32_t *)WPIACNT4)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT5                        ((volatile uint32_t *)WPIACNT5)                         /* Watchpoint Instruction Address Count Register */
-#define pWPDACTL                         ((volatile uint32_t *)WPDACTL)                          /* Watchpoint Data Address Control Register */
-#define pWPDA0                           ((void * volatile *)WPDA0)                              /* Watchpoint Data Address Register */
-#define pWPDA1                           ((void * volatile *)WPDA1)                              /* Watchpoint Data Address Register */
-#define pWPDACNT0                        ((volatile uint32_t *)WPDACNT0)                         /* Watchpoint Data Address Count Value Register */
-#define pWPDACNT1                        ((volatile uint32_t *)WPDACNT1)                         /* Watchpoint Data Address Count Value Register */
-#define pWPSTAT                          ((volatile uint32_t *)WPSTAT)                           /* Watchpoint Status Register */
-
-
-/* =========================================================================
-       PF0
-   ========================================================================= */
-#define pPFCTL                           ((volatile uint32_t *)PFCTL)                            /* Performance Monitor Control Register */
-#define pPFCNTR0                         ((volatile uint32_t *)PFCNTR0)                          /* Performance Monitor Counter 0 */
-#define pPFCNTR1                         ((volatile uint32_t *)PFCNTR1)                          /* Performance Monitor Counter 1 */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif	/* end ifndef _CDEF_BF608_H */
diff --git a/libgloss/bfin/include/cdefBF609.h b/libgloss/bfin/include/cdefBF609.h
deleted file mode 100644
index 1a3a3e704..000000000
--- a/libgloss/bfin/include/cdefBF609.h
+++ /dev/null
@@ -1,4419 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* =========================================================================
-
-     Project      :   ADSP-BF609
-     File         :   cdefBF609.h
-     Description  :   C register and bitfield definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ========================================================================= */
-#ifndef _CDEF_BF609_H
-#define _CDEF_BF609_H
-
-#include <stdint.h>
-#include <defBF609.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_7:"ADI header will re-use identifiers")
-#pragma diag(suppress:misra_rule_6_3:"ADI header allows use of basic types")
-#endif /* _MISRA_RULES */
-
-
-
-
-/* =========================================================================
-       CNT0
-   ========================================================================= */
-#define pREG_CNT0_CFG                    ((volatile uint16_t *)REG_CNT0_CFG)                     /* CNT0 Configuration Register */
-#define pREG_CNT0_IMSK                   ((volatile uint16_t *)REG_CNT0_IMSK)                    /* CNT0 Interrupt Mask Register */
-#define pREG_CNT0_STAT                   ((volatile uint16_t *)REG_CNT0_STAT)                    /* CNT0 Status Register */
-#define pREG_CNT0_CMD                    ((volatile uint16_t *)REG_CNT0_CMD)                     /* CNT0 Command Register */
-#define pREG_CNT0_DEBNCE                 ((volatile uint16_t *)REG_CNT0_DEBNCE)                  /* CNT0 Debounce Register */
-#define pREG_CNT0_CNTR                   ((volatile uint32_t *)REG_CNT0_CNTR)                    /* CNT0 Counter Register */
-#define pREG_CNT0_MAX                    ((volatile uint32_t *)REG_CNT0_MAX)                     /* CNT0 Maximum Count Register */
-#define pREG_CNT0_MIN                    ((volatile uint32_t *)REG_CNT0_MIN)                     /* CNT0 Minimum Count Register */
-
-
-/* =========================================================================
-       RSI0
-   ========================================================================= */
-#define pREG_RSI0_CTL                    ((volatile uint16_t *)REG_RSI0_CTL)                     /* RSI0 Control Register */
-#define pREG_RSI0_ARG                    ((volatile uint32_t *)REG_RSI0_ARG)                     /* RSI0 Argument Register */
-#define pREG_RSI0_CMD                    ((volatile uint16_t *)REG_RSI0_CMD)                     /* RSI0 Command Register */
-#define pREG_RSI0_RESP_CMD               ((volatile uint16_t *)REG_RSI0_RESP_CMD)                /* RSI0 Response Command Register */
-#define pREG_RSI0_RESP0                  ((volatile uint32_t *)REG_RSI0_RESP0)                   /* RSI0 Response 0 Register */
-#define pREG_RSI0_RESP1                  ((volatile uint32_t *)REG_RSI0_RESP1)                   /* RSI0 Response 1 Register */
-#define pREG_RSI0_RESP2                  ((volatile uint32_t *)REG_RSI0_RESP2)                   /* RSI0 Response 2 Register */
-#define pREG_RSI0_RESP3                  ((volatile uint32_t *)REG_RSI0_RESP3)                   /* RSI0 Response 3 Register */
-#define pREG_RSI0_DATA_TMR               ((volatile uint32_t *)REG_RSI0_DATA_TMR)                /* RSI0 Data Timer Register */
-#define pREG_RSI0_DATA_LEN               ((volatile uint16_t *)REG_RSI0_DATA_LEN)                /* RSI0 Data Length Register */
-#define pREG_RSI0_DATA_CTL               ((volatile uint16_t *)REG_RSI0_DATA_CTL)                /* RSI0 Data Control Register */
-#define pREG_RSI0_DATA_CNT               ((volatile uint16_t *)REG_RSI0_DATA_CNT)                /* RSI0 Data Count Register */
-#define pREG_RSI0_XFRSTAT                ((volatile uint32_t *)REG_RSI0_XFRSTAT)                 /* RSI0 Status Register */
-#define pREG_RSI0_XFRSTAT_CLR            ((volatile uint16_t *)REG_RSI0_XFRSTAT_CLR)             /* RSI0 Status Clear Register */
-#define pREG_RSI0_XFR_IMSK0              ((volatile uint32_t *)REG_RSI0_XFR_IMSK0)               /* RSI0 Interrupt 0 Mask Register */
-#define pREG_RSI0_XFR_IMSK1              ((volatile uint32_t *)REG_RSI0_XFR_IMSK1)               /* RSI0 Interrupt 1 Mask Register */
-#define pREG_RSI0_FIFO_CNT               ((volatile uint16_t *)REG_RSI0_FIFO_CNT)                /* RSI0 FIFO Counter Register */
-#define pREG_RSI0_CEATA                  ((volatile uint32_t *)REG_RSI0_CEATA)                   /* RSI0 This register contains bit to dis CCS gen */
-#define pREG_RSI0_BOOT_TCNTR             ((volatile uint16_t *)REG_RSI0_BOOT_TCNTR)              /* RSI0 Boot Timing Counter Register */
-#define pREG_RSI0_BACK_TOUT              ((volatile uint32_t *)REG_RSI0_BACK_TOUT)               /* RSI0 Boot Acknowledge Timeout Register */
-#define pREG_RSI0_SLP_WKUP_TOUT          ((volatile uint32_t *)REG_RSI0_SLP_WKUP_TOUT)           /* RSI0 Sleep Wakeup Timeout Register */
-#define pREG_RSI0_BLKSZ                  ((volatile uint16_t *)REG_RSI0_BLKSZ)                   /* RSI0 Block Size Register */
-#define pREG_RSI0_FIFO                   ((volatile uint32_t *)REG_RSI0_FIFO)                    /* RSI0 Data FIFO Register */
-#define pREG_RSI0_STAT0                  ((volatile uint32_t *)REG_RSI0_STAT0)                   /* RSI0 Exception Status Register */
-#define pREG_RSI0_IMSK0                  ((volatile uint32_t *)REG_RSI0_IMSK0)                   /* RSI0 Exception Mask Register */
-#define pREG_RSI0_CFG                    ((volatile uint16_t *)REG_RSI0_CFG)                     /* RSI0 Configuration Register */
-#define pREG_RSI0_RD_WAIT                ((volatile uint16_t *)REG_RSI0_RD_WAIT)                 /* RSI0 Read Wait Enable Register */
-#define pREG_RSI0_PID0                   ((volatile uint32_t *)REG_RSI0_PID0)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID1                   ((volatile uint32_t *)REG_RSI0_PID1)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID2                   ((volatile uint32_t *)REG_RSI0_PID2)                    /* RSI0 Peripheral Identification Register */
-#define pREG_RSI0_PID3                   ((volatile uint32_t *)REG_RSI0_PID3)                    /* RSI0 Peripheral Identification Register */
-
-
-/* =========================================================================
-       CAN0
-   ========================================================================= */
-#define pREG_CAN0_MC1                    ((volatile uint16_t *)REG_CAN0_MC1)                     /* CAN0 Mailbox Configuration 1 Register */
-#define pREG_CAN0_MD1                    ((volatile uint16_t *)REG_CAN0_MD1)                     /* CAN0 Mailbox Direction 1 Register */
-#define pREG_CAN0_TRS1                   ((volatile uint16_t *)REG_CAN0_TRS1)                    /* CAN0 Transmission Request Set 1 Register */
-#define pREG_CAN0_TRR1                   ((volatile uint16_t *)REG_CAN0_TRR1)                    /* CAN0 Transmission Request Reset 1 Register */
-#define pREG_CAN0_TA1                    ((volatile uint16_t *)REG_CAN0_TA1)                     /* CAN0 Transmission Acknowledge 1 Register */
-#define pREG_CAN0_AA1                    ((volatile uint16_t *)REG_CAN0_AA1)                     /* CAN0 Abort Acknowledge 1 Register */
-#define pREG_CAN0_RMP1                   ((volatile uint16_t *)REG_CAN0_RMP1)                    /* CAN0 Receive Message Pending 1 Register */
-#define pREG_CAN0_RML1                   ((volatile uint16_t *)REG_CAN0_RML1)                    /* CAN0 Receive Message Lost 1 Register */
-#define pREG_CAN0_MBTIF1                 ((volatile uint16_t *)REG_CAN0_MBTIF1)                  /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define pREG_CAN0_MBRIF1                 ((volatile uint16_t *)REG_CAN0_MBRIF1)                  /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define pREG_CAN0_MBIM1                  ((volatile uint16_t *)REG_CAN0_MBIM1)                   /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define pREG_CAN0_RFH1                   ((volatile uint16_t *)REG_CAN0_RFH1)                    /* CAN0 Remote Frame Handling 1 Register */
-#define pREG_CAN0_OPSS1                  ((volatile uint16_t *)REG_CAN0_OPSS1)                   /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define pREG_CAN0_MC2                    ((volatile uint16_t *)REG_CAN0_MC2)                     /* CAN0 Mailbox Configuration 2 Register */
-#define pREG_CAN0_MD2                    ((volatile uint16_t *)REG_CAN0_MD2)                     /* CAN0 Mailbox Direction 2 Register */
-#define pREG_CAN0_TRS2                   ((volatile uint16_t *)REG_CAN0_TRS2)                    /* CAN0 Transmission Request Set 2 Register */
-#define pREG_CAN0_TRR2                   ((volatile uint16_t *)REG_CAN0_TRR2)                    /* CAN0 Transmission Request Reset 2 Register */
-#define pREG_CAN0_TA2                    ((volatile uint16_t *)REG_CAN0_TA2)                     /* CAN0 Transmission Acknowledge 2 Register */
-#define pREG_CAN0_AA2                    ((volatile uint16_t *)REG_CAN0_AA2)                     /* CAN0 Abort Acknowledge 2 Register */
-#define pREG_CAN0_RMP2                   ((volatile uint16_t *)REG_CAN0_RMP2)                    /* CAN0 Receive Message Pending 2 Register */
-#define pREG_CAN0_RML2                   ((volatile uint16_t *)REG_CAN0_RML2)                    /* CAN0 Receive Message Lost 2 Register */
-#define pREG_CAN0_MBTIF2                 ((volatile uint16_t *)REG_CAN0_MBTIF2)                  /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define pREG_CAN0_MBRIF2                 ((volatile uint16_t *)REG_CAN0_MBRIF2)                  /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define pREG_CAN0_MBIM2                  ((volatile uint16_t *)REG_CAN0_MBIM2)                   /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define pREG_CAN0_RFH2                   ((volatile uint16_t *)REG_CAN0_RFH2)                    /* CAN0 Remote Frame Handling 2 Register */
-#define pREG_CAN0_OPSS2                  ((volatile uint16_t *)REG_CAN0_OPSS2)                   /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define pREG_CAN0_CLK                    ((volatile uint16_t *)REG_CAN0_CLK)                     /* CAN0 Clock Register */
-#define pREG_CAN0_TIMING                 ((volatile uint16_t *)REG_CAN0_TIMING)                  /* CAN0 Timing Register */
-#define pREG_CAN0_DBG                    ((volatile uint16_t *)REG_CAN0_DBG)                     /* CAN0 Debug Register */
-#define pREG_CAN0_STAT                   ((volatile uint16_t *)REG_CAN0_STAT)                    /* CAN0 Status Register */
-#define pREG_CAN0_CEC                    ((volatile uint16_t *)REG_CAN0_CEC)                     /* CAN0 Error Counter Register */
-#define pREG_CAN0_GIS                    ((volatile uint16_t *)REG_CAN0_GIS)                     /* CAN0 Global CAN Interrupt Status Register */
-#define pREG_CAN0_GIM                    ((volatile uint16_t *)REG_CAN0_GIM)                     /* CAN0 Global CAN Interrupt Mask Register */
-#define pREG_CAN0_GIF                    ((volatile uint16_t *)REG_CAN0_GIF)                     /* CAN0 Global CAN Interrupt Flag Register */
-#define pREG_CAN0_CTL                    ((volatile uint16_t *)REG_CAN0_CTL)                     /* CAN0 CAN Master Control Register */
-#define pREG_CAN0_INT                    ((volatile uint16_t *)REG_CAN0_INT)                     /* CAN0 Interrupt Pending Register */
-#define pREG_CAN0_MBTD                   ((volatile uint16_t *)REG_CAN0_MBTD)                    /* CAN0 Temporary Mailbox Disable Register */
-#define pREG_CAN0_EWR                    ((volatile uint16_t *)REG_CAN0_EWR)                     /* CAN0 Error Counter Warning Level Register */
-#define pREG_CAN0_ESR                    ((volatile uint16_t *)REG_CAN0_ESR)                     /* CAN0 Error Status Register */
-#define pREG_CAN0_UCCNT                  ((volatile uint16_t *)REG_CAN0_UCCNT)                   /* CAN0 Universal Counter Register */
-#define pREG_CAN0_UCRC                   ((volatile uint16_t *)REG_CAN0_UCRC)                    /* CAN0 Universal Counter Reload/Capture Register */
-#define pREG_CAN0_UCCNF                  ((volatile uint16_t *)REG_CAN0_UCCNF)                   /* CAN0 Universal Counter Configuration Mode Register */
-#define pREG_CAN0_AM00L                  ((volatile uint16_t *)REG_CAN0_AM00L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM01L                  ((volatile uint16_t *)REG_CAN0_AM01L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM02L                  ((volatile uint16_t *)REG_CAN0_AM02L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM03L                  ((volatile uint16_t *)REG_CAN0_AM03L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM04L                  ((volatile uint16_t *)REG_CAN0_AM04L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM05L                  ((volatile uint16_t *)REG_CAN0_AM05L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM06L                  ((volatile uint16_t *)REG_CAN0_AM06L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM07L                  ((volatile uint16_t *)REG_CAN0_AM07L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM08L                  ((volatile uint16_t *)REG_CAN0_AM08L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM09L                  ((volatile uint16_t *)REG_CAN0_AM09L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM10L                  ((volatile uint16_t *)REG_CAN0_AM10L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM11L                  ((volatile uint16_t *)REG_CAN0_AM11L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM12L                  ((volatile uint16_t *)REG_CAN0_AM12L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM13L                  ((volatile uint16_t *)REG_CAN0_AM13L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM14L                  ((volatile uint16_t *)REG_CAN0_AM14L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM15L                  ((volatile uint16_t *)REG_CAN0_AM15L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM16L                  ((volatile uint16_t *)REG_CAN0_AM16L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM17L                  ((volatile uint16_t *)REG_CAN0_AM17L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM18L                  ((volatile uint16_t *)REG_CAN0_AM18L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM19L                  ((volatile uint16_t *)REG_CAN0_AM19L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM20L                  ((volatile uint16_t *)REG_CAN0_AM20L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM21L                  ((volatile uint16_t *)REG_CAN0_AM21L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM22L                  ((volatile uint16_t *)REG_CAN0_AM22L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM23L                  ((volatile uint16_t *)REG_CAN0_AM23L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM24L                  ((volatile uint16_t *)REG_CAN0_AM24L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM25L                  ((volatile uint16_t *)REG_CAN0_AM25L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM26L                  ((volatile uint16_t *)REG_CAN0_AM26L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM27L                  ((volatile uint16_t *)REG_CAN0_AM27L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM28L                  ((volatile uint16_t *)REG_CAN0_AM28L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM29L                  ((volatile uint16_t *)REG_CAN0_AM29L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM30L                  ((volatile uint16_t *)REG_CAN0_AM30L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM31L                  ((volatile uint16_t *)REG_CAN0_AM31L)                   /* CAN0 Acceptance Mask (L) Register */
-#define pREG_CAN0_AM00H                  ((volatile uint16_t *)REG_CAN0_AM00H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM01H                  ((volatile uint16_t *)REG_CAN0_AM01H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM02H                  ((volatile uint16_t *)REG_CAN0_AM02H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM03H                  ((volatile uint16_t *)REG_CAN0_AM03H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM04H                  ((volatile uint16_t *)REG_CAN0_AM04H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM05H                  ((volatile uint16_t *)REG_CAN0_AM05H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM06H                  ((volatile uint16_t *)REG_CAN0_AM06H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM07H                  ((volatile uint16_t *)REG_CAN0_AM07H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM08H                  ((volatile uint16_t *)REG_CAN0_AM08H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM09H                  ((volatile uint16_t *)REG_CAN0_AM09H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM10H                  ((volatile uint16_t *)REG_CAN0_AM10H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM11H                  ((volatile uint16_t *)REG_CAN0_AM11H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM12H                  ((volatile uint16_t *)REG_CAN0_AM12H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM13H                  ((volatile uint16_t *)REG_CAN0_AM13H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM14H                  ((volatile uint16_t *)REG_CAN0_AM14H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM15H                  ((volatile uint16_t *)REG_CAN0_AM15H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM16H                  ((volatile uint16_t *)REG_CAN0_AM16H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM17H                  ((volatile uint16_t *)REG_CAN0_AM17H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM18H                  ((volatile uint16_t *)REG_CAN0_AM18H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM19H                  ((volatile uint16_t *)REG_CAN0_AM19H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM20H                  ((volatile uint16_t *)REG_CAN0_AM20H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM21H                  ((volatile uint16_t *)REG_CAN0_AM21H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM22H                  ((volatile uint16_t *)REG_CAN0_AM22H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM23H                  ((volatile uint16_t *)REG_CAN0_AM23H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM24H                  ((volatile uint16_t *)REG_CAN0_AM24H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM25H                  ((volatile uint16_t *)REG_CAN0_AM25H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM26H                  ((volatile uint16_t *)REG_CAN0_AM26H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM27H                  ((volatile uint16_t *)REG_CAN0_AM27H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM28H                  ((volatile uint16_t *)REG_CAN0_AM28H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM29H                  ((volatile uint16_t *)REG_CAN0_AM29H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM30H                  ((volatile uint16_t *)REG_CAN0_AM30H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_AM31H                  ((volatile uint16_t *)REG_CAN0_AM31H)                   /* CAN0 Acceptance Mask (H) Register */
-#define pREG_CAN0_MB00_DATA0             ((volatile uint16_t *)REG_CAN0_MB00_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB01_DATA0             ((volatile uint16_t *)REG_CAN0_MB01_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB02_DATA0             ((volatile uint16_t *)REG_CAN0_MB02_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB03_DATA0             ((volatile uint16_t *)REG_CAN0_MB03_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB04_DATA0             ((volatile uint16_t *)REG_CAN0_MB04_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB05_DATA0             ((volatile uint16_t *)REG_CAN0_MB05_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB06_DATA0             ((volatile uint16_t *)REG_CAN0_MB06_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB07_DATA0             ((volatile uint16_t *)REG_CAN0_MB07_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB08_DATA0             ((volatile uint16_t *)REG_CAN0_MB08_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB09_DATA0             ((volatile uint16_t *)REG_CAN0_MB09_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB10_DATA0             ((volatile uint16_t *)REG_CAN0_MB10_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB11_DATA0             ((volatile uint16_t *)REG_CAN0_MB11_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB12_DATA0             ((volatile uint16_t *)REG_CAN0_MB12_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB13_DATA0             ((volatile uint16_t *)REG_CAN0_MB13_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB14_DATA0             ((volatile uint16_t *)REG_CAN0_MB14_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB15_DATA0             ((volatile uint16_t *)REG_CAN0_MB15_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB16_DATA0             ((volatile uint16_t *)REG_CAN0_MB16_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB17_DATA0             ((volatile uint16_t *)REG_CAN0_MB17_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB18_DATA0             ((volatile uint16_t *)REG_CAN0_MB18_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB19_DATA0             ((volatile uint16_t *)REG_CAN0_MB19_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB20_DATA0             ((volatile uint16_t *)REG_CAN0_MB20_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB21_DATA0             ((volatile uint16_t *)REG_CAN0_MB21_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB22_DATA0             ((volatile uint16_t *)REG_CAN0_MB22_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB23_DATA0             ((volatile uint16_t *)REG_CAN0_MB23_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB24_DATA0             ((volatile uint16_t *)REG_CAN0_MB24_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB25_DATA0             ((volatile uint16_t *)REG_CAN0_MB25_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB26_DATA0             ((volatile uint16_t *)REG_CAN0_MB26_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB27_DATA0             ((volatile uint16_t *)REG_CAN0_MB27_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB28_DATA0             ((volatile uint16_t *)REG_CAN0_MB28_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB29_DATA0             ((volatile uint16_t *)REG_CAN0_MB29_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB30_DATA0             ((volatile uint16_t *)REG_CAN0_MB30_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB31_DATA0             ((volatile uint16_t *)REG_CAN0_MB31_DATA0)              /* CAN0 Mailbox Word 0 Register */
-#define pREG_CAN0_MB00_DATA1             ((volatile uint16_t *)REG_CAN0_MB00_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB01_DATA1             ((volatile uint16_t *)REG_CAN0_MB01_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB02_DATA1             ((volatile uint16_t *)REG_CAN0_MB02_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB03_DATA1             ((volatile uint16_t *)REG_CAN0_MB03_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB04_DATA1             ((volatile uint16_t *)REG_CAN0_MB04_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB05_DATA1             ((volatile uint16_t *)REG_CAN0_MB05_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB06_DATA1             ((volatile uint16_t *)REG_CAN0_MB06_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB07_DATA1             ((volatile uint16_t *)REG_CAN0_MB07_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB08_DATA1             ((volatile uint16_t *)REG_CAN0_MB08_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB09_DATA1             ((volatile uint16_t *)REG_CAN0_MB09_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB10_DATA1             ((volatile uint16_t *)REG_CAN0_MB10_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB11_DATA1             ((volatile uint16_t *)REG_CAN0_MB11_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB12_DATA1             ((volatile uint16_t *)REG_CAN0_MB12_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB13_DATA1             ((volatile uint16_t *)REG_CAN0_MB13_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB14_DATA1             ((volatile uint16_t *)REG_CAN0_MB14_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB15_DATA1             ((volatile uint16_t *)REG_CAN0_MB15_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB16_DATA1             ((volatile uint16_t *)REG_CAN0_MB16_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB17_DATA1             ((volatile uint16_t *)REG_CAN0_MB17_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB18_DATA1             ((volatile uint16_t *)REG_CAN0_MB18_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB19_DATA1             ((volatile uint16_t *)REG_CAN0_MB19_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB20_DATA1             ((volatile uint16_t *)REG_CAN0_MB20_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB21_DATA1             ((volatile uint16_t *)REG_CAN0_MB21_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB22_DATA1             ((volatile uint16_t *)REG_CAN0_MB22_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB23_DATA1             ((volatile uint16_t *)REG_CAN0_MB23_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB24_DATA1             ((volatile uint16_t *)REG_CAN0_MB24_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB25_DATA1             ((volatile uint16_t *)REG_CAN0_MB25_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB26_DATA1             ((volatile uint16_t *)REG_CAN0_MB26_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB27_DATA1             ((volatile uint16_t *)REG_CAN0_MB27_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB28_DATA1             ((volatile uint16_t *)REG_CAN0_MB28_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB29_DATA1             ((volatile uint16_t *)REG_CAN0_MB29_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB30_DATA1             ((volatile uint16_t *)REG_CAN0_MB30_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB31_DATA1             ((volatile uint16_t *)REG_CAN0_MB31_DATA1)              /* CAN0 Mailbox Word 1 Register */
-#define pREG_CAN0_MB00_DATA2             ((volatile uint16_t *)REG_CAN0_MB00_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB01_DATA2             ((volatile uint16_t *)REG_CAN0_MB01_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB02_DATA2             ((volatile uint16_t *)REG_CAN0_MB02_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB03_DATA2             ((volatile uint16_t *)REG_CAN0_MB03_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB04_DATA2             ((volatile uint16_t *)REG_CAN0_MB04_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB05_DATA2             ((volatile uint16_t *)REG_CAN0_MB05_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB06_DATA2             ((volatile uint16_t *)REG_CAN0_MB06_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB07_DATA2             ((volatile uint16_t *)REG_CAN0_MB07_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB08_DATA2             ((volatile uint16_t *)REG_CAN0_MB08_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB09_DATA2             ((volatile uint16_t *)REG_CAN0_MB09_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB10_DATA2             ((volatile uint16_t *)REG_CAN0_MB10_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB11_DATA2             ((volatile uint16_t *)REG_CAN0_MB11_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB12_DATA2             ((volatile uint16_t *)REG_CAN0_MB12_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB13_DATA2             ((volatile uint16_t *)REG_CAN0_MB13_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB14_DATA2             ((volatile uint16_t *)REG_CAN0_MB14_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB15_DATA2             ((volatile uint16_t *)REG_CAN0_MB15_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB16_DATA2             ((volatile uint16_t *)REG_CAN0_MB16_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB17_DATA2             ((volatile uint16_t *)REG_CAN0_MB17_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB18_DATA2             ((volatile uint16_t *)REG_CAN0_MB18_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB19_DATA2             ((volatile uint16_t *)REG_CAN0_MB19_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB20_DATA2             ((volatile uint16_t *)REG_CAN0_MB20_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB21_DATA2             ((volatile uint16_t *)REG_CAN0_MB21_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB22_DATA2             ((volatile uint16_t *)REG_CAN0_MB22_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB23_DATA2             ((volatile uint16_t *)REG_CAN0_MB23_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB24_DATA2             ((volatile uint16_t *)REG_CAN0_MB24_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB25_DATA2             ((volatile uint16_t *)REG_CAN0_MB25_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB26_DATA2             ((volatile uint16_t *)REG_CAN0_MB26_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB27_DATA2             ((volatile uint16_t *)REG_CAN0_MB27_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB28_DATA2             ((volatile uint16_t *)REG_CAN0_MB28_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB29_DATA2             ((volatile uint16_t *)REG_CAN0_MB29_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB30_DATA2             ((volatile uint16_t *)REG_CAN0_MB30_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB31_DATA2             ((volatile uint16_t *)REG_CAN0_MB31_DATA2)              /* CAN0 Mailbox Word 2 Register */
-#define pREG_CAN0_MB00_DATA3             ((volatile uint16_t *)REG_CAN0_MB00_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB01_DATA3             ((volatile uint16_t *)REG_CAN0_MB01_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB02_DATA3             ((volatile uint16_t *)REG_CAN0_MB02_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB03_DATA3             ((volatile uint16_t *)REG_CAN0_MB03_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB04_DATA3             ((volatile uint16_t *)REG_CAN0_MB04_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB05_DATA3             ((volatile uint16_t *)REG_CAN0_MB05_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB06_DATA3             ((volatile uint16_t *)REG_CAN0_MB06_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB07_DATA3             ((volatile uint16_t *)REG_CAN0_MB07_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB08_DATA3             ((volatile uint16_t *)REG_CAN0_MB08_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB09_DATA3             ((volatile uint16_t *)REG_CAN0_MB09_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB10_DATA3             ((volatile uint16_t *)REG_CAN0_MB10_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB11_DATA3             ((volatile uint16_t *)REG_CAN0_MB11_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB12_DATA3             ((volatile uint16_t *)REG_CAN0_MB12_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB13_DATA3             ((volatile uint16_t *)REG_CAN0_MB13_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB14_DATA3             ((volatile uint16_t *)REG_CAN0_MB14_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB15_DATA3             ((volatile uint16_t *)REG_CAN0_MB15_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB16_DATA3             ((volatile uint16_t *)REG_CAN0_MB16_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB17_DATA3             ((volatile uint16_t *)REG_CAN0_MB17_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB18_DATA3             ((volatile uint16_t *)REG_CAN0_MB18_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB19_DATA3             ((volatile uint16_t *)REG_CAN0_MB19_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB20_DATA3             ((volatile uint16_t *)REG_CAN0_MB20_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB21_DATA3             ((volatile uint16_t *)REG_CAN0_MB21_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB22_DATA3             ((volatile uint16_t *)REG_CAN0_MB22_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB23_DATA3             ((volatile uint16_t *)REG_CAN0_MB23_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB24_DATA3             ((volatile uint16_t *)REG_CAN0_MB24_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB25_DATA3             ((volatile uint16_t *)REG_CAN0_MB25_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB26_DATA3             ((volatile uint16_t *)REG_CAN0_MB26_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB27_DATA3             ((volatile uint16_t *)REG_CAN0_MB27_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB28_DATA3             ((volatile uint16_t *)REG_CAN0_MB28_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB29_DATA3             ((volatile uint16_t *)REG_CAN0_MB29_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB30_DATA3             ((volatile uint16_t *)REG_CAN0_MB30_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB31_DATA3             ((volatile uint16_t *)REG_CAN0_MB31_DATA3)              /* CAN0 Mailbox Word 3 Register */
-#define pREG_CAN0_MB00_LENGTH            ((volatile uint16_t *)REG_CAN0_MB00_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB01_LENGTH            ((volatile uint16_t *)REG_CAN0_MB01_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB02_LENGTH            ((volatile uint16_t *)REG_CAN0_MB02_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB03_LENGTH            ((volatile uint16_t *)REG_CAN0_MB03_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB04_LENGTH            ((volatile uint16_t *)REG_CAN0_MB04_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB05_LENGTH            ((volatile uint16_t *)REG_CAN0_MB05_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB06_LENGTH            ((volatile uint16_t *)REG_CAN0_MB06_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB07_LENGTH            ((volatile uint16_t *)REG_CAN0_MB07_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB08_LENGTH            ((volatile uint16_t *)REG_CAN0_MB08_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB09_LENGTH            ((volatile uint16_t *)REG_CAN0_MB09_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB10_LENGTH            ((volatile uint16_t *)REG_CAN0_MB10_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB11_LENGTH            ((volatile uint16_t *)REG_CAN0_MB11_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB12_LENGTH            ((volatile uint16_t *)REG_CAN0_MB12_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB13_LENGTH            ((volatile uint16_t *)REG_CAN0_MB13_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB14_LENGTH            ((volatile uint16_t *)REG_CAN0_MB14_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB15_LENGTH            ((volatile uint16_t *)REG_CAN0_MB15_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB16_LENGTH            ((volatile uint16_t *)REG_CAN0_MB16_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB17_LENGTH            ((volatile uint16_t *)REG_CAN0_MB17_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB18_LENGTH            ((volatile uint16_t *)REG_CAN0_MB18_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB19_LENGTH            ((volatile uint16_t *)REG_CAN0_MB19_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB20_LENGTH            ((volatile uint16_t *)REG_CAN0_MB20_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB21_LENGTH            ((volatile uint16_t *)REG_CAN0_MB21_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB22_LENGTH            ((volatile uint16_t *)REG_CAN0_MB22_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB23_LENGTH            ((volatile uint16_t *)REG_CAN0_MB23_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB24_LENGTH            ((volatile uint16_t *)REG_CAN0_MB24_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB25_LENGTH            ((volatile uint16_t *)REG_CAN0_MB25_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB26_LENGTH            ((volatile uint16_t *)REG_CAN0_MB26_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB27_LENGTH            ((volatile uint16_t *)REG_CAN0_MB27_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB28_LENGTH            ((volatile uint16_t *)REG_CAN0_MB28_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB29_LENGTH            ((volatile uint16_t *)REG_CAN0_MB29_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB30_LENGTH            ((volatile uint16_t *)REG_CAN0_MB30_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB31_LENGTH            ((volatile uint16_t *)REG_CAN0_MB31_LENGTH)             /* CAN0 Mailbox Length Register */
-#define pREG_CAN0_MB00_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB00_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB01_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB01_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB02_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB02_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB03_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB03_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB04_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB04_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB05_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB05_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB06_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB06_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB07_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB07_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB08_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB08_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB09_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB09_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB10_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB10_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB11_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB11_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB12_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB12_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB13_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB13_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB14_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB14_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB15_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB15_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB16_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB16_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB17_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB17_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB18_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB18_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB19_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB19_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB20_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB20_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB21_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB21_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB22_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB22_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB23_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB23_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB24_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB24_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB25_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB25_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB26_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB26_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB27_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB27_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB28_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB28_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB29_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB29_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB30_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB30_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB31_TIMESTAMP         ((volatile uint16_t *)REG_CAN0_MB31_TIMESTAMP)          /* CAN0 Mailbox Timestamp Register */
-#define pREG_CAN0_MB00_ID0               ((volatile uint16_t *)REG_CAN0_MB00_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB01_ID0               ((volatile uint16_t *)REG_CAN0_MB01_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB02_ID0               ((volatile uint16_t *)REG_CAN0_MB02_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB03_ID0               ((volatile uint16_t *)REG_CAN0_MB03_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB04_ID0               ((volatile uint16_t *)REG_CAN0_MB04_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB05_ID0               ((volatile uint16_t *)REG_CAN0_MB05_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB06_ID0               ((volatile uint16_t *)REG_CAN0_MB06_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB07_ID0               ((volatile uint16_t *)REG_CAN0_MB07_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB08_ID0               ((volatile uint16_t *)REG_CAN0_MB08_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB09_ID0               ((volatile uint16_t *)REG_CAN0_MB09_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB10_ID0               ((volatile uint16_t *)REG_CAN0_MB10_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB11_ID0               ((volatile uint16_t *)REG_CAN0_MB11_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB12_ID0               ((volatile uint16_t *)REG_CAN0_MB12_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB13_ID0               ((volatile uint16_t *)REG_CAN0_MB13_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB14_ID0               ((volatile uint16_t *)REG_CAN0_MB14_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB15_ID0               ((volatile uint16_t *)REG_CAN0_MB15_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB16_ID0               ((volatile uint16_t *)REG_CAN0_MB16_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB17_ID0               ((volatile uint16_t *)REG_CAN0_MB17_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB18_ID0               ((volatile uint16_t *)REG_CAN0_MB18_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB19_ID0               ((volatile uint16_t *)REG_CAN0_MB19_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB20_ID0               ((volatile uint16_t *)REG_CAN0_MB20_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB21_ID0               ((volatile uint16_t *)REG_CAN0_MB21_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB22_ID0               ((volatile uint16_t *)REG_CAN0_MB22_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB23_ID0               ((volatile uint16_t *)REG_CAN0_MB23_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB24_ID0               ((volatile uint16_t *)REG_CAN0_MB24_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB25_ID0               ((volatile uint16_t *)REG_CAN0_MB25_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB26_ID0               ((volatile uint16_t *)REG_CAN0_MB26_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB27_ID0               ((volatile uint16_t *)REG_CAN0_MB27_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB28_ID0               ((volatile uint16_t *)REG_CAN0_MB28_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB29_ID0               ((volatile uint16_t *)REG_CAN0_MB29_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB30_ID0               ((volatile uint16_t *)REG_CAN0_MB30_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB31_ID0               ((volatile uint16_t *)REG_CAN0_MB31_ID0)                /* CAN0 Mailbox ID 0 Register */
-#define pREG_CAN0_MB00_ID1               ((volatile uint16_t *)REG_CAN0_MB00_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB01_ID1               ((volatile uint16_t *)REG_CAN0_MB01_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB02_ID1               ((volatile uint16_t *)REG_CAN0_MB02_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB03_ID1               ((volatile uint16_t *)REG_CAN0_MB03_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB04_ID1               ((volatile uint16_t *)REG_CAN0_MB04_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB05_ID1               ((volatile uint16_t *)REG_CAN0_MB05_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB06_ID1               ((volatile uint16_t *)REG_CAN0_MB06_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB07_ID1               ((volatile uint16_t *)REG_CAN0_MB07_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB08_ID1               ((volatile uint16_t *)REG_CAN0_MB08_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB09_ID1               ((volatile uint16_t *)REG_CAN0_MB09_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB10_ID1               ((volatile uint16_t *)REG_CAN0_MB10_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB11_ID1               ((volatile uint16_t *)REG_CAN0_MB11_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB12_ID1               ((volatile uint16_t *)REG_CAN0_MB12_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB13_ID1               ((volatile uint16_t *)REG_CAN0_MB13_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB14_ID1               ((volatile uint16_t *)REG_CAN0_MB14_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB15_ID1               ((volatile uint16_t *)REG_CAN0_MB15_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB16_ID1               ((volatile uint16_t *)REG_CAN0_MB16_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB17_ID1               ((volatile uint16_t *)REG_CAN0_MB17_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB18_ID1               ((volatile uint16_t *)REG_CAN0_MB18_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB19_ID1               ((volatile uint16_t *)REG_CAN0_MB19_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB20_ID1               ((volatile uint16_t *)REG_CAN0_MB20_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB21_ID1               ((volatile uint16_t *)REG_CAN0_MB21_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB22_ID1               ((volatile uint16_t *)REG_CAN0_MB22_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB23_ID1               ((volatile uint16_t *)REG_CAN0_MB23_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB24_ID1               ((volatile uint16_t *)REG_CAN0_MB24_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB25_ID1               ((volatile uint16_t *)REG_CAN0_MB25_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB26_ID1               ((volatile uint16_t *)REG_CAN0_MB26_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB27_ID1               ((volatile uint16_t *)REG_CAN0_MB27_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB28_ID1               ((volatile uint16_t *)REG_CAN0_MB28_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB29_ID1               ((volatile uint16_t *)REG_CAN0_MB29_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB30_ID1               ((volatile uint16_t *)REG_CAN0_MB30_ID1)                /* CAN0 Mailbox ID 1 Register */
-#define pREG_CAN0_MB31_ID1               ((volatile uint16_t *)REG_CAN0_MB31_ID1)                /* CAN0 Mailbox ID 1 Register */
-
-
-/* =========================================================================
-       LP0
-   ========================================================================= */
-#define pREG_LP0_CTL                     ((volatile uint32_t *)REG_LP0_CTL)                      /* LP0 Control Register */
-#define pREG_LP0_STAT                    ((volatile uint32_t *)REG_LP0_STAT)                     /* LP0 Status Register */
-#define pREG_LP0_DIV                     ((volatile uint32_t *)REG_LP0_DIV)                      /* LP0 Clock Divider Value */
-#define pREG_LP0_TX                      ((volatile uint32_t *)REG_LP0_TX)                       /* LP0 Transmit Buffer */
-#define pREG_LP0_RX                      ((volatile uint32_t *)REG_LP0_RX)                       /* LP0 Receive Buffer */
-#define pREG_LP0_TXIN_SHDW               ((volatile uint32_t *)REG_LP0_TXIN_SHDW)                /* LP0 Shadow Input Transmit Buffer */
-#define pREG_LP0_TXOUT_SHDW              ((volatile uint32_t *)REG_LP0_TXOUT_SHDW)               /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP1
-   ========================================================================= */
-#define pREG_LP1_CTL                     ((volatile uint32_t *)REG_LP1_CTL)                      /* LP1 Control Register */
-#define pREG_LP1_STAT                    ((volatile uint32_t *)REG_LP1_STAT)                     /* LP1 Status Register */
-#define pREG_LP1_DIV                     ((volatile uint32_t *)REG_LP1_DIV)                      /* LP1 Clock Divider Value */
-#define pREG_LP1_TX                      ((volatile uint32_t *)REG_LP1_TX)                       /* LP1 Transmit Buffer */
-#define pREG_LP1_RX                      ((volatile uint32_t *)REG_LP1_RX)                       /* LP1 Receive Buffer */
-#define pREG_LP1_TXIN_SHDW               ((volatile uint32_t *)REG_LP1_TXIN_SHDW)                /* LP1 Shadow Input Transmit Buffer */
-#define pREG_LP1_TXOUT_SHDW              ((volatile uint32_t *)REG_LP1_TXOUT_SHDW)               /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP2
-   ========================================================================= */
-#define pREG_LP2_CTL                     ((volatile uint32_t *)REG_LP2_CTL)                      /* LP2 Control Register */
-#define pREG_LP2_STAT                    ((volatile uint32_t *)REG_LP2_STAT)                     /* LP2 Status Register */
-#define pREG_LP2_DIV                     ((volatile uint32_t *)REG_LP2_DIV)                      /* LP2 Clock Divider Value */
-#define pREG_LP2_TX                      ((volatile uint32_t *)REG_LP2_TX)                       /* LP2 Transmit Buffer */
-#define pREG_LP2_RX                      ((volatile uint32_t *)REG_LP2_RX)                       /* LP2 Receive Buffer */
-#define pREG_LP2_TXIN_SHDW               ((volatile uint32_t *)REG_LP2_TXIN_SHDW)                /* LP2 Shadow Input Transmit Buffer */
-#define pREG_LP2_TXOUT_SHDW              ((volatile uint32_t *)REG_LP2_TXOUT_SHDW)               /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================================================================
-       LP3
-   ========================================================================= */
-#define pREG_LP3_CTL                     ((volatile uint32_t *)REG_LP3_CTL)                      /* LP3 Control Register */
-#define pREG_LP3_STAT                    ((volatile uint32_t *)REG_LP3_STAT)                     /* LP3 Status Register */
-#define pREG_LP3_DIV                     ((volatile uint32_t *)REG_LP3_DIV)                      /* LP3 Clock Divider Value */
-#define pREG_LP3_TX                      ((volatile uint32_t *)REG_LP3_TX)                       /* LP3 Transmit Buffer */
-#define pREG_LP3_RX                      ((volatile uint32_t *)REG_LP3_RX)                       /* LP3 Receive Buffer */
-#define pREG_LP3_TXIN_SHDW               ((volatile uint32_t *)REG_LP3_TXIN_SHDW)                /* LP3 Shadow Input Transmit Buffer */
-#define pREG_LP3_TXOUT_SHDW              ((volatile uint32_t *)REG_LP3_TXOUT_SHDW)               /* LP3 Shadow Output Transmit Buffer */
-
-
-/* =========================================================================
-       TIMER0
-   ========================================================================= */
-#define pREG_TIMER0_REVID                ((volatile uint16_t *)REG_TIMER0_REVID)                 /* TIMER0 Revision ID Register */
-#define pREG_TIMER0_RUN                  ((volatile uint16_t *)REG_TIMER0_RUN)                   /* TIMER0 Run Register */
-#define pREG_TIMER0_RUN_SET              ((volatile uint16_t *)REG_TIMER0_RUN_SET)               /* TIMER0 Run Set Register */
-#define pREG_TIMER0_RUN_CLR              ((volatile uint16_t *)REG_TIMER0_RUN_CLR)               /* TIMER0 Run Clear Register */
-#define pREG_TIMER0_STOP_CFG             ((volatile uint16_t *)REG_TIMER0_STOP_CFG)              /* TIMER0 Stop Configuration Register */
-#define pREG_TIMER0_STOP_CFG_SET         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_SET)          /* TIMER0 Stop Configuration Set Register */
-#define pREG_TIMER0_STOP_CFG_CLR         ((volatile uint16_t *)REG_TIMER0_STOP_CFG_CLR)          /* TIMER0 Stop Configuration Clear Register */
-#define pREG_TIMER0_DATA_IMSK            ((volatile uint16_t *)REG_TIMER0_DATA_IMSK)             /* TIMER0 Data Interrupt Mask Register */
-#define pREG_TIMER0_STAT_IMSK            ((volatile uint16_t *)REG_TIMER0_STAT_IMSK)             /* TIMER0 Status Interrupt Mask Register */
-#define pREG_TIMER0_TRG_MSK              ((volatile uint16_t *)REG_TIMER0_TRG_MSK)               /* TIMER0 Trigger Master Mask Register */
-#define pREG_TIMER0_TRG_IE               ((volatile uint16_t *)REG_TIMER0_TRG_IE)                /* TIMER0 Trigger Slave Enable Register */
-#define pREG_TIMER0_DATA_ILAT            ((volatile uint16_t *)REG_TIMER0_DATA_ILAT)             /* TIMER0 Data Interrupt Latch Register */
-#define pREG_TIMER0_STAT_ILAT            ((volatile uint16_t *)REG_TIMER0_STAT_ILAT)             /* TIMER0 Status Interrupt Latch Register */
-#define pREG_TIMER0_ERR_TYPE             ((volatile uint32_t *)REG_TIMER0_ERR_TYPE)              /* TIMER0 Error Type Status Register */
-#define pREG_TIMER0_BCAST_PER            ((volatile uint32_t *)REG_TIMER0_BCAST_PER)             /* TIMER0 Broadcast Period Register */
-#define pREG_TIMER0_BCAST_WID            ((volatile uint32_t *)REG_TIMER0_BCAST_WID)             /* TIMER0 Broadcast Width Register */
-#define pREG_TIMER0_BCAST_DLY            ((volatile uint32_t *)REG_TIMER0_BCAST_DLY)             /* TIMER0 Broadcast Delay Register */
-#define pREG_TIMER0_TMR0_CFG             ((volatile uint16_t *)REG_TIMER0_TMR0_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR1_CFG             ((volatile uint16_t *)REG_TIMER0_TMR1_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR2_CFG             ((volatile uint16_t *)REG_TIMER0_TMR2_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR3_CFG             ((volatile uint16_t *)REG_TIMER0_TMR3_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR4_CFG             ((volatile uint16_t *)REG_TIMER0_TMR4_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR5_CFG             ((volatile uint16_t *)REG_TIMER0_TMR5_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR6_CFG             ((volatile uint16_t *)REG_TIMER0_TMR6_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR7_CFG             ((volatile uint16_t *)REG_TIMER0_TMR7_CFG)              /* TIMER0 Timer n Configuration Register */
-#define pREG_TIMER0_TMR0_CNT             ((volatile uint32_t *)REG_TIMER0_TMR0_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR1_CNT             ((volatile uint32_t *)REG_TIMER0_TMR1_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR2_CNT             ((volatile uint32_t *)REG_TIMER0_TMR2_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR3_CNT             ((volatile uint32_t *)REG_TIMER0_TMR3_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR4_CNT             ((volatile uint32_t *)REG_TIMER0_TMR4_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR5_CNT             ((volatile uint32_t *)REG_TIMER0_TMR5_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR6_CNT             ((volatile uint32_t *)REG_TIMER0_TMR6_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR7_CNT             ((volatile uint32_t *)REG_TIMER0_TMR7_CNT)              /* TIMER0 Timer n Counter Register */
-#define pREG_TIMER0_TMR0_PER             ((volatile uint32_t *)REG_TIMER0_TMR0_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR1_PER             ((volatile uint32_t *)REG_TIMER0_TMR1_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR2_PER             ((volatile uint32_t *)REG_TIMER0_TMR2_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR3_PER             ((volatile uint32_t *)REG_TIMER0_TMR3_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR4_PER             ((volatile uint32_t *)REG_TIMER0_TMR4_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR5_PER             ((volatile uint32_t *)REG_TIMER0_TMR5_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR6_PER             ((volatile uint32_t *)REG_TIMER0_TMR6_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR7_PER             ((volatile uint32_t *)REG_TIMER0_TMR7_PER)              /* TIMER0 Timer n Period Register */
-#define pREG_TIMER0_TMR0_WID             ((volatile uint32_t *)REG_TIMER0_TMR0_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR1_WID             ((volatile uint32_t *)REG_TIMER0_TMR1_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR2_WID             ((volatile uint32_t *)REG_TIMER0_TMR2_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR3_WID             ((volatile uint32_t *)REG_TIMER0_TMR3_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR4_WID             ((volatile uint32_t *)REG_TIMER0_TMR4_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR5_WID             ((volatile uint32_t *)REG_TIMER0_TMR5_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR6_WID             ((volatile uint32_t *)REG_TIMER0_TMR6_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR7_WID             ((volatile uint32_t *)REG_TIMER0_TMR7_WID)              /* TIMER0 Timer n Width Register */
-#define pREG_TIMER0_TMR0_DLY             ((volatile uint32_t *)REG_TIMER0_TMR0_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR1_DLY             ((volatile uint32_t *)REG_TIMER0_TMR1_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR2_DLY             ((volatile uint32_t *)REG_TIMER0_TMR2_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR3_DLY             ((volatile uint32_t *)REG_TIMER0_TMR3_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR4_DLY             ((volatile uint32_t *)REG_TIMER0_TMR4_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR5_DLY             ((volatile uint32_t *)REG_TIMER0_TMR5_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR6_DLY             ((volatile uint32_t *)REG_TIMER0_TMR6_DLY)              /* TIMER0 Timer n Delay Register */
-#define pREG_TIMER0_TMR7_DLY             ((volatile uint32_t *)REG_TIMER0_TMR7_DLY)              /* TIMER0 Timer n Delay Register */
-
-
-/* =========================================================================
-       CRC0
-   ========================================================================= */
-#define pREG_CRC0_CTL                    ((volatile uint32_t *)REG_CRC0_CTL)                     /* CRC0 Control Register */
-#define pREG_CRC0_DCNT                   ((volatile uint32_t *)REG_CRC0_DCNT)                    /* CRC0 Data Word Count Register */
-#define pREG_CRC0_DCNTRLD                ((volatile uint32_t *)REG_CRC0_DCNTRLD)                 /* CRC0 Data Word Count Reload Register */
-#define pREG_CRC0_COMP                   ((volatile uint32_t *)REG_CRC0_COMP)                    /* CRC0 Data Compare Register */
-#define pREG_CRC0_FILLVAL                ((volatile uint32_t *)REG_CRC0_FILLVAL)                 /* CRC0 Fill Value Register */
-#define pREG_CRC0_DFIFO                  ((volatile uint32_t *)REG_CRC0_DFIFO)                   /* CRC0 Data FIFO Register */
-#define pREG_CRC0_INEN                   ((volatile uint32_t *)REG_CRC0_INEN)                    /* CRC0 Interrupt Enable Register */
-#define pREG_CRC0_INEN_SET               ((volatile uint32_t *)REG_CRC0_INEN_SET)                /* CRC0 Interrupt Enable Set Register */
-#define pREG_CRC0_INEN_CLR               ((volatile uint32_t *)REG_CRC0_INEN_CLR)                /* CRC0 Interrupt Enable Clear Register */
-#define pREG_CRC0_POLY                   ((volatile uint32_t *)REG_CRC0_POLY)                    /* CRC0 Polynomial Register */
-#define pREG_CRC0_STAT                   ((volatile uint32_t *)REG_CRC0_STAT)                    /* CRC0 Status Register */
-#define pREG_CRC0_DCNTCAP                ((volatile uint32_t *)REG_CRC0_DCNTCAP)                 /* CRC0 Data Count Capture Register */
-#define pREG_CRC0_RESULT_FIN             ((volatile uint32_t *)REG_CRC0_RESULT_FIN)              /* CRC0 CRC Final Result Register */
-#define pREG_CRC0_RESULT_CUR             ((volatile uint32_t *)REG_CRC0_RESULT_CUR)              /* CRC0 CRC Current Result Register */
-#define pREG_CRC0_REVID                  ((volatile uint32_t *)REG_CRC0_REVID)                   /* CRC0 Revision ID Register */
-
-/* =========================================================================
-       CRC1
-   ========================================================================= */
-#define pREG_CRC1_CTL                    ((volatile uint32_t *)REG_CRC1_CTL)                     /* CRC1 Control Register */
-#define pREG_CRC1_DCNT                   ((volatile uint32_t *)REG_CRC1_DCNT)                    /* CRC1 Data Word Count Register */
-#define pREG_CRC1_DCNTRLD                ((volatile uint32_t *)REG_CRC1_DCNTRLD)                 /* CRC1 Data Word Count Reload Register */
-#define pREG_CRC1_COMP                   ((volatile uint32_t *)REG_CRC1_COMP)                    /* CRC1 Data Compare Register */
-#define pREG_CRC1_FILLVAL                ((volatile uint32_t *)REG_CRC1_FILLVAL)                 /* CRC1 Fill Value Register */
-#define pREG_CRC1_DFIFO                  ((volatile uint32_t *)REG_CRC1_DFIFO)                   /* CRC1 Data FIFO Register */
-#define pREG_CRC1_INEN                   ((volatile uint32_t *)REG_CRC1_INEN)                    /* CRC1 Interrupt Enable Register */
-#define pREG_CRC1_INEN_SET               ((volatile uint32_t *)REG_CRC1_INEN_SET)                /* CRC1 Interrupt Enable Set Register */
-#define pREG_CRC1_INEN_CLR               ((volatile uint32_t *)REG_CRC1_INEN_CLR)                /* CRC1 Interrupt Enable Clear Register */
-#define pREG_CRC1_POLY                   ((volatile uint32_t *)REG_CRC1_POLY)                    /* CRC1 Polynomial Register */
-#define pREG_CRC1_STAT                   ((volatile uint32_t *)REG_CRC1_STAT)                    /* CRC1 Status Register */
-#define pREG_CRC1_DCNTCAP                ((volatile uint32_t *)REG_CRC1_DCNTCAP)                 /* CRC1 Data Count Capture Register */
-#define pREG_CRC1_RESULT_FIN             ((volatile uint32_t *)REG_CRC1_RESULT_FIN)              /* CRC1 CRC Final Result Register */
-#define pREG_CRC1_RESULT_CUR             ((volatile uint32_t *)REG_CRC1_RESULT_CUR)              /* CRC1 CRC Current Result Register */
-#define pREG_CRC1_REVID                  ((volatile uint32_t *)REG_CRC1_REVID)                   /* CRC1 Revision ID Register */
-
-
-/* =========================================================================
-       TWI0
-   ========================================================================= */
-#define pREG_TWI0_CLKDIV                 ((volatile uint16_t *)REG_TWI0_CLKDIV)                  /* TWI0 SCL Clock Divider Register */
-#define pREG_TWI0_CTL                    ((volatile uint16_t *)REG_TWI0_CTL)                     /* TWI0 Control Register */
-#define pREG_TWI0_SLVCTL                 ((volatile uint16_t *)REG_TWI0_SLVCTL)                  /* TWI0 Slave Mode Control Register */
-#define pREG_TWI0_SLVSTAT                ((volatile uint16_t *)REG_TWI0_SLVSTAT)                 /* TWI0 Slave Mode Status Register */
-#define pREG_TWI0_SLVADDR                ((volatile uint16_t *)REG_TWI0_SLVADDR)                 /* TWI0 Slave Mode Address Register */
-#define pREG_TWI0_MSTRCTL                ((volatile uint16_t *)REG_TWI0_MSTRCTL)                 /* TWI0 Master Mode Control Registers */
-#define pREG_TWI0_MSTRSTAT               ((volatile uint16_t *)REG_TWI0_MSTRSTAT)                /* TWI0 Master Mode Status Register */
-#define pREG_TWI0_MSTRADDR               ((volatile uint16_t *)REG_TWI0_MSTRADDR)                /* TWI0 Master Mode Address Register */
-#define pREG_TWI0_ISTAT                  ((volatile uint16_t *)REG_TWI0_ISTAT)                   /* TWI0 Interrupt Status Register */
-#define pREG_TWI0_IMSK                   ((volatile uint16_t *)REG_TWI0_IMSK)                    /* TWI0 Interrupt Mask Register */
-#define pREG_TWI0_FIFOCTL                ((volatile uint16_t *)REG_TWI0_FIFOCTL)                 /* TWI0 FIFO Control Register */
-#define pREG_TWI0_FIFOSTAT               ((volatile uint16_t *)REG_TWI0_FIFOSTAT)                /* TWI0 FIFO Status Register */
-#define pREG_TWI0_TXDATA8                ((volatile uint16_t *)REG_TWI0_TXDATA8)                 /* TWI0 Tx Data Single-Byte Register */
-#define pREG_TWI0_TXDATA16               ((volatile uint16_t *)REG_TWI0_TXDATA16)                /* TWI0 Tx Data Double-Byte Register */
-#define pREG_TWI0_RXDATA8                ((volatile uint16_t *)REG_TWI0_RXDATA8)                 /* TWI0 Rx Data Single-Byte Register */
-#define pREG_TWI0_RXDATA16               ((volatile uint16_t *)REG_TWI0_RXDATA16)                /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================================================================
-       TWI1
-   ========================================================================= */
-#define pREG_TWI1_CLKDIV                 ((volatile uint16_t *)REG_TWI1_CLKDIV)                  /* TWI1 SCL Clock Divider Register */
-#define pREG_TWI1_CTL                    ((volatile uint16_t *)REG_TWI1_CTL)                     /* TWI1 Control Register */
-#define pREG_TWI1_SLVCTL                 ((volatile uint16_t *)REG_TWI1_SLVCTL)                  /* TWI1 Slave Mode Control Register */
-#define pREG_TWI1_SLVSTAT                ((volatile uint16_t *)REG_TWI1_SLVSTAT)                 /* TWI1 Slave Mode Status Register */
-#define pREG_TWI1_SLVADDR                ((volatile uint16_t *)REG_TWI1_SLVADDR)                 /* TWI1 Slave Mode Address Register */
-#define pREG_TWI1_MSTRCTL                ((volatile uint16_t *)REG_TWI1_MSTRCTL)                 /* TWI1 Master Mode Control Registers */
-#define pREG_TWI1_MSTRSTAT               ((volatile uint16_t *)REG_TWI1_MSTRSTAT)                /* TWI1 Master Mode Status Register */
-#define pREG_TWI1_MSTRADDR               ((volatile uint16_t *)REG_TWI1_MSTRADDR)                /* TWI1 Master Mode Address Register */
-#define pREG_TWI1_ISTAT                  ((volatile uint16_t *)REG_TWI1_ISTAT)                   /* TWI1 Interrupt Status Register */
-#define pREG_TWI1_IMSK                   ((volatile uint16_t *)REG_TWI1_IMSK)                    /* TWI1 Interrupt Mask Register */
-#define pREG_TWI1_FIFOCTL                ((volatile uint16_t *)REG_TWI1_FIFOCTL)                 /* TWI1 FIFO Control Register */
-#define pREG_TWI1_FIFOSTAT               ((volatile uint16_t *)REG_TWI1_FIFOSTAT)                /* TWI1 FIFO Status Register */
-#define pREG_TWI1_TXDATA8                ((volatile uint16_t *)REG_TWI1_TXDATA8)                 /* TWI1 Tx Data Single-Byte Register */
-#define pREG_TWI1_TXDATA16               ((volatile uint16_t *)REG_TWI1_TXDATA16)                /* TWI1 Tx Data Double-Byte Register */
-#define pREG_TWI1_RXDATA8                ((volatile uint16_t *)REG_TWI1_RXDATA8)                 /* TWI1 Rx Data Single-Byte Register */
-#define pREG_TWI1_RXDATA16               ((volatile uint16_t *)REG_TWI1_RXDATA16)                /* TWI1 Rx Data Double-Byte Register */
-
-
-/* =========================================================================
-       UART0
-   ========================================================================= */
-#define pREG_UART0_REVID                 ((volatile uint32_t *)REG_UART0_REVID)                  /* UART0 Revision ID Register */
-#define pREG_UART0_CTL                   ((volatile uint32_t *)REG_UART0_CTL)                    /* UART0 Control Register */
-#define pREG_UART0_STAT                  ((volatile uint32_t *)REG_UART0_STAT)                   /* UART0 Status Register */
-#define pREG_UART0_SCR                   ((volatile uint32_t *)REG_UART0_SCR)                    /* UART0 Scratch Register */
-#define pREG_UART0_CLK                   ((volatile uint32_t *)REG_UART0_CLK)                    /* UART0 Clock Rate Register */
-#define pREG_UART0_IMSK                  ((volatile uint32_t *)REG_UART0_IMSK)                   /* UART0 Interrupt Mask Register */
-#define pREG_UART0_IMSK_SET              ((volatile uint32_t *)REG_UART0_IMSK_SET)               /* UART0 Interrupt Mask Set Register */
-#define pREG_UART0_IMSK_CLR              ((volatile uint32_t *)REG_UART0_IMSK_CLR)               /* UART0 Interrupt Mask Clear Register */
-#define pREG_UART0_RBR                   ((volatile uint32_t *)REG_UART0_RBR)                    /* UART0 Receive Buffer Register */
-#define pREG_UART0_THR                   ((volatile uint32_t *)REG_UART0_THR)                    /* UART0 Transmit Hold Register */
-#define pREG_UART0_TAIP                  ((volatile uint32_t *)REG_UART0_TAIP)                   /* UART0 Transmit Address/Insert Pulse Register */
-#define pREG_UART0_TSR                   ((volatile uint32_t *)REG_UART0_TSR)                    /* UART0 Transmit Shift Register */
-#define pREG_UART0_RSR                   ((volatile uint32_t *)REG_UART0_RSR)                    /* UART0 Receive Shift Register */
-#define pREG_UART0_TXCNT                 ((volatile uint32_t *)REG_UART0_TXCNT)                  /* UART0 Transmit Counter Register */
-#define pREG_UART0_RXCNT                 ((volatile uint32_t *)REG_UART0_RXCNT)                  /* UART0 Receive Counter Register */
-
-/* =========================================================================
-       UART1
-   ========================================================================= */
-#define pREG_UART1_REVID                 ((volatile uint32_t *)REG_UART1_REVID)                  /* UART1 Revision ID Register */
-#define pREG_UART1_CTL                   ((volatile uint32_t *)REG_UART1_CTL)                    /* UART1 Control Register */
-#define pREG_UART1_STAT                  ((volatile uint32_t *)REG_UART1_STAT)                   /* UART1 Status Register */
-#define pREG_UART1_SCR                   ((volatile uint32_t *)REG_UART1_SCR)                    /* UART1 Scratch Register */
-#define pREG_UART1_CLK                   ((volatile uint32_t *)REG_UART1_CLK)                    /* UART1 Clock Rate Register */
-#define pREG_UART1_IMSK                  ((volatile uint32_t *)REG_UART1_IMSK)                   /* UART1 Interrupt Mask Register */
-#define pREG_UART1_IMSK_SET              ((volatile uint32_t *)REG_UART1_IMSK_SET)               /* UART1 Interrupt Mask Set Register */
-#define pREG_UART1_IMSK_CLR              ((volatile uint32_t *)REG_UART1_IMSK_CLR)               /* UART1 Interrupt Mask Clear Register */
-#define pREG_UART1_RBR                   ((volatile uint32_t *)REG_UART1_RBR)                    /* UART1 Receive Buffer Register */
-#define pREG_UART1_THR                   ((volatile uint32_t *)REG_UART1_THR)                    /* UART1 Transmit Hold Register */
-#define pREG_UART1_TAIP                  ((volatile uint32_t *)REG_UART1_TAIP)                   /* UART1 Transmit Address/Insert Pulse Register */
-#define pREG_UART1_TSR                   ((volatile uint32_t *)REG_UART1_TSR)                    /* UART1 Transmit Shift Register */
-#define pREG_UART1_RSR                   ((volatile uint32_t *)REG_UART1_RSR)                    /* UART1 Receive Shift Register */
-#define pREG_UART1_TXCNT                 ((volatile uint32_t *)REG_UART1_TXCNT)                  /* UART1 Transmit Counter Register */
-#define pREG_UART1_RXCNT                 ((volatile uint32_t *)REG_UART1_RXCNT)                  /* UART1 Receive Counter Register */
-
-
-/* =========================================================================
-       PORTA
-   ========================================================================= */
-#define pREG_PORTA_FER                   ((volatile uint32_t *)REG_PORTA_FER)                    /* PORTA Port x Function Enable Register */
-#define pREG_PORTA_FER_SET               ((volatile uint32_t *)REG_PORTA_FER_SET)                /* PORTA Port x Function Enable Set Register */
-#define pREG_PORTA_FER_CLR               ((volatile uint32_t *)REG_PORTA_FER_CLR)                /* PORTA Port x Function Enable Clear Register */
-#define pREG_PORTA_DATA                  ((volatile uint32_t *)REG_PORTA_DATA)                   /* PORTA Port x GPIO Data Register */
-#define pREG_PORTA_DATA_SET              ((volatile uint32_t *)REG_PORTA_DATA_SET)               /* PORTA Port x GPIO Data Set Register */
-#define pREG_PORTA_DATA_CLR              ((volatile uint32_t *)REG_PORTA_DATA_CLR)               /* PORTA Port x GPIO Data Clear Register */
-#define pREG_PORTA_DIR                   ((volatile uint32_t *)REG_PORTA_DIR)                    /* PORTA Port x GPIO Direction Register */
-#define pREG_PORTA_DIR_SET               ((volatile uint32_t *)REG_PORTA_DIR_SET)                /* PORTA Port x GPIO Direction Set Register */
-#define pREG_PORTA_DIR_CLR               ((volatile uint32_t *)REG_PORTA_DIR_CLR)                /* PORTA Port x GPIO Direction Clear Register */
-#define pREG_PORTA_INEN                  ((volatile uint32_t *)REG_PORTA_INEN)                   /* PORTA Port x GPIO Input Enable Register */
-#define pREG_PORTA_INEN_SET              ((volatile uint32_t *)REG_PORTA_INEN_SET)               /* PORTA Port x GPIO Input Enable Set Register */
-#define pREG_PORTA_INEN_CLR              ((volatile uint32_t *)REG_PORTA_INEN_CLR)               /* PORTA Port x GPIO Input Enable Clear Register */
-#define pREG_PORTA_MUX                   ((volatile uint32_t *)REG_PORTA_MUX)                    /* PORTA Port x Multiplexer Control Register */
-#define pREG_PORTA_DATA_TGL              ((volatile uint32_t *)REG_PORTA_DATA_TGL)               /* PORTA Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTA_POL                   ((volatile uint32_t *)REG_PORTA_POL)                    /* PORTA Port x GPIO Polarity Invert Register */
-#define pREG_PORTA_POL_SET               ((volatile uint32_t *)REG_PORTA_POL_SET)                /* PORTA Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTA_POL_CLR               ((volatile uint32_t *)REG_PORTA_POL_CLR)                /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTA_LOCK                  ((volatile uint32_t *)REG_PORTA_LOCK)                   /* PORTA Port x GPIO Lock Register */
-#define pREG_PORTA_REVID                 ((volatile uint32_t *)REG_PORTA_REVID)                  /* PORTA Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTB
-   ========================================================================= */
-#define pREG_PORTB_FER                   ((volatile uint32_t *)REG_PORTB_FER)                    /* PORTB Port x Function Enable Register */
-#define pREG_PORTB_FER_SET               ((volatile uint32_t *)REG_PORTB_FER_SET)                /* PORTB Port x Function Enable Set Register */
-#define pREG_PORTB_FER_CLR               ((volatile uint32_t *)REG_PORTB_FER_CLR)                /* PORTB Port x Function Enable Clear Register */
-#define pREG_PORTB_DATA                  ((volatile uint32_t *)REG_PORTB_DATA)                   /* PORTB Port x GPIO Data Register */
-#define pREG_PORTB_DATA_SET              ((volatile uint32_t *)REG_PORTB_DATA_SET)               /* PORTB Port x GPIO Data Set Register */
-#define pREG_PORTB_DATA_CLR              ((volatile uint32_t *)REG_PORTB_DATA_CLR)               /* PORTB Port x GPIO Data Clear Register */
-#define pREG_PORTB_DIR                   ((volatile uint32_t *)REG_PORTB_DIR)                    /* PORTB Port x GPIO Direction Register */
-#define pREG_PORTB_DIR_SET               ((volatile uint32_t *)REG_PORTB_DIR_SET)                /* PORTB Port x GPIO Direction Set Register */
-#define pREG_PORTB_DIR_CLR               ((volatile uint32_t *)REG_PORTB_DIR_CLR)                /* PORTB Port x GPIO Direction Clear Register */
-#define pREG_PORTB_INEN                  ((volatile uint32_t *)REG_PORTB_INEN)                   /* PORTB Port x GPIO Input Enable Register */
-#define pREG_PORTB_INEN_SET              ((volatile uint32_t *)REG_PORTB_INEN_SET)               /* PORTB Port x GPIO Input Enable Set Register */
-#define pREG_PORTB_INEN_CLR              ((volatile uint32_t *)REG_PORTB_INEN_CLR)               /* PORTB Port x GPIO Input Enable Clear Register */
-#define pREG_PORTB_MUX                   ((volatile uint32_t *)REG_PORTB_MUX)                    /* PORTB Port x Multiplexer Control Register */
-#define pREG_PORTB_DATA_TGL              ((volatile uint32_t *)REG_PORTB_DATA_TGL)               /* PORTB Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTB_POL                   ((volatile uint32_t *)REG_PORTB_POL)                    /* PORTB Port x GPIO Polarity Invert Register */
-#define pREG_PORTB_POL_SET               ((volatile uint32_t *)REG_PORTB_POL_SET)                /* PORTB Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTB_POL_CLR               ((volatile uint32_t *)REG_PORTB_POL_CLR)                /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTB_LOCK                  ((volatile uint32_t *)REG_PORTB_LOCK)                   /* PORTB Port x GPIO Lock Register */
-#define pREG_PORTB_REVID                 ((volatile uint32_t *)REG_PORTB_REVID)                  /* PORTB Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTC
-   ========================================================================= */
-#define pREG_PORTC_FER                   ((volatile uint32_t *)REG_PORTC_FER)                    /* PORTC Port x Function Enable Register */
-#define pREG_PORTC_FER_SET               ((volatile uint32_t *)REG_PORTC_FER_SET)                /* PORTC Port x Function Enable Set Register */
-#define pREG_PORTC_FER_CLR               ((volatile uint32_t *)REG_PORTC_FER_CLR)                /* PORTC Port x Function Enable Clear Register */
-#define pREG_PORTC_DATA                  ((volatile uint32_t *)REG_PORTC_DATA)                   /* PORTC Port x GPIO Data Register */
-#define pREG_PORTC_DATA_SET              ((volatile uint32_t *)REG_PORTC_DATA_SET)               /* PORTC Port x GPIO Data Set Register */
-#define pREG_PORTC_DATA_CLR              ((volatile uint32_t *)REG_PORTC_DATA_CLR)               /* PORTC Port x GPIO Data Clear Register */
-#define pREG_PORTC_DIR                   ((volatile uint32_t *)REG_PORTC_DIR)                    /* PORTC Port x GPIO Direction Register */
-#define pREG_PORTC_DIR_SET               ((volatile uint32_t *)REG_PORTC_DIR_SET)                /* PORTC Port x GPIO Direction Set Register */
-#define pREG_PORTC_DIR_CLR               ((volatile uint32_t *)REG_PORTC_DIR_CLR)                /* PORTC Port x GPIO Direction Clear Register */
-#define pREG_PORTC_INEN                  ((volatile uint32_t *)REG_PORTC_INEN)                   /* PORTC Port x GPIO Input Enable Register */
-#define pREG_PORTC_INEN_SET              ((volatile uint32_t *)REG_PORTC_INEN_SET)               /* PORTC Port x GPIO Input Enable Set Register */
-#define pREG_PORTC_INEN_CLR              ((volatile uint32_t *)REG_PORTC_INEN_CLR)               /* PORTC Port x GPIO Input Enable Clear Register */
-#define pREG_PORTC_MUX                   ((volatile uint32_t *)REG_PORTC_MUX)                    /* PORTC Port x Multiplexer Control Register */
-#define pREG_PORTC_DATA_TGL              ((volatile uint32_t *)REG_PORTC_DATA_TGL)               /* PORTC Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTC_POL                   ((volatile uint32_t *)REG_PORTC_POL)                    /* PORTC Port x GPIO Polarity Invert Register */
-#define pREG_PORTC_POL_SET               ((volatile uint32_t *)REG_PORTC_POL_SET)                /* PORTC Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTC_POL_CLR               ((volatile uint32_t *)REG_PORTC_POL_CLR)                /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTC_LOCK                  ((volatile uint32_t *)REG_PORTC_LOCK)                   /* PORTC Port x GPIO Lock Register */
-#define pREG_PORTC_REVID                 ((volatile uint32_t *)REG_PORTC_REVID)                  /* PORTC Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTD
-   ========================================================================= */
-#define pREG_PORTD_FER                   ((volatile uint32_t *)REG_PORTD_FER)                    /* PORTD Port x Function Enable Register */
-#define pREG_PORTD_FER_SET               ((volatile uint32_t *)REG_PORTD_FER_SET)                /* PORTD Port x Function Enable Set Register */
-#define pREG_PORTD_FER_CLR               ((volatile uint32_t *)REG_PORTD_FER_CLR)                /* PORTD Port x Function Enable Clear Register */
-#define pREG_PORTD_DATA                  ((volatile uint32_t *)REG_PORTD_DATA)                   /* PORTD Port x GPIO Data Register */
-#define pREG_PORTD_DATA_SET              ((volatile uint32_t *)REG_PORTD_DATA_SET)               /* PORTD Port x GPIO Data Set Register */
-#define pREG_PORTD_DATA_CLR              ((volatile uint32_t *)REG_PORTD_DATA_CLR)               /* PORTD Port x GPIO Data Clear Register */
-#define pREG_PORTD_DIR                   ((volatile uint32_t *)REG_PORTD_DIR)                    /* PORTD Port x GPIO Direction Register */
-#define pREG_PORTD_DIR_SET               ((volatile uint32_t *)REG_PORTD_DIR_SET)                /* PORTD Port x GPIO Direction Set Register */
-#define pREG_PORTD_DIR_CLR               ((volatile uint32_t *)REG_PORTD_DIR_CLR)                /* PORTD Port x GPIO Direction Clear Register */
-#define pREG_PORTD_INEN                  ((volatile uint32_t *)REG_PORTD_INEN)                   /* PORTD Port x GPIO Input Enable Register */
-#define pREG_PORTD_INEN_SET              ((volatile uint32_t *)REG_PORTD_INEN_SET)               /* PORTD Port x GPIO Input Enable Set Register */
-#define pREG_PORTD_INEN_CLR              ((volatile uint32_t *)REG_PORTD_INEN_CLR)               /* PORTD Port x GPIO Input Enable Clear Register */
-#define pREG_PORTD_MUX                   ((volatile uint32_t *)REG_PORTD_MUX)                    /* PORTD Port x Multiplexer Control Register */
-#define pREG_PORTD_DATA_TGL              ((volatile uint32_t *)REG_PORTD_DATA_TGL)               /* PORTD Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTD_POL                   ((volatile uint32_t *)REG_PORTD_POL)                    /* PORTD Port x GPIO Polarity Invert Register */
-#define pREG_PORTD_POL_SET               ((volatile uint32_t *)REG_PORTD_POL_SET)                /* PORTD Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTD_POL_CLR               ((volatile uint32_t *)REG_PORTD_POL_CLR)                /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTD_LOCK                  ((volatile uint32_t *)REG_PORTD_LOCK)                   /* PORTD Port x GPIO Lock Register */
-#define pREG_PORTD_REVID                 ((volatile uint32_t *)REG_PORTD_REVID)                  /* PORTD Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTE
-   ========================================================================= */
-#define pREG_PORTE_FER                   ((volatile uint32_t *)REG_PORTE_FER)                    /* PORTE Port x Function Enable Register */
-#define pREG_PORTE_FER_SET               ((volatile uint32_t *)REG_PORTE_FER_SET)                /* PORTE Port x Function Enable Set Register */
-#define pREG_PORTE_FER_CLR               ((volatile uint32_t *)REG_PORTE_FER_CLR)                /* PORTE Port x Function Enable Clear Register */
-#define pREG_PORTE_DATA                  ((volatile uint32_t *)REG_PORTE_DATA)                   /* PORTE Port x GPIO Data Register */
-#define pREG_PORTE_DATA_SET              ((volatile uint32_t *)REG_PORTE_DATA_SET)               /* PORTE Port x GPIO Data Set Register */
-#define pREG_PORTE_DATA_CLR              ((volatile uint32_t *)REG_PORTE_DATA_CLR)               /* PORTE Port x GPIO Data Clear Register */
-#define pREG_PORTE_DIR                   ((volatile uint32_t *)REG_PORTE_DIR)                    /* PORTE Port x GPIO Direction Register */
-#define pREG_PORTE_DIR_SET               ((volatile uint32_t *)REG_PORTE_DIR_SET)                /* PORTE Port x GPIO Direction Set Register */
-#define pREG_PORTE_DIR_CLR               ((volatile uint32_t *)REG_PORTE_DIR_CLR)                /* PORTE Port x GPIO Direction Clear Register */
-#define pREG_PORTE_INEN                  ((volatile uint32_t *)REG_PORTE_INEN)                   /* PORTE Port x GPIO Input Enable Register */
-#define pREG_PORTE_INEN_SET              ((volatile uint32_t *)REG_PORTE_INEN_SET)               /* PORTE Port x GPIO Input Enable Set Register */
-#define pREG_PORTE_INEN_CLR              ((volatile uint32_t *)REG_PORTE_INEN_CLR)               /* PORTE Port x GPIO Input Enable Clear Register */
-#define pREG_PORTE_MUX                   ((volatile uint32_t *)REG_PORTE_MUX)                    /* PORTE Port x Multiplexer Control Register */
-#define pREG_PORTE_DATA_TGL              ((volatile uint32_t *)REG_PORTE_DATA_TGL)               /* PORTE Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTE_POL                   ((volatile uint32_t *)REG_PORTE_POL)                    /* PORTE Port x GPIO Polarity Invert Register */
-#define pREG_PORTE_POL_SET               ((volatile uint32_t *)REG_PORTE_POL_SET)                /* PORTE Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTE_POL_CLR               ((volatile uint32_t *)REG_PORTE_POL_CLR)                /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTE_LOCK                  ((volatile uint32_t *)REG_PORTE_LOCK)                   /* PORTE Port x GPIO Lock Register */
-#define pREG_PORTE_REVID                 ((volatile uint32_t *)REG_PORTE_REVID)                  /* PORTE Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTF
-   ========================================================================= */
-#define pREG_PORTF_FER                   ((volatile uint32_t *)REG_PORTF_FER)                    /* PORTF Port x Function Enable Register */
-#define pREG_PORTF_FER_SET               ((volatile uint32_t *)REG_PORTF_FER_SET)                /* PORTF Port x Function Enable Set Register */
-#define pREG_PORTF_FER_CLR               ((volatile uint32_t *)REG_PORTF_FER_CLR)                /* PORTF Port x Function Enable Clear Register */
-#define pREG_PORTF_DATA                  ((volatile uint32_t *)REG_PORTF_DATA)                   /* PORTF Port x GPIO Data Register */
-#define pREG_PORTF_DATA_SET              ((volatile uint32_t *)REG_PORTF_DATA_SET)               /* PORTF Port x GPIO Data Set Register */
-#define pREG_PORTF_DATA_CLR              ((volatile uint32_t *)REG_PORTF_DATA_CLR)               /* PORTF Port x GPIO Data Clear Register */
-#define pREG_PORTF_DIR                   ((volatile uint32_t *)REG_PORTF_DIR)                    /* PORTF Port x GPIO Direction Register */
-#define pREG_PORTF_DIR_SET               ((volatile uint32_t *)REG_PORTF_DIR_SET)                /* PORTF Port x GPIO Direction Set Register */
-#define pREG_PORTF_DIR_CLR               ((volatile uint32_t *)REG_PORTF_DIR_CLR)                /* PORTF Port x GPIO Direction Clear Register */
-#define pREG_PORTF_INEN                  ((volatile uint32_t *)REG_PORTF_INEN)                   /* PORTF Port x GPIO Input Enable Register */
-#define pREG_PORTF_INEN_SET              ((volatile uint32_t *)REG_PORTF_INEN_SET)               /* PORTF Port x GPIO Input Enable Set Register */
-#define pREG_PORTF_INEN_CLR              ((volatile uint32_t *)REG_PORTF_INEN_CLR)               /* PORTF Port x GPIO Input Enable Clear Register */
-#define pREG_PORTF_MUX                   ((volatile uint32_t *)REG_PORTF_MUX)                    /* PORTF Port x Multiplexer Control Register */
-#define pREG_PORTF_DATA_TGL              ((volatile uint32_t *)REG_PORTF_DATA_TGL)               /* PORTF Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTF_POL                   ((volatile uint32_t *)REG_PORTF_POL)                    /* PORTF Port x GPIO Polarity Invert Register */
-#define pREG_PORTF_POL_SET               ((volatile uint32_t *)REG_PORTF_POL_SET)                /* PORTF Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTF_POL_CLR               ((volatile uint32_t *)REG_PORTF_POL_CLR)                /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTF_LOCK                  ((volatile uint32_t *)REG_PORTF_LOCK)                   /* PORTF Port x GPIO Lock Register */
-#define pREG_PORTF_REVID                 ((volatile uint32_t *)REG_PORTF_REVID)                  /* PORTF Port x GPIO Revision ID */
-
-/* =========================================================================
-       PORTG
-   ========================================================================= */
-#define pREG_PORTG_FER                   ((volatile uint32_t *)REG_PORTG_FER)                    /* PORTG Port x Function Enable Register */
-#define pREG_PORTG_FER_SET               ((volatile uint32_t *)REG_PORTG_FER_SET)                /* PORTG Port x Function Enable Set Register */
-#define pREG_PORTG_FER_CLR               ((volatile uint32_t *)REG_PORTG_FER_CLR)                /* PORTG Port x Function Enable Clear Register */
-#define pREG_PORTG_DATA                  ((volatile uint32_t *)REG_PORTG_DATA)                   /* PORTG Port x GPIO Data Register */
-#define pREG_PORTG_DATA_SET              ((volatile uint32_t *)REG_PORTG_DATA_SET)               /* PORTG Port x GPIO Data Set Register */
-#define pREG_PORTG_DATA_CLR              ((volatile uint32_t *)REG_PORTG_DATA_CLR)               /* PORTG Port x GPIO Data Clear Register */
-#define pREG_PORTG_DIR                   ((volatile uint32_t *)REG_PORTG_DIR)                    /* PORTG Port x GPIO Direction Register */
-#define pREG_PORTG_DIR_SET               ((volatile uint32_t *)REG_PORTG_DIR_SET)                /* PORTG Port x GPIO Direction Set Register */
-#define pREG_PORTG_DIR_CLR               ((volatile uint32_t *)REG_PORTG_DIR_CLR)                /* PORTG Port x GPIO Direction Clear Register */
-#define pREG_PORTG_INEN                  ((volatile uint32_t *)REG_PORTG_INEN)                   /* PORTG Port x GPIO Input Enable Register */
-#define pREG_PORTG_INEN_SET              ((volatile uint32_t *)REG_PORTG_INEN_SET)               /* PORTG Port x GPIO Input Enable Set Register */
-#define pREG_PORTG_INEN_CLR              ((volatile uint32_t *)REG_PORTG_INEN_CLR)               /* PORTG Port x GPIO Input Enable Clear Register */
-#define pREG_PORTG_MUX                   ((volatile uint32_t *)REG_PORTG_MUX)                    /* PORTG Port x Multiplexer Control Register */
-#define pREG_PORTG_DATA_TGL              ((volatile uint32_t *)REG_PORTG_DATA_TGL)               /* PORTG Port x GPIO Input Enable Toggle Register */
-#define pREG_PORTG_POL                   ((volatile uint32_t *)REG_PORTG_POL)                    /* PORTG Port x GPIO Polarity Invert Register */
-#define pREG_PORTG_POL_SET               ((volatile uint32_t *)REG_PORTG_POL_SET)                /* PORTG Port x GPIO Polarity Invert Set Register */
-#define pREG_PORTG_POL_CLR               ((volatile uint32_t *)REG_PORTG_POL_CLR)                /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define pREG_PORTG_LOCK                  ((volatile uint32_t *)REG_PORTG_LOCK)                   /* PORTG Port x GPIO Lock Register */
-#define pREG_PORTG_REVID                 ((volatile uint32_t *)REG_PORTG_REVID)                  /* PORTG Port x GPIO Revision ID */
-
-
-/* =========================================================================
-       PADS0
-   ========================================================================= */
-#define pREG_PADS0_EMAC_PTP_CLKSEL       ((volatile uint32_t *)REG_PADS0_EMAC_PTP_CLKSEL)        /* PADS0 Clock Selection for EMAC and PTP */
-#define pREG_PADS0_TWI_VSEL              ((volatile uint32_t *)REG_PADS0_TWI_VSEL)               /* PADS0 TWI Voltage Selection */
-#define pREG_PADS0_PORTS_HYST            ((volatile uint32_t *)REG_PADS0_PORTS_HYST)             /* PADS0 Hysteresis Enable Register */
-
-
-/* =========================================================================
-       PINT0
-   ========================================================================= */
-#define pREG_PINT0_MSK_SET               ((volatile uint32_t *)REG_PINT0_MSK_SET)                /* PINT0 Pint Mask Set Register */
-#define pREG_PINT0_MSK_CLR               ((volatile uint32_t *)REG_PINT0_MSK_CLR)                /* PINT0 Pint Mask Clear Register */
-#define pREG_PINT0_REQ                   ((volatile uint32_t *)REG_PINT0_REQ)                    /* PINT0 Pint Request Register */
-#define pREG_PINT0_ASSIGN                ((volatile uint32_t *)REG_PINT0_ASSIGN)                 /* PINT0 Pint Assign Register */
-#define pREG_PINT0_EDGE_SET              ((volatile uint32_t *)REG_PINT0_EDGE_SET)               /* PINT0 Pint Edge Set Register */
-#define pREG_PINT0_EDGE_CLR              ((volatile uint32_t *)REG_PINT0_EDGE_CLR)               /* PINT0 Pint Edge Clear Register */
-#define pREG_PINT0_INV_SET               ((volatile uint32_t *)REG_PINT0_INV_SET)                /* PINT0 Pint Invert Set Register */
-#define pREG_PINT0_INV_CLR               ((volatile uint32_t *)REG_PINT0_INV_CLR)                /* PINT0 Pint Invert Clear Register */
-#define pREG_PINT0_PINSTATE              ((volatile uint32_t *)REG_PINT0_PINSTATE)               /* PINT0 Pint Pinstate Register */
-#define pREG_PINT0_LATCH                 ((volatile uint32_t *)REG_PINT0_LATCH)                  /* PINT0 Pint Latch Register */
-
-/* =========================================================================
-       PINT1
-   ========================================================================= */
-#define pREG_PINT1_MSK_SET               ((volatile uint32_t *)REG_PINT1_MSK_SET)                /* PINT1 Pint Mask Set Register */
-#define pREG_PINT1_MSK_CLR               ((volatile uint32_t *)REG_PINT1_MSK_CLR)                /* PINT1 Pint Mask Clear Register */
-#define pREG_PINT1_REQ                   ((volatile uint32_t *)REG_PINT1_REQ)                    /* PINT1 Pint Request Register */
-#define pREG_PINT1_ASSIGN                ((volatile uint32_t *)REG_PINT1_ASSIGN)                 /* PINT1 Pint Assign Register */
-#define pREG_PINT1_EDGE_SET              ((volatile uint32_t *)REG_PINT1_EDGE_SET)               /* PINT1 Pint Edge Set Register */
-#define pREG_PINT1_EDGE_CLR              ((volatile uint32_t *)REG_PINT1_EDGE_CLR)               /* PINT1 Pint Edge Clear Register */
-#define pREG_PINT1_INV_SET               ((volatile uint32_t *)REG_PINT1_INV_SET)                /* PINT1 Pint Invert Set Register */
-#define pREG_PINT1_INV_CLR               ((volatile uint32_t *)REG_PINT1_INV_CLR)                /* PINT1 Pint Invert Clear Register */
-#define pREG_PINT1_PINSTATE              ((volatile uint32_t *)REG_PINT1_PINSTATE)               /* PINT1 Pint Pinstate Register */
-#define pREG_PINT1_LATCH                 ((volatile uint32_t *)REG_PINT1_LATCH)                  /* PINT1 Pint Latch Register */
-
-/* =========================================================================
-       PINT2
-   ========================================================================= */
-#define pREG_PINT2_MSK_SET               ((volatile uint32_t *)REG_PINT2_MSK_SET)                /* PINT2 Pint Mask Set Register */
-#define pREG_PINT2_MSK_CLR               ((volatile uint32_t *)REG_PINT2_MSK_CLR)                /* PINT2 Pint Mask Clear Register */
-#define pREG_PINT2_REQ                   ((volatile uint32_t *)REG_PINT2_REQ)                    /* PINT2 Pint Request Register */
-#define pREG_PINT2_ASSIGN                ((volatile uint32_t *)REG_PINT2_ASSIGN)                 /* PINT2 Pint Assign Register */
-#define pREG_PINT2_EDGE_SET              ((volatile uint32_t *)REG_PINT2_EDGE_SET)               /* PINT2 Pint Edge Set Register */
-#define pREG_PINT2_EDGE_CLR              ((volatile uint32_t *)REG_PINT2_EDGE_CLR)               /* PINT2 Pint Edge Clear Register */
-#define pREG_PINT2_INV_SET               ((volatile uint32_t *)REG_PINT2_INV_SET)                /* PINT2 Pint Invert Set Register */
-#define pREG_PINT2_INV_CLR               ((volatile uint32_t *)REG_PINT2_INV_CLR)                /* PINT2 Pint Invert Clear Register */
-#define pREG_PINT2_PINSTATE              ((volatile uint32_t *)REG_PINT2_PINSTATE)               /* PINT2 Pint Pinstate Register */
-#define pREG_PINT2_LATCH                 ((volatile uint32_t *)REG_PINT2_LATCH)                  /* PINT2 Pint Latch Register */
-
-/* =========================================================================
-       PINT3
-   ========================================================================= */
-#define pREG_PINT3_MSK_SET               ((volatile uint32_t *)REG_PINT3_MSK_SET)                /* PINT3 Pint Mask Set Register */
-#define pREG_PINT3_MSK_CLR               ((volatile uint32_t *)REG_PINT3_MSK_CLR)                /* PINT3 Pint Mask Clear Register */
-#define pREG_PINT3_REQ                   ((volatile uint32_t *)REG_PINT3_REQ)                    /* PINT3 Pint Request Register */
-#define pREG_PINT3_ASSIGN                ((volatile uint32_t *)REG_PINT3_ASSIGN)                 /* PINT3 Pint Assign Register */
-#define pREG_PINT3_EDGE_SET              ((volatile uint32_t *)REG_PINT3_EDGE_SET)               /* PINT3 Pint Edge Set Register */
-#define pREG_PINT3_EDGE_CLR              ((volatile uint32_t *)REG_PINT3_EDGE_CLR)               /* PINT3 Pint Edge Clear Register */
-#define pREG_PINT3_INV_SET               ((volatile uint32_t *)REG_PINT3_INV_SET)                /* PINT3 Pint Invert Set Register */
-#define pREG_PINT3_INV_CLR               ((volatile uint32_t *)REG_PINT3_INV_CLR)                /* PINT3 Pint Invert Clear Register */
-#define pREG_PINT3_PINSTATE              ((volatile uint32_t *)REG_PINT3_PINSTATE)               /* PINT3 Pint Pinstate Register */
-#define pREG_PINT3_LATCH                 ((volatile uint32_t *)REG_PINT3_LATCH)                  /* PINT3 Pint Latch Register */
-
-/* =========================================================================
-       PINT4
-   ========================================================================= */
-#define pREG_PINT4_MSK_SET               ((volatile uint32_t *)REG_PINT4_MSK_SET)                /* PINT4 Pint Mask Set Register */
-#define pREG_PINT4_MSK_CLR               ((volatile uint32_t *)REG_PINT4_MSK_CLR)                /* PINT4 Pint Mask Clear Register */
-#define pREG_PINT4_REQ                   ((volatile uint32_t *)REG_PINT4_REQ)                    /* PINT4 Pint Request Register */
-#define pREG_PINT4_ASSIGN                ((volatile uint32_t *)REG_PINT4_ASSIGN)                 /* PINT4 Pint Assign Register */
-#define pREG_PINT4_EDGE_SET              ((volatile uint32_t *)REG_PINT4_EDGE_SET)               /* PINT4 Pint Edge Set Register */
-#define pREG_PINT4_EDGE_CLR              ((volatile uint32_t *)REG_PINT4_EDGE_CLR)               /* PINT4 Pint Edge Clear Register */
-#define pREG_PINT4_INV_SET               ((volatile uint32_t *)REG_PINT4_INV_SET)                /* PINT4 Pint Invert Set Register */
-#define pREG_PINT4_INV_CLR               ((volatile uint32_t *)REG_PINT4_INV_CLR)                /* PINT4 Pint Invert Clear Register */
-#define pREG_PINT4_PINSTATE              ((volatile uint32_t *)REG_PINT4_PINSTATE)               /* PINT4 Pint Pinstate Register */
-#define pREG_PINT4_LATCH                 ((volatile uint32_t *)REG_PINT4_LATCH)                  /* PINT4 Pint Latch Register */
-
-/* =========================================================================
-       PINT5
-   ========================================================================= */
-#define pREG_PINT5_MSK_SET               ((volatile uint32_t *)REG_PINT5_MSK_SET)                /* PINT5 Pint Mask Set Register */
-#define pREG_PINT5_MSK_CLR               ((volatile uint32_t *)REG_PINT5_MSK_CLR)                /* PINT5 Pint Mask Clear Register */
-#define pREG_PINT5_REQ                   ((volatile uint32_t *)REG_PINT5_REQ)                    /* PINT5 Pint Request Register */
-#define pREG_PINT5_ASSIGN                ((volatile uint32_t *)REG_PINT5_ASSIGN)                 /* PINT5 Pint Assign Register */
-#define pREG_PINT5_EDGE_SET              ((volatile uint32_t *)REG_PINT5_EDGE_SET)               /* PINT5 Pint Edge Set Register */
-#define pREG_PINT5_EDGE_CLR              ((volatile uint32_t *)REG_PINT5_EDGE_CLR)               /* PINT5 Pint Edge Clear Register */
-#define pREG_PINT5_INV_SET               ((volatile uint32_t *)REG_PINT5_INV_SET)                /* PINT5 Pint Invert Set Register */
-#define pREG_PINT5_INV_CLR               ((volatile uint32_t *)REG_PINT5_INV_CLR)                /* PINT5 Pint Invert Clear Register */
-#define pREG_PINT5_PINSTATE              ((volatile uint32_t *)REG_PINT5_PINSTATE)               /* PINT5 Pint Pinstate Register */
-#define pREG_PINT5_LATCH                 ((volatile uint32_t *)REG_PINT5_LATCH)                  /* PINT5 Pint Latch Register */
-
-
-/* =========================================================================
-       SMC0
-   ========================================================================= */
-#define pREG_SMC0_GCTL                   ((volatile uint32_t *)REG_SMC0_GCTL)                    /* SMC0 Grant Control Register */
-#define pREG_SMC0_GSTAT                  ((volatile uint32_t *)REG_SMC0_GSTAT)                   /* SMC0 Grant Status Register */
-#define pREG_SMC0_B0CTL                  ((volatile uint32_t *)REG_SMC0_B0CTL)                   /* SMC0 Bank 0 Control Register */
-#define pREG_SMC0_B0TIM                  ((volatile uint32_t *)REG_SMC0_B0TIM)                   /* SMC0 Bank 0 Timing Register */
-#define pREG_SMC0_B0ETIM                 ((volatile uint32_t *)REG_SMC0_B0ETIM)                  /* SMC0 Bank 0 Extended Timing Register */
-#define pREG_SMC0_B1CTL                  ((volatile uint32_t *)REG_SMC0_B1CTL)                   /* SMC0 Bank 1 Control Register */
-#define pREG_SMC0_B1TIM                  ((volatile uint32_t *)REG_SMC0_B1TIM)                   /* SMC0 Bank 1 Timing Register */
-#define pREG_SMC0_B1ETIM                 ((volatile uint32_t *)REG_SMC0_B1ETIM)                  /* SMC0 Bank 1 Extended Timing Register */
-#define pREG_SMC0_B2CTL                  ((volatile uint32_t *)REG_SMC0_B2CTL)                   /* SMC0 Bank 2 Control Register */
-#define pREG_SMC0_B2TIM                  ((volatile uint32_t *)REG_SMC0_B2TIM)                   /* SMC0 Bank 2 Timing Register */
-#define pREG_SMC0_B2ETIM                 ((volatile uint32_t *)REG_SMC0_B2ETIM)                  /* SMC0 Bank 2 Extended Timing Register */
-#define pREG_SMC0_B3CTL                  ((volatile uint32_t *)REG_SMC0_B3CTL)                   /* SMC0 Bank 3 Control Register */
-#define pREG_SMC0_B3TIM                  ((volatile uint32_t *)REG_SMC0_B3TIM)                   /* SMC0 Bank 3 Timing Register */
-#define pREG_SMC0_B3ETIM                 ((volatile uint32_t *)REG_SMC0_B3ETIM)                  /* SMC0 Bank 3 Extended Timing Register */
-
-
-/* =========================================================================
-       WDOG0
-   ========================================================================= */
-#define pREG_WDOG0_CTL                   ((volatile uint32_t *)REG_WDOG0_CTL)                    /* WDOG0 Control Register */
-#define pREG_WDOG0_CNT                   ((volatile uint32_t *)REG_WDOG0_CNT)                    /* WDOG0 Count Register */
-#define pREG_WDOG0_STAT                  ((volatile uint32_t *)REG_WDOG0_STAT)                   /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================================================================
-       WDOG1
-   ========================================================================= */
-#define pREG_WDOG1_CTL                   ((volatile uint32_t *)REG_WDOG1_CTL)                    /* WDOG1 Control Register */
-#define pREG_WDOG1_CNT                   ((volatile uint32_t *)REG_WDOG1_CNT)                    /* WDOG1 Count Register */
-#define pREG_WDOG1_STAT                  ((volatile uint32_t *)REG_WDOG1_STAT)                   /* WDOG1 Watchdog Timer Status Register */
-
-
-/* =========================================================================
-       EPPI0
-   ========================================================================= */
-#define pREG_EPPI0_STAT                  ((volatile uint32_t *)REG_EPPI0_STAT)                   /* EPPI0 Status Register */
-#define pREG_EPPI0_HCNT                  ((volatile uint32_t *)REG_EPPI0_HCNT)                   /* EPPI0 Horizontal Transfer Count Register */
-#define pREG_EPPI0_HDLY                  ((volatile uint32_t *)REG_EPPI0_HDLY)                   /* EPPI0 Horizontal Delay Count Register */
-#define pREG_EPPI0_VCNT                  ((volatile uint32_t *)REG_EPPI0_VCNT)                   /* EPPI0 Vertical Transfer Count Register */
-#define pREG_EPPI0_VDLY                  ((volatile uint32_t *)REG_EPPI0_VDLY)                   /* EPPI0 Vertical Delay Count Register */
-#define pREG_EPPI0_FRAME                 ((volatile uint32_t *)REG_EPPI0_FRAME)                  /* EPPI0 Lines Per Frame Register */
-#define pREG_EPPI0_LINE                  ((volatile uint32_t *)REG_EPPI0_LINE)                   /* EPPI0 Samples Per Line Register */
-#define pREG_EPPI0_CLKDIV                ((volatile uint32_t *)REG_EPPI0_CLKDIV)                 /* EPPI0 Clock Divide Register */
-#define pREG_EPPI0_CTL                   ((volatile uint32_t *)REG_EPPI0_CTL)                    /* EPPI0 Control Register */
-#define pREG_EPPI0_FS1_WLHB              ((volatile uint32_t *)REG_EPPI0_FS1_WLHB)               /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI0_FS1_PASPL             ((volatile uint32_t *)REG_EPPI0_FS1_PASPL)              /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI0_FS2_WLVB              ((volatile uint32_t *)REG_EPPI0_FS2_WLVB)               /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI0_FS2_PALPF             ((volatile uint32_t *)REG_EPPI0_FS2_PALPF)              /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI0_IMSK                  ((volatile uint32_t *)REG_EPPI0_IMSK)                   /* EPPI0 Interrupt Mask Register */
-#define pREG_EPPI0_ODDCLIP               ((volatile uint32_t *)REG_EPPI0_ODDCLIP)                /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI0_EVENCLIP              ((volatile uint32_t *)REG_EPPI0_EVENCLIP)               /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI0_FS1_DLY               ((volatile uint32_t *)REG_EPPI0_FS1_DLY)                /* EPPI0 Frame Sync 1 Delay Value */
-#define pREG_EPPI0_FS2_DLY               ((volatile uint32_t *)REG_EPPI0_FS2_DLY)                /* EPPI0 Frame Sync 2 Delay Value */
-#define pREG_EPPI0_CTL2                  ((volatile uint32_t *)REG_EPPI0_CTL2)                   /* EPPI0 Control Register 2 */
-
-/* =========================================================================
-       EPPI1
-   ========================================================================= */
-#define pREG_EPPI1_STAT                  ((volatile uint32_t *)REG_EPPI1_STAT)                   /* EPPI1 Status Register */
-#define pREG_EPPI1_HCNT                  ((volatile uint32_t *)REG_EPPI1_HCNT)                   /* EPPI1 Horizontal Transfer Count Register */
-#define pREG_EPPI1_HDLY                  ((volatile uint32_t *)REG_EPPI1_HDLY)                   /* EPPI1 Horizontal Delay Count Register */
-#define pREG_EPPI1_VCNT                  ((volatile uint32_t *)REG_EPPI1_VCNT)                   /* EPPI1 Vertical Transfer Count Register */
-#define pREG_EPPI1_VDLY                  ((volatile uint32_t *)REG_EPPI1_VDLY)                   /* EPPI1 Vertical Delay Count Register */
-#define pREG_EPPI1_FRAME                 ((volatile uint32_t *)REG_EPPI1_FRAME)                  /* EPPI1 Lines Per Frame Register */
-#define pREG_EPPI1_LINE                  ((volatile uint32_t *)REG_EPPI1_LINE)                   /* EPPI1 Samples Per Line Register */
-#define pREG_EPPI1_CLKDIV                ((volatile uint32_t *)REG_EPPI1_CLKDIV)                 /* EPPI1 Clock Divide Register */
-#define pREG_EPPI1_CTL                   ((volatile uint32_t *)REG_EPPI1_CTL)                    /* EPPI1 Control Register */
-#define pREG_EPPI1_FS1_WLHB              ((volatile uint32_t *)REG_EPPI1_FS1_WLHB)               /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI1_FS1_PASPL             ((volatile uint32_t *)REG_EPPI1_FS1_PASPL)              /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI1_FS2_WLVB              ((volatile uint32_t *)REG_EPPI1_FS2_WLVB)               /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI1_FS2_PALPF             ((volatile uint32_t *)REG_EPPI1_FS2_PALPF)              /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI1_IMSK                  ((volatile uint32_t *)REG_EPPI1_IMSK)                   /* EPPI1 Interrupt Mask Register */
-#define pREG_EPPI1_ODDCLIP               ((volatile uint32_t *)REG_EPPI1_ODDCLIP)                /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI1_EVENCLIP              ((volatile uint32_t *)REG_EPPI1_EVENCLIP)               /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI1_FS1_DLY               ((volatile uint32_t *)REG_EPPI1_FS1_DLY)                /* EPPI1 Frame Sync 1 Delay Value */
-#define pREG_EPPI1_FS2_DLY               ((volatile uint32_t *)REG_EPPI1_FS2_DLY)                /* EPPI1 Frame Sync 2 Delay Value */
-#define pREG_EPPI1_CTL2                  ((volatile uint32_t *)REG_EPPI1_CTL2)                   /* EPPI1 Control Register 2 */
-
-/* =========================================================================
-       EPPI2
-   ========================================================================= */
-#define pREG_EPPI2_STAT                  ((volatile uint32_t *)REG_EPPI2_STAT)                   /* EPPI2 Status Register */
-#define pREG_EPPI2_HCNT                  ((volatile uint32_t *)REG_EPPI2_HCNT)                   /* EPPI2 Horizontal Transfer Count Register */
-#define pREG_EPPI2_HDLY                  ((volatile uint32_t *)REG_EPPI2_HDLY)                   /* EPPI2 Horizontal Delay Count Register */
-#define pREG_EPPI2_VCNT                  ((volatile uint32_t *)REG_EPPI2_VCNT)                   /* EPPI2 Vertical Transfer Count Register */
-#define pREG_EPPI2_VDLY                  ((volatile uint32_t *)REG_EPPI2_VDLY)                   /* EPPI2 Vertical Delay Count Register */
-#define pREG_EPPI2_FRAME                 ((volatile uint32_t *)REG_EPPI2_FRAME)                  /* EPPI2 Lines Per Frame Register */
-#define pREG_EPPI2_LINE                  ((volatile uint32_t *)REG_EPPI2_LINE)                   /* EPPI2 Samples Per Line Register */
-#define pREG_EPPI2_CLKDIV                ((volatile uint32_t *)REG_EPPI2_CLKDIV)                 /* EPPI2 Clock Divide Register */
-#define pREG_EPPI2_CTL                   ((volatile uint32_t *)REG_EPPI2_CTL)                    /* EPPI2 Control Register */
-#define pREG_EPPI2_FS1_WLHB              ((volatile uint32_t *)REG_EPPI2_FS1_WLHB)               /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define pREG_EPPI2_FS1_PASPL             ((volatile uint32_t *)REG_EPPI2_FS1_PASPL)              /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define pREG_EPPI2_FS2_WLVB              ((volatile uint32_t *)REG_EPPI2_FS2_WLVB)               /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define pREG_EPPI2_FS2_PALPF             ((volatile uint32_t *)REG_EPPI2_FS2_PALPF)              /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define pREG_EPPI2_IMSK                  ((volatile uint32_t *)REG_EPPI2_IMSK)                   /* EPPI2 Interrupt Mask Register */
-#define pREG_EPPI2_ODDCLIP               ((volatile uint32_t *)REG_EPPI2_ODDCLIP)                /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define pREG_EPPI2_EVENCLIP              ((volatile uint32_t *)REG_EPPI2_EVENCLIP)               /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define pREG_EPPI2_FS1_DLY               ((volatile uint32_t *)REG_EPPI2_FS1_DLY)                /* EPPI2 Frame Sync 1 Delay Value */
-#define pREG_EPPI2_FS2_DLY               ((volatile uint32_t *)REG_EPPI2_FS2_DLY)                /* EPPI2 Frame Sync 2 Delay Value */
-#define pREG_EPPI2_CTL2                  ((volatile uint32_t *)REG_EPPI2_CTL2)                   /* EPPI2 Control Register 2 */
-
-
-/* =========================================================================
-       PIXC0
-   ========================================================================= */
-#define pREG_PIXC0_CTL                   ((volatile uint32_t *)REG_PIXC0_CTL)                    /* PIXC0 Control Register */
-#define pREG_PIXC0_PPL                   ((volatile uint16_t *)REG_PIXC0_PPL)                    /* PIXC0 Pixels Per Line Register */
-#define pREG_PIXC0_LPF                   ((volatile uint16_t *)REG_PIXC0_LPF)                    /* PIXC0 Line Per Frame Register */
-#define pREG_PIXC0_HSTART_A              ((volatile uint16_t *)REG_PIXC0_HSTART_A)               /* PIXC0 Overlay A Horizontal Start Register */
-#define pREG_PIXC0_HEND_A                ((volatile uint16_t *)REG_PIXC0_HEND_A)                 /* PIXC0 Overlay A Horizontal End Register */
-#define pREG_PIXC0_VSTART_A              ((volatile uint16_t *)REG_PIXC0_VSTART_A)               /* PIXC0 Overlay A Vertical Start Register */
-#define pREG_PIXC0_VEND_A                ((volatile uint16_t *)REG_PIXC0_VEND_A)                 /* PIXC0 Overlay A Vertical End Register */
-#define pREG_PIXC0_TRANSP_A              ((volatile uint16_t *)REG_PIXC0_TRANSP_A)               /* PIXC0 Overlay A Transparency Ratio Register */
-#define pREG_PIXC0_HSTART_B              ((volatile uint16_t *)REG_PIXC0_HSTART_B)               /* PIXC0 Overlay B Horizontal Start Register */
-#define pREG_PIXC0_HEND_B                ((volatile uint16_t *)REG_PIXC0_HEND_B)                 /* PIXC0 Overlay B Horizontal End Register */
-#define pREG_PIXC0_VSTART_B              ((volatile uint16_t *)REG_PIXC0_VSTART_B)               /* PIXC0 Overlay B Vertical Start Register */
-#define pREG_PIXC0_VEND_B                ((volatile uint16_t *)REG_PIXC0_VEND_B)                 /* PIXC0 Overlay B Vertical End Register */
-#define pREG_PIXC0_TRANSP_B              ((volatile uint16_t *)REG_PIXC0_TRANSP_B)               /* PIXC0 Overlay B Transparency Ratio Register */
-#define pREG_PIXC0_IRQSTAT               ((volatile uint16_t *)REG_PIXC0_IRQSTAT)                /* PIXC0 Interrupt Status Register */
-#define pREG_PIXC0_CONRY                 ((volatile uint32_t *)REG_PIXC0_CONRY)                  /* PIXC0 RY Conversion Component Register */
-#define pREG_PIXC0_CONGU                 ((volatile uint32_t *)REG_PIXC0_CONGU)                  /* PIXC0 GU Conversion Component Register */
-#define pREG_PIXC0_CONBV                 ((volatile uint32_t *)REG_PIXC0_CONBV)                  /* PIXC0 BV Conversion Component Register */
-#define pREG_PIXC0_CCBIAS                ((volatile uint32_t *)REG_PIXC0_CCBIAS)                 /* PIXC0 Conversion Bias Register */
-#define pREG_PIXC0_TC                    ((volatile uint32_t *)REG_PIXC0_TC)                     /* PIXC0 Transparency Color Register */
-#define pREG_PIXC0_REVID                 ((volatile uint32_t *)REG_PIXC0_REVID)                  /* PIXC0 Revision Id */
-
-
-/* =========================================================================
-       PVP0
-   ========================================================================= */
-#define pREG_PVP0_REVID                  ((volatile uint32_t *)REG_PVP0_REVID)                   /* PVP0 Revision ID */
-#define pREG_PVP0_CTL                    ((volatile uint32_t *)REG_PVP0_CTL)                     /* PVP0 Control */
-#define pREG_PVP0_IMSK0                  ((volatile uint32_t *)REG_PVP0_IMSK0)                   /* PVP0 Interrupt Mask n */
-#define pREG_PVP0_IMSK1                  ((volatile uint32_t *)REG_PVP0_IMSK1)                   /* PVP0 Interrupt Mask n */
-#define pREG_PVP0_STAT                   ((volatile uint32_t *)REG_PVP0_STAT)                    /* PVP0 Status */
-#define pREG_PVP0_ILAT                   ((volatile uint32_t *)REG_PVP0_ILAT)                    /* PVP0 Interrupt Latch Status n */
-#define pREG_PVP0_IREQ0                  ((volatile uint32_t *)REG_PVP0_IREQ0)                   /* PVP0 Interrupt Request n */
-#define pREG_PVP0_IREQ1                  ((volatile uint32_t *)REG_PVP0_IREQ1)                   /* PVP0 Interrupt Request n */
-#define pREG_PVP0_OPF0_CFG               ((volatile uint32_t *)REG_PVP0_OPF0_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF1_CFG               ((volatile uint32_t *)REG_PVP0_OPF1_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF2_CFG               ((volatile uint32_t *)REG_PVP0_OPF2_CFG)                /* PVP0 OPFn (Camera Pipe) Configuration */
-#define pREG_PVP0_OPF0_CTL               ((volatile uint32_t *)REG_PVP0_OPF0_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF1_CTL               ((volatile uint32_t *)REG_PVP0_OPF1_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF2_CTL               ((volatile uint32_t *)REG_PVP0_OPF2_CTL)                /* PVP0 OPFn (Camera Pipe) Control */
-#define pREG_PVP0_OPF3_CFG               ((volatile uint32_t *)REG_PVP0_OPF3_CFG)                /* PVP0 OPF3 (Memory Pipe) Configuration */
-#define pREG_PVP0_OPF3_CTL               ((volatile uint32_t *)REG_PVP0_OPF3_CTL)                /* PVP0 OPF3 (Memory Pipe) Control */
-#define pREG_PVP0_PEC_CFG                ((volatile uint32_t *)REG_PVP0_PEC_CFG)                 /* PVP0 PEC Configuration */
-#define pREG_PVP0_PEC_CTL                ((volatile uint32_t *)REG_PVP0_PEC_CTL)                 /* PVP0 PEC Control */
-#define pREG_PVP0_PEC_D1TH0              ((volatile uint32_t *)REG_PVP0_PEC_D1TH0)               /* PVP0 PEC Lower Hysteresis Threshold */
-#define pREG_PVP0_PEC_D1TH1              ((volatile uint32_t *)REG_PVP0_PEC_D1TH1)               /* PVP0 PEC Upper Hysteresis Threshold */
-#define pREG_PVP0_PEC_D2TH0              ((volatile uint32_t *)REG_PVP0_PEC_D2TH0)               /* PVP0 PEC Weak Zero Crossing Threshold */
-#define pREG_PVP0_PEC_D2TH1              ((volatile uint32_t *)REG_PVP0_PEC_D2TH1)               /* PVP0 PEC Strong Zero Crossing Threshold */
-#define pREG_PVP0_IIM0_CFG               ((volatile uint32_t *)REG_PVP0_IIM0_CFG)                /* PVP0 IIMn Configuration */
-#define pREG_PVP0_IIM1_CFG               ((volatile uint32_t *)REG_PVP0_IIM1_CFG)                /* PVP0 IIMn Configuration */
-#define pREG_PVP0_IIM0_CTL               ((volatile uint32_t *)REG_PVP0_IIM0_CTL)                /* PVP0 IIMn Control */
-#define pREG_PVP0_IIM1_CTL               ((volatile uint32_t *)REG_PVP0_IIM1_CTL)                /* PVP0 IIMn Control */
-#define pREG_PVP0_IIM0_SCALE             ((volatile uint32_t *)REG_PVP0_IIM0_SCALE)              /* PVP0 IIMn Scaling Values */
-#define pREG_PVP0_IIM1_SCALE             ((volatile uint32_t *)REG_PVP0_IIM1_SCALE)              /* PVP0 IIMn Scaling Values */
-#define pREG_PVP0_IIM0_SOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM0_SOVF_STAT)          /* PVP0 IIMn Signed Overflow Status */
-#define pREG_PVP0_IIM1_SOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM1_SOVF_STAT)          /* PVP0 IIMn Signed Overflow Status */
-#define pREG_PVP0_IIM0_UOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM0_UOVF_STAT)          /* PVP0 IIMn Unsigned Overflow Status */
-#define pREG_PVP0_IIM1_UOVF_STAT         ((volatile uint32_t *)REG_PVP0_IIM1_UOVF_STAT)          /* PVP0 IIMn Unsigned Overflow Status */
-#define pREG_PVP0_ACU_CFG                ((volatile uint32_t *)REG_PVP0_ACU_CFG)                 /* PVP0 ACU Configuration */
-#define pREG_PVP0_ACU_CTL                ((volatile uint32_t *)REG_PVP0_ACU_CTL)                 /* PVP0 ACU Control */
-#define pREG_PVP0_ACU_OFFSET             ((volatile uint32_t *)REG_PVP0_ACU_OFFSET)              /* PVP0 ACU SUM Constant */
-#define pREG_PVP0_ACU_FACTOR             ((volatile uint32_t *)REG_PVP0_ACU_FACTOR)              /* PVP0 ACU PROD Constant */
-#define pREG_PVP0_ACU_SHIFT              ((volatile uint32_t *)REG_PVP0_ACU_SHIFT)               /* PVP0 ACU Shift Constant */
-#define pREG_PVP0_ACU_MIN                ((volatile uint32_t *)REG_PVP0_ACU_MIN)                 /* PVP0 ACU Lower Sat Threshold Min */
-#define pREG_PVP0_ACU_MAX                ((volatile uint32_t *)REG_PVP0_ACU_MAX)                 /* PVP0 ACU Upper Sat Threshold Max */
-#define pREG_PVP0_UDS_CFG                ((volatile uint32_t *)REG_PVP0_UDS_CFG)                 /* PVP0 UDS Configuration */
-#define pREG_PVP0_UDS_CTL                ((volatile uint32_t *)REG_PVP0_UDS_CTL)                 /* PVP0 UDS Control */
-#define pREG_PVP0_UDS_OHCNT              ((volatile uint32_t *)REG_PVP0_UDS_OHCNT)               /* PVP0 UDS Output HCNT */
-#define pREG_PVP0_UDS_OVCNT              ((volatile uint32_t *)REG_PVP0_UDS_OVCNT)               /* PVP0 UDS Output VCNT */
-#define pREG_PVP0_UDS_HAVG               ((volatile uint32_t *)REG_PVP0_UDS_HAVG)                /* PVP0 UDS HAVG */
-#define pREG_PVP0_UDS_VAVG               ((volatile uint32_t *)REG_PVP0_UDS_VAVG)                /* PVP0 UDS VAVG */
-#define pREG_PVP0_IPF0_CFG               ((volatile uint32_t *)REG_PVP0_IPF0_CFG)                /* PVP0 IPF0 (Camera Pipe) Configuration */
-#define pREG_PVP0_IPF0_PIPECTL           ((volatile uint32_t *)REG_PVP0_IPF0_PIPECTL)            /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define pREG_PVP0_IPF1_PIPECTL           ((volatile uint32_t *)REG_PVP0_IPF1_PIPECTL)            /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define pREG_PVP0_IPF0_CTL               ((volatile uint32_t *)REG_PVP0_IPF0_CTL)                /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define pREG_PVP0_IPF1_CTL               ((volatile uint32_t *)REG_PVP0_IPF1_CTL)                /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define pREG_PVP0_IPF0_TAG               ((volatile uint32_t *)REG_PVP0_IPF0_TAG)                /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define pREG_PVP0_IPF1_TAG               ((volatile uint32_t *)REG_PVP0_IPF1_TAG)                /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define pREG_PVP0_IPF0_FCNT              ((volatile uint32_t *)REG_PVP0_IPF0_FCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define pREG_PVP0_IPF1_FCNT              ((volatile uint32_t *)REG_PVP0_IPF1_FCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define pREG_PVP0_IPF0_HCNT              ((volatile uint32_t *)REG_PVP0_IPF0_HCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define pREG_PVP0_IPF1_HCNT              ((volatile uint32_t *)REG_PVP0_IPF1_HCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define pREG_PVP0_IPF0_VCNT              ((volatile uint32_t *)REG_PVP0_IPF0_VCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define pREG_PVP0_IPF1_VCNT              ((volatile uint32_t *)REG_PVP0_IPF1_VCNT)               /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define pREG_PVP0_IPF0_HPOS              ((volatile uint32_t *)REG_PVP0_IPF0_HPOS)               /* PVP0 IPF0 (Camera Pipe) Horizontal Position */
-#define pREG_PVP0_IPF0_VPOS              ((volatile uint32_t *)REG_PVP0_IPF0_VPOS)               /* PVP0 IPF0 (Camera Pipe) Vertical Position */
-#define pREG_PVP0_IPF0_TAG_STAT          ((volatile uint32_t *)REG_PVP0_IPF0_TAG_STAT)           /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define pREG_PVP0_IPF1_TAG_STAT          ((volatile uint32_t *)REG_PVP0_IPF1_TAG_STAT)           /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define pREG_PVP0_IPF1_CFG               ((volatile uint32_t *)REG_PVP0_IPF1_CFG)                /* PVP0 IPF1 (Memory Pipe) Configuration */
-#define pREG_PVP0_CNV0_CFG               ((volatile uint32_t *)REG_PVP0_CNV0_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV1_CFG               ((volatile uint32_t *)REG_PVP0_CNV1_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV2_CFG               ((volatile uint32_t *)REG_PVP0_CNV2_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV3_CFG               ((volatile uint32_t *)REG_PVP0_CNV3_CFG)                /* PVP0 CNVn Configuration */
-#define pREG_PVP0_CNV0_CTL               ((volatile uint32_t *)REG_PVP0_CNV0_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV1_CTL               ((volatile uint32_t *)REG_PVP0_CNV1_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV2_CTL               ((volatile uint32_t *)REG_PVP0_CNV2_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV3_CTL               ((volatile uint32_t *)REG_PVP0_CNV3_CTL)                /* PVP0 CNVn Control */
-#define pREG_PVP0_CNV0_C00C01            ((volatile uint32_t *)REG_PVP0_CNV0_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV1_C00C01            ((volatile uint32_t *)REG_PVP0_CNV1_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV2_C00C01            ((volatile uint32_t *)REG_PVP0_CNV2_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV3_C00C01            ((volatile uint32_t *)REG_PVP0_CNV3_C00C01)             /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define pREG_PVP0_CNV0_C02C03            ((volatile uint32_t *)REG_PVP0_CNV0_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV1_C02C03            ((volatile uint32_t *)REG_PVP0_CNV1_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV2_C02C03            ((volatile uint32_t *)REG_PVP0_CNV2_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV3_C02C03            ((volatile uint32_t *)REG_PVP0_CNV3_C02C03)             /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define pREG_PVP0_CNV0_C04               ((volatile uint32_t *)REG_PVP0_CNV0_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV1_C04               ((volatile uint32_t *)REG_PVP0_CNV1_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV2_C04               ((volatile uint32_t *)REG_PVP0_CNV2_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV3_C04               ((volatile uint32_t *)REG_PVP0_CNV3_C04)                /* PVP0 CNVn Coefficient 0,4 */
-#define pREG_PVP0_CNV0_C10C11            ((volatile uint32_t *)REG_PVP0_CNV0_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV1_C10C11            ((volatile uint32_t *)REG_PVP0_CNV1_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV2_C10C11            ((volatile uint32_t *)REG_PVP0_CNV2_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV3_C10C11            ((volatile uint32_t *)REG_PVP0_CNV3_C10C11)             /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define pREG_PVP0_CNV0_C12C13            ((volatile uint32_t *)REG_PVP0_CNV0_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV1_C12C13            ((volatile uint32_t *)REG_PVP0_CNV1_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV2_C12C13            ((volatile uint32_t *)REG_PVP0_CNV2_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV3_C12C13            ((volatile uint32_t *)REG_PVP0_CNV3_C12C13)             /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define pREG_PVP0_CNV0_C14               ((volatile uint32_t *)REG_PVP0_CNV0_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV1_C14               ((volatile uint32_t *)REG_PVP0_CNV1_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV2_C14               ((volatile uint32_t *)REG_PVP0_CNV2_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV3_C14               ((volatile uint32_t *)REG_PVP0_CNV3_C14)                /* PVP0 CNVn Coefficient 1,4 */
-#define pREG_PVP0_CNV0_C20C21            ((volatile uint32_t *)REG_PVP0_CNV0_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV1_C20C21            ((volatile uint32_t *)REG_PVP0_CNV1_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV2_C20C21            ((volatile uint32_t *)REG_PVP0_CNV2_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV3_C20C21            ((volatile uint32_t *)REG_PVP0_CNV3_C20C21)             /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define pREG_PVP0_CNV0_C22C23            ((volatile uint32_t *)REG_PVP0_CNV0_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV1_C22C23            ((volatile uint32_t *)REG_PVP0_CNV1_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV2_C22C23            ((volatile uint32_t *)REG_PVP0_CNV2_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV3_C22C23            ((volatile uint32_t *)REG_PVP0_CNV3_C22C23)             /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define pREG_PVP0_CNV0_C24               ((volatile uint32_t *)REG_PVP0_CNV0_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV1_C24               ((volatile uint32_t *)REG_PVP0_CNV1_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV2_C24               ((volatile uint32_t *)REG_PVP0_CNV2_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV3_C24               ((volatile uint32_t *)REG_PVP0_CNV3_C24)                /* PVP0 CNVn Coefficient 2,4 */
-#define pREG_PVP0_CNV0_C30C31            ((volatile uint32_t *)REG_PVP0_CNV0_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV1_C30C31            ((volatile uint32_t *)REG_PVP0_CNV1_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV2_C30C31            ((volatile uint32_t *)REG_PVP0_CNV2_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV3_C30C31            ((volatile uint32_t *)REG_PVP0_CNV3_C30C31)             /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define pREG_PVP0_CNV0_C32C33            ((volatile uint32_t *)REG_PVP0_CNV0_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV1_C32C33            ((volatile uint32_t *)REG_PVP0_CNV1_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV2_C32C33            ((volatile uint32_t *)REG_PVP0_CNV2_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV3_C32C33            ((volatile uint32_t *)REG_PVP0_CNV3_C32C33)             /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define pREG_PVP0_CNV0_C34               ((volatile uint32_t *)REG_PVP0_CNV0_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV1_C34               ((volatile uint32_t *)REG_PVP0_CNV1_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV2_C34               ((volatile uint32_t *)REG_PVP0_CNV2_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV3_C34               ((volatile uint32_t *)REG_PVP0_CNV3_C34)                /* PVP0 CNVn Coefficient 3,4 */
-#define pREG_PVP0_CNV0_C40C41            ((volatile uint32_t *)REG_PVP0_CNV0_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV1_C40C41            ((volatile uint32_t *)REG_PVP0_CNV1_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV2_C40C41            ((volatile uint32_t *)REG_PVP0_CNV2_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV3_C40C41            ((volatile uint32_t *)REG_PVP0_CNV3_C40C41)             /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define pREG_PVP0_CNV0_C42C43            ((volatile uint32_t *)REG_PVP0_CNV0_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV1_C42C43            ((volatile uint32_t *)REG_PVP0_CNV1_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV2_C42C43            ((volatile uint32_t *)REG_PVP0_CNV2_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV3_C42C43            ((volatile uint32_t *)REG_PVP0_CNV3_C42C43)             /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define pREG_PVP0_CNV0_C44               ((volatile uint32_t *)REG_PVP0_CNV0_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV1_C44               ((volatile uint32_t *)REG_PVP0_CNV1_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV2_C44               ((volatile uint32_t *)REG_PVP0_CNV2_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV3_C44               ((volatile uint32_t *)REG_PVP0_CNV3_C44)                /* PVP0 CNVn Coefficient 4,4 */
-#define pREG_PVP0_CNV0_SCALE             ((volatile uint32_t *)REG_PVP0_CNV0_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV1_SCALE             ((volatile uint32_t *)REG_PVP0_CNV1_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV2_SCALE             ((volatile uint32_t *)REG_PVP0_CNV2_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_CNV3_SCALE             ((volatile uint32_t *)REG_PVP0_CNV3_SCALE)              /* PVP0 CNVn Scaling Factor */
-#define pREG_PVP0_THC0_CFG               ((volatile uint32_t *)REG_PVP0_THC0_CFG)                /* PVP0 THCn Configuration */
-#define pREG_PVP0_THC1_CFG               ((volatile uint32_t *)REG_PVP0_THC1_CFG)                /* PVP0 THCn Configuration */
-#define pREG_PVP0_THC0_CTL               ((volatile uint32_t *)REG_PVP0_THC0_CTL)                /* PVP0 THCn Control */
-#define pREG_PVP0_THC1_CTL               ((volatile uint32_t *)REG_PVP0_THC1_CTL)                /* PVP0 THCn Control */
-#define pREG_PVP0_THC0_HFCNT             ((volatile uint32_t *)REG_PVP0_THC0_HFCNT)              /* PVP0 THCn Histogram Frame Count */
-#define pREG_PVP0_THC1_HFCNT             ((volatile uint32_t *)REG_PVP0_THC1_HFCNT)              /* PVP0 THCn Histogram Frame Count */
-#define pREG_PVP0_THC0_RMAXREP           ((volatile uint32_t *)REG_PVP0_THC0_RMAXREP)            /* PVP0 THCn Max RLE Reports */
-#define pREG_PVP0_THC1_RMAXREP           ((volatile uint32_t *)REG_PVP0_THC1_RMAXREP)            /* PVP0 THCn Max RLE Reports */
-#define pREG_PVP0_THC0_CMINVAL           ((volatile  int32_t *)REG_PVP0_THC0_CMINVAL)            /* PVP0 THCn Min Clip Value */
-#define pREG_PVP0_THC1_CMINVAL           ((volatile  int32_t *)REG_PVP0_THC1_CMINVAL)            /* PVP0 THCn Min Clip Value */
-#define pREG_PVP0_THC0_CMINTH            ((volatile  int32_t *)REG_PVP0_THC0_CMINTH)             /* PVP0 THCn Clip Min Threshold */
-#define pREG_PVP0_THC1_CMINTH            ((volatile  int32_t *)REG_PVP0_THC1_CMINTH)             /* PVP0 THCn Clip Min Threshold */
-#define pREG_PVP0_THC0_CMAXTH            ((volatile  int32_t *)REG_PVP0_THC0_CMAXTH)             /* PVP0 THCn Clip Max Threshold */
-#define pREG_PVP0_THC1_CMAXTH            ((volatile  int32_t *)REG_PVP0_THC1_CMAXTH)             /* PVP0 THCn Clip Max Threshold */
-#define pREG_PVP0_THC0_CMAXVAL           ((volatile  int32_t *)REG_PVP0_THC0_CMAXVAL)            /* PVP0 THCn Max Clip Value */
-#define pREG_PVP0_THC1_CMAXVAL           ((volatile  int32_t *)REG_PVP0_THC1_CMAXVAL)            /* PVP0 THCn Max Clip Value */
-#define pREG_PVP0_THC0_TH0               ((volatile  int32_t *)REG_PVP0_THC0_TH0)                /* PVP0 THCn Threshold Value 0 */
-#define pREG_PVP0_THC1_TH0               ((volatile  int32_t *)REG_PVP0_THC1_TH0)                /* PVP0 THCn Threshold Value 0 */
-#define pREG_PVP0_THC0_TH1               ((volatile  int32_t *)REG_PVP0_THC0_TH1)                /* PVP0 THCn Threshold Value 1 */
-#define pREG_PVP0_THC1_TH1               ((volatile  int32_t *)REG_PVP0_THC1_TH1)                /* PVP0 THCn Threshold Value 1 */
-#define pREG_PVP0_THC0_TH2               ((volatile  int32_t *)REG_PVP0_THC0_TH2)                /* PVP0 THCn Threshold Value 2 */
-#define pREG_PVP0_THC1_TH2               ((volatile  int32_t *)REG_PVP0_THC1_TH2)                /* PVP0 THCn Threshold Value 2 */
-#define pREG_PVP0_THC0_TH3               ((volatile  int32_t *)REG_PVP0_THC0_TH3)                /* PVP0 THCn Threshold Value 3 */
-#define pREG_PVP0_THC1_TH3               ((volatile  int32_t *)REG_PVP0_THC1_TH3)                /* PVP0 THCn Threshold Value 3 */
-#define pREG_PVP0_THC0_TH4               ((volatile  int32_t *)REG_PVP0_THC0_TH4)                /* PVP0 THCn Threshold Value 4 */
-#define pREG_PVP0_THC1_TH4               ((volatile  int32_t *)REG_PVP0_THC1_TH4)                /* PVP0 THCn Threshold Value 4 */
-#define pREG_PVP0_THC0_TH5               ((volatile  int32_t *)REG_PVP0_THC0_TH5)                /* PVP0 THCn Threshold Value 5 */
-#define pREG_PVP0_THC1_TH5               ((volatile  int32_t *)REG_PVP0_THC1_TH5)                /* PVP0 THCn Threshold Value 5 */
-#define pREG_PVP0_THC0_TH6               ((volatile  int32_t *)REG_PVP0_THC0_TH6)                /* PVP0 THCn Threshold Value 6 */
-#define pREG_PVP0_THC1_TH6               ((volatile  int32_t *)REG_PVP0_THC1_TH6)                /* PVP0 THCn Threshold Value 6 */
-#define pREG_PVP0_THC0_TH7               ((volatile  int32_t *)REG_PVP0_THC0_TH7)                /* PVP0 THCn Threshold Value 7 */
-#define pREG_PVP0_THC1_TH7               ((volatile  int32_t *)REG_PVP0_THC1_TH7)                /* PVP0 THCn Threshold Value 7 */
-#define pREG_PVP0_THC0_TH8               ((volatile  int32_t *)REG_PVP0_THC0_TH8)                /* PVP0 THCn Threshold Value 8 */
-#define pREG_PVP0_THC1_TH8               ((volatile  int32_t *)REG_PVP0_THC1_TH8)                /* PVP0 THCn Threshold Value 8 */
-#define pREG_PVP0_THC0_TH9               ((volatile  int32_t *)REG_PVP0_THC0_TH9)                /* PVP0 THCn Threshold Value 9 */
-#define pREG_PVP0_THC1_TH9               ((volatile  int32_t *)REG_PVP0_THC1_TH9)                /* PVP0 THCn Threshold Value 9 */
-#define pREG_PVP0_THC0_TH10              ((volatile  int32_t *)REG_PVP0_THC0_TH10)               /* PVP0 THCn Threshold Value 10 */
-#define pREG_PVP0_THC1_TH10              ((volatile  int32_t *)REG_PVP0_THC1_TH10)               /* PVP0 THCn Threshold Value 10 */
-#define pREG_PVP0_THC0_TH11              ((volatile  int32_t *)REG_PVP0_THC0_TH11)               /* PVP0 THCn Threshold Value 11 */
-#define pREG_PVP0_THC1_TH11              ((volatile  int32_t *)REG_PVP0_THC1_TH11)               /* PVP0 THCn Threshold Value 11 */
-#define pREG_PVP0_THC0_TH12              ((volatile  int32_t *)REG_PVP0_THC0_TH12)               /* PVP0 THCn Threshold Value 12 */
-#define pREG_PVP0_THC1_TH12              ((volatile  int32_t *)REG_PVP0_THC1_TH12)               /* PVP0 THCn Threshold Value 12 */
-#define pREG_PVP0_THC0_TH13              ((volatile  int32_t *)REG_PVP0_THC0_TH13)               /* PVP0 THCn Threshold Value 13 */
-#define pREG_PVP0_THC1_TH13              ((volatile  int32_t *)REG_PVP0_THC1_TH13)               /* PVP0 THCn Threshold Value 13 */
-#define pREG_PVP0_THC0_TH14              ((volatile  int32_t *)REG_PVP0_THC0_TH14)               /* PVP0 THCn Threshold Value 14 */
-#define pREG_PVP0_THC1_TH14              ((volatile  int32_t *)REG_PVP0_THC1_TH14)               /* PVP0 THCn Threshold Value 14 */
-#define pREG_PVP0_THC0_TH15              ((volatile  int32_t *)REG_PVP0_THC0_TH15)               /* PVP0 THCn Threshold Value 15 */
-#define pREG_PVP0_THC1_TH15              ((volatile  int32_t *)REG_PVP0_THC1_TH15)               /* PVP0 THCn Threshold Value 15 */
-#define pREG_PVP0_THC0_HHPOS             ((volatile uint32_t *)REG_PVP0_THC0_HHPOS)              /* PVP0 THCn Histogram Horzontal Position */
-#define pREG_PVP0_THC1_HHPOS             ((volatile uint32_t *)REG_PVP0_THC1_HHPOS)              /* PVP0 THCn Histogram Horzontal Position */
-#define pREG_PVP0_THC0_HVPOS             ((volatile uint32_t *)REG_PVP0_THC0_HVPOS)              /* PVP0 THCn Histogram Vertical Position */
-#define pREG_PVP0_THC1_HVPOS             ((volatile uint32_t *)REG_PVP0_THC1_HVPOS)              /* PVP0 THCn Histogram Vertical Position */
-#define pREG_PVP0_THC0_HHCNT             ((volatile uint32_t *)REG_PVP0_THC0_HHCNT)              /* PVP0 THCn Histogram Horizontal Count */
-#define pREG_PVP0_THC1_HHCNT             ((volatile uint32_t *)REG_PVP0_THC1_HHCNT)              /* PVP0 THCn Histogram Horizontal Count */
-#define pREG_PVP0_THC0_HVCNT             ((volatile uint32_t *)REG_PVP0_THC0_HVCNT)              /* PVP0 THCn Histogram Vertical Count */
-#define pREG_PVP0_THC1_HVCNT             ((volatile uint32_t *)REG_PVP0_THC1_HVCNT)              /* PVP0 THCn Histogram Vertical Count */
-#define pREG_PVP0_THC0_RHPOS             ((volatile uint32_t *)REG_PVP0_THC0_RHPOS)              /* PVP0 THCn RLE Horizontal Position */
-#define pREG_PVP0_THC1_RHPOS             ((volatile uint32_t *)REG_PVP0_THC1_RHPOS)              /* PVP0 THCn RLE Horizontal Position */
-#define pREG_PVP0_THC0_RVPOS             ((volatile uint32_t *)REG_PVP0_THC0_RVPOS)              /* PVP0 THCn RLE Vertical Position */
-#define pREG_PVP0_THC1_RVPOS             ((volatile uint32_t *)REG_PVP0_THC1_RVPOS)              /* PVP0 THCn RLE Vertical Position */
-#define pREG_PVP0_THC0_RHCNT             ((volatile uint32_t *)REG_PVP0_THC0_RHCNT)              /* PVP0 THCn RLE Horizontal Count */
-#define pREG_PVP0_THC1_RHCNT             ((volatile uint32_t *)REG_PVP0_THC1_RHCNT)              /* PVP0 THCn RLE Horizontal Count */
-#define pREG_PVP0_THC0_RVCNT             ((volatile uint32_t *)REG_PVP0_THC0_RVCNT)              /* PVP0 THCn RLE Vertical Count */
-#define pREG_PVP0_THC1_RVCNT             ((volatile uint32_t *)REG_PVP0_THC1_RVCNT)              /* PVP0 THCn RLE Vertical Count */
-#define pREG_PVP0_THC0_HFCNT_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HFCNT_STAT)         /* PVP0 THCn Histogram Frame Count Status */
-#define pREG_PVP0_THC1_HFCNT_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HFCNT_STAT)         /* PVP0 THCn Histogram Frame Count Status */
-#define pREG_PVP0_THC0_HCNT0_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT0_STAT)         /* PVP0 THCn Histogram Counter Value 0 */
-#define pREG_PVP0_THC1_HCNT0_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT0_STAT)         /* PVP0 THCn Histogram Counter Value 0 */
-#define pREG_PVP0_THC0_HCNT1_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT1_STAT)         /* PVP0 THCn Histogram Counter Value 1 */
-#define pREG_PVP0_THC1_HCNT1_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT1_STAT)         /* PVP0 THCn Histogram Counter Value 1 */
-#define pREG_PVP0_THC0_HCNT2_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT2_STAT)         /* PVP0 THCn Histogram Counter Value 2 */
-#define pREG_PVP0_THC1_HCNT2_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT2_STAT)         /* PVP0 THCn Histogram Counter Value 2 */
-#define pREG_PVP0_THC0_HCNT3_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT3_STAT)         /* PVP0 THCn Histogram Counter Value 3 */
-#define pREG_PVP0_THC1_HCNT3_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT3_STAT)         /* PVP0 THCn Histogram Counter Value 3 */
-#define pREG_PVP0_THC0_HCNT4_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT4_STAT)         /* PVP0 THCn Histogram Counter Value 4 */
-#define pREG_PVP0_THC1_HCNT4_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT4_STAT)         /* PVP0 THCn Histogram Counter Value 4 */
-#define pREG_PVP0_THC0_HCNT5_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT5_STAT)         /* PVP0 THCn Histogram Counter Value 5 */
-#define pREG_PVP0_THC1_HCNT5_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT5_STAT)         /* PVP0 THCn Histogram Counter Value 5 */
-#define pREG_PVP0_THC0_HCNT6_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT6_STAT)         /* PVP0 THCn Histogram Counter Value 6 */
-#define pREG_PVP0_THC1_HCNT6_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT6_STAT)         /* PVP0 THCn Histogram Counter Value 6 */
-#define pREG_PVP0_THC0_HCNT7_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT7_STAT)         /* PVP0 THCn Histogram Counter Value 7 */
-#define pREG_PVP0_THC1_HCNT7_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT7_STAT)         /* PVP0 THCn Histogram Counter Value 7 */
-#define pREG_PVP0_THC0_HCNT8_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT8_STAT)         /* PVP0 THCn Histogram Counter Value 8 */
-#define pREG_PVP0_THC1_HCNT8_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT8_STAT)         /* PVP0 THCn Histogram Counter Value 8 */
-#define pREG_PVP0_THC0_HCNT9_STAT        ((volatile uint32_t *)REG_PVP0_THC0_HCNT9_STAT)         /* PVP0 THCn Histogram Counter Value 9 */
-#define pREG_PVP0_THC1_HCNT9_STAT        ((volatile uint32_t *)REG_PVP0_THC1_HCNT9_STAT)         /* PVP0 THCn Histogram Counter Value 9 */
-#define pREG_PVP0_THC0_HCNT10_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT10_STAT)        /* PVP0 THCn Histogram Counter Value 10 */
-#define pREG_PVP0_THC1_HCNT10_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT10_STAT)        /* PVP0 THCn Histogram Counter Value 10 */
-#define pREG_PVP0_THC0_HCNT11_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT11_STAT)        /* PVP0 THCn Histogram Counter Value 11 */
-#define pREG_PVP0_THC1_HCNT11_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT11_STAT)        /* PVP0 THCn Histogram Counter Value 11 */
-#define pREG_PVP0_THC0_HCNT12_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT12_STAT)        /* PVP0 THCn Histogram Counter Value 12 */
-#define pREG_PVP0_THC1_HCNT12_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT12_STAT)        /* PVP0 THCn Histogram Counter Value 12 */
-#define pREG_PVP0_THC0_HCNT13_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT13_STAT)        /* PVP0 THCn Histogram Counter Value 13 */
-#define pREG_PVP0_THC1_HCNT13_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT13_STAT)        /* PVP0 THCn Histogram Counter Value 13 */
-#define pREG_PVP0_THC0_HCNT14_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT14_STAT)        /* PVP0 THCn Histogram Counter Value 14 */
-#define pREG_PVP0_THC1_HCNT14_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT14_STAT)        /* PVP0 THCn Histogram Counter Value 14 */
-#define pREG_PVP0_THC0_HCNT15_STAT       ((volatile uint32_t *)REG_PVP0_THC0_HCNT15_STAT)        /* PVP0 THCn Histogram Counter Value 15 */
-#define pREG_PVP0_THC1_HCNT15_STAT       ((volatile uint32_t *)REG_PVP0_THC1_HCNT15_STAT)        /* PVP0 THCn Histogram Counter Value 15 */
-#define pREG_PVP0_THC0_RREP_STAT         ((volatile uint32_t *)REG_PVP0_THC0_RREP_STAT)          /* PVP0 THCn Number of RLE Reports */
-#define pREG_PVP0_THC1_RREP_STAT         ((volatile uint32_t *)REG_PVP0_THC1_RREP_STAT)          /* PVP0 THCn Number of RLE Reports */
-#define pREG_PVP0_PMA_CFG                ((volatile uint32_t *)REG_PVP0_PMA_CFG)                 /* PVP0 PMA Configuration */
-
-
-/* =========================================================================
-       PWM0
-   ========================================================================= */
-#define pREG_PWM0_CTL                    ((volatile uint32_t *)REG_PWM0_CTL)                     /* PWM0 Control Register */
-#define pREG_PWM0_CHANCFG                ((volatile uint32_t *)REG_PWM0_CHANCFG)                 /* PWM0 Channel Config Register */
-#define pREG_PWM0_TRIPCFG                ((volatile uint32_t *)REG_PWM0_TRIPCFG)                 /* PWM0 Trip Config Register */
-#define pREG_PWM0_STAT                   ((volatile uint32_t *)REG_PWM0_STAT)                    /* PWM0 Status Register */
-#define pREG_PWM0_IMSK                   ((volatile uint32_t *)REG_PWM0_IMSK)                    /* PWM0 Interrupt Mask Register */
-#define pREG_PWM0_ILAT                   ((volatile uint32_t *)REG_PWM0_ILAT)                    /* PWM0 Interrupt Latch Register */
-#define pREG_PWM0_CHOPCFG                ((volatile uint32_t *)REG_PWM0_CHOPCFG)                 /* PWM0 Chop Configuration Register */
-#define pREG_PWM0_DT                     ((volatile uint32_t *)REG_PWM0_DT)                      /* PWM0 Dead Time Register */
-#define pREG_PWM0_SYNC_WID               ((volatile uint32_t *)REG_PWM0_SYNC_WID)                /* PWM0 Sync Pulse Width Register */
-#define pREG_PWM0_TM0                    ((volatile uint32_t *)REG_PWM0_TM0)                     /* PWM0 Timer 0 Period Register */
-#define pREG_PWM0_TM1                    ((volatile uint32_t *)REG_PWM0_TM1)                     /* PWM0 Timer 1 Period Register */
-#define pREG_PWM0_TM2                    ((volatile uint32_t *)REG_PWM0_TM2)                     /* PWM0 Timer 2 Period Register */
-#define pREG_PWM0_TM3                    ((volatile uint32_t *)REG_PWM0_TM3)                     /* PWM0 Timer 3 Period Register */
-#define pREG_PWM0_TM4                    ((volatile uint32_t *)REG_PWM0_TM4)                     /* PWM0 Timer 4 Period Register */
-#define pREG_PWM0_DLYA                   ((volatile uint32_t *)REG_PWM0_DLYA)                    /* PWM0 Channel A Delay Register */
-#define pREG_PWM0_DLYB                   ((volatile uint32_t *)REG_PWM0_DLYB)                    /* PWM0 Channel B Delay Register */
-#define pREG_PWM0_DLYC                   ((volatile uint32_t *)REG_PWM0_DLYC)                    /* PWM0 Channel C Delay Register */
-#define pREG_PWM0_DLYD                   ((volatile uint32_t *)REG_PWM0_DLYD)                    /* PWM0 Channel D Delay Register */
-#define pREG_PWM0_ACTL                   ((volatile uint32_t *)REG_PWM0_ACTL)                    /* PWM0 Channel A Control Register */
-#define pREG_PWM0_AH0                    ((volatile uint32_t *)REG_PWM0_AH0)                     /* PWM0 Channel A-High Duty-0 Register */
-#define pREG_PWM0_AH1                    ((volatile uint32_t *)REG_PWM0_AH1)                     /* PWM0 Channel A-High Duty-1 Register */
-#define pREG_PWM0_AL0                    ((volatile uint32_t *)REG_PWM0_AL0)                     /* PWM0 Channel A-Low Duty-0 Register */
-#define pREG_PWM0_AL1                    ((volatile uint32_t *)REG_PWM0_AL1)                     /* PWM0 Channel A-Low Duty-1 Register */
-#define pREG_PWM0_BCTL                   ((volatile uint32_t *)REG_PWM0_BCTL)                    /* PWM0 Channel B Control Register */
-#define pREG_PWM0_BH0                    ((volatile uint32_t *)REG_PWM0_BH0)                     /* PWM0 Channel B-High Duty-0 Register */
-#define pREG_PWM0_BH1                    ((volatile uint32_t *)REG_PWM0_BH1)                     /* PWM0 Channel B-High Duty-1 Register */
-#define pREG_PWM0_BL0                    ((volatile uint32_t *)REG_PWM0_BL0)                     /* PWM0 Channel B-Low Duty-0 Register */
-#define pREG_PWM0_BL1                    ((volatile uint32_t *)REG_PWM0_BL1)                     /* PWM0 Channel B-Low Duty-1 Register */
-#define pREG_PWM0_CCTL                   ((volatile uint32_t *)REG_PWM0_CCTL)                    /* PWM0 Channel C Control Register */
-#define pREG_PWM0_CH0                    ((volatile uint32_t *)REG_PWM0_CH0)                     /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM0_CH1                    ((volatile uint32_t *)REG_PWM0_CH1)                     /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM0_CL0                    ((volatile uint32_t *)REG_PWM0_CL0)                     /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM0_CL1                    ((volatile uint32_t *)REG_PWM0_CL1)                     /* PWM0 Channel C-Low Duty-1 Register */
-#define pREG_PWM0_DCTL                   ((volatile uint32_t *)REG_PWM0_DCTL)                    /* PWM0 Channel D Control Register */
-#define pREG_PWM0_DH0                    ((volatile uint32_t *)REG_PWM0_DH0)                     /* PWM0 Channel D-High Duty-0 Register */
-#define pREG_PWM0_DH1                    ((volatile uint32_t *)REG_PWM0_DH1)                     /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM0_DL0                    ((volatile uint32_t *)REG_PWM0_DL0)                     /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM0_DL1                    ((volatile uint32_t *)REG_PWM0_DL1)                     /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================================================================
-       PWM1
-   ========================================================================= */
-#define pREG_PWM1_CTL                    ((volatile uint32_t *)REG_PWM1_CTL)                     /* PWM1 Control Register */
-#define pREG_PWM1_CHANCFG                ((volatile uint32_t *)REG_PWM1_CHANCFG)                 /* PWM1 Channel Config Register */
-#define pREG_PWM1_TRIPCFG                ((volatile uint32_t *)REG_PWM1_TRIPCFG)                 /* PWM1 Trip Config Register */
-#define pREG_PWM1_STAT                   ((volatile uint32_t *)REG_PWM1_STAT)                    /* PWM1 Status Register */
-#define pREG_PWM1_IMSK                   ((volatile uint32_t *)REG_PWM1_IMSK)                    /* PWM1 Interrupt Mask Register */
-#define pREG_PWM1_ILAT                   ((volatile uint32_t *)REG_PWM1_ILAT)                    /* PWM1 Interrupt Latch Register */
-#define pREG_PWM1_CHOPCFG                ((volatile uint32_t *)REG_PWM1_CHOPCFG)                 /* PWM1 Chop Configuration Register */
-#define pREG_PWM1_DT                     ((volatile uint32_t *)REG_PWM1_DT)                      /* PWM1 Dead Time Register */
-#define pREG_PWM1_SYNC_WID               ((volatile uint32_t *)REG_PWM1_SYNC_WID)                /* PWM1 Sync Pulse Width Register */
-#define pREG_PWM1_TM0                    ((volatile uint32_t *)REG_PWM1_TM0)                     /* PWM1 Timer 0 Period Register */
-#define pREG_PWM1_TM1                    ((volatile uint32_t *)REG_PWM1_TM1)                     /* PWM1 Timer 1 Period Register */
-#define pREG_PWM1_TM2                    ((volatile uint32_t *)REG_PWM1_TM2)                     /* PWM1 Timer 2 Period Register */
-#define pREG_PWM1_TM3                    ((volatile uint32_t *)REG_PWM1_TM3)                     /* PWM1 Timer 3 Period Register */
-#define pREG_PWM1_TM4                    ((volatile uint32_t *)REG_PWM1_TM4)                     /* PWM1 Timer 4 Period Register */
-#define pREG_PWM1_DLYA                   ((volatile uint32_t *)REG_PWM1_DLYA)                    /* PWM1 Channel A Delay Register */
-#define pREG_PWM1_DLYB                   ((volatile uint32_t *)REG_PWM1_DLYB)                    /* PWM1 Channel B Delay Register */
-#define pREG_PWM1_DLYC                   ((volatile uint32_t *)REG_PWM1_DLYC)                    /* PWM1 Channel C Delay Register */
-#define pREG_PWM1_DLYD                   ((volatile uint32_t *)REG_PWM1_DLYD)                    /* PWM1 Channel D Delay Register */
-#define pREG_PWM1_ACTL                   ((volatile uint32_t *)REG_PWM1_ACTL)                    /* PWM1 Channel A Control Register */
-#define pREG_PWM1_AH0                    ((volatile uint32_t *)REG_PWM1_AH0)                     /* PWM1 Channel A-High Duty-0 Register */
-#define pREG_PWM1_AH1                    ((volatile uint32_t *)REG_PWM1_AH1)                     /* PWM1 Channel A-High Duty-1 Register */
-#define pREG_PWM1_AL0                    ((volatile uint32_t *)REG_PWM1_AL0)                     /* PWM1 Channel A-Low Duty-0 Register */
-#define pREG_PWM1_AL1                    ((volatile uint32_t *)REG_PWM1_AL1)                     /* PWM1 Channel A-Low Duty-1 Register */
-#define pREG_PWM1_BCTL                   ((volatile uint32_t *)REG_PWM1_BCTL)                    /* PWM1 Channel B Control Register */
-#define pREG_PWM1_BH0                    ((volatile uint32_t *)REG_PWM1_BH0)                     /* PWM1 Channel B-High Duty-0 Register */
-#define pREG_PWM1_BH1                    ((volatile uint32_t *)REG_PWM1_BH1)                     /* PWM1 Channel B-High Duty-1 Register */
-#define pREG_PWM1_BL0                    ((volatile uint32_t *)REG_PWM1_BL0)                     /* PWM1 Channel B-Low Duty-0 Register */
-#define pREG_PWM1_BL1                    ((volatile uint32_t *)REG_PWM1_BL1)                     /* PWM1 Channel B-Low Duty-1 Register */
-#define pREG_PWM1_CCTL                   ((volatile uint32_t *)REG_PWM1_CCTL)                    /* PWM1 Channel C Control Register */
-#define pREG_PWM1_CH0                    ((volatile uint32_t *)REG_PWM1_CH0)                     /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define pREG_PWM1_CH1                    ((volatile uint32_t *)REG_PWM1_CH1)                     /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define pREG_PWM1_CL0                    ((volatile uint32_t *)REG_PWM1_CL0)                     /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define pREG_PWM1_CL1                    ((volatile uint32_t *)REG_PWM1_CL1)                     /* PWM1 Channel C-Low Duty-1 Register */
-#define pREG_PWM1_DCTL                   ((volatile uint32_t *)REG_PWM1_DCTL)                    /* PWM1 Channel D Control Register */
-#define pREG_PWM1_DH0                    ((volatile uint32_t *)REG_PWM1_DH0)                     /* PWM1 Channel D-High Duty-0 Register */
-#define pREG_PWM1_DH1                    ((volatile uint32_t *)REG_PWM1_DH1)                     /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define pREG_PWM1_DL0                    ((volatile uint32_t *)REG_PWM1_DL0)                     /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define pREG_PWM1_DL1                    ((volatile uint32_t *)REG_PWM1_DL1)                     /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-
-/* =========================================================================
-       VID0
-   ========================================================================= */
-#define pREG_VID0_CONN                   ((volatile uint32_t *)REG_VID0_CONN)                    /* VID0 Video Subsystem Connect Register */
-
-
-/* =========================================================================
-       SWU0
-   ========================================================================= */
-#define pREG_SWU0_GCTL                   ((volatile uint32_t *)REG_SWU0_GCTL)                    /* SWU0 Global Control Register */
-#define pREG_SWU0_GSTAT                  ((volatile uint32_t *)REG_SWU0_GSTAT)                   /* SWU0 Global Status Register */
-#define pREG_SWU0_CTL0                   ((volatile uint32_t *)REG_SWU0_CTL0)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL1                   ((volatile uint32_t *)REG_SWU0_CTL1)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL2                   ((volatile uint32_t *)REG_SWU0_CTL2)                    /* SWU0 Control Register n */
-#define pREG_SWU0_CTL3                   ((volatile uint32_t *)REG_SWU0_CTL3)                    /* SWU0 Control Register n */
-#define pREG_SWU0_LA0                    ((void * volatile *)REG_SWU0_LA0)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA1                    ((void * volatile *)REG_SWU0_LA1)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA2                    ((void * volatile *)REG_SWU0_LA2)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_LA3                    ((void * volatile *)REG_SWU0_LA3)                       /* SWU0 Lower Address Register n */
-#define pREG_SWU0_UA0                    ((void * volatile *)REG_SWU0_UA0)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA1                    ((void * volatile *)REG_SWU0_UA1)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA2                    ((void * volatile *)REG_SWU0_UA2)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_UA3                    ((void * volatile *)REG_SWU0_UA3)                       /* SWU0 Upper Address Register n */
-#define pREG_SWU0_ID0                    ((volatile uint32_t *)REG_SWU0_ID0)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID1                    ((volatile uint32_t *)REG_SWU0_ID1)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID2                    ((volatile uint32_t *)REG_SWU0_ID2)                     /* SWU0 ID Register n */
-#define pREG_SWU0_ID3                    ((volatile uint32_t *)REG_SWU0_ID3)                     /* SWU0 ID Register n */
-#define pREG_SWU0_CNT0                   ((volatile uint32_t *)REG_SWU0_CNT0)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT1                   ((volatile uint32_t *)REG_SWU0_CNT1)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT2                   ((volatile uint32_t *)REG_SWU0_CNT2)                    /* SWU0 Count Register n */
-#define pREG_SWU0_CNT3                   ((volatile uint32_t *)REG_SWU0_CNT3)                    /* SWU0 Count Register n */
-#define pREG_SWU0_TARG0                  ((volatile uint32_t *)REG_SWU0_TARG0)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG1                  ((volatile uint32_t *)REG_SWU0_TARG1)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG2                  ((volatile uint32_t *)REG_SWU0_TARG2)                   /* SWU0 Target Register n */
-#define pREG_SWU0_TARG3                  ((volatile uint32_t *)REG_SWU0_TARG3)                   /* SWU0 Target Register n */
-#define pREG_SWU0_HIST0                  ((volatile uint32_t *)REG_SWU0_HIST0)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST1                  ((volatile uint32_t *)REG_SWU0_HIST1)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST2                  ((volatile uint32_t *)REG_SWU0_HIST2)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_HIST3                  ((volatile uint32_t *)REG_SWU0_HIST3)                   /* SWU0 Bandwidth History Register n */
-#define pREG_SWU0_CUR0                   ((volatile uint32_t *)REG_SWU0_CUR0)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR1                   ((volatile uint32_t *)REG_SWU0_CUR1)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR2                   ((volatile uint32_t *)REG_SWU0_CUR2)                    /* SWU0 Current Register n */
-#define pREG_SWU0_CUR3                   ((volatile uint32_t *)REG_SWU0_CUR3)                    /* SWU0 Current Register n */
-
-/* =========================================================================
-       SWU1
-   ========================================================================= */
-#define pREG_SWU1_GCTL                   ((volatile uint32_t *)REG_SWU1_GCTL)                    /* SWU1 Global Control Register */
-#define pREG_SWU1_GSTAT                  ((volatile uint32_t *)REG_SWU1_GSTAT)                   /* SWU1 Global Status Register */
-#define pREG_SWU1_CTL0                   ((volatile uint32_t *)REG_SWU1_CTL0)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL1                   ((volatile uint32_t *)REG_SWU1_CTL1)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL2                   ((volatile uint32_t *)REG_SWU1_CTL2)                    /* SWU1 Control Register n */
-#define pREG_SWU1_CTL3                   ((volatile uint32_t *)REG_SWU1_CTL3)                    /* SWU1 Control Register n */
-#define pREG_SWU1_LA0                    ((void * volatile *)REG_SWU1_LA0)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA1                    ((void * volatile *)REG_SWU1_LA1)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA2                    ((void * volatile *)REG_SWU1_LA2)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_LA3                    ((void * volatile *)REG_SWU1_LA3)                       /* SWU1 Lower Address Register n */
-#define pREG_SWU1_UA0                    ((void * volatile *)REG_SWU1_UA0)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA1                    ((void * volatile *)REG_SWU1_UA1)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA2                    ((void * volatile *)REG_SWU1_UA2)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_UA3                    ((void * volatile *)REG_SWU1_UA3)                       /* SWU1 Upper Address Register n */
-#define pREG_SWU1_ID0                    ((volatile uint32_t *)REG_SWU1_ID0)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID1                    ((volatile uint32_t *)REG_SWU1_ID1)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID2                    ((volatile uint32_t *)REG_SWU1_ID2)                     /* SWU1 ID Register n */
-#define pREG_SWU1_ID3                    ((volatile uint32_t *)REG_SWU1_ID3)                     /* SWU1 ID Register n */
-#define pREG_SWU1_CNT0                   ((volatile uint32_t *)REG_SWU1_CNT0)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT1                   ((volatile uint32_t *)REG_SWU1_CNT1)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT2                   ((volatile uint32_t *)REG_SWU1_CNT2)                    /* SWU1 Count Register n */
-#define pREG_SWU1_CNT3                   ((volatile uint32_t *)REG_SWU1_CNT3)                    /* SWU1 Count Register n */
-#define pREG_SWU1_TARG0                  ((volatile uint32_t *)REG_SWU1_TARG0)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG1                  ((volatile uint32_t *)REG_SWU1_TARG1)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG2                  ((volatile uint32_t *)REG_SWU1_TARG2)                   /* SWU1 Target Register n */
-#define pREG_SWU1_TARG3                  ((volatile uint32_t *)REG_SWU1_TARG3)                   /* SWU1 Target Register n */
-#define pREG_SWU1_HIST0                  ((volatile uint32_t *)REG_SWU1_HIST0)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST1                  ((volatile uint32_t *)REG_SWU1_HIST1)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST2                  ((volatile uint32_t *)REG_SWU1_HIST2)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_HIST3                  ((volatile uint32_t *)REG_SWU1_HIST3)                   /* SWU1 Bandwidth History Register n */
-#define pREG_SWU1_CUR0                   ((volatile uint32_t *)REG_SWU1_CUR0)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR1                   ((volatile uint32_t *)REG_SWU1_CUR1)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR2                   ((volatile uint32_t *)REG_SWU1_CUR2)                    /* SWU1 Current Register n */
-#define pREG_SWU1_CUR3                   ((volatile uint32_t *)REG_SWU1_CUR3)                    /* SWU1 Current Register n */
-
-/* =========================================================================
-       SWU2
-   ========================================================================= */
-#define pREG_SWU2_GCTL                   ((volatile uint32_t *)REG_SWU2_GCTL)                    /* SWU2 Global Control Register */
-#define pREG_SWU2_GSTAT                  ((volatile uint32_t *)REG_SWU2_GSTAT)                   /* SWU2 Global Status Register */
-#define pREG_SWU2_CTL0                   ((volatile uint32_t *)REG_SWU2_CTL0)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL1                   ((volatile uint32_t *)REG_SWU2_CTL1)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL2                   ((volatile uint32_t *)REG_SWU2_CTL2)                    /* SWU2 Control Register n */
-#define pREG_SWU2_CTL3                   ((volatile uint32_t *)REG_SWU2_CTL3)                    /* SWU2 Control Register n */
-#define pREG_SWU2_LA0                    ((void * volatile *)REG_SWU2_LA0)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA1                    ((void * volatile *)REG_SWU2_LA1)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA2                    ((void * volatile *)REG_SWU2_LA2)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_LA3                    ((void * volatile *)REG_SWU2_LA3)                       /* SWU2 Lower Address Register n */
-#define pREG_SWU2_UA0                    ((void * volatile *)REG_SWU2_UA0)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA1                    ((void * volatile *)REG_SWU2_UA1)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA2                    ((void * volatile *)REG_SWU2_UA2)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_UA3                    ((void * volatile *)REG_SWU2_UA3)                       /* SWU2 Upper Address Register n */
-#define pREG_SWU2_ID0                    ((volatile uint32_t *)REG_SWU2_ID0)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID1                    ((volatile uint32_t *)REG_SWU2_ID1)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID2                    ((volatile uint32_t *)REG_SWU2_ID2)                     /* SWU2 ID Register n */
-#define pREG_SWU2_ID3                    ((volatile uint32_t *)REG_SWU2_ID3)                     /* SWU2 ID Register n */
-#define pREG_SWU2_CNT0                   ((volatile uint32_t *)REG_SWU2_CNT0)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT1                   ((volatile uint32_t *)REG_SWU2_CNT1)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT2                   ((volatile uint32_t *)REG_SWU2_CNT2)                    /* SWU2 Count Register n */
-#define pREG_SWU2_CNT3                   ((volatile uint32_t *)REG_SWU2_CNT3)                    /* SWU2 Count Register n */
-#define pREG_SWU2_TARG0                  ((volatile uint32_t *)REG_SWU2_TARG0)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG1                  ((volatile uint32_t *)REG_SWU2_TARG1)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG2                  ((volatile uint32_t *)REG_SWU2_TARG2)                   /* SWU2 Target Register n */
-#define pREG_SWU2_TARG3                  ((volatile uint32_t *)REG_SWU2_TARG3)                   /* SWU2 Target Register n */
-#define pREG_SWU2_HIST0                  ((volatile uint32_t *)REG_SWU2_HIST0)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST1                  ((volatile uint32_t *)REG_SWU2_HIST1)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST2                  ((volatile uint32_t *)REG_SWU2_HIST2)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_HIST3                  ((volatile uint32_t *)REG_SWU2_HIST3)                   /* SWU2 Bandwidth History Register n */
-#define pREG_SWU2_CUR0                   ((volatile uint32_t *)REG_SWU2_CUR0)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR1                   ((volatile uint32_t *)REG_SWU2_CUR1)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR2                   ((volatile uint32_t *)REG_SWU2_CUR2)                    /* SWU2 Current Register n */
-#define pREG_SWU2_CUR3                   ((volatile uint32_t *)REG_SWU2_CUR3)                    /* SWU2 Current Register n */
-
-/* =========================================================================
-       SWU3
-   ========================================================================= */
-#define pREG_SWU3_GCTL                   ((volatile uint32_t *)REG_SWU3_GCTL)                    /* SWU3 Global Control Register */
-#define pREG_SWU3_GSTAT                  ((volatile uint32_t *)REG_SWU3_GSTAT)                   /* SWU3 Global Status Register */
-#define pREG_SWU3_CTL0                   ((volatile uint32_t *)REG_SWU3_CTL0)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL1                   ((volatile uint32_t *)REG_SWU3_CTL1)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL2                   ((volatile uint32_t *)REG_SWU3_CTL2)                    /* SWU3 Control Register n */
-#define pREG_SWU3_CTL3                   ((volatile uint32_t *)REG_SWU3_CTL3)                    /* SWU3 Control Register n */
-#define pREG_SWU3_LA0                    ((void * volatile *)REG_SWU3_LA0)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA1                    ((void * volatile *)REG_SWU3_LA1)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA2                    ((void * volatile *)REG_SWU3_LA2)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_LA3                    ((void * volatile *)REG_SWU3_LA3)                       /* SWU3 Lower Address Register n */
-#define pREG_SWU3_UA0                    ((void * volatile *)REG_SWU3_UA0)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA1                    ((void * volatile *)REG_SWU3_UA1)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA2                    ((void * volatile *)REG_SWU3_UA2)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_UA3                    ((void * volatile *)REG_SWU3_UA3)                       /* SWU3 Upper Address Register n */
-#define pREG_SWU3_ID0                    ((volatile uint32_t *)REG_SWU3_ID0)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID1                    ((volatile uint32_t *)REG_SWU3_ID1)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID2                    ((volatile uint32_t *)REG_SWU3_ID2)                     /* SWU3 ID Register n */
-#define pREG_SWU3_ID3                    ((volatile uint32_t *)REG_SWU3_ID3)                     /* SWU3 ID Register n */
-#define pREG_SWU3_CNT0                   ((volatile uint32_t *)REG_SWU3_CNT0)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT1                   ((volatile uint32_t *)REG_SWU3_CNT1)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT2                   ((volatile uint32_t *)REG_SWU3_CNT2)                    /* SWU3 Count Register n */
-#define pREG_SWU3_CNT3                   ((volatile uint32_t *)REG_SWU3_CNT3)                    /* SWU3 Count Register n */
-#define pREG_SWU3_TARG0                  ((volatile uint32_t *)REG_SWU3_TARG0)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG1                  ((volatile uint32_t *)REG_SWU3_TARG1)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG2                  ((volatile uint32_t *)REG_SWU3_TARG2)                   /* SWU3 Target Register n */
-#define pREG_SWU3_TARG3                  ((volatile uint32_t *)REG_SWU3_TARG3)                   /* SWU3 Target Register n */
-#define pREG_SWU3_HIST0                  ((volatile uint32_t *)REG_SWU3_HIST0)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST1                  ((volatile uint32_t *)REG_SWU3_HIST1)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST2                  ((volatile uint32_t *)REG_SWU3_HIST2)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_HIST3                  ((volatile uint32_t *)REG_SWU3_HIST3)                   /* SWU3 Bandwidth History Register n */
-#define pREG_SWU3_CUR0                   ((volatile uint32_t *)REG_SWU3_CUR0)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR1                   ((volatile uint32_t *)REG_SWU3_CUR1)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR2                   ((volatile uint32_t *)REG_SWU3_CUR2)                    /* SWU3 Current Register n */
-#define pREG_SWU3_CUR3                   ((volatile uint32_t *)REG_SWU3_CUR3)                    /* SWU3 Current Register n */
-
-/* =========================================================================
-       SWU4
-   ========================================================================= */
-#define pREG_SWU4_GCTL                   ((volatile uint32_t *)REG_SWU4_GCTL)                    /* SWU4 Global Control Register */
-#define pREG_SWU4_GSTAT                  ((volatile uint32_t *)REG_SWU4_GSTAT)                   /* SWU4 Global Status Register */
-#define pREG_SWU4_CTL0                   ((volatile uint32_t *)REG_SWU4_CTL0)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL1                   ((volatile uint32_t *)REG_SWU4_CTL1)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL2                   ((volatile uint32_t *)REG_SWU4_CTL2)                    /* SWU4 Control Register n */
-#define pREG_SWU4_CTL3                   ((volatile uint32_t *)REG_SWU4_CTL3)                    /* SWU4 Control Register n */
-#define pREG_SWU4_LA0                    ((void * volatile *)REG_SWU4_LA0)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA1                    ((void * volatile *)REG_SWU4_LA1)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA2                    ((void * volatile *)REG_SWU4_LA2)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_LA3                    ((void * volatile *)REG_SWU4_LA3)                       /* SWU4 Lower Address Register n */
-#define pREG_SWU4_UA0                    ((void * volatile *)REG_SWU4_UA0)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA1                    ((void * volatile *)REG_SWU4_UA1)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA2                    ((void * volatile *)REG_SWU4_UA2)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_UA3                    ((void * volatile *)REG_SWU4_UA3)                       /* SWU4 Upper Address Register n */
-#define pREG_SWU4_ID0                    ((volatile uint32_t *)REG_SWU4_ID0)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID1                    ((volatile uint32_t *)REG_SWU4_ID1)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID2                    ((volatile uint32_t *)REG_SWU4_ID2)                     /* SWU4 ID Register n */
-#define pREG_SWU4_ID3                    ((volatile uint32_t *)REG_SWU4_ID3)                     /* SWU4 ID Register n */
-#define pREG_SWU4_CNT0                   ((volatile uint32_t *)REG_SWU4_CNT0)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT1                   ((volatile uint32_t *)REG_SWU4_CNT1)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT2                   ((volatile uint32_t *)REG_SWU4_CNT2)                    /* SWU4 Count Register n */
-#define pREG_SWU4_CNT3                   ((volatile uint32_t *)REG_SWU4_CNT3)                    /* SWU4 Count Register n */
-#define pREG_SWU4_TARG0                  ((volatile uint32_t *)REG_SWU4_TARG0)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG1                  ((volatile uint32_t *)REG_SWU4_TARG1)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG2                  ((volatile uint32_t *)REG_SWU4_TARG2)                   /* SWU4 Target Register n */
-#define pREG_SWU4_TARG3                  ((volatile uint32_t *)REG_SWU4_TARG3)                   /* SWU4 Target Register n */
-#define pREG_SWU4_HIST0                  ((volatile uint32_t *)REG_SWU4_HIST0)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST1                  ((volatile uint32_t *)REG_SWU4_HIST1)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST2                  ((volatile uint32_t *)REG_SWU4_HIST2)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_HIST3                  ((volatile uint32_t *)REG_SWU4_HIST3)                   /* SWU4 Bandwidth History Register n */
-#define pREG_SWU4_CUR0                   ((volatile uint32_t *)REG_SWU4_CUR0)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR1                   ((volatile uint32_t *)REG_SWU4_CUR1)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR2                   ((volatile uint32_t *)REG_SWU4_CUR2)                    /* SWU4 Current Register n */
-#define pREG_SWU4_CUR3                   ((volatile uint32_t *)REG_SWU4_CUR3)                    /* SWU4 Current Register n */
-
-/* =========================================================================
-       SWU5
-   ========================================================================= */
-#define pREG_SWU5_GCTL                   ((volatile uint32_t *)REG_SWU5_GCTL)                    /* SWU5 Global Control Register */
-#define pREG_SWU5_GSTAT                  ((volatile uint32_t *)REG_SWU5_GSTAT)                   /* SWU5 Global Status Register */
-#define pREG_SWU5_CTL0                   ((volatile uint32_t *)REG_SWU5_CTL0)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL1                   ((volatile uint32_t *)REG_SWU5_CTL1)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL2                   ((volatile uint32_t *)REG_SWU5_CTL2)                    /* SWU5 Control Register n */
-#define pREG_SWU5_CTL3                   ((volatile uint32_t *)REG_SWU5_CTL3)                    /* SWU5 Control Register n */
-#define pREG_SWU5_LA0                    ((void * volatile *)REG_SWU5_LA0)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA1                    ((void * volatile *)REG_SWU5_LA1)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA2                    ((void * volatile *)REG_SWU5_LA2)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_LA3                    ((void * volatile *)REG_SWU5_LA3)                       /* SWU5 Lower Address Register n */
-#define pREG_SWU5_UA0                    ((void * volatile *)REG_SWU5_UA0)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA1                    ((void * volatile *)REG_SWU5_UA1)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA2                    ((void * volatile *)REG_SWU5_UA2)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_UA3                    ((void * volatile *)REG_SWU5_UA3)                       /* SWU5 Upper Address Register n */
-#define pREG_SWU5_ID0                    ((volatile uint32_t *)REG_SWU5_ID0)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID1                    ((volatile uint32_t *)REG_SWU5_ID1)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID2                    ((volatile uint32_t *)REG_SWU5_ID2)                     /* SWU5 ID Register n */
-#define pREG_SWU5_ID3                    ((volatile uint32_t *)REG_SWU5_ID3)                     /* SWU5 ID Register n */
-#define pREG_SWU5_CNT0                   ((volatile uint32_t *)REG_SWU5_CNT0)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT1                   ((volatile uint32_t *)REG_SWU5_CNT1)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT2                   ((volatile uint32_t *)REG_SWU5_CNT2)                    /* SWU5 Count Register n */
-#define pREG_SWU5_CNT3                   ((volatile uint32_t *)REG_SWU5_CNT3)                    /* SWU5 Count Register n */
-#define pREG_SWU5_TARG0                  ((volatile uint32_t *)REG_SWU5_TARG0)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG1                  ((volatile uint32_t *)REG_SWU5_TARG1)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG2                  ((volatile uint32_t *)REG_SWU5_TARG2)                   /* SWU5 Target Register n */
-#define pREG_SWU5_TARG3                  ((volatile uint32_t *)REG_SWU5_TARG3)                   /* SWU5 Target Register n */
-#define pREG_SWU5_HIST0                  ((volatile uint32_t *)REG_SWU5_HIST0)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST1                  ((volatile uint32_t *)REG_SWU5_HIST1)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST2                  ((volatile uint32_t *)REG_SWU5_HIST2)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_HIST3                  ((volatile uint32_t *)REG_SWU5_HIST3)                   /* SWU5 Bandwidth History Register n */
-#define pREG_SWU5_CUR0                   ((volatile uint32_t *)REG_SWU5_CUR0)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR1                   ((volatile uint32_t *)REG_SWU5_CUR1)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR2                   ((volatile uint32_t *)REG_SWU5_CUR2)                    /* SWU5 Current Register n */
-#define pREG_SWU5_CUR3                   ((volatile uint32_t *)REG_SWU5_CUR3)                    /* SWU5 Current Register n */
-
-/* =========================================================================
-       SWU6
-   ========================================================================= */
-#define pREG_SWU6_GCTL                   ((volatile uint32_t *)REG_SWU6_GCTL)                    /* SWU6 Global Control Register */
-#define pREG_SWU6_GSTAT                  ((volatile uint32_t *)REG_SWU6_GSTAT)                   /* SWU6 Global Status Register */
-#define pREG_SWU6_CTL0                   ((volatile uint32_t *)REG_SWU6_CTL0)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL1                   ((volatile uint32_t *)REG_SWU6_CTL1)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL2                   ((volatile uint32_t *)REG_SWU6_CTL2)                    /* SWU6 Control Register n */
-#define pREG_SWU6_CTL3                   ((volatile uint32_t *)REG_SWU6_CTL3)                    /* SWU6 Control Register n */
-#define pREG_SWU6_LA0                    ((void * volatile *)REG_SWU6_LA0)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA1                    ((void * volatile *)REG_SWU6_LA1)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA2                    ((void * volatile *)REG_SWU6_LA2)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_LA3                    ((void * volatile *)REG_SWU6_LA3)                       /* SWU6 Lower Address Register n */
-#define pREG_SWU6_UA0                    ((void * volatile *)REG_SWU6_UA0)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA1                    ((void * volatile *)REG_SWU6_UA1)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA2                    ((void * volatile *)REG_SWU6_UA2)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_UA3                    ((void * volatile *)REG_SWU6_UA3)                       /* SWU6 Upper Address Register n */
-#define pREG_SWU6_ID0                    ((volatile uint32_t *)REG_SWU6_ID0)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID1                    ((volatile uint32_t *)REG_SWU6_ID1)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID2                    ((volatile uint32_t *)REG_SWU6_ID2)                     /* SWU6 ID Register n */
-#define pREG_SWU6_ID3                    ((volatile uint32_t *)REG_SWU6_ID3)                     /* SWU6 ID Register n */
-#define pREG_SWU6_CNT0                   ((volatile uint32_t *)REG_SWU6_CNT0)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT1                   ((volatile uint32_t *)REG_SWU6_CNT1)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT2                   ((volatile uint32_t *)REG_SWU6_CNT2)                    /* SWU6 Count Register n */
-#define pREG_SWU6_CNT3                   ((volatile uint32_t *)REG_SWU6_CNT3)                    /* SWU6 Count Register n */
-#define pREG_SWU6_TARG0                  ((volatile uint32_t *)REG_SWU6_TARG0)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG1                  ((volatile uint32_t *)REG_SWU6_TARG1)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG2                  ((volatile uint32_t *)REG_SWU6_TARG2)                   /* SWU6 Target Register n */
-#define pREG_SWU6_TARG3                  ((volatile uint32_t *)REG_SWU6_TARG3)                   /* SWU6 Target Register n */
-#define pREG_SWU6_HIST0                  ((volatile uint32_t *)REG_SWU6_HIST0)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST1                  ((volatile uint32_t *)REG_SWU6_HIST1)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST2                  ((volatile uint32_t *)REG_SWU6_HIST2)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_HIST3                  ((volatile uint32_t *)REG_SWU6_HIST3)                   /* SWU6 Bandwidth History Register n */
-#define pREG_SWU6_CUR0                   ((volatile uint32_t *)REG_SWU6_CUR0)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR1                   ((volatile uint32_t *)REG_SWU6_CUR1)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR2                   ((volatile uint32_t *)REG_SWU6_CUR2)                    /* SWU6 Current Register n */
-#define pREG_SWU6_CUR3                   ((volatile uint32_t *)REG_SWU6_CUR3)                    /* SWU6 Current Register n */
-
-
-/* =========================================================================
-       SDU0
-   ========================================================================= */
-#define pREG_SDU0_IDCODE                 ((volatile uint32_t *)REG_SDU0_IDCODE)                  /* SDU0 ID Code Register */
-#define pREG_SDU0_CTL                    ((volatile uint32_t *)REG_SDU0_CTL)                     /* SDU0 Control Register */
-#define pREG_SDU0_STAT                   ((volatile uint32_t *)REG_SDU0_STAT)                    /* SDU0 Status Register */
-#define pREG_SDU0_MACCTL                 ((volatile uint32_t *)REG_SDU0_MACCTL)                  /* SDU0 Memory Access Control Register */
-#define pREG_SDU0_MACADDR                ((void * volatile *)REG_SDU0_MACADDR)                   /* SDU0 Memory Access Address Register */
-#define pREG_SDU0_MACDATA                ((volatile uint32_t *)REG_SDU0_MACDATA)                 /* SDU0 Memory Access Data Register */
-#define pREG_SDU0_DMARD                  ((volatile uint32_t *)REG_SDU0_DMARD)                   /* SDU0 DMA Read Data Register */
-#define pREG_SDU0_DMAWD                  ((volatile uint32_t *)REG_SDU0_DMAWD)                   /* SDU0 DMA Write Data Register */
-#define pREG_SDU0_MSG                    ((volatile uint32_t *)REG_SDU0_MSG)                     /* SDU0 Message Register */
-#define pREG_SDU0_MSG_SET                ((volatile uint32_t *)REG_SDU0_MSG_SET)                 /* SDU0 Message Set Register */
-#define pREG_SDU0_MSG_CLR                ((volatile uint32_t *)REG_SDU0_MSG_CLR)                 /* SDU0 Message Clear Register */
-#define pREG_SDU0_GHLT                   ((volatile uint32_t *)REG_SDU0_GHLT)                    /* SDU0 Group Halt Register */
-
-
-/* =========================================================================
-       EMAC0
-   ========================================================================= */
-#define pREG_EMAC0_MACCFG                ((volatile uint32_t *)REG_EMAC0_MACCFG)                 /* EMAC0 MAC Configuration Register */
-#define pREG_EMAC0_MACFRMFILT            ((volatile uint32_t *)REG_EMAC0_MACFRMFILT)             /* EMAC0 MAC Rx Frame Filter Register */
-#define pREG_EMAC0_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC0_HASHTBL_HI)             /* EMAC0 Hash Table High Register */
-#define pREG_EMAC0_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC0_HASHTBL_LO)             /* EMAC0 Hash Table Low Register */
-#define pREG_EMAC0_SMI_ADDR              ((volatile uint32_t *)REG_EMAC0_SMI_ADDR)               /* EMAC0 SMI Address Register */
-#define pREG_EMAC0_SMI_DATA              ((volatile uint32_t *)REG_EMAC0_SMI_DATA)               /* EMAC0 SMI Data Register */
-#define pREG_EMAC0_FLOWCTL               ((volatile uint32_t *)REG_EMAC0_FLOWCTL)                /* EMAC0 FLow Control Register */
-#define pREG_EMAC0_VLANTAG               ((volatile uint32_t *)REG_EMAC0_VLANTAG)                /* EMAC0 VLAN Tag Register */
-#define pREG_EMAC0_DBG                   ((volatile uint32_t *)REG_EMAC0_DBG)                    /* EMAC0 Debug Register */
-#define pREG_EMAC0_ISTAT                 ((volatile uint32_t *)REG_EMAC0_ISTAT)                  /* EMAC0 Interrupt Status Register */
-#define pREG_EMAC0_IMSK                  ((volatile uint32_t *)REG_EMAC0_IMSK)                   /* EMAC0 Interrupt Mask Register */
-#define pREG_EMAC0_ADDR0_HI              ((volatile uint32_t *)REG_EMAC0_ADDR0_HI)               /* EMAC0 MAC Address 0 High Register */
-#define pREG_EMAC0_ADDR0_LO              ((volatile uint32_t *)REG_EMAC0_ADDR0_LO)               /* EMAC0 MAC Address 0 Low Register */
-#define pREG_EMAC0_MMC_CTL               ((volatile uint32_t *)REG_EMAC0_MMC_CTL)                /* EMAC0 MMC Control Register */
-#define pREG_EMAC0_MMC_RXINT             ((volatile uint32_t *)REG_EMAC0_MMC_RXINT)              /* EMAC0 MMC Rx Interrupt Register */
-#define pREG_EMAC0_MMC_TXINT             ((volatile uint32_t *)REG_EMAC0_MMC_TXINT)              /* EMAC0 MMC Tx Interrupt Register */
-#define pREG_EMAC0_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_RXIMSK)             /* EMAC0 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC0_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC0_MMC_TXIMSK)             /* EMAC0 MMC TX Interrupt Mask Register */
-#define pREG_EMAC0_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_GB)            /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC0_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_GB)            /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_G)           /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_G)           /* EMAC0 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC0_TX64_GB               ((volatile uint32_t *)REG_EMAC0_TX64_GB)                /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_TX65TO127_GB)           /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_TX128TO255_GB)          /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_TX256TO511_GB)          /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_TX512TO1023_GB)         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_TX1024TOMAX_GB)         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXUCASTFRM_GB)          /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXMCASTFRM_GB)          /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC0_TXBCASTFRM_GB)          /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC0_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC0_TXUNDR_ERR)             /* EMAC0 Tx Underflow Error Register */
-#define pREG_EMAC0_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC0_TXSNGCOL_G)             /* EMAC0 Tx Single Collision (Good) Register */
-#define pREG_EMAC0_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC0_TXMULTCOL_G)            /* EMAC0 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC0_TXDEFERRED            ((volatile uint32_t *)REG_EMAC0_TXDEFERRED)             /* EMAC0 Tx Deferred Register */
-#define pREG_EMAC0_TXLATECOL             ((volatile uint32_t *)REG_EMAC0_TXLATECOL)              /* EMAC0 Tx Late Collision Register */
-#define pREG_EMAC0_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC0_TXEXCESSCOL)            /* EMAC0 Tx Excess Collision Register */
-#define pREG_EMAC0_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC0_TXCARR_ERR)             /* EMAC0 Tx Carrier Error Register */
-#define pREG_EMAC0_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_TXOCTCNT_G)             /* EMAC0 Tx Octet Count (Good) Register */
-#define pREG_EMAC0_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC0_TXFRMCNT_G)             /* EMAC0 Tx Frame Count (Good) Register */
-#define pREG_EMAC0_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC0_TXEXCESSDEF)            /* EMAC0 Tx Excess Deferral Register */
-#define pREG_EMAC0_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_TXPAUSEFRM)             /* EMAC0 Tx Pause Frame Register */
-#define pREG_EMAC0_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC0_TXVLANFRM_G)            /* EMAC0 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC0_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXFRMCNT_GB)            /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_GB)            /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC0_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC0_RXOCTCNT_G)             /* EMAC0 Rx Octet Count (Good) Register */
-#define pREG_EMAC0_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXBCASTFRM_G)           /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC0_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXMCASTFRM_G)           /* EMAC0 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC0_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC0_RXCRC_ERR)              /* EMAC0 Rx CRC Error Register */
-#define pREG_EMAC0_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC0_RXALIGN_ERR)            /* EMAC0 Rx alignment Error Register */
-#define pREG_EMAC0_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC0_RXRUNT_ERR)             /* EMAC0 Rx Runt Error Register */
-#define pREG_EMAC0_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC0_RXJAB_ERR)              /* EMAC0 Rx Jab Error Register */
-#define pREG_EMAC0_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXUSIZE_G)              /* EMAC0 Rx Undersize (Good) Register */
-#define pREG_EMAC0_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC0_RXOSIZE_G)              /* EMAC0 Rx Oversize (Good) Register */
-#define pREG_EMAC0_RX64_GB               ((volatile uint32_t *)REG_EMAC0_RX64_GB)                /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC0_RX65TO127_GB)           /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC0_RX128TO255_GB)          /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC0_RX256TO511_GB)          /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC0_RX512TO1023_GB)         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC0_RX1024TOMAX_GB)         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC0_RXUCASTFRM_G)           /* EMAC0 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC0_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC0_RXLEN_ERR)              /* EMAC0 Rx Length Error Register */
-#define pREG_EMAC0_RXOORTYPE             ((volatile uint32_t *)REG_EMAC0_RXOORTYPE)              /* EMAC0 Rx Out Of Range Type Register */
-#define pREG_EMAC0_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC0_RXPAUSEFRM)             /* EMAC0 Rx Pause Frames Register */
-#define pREG_EMAC0_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC0_RXFIFO_OVF)             /* EMAC0 Rx FIFO Overflow Register */
-#define pREG_EMAC0_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC0_RXVLANFRM_GB)           /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC0_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC0_RXWDOG_ERR)             /* EMAC0 Rx Watch Dog Error Register */
-#define pREG_EMAC0_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC0_IPC_RXIMSK)             /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC0_IPC_RXINT             ((volatile uint32_t *)REG_EMAC0_IPC_RXINT)              /* EMAC0 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC0_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_FRM)          /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_FRM)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_FRM)       /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC0_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_FRM)        /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_FRM)       /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC0_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_FRM)          /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_FRM)     /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_FRM)       /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC0_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_FRM)           /* EMAC0 Rx UDP Good Frames Register */
-#define pREG_EMAC0_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_FRM)          /* EMAC0 Rx UDP Error Frames Register */
-#define pREG_EMAC0_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_FRM)           /* EMAC0 Rx TCP Good Frames Register */
-#define pREG_EMAC0_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_FRM)          /* EMAC0 Rx TCP Error Frames Register */
-#define pREG_EMAC0_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_FRM)          /* EMAC0 Rx ICMP Good Frames Register */
-#define pREG_EMAC0_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_FRM)         /* EMAC0 Rx ICMP Error Frames Register */
-#define pREG_EMAC0_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV4_GD_OCT)          /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC0_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV4_HDR_ERR_OCT)     /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC0_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_NOPAY_OCT)       /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC0_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC0_RXIPV4_FRAG_OCT)        /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC0_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV4_UDSBL_OCT)       /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC0_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXIPV6_GD_OCT)          /* EMAC0 Rx IPv6 Good Octets Register */
-#define pREG_EMAC0_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC0_RXIPV6_HDR_ERR_OCT)     /* EMAC0 Rx IPv6 Header Errors Register */
-#define pREG_EMAC0_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC0_RXIPV6_NOPAY_OCT)       /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC0_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXUDP_GD_OCT)           /* EMAC0 Rx UDP Good Octets Register */
-#define pREG_EMAC0_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXUDP_ERR_OCT)          /* EMAC0 Rx UDP Error Octets Register */
-#define pREG_EMAC0_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC0_RXTCP_GD_OCT)           /* EMAC0 Rx TCP Good Octets Register */
-#define pREG_EMAC0_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC0_RXTCP_ERR_OCT)          /* EMAC0 Rx TCP Error Octets Register */
-#define pREG_EMAC0_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC0_RXICMP_GD_OCT)          /* EMAC0 Rx ICMP Good Octets Register */
-#define pREG_EMAC0_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC0_RXICMP_ERR_OCT)         /* EMAC0 Rx ICMP Error Octets Register */
-#define pREG_EMAC0_TM_CTL                ((volatile uint32_t *)REG_EMAC0_TM_CTL)                 /* EMAC0 Time Stamp Control Register */
-#define pREG_EMAC0_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC0_TM_SUBSEC)              /* EMAC0 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC0_TM_SEC                ((volatile uint32_t *)REG_EMAC0_TM_SEC)                 /* EMAC0 Time Stamp Low Seconds Register */
-#define pREG_EMAC0_TM_NSEC               ((volatile uint32_t *)REG_EMAC0_TM_NSEC)                /* EMAC0 Time Stamp Nano Seconds Register */
-#define pREG_EMAC0_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC0_TM_SECUPDT)             /* EMAC0 Time Stamp Seconds Update Register */
-#define pREG_EMAC0_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC0_TM_NSECUPDT)            /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC0_TM_ADDEND             ((volatile uint32_t *)REG_EMAC0_TM_ADDEND)              /* EMAC0 Time Stamp Addend Register */
-#define pREG_EMAC0_TM_TGTM               ((volatile uint32_t *)REG_EMAC0_TM_TGTM)                /* EMAC0 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC0_TM_NTGTM              ((volatile uint32_t *)REG_EMAC0_TM_NTGTM)               /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC0_TM_HISEC              ((volatile uint32_t *)REG_EMAC0_TM_HISEC)               /* EMAC0 Time Stamp High Second Register */
-#define pREG_EMAC0_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC0_TM_STMPSTAT)            /* EMAC0 Time Stamp Status Register */
-#define pREG_EMAC0_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC0_TM_PPSCTL)              /* EMAC0 PPS Control Register */
-#define pREG_EMAC0_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_NSEC)        /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC0_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC0_TM_AUXSTMP_SEC)         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC0_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC0_TM_PPSINTVL)            /* EMAC0 Time Stamp PPS Interval Register */
-#define pREG_EMAC0_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC0_TM_PPSWIDTH)            /* EMAC0 PPS Width Register */
-#define pREG_EMAC0_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC0_DMA_BUSMODE)            /* EMAC0 DMA Bus Mode Register */
-#define pREG_EMAC0_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_TXPOLL)             /* EMAC0 DMA Tx Poll Demand Register */
-#define pREG_EMAC0_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC0_DMA_RXPOLL)             /* EMAC0 DMA Rx Poll Demand register */
-#define pREG_EMAC0_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_ADDR)         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_ADDR)         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC0_DMA_STAT              ((volatile uint32_t *)REG_EMAC0_DMA_STAT)               /* EMAC0 DMA Status Register */
-#define pREG_EMAC0_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC0_DMA_OPMODE)             /* EMAC0 DMA Operation Mode Register */
-#define pREG_EMAC0_DMA_IEN               ((volatile uint32_t *)REG_EMAC0_DMA_IEN)                /* EMAC0 DMA Interrupt Enable Register */
-#define pREG_EMAC0_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC0_DMA_MISS_FRM)           /* EMAC0 DMA Missed Frame Register */
-#define pREG_EMAC0_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC0_DMA_RXIWDOG)            /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC0_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC0_DMA_BMMODE)             /* EMAC0 DMA SCB Bus Mode Register */
-#define pREG_EMAC0_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC0_DMA_BMSTAT)             /* EMAC0 DMA SCB Status Register */
-#define pREG_EMAC0_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXDSC_CUR)          /* EMAC0 DMA Tx Descriptor Current Register */
-#define pREG_EMAC0_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXDSC_CUR)          /* EMAC0 DMA Rx Descriptor Current Register */
-#define pREG_EMAC0_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_TXBUF_CUR)          /* EMAC0 DMA Tx Buffer Current Register */
-#define pREG_EMAC0_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC0_DMA_RXBUF_CUR)          /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================================================================
-       EMAC1
-   ========================================================================= */
-#define pREG_EMAC1_MACCFG                ((volatile uint32_t *)REG_EMAC1_MACCFG)                 /* EMAC1 MAC Configuration Register */
-#define pREG_EMAC1_MACFRMFILT            ((volatile uint32_t *)REG_EMAC1_MACFRMFILT)             /* EMAC1 MAC Rx Frame Filter Register */
-#define pREG_EMAC1_HASHTBL_HI            ((volatile uint32_t *)REG_EMAC1_HASHTBL_HI)             /* EMAC1 Hash Table High Register */
-#define pREG_EMAC1_HASHTBL_LO            ((volatile uint32_t *)REG_EMAC1_HASHTBL_LO)             /* EMAC1 Hash Table Low Register */
-#define pREG_EMAC1_SMI_ADDR              ((volatile uint32_t *)REG_EMAC1_SMI_ADDR)               /* EMAC1 SMI Address Register */
-#define pREG_EMAC1_SMI_DATA              ((volatile uint32_t *)REG_EMAC1_SMI_DATA)               /* EMAC1 SMI Data Register */
-#define pREG_EMAC1_FLOWCTL               ((volatile uint32_t *)REG_EMAC1_FLOWCTL)                /* EMAC1 FLow Control Register */
-#define pREG_EMAC1_VLANTAG               ((volatile uint32_t *)REG_EMAC1_VLANTAG)                /* EMAC1 VLAN Tag Register */
-#define pREG_EMAC1_DBG                   ((volatile uint32_t *)REG_EMAC1_DBG)                    /* EMAC1 Debug Register */
-#define pREG_EMAC1_ISTAT                 ((volatile uint32_t *)REG_EMAC1_ISTAT)                  /* EMAC1 Interrupt Status Register */
-#define pREG_EMAC1_IMSK                  ((volatile uint32_t *)REG_EMAC1_IMSK)                   /* EMAC1 Interrupt Mask Register */
-#define pREG_EMAC1_ADDR0_HI              ((volatile uint32_t *)REG_EMAC1_ADDR0_HI)               /* EMAC1 MAC Address 0 High Register */
-#define pREG_EMAC1_ADDR0_LO              ((volatile uint32_t *)REG_EMAC1_ADDR0_LO)               /* EMAC1 MAC Address 0 Low Register */
-#define pREG_EMAC1_MMC_CTL               ((volatile uint32_t *)REG_EMAC1_MMC_CTL)                /* EMAC1 MMC Control Register */
-#define pREG_EMAC1_MMC_RXINT             ((volatile uint32_t *)REG_EMAC1_MMC_RXINT)              /* EMAC1 MMC Rx Interrupt Register */
-#define pREG_EMAC1_MMC_TXINT             ((volatile uint32_t *)REG_EMAC1_MMC_TXINT)              /* EMAC1 MMC Tx Interrupt Register */
-#define pREG_EMAC1_MMC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_RXIMSK)             /* EMAC1 MMC Rx Interrupt Mask Register */
-#define pREG_EMAC1_MMC_TXIMSK            ((volatile uint32_t *)REG_EMAC1_MMC_TXIMSK)             /* EMAC1 MMC TX Interrupt Mask Register */
-#define pREG_EMAC1_TXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_GB)            /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define pREG_EMAC1_TXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_GB)            /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_G)           /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_TXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_G)           /* EMAC1 Tx Multicast Frames (Good) Register */
-#define pREG_EMAC1_TX64_GB               ((volatile uint32_t *)REG_EMAC1_TX64_GB)                /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_TX65TO127_GB)           /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_TX128TO255_GB)          /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_TX256TO511_GB)          /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_TX512TO1023_GB)         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_TX1024TOMAX_GB)         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXUCASTFRM_GB)          /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXMCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXMCASTFRM_GB)          /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXBCASTFRM_GB         ((volatile uint32_t *)REG_EMAC1_TXBCASTFRM_GB)          /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define pREG_EMAC1_TXUNDR_ERR            ((volatile uint32_t *)REG_EMAC1_TXUNDR_ERR)             /* EMAC1 Tx Underflow Error Register */
-#define pREG_EMAC1_TXSNGCOL_G            ((volatile uint32_t *)REG_EMAC1_TXSNGCOL_G)             /* EMAC1 Tx Single Collision (Good) Register */
-#define pREG_EMAC1_TXMULTCOL_G           ((volatile uint32_t *)REG_EMAC1_TXMULTCOL_G)            /* EMAC1 Tx Multiple Collision (Good) Register */
-#define pREG_EMAC1_TXDEFERRED            ((volatile uint32_t *)REG_EMAC1_TXDEFERRED)             /* EMAC1 Tx Deferred Register */
-#define pREG_EMAC1_TXLATECOL             ((volatile uint32_t *)REG_EMAC1_TXLATECOL)              /* EMAC1 Tx Late Collision Register */
-#define pREG_EMAC1_TXEXCESSCOL           ((volatile uint32_t *)REG_EMAC1_TXEXCESSCOL)            /* EMAC1 Tx Excess Collision Register */
-#define pREG_EMAC1_TXCARR_ERR            ((volatile uint32_t *)REG_EMAC1_TXCARR_ERR)             /* EMAC1 Tx Carrier Error Register */
-#define pREG_EMAC1_TXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_TXOCTCNT_G)             /* EMAC1 Tx Octet Count (Good) Register */
-#define pREG_EMAC1_TXFRMCNT_G            ((volatile uint32_t *)REG_EMAC1_TXFRMCNT_G)             /* EMAC1 Tx Frame Count (Good) Register */
-#define pREG_EMAC1_TXEXCESSDEF           ((volatile uint32_t *)REG_EMAC1_TXEXCESSDEF)            /* EMAC1 Tx Excess Deferral Register */
-#define pREG_EMAC1_TXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_TXPAUSEFRM)             /* EMAC1 Tx Pause Frame Register */
-#define pREG_EMAC1_TXVLANFRM_G           ((volatile uint32_t *)REG_EMAC1_TXVLANFRM_G)            /* EMAC1 Tx VLAN Frames (Good) Register */
-#define pREG_EMAC1_RXFRMCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXFRMCNT_GB)            /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_GB           ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_GB)            /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define pREG_EMAC1_RXOCTCNT_G            ((volatile uint32_t *)REG_EMAC1_RXOCTCNT_G)             /* EMAC1 Rx Octet Count (Good) Register */
-#define pREG_EMAC1_RXBCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXBCASTFRM_G)           /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define pREG_EMAC1_RXMCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXMCASTFRM_G)           /* EMAC1 Rx Multicast Frames (Good) Register */
-#define pREG_EMAC1_RXCRC_ERR             ((volatile uint32_t *)REG_EMAC1_RXCRC_ERR)              /* EMAC1 Rx CRC Error Register */
-#define pREG_EMAC1_RXALIGN_ERR           ((volatile uint32_t *)REG_EMAC1_RXALIGN_ERR)            /* EMAC1 Rx alignment Error Register */
-#define pREG_EMAC1_RXRUNT_ERR            ((volatile uint32_t *)REG_EMAC1_RXRUNT_ERR)             /* EMAC1 Rx Runt Error Register */
-#define pREG_EMAC1_RXJAB_ERR             ((volatile uint32_t *)REG_EMAC1_RXJAB_ERR)              /* EMAC1 Rx Jab Error Register */
-#define pREG_EMAC1_RXUSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXUSIZE_G)              /* EMAC1 Rx Undersize (Good) Register */
-#define pREG_EMAC1_RXOSIZE_G             ((volatile uint32_t *)REG_EMAC1_RXOSIZE_G)              /* EMAC1 Rx Oversize (Good) Register */
-#define pREG_EMAC1_RX64_GB               ((volatile uint32_t *)REG_EMAC1_RX64_GB)                /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX65TO127_GB          ((volatile uint32_t *)REG_EMAC1_RX65TO127_GB)           /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX128TO255_GB         ((volatile uint32_t *)REG_EMAC1_RX128TO255_GB)          /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX256TO511_GB         ((volatile uint32_t *)REG_EMAC1_RX256TO511_GB)          /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX512TO1023_GB        ((volatile uint32_t *)REG_EMAC1_RX512TO1023_GB)         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RX1024TOMAX_GB        ((volatile uint32_t *)REG_EMAC1_RX1024TOMAX_GB)         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXUCASTFRM_G          ((volatile uint32_t *)REG_EMAC1_RXUCASTFRM_G)           /* EMAC1 Rx Unicast Frames (Good) Register */
-#define pREG_EMAC1_RXLEN_ERR             ((volatile uint32_t *)REG_EMAC1_RXLEN_ERR)              /* EMAC1 Rx Length Error Register */
-#define pREG_EMAC1_RXOORTYPE             ((volatile uint32_t *)REG_EMAC1_RXOORTYPE)              /* EMAC1 Rx Out Of Range Type Register */
-#define pREG_EMAC1_RXPAUSEFRM            ((volatile uint32_t *)REG_EMAC1_RXPAUSEFRM)             /* EMAC1 Rx Pause Frames Register */
-#define pREG_EMAC1_RXFIFO_OVF            ((volatile uint32_t *)REG_EMAC1_RXFIFO_OVF)             /* EMAC1 Rx FIFO Overflow Register */
-#define pREG_EMAC1_RXVLANFRM_GB          ((volatile uint32_t *)REG_EMAC1_RXVLANFRM_GB)           /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define pREG_EMAC1_RXWDOG_ERR            ((volatile uint32_t *)REG_EMAC1_RXWDOG_ERR)             /* EMAC1 Rx Watch Dog Error Register */
-#define pREG_EMAC1_IPC_RXIMSK            ((volatile uint32_t *)REG_EMAC1_IPC_RXIMSK)             /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define pREG_EMAC1_IPC_RXINT             ((volatile uint32_t *)REG_EMAC1_IPC_RXINT)              /* EMAC1 MMC IPC Rx Interrupt Register */
-#define pREG_EMAC1_RXIPV4_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_FRM)          /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_FRM)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_FRM)       /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define pREG_EMAC1_RXIPV4_FRAG_FRM       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_FRM)        /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_FRM)       /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define pREG_EMAC1_RXIPV6_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_FRM)          /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_FRM    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_FRM)     /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_FRM      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_FRM)       /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define pREG_EMAC1_RXUDP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_FRM)           /* EMAC1 Rx UDP Good Frames Register */
-#define pREG_EMAC1_RXUDP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_FRM)          /* EMAC1 Rx UDP Error Frames Register */
-#define pREG_EMAC1_RXTCP_GD_FRM          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_FRM)           /* EMAC1 Rx TCP Good Frames Register */
-#define pREG_EMAC1_RXTCP_ERR_FRM         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_FRM)          /* EMAC1 Rx TCP Error Frames Register */
-#define pREG_EMAC1_RXICMP_GD_FRM         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_FRM)          /* EMAC1 Rx ICMP Good Frames Register */
-#define pREG_EMAC1_RXICMP_ERR_FRM        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_FRM)         /* EMAC1 Rx ICMP Error Frames Register */
-#define pREG_EMAC1_RXIPV4_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV4_GD_OCT)          /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define pREG_EMAC1_RXIPV4_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV4_HDR_ERR_OCT)     /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define pREG_EMAC1_RXIPV4_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_NOPAY_OCT)       /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define pREG_EMAC1_RXIPV4_FRAG_OCT       ((volatile uint32_t *)REG_EMAC1_RXIPV4_FRAG_OCT)        /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define pREG_EMAC1_RXIPV4_UDSBL_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV4_UDSBL_OCT)       /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define pREG_EMAC1_RXIPV6_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXIPV6_GD_OCT)          /* EMAC1 Rx IPv6 Good Octets Register */
-#define pREG_EMAC1_RXIPV6_HDR_ERR_OCT    ((volatile uint32_t *)REG_EMAC1_RXIPV6_HDR_ERR_OCT)     /* EMAC1 Rx IPv6 Header Errors Register */
-#define pREG_EMAC1_RXIPV6_NOPAY_OCT      ((volatile uint32_t *)REG_EMAC1_RXIPV6_NOPAY_OCT)       /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define pREG_EMAC1_RXUDP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXUDP_GD_OCT)           /* EMAC1 Rx UDP Good Octets Register */
-#define pREG_EMAC1_RXUDP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXUDP_ERR_OCT)          /* EMAC1 Rx UDP Error Octets Register */
-#define pREG_EMAC1_RXTCP_GD_OCT          ((volatile uint32_t *)REG_EMAC1_RXTCP_GD_OCT)           /* EMAC1 Rx TCP Good Octets Register */
-#define pREG_EMAC1_RXTCP_ERR_OCT         ((volatile uint32_t *)REG_EMAC1_RXTCP_ERR_OCT)          /* EMAC1 Rx TCP Error Octets Register */
-#define pREG_EMAC1_RXICMP_GD_OCT         ((volatile uint32_t *)REG_EMAC1_RXICMP_GD_OCT)          /* EMAC1 Rx ICMP Good Octets Register */
-#define pREG_EMAC1_RXICMP_ERR_OCT        ((volatile uint32_t *)REG_EMAC1_RXICMP_ERR_OCT)         /* EMAC1 Rx ICMP Error Octets Register */
-#define pREG_EMAC1_TM_CTL                ((volatile uint32_t *)REG_EMAC1_TM_CTL)                 /* EMAC1 Time Stamp Control Register */
-#define pREG_EMAC1_TM_SUBSEC             ((volatile uint32_t *)REG_EMAC1_TM_SUBSEC)              /* EMAC1 Time Stamp Sub Second Increment Register */
-#define pREG_EMAC1_TM_SEC                ((volatile uint32_t *)REG_EMAC1_TM_SEC)                 /* EMAC1 Time Stamp Low Seconds Register */
-#define pREG_EMAC1_TM_NSEC               ((volatile uint32_t *)REG_EMAC1_TM_NSEC)                /* EMAC1 Time Stamp Nano Seconds Register */
-#define pREG_EMAC1_TM_SECUPDT            ((volatile uint32_t *)REG_EMAC1_TM_SECUPDT)             /* EMAC1 Time Stamp Seconds Update Register */
-#define pREG_EMAC1_TM_NSECUPDT           ((volatile uint32_t *)REG_EMAC1_TM_NSECUPDT)            /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define pREG_EMAC1_TM_ADDEND             ((volatile uint32_t *)REG_EMAC1_TM_ADDEND)              /* EMAC1 Time Stamp Addend Register */
-#define pREG_EMAC1_TM_TGTM               ((volatile uint32_t *)REG_EMAC1_TM_TGTM)                /* EMAC1 Time Stamp Target Time Seconds Register */
-#define pREG_EMAC1_TM_NTGTM              ((volatile uint32_t *)REG_EMAC1_TM_NTGTM)               /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define pREG_EMAC1_TM_HISEC              ((volatile uint32_t *)REG_EMAC1_TM_HISEC)               /* EMAC1 Time Stamp High Second Register */
-#define pREG_EMAC1_TM_STMPSTAT           ((volatile uint32_t *)REG_EMAC1_TM_STMPSTAT)            /* EMAC1 Time Stamp Status Register */
-#define pREG_EMAC1_TM_PPSCTL             ((volatile uint32_t *)REG_EMAC1_TM_PPSCTL)              /* EMAC1 PPS Control Register */
-#define pREG_EMAC1_TM_AUXSTMP_NSEC       ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_NSEC)        /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define pREG_EMAC1_TM_AUXSTMP_SEC        ((volatile uint32_t *)REG_EMAC1_TM_AUXSTMP_SEC)         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define pREG_EMAC1_TM_PPSINTVL           ((volatile uint32_t *)REG_EMAC1_TM_PPSINTVL)            /* EMAC1 Time Stamp PPS Interval Register */
-#define pREG_EMAC1_TM_PPSWIDTH           ((volatile uint32_t *)REG_EMAC1_TM_PPSWIDTH)            /* EMAC1 PPS Width Register */
-#define pREG_EMAC1_DMA_BUSMODE           ((volatile uint32_t *)REG_EMAC1_DMA_BUSMODE)            /* EMAC1 DMA Bus Mode Register */
-#define pREG_EMAC1_DMA_TXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_TXPOLL)             /* EMAC1 DMA Tx Poll Demand Register */
-#define pREG_EMAC1_DMA_RXPOLL            ((volatile uint32_t *)REG_EMAC1_DMA_RXPOLL)             /* EMAC1 DMA Rx Poll Demand register */
-#define pREG_EMAC1_DMA_RXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_ADDR)         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_TXDSC_ADDR        ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_ADDR)         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define pREG_EMAC1_DMA_STAT              ((volatile uint32_t *)REG_EMAC1_DMA_STAT)               /* EMAC1 DMA Status Register */
-#define pREG_EMAC1_DMA_OPMODE            ((volatile uint32_t *)REG_EMAC1_DMA_OPMODE)             /* EMAC1 DMA Operation Mode Register */
-#define pREG_EMAC1_DMA_IEN               ((volatile uint32_t *)REG_EMAC1_DMA_IEN)                /* EMAC1 DMA Interrupt Enable Register */
-#define pREG_EMAC1_DMA_MISS_FRM          ((volatile uint32_t *)REG_EMAC1_DMA_MISS_FRM)           /* EMAC1 DMA Missed Frame Register */
-#define pREG_EMAC1_DMA_RXIWDOG           ((volatile uint32_t *)REG_EMAC1_DMA_RXIWDOG)            /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define pREG_EMAC1_DMA_BMMODE            ((volatile uint32_t *)REG_EMAC1_DMA_BMMODE)             /* EMAC1 DMA SCB Bus Mode Register */
-#define pREG_EMAC1_DMA_BMSTAT            ((volatile uint32_t *)REG_EMAC1_DMA_BMSTAT)             /* EMAC1 DMA SCB Status Register */
-#define pREG_EMAC1_DMA_TXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXDSC_CUR)          /* EMAC1 DMA Tx Descriptor Current Register */
-#define pREG_EMAC1_DMA_RXDSC_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXDSC_CUR)          /* EMAC1 DMA Rx Descriptor Current Register */
-#define pREG_EMAC1_DMA_TXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_TXBUF_CUR)          /* EMAC1 DMA Tx Buffer Current Register */
-#define pREG_EMAC1_DMA_RXBUF_CUR         ((volatile uint32_t *)REG_EMAC1_DMA_RXBUF_CUR)          /* EMAC1 DMA Rx Buffer Current Register */
-
-
-/* =========================================================================
-       SPORT0
-   ========================================================================= */
-#define pREG_SPORT0_CTL_A                ((volatile uint32_t *)REG_SPORT0_CTL_A)                 /* SPORT0 Half SPORT 'A' Control Register */
-#define pREG_SPORT0_DIV_A                ((volatile uint32_t *)REG_SPORT0_DIV_A)                 /* SPORT0 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT0_MCTL_A               ((volatile uint32_t *)REG_SPORT0_MCTL_A)                /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_A                ((volatile uint32_t *)REG_SPORT0_CS0_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_A                ((volatile uint32_t *)REG_SPORT0_CS1_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_A                ((volatile uint32_t *)REG_SPORT0_CS2_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT0_CS3_A                ((volatile uint32_t *)REG_SPORT0_CS3_A)                 /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT0_ERR_A                ((volatile uint32_t *)REG_SPORT0_ERR_A)                 /* SPORT0 Half SPORT 'A' Error Register */
-#define pREG_SPORT0_MSTAT_A              ((volatile uint32_t *)REG_SPORT0_MSTAT_A)               /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_A               ((volatile uint32_t *)REG_SPORT0_CTL2_A)                /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT0_TXPRI_A              ((volatile uint32_t *)REG_SPORT0_TXPRI_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_A              ((volatile uint32_t *)REG_SPORT0_RXPRI_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_A              ((volatile uint32_t *)REG_SPORT0_TXSEC_A)               /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_A              ((volatile uint32_t *)REG_SPORT0_RXSEC_A)               /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT0_CTL_B                ((volatile uint32_t *)REG_SPORT0_CTL_B)                 /* SPORT0 Half SPORT 'B' Control Register */
-#define pREG_SPORT0_DIV_B                ((volatile uint32_t *)REG_SPORT0_DIV_B)                 /* SPORT0 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT0_MCTL_B               ((volatile uint32_t *)REG_SPORT0_MCTL_B)                /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT0_CS0_B                ((volatile uint32_t *)REG_SPORT0_CS0_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT0_CS1_B                ((volatile uint32_t *)REG_SPORT0_CS1_B)                 /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT0_CS2_B                ((volatile uint32_t *)REG_SPORT0_CS2_B)                 /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT0_CS3_B                ((volatile uint32_t *)REG_SPORT0_CS3_B)                 /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT0_ERR_B                ((volatile uint32_t *)REG_SPORT0_ERR_B)                 /* SPORT0 Half SPORT 'B' Error Register */
-#define pREG_SPORT0_MSTAT_B              ((volatile uint32_t *)REG_SPORT0_MSTAT_B)               /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT0_CTL2_B               ((volatile uint32_t *)REG_SPORT0_CTL2_B)                /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT0_TXPRI_B              ((volatile uint32_t *)REG_SPORT0_TXPRI_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT0_RXPRI_B              ((volatile uint32_t *)REG_SPORT0_RXPRI_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT0_TXSEC_B              ((volatile uint32_t *)REG_SPORT0_TXSEC_B)               /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT0_RXSEC_B              ((volatile uint32_t *)REG_SPORT0_RXSEC_B)               /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT1
-   ========================================================================= */
-#define pREG_SPORT1_CTL_A                ((volatile uint32_t *)REG_SPORT1_CTL_A)                 /* SPORT1 Half SPORT 'A' Control Register */
-#define pREG_SPORT1_DIV_A                ((volatile uint32_t *)REG_SPORT1_DIV_A)                 /* SPORT1 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT1_MCTL_A               ((volatile uint32_t *)REG_SPORT1_MCTL_A)                /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_A                ((volatile uint32_t *)REG_SPORT1_CS0_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_A                ((volatile uint32_t *)REG_SPORT1_CS1_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_A                ((volatile uint32_t *)REG_SPORT1_CS2_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT1_CS3_A                ((volatile uint32_t *)REG_SPORT1_CS3_A)                 /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT1_ERR_A                ((volatile uint32_t *)REG_SPORT1_ERR_A)                 /* SPORT1 Half SPORT 'A' Error Register */
-#define pREG_SPORT1_MSTAT_A              ((volatile uint32_t *)REG_SPORT1_MSTAT_A)               /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_A               ((volatile uint32_t *)REG_SPORT1_CTL2_A)                /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT1_TXPRI_A              ((volatile uint32_t *)REG_SPORT1_TXPRI_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_A              ((volatile uint32_t *)REG_SPORT1_RXPRI_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_A              ((volatile uint32_t *)REG_SPORT1_TXSEC_A)               /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_A              ((volatile uint32_t *)REG_SPORT1_RXSEC_A)               /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT1_CTL_B                ((volatile uint32_t *)REG_SPORT1_CTL_B)                 /* SPORT1 Half SPORT 'B' Control Register */
-#define pREG_SPORT1_DIV_B                ((volatile uint32_t *)REG_SPORT1_DIV_B)                 /* SPORT1 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT1_MCTL_B               ((volatile uint32_t *)REG_SPORT1_MCTL_B)                /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT1_CS0_B                ((volatile uint32_t *)REG_SPORT1_CS0_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT1_CS1_B                ((volatile uint32_t *)REG_SPORT1_CS1_B)                 /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT1_CS2_B                ((volatile uint32_t *)REG_SPORT1_CS2_B)                 /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT1_CS3_B                ((volatile uint32_t *)REG_SPORT1_CS3_B)                 /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT1_ERR_B                ((volatile uint32_t *)REG_SPORT1_ERR_B)                 /* SPORT1 Half SPORT 'B' Error Register */
-#define pREG_SPORT1_MSTAT_B              ((volatile uint32_t *)REG_SPORT1_MSTAT_B)               /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT1_CTL2_B               ((volatile uint32_t *)REG_SPORT1_CTL2_B)                /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT1_TXPRI_B              ((volatile uint32_t *)REG_SPORT1_TXPRI_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT1_RXPRI_B              ((volatile uint32_t *)REG_SPORT1_RXPRI_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT1_TXSEC_B              ((volatile uint32_t *)REG_SPORT1_TXSEC_B)               /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT1_RXSEC_B              ((volatile uint32_t *)REG_SPORT1_RXSEC_B)               /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================================================================
-       SPORT2
-   ========================================================================= */
-#define pREG_SPORT2_CTL_A                ((volatile uint32_t *)REG_SPORT2_CTL_A)                 /* SPORT2 Half SPORT 'A' Control Register */
-#define pREG_SPORT2_DIV_A                ((volatile uint32_t *)REG_SPORT2_DIV_A)                 /* SPORT2 Half SPORT 'A' Divisor Register */
-#define pREG_SPORT2_MCTL_A               ((volatile uint32_t *)REG_SPORT2_MCTL_A)                /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_A                ((volatile uint32_t *)REG_SPORT2_CS0_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_A                ((volatile uint32_t *)REG_SPORT2_CS1_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_A                ((volatile uint32_t *)REG_SPORT2_CS2_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define pREG_SPORT2_CS3_A                ((volatile uint32_t *)REG_SPORT2_CS3_A)                 /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define pREG_SPORT2_ERR_A                ((volatile uint32_t *)REG_SPORT2_ERR_A)                 /* SPORT2 Half SPORT 'A' Error Register */
-#define pREG_SPORT2_MSTAT_A              ((volatile uint32_t *)REG_SPORT2_MSTAT_A)               /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_A               ((volatile uint32_t *)REG_SPORT2_CTL2_A)                /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define pREG_SPORT2_TXPRI_A              ((volatile uint32_t *)REG_SPORT2_TXPRI_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_A              ((volatile uint32_t *)REG_SPORT2_RXPRI_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_A              ((volatile uint32_t *)REG_SPORT2_TXSEC_A)               /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_A              ((volatile uint32_t *)REG_SPORT2_RXSEC_A)               /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define pREG_SPORT2_CTL_B                ((volatile uint32_t *)REG_SPORT2_CTL_B)                 /* SPORT2 Half SPORT 'B' Control Register */
-#define pREG_SPORT2_DIV_B                ((volatile uint32_t *)REG_SPORT2_DIV_B)                 /* SPORT2 Half SPORT 'B' Divisor Register */
-#define pREG_SPORT2_MCTL_B               ((volatile uint32_t *)REG_SPORT2_MCTL_B)                /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define pREG_SPORT2_CS0_B                ((volatile uint32_t *)REG_SPORT2_CS0_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define pREG_SPORT2_CS1_B                ((volatile uint32_t *)REG_SPORT2_CS1_B)                 /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define pREG_SPORT2_CS2_B                ((volatile uint32_t *)REG_SPORT2_CS2_B)                 /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define pREG_SPORT2_CS3_B                ((volatile uint32_t *)REG_SPORT2_CS3_B)                 /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define pREG_SPORT2_ERR_B                ((volatile uint32_t *)REG_SPORT2_ERR_B)                 /* SPORT2 Half SPORT 'B' Error Register */
-#define pREG_SPORT2_MSTAT_B              ((volatile uint32_t *)REG_SPORT2_MSTAT_B)               /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define pREG_SPORT2_CTL2_B               ((volatile uint32_t *)REG_SPORT2_CTL2_B)                /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define pREG_SPORT2_TXPRI_B              ((volatile uint32_t *)REG_SPORT2_TXPRI_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define pREG_SPORT2_RXPRI_B              ((volatile uint32_t *)REG_SPORT2_RXPRI_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define pREG_SPORT2_TXSEC_B              ((volatile uint32_t *)REG_SPORT2_TXSEC_B)               /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define pREG_SPORT2_RXSEC_B              ((volatile uint32_t *)REG_SPORT2_RXSEC_B)               /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-
-/* =========================================================================
-       SPI0
-   ========================================================================= */
-#define pREG_SPI0_CTL                    ((volatile uint32_t *)REG_SPI0_CTL)                     /* SPI0 Control Register */
-#define pREG_SPI0_RXCTL                  ((volatile uint32_t *)REG_SPI0_RXCTL)                   /* SPI0 Receive Control Register */
-#define pREG_SPI0_TXCTL                  ((volatile uint32_t *)REG_SPI0_TXCTL)                   /* SPI0 Transmit Control Register */
-#define pREG_SPI0_CLK                    ((volatile uint32_t *)REG_SPI0_CLK)                     /* SPI0 Clock Rate Register */
-#define pREG_SPI0_DLY                    ((volatile uint32_t *)REG_SPI0_DLY)                     /* SPI0 Delay Register */
-#define pREG_SPI0_SLVSEL                 ((volatile uint32_t *)REG_SPI0_SLVSEL)                  /* SPI0 Slave Select Register */
-#define pREG_SPI0_RWC                    ((volatile uint32_t *)REG_SPI0_RWC)                     /* SPI0 Received Word Count Register */
-#define pREG_SPI0_RWCR                   ((volatile uint32_t *)REG_SPI0_RWCR)                    /* SPI0 Received Word Count Reload Register */
-#define pREG_SPI0_TWC                    ((volatile uint32_t *)REG_SPI0_TWC)                     /* SPI0 Transmitted Word Count Register */
-#define pREG_SPI0_TWCR                   ((volatile uint32_t *)REG_SPI0_TWCR)                    /* SPI0 Transmitted Word Count Reload Register */
-#define pREG_SPI0_IMSK                   ((volatile uint32_t *)REG_SPI0_IMSK)                    /* SPI0 Interrupt Mask Register */
-#define pREG_SPI0_IMSK_CLR               ((volatile uint32_t *)REG_SPI0_IMSK_CLR)                /* SPI0 Interrupt Mask Clear Register */
-#define pREG_SPI0_IMSK_SET               ((volatile uint32_t *)REG_SPI0_IMSK_SET)                /* SPI0 Interrupt Mask Set Register */
-#define pREG_SPI0_STAT                   ((volatile uint32_t *)REG_SPI0_STAT)                    /* SPI0 Status Register */
-#define pREG_SPI0_ILAT                   ((volatile uint32_t *)REG_SPI0_ILAT)                    /* SPI0 Masked Interrupt Condition Register */
-#define pREG_SPI0_ILAT_CLR               ((volatile uint32_t *)REG_SPI0_ILAT_CLR)                /* SPI0 Masked Interrupt Clear Register */
-#define pREG_SPI0_RFIFO                  ((volatile uint32_t *)REG_SPI0_RFIFO)                   /* SPI0 Receive FIFO Data Register */
-#define pREG_SPI0_TFIFO                  ((volatile uint32_t *)REG_SPI0_TFIFO)                   /* SPI0 Transmit FIFO Data Register */
-
-/* =========================================================================
-       SPI1
-   ========================================================================= */
-#define pREG_SPI1_CTL                    ((volatile uint32_t *)REG_SPI1_CTL)                     /* SPI1 Control Register */
-#define pREG_SPI1_RXCTL                  ((volatile uint32_t *)REG_SPI1_RXCTL)                   /* SPI1 Receive Control Register */
-#define pREG_SPI1_TXCTL                  ((volatile uint32_t *)REG_SPI1_TXCTL)                   /* SPI1 Transmit Control Register */
-#define pREG_SPI1_CLK                    ((volatile uint32_t *)REG_SPI1_CLK)                     /* SPI1 Clock Rate Register */
-#define pREG_SPI1_DLY                    ((volatile uint32_t *)REG_SPI1_DLY)                     /* SPI1 Delay Register */
-#define pREG_SPI1_SLVSEL                 ((volatile uint32_t *)REG_SPI1_SLVSEL)                  /* SPI1 Slave Select Register */
-#define pREG_SPI1_RWC                    ((volatile uint32_t *)REG_SPI1_RWC)                     /* SPI1 Received Word Count Register */
-#define pREG_SPI1_RWCR                   ((volatile uint32_t *)REG_SPI1_RWCR)                    /* SPI1 Received Word Count Reload Register */
-#define pREG_SPI1_TWC                    ((volatile uint32_t *)REG_SPI1_TWC)                     /* SPI1 Transmitted Word Count Register */
-#define pREG_SPI1_TWCR                   ((volatile uint32_t *)REG_SPI1_TWCR)                    /* SPI1 Transmitted Word Count Reload Register */
-#define pREG_SPI1_IMSK                   ((volatile uint32_t *)REG_SPI1_IMSK)                    /* SPI1 Interrupt Mask Register */
-#define pREG_SPI1_IMSK_CLR               ((volatile uint32_t *)REG_SPI1_IMSK_CLR)                /* SPI1 Interrupt Mask Clear Register */
-#define pREG_SPI1_IMSK_SET               ((volatile uint32_t *)REG_SPI1_IMSK_SET)                /* SPI1 Interrupt Mask Set Register */
-#define pREG_SPI1_STAT                   ((volatile uint32_t *)REG_SPI1_STAT)                    /* SPI1 Status Register */
-#define pREG_SPI1_ILAT                   ((volatile uint32_t *)REG_SPI1_ILAT)                    /* SPI1 Masked Interrupt Condition Register */
-#define pREG_SPI1_ILAT_CLR               ((volatile uint32_t *)REG_SPI1_ILAT_CLR)                /* SPI1 Masked Interrupt Clear Register */
-#define pREG_SPI1_RFIFO                  ((volatile uint32_t *)REG_SPI1_RFIFO)                   /* SPI1 Receive FIFO Data Register */
-#define pREG_SPI1_TFIFO                  ((volatile uint32_t *)REG_SPI1_TFIFO)                   /* SPI1 Transmit FIFO Data Register */
-
-
-/* =========================================================================
-       DMA0
-   ========================================================================= */
-#define pREG_DMA0_DSCPTR_NXT             ((void * volatile *)REG_DMA0_DSCPTR_NXT)                /* DMA0 Pointer to Next Initial Descriptor */
-#define pREG_DMA0_ADDRSTART              ((void * volatile *)REG_DMA0_ADDRSTART)                 /* DMA0 Start Address of Current Buffer */
-#define pREG_DMA0_CFG                    ((volatile uint32_t *)REG_DMA0_CFG)                     /* DMA0 Configuration Register */
-#define pREG_DMA0_XCNT                   ((volatile uint32_t *)REG_DMA0_XCNT)                    /* DMA0 Inner Loop Count Start Value */
-#define pREG_DMA0_XMOD                   ((volatile  int32_t *)REG_DMA0_XMOD)                    /* DMA0 Inner Loop Address Increment */
-#define pREG_DMA0_YCNT                   ((volatile uint32_t *)REG_DMA0_YCNT)                    /* DMA0 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA0_YMOD                   ((volatile  int32_t *)REG_DMA0_YMOD)                    /* DMA0 Outer Loop Address Increment (2D only) */
-#define pREG_DMA0_DSCPTR_CUR             ((void * volatile *)REG_DMA0_DSCPTR_CUR)                /* DMA0 Current Descriptor Pointer */
-#define pREG_DMA0_DSCPTR_PRV             ((void * volatile *)REG_DMA0_DSCPTR_PRV)                /* DMA0 Previous Initial Descriptor Pointer */
-#define pREG_DMA0_ADDR_CUR               ((void * volatile *)REG_DMA0_ADDR_CUR)                  /* DMA0 Current Address */
-#define pREG_DMA0_STAT                   ((volatile uint32_t *)REG_DMA0_STAT)                    /* DMA0 Status Register */
-#define pREG_DMA0_XCNT_CUR               ((volatile uint32_t *)REG_DMA0_XCNT_CUR)                /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA0_YCNT_CUR               ((volatile uint32_t *)REG_DMA0_YCNT_CUR)                /* DMA0 Current Row Count (2D only) */
-#define pREG_DMA0_BWLCNT                 ((volatile uint32_t *)REG_DMA0_BWLCNT)                  /* DMA0 Bandwidth Limit Count */
-#define pREG_DMA0_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWLCNT_CUR)              /* DMA0 Bandwidth Limit Count Current */
-#define pREG_DMA0_BWMCNT                 ((volatile uint32_t *)REG_DMA0_BWMCNT)                  /* DMA0 Bandwidth Monitor Count */
-#define pREG_DMA0_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA0_BWMCNT_CUR)              /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA1
-   ========================================================================= */
-#define pREG_DMA1_DSCPTR_NXT             ((void * volatile *)REG_DMA1_DSCPTR_NXT)                /* DMA1 Pointer to Next Initial Descriptor */
-#define pREG_DMA1_ADDRSTART              ((void * volatile *)REG_DMA1_ADDRSTART)                 /* DMA1 Start Address of Current Buffer */
-#define pREG_DMA1_CFG                    ((volatile uint32_t *)REG_DMA1_CFG)                     /* DMA1 Configuration Register */
-#define pREG_DMA1_XCNT                   ((volatile uint32_t *)REG_DMA1_XCNT)                    /* DMA1 Inner Loop Count Start Value */
-#define pREG_DMA1_XMOD                   ((volatile  int32_t *)REG_DMA1_XMOD)                    /* DMA1 Inner Loop Address Increment */
-#define pREG_DMA1_YCNT                   ((volatile uint32_t *)REG_DMA1_YCNT)                    /* DMA1 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA1_YMOD                   ((volatile  int32_t *)REG_DMA1_YMOD)                    /* DMA1 Outer Loop Address Increment (2D only) */
-#define pREG_DMA1_DSCPTR_CUR             ((void * volatile *)REG_DMA1_DSCPTR_CUR)                /* DMA1 Current Descriptor Pointer */
-#define pREG_DMA1_DSCPTR_PRV             ((void * volatile *)REG_DMA1_DSCPTR_PRV)                /* DMA1 Previous Initial Descriptor Pointer */
-#define pREG_DMA1_ADDR_CUR               ((void * volatile *)REG_DMA1_ADDR_CUR)                  /* DMA1 Current Address */
-#define pREG_DMA1_STAT                   ((volatile uint32_t *)REG_DMA1_STAT)                    /* DMA1 Status Register */
-#define pREG_DMA1_XCNT_CUR               ((volatile uint32_t *)REG_DMA1_XCNT_CUR)                /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA1_YCNT_CUR               ((volatile uint32_t *)REG_DMA1_YCNT_CUR)                /* DMA1 Current Row Count (2D only) */
-#define pREG_DMA1_BWLCNT                 ((volatile uint32_t *)REG_DMA1_BWLCNT)                  /* DMA1 Bandwidth Limit Count */
-#define pREG_DMA1_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWLCNT_CUR)              /* DMA1 Bandwidth Limit Count Current */
-#define pREG_DMA1_BWMCNT                 ((volatile uint32_t *)REG_DMA1_BWMCNT)                  /* DMA1 Bandwidth Monitor Count */
-#define pREG_DMA1_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA1_BWMCNT_CUR)              /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA2
-   ========================================================================= */
-#define pREG_DMA2_DSCPTR_NXT             ((void * volatile *)REG_DMA2_DSCPTR_NXT)                /* DMA2 Pointer to Next Initial Descriptor */
-#define pREG_DMA2_ADDRSTART              ((void * volatile *)REG_DMA2_ADDRSTART)                 /* DMA2 Start Address of Current Buffer */
-#define pREG_DMA2_CFG                    ((volatile uint32_t *)REG_DMA2_CFG)                     /* DMA2 Configuration Register */
-#define pREG_DMA2_XCNT                   ((volatile uint32_t *)REG_DMA2_XCNT)                    /* DMA2 Inner Loop Count Start Value */
-#define pREG_DMA2_XMOD                   ((volatile  int32_t *)REG_DMA2_XMOD)                    /* DMA2 Inner Loop Address Increment */
-#define pREG_DMA2_YCNT                   ((volatile uint32_t *)REG_DMA2_YCNT)                    /* DMA2 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA2_YMOD                   ((volatile  int32_t *)REG_DMA2_YMOD)                    /* DMA2 Outer Loop Address Increment (2D only) */
-#define pREG_DMA2_DSCPTR_CUR             ((void * volatile *)REG_DMA2_DSCPTR_CUR)                /* DMA2 Current Descriptor Pointer */
-#define pREG_DMA2_DSCPTR_PRV             ((void * volatile *)REG_DMA2_DSCPTR_PRV)                /* DMA2 Previous Initial Descriptor Pointer */
-#define pREG_DMA2_ADDR_CUR               ((void * volatile *)REG_DMA2_ADDR_CUR)                  /* DMA2 Current Address */
-#define pREG_DMA2_STAT                   ((volatile uint32_t *)REG_DMA2_STAT)                    /* DMA2 Status Register */
-#define pREG_DMA2_XCNT_CUR               ((volatile uint32_t *)REG_DMA2_XCNT_CUR)                /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA2_YCNT_CUR               ((volatile uint32_t *)REG_DMA2_YCNT_CUR)                /* DMA2 Current Row Count (2D only) */
-#define pREG_DMA2_BWLCNT                 ((volatile uint32_t *)REG_DMA2_BWLCNT)                  /* DMA2 Bandwidth Limit Count */
-#define pREG_DMA2_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWLCNT_CUR)              /* DMA2 Bandwidth Limit Count Current */
-#define pREG_DMA2_BWMCNT                 ((volatile uint32_t *)REG_DMA2_BWMCNT)                  /* DMA2 Bandwidth Monitor Count */
-#define pREG_DMA2_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA2_BWMCNT_CUR)              /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA3
-   ========================================================================= */
-#define pREG_DMA3_DSCPTR_NXT             ((void * volatile *)REG_DMA3_DSCPTR_NXT)                /* DMA3 Pointer to Next Initial Descriptor */
-#define pREG_DMA3_ADDRSTART              ((void * volatile *)REG_DMA3_ADDRSTART)                 /* DMA3 Start Address of Current Buffer */
-#define pREG_DMA3_CFG                    ((volatile uint32_t *)REG_DMA3_CFG)                     /* DMA3 Configuration Register */
-#define pREG_DMA3_XCNT                   ((volatile uint32_t *)REG_DMA3_XCNT)                    /* DMA3 Inner Loop Count Start Value */
-#define pREG_DMA3_XMOD                   ((volatile  int32_t *)REG_DMA3_XMOD)                    /* DMA3 Inner Loop Address Increment */
-#define pREG_DMA3_YCNT                   ((volatile uint32_t *)REG_DMA3_YCNT)                    /* DMA3 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA3_YMOD                   ((volatile  int32_t *)REG_DMA3_YMOD)                    /* DMA3 Outer Loop Address Increment (2D only) */
-#define pREG_DMA3_DSCPTR_CUR             ((void * volatile *)REG_DMA3_DSCPTR_CUR)                /* DMA3 Current Descriptor Pointer */
-#define pREG_DMA3_DSCPTR_PRV             ((void * volatile *)REG_DMA3_DSCPTR_PRV)                /* DMA3 Previous Initial Descriptor Pointer */
-#define pREG_DMA3_ADDR_CUR               ((void * volatile *)REG_DMA3_ADDR_CUR)                  /* DMA3 Current Address */
-#define pREG_DMA3_STAT                   ((volatile uint32_t *)REG_DMA3_STAT)                    /* DMA3 Status Register */
-#define pREG_DMA3_XCNT_CUR               ((volatile uint32_t *)REG_DMA3_XCNT_CUR)                /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA3_YCNT_CUR               ((volatile uint32_t *)REG_DMA3_YCNT_CUR)                /* DMA3 Current Row Count (2D only) */
-#define pREG_DMA3_BWLCNT                 ((volatile uint32_t *)REG_DMA3_BWLCNT)                  /* DMA3 Bandwidth Limit Count */
-#define pREG_DMA3_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWLCNT_CUR)              /* DMA3 Bandwidth Limit Count Current */
-#define pREG_DMA3_BWMCNT                 ((volatile uint32_t *)REG_DMA3_BWMCNT)                  /* DMA3 Bandwidth Monitor Count */
-#define pREG_DMA3_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA3_BWMCNT_CUR)              /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA4
-   ========================================================================= */
-#define pREG_DMA4_DSCPTR_NXT             ((void * volatile *)REG_DMA4_DSCPTR_NXT)                /* DMA4 Pointer to Next Initial Descriptor */
-#define pREG_DMA4_ADDRSTART              ((void * volatile *)REG_DMA4_ADDRSTART)                 /* DMA4 Start Address of Current Buffer */
-#define pREG_DMA4_CFG                    ((volatile uint32_t *)REG_DMA4_CFG)                     /* DMA4 Configuration Register */
-#define pREG_DMA4_XCNT                   ((volatile uint32_t *)REG_DMA4_XCNT)                    /* DMA4 Inner Loop Count Start Value */
-#define pREG_DMA4_XMOD                   ((volatile  int32_t *)REG_DMA4_XMOD)                    /* DMA4 Inner Loop Address Increment */
-#define pREG_DMA4_YCNT                   ((volatile uint32_t *)REG_DMA4_YCNT)                    /* DMA4 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA4_YMOD                   ((volatile  int32_t *)REG_DMA4_YMOD)                    /* DMA4 Outer Loop Address Increment (2D only) */
-#define pREG_DMA4_DSCPTR_CUR             ((void * volatile *)REG_DMA4_DSCPTR_CUR)                /* DMA4 Current Descriptor Pointer */
-#define pREG_DMA4_DSCPTR_PRV             ((void * volatile *)REG_DMA4_DSCPTR_PRV)                /* DMA4 Previous Initial Descriptor Pointer */
-#define pREG_DMA4_ADDR_CUR               ((void * volatile *)REG_DMA4_ADDR_CUR)                  /* DMA4 Current Address */
-#define pREG_DMA4_STAT                   ((volatile uint32_t *)REG_DMA4_STAT)                    /* DMA4 Status Register */
-#define pREG_DMA4_XCNT_CUR               ((volatile uint32_t *)REG_DMA4_XCNT_CUR)                /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA4_YCNT_CUR               ((volatile uint32_t *)REG_DMA4_YCNT_CUR)                /* DMA4 Current Row Count (2D only) */
-#define pREG_DMA4_BWLCNT                 ((volatile uint32_t *)REG_DMA4_BWLCNT)                  /* DMA4 Bandwidth Limit Count */
-#define pREG_DMA4_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWLCNT_CUR)              /* DMA4 Bandwidth Limit Count Current */
-#define pREG_DMA4_BWMCNT                 ((volatile uint32_t *)REG_DMA4_BWMCNT)                  /* DMA4 Bandwidth Monitor Count */
-#define pREG_DMA4_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA4_BWMCNT_CUR)              /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA5
-   ========================================================================= */
-#define pREG_DMA5_DSCPTR_NXT             ((void * volatile *)REG_DMA5_DSCPTR_NXT)                /* DMA5 Pointer to Next Initial Descriptor */
-#define pREG_DMA5_ADDRSTART              ((void * volatile *)REG_DMA5_ADDRSTART)                 /* DMA5 Start Address of Current Buffer */
-#define pREG_DMA5_CFG                    ((volatile uint32_t *)REG_DMA5_CFG)                     /* DMA5 Configuration Register */
-#define pREG_DMA5_XCNT                   ((volatile uint32_t *)REG_DMA5_XCNT)                    /* DMA5 Inner Loop Count Start Value */
-#define pREG_DMA5_XMOD                   ((volatile  int32_t *)REG_DMA5_XMOD)                    /* DMA5 Inner Loop Address Increment */
-#define pREG_DMA5_YCNT                   ((volatile uint32_t *)REG_DMA5_YCNT)                    /* DMA5 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA5_YMOD                   ((volatile  int32_t *)REG_DMA5_YMOD)                    /* DMA5 Outer Loop Address Increment (2D only) */
-#define pREG_DMA5_DSCPTR_CUR             ((void * volatile *)REG_DMA5_DSCPTR_CUR)                /* DMA5 Current Descriptor Pointer */
-#define pREG_DMA5_DSCPTR_PRV             ((void * volatile *)REG_DMA5_DSCPTR_PRV)                /* DMA5 Previous Initial Descriptor Pointer */
-#define pREG_DMA5_ADDR_CUR               ((void * volatile *)REG_DMA5_ADDR_CUR)                  /* DMA5 Current Address */
-#define pREG_DMA5_STAT                   ((volatile uint32_t *)REG_DMA5_STAT)                    /* DMA5 Status Register */
-#define pREG_DMA5_XCNT_CUR               ((volatile uint32_t *)REG_DMA5_XCNT_CUR)                /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA5_YCNT_CUR               ((volatile uint32_t *)REG_DMA5_YCNT_CUR)                /* DMA5 Current Row Count (2D only) */
-#define pREG_DMA5_BWLCNT                 ((volatile uint32_t *)REG_DMA5_BWLCNT)                  /* DMA5 Bandwidth Limit Count */
-#define pREG_DMA5_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWLCNT_CUR)              /* DMA5 Bandwidth Limit Count Current */
-#define pREG_DMA5_BWMCNT                 ((volatile uint32_t *)REG_DMA5_BWMCNT)                  /* DMA5 Bandwidth Monitor Count */
-#define pREG_DMA5_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA5_BWMCNT_CUR)              /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA6
-   ========================================================================= */
-#define pREG_DMA6_DSCPTR_NXT             ((void * volatile *)REG_DMA6_DSCPTR_NXT)                /* DMA6 Pointer to Next Initial Descriptor */
-#define pREG_DMA6_ADDRSTART              ((void * volatile *)REG_DMA6_ADDRSTART)                 /* DMA6 Start Address of Current Buffer */
-#define pREG_DMA6_CFG                    ((volatile uint32_t *)REG_DMA6_CFG)                     /* DMA6 Configuration Register */
-#define pREG_DMA6_XCNT                   ((volatile uint32_t *)REG_DMA6_XCNT)                    /* DMA6 Inner Loop Count Start Value */
-#define pREG_DMA6_XMOD                   ((volatile  int32_t *)REG_DMA6_XMOD)                    /* DMA6 Inner Loop Address Increment */
-#define pREG_DMA6_YCNT                   ((volatile uint32_t *)REG_DMA6_YCNT)                    /* DMA6 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA6_YMOD                   ((volatile  int32_t *)REG_DMA6_YMOD)                    /* DMA6 Outer Loop Address Increment (2D only) */
-#define pREG_DMA6_DSCPTR_CUR             ((void * volatile *)REG_DMA6_DSCPTR_CUR)                /* DMA6 Current Descriptor Pointer */
-#define pREG_DMA6_DSCPTR_PRV             ((void * volatile *)REG_DMA6_DSCPTR_PRV)                /* DMA6 Previous Initial Descriptor Pointer */
-#define pREG_DMA6_ADDR_CUR               ((void * volatile *)REG_DMA6_ADDR_CUR)                  /* DMA6 Current Address */
-#define pREG_DMA6_STAT                   ((volatile uint32_t *)REG_DMA6_STAT)                    /* DMA6 Status Register */
-#define pREG_DMA6_XCNT_CUR               ((volatile uint32_t *)REG_DMA6_XCNT_CUR)                /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA6_YCNT_CUR               ((volatile uint32_t *)REG_DMA6_YCNT_CUR)                /* DMA6 Current Row Count (2D only) */
-#define pREG_DMA6_BWLCNT                 ((volatile uint32_t *)REG_DMA6_BWLCNT)                  /* DMA6 Bandwidth Limit Count */
-#define pREG_DMA6_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWLCNT_CUR)              /* DMA6 Bandwidth Limit Count Current */
-#define pREG_DMA6_BWMCNT                 ((volatile uint32_t *)REG_DMA6_BWMCNT)                  /* DMA6 Bandwidth Monitor Count */
-#define pREG_DMA6_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA6_BWMCNT_CUR)              /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA7
-   ========================================================================= */
-#define pREG_DMA7_DSCPTR_NXT             ((void * volatile *)REG_DMA7_DSCPTR_NXT)                /* DMA7 Pointer to Next Initial Descriptor */
-#define pREG_DMA7_ADDRSTART              ((void * volatile *)REG_DMA7_ADDRSTART)                 /* DMA7 Start Address of Current Buffer */
-#define pREG_DMA7_CFG                    ((volatile uint32_t *)REG_DMA7_CFG)                     /* DMA7 Configuration Register */
-#define pREG_DMA7_XCNT                   ((volatile uint32_t *)REG_DMA7_XCNT)                    /* DMA7 Inner Loop Count Start Value */
-#define pREG_DMA7_XMOD                   ((volatile  int32_t *)REG_DMA7_XMOD)                    /* DMA7 Inner Loop Address Increment */
-#define pREG_DMA7_YCNT                   ((volatile uint32_t *)REG_DMA7_YCNT)                    /* DMA7 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA7_YMOD                   ((volatile  int32_t *)REG_DMA7_YMOD)                    /* DMA7 Outer Loop Address Increment (2D only) */
-#define pREG_DMA7_DSCPTR_CUR             ((void * volatile *)REG_DMA7_DSCPTR_CUR)                /* DMA7 Current Descriptor Pointer */
-#define pREG_DMA7_DSCPTR_PRV             ((void * volatile *)REG_DMA7_DSCPTR_PRV)                /* DMA7 Previous Initial Descriptor Pointer */
-#define pREG_DMA7_ADDR_CUR               ((void * volatile *)REG_DMA7_ADDR_CUR)                  /* DMA7 Current Address */
-#define pREG_DMA7_STAT                   ((volatile uint32_t *)REG_DMA7_STAT)                    /* DMA7 Status Register */
-#define pREG_DMA7_XCNT_CUR               ((volatile uint32_t *)REG_DMA7_XCNT_CUR)                /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA7_YCNT_CUR               ((volatile uint32_t *)REG_DMA7_YCNT_CUR)                /* DMA7 Current Row Count (2D only) */
-#define pREG_DMA7_BWLCNT                 ((volatile uint32_t *)REG_DMA7_BWLCNT)                  /* DMA7 Bandwidth Limit Count */
-#define pREG_DMA7_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWLCNT_CUR)              /* DMA7 Bandwidth Limit Count Current */
-#define pREG_DMA7_BWMCNT                 ((volatile uint32_t *)REG_DMA7_BWMCNT)                  /* DMA7 Bandwidth Monitor Count */
-#define pREG_DMA7_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA7_BWMCNT_CUR)              /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA8
-   ========================================================================= */
-#define pREG_DMA8_DSCPTR_NXT             ((void * volatile *)REG_DMA8_DSCPTR_NXT)                /* DMA8 Pointer to Next Initial Descriptor */
-#define pREG_DMA8_ADDRSTART              ((void * volatile *)REG_DMA8_ADDRSTART)                 /* DMA8 Start Address of Current Buffer */
-#define pREG_DMA8_CFG                    ((volatile uint32_t *)REG_DMA8_CFG)                     /* DMA8 Configuration Register */
-#define pREG_DMA8_XCNT                   ((volatile uint32_t *)REG_DMA8_XCNT)                    /* DMA8 Inner Loop Count Start Value */
-#define pREG_DMA8_XMOD                   ((volatile  int32_t *)REG_DMA8_XMOD)                    /* DMA8 Inner Loop Address Increment */
-#define pREG_DMA8_YCNT                   ((volatile uint32_t *)REG_DMA8_YCNT)                    /* DMA8 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA8_YMOD                   ((volatile  int32_t *)REG_DMA8_YMOD)                    /* DMA8 Outer Loop Address Increment (2D only) */
-#define pREG_DMA8_DSCPTR_CUR             ((void * volatile *)REG_DMA8_DSCPTR_CUR)                /* DMA8 Current Descriptor Pointer */
-#define pREG_DMA8_DSCPTR_PRV             ((void * volatile *)REG_DMA8_DSCPTR_PRV)                /* DMA8 Previous Initial Descriptor Pointer */
-#define pREG_DMA8_ADDR_CUR               ((void * volatile *)REG_DMA8_ADDR_CUR)                  /* DMA8 Current Address */
-#define pREG_DMA8_STAT                   ((volatile uint32_t *)REG_DMA8_STAT)                    /* DMA8 Status Register */
-#define pREG_DMA8_XCNT_CUR               ((volatile uint32_t *)REG_DMA8_XCNT_CUR)                /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA8_YCNT_CUR               ((volatile uint32_t *)REG_DMA8_YCNT_CUR)                /* DMA8 Current Row Count (2D only) */
-#define pREG_DMA8_BWLCNT                 ((volatile uint32_t *)REG_DMA8_BWLCNT)                  /* DMA8 Bandwidth Limit Count */
-#define pREG_DMA8_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWLCNT_CUR)              /* DMA8 Bandwidth Limit Count Current */
-#define pREG_DMA8_BWMCNT                 ((volatile uint32_t *)REG_DMA8_BWMCNT)                  /* DMA8 Bandwidth Monitor Count */
-#define pREG_DMA8_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA8_BWMCNT_CUR)              /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA9
-   ========================================================================= */
-#define pREG_DMA9_DSCPTR_NXT             ((void * volatile *)REG_DMA9_DSCPTR_NXT)                /* DMA9 Pointer to Next Initial Descriptor */
-#define pREG_DMA9_ADDRSTART              ((void * volatile *)REG_DMA9_ADDRSTART)                 /* DMA9 Start Address of Current Buffer */
-#define pREG_DMA9_CFG                    ((volatile uint32_t *)REG_DMA9_CFG)                     /* DMA9 Configuration Register */
-#define pREG_DMA9_XCNT                   ((volatile uint32_t *)REG_DMA9_XCNT)                    /* DMA9 Inner Loop Count Start Value */
-#define pREG_DMA9_XMOD                   ((volatile  int32_t *)REG_DMA9_XMOD)                    /* DMA9 Inner Loop Address Increment */
-#define pREG_DMA9_YCNT                   ((volatile uint32_t *)REG_DMA9_YCNT)                    /* DMA9 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA9_YMOD                   ((volatile  int32_t *)REG_DMA9_YMOD)                    /* DMA9 Outer Loop Address Increment (2D only) */
-#define pREG_DMA9_DSCPTR_CUR             ((void * volatile *)REG_DMA9_DSCPTR_CUR)                /* DMA9 Current Descriptor Pointer */
-#define pREG_DMA9_DSCPTR_PRV             ((void * volatile *)REG_DMA9_DSCPTR_PRV)                /* DMA9 Previous Initial Descriptor Pointer */
-#define pREG_DMA9_ADDR_CUR               ((void * volatile *)REG_DMA9_ADDR_CUR)                  /* DMA9 Current Address */
-#define pREG_DMA9_STAT                   ((volatile uint32_t *)REG_DMA9_STAT)                    /* DMA9 Status Register */
-#define pREG_DMA9_XCNT_CUR               ((volatile uint32_t *)REG_DMA9_XCNT_CUR)                /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA9_YCNT_CUR               ((volatile uint32_t *)REG_DMA9_YCNT_CUR)                /* DMA9 Current Row Count (2D only) */
-#define pREG_DMA9_BWLCNT                 ((volatile uint32_t *)REG_DMA9_BWLCNT)                  /* DMA9 Bandwidth Limit Count */
-#define pREG_DMA9_BWLCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWLCNT_CUR)              /* DMA9 Bandwidth Limit Count Current */
-#define pREG_DMA9_BWMCNT                 ((volatile uint32_t *)REG_DMA9_BWMCNT)                  /* DMA9 Bandwidth Monitor Count */
-#define pREG_DMA9_BWMCNT_CUR             ((volatile uint32_t *)REG_DMA9_BWMCNT_CUR)              /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA10
-   ========================================================================= */
-#define pREG_DMA10_DSCPTR_NXT            ((void * volatile *)REG_DMA10_DSCPTR_NXT)               /* DMA10 Pointer to Next Initial Descriptor */
-#define pREG_DMA10_ADDRSTART             ((void * volatile *)REG_DMA10_ADDRSTART)                /* DMA10 Start Address of Current Buffer */
-#define pREG_DMA10_CFG                   ((volatile uint32_t *)REG_DMA10_CFG)                    /* DMA10 Configuration Register */
-#define pREG_DMA10_XCNT                  ((volatile uint32_t *)REG_DMA10_XCNT)                   /* DMA10 Inner Loop Count Start Value */
-#define pREG_DMA10_XMOD                  ((volatile  int32_t *)REG_DMA10_XMOD)                   /* DMA10 Inner Loop Address Increment */
-#define pREG_DMA10_YCNT                  ((volatile uint32_t *)REG_DMA10_YCNT)                   /* DMA10 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA10_YMOD                  ((volatile  int32_t *)REG_DMA10_YMOD)                   /* DMA10 Outer Loop Address Increment (2D only) */
-#define pREG_DMA10_DSCPTR_CUR            ((void * volatile *)REG_DMA10_DSCPTR_CUR)               /* DMA10 Current Descriptor Pointer */
-#define pREG_DMA10_DSCPTR_PRV            ((void * volatile *)REG_DMA10_DSCPTR_PRV)               /* DMA10 Previous Initial Descriptor Pointer */
-#define pREG_DMA10_ADDR_CUR              ((void * volatile *)REG_DMA10_ADDR_CUR)                 /* DMA10 Current Address */
-#define pREG_DMA10_STAT                  ((volatile uint32_t *)REG_DMA10_STAT)                   /* DMA10 Status Register */
-#define pREG_DMA10_XCNT_CUR              ((volatile uint32_t *)REG_DMA10_XCNT_CUR)               /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA10_YCNT_CUR              ((volatile uint32_t *)REG_DMA10_YCNT_CUR)               /* DMA10 Current Row Count (2D only) */
-#define pREG_DMA10_BWLCNT                ((volatile uint32_t *)REG_DMA10_BWLCNT)                 /* DMA10 Bandwidth Limit Count */
-#define pREG_DMA10_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWLCNT_CUR)             /* DMA10 Bandwidth Limit Count Current */
-#define pREG_DMA10_BWMCNT                ((volatile uint32_t *)REG_DMA10_BWMCNT)                 /* DMA10 Bandwidth Monitor Count */
-#define pREG_DMA10_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA10_BWMCNT_CUR)             /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA11
-   ========================================================================= */
-#define pREG_DMA11_DSCPTR_NXT            ((void * volatile *)REG_DMA11_DSCPTR_NXT)               /* DMA11 Pointer to Next Initial Descriptor */
-#define pREG_DMA11_ADDRSTART             ((void * volatile *)REG_DMA11_ADDRSTART)                /* DMA11 Start Address of Current Buffer */
-#define pREG_DMA11_CFG                   ((volatile uint32_t *)REG_DMA11_CFG)                    /* DMA11 Configuration Register */
-#define pREG_DMA11_XCNT                  ((volatile uint32_t *)REG_DMA11_XCNT)                   /* DMA11 Inner Loop Count Start Value */
-#define pREG_DMA11_XMOD                  ((volatile  int32_t *)REG_DMA11_XMOD)                   /* DMA11 Inner Loop Address Increment */
-#define pREG_DMA11_YCNT                  ((volatile uint32_t *)REG_DMA11_YCNT)                   /* DMA11 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA11_YMOD                  ((volatile  int32_t *)REG_DMA11_YMOD)                   /* DMA11 Outer Loop Address Increment (2D only) */
-#define pREG_DMA11_DSCPTR_CUR            ((void * volatile *)REG_DMA11_DSCPTR_CUR)               /* DMA11 Current Descriptor Pointer */
-#define pREG_DMA11_DSCPTR_PRV            ((void * volatile *)REG_DMA11_DSCPTR_PRV)               /* DMA11 Previous Initial Descriptor Pointer */
-#define pREG_DMA11_ADDR_CUR              ((void * volatile *)REG_DMA11_ADDR_CUR)                 /* DMA11 Current Address */
-#define pREG_DMA11_STAT                  ((volatile uint32_t *)REG_DMA11_STAT)                   /* DMA11 Status Register */
-#define pREG_DMA11_XCNT_CUR              ((volatile uint32_t *)REG_DMA11_XCNT_CUR)               /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA11_YCNT_CUR              ((volatile uint32_t *)REG_DMA11_YCNT_CUR)               /* DMA11 Current Row Count (2D only) */
-#define pREG_DMA11_BWLCNT                ((volatile uint32_t *)REG_DMA11_BWLCNT)                 /* DMA11 Bandwidth Limit Count */
-#define pREG_DMA11_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWLCNT_CUR)             /* DMA11 Bandwidth Limit Count Current */
-#define pREG_DMA11_BWMCNT                ((volatile uint32_t *)REG_DMA11_BWMCNT)                 /* DMA11 Bandwidth Monitor Count */
-#define pREG_DMA11_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA11_BWMCNT_CUR)             /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA12
-   ========================================================================= */
-#define pREG_DMA12_DSCPTR_NXT            ((void * volatile *)REG_DMA12_DSCPTR_NXT)               /* DMA12 Pointer to Next Initial Descriptor */
-#define pREG_DMA12_ADDRSTART             ((void * volatile *)REG_DMA12_ADDRSTART)                /* DMA12 Start Address of Current Buffer */
-#define pREG_DMA12_CFG                   ((volatile uint32_t *)REG_DMA12_CFG)                    /* DMA12 Configuration Register */
-#define pREG_DMA12_XCNT                  ((volatile uint32_t *)REG_DMA12_XCNT)                   /* DMA12 Inner Loop Count Start Value */
-#define pREG_DMA12_XMOD                  ((volatile  int32_t *)REG_DMA12_XMOD)                   /* DMA12 Inner Loop Address Increment */
-#define pREG_DMA12_YCNT                  ((volatile uint32_t *)REG_DMA12_YCNT)                   /* DMA12 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA12_YMOD                  ((volatile  int32_t *)REG_DMA12_YMOD)                   /* DMA12 Outer Loop Address Increment (2D only) */
-#define pREG_DMA12_DSCPTR_CUR            ((void * volatile *)REG_DMA12_DSCPTR_CUR)               /* DMA12 Current Descriptor Pointer */
-#define pREG_DMA12_DSCPTR_PRV            ((void * volatile *)REG_DMA12_DSCPTR_PRV)               /* DMA12 Previous Initial Descriptor Pointer */
-#define pREG_DMA12_ADDR_CUR              ((void * volatile *)REG_DMA12_ADDR_CUR)                 /* DMA12 Current Address */
-#define pREG_DMA12_STAT                  ((volatile uint32_t *)REG_DMA12_STAT)                   /* DMA12 Status Register */
-#define pREG_DMA12_XCNT_CUR              ((volatile uint32_t *)REG_DMA12_XCNT_CUR)               /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA12_YCNT_CUR              ((volatile uint32_t *)REG_DMA12_YCNT_CUR)               /* DMA12 Current Row Count (2D only) */
-#define pREG_DMA12_BWLCNT                ((volatile uint32_t *)REG_DMA12_BWLCNT)                 /* DMA12 Bandwidth Limit Count */
-#define pREG_DMA12_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWLCNT_CUR)             /* DMA12 Bandwidth Limit Count Current */
-#define pREG_DMA12_BWMCNT                ((volatile uint32_t *)REG_DMA12_BWMCNT)                 /* DMA12 Bandwidth Monitor Count */
-#define pREG_DMA12_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA12_BWMCNT_CUR)             /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA13
-   ========================================================================= */
-#define pREG_DMA13_DSCPTR_NXT            ((void * volatile *)REG_DMA13_DSCPTR_NXT)               /* DMA13 Pointer to Next Initial Descriptor */
-#define pREG_DMA13_ADDRSTART             ((void * volatile *)REG_DMA13_ADDRSTART)                /* DMA13 Start Address of Current Buffer */
-#define pREG_DMA13_CFG                   ((volatile uint32_t *)REG_DMA13_CFG)                    /* DMA13 Configuration Register */
-#define pREG_DMA13_XCNT                  ((volatile uint32_t *)REG_DMA13_XCNT)                   /* DMA13 Inner Loop Count Start Value */
-#define pREG_DMA13_XMOD                  ((volatile  int32_t *)REG_DMA13_XMOD)                   /* DMA13 Inner Loop Address Increment */
-#define pREG_DMA13_YCNT                  ((volatile uint32_t *)REG_DMA13_YCNT)                   /* DMA13 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA13_YMOD                  ((volatile  int32_t *)REG_DMA13_YMOD)                   /* DMA13 Outer Loop Address Increment (2D only) */
-#define pREG_DMA13_DSCPTR_CUR            ((void * volatile *)REG_DMA13_DSCPTR_CUR)               /* DMA13 Current Descriptor Pointer */
-#define pREG_DMA13_DSCPTR_PRV            ((void * volatile *)REG_DMA13_DSCPTR_PRV)               /* DMA13 Previous Initial Descriptor Pointer */
-#define pREG_DMA13_ADDR_CUR              ((void * volatile *)REG_DMA13_ADDR_CUR)                 /* DMA13 Current Address */
-#define pREG_DMA13_STAT                  ((volatile uint32_t *)REG_DMA13_STAT)                   /* DMA13 Status Register */
-#define pREG_DMA13_XCNT_CUR              ((volatile uint32_t *)REG_DMA13_XCNT_CUR)               /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA13_YCNT_CUR              ((volatile uint32_t *)REG_DMA13_YCNT_CUR)               /* DMA13 Current Row Count (2D only) */
-#define pREG_DMA13_BWLCNT                ((volatile uint32_t *)REG_DMA13_BWLCNT)                 /* DMA13 Bandwidth Limit Count */
-#define pREG_DMA13_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWLCNT_CUR)             /* DMA13 Bandwidth Limit Count Current */
-#define pREG_DMA13_BWMCNT                ((volatile uint32_t *)REG_DMA13_BWMCNT)                 /* DMA13 Bandwidth Monitor Count */
-#define pREG_DMA13_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA13_BWMCNT_CUR)             /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA14
-   ========================================================================= */
-#define pREG_DMA14_DSCPTR_NXT            ((void * volatile *)REG_DMA14_DSCPTR_NXT)               /* DMA14 Pointer to Next Initial Descriptor */
-#define pREG_DMA14_ADDRSTART             ((void * volatile *)REG_DMA14_ADDRSTART)                /* DMA14 Start Address of Current Buffer */
-#define pREG_DMA14_CFG                   ((volatile uint32_t *)REG_DMA14_CFG)                    /* DMA14 Configuration Register */
-#define pREG_DMA14_XCNT                  ((volatile uint32_t *)REG_DMA14_XCNT)                   /* DMA14 Inner Loop Count Start Value */
-#define pREG_DMA14_XMOD                  ((volatile  int32_t *)REG_DMA14_XMOD)                   /* DMA14 Inner Loop Address Increment */
-#define pREG_DMA14_YCNT                  ((volatile uint32_t *)REG_DMA14_YCNT)                   /* DMA14 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA14_YMOD                  ((volatile  int32_t *)REG_DMA14_YMOD)                   /* DMA14 Outer Loop Address Increment (2D only) */
-#define pREG_DMA14_DSCPTR_CUR            ((void * volatile *)REG_DMA14_DSCPTR_CUR)               /* DMA14 Current Descriptor Pointer */
-#define pREG_DMA14_DSCPTR_PRV            ((void * volatile *)REG_DMA14_DSCPTR_PRV)               /* DMA14 Previous Initial Descriptor Pointer */
-#define pREG_DMA14_ADDR_CUR              ((void * volatile *)REG_DMA14_ADDR_CUR)                 /* DMA14 Current Address */
-#define pREG_DMA14_STAT                  ((volatile uint32_t *)REG_DMA14_STAT)                   /* DMA14 Status Register */
-#define pREG_DMA14_XCNT_CUR              ((volatile uint32_t *)REG_DMA14_XCNT_CUR)               /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA14_YCNT_CUR              ((volatile uint32_t *)REG_DMA14_YCNT_CUR)               /* DMA14 Current Row Count (2D only) */
-#define pREG_DMA14_BWLCNT                ((volatile uint32_t *)REG_DMA14_BWLCNT)                 /* DMA14 Bandwidth Limit Count */
-#define pREG_DMA14_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWLCNT_CUR)             /* DMA14 Bandwidth Limit Count Current */
-#define pREG_DMA14_BWMCNT                ((volatile uint32_t *)REG_DMA14_BWMCNT)                 /* DMA14 Bandwidth Monitor Count */
-#define pREG_DMA14_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA14_BWMCNT_CUR)             /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA15
-   ========================================================================= */
-#define pREG_DMA15_DSCPTR_NXT            ((void * volatile *)REG_DMA15_DSCPTR_NXT)               /* DMA15 Pointer to Next Initial Descriptor */
-#define pREG_DMA15_ADDRSTART             ((void * volatile *)REG_DMA15_ADDRSTART)                /* DMA15 Start Address of Current Buffer */
-#define pREG_DMA15_CFG                   ((volatile uint32_t *)REG_DMA15_CFG)                    /* DMA15 Configuration Register */
-#define pREG_DMA15_XCNT                  ((volatile uint32_t *)REG_DMA15_XCNT)                   /* DMA15 Inner Loop Count Start Value */
-#define pREG_DMA15_XMOD                  ((volatile  int32_t *)REG_DMA15_XMOD)                   /* DMA15 Inner Loop Address Increment */
-#define pREG_DMA15_YCNT                  ((volatile uint32_t *)REG_DMA15_YCNT)                   /* DMA15 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA15_YMOD                  ((volatile  int32_t *)REG_DMA15_YMOD)                   /* DMA15 Outer Loop Address Increment (2D only) */
-#define pREG_DMA15_DSCPTR_CUR            ((void * volatile *)REG_DMA15_DSCPTR_CUR)               /* DMA15 Current Descriptor Pointer */
-#define pREG_DMA15_DSCPTR_PRV            ((void * volatile *)REG_DMA15_DSCPTR_PRV)               /* DMA15 Previous Initial Descriptor Pointer */
-#define pREG_DMA15_ADDR_CUR              ((void * volatile *)REG_DMA15_ADDR_CUR)                 /* DMA15 Current Address */
-#define pREG_DMA15_STAT                  ((volatile uint32_t *)REG_DMA15_STAT)                   /* DMA15 Status Register */
-#define pREG_DMA15_XCNT_CUR              ((volatile uint32_t *)REG_DMA15_XCNT_CUR)               /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA15_YCNT_CUR              ((volatile uint32_t *)REG_DMA15_YCNT_CUR)               /* DMA15 Current Row Count (2D only) */
-#define pREG_DMA15_BWLCNT                ((volatile uint32_t *)REG_DMA15_BWLCNT)                 /* DMA15 Bandwidth Limit Count */
-#define pREG_DMA15_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWLCNT_CUR)             /* DMA15 Bandwidth Limit Count Current */
-#define pREG_DMA15_BWMCNT                ((volatile uint32_t *)REG_DMA15_BWMCNT)                 /* DMA15 Bandwidth Monitor Count */
-#define pREG_DMA15_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA15_BWMCNT_CUR)             /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA16
-   ========================================================================= */
-#define pREG_DMA16_DSCPTR_NXT            ((void * volatile *)REG_DMA16_DSCPTR_NXT)               /* DMA16 Pointer to Next Initial Descriptor */
-#define pREG_DMA16_ADDRSTART             ((void * volatile *)REG_DMA16_ADDRSTART)                /* DMA16 Start Address of Current Buffer */
-#define pREG_DMA16_CFG                   ((volatile uint32_t *)REG_DMA16_CFG)                    /* DMA16 Configuration Register */
-#define pREG_DMA16_XCNT                  ((volatile uint32_t *)REG_DMA16_XCNT)                   /* DMA16 Inner Loop Count Start Value */
-#define pREG_DMA16_XMOD                  ((volatile  int32_t *)REG_DMA16_XMOD)                   /* DMA16 Inner Loop Address Increment */
-#define pREG_DMA16_YCNT                  ((volatile uint32_t *)REG_DMA16_YCNT)                   /* DMA16 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA16_YMOD                  ((volatile  int32_t *)REG_DMA16_YMOD)                   /* DMA16 Outer Loop Address Increment (2D only) */
-#define pREG_DMA16_DSCPTR_CUR            ((void * volatile *)REG_DMA16_DSCPTR_CUR)               /* DMA16 Current Descriptor Pointer */
-#define pREG_DMA16_DSCPTR_PRV            ((void * volatile *)REG_DMA16_DSCPTR_PRV)               /* DMA16 Previous Initial Descriptor Pointer */
-#define pREG_DMA16_ADDR_CUR              ((void * volatile *)REG_DMA16_ADDR_CUR)                 /* DMA16 Current Address */
-#define pREG_DMA16_STAT                  ((volatile uint32_t *)REG_DMA16_STAT)                   /* DMA16 Status Register */
-#define pREG_DMA16_XCNT_CUR              ((volatile uint32_t *)REG_DMA16_XCNT_CUR)               /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA16_YCNT_CUR              ((volatile uint32_t *)REG_DMA16_YCNT_CUR)               /* DMA16 Current Row Count (2D only) */
-#define pREG_DMA16_BWLCNT                ((volatile uint32_t *)REG_DMA16_BWLCNT)                 /* DMA16 Bandwidth Limit Count */
-#define pREG_DMA16_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWLCNT_CUR)             /* DMA16 Bandwidth Limit Count Current */
-#define pREG_DMA16_BWMCNT                ((volatile uint32_t *)REG_DMA16_BWMCNT)                 /* DMA16 Bandwidth Monitor Count */
-#define pREG_DMA16_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA16_BWMCNT_CUR)             /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA17
-   ========================================================================= */
-#define pREG_DMA17_DSCPTR_NXT            ((void * volatile *)REG_DMA17_DSCPTR_NXT)               /* DMA17 Pointer to Next Initial Descriptor */
-#define pREG_DMA17_ADDRSTART             ((void * volatile *)REG_DMA17_ADDRSTART)                /* DMA17 Start Address of Current Buffer */
-#define pREG_DMA17_CFG                   ((volatile uint32_t *)REG_DMA17_CFG)                    /* DMA17 Configuration Register */
-#define pREG_DMA17_XCNT                  ((volatile uint32_t *)REG_DMA17_XCNT)                   /* DMA17 Inner Loop Count Start Value */
-#define pREG_DMA17_XMOD                  ((volatile  int32_t *)REG_DMA17_XMOD)                   /* DMA17 Inner Loop Address Increment */
-#define pREG_DMA17_YCNT                  ((volatile uint32_t *)REG_DMA17_YCNT)                   /* DMA17 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA17_YMOD                  ((volatile  int32_t *)REG_DMA17_YMOD)                   /* DMA17 Outer Loop Address Increment (2D only) */
-#define pREG_DMA17_DSCPTR_CUR            ((void * volatile *)REG_DMA17_DSCPTR_CUR)               /* DMA17 Current Descriptor Pointer */
-#define pREG_DMA17_DSCPTR_PRV            ((void * volatile *)REG_DMA17_DSCPTR_PRV)               /* DMA17 Previous Initial Descriptor Pointer */
-#define pREG_DMA17_ADDR_CUR              ((void * volatile *)REG_DMA17_ADDR_CUR)                 /* DMA17 Current Address */
-#define pREG_DMA17_STAT                  ((volatile uint32_t *)REG_DMA17_STAT)                   /* DMA17 Status Register */
-#define pREG_DMA17_XCNT_CUR              ((volatile uint32_t *)REG_DMA17_XCNT_CUR)               /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA17_YCNT_CUR              ((volatile uint32_t *)REG_DMA17_YCNT_CUR)               /* DMA17 Current Row Count (2D only) */
-#define pREG_DMA17_BWLCNT                ((volatile uint32_t *)REG_DMA17_BWLCNT)                 /* DMA17 Bandwidth Limit Count */
-#define pREG_DMA17_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWLCNT_CUR)             /* DMA17 Bandwidth Limit Count Current */
-#define pREG_DMA17_BWMCNT                ((volatile uint32_t *)REG_DMA17_BWMCNT)                 /* DMA17 Bandwidth Monitor Count */
-#define pREG_DMA17_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA17_BWMCNT_CUR)             /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA18
-   ========================================================================= */
-#define pREG_DMA18_DSCPTR_NXT            ((void * volatile *)REG_DMA18_DSCPTR_NXT)               /* DMA18 Pointer to Next Initial Descriptor */
-#define pREG_DMA18_ADDRSTART             ((void * volatile *)REG_DMA18_ADDRSTART)                /* DMA18 Start Address of Current Buffer */
-#define pREG_DMA18_CFG                   ((volatile uint32_t *)REG_DMA18_CFG)                    /* DMA18 Configuration Register */
-#define pREG_DMA18_XCNT                  ((volatile uint32_t *)REG_DMA18_XCNT)                   /* DMA18 Inner Loop Count Start Value */
-#define pREG_DMA18_XMOD                  ((volatile  int32_t *)REG_DMA18_XMOD)                   /* DMA18 Inner Loop Address Increment */
-#define pREG_DMA18_YCNT                  ((volatile uint32_t *)REG_DMA18_YCNT)                   /* DMA18 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA18_YMOD                  ((volatile  int32_t *)REG_DMA18_YMOD)                   /* DMA18 Outer Loop Address Increment (2D only) */
-#define pREG_DMA18_DSCPTR_CUR            ((void * volatile *)REG_DMA18_DSCPTR_CUR)               /* DMA18 Current Descriptor Pointer */
-#define pREG_DMA18_DSCPTR_PRV            ((void * volatile *)REG_DMA18_DSCPTR_PRV)               /* DMA18 Previous Initial Descriptor Pointer */
-#define pREG_DMA18_ADDR_CUR              ((void * volatile *)REG_DMA18_ADDR_CUR)                 /* DMA18 Current Address */
-#define pREG_DMA18_STAT                  ((volatile uint32_t *)REG_DMA18_STAT)                   /* DMA18 Status Register */
-#define pREG_DMA18_XCNT_CUR              ((volatile uint32_t *)REG_DMA18_XCNT_CUR)               /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA18_YCNT_CUR              ((volatile uint32_t *)REG_DMA18_YCNT_CUR)               /* DMA18 Current Row Count (2D only) */
-#define pREG_DMA18_BWLCNT                ((volatile uint32_t *)REG_DMA18_BWLCNT)                 /* DMA18 Bandwidth Limit Count */
-#define pREG_DMA18_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWLCNT_CUR)             /* DMA18 Bandwidth Limit Count Current */
-#define pREG_DMA18_BWMCNT                ((volatile uint32_t *)REG_DMA18_BWMCNT)                 /* DMA18 Bandwidth Monitor Count */
-#define pREG_DMA18_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA18_BWMCNT_CUR)             /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA19
-   ========================================================================= */
-#define pREG_DMA19_DSCPTR_NXT            ((void * volatile *)REG_DMA19_DSCPTR_NXT)               /* DMA19 Pointer to Next Initial Descriptor */
-#define pREG_DMA19_ADDRSTART             ((void * volatile *)REG_DMA19_ADDRSTART)                /* DMA19 Start Address of Current Buffer */
-#define pREG_DMA19_CFG                   ((volatile uint32_t *)REG_DMA19_CFG)                    /* DMA19 Configuration Register */
-#define pREG_DMA19_XCNT                  ((volatile uint32_t *)REG_DMA19_XCNT)                   /* DMA19 Inner Loop Count Start Value */
-#define pREG_DMA19_XMOD                  ((volatile  int32_t *)REG_DMA19_XMOD)                   /* DMA19 Inner Loop Address Increment */
-#define pREG_DMA19_YCNT                  ((volatile uint32_t *)REG_DMA19_YCNT)                   /* DMA19 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA19_YMOD                  ((volatile  int32_t *)REG_DMA19_YMOD)                   /* DMA19 Outer Loop Address Increment (2D only) */
-#define pREG_DMA19_DSCPTR_CUR            ((void * volatile *)REG_DMA19_DSCPTR_CUR)               /* DMA19 Current Descriptor Pointer */
-#define pREG_DMA19_DSCPTR_PRV            ((void * volatile *)REG_DMA19_DSCPTR_PRV)               /* DMA19 Previous Initial Descriptor Pointer */
-#define pREG_DMA19_ADDR_CUR              ((void * volatile *)REG_DMA19_ADDR_CUR)                 /* DMA19 Current Address */
-#define pREG_DMA19_STAT                  ((volatile uint32_t *)REG_DMA19_STAT)                   /* DMA19 Status Register */
-#define pREG_DMA19_XCNT_CUR              ((volatile uint32_t *)REG_DMA19_XCNT_CUR)               /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA19_YCNT_CUR              ((volatile uint32_t *)REG_DMA19_YCNT_CUR)               /* DMA19 Current Row Count (2D only) */
-#define pREG_DMA19_BWLCNT                ((volatile uint32_t *)REG_DMA19_BWLCNT)                 /* DMA19 Bandwidth Limit Count */
-#define pREG_DMA19_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWLCNT_CUR)             /* DMA19 Bandwidth Limit Count Current */
-#define pREG_DMA19_BWMCNT                ((volatile uint32_t *)REG_DMA19_BWMCNT)                 /* DMA19 Bandwidth Monitor Count */
-#define pREG_DMA19_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA19_BWMCNT_CUR)             /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA20
-   ========================================================================= */
-#define pREG_DMA20_DSCPTR_NXT            ((void * volatile *)REG_DMA20_DSCPTR_NXT)               /* DMA20 Pointer to Next Initial Descriptor */
-#define pREG_DMA20_ADDRSTART             ((void * volatile *)REG_DMA20_ADDRSTART)                /* DMA20 Start Address of Current Buffer */
-#define pREG_DMA20_CFG                   ((volatile uint32_t *)REG_DMA20_CFG)                    /* DMA20 Configuration Register */
-#define pREG_DMA20_XCNT                  ((volatile uint32_t *)REG_DMA20_XCNT)                   /* DMA20 Inner Loop Count Start Value */
-#define pREG_DMA20_XMOD                  ((volatile  int32_t *)REG_DMA20_XMOD)                   /* DMA20 Inner Loop Address Increment */
-#define pREG_DMA20_YCNT                  ((volatile uint32_t *)REG_DMA20_YCNT)                   /* DMA20 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA20_YMOD                  ((volatile  int32_t *)REG_DMA20_YMOD)                   /* DMA20 Outer Loop Address Increment (2D only) */
-#define pREG_DMA20_DSCPTR_CUR            ((void * volatile *)REG_DMA20_DSCPTR_CUR)               /* DMA20 Current Descriptor Pointer */
-#define pREG_DMA20_DSCPTR_PRV            ((void * volatile *)REG_DMA20_DSCPTR_PRV)               /* DMA20 Previous Initial Descriptor Pointer */
-#define pREG_DMA20_ADDR_CUR              ((void * volatile *)REG_DMA20_ADDR_CUR)                 /* DMA20 Current Address */
-#define pREG_DMA20_STAT                  ((volatile uint32_t *)REG_DMA20_STAT)                   /* DMA20 Status Register */
-#define pREG_DMA20_XCNT_CUR              ((volatile uint32_t *)REG_DMA20_XCNT_CUR)               /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA20_YCNT_CUR              ((volatile uint32_t *)REG_DMA20_YCNT_CUR)               /* DMA20 Current Row Count (2D only) */
-#define pREG_DMA20_BWLCNT                ((volatile uint32_t *)REG_DMA20_BWLCNT)                 /* DMA20 Bandwidth Limit Count */
-#define pREG_DMA20_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWLCNT_CUR)             /* DMA20 Bandwidth Limit Count Current */
-#define pREG_DMA20_BWMCNT                ((volatile uint32_t *)REG_DMA20_BWMCNT)                 /* DMA20 Bandwidth Monitor Count */
-#define pREG_DMA20_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA20_BWMCNT_CUR)             /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA21
-   ========================================================================= */
-#define pREG_DMA21_DSCPTR_NXT            ((void * volatile *)REG_DMA21_DSCPTR_NXT)               /* DMA21 Pointer to Next Initial Descriptor */
-#define pREG_DMA21_ADDRSTART             ((void * volatile *)REG_DMA21_ADDRSTART)                /* DMA21 Start Address of Current Buffer */
-#define pREG_DMA21_CFG                   ((volatile uint32_t *)REG_DMA21_CFG)                    /* DMA21 Configuration Register */
-#define pREG_DMA21_XCNT                  ((volatile uint32_t *)REG_DMA21_XCNT)                   /* DMA21 Inner Loop Count Start Value */
-#define pREG_DMA21_XMOD                  ((volatile  int32_t *)REG_DMA21_XMOD)                   /* DMA21 Inner Loop Address Increment */
-#define pREG_DMA21_YCNT                  ((volatile uint32_t *)REG_DMA21_YCNT)                   /* DMA21 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA21_YMOD                  ((volatile  int32_t *)REG_DMA21_YMOD)                   /* DMA21 Outer Loop Address Increment (2D only) */
-#define pREG_DMA21_DSCPTR_CUR            ((void * volatile *)REG_DMA21_DSCPTR_CUR)               /* DMA21 Current Descriptor Pointer */
-#define pREG_DMA21_DSCPTR_PRV            ((void * volatile *)REG_DMA21_DSCPTR_PRV)               /* DMA21 Previous Initial Descriptor Pointer */
-#define pREG_DMA21_ADDR_CUR              ((void * volatile *)REG_DMA21_ADDR_CUR)                 /* DMA21 Current Address */
-#define pREG_DMA21_STAT                  ((volatile uint32_t *)REG_DMA21_STAT)                   /* DMA21 Status Register */
-#define pREG_DMA21_XCNT_CUR              ((volatile uint32_t *)REG_DMA21_XCNT_CUR)               /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA21_YCNT_CUR              ((volatile uint32_t *)REG_DMA21_YCNT_CUR)               /* DMA21 Current Row Count (2D only) */
-#define pREG_DMA21_BWLCNT                ((volatile uint32_t *)REG_DMA21_BWLCNT)                 /* DMA21 Bandwidth Limit Count */
-#define pREG_DMA21_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWLCNT_CUR)             /* DMA21 Bandwidth Limit Count Current */
-#define pREG_DMA21_BWMCNT                ((volatile uint32_t *)REG_DMA21_BWMCNT)                 /* DMA21 Bandwidth Monitor Count */
-#define pREG_DMA21_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA21_BWMCNT_CUR)             /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA22
-   ========================================================================= */
-#define pREG_DMA22_DSCPTR_NXT            ((void * volatile *)REG_DMA22_DSCPTR_NXT)               /* DMA22 Pointer to Next Initial Descriptor */
-#define pREG_DMA22_ADDRSTART             ((void * volatile *)REG_DMA22_ADDRSTART)                /* DMA22 Start Address of Current Buffer */
-#define pREG_DMA22_CFG                   ((volatile uint32_t *)REG_DMA22_CFG)                    /* DMA22 Configuration Register */
-#define pREG_DMA22_XCNT                  ((volatile uint32_t *)REG_DMA22_XCNT)                   /* DMA22 Inner Loop Count Start Value */
-#define pREG_DMA22_XMOD                  ((volatile  int32_t *)REG_DMA22_XMOD)                   /* DMA22 Inner Loop Address Increment */
-#define pREG_DMA22_YCNT                  ((volatile uint32_t *)REG_DMA22_YCNT)                   /* DMA22 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA22_YMOD                  ((volatile  int32_t *)REG_DMA22_YMOD)                   /* DMA22 Outer Loop Address Increment (2D only) */
-#define pREG_DMA22_DSCPTR_CUR            ((void * volatile *)REG_DMA22_DSCPTR_CUR)               /* DMA22 Current Descriptor Pointer */
-#define pREG_DMA22_DSCPTR_PRV            ((void * volatile *)REG_DMA22_DSCPTR_PRV)               /* DMA22 Previous Initial Descriptor Pointer */
-#define pREG_DMA22_ADDR_CUR              ((void * volatile *)REG_DMA22_ADDR_CUR)                 /* DMA22 Current Address */
-#define pREG_DMA22_STAT                  ((volatile uint32_t *)REG_DMA22_STAT)                   /* DMA22 Status Register */
-#define pREG_DMA22_XCNT_CUR              ((volatile uint32_t *)REG_DMA22_XCNT_CUR)               /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA22_YCNT_CUR              ((volatile uint32_t *)REG_DMA22_YCNT_CUR)               /* DMA22 Current Row Count (2D only) */
-#define pREG_DMA22_BWLCNT                ((volatile uint32_t *)REG_DMA22_BWLCNT)                 /* DMA22 Bandwidth Limit Count */
-#define pREG_DMA22_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWLCNT_CUR)             /* DMA22 Bandwidth Limit Count Current */
-#define pREG_DMA22_BWMCNT                ((volatile uint32_t *)REG_DMA22_BWMCNT)                 /* DMA22 Bandwidth Monitor Count */
-#define pREG_DMA22_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA22_BWMCNT_CUR)             /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA23
-   ========================================================================= */
-#define pREG_DMA23_DSCPTR_NXT            ((void * volatile *)REG_DMA23_DSCPTR_NXT)               /* DMA23 Pointer to Next Initial Descriptor */
-#define pREG_DMA23_ADDRSTART             ((void * volatile *)REG_DMA23_ADDRSTART)                /* DMA23 Start Address of Current Buffer */
-#define pREG_DMA23_CFG                   ((volatile uint32_t *)REG_DMA23_CFG)                    /* DMA23 Configuration Register */
-#define pREG_DMA23_XCNT                  ((volatile uint32_t *)REG_DMA23_XCNT)                   /* DMA23 Inner Loop Count Start Value */
-#define pREG_DMA23_XMOD                  ((volatile  int32_t *)REG_DMA23_XMOD)                   /* DMA23 Inner Loop Address Increment */
-#define pREG_DMA23_YCNT                  ((volatile uint32_t *)REG_DMA23_YCNT)                   /* DMA23 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA23_YMOD                  ((volatile  int32_t *)REG_DMA23_YMOD)                   /* DMA23 Outer Loop Address Increment (2D only) */
-#define pREG_DMA23_DSCPTR_CUR            ((void * volatile *)REG_DMA23_DSCPTR_CUR)               /* DMA23 Current Descriptor Pointer */
-#define pREG_DMA23_DSCPTR_PRV            ((void * volatile *)REG_DMA23_DSCPTR_PRV)               /* DMA23 Previous Initial Descriptor Pointer */
-#define pREG_DMA23_ADDR_CUR              ((void * volatile *)REG_DMA23_ADDR_CUR)                 /* DMA23 Current Address */
-#define pREG_DMA23_STAT                  ((volatile uint32_t *)REG_DMA23_STAT)                   /* DMA23 Status Register */
-#define pREG_DMA23_XCNT_CUR              ((volatile uint32_t *)REG_DMA23_XCNT_CUR)               /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA23_YCNT_CUR              ((volatile uint32_t *)REG_DMA23_YCNT_CUR)               /* DMA23 Current Row Count (2D only) */
-#define pREG_DMA23_BWLCNT                ((volatile uint32_t *)REG_DMA23_BWLCNT)                 /* DMA23 Bandwidth Limit Count */
-#define pREG_DMA23_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWLCNT_CUR)             /* DMA23 Bandwidth Limit Count Current */
-#define pREG_DMA23_BWMCNT                ((volatile uint32_t *)REG_DMA23_BWMCNT)                 /* DMA23 Bandwidth Monitor Count */
-#define pREG_DMA23_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA23_BWMCNT_CUR)             /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA24
-   ========================================================================= */
-#define pREG_DMA24_DSCPTR_NXT            ((void * volatile *)REG_DMA24_DSCPTR_NXT)               /* DMA24 Pointer to Next Initial Descriptor */
-#define pREG_DMA24_ADDRSTART             ((void * volatile *)REG_DMA24_ADDRSTART)                /* DMA24 Start Address of Current Buffer */
-#define pREG_DMA24_CFG                   ((volatile uint32_t *)REG_DMA24_CFG)                    /* DMA24 Configuration Register */
-#define pREG_DMA24_XCNT                  ((volatile uint32_t *)REG_DMA24_XCNT)                   /* DMA24 Inner Loop Count Start Value */
-#define pREG_DMA24_XMOD                  ((volatile  int32_t *)REG_DMA24_XMOD)                   /* DMA24 Inner Loop Address Increment */
-#define pREG_DMA24_YCNT                  ((volatile uint32_t *)REG_DMA24_YCNT)                   /* DMA24 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA24_YMOD                  ((volatile  int32_t *)REG_DMA24_YMOD)                   /* DMA24 Outer Loop Address Increment (2D only) */
-#define pREG_DMA24_DSCPTR_CUR            ((void * volatile *)REG_DMA24_DSCPTR_CUR)               /* DMA24 Current Descriptor Pointer */
-#define pREG_DMA24_DSCPTR_PRV            ((void * volatile *)REG_DMA24_DSCPTR_PRV)               /* DMA24 Previous Initial Descriptor Pointer */
-#define pREG_DMA24_ADDR_CUR              ((void * volatile *)REG_DMA24_ADDR_CUR)                 /* DMA24 Current Address */
-#define pREG_DMA24_STAT                  ((volatile uint32_t *)REG_DMA24_STAT)                   /* DMA24 Status Register */
-#define pREG_DMA24_XCNT_CUR              ((volatile uint32_t *)REG_DMA24_XCNT_CUR)               /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA24_YCNT_CUR              ((volatile uint32_t *)REG_DMA24_YCNT_CUR)               /* DMA24 Current Row Count (2D only) */
-#define pREG_DMA24_BWLCNT                ((volatile uint32_t *)REG_DMA24_BWLCNT)                 /* DMA24 Bandwidth Limit Count */
-#define pREG_DMA24_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWLCNT_CUR)             /* DMA24 Bandwidth Limit Count Current */
-#define pREG_DMA24_BWMCNT                ((volatile uint32_t *)REG_DMA24_BWMCNT)                 /* DMA24 Bandwidth Monitor Count */
-#define pREG_DMA24_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA24_BWMCNT_CUR)             /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA25
-   ========================================================================= */
-#define pREG_DMA25_DSCPTR_NXT            ((void * volatile *)REG_DMA25_DSCPTR_NXT)               /* DMA25 Pointer to Next Initial Descriptor */
-#define pREG_DMA25_ADDRSTART             ((void * volatile *)REG_DMA25_ADDRSTART)                /* DMA25 Start Address of Current Buffer */
-#define pREG_DMA25_CFG                   ((volatile uint32_t *)REG_DMA25_CFG)                    /* DMA25 Configuration Register */
-#define pREG_DMA25_XCNT                  ((volatile uint32_t *)REG_DMA25_XCNT)                   /* DMA25 Inner Loop Count Start Value */
-#define pREG_DMA25_XMOD                  ((volatile  int32_t *)REG_DMA25_XMOD)                   /* DMA25 Inner Loop Address Increment */
-#define pREG_DMA25_YCNT                  ((volatile uint32_t *)REG_DMA25_YCNT)                   /* DMA25 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA25_YMOD                  ((volatile  int32_t *)REG_DMA25_YMOD)                   /* DMA25 Outer Loop Address Increment (2D only) */
-#define pREG_DMA25_DSCPTR_CUR            ((void * volatile *)REG_DMA25_DSCPTR_CUR)               /* DMA25 Current Descriptor Pointer */
-#define pREG_DMA25_DSCPTR_PRV            ((void * volatile *)REG_DMA25_DSCPTR_PRV)               /* DMA25 Previous Initial Descriptor Pointer */
-#define pREG_DMA25_ADDR_CUR              ((void * volatile *)REG_DMA25_ADDR_CUR)                 /* DMA25 Current Address */
-#define pREG_DMA25_STAT                  ((volatile uint32_t *)REG_DMA25_STAT)                   /* DMA25 Status Register */
-#define pREG_DMA25_XCNT_CUR              ((volatile uint32_t *)REG_DMA25_XCNT_CUR)               /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA25_YCNT_CUR              ((volatile uint32_t *)REG_DMA25_YCNT_CUR)               /* DMA25 Current Row Count (2D only) */
-#define pREG_DMA25_BWLCNT                ((volatile uint32_t *)REG_DMA25_BWLCNT)                 /* DMA25 Bandwidth Limit Count */
-#define pREG_DMA25_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWLCNT_CUR)             /* DMA25 Bandwidth Limit Count Current */
-#define pREG_DMA25_BWMCNT                ((volatile uint32_t *)REG_DMA25_BWMCNT)                 /* DMA25 Bandwidth Monitor Count */
-#define pREG_DMA25_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA25_BWMCNT_CUR)             /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA26
-   ========================================================================= */
-#define pREG_DMA26_DSCPTR_NXT            ((void * volatile *)REG_DMA26_DSCPTR_NXT)               /* DMA26 Pointer to Next Initial Descriptor */
-#define pREG_DMA26_ADDRSTART             ((void * volatile *)REG_DMA26_ADDRSTART)                /* DMA26 Start Address of Current Buffer */
-#define pREG_DMA26_CFG                   ((volatile uint32_t *)REG_DMA26_CFG)                    /* DMA26 Configuration Register */
-#define pREG_DMA26_XCNT                  ((volatile uint32_t *)REG_DMA26_XCNT)                   /* DMA26 Inner Loop Count Start Value */
-#define pREG_DMA26_XMOD                  ((volatile  int32_t *)REG_DMA26_XMOD)                   /* DMA26 Inner Loop Address Increment */
-#define pREG_DMA26_YCNT                  ((volatile uint32_t *)REG_DMA26_YCNT)                   /* DMA26 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA26_YMOD                  ((volatile  int32_t *)REG_DMA26_YMOD)                   /* DMA26 Outer Loop Address Increment (2D only) */
-#define pREG_DMA26_DSCPTR_CUR            ((void * volatile *)REG_DMA26_DSCPTR_CUR)               /* DMA26 Current Descriptor Pointer */
-#define pREG_DMA26_DSCPTR_PRV            ((void * volatile *)REG_DMA26_DSCPTR_PRV)               /* DMA26 Previous Initial Descriptor Pointer */
-#define pREG_DMA26_ADDR_CUR              ((void * volatile *)REG_DMA26_ADDR_CUR)                 /* DMA26 Current Address */
-#define pREG_DMA26_STAT                  ((volatile uint32_t *)REG_DMA26_STAT)                   /* DMA26 Status Register */
-#define pREG_DMA26_XCNT_CUR              ((volatile uint32_t *)REG_DMA26_XCNT_CUR)               /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA26_YCNT_CUR              ((volatile uint32_t *)REG_DMA26_YCNT_CUR)               /* DMA26 Current Row Count (2D only) */
-#define pREG_DMA26_BWLCNT                ((volatile uint32_t *)REG_DMA26_BWLCNT)                 /* DMA26 Bandwidth Limit Count */
-#define pREG_DMA26_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWLCNT_CUR)             /* DMA26 Bandwidth Limit Count Current */
-#define pREG_DMA26_BWMCNT                ((volatile uint32_t *)REG_DMA26_BWMCNT)                 /* DMA26 Bandwidth Monitor Count */
-#define pREG_DMA26_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA26_BWMCNT_CUR)             /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA27
-   ========================================================================= */
-#define pREG_DMA27_DSCPTR_NXT            ((void * volatile *)REG_DMA27_DSCPTR_NXT)               /* DMA27 Pointer to Next Initial Descriptor */
-#define pREG_DMA27_ADDRSTART             ((void * volatile *)REG_DMA27_ADDRSTART)                /* DMA27 Start Address of Current Buffer */
-#define pREG_DMA27_CFG                   ((volatile uint32_t *)REG_DMA27_CFG)                    /* DMA27 Configuration Register */
-#define pREG_DMA27_XCNT                  ((volatile uint32_t *)REG_DMA27_XCNT)                   /* DMA27 Inner Loop Count Start Value */
-#define pREG_DMA27_XMOD                  ((volatile  int32_t *)REG_DMA27_XMOD)                   /* DMA27 Inner Loop Address Increment */
-#define pREG_DMA27_YCNT                  ((volatile uint32_t *)REG_DMA27_YCNT)                   /* DMA27 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA27_YMOD                  ((volatile  int32_t *)REG_DMA27_YMOD)                   /* DMA27 Outer Loop Address Increment (2D only) */
-#define pREG_DMA27_DSCPTR_CUR            ((void * volatile *)REG_DMA27_DSCPTR_CUR)               /* DMA27 Current Descriptor Pointer */
-#define pREG_DMA27_DSCPTR_PRV            ((void * volatile *)REG_DMA27_DSCPTR_PRV)               /* DMA27 Previous Initial Descriptor Pointer */
-#define pREG_DMA27_ADDR_CUR              ((void * volatile *)REG_DMA27_ADDR_CUR)                 /* DMA27 Current Address */
-#define pREG_DMA27_STAT                  ((volatile uint32_t *)REG_DMA27_STAT)                   /* DMA27 Status Register */
-#define pREG_DMA27_XCNT_CUR              ((volatile uint32_t *)REG_DMA27_XCNT_CUR)               /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA27_YCNT_CUR              ((volatile uint32_t *)REG_DMA27_YCNT_CUR)               /* DMA27 Current Row Count (2D only) */
-#define pREG_DMA27_BWLCNT                ((volatile uint32_t *)REG_DMA27_BWLCNT)                 /* DMA27 Bandwidth Limit Count */
-#define pREG_DMA27_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWLCNT_CUR)             /* DMA27 Bandwidth Limit Count Current */
-#define pREG_DMA27_BWMCNT                ((volatile uint32_t *)REG_DMA27_BWMCNT)                 /* DMA27 Bandwidth Monitor Count */
-#define pREG_DMA27_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA27_BWMCNT_CUR)             /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA28
-   ========================================================================= */
-#define pREG_DMA28_DSCPTR_NXT            ((void * volatile *)REG_DMA28_DSCPTR_NXT)               /* DMA28 Pointer to Next Initial Descriptor */
-#define pREG_DMA28_ADDRSTART             ((void * volatile *)REG_DMA28_ADDRSTART)                /* DMA28 Start Address of Current Buffer */
-#define pREG_DMA28_CFG                   ((volatile uint32_t *)REG_DMA28_CFG)                    /* DMA28 Configuration Register */
-#define pREG_DMA28_XCNT                  ((volatile uint32_t *)REG_DMA28_XCNT)                   /* DMA28 Inner Loop Count Start Value */
-#define pREG_DMA28_XMOD                  ((volatile  int32_t *)REG_DMA28_XMOD)                   /* DMA28 Inner Loop Address Increment */
-#define pREG_DMA28_YCNT                  ((volatile uint32_t *)REG_DMA28_YCNT)                   /* DMA28 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA28_YMOD                  ((volatile  int32_t *)REG_DMA28_YMOD)                   /* DMA28 Outer Loop Address Increment (2D only) */
-#define pREG_DMA28_DSCPTR_CUR            ((void * volatile *)REG_DMA28_DSCPTR_CUR)               /* DMA28 Current Descriptor Pointer */
-#define pREG_DMA28_DSCPTR_PRV            ((void * volatile *)REG_DMA28_DSCPTR_PRV)               /* DMA28 Previous Initial Descriptor Pointer */
-#define pREG_DMA28_ADDR_CUR              ((void * volatile *)REG_DMA28_ADDR_CUR)                 /* DMA28 Current Address */
-#define pREG_DMA28_STAT                  ((volatile uint32_t *)REG_DMA28_STAT)                   /* DMA28 Status Register */
-#define pREG_DMA28_XCNT_CUR              ((volatile uint32_t *)REG_DMA28_XCNT_CUR)               /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA28_YCNT_CUR              ((volatile uint32_t *)REG_DMA28_YCNT_CUR)               /* DMA28 Current Row Count (2D only) */
-#define pREG_DMA28_BWLCNT                ((volatile uint32_t *)REG_DMA28_BWLCNT)                 /* DMA28 Bandwidth Limit Count */
-#define pREG_DMA28_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWLCNT_CUR)             /* DMA28 Bandwidth Limit Count Current */
-#define pREG_DMA28_BWMCNT                ((volatile uint32_t *)REG_DMA28_BWMCNT)                 /* DMA28 Bandwidth Monitor Count */
-#define pREG_DMA28_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA28_BWMCNT_CUR)             /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA29
-   ========================================================================= */
-#define pREG_DMA29_DSCPTR_NXT            ((void * volatile *)REG_DMA29_DSCPTR_NXT)               /* DMA29 Pointer to Next Initial Descriptor */
-#define pREG_DMA29_ADDRSTART             ((void * volatile *)REG_DMA29_ADDRSTART)                /* DMA29 Start Address of Current Buffer */
-#define pREG_DMA29_CFG                   ((volatile uint32_t *)REG_DMA29_CFG)                    /* DMA29 Configuration Register */
-#define pREG_DMA29_XCNT                  ((volatile uint32_t *)REG_DMA29_XCNT)                   /* DMA29 Inner Loop Count Start Value */
-#define pREG_DMA29_XMOD                  ((volatile  int32_t *)REG_DMA29_XMOD)                   /* DMA29 Inner Loop Address Increment */
-#define pREG_DMA29_YCNT                  ((volatile uint32_t *)REG_DMA29_YCNT)                   /* DMA29 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA29_YMOD                  ((volatile  int32_t *)REG_DMA29_YMOD)                   /* DMA29 Outer Loop Address Increment (2D only) */
-#define pREG_DMA29_DSCPTR_CUR            ((void * volatile *)REG_DMA29_DSCPTR_CUR)               /* DMA29 Current Descriptor Pointer */
-#define pREG_DMA29_DSCPTR_PRV            ((void * volatile *)REG_DMA29_DSCPTR_PRV)               /* DMA29 Previous Initial Descriptor Pointer */
-#define pREG_DMA29_ADDR_CUR              ((void * volatile *)REG_DMA29_ADDR_CUR)                 /* DMA29 Current Address */
-#define pREG_DMA29_STAT                  ((volatile uint32_t *)REG_DMA29_STAT)                   /* DMA29 Status Register */
-#define pREG_DMA29_XCNT_CUR              ((volatile uint32_t *)REG_DMA29_XCNT_CUR)               /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA29_YCNT_CUR              ((volatile uint32_t *)REG_DMA29_YCNT_CUR)               /* DMA29 Current Row Count (2D only) */
-#define pREG_DMA29_BWLCNT                ((volatile uint32_t *)REG_DMA29_BWLCNT)                 /* DMA29 Bandwidth Limit Count */
-#define pREG_DMA29_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWLCNT_CUR)             /* DMA29 Bandwidth Limit Count Current */
-#define pREG_DMA29_BWMCNT                ((volatile uint32_t *)REG_DMA29_BWMCNT)                 /* DMA29 Bandwidth Monitor Count */
-#define pREG_DMA29_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA29_BWMCNT_CUR)             /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA30
-   ========================================================================= */
-#define pREG_DMA30_DSCPTR_NXT            ((void * volatile *)REG_DMA30_DSCPTR_NXT)               /* DMA30 Pointer to Next Initial Descriptor */
-#define pREG_DMA30_ADDRSTART             ((void * volatile *)REG_DMA30_ADDRSTART)                /* DMA30 Start Address of Current Buffer */
-#define pREG_DMA30_CFG                   ((volatile uint32_t *)REG_DMA30_CFG)                    /* DMA30 Configuration Register */
-#define pREG_DMA30_XCNT                  ((volatile uint32_t *)REG_DMA30_XCNT)                   /* DMA30 Inner Loop Count Start Value */
-#define pREG_DMA30_XMOD                  ((volatile  int32_t *)REG_DMA30_XMOD)                   /* DMA30 Inner Loop Address Increment */
-#define pREG_DMA30_YCNT                  ((volatile uint32_t *)REG_DMA30_YCNT)                   /* DMA30 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA30_YMOD                  ((volatile  int32_t *)REG_DMA30_YMOD)                   /* DMA30 Outer Loop Address Increment (2D only) */
-#define pREG_DMA30_DSCPTR_CUR            ((void * volatile *)REG_DMA30_DSCPTR_CUR)               /* DMA30 Current Descriptor Pointer */
-#define pREG_DMA30_DSCPTR_PRV            ((void * volatile *)REG_DMA30_DSCPTR_PRV)               /* DMA30 Previous Initial Descriptor Pointer */
-#define pREG_DMA30_ADDR_CUR              ((void * volatile *)REG_DMA30_ADDR_CUR)                 /* DMA30 Current Address */
-#define pREG_DMA30_STAT                  ((volatile uint32_t *)REG_DMA30_STAT)                   /* DMA30 Status Register */
-#define pREG_DMA30_XCNT_CUR              ((volatile uint32_t *)REG_DMA30_XCNT_CUR)               /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA30_YCNT_CUR              ((volatile uint32_t *)REG_DMA30_YCNT_CUR)               /* DMA30 Current Row Count (2D only) */
-#define pREG_DMA30_BWLCNT                ((volatile uint32_t *)REG_DMA30_BWLCNT)                 /* DMA30 Bandwidth Limit Count */
-#define pREG_DMA30_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWLCNT_CUR)             /* DMA30 Bandwidth Limit Count Current */
-#define pREG_DMA30_BWMCNT                ((volatile uint32_t *)REG_DMA30_BWMCNT)                 /* DMA30 Bandwidth Monitor Count */
-#define pREG_DMA30_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA30_BWMCNT_CUR)             /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA31
-   ========================================================================= */
-#define pREG_DMA31_DSCPTR_NXT            ((void * volatile *)REG_DMA31_DSCPTR_NXT)               /* DMA31 Pointer to Next Initial Descriptor */
-#define pREG_DMA31_ADDRSTART             ((void * volatile *)REG_DMA31_ADDRSTART)                /* DMA31 Start Address of Current Buffer */
-#define pREG_DMA31_CFG                   ((volatile uint32_t *)REG_DMA31_CFG)                    /* DMA31 Configuration Register */
-#define pREG_DMA31_XCNT                  ((volatile uint32_t *)REG_DMA31_XCNT)                   /* DMA31 Inner Loop Count Start Value */
-#define pREG_DMA31_XMOD                  ((volatile  int32_t *)REG_DMA31_XMOD)                   /* DMA31 Inner Loop Address Increment */
-#define pREG_DMA31_YCNT                  ((volatile uint32_t *)REG_DMA31_YCNT)                   /* DMA31 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA31_YMOD                  ((volatile  int32_t *)REG_DMA31_YMOD)                   /* DMA31 Outer Loop Address Increment (2D only) */
-#define pREG_DMA31_DSCPTR_CUR            ((void * volatile *)REG_DMA31_DSCPTR_CUR)               /* DMA31 Current Descriptor Pointer */
-#define pREG_DMA31_DSCPTR_PRV            ((void * volatile *)REG_DMA31_DSCPTR_PRV)               /* DMA31 Previous Initial Descriptor Pointer */
-#define pREG_DMA31_ADDR_CUR              ((void * volatile *)REG_DMA31_ADDR_CUR)                 /* DMA31 Current Address */
-#define pREG_DMA31_STAT                  ((volatile uint32_t *)REG_DMA31_STAT)                   /* DMA31 Status Register */
-#define pREG_DMA31_XCNT_CUR              ((volatile uint32_t *)REG_DMA31_XCNT_CUR)               /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA31_YCNT_CUR              ((volatile uint32_t *)REG_DMA31_YCNT_CUR)               /* DMA31 Current Row Count (2D only) */
-#define pREG_DMA31_BWLCNT                ((volatile uint32_t *)REG_DMA31_BWLCNT)                 /* DMA31 Bandwidth Limit Count */
-#define pREG_DMA31_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWLCNT_CUR)             /* DMA31 Bandwidth Limit Count Current */
-#define pREG_DMA31_BWMCNT                ((volatile uint32_t *)REG_DMA31_BWMCNT)                 /* DMA31 Bandwidth Monitor Count */
-#define pREG_DMA31_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA31_BWMCNT_CUR)             /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA32
-   ========================================================================= */
-#define pREG_DMA32_DSCPTR_NXT            ((void * volatile *)REG_DMA32_DSCPTR_NXT)               /* DMA32 Pointer to Next Initial Descriptor */
-#define pREG_DMA32_ADDRSTART             ((void * volatile *)REG_DMA32_ADDRSTART)                /* DMA32 Start Address of Current Buffer */
-#define pREG_DMA32_CFG                   ((volatile uint32_t *)REG_DMA32_CFG)                    /* DMA32 Configuration Register */
-#define pREG_DMA32_XCNT                  ((volatile uint32_t *)REG_DMA32_XCNT)                   /* DMA32 Inner Loop Count Start Value */
-#define pREG_DMA32_XMOD                  ((volatile  int32_t *)REG_DMA32_XMOD)                   /* DMA32 Inner Loop Address Increment */
-#define pREG_DMA32_YCNT                  ((volatile uint32_t *)REG_DMA32_YCNT)                   /* DMA32 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA32_YMOD                  ((volatile  int32_t *)REG_DMA32_YMOD)                   /* DMA32 Outer Loop Address Increment (2D only) */
-#define pREG_DMA32_DSCPTR_CUR            ((void * volatile *)REG_DMA32_DSCPTR_CUR)               /* DMA32 Current Descriptor Pointer */
-#define pREG_DMA32_DSCPTR_PRV            ((void * volatile *)REG_DMA32_DSCPTR_PRV)               /* DMA32 Previous Initial Descriptor Pointer */
-#define pREG_DMA32_ADDR_CUR              ((void * volatile *)REG_DMA32_ADDR_CUR)                 /* DMA32 Current Address */
-#define pREG_DMA32_STAT                  ((volatile uint32_t *)REG_DMA32_STAT)                   /* DMA32 Status Register */
-#define pREG_DMA32_XCNT_CUR              ((volatile uint32_t *)REG_DMA32_XCNT_CUR)               /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA32_YCNT_CUR              ((volatile uint32_t *)REG_DMA32_YCNT_CUR)               /* DMA32 Current Row Count (2D only) */
-#define pREG_DMA32_BWLCNT                ((volatile uint32_t *)REG_DMA32_BWLCNT)                 /* DMA32 Bandwidth Limit Count */
-#define pREG_DMA32_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWLCNT_CUR)             /* DMA32 Bandwidth Limit Count Current */
-#define pREG_DMA32_BWMCNT                ((volatile uint32_t *)REG_DMA32_BWMCNT)                 /* DMA32 Bandwidth Monitor Count */
-#define pREG_DMA32_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA32_BWMCNT_CUR)             /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA33
-   ========================================================================= */
-#define pREG_DMA33_DSCPTR_NXT            ((void * volatile *)REG_DMA33_DSCPTR_NXT)               /* DMA33 Pointer to Next Initial Descriptor */
-#define pREG_DMA33_ADDRSTART             ((void * volatile *)REG_DMA33_ADDRSTART)                /* DMA33 Start Address of Current Buffer */
-#define pREG_DMA33_CFG                   ((volatile uint32_t *)REG_DMA33_CFG)                    /* DMA33 Configuration Register */
-#define pREG_DMA33_XCNT                  ((volatile uint32_t *)REG_DMA33_XCNT)                   /* DMA33 Inner Loop Count Start Value */
-#define pREG_DMA33_XMOD                  ((volatile  int32_t *)REG_DMA33_XMOD)                   /* DMA33 Inner Loop Address Increment */
-#define pREG_DMA33_YCNT                  ((volatile uint32_t *)REG_DMA33_YCNT)                   /* DMA33 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA33_YMOD                  ((volatile  int32_t *)REG_DMA33_YMOD)                   /* DMA33 Outer Loop Address Increment (2D only) */
-#define pREG_DMA33_DSCPTR_CUR            ((void * volatile *)REG_DMA33_DSCPTR_CUR)               /* DMA33 Current Descriptor Pointer */
-#define pREG_DMA33_DSCPTR_PRV            ((void * volatile *)REG_DMA33_DSCPTR_PRV)               /* DMA33 Previous Initial Descriptor Pointer */
-#define pREG_DMA33_ADDR_CUR              ((void * volatile *)REG_DMA33_ADDR_CUR)                 /* DMA33 Current Address */
-#define pREG_DMA33_STAT                  ((volatile uint32_t *)REG_DMA33_STAT)                   /* DMA33 Status Register */
-#define pREG_DMA33_XCNT_CUR              ((volatile uint32_t *)REG_DMA33_XCNT_CUR)               /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA33_YCNT_CUR              ((volatile uint32_t *)REG_DMA33_YCNT_CUR)               /* DMA33 Current Row Count (2D only) */
-#define pREG_DMA33_BWLCNT                ((volatile uint32_t *)REG_DMA33_BWLCNT)                 /* DMA33 Bandwidth Limit Count */
-#define pREG_DMA33_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWLCNT_CUR)             /* DMA33 Bandwidth Limit Count Current */
-#define pREG_DMA33_BWMCNT                ((volatile uint32_t *)REG_DMA33_BWMCNT)                 /* DMA33 Bandwidth Monitor Count */
-#define pREG_DMA33_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA33_BWMCNT_CUR)             /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA34
-   ========================================================================= */
-#define pREG_DMA34_DSCPTR_NXT            ((void * volatile *)REG_DMA34_DSCPTR_NXT)               /* DMA34 Pointer to Next Initial Descriptor */
-#define pREG_DMA34_ADDRSTART             ((void * volatile *)REG_DMA34_ADDRSTART)                /* DMA34 Start Address of Current Buffer */
-#define pREG_DMA34_CFG                   ((volatile uint32_t *)REG_DMA34_CFG)                    /* DMA34 Configuration Register */
-#define pREG_DMA34_XCNT                  ((volatile uint32_t *)REG_DMA34_XCNT)                   /* DMA34 Inner Loop Count Start Value */
-#define pREG_DMA34_XMOD                  ((volatile  int32_t *)REG_DMA34_XMOD)                   /* DMA34 Inner Loop Address Increment */
-#define pREG_DMA34_YCNT                  ((volatile uint32_t *)REG_DMA34_YCNT)                   /* DMA34 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA34_YMOD                  ((volatile  int32_t *)REG_DMA34_YMOD)                   /* DMA34 Outer Loop Address Increment (2D only) */
-#define pREG_DMA34_DSCPTR_CUR            ((void * volatile *)REG_DMA34_DSCPTR_CUR)               /* DMA34 Current Descriptor Pointer */
-#define pREG_DMA34_DSCPTR_PRV            ((void * volatile *)REG_DMA34_DSCPTR_PRV)               /* DMA34 Previous Initial Descriptor Pointer */
-#define pREG_DMA34_ADDR_CUR              ((void * volatile *)REG_DMA34_ADDR_CUR)                 /* DMA34 Current Address */
-#define pREG_DMA34_STAT                  ((volatile uint32_t *)REG_DMA34_STAT)                   /* DMA34 Status Register */
-#define pREG_DMA34_XCNT_CUR              ((volatile uint32_t *)REG_DMA34_XCNT_CUR)               /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA34_YCNT_CUR              ((volatile uint32_t *)REG_DMA34_YCNT_CUR)               /* DMA34 Current Row Count (2D only) */
-#define pREG_DMA34_BWLCNT                ((volatile uint32_t *)REG_DMA34_BWLCNT)                 /* DMA34 Bandwidth Limit Count */
-#define pREG_DMA34_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWLCNT_CUR)             /* DMA34 Bandwidth Limit Count Current */
-#define pREG_DMA34_BWMCNT                ((volatile uint32_t *)REG_DMA34_BWMCNT)                 /* DMA34 Bandwidth Monitor Count */
-#define pREG_DMA34_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA34_BWMCNT_CUR)             /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA35
-   ========================================================================= */
-#define pREG_DMA35_DSCPTR_NXT            ((void * volatile *)REG_DMA35_DSCPTR_NXT)               /* DMA35 Pointer to Next Initial Descriptor */
-#define pREG_DMA35_ADDRSTART             ((void * volatile *)REG_DMA35_ADDRSTART)                /* DMA35 Start Address of Current Buffer */
-#define pREG_DMA35_CFG                   ((volatile uint32_t *)REG_DMA35_CFG)                    /* DMA35 Configuration Register */
-#define pREG_DMA35_XCNT                  ((volatile uint32_t *)REG_DMA35_XCNT)                   /* DMA35 Inner Loop Count Start Value */
-#define pREG_DMA35_XMOD                  ((volatile  int32_t *)REG_DMA35_XMOD)                   /* DMA35 Inner Loop Address Increment */
-#define pREG_DMA35_YCNT                  ((volatile uint32_t *)REG_DMA35_YCNT)                   /* DMA35 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA35_YMOD                  ((volatile  int32_t *)REG_DMA35_YMOD)                   /* DMA35 Outer Loop Address Increment (2D only) */
-#define pREG_DMA35_DSCPTR_CUR            ((void * volatile *)REG_DMA35_DSCPTR_CUR)               /* DMA35 Current Descriptor Pointer */
-#define pREG_DMA35_DSCPTR_PRV            ((void * volatile *)REG_DMA35_DSCPTR_PRV)               /* DMA35 Previous Initial Descriptor Pointer */
-#define pREG_DMA35_ADDR_CUR              ((void * volatile *)REG_DMA35_ADDR_CUR)                 /* DMA35 Current Address */
-#define pREG_DMA35_STAT                  ((volatile uint32_t *)REG_DMA35_STAT)                   /* DMA35 Status Register */
-#define pREG_DMA35_XCNT_CUR              ((volatile uint32_t *)REG_DMA35_XCNT_CUR)               /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA35_YCNT_CUR              ((volatile uint32_t *)REG_DMA35_YCNT_CUR)               /* DMA35 Current Row Count (2D only) */
-#define pREG_DMA35_BWLCNT                ((volatile uint32_t *)REG_DMA35_BWLCNT)                 /* DMA35 Bandwidth Limit Count */
-#define pREG_DMA35_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWLCNT_CUR)             /* DMA35 Bandwidth Limit Count Current */
-#define pREG_DMA35_BWMCNT                ((volatile uint32_t *)REG_DMA35_BWMCNT)                 /* DMA35 Bandwidth Monitor Count */
-#define pREG_DMA35_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA35_BWMCNT_CUR)             /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA36
-   ========================================================================= */
-#define pREG_DMA36_DSCPTR_NXT            ((void * volatile *)REG_DMA36_DSCPTR_NXT)               /* DMA36 Pointer to Next Initial Descriptor */
-#define pREG_DMA36_ADDRSTART             ((void * volatile *)REG_DMA36_ADDRSTART)                /* DMA36 Start Address of Current Buffer */
-#define pREG_DMA36_CFG                   ((volatile uint32_t *)REG_DMA36_CFG)                    /* DMA36 Configuration Register */
-#define pREG_DMA36_XCNT                  ((volatile uint32_t *)REG_DMA36_XCNT)                   /* DMA36 Inner Loop Count Start Value */
-#define pREG_DMA36_XMOD                  ((volatile  int32_t *)REG_DMA36_XMOD)                   /* DMA36 Inner Loop Address Increment */
-#define pREG_DMA36_YCNT                  ((volatile uint32_t *)REG_DMA36_YCNT)                   /* DMA36 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA36_YMOD                  ((volatile  int32_t *)REG_DMA36_YMOD)                   /* DMA36 Outer Loop Address Increment (2D only) */
-#define pREG_DMA36_DSCPTR_CUR            ((void * volatile *)REG_DMA36_DSCPTR_CUR)               /* DMA36 Current Descriptor Pointer */
-#define pREG_DMA36_DSCPTR_PRV            ((void * volatile *)REG_DMA36_DSCPTR_PRV)               /* DMA36 Previous Initial Descriptor Pointer */
-#define pREG_DMA36_ADDR_CUR              ((void * volatile *)REG_DMA36_ADDR_CUR)                 /* DMA36 Current Address */
-#define pREG_DMA36_STAT                  ((volatile uint32_t *)REG_DMA36_STAT)                   /* DMA36 Status Register */
-#define pREG_DMA36_XCNT_CUR              ((volatile uint32_t *)REG_DMA36_XCNT_CUR)               /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA36_YCNT_CUR              ((volatile uint32_t *)REG_DMA36_YCNT_CUR)               /* DMA36 Current Row Count (2D only) */
-#define pREG_DMA36_BWLCNT                ((volatile uint32_t *)REG_DMA36_BWLCNT)                 /* DMA36 Bandwidth Limit Count */
-#define pREG_DMA36_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWLCNT_CUR)             /* DMA36 Bandwidth Limit Count Current */
-#define pREG_DMA36_BWMCNT                ((volatile uint32_t *)REG_DMA36_BWMCNT)                 /* DMA36 Bandwidth Monitor Count */
-#define pREG_DMA36_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA36_BWMCNT_CUR)             /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA37
-   ========================================================================= */
-#define pREG_DMA37_DSCPTR_NXT            ((void * volatile *)REG_DMA37_DSCPTR_NXT)               /* DMA37 Pointer to Next Initial Descriptor */
-#define pREG_DMA37_ADDRSTART             ((void * volatile *)REG_DMA37_ADDRSTART)                /* DMA37 Start Address of Current Buffer */
-#define pREG_DMA37_CFG                   ((volatile uint32_t *)REG_DMA37_CFG)                    /* DMA37 Configuration Register */
-#define pREG_DMA37_XCNT                  ((volatile uint32_t *)REG_DMA37_XCNT)                   /* DMA37 Inner Loop Count Start Value */
-#define pREG_DMA37_XMOD                  ((volatile  int32_t *)REG_DMA37_XMOD)                   /* DMA37 Inner Loop Address Increment */
-#define pREG_DMA37_YCNT                  ((volatile uint32_t *)REG_DMA37_YCNT)                   /* DMA37 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA37_YMOD                  ((volatile  int32_t *)REG_DMA37_YMOD)                   /* DMA37 Outer Loop Address Increment (2D only) */
-#define pREG_DMA37_DSCPTR_CUR            ((void * volatile *)REG_DMA37_DSCPTR_CUR)               /* DMA37 Current Descriptor Pointer */
-#define pREG_DMA37_DSCPTR_PRV            ((void * volatile *)REG_DMA37_DSCPTR_PRV)               /* DMA37 Previous Initial Descriptor Pointer */
-#define pREG_DMA37_ADDR_CUR              ((void * volatile *)REG_DMA37_ADDR_CUR)                 /* DMA37 Current Address */
-#define pREG_DMA37_STAT                  ((volatile uint32_t *)REG_DMA37_STAT)                   /* DMA37 Status Register */
-#define pREG_DMA37_XCNT_CUR              ((volatile uint32_t *)REG_DMA37_XCNT_CUR)               /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA37_YCNT_CUR              ((volatile uint32_t *)REG_DMA37_YCNT_CUR)               /* DMA37 Current Row Count (2D only) */
-#define pREG_DMA37_BWLCNT                ((volatile uint32_t *)REG_DMA37_BWLCNT)                 /* DMA37 Bandwidth Limit Count */
-#define pREG_DMA37_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWLCNT_CUR)             /* DMA37 Bandwidth Limit Count Current */
-#define pREG_DMA37_BWMCNT                ((volatile uint32_t *)REG_DMA37_BWMCNT)                 /* DMA37 Bandwidth Monitor Count */
-#define pREG_DMA37_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA37_BWMCNT_CUR)             /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA38
-   ========================================================================= */
-#define pREG_DMA38_DSCPTR_NXT            ((void * volatile *)REG_DMA38_DSCPTR_NXT)               /* DMA38 Pointer to Next Initial Descriptor */
-#define pREG_DMA38_ADDRSTART             ((void * volatile *)REG_DMA38_ADDRSTART)                /* DMA38 Start Address of Current Buffer */
-#define pREG_DMA38_CFG                   ((volatile uint32_t *)REG_DMA38_CFG)                    /* DMA38 Configuration Register */
-#define pREG_DMA38_XCNT                  ((volatile uint32_t *)REG_DMA38_XCNT)                   /* DMA38 Inner Loop Count Start Value */
-#define pREG_DMA38_XMOD                  ((volatile  int32_t *)REG_DMA38_XMOD)                   /* DMA38 Inner Loop Address Increment */
-#define pREG_DMA38_YCNT                  ((volatile uint32_t *)REG_DMA38_YCNT)                   /* DMA38 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA38_YMOD                  ((volatile  int32_t *)REG_DMA38_YMOD)                   /* DMA38 Outer Loop Address Increment (2D only) */
-#define pREG_DMA38_DSCPTR_CUR            ((void * volatile *)REG_DMA38_DSCPTR_CUR)               /* DMA38 Current Descriptor Pointer */
-#define pREG_DMA38_DSCPTR_PRV            ((void * volatile *)REG_DMA38_DSCPTR_PRV)               /* DMA38 Previous Initial Descriptor Pointer */
-#define pREG_DMA38_ADDR_CUR              ((void * volatile *)REG_DMA38_ADDR_CUR)                 /* DMA38 Current Address */
-#define pREG_DMA38_STAT                  ((volatile uint32_t *)REG_DMA38_STAT)                   /* DMA38 Status Register */
-#define pREG_DMA38_XCNT_CUR              ((volatile uint32_t *)REG_DMA38_XCNT_CUR)               /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA38_YCNT_CUR              ((volatile uint32_t *)REG_DMA38_YCNT_CUR)               /* DMA38 Current Row Count (2D only) */
-#define pREG_DMA38_BWLCNT                ((volatile uint32_t *)REG_DMA38_BWLCNT)                 /* DMA38 Bandwidth Limit Count */
-#define pREG_DMA38_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWLCNT_CUR)             /* DMA38 Bandwidth Limit Count Current */
-#define pREG_DMA38_BWMCNT                ((volatile uint32_t *)REG_DMA38_BWMCNT)                 /* DMA38 Bandwidth Monitor Count */
-#define pREG_DMA38_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA38_BWMCNT_CUR)             /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA39
-   ========================================================================= */
-#define pREG_DMA39_DSCPTR_NXT            ((void * volatile *)REG_DMA39_DSCPTR_NXT)               /* DMA39 Pointer to Next Initial Descriptor */
-#define pREG_DMA39_ADDRSTART             ((void * volatile *)REG_DMA39_ADDRSTART)                /* DMA39 Start Address of Current Buffer */
-#define pREG_DMA39_CFG                   ((volatile uint32_t *)REG_DMA39_CFG)                    /* DMA39 Configuration Register */
-#define pREG_DMA39_XCNT                  ((volatile uint32_t *)REG_DMA39_XCNT)                   /* DMA39 Inner Loop Count Start Value */
-#define pREG_DMA39_XMOD                  ((volatile  int32_t *)REG_DMA39_XMOD)                   /* DMA39 Inner Loop Address Increment */
-#define pREG_DMA39_YCNT                  ((volatile uint32_t *)REG_DMA39_YCNT)                   /* DMA39 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA39_YMOD                  ((volatile  int32_t *)REG_DMA39_YMOD)                   /* DMA39 Outer Loop Address Increment (2D only) */
-#define pREG_DMA39_DSCPTR_CUR            ((void * volatile *)REG_DMA39_DSCPTR_CUR)               /* DMA39 Current Descriptor Pointer */
-#define pREG_DMA39_DSCPTR_PRV            ((void * volatile *)REG_DMA39_DSCPTR_PRV)               /* DMA39 Previous Initial Descriptor Pointer */
-#define pREG_DMA39_ADDR_CUR              ((void * volatile *)REG_DMA39_ADDR_CUR)                 /* DMA39 Current Address */
-#define pREG_DMA39_STAT                  ((volatile uint32_t *)REG_DMA39_STAT)                   /* DMA39 Status Register */
-#define pREG_DMA39_XCNT_CUR              ((volatile uint32_t *)REG_DMA39_XCNT_CUR)               /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA39_YCNT_CUR              ((volatile uint32_t *)REG_DMA39_YCNT_CUR)               /* DMA39 Current Row Count (2D only) */
-#define pREG_DMA39_BWLCNT                ((volatile uint32_t *)REG_DMA39_BWLCNT)                 /* DMA39 Bandwidth Limit Count */
-#define pREG_DMA39_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWLCNT_CUR)             /* DMA39 Bandwidth Limit Count Current */
-#define pREG_DMA39_BWMCNT                ((volatile uint32_t *)REG_DMA39_BWMCNT)                 /* DMA39 Bandwidth Monitor Count */
-#define pREG_DMA39_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA39_BWMCNT_CUR)             /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA40
-   ========================================================================= */
-#define pREG_DMA40_DSCPTR_NXT            ((void * volatile *)REG_DMA40_DSCPTR_NXT)               /* DMA40 Pointer to Next Initial Descriptor */
-#define pREG_DMA40_ADDRSTART             ((void * volatile *)REG_DMA40_ADDRSTART)                /* DMA40 Start Address of Current Buffer */
-#define pREG_DMA40_CFG                   ((volatile uint32_t *)REG_DMA40_CFG)                    /* DMA40 Configuration Register */
-#define pREG_DMA40_XCNT                  ((volatile uint32_t *)REG_DMA40_XCNT)                   /* DMA40 Inner Loop Count Start Value */
-#define pREG_DMA40_XMOD                  ((volatile  int32_t *)REG_DMA40_XMOD)                   /* DMA40 Inner Loop Address Increment */
-#define pREG_DMA40_YCNT                  ((volatile uint32_t *)REG_DMA40_YCNT)                   /* DMA40 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA40_YMOD                  ((volatile  int32_t *)REG_DMA40_YMOD)                   /* DMA40 Outer Loop Address Increment (2D only) */
-#define pREG_DMA40_DSCPTR_CUR            ((void * volatile *)REG_DMA40_DSCPTR_CUR)               /* DMA40 Current Descriptor Pointer */
-#define pREG_DMA40_DSCPTR_PRV            ((void * volatile *)REG_DMA40_DSCPTR_PRV)               /* DMA40 Previous Initial Descriptor Pointer */
-#define pREG_DMA40_ADDR_CUR              ((void * volatile *)REG_DMA40_ADDR_CUR)                 /* DMA40 Current Address */
-#define pREG_DMA40_STAT                  ((volatile uint32_t *)REG_DMA40_STAT)                   /* DMA40 Status Register */
-#define pREG_DMA40_XCNT_CUR              ((volatile uint32_t *)REG_DMA40_XCNT_CUR)               /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA40_YCNT_CUR              ((volatile uint32_t *)REG_DMA40_YCNT_CUR)               /* DMA40 Current Row Count (2D only) */
-#define pREG_DMA40_BWLCNT                ((volatile uint32_t *)REG_DMA40_BWLCNT)                 /* DMA40 Bandwidth Limit Count */
-#define pREG_DMA40_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWLCNT_CUR)             /* DMA40 Bandwidth Limit Count Current */
-#define pREG_DMA40_BWMCNT                ((volatile uint32_t *)REG_DMA40_BWMCNT)                 /* DMA40 Bandwidth Monitor Count */
-#define pREG_DMA40_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA40_BWMCNT_CUR)             /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA41
-   ========================================================================= */
-#define pREG_DMA41_DSCPTR_NXT            ((void * volatile *)REG_DMA41_DSCPTR_NXT)               /* DMA41 Pointer to Next Initial Descriptor */
-#define pREG_DMA41_ADDRSTART             ((void * volatile *)REG_DMA41_ADDRSTART)                /* DMA41 Start Address of Current Buffer */
-#define pREG_DMA41_CFG                   ((volatile uint32_t *)REG_DMA41_CFG)                    /* DMA41 Configuration Register */
-#define pREG_DMA41_XCNT                  ((volatile uint32_t *)REG_DMA41_XCNT)                   /* DMA41 Inner Loop Count Start Value */
-#define pREG_DMA41_XMOD                  ((volatile  int32_t *)REG_DMA41_XMOD)                   /* DMA41 Inner Loop Address Increment */
-#define pREG_DMA41_YCNT                  ((volatile uint32_t *)REG_DMA41_YCNT)                   /* DMA41 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA41_YMOD                  ((volatile  int32_t *)REG_DMA41_YMOD)                   /* DMA41 Outer Loop Address Increment (2D only) */
-#define pREG_DMA41_DSCPTR_CUR            ((void * volatile *)REG_DMA41_DSCPTR_CUR)               /* DMA41 Current Descriptor Pointer */
-#define pREG_DMA41_DSCPTR_PRV            ((void * volatile *)REG_DMA41_DSCPTR_PRV)               /* DMA41 Previous Initial Descriptor Pointer */
-#define pREG_DMA41_ADDR_CUR              ((void * volatile *)REG_DMA41_ADDR_CUR)                 /* DMA41 Current Address */
-#define pREG_DMA41_STAT                  ((volatile uint32_t *)REG_DMA41_STAT)                   /* DMA41 Status Register */
-#define pREG_DMA41_XCNT_CUR              ((volatile uint32_t *)REG_DMA41_XCNT_CUR)               /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA41_YCNT_CUR              ((volatile uint32_t *)REG_DMA41_YCNT_CUR)               /* DMA41 Current Row Count (2D only) */
-#define pREG_DMA41_BWLCNT                ((volatile uint32_t *)REG_DMA41_BWLCNT)                 /* DMA41 Bandwidth Limit Count */
-#define pREG_DMA41_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWLCNT_CUR)             /* DMA41 Bandwidth Limit Count Current */
-#define pREG_DMA41_BWMCNT                ((volatile uint32_t *)REG_DMA41_BWMCNT)                 /* DMA41 Bandwidth Monitor Count */
-#define pREG_DMA41_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA41_BWMCNT_CUR)             /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA42
-   ========================================================================= */
-#define pREG_DMA42_DSCPTR_NXT            ((void * volatile *)REG_DMA42_DSCPTR_NXT)               /* DMA42 Pointer to Next Initial Descriptor */
-#define pREG_DMA42_ADDRSTART             ((void * volatile *)REG_DMA42_ADDRSTART)                /* DMA42 Start Address of Current Buffer */
-#define pREG_DMA42_CFG                   ((volatile uint32_t *)REG_DMA42_CFG)                    /* DMA42 Configuration Register */
-#define pREG_DMA42_XCNT                  ((volatile uint32_t *)REG_DMA42_XCNT)                   /* DMA42 Inner Loop Count Start Value */
-#define pREG_DMA42_XMOD                  ((volatile  int32_t *)REG_DMA42_XMOD)                   /* DMA42 Inner Loop Address Increment */
-#define pREG_DMA42_YCNT                  ((volatile uint32_t *)REG_DMA42_YCNT)                   /* DMA42 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA42_YMOD                  ((volatile  int32_t *)REG_DMA42_YMOD)                   /* DMA42 Outer Loop Address Increment (2D only) */
-#define pREG_DMA42_DSCPTR_CUR            ((void * volatile *)REG_DMA42_DSCPTR_CUR)               /* DMA42 Current Descriptor Pointer */
-#define pREG_DMA42_DSCPTR_PRV            ((void * volatile *)REG_DMA42_DSCPTR_PRV)               /* DMA42 Previous Initial Descriptor Pointer */
-#define pREG_DMA42_ADDR_CUR              ((void * volatile *)REG_DMA42_ADDR_CUR)                 /* DMA42 Current Address */
-#define pREG_DMA42_STAT                  ((volatile uint32_t *)REG_DMA42_STAT)                   /* DMA42 Status Register */
-#define pREG_DMA42_XCNT_CUR              ((volatile uint32_t *)REG_DMA42_XCNT_CUR)               /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA42_YCNT_CUR              ((volatile uint32_t *)REG_DMA42_YCNT_CUR)               /* DMA42 Current Row Count (2D only) */
-#define pREG_DMA42_BWLCNT                ((volatile uint32_t *)REG_DMA42_BWLCNT)                 /* DMA42 Bandwidth Limit Count */
-#define pREG_DMA42_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWLCNT_CUR)             /* DMA42 Bandwidth Limit Count Current */
-#define pREG_DMA42_BWMCNT                ((volatile uint32_t *)REG_DMA42_BWMCNT)                 /* DMA42 Bandwidth Monitor Count */
-#define pREG_DMA42_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA42_BWMCNT_CUR)             /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA43
-   ========================================================================= */
-#define pREG_DMA43_DSCPTR_NXT            ((void * volatile *)REG_DMA43_DSCPTR_NXT)               /* DMA43 Pointer to Next Initial Descriptor */
-#define pREG_DMA43_ADDRSTART             ((void * volatile *)REG_DMA43_ADDRSTART)                /* DMA43 Start Address of Current Buffer */
-#define pREG_DMA43_CFG                   ((volatile uint32_t *)REG_DMA43_CFG)                    /* DMA43 Configuration Register */
-#define pREG_DMA43_XCNT                  ((volatile uint32_t *)REG_DMA43_XCNT)                   /* DMA43 Inner Loop Count Start Value */
-#define pREG_DMA43_XMOD                  ((volatile  int32_t *)REG_DMA43_XMOD)                   /* DMA43 Inner Loop Address Increment */
-#define pREG_DMA43_YCNT                  ((volatile uint32_t *)REG_DMA43_YCNT)                   /* DMA43 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA43_YMOD                  ((volatile  int32_t *)REG_DMA43_YMOD)                   /* DMA43 Outer Loop Address Increment (2D only) */
-#define pREG_DMA43_DSCPTR_CUR            ((void * volatile *)REG_DMA43_DSCPTR_CUR)               /* DMA43 Current Descriptor Pointer */
-#define pREG_DMA43_DSCPTR_PRV            ((void * volatile *)REG_DMA43_DSCPTR_PRV)               /* DMA43 Previous Initial Descriptor Pointer */
-#define pREG_DMA43_ADDR_CUR              ((void * volatile *)REG_DMA43_ADDR_CUR)                 /* DMA43 Current Address */
-#define pREG_DMA43_STAT                  ((volatile uint32_t *)REG_DMA43_STAT)                   /* DMA43 Status Register */
-#define pREG_DMA43_XCNT_CUR              ((volatile uint32_t *)REG_DMA43_XCNT_CUR)               /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA43_YCNT_CUR              ((volatile uint32_t *)REG_DMA43_YCNT_CUR)               /* DMA43 Current Row Count (2D only) */
-#define pREG_DMA43_BWLCNT                ((volatile uint32_t *)REG_DMA43_BWLCNT)                 /* DMA43 Bandwidth Limit Count */
-#define pREG_DMA43_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWLCNT_CUR)             /* DMA43 Bandwidth Limit Count Current */
-#define pREG_DMA43_BWMCNT                ((volatile uint32_t *)REG_DMA43_BWMCNT)                 /* DMA43 Bandwidth Monitor Count */
-#define pREG_DMA43_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA43_BWMCNT_CUR)             /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA44
-   ========================================================================= */
-#define pREG_DMA44_DSCPTR_NXT            ((void * volatile *)REG_DMA44_DSCPTR_NXT)               /* DMA44 Pointer to Next Initial Descriptor */
-#define pREG_DMA44_ADDRSTART             ((void * volatile *)REG_DMA44_ADDRSTART)                /* DMA44 Start Address of Current Buffer */
-#define pREG_DMA44_CFG                   ((volatile uint32_t *)REG_DMA44_CFG)                    /* DMA44 Configuration Register */
-#define pREG_DMA44_XCNT                  ((volatile uint32_t *)REG_DMA44_XCNT)                   /* DMA44 Inner Loop Count Start Value */
-#define pREG_DMA44_XMOD                  ((volatile  int32_t *)REG_DMA44_XMOD)                   /* DMA44 Inner Loop Address Increment */
-#define pREG_DMA44_YCNT                  ((volatile uint32_t *)REG_DMA44_YCNT)                   /* DMA44 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA44_YMOD                  ((volatile  int32_t *)REG_DMA44_YMOD)                   /* DMA44 Outer Loop Address Increment (2D only) */
-#define pREG_DMA44_DSCPTR_CUR            ((void * volatile *)REG_DMA44_DSCPTR_CUR)               /* DMA44 Current Descriptor Pointer */
-#define pREG_DMA44_DSCPTR_PRV            ((void * volatile *)REG_DMA44_DSCPTR_PRV)               /* DMA44 Previous Initial Descriptor Pointer */
-#define pREG_DMA44_ADDR_CUR              ((void * volatile *)REG_DMA44_ADDR_CUR)                 /* DMA44 Current Address */
-#define pREG_DMA44_STAT                  ((volatile uint32_t *)REG_DMA44_STAT)                   /* DMA44 Status Register */
-#define pREG_DMA44_XCNT_CUR              ((volatile uint32_t *)REG_DMA44_XCNT_CUR)               /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA44_YCNT_CUR              ((volatile uint32_t *)REG_DMA44_YCNT_CUR)               /* DMA44 Current Row Count (2D only) */
-#define pREG_DMA44_BWLCNT                ((volatile uint32_t *)REG_DMA44_BWLCNT)                 /* DMA44 Bandwidth Limit Count */
-#define pREG_DMA44_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWLCNT_CUR)             /* DMA44 Bandwidth Limit Count Current */
-#define pREG_DMA44_BWMCNT                ((volatile uint32_t *)REG_DMA44_BWMCNT)                 /* DMA44 Bandwidth Monitor Count */
-#define pREG_DMA44_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA44_BWMCNT_CUR)             /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA45
-   ========================================================================= */
-#define pREG_DMA45_DSCPTR_NXT            ((void * volatile *)REG_DMA45_DSCPTR_NXT)               /* DMA45 Pointer to Next Initial Descriptor */
-#define pREG_DMA45_ADDRSTART             ((void * volatile *)REG_DMA45_ADDRSTART)                /* DMA45 Start Address of Current Buffer */
-#define pREG_DMA45_CFG                   ((volatile uint32_t *)REG_DMA45_CFG)                    /* DMA45 Configuration Register */
-#define pREG_DMA45_XCNT                  ((volatile uint32_t *)REG_DMA45_XCNT)                   /* DMA45 Inner Loop Count Start Value */
-#define pREG_DMA45_XMOD                  ((volatile  int32_t *)REG_DMA45_XMOD)                   /* DMA45 Inner Loop Address Increment */
-#define pREG_DMA45_YCNT                  ((volatile uint32_t *)REG_DMA45_YCNT)                   /* DMA45 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA45_YMOD                  ((volatile  int32_t *)REG_DMA45_YMOD)                   /* DMA45 Outer Loop Address Increment (2D only) */
-#define pREG_DMA45_DSCPTR_CUR            ((void * volatile *)REG_DMA45_DSCPTR_CUR)               /* DMA45 Current Descriptor Pointer */
-#define pREG_DMA45_DSCPTR_PRV            ((void * volatile *)REG_DMA45_DSCPTR_PRV)               /* DMA45 Previous Initial Descriptor Pointer */
-#define pREG_DMA45_ADDR_CUR              ((void * volatile *)REG_DMA45_ADDR_CUR)                 /* DMA45 Current Address */
-#define pREG_DMA45_STAT                  ((volatile uint32_t *)REG_DMA45_STAT)                   /* DMA45 Status Register */
-#define pREG_DMA45_XCNT_CUR              ((volatile uint32_t *)REG_DMA45_XCNT_CUR)               /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA45_YCNT_CUR              ((volatile uint32_t *)REG_DMA45_YCNT_CUR)               /* DMA45 Current Row Count (2D only) */
-#define pREG_DMA45_BWLCNT                ((volatile uint32_t *)REG_DMA45_BWLCNT)                 /* DMA45 Bandwidth Limit Count */
-#define pREG_DMA45_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWLCNT_CUR)             /* DMA45 Bandwidth Limit Count Current */
-#define pREG_DMA45_BWMCNT                ((volatile uint32_t *)REG_DMA45_BWMCNT)                 /* DMA45 Bandwidth Monitor Count */
-#define pREG_DMA45_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA45_BWMCNT_CUR)             /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================================================================
-       DMA46
-   ========================================================================= */
-#define pREG_DMA46_DSCPTR_NXT            ((void * volatile *)REG_DMA46_DSCPTR_NXT)               /* DMA46 Pointer to Next Initial Descriptor */
-#define pREG_DMA46_ADDRSTART             ((void * volatile *)REG_DMA46_ADDRSTART)                /* DMA46 Start Address of Current Buffer */
-#define pREG_DMA46_CFG                   ((volatile uint32_t *)REG_DMA46_CFG)                    /* DMA46 Configuration Register */
-#define pREG_DMA46_XCNT                  ((volatile uint32_t *)REG_DMA46_XCNT)                   /* DMA46 Inner Loop Count Start Value */
-#define pREG_DMA46_XMOD                  ((volatile  int32_t *)REG_DMA46_XMOD)                   /* DMA46 Inner Loop Address Increment */
-#define pREG_DMA46_YCNT                  ((volatile uint32_t *)REG_DMA46_YCNT)                   /* DMA46 Outer Loop Count Start Value (2D only) */
-#define pREG_DMA46_YMOD                  ((volatile  int32_t *)REG_DMA46_YMOD)                   /* DMA46 Outer Loop Address Increment (2D only) */
-#define pREG_DMA46_DSCPTR_CUR            ((void * volatile *)REG_DMA46_DSCPTR_CUR)               /* DMA46 Current Descriptor Pointer */
-#define pREG_DMA46_DSCPTR_PRV            ((void * volatile *)REG_DMA46_DSCPTR_PRV)               /* DMA46 Previous Initial Descriptor Pointer */
-#define pREG_DMA46_ADDR_CUR              ((void * volatile *)REG_DMA46_ADDR_CUR)                 /* DMA46 Current Address */
-#define pREG_DMA46_STAT                  ((volatile uint32_t *)REG_DMA46_STAT)                   /* DMA46 Status Register */
-#define pREG_DMA46_XCNT_CUR              ((volatile uint32_t *)REG_DMA46_XCNT_CUR)               /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define pREG_DMA46_YCNT_CUR              ((volatile uint32_t *)REG_DMA46_YCNT_CUR)               /* DMA46 Current Row Count (2D only) */
-#define pREG_DMA46_BWLCNT                ((volatile uint32_t *)REG_DMA46_BWLCNT)                 /* DMA46 Bandwidth Limit Count */
-#define pREG_DMA46_BWLCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWLCNT_CUR)             /* DMA46 Bandwidth Limit Count Current */
-#define pREG_DMA46_BWMCNT                ((volatile uint32_t *)REG_DMA46_BWMCNT)                 /* DMA46 Bandwidth Monitor Count */
-#define pREG_DMA46_BWMCNT_CUR            ((volatile uint32_t *)REG_DMA46_BWMCNT_CUR)             /* DMA46 Bandwidth Monitor Count Current */
-
-
-/* =========================================================================
-       ACM0
-   ========================================================================= */
-#define pREG_ACM0_CTL                    ((volatile uint32_t *)REG_ACM0_CTL)                     /* ACM0 ACM Control Register */
-#define pREG_ACM0_TC0                    ((volatile uint32_t *)REG_ACM0_TC0)                     /* ACM0 ACM Timing Configuration 0 Register */
-#define pREG_ACM0_TC1                    ((volatile uint32_t *)REG_ACM0_TC1)                     /* ACM0 ACM Timing Configuration 1 Register */
-#define pREG_ACM0_STAT                   ((volatile uint32_t *)REG_ACM0_STAT)                    /* ACM0 ACM Status Register */
-#define pREG_ACM0_EVSTAT                 ((volatile uint32_t *)REG_ACM0_EVSTAT)                  /* ACM0 ACM Event Status Register */
-#define pREG_ACM0_EVMSK                  ((volatile uint32_t *)REG_ACM0_EVMSK)                   /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define pREG_ACM0_MEVSTAT                ((volatile uint32_t *)REG_ACM0_MEVSTAT)                 /* ACM0 ACM Missed Event Status Register */
-#define pREG_ACM0_MEVMSK                 ((volatile uint32_t *)REG_ACM0_MEVMSK)                  /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define pREG_ACM0_EVCTL0                 ((volatile uint32_t *)REG_ACM0_EVCTL0)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL1                 ((volatile uint32_t *)REG_ACM0_EVCTL1)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL2                 ((volatile uint32_t *)REG_ACM0_EVCTL2)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL3                 ((volatile uint32_t *)REG_ACM0_EVCTL3)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL4                 ((volatile uint32_t *)REG_ACM0_EVCTL4)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL5                 ((volatile uint32_t *)REG_ACM0_EVCTL5)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL6                 ((volatile uint32_t *)REG_ACM0_EVCTL6)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL7                 ((volatile uint32_t *)REG_ACM0_EVCTL7)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL8                 ((volatile uint32_t *)REG_ACM0_EVCTL8)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL9                 ((volatile uint32_t *)REG_ACM0_EVCTL9)                  /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL10                ((volatile uint32_t *)REG_ACM0_EVCTL10)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL11                ((volatile uint32_t *)REG_ACM0_EVCTL11)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL12                ((volatile uint32_t *)REG_ACM0_EVCTL12)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL13                ((volatile uint32_t *)REG_ACM0_EVCTL13)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL14                ((volatile uint32_t *)REG_ACM0_EVCTL14)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVCTL15                ((volatile uint32_t *)REG_ACM0_EVCTL15)                 /* ACM0 ACM Eventn Control Register */
-#define pREG_ACM0_EVTIME0                ((volatile uint32_t *)REG_ACM0_EVTIME0)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME1                ((volatile uint32_t *)REG_ACM0_EVTIME1)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME2                ((volatile uint32_t *)REG_ACM0_EVTIME2)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME3                ((volatile uint32_t *)REG_ACM0_EVTIME3)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME4                ((volatile uint32_t *)REG_ACM0_EVTIME4)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME5                ((volatile uint32_t *)REG_ACM0_EVTIME5)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME6                ((volatile uint32_t *)REG_ACM0_EVTIME6)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME7                ((volatile uint32_t *)REG_ACM0_EVTIME7)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME8                ((volatile uint32_t *)REG_ACM0_EVTIME8)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME9                ((volatile uint32_t *)REG_ACM0_EVTIME9)                 /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME10               ((volatile uint32_t *)REG_ACM0_EVTIME10)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME11               ((volatile uint32_t *)REG_ACM0_EVTIME11)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME12               ((volatile uint32_t *)REG_ACM0_EVTIME12)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME13               ((volatile uint32_t *)REG_ACM0_EVTIME13)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME14               ((volatile uint32_t *)REG_ACM0_EVTIME14)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVTIME15               ((volatile uint32_t *)REG_ACM0_EVTIME15)                /* ACM0 ACM Eventn Time Register */
-#define pREG_ACM0_EVORD0                 ((volatile uint32_t *)REG_ACM0_EVORD0)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD1                 ((volatile uint32_t *)REG_ACM0_EVORD1)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD2                 ((volatile uint32_t *)REG_ACM0_EVORD2)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD3                 ((volatile uint32_t *)REG_ACM0_EVORD3)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD4                 ((volatile uint32_t *)REG_ACM0_EVORD4)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD5                 ((volatile uint32_t *)REG_ACM0_EVORD5)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD6                 ((volatile uint32_t *)REG_ACM0_EVORD6)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD7                 ((volatile uint32_t *)REG_ACM0_EVORD7)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD8                 ((volatile uint32_t *)REG_ACM0_EVORD8)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD9                 ((volatile uint32_t *)REG_ACM0_EVORD9)                  /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD10                ((volatile uint32_t *)REG_ACM0_EVORD10)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD11                ((volatile uint32_t *)REG_ACM0_EVORD11)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD12                ((volatile uint32_t *)REG_ACM0_EVORD12)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD13                ((volatile uint32_t *)REG_ACM0_EVORD13)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD14                ((volatile uint32_t *)REG_ACM0_EVORD14)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_EVORD15                ((volatile uint32_t *)REG_ACM0_EVORD15)                 /* ACM0 ACM Eventn Order Register */
-#define pREG_ACM0_TMR0                   ((volatile uint32_t *)REG_ACM0_TMR0)                    /* ACM0 ACM Timer 0 Register */
-#define pREG_ACM0_TMR1                   ((volatile uint32_t *)REG_ACM0_TMR1)                    /* ACM0 ACM Timer 1 Register */
-
-
-/* =========================================================================
-       DMC0
-   ========================================================================= */
-#define pREG_DMC0_CTL                    ((volatile uint32_t *)REG_DMC0_CTL)                     /* DMC0 Control Register */
-#define pREG_DMC0_STAT                   ((volatile uint32_t *)REG_DMC0_STAT)                    /* DMC0 Status Register */
-#define pREG_DMC0_EFFCTL                 ((volatile uint32_t *)REG_DMC0_EFFCTL)                  /* DMC0 Efficiency Control Register */
-#define pREG_DMC0_PRIO                   ((volatile uint32_t *)REG_DMC0_PRIO)                    /* DMC0 Priority ID Register */
-#define pREG_DMC0_PRIOMSK                ((volatile uint32_t *)REG_DMC0_PRIOMSK)                 /* DMC0 Priority ID Mask Register */
-#define pREG_DMC0_CFG                    ((volatile uint32_t *)REG_DMC0_CFG)                     /* DMC0 Configuration Register */
-#define pREG_DMC0_TR0                    ((volatile uint32_t *)REG_DMC0_TR0)                     /* DMC0 Timing 0 Register */
-#define pREG_DMC0_TR1                    ((volatile uint32_t *)REG_DMC0_TR1)                     /* DMC0 Timing 1 Register */
-#define pREG_DMC0_TR2                    ((volatile uint32_t *)REG_DMC0_TR2)                     /* DMC0 Timing 2 Register */
-#define pREG_DMC0_MSK                    ((volatile uint32_t *)REG_DMC0_MSK)                     /* DMC0 Mask (Mode Register Shadow) Register */
-#define pREG_DMC0_MR                     ((volatile uint32_t *)REG_DMC0_MR)                      /* DMC0 Shadow MR Register */
-#define pREG_DMC0_EMR1                   ((volatile uint32_t *)REG_DMC0_EMR1)                    /* DMC0 Shadow EMR1 Register */
-#define pREG_DMC0_EMR2                   ((volatile uint32_t *)REG_DMC0_EMR2)                    /* DMC0 Shadow EMR2 Register */
-#define pREG_DMC0_EMR3                   ((volatile uint32_t *)REG_DMC0_EMR3)                    /* DMC0 Shadow EMR3 Register */
-#define pREG_DMC0_DLLCTL                 ((volatile uint32_t *)REG_DMC0_DLLCTL)                  /* DMC0 DLL Control Register */
-#define pREG_DMC0_PHY_CTL0               ((volatile uint32_t *)REG_DMC0_PHY_CTL0)                /* DMC0 PHY Control 0 Register */
-#define pREG_DMC0_PHY_CTL1               ((volatile uint32_t *)REG_DMC0_PHY_CTL1)                /* DMC0 PHY Control 1 Register */
-#define pREG_DMC0_PHY_CTL2               ((volatile uint32_t *)REG_DMC0_PHY_CTL2)                /* DMC0 PHY Control 2 Register */
-#define pREG_DMC0_PHY_CTL3               ((volatile uint32_t *)REG_DMC0_PHY_CTL3)                /* DMC0 PHY Control 3 Register */
-#define pREG_DMC0_PADCTL                 ((volatile uint32_t *)REG_DMC0_PADCTL)                  /* DMC0 PAD Control Register */
-
-
-/* =========================================================================
-       SCB0
-   ========================================================================= */
-#define pREG_SCB0_ARBR0                  ((volatile uint32_t *)REG_SCB0_ARBR0)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR1                  ((volatile uint32_t *)REG_SCB0_ARBR1)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR2                  ((volatile uint32_t *)REG_SCB0_ARBR2)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR3                  ((volatile uint32_t *)REG_SCB0_ARBR3)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR4                  ((volatile uint32_t *)REG_SCB0_ARBR4)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBR5                  ((volatile uint32_t *)REG_SCB0_ARBR5)                   /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB0_ARBW0                  ((volatile uint32_t *)REG_SCB0_ARBW0)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW1                  ((volatile uint32_t *)REG_SCB0_ARBW1)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW2                  ((volatile uint32_t *)REG_SCB0_ARBW2)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW3                  ((volatile uint32_t *)REG_SCB0_ARBW3)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW4                  ((volatile uint32_t *)REG_SCB0_ARBW4)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_ARBW5                  ((volatile uint32_t *)REG_SCB0_ARBW5)                   /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB0_SLAVES                 ((volatile uint32_t *)REG_SCB0_SLAVES)                  /* SCB0 Slave Interfaces Number Register */
-#define pREG_SCB0_MASTERS                ((volatile uint32_t *)REG_SCB0_MASTERS)                 /* SCB0 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB1
-   ========================================================================= */
-#define pREG_SCB1_ARBR0                  ((volatile uint32_t *)REG_SCB1_ARBR0)                   /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB1_ARBW0                  ((volatile uint32_t *)REG_SCB1_ARBW0)                   /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB1_SLAVES                 ((volatile uint32_t *)REG_SCB1_SLAVES)                  /* SCB1 Slave Interfaces Number Register */
-#define pREG_SCB1_MASTERS                ((volatile uint32_t *)REG_SCB1_MASTERS)                 /* SCB1 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB2
-   ========================================================================= */
-#define pREG_SCB2_ARBR0                  ((volatile uint32_t *)REG_SCB2_ARBR0)                   /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB2_ARBW0                  ((volatile uint32_t *)REG_SCB2_ARBW0)                   /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB2_SLAVES                 ((volatile uint32_t *)REG_SCB2_SLAVES)                  /* SCB2 Slave Interfaces Number Register */
-#define pREG_SCB2_MASTERS                ((volatile uint32_t *)REG_SCB2_MASTERS)                 /* SCB2 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB3
-   ========================================================================= */
-#define pREG_SCB3_ARBR0                  ((volatile uint32_t *)REG_SCB3_ARBR0)                   /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB3_ARBW0                  ((volatile uint32_t *)REG_SCB3_ARBW0)                   /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB3_SLAVES                 ((volatile uint32_t *)REG_SCB3_SLAVES)                  /* SCB3 Slave Interfaces Number Register */
-#define pREG_SCB3_MASTERS                ((volatile uint32_t *)REG_SCB3_MASTERS)                 /* SCB3 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB4
-   ========================================================================= */
-#define pREG_SCB4_ARBR0                  ((volatile uint32_t *)REG_SCB4_ARBR0)                   /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB4_ARBW0                  ((volatile uint32_t *)REG_SCB4_ARBW0)                   /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB4_SLAVES                 ((volatile uint32_t *)REG_SCB4_SLAVES)                  /* SCB4 Slave Interfaces Number Register */
-#define pREG_SCB4_MASTERS                ((volatile uint32_t *)REG_SCB4_MASTERS)                 /* SCB4 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB5
-   ========================================================================= */
-#define pREG_SCB5_ARBR0                  ((volatile uint32_t *)REG_SCB5_ARBR0)                   /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB5_ARBW0                  ((volatile uint32_t *)REG_SCB5_ARBW0)                   /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB5_SLAVES                 ((volatile uint32_t *)REG_SCB5_SLAVES)                  /* SCB5 Slave Interfaces Number Register */
-#define pREG_SCB5_MASTERS                ((volatile uint32_t *)REG_SCB5_MASTERS)                 /* SCB5 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB6
-   ========================================================================= */
-#define pREG_SCB6_ARBR0                  ((volatile uint32_t *)REG_SCB6_ARBR0)                   /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB6_ARBW0                  ((volatile uint32_t *)REG_SCB6_ARBW0)                   /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB6_SLAVES                 ((volatile uint32_t *)REG_SCB6_SLAVES)                  /* SCB6 Slave Interfaces Number Register */
-#define pREG_SCB6_MASTERS                ((volatile uint32_t *)REG_SCB6_MASTERS)                 /* SCB6 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB7
-   ========================================================================= */
-#define pREG_SCB7_ARBR0                  ((volatile uint32_t *)REG_SCB7_ARBR0)                   /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB7_ARBW0                  ((volatile uint32_t *)REG_SCB7_ARBW0)                   /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB7_SLAVES                 ((volatile uint32_t *)REG_SCB7_SLAVES)                  /* SCB7 Slave Interfaces Number Register */
-#define pREG_SCB7_MASTERS                ((volatile uint32_t *)REG_SCB7_MASTERS)                 /* SCB7 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB8
-   ========================================================================= */
-#define pREG_SCB8_ARBR0                  ((volatile uint32_t *)REG_SCB8_ARBR0)                   /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB8_ARBW0                  ((volatile uint32_t *)REG_SCB8_ARBW0)                   /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB8_SLAVES                 ((volatile uint32_t *)REG_SCB8_SLAVES)                  /* SCB8 Slave Interfaces Number Register */
-#define pREG_SCB8_MASTERS                ((volatile uint32_t *)REG_SCB8_MASTERS)                 /* SCB8 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB9
-   ========================================================================= */
-#define pREG_SCB9_ARBR0                  ((volatile uint32_t *)REG_SCB9_ARBR0)                   /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB9_ARBW0                  ((volatile uint32_t *)REG_SCB9_ARBW0)                   /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB9_SLAVES                 ((volatile uint32_t *)REG_SCB9_SLAVES)                  /* SCB9 Slave Interfaces Number Register */
-#define pREG_SCB9_MASTERS                ((volatile uint32_t *)REG_SCB9_MASTERS)                 /* SCB9 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB10
-   ========================================================================= */
-#define pREG_SCB10_ARBR0                 ((volatile uint32_t *)REG_SCB10_ARBR0)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR1                 ((volatile uint32_t *)REG_SCB10_ARBR1)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBR2                 ((volatile uint32_t *)REG_SCB10_ARBR2)                  /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB10_ARBW0                 ((volatile uint32_t *)REG_SCB10_ARBW0)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW1                 ((volatile uint32_t *)REG_SCB10_ARBW1)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_ARBW2                 ((volatile uint32_t *)REG_SCB10_ARBW2)                  /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB10_SLAVES                ((volatile uint32_t *)REG_SCB10_SLAVES)                 /* SCB10 Slave Interfaces Number Register */
-#define pREG_SCB10_MASTERS               ((volatile uint32_t *)REG_SCB10_MASTERS)                /* SCB10 Master Interfaces Number Register */
-
-/* =========================================================================
-       SCB11
-   ========================================================================= */
-#define pREG_SCB11_ARBR0                 ((volatile uint32_t *)REG_SCB11_ARBR0)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR1                 ((volatile uint32_t *)REG_SCB11_ARBR1)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR2                 ((volatile uint32_t *)REG_SCB11_ARBR2)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR3                 ((volatile uint32_t *)REG_SCB11_ARBR3)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR4                 ((volatile uint32_t *)REG_SCB11_ARBR4)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR5                 ((volatile uint32_t *)REG_SCB11_ARBR5)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBR6                 ((volatile uint32_t *)REG_SCB11_ARBR6)                  /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define pREG_SCB11_ARBW0                 ((volatile uint32_t *)REG_SCB11_ARBW0)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW1                 ((volatile uint32_t *)REG_SCB11_ARBW1)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW2                 ((volatile uint32_t *)REG_SCB11_ARBW2)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW3                 ((volatile uint32_t *)REG_SCB11_ARBW3)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW4                 ((volatile uint32_t *)REG_SCB11_ARBW4)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW5                 ((volatile uint32_t *)REG_SCB11_ARBW5)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_ARBW6                 ((volatile uint32_t *)REG_SCB11_ARBW6)                  /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define pREG_SCB11_SLAVES                ((volatile uint32_t *)REG_SCB11_SLAVES)                 /* SCB11 Slave Interfaces Number Register */
-#define pREG_SCB11_MASTERS               ((volatile uint32_t *)REG_SCB11_MASTERS)                /* SCB11 Master Interfaces Number Register */
-
-
-/* =========================================================================
-       L2CTL0
-   ========================================================================= */
-#define pREG_L2CTL0_CTL                  ((volatile uint32_t *)REG_L2CTL0_CTL)                   /* L2CTL0 Control Register */
-#define pREG_L2CTL0_ACTL_C0              ((volatile uint32_t *)REG_L2CTL0_ACTL_C0)               /* L2CTL0 Access Control Core 0 Register */
-#define pREG_L2CTL0_ACTL_C1              ((volatile uint32_t *)REG_L2CTL0_ACTL_C1)               /* L2CTL0 Access Control Core 1 Register */
-#define pREG_L2CTL0_ACTL_SYS             ((volatile uint32_t *)REG_L2CTL0_ACTL_SYS)              /* L2CTL0 Access Control System Register */
-#define pREG_L2CTL0_STAT                 ((volatile uint32_t *)REG_L2CTL0_STAT)                  /* L2CTL0 Status Register */
-#define pREG_L2CTL0_RPCR                 ((volatile uint32_t *)REG_L2CTL0_RPCR)                  /* L2CTL0 Read Priority Count Register */
-#define pREG_L2CTL0_WPCR                 ((volatile uint32_t *)REG_L2CTL0_WPCR)                  /* L2CTL0 Write Priority Count Register */
-#define pREG_L2CTL0_RFA                  ((void * volatile *)REG_L2CTL0_RFA)                     /* L2CTL0 Refresh Address Register */
-#define pREG_L2CTL0_ERRADDR0             ((void * volatile *)REG_L2CTL0_ERRADDR0)                /* L2CTL0 ECC Error Address 0 Register */
-#define pREG_L2CTL0_ERRADDR1             ((void * volatile *)REG_L2CTL0_ERRADDR1)                /* L2CTL0 ECC Error Address 1 Register */
-#define pREG_L2CTL0_ERRADDR2             ((void * volatile *)REG_L2CTL0_ERRADDR2)                /* L2CTL0 ECC Error Address 2 Register */
-#define pREG_L2CTL0_ERRADDR3             ((void * volatile *)REG_L2CTL0_ERRADDR3)                /* L2CTL0 ECC Error Address 3 Register */
-#define pREG_L2CTL0_ERRADDR4             ((void * volatile *)REG_L2CTL0_ERRADDR4)                /* L2CTL0 ECC Error Address 4 Register */
-#define pREG_L2CTL0_ERRADDR5             ((void * volatile *)REG_L2CTL0_ERRADDR5)                /* L2CTL0 ECC Error Address 5 Register */
-#define pREG_L2CTL0_ERRADDR6             ((void * volatile *)REG_L2CTL0_ERRADDR6)                /* L2CTL0 ECC Error Address 6 Register */
-#define pREG_L2CTL0_ERRADDR7             ((void * volatile *)REG_L2CTL0_ERRADDR7)                /* L2CTL0 ECC Error Address 7 Register */
-#define pREG_L2CTL0_ET0                  ((volatile uint32_t *)REG_L2CTL0_ET0)                   /* L2CTL0 Error Type 0 Register */
-#define pREG_L2CTL0_EADDR0               ((void * volatile *)REG_L2CTL0_EADDR0)                  /* L2CTL0 Error Type 0 Address Register */
-#define pREG_L2CTL0_ET1                  ((volatile uint32_t *)REG_L2CTL0_ET1)                   /* L2CTL0 Error Type 1 Register */
-#define pREG_L2CTL0_EADDR1               ((void * volatile *)REG_L2CTL0_EADDR1)                  /* L2CTL0 Error Type 1 Address Register */
-
-
-/* =========================================================================
-       SEC0
-   ========================================================================= */
-
-/*    SEC Core Interface (SCI) Registers    */
-#define pREG_SEC0_CCTL0                  ((volatile uint32_t *)REG_SEC0_CCTL0)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CCTL1                  ((volatile uint32_t *)REG_SEC0_CCTL1)                   /* SEC0 SCI Control Register n */
-#define pREG_SEC0_CSTAT0                 ((volatile uint32_t *)REG_SEC0_CSTAT0)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CSTAT1                 ((volatile uint32_t *)REG_SEC0_CSTAT1)                  /* SEC0 SCI Status Register n */
-#define pREG_SEC0_CPND0                  ((volatile uint32_t *)REG_SEC0_CPND0)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CPND1                  ((volatile uint32_t *)REG_SEC0_CPND1)                   /* SEC0 Core Pending Register n */
-#define pREG_SEC0_CACT0                  ((volatile uint32_t *)REG_SEC0_CACT0)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CACT1                  ((volatile uint32_t *)REG_SEC0_CACT1)                   /* SEC0 SCI Active Register n */
-#define pREG_SEC0_CPMSK0                 ((volatile uint32_t *)REG_SEC0_CPMSK0)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CPMSK1                 ((volatile uint32_t *)REG_SEC0_CPMSK1)                  /* SEC0 SCI Priority Mask Register n */
-#define pREG_SEC0_CGMSK0                 ((volatile uint32_t *)REG_SEC0_CGMSK0)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CGMSK1                 ((volatile uint32_t *)REG_SEC0_CGMSK1)                  /* SEC0 SCI Group Mask Register n */
-#define pREG_SEC0_CPLVL0                 ((volatile uint32_t *)REG_SEC0_CPLVL0)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CPLVL1                 ((volatile uint32_t *)REG_SEC0_CPLVL1)                  /* SEC0 SCI Priority Level Register n */
-#define pREG_SEC0_CSID0                  ((volatile uint32_t *)REG_SEC0_CSID0)                   /* SEC0 SCI Source ID Register n */
-#define pREG_SEC0_CSID1                  ((volatile uint32_t *)REG_SEC0_CSID1)                   /* SEC0 SCI Source ID Register n */
-
-/*    SEC Fault Management Interface (SFI) Registers    */
-#define pREG_SEC0_FCTL                   ((volatile uint32_t *)REG_SEC0_FCTL)                    /* SEC0 Fault Control Register */
-#define pREG_SEC0_FSTAT                  ((volatile uint32_t *)REG_SEC0_FSTAT)                   /* SEC0 Fault Status Register */
-#define pREG_SEC0_FSID                   ((volatile uint32_t *)REG_SEC0_FSID)                    /* SEC0 Fault Source ID Register */
-#define pREG_SEC0_FEND                   ((volatile uint32_t *)REG_SEC0_FEND)                    /* SEC0 Fault End Register */
-#define pREG_SEC0_FDLY                   ((volatile uint32_t *)REG_SEC0_FDLY)                    /* SEC0 Fault Delay Register */
-#define pREG_SEC0_FDLY_CUR               ((volatile uint32_t *)REG_SEC0_FDLY_CUR)                /* SEC0 Fault Delay Current Register */
-#define pREG_SEC0_FSRDLY                 ((volatile uint32_t *)REG_SEC0_FSRDLY)                  /* SEC0 Fault System Reset Delay Register */
-#define pREG_SEC0_FSRDLY_CUR             ((volatile uint32_t *)REG_SEC0_FSRDLY_CUR)              /* SEC0 Fault System Reset Delay Current Register */
-#define pREG_SEC0_FCOPP                  ((volatile uint32_t *)REG_SEC0_FCOPP)                   /* SEC0 Fault COP Period Register */
-#define pREG_SEC0_FCOPP_CUR              ((volatile uint32_t *)REG_SEC0_FCOPP_CUR)               /* SEC0 Fault COP Period Current Register */
-
-/*    SEC Global Registers    */
-#define pREG_SEC0_GCTL                   ((volatile uint32_t *)REG_SEC0_GCTL)                    /* SEC0 Global Control Register */
-#define pREG_SEC0_GSTAT                  ((volatile uint32_t *)REG_SEC0_GSTAT)                   /* SEC0 Global Status Register */
-#define pREG_SEC0_RAISE                  ((volatile uint32_t *)REG_SEC0_RAISE)                   /* SEC0 Global Raise Register */
-#define pREG_SEC0_END                    ((volatile uint32_t *)REG_SEC0_END)                     /* SEC0 Global End Register */
-
-/*    SEC Source Interface (SSI) Registers    */
-#define pREG_SEC0_SCTL0                  ((volatile uint32_t *)REG_SEC0_SCTL0)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL1                  ((volatile uint32_t *)REG_SEC0_SCTL1)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL2                  ((volatile uint32_t *)REG_SEC0_SCTL2)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL3                  ((volatile uint32_t *)REG_SEC0_SCTL3)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL4                  ((volatile uint32_t *)REG_SEC0_SCTL4)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL5                  ((volatile uint32_t *)REG_SEC0_SCTL5)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL6                  ((volatile uint32_t *)REG_SEC0_SCTL6)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL7                  ((volatile uint32_t *)REG_SEC0_SCTL7)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL8                  ((volatile uint32_t *)REG_SEC0_SCTL8)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL9                  ((volatile uint32_t *)REG_SEC0_SCTL9)                   /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL10                 ((volatile uint32_t *)REG_SEC0_SCTL10)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL11                 ((volatile uint32_t *)REG_SEC0_SCTL11)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL12                 ((volatile uint32_t *)REG_SEC0_SCTL12)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL13                 ((volatile uint32_t *)REG_SEC0_SCTL13)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL14                 ((volatile uint32_t *)REG_SEC0_SCTL14)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL15                 ((volatile uint32_t *)REG_SEC0_SCTL15)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL16                 ((volatile uint32_t *)REG_SEC0_SCTL16)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL17                 ((volatile uint32_t *)REG_SEC0_SCTL17)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL18                 ((volatile uint32_t *)REG_SEC0_SCTL18)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL19                 ((volatile uint32_t *)REG_SEC0_SCTL19)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL20                 ((volatile uint32_t *)REG_SEC0_SCTL20)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL21                 ((volatile uint32_t *)REG_SEC0_SCTL21)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL22                 ((volatile uint32_t *)REG_SEC0_SCTL22)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL23                 ((volatile uint32_t *)REG_SEC0_SCTL23)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL24                 ((volatile uint32_t *)REG_SEC0_SCTL24)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL25                 ((volatile uint32_t *)REG_SEC0_SCTL25)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL26                 ((volatile uint32_t *)REG_SEC0_SCTL26)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL27                 ((volatile uint32_t *)REG_SEC0_SCTL27)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL28                 ((volatile uint32_t *)REG_SEC0_SCTL28)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL29                 ((volatile uint32_t *)REG_SEC0_SCTL29)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL30                 ((volatile uint32_t *)REG_SEC0_SCTL30)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL31                 ((volatile uint32_t *)REG_SEC0_SCTL31)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL32                 ((volatile uint32_t *)REG_SEC0_SCTL32)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL33                 ((volatile uint32_t *)REG_SEC0_SCTL33)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL34                 ((volatile uint32_t *)REG_SEC0_SCTL34)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL35                 ((volatile uint32_t *)REG_SEC0_SCTL35)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL36                 ((volatile uint32_t *)REG_SEC0_SCTL36)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL37                 ((volatile uint32_t *)REG_SEC0_SCTL37)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL38                 ((volatile uint32_t *)REG_SEC0_SCTL38)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL39                 ((volatile uint32_t *)REG_SEC0_SCTL39)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL40                 ((volatile uint32_t *)REG_SEC0_SCTL40)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL41                 ((volatile uint32_t *)REG_SEC0_SCTL41)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL42                 ((volatile uint32_t *)REG_SEC0_SCTL42)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL43                 ((volatile uint32_t *)REG_SEC0_SCTL43)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL44                 ((volatile uint32_t *)REG_SEC0_SCTL44)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL45                 ((volatile uint32_t *)REG_SEC0_SCTL45)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL46                 ((volatile uint32_t *)REG_SEC0_SCTL46)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL47                 ((volatile uint32_t *)REG_SEC0_SCTL47)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL48                 ((volatile uint32_t *)REG_SEC0_SCTL48)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL49                 ((volatile uint32_t *)REG_SEC0_SCTL49)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL50                 ((volatile uint32_t *)REG_SEC0_SCTL50)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL51                 ((volatile uint32_t *)REG_SEC0_SCTL51)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL52                 ((volatile uint32_t *)REG_SEC0_SCTL52)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL53                 ((volatile uint32_t *)REG_SEC0_SCTL53)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL54                 ((volatile uint32_t *)REG_SEC0_SCTL54)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL55                 ((volatile uint32_t *)REG_SEC0_SCTL55)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL56                 ((volatile uint32_t *)REG_SEC0_SCTL56)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL57                 ((volatile uint32_t *)REG_SEC0_SCTL57)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL58                 ((volatile uint32_t *)REG_SEC0_SCTL58)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL59                 ((volatile uint32_t *)REG_SEC0_SCTL59)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL60                 ((volatile uint32_t *)REG_SEC0_SCTL60)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL61                 ((volatile uint32_t *)REG_SEC0_SCTL61)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL62                 ((volatile uint32_t *)REG_SEC0_SCTL62)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL63                 ((volatile uint32_t *)REG_SEC0_SCTL63)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL64                 ((volatile uint32_t *)REG_SEC0_SCTL64)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL65                 ((volatile uint32_t *)REG_SEC0_SCTL65)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL66                 ((volatile uint32_t *)REG_SEC0_SCTL66)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL67                 ((volatile uint32_t *)REG_SEC0_SCTL67)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL68                 ((volatile uint32_t *)REG_SEC0_SCTL68)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL69                 ((volatile uint32_t *)REG_SEC0_SCTL69)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL70                 ((volatile uint32_t *)REG_SEC0_SCTL70)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL71                 ((volatile uint32_t *)REG_SEC0_SCTL71)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL72                 ((volatile uint32_t *)REG_SEC0_SCTL72)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL73                 ((volatile uint32_t *)REG_SEC0_SCTL73)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL74                 ((volatile uint32_t *)REG_SEC0_SCTL74)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL75                 ((volatile uint32_t *)REG_SEC0_SCTL75)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL76                 ((volatile uint32_t *)REG_SEC0_SCTL76)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL77                 ((volatile uint32_t *)REG_SEC0_SCTL77)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL78                 ((volatile uint32_t *)REG_SEC0_SCTL78)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL79                 ((volatile uint32_t *)REG_SEC0_SCTL79)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL80                 ((volatile uint32_t *)REG_SEC0_SCTL80)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL81                 ((volatile uint32_t *)REG_SEC0_SCTL81)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL82                 ((volatile uint32_t *)REG_SEC0_SCTL82)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL83                 ((volatile uint32_t *)REG_SEC0_SCTL83)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL84                 ((volatile uint32_t *)REG_SEC0_SCTL84)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL85                 ((volatile uint32_t *)REG_SEC0_SCTL85)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL86                 ((volatile uint32_t *)REG_SEC0_SCTL86)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL87                 ((volatile uint32_t *)REG_SEC0_SCTL87)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL88                 ((volatile uint32_t *)REG_SEC0_SCTL88)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL89                 ((volatile uint32_t *)REG_SEC0_SCTL89)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL90                 ((volatile uint32_t *)REG_SEC0_SCTL90)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL91                 ((volatile uint32_t *)REG_SEC0_SCTL91)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL92                 ((volatile uint32_t *)REG_SEC0_SCTL92)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL93                 ((volatile uint32_t *)REG_SEC0_SCTL93)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL94                 ((volatile uint32_t *)REG_SEC0_SCTL94)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL95                 ((volatile uint32_t *)REG_SEC0_SCTL95)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL96                 ((volatile uint32_t *)REG_SEC0_SCTL96)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL97                 ((volatile uint32_t *)REG_SEC0_SCTL97)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL98                 ((volatile uint32_t *)REG_SEC0_SCTL98)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL99                 ((volatile uint32_t *)REG_SEC0_SCTL99)                  /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL100                ((volatile uint32_t *)REG_SEC0_SCTL100)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL101                ((volatile uint32_t *)REG_SEC0_SCTL101)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL102                ((volatile uint32_t *)REG_SEC0_SCTL102)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL103                ((volatile uint32_t *)REG_SEC0_SCTL103)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL104                ((volatile uint32_t *)REG_SEC0_SCTL104)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL105                ((volatile uint32_t *)REG_SEC0_SCTL105)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL106                ((volatile uint32_t *)REG_SEC0_SCTL106)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL107                ((volatile uint32_t *)REG_SEC0_SCTL107)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL108                ((volatile uint32_t *)REG_SEC0_SCTL108)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL109                ((volatile uint32_t *)REG_SEC0_SCTL109)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL110                ((volatile uint32_t *)REG_SEC0_SCTL110)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL111                ((volatile uint32_t *)REG_SEC0_SCTL111)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL112                ((volatile uint32_t *)REG_SEC0_SCTL112)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL113                ((volatile uint32_t *)REG_SEC0_SCTL113)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL114                ((volatile uint32_t *)REG_SEC0_SCTL114)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL115                ((volatile uint32_t *)REG_SEC0_SCTL115)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL116                ((volatile uint32_t *)REG_SEC0_SCTL116)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL117                ((volatile uint32_t *)REG_SEC0_SCTL117)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL118                ((volatile uint32_t *)REG_SEC0_SCTL118)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL119                ((volatile uint32_t *)REG_SEC0_SCTL119)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL120                ((volatile uint32_t *)REG_SEC0_SCTL120)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL121                ((volatile uint32_t *)REG_SEC0_SCTL121)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL122                ((volatile uint32_t *)REG_SEC0_SCTL122)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL123                ((volatile uint32_t *)REG_SEC0_SCTL123)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL124                ((volatile uint32_t *)REG_SEC0_SCTL124)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL125                ((volatile uint32_t *)REG_SEC0_SCTL125)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL126                ((volatile uint32_t *)REG_SEC0_SCTL126)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL127                ((volatile uint32_t *)REG_SEC0_SCTL127)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL128                ((volatile uint32_t *)REG_SEC0_SCTL128)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL129                ((volatile uint32_t *)REG_SEC0_SCTL129)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL130                ((volatile uint32_t *)REG_SEC0_SCTL130)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL131                ((volatile uint32_t *)REG_SEC0_SCTL131)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL132                ((volatile uint32_t *)REG_SEC0_SCTL132)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL133                ((volatile uint32_t *)REG_SEC0_SCTL133)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL134                ((volatile uint32_t *)REG_SEC0_SCTL134)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL135                ((volatile uint32_t *)REG_SEC0_SCTL135)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL136                ((volatile uint32_t *)REG_SEC0_SCTL136)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL137                ((volatile uint32_t *)REG_SEC0_SCTL137)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL138                ((volatile uint32_t *)REG_SEC0_SCTL138)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SCTL139                ((volatile uint32_t *)REG_SEC0_SCTL139)                 /* SEC0 Source Control Register n */
-#define pREG_SEC0_SSTAT0                 ((volatile uint32_t *)REG_SEC0_SSTAT0)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT1                 ((volatile uint32_t *)REG_SEC0_SSTAT1)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT2                 ((volatile uint32_t *)REG_SEC0_SSTAT2)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT3                 ((volatile uint32_t *)REG_SEC0_SSTAT3)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT4                 ((volatile uint32_t *)REG_SEC0_SSTAT4)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT5                 ((volatile uint32_t *)REG_SEC0_SSTAT5)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT6                 ((volatile uint32_t *)REG_SEC0_SSTAT6)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT7                 ((volatile uint32_t *)REG_SEC0_SSTAT7)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT8                 ((volatile uint32_t *)REG_SEC0_SSTAT8)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT9                 ((volatile uint32_t *)REG_SEC0_SSTAT9)                  /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT10                ((volatile uint32_t *)REG_SEC0_SSTAT10)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT11                ((volatile uint32_t *)REG_SEC0_SSTAT11)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT12                ((volatile uint32_t *)REG_SEC0_SSTAT12)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT13                ((volatile uint32_t *)REG_SEC0_SSTAT13)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT14                ((volatile uint32_t *)REG_SEC0_SSTAT14)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT15                ((volatile uint32_t *)REG_SEC0_SSTAT15)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT16                ((volatile uint32_t *)REG_SEC0_SSTAT16)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT17                ((volatile uint32_t *)REG_SEC0_SSTAT17)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT18                ((volatile uint32_t *)REG_SEC0_SSTAT18)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT19                ((volatile uint32_t *)REG_SEC0_SSTAT19)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT20                ((volatile uint32_t *)REG_SEC0_SSTAT20)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT21                ((volatile uint32_t *)REG_SEC0_SSTAT21)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT22                ((volatile uint32_t *)REG_SEC0_SSTAT22)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT23                ((volatile uint32_t *)REG_SEC0_SSTAT23)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT24                ((volatile uint32_t *)REG_SEC0_SSTAT24)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT25                ((volatile uint32_t *)REG_SEC0_SSTAT25)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT26                ((volatile uint32_t *)REG_SEC0_SSTAT26)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT27                ((volatile uint32_t *)REG_SEC0_SSTAT27)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT28                ((volatile uint32_t *)REG_SEC0_SSTAT28)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT29                ((volatile uint32_t *)REG_SEC0_SSTAT29)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT30                ((volatile uint32_t *)REG_SEC0_SSTAT30)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT31                ((volatile uint32_t *)REG_SEC0_SSTAT31)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT32                ((volatile uint32_t *)REG_SEC0_SSTAT32)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT33                ((volatile uint32_t *)REG_SEC0_SSTAT33)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT34                ((volatile uint32_t *)REG_SEC0_SSTAT34)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT35                ((volatile uint32_t *)REG_SEC0_SSTAT35)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT36                ((volatile uint32_t *)REG_SEC0_SSTAT36)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT37                ((volatile uint32_t *)REG_SEC0_SSTAT37)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT38                ((volatile uint32_t *)REG_SEC0_SSTAT38)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT39                ((volatile uint32_t *)REG_SEC0_SSTAT39)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT40                ((volatile uint32_t *)REG_SEC0_SSTAT40)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT41                ((volatile uint32_t *)REG_SEC0_SSTAT41)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT42                ((volatile uint32_t *)REG_SEC0_SSTAT42)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT43                ((volatile uint32_t *)REG_SEC0_SSTAT43)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT44                ((volatile uint32_t *)REG_SEC0_SSTAT44)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT45                ((volatile uint32_t *)REG_SEC0_SSTAT45)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT46                ((volatile uint32_t *)REG_SEC0_SSTAT46)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT47                ((volatile uint32_t *)REG_SEC0_SSTAT47)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT48                ((volatile uint32_t *)REG_SEC0_SSTAT48)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT49                ((volatile uint32_t *)REG_SEC0_SSTAT49)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT50                ((volatile uint32_t *)REG_SEC0_SSTAT50)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT51                ((volatile uint32_t *)REG_SEC0_SSTAT51)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT52                ((volatile uint32_t *)REG_SEC0_SSTAT52)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT53                ((volatile uint32_t *)REG_SEC0_SSTAT53)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT54                ((volatile uint32_t *)REG_SEC0_SSTAT54)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT55                ((volatile uint32_t *)REG_SEC0_SSTAT55)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT56                ((volatile uint32_t *)REG_SEC0_SSTAT56)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT57                ((volatile uint32_t *)REG_SEC0_SSTAT57)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT58                ((volatile uint32_t *)REG_SEC0_SSTAT58)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT59                ((volatile uint32_t *)REG_SEC0_SSTAT59)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT60                ((volatile uint32_t *)REG_SEC0_SSTAT60)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT61                ((volatile uint32_t *)REG_SEC0_SSTAT61)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT62                ((volatile uint32_t *)REG_SEC0_SSTAT62)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT63                ((volatile uint32_t *)REG_SEC0_SSTAT63)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT64                ((volatile uint32_t *)REG_SEC0_SSTAT64)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT65                ((volatile uint32_t *)REG_SEC0_SSTAT65)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT66                ((volatile uint32_t *)REG_SEC0_SSTAT66)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT67                ((volatile uint32_t *)REG_SEC0_SSTAT67)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT68                ((volatile uint32_t *)REG_SEC0_SSTAT68)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT69                ((volatile uint32_t *)REG_SEC0_SSTAT69)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT70                ((volatile uint32_t *)REG_SEC0_SSTAT70)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT71                ((volatile uint32_t *)REG_SEC0_SSTAT71)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT72                ((volatile uint32_t *)REG_SEC0_SSTAT72)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT73                ((volatile uint32_t *)REG_SEC0_SSTAT73)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT74                ((volatile uint32_t *)REG_SEC0_SSTAT74)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT75                ((volatile uint32_t *)REG_SEC0_SSTAT75)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT76                ((volatile uint32_t *)REG_SEC0_SSTAT76)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT77                ((volatile uint32_t *)REG_SEC0_SSTAT77)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT78                ((volatile uint32_t *)REG_SEC0_SSTAT78)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT79                ((volatile uint32_t *)REG_SEC0_SSTAT79)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT80                ((volatile uint32_t *)REG_SEC0_SSTAT80)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT81                ((volatile uint32_t *)REG_SEC0_SSTAT81)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT82                ((volatile uint32_t *)REG_SEC0_SSTAT82)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT83                ((volatile uint32_t *)REG_SEC0_SSTAT83)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT84                ((volatile uint32_t *)REG_SEC0_SSTAT84)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT85                ((volatile uint32_t *)REG_SEC0_SSTAT85)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT86                ((volatile uint32_t *)REG_SEC0_SSTAT86)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT87                ((volatile uint32_t *)REG_SEC0_SSTAT87)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT88                ((volatile uint32_t *)REG_SEC0_SSTAT88)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT89                ((volatile uint32_t *)REG_SEC0_SSTAT89)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT90                ((volatile uint32_t *)REG_SEC0_SSTAT90)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT91                ((volatile uint32_t *)REG_SEC0_SSTAT91)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT92                ((volatile uint32_t *)REG_SEC0_SSTAT92)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT93                ((volatile uint32_t *)REG_SEC0_SSTAT93)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT94                ((volatile uint32_t *)REG_SEC0_SSTAT94)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT95                ((volatile uint32_t *)REG_SEC0_SSTAT95)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT96                ((volatile uint32_t *)REG_SEC0_SSTAT96)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT97                ((volatile uint32_t *)REG_SEC0_SSTAT97)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT98                ((volatile uint32_t *)REG_SEC0_SSTAT98)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT99                ((volatile uint32_t *)REG_SEC0_SSTAT99)                 /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT100               ((volatile uint32_t *)REG_SEC0_SSTAT100)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT101               ((volatile uint32_t *)REG_SEC0_SSTAT101)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT102               ((volatile uint32_t *)REG_SEC0_SSTAT102)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT103               ((volatile uint32_t *)REG_SEC0_SSTAT103)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT104               ((volatile uint32_t *)REG_SEC0_SSTAT104)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT105               ((volatile uint32_t *)REG_SEC0_SSTAT105)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT106               ((volatile uint32_t *)REG_SEC0_SSTAT106)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT107               ((volatile uint32_t *)REG_SEC0_SSTAT107)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT108               ((volatile uint32_t *)REG_SEC0_SSTAT108)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT109               ((volatile uint32_t *)REG_SEC0_SSTAT109)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT110               ((volatile uint32_t *)REG_SEC0_SSTAT110)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT111               ((volatile uint32_t *)REG_SEC0_SSTAT111)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT112               ((volatile uint32_t *)REG_SEC0_SSTAT112)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT113               ((volatile uint32_t *)REG_SEC0_SSTAT113)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT114               ((volatile uint32_t *)REG_SEC0_SSTAT114)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT115               ((volatile uint32_t *)REG_SEC0_SSTAT115)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT116               ((volatile uint32_t *)REG_SEC0_SSTAT116)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT117               ((volatile uint32_t *)REG_SEC0_SSTAT117)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT118               ((volatile uint32_t *)REG_SEC0_SSTAT118)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT119               ((volatile uint32_t *)REG_SEC0_SSTAT119)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT120               ((volatile uint32_t *)REG_SEC0_SSTAT120)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT121               ((volatile uint32_t *)REG_SEC0_SSTAT121)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT122               ((volatile uint32_t *)REG_SEC0_SSTAT122)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT123               ((volatile uint32_t *)REG_SEC0_SSTAT123)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT124               ((volatile uint32_t *)REG_SEC0_SSTAT124)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT125               ((volatile uint32_t *)REG_SEC0_SSTAT125)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT126               ((volatile uint32_t *)REG_SEC0_SSTAT126)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT127               ((volatile uint32_t *)REG_SEC0_SSTAT127)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT128               ((volatile uint32_t *)REG_SEC0_SSTAT128)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT129               ((volatile uint32_t *)REG_SEC0_SSTAT129)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT130               ((volatile uint32_t *)REG_SEC0_SSTAT130)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT131               ((volatile uint32_t *)REG_SEC0_SSTAT131)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT132               ((volatile uint32_t *)REG_SEC0_SSTAT132)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT133               ((volatile uint32_t *)REG_SEC0_SSTAT133)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT134               ((volatile uint32_t *)REG_SEC0_SSTAT134)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT135               ((volatile uint32_t *)REG_SEC0_SSTAT135)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT136               ((volatile uint32_t *)REG_SEC0_SSTAT136)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT137               ((volatile uint32_t *)REG_SEC0_SSTAT137)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT138               ((volatile uint32_t *)REG_SEC0_SSTAT138)                /* SEC0 Source Status Register n */
-#define pREG_SEC0_SSTAT139               ((volatile uint32_t *)REG_SEC0_SSTAT139)                /* SEC0 Source Status Register n */
-
-
-/* =========================================================================
-       TRU0
-   ========================================================================= */
-#define pREG_TRU0_SSR0                   ((volatile uint32_t *)REG_TRU0_SSR0)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR1                   ((volatile uint32_t *)REG_TRU0_SSR1)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR2                   ((volatile uint32_t *)REG_TRU0_SSR2)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR3                   ((volatile uint32_t *)REG_TRU0_SSR3)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR4                   ((volatile uint32_t *)REG_TRU0_SSR4)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR5                   ((volatile uint32_t *)REG_TRU0_SSR5)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR6                   ((volatile uint32_t *)REG_TRU0_SSR6)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR7                   ((volatile uint32_t *)REG_TRU0_SSR7)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR8                   ((volatile uint32_t *)REG_TRU0_SSR8)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR9                   ((volatile uint32_t *)REG_TRU0_SSR9)                    /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR10                  ((volatile uint32_t *)REG_TRU0_SSR10)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR11                  ((volatile uint32_t *)REG_TRU0_SSR11)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR12                  ((volatile uint32_t *)REG_TRU0_SSR12)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR13                  ((volatile uint32_t *)REG_TRU0_SSR13)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR14                  ((volatile uint32_t *)REG_TRU0_SSR14)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR15                  ((volatile uint32_t *)REG_TRU0_SSR15)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR16                  ((volatile uint32_t *)REG_TRU0_SSR16)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR17                  ((volatile uint32_t *)REG_TRU0_SSR17)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR18                  ((volatile uint32_t *)REG_TRU0_SSR18)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR19                  ((volatile uint32_t *)REG_TRU0_SSR19)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR20                  ((volatile uint32_t *)REG_TRU0_SSR20)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR21                  ((volatile uint32_t *)REG_TRU0_SSR21)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR22                  ((volatile uint32_t *)REG_TRU0_SSR22)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR23                  ((volatile uint32_t *)REG_TRU0_SSR23)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR24                  ((volatile uint32_t *)REG_TRU0_SSR24)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR25                  ((volatile uint32_t *)REG_TRU0_SSR25)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR26                  ((volatile uint32_t *)REG_TRU0_SSR26)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR27                  ((volatile uint32_t *)REG_TRU0_SSR27)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR28                  ((volatile uint32_t *)REG_TRU0_SSR28)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR29                  ((volatile uint32_t *)REG_TRU0_SSR29)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR30                  ((volatile uint32_t *)REG_TRU0_SSR30)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR31                  ((volatile uint32_t *)REG_TRU0_SSR31)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR32                  ((volatile uint32_t *)REG_TRU0_SSR32)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR33                  ((volatile uint32_t *)REG_TRU0_SSR33)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR34                  ((volatile uint32_t *)REG_TRU0_SSR34)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR35                  ((volatile uint32_t *)REG_TRU0_SSR35)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR36                  ((volatile uint32_t *)REG_TRU0_SSR36)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR37                  ((volatile uint32_t *)REG_TRU0_SSR37)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR38                  ((volatile uint32_t *)REG_TRU0_SSR38)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR39                  ((volatile uint32_t *)REG_TRU0_SSR39)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR40                  ((volatile uint32_t *)REG_TRU0_SSR40)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR41                  ((volatile uint32_t *)REG_TRU0_SSR41)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR42                  ((volatile uint32_t *)REG_TRU0_SSR42)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR43                  ((volatile uint32_t *)REG_TRU0_SSR43)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR44                  ((volatile uint32_t *)REG_TRU0_SSR44)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR45                  ((volatile uint32_t *)REG_TRU0_SSR45)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR46                  ((volatile uint32_t *)REG_TRU0_SSR46)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR47                  ((volatile uint32_t *)REG_TRU0_SSR47)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR48                  ((volatile uint32_t *)REG_TRU0_SSR48)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR49                  ((volatile uint32_t *)REG_TRU0_SSR49)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR50                  ((volatile uint32_t *)REG_TRU0_SSR50)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR51                  ((volatile uint32_t *)REG_TRU0_SSR51)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR52                  ((volatile uint32_t *)REG_TRU0_SSR52)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR53                  ((volatile uint32_t *)REG_TRU0_SSR53)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR54                  ((volatile uint32_t *)REG_TRU0_SSR54)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR55                  ((volatile uint32_t *)REG_TRU0_SSR55)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR56                  ((volatile uint32_t *)REG_TRU0_SSR56)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR57                  ((volatile uint32_t *)REG_TRU0_SSR57)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR58                  ((volatile uint32_t *)REG_TRU0_SSR58)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR59                  ((volatile uint32_t *)REG_TRU0_SSR59)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR60                  ((volatile uint32_t *)REG_TRU0_SSR60)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR61                  ((volatile uint32_t *)REG_TRU0_SSR61)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR62                  ((volatile uint32_t *)REG_TRU0_SSR62)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR63                  ((volatile uint32_t *)REG_TRU0_SSR63)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR64                  ((volatile uint32_t *)REG_TRU0_SSR64)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR65                  ((volatile uint32_t *)REG_TRU0_SSR65)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR66                  ((volatile uint32_t *)REG_TRU0_SSR66)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR67                  ((volatile uint32_t *)REG_TRU0_SSR67)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR68                  ((volatile uint32_t *)REG_TRU0_SSR68)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR69                  ((volatile uint32_t *)REG_TRU0_SSR69)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR70                  ((volatile uint32_t *)REG_TRU0_SSR70)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR71                  ((volatile uint32_t *)REG_TRU0_SSR71)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR72                  ((volatile uint32_t *)REG_TRU0_SSR72)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR73                  ((volatile uint32_t *)REG_TRU0_SSR73)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR74                  ((volatile uint32_t *)REG_TRU0_SSR74)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR75                  ((volatile uint32_t *)REG_TRU0_SSR75)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR76                  ((volatile uint32_t *)REG_TRU0_SSR76)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR77                  ((volatile uint32_t *)REG_TRU0_SSR77)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR78                  ((volatile uint32_t *)REG_TRU0_SSR78)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR79                  ((volatile uint32_t *)REG_TRU0_SSR79)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR80                  ((volatile uint32_t *)REG_TRU0_SSR80)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR81                  ((volatile uint32_t *)REG_TRU0_SSR81)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR82                  ((volatile uint32_t *)REG_TRU0_SSR82)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR83                  ((volatile uint32_t *)REG_TRU0_SSR83)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR84                  ((volatile uint32_t *)REG_TRU0_SSR84)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR85                  ((volatile uint32_t *)REG_TRU0_SSR85)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_SSR86                  ((volatile uint32_t *)REG_TRU0_SSR86)                   /* TRU0 Slave Select Register */
-#define pREG_TRU0_MTR                    ((volatile uint32_t *)REG_TRU0_MTR)                     /* TRU0 Master Trigger Register */
-#define pREG_TRU0_ERRADDR                ((volatile uint32_t *)REG_TRU0_ERRADDR)                 /* TRU0 Error Address Register */
-#define pREG_TRU0_STAT                   ((volatile uint32_t *)REG_TRU0_STAT)                    /* TRU0 Status Information Register */
-#define pREG_TRU0_REVID                  ((volatile uint32_t *)REG_TRU0_REVID)                   /* TRU0 Revision ID Register */
-#define pREG_TRU0_GCTL                   ((volatile uint32_t *)REG_TRU0_GCTL)                    /* TRU0 Global Control Register */
-
-
-/* =========================================================================
-       RCU0
-   ========================================================================= */
-#define pREG_RCU0_CTL                    ((volatile uint32_t *)REG_RCU0_CTL)                     /* RCU0 Control Register */
-#define pREG_RCU0_STAT                   ((volatile uint32_t *)REG_RCU0_STAT)                    /* RCU0 Status Register */
-#define pREG_RCU0_CRCTL                  ((volatile uint32_t *)REG_RCU0_CRCTL)                   /* RCU0 Core Reset Control Register */
-#define pREG_RCU0_CRSTAT                 ((volatile uint32_t *)REG_RCU0_CRSTAT)                  /* RCU0 Core Reset Status Register */
-#define pREG_RCU0_SIDIS                  ((volatile uint32_t *)REG_RCU0_SIDIS)                   /* RCU0 System Interface Disable Register */
-#define pREG_RCU0_SISTAT                 ((volatile uint32_t *)REG_RCU0_SISTAT)                  /* RCU0 System Interface Status Register */
-#define pREG_RCU0_SVECT_LCK              ((volatile uint32_t *)REG_RCU0_SVECT_LCK)               /* RCU0 SVECT Lock Register */
-#define pREG_RCU0_BCODE                  ((volatile uint32_t *)REG_RCU0_BCODE)                   /* RCU0 Boot Code Register */
-#define pREG_RCU0_SVECT0                 ((void * volatile *)REG_RCU0_SVECT0)                    /* RCU0 Software Vector Register n */
-#define pREG_RCU0_SVECT1                 ((void * volatile *)REG_RCU0_SVECT1)                    /* RCU0 Software Vector Register n */
-
-
-/* =========================================================================
-       SPU0
-   ========================================================================= */
-#define pREG_SPU0_CTL                    ((volatile uint32_t *)REG_SPU0_CTL)                     /* SPU0 Control Register */
-#define pREG_SPU0_STAT                   ((volatile uint32_t *)REG_SPU0_STAT)                    /* SPU0 Status Register */
-#define pREG_SPU0_WP0                    ((volatile uint32_t *)REG_SPU0_WP0)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP1                    ((volatile uint32_t *)REG_SPU0_WP1)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP2                    ((volatile uint32_t *)REG_SPU0_WP2)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP3                    ((volatile uint32_t *)REG_SPU0_WP3)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP4                    ((volatile uint32_t *)REG_SPU0_WP4)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP5                    ((volatile uint32_t *)REG_SPU0_WP5)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP6                    ((volatile uint32_t *)REG_SPU0_WP6)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP7                    ((volatile uint32_t *)REG_SPU0_WP7)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP8                    ((volatile uint32_t *)REG_SPU0_WP8)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP9                    ((volatile uint32_t *)REG_SPU0_WP9)                     /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP10                   ((volatile uint32_t *)REG_SPU0_WP10)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP11                   ((volatile uint32_t *)REG_SPU0_WP11)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP12                   ((volatile uint32_t *)REG_SPU0_WP12)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP13                   ((volatile uint32_t *)REG_SPU0_WP13)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP14                   ((volatile uint32_t *)REG_SPU0_WP14)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP15                   ((volatile uint32_t *)REG_SPU0_WP15)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP16                   ((volatile uint32_t *)REG_SPU0_WP16)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP17                   ((volatile uint32_t *)REG_SPU0_WP17)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP18                   ((volatile uint32_t *)REG_SPU0_WP18)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP19                   ((volatile uint32_t *)REG_SPU0_WP19)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP20                   ((volatile uint32_t *)REG_SPU0_WP20)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP21                   ((volatile uint32_t *)REG_SPU0_WP21)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP22                   ((volatile uint32_t *)REG_SPU0_WP22)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP23                   ((volatile uint32_t *)REG_SPU0_WP23)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP24                   ((volatile uint32_t *)REG_SPU0_WP24)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP25                   ((volatile uint32_t *)REG_SPU0_WP25)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP26                   ((volatile uint32_t *)REG_SPU0_WP26)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP27                   ((volatile uint32_t *)REG_SPU0_WP27)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP28                   ((volatile uint32_t *)REG_SPU0_WP28)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP29                   ((volatile uint32_t *)REG_SPU0_WP29)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP30                   ((volatile uint32_t *)REG_SPU0_WP30)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP31                   ((volatile uint32_t *)REG_SPU0_WP31)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP32                   ((volatile uint32_t *)REG_SPU0_WP32)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP33                   ((volatile uint32_t *)REG_SPU0_WP33)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP34                   ((volatile uint32_t *)REG_SPU0_WP34)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP35                   ((volatile uint32_t *)REG_SPU0_WP35)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP36                   ((volatile uint32_t *)REG_SPU0_WP36)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP37                   ((volatile uint32_t *)REG_SPU0_WP37)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP38                   ((volatile uint32_t *)REG_SPU0_WP38)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP39                   ((volatile uint32_t *)REG_SPU0_WP39)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP40                   ((volatile uint32_t *)REG_SPU0_WP40)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP41                   ((volatile uint32_t *)REG_SPU0_WP41)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP42                   ((volatile uint32_t *)REG_SPU0_WP42)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP43                   ((volatile uint32_t *)REG_SPU0_WP43)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP44                   ((volatile uint32_t *)REG_SPU0_WP44)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP45                   ((volatile uint32_t *)REG_SPU0_WP45)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP46                   ((volatile uint32_t *)REG_SPU0_WP46)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP47                   ((volatile uint32_t *)REG_SPU0_WP47)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP48                   ((volatile uint32_t *)REG_SPU0_WP48)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP49                   ((volatile uint32_t *)REG_SPU0_WP49)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP50                   ((volatile uint32_t *)REG_SPU0_WP50)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP51                   ((volatile uint32_t *)REG_SPU0_WP51)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP52                   ((volatile uint32_t *)REG_SPU0_WP52)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP53                   ((volatile uint32_t *)REG_SPU0_WP53)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP54                   ((volatile uint32_t *)REG_SPU0_WP54)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP55                   ((volatile uint32_t *)REG_SPU0_WP55)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP56                   ((volatile uint32_t *)REG_SPU0_WP56)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP57                   ((volatile uint32_t *)REG_SPU0_WP57)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP58                   ((volatile uint32_t *)REG_SPU0_WP58)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP59                   ((volatile uint32_t *)REG_SPU0_WP59)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP60                   ((volatile uint32_t *)REG_SPU0_WP60)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP61                   ((volatile uint32_t *)REG_SPU0_WP61)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP62                   ((volatile uint32_t *)REG_SPU0_WP62)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP63                   ((volatile uint32_t *)REG_SPU0_WP63)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP64                   ((volatile uint32_t *)REG_SPU0_WP64)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP65                   ((volatile uint32_t *)REG_SPU0_WP65)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP66                   ((volatile uint32_t *)REG_SPU0_WP66)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP67                   ((volatile uint32_t *)REG_SPU0_WP67)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP68                   ((volatile uint32_t *)REG_SPU0_WP68)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP69                   ((volatile uint32_t *)REG_SPU0_WP69)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP70                   ((volatile uint32_t *)REG_SPU0_WP70)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP71                   ((volatile uint32_t *)REG_SPU0_WP71)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP72                   ((volatile uint32_t *)REG_SPU0_WP72)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP73                   ((volatile uint32_t *)REG_SPU0_WP73)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP74                   ((volatile uint32_t *)REG_SPU0_WP74)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP75                   ((volatile uint32_t *)REG_SPU0_WP75)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP76                   ((volatile uint32_t *)REG_SPU0_WP76)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP77                   ((volatile uint32_t *)REG_SPU0_WP77)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP78                   ((volatile uint32_t *)REG_SPU0_WP78)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP79                   ((volatile uint32_t *)REG_SPU0_WP79)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP80                   ((volatile uint32_t *)REG_SPU0_WP80)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP81                   ((volatile uint32_t *)REG_SPU0_WP81)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP82                   ((volatile uint32_t *)REG_SPU0_WP82)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP83                   ((volatile uint32_t *)REG_SPU0_WP83)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP84                   ((volatile uint32_t *)REG_SPU0_WP84)                    /* SPU0 Write Protect Register n */
-#define pREG_SPU0_WP85                   ((volatile uint32_t *)REG_SPU0_WP85)                    /* SPU0 Write Protect Register n */
-
-
-/* =========================================================================
-       CGU0
-   ========================================================================= */
-#define pREG_CGU0_CTL                    ((volatile uint32_t *)REG_CGU0_CTL)                     /* CGU0 Control Register */
-#define pREG_CGU0_STAT                   ((volatile uint32_t *)REG_CGU0_STAT)                    /* CGU0 Status Register */
-#define pREG_CGU0_DIV                    ((volatile uint32_t *)REG_CGU0_DIV)                     /* CGU0 Divisor Register */
-#define pREG_CGU0_CLKOUTSEL              ((volatile uint32_t *)REG_CGU0_CLKOUTSEL)               /* CGU0 CLKOUT Select Register */
-
-
-/* =========================================================================
-       DPM0
-   ========================================================================= */
-#define pREG_DPM0_CTL                    ((volatile uint32_t *)REG_DPM0_CTL)                     /* DPM0 Control Register */
-#define pREG_DPM0_STAT                   ((volatile uint32_t *)REG_DPM0_STAT)                    /* DPM0 Status Register */
-#define pREG_DPM0_CCBF_DIS               ((volatile uint32_t *)REG_DPM0_CCBF_DIS)                /* DPM0 Core Clock Buffer Disable Register */
-#define pREG_DPM0_CCBF_EN                ((volatile uint32_t *)REG_DPM0_CCBF_EN)                 /* DPM0 Core Clock Buffer Enable Register */
-#define pREG_DPM0_CCBF_STAT              ((volatile uint32_t *)REG_DPM0_CCBF_STAT)               /* DPM0 Core Clock Buffer Status Register */
-#define pREG_DPM0_CCBF_STAT_STKY         ((volatile uint32_t *)REG_DPM0_CCBF_STAT_STKY)          /* DPM0 Core Clock Buffer Status Sticky Register */
-#define pREG_DPM0_SCBF_DIS               ((volatile uint32_t *)REG_DPM0_SCBF_DIS)                /* DPM0 System Clock Buffer Disable Register */
-#define pREG_DPM0_WAKE_EN                ((volatile uint32_t *)REG_DPM0_WAKE_EN)                 /* DPM0 Wakeup Enable Register */
-#define pREG_DPM0_WAKE_POL               ((volatile uint32_t *)REG_DPM0_WAKE_POL)                /* DPM0 Wakeup Polarity Register */
-#define pREG_DPM0_WAKE_STAT              ((volatile uint32_t *)REG_DPM0_WAKE_STAT)               /* DPM0 Wakeup Status Register */
-#define pREG_DPM0_HIB_DIS                ((volatile uint32_t *)REG_DPM0_HIB_DIS)                 /* DPM0 Hibernate Disable Register */
-#define pREG_DPM0_PGCNTR                 ((volatile uint32_t *)REG_DPM0_PGCNTR)                  /* DPM0 Power Good Counter Register */
-#define pREG_DPM0_RESTORE0               ((volatile uint32_t *)REG_DPM0_RESTORE0)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE1               ((volatile uint32_t *)REG_DPM0_RESTORE1)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE2               ((volatile uint32_t *)REG_DPM0_RESTORE2)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE3               ((volatile uint32_t *)REG_DPM0_RESTORE3)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE4               ((volatile uint32_t *)REG_DPM0_RESTORE4)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE5               ((volatile uint32_t *)REG_DPM0_RESTORE5)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE6               ((volatile uint32_t *)REG_DPM0_RESTORE6)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE7               ((volatile uint32_t *)REG_DPM0_RESTORE7)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE8               ((volatile uint32_t *)REG_DPM0_RESTORE8)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE9               ((volatile uint32_t *)REG_DPM0_RESTORE9)                /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE10              ((volatile uint32_t *)REG_DPM0_RESTORE10)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE11              ((volatile uint32_t *)REG_DPM0_RESTORE11)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE12              ((volatile uint32_t *)REG_DPM0_RESTORE12)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE13              ((volatile uint32_t *)REG_DPM0_RESTORE13)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE14              ((volatile uint32_t *)REG_DPM0_RESTORE14)               /* DPM0 Restore n Register */
-#define pREG_DPM0_RESTORE15              ((volatile uint32_t *)REG_DPM0_RESTORE15)               /* DPM0 Restore n Register */
-
-
-/* =========================================================================
-       EFS0
-   ========================================================================= */
-#define pREG_EFS0_CTL                    ((volatile uint32_t *)REG_EFS0_CTL)                     /* EFS0 Control Register */
-#define pREG_EFS0_DAT0                   ((volatile uint32_t *)REG_EFS0_DAT0)                    /* EFS0 Data Register 0 */
-#define pREG_EFS0_DAT1                   ((volatile uint32_t *)REG_EFS0_DAT1)                    /* EFS0 Data Register 1 */
-#define pREG_EFS0_DAT2                   ((volatile uint32_t *)REG_EFS0_DAT2)                    /* EFS0 Data Register 2 */
-#define pREG_EFS0_DAT3                   ((volatile uint32_t *)REG_EFS0_DAT3)                    /* EFS0 Data Register 3 */
-#define pREG_EFS0_DAT4                   ((volatile uint32_t *)REG_EFS0_DAT4)                    /* EFS0 Data Register 4 */
-#define pREG_EFS0_DAT5                   ((volatile uint32_t *)REG_EFS0_DAT5)                    /* EFS0 Data Register 5 */
-#define pREG_EFS0_DAT6                   ((volatile uint32_t *)REG_EFS0_DAT6)                    /* EFS0 Data Register 6 */
-#define pREG_EFS0_DAT7                   ((volatile uint32_t *)REG_EFS0_DAT7)                    /* EFS0 Data Register 7 */
-
-
-/* =========================================================================
-       USB0
-   ========================================================================= */
-#define pREG_USB0_FADDR                  ((volatile  uint8_t *)REG_USB0_FADDR)                   /* USB0 Function Address Register */
-#define pREG_USB0_POWER                  ((volatile  uint8_t *)REG_USB0_POWER)                   /* USB0 Power and Device Control Register */
-#define pREG_USB0_INTRTX                 ((volatile uint16_t *)REG_USB0_INTRTX)                  /* USB0 Transmit Interrupt Register */
-#define pREG_USB0_INTRRX                 ((volatile uint16_t *)REG_USB0_INTRRX)                  /* USB0 Receive Interrupt Register */
-#define pREG_USB0_INTRTXE                ((volatile uint16_t *)REG_USB0_INTRTXE)                 /* USB0 Transmit Interrupt Enable Register */
-#define pREG_USB0_INTRRXE                ((volatile uint16_t *)REG_USB0_INTRRXE)                 /* USB0 Receive Interrupt Enable Register */
-#define pREG_USB0_IRQ                    ((volatile  uint8_t *)REG_USB0_IRQ)                     /* USB0 Common Interrupts Register */
-#define pREG_USB0_IEN                    ((volatile  uint8_t *)REG_USB0_IEN)                     /* USB0 Common Interrupts Enable Register */
-#define pREG_USB0_FRAME                  ((volatile uint16_t *)REG_USB0_FRAME)                   /* USB0 Frame Number Register */
-#define pREG_USB0_INDEX                  ((volatile  uint8_t *)REG_USB0_INDEX)                   /* USB0 Index Register */
-#define pREG_USB0_TESTMODE               ((volatile  uint8_t *)REG_USB0_TESTMODE)                /* USB0 Testmode Register */
-#define pREG_USB0_EPI_TXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_TXMAXP0)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EPI_TXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_P0)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EPI_TXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_TXCSR_H0)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0I_CSR0_P            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_P)             /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CSR0_H            ((volatile uint16_t *)REG_USB0_EP0I_CSR0_H)             /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXMAXP0            ((volatile uint16_t *)REG_USB0_EPI_RXMAXP0)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EPI_RXCSR_H0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_H0)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EPI_RXCSR_P0           ((volatile uint16_t *)REG_USB0_EPI_RXCSR_P0)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0I_CNT0              ((volatile uint16_t *)REG_USB0_EP0I_CNT0)               /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EPI_RXCNT0             ((volatile uint16_t *)REG_USB0_EPI_RXCNT0)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EPI_TXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_TXTYPE0)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0I_TYPE0             ((volatile  uint8_t *)REG_USB0_EP0I_TYPE0)              /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EPI_TXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_TXINTERVAL0)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0I_NAKLIMIT0         ((volatile  uint8_t *)REG_USB0_EP0I_NAKLIMIT0)          /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EPI_RXTYPE0            ((volatile  uint8_t *)REG_USB0_EPI_RXTYPE0)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EPI_RXINTERVAL0        ((volatile  uint8_t *)REG_USB0_EPI_RXINTERVAL0)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0I_CFGDATA0          ((volatile  uint8_t *)REG_USB0_EP0I_CFGDATA0)           /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_FIFOB0                 ((volatile  uint8_t *)REG_USB0_FIFOB0)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB1                 ((volatile  uint8_t *)REG_USB0_FIFOB1)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB2                 ((volatile  uint8_t *)REG_USB0_FIFOB2)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB3                 ((volatile  uint8_t *)REG_USB0_FIFOB3)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB4                 ((volatile  uint8_t *)REG_USB0_FIFOB4)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB5                 ((volatile  uint8_t *)REG_USB0_FIFOB5)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB6                 ((volatile  uint8_t *)REG_USB0_FIFOB6)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB7                 ((volatile  uint8_t *)REG_USB0_FIFOB7)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB8                 ((volatile  uint8_t *)REG_USB0_FIFOB8)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB9                 ((volatile  uint8_t *)REG_USB0_FIFOB9)                  /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB10                ((volatile  uint8_t *)REG_USB0_FIFOB10)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOB11                ((volatile  uint8_t *)REG_USB0_FIFOB11)                 /* USB0 FIFO Byte (8-Bit) Register */
-#define pREG_USB0_FIFOH0                 ((volatile uint16_t *)REG_USB0_FIFOH0)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH1                 ((volatile uint16_t *)REG_USB0_FIFOH1)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH2                 ((volatile uint16_t *)REG_USB0_FIFOH2)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH3                 ((volatile uint16_t *)REG_USB0_FIFOH3)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH4                 ((volatile uint16_t *)REG_USB0_FIFOH4)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH5                 ((volatile uint16_t *)REG_USB0_FIFOH5)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH6                 ((volatile uint16_t *)REG_USB0_FIFOH6)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH7                 ((volatile uint16_t *)REG_USB0_FIFOH7)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH8                 ((volatile uint16_t *)REG_USB0_FIFOH8)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH9                 ((volatile uint16_t *)REG_USB0_FIFOH9)                  /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH10                ((volatile uint16_t *)REG_USB0_FIFOH10)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFOH11                ((volatile uint16_t *)REG_USB0_FIFOH11)                 /* USB0 FIFO Half-Word (16-Bit) Register */
-#define pREG_USB0_FIFO0                  ((volatile uint32_t *)REG_USB0_FIFO0)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO1                  ((volatile uint32_t *)REG_USB0_FIFO1)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO2                  ((volatile uint32_t *)REG_USB0_FIFO2)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO3                  ((volatile uint32_t *)REG_USB0_FIFO3)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO4                  ((volatile uint32_t *)REG_USB0_FIFO4)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO5                  ((volatile uint32_t *)REG_USB0_FIFO5)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO6                  ((volatile uint32_t *)REG_USB0_FIFO6)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO7                  ((volatile uint32_t *)REG_USB0_FIFO7)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO8                  ((volatile uint32_t *)REG_USB0_FIFO8)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO9                  ((volatile uint32_t *)REG_USB0_FIFO9)                   /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO10                 ((volatile uint32_t *)REG_USB0_FIFO10)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_FIFO11                 ((volatile uint32_t *)REG_USB0_FIFO11)                  /* USB0 FIFO Word (32-Bit) Register */
-#define pREG_USB0_DEV_CTL                ((volatile  uint8_t *)REG_USB0_DEV_CTL)                 /* USB0 Device Control Register */
-#define pREG_USB0_TXFIFOSZ               ((volatile  uint8_t *)REG_USB0_TXFIFOSZ)                /* USB0 Transmit FIFO Size Register */
-#define pREG_USB0_RXFIFOSZ               ((volatile  uint8_t *)REG_USB0_RXFIFOSZ)                /* USB0 Receive FIFO Size Register */
-#define pREG_USB0_TXFIFOADDR             ((volatile uint16_t *)REG_USB0_TXFIFOADDR)              /* USB0 Transmit FIFO Address Register */
-#define pREG_USB0_RXFIFOADDR             ((volatile uint16_t *)REG_USB0_RXFIFOADDR)              /* USB0 Receive FIFO Address Register */
-#define pREG_USB0_EPINFO                 ((volatile  uint8_t *)REG_USB0_EPINFO)                  /* USB0 Endpoint Information Register */
-#define pREG_USB0_RAMINFO                ((volatile  uint8_t *)REG_USB0_RAMINFO)                 /* USB0 RAM Information Register */
-#define pREG_USB0_LINKINFO               ((volatile  uint8_t *)REG_USB0_LINKINFO)                /* USB0 Link Information Register */
-#define pREG_USB0_VPLEN                  ((volatile  uint8_t *)REG_USB0_VPLEN)                   /* USB0 VBUS Pulse Length Register */
-#define pREG_USB0_HS_EOF1                ((volatile  uint8_t *)REG_USB0_HS_EOF1)                 /* USB0 High-Speed EOF 1 Register */
-#define pREG_USB0_FS_EOF1                ((volatile  uint8_t *)REG_USB0_FS_EOF1)                 /* USB0 Full-Speed EOF 1 Register */
-#define pREG_USB0_LS_EOF1                ((volatile  uint8_t *)REG_USB0_LS_EOF1)                 /* USB0 Low-Speed EOF 1 Register */
-#define pREG_USB0_SOFT_RST               ((volatile  uint8_t *)REG_USB0_SOFT_RST)                /* USB0 Software Reset Register */
-#define pREG_USB0_MP0_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP1_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP2_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP3_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP4_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP5_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP6_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP7_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP8_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP9_TXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_TXFUNCADDR)          /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP10_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP11_TXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_TXFUNCADDR)         /* USB0 MPn Transmit Function Address Register */
-#define pREG_USB0_MP0_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP1_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP2_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP3_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP4_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP5_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP6_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP7_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP8_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP9_TXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBADDR)           /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP10_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP11_TXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBADDR)          /* USB0 MPn Transmit Hub Address Register */
-#define pREG_USB0_MP0_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP1_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP2_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP3_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP4_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP5_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP6_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP7_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP8_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP9_TXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_TXHUBPORT)           /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP10_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP11_TXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_TXHUBPORT)          /* USB0 MPn Transmit Hub Port Register */
-#define pREG_USB0_MP0_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP0_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP1_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP1_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP2_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP2_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP3_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP3_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP4_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP4_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP5_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP5_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP6_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP6_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP7_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP7_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP8_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP8_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP9_RXFUNCADDR         ((volatile  uint8_t *)REG_USB0_MP9_RXFUNCADDR)          /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP10_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP10_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP11_RXFUNCADDR        ((volatile  uint8_t *)REG_USB0_MP11_RXFUNCADDR)         /* USB0 MPn Receive Function Address Register */
-#define pREG_USB0_MP0_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP1_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP2_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP3_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP4_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP5_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP6_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP7_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP8_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP9_RXHUBADDR          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBADDR)           /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP10_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP11_RXHUBADDR         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBADDR)          /* USB0 MPn Receive Hub Address Register */
-#define pREG_USB0_MP0_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP0_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP1_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP1_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP2_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP2_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP3_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP3_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP4_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP4_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP5_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP5_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP6_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP6_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP7_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP7_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP8_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP8_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP9_RXHUBPORT          ((volatile  uint8_t *)REG_USB0_MP9_RXHUBPORT)           /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP10_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP10_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_MP11_RXHUBPORT         ((volatile  uint8_t *)REG_USB0_MP11_RXHUBPORT)          /* USB0 MPn Receive Hub Port Register */
-#define pREG_USB0_EP0_TXMAXP             ((volatile uint16_t *)REG_USB0_EP0_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP1_TXMAXP             ((volatile uint16_t *)REG_USB0_EP1_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP2_TXMAXP             ((volatile uint16_t *)REG_USB0_EP2_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP3_TXMAXP             ((volatile uint16_t *)REG_USB0_EP3_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP4_TXMAXP             ((volatile uint16_t *)REG_USB0_EP4_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP5_TXMAXP             ((volatile uint16_t *)REG_USB0_EP5_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP6_TXMAXP             ((volatile uint16_t *)REG_USB0_EP6_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP7_TXMAXP             ((volatile uint16_t *)REG_USB0_EP7_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP8_TXMAXP             ((volatile uint16_t *)REG_USB0_EP8_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP9_TXMAXP             ((volatile uint16_t *)REG_USB0_EP9_TXMAXP)              /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP10_TXMAXP            ((volatile uint16_t *)REG_USB0_EP10_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP11_TXMAXP            ((volatile uint16_t *)REG_USB0_EP11_TXMAXP)             /* USB0 EPn Transmit Maximum Packet Length Register */
-#define pREG_USB0_EP0_CSR0_H             ((volatile uint16_t *)REG_USB0_EP0_CSR0_H)              /* USB0 EP0 Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_TXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_H)             /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_TXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_H)            /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_CSR0_P             ((volatile uint16_t *)REG_USB0_EP0_CSR0_P)              /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_TXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_TXCSR_P)             /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_TXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_TXCSR_P)            /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_RXMAXP             ((volatile uint16_t *)REG_USB0_EP0_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP1_RXMAXP             ((volatile uint16_t *)REG_USB0_EP1_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP2_RXMAXP             ((volatile uint16_t *)REG_USB0_EP2_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP3_RXMAXP             ((volatile uint16_t *)REG_USB0_EP3_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP4_RXMAXP             ((volatile uint16_t *)REG_USB0_EP4_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP5_RXMAXP             ((volatile uint16_t *)REG_USB0_EP5_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP6_RXMAXP             ((volatile uint16_t *)REG_USB0_EP6_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP7_RXMAXP             ((volatile uint16_t *)REG_USB0_EP7_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP8_RXMAXP             ((volatile uint16_t *)REG_USB0_EP8_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP9_RXMAXP             ((volatile uint16_t *)REG_USB0_EP9_RXMAXP)              /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP10_RXMAXP            ((volatile uint16_t *)REG_USB0_EP10_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP11_RXMAXP            ((volatile uint16_t *)REG_USB0_EP11_RXMAXP)             /* USB0 EPn Receive Maximum Packet Length Register */
-#define pREG_USB0_EP0_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP1_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP2_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP3_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP4_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP5_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP6_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP7_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP8_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP9_RXCSR_H            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_H)             /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP10_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP11_RXCSR_H           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_H)            /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define pREG_USB0_EP0_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP0_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP1_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP1_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP2_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP2_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP3_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP3_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP4_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP4_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP5_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP5_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP6_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP6_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP7_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP7_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP8_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP8_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP9_RXCSR_P            ((volatile uint16_t *)REG_USB0_EP9_RXCSR_P)             /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP10_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP10_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP11_RXCSR_P           ((volatile uint16_t *)REG_USB0_EP11_RXCSR_P)            /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define pREG_USB0_EP0_CNT0               ((volatile uint16_t *)REG_USB0_EP0_CNT0)                /* USB0 EP0 Number of Received Bytes Register */
-#define pREG_USB0_EP0_RXCNT              ((volatile uint16_t *)REG_USB0_EP0_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP1_RXCNT              ((volatile uint16_t *)REG_USB0_EP1_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP2_RXCNT              ((volatile uint16_t *)REG_USB0_EP2_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP3_RXCNT              ((volatile uint16_t *)REG_USB0_EP3_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP4_RXCNT              ((volatile uint16_t *)REG_USB0_EP4_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP5_RXCNT              ((volatile uint16_t *)REG_USB0_EP5_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP6_RXCNT              ((volatile uint16_t *)REG_USB0_EP6_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP7_RXCNT              ((volatile uint16_t *)REG_USB0_EP7_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP8_RXCNT              ((volatile uint16_t *)REG_USB0_EP8_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP9_RXCNT              ((volatile uint16_t *)REG_USB0_EP9_RXCNT)               /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP10_RXCNT             ((volatile uint16_t *)REG_USB0_EP10_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP11_RXCNT             ((volatile uint16_t *)REG_USB0_EP11_RXCNT)              /* USB0 EPn Number of Bytes Received Register */
-#define pREG_USB0_EP0_TYPE0              ((volatile  uint8_t *)REG_USB0_EP0_TYPE0)               /* USB0 EP0 Connection Type Register */
-#define pREG_USB0_EP0_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP1_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP2_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP3_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP4_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP5_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP6_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP7_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP8_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP9_TXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_TXTYPE)              /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP10_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP11_TXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_TXTYPE)             /* USB0 EPn Transmit Type Register */
-#define pREG_USB0_EP0_NAKLIMIT0          ((volatile  uint8_t *)REG_USB0_EP0_NAKLIMIT0)           /* USB0 EP0 NAK Limit Register */
-#define pREG_USB0_EP0_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP1_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP2_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP3_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP4_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP5_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP6_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP7_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP8_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP9_TXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_TXINTERVAL)          /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP10_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP11_TXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_TXINTERVAL)         /* USB0 EPn Transmit Polling Interval Register */
-#define pREG_USB0_EP0_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP0_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP1_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP1_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP2_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP2_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP3_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP3_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP4_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP4_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP5_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP5_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP6_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP6_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP7_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP7_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP8_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP8_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP9_RXTYPE             ((volatile  uint8_t *)REG_USB0_EP9_RXTYPE)              /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP10_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP10_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP11_RXTYPE            ((volatile  uint8_t *)REG_USB0_EP11_RXTYPE)             /* USB0 EPn Receive Type Register */
-#define pREG_USB0_EP0_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP0_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP1_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP1_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP2_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP2_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP3_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP3_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP4_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP4_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP5_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP5_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP6_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP6_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP7_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP7_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP8_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP8_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP9_RXINTERVAL         ((volatile  uint8_t *)REG_USB0_EP9_RXINTERVAL)          /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP10_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP10_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP11_RXINTERVAL        ((volatile  uint8_t *)REG_USB0_EP11_RXINTERVAL)         /* USB0 EPn Receive Polling Interval Register */
-#define pREG_USB0_EP0_CFGDATA0           ((volatile  uint8_t *)REG_USB0_EP0_CFGDATA0)            /* USB0 EP0 Configuration Information Register */
-#define pREG_USB0_DMA_IRQ                ((volatile  uint8_t *)REG_USB0_DMA_IRQ)                 /* USB0 DMA Interrupt Register */
-#define pREG_USB0_DMA0_CTL               ((volatile uint16_t *)REG_USB0_DMA0_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA1_CTL               ((volatile uint16_t *)REG_USB0_DMA1_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA2_CTL               ((volatile uint16_t *)REG_USB0_DMA2_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA3_CTL               ((volatile uint16_t *)REG_USB0_DMA3_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA4_CTL               ((volatile uint16_t *)REG_USB0_DMA4_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA5_CTL               ((volatile uint16_t *)REG_USB0_DMA5_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA6_CTL               ((volatile uint16_t *)REG_USB0_DMA6_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA7_CTL               ((volatile uint16_t *)REG_USB0_DMA7_CTL)                /* USB0 DMA Channel n Control Register */
-#define pREG_USB0_DMA0_ADDR              ((void * volatile *)REG_USB0_DMA0_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA1_ADDR              ((void * volatile *)REG_USB0_DMA1_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA2_ADDR              ((void * volatile *)REG_USB0_DMA2_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA3_ADDR              ((void * volatile *)REG_USB0_DMA3_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA4_ADDR              ((void * volatile *)REG_USB0_DMA4_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA5_ADDR              ((void * volatile *)REG_USB0_DMA5_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA6_ADDR              ((void * volatile *)REG_USB0_DMA6_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA7_ADDR              ((void * volatile *)REG_USB0_DMA7_ADDR)                 /* USB0 DMA Channel n Address Register */
-#define pREG_USB0_DMA0_CNT               ((volatile uint32_t *)REG_USB0_DMA0_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA1_CNT               ((volatile uint32_t *)REG_USB0_DMA1_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA2_CNT               ((volatile uint32_t *)REG_USB0_DMA2_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA3_CNT               ((volatile uint32_t *)REG_USB0_DMA3_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA4_CNT               ((volatile uint32_t *)REG_USB0_DMA4_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA5_CNT               ((volatile uint32_t *)REG_USB0_DMA5_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA6_CNT               ((volatile uint32_t *)REG_USB0_DMA6_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_DMA7_CNT               ((volatile uint32_t *)REG_USB0_DMA7_CNT)                /* USB0 DMA Channel n Count Register */
-#define pREG_USB0_RQPKTCNT0              ((volatile uint16_t *)REG_USB0_RQPKTCNT0)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT1              ((volatile uint16_t *)REG_USB0_RQPKTCNT1)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT2              ((volatile uint16_t *)REG_USB0_RQPKTCNT2)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT3              ((volatile uint16_t *)REG_USB0_RQPKTCNT3)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT4              ((volatile uint16_t *)REG_USB0_RQPKTCNT4)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT5              ((volatile uint16_t *)REG_USB0_RQPKTCNT5)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT6              ((volatile uint16_t *)REG_USB0_RQPKTCNT6)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT7              ((volatile uint16_t *)REG_USB0_RQPKTCNT7)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT8              ((volatile uint16_t *)REG_USB0_RQPKTCNT8)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT9              ((volatile uint16_t *)REG_USB0_RQPKTCNT9)               /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_RQPKTCNT10             ((volatile uint16_t *)REG_USB0_RQPKTCNT10)              /* USB0 EPn Request Packet Count Register */
-#define pREG_USB0_CT_UCH                 ((volatile uint16_t *)REG_USB0_CT_UCH)                  /* USB0 Chirp Timeout Register */
-#define pREG_USB0_CT_HHSRTN              ((volatile uint16_t *)REG_USB0_CT_HHSRTN)               /* USB0 Host High Speed Return to Normal Register */
-#define pREG_USB0_CT_HSBT                ((volatile uint16_t *)REG_USB0_CT_HSBT)                 /* USB0 High Speed Timeout Register */
-#define pREG_USB0_LPM_ATTR               ((volatile uint16_t *)REG_USB0_LPM_ATTR)                /* USB0 LPM Attribute Register */
-#define pREG_USB0_LPM_CTL                ((volatile  uint8_t *)REG_USB0_LPM_CTL)                 /* USB0 LPM Control Register */
-#define pREG_USB0_LPM_IEN                ((volatile  uint8_t *)REG_USB0_LPM_IEN)                 /* USB0 LPM Interrupt Enable Register */
-#define pREG_USB0_LPM_IRQ                ((volatile  uint8_t *)REG_USB0_LPM_IRQ)                 /* USB0 LPM Interrupt Status Register */
-#define pREG_USB0_LPM_FADDR              ((volatile  uint8_t *)REG_USB0_LPM_FADDR)               /* USB0 LPM Function Address Register */
-#define pREG_USB0_VBUS_CTL               ((volatile  uint8_t *)REG_USB0_VBUS_CTL)                /* USB0 VBUS Control Register */
-#define pREG_USB0_BAT_CHG                ((volatile  uint8_t *)REG_USB0_BAT_CHG)                 /* USB0 Battery Charging Control Register */
-#define pREG_USB0_PHY_CTL                ((volatile  uint8_t *)REG_USB0_PHY_CTL)                 /* USB0 PHY Control Register */
-#define pREG_USB0_PLL_OSC                ((volatile uint16_t *)REG_USB0_PLL_OSC)                 /* USB0 PLL and Oscillator Control Register */
-
-
-/* =========================================================================
-       L1DM0
-   ========================================================================= */
-#define pSRAM_BASE_ADDRESS               ((void * volatile *)SRAM_BASE_ADDRESS)                  /* SRAM Base Address */
-#define pDMEM_CONTROL                    ((volatile uint32_t *)DMEM_CONTROL)                     /* Data memory control */
-#define pDCPLB_STATUS                    ((volatile uint32_t *)DCPLB_STATUS)                     /* Data Cacheability Protection Lookaside Buffer Status */
-#define pDCPLB_FAULT_ADDR                ((void * volatile *)DCPLB_FAULT_ADDR)                   /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define pDCPLB_ADDR0                     ((void * volatile *)DCPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR1                     ((void * volatile *)DCPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR2                     ((void * volatile *)DCPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR3                     ((void * volatile *)DCPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR4                     ((void * volatile *)DCPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR5                     ((void * volatile *)DCPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR6                     ((void * volatile *)DCPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR7                     ((void * volatile *)DCPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR8                     ((void * volatile *)DCPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR9                     ((void * volatile *)DCPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR10                    ((void * volatile *)DCPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR11                    ((void * volatile *)DCPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR12                    ((void * volatile *)DCPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR13                    ((void * volatile *)DCPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR14                    ((void * volatile *)DCPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_ADDR15                    ((void * volatile *)DCPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pDCPLB_DATA0                     ((volatile uint32_t *)DCPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA1                     ((volatile uint32_t *)DCPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA2                     ((volatile uint32_t *)DCPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA3                     ((volatile uint32_t *)DCPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA4                     ((volatile uint32_t *)DCPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA5                     ((volatile uint32_t *)DCPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA6                     ((volatile uint32_t *)DCPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA7                     ((volatile uint32_t *)DCPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA8                     ((volatile uint32_t *)DCPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA9                     ((volatile uint32_t *)DCPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA10                    ((volatile uint32_t *)DCPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA11                    ((volatile uint32_t *)DCPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA12                    ((volatile uint32_t *)DCPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA13                    ((volatile uint32_t *)DCPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA14                    ((volatile uint32_t *)DCPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDCPLB_DATA15                    ((volatile uint32_t *)DCPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define pDTEST_COMMAND                   ((volatile uint32_t *)DTEST_COMMAND)                    /* Data Test Command Register */
-#define pDTEST_DATA0                     ((volatile uint32_t *)DTEST_DATA0)                      /* Data Test Data Register */
-#define pDTEST_DATA1                     ((volatile uint32_t *)DTEST_DATA1)                      /* Data Test Data Register */
-#define pL1DBNKA_PELOC                   ((volatile uint32_t *)L1DBNKA_PELOC)                    /* Data Bank A Parity Error Location */
-#define pL1DBNKB_PELOC                   ((volatile uint32_t *)L1DBNKB_PELOC)                    /* Data Bank B Parity Error Location */
-
-
-/* =========================================================================
-       L1IM0
-   ========================================================================= */
-#define pIMEM_CONTROL                    ((volatile uint32_t *)IMEM_CONTROL)                     /* Instruction memory control */
-#define pICPLB_STATUS                    ((volatile uint32_t *)ICPLB_STATUS)                     /* Cacheability Protection Lookaside Buffer Status */
-#define pICPLB_FAULT_ADDR                ((void * volatile *)ICPLB_FAULT_ADDR)                   /* Cacheability Protection Lookaside Buffer Fault Address */
-#define pICPLB_ADDR0                     ((void * volatile *)ICPLB_ADDR0)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR1                     ((void * volatile *)ICPLB_ADDR1)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR2                     ((void * volatile *)ICPLB_ADDR2)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR3                     ((void * volatile *)ICPLB_ADDR3)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR4                     ((void * volatile *)ICPLB_ADDR4)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR5                     ((void * volatile *)ICPLB_ADDR5)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR6                     ((void * volatile *)ICPLB_ADDR6)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR7                     ((void * volatile *)ICPLB_ADDR7)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR8                     ((void * volatile *)ICPLB_ADDR8)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR9                     ((void * volatile *)ICPLB_ADDR9)                        /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR10                    ((void * volatile *)ICPLB_ADDR10)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR11                    ((void * volatile *)ICPLB_ADDR11)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR12                    ((void * volatile *)ICPLB_ADDR12)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR13                    ((void * volatile *)ICPLB_ADDR13)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR14                    ((void * volatile *)ICPLB_ADDR14)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_ADDR15                    ((void * volatile *)ICPLB_ADDR15)                       /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define pICPLB_DATA0                     ((volatile uint32_t *)ICPLB_DATA0)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA1                     ((volatile uint32_t *)ICPLB_DATA1)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA2                     ((volatile uint32_t *)ICPLB_DATA2)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA3                     ((volatile uint32_t *)ICPLB_DATA3)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA4                     ((volatile uint32_t *)ICPLB_DATA4)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA5                     ((volatile uint32_t *)ICPLB_DATA5)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA6                     ((volatile uint32_t *)ICPLB_DATA6)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA7                     ((volatile uint32_t *)ICPLB_DATA7)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA8                     ((volatile uint32_t *)ICPLB_DATA8)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA9                     ((volatile uint32_t *)ICPLB_DATA9)                      /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA10                    ((volatile uint32_t *)ICPLB_DATA10)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA11                    ((volatile uint32_t *)ICPLB_DATA11)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA12                    ((volatile uint32_t *)ICPLB_DATA12)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA13                    ((volatile uint32_t *)ICPLB_DATA13)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA14                    ((volatile uint32_t *)ICPLB_DATA14)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pICPLB_DATA15                    ((volatile uint32_t *)ICPLB_DATA15)                     /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define pITEST_COMMAND                   ((volatile uint32_t *)ITEST_COMMAND)                    /* Instruction Test Command Register */
-#define pITEST_DATA0                     ((volatile uint32_t *)ITEST_DATA0)                      /* Instruction Test Data Register */
-#define pITEST_DATA1                     ((volatile uint32_t *)ITEST_DATA1)                      /* Instruction Test Data Register */
-#define pL1IBNKA_PELOC                   ((volatile uint32_t *)L1IBNKA_PELOC)                    /* Instruction Bank A Parity Error Location */
-#define pL1IBNKB_PELOC                   ((volatile uint32_t *)L1IBNKB_PELOC)                    /* Instruction Bank B Parity Error Location */
-#define pL1IBNKC_PELOC                   ((volatile uint32_t *)L1IBNKC_PELOC)                    /* Instruction Bank C Parity Error Location */
-
-
-/* =========================================================================
-       ICU0
-   ========================================================================= */
-#define pEVT0                            ((void * volatile *)EVT0)                               /* Event Vector */
-#define pEVT1                            ((void * volatile *)EVT1)                               /* Event Vector */
-#define pEVT2                            ((void * volatile *)EVT2)                               /* Event Vector */
-#define pEVT3                            ((void * volatile *)EVT3)                               /* Event Vector */
-#define pEVT4                            ((void * volatile *)EVT4)                               /* Event Vector */
-#define pEVT5                            ((void * volatile *)EVT5)                               /* Event Vector */
-#define pEVT6                            ((void * volatile *)EVT6)                               /* Event Vector */
-#define pEVT7                            ((void * volatile *)EVT7)                               /* Event Vector */
-#define pEVT8                            ((void * volatile *)EVT8)                               /* Event Vector */
-#define pEVT9                            ((void * volatile *)EVT9)                               /* Event Vector */
-#define pEVT10                           ((void * volatile *)EVT10)                              /* Event Vector */
-#define pEVT11                           ((void * volatile *)EVT11)                              /* Event Vector */
-#define pEVT12                           ((void * volatile *)EVT12)                              /* Event Vector */
-#define pEVT13                           ((void * volatile *)EVT13)                              /* Event Vector */
-#define pEVT14                           ((void * volatile *)EVT14)                              /* Event Vector */
-#define pEVT15                           ((void * volatile *)EVT15)                              /* Event Vector */
-#define pIMASK                           ((volatile uint32_t *)IMASK)                            /* Interrupt Mask Register */
-#define pIPEND                           ((volatile uint32_t *)IPEND)                            /* Interrupts Pending Register */
-#define pILAT                            ((volatile uint32_t *)ILAT)                             /* Interrupt Latch Register */
-#define pIPRIO                           ((volatile uint32_t *)IPRIO)                            /* Interrupt Priority Register */
-#define pCEC_SID                         ((volatile uint32_t *)CEC_SID)                          /* Core System Interrupt ID */
-
-
-/* =========================================================================
-       TMR0
-   ========================================================================= */
-#define pTCNTL                           ((volatile uint32_t *)TCNTL)                            /* Timer Control Register */
-#define pTPERIOD                         ((volatile uint32_t *)TPERIOD)                          /* Timer Period Register */
-#define pTSCALE                          ((volatile uint32_t *)TSCALE)                           /* Timer Scale Register */
-#define pTCOUNT                          ((volatile uint32_t *)TCOUNT)                           /* Timer Count Register */
-
-
-/* =========================================================================
-       DBG0
-   ========================================================================= */
-#define pDSPID                           ((volatile uint32_t *)DSPID)                            /* DSP Identification Register */
-
-
-/* =========================================================================
-       TB0
-   ========================================================================= */
-#define pTBUFCTL                         ((volatile uint32_t *)TBUFCTL)                          /* Trace Buffer Control Register */
-#define pTBUFSTAT                        ((volatile uint32_t *)TBUFSTAT)                         /* Trace Buffer Status Register */
-#define pTBUF                            ((void * volatile *)TBUF)                               /* Trace Buffer */
-
-
-/* =========================================================================
-       WP0
-   ========================================================================= */
-#define pWPIACTL                         ((volatile uint32_t *)WPIACTL)                          /* Watchpoint Instruction Address Control Register 01 */
-#define pWPIA0                           ((void * volatile *)WPIA0)                              /* Watchpoint Instruction Address Register */
-#define pWPIA1                           ((void * volatile *)WPIA1)                              /* Watchpoint Instruction Address Register */
-#define pWPIA2                           ((void * volatile *)WPIA2)                              /* Watchpoint Instruction Address Register */
-#define pWPIA3                           ((void * volatile *)WPIA3)                              /* Watchpoint Instruction Address Register */
-#define pWPIA4                           ((void * volatile *)WPIA4)                              /* Watchpoint Instruction Address Register */
-#define pWPIA5                           ((void * volatile *)WPIA5)                              /* Watchpoint Instruction Address Register */
-#define pWPIACNT0                        ((volatile uint32_t *)WPIACNT0)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT1                        ((volatile uint32_t *)WPIACNT1)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT2                        ((volatile uint32_t *)WPIACNT2)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT3                        ((volatile uint32_t *)WPIACNT3)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT4                        ((volatile uint32_t *)WPIACNT4)                         /* Watchpoint Instruction Address Count Register */
-#define pWPIACNT5                        ((volatile uint32_t *)WPIACNT5)                         /* Watchpoint Instruction Address Count Register */
-#define pWPDACTL                         ((volatile uint32_t *)WPDACTL)                          /* Watchpoint Data Address Control Register */
-#define pWPDA0                           ((void * volatile *)WPDA0)                              /* Watchpoint Data Address Register */
-#define pWPDA1                           ((void * volatile *)WPDA1)                              /* Watchpoint Data Address Register */
-#define pWPDACNT0                        ((volatile uint32_t *)WPDACNT0)                         /* Watchpoint Data Address Count Value Register */
-#define pWPDACNT1                        ((volatile uint32_t *)WPDACNT1)                         /* Watchpoint Data Address Count Value Register */
-#define pWPSTAT                          ((volatile uint32_t *)WPSTAT)                           /* Watchpoint Status Register */
-
-
-/* =========================================================================
-       PF0
-   ========================================================================= */
-#define pPFCTL                           ((volatile uint32_t *)PFCTL)                            /* Performance Monitor Control Register */
-#define pPFCNTR0                         ((volatile uint32_t *)PFCNTR0)                          /* Performance Monitor Counter 0 */
-#define pPFCNTR1                         ((volatile uint32_t *)PFCNTR1)                          /* Performance Monitor Counter 1 */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif	/* end ifndef _CDEF_BF609_H */
diff --git a/libgloss/bfin/include/cdef_LPBlackfin.h b/libgloss/bfin/include/cdef_LPBlackfin.h
deleted file mode 100644
index 303427358..000000000
--- a/libgloss/bfin/include/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdef_LPBlackfin.h
- *
- * (c) Copyright 2002-2005 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-/* Cache & SRAM Memory */
-#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
-#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
-#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
-#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
-#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
-#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
-#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
-#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
-#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
-#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
-#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
-#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
-#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
-#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
-#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
-#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
-#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
-#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
-#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
-#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
-#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
-#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
-#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
-#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
-#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
-#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
-#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
-#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
-#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
-#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
-#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
-#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
-#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
-#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
-#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
-#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
-#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
-#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
-#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
-#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
-#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
-#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
-#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
-#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
-#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
-#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
-#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
-#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
-#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
-#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
-#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
-#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
-#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
-#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
-#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
-#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
-#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
-#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
-#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
-#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
-#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
-#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
-#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
-#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
-#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
-#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
-#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
-#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
-#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
-#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
-#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
-#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
-#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
-#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
-
-/* Event/Interrupt Registers */
-#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
-#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
-#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
-#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
-#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
-#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
-#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
-#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
-#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
-#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
-#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
-#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
-#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
-#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
-#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
-#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
-#define pIMASK ((volatile unsigned long *)IMASK)
-#define pIPEND ((volatile unsigned long *)IPEND)
-#define pILAT ((volatile unsigned long *)ILAT)
-
-/* Core Timer Registers */
-#define pTCNTL ((volatile unsigned long *)TCNTL)
-#define pTPERIOD ((volatile unsigned long *)TPERIOD)
-#define pTSCALE ((volatile unsigned long *)TSCALE)
-#define pTCOUNT ((volatile unsigned long *)TCOUNT)
-
-/* Debug/MP/Emulation Registers */
-#define pDSPID ((volatile unsigned long *)DSPID)
-#define pDBGCTL ((volatile unsigned long *)DBGCTL)
-#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
-#define pEMUDAT ((volatile unsigned long *)EMUDAT)
-
-/* Trace Buffer Registers */
-#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
-#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
-#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
-
-/* Watch Point Control Registers */
-#define pWPIACTL ((volatile unsigned long *)WPIACTL)
-#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
-#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
-#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
-#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
-#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
-#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
-#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
-#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
-#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
-#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
-#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
-#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
-#define pWPDACTL ((volatile unsigned long *)WPDACTL)
-#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
-#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
-#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
-#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
-#define pWPSTAT ((volatile unsigned long *)WPSTAT)
-
-/* Performance Monitor Registers */
-#define pPFCTL ((volatile unsigned long *)PFCTL)
-#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
-#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_LPBLACKFIN_H */
diff --git a/libgloss/bfin/include/cdefblackfin.h b/libgloss/bfin/include/cdefblackfin.h
deleted file mode 100644
index 031a42982..000000000
--- a/libgloss/bfin/include/cdefblackfin.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cdefblackfin.h
- *
- * (c) Copyright 2002-2005 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _CDEF_BLACKFIN_H
-#define _CDEF_BLACKFIN_H
-
-#if defined(__ADSPLPBLACKFIN__)
-#warning cdefblackfin.h should only be included for 535 compatible chips.
-#endif
-#include <defblackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-#ifndef _PTR_TO_VOL_VOID_PTR
-#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
-#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
-#else
-#define _PTR_TO_VOL_VOID_PTR (volatile void **)
-#endif
-#endif
-
-/* Cache & SRAM Memory */
-#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
-#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
-#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
-#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
-#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
-#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
-#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
-#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
-#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
-#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
-#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
-#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
-#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
-#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
-#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
-#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
-#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
-#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
-#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
-#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
-#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
-#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
-#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
-#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
-#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
-#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
-#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
-#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
-#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
-#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
-#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
-#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
-#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
-#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
-#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
-#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
-#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
-#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
-#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
-#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
-#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
-#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
-#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
-#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
-#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
-#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
-#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
-#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
-#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
-#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
-#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
-#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
-#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
-#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
-#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
-#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
-#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
-#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
-#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
-#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
-#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
-#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
-#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
-#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
-#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
-#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
-#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
-#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
-#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
-#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
-#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
-#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
-#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
-#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
-#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
-#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
-#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
-
-/* Event/Interrupt Registers */
-#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
-#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
-#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
-#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
-#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
-#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
-#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
-#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
-#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
-#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
-#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
-#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
-#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
-#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
-#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
-#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
-#define pIMASK ((volatile unsigned short *)IMASK)
-#define pIPEND ((volatile unsigned short *)IPEND)
-#define pILAT ((volatile unsigned short *)ILAT)
-
-/* Core Timer Registers */
-#define pTCNTL ((volatile unsigned long *)TCNTL)
-#define pTPERIOD ((volatile unsigned long *)TPERIOD)
-#define pTSCALE ((volatile unsigned long *)TSCALE)
-#define pTCOUNT ((volatile unsigned long *)TCOUNT)
-
-/* Debug/MP/Emulation Registers */
-#define pDSPID ((volatile unsigned long *)DSPID)
-#define pDBGCTL ((volatile unsigned long *)DBGCTL)
-#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
-#define pEMUDAT ((volatile unsigned long *)EMUDAT)
-
-/* Trace Buffer Registers */
-#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
-#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
-#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
-
-/* Watch Point Control Registers */
-#define pWPIACTL ((volatile unsigned long *)WPIACTL)
-#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
-#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
-#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
-#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
-#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
-#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
-#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
-#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
-#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
-#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
-#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
-#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
-#define pWPDACTL ((volatile unsigned long *)WPDACTL)
-#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
-#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
-#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
-#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
-#define pWPSTAT ((volatile unsigned long *)WPSTAT)
-
-/* Performance Monitor Registers */
-#define pPFCTL ((volatile unsigned long *)PFCTL)
-#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
-#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CDEF_BLACKFIN_H */
diff --git a/libgloss/bfin/include/cplb.h b/libgloss/bfin/include/cplb.h
deleted file mode 100644
index 71a47c6b2..000000000
--- a/libgloss/bfin/include/cplb.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * cplb.h
- *
- * (c) Copyright 2002-2007 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* Defines necessary for cplb initialisation routines. */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <sys/platform.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#endif /* _MISRA_RULES */
-
-#define CPLB_ENABLE_ICACHE_P  0
-#define CPLB_ENABLE_DCACHE_P  1
-#define CPLB_ENABLE_DCACHE2_P 2
-#define CPLB_ENABLE_CPLBS_P   3  /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P  4
-#define CPLB_ENABLE_DCPLBS_P  5
-#define CPLB_SET_DCBS_P       6
-#define CPLB_INVALIDATE_B_P   23
-
-/* ___cplb_ctrl bitmasks */
-#define CPLB_ENABLE_ICACHE   (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE   (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2  (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS    (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS   (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS   (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS  \
-           ( CPLB_ENABLE_CPLBS | CPLB_ENABLE_ICPLBS | CPLB_ENABLE_DCPLBS )
-#define CPLB_SET_DCBS        (1<<CPLB_SET_DCBS_P)
-
-/* Bitmasks for dcache_invalidate routine parameters */
-#define CPLB_INVALIDATE_A  0
-#define CPLB_INVALIDATE_B  (1<<CPLB_INVALIDATE_B_P)
-
-/* _cplb_mgr return values */
-#define CPLB_RELOADED      0x0000
-#define CPLB_NO_UNLOCKED   0x0001
-#define CPLB_NO_ADDR_MATCH 0x0002
-#define CPLB_PROT_VIOL     0x0003
-#define CPLB_NO_ACTION     0x0004
-
-/* CPLB configurations */
-#define CPLB_DEF_CACHE_WT  ( CPLB_L1_CHBL | CPLB_WT )
-#define CPLB_DEF_CACHE_WB  ( CPLB_L1_CHBL )
-#define CPLB_CACHE_ENABLED ( CPLB_L1_CHBL | CPLB_DIRTY )
-
-#define CPLB_DEF_CACHE     ( CPLB_L1_CHBL | CPLB_WT )
-#define CPLB_ALL_ACCESS    ( CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR )
-
-#define CPLB_I_PAGE_MGMT   ( CPLB_LOCK | CPLB_VALID )
-#define CPLB_D_PAGE_MGMT   ( CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID )
-#define CPLB_DNOCACHE      ( CPLB_ALL_ACCESS | CPLB_VALID )
-#define CPLB_DDOCACHE      ( CPLB_DNOCACHE | CPLB_DEF_CACHE )
-#define CPLB_INOCACHE      ( CPLB_USER_RD | CPLB_VALID )
-#define CPLB_IDOCACHE      ( CPLB_INOCACHE | CPLB_L1_CHBL )
-
-#define CPLB_DDOCACHE_WT   ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WT )
-#define CPLB_DDOCACHE_WB   ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WB )
-
-/* Event type parameter for replacement manager _cplb_mgr */
-#define CPLB_EVT_ICPLB_MISS   0
-#define CPLB_EVT_DCPLB_MISS   1
-#define CPLB_EVT_DCPLB_WRITE  2
-
-/* size of cplb tables */
-#define __CPLB_TABLE_SIZE    16
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CPLB_H */
diff --git a/libgloss/bfin/include/cplbtab.h b/libgloss/bfin/include/cplbtab.h
deleted file mode 100644
index e3cd97cac..000000000
--- a/libgloss/bfin/include/cplbtab.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#pragma once
-#ifndef __NO_BUILTIN
-#pragma system_header /* cplbtab.h */
-#endif
-/************************************************************************
- *
- * cplbtab.h
- *
- * (c) Copyright 2002-2007 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* Define structures for the CPLB tables. */
-
-#ifndef _CPLBTAB_H
-#define _CPLBTAB_H
-
-#include <cplb.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_6_3)
-#pragma diag(suppress:misra_rule_8_12)
-#endif /* _MISRA_RULES */
-
-typedef struct {
-  unsigned long addr;
-  unsigned long flags;
-} cplb_entry;
-
-extern cplb_entry dcplbs_table[];
-extern cplb_entry icplbs_table[];
-extern int __cplb_ctrl;
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-void cplb_init(int _enable_cpls_caches);
-int cplb_mgr(int _is_data_miss, int _enable_cache);
-void cplb_hdr(void);
-void cache_invalidate(int _caches);
-void icache_invalidate(void);
-void dcache_invalidate(int _caches);
-void dcache_invalidate_both(void);
-void flush_data_cache(void);
-void flush_data_buffer(void *_start, void *_end, int _invalidate);
-void disable_data_cache(void);
-void enable_data_cache(int _cplb_ctrl);
-
-#ifdef __cplusplus
- }
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _CPLBTAB_H */
-
diff --git a/libgloss/bfin/include/defBF504.h b/libgloss/bfin/include/defBF504.h
deleted file mode 100644
index 220e2641d..000000000
--- a/libgloss/bfin/include/defBF504.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF504 processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _DEF_BF504_H
-#define _DEF_BF504_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* Include defBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <defBF50x_base.h>
-
-/* Define the set of macros that are specific to the ADSP-BF504 processor */
-
-#endif /* _DEF_BF504_H */
diff --git a/libgloss/bfin/include/defBF504F.h b/libgloss/bfin/include/defBF504F.h
deleted file mode 100644
index be3e202c1..000000000
--- a/libgloss/bfin/include/defBF504F.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF504F processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _DEF_BF504F_H
-#define _DEF_BF504F_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_1:"ADI header disables rule 5.1 which bars use of long identifiers (>31 chars).")
-#endif /* _MISRA_RULES */
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* Include defBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <defBF50x_base.h>
-
-/* Define the set of macros that are specific to the ADSP-BF504F processor */
-
-
-/* Flash commands */
-#define FLASH_CMD_BLOCK_LOCK_CONFIRM     0x01
-#define FLASH_CMD_SET_CONFIG_CONFIRM     0x03
-#define FLASH_CMD_ALT_PROGRAM_SETUP      0x10
-#define FLASH_CMD_BLOCK_ERASE_SETUP      0x20
-#define FLASH_CMD_BLOCK_LOCKDOWN_CONFIRM 0x2F
-#define FLASH_CMD_ENH_FACT_PROG_SETUP    0x30
-#define FLASH_CMD_DOUBLE_WORD_PROG_SETUP 0x35
-#define FLASH_CMD_PROGRAM_SETUP          0x40
-#define FLASH_CMD_CLEAR_STATUS           0x50
-#define FLASH_CMD_QUAD_WORD_PROG_SETUP   0x56
-#define FLASH_CMD_BLOCK_LOCK_SETUP       0x60
-#define FLASH_CMD_BLOCK_UNLOCK_SETUP     0x60
-#define FLASH_CMD_BLOCK_LOCKDOWN_SETUP   0x60
-#define FLASH_CMD_SET_CONFIG_SETUP       0x60
-#define FLASH_CMD_READ_STATUS            0x70
-#define FLASH_CMD_QUAD_ENH_PROG_SETUP    0x75
-#define FLASH_CMD_READ_ELECTRONIC_SIG    0x90
-#define FLASH_CMD_READ_CFI_QUERY         0x98
-#define FLASH_CMD_PROGRAM_SUSPEND        0xB0
-#define FLASH_CMD_ERASE_SUSPEND          0xB0
-#define FLASH_CMD_PROTECTION_REG_PROGRAM 0xC0
-#define FLASH_CMD_PROGRAM_RESUME         0xD0
-#define FLASH_CMD_ERASE_RESUME           0xD0
-#define FLASH_CMD_BLOCK_ERASE_CONFIRM    0xD0
-#define FLASH_CMD_BLOCK_UNLOCK_CONFIRM   0xD0
-#define FLASH_CMD_ENH_FACT_PROG_CONFIRM  0xD0
-#define FLASH_CMD_READ_ARRAY             0xFF
-
-/* Bit definitions for Flash Configuration Register */
-#define FLASH_CR_ASYNC_READ            0x8000
-#define FLASH_CR_XLAT_5                0x2800
-#define FLASH_CR_XLAT_4                0x2000
-#define FLASH_CR_XLAT_3                0x1800
-#define FLASH_CR_XLAT_2                0x1000
-#define FLASH_CR_WAIT_HIGH             0x0400
-#define FLASH_CR_DATA_HOLD             0x0200
-#define FLASH_CR_WAIT_ONE              0x0100
-#define FLASH_CR_BURST_SEQ             0x0080
-#define FLASH_CR_CLK_RISE              0x0040
-#define FLASH_CR_WRAP_DIS              0x0008
-#define FLASH_CR_BURST_CONT            0x0007
-#define FLASH_CR_BURST_16              0x0003
-#define FLASH_CR_BURST_8               0x0002
-#define FLASH_CR_BURST_4               0x0001
-
-/* Bit definitions for Flash Status Register */
-#define FLASH_SR_PRG_ERASE_READY       0x0080
-#define FLASH_SR_ERASE_SUSPENDED       0x0040
-#define FLASH_SR_ERASE_ERROR           0x0020
-#define FLASH_SR_PRG_ERROR             0x0010
-#define FLASH_SR_VPP_INVALID_ABORT     0x0008
-#define FLASH_SR_PRG_SUSPENDED         0x0004
-#define FLASH_SR_BLK_PROT_ABORT        0x0002
-#define FLASH_SR_BNK_WRITE             0x0001
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF504F_H */
diff --git a/libgloss/bfin/include/defBF506F.h b/libgloss/bfin/include/defBF506F.h
deleted file mode 100644
index 89f94b2a8..000000000
--- a/libgloss/bfin/include/defBF506F.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable programs
-** to use symbolic names for register-access and bit-manipulation for the
-** ADSP-BF506F processor.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _DEF_BF506F_H
-#define _DEF_BF506F_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_1:"ADI header disables rule 5.1 which bars use of long identifiers (>31 chars).")
-#endif /* _MISRA_RULES */
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* Include defBF50x_base.h for the set of #defines that are
-** common to all ADSP-BF50x processors
-*/
-#include <defBF50x_base.h>
-
-/*
-** Define the set of macros that are specific to the ADSP-BF506F processor
-*/
-
-/* Flash commands */
-#define FLASH_CMD_BLOCK_LOCK_CONFIRM     0x01
-#define FLASH_CMD_SET_CONFIG_CONFIRM     0x03
-#define FLASH_CMD_ALT_PROGRAM_SETUP      0x10
-#define FLASH_CMD_BLOCK_ERASE_SETUP      0x20
-#define FLASH_CMD_BLOCK_LOCKDOWN_CONFIRM 0x2F
-#define FLASH_CMD_ENH_FACT_PROG_SETUP    0x30
-#define FLASH_CMD_DOUBLE_WORD_PROG_SETUP 0x35
-#define FLASH_CMD_PROGRAM_SETUP          0x40
-#define FLASH_CMD_CLEAR_STATUS           0x50
-#define FLASH_CMD_QUAD_WORD_PROG_SETUP   0x56
-#define FLASH_CMD_BLOCK_LOCK_SETUP       0x60
-#define FLASH_CMD_BLOCK_UNLOCK_SETUP     0x60
-#define FLASH_CMD_BLOCK_LOCKDOWN_SETUP   0x60
-#define FLASH_CMD_SET_CONFIG_SETUP       0x60
-#define FLASH_CMD_READ_STATUS            0x70
-#define FLASH_CMD_QUAD_ENH_PROG_SETUP    0x75
-#define FLASH_CMD_READ_ELECTRONIC_SIG    0x90
-#define FLASH_CMD_READ_CFI_QUERY         0x98
-#define FLASH_CMD_PROGRAM_SUSPEND        0xB0
-#define FLASH_CMD_ERASE_SUSPEND          0xB0
-#define FLASH_CMD_PROTECTION_REG_PROGRAM 0xC0
-#define FLASH_CMD_PROGRAM_RESUME         0xD0
-#define FLASH_CMD_ERASE_RESUME           0xD0
-#define FLASH_CMD_BLOCK_ERASE_CONFIRM    0xD0
-#define FLASH_CMD_BLOCK_UNLOCK_CONFIRM   0xD0
-#define FLASH_CMD_ENH_FACT_PROG_CONFIRM  0xD0
-#define FLASH_CMD_READ_ARRAY             0xFF
-
-/* Bit definitions for Flash Configuration Register */
-#define FLASH_CR_ASYNC_READ            0x8000
-#define FLASH_CR_XLAT_5                0x2800
-#define FLASH_CR_XLAT_4                0x2000
-#define FLASH_CR_XLAT_3                0x1800
-#define FLASH_CR_XLAT_2                0x1000
-#define FLASH_CR_WAIT_HIGH             0x0400
-#define FLASH_CR_DATA_HOLD             0x0200
-#define FLASH_CR_WAIT_ONE              0x0100
-#define FLASH_CR_BURST_SEQ             0x0080
-#define FLASH_CR_CLK_RISE              0x0040
-#define FLASH_CR_WRAP_DIS              0x0008
-#define FLASH_CR_BURST_CONT            0x0007
-#define FLASH_CR_BURST_16              0x0003
-#define FLASH_CR_BURST_8               0x0002
-#define FLASH_CR_BURST_4               0x0001
-
-/* Bit definitions for Flash Status Register */
-#define FLASH_SR_PRG_ERASE_READY       0x0080
-#define FLASH_SR_ERASE_SUSPENDED       0x0040
-#define FLASH_SR_ERASE_ERROR           0x0020
-#define FLASH_SR_PRG_ERROR             0x0010
-#define FLASH_SR_VPP_INVALID_ABORT     0x0008
-#define FLASH_SR_PRG_SUSPENDED         0x0004
-#define FLASH_SR_BLK_PROT_ABORT        0x0002
-#define FLASH_SR_BNK_WRITE             0x0001
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF506F_H */
diff --git a/libgloss/bfin/include/defBF50x_base.h b/libgloss/bfin/include/defBF50x_base.h
deleted file mode 100644
index a5aa09d0d..000000000
--- a/libgloss/bfin/include/defBF50x_base.h
+++ /dev/null
@@ -1,3445 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF50x_base.h
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the system MMRs common to the ADSP-BF50x parts
-** peripherals.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _DEF_BF50X_H
-#define _DEF_BF50X_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros.")
-#endif /* _MISRA_RULES */
-
-
-/* ************************************************************************************************************** */
-/*                           SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF50x                            */
-/* ************************************************************************************************************** */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                   */
-#define PLL_CTL                 0xFFC00000  /* PLL Control Register                         */
-#define PLL_DIV                 0xFFC00004  /* PLL Divide Register                          */
-#define VR_CTL                  0xFFC00008  /* Voltage Regulator Control Register           */
-#define PLL_STAT                0xFFC0000C  /* PLL Status Register                          */
-#define PLL_LOCKCNT             0xFFC00010  /* PLL Lock Count Register                      */
-#define CHIPID                  0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller  (0xFFC00100 - 0xFFC001FF)                                   */
-#define SWRST                   0xFFC00100  /* Software Reset Register                      */
-#define SYSCR                   0xFFC00104  /* System Configuration Register                */
-
-#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register                      */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IMASK               (SIC_IMASK0)
-#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0              */
-#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1              */
-#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2              */
-#define SIC_IAR3                0xFFC0011C  /* Interrupt Assignment Register 3              */
-#define SIC_ISR0                0xFFC00120  /* Interrupt Status Register                    */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_ISR                 (SIC_ISR0)
-#define SIC_IWR0                0xFFC00124  /* Interrupt Wakeup Register                    */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IWR                 (SIC_IWR0)
-
-/* SIC Additions to ADSP-BF50x  (0xFFC0014C - 0xFFC00162)                                   */
-#define SIC_IMASK1              0xFFC0014C  /* Interrupt Mask register of SIC2              */
-#define SIC_IAR4                0xFFC00150  /* Interrupt Assignment register4               */
-#define SIC_IAR5                0xFFC00154  /* Interrupt Assignment register5               */
-#define SIC_IAR6                0xFFC00158  /* Interrupt Assignment register6               */
-#define SIC_ISR1                0xFFC00160  /* Interrupt Statur register                    */
-#define SIC_IWR1                0xFFC00164  /* Interrupt Wakeup register                    */
-
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                   */
-#define WDOG_CTL                0xFFC00200  /* Watchdog Control Register                    */
-#define WDOG_CNT                0xFFC00204  /* Watchdog Count Register                      */
-#define WDOG_STAT               0xFFC00208  /* Watchdog Status Register                     */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                   */
-#define UART0_DLL               0xffc00400   /* Divisor Latch Low Byte                      */
-#define UART0_DLH               0xffc00404   /* Divisor Latch High Byte                     */
-#define UART0_GCTL              0xffc00408   /* Global Control Register                     */
-#define UART0_LCR               0xffc0040c   /* Line Control Register                       */
-#define UART0_MCR               0xffc00410   /* Modem Control Register                      */
-#define UART0_LSR               0xffc00414   /* Line Status Register                        */
-#define UART0_MSR               0xffc00418   /* Modem Status Register                       */
-#define UART0_SCR               0xffc0041c   /* Scratch Register                            */
-#define UART0_IER_SET           0xffc00420   /* Interrupt Enable Register Set               */
-#define UART0_IER_CLEAR         0xffc00424   /* Interrupt Enable Register Clear             */
-#define UART0_THR               0xffc00428   /* Transmit Hold Register                      */
-#define UART0_RBR               0xffc0042c   /* Receive Buffer Register                     */
-
-/* SPI0 Controller              (0xFFC00500 - 0xFFC005FF)                                   */
-#define SPI0_CTL                0xFFC00500  /* SPI Control Register                         */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_CTL                 (SPI0_CTL)
-#define SPI0_FLG                0xFFC00504  /* SPI Flag register                            */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_FLG                 (SPI0_FLG)
-#define SPI0_STAT               0xFFC00508  /* SPI Status register                          */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_STAT                (SPI0_STAT)
-#define SPI0_TDBR               0xFFC0050C  /* SPI Transmit Data Buffer Register            */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_TDBR                (SPI0_TDBR)
-#define SPI0_RDBR               0xFFC00510  /* SPI Receive Data Buffer Register             */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_RDBR                (SPI0_RDBR)
-#define SPI0_BAUD               0xFFC00514  /* SPI Baud rate Register                       */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_BAUD                (SPI0_BAUD)
-#define SPI0_SHADOW             0xFFC00518  /* SPI_RDBR Shadow Register                     */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_SHADOW              (SPI0_SHADOW)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                   */
-#define TIMER0_CONFIG           0xFFC00600  /* Timer 0 Configuration Register               */
-#define TIMER0_COUNTER          0xFFC00604  /* Timer 0 Counter Register                     */
-#define TIMER0_PERIOD           0xFFC00608  /* Timer 0 Period Register                      */
-#define TIMER0_WIDTH            0xFFC0060C  /* Timer 0 Width Register                       */
-
-#define TIMER1_CONFIG           0xFFC00610  /* Timer 1 Configuration Register               */
-#define TIMER1_COUNTER          0xFFC00614  /* Timer 1 Counter Register                     */
-#define TIMER1_PERIOD           0xFFC00618  /* Timer 1 Period Register                      */
-#define TIMER1_WIDTH            0xFFC0061C  /* Timer 1 Width Register                       */
-
-#define TIMER2_CONFIG           0xFFC00620  /* Timer 2 Configuration Register               */
-#define TIMER2_COUNTER          0xFFC00624  /* Timer 2 Counter Register                     */
-#define TIMER2_PERIOD           0xFFC00628  /* Timer 2 Period Register                      */
-#define TIMER2_WIDTH            0xFFC0062C  /* Timer 2 Width Register                       */
-
-#define TIMER3_CONFIG           0xFFC00630  /* Timer 3 Configuration Register               */
-#define TIMER3_COUNTER          0xFFC00634  /* Timer 3 Counter Register                     */
-#define TIMER3_PERIOD           0xFFC00638  /* Timer 3 Period Register                      */
-#define TIMER3_WIDTH            0xFFC0063C  /* Timer 3 Width Register                       */
-
-#define TIMER4_CONFIG           0xFFC00640  /* Timer 4 Configuration Register               */
-#define TIMER4_COUNTER          0xFFC00644  /* Timer 4 Counter Register                     */
-#define TIMER4_PERIOD           0xFFC00648  /* Timer 4 Period Register                      */
-#define TIMER4_WIDTH            0xFFC0064C  /* Timer 4 Width Register                       */
-
-#define TIMER5_CONFIG           0xFFC00650  /* Timer 5 Configuration Register               */
-#define TIMER5_COUNTER          0xFFC00654  /* Timer 5 Counter Register                     */
-#define TIMER5_PERIOD           0xFFC00658  /* Timer 5 Period Register                      */
-#define TIMER5_WIDTH            0xFFC0065C  /* Timer 5 Width Register                       */
-
-#define TIMER6_CONFIG           0xFFC00660  /* Timer 6 Configuration Register               */
-#define TIMER6_COUNTER          0xFFC00664  /* Timer 6 Counter Register                     */
-#define TIMER6_PERIOD           0xFFC00668  /* Timer 6 Period Register                      */
-#define TIMER6_WIDTH            0xFFC0066C  /* Timer 6 Width Register                       */
-
-#define TIMER7_CONFIG           0xFFC00670  /* Timer 7 Configuration Register               */
-#define TIMER7_COUNTER          0xFFC00674  /* Timer 7 Counter Register                     */
-#define TIMER7_PERIOD           0xFFC00678  /* Timer 7 Period Register                      */
-#define TIMER7_WIDTH            0xFFC0067C  /* Timer 7 Width Register                       */
-
-#define TIMER_ENABLE            0xFFC00680  /* Timer Enable Register                        */
-#define TIMER_DISABLE           0xFFC00684  /* Timer Disable Register                       */
-#define TIMER_STATUS            0xFFC00688  /* Timer Status Register                        */
-
-
-/* General Purpose I/O Port F   (0xFFC00700 - 0xFFC007FF)                                   */
-#define PORTFIO                 0xFFC00700  /* Port F I/O Pin State Specify Register        */
-#define PORTFIO_CLEAR           0xFFC00704  /* Port F I/O Peripheral Interrupt Clear Register   */
-#define PORTFIO_SET             0xFFC00708  /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE          0xFFC0070C  /* Port F I/O Pin State Toggle Register         */
-#define PORTFIO_MASKA           0xFFC00710  /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR     0xFFC00714  /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET       0xFFC00718  /* Port F I/O Mask Enable Interrupt A Register  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C  /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB           0xFFC00720  /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR     0xFFC00724  /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET       0xFFC00728  /* Port F I/O Mask Enable Interrupt B Register  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C  /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR             0xFFC00730  /* Port F I/O Direction Register                */
-#define PORTFIO_POLAR           0xFFC00734  /* Port F I/O Source Polarity Register          */
-#define PORTFIO_EDGE            0xFFC00738  /* Port F I/O Source Sensitivity Register       */
-#define PORTFIO_BOTH            0xFFC0073C  /* Port F I/O Set on BOTH Edges Register        */
-#define PORTFIO_INEN            0xFFC00740  /* Port F I/O Input Enable Register             */
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                   */
-#define SPORT0_TCR1             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register     */
-#define SPORT0_TCR2             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register     */
-#define SPORT0_TCLKDIV          0xFFC00808  /* SPORT0 Transmit Clock Divider                */
-#define SPORT0_TFSDIV           0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider           */
-#define SPORT0_TX               0xFFC00810  /* SPORT0 TX Data Register                      */
-#define SPORT0_RX               0xFFC00818  /* SPORT0 RX Data Register                      */
-#define SPORT0_RCR1             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register     */
-#define SPORT0_RCR2             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register     */
-#define SPORT0_RCLKDIV          0xFFC00828  /* SPORT0 Receive Clock Divider                 */
-#define SPORT0_RFSDIV           0xFFC0082C  /* SPORT0 Receive Frame Sync Divider            */
-#define SPORT0_STAT             0xFFC00830  /* SPORT0 Status Register                       */
-#define SPORT0_CHNL             0xFFC00834  /* SPORT0 Current Channel Register              */
-#define SPORT0_MCMC1            0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1    */
-#define SPORT0_MCMC2            0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2    */
-#define SPORT0_MTCS0            0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0  */
-#define SPORT0_MTCS1            0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1  */
-#define SPORT0_MTCS2            0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2  */
-#define SPORT0_MTCS3            0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3  */
-#define SPORT0_MRCS0            0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0   */
-#define SPORT0_MRCS1            0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1   */
-#define SPORT0_MRCS2            0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2   */
-#define SPORT0_MRCS3            0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3   */
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                   */
-#define SPORT1_TCR1             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register     */
-#define SPORT1_TCR2             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register     */
-#define SPORT1_TCLKDIV          0xFFC00908  /* SPORT1 Transmit Clock Divider                */
-#define SPORT1_TFSDIV           0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider           */
-#define SPORT1_TX               0xFFC00910  /* SPORT1 TX Data Register                      */
-#define SPORT1_RX               0xFFC00918  /* SPORT1 RX Data Register                      */
-#define SPORT1_RCR1             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register     */
-#define SPORT1_RCR2             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register     */
-#define SPORT1_RCLKDIV          0xFFC00928  /* SPORT1 Receive Clock Divider                 */
-#define SPORT1_RFSDIV           0xFFC0092C  /* SPORT1 Receive Frame Sync Divider            */
-#define SPORT1_STAT             0xFFC00930  /* SPORT1 Status Register                       */
-#define SPORT1_CHNL             0xFFC00934  /* SPORT1 Current Channel Register              */
-#define SPORT1_MCMC1            0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1    */
-#define SPORT1_MCMC2            0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2    */
-#define SPORT1_MTCS0            0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0  */
-#define SPORT1_MTCS1            0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1  */
-#define SPORT1_MTCS2            0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2  */
-#define SPORT1_MTCS3            0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3  */
-#define SPORT1_MRCS0            0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0   */
-#define SPORT1_MRCS1            0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1   */
-#define SPORT1_MRCS2            0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2   */
-#define SPORT1_MRCS3            0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3   */
-
-
-/* External Bus Interface Unit  (0xFFC00A00 - 0xFFC00AFF)                                   */
-#define EBIU_AMGCTL             0xFFC00A00  /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL             0xFFC00A04  /* Asynchronous Memory Bank Control Register    */
-#define EBIU_MODE               0xFFC00A20  /* Asynchronous Memory Mode Control Register    */
-#define EBIU_FCTL               0xFFC00A24  /* Asynchronous Memory Parameter Control Register */
-
-#define EBIU_AMBCTL0            (EBIU_AMBCTL)/* Asynchronous Memory Bank Control Register    */
-
-/* DMA Traffic Control Registers    (0xFFC00B00 - 0xFFC00BFF)                               */
-#define DMA_TC_PER              0xFFC00B0C  /* Traffic Control Periods Register             */
-#define DMA_TC_CNT              0xFFC00B10  /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility    */
-#define DMA_TCPER               0xFFC00B0C  /* Traffic Control Periods Register             */
-#define DMA_TCCNT               0xFFC00B10  /* Traffic Control Current Counts Register      */
-
-/* DMA Controller               (0xFFC00C00 - 0xFFC00FFF)                                   */
-#define DMA0_NEXT_DESC_PTR      0xFFC00C00  /* DMA Channel 0 Next Descriptor Pointer Register   */
-#define DMA0_START_ADDR         0xFFC00C04  /* DMA Channel 0 Start Address Register         */
-#define DMA0_CONFIG             0xFFC00C08  /* DMA Channel 0 Configuration Register         */
-#define DMA0_X_COUNT            0xFFC00C10  /* DMA Channel 0 X Count Register               */
-#define DMA0_X_MODIFY           0xFFC00C14  /* DMA Channel 0 X Modify Register              */
-#define DMA0_Y_COUNT            0xFFC00C18  /* DMA Channel 0 Y Count Register               */
-#define DMA0_Y_MODIFY           0xFFC00C1C  /* DMA Channel 0 Y Modify Register              */
-#define DMA0_CURR_DESC_PTR      0xFFC00C20  /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR          0xFFC00C24  /* DMA Channel 0 Current Address Register       */
-#define DMA0_IRQ_STATUS         0xFFC00C28  /* DMA Channel 0 Interrupt/Status Register      */
-#define DMA0_PERIPHERAL_MAP     0xFFC00C2C  /* DMA Channel 0 Peripheral Map Register        */
-#define DMA0_CURR_X_COUNT       0xFFC00C30  /* DMA Channel 0 Current X Count Register       */
-#define DMA0_CURR_Y_COUNT       0xFFC00C38  /* DMA Channel 0 Current Y Count Register       */
-
-#define DMA1_NEXT_DESC_PTR      0xFFC00C40  /* DMA Channel 1 Next Descriptor Pointer Register   */
-#define DMA1_START_ADDR         0xFFC00C44  /* DMA Channel 1 Start Address Register         */
-#define DMA1_CONFIG             0xFFC00C48  /* DMA Channel 1 Configuration Register         */
-#define DMA1_X_COUNT            0xFFC00C50  /* DMA Channel 1 X Count Register               */
-#define DMA1_X_MODIFY           0xFFC00C54  /* DMA Channel 1 X Modify Register              */
-#define DMA1_Y_COUNT            0xFFC00C58  /* DMA Channel 1 Y Count Register               */
-#define DMA1_Y_MODIFY           0xFFC00C5C  /* DMA Channel 1 Y Modify Register              */
-#define DMA1_CURR_DESC_PTR      0xFFC00C60  /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR          0xFFC00C64  /* DMA Channel 1 Current Address Register       */
-#define DMA1_IRQ_STATUS         0xFFC00C68  /* DMA Channel 1 Interrupt/Status Register      */
-#define DMA1_PERIPHERAL_MAP     0xFFC00C6C  /* DMA Channel 1 Peripheral Map Register        */
-#define DMA1_CURR_X_COUNT       0xFFC00C70  /* DMA Channel 1 Current X Count Register       */
-#define DMA1_CURR_Y_COUNT       0xFFC00C78  /* DMA Channel 1 Current Y Count Register       */
-
-#define DMA2_NEXT_DESC_PTR      0xFFC00C80  /* DMA Channel 2 Next Descriptor Pointer Register   */
-#define DMA2_START_ADDR         0xFFC00C84  /* DMA Channel 2 Start Address Register         */
-#define DMA2_CONFIG             0xFFC00C88  /* DMA Channel 2 Configuration Register         */
-#define DMA2_X_COUNT            0xFFC00C90  /* DMA Channel 2 X Count Register               */
-#define DMA2_X_MODIFY           0xFFC00C94  /* DMA Channel 2 X Modify Register              */
-#define DMA2_Y_COUNT            0xFFC00C98  /* DMA Channel 2 Y Count Register               */
-#define DMA2_Y_MODIFY           0xFFC00C9C  /* DMA Channel 2 Y Modify Register              */
-#define DMA2_CURR_DESC_PTR      0xFFC00CA0  /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR          0xFFC00CA4  /* DMA Channel 2 Current Address Register       */
-#define DMA2_IRQ_STATUS         0xFFC00CA8  /* DMA Channel 2 Interrupt/Status Register      */
-#define DMA2_PERIPHERAL_MAP     0xFFC00CAC  /* DMA Channel 2 Peripheral Map Register        */
-#define DMA2_CURR_X_COUNT       0xFFC00CB0  /* DMA Channel 2 Current X Count Register       */
-#define DMA2_CURR_Y_COUNT       0xFFC00CB8  /* DMA Channel 2 Current Y Count Register       */
-
-#define DMA3_NEXT_DESC_PTR      0xFFC00CC0  /* DMA Channel 3 Next Descriptor Pointer Register   */
-#define DMA3_START_ADDR         0xFFC00CC4  /* DMA Channel 3 Start Address Register         */
-#define DMA3_CONFIG             0xFFC00CC8  /* DMA Channel 3 Configuration Register         */
-#define DMA3_X_COUNT            0xFFC00CD0  /* DMA Channel 3 X Count Register               */
-#define DMA3_X_MODIFY           0xFFC00CD4  /* DMA Channel 3 X Modify Register              */
-#define DMA3_Y_COUNT            0xFFC00CD8  /* DMA Channel 3 Y Count Register               */
-#define DMA3_Y_MODIFY           0xFFC00CDC  /* DMA Channel 3 Y Modify Register              */
-#define DMA3_CURR_DESC_PTR      0xFFC00CE0  /* DMA Channel 3 Current Descriptor Pointer Register            */
-#define DMA3_CURR_ADDR          0xFFC00CE4  /* DMA Channel 3 Current Address Register       */
-#define DMA3_IRQ_STATUS         0xFFC00CE8  /* DMA Channel 3 Interrupt/Status Register      */
-#define DMA3_PERIPHERAL_MAP     0xFFC00CEC  /* DMA Channel 3 Peripheral Map Register        */
-#define DMA3_CURR_X_COUNT       0xFFC00CF0  /* DMA Channel 3 Current X Count Register       */
-#define DMA3_CURR_Y_COUNT       0xFFC00CF8  /* DMA Channel 3 Current Y Count Register       */
-
-#define DMA4_NEXT_DESC_PTR      0xFFC00D00  /* DMA Channel 4 Next Descriptor Pointer Register   */
-#define DMA4_START_ADDR         0xFFC00D04  /* DMA Channel 4 Start Address Register         */
-#define DMA4_CONFIG             0xFFC00D08  /* DMA Channel 4 Configuration Register         */
-#define DMA4_X_COUNT            0xFFC00D10  /* DMA Channel 4 X Count Register               */
-#define DMA4_X_MODIFY           0xFFC00D14  /* DMA Channel 4 X Modify Register              */
-#define DMA4_Y_COUNT            0xFFC00D18  /* DMA Channel 4 Y Count Register               */
-#define DMA4_Y_MODIFY           0xFFC00D1C  /* DMA Channel 4 Y Modify Register              */
-#define DMA4_CURR_DESC_PTR      0xFFC00D20  /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR          0xFFC00D24  /* DMA Channel 4 Current Address Register       */
-#define DMA4_IRQ_STATUS         0xFFC00D28  /* DMA Channel 4 Interrupt/Status Register      */
-#define DMA4_PERIPHERAL_MAP     0xFFC00D2C  /* DMA Channel 4 Peripheral Map Register        */
-#define DMA4_CURR_X_COUNT       0xFFC00D30  /* DMA Channel 4 Current X Count Register       */
-#define DMA4_CURR_Y_COUNT       0xFFC00D38  /* DMA Channel 4 Current Y Count Register       */
-
-#define DMA5_NEXT_DESC_PTR      0xFFC00D40  /* DMA Channel 5 Next Descriptor Pointer Register   */
-#define DMA5_START_ADDR         0xFFC00D44  /* DMA Channel 5 Start Address Register         */
-#define DMA5_CONFIG             0xFFC00D48  /* DMA Channel 5 Configuration Register         */
-#define DMA5_X_COUNT            0xFFC00D50  /* DMA Channel 5 X Count Register               */
-#define DMA5_X_MODIFY           0xFFC00D54  /* DMA Channel 5 X Modify Register              */
-#define DMA5_Y_COUNT            0xFFC00D58  /* DMA Channel 5 Y Count Register               */
-#define DMA5_Y_MODIFY           0xFFC00D5C  /* DMA Channel 5 Y Modify Register              */
-#define DMA5_CURR_DESC_PTR      0xFFC00D60  /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR          0xFFC00D64  /* DMA Channel 5 Current Address Register       */
-#define DMA5_IRQ_STATUS         0xFFC00D68  /* DMA Channel 5 Interrupt/Status Register      */
-#define DMA5_PERIPHERAL_MAP     0xFFC00D6C  /* DMA Channel 5 Peripheral Map Register        */
-#define DMA5_CURR_X_COUNT       0xFFC00D70  /* DMA Channel 5 Current X Count Register       */
-#define DMA5_CURR_Y_COUNT       0xFFC00D78  /* DMA Channel 5 Current Y Count Register       */
-
-#define DMA6_NEXT_DESC_PTR      0xFFC00D80  /* DMA Channel 6 Next Descriptor Pointer Register   */
-#define DMA6_START_ADDR         0xFFC00D84  /* DMA Channel 6 Start Address Register         */
-#define DMA6_CONFIG             0xFFC00D88  /* DMA Channel 6 Configuration Register         */
-#define DMA6_X_COUNT            0xFFC00D90  /* DMA Channel 6 X Count Register               */
-#define DMA6_X_MODIFY           0xFFC00D94  /* DMA Channel 6 X Modify Register              */
-#define DMA6_Y_COUNT            0xFFC00D98  /* DMA Channel 6 Y Count Register               */
-#define DMA6_Y_MODIFY           0xFFC00D9C  /* DMA Channel 6 Y Modify Register              */
-#define DMA6_CURR_DESC_PTR      0xFFC00DA0  /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR          0xFFC00DA4  /* DMA Channel 6 Current Address Register       */
-#define DMA6_IRQ_STATUS         0xFFC00DA8  /* DMA Channel 6 Interrupt/Status Register      */
-#define DMA6_PERIPHERAL_MAP     0xFFC00DAC  /* DMA Channel 6 Peripheral Map Register        */
-#define DMA6_CURR_X_COUNT       0xFFC00DB0  /* DMA Channel 6 Current X Count Register       */
-#define DMA6_CURR_Y_COUNT       0xFFC00DB8  /* DMA Channel 6 Current Y Count Register       */
-
-#define DMA7_NEXT_DESC_PTR      0xFFC00DC0  /* DMA Channel 7 Next Descriptor Pointer Register   */
-#define DMA7_START_ADDR         0xFFC00DC4  /* DMA Channel 7 Start Address Register         */
-#define DMA7_CONFIG             0xFFC00DC8  /* DMA Channel 7 Configuration Register         */
-#define DMA7_X_COUNT            0xFFC00DD0  /* DMA Channel 7 X Count Register               */
-#define DMA7_X_MODIFY           0xFFC00DD4  /* DMA Channel 7 X Modify Register              */
-#define DMA7_Y_COUNT            0xFFC00DD8  /* DMA Channel 7 Y Count Register               */
-#define DMA7_Y_MODIFY           0xFFC00DDC  /* DMA Channel 7 Y Modify Register              */
-#define DMA7_CURR_DESC_PTR      0xFFC00DE0  /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR          0xFFC00DE4  /* DMA Channel 7 Current Address Register       */
-#define DMA7_IRQ_STATUS         0xFFC00DE8  /* DMA Channel 7 Interrupt/Status Register      */
-#define DMA7_PERIPHERAL_MAP     0xFFC00DEC  /* DMA Channel 7 Peripheral Map Register        */
-#define DMA7_CURR_X_COUNT       0xFFC00DF0  /* DMA Channel 7 Current X Count Register       */
-#define DMA7_CURR_Y_COUNT       0xFFC00DF8  /* DMA Channel 7 Current Y Count Register       */
-
-#define DMA8_NEXT_DESC_PTR      0xFFC00E00  /* DMA Channel 8 Next Descriptor Pointer Register   */
-#define DMA8_START_ADDR         0xFFC00E04  /* DMA Channel 8 Start Address Register         */
-#define DMA8_CONFIG             0xFFC00E08  /* DMA Channel 8 Configuration Register         */
-#define DMA8_X_COUNT            0xFFC00E10  /* DMA Channel 8 X Count Register               */
-#define DMA8_X_MODIFY           0xFFC00E14  /* DMA Channel 8 X Modify Register              */
-#define DMA8_Y_COUNT            0xFFC00E18  /* DMA Channel 8 Y Count Register               */
-#define DMA8_Y_MODIFY           0xFFC00E1C  /* DMA Channel 8 Y Modify Register              */
-#define DMA8_CURR_DESC_PTR      0xFFC00E20  /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR          0xFFC00E24  /* DMA Channel 8 Current Address Register       */
-#define DMA8_IRQ_STATUS         0xFFC00E28  /* DMA Channel 8 Interrupt/Status Register      */
-#define DMA8_PERIPHERAL_MAP     0xFFC00E2C  /* DMA Channel 8 Peripheral Map Register        */
-#define DMA8_CURR_X_COUNT       0xFFC00E30  /* DMA Channel 8 Current X Count Register       */
-#define DMA8_CURR_Y_COUNT       0xFFC00E38  /* DMA Channel 8 Current Y Count Register       */
-
-#define DMA9_NEXT_DESC_PTR      0xFFC00E40  /* DMA Channel 9 Next Descriptor Pointer Register   */
-#define DMA9_START_ADDR         0xFFC00E44  /* DMA Channel 9 Start Address Register         */
-#define DMA9_CONFIG             0xFFC00E48  /* DMA Channel 9 Configuration Register         */
-#define DMA9_X_COUNT            0xFFC00E50  /* DMA Channel 9 X Count Register               */
-#define DMA9_X_MODIFY           0xFFC00E54  /* DMA Channel 9 X Modify Register              */
-#define DMA9_Y_COUNT            0xFFC00E58  /* DMA Channel 9 Y Count Register               */
-#define DMA9_Y_MODIFY           0xFFC00E5C  /* DMA Channel 9 Y Modify Register              */
-#define DMA9_CURR_DESC_PTR      0xFFC00E60  /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR          0xFFC00E64  /* DMA Channel 9 Current Address Register       */
-#define DMA9_IRQ_STATUS         0xFFC00E68  /* DMA Channel 9 Interrupt/Status Register      */
-#define DMA9_PERIPHERAL_MAP     0xFFC00E6C  /* DMA Channel 9 Peripheral Map Register        */
-#define DMA9_CURR_X_COUNT       0xFFC00E70  /* DMA Channel 9 Current X Count Register       */
-#define DMA9_CURR_Y_COUNT       0xFFC00E78  /* DMA Channel 9 Current Y Count Register       */
-
-#define DMA10_NEXT_DESC_PTR     0xFFC00E80  /* DMA Channel 10 Next Descriptor Pointer Register  */
-#define DMA10_START_ADDR        0xFFC00E84  /* DMA Channel 10 Start Address Register        */
-#define DMA10_CONFIG            0xFFC00E88  /* DMA Channel 10 Configuration Register        */
-#define DMA10_X_COUNT           0xFFC00E90  /* DMA Channel 10 X Count Register              */
-#define DMA10_X_MODIFY          0xFFC00E94  /* DMA Channel 10 X Modify Register             */
-#define DMA10_Y_COUNT           0xFFC00E98  /* DMA Channel 10 Y Count Register              */
-#define DMA10_Y_MODIFY          0xFFC00E9C  /* DMA Channel 10 Y Modify Register             */
-#define DMA10_CURR_DESC_PTR     0xFFC00EA0  /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR         0xFFC00EA4  /* DMA Channel 10 Current Address Register      */
-#define DMA10_IRQ_STATUS        0xFFC00EA8  /* DMA Channel 10 Interrupt/Status Register     */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC  /* DMA Channel 10 Peripheral Map Register       */
-#define DMA10_CURR_X_COUNT      0xFFC00EB0  /* DMA Channel 10 Current X Count Register      */
-#define DMA10_CURR_Y_COUNT      0xFFC00EB8  /* DMA Channel 10 Current Y Count Register      */
-
-#define DMA11_NEXT_DESC_PTR     0xFFC00EC0  /* DMA Channel 11 Next Descriptor Pointer Register  */
-#define DMA11_START_ADDR        0xFFC00EC4  /* DMA Channel 11 Start Address Register        */
-#define DMA11_CONFIG            0xFFC00EC8  /* DMA Channel 11 Configuration Register        */
-#define DMA11_X_COUNT           0xFFC00ED0  /* DMA Channel 11 X Count Register              */
-#define DMA11_X_MODIFY          0xFFC00ED4  /* DMA Channel 11 X Modify Register             */
-#define DMA11_Y_COUNT           0xFFC00ED8  /* DMA Channel 11 Y Count Register              */
-#define DMA11_Y_MODIFY          0xFFC00EDC  /* DMA Channel 11 Y Modify Register             */
-#define DMA11_CURR_DESC_PTR     0xFFC00EE0  /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR         0xFFC00EE4  /* DMA Channel 11 Current Address Register      */
-#define DMA11_IRQ_STATUS        0xFFC00EE8  /* DMA Channel 11 Interrupt/Status Register     */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC  /* DMA Channel 11 Peripheral Map Register       */
-#define DMA11_CURR_X_COUNT      0xFFC00EF0  /* DMA Channel 11 Current X Count Register      */
-#define DMA11_CURR_Y_COUNT      0xFFC00EF8  /* DMA Channel 11 Current Y Count Register      */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00  /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR      0xFFC00F04  /* MemDMA Stream 0 Destination Start Address Register       */
-#define MDMA_D0_CONFIG          0xFFC00F08  /* MemDMA Stream 0 Destination Configuration Register       */
-#define MDMA_D0_X_COUNT         0xFFC00F10  /* MemDMA Stream 0 Destination X Count Register             */
-#define MDMA_D0_X_MODIFY        0xFFC00F14  /* MemDMA Stream 0 Destination X Modify Register            */
-#define MDMA_D0_Y_COUNT         0xFFC00F18  /* MemDMA Stream 0 Destination Y Count Register             */
-#define MDMA_D0_Y_MODIFY        0xFFC00F1C  /* MemDMA Stream 0 Destination Y Modify Register            */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20  /* MemDMA Stream 0 Destination Current Descriptor Pointer Register  */
-#define MDMA_D0_CURR_ADDR       0xFFC00F24  /* MemDMA Stream 0 Destination Current Address Register     */
-#define MDMA_D0_IRQ_STATUS      0xFFC00F28  /* MemDMA Stream 0 Destination Interrupt/Status Register    */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C  /* MemDMA Stream 0 Destination Peripheral Map Register      */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30  /* MemDMA Stream 0 Destination Current X Count Register     */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38  /* MemDMA Stream 0 Destination Current Y Count Register     */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40  /* MemDMA Stream 0 Source Next Descriptor Pointer Register  */
-#define MDMA_S0_START_ADDR      0xFFC00F44  /* MemDMA Stream 0 Source Start Address Register            */
-#define MDMA_S0_CONFIG          0xFFC00F48  /* MemDMA Stream 0 Source Configuration Register            */
-#define MDMA_S0_X_COUNT         0xFFC00F50  /* MemDMA Stream 0 Source X Count Register                  */
-#define MDMA_S0_X_MODIFY        0xFFC00F54  /* MemDMA Stream 0 Source X Modify Register                 */
-#define MDMA_S0_Y_COUNT         0xFFC00F58  /* MemDMA Stream 0 Source Y Count Register                  */
-#define MDMA_S0_Y_MODIFY        0xFFC00F5C  /* MemDMA Stream 0 Source Y Modify Register                 */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60  /* MemDMA Stream 0 Source Current Descriptor Pointer Register   */
-#define MDMA_S0_CURR_ADDR       0xFFC00F64  /* MemDMA Stream 0 Source Current Address Register          */
-#define MDMA_S0_IRQ_STATUS      0xFFC00F68  /* MemDMA Stream 0 Source Interrupt/Status Register         */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C  /* MemDMA Stream 0 Source Peripheral Map Register           */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70  /* MemDMA Stream 0 Source Current X Count Register          */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78  /* MemDMA Stream 0 Source Current Y Count Register          */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80  /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR      0xFFC00F84  /* MemDMA Stream 1 Destination Start Address Register       */
-#define MDMA_D1_CONFIG          0xFFC00F88  /* MemDMA Stream 1 Destination Configuration Register       */
-#define MDMA_D1_X_COUNT         0xFFC00F90  /* MemDMA Stream 1 Destination X Count Register             */
-#define MDMA_D1_X_MODIFY        0xFFC00F94  /* MemDMA Stream 1 Destination X Modify Register            */
-#define MDMA_D1_Y_COUNT         0xFFC00F98  /* MemDMA Stream 1 Destination Y Count Register             */
-#define MDMA_D1_Y_MODIFY        0xFFC00F9C  /* MemDMA Stream 1 Destination Y Modify Register            */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0  /* MemDMA Stream 1 Destination Current Descriptor Pointer Register  */
-#define MDMA_D1_CURR_ADDR       0xFFC00FA4  /* MemDMA Stream 1 Destination Current Address Register     */
-#define MDMA_D1_IRQ_STATUS      0xFFC00FA8  /* MemDMA Stream 1 Destination Interrupt/Status Register    */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC  /* MemDMA Stream 1 Destination Peripheral Map Register      */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0  /* MemDMA Stream 1 Destination Current X Count Register     */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8  /* MemDMA Stream 1 Destination Current Y Count Register     */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0  /* MemDMA Stream 1 Source Next Descriptor Pointer Register  */
-#define MDMA_S1_START_ADDR      0xFFC00FC4  /* MemDMA Stream 1 Source Start Address Register            */
-#define MDMA_S1_CONFIG          0xFFC00FC8  /* MemDMA Stream 1 Source Configuration Register            */
-#define MDMA_S1_X_COUNT         0xFFC00FD0  /* MemDMA Stream 1 Source X Count Register                  */
-#define MDMA_S1_X_MODIFY        0xFFC00FD4  /* MemDMA Stream 1 Source X Modify Register                 */
-#define MDMA_S1_Y_COUNT         0xFFC00FD8  /* MemDMA Stream 1 Source Y Count Register                  */
-#define MDMA_S1_Y_MODIFY        0xFFC00FDC  /* MemDMA Stream 1 Source Y Modify Register                 */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0  /* MemDMA Stream 1 Source Current Descriptor Pointer Register   */
-#define MDMA_S1_CURR_ADDR       0xFFC00FE4  /* MemDMA Stream 1 Source Current Address Register          */
-#define MDMA_S1_IRQ_STATUS      0xFFC00FE8  /* MemDMA Stream 1 Source Interrupt/Status Register         */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC  /* MemDMA Stream 1 Source Peripheral Map Register           */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0  /* MemDMA Stream 1 Source Current X Count Register          */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8  /* MemDMA Stream 1 Source Current Y Count Register          */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                  */
-#define PPI_CONTROL             0xFFC01000  /* PPI Control Register                         */
-#define PPI_STATUS              0xFFC01004  /* PPI Status Register                          */
-#define PPI_COUNT               0xFFC01008  /* PPI Transfer Count Register                  */
-#define PPI_DELAY               0xFFC0100C  /* PPI Delay Count Register                     */
-#define PPI_FRAME               0xFFC01010  /* PPI Frame Length Register                    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                   */
-#define TWI_CLKDIV              0xFFC01400  /* Serial Clock Divider Register                */
-#define TWI_CONTROL             0xFFC01404  /* TWI Control Register                         */
-#define TWI_SLAVE_CTL           0xFFC01408  /* Slave Mode Control Register                  */
-#define TWI_SLAVE_STAT          0xFFC0140C  /* Slave Mode Status Register                   */
-#define TWI_SLAVE_ADDR          0xFFC01410  /* Slave Mode Address Register                  */
-#define TWI_MASTER_CTL          0xFFC01414  /* Master Mode Control Register                 */
-#define TWI_MASTER_STAT         0xFFC01418  /* Master Mode Status Register                  */
-#define TWI_MASTER_ADDR         0xFFC0141C  /* Master Mode Address Register                 */
-#define TWI_INT_STAT            0xFFC01420  /* TWI Interrupt Status Register                */
-#define TWI_INT_MASK            0xFFC01424  /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428  /* FIFO Control Register                        */
-#define TWI_FIFO_STAT           0xFFC0142C  /* FIFO Status Register                         */
-#define TWI_XMT_DATA8           0xFFC01480  /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484  /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488  /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C  /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G   (0xFFC01500 - 0xFFC015FF)                                   */
-#define PORTGIO                 0xFFC01500  /* Port G I/O Pin State Specify Register        */
-#define PORTGIO_CLEAR           0xFFC01504  /* Port G I/O Peripheral Interrupt Clear Register   */
-#define PORTGIO_SET             0xFFC01508  /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE          0xFFC0150C  /* Port G I/O Pin State Toggle Register         */
-#define PORTGIO_MASKA           0xFFC01510  /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR     0xFFC01514  /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET       0xFFC01518  /* Port G I/O Mask Enable Interrupt A Register  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C  /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB           0xFFC01520  /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR     0xFFC01524  /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET       0xFFC01528  /* Port G I/O Mask Enable Interrupt B Register  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C  /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR             0xFFC01530  /* Port G I/O Direction Register                */
-#define PORTGIO_POLAR           0xFFC01534  /* Port G I/O Source Polarity Register          */
-#define PORTGIO_EDGE            0xFFC01538  /* Port G I/O Source Sensitivity Register       */
-#define PORTGIO_BOTH            0xFFC0153C  /* Port G I/O Set on BOTH Edges Register        */
-#define PORTGIO_INEN            0xFFC01540  /* Port G I/O Input Enable Register             */
-
-
-/* General Purpose I/O Port H   (0xFFC01700 - 0xFFC017FF)                                   */
-#define PORTHIO                 0xFFC01700  /* Port H I/O Pin State Specify Register        */
-#define PORTHIO_CLEAR           0xFFC01704  /* Port H I/O Peripheral Interrupt Clear Register   */
-#define PORTHIO_SET             0xFFC01708  /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE          0xFFC0170C  /* Port H I/O Pin State Toggle Register         */
-#define PORTHIO_MASKA           0xFFC01710  /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR     0xFFC01714  /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET       0xFFC01718  /* Port H I/O Mask Enable Interrupt A Register  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C  /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB           0xFFC01720  /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR     0xFFC01724  /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET       0xFFC01728  /* Port H I/O Mask Enable Interrupt B Register  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C  /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR             0xFFC01730  /* Port H I/O Direction Register                */
-#define PORTHIO_POLAR           0xFFC01734  /* Port H I/O Source Polarity Register          */
-#define PORTHIO_EDGE            0xFFC01738  /* Port H I/O Source Sensitivity Register       */
-#define PORTHIO_BOTH            0xFFC0173C  /* Port H I/O Set on BOTH Edges Register        */
-#define PORTHIO_INEN            0xFFC01740  /* Port H I/O Input Enable Register             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                   */
-#define UART1_DLL               0xffc02000   /* Divisor Latch Low Byte                      */
-#define UART1_DLH               0xffc02004   /* Divisor Latch High Byte                     */
-#define UART1_GCTL              0xffc02008   /* Global Control Register                     */
-#define UART1_LCR               0xffc0200c   /* Line Control Register                       */
-#define UART1_MCR               0xffc02010   /* Modem Control Register                      */
-#define UART1_LSR               0xffc02014   /* Line Status Register                        */
-#define UART1_MSR               0xffc02018   /* Modem Status Register                       */
-#define UART1_SCR               0xffc0201c   /* Scratch Register                            */
-#define UART1_IER_SET           0xffc02020   /* Interrupt Enable Register Set               */
-#define UART1_IER_CLEAR         0xffc02024   /* Interrupt Enable Register Clear             */
-#define UART1_THR               0xffc02028   /* Transmit Hold Register                      */
-#define UART1_RBR               0xffc0202c   /* Receive Buffer Register                     */
-
-
-/* CAN Controller       (0xFFC02A00 - 0xFFC02FFF)                                           */
-/* For Mailboxes 0-15                                                                       */
-#define CAN_MC1             0xFFC02A00  /* Mailbox config reg 1                             */
-#define CAN_MD1             0xFFC02A04  /* Mailbox direction reg 1                          */
-#define CAN_TRS1            0xFFC02A08  /* Transmit Request Set reg 1                       */
-#define CAN_TRR1            0xFFC02A0C  /* Transmit Request Reset reg 1                     */
-#define CAN_TA1             0xFFC02A10  /* Transmit Acknowledge reg 1                       */
-#define CAN_AA1             0xFFC02A14  /* Transmit Abort Acknowledge reg 1                 */
-#define CAN_RMP1            0xFFC02A18  /* Receive Message Pending reg 1                    */
-#define CAN_RML1            0xFFC02A1C  /* Receive Message Lost reg 1                       */
-#define CAN_MBTIF1          0xFFC02A20  /* Mailbox Transmit Interrupt Flag reg 1            */
-#define CAN_MBRIF1          0xFFC02A24  /* Mailbox Receive  Interrupt Flag reg 1            */
-#define CAN_MBIM1           0xFFC02A28  /* Mailbox Interrupt Mask reg 1                     */
-#define CAN_RFH1            0xFFC02A2C  /* Remote Frame Handling reg 1                      */
-#define CAN_OPSS1           0xFFC02A30  /* Overwrite Protection Single Shot Xmission reg 1  */
-
-/* For Mailboxes 16-31                                                                      */
-#define CAN_MC2             0xFFC02A40  /* Mailbox config reg 2                             */
-#define CAN_MD2             0xFFC02A44  /* Mailbox direction reg 2                          */
-#define CAN_TRS2            0xFFC02A48  /* Transmit Request Set reg 2                       */
-#define CAN_TRR2            0xFFC02A4C  /* Transmit Request Reset reg 2                     */
-#define CAN_TA2             0xFFC02A50  /* Transmit Acknowledge reg 2                       */
-#define CAN_AA2             0xFFC02A54  /* Transmit Abort Acknowledge reg 2                 */
-#define CAN_RMP2            0xFFC02A58  /* Receive Message Pending reg 2                    */
-#define CAN_RML2            0xFFC02A5C  /* Receive Message Lost reg 2                       */
-#define CAN_MBTIF2          0xFFC02A60  /* Mailbox Transmit Interrupt Flag reg 2            */
-#define CAN_MBRIF2          0xFFC02A64  /* Mailbox Receive  Interrupt Flag reg 2            */
-#define CAN_MBIM2           0xFFC02A68  /* Mailbox Interrupt Mask reg 2                     */
-#define CAN_RFH2            0xFFC02A6C  /* Remote Frame Handling reg 2                      */
-#define CAN_OPSS2           0xFFC02A70  /* Overwrite Protection Single Shot Xmission reg 2  */
-
-#define CAN_CLOCK           0xFFC02A80  /* Bit Timing Configuration register 0              */
-#define CAN_TIMING          0xFFC02A84  /* Bit Timing Configuration register 1              */
-
-#define CAN_DEBUG           0xFFC02A88  /* Debug Register                                   */
-/* the following is for backwards compatibility */
-#define CAN_CNF             (CAN_DEBUG )
-
-#define CAN_STATUS          0xFFC02A8C  /* Global Status Register                           */
-#define CAN_CEC             0xFFC02A90  /* Error Counter Register                           */
-#define CAN_GIS             0xFFC02A94  /* Global Interrupt Status Register                 */
-#define CAN_GIM             0xFFC02A98  /* Global Interrupt Mask Register                   */
-#define CAN_GIF             0xFFC02A9C  /* Global Interrupt Flag Register                   */
-#define CAN_CONTROL         0xFFC02AA0  /* Master Control Register                          */
-#define CAN_INTR            0xFFC02AA4  /* Interrupt Pending Register                       */
-#define CAN_MBTD            0xFFC02AAC  /* Mailbox Temporary Disable Feature                */
-#define CAN_EWR             0xFFC02AB0  /* Programmable Warning Level                       */
-#define CAN_ESR             0xFFC02AB4  /* Error Status Register                            */
-#define CAN_UCCNT           0xFFC02AC4  /* Universal Counter                                */
-#define CAN_UCRC            0xFFC02AC8  /* Universal Counter Reload/Capture Register    */
-#define CAN_UCCNF           0xFFC02ACC  /* Universal Counter Configuration Register         */
-
-/* Mailbox Acceptance Masks                                                 */
-#define CAN_AM00L           0xFFC02B00  /* Mailbox 0 Low Acceptance Mask    */
-#define CAN_AM00H           0xFFC02B04  /* Mailbox 0 High Acceptance Mask   */
-#define CAN_AM01L           0xFFC02B08  /* Mailbox 1 Low Acceptance Mask    */
-#define CAN_AM01H           0xFFC02B0C  /* Mailbox 1 High Acceptance Mask   */
-#define CAN_AM02L           0xFFC02B10  /* Mailbox 2 Low Acceptance Mask    */
-#define CAN_AM02H           0xFFC02B14  /* Mailbox 2 High Acceptance Mask   */
-#define CAN_AM03L           0xFFC02B18  /* Mailbox 3 Low Acceptance Mask    */
-#define CAN_AM03H           0xFFC02B1C  /* Mailbox 3 High Acceptance Mask   */
-#define CAN_AM04L           0xFFC02B20  /* Mailbox 4 Low Acceptance Mask    */
-#define CAN_AM04H           0xFFC02B24  /* Mailbox 4 High Acceptance Mask   */
-#define CAN_AM05L           0xFFC02B28  /* Mailbox 5 Low Acceptance Mask    */
-#define CAN_AM05H           0xFFC02B2C  /* Mailbox 5 High Acceptance Mask   */
-#define CAN_AM06L           0xFFC02B30  /* Mailbox 6 Low Acceptance Mask    */
-#define CAN_AM06H           0xFFC02B34  /* Mailbox 6 High Acceptance Mask   */
-#define CAN_AM07L           0xFFC02B38  /* Mailbox 7 Low Acceptance Mask    */
-#define CAN_AM07H           0xFFC02B3C  /* Mailbox 7 High Acceptance Mask   */
-#define CAN_AM08L           0xFFC02B40  /* Mailbox 8 Low Acceptance Mask    */
-#define CAN_AM08H           0xFFC02B44  /* Mailbox 8 High Acceptance Mask   */
-#define CAN_AM09L           0xFFC02B48  /* Mailbox 9 Low Acceptance Mask    */
-#define CAN_AM09H           0xFFC02B4C  /* Mailbox 9 High Acceptance Mask   */
-#define CAN_AM10L           0xFFC02B50  /* Mailbox 10 Low Acceptance Mask   */
-#define CAN_AM10H           0xFFC02B54  /* Mailbox 10 High Acceptance Mask  */
-#define CAN_AM11L           0xFFC02B58  /* Mailbox 11 Low Acceptance Mask   */
-#define CAN_AM11H           0xFFC02B5C  /* Mailbox 11 High Acceptance Mask  */
-#define CAN_AM12L           0xFFC02B60  /* Mailbox 12 Low Acceptance Mask   */
-#define CAN_AM12H           0xFFC02B64  /* Mailbox 12 High Acceptance Mask  */
-#define CAN_AM13L           0xFFC02B68  /* Mailbox 13 Low Acceptance Mask   */
-#define CAN_AM13H           0xFFC02B6C  /* Mailbox 13 High Acceptance Mask  */
-#define CAN_AM14L           0xFFC02B70  /* Mailbox 14 Low Acceptance Mask   */
-#define CAN_AM14H           0xFFC02B74  /* Mailbox 14 High Acceptance Mask  */
-#define CAN_AM15L           0xFFC02B78  /* Mailbox 15 Low Acceptance Mask   */
-#define CAN_AM15H           0xFFC02B7C  /* Mailbox 15 High Acceptance Mask  */
-
-#define CAN_AM16L           0xFFC02B80  /* Mailbox 16 Low Acceptance Mask   */
-#define CAN_AM16H           0xFFC02B84  /* Mailbox 16 High Acceptance Mask  */
-#define CAN_AM17L           0xFFC02B88  /* Mailbox 17 Low Acceptance Mask   */
-#define CAN_AM17H           0xFFC02B8C  /* Mailbox 17 High Acceptance Mask  */
-#define CAN_AM18L           0xFFC02B90  /* Mailbox 18 Low Acceptance Mask   */
-#define CAN_AM18H           0xFFC02B94  /* Mailbox 18 High Acceptance Mask  */
-#define CAN_AM19L           0xFFC02B98  /* Mailbox 19 Low Acceptance Mask   */
-#define CAN_AM19H           0xFFC02B9C  /* Mailbox 19 High Acceptance Mask  */
-#define CAN_AM20L           0xFFC02BA0  /* Mailbox 20 Low Acceptance Mask   */
-#define CAN_AM20H           0xFFC02BA4  /* Mailbox 20 High Acceptance Mask  */
-#define CAN_AM21L           0xFFC02BA8  /* Mailbox 21 Low Acceptance Mask   */
-#define CAN_AM21H           0xFFC02BAC  /* Mailbox 21 High Acceptance Mask  */
-#define CAN_AM22L           0xFFC02BB0  /* Mailbox 22 Low Acceptance Mask   */
-#define CAN_AM22H           0xFFC02BB4  /* Mailbox 22 High Acceptance Mask  */
-#define CAN_AM23L           0xFFC02BB8  /* Mailbox 23 Low Acceptance Mask   */
-#define CAN_AM23H           0xFFC02BBC  /* Mailbox 23 High Acceptance Mask  */
-#define CAN_AM24L           0xFFC02BC0  /* Mailbox 24 Low Acceptance Mask   */
-#define CAN_AM24H           0xFFC02BC4  /* Mailbox 24 High Acceptance Mask  */
-#define CAN_AM25L           0xFFC02BC8  /* Mailbox 25 Low Acceptance Mask   */
-#define CAN_AM25H           0xFFC02BCC  /* Mailbox 25 High Acceptance Mask  */
-#define CAN_AM26L           0xFFC02BD0  /* Mailbox 26 Low Acceptance Mask   */
-#define CAN_AM26H           0xFFC02BD4  /* Mailbox 26 High Acceptance Mask  */
-#define CAN_AM27L           0xFFC02BD8  /* Mailbox 27 Low Acceptance Mask   */
-#define CAN_AM27H           0xFFC02BDC  /* Mailbox 27 High Acceptance Mask  */
-#define CAN_AM28L           0xFFC02BE0  /* Mailbox 28 Low Acceptance Mask   */
-#define CAN_AM28H           0xFFC02BE4  /* Mailbox 28 High Acceptance Mask  */
-#define CAN_AM29L           0xFFC02BE8  /* Mailbox 29 Low Acceptance Mask   */
-#define CAN_AM29H           0xFFC02BEC  /* Mailbox 29 High Acceptance Mask  */
-#define CAN_AM30L           0xFFC02BF0  /* Mailbox 30 Low Acceptance Mask   */
-#define CAN_AM30H           0xFFC02BF4  /* Mailbox 30 High Acceptance Mask  */
-#define CAN_AM31L           0xFFC02BF8  /* Mailbox 31 Low Acceptance Mask   */
-#define CAN_AM31H           0xFFC02BFC  /* Mailbox 31 High Acceptance Mask  */
-
-/* CAN Acceptance Mask Macros               */
-#define CAN_AM_L(x)         (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)         (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers                                                                */
-#define CAN_MB00_DATA0      0xFFC02C00  /* Mailbox 0 Data Word 0 [15:0] Register    */
-#define CAN_MB00_DATA1      0xFFC02C04  /* Mailbox 0 Data Word 1 [31:16] Register   */
-#define CAN_MB00_DATA2      0xFFC02C08  /* Mailbox 0 Data Word 2 [47:32] Register   */
-#define CAN_MB00_DATA3      0xFFC02C0C  /* Mailbox 0 Data Word 3 [63:48] Register   */
-#define CAN_MB00_LENGTH     0xFFC02C10  /* Mailbox 0 Data Length Code Register      */
-#define CAN_MB00_TIMESTAMP  0xFFC02C14  /* Mailbox 0 Time Stamp Value Register      */
-#define CAN_MB00_ID0        0xFFC02C18  /* Mailbox 0 Identifier Low Register        */
-#define CAN_MB00_ID1        0xFFC02C1C  /* Mailbox 0 Identifier High Register       */
-
-#define CAN_MB01_DATA0      0xFFC02C20  /* Mailbox 1 Data Word 0 [15:0] Register    */
-#define CAN_MB01_DATA1      0xFFC02C24  /* Mailbox 1 Data Word 1 [31:16] Register   */
-#define CAN_MB01_DATA2      0xFFC02C28  /* Mailbox 1 Data Word 2 [47:32] Register   */
-#define CAN_MB01_DATA3      0xFFC02C2C  /* Mailbox 1 Data Word 3 [63:48] Register   */
-#define CAN_MB01_LENGTH     0xFFC02C30  /* Mailbox 1 Data Length Code Register      */
-#define CAN_MB01_TIMESTAMP  0xFFC02C34  /* Mailbox 1 Time Stamp Value Register      */
-#define CAN_MB01_ID0        0xFFC02C38  /* Mailbox 1 Identifier Low Register        */
-#define CAN_MB01_ID1        0xFFC02C3C  /* Mailbox 1 Identifier High Register       */
-
-#define CAN_MB02_DATA0      0xFFC02C40  /* Mailbox 2 Data Word 0 [15:0] Register    */
-#define CAN_MB02_DATA1      0xFFC02C44  /* Mailbox 2 Data Word 1 [31:16] Register   */
-#define CAN_MB02_DATA2      0xFFC02C48  /* Mailbox 2 Data Word 2 [47:32] Register   */
-#define CAN_MB02_DATA3      0xFFC02C4C  /* Mailbox 2 Data Word 3 [63:48] Register   */
-#define CAN_MB02_LENGTH     0xFFC02C50  /* Mailbox 2 Data Length Code Register      */
-#define CAN_MB02_TIMESTAMP  0xFFC02C54  /* Mailbox 2 Time Stamp Value Register      */
-#define CAN_MB02_ID0        0xFFC02C58  /* Mailbox 2 Identifier Low Register        */
-#define CAN_MB02_ID1        0xFFC02C5C  /* Mailbox 2 Identifier High Register       */
-
-#define CAN_MB03_DATA0      0xFFC02C60  /* Mailbox 3 Data Word 0 [15:0] Register    */
-#define CAN_MB03_DATA1      0xFFC02C64  /* Mailbox 3 Data Word 1 [31:16] Register   */
-#define CAN_MB03_DATA2      0xFFC02C68  /* Mailbox 3 Data Word 2 [47:32] Register   */
-#define CAN_MB03_DATA3      0xFFC02C6C  /* Mailbox 3 Data Word 3 [63:48] Register   */
-#define CAN_MB03_LENGTH     0xFFC02C70  /* Mailbox 3 Data Length Code Register      */
-#define CAN_MB03_TIMESTAMP  0xFFC02C74  /* Mailbox 3 Time Stamp Value Register      */
-#define CAN_MB03_ID0        0xFFC02C78  /* Mailbox 3 Identifier Low Register        */
-#define CAN_MB03_ID1        0xFFC02C7C  /* Mailbox 3 Identifier High Register       */
-
-#define CAN_MB04_DATA0      0xFFC02C80  /* Mailbox 4 Data Word 0 [15:0] Register    */
-#define CAN_MB04_DATA1      0xFFC02C84  /* Mailbox 4 Data Word 1 [31:16] Register   */
-#define CAN_MB04_DATA2      0xFFC02C88  /* Mailbox 4 Data Word 2 [47:32] Register   */
-#define CAN_MB04_DATA3      0xFFC02C8C  /* Mailbox 4 Data Word 3 [63:48] Register   */
-#define CAN_MB04_LENGTH     0xFFC02C90  /* Mailbox 4 Data Length Code Register      */
-#define CAN_MB04_TIMESTAMP  0xFFC02C94  /* Mailbox 4 Time Stamp Value Register      */
-#define CAN_MB04_ID0        0xFFC02C98  /* Mailbox 4 Identifier Low Register        */
-#define CAN_MB04_ID1        0xFFC02C9C  /* Mailbox 4 Identifier High Register       */
-
-#define CAN_MB05_DATA0      0xFFC02CA0  /* Mailbox 5 Data Word 0 [15:0] Register    */
-#define CAN_MB05_DATA1      0xFFC02CA4  /* Mailbox 5 Data Word 1 [31:16] Register   */
-#define CAN_MB05_DATA2      0xFFC02CA8  /* Mailbox 5 Data Word 2 [47:32] Register   */
-#define CAN_MB05_DATA3      0xFFC02CAC  /* Mailbox 5 Data Word 3 [63:48] Register   */
-#define CAN_MB05_LENGTH     0xFFC02CB0  /* Mailbox 5 Data Length Code Register      */
-#define CAN_MB05_TIMESTAMP  0xFFC02CB4  /* Mailbox 5 Time Stamp Value Register      */
-#define CAN_MB05_ID0        0xFFC02CB8  /* Mailbox 5 Identifier Low Register        */
-#define CAN_MB05_ID1        0xFFC02CBC  /* Mailbox 5 Identifier High Register       */
-
-#define CAN_MB06_DATA0      0xFFC02CC0  /* Mailbox 6 Data Word 0 [15:0] Register    */
-#define CAN_MB06_DATA1      0xFFC02CC4  /* Mailbox 6 Data Word 1 [31:16] Register   */
-#define CAN_MB06_DATA2      0xFFC02CC8  /* Mailbox 6 Data Word 2 [47:32] Register   */
-#define CAN_MB06_DATA3      0xFFC02CCC  /* Mailbox 6 Data Word 3 [63:48] Register   */
-#define CAN_MB06_LENGTH     0xFFC02CD0  /* Mailbox 6 Data Length Code Register      */
-#define CAN_MB06_TIMESTAMP  0xFFC02CD4  /* Mailbox 6 Time Stamp Value Register      */
-#define CAN_MB06_ID0        0xFFC02CD8  /* Mailbox 6 Identifier Low Register        */
-#define CAN_MB06_ID1        0xFFC02CDC  /* Mailbox 6 Identifier High Register       */
-
-#define CAN_MB07_DATA0      0xFFC02CE0  /* Mailbox 7 Data Word 0 [15:0] Register    */
-#define CAN_MB07_DATA1      0xFFC02CE4  /* Mailbox 7 Data Word 1 [31:16] Register   */
-#define CAN_MB07_DATA2      0xFFC02CE8  /* Mailbox 7 Data Word 2 [47:32] Register   */
-#define CAN_MB07_DATA3      0xFFC02CEC  /* Mailbox 7 Data Word 3 [63:48] Register   */
-#define CAN_MB07_LENGTH     0xFFC02CF0  /* Mailbox 7 Data Length Code Register      */
-#define CAN_MB07_TIMESTAMP  0xFFC02CF4  /* Mailbox 7 Time Stamp Value Register      */
-#define CAN_MB07_ID0        0xFFC02CF8  /* Mailbox 7 Identifier Low Register        */
-#define CAN_MB07_ID1        0xFFC02CFC  /* Mailbox 7 Identifier High Register       */
-
-#define CAN_MB08_DATA0      0xFFC02D00  /* Mailbox 8 Data Word 0 [15:0] Register    */
-#define CAN_MB08_DATA1      0xFFC02D04  /* Mailbox 8 Data Word 1 [31:16] Register   */
-#define CAN_MB08_DATA2      0xFFC02D08  /* Mailbox 8 Data Word 2 [47:32] Register   */
-#define CAN_MB08_DATA3      0xFFC02D0C  /* Mailbox 8 Data Word 3 [63:48] Register   */
-#define CAN_MB08_LENGTH     0xFFC02D10  /* Mailbox 8 Data Length Code Register      */
-#define CAN_MB08_TIMESTAMP  0xFFC02D14  /* Mailbox 8 Time Stamp Value Register      */
-#define CAN_MB08_ID0        0xFFC02D18  /* Mailbox 8 Identifier Low Register        */
-#define CAN_MB08_ID1        0xFFC02D1C  /* Mailbox 8 Identifier High Register       */
-
-#define CAN_MB09_DATA0      0xFFC02D20  /* Mailbox 9 Data Word 0 [15:0] Register    */
-#define CAN_MB09_DATA1      0xFFC02D24  /* Mailbox 9 Data Word 1 [31:16] Register   */
-#define CAN_MB09_DATA2      0xFFC02D28  /* Mailbox 9 Data Word 2 [47:32] Register   */
-#define CAN_MB09_DATA3      0xFFC02D2C  /* Mailbox 9 Data Word 3 [63:48] Register   */
-#define CAN_MB09_LENGTH     0xFFC02D30  /* Mailbox 9 Data Length Code Register      */
-#define CAN_MB09_TIMESTAMP  0xFFC02D34  /* Mailbox 9 Time Stamp Value Register      */
-#define CAN_MB09_ID0        0xFFC02D38  /* Mailbox 9 Identifier Low Register        */
-#define CAN_MB09_ID1        0xFFC02D3C  /* Mailbox 9 Identifier High Register       */
-
-#define CAN_MB10_DATA0      0xFFC02D40  /* Mailbox 10 Data Word 0 [15:0] Register   */
-#define CAN_MB10_DATA1      0xFFC02D44  /* Mailbox 10 Data Word 1 [31:16] Register  */
-#define CAN_MB10_DATA2      0xFFC02D48  /* Mailbox 10 Data Word 2 [47:32] Register  */
-#define CAN_MB10_DATA3      0xFFC02D4C  /* Mailbox 10 Data Word 3 [63:48] Register  */
-#define CAN_MB10_LENGTH     0xFFC02D50  /* Mailbox 10 Data Length Code Register     */
-#define CAN_MB10_TIMESTAMP  0xFFC02D54  /* Mailbox 10 Time Stamp Value Register     */
-#define CAN_MB10_ID0        0xFFC02D58  /* Mailbox 10 Identifier Low Register       */
-#define CAN_MB10_ID1        0xFFC02D5C  /* Mailbox 10 Identifier High Register      */
-
-#define CAN_MB11_DATA0      0xFFC02D60  /* Mailbox 11 Data Word 0 [15:0] Register   */
-#define CAN_MB11_DATA1      0xFFC02D64  /* Mailbox 11 Data Word 1 [31:16] Register  */
-#define CAN_MB11_DATA2      0xFFC02D68  /* Mailbox 11 Data Word 2 [47:32] Register  */
-#define CAN_MB11_DATA3      0xFFC02D6C  /* Mailbox 11 Data Word 3 [63:48] Register  */
-#define CAN_MB11_LENGTH     0xFFC02D70  /* Mailbox 11 Data Length Code Register     */
-#define CAN_MB11_TIMESTAMP  0xFFC02D74  /* Mailbox 11 Time Stamp Value Register     */
-#define CAN_MB11_ID0        0xFFC02D78  /* Mailbox 11 Identifier Low Register       */
-#define CAN_MB11_ID1        0xFFC02D7C  /* Mailbox 11 Identifier High Register      */
-
-#define CAN_MB12_DATA0      0xFFC02D80  /* Mailbox 12 Data Word 0 [15:0] Register   */
-#define CAN_MB12_DATA1      0xFFC02D84  /* Mailbox 12 Data Word 1 [31:16] Register  */
-#define CAN_MB12_DATA2      0xFFC02D88  /* Mailbox 12 Data Word 2 [47:32] Register  */
-#define CAN_MB12_DATA3      0xFFC02D8C  /* Mailbox 12 Data Word 3 [63:48] Register  */
-#define CAN_MB12_LENGTH     0xFFC02D90  /* Mailbox 12 Data Length Code Register     */
-#define CAN_MB12_TIMESTAMP  0xFFC02D94  /* Mailbox 12 Time Stamp Value Register     */
-#define CAN_MB12_ID0        0xFFC02D98  /* Mailbox 12 Identifier Low Register       */
-#define CAN_MB12_ID1        0xFFC02D9C  /* Mailbox 12 Identifier High Register      */
-
-#define CAN_MB13_DATA0      0xFFC02DA0  /* Mailbox 13 Data Word 0 [15:0] Register   */
-#define CAN_MB13_DATA1      0xFFC02DA4  /* Mailbox 13 Data Word 1 [31:16] Register  */
-#define CAN_MB13_DATA2      0xFFC02DA8  /* Mailbox 13 Data Word 2 [47:32] Register  */
-#define CAN_MB13_DATA3      0xFFC02DAC  /* Mailbox 13 Data Word 3 [63:48] Register  */
-#define CAN_MB13_LENGTH     0xFFC02DB0  /* Mailbox 13 Data Length Code Register     */
-#define CAN_MB13_TIMESTAMP  0xFFC02DB4  /* Mailbox 13 Time Stamp Value Register     */
-#define CAN_MB13_ID0        0xFFC02DB8  /* Mailbox 13 Identifier Low Register       */
-#define CAN_MB13_ID1        0xFFC02DBC  /* Mailbox 13 Identifier High Register      */
-
-#define CAN_MB14_DATA0      0xFFC02DC0  /* Mailbox 14 Data Word 0 [15:0] Register   */
-#define CAN_MB14_DATA1      0xFFC02DC4  /* Mailbox 14 Data Word 1 [31:16] Register  */
-#define CAN_MB14_DATA2      0xFFC02DC8  /* Mailbox 14 Data Word 2 [47:32] Register  */
-#define CAN_MB14_DATA3      0xFFC02DCC  /* Mailbox 14 Data Word 3 [63:48] Register  */
-#define CAN_MB14_LENGTH     0xFFC02DD0  /* Mailbox 14 Data Length Code Register     */
-#define CAN_MB14_TIMESTAMP  0xFFC02DD4  /* Mailbox 14 Time Stamp Value Register     */
-#define CAN_MB14_ID0        0xFFC02DD8  /* Mailbox 14 Identifier Low Register       */
-#define CAN_MB14_ID1        0xFFC02DDC  /* Mailbox 14 Identifier High Register      */
-
-#define CAN_MB15_DATA0      0xFFC02DE0  /* Mailbox 15 Data Word 0 [15:0] Register   */
-#define CAN_MB15_DATA1      0xFFC02DE4  /* Mailbox 15 Data Word 1 [31:16] Register  */
-#define CAN_MB15_DATA2      0xFFC02DE8  /* Mailbox 15 Data Word 2 [47:32] Register  */
-#define CAN_MB15_DATA3      0xFFC02DEC  /* Mailbox 15 Data Word 3 [63:48] Register  */
-#define CAN_MB15_LENGTH     0xFFC02DF0  /* Mailbox 15 Data Length Code Register     */
-#define CAN_MB15_TIMESTAMP  0xFFC02DF4  /* Mailbox 15 Time Stamp Value Register     */
-#define CAN_MB15_ID0        0xFFC02DF8  /* Mailbox 15 Identifier Low Register       */
-#define CAN_MB15_ID1        0xFFC02DFC  /* Mailbox 15 Identifier High Register      */
-
-#define CAN_MB16_DATA0      0xFFC02E00  /* Mailbox 16 Data Word 0 [15:0] Register   */
-#define CAN_MB16_DATA1      0xFFC02E04  /* Mailbox 16 Data Word 1 [31:16] Register  */
-#define CAN_MB16_DATA2      0xFFC02E08  /* Mailbox 16 Data Word 2 [47:32] Register  */
-#define CAN_MB16_DATA3      0xFFC02E0C  /* Mailbox 16 Data Word 3 [63:48] Register  */
-#define CAN_MB16_LENGTH     0xFFC02E10  /* Mailbox 16 Data Length Code Register     */
-#define CAN_MB16_TIMESTAMP  0xFFC02E14  /* Mailbox 16 Time Stamp Value Register     */
-#define CAN_MB16_ID0        0xFFC02E18  /* Mailbox 16 Identifier Low Register       */
-#define CAN_MB16_ID1        0xFFC02E1C  /* Mailbox 16 Identifier High Register      */
-
-#define CAN_MB17_DATA0      0xFFC02E20  /* Mailbox 17 Data Word 0 [15:0] Register   */
-#define CAN_MB17_DATA1      0xFFC02E24  /* Mailbox 17 Data Word 1 [31:16] Register  */
-#define CAN_MB17_DATA2      0xFFC02E28  /* Mailbox 17 Data Word 2 [47:32] Register  */
-#define CAN_MB17_DATA3      0xFFC02E2C  /* Mailbox 17 Data Word 3 [63:48] Register  */
-#define CAN_MB17_LENGTH     0xFFC02E30  /* Mailbox 17 Data Length Code Register     */
-#define CAN_MB17_TIMESTAMP  0xFFC02E34  /* Mailbox 17 Time Stamp Value Register     */
-#define CAN_MB17_ID0        0xFFC02E38  /* Mailbox 17 Identifier Low Register       */
-#define CAN_MB17_ID1        0xFFC02E3C  /* Mailbox 17 Identifier High Register      */
-
-#define CAN_MB18_DATA0      0xFFC02E40  /* Mailbox 18 Data Word 0 [15:0] Register   */
-#define CAN_MB18_DATA1      0xFFC02E44  /* Mailbox 18 Data Word 1 [31:16] Register  */
-#define CAN_MB18_DATA2      0xFFC02E48  /* Mailbox 18 Data Word 2 [47:32] Register  */
-#define CAN_MB18_DATA3      0xFFC02E4C  /* Mailbox 18 Data Word 3 [63:48] Register  */
-#define CAN_MB18_LENGTH     0xFFC02E50  /* Mailbox 18 Data Length Code Register     */
-#define CAN_MB18_TIMESTAMP  0xFFC02E54  /* Mailbox 18 Time Stamp Value Register     */
-#define CAN_MB18_ID0        0xFFC02E58  /* Mailbox 18 Identifier Low Register       */
-#define CAN_MB18_ID1        0xFFC02E5C  /* Mailbox 18 Identifier High Register      */
-
-#define CAN_MB19_DATA0      0xFFC02E60  /* Mailbox 19 Data Word 0 [15:0] Register   */
-#define CAN_MB19_DATA1      0xFFC02E64  /* Mailbox 19 Data Word 1 [31:16] Register  */
-#define CAN_MB19_DATA2      0xFFC02E68  /* Mailbox 19 Data Word 2 [47:32] Register  */
-#define CAN_MB19_DATA3      0xFFC02E6C  /* Mailbox 19 Data Word 3 [63:48] Register  */
-#define CAN_MB19_LENGTH     0xFFC02E70  /* Mailbox 19 Data Length Code Register     */
-#define CAN_MB19_TIMESTAMP  0xFFC02E74  /* Mailbox 19 Time Stamp Value Register     */
-#define CAN_MB19_ID0        0xFFC02E78  /* Mailbox 19 Identifier Low Register       */
-#define CAN_MB19_ID1        0xFFC02E7C  /* Mailbox 19 Identifier High Register      */
-
-#define CAN_MB20_DATA0      0xFFC02E80  /* Mailbox 20 Data Word 0 [15:0] Register   */
-#define CAN_MB20_DATA1      0xFFC02E84  /* Mailbox 20 Data Word 1 [31:16] Register  */
-#define CAN_MB20_DATA2      0xFFC02E88  /* Mailbox 20 Data Word 2 [47:32] Register  */
-#define CAN_MB20_DATA3      0xFFC02E8C  /* Mailbox 20 Data Word 3 [63:48] Register  */
-#define CAN_MB20_LENGTH     0xFFC02E90  /* Mailbox 20 Data Length Code Register     */
-#define CAN_MB20_TIMESTAMP  0xFFC02E94  /* Mailbox 20 Time Stamp Value Register     */
-#define CAN_MB20_ID0        0xFFC02E98  /* Mailbox 20 Identifier Low Register       */
-#define CAN_MB20_ID1        0xFFC02E9C  /* Mailbox 20 Identifier High Register      */
-
-#define CAN_MB21_DATA0      0xFFC02EA0  /* Mailbox 21 Data Word 0 [15:0] Register   */
-#define CAN_MB21_DATA1      0xFFC02EA4  /* Mailbox 21 Data Word 1 [31:16] Register  */
-#define CAN_MB21_DATA2      0xFFC02EA8  /* Mailbox 21 Data Word 2 [47:32] Register  */
-#define CAN_MB21_DATA3      0xFFC02EAC  /* Mailbox 21 Data Word 3 [63:48] Register  */
-#define CAN_MB21_LENGTH     0xFFC02EB0  /* Mailbox 21 Data Length Code Register     */
-#define CAN_MB21_TIMESTAMP  0xFFC02EB4  /* Mailbox 21 Time Stamp Value Register     */
-#define CAN_MB21_ID0        0xFFC02EB8  /* Mailbox 21 Identifier Low Register       */
-#define CAN_MB21_ID1        0xFFC02EBC  /* Mailbox 21 Identifier High Register      */
-
-#define CAN_MB22_DATA0      0xFFC02EC0  /* Mailbox 22 Data Word 0 [15:0] Register   */
-#define CAN_MB22_DATA1      0xFFC02EC4  /* Mailbox 22 Data Word 1 [31:16] Register  */
-#define CAN_MB22_DATA2      0xFFC02EC8  /* Mailbox 22 Data Word 2 [47:32] Register  */
-#define CAN_MB22_DATA3      0xFFC02ECC  /* Mailbox 22 Data Word 3 [63:48] Register  */
-#define CAN_MB22_LENGTH     0xFFC02ED0  /* Mailbox 22 Data Length Code Register     */
-#define CAN_MB22_TIMESTAMP  0xFFC02ED4  /* Mailbox 22 Time Stamp Value Register     */
-#define CAN_MB22_ID0        0xFFC02ED8  /* Mailbox 22 Identifier Low Register       */
-#define CAN_MB22_ID1        0xFFC02EDC  /* Mailbox 22 Identifier High Register      */
-
-#define CAN_MB23_DATA0      0xFFC02EE0  /* Mailbox 23 Data Word 0 [15:0] Register   */
-#define CAN_MB23_DATA1      0xFFC02EE4  /* Mailbox 23 Data Word 1 [31:16] Register  */
-#define CAN_MB23_DATA2      0xFFC02EE8  /* Mailbox 23 Data Word 2 [47:32] Register  */
-#define CAN_MB23_DATA3      0xFFC02EEC  /* Mailbox 23 Data Word 3 [63:48] Register  */
-#define CAN_MB23_LENGTH     0xFFC02EF0  /* Mailbox 23 Data Length Code Register     */
-#define CAN_MB23_TIMESTAMP  0xFFC02EF4  /* Mailbox 23 Time Stamp Value Register     */
-#define CAN_MB23_ID0        0xFFC02EF8  /* Mailbox 23 Identifier Low Register       */
-#define CAN_MB23_ID1        0xFFC02EFC  /* Mailbox 23 Identifier High Register      */
-
-#define CAN_MB24_DATA0      0xFFC02F00  /* Mailbox 24 Data Word 0 [15:0] Register   */
-#define CAN_MB24_DATA1      0xFFC02F04  /* Mailbox 24 Data Word 1 [31:16] Register  */
-#define CAN_MB24_DATA2      0xFFC02F08  /* Mailbox 24 Data Word 2 [47:32] Register  */
-#define CAN_MB24_DATA3      0xFFC02F0C  /* Mailbox 24 Data Word 3 [63:48] Register  */
-#define CAN_MB24_LENGTH     0xFFC02F10  /* Mailbox 24 Data Length Code Register     */
-#define CAN_MB24_TIMESTAMP  0xFFC02F14  /* Mailbox 24 Time Stamp Value Register     */
-#define CAN_MB24_ID0        0xFFC02F18  /* Mailbox 24 Identifier Low Register       */
-#define CAN_MB24_ID1        0xFFC02F1C  /* Mailbox 24 Identifier High Register      */
-
-#define CAN_MB25_DATA0      0xFFC02F20  /* Mailbox 25 Data Word 0 [15:0] Register   */
-#define CAN_MB25_DATA1      0xFFC02F24  /* Mailbox 25 Data Word 1 [31:16] Register  */
-#define CAN_MB25_DATA2      0xFFC02F28  /* Mailbox 25 Data Word 2 [47:32] Register  */
-#define CAN_MB25_DATA3      0xFFC02F2C  /* Mailbox 25 Data Word 3 [63:48] Register  */
-#define CAN_MB25_LENGTH     0xFFC02F30  /* Mailbox 25 Data Length Code Register     */
-#define CAN_MB25_TIMESTAMP  0xFFC02F34  /* Mailbox 25 Time Stamp Value Register     */
-#define CAN_MB25_ID0        0xFFC02F38  /* Mailbox 25 Identifier Low Register       */
-#define CAN_MB25_ID1        0xFFC02F3C  /* Mailbox 25 Identifier High Register      */
-
-#define CAN_MB26_DATA0      0xFFC02F40  /* Mailbox 26 Data Word 0 [15:0] Register   */
-#define CAN_MB26_DATA1      0xFFC02F44  /* Mailbox 26 Data Word 1 [31:16] Register  */
-#define CAN_MB26_DATA2      0xFFC02F48  /* Mailbox 26 Data Word 2 [47:32] Register  */
-#define CAN_MB26_DATA3      0xFFC02F4C  /* Mailbox 26 Data Word 3 [63:48] Register  */
-#define CAN_MB26_LENGTH     0xFFC02F50  /* Mailbox 26 Data Length Code Register     */
-#define CAN_MB26_TIMESTAMP  0xFFC02F54  /* Mailbox 26 Time Stamp Value Register     */
-#define CAN_MB26_ID0        0xFFC02F58  /* Mailbox 26 Identifier Low Register       */
-#define CAN_MB26_ID1        0xFFC02F5C  /* Mailbox 26 Identifier High Register      */
-
-#define CAN_MB27_DATA0      0xFFC02F60  /* Mailbox 27 Data Word 0 [15:0] Register   */
-#define CAN_MB27_DATA1      0xFFC02F64  /* Mailbox 27 Data Word 1 [31:16] Register  */
-#define CAN_MB27_DATA2      0xFFC02F68  /* Mailbox 27 Data Word 2 [47:32] Register  */
-#define CAN_MB27_DATA3      0xFFC02F6C  /* Mailbox 27 Data Word 3 [63:48] Register  */
-#define CAN_MB27_LENGTH     0xFFC02F70  /* Mailbox 27 Data Length Code Register     */
-#define CAN_MB27_TIMESTAMP  0xFFC02F74  /* Mailbox 27 Time Stamp Value Register     */
-#define CAN_MB27_ID0        0xFFC02F78  /* Mailbox 27 Identifier Low Register       */
-#define CAN_MB27_ID1        0xFFC02F7C  /* Mailbox 27 Identifier High Register      */
-
-#define CAN_MB28_DATA0      0xFFC02F80  /* Mailbox 28 Data Word 0 [15:0] Register   */
-#define CAN_MB28_DATA1      0xFFC02F84  /* Mailbox 28 Data Word 1 [31:16] Register  */
-#define CAN_MB28_DATA2      0xFFC02F88  /* Mailbox 28 Data Word 2 [47:32] Register  */
-#define CAN_MB28_DATA3      0xFFC02F8C  /* Mailbox 28 Data Word 3 [63:48] Register  */
-#define CAN_MB28_LENGTH     0xFFC02F90  /* Mailbox 28 Data Length Code Register     */
-#define CAN_MB28_TIMESTAMP  0xFFC02F94  /* Mailbox 28 Time Stamp Value Register     */
-#define CAN_MB28_ID0        0xFFC02F98  /* Mailbox 28 Identifier Low Register       */
-#define CAN_MB28_ID1        0xFFC02F9C  /* Mailbox 28 Identifier High Register      */
-
-#define CAN_MB29_DATA0      0xFFC02FA0  /* Mailbox 29 Data Word 0 [15:0] Register   */
-#define CAN_MB29_DATA1      0xFFC02FA4  /* Mailbox 29 Data Word 1 [31:16] Register  */
-#define CAN_MB29_DATA2      0xFFC02FA8  /* Mailbox 29 Data Word 2 [47:32] Register  */
-#define CAN_MB29_DATA3      0xFFC02FAC  /* Mailbox 29 Data Word 3 [63:48] Register  */
-#define CAN_MB29_LENGTH     0xFFC02FB0  /* Mailbox 29 Data Length Code Register     */
-#define CAN_MB29_TIMESTAMP  0xFFC02FB4  /* Mailbox 29 Time Stamp Value Register     */
-#define CAN_MB29_ID0        0xFFC02FB8  /* Mailbox 29 Identifier Low Register       */
-#define CAN_MB29_ID1        0xFFC02FBC  /* Mailbox 29 Identifier High Register      */
-
-#define CAN_MB30_DATA0      0xFFC02FC0  /* Mailbox 30 Data Word 0 [15:0] Register   */
-#define CAN_MB30_DATA1      0xFFC02FC4  /* Mailbox 30 Data Word 1 [31:16] Register  */
-#define CAN_MB30_DATA2      0xFFC02FC8  /* Mailbox 30 Data Word 2 [47:32] Register  */
-#define CAN_MB30_DATA3      0xFFC02FCC  /* Mailbox 30 Data Word 3 [63:48] Register  */
-#define CAN_MB30_LENGTH     0xFFC02FD0  /* Mailbox 30 Data Length Code Register     */
-#define CAN_MB30_TIMESTAMP  0xFFC02FD4  /* Mailbox 30 Time Stamp Value Register     */
-#define CAN_MB30_ID0        0xFFC02FD8  /* Mailbox 30 Identifier Low Register       */
-#define CAN_MB30_ID1        0xFFC02FDC  /* Mailbox 30 Identifier High Register      */
-
-#define CAN_MB31_DATA0      0xFFC02FE0  /* Mailbox 31 Data Word 0 [15:0] Register   */
-#define CAN_MB31_DATA1      0xFFC02FE4  /* Mailbox 31 Data Word 1 [31:16] Register  */
-#define CAN_MB31_DATA2      0xFFC02FE8  /* Mailbox 31 Data Word 2 [47:32] Register  */
-#define CAN_MB31_DATA3      0xFFC02FEC  /* Mailbox 31 Data Word 3 [63:48] Register  */
-#define CAN_MB31_LENGTH     0xFFC02FF0  /* Mailbox 31 Data Length Code Register     */
-#define CAN_MB31_TIMESTAMP  0xFFC02FF4  /* Mailbox 31 Time Stamp Value Register     */
-#define CAN_MB31_ID0        0xFFC02FF8  /* Mailbox 31 Identifier Low Register       */
-#define CAN_MB31_ID1        0xFFC02FFC  /* Mailbox 31 Identifier High Register      */
-
-/* CAN Mailbox Area Macros              */
-#define CAN_MB_ID1(x)       (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)       (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)    (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)     (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)     (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)     (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)     (CAN_MB00_DATA0+((x)*0x20))
-
-
-
-/* Motor Control PWM1 Registers (0xFFC03000 - 0xFFC030FF)                                   */
-#define PWM1_CTRL               0xFFC03000  /* PWM1 Control Register                        */
-#define PWM1_STAT               0xFFC03004  /* PWM1 Status Register                         */
-#define PWM1_TM                 0xFFC03008  /* PWM1 Period Register                         */
-#define PWM1_DT                 0xFFC0300C  /* PWM1 Dead Time Register                      */
-#define PWM1_GATE               0xFFC03010  /* PWM1 Chopping Control                        */
-#define PWM1_CHA                0xFFC03014  /* PWM1 Channel A Duty Control                  */
-#define PWM1_CHB                0xFFC03018  /* PWM1 Channel B Duty Control                  */
-#define PWM1_CHC                0xFFC0301C  /* PWM1 Channel C Duty Control                  */
-#define PWM1_SEG                0xFFC03020  /* PWM1 Crossover and Output Enable             */
-#define PWM1_SYNCWT             0xFFC03024  /* PWM1 Sync pulse width control                */
-#define PWM1_CHAL               0xFFC03028  /* PWM1 Channel AL Duty Control (SR mode only)  */
-#define PWM1_CHBL               0xFFC0302C  /* PWM1 Channel BL Duty Control (SR mode only)  */
-#define PWM1_CHCL               0xFFC03030  /* PWM1 Channel CL Duty Control (SR mode only)  */
-#define PWM1_LSI                0xFFC03034  /* Low Side Invert (SR mode only)               */
-#define PWM1_STAT2              0xFFC03038  /* PWM1 Status Register                         */
-
-
-/* ADC Controller Module Registers (0xFFC03100 - 0xFFC031FF) */
-#define ACM_CTL        0xFFC03100  /* ACM Control Register                  */
-#define ACM_TC0        0xFFC03104  /* ACM Timing Configuration 0 Register   */
-#define ACM_TC1        0xFFC03108  /* ACM Timing Configuration 1 Register   */
-#define ACM_STAT       0xFFC0310C  /* ACM Status Register                   */
-#define ACM_ES         0xFFC03110  /* ACM Event Status Register             */
-#define ACM_IMSK       0xFFC03114  /* ACM Interrupt Mask Register           */
-#define ACM_MS         0xFFC03118  /* ACM Missed Event Status Register      */
-#define ACM_EMSK       0xFFC0311C  /* ACM Missed Event Interrupt Mask Register */
-
-#define ACM_ER0        0xFFC03120  /* ACM Event 0 Control Register          */
-#define ACM_ER1        0xFFC03124  /* ACM Event 1 Control Register          */
-#define ACM_ER2        0xFFC03128  /* ACM Event 2 Control Register          */
-#define ACM_ER3        0xFFC0312C  /* ACM Event 3 Control Register          */
-#define ACM_ER4        0xFFC03130  /* ACM Event 4 Control Register          */
-#define ACM_ER5        0xFFC03134  /* ACM Event 5 Control Register          */
-#define ACM_ER6        0xFFC03138  /* ACM Event 6 Control Register          */
-#define ACM_ER7        0xFFC0313C  /* ACM Event 7 Control Register          */
-#define ACM_ER8        0xFFC03140  /* ACM Event 8 Control Register          */
-#define ACM_ER9        0xFFC03144  /* ACM Event 9 Control Register          */
-#define ACM_ER10       0xFFC03148  /* ACM Event 10 Control Register         */
-#define ACM_ER11       0xFFC0314C  /* ACM Event 11 Control Register         */
-#define ACM_ER12       0xFFC03150  /* ACM Event 12 Control Register         */
-#define ACM_ER13       0xFFC03154  /* ACM Event 13 Control Register         */
-#define ACM_ER14       0xFFC03158  /* ACM Event 14 Control Register         */
-#define ACM_ER15       0xFFC0315C  /* ACM Event 15 Control Register         */
-
-#define ACM_ET0        0xFFC03180  /* ACM Event 0 Time Register             */
-#define ACM_ET1        0xFFC03184  /* ACM Event 1 Time Register             */
-#define ACM_ET2        0xFFC03188  /* ACM Event 2 Time Register             */
-#define ACM_ET3        0xFFC0318C  /* ACM Event 3 Time Register             */
-#define ACM_ET4        0xFFC03190  /* ACM Event 4 Time Register             */
-#define ACM_ET5        0xFFC03194  /* ACM Event 5 Time Register             */
-#define ACM_ET6        0xFFC03198  /* ACM Event 6 Time Register             */
-#define ACM_ET7        0xFFC0319C  /* ACM Event 7 Time Register             */
-#define ACM_ET8        0xFFC031A0  /* ACM Event 8 Time Register             */
-#define ACM_ET9        0xFFC031A4  /* ACM Event 9 Time Register             */
-#define ACM_ET10       0xFFC031A8  /* ACM Event 10 Time Register            */
-#define ACM_ET11       0xFFC031AC  /* ACM Event 11 Time Register            */
-#define ACM_ET12       0xFFC031B0  /* ACM Event 12 Time Register            */
-#define ACM_ET13       0xFFC031B4  /* ACM Event 13 Time Register            */
-#define ACM_ET14       0xFFC031B8  /* ACM Event 14 Time Register            */
-#define ACM_ET15       0xFFC031BC  /* ACM Event 15 Time Register            */
-
-#define ACM_TMR0       0xFFC031C0  /* ACM Timer 0 Registers                 */
-#define ACM_TMR1       0xFFC031C4  /* ACM Timer 1 Registers                 */
-
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                   */
-#define PORTF_FER               0xFFC03200  /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER               0xFFC03204  /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER               0xFFC03208  /* Port H Function Enable Register (Alternate/Flag*) */
-
-
-/* GPIO PIN mux                 (0xFFC03210 - OxFFC03288)                                   */
-#define PORTF_MUX               0xFFC03210  /* Port F mux control                           */
-#define PORTG_MUX               0xFFC03214  /* Port G mux control                           */
-#define PORTH_MUX               0xFFC03218  /* Port H mux control                           */
-#define PORTF_HYSTERESIS        0xFFC03240  /* Port F Schmitt trigger control               */
-#define PORTG_HYSTERESIS        0xFFC03244  /* Port G Schmitt trigger control               */
-#define PORTH_HYSTERESIS        0xFFC03248  /* Port H Schmitt trigger control               */
-
-#define NONGPIO_DRIVE           0xFFC03280  /* Misc Port drive strength control             */
-#define NONGPIO_HYSTERESIS      0xFFC03288  /* Misc Port Schmitt Trigger control            */
-
-#define FLASH_CONTROL           0xFFC0328C  /* Stacked flash control register               */
-#define FLASH_CONTROL_SET       0xFFC03290  /* Stacked flash control set register           */
-#define FLASH_CONTROL_CLEAR     0xFFC03294  /* Stacked flash control clear register         */
-
-
-/* Counter 1 Registers          (0xFFC03300 - 0xFFC033FF)                                   */
-#define CNT1_CONFIG             0xFFC03300  /* Counter 1 Configuration Register             */
-#define CNT1_IMASK              0xFFC03304  /* Counter 1 Interrupt Mask Register            */
-#define CNT1_STATUS             0xFFC03308  /* Counter 1 Status Register                    */
-#define CNT1_COMMAND            0xFFC0330C  /* Counter 1 Command Register                   */
-#define CNT1_DEBOUNCE           0xFFC03310  /* Counter 1 Debounce Register                  */
-#define CNT1_COUNTER            0xFFC03314  /* Counter 1 Counter Register                   */
-#define CNT1_MAX                0xFFC03318  /* Counter 1 Boundry Value Register - max count */
-#define CNT1_MIN                0xFFC0331C  /* Counter 1 Boundry Value Register - min count */
-
-
-/* SPI1 Controller              (0xFFC03400 - 0xFFC034FF)                                   */
-#define SPI1_CTL                0xFFC03400  /* SPI1 Control Register                        */
-#define SPI1_FLG                0xFFC03404  /* SPI1 Flag register                           */
-#define SPI1_STAT               0xFFC03408  /* SPI1 Status register                         */
-#define SPI1_TDBR               0xFFC0340C  /* SPI1 Transmit Data Buffer Register           */
-#define SPI1_RDBR               0xFFC03410  /* SPI1 Receive Data Buffer Register            */
-#define SPI1_BAUD               0xFFC03414  /* SPI1 Baud rate Register                      */
-#define SPI1_SHADOW             0xFFC03418  /* SPI1_RDBR Shadow Register                    */
-
-
-/* Counter 0 Registers          (0xFFC03500 - 0xFFC035FF)                                   */
-#define CNT0_CONFIG             0xFFC03500  /* Counter 0 Configuration Register             */
-#define CNT0_IMASK              0xFFC03504  /* Counter 0 Interrupt Mask Register            */
-#define CNT0_STATUS             0xFFC03508  /* Counter 0 Status Register                    */
-#define CNT0_COMMAND            0xFFC0350C  /* Counter 0 Command Register                   */
-#define CNT0_DEBOUNCE           0xFFC03510  /* Counter 0 Debounce Register                  */
-#define CNT0_COUNTER            0xFFC03514  /* Counter 0 Counter Register                   */
-#define CNT0_MAX                0xFFC03518  /* Counter 0 Boundry Value Register - max count */
-#define CNT0_MIN                0xFFC0351C  /* Counter 0 Boundry Value Register - min count */
-
-
-/* Motor Control PWM0 Registers (0xFFC03700 - 0xFFC037FF)                                   */
-#define PWM0_CTRL               0xFFC03700  /* PWM0 Control Register                        */
-#define PWM0_STAT               0xFFC03704  /* PWM0 Status Register                         */
-#define PWM0_TM                 0xFFC03708  /* PWM0 Period Register                         */
-#define PWM0_DT                 0xFFC0370C  /* PWM0 Dead Time Register                      */
-#define PWM0_GATE               0xFFC03710  /* PWM0 Chopping Control                        */
-#define PWM0_CHA                0xFFC03714  /* PWM0 Channel A Duty Control                  */
-#define PWM0_CHB                0xFFC03718  /* PWM0 Channel B Duty Control                  */
-#define PWM0_CHC                0xFFC0371C  /* PWM0 Channel C Duty Control                  */
-#define PWM0_SEG                0xFFC03720  /* PWM0 Crossover and Output Enable             */
-#define PWM0_SYNCWT             0xFFC03724  /* PWM0 Sync pulse width control                */
-#define PWM0_CHAL               0xFFC03728  /* PWM0 Channel AL Duty Control (SR mode only)  */
-#define PWM0_CHBL               0xFFC0372C  /* PWM0 Channel BL Duty Control (SR mode only)  */
-#define PWM0_CHCL               0xFFC03730  /* PWM0 Channel CL Duty Control (SR mode only)  */
-#define PWM0_LSI                0xFFC03734  /* Low Side Invert (SR mode only)               */
-#define PWM0_STAT2              0xFFC03738  /* PWM0 Status Register                         */
-
-
-/* RSI Registers                (0xFFC03800 - 0xFFC03CFF)                                   */
-#define RSI_PWR_CONTROL         0xFFC03800      /* RSI Power Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PWR_CTL             (RSI_PWR_CONTROL)/* SDH Power Control */
-#define RSI_CLK_CONTROL         0xFFC03804      /* RSI Clock Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CLK_CTL             (RSI_CLK_CONTROL)/* SDH Clock Control */
-#define RSI_ARGUMENT            0xFFC03808      /* RSI Argument Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_ARGUMENT            (RSI_ARGUMENT)  /* SDH Argument */
-#define RSI_COMMAND             0xFFC0380C      /* RSI Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_COMMAND             (RSI_COMMAND)       /* SDH Command */
-#define RSI_RESP_CMD            0xFFC03810      /* RSI Response Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESP_CMD            (RSI_RESP_CMD)      /* SDH Response Command */
-#define RSI_RESPONSE0           0xFFC03814      /* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE0           (RSI_RESPONSE0)     /* SDH Response0 */
-#define RSI_RESPONSE1           0xFFC03818      /* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE1           (RSI_RESPONSE1)     /* SDH Response1 */
-#define RSI_RESPONSE2           0xFFC0381C  /* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE2           (RSI_RESPONSE2)     /* SDH Response2 */
-#define RSI_RESPONSE3           0xFFC03820      /* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE3           (RSI_RESPONSE3)     /* SDH Response3 */
-#define RSI_DATA_TIMER          0xFFC03824      /* RSI Data Timer Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_TIMER          (RSI_DATA_TIMER)    /* SDH Data Timer */
-#define RSI_DATA_LGTH           0xFFC03828      /* RSI Data Length Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_LGTH           (RSI_DATA_LGTH)     /* SDH Data Length */
-#define RSI_DATA_CONTROL        0xFFC0382C      /* RSI Data Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CTL            (RSI_DATA_CONTROL)  /* SDH Data Control */
-#define RSI_DATA_CNT            0xFFC03830      /* RSI Data Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CNT            (RSI_DATA_CNT)      /* SDH Data Counter */
-#define RSI_STATUS              0xFFC03834      /* RSI Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS              (RSI_STATUS)        /* SDH Status */
-#define RSI_STATUSCL            0xFFC03838      /* RSI Status Clear Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS_CLR          (RSI_STATUSCL)      /* SDH Status Clear */
-#define RSI_MASK0               0xFFC0383C      /* RSI Interrupt 0 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK0               (RSI_MASK0)         /* SDH Interrupt0 Mask */
-#define RSI_MASK1               0xFFC03840      /* RSI Interrupt 1 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK1               (RSI_MASK1)         /* SDH Interrupt1 Mask */
-#define RSI_FIFO_CNT            0xFFC03848      /* RSI FIFO Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO_CNT            (RSI_FIFO_CNT)      /* SDH FIFO Counter */
-#define RSI_CEATA_CONTROL       0xFFC0384C      /* RSI CEATA Register */
-#define RSI_FIFO                0xFFC03880      /* RSI Data FIFO Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO                (RSI_FIFO)          /* SDH Data FIFO */
-#define RSI_ESTAT               0xFFC038C0      /* RSI Exception Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_STATUS            (RSI_ESTAT)         /* SDH Exception Status */
-#define RSI_EMASK               0xFFC038C4      /* RSI Exception Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_MASK              (RSI_EMASK)         /* SDH Exception Mask */
-#define RSI_CONFIG              0xFFC038C8      /* RSI Configuration Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CFG                 (RSI_CONFIG)        /* SDH Configuration */
-#define RSI_RD_WAIT_EN          0xFFC038CC      /* RSI Read Wait Enable Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RD_WAIT_EN          (RSI_RD_WAIT_EN)    /* SDH Read Wait Enable */
-#define RSI_PID0                0xFFC038D0      /* RSI Peripheral ID Register 0 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID0                (RSI_PID0)          /* SDH Peripheral Identification0 */
-#define RSI_PID1                0xFFC038D4      /* RSI Peripheral ID Register 1 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID1                (RSI_PID1)          /* SDH Peripheral Identification1 */
-#define RSI_PID2                0xFFC038D8      /* RSI Peripheral ID Register 2 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID2                (RSI_PID2)          /* SDH Peripheral Identification2 */
-#define RSI_PID3                0xFFC038DC      /* RSI Peripheral ID Register 3 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID3                (RSI_PID3)          /* SDH Peripheral Identification3 */
-
-
-/******************************************************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**          Use these macros carefully, as any that do left shifts for field
-**          depositing will result in the lower order bits being destroyed.  Any
-**          macro that shifts left to properly position the bit-field should be
-**          used as part of an OR to initialize a register and NOT as a dynamic
-**          modifier UNLESS the lower order bits are saved and ORed back in when
-**          the macro is used.
-*******************************************************************************************************************/
-
-/************************************** PLL AND RESET MASKS *******************************************************/
-
-/* PLL_CTL Masks */
-#define DF                  0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                     */
-#define PLL_OFF             0x0002  /* PLL Not Powered                              */
-#define STOPCK              0x0008  /* Core Clock Off                                   */
-#define PDWN                0x0020  /* Enter Deep Sleep Mode                            */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                    */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                   */
-#define BYPASS              0x0100  /* Bypass the PLL                                   */
-#define MSEL                0x7E00  /* Multiplier Select For CCLK/VCO Factors                   */
-
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x) (((x)&0x3Fu) << 0x9)    /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL                 */
-#else
-#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL                 */
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL                0x000F  /* System Select                                    */
-#define CSEL                0x0030  /* Core Select                                  */
-#define CSEL_DIV1               0x0000  /* CCLK = VCO / 1                                   */
-#define CSEL_DIV2               0x0010  /* CCLK = VCO / 2                                   */
-#define CSEL_DIV4               0x0020  /* CCLK = VCO / 4                                   */
-#define CSEL_DIV8               0x0030  /* CCLK = VCO / 8                                   */
-
-/* PLL_DIV Macros   */
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)         ((x)&0xFu)  /* Set SSEL = 0-15 --> SCLK = VCO/SSEL                  */
-#else
-#define SET_SSEL(x)         ((x)&0xF)   /* Set SSEL = 0-15 --> SCLK = VCO/SSEL                  */
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks */
-#define WAKE_POLARITY           0x8000  /* GPIO wakeup active level                         */
-#define EXTCLK_OE               0x4000  /* Enable/disable EXTCLK                            */
-#define EXTCLK_SEL              0x2000  /* EXTCLK Select                                    */
-#define HIBERNATEB              0x1000  /* Bit mask for HIBERNATEB                          */
-#define HIBERNATE               0x0000  /* Enter Hibernate - this bit is active LOW         */
-#define WAKE_EN0				0x0100	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN0 signal	*/
-#define WAKE_EN1				0x0200	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN1 signal	*/
-#define CANWE                   0x0400  /* CAN Rx Wakeup Enable                             */
-#define WAKE_EN2				0x0800	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN3 signal	*/
-
-/* PLL_STAT Masks   */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled                */
-#define FULL_ON             0x0002  /* Processor In Full On Mode                            */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled               */
-#define PLL_LOCKED          0x0020  /* PLL_LOCKCNT Has Been Reached                     */
-
-/* SWRST Masks */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                       */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG          0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST               */
-
-/* SYSCR Masks */
-#define BMODE_BYPASS            0x0000  /* Bypass boot ROM, execute from 16-bit external memory  */
-#define BMODE_FLASH_ASYNC       0x0001  /* Boot from stacked parallel flash in asynchornous mode */
-#define BMODE_FLASH_SYNC        0x0002  /* Boot from stacked parallel flash in synchornous mode  */
-#define BMODE_SPIMEM            0x0003  /* Boot from serial SPI memory (master mode)             */
-#define BMODE_SPIHOST           0x0004  /* Boot from SPI0 host (slave mode)                      */
-#define BMODE_PPIHOST           0x0005  /* Boot from PPI host                                    */
-#define BMODE_UART0HOST         0x0007  /* Boot from UART0 host                                  */
-
-#define BMODE                   0x000F  /* Boot Mode. Mirror of BMODE Mode Pins                  */
-
-#define BCODE                   0x00F0
-#define BCODE_NORMAL            0x0000  /* normal boot, update PLL/VR, quickboot as by WURESET   */
-#define BCODE_NOBOOT            0x0010  /* bypass boot, don't update PLL/VR                      */
-#define BCODE_QUICKBOOT         0x0020  /* quick boot, overrule WURESET, don't update PLL/VR     */
-#define BCODE_ALLBOOT           0x0040  /* no quick boot, overrule WURESET, don't update PLL/VR  */
-#define BCODE_FULLBOOT          0x0060  /* no quick boot, overrule WURESET, update PLL/VR        */
-
-#define WURESET                 0x1000  /* wakeup event since last hardware reset                */
-#define DFRESET                 0x2000  /* recent reset was due to a double fault event          */
-#define WDRESET                 0x4000  /* recent reset was due to a watchdog event              */
-#define SWRESET                 0x8000  /* recent reset was issued by software                   */
-
-/*********************************  SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/
-
-/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
-#define IRQ_PLL_WAKEUP          0x00000001  /* PLL Wakeup Interrupt                                     */
-#define IRQ_DMA_ERR0            0x00000002  /* Error Interrupt (DMA error interrupt (generic))          */
-#define IRQ_PPI_ERR             0x00000004  /* Error Interrupt (PPI error interrupt)                    */
-#define IRQ_SPORT0_ERR          0x00000008  /* Error Interrupt (SPORT0 status interrupt)                */
-#define IRQ_SPORT1_ERR          0x00000010  /* Error Interrupt (SPORT1 status interrupt)                */
-#define IRQ_UART0_ERR           0x00000020  /* Error Interrupt (UART0 status interrupt)                 */
-#define IRQ_UART1_ERR           0x00000040  /* Error Interrupt (UART1 status interrupt)                 */
-#define IRQ_SPI0_ERR            0x00000080  /* Error Interrupt (SPI0 status interrupt)                  */
-#define IRQ_SPI1_ERR            0x00000100  /* Error Interrupt (SPI1 status interrupt)                  */
-#define IRQ_CAN_ERR             0x00000200  /* Error Interrupt (CAN status interrupt)                   */
-#define IRQ_RSI_INT0            0x00000400  /* RSI Mask 0 Interrupt                                     */
-                                            /* Bit 11 is reserved                                       */
-#define IRQ_CNT0                0x00001000  /* GP Counter 0 Interrupt                                   */
-#define IRQ_CNT1                0x00002000  /* GP Counter 1 Interrupt                                   */
-#define IRQ_DMA0                0x00004000  /* DMA Channel 0 (PPI Rx/Tx) Interrupt                      */
-#define IRQ_DMA1                0x00008000  /* DMA Channel 1 (RSI Rx/Tx) Interrupt                      */
-#define IRQ_DMA2                0x00010000  /* DMA Channel 2 (SPORT0 Rx) Interrupt                      */
-#define IRQ_DMA3                0x00020000  /* DMA Channel 3 (SPORT0 Tx) Interrupt                      */
-#define IRQ_DMA4                0x00040000  /* DMA Channel 4 (SPORT1 Rx) Interrupt                      */
-#define IRQ_DMA5                0x00080000  /* DMA Channel 5 (SPORT1 Tx) Interrupt                      */
-#define IRQ_DMA6                0x00100000  /* DMA Channel 6 (SPI0 Rx/Tx) Interrupt                     */
-#define IRQ_DMA7                0x00200000  /* DMA Channel 7 (SPI1 Rx/Tx) Interrupt                     */
-#define IRQ_DMA8                0x00400000  /* DMA Channel 8 (UART0 Rx) Interrupt                       */
-#define IRQ_DMA9                0x00800000  /* DMA Channel 9 (UART0 Tx) Interrupt                       */
-#define IRQ_DMA10               0x01000000  /* DMA Channel 10 (UART1 Rx) Interrupt                      */
-#define IRQ_DMA11               0x02000000  /* DMA Channel 11 (UART1 Tx) Interrupt                      */
-#define IRQ_CAN_RX              0x04000000  /* CAN Rx Interrupt                                         */
-#define IRQ_CAN_TX              0x08000000  /* CAN Tx Interrupt                                         */
-#define IRQ_TWI                 0x10000000  /* TWI Interrupt                                            */
-#define IRQ_PFA_PORTF           0x20000000  /* PF Port F Interrupt A                                    */
-#define IRQ_PFB_PORTF           0x40000000  /* PF Port F Interrupt B                                    */
-                                            /* Bit 31 is reserved                                       */
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define IRQ_TIMER0              0x00000001  /* Timer 0 Interrupt                                        */
-#define IRQ_TIMER1              0x00000002  /* Timer 1 Interrupt                                        */
-#define IRQ_TIMER2              0x00000004  /* Timer 2 Interrupt                                        */
-#define IRQ_TIMER3              0x00000008  /* Timer 3 Interrupt                                        */
-#define IRQ_TIMER4              0x00000010  /* Timer 4 Interrupt                                        */
-#define IRQ_TIMER5              0x00000020  /* Timer 5 Interrupt                                        */
-#define IRQ_TIMER6              0x00000040  /* Timer 6 Interrupt                                        */
-#define IRQ_TIMER7              0x00000080  /* Timer 7 Interrupt                                        */
-#define IRQ_PFA_PORTG           0x00000100  /* PF Port G Interrupt A                                    */
-#define IRQ_PFB_PORTG           0x00000200  /* PF Port G Interrupt B                                    */
-#define IRQ_DMA12               0x00000400  /* DMA Channel 12 (MDMA0 Destination) Rx Interrupt          */
-#define IRQ_DMA13               0x00000400  /* DMA Channel 13 (MDMA0 Source) Tx Interrupt               */
-#define IRQ_DMA14               0x00000800  /* DMA Channels 14 (MDMA1 Destination) Rx Interrupt         */
-#define IRQ_DMA15               0x00000800  /* DMA Channels 15 (MDMA1 Source) Tx Interrupt              */
-#define IRQ_WDOG                0x00001000  /* Software Watchdog Timer Interrupt                        */
-#define IRQ_PFA_PORTH           0x00002000  /* PF Port H Interrupt A                                    */
-#define IRQ_PFB_PORTH           0x00004000  /* PF Port H Interrupt B                                    */
-#define IRQ_ACM_ERR             0x00008000  /* Error Interrupt (ACM status interrupt)                   */
-#define IRQ_ACM                 0x00010000  /* ACM (ADC Controller Module) Interrupt                    */
-                                            /* Bit 49 is reserved                                       */
-                                            /* Bit 50 is reserved                                       */
-#define IRQ_PWM0_TRIPINT        0x00080000  /* PWM 0 Trip Interrupt                                     */
-#define IRQ_PWM0_SYNCINT        0x00100000  /* PWM 0 Sync Interrupt                                     */
-#define IRQ_PWM1_TRIPINT        0x00200000  /* PWM 1 Trip Interrupt                                     */
-#define IRQ_PWM1_SYNCINT        0x00400000  /* PWM 1 Sync Interrupt                                     */
-#define IRQ_RSI_INT1            0x00800000  /* RSI Mask 1 interrupt                                     */
-                                            /* Bits 63:56 are reserved                                  */
-
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define IWR_DISABLE_ALL         0x00000000  /* Wakeup Disable all peripherals                       */
-#define IWR_ENABLE_ALL              0xFFFFFFFF  /* Wakeup Enable all peripherals                        */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)               (1 << (x))  /* Wakeup Enable Peripheral #x                      */
-#define IWR_DISABLE(x)   (0xFFFFFFFF^(1<<(x)))  /* Wakeup Disable Peripheral #x                         */
-
-#ifdef _MISRA_RULES
-#define _MF15   0xFu
-#define _MF7    7u
-#else
-#define _MF15   0xF
-#define _MF7    7
-#endif /* _MISRA_RULES */
-
-
-/* SIC_IAR0 Macros*/
-#define P0_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #0 assigned IVG #x    */
-#define P1_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #1 assigned IVG #x    */
-#define P2_IVG(x)       ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #2 assigned IVG #x    */
-#define P3_IVG(x)       ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #3 assigned IVG #x    */
-#define P4_IVG(x)       ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x    */
-#define P5_IVG(x)       ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x    */
-#define P6_IVG(x)       ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x    */
-#define P7_IVG(x)       ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x    */
-
-/* SIC_IAR1 Macros*/
-#define P8_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #8 assigned IVG #x    */
-#define P9_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #9 assigned IVG #x    */
-#define P10_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #10 assigned IVG #x   */
-#define P11_IVG(x)                                   /* Reserved                         */
-#define P12_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x   */
-#define P13_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x   */
-#define P14_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x   */
-#define P15_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x   */
-
-/* SIC_IAR2 Macros*/
-#define P16_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #16 assigned IVG #x   */
-#define P17_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #17 assigned IVG #x   */
-#define P18_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #18 assigned IVG #x   */
-#define P19_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #19 assigned IVG #x   */
-#define P20_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x   */
-#define P21_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x   */
-#define P22_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x   */
-#define P23_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x   */
-
-
-/* SIC_IAR3 Macros*/
-#define P24_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #24 assigned IVG #x   */
-#define P25_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #25 assigned IVG #x   */
-#define P26_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #26 assigned IVG #x   */
-#define P27_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #27 assigned IVG #x   */
-#define P28_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x   */
-#define P29_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x   */
-#define P30_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x   */
-#define P31_IVG(x)                                   /* Reserved                         */
-
-/* SIC_IAR4 Macros*/
-#define P32_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #32 assigned IVG #x   */
-#define P33_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #33 assigned IVG #x   */
-#define P34_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #34 assigned IVG #x   */
-#define P35_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #35 assigned IVG #x   */
-#define P36_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x   */
-#define P37_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x   */
-#define P38_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x   */
-#define P39_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x   */
-
-/* SIC_IAR5 Macros*/
-#define P40_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #40 assigned IVG #x   */
-#define P41_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #41 assigned IVG #x   */
-#define P42_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #42 assigned IVG #x   */
-#define P43_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #43 assigned IVG #x   */
-#define P44_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x   */
-#define P45_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x   */
-#define P46_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x   */
-#define P47_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x   */
-
-/* SIC_IAR6 Macros*/
-#define P48_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #48 assigned IVG #x   */
-#define P49_IVG(x)                                   /* Reserved                         */
-#define P50_IVG(x)                                   /* Reserved                         */
-#define P51_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #51 assigned IVG #x   */
-#define P52_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x   */
-#define P53_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x   */
-#define P54_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x   */
-#define P55_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x   */
-
-
-/* SIC_IMASK0 Masks*/
-#define SIC_UNMASK0_ALL 0x00000000              /* Unmask all peripheral interrupts */
-#define SIC_MASK0_ALL   0xEFFFF7FF              /* Mask all peripheral interrupts   */
-
-#if 0 /* scheduled for removal */
-#ifdef _MISRA_RULES
-#define SIC_MASK0(x)    (1 << ((x)&0x1Fu))      /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK0(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK0(x)    (1 << ((x)&0x1F))           /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK0(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt   */
-#endif /* _MISRA_RULES */
-#endif
-
-/* SIC_IMASK1 Masks*/
-#define SIC_UNMASK1_ALL 0x00000000              /* Unmask all peripheral interrupts */
-#define SIC_MASK1_ALL   0x00F9FFFF              /* Mask all peripheral interrupts   */
-
-#if 0 /* scheduled for removal */
-#ifdef _MISRA_RULES
-#define SIC_MASK1(x)    (1 << ((x)&0x1Fu))      /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK1(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK1(x)    (1 << ((x)&0x1F))           /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK1(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Unmask Peripheral #x interrupt   */
-#endif /* _MISRA_RULES */
-#endif
-
-
-/* SIC_IWR0 Masks*/
-#define IWR0_DISABLE_ALL 0x00000000             /* Wakeup Disable all peripherals   */
-#define IWR0_ENABLE_ALL  0xEFFFF7FF             /* Wakeup Enable all peripherals    */
-
-#if 0 /* scheduled for removal */
-#ifdef _MISRA_RULES
-#define IWR0_ENABLE(x)   (1 << ((x)&0x1Fu))     /* Wakeup Enable Peripheral #x  */
-#define IWR0_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/*Wakeup Disable Peripheral #x   */
-#else
-#define IWR0_ENABLE(x)   (1 << ((x)&0x1F))      /* Wakeup Enable Peripheral #x  */
-#define IWR0_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x    */
-#endif /* _MISRA_RULES */
-#endif
-
-/* SIC_IWR1 Masks*/
-#define IWR1_DISABLE_ALL 0x00000000             /* Wakeup Disable all peripherals   */
-#define IWR1_ENABLE_ALL  0x00F9FFFF             /* Wakeup Enable all peripherals    */
-
-#if 0 /* scheduled for removal */
-#ifdef _MISRA_RULES
-#define IWR1_ENABLE(x)   (1 << ((x)&0x1Fu))     /* Wakeup Enable Peripheral #x  */
-#define IWR1_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))/* Wakeup Disable Peripheral #x*/
-#else
-#define IWR1_ENABLE(x)   (1 << ((x)&0x1F))      /* Wakeup Enable Peripheral #x  */
-#define IWR1_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x    */
-#endif /* _MISRA_RULES */
-#endif
-
-
-/* ************************************** WATCHDOG TIMER MASKS ****************************************************/
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define WDEV(x)      (((x)<<1) & 0x0006u)   /* event generated on roll over                         */
-#else
-#define WDEV(x)         (((x)<<1) & 0x0006) /* event generated on roll over                         */
-#endif /* _MISRA_RULES */
-
-#define WDEV_RESET          0x0000  /* generate reset event on roll over                    */
-#define WDEV_NMI                0x0002  /* generate NMI event on roll over                      */
-#define WDEV_GPI                0x0004  /* generate GP IRQ on roll over                         */
-#define WDEV_NONE           0x0006  /* no event on roll over                            */
-#define WDEN                0x0FF0  /* enable watchdog                              */
-#define WDDIS               0x0AD0  /* disable watchdog                                 */
-#define WDRO                0x8000  /* watchdog rolled over latch                       */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-#define ICTL                (WDEV)
-#define ENABLE_RESET            (WDEV_RESET)
-#define WDOG_RESET          (WDEV_RESET)
-#define ENABLE_NMI          (WDEV_NMI)
-#define WDOG_NMI                (WDEV_NMI)
-#define ENABLE_GPI          (WDEV_GPI)
-#define WDOG_GPI                (WDEV_GPI)
-#define DISABLE_EVT             (WDEV_NONE)
-#define WDOG_NONE           (WDEV_NONE)
-
-#define TMR_EN              (WDEN)
-#define TMR_DIS                 (WDDIS)
-#define TRO                 (WDRO)
-#define ICTL_P0                 (0x01)
-#define ICTL_P1                 (0x02)
-#define TRO_P               (0x0F)
-
-
-/* ************************************ UART CONTROLLER MASKS *****************************************************/
-
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                      nSTB  0x0
-#define                       PEN  0x8        /* Parity Enable */
-#define                      nPEN  0x0
-#define                       EPS  0x10       /* Even Parity Select */
-#define                      nEPS  0x0
-#define                       STP  0x20       /* Sticky Parity */
-#define                      nSTP  0x0
-#define                        SB  0x40       /* Set Break */
-#define                       nSB  0x0
-
-/* for legacy compatibility */
-
-#ifdef _MISRA_RULES
-#define WLS(x)  (((x)-5u) & 0x03u) /* Word Length Select */
-#else
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                     nXOFF  0x0
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                     nMRTS  0x0
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                     nRFIT  0x0
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                     nRFRT  0x0
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                 nLOOP_ENA  0x0
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                    nFCPOL  0x0
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                     nARTS  0x0
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-#define                     nACTS  0x0
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                       nDR  0x0
-#define                        OE  0x2        /* Overrun Error */
-#define                       nOE  0x0
-#define                        PE  0x4        /* Parity Error */
-#define                       nPE  0x0
-#define                        FE  0x8        /* Framing Error */
-#define                       nFE  0x0
-#define                        BI  0x10       /* Break Interrupt */
-#define                       nBI  0x0
-#define                      THRE  0x20       /* THR Empty */
-#define                     nTHRE  0x0
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                     nTEMT  0x0
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-#define                      nTFI  0x0
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                     nSCTS  0x0
-#define                       CTS  0x10       /* Clear To Send */
-#define                      nCTS  0x0
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-#define                     nRFCS  0x0
-
-/* Bit masks for UARTx_IER_SET and UARTx_IER_CLEAR */
-
-#define                     ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                    nERBFI  0x0
-#define                     ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    nETBEI  0x0
-#define                      ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                     nELSI  0x0
-#define                     EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                    nEDSSI  0x0
-
-#define                      ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                     nETFI  0x0
-
-#define                     ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-#define                    nERFCI  0x0
-
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                     nUCEN  0x0
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     nIREN  0x0
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                    nTPOLC  0x0
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                    nRPOLC  0x0
-#define                       FPE  0x10       /* Force Parity Error */
-#define                      nFPE  0x0
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      nFFE  0x0
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     nEDBO  0x0
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-#define                    nEGLSI  0x0
-
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
-
-/********************************  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ***************************************/
-
-/* SPI_CTL Masks*/
-#define TIMOD               0x0003  /* Transfer Initiate Mode                           */
-#define RDBR_CORE               0x0000  /* RDBR Read Initiates, IRQ When RDBR Full              */
-#define TDBR_CORE               0x0001  /* TDBR Write Initiates, IRQ When TDBR Empty                */
-#define RDBR_DMA                0x0002  /* DMA Read, DMA Until FIFO Empty                       */
-#define TDBR_DMA                0x0003  /* DMA Write, DMA Until FIFO Full                       */
-#define SZ                  0x0004  /* Send Zero (When TDBR Empty, Send Zero/Last*)             */
-#define GM                  0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)            */
-#define PSSE                0x0010  /* Slave-Select Input Enable                            */
-#define EMISO               0x0020  /* Enable MISO As Output                            */
-#define SIZE                0x0100  /* Size of Words (16/8* Bits)                           */
-#define LSBF                0x0200  /* LSB First                                    */
-#define CPHA                0x0400  /* Clock Phase                                  */
-#define CPOL                0x0800  /* Clock Polarity                                   */
-#define MSTR                0x1000  /* Master/Slave*                                    */
-#define WOM                 0x2000  /* Write Open Drain Master                          */
-#define SPE                 0x4000  /* SPI Enable                                   */
-
-/* SPI_FLG Masks*/
-#define FLS1                0x0002  /* Enables SPI_FLOUT1 as SPI Slave-Select Output            */
-#define FLS2                0x0004  /* Enables SPI_FLOUT2 as SPI Slave-Select Output            */
-#define FLS3                0x0008  /* Enables SPI_FLOUT3 as SPI Slave-Select Output            */
-#define FLS4                0x0010  /* Enables SPI_FLOUT4 as SPI Slave-Select Output            */
-#define FLS5                0x0020  /* Enables SPI_FLOUT5 as SPI Slave-Select Output            */
-#define FLS6                0x0040  /* Enables SPI_FLOUT6 as SPI Slave-Select Output            */
-#define FLS7                0x0080  /* Enables SPI_FLOUT7 as SPI Slave-Select Output            */
-#define FLG1                0xFDFF  /* Activates SPI_FLOUT1                             */
-#define FLG2                0xFBFF  /* Activates SPI_FLOUT2                             */
-#define FLG3                0xF7FF  /* Activates SPI_FLOUT3                             */
-#define FLG4                0xEFFF  /* Activates SPI_FLOUT4                             */
-#define FLG5                0xDFFF  /* Activates SPI_FLOUT5                             */
-#define FLG6                0xBFFF  /* Activates SPI_FLOUT6                             */
-#define FLG7                0x7FFF  /* Activates SPI_FLOUT7                             */
-
-/* SPI_STAT Masks*/
-#define SPIF                0x0001  /* SPI Finished (Single-Word Transfer Complete)             */
-#define MODF                0x0002  /* Mode Fault Error (Another Device Tried To Become Master)     */
-#define TXE                 0x0004  /* Transmission Error (Data Sent With No New Data In TDBR)      */
-#define TXS                 0x0008  /* SPI_TDBR Data Buffer Status (Full/Empty*)                */
-#define RBSY                0x0010  /* Receive Error (Data Received With RDBR Full)             */
-#define RXS                 0x0020  /* SPI_RDBR Data Buffer Status (Full/Empty*)                */
-#define TXCOL               0x0040  /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-
-/***********************************  GENERAL PURPOSE TIMER MASKS  ************************************************/
-/* TIMER_ENABLE Masks*/
-#define TIMEN0              0x0001  /* Enable Timer 0                                   */
-#define TIMEN1              0x0002  /* Enable Timer 1                                   */
-#define TIMEN2              0x0004  /* Enable Timer 2                                   */
-#define TIMEN3              0x0008  /* Enable Timer 3                                   */
-#define TIMEN4              0x0010  /* Enable Timer 4                                   */
-#define TIMEN5              0x0020  /* Enable Timer 5                                   */
-#define TIMEN6              0x0040  /* Enable Timer 6                                   */
-#define TIMEN7              0x0080  /* Enable Timer 7                                   */
-
-/* TIMER_DISABLE Masks*/
-#define TIMDIS0             (TIMEN0)  /* Disable Timer 0                              */
-#define TIMDIS1             (TIMEN1)  /* Disable Timer 1                              */
-#define TIMDIS2             (TIMEN2)  /* Disable Timer 2                              */
-#define TIMDIS3             (TIMEN3)  /* Disable Timer 3                              */
-#define TIMDIS4             (TIMEN4)  /* Disable Timer 4                              */
-#define TIMDIS5             (TIMEN5)  /* Disable Timer 5                              */
-#define TIMDIS6             (TIMEN6)  /* Disable Timer 6                              */
-#define TIMDIS7             (TIMEN7)  /* Disable Timer 7                              */
-
-/* TIMER_STATUS Masks*/
-#define TIMIL0              0x00000001  /* Timer 0 Interrupt                                */
-#define TIMIL1              0x00000002  /* Timer 1 Interrupt                                */
-#define TIMIL2              0x00000004  /* Timer 2 Interrupt                                */
-#define TIMIL3              0x00000008  /* Timer 3 Interrupt                                */
-#define TOVF_ERR0               0x00000010  /* Timer 0 Counter Overflow                         */
-#define TOVF_ERR1               0x00000020  /* Timer 1 Counter Overflow                         */
-#define TOVF_ERR2               0x00000040  /* Timer 2 Counter Overflow                         */
-#define TOVF_ERR3               0x00000080  /* Timer 3 Counter Overflow                         */
-#define TRUN0               0x00001000  /* Timer 0 Slave Enable Status                      */
-#define TRUN1               0x00002000  /* Timer 1 Slave Enable Status                      */
-#define TRUN2               0x00004000  /* Timer 2 Slave Enable Status                      */
-#define TRUN3               0x00008000  /* Timer 3 Slave Enable Status                      */
-#define TIMIL4              0x00010000  /* Timer 4 Interrupt                                */
-#define TIMIL5              0x00020000  /* Timer 5 Interrupt                                */
-#define TIMIL6              0x00040000  /* Timer 6 Interrupt                                */
-#define TIMIL7              0x00080000  /* Timer 7 Interrupt                                */
-#define TOVF_ERR4               0x00100000  /* Timer 4 Counter Overflow                         */
-#define TOVF_ERR5               0x00200000  /* Timer 5 Counter Overflow                         */
-#define TOVF_ERR6               0x00400000  /* Timer 6 Counter Overflow                         */
-#define TOVF_ERR7               0x00800000  /* Timer 7 Counter Overflow                         */
-#define TRUN4               0x10000000  /* Timer 4 Slave Enable Status                      */
-#define TRUN5               0x20000000  /* Timer 5 Slave Enable Status                      */
-#define TRUN6               0x40000000  /* Timer 6 Slave Enable Status                      */
-#define TRUN7               0x80000000  /* Timer 7 Slave Enable Status                      */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0           (TOVF_ERR0)
-#define TOVL_ERR1               (TOVF_ERR1)
-#define TOVL_ERR2           (TOVF_ERR2)
-#define TOVL_ERR3           (TOVF_ERR3)
-#define TOVL_ERR4           (TOVF_ERR4)
-#define TOVL_ERR5           (TOVF_ERR5)
-#define TOVL_ERR6           (TOVF_ERR6)
-#define TOVL_ERR7           (TOVF_ERR7)
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT             0x0001  /* Pulse-Width Modulation Output Mode                   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                         */
-#define EXT_CLK             0x0003  /* External Clock Mode                              */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)                    */
-#define PERIOD_CNT          0x0008  /* Period Count                                 */
-#define IRQ_ENA             0x0010  /* Interrupt Request Enable                         */
-#define TIN_SEL             0x0020  /* Timer Input Select                               */
-#define OUT_DIS             0x0040  /* Output Pad Disable                               */
-#define CLK_SEL             0x0080  /* Timer Clock Select                               */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                     */
-#define EMU_RUN             0x0200  /* Emulation Behavior Select                            */
-#define ERR_TYP             0xC000  /* Error Type                                   */
-
-
-/* *************************************   GPIO PORTS F, G, H MASKS  **********************************************/
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-/* Port F Masks */
-#define PF0                 0x0001
-#define PF1                 0x0002
-#define PF2                 0x0004
-#define PF3                 0x0008
-#define PF4                 0x0010
-#define PF5                 0x0020
-#define PF6                 0x0040
-#define PF7                 0x0080
-#define PF8                 0x0100
-#define PF9                 0x0200
-#define PF10                0x0400
-#define PF11                0x0800
-#define PF12                0x1000
-#define PF13                0x2000
-#define PF14                0x4000
-#define PF15                0x8000
-
-/* Port G Masks */
-#define PG0                 0x0001
-#define PG1                 0x0002
-#define PG2                 0x0004
-#define PG3                 0x0008
-#define PG4                 0x0010
-#define PG5                 0x0020
-#define PG6                 0x0040
-#define PG7                 0x0080
-#define PG8                 0x0100
-#define PG9                 0x0200
-#define PG10                0x0400
-#define PG11                0x0800
-#define PG12                0x1000
-#define PG13                0x2000
-#define PG14                0x4000
-#define PG15                0x8000
-
-/* Port H Masks */
-#define PH0                 0x0001
-#define PH1                 0x0002
-#define PH2                 0x0004
-
-
-/* **************************************  SERIAL PORT MASKS  *****************************************************/
-/* SPORTx_TCR1 Masks */
-#define TSPEN               0x0001  /* Transmit Enable                              */
-#define ITCLK               0x0002  /* Internal Transmit Clock Select                       */
-#define DTYPE_NORM          0x0004  /* Data Format Normal                               */
-#define DTYPE_ULAW          0x0008  /* Compand Using u-Law                              */
-#define DTYPE_ALAW          0x000C  /* Compand Using A-Law                              */
-#define TLSBIT              0x0010  /* Transmit Bit Order                               */
-#define ITFS                0x0200  /* Internal Transmit Frame Sync Select                  */
-#define TFSR                0x0400  /* Transmit Frame Sync Required Select                  */
-#define DITFS               0x0800  /* Data-Independent Transmit Frame Sync Select              */
-#define LTFS                0x1000  /* Low Transmit Frame Sync Select                       */
-#define LATFS               0x2000  /* Late Transmit Frame Sync Select                      */
-#define TCKFE               0x4000  /* Clock Falling Edge Select                            */
-
-/* SPORTx_TCR2 Masks and Macro */
-#ifdef _MISRA_RULES
-#define SLEN(x)             ((x)&0x1Fu) /* SPORT TX Word Length (2 - 31)                        */
-#else
-#define SLEN(x)             ((x)&0x1F)  /* SPORT TX Word Length (2 - 31)                        */
-#endif /* _MISRA_RULES */
-
-#define TXSE                0x0100  /* TX Secondary Enable                              */
-#define TSFSE               0x0200  /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST               0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN               0x0001  /* Receive Enable                               */
-#define IRCLK               0x0002  /* Internal Receive Clock Select                        */
-#define DTYPE_NORM          0x0004  /* Data Format Normal                               */
-#define DTYPE_ULAW          0x0008  /* Compand Using u-Law                              */
-#define DTYPE_ALAW          0x000C  /* Compand Using A-Law                              */
-#define RLSBIT              0x0010  /* Receive Bit Order                                */
-#define IRFS                0x0200  /* Internal Receive Frame Sync Select                   */
-#define RFSR                0x0400  /* Receive Frame Sync Required Select                   */
-#define LRFS                0x1000  /* Low Receive Frame Sync Select                        */
-#define LARFS               0x2000  /* Late Receive Frame Sync Select                       */
-#define RCKFE               0x4000  /* Clock Falling Edge Select                            */
-
-/* SPORTx_RCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)             ((x)&0x1Fu) /* SPORT RX Word Length (2 - 31)                        */
-#else
-#define SLEN(x)             ((x)&0x1F)  /* SPORT RX Word Length (2 - 31)                        */
-#endif /* _MISRA_RULES */
-
-#define RXSE                0x0100  /* RX Secondary Enable                              */
-#define RSFSE               0x0200  /* RX Stereo Frame Sync Enable                      */
-#define RRFST               0x0400  /* Right-First Data Order                           */
-
-/* SPORTx_STAT Masks */
-#define RXNE                0x0001  /* Receive FIFO Not Empty Status                        */
-#define RUVF                0x0002  /* Sticky Receive Underflow Status                      */
-#define ROVF                0x0004  /* Sticky Receive Overflow Status                       */
-#define TXF                 0x0008  /* Transmit FIFO Full Status                            */
-#define TUVF                0x0010  /* Sticky Transmit Underflow Status                     */
-#define TOVF                0x0020  /* Sticky Transmit Overflow Status                      */
-#define TXHRE               0x0040  /* Transmit Hold Register Empty                     */
-
-/* SPORTx_MCMC1 Macros */
-#ifdef _MISRA_RULES
-#define WOFF(x)     ((x) & 0x3FFu)      /* Multichannel Window Offset Field                     */
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/
-#define WSIZE(x)        (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1               */
-#else
-#define WOFF(x)     ((x) & 0x3FF)       /* Multichannel Window Offset Field                     */
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                */
-#define WSIZE(x)    (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1                   */
-#endif /* _MISRA_RULES */
-
-/* SPORTx_MCMC2 Masks */
-#define REC_BYPASS          0x0000  /* Bypass Mode (No Clock Recovery)                      */
-#define REC_2FROM4          0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16         0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                    */
-#define MCDTXPE             0x0004  /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE             0x0008  /* Multichannel DMA Receive Packing                     */
-#define MCMEN               0x0010  /* Multichannel Frame Mode Enable                       */
-#define FSDR                0x0080  /* Multichannel Frame Sync to Data Relationship             */
-#define MFD_0               0x0000  /* Multichannel Frame Delay = 0                     */
-#define MFD_1               0x1000  /* Multichannel Frame Delay = 1                     */
-#define MFD_2               0x2000  /* Multichannel Frame Delay = 2                     */
-#define MFD_3               0x3000  /* Multichannel Frame Delay = 3                     */
-#define MFD_4               0x4000  /* Multichannel Frame Delay = 4                     */
-#define MFD_5               0x5000  /* Multichannel Frame Delay = 5                     */
-#define MFD_6               0x6000  /* Multichannel Frame Delay = 6                     */
-#define MFD_7               0x7000  /* Multichannel Frame Delay = 7                     */
-#define MFD_8               0x8000  /* Multichannel Frame Delay = 8                     */
-#define MFD_9               0x9000  /* Multichannel Frame Delay = 9                     */
-#define MFD_10              0xA000  /* Multichannel Frame Delay = 10                        */
-#define MFD_11              0xB000  /* Multichannel Frame Delay = 11                        */
-#define MFD_12              0xC000  /* Multichannel Frame Delay = 12                        */
-#define MFD_13              0xD000  /* Multichannel Frame Delay = 13                        */
-#define MFD_14              0xE000  /* Multichannel Frame Delay = 14                        */
-#define MFD_15              0xF000  /* Multichannel Frame Delay = 15                        */
-
-
-/***********************************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ***************************************/
-
-/* EBIU_AMGCTL Masks */
-#define AMCKEN                  0x0001  /* Enable CLKOUT                                         */
-#define AMBEN                   0x0002  /* Enable Asynchronous memory bank                       */
-#define AMBEN_NONE              0x0000  /* All Banks Disabled                                    */
-
-#define AMBEN_B0        (AMBEN) /* Enable Async Memory Bank 0 only          */
-
-#define AMBEN_ALL               0x0002  /* Enable Asynchronous memory bank                       */
-#define CDPRIO                  0x0100  /* DMA has priority over core for for external accesses  */
-
-/* EBIU_AMBCTL Masks */
-#define RDYEN               0x00000001  /* ARDY Enable                                           */
-#define RDYPOL              0x00000002  /* RDY Active High                                       */
-#define TT_1                0x00000004  /* Transition Time (Read to Write) = 1 cycle             */
-#define TT_2                0x00000008  /* Transition Time (Read to Write) = 2 cycles            */
-#define TT_3                0x0000000C  /* Transition Time (Read to Write) = 3 cycles            */
-#define TT_4                0x00000000  /* Transition Time (Read to Write) = 4 cycles            */
-#define ST_1                0x00000010  /* Setup Time (AOE to Read/Write) = 1 cycle              */
-#define ST_2                0x00000020  /* Setup Time (AOE to Read/Write) = 2 cycles             */
-#define ST_3                0x00000030  /* Setup Time (AOE to Read/Write) = 3 cycles             */
-#define ST_4                0x00000000  /* Setup Time (AOE to Read/Write) = 4 cycles             */
-#define HT_1                0x00000040  /* Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define HT_2                0x00000080  /* Hold Time (~Read/Write to ~AOE) = 2 cycles            */
-#define HT_3                0x000000C0  /* Hold Time (~Read/Write to ~AOE) = 3 cycles            */
-#define HT_0                0x00000000  /* Hold Time (~Read/Write to ~AOE) = 0 cycles            */
-#define RAT_1               0x00000100  /* Read Access Time = 1 cycle                            */
-#define RAT_2               0x00000200  /* Read Access Time = 2 cycles                           */
-#define RAT_3               0x00000300  /* Read Access Time = 3 cycles                           */
-#define RAT_4               0x00000400  /* Read Access Time = 4 cycles                           */
-#define RAT_5               0x00000500  /* Read Access Time = 5 cycles                           */
-#define RAT_6               0x00000600  /* Read Access Time = 6 cycles                           */
-#define RAT_7               0x00000700  /* Read Access Time = 7 cycles                           */
-#define RAT_8               0x00000800  /* Read Access Time = 8 cycles                           */
-#define RAT_9               0x00000900  /* Read Access Time = 9 cycles                           */
-#define RAT_10              0x00000A00  /* Read Access Time = 10 cycles                          */
-#define RAT_11              0x00000B00  /* Read Access Time = 11 cycles                          */
-#define RAT_12              0x00000C00  /* Read Access Time = 12 cycles                          */
-#define RAT_13              0x00000D00  /* Read Access Time = 13 cycles                          */
-#define RAT_14              0x00000E00  /* Read Access Time = 14 cycles                          */
-#define RAT_15              0x00000F00  /* Read Access Time = 15 cycles                          */
-#define WAT_1               0x00001000  /* Write Access Time = 1 cycle                           */
-#define WAT_2               0x00002000  /* Write Access Time = 2 cycles                          */
-#define WAT_3               0x00003000  /* Write Access Time = 3 cycles                          */
-#define WAT_4               0x00004000  /* Write Access Time = 4 cycles                          */
-#define WAT_5               0x00005000  /* Write Access Time = 5 cycles                          */
-#define WAT_6               0x00006000  /* Write Access Time = 6 cycles                          */
-#define WAT_7               0x00007000  /* Write Access Time = 7 cycles                          */
-#define WAT_8               0x00008000  /* Write Access Time = 8 cycles                          */
-#define WAT_9               0x00009000  /* Write Access Time = 9 cycles                          */
-#define WAT_10              0x0000A000  /* Write Access Time = 10 cycles                         */
-#define WAT_11              0x0000B000  /* Write Access Time = 11 cycles                         */
-#define WAT_12              0x0000C000  /* Write Access Time = 12 cycles                         */
-#define WAT_13              0x0000D000  /* Write Access Time = 13 cycles                         */
-#define WAT_14              0x0000E000  /* Write Access Time = 14 cycles                         */
-#define WAT_15              0x0000F000  /* Write Access Time = 15 cycles                         */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN             (RDYEN)     /* Bank 0 (B0) RDY Enable                                */
-#define B0RDYPOL            (RDYPOL)    /* B0 RDY Active High                                    */
-#define B0TT_1              (TT_1)      /* B0 Transition Time (Read to Write) = 1 cycle          */
-#define B0TT_2              (TT_2)      /* B0 Transition Time (Read to Write) = 2 cycles         */
-#define B0TT_3              (TT_3)      /* B0 Transition Time (Read to Write) = 3 cycles         */
-#define B0TT_4              (TT_4)      /* B0 Transition Time (Read to Write) = 4 cycles         */
-#define B0ST_1              (ST_1)      /* B0 Setup Time (AOE to Read/Write) = 1 cycle           */
-#define B0ST_2              (ST_2)      /* B0 Setup Time (AOE to Read/Write) = 2 cycles          */
-#define B0ST_3              (ST_3)      /* B0 Setup Time (AOE to Read/Write) = 3 cycles          */
-#define B0ST_4              (ST_4)      /* B0 Setup Time (AOE to Read/Write) = 4 cycles          */
-#define B0HT_1              (HT_1)      /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle          */
-#define B0HT_2              (HT_2)      /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles         */
-#define B0HT_3              (HT_3)      /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles         */
-#define B0HT_0              (HT_0)      /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles         */
-#define B0RAT_1             (RAT_1)     /* B0 Read Access Time = 1 cycle                         */
-#define B0RAT_2             (RAT_2)     /* B0 Read Access Time = 2 cycles                        */
-#define B0RAT_3             (RAT_3)     /* B0 Read Access Time = 3 cycles                        */
-#define B0RAT_4             (RAT_4)     /* B0 Read Access Time = 4 cycles                        */
-#define B0RAT_5             (RAT_5)     /* B0 Read Access Time = 5 cycles                        */
-#define B0RAT_6             (RAT_6)     /* B0 Read Access Time = 6 cycles                        */
-#define B0RAT_7             (RAT_7)     /* B0 Read Access Time = 7 cycles                        */
-#define B0RAT_8             (RAT_8)     /* B0 Read Access Time = 8 cycles                        */
-#define B0RAT_9             (RAT_9)     /* B0 Read Access Time = 9 cycles                        */
-#define B0RAT_10            (RAT_10)    /* B0 Read Access Time = 10 cycles                       */
-#define B0RAT_11            (RAT_11)    /* B0 Read Access Time = 11 cycles                       */
-#define B0RAT_12            (RAT_12)    /* B0 Read Access Time = 12 cycles                       */
-#define B0RAT_13            (RAT_13)    /* B0 Read Access Time = 13 cycles                       */
-#define B0RAT_14            (RAT_14)    /* B0 Read Access Time = 14 cycles                       */
-#define B0RAT_15            (RAT_15)    /* B0 Read Access Time = 15 cycles                       */
-#define B0WAT_1             (WAT_1)     /* B0 Write Access Time = 1 cycle                        */
-#define B0WAT_2             (WAT_2)     /* B0 Write Access Time = 2 cycles                       */
-#define B0WAT_3             (WAT_3)     /* B0 Write Access Time = 3 cycles                       */
-#define B0WAT_4             (WAT_4)     /* B0 Write Access Time = 4 cycles                       */
-#define B0WAT_5             (WAT_5)     /* B0 Write Access Time = 5 cycles                       */
-#define B0WAT_6             (WAT_6)     /* B0 Write Access Time = 6 cycles                       */
-#define B0WAT_7             (WAT_7)     /* B0 Write Access Time = 7 cycles                       */
-#define B0WAT_8             (WAT_8)     /* B0 Write Access Time = 8 cycles                       */
-#define B0WAT_9             (WAT_9)     /* B0 Write Access Time = 9 cycles                       */
-#define B0WAT_10            (WAT_10)    /* B0 Write Access Time = 10 cycles                      */
-#define B0WAT_11            (WAT_11)    /* B0 Write Access Time = 11 cycles                      */
-#define B0WAT_12            (WAT_12)    /* B0 Write Access Time = 12 cycles                      */
-#define B0WAT_13            (WAT_13)    /* B0 Write Access Time = 13 cycles                      */
-#define B0WAT_14            (WAT_14)    /* B0 Write Access Time = 14 cycles                      */
-#define B0WAT_15            (WAT_15)    /* B0 Write Access Time = 15 cycles                      */
-
-
-/* Bit masks for EBIU_MODE */
-
-#define B0MODE              0x3         /* Async Memory Bank Access Mode                         */
-
-/* Bit masks for EBIU_MODE */
-#define MODE_ASYNC          0x00000000  /* Access Mode - 00 - Asynchronous Mode                  */
-#define MODE_FLASH          0x00000001  /* Access Mode - 01 - Asynchronous Flash Mode            */
-#define MODE_BURST          0x00000003  /* Access Mode - 11 - Synchronous (Burst) Mode           */
-
-/* legacy bit fields (below) provided for backwards code compatibility */
-#define B0MODE_ASYNC          (MODE_ASYNC)
-#define B0MODE_FLASH          (MODE_FLASH)
-#define B0MODE_BURST          (MODE_BURST)
-
-/* Bit masks for EBIU_FCTL (BCLK) */
-#define BCLK2               0x00000002  /* Burst clock frequency: 01 - SCLK/2                    */
-#define BCLK3               0x00000004  /* Burst clock frequency: 10 - SCLK/3                    */
-#define BCLK4               0x00000006  /* Burst clock frequency: 11 - SCLK/4                    */
-
-
-/****************************************  DMA CONTROLLER MASKS  **************************************************/
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN               0x0001  /* DMA Channel Enable                               */
-#define WNR                 0x0002  /* Channel Direction (W/R*)                         */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8                           */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16                          */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32                          */
-#define DMA2D               0x0010  /* DMA Mode (2D/1D*)                                */
-#define SYNC                0x0020  /* DMA Buffer Clear                             */
-#define DI_SEL              0x0040  /* Data Interrupt Timing Select                     */
-#define DI_EN               0x0080  /* Data Interrupt Enable                            */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)               */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                         */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                         */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                         */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                         */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                         */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                         */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                         */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                         */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                         */
-#define FLOW_STOP               0x0000  /* Stop Mode                                    */
-#define FLOW_AUTO               0x1000  /* Autobuffer Mode                              */
-#define FLOW_ARRAY          0x4000  /* Descriptor Array Mode                            */
-#define FLOW_SMALL          0x6000  /* Small Model Descriptor List Mode                     */
-#define FLOW_LARGE          0x7000  /* Large Model Descriptor List Mode                     */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral)        */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                     */
-#define PMAP_PPI                0x0000  /* PPI Port DMA                                          */
-#define PMAP_RSI                0x1000  /* RSI DMA                                               */
-#define PMAP_SPORT0RX           0x2000  /* SPORT0 Receive DMA                                    */
-#define PMAP_SPORT0TX           0x3000  /* SPORT0 Transmit DMA                                   */
-#define PMAP_SPORT1RX           0x4000  /* SPORT1 Receive DMA                                    */
-#define PMAP_SPORT1TX           0x5000  /* SPORT1 Transmit DMA                                   */
-#define PMAP_SPI0               0x6000  /* SPI0 Transmit/Receive DMA                             */
-#define PMAP_SPI1               0x7000  /* SPI1 Transmit/Receive DMA                             */
-#define PMAP_UART0RX            0x8000  /* UART0 Port Receive DMA                                */
-#define PMAP_UART0TX            0x9000  /* UART0 Port Transmit DMA                               */
-#define PMAP_UART1RX            0xA000  /* UART1 Port Receive DMA                                */
-#define PMAP_UART1TX            0xB000  /* UART1 Port Transmit DMA                               */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status                      */
-#define DMA_ERR             0x0002  /* DMA Error Interrupt Status                           */
-#define DFETCH              0x0004  /* DMA Descriptor Fetch Indicator                       */
-#define DMA_RUN             0x0008  /* DMA Channel Running Indicator                        */
-
-
-/*********************************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/
-
-/*  PPI_CONTROL Masks */
-#define PORT_EN             0x0001  /* PPI Port Enable                              */
-#define PORT_DIR                0x0002  /* PPI Port Direction                               */
-#define XFR_TYPE                0x000C  /* PPI Transfer Type                                */
-#define PORT_CFG                0x0030  /* PPI Port Configuration                           */
-#define FLD_SEL             0x0040  /* PPI Active Field Select                          */
-#define PACK_EN             0x0080  /* PPI Packing Mode                             */ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN             0x0200  /* PPI Skip Element Enable                          */
-#define SKIP_EO             0x0400  /* PPI Skip Even/Odd Elements                           */
-#define DLEN_8              0x0000  /* Data Length = 8 Bits                             */
-#define DLEN_10             0x0800  /* Data Length = 10 Bits                            */
-#define DLEN_11             0x1000  /* Data Length = 11 Bits                            */
-#define DLEN_12             0x1800  /* Data Length = 12 Bits                            */
-#define DLEN_13             0x2000  /* Data Length = 13 Bits                            */
-#define DLEN_14             0x2800  /* Data Length = 14 Bits                            */
-#define DLEN_15             0x3000  /* Data Length = 15 Bits                            */
-#define DLEN_16             0x3800  /* Data Length = 16 Bits                            */
-#define POLC                0x4000  /* PPI Clock Polarity                               */
-#define POLS                0x8000  /* PPI Frame Sync Polarity                          */
-
-/* PPI_STATUS Masks */
-#define LT_ERR_OVR          0x0100  /* Line Track Overflow Error                            */
-#define LT_ERR_UNDR         0x0200  /* Line Track Underflow Error                           */
-#define FLD                 0x0400  /* Field Indicator                              */
-#define FT_ERR              0x0800  /* Frame Track Error                                */
-#define OVR                 0x1000  /* FIFO Overflow Error                              */
-#define UNDR                0x2000  /* FIFO Underrun Error                              */
-#define ERR_DET             0x4000  /* Error Detected Indicator                         */
-#define ERR_NCOR                0x8000  /* Error Not Corrected Indicator                        */
-
-
-/***************************************  TWO-WIRE INTERFACE (TWI) MASKS  *****************************************/
-
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)               ((x) & 0xFFu)/* Periods Clock Is Held Low                           */
-#define CLKHI(y)                (((y)&0xFFu)<<0x8)/* Periods Before New Clock Low                   */
-#else
-#define CLKLOW(x)               ((x) & 0xFF)/* Periods Clock Is Held Low                            */
-#define CLKHI(y)                (((y)&0xFF)<<0x8)   /* Periods Before New Clock Low                 */
-#endif /* _MISRA_RULES */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE                0x007F  /* SCLKs Per Internal Time Reference (10MHz)                */
-#define TWI_ENA             0x0080  /* TWI Enable                                   */
-#define SCCB                0x0200  /* SCCB Compatibility Enable                            */
-
-/* TWI_SLAVE_CTRL Masks */
-#define SEN                 0x0001  /* Slave Enable                                 */
-#define SADD_LEN                0x0002  /* Slave Address Length                             */
-#define STDVAL              0x0004  /* Slave Transmit Data Valid                            */
-#define NAK                 0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer             */
-#define GEN                 0x0010  /* General Call Adrress Matching Enabled                    */
-
-/* TWI_SLAVE_STAT Masks */
-#define SDIR                0x0001  /* Slave Transfer Direction (Transmit/Receive*)             */
-#define GCALL               0x0002  /* General Call Indicator                           */
-
-/* TWI_MASTER_CTRL Masks */
-#define MEN                 0x0001  /* Master Mode Enable                               */
-#define MADD_LEN                0x0002  /* Master Address Length                            */
-#define MDIR                0x0004  /* Master Transmit Direction (RX/TX*)                   */
-#define FAST                0x0008  /* Use Fast Mode Timing Specs                           */
-#define STOP                0x0010  /* Issue Stop Condition                             */
-#define RSTART              0x0020  /* Repeat Start or Stop* At End Of Transfer             */
-#define DCNT                0x3FC0  /* Data Bytes To Transfer                           */
-#define SDAOVR              0x4000  /* Serial Data Override                             */
-#define SCLOVR              0x8000  /* Serial Clock Override                            */
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG               0x0001  /* Master Transfer In Progress                      */
-#define LOSTARB             0x0002  /* Lost Arbitration Indicator (Xfer Aborted)                */
-#define ANAK                0x0004  /* Address Not Acknowledged                         */
-#define DNAK                0x0008  /* Data Not Acknowledged                            */
-#define BUFRDERR                0x0010  /* Buffer Read Error                                */
-#define BUFWRERR                0x0020  /* Buffer Write Error                               */
-#define SDASEN              0x0040  /* Serial Data Sense                                */
-#define SCLSEN              0x0080  /* Serial Clock Sense                               */
-#define BUSBUSY             0x0100  /* Bus Busy Indicator                               */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT               0x0001  /* Slave Transfer Initiated                         */
-#define SCOMP               0x0002  /* Slave Transfer Complete                          */
-#define SERR                0x0004  /* Slave Transfer Error                             */
-#define SOVF                0x0008  /* Slave Overflow                                   */
-#define MCOMP               0x0010  /* Master Transfer Complete                         */
-#define MERR                0x0020  /* Master Transfer Error                            */
-#define XMTSERV             0x0040  /* Transmit FIFO Service                            */
-#define RCVSERV             0x0080  /* Receive FIFO Service                             */
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH                0x0001  /* Transmit Buffer Flush                            */
-#define RCVFLUSH                0x0002  /* Receive Buffer Flush                             */
-#define XMTINTLEN               0x0004  /* Transmit Buffer Interrupt Length                     */
-#define RCVINTLEN               0x0008  /* Receive Buffer Interrupt Length                      */
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT             0x0003  /* Transmit FIFO Status                             */
-#define XMT_EMPTY               0x0000  /* Transmit FIFO Empty                              */
-#define XMT_HALF                0x0001  /* Transmit FIFO Has 1 Byte To Write                    */
-#define XMT_FULL                0x0003  /* Transmit FIFO Full (2 Bytes To Write)                    */
-
-#define RCVSTAT             0x000C  /* Receive FIFO Status                              */
-#define RCV_EMPTY               0x0000  /* Receive FIFO Empty                               */
-#define RCV_HALF                0x0004  /* Receive FIFO Has 1 Byte To Read                      */
-#define RCV_FULL                0x000C  /* Receive FIFO Full (2 Bytes To Read)                  */
-
-
-/*************************************  STACKED FLASH REGISTER MASKS AND DEFINITIONS ******************************/
-
-#define FLASH_ENABLE            0x0001  /* Enable stacked flash for reads/writes or reset flash  */
-#define FLASH_UNPROTECT         0x0100  /* Protect/unprotect stacked flash from programming/erase */
-#define FLASH_UNLOCK            0x8000  /* Enable/disable the setting of the upper byte of FLASH_CONTROL */
-
-#define FLASH_BASE_ADDRESS 0x20000000
-
-
-
-/****************************************   COUNTER MASKS    ******************************************************/
-
-/* Bit masks for CNT_CONFIG */
-#define CNTE                0x1        /* Counter Enable                                    */
-#define nCNTE               0x0
-#define DEBE                0x2        /* Debounce Enable                               */
-#define nDEBE               0x0
-#define CDGINV                  0x10       /* CDG Pin Polarity Invert                           */
-#define nCDGINV                 0x0
-#define CUDINV                  0x20       /* CUD Pin Polarity Invert                           */
-#define nCUDINV                 0x0
-#define CZMINV                  0x40       /* CZM Pin Polarity Invert                           */
-#define nCZMINV                 0x0
-#define CNTMODE                 0x700      /* Counter Operating Mode                            */
-#define ZMZC                0x800      /* CZM Zeroes Counter Enable                             */
-#define nZMZC               0x0
-#define BNDMODE                 0x3000     /* Boundary register Mode                            */
-#define INPDIS                  0x8000     /* CUG and CDG Input Disable                             */
-#define nINPDIS                 0x0
-
-/* Bit masks for CNT_IMASK */
-#define ICIE                0x1        /* Illegal Gray/Binary Code Interrupt Enable                 */
-#define nICIE               0x0
-#define UCIE                0x2        /* Up count Interrupt Enable                             */
-#define nUCIE               0x0
-#define DCIE                0x4        /* Down count Interrupt Enable                       */
-#define nDCIE               0x0
-#define MINCIE                  0x8        /* Min Count Interrupt Enable                            */
-#define nMINCIE                 0x0
-#define MAXCIE                  0x10       /* Max Count Interrupt Enable                            */
-#define nMAXCIE                 0x0
-#define COV31IE                 0x20       /* Bit 31 Overflow Interrupt Enable                      */
-#define nCOV31IE            0x0
-#define COV15IE                 0x40       /* Bit 15 Overflow Interrupt Enable                      */
-#define nCOV15IE            0x0
-#define CZEROIE                 0x80       /* Count to Zero Interrupt Enable                        */
-#define nCZEROIE            0x0
-#define CZMIE               0x100      /* CZM Pin Interrupt Enable                          */
-#define nCZMIE              0x0
-#define CZMEIE                  0x200      /* CZM Error Interrupt Enable                            */
-#define nCZMEIE                 0x0
-#define CZMZIE                  0x400      /* CZM Zeroes Counter Interrupt Enable                   */
-#define nCZMZIE                 0x0
-
-/* Bit masks for CNT_STATUS */
-#define ICII                0x1        /* Illegal Gray/Binary Code Interrupt Identifier             */
-#define nICII               0x0
-#define UCII                0x2        /* Up count Interrupt Identifier                         */
-#define nUCII               0x0
-#define DCII                0x4        /* Down count Interrupt Identifier                       */
-#define nDCII               0x0
-#define MINCII                  0x8        /* Min Count Interrupt Identifier                        */
-#define nMINCII                 0x0
-#define MAXCII                  0x10       /* Max Count Interrupt Identifier                        */
-#define nMAXCII                 0x0
-#define COV31II                 0x20       /* Bit 31 Overflow Interrupt Identifier                  */
-#define nCOV31II            0x0
-#define COV15II                 0x40       /* Bit 15 Overflow Interrupt Identifier                  */
-#define nCOV15II            0x0
-#define CZEROII                 0x80       /* Count to Zero Interrupt Identifier                    */
-#define nCZEROII            0x0
-#define CZMII               0x100      /* CZM Pin Interrupt Identifier                      */
-#define nCZMII                  0x0
-#define CZMEII                  0x200      /* CZM Error Interrupt Identifier                        */
-#define nCZMEII                 0x0
-#define CZMZII                  0x400      /* CZM Zeroes Counter Interrupt Identifier               */
-#define nCZMZII                 0x0
-
-/* Bit masks for CNT_COMMAND */
-#define W1LCNT                  0xf        /* Load Counter Register                             */
-#define W1LMIN                  0xf0       /* Load Min Register                                 */
-#define W1LMAX                  0xf00      /* Load Max Register                                 */
-#define W1ZMONCE            0x1000     /* Enable CZM Clear Counter Once                         */
-#define nW1ZMONCE           0x0
-
-/* Bit masks for CNT_DEBOUNCE */
-#define DPRESCALE               0xf        /* Load Counter Register                             */
-
-
-/**********************************************  PWM Masks  *******************************************************/
-
-/* Bit masks for PWM_CTRL */
-#define PWM_EN              0x1     /* PWM Enable                                   */
-#define PWM_SYNC_EN             0X2     /* Enable Sync Enable                               */
-#define PWM_DBL                 0x4     /* Double Update Mode                               */
-#define PWM_EXTSYNC         0x8     /* External Sync                                    */
-#define PWM_SYNCSEL             0x10        /* External Sync Select                             */
-#define PWM_POLARITY            0x20        /* PWM Output Polarity                              */
-#define PWM_SRMODE          0x40        /* PWM SR MODE                                  */
-#define PWMTRIPINT_EN           0x80        /* Trip Interrupt Enable                            */
-#define PWMSYNCINT_EN           0x100       /* Sync Interrupt Enable                            */
-#define PWMTRIP_DSBL            0x200           /* Trip Input Disable                               */
-
-/* Bit masks for PWM_STAT */
-#define PWM_PHASE               0x1     /* PWM phase                                    */
-#define PWM_POL                 0x2     /* PWM polarity                                     */
-#define PWM_SR              0x4     /* PWM SR mode                                  */
-#define PWM_TRIP                0x8     /* PWM Trip mode                                    */
-#define PWM_TRIPINT         0x100       /* PWM Trip Interrupt                               */
-#define PWM_SYNCINT         0x200       /* PWM Sync Interrupt                               */
-
-/* Bit masks for PWMGATE Register */
-
-#define CHOPHI              0x100       /* Gate Chopping Enable High Side                       */
-#define CHOPLO              0x200       /* Gate Chopping Enable Low Side                        */
-
-/* Bit masks for PWMSEG Register */
-
-#define CH_EN               0x1     /* CH output Enable                                 */
-#define CL_EN               0x2     /* CL output Enable                                 */
-#define BH_EN               0x4     /* BH output Enable                                 */
-#define BL_EN               0x8     /* BL output Enable                             */
-#define AH_EN               0x10        /* AH output Enable                                 */
-#define AL_EN               0x20        /* AL output Enable                                 */
-#define CHCL_XOVR           0x40        /* Channel C output Crossover                       */
-#define BHBL_XOVR           0x80        /* Channel B output Crossover                       */
-#define AHAL_XOVR           0x100       /* Channel A output Crossover                       */
-
-/* Bit masks for PWMLSI Register */
-#define PWM_SR_LSI_A            0x1     /* PWM SR Low Side Invert Channel A                     */
-#define PWM_SR_LSI_B            0x2     /* PWM SR Low Side Invert Channel A                     */
-#define PWM_SR_LSI_C            0x4     /* PWM SR Low Side Invert Channel A                     */
-
-/* Bit masks for PWM_STAT2 Register */
-#define PWM_AL              0x1     /* pwm_al output signal for S/W observation                 */
-#define PWM_AH              0x2     /* pwm_ah output signal for S/W observation                 */
-#define PWM_BL              0x4     /* pwm_bl output signal for S/W observation                 */
-#define PWM_BH              0x8     /* pwm_bh output signal for S/W observation                 */
-#define PWM_CL              0x10        /* pwm_cl output signal for S/W observation                 */
-#define PWM_CH              0x20        /* pwm_ch output signal for S/W observation                 */
-
-
-/***********************************  RSI MASKS  ************************************/
-
-/* Bit masks for RSI_PWR_CONTROL */
-#define                    PWR_ON  0x3              /* Power On */
-#define                RSI_CMD_OD  0x40             /* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 SD_CMD_OD  (RSI_CMD_OD)     /* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nSD_CMD_OD  0x0
-/* legacy bit mask (below) provided for backwards code compatibility */
-#if 0
-#define                       TBD  0x3c             /* TBD */
-#endif
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   ROD_CTL  0x80
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nROD_CTL  0x80
-
-
-/* Bit masks for RSI_CLK_CONTROL */
-#define                    CLKDIV  0xff             /* MC_CLK Divisor */
-#define                    CLK_EN  0x100            /* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CLK_E  (CLK_EN)         /* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCLK_E  0x0
-#define                 PWR_SV_EN  0x200            /* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  PWR_SV_E  (PWR_SV_EN)      /* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400            /* Bypass Divisor */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCLKDIV_BYPASS  0x0
-#define                  BUS_MODE  0x1800           /* Bus width selection */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  WIDE_BUS  0x0800       /* Wide Bus Mode Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nWIDE_BUS  0x0
-
-
-/* Bit masks for RSI_COMMAND */
-#define                   CMD_IDX  0x3f             /* Command Index */
-#define                CMD_RSP_EN  0x40             /* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CMD_RSP  (CMD_RSP_EN)     /* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_RSP  0x0
-#define               CMD_LRSP_EN  0x80             /* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_L_RSP  (CMD_LRSP_EN)    /* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_L_RSP  0x0
-#define                CMD_INT_EN  0x100            /* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_INT_E  (CMD_INT_EN)     /* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_INT_E  0x0
-#define               CMD_PEND_EN  0x200            /* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                CMD_PEND_E  (CMD_PEND_EN)    /* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nCMD_PEND_E  0x0
-#define                    CMD_EN  0x400            /* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CMD_E  (CMD_EN)         /* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCMD_E  0x0
-
-
-/* Bit masks for RSI_RESP_CMD */
-#define                  RESP_CMD  0x3f             /* Response Command */
-
-/* Bit masks for RSI_DATA_LGTH */
-#define               DATA_LENGTH  0xffff           /* Data Length */
-
-
-/* Bit masks for RSI_DATA_CONTROL */
-#define                   DATA_EN  0x1              /* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     DTX_E  (DATA_EN)        /* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nDTX_E  0x0
-#define                  DATA_DIR  0x2              /* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   DTX_DIR  (DATA_DIR)       /* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDTX_DIR  0x0
-#define                 DATA_MODE  0x4              /* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  DTX_MODE  (DATA_MODE)      /* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nDTX_MODE  0x0
-#define               DATA_DMA_EN  0x8              /* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 DTX_DMA_E  0x8              /* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nDTX_DMA_E  0x0
-#define             DATA_BLK_LGTH  0xf0             /* Data Transfer Block Length */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              DTX_BLK_LGTH  0xf0             /* Data Transfer Block Length */
-#define                      CEATA_EN  0x100          /* CE-ATA operation mode enable */
-#define                  CEATA_CCS_EN  0x200          /* CE-ATA CCS mode enable */
-
-/* Bit masks for RSI_DATA_CNT */
-#define               DATA_COUNT  0xffff            /* Data Count */
-
-/* Bit masks for RSI_STATUS */
-#define              CMD_CRC_FAIL  0x1              /* CMD CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2              /* Data CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4              /* CMD Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8              /* Data Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10             /* Transmit Underrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20             /* Receive Overrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40             /* CMD Response End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80             /* CMD Sent */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100            /* Data End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200            /* Start Bit Error */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400            /* Data Block End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800            /* CMD Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000           /* Transmit Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000           /* Receive Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000           /* Transmit FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000           /* Receive FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000          /* Transmit FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000          /* Receive FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000          /* Transmit FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000          /* Receive FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000         /* Transmit Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000         /* Receive Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for RSI_STATCL */
-
-#define         CMD_CRC_FAIL_STAT  0x1              /* CMD CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2              /* Data CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4              /* CMD Time Out Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8              /* Data Time Out status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10             /* Transmit Underrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20             /* Receive Overrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40             /* CMD Response End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80             /* CMD Sent Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100            /* Data End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200            /* Start Bit Error Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400            /* Data Block End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for RSI_MASKx */
-
-#define         CMD_CRC_FAIL_MASK  0x1              /* CMD CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2              /* Data CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4              /* CMD Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8              /* Data Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10             /* Transmit Underrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20             /* Receive Overrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40             /* CMD Response End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80             /* CMD Sent Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100            /* Data End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200            /* Start Bit Error Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400            /* Data Block End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800            /* CMD Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000           /* Transmit Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000           /* Receive Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000           /* Transmit FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000           /* Receive FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000          /* Transmit FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000          /* Receive FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000          /* Transmit FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000          /* Receive FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000         /* Transmit Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000         /* Receive Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for RSI_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff           /* FIFO Count */
-
-/* Bit masks for RSI_CEATA_CONTROL */
-#define       CEATA_TX_CCSD  0x1                /* Send CE-ATA CCSD sequence */
-
-/* Bit masks for RSI_ESTAT */
-#define              SDIO_INT_DET  0x2              /* SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10             /* SD Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nSD_CARD_DET  0x0
-#define             CEATA_INT_DET  0x20
-
-/* Bit masks for RSI_EMASK */
-#define         SDIO_INT_DET_MASK  0x2                /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SDIO_MSK  (SDIO_INT_DET_MASK)/* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nSDIO_MSK  0x0
-#define          SD_CARD_DET_MASK  0x10               /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SCD_MASK  (SD_CARD_DET_MASK) /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nSCD_MSK  0x0
-#define        CEATA_INT_DET_MASK  0x20
-
-
-/* Bit masks for SDH_CFG */
-
-/* Left in for backwards compatibility */
-#define                RSI_CLK_EN  0x1
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CLKS_EN  (RSI_CLK_EN)         /* Clocks Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCLKS_EN  0x0
-#define                  SDIO4_EN  0x4              /* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      SD4E  (SDIO4_EN)       /* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     nSD4E  0x0
-#define                     MW_EN  0x8              /* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       MWE  (MW_EN)          /* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nMWE  0x0
-#define                   RSI_RST  0x10             /* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    SD_RST  (RSI_RST)        /* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nSD_RST  0x0
-#define                    PU_DAT  0x20             /* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PUP_SDDAT  (PU_DAT)         /* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPUP_SDDAT  0x0
-#define                   PU_DAT3  0x40             /* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                PUP_SDDAT3  (PU_DAT3)        /* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nPUP_SDDAT3  0x0
-#define                   PD_DAT3  0x80             /* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PD_SDDAT3  (PD_DAT3)        /* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPD_SDDAT3  0x0
-
-
-/* Bit masks for RSI_RD_WAIT_EN */
-#define          SDIO_RWR  0x1              /* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       RWR  (SDIO_RWR)       /* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nRWR  0x0
-
-/* Bit masks for RSI_PIDx */
-#define                   RSI_PID  0xff         /* RSI Peripheral ID */
-
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-
-/* CAN_CONTROL Masks                                                */
-#define SRS         0x0001  /* Software Reset                       */
-#define DNM         0x0002  /* Device Net Mode                      */
-#define ABO         0x0004  /* Auto-Bus On Enable                   */
-#define WBA         0x0010  /* Wake-Up On CAN Bus Activity Enable   */
-#define SMR         0x0020  /* Sleep Mode Request                   */
-#define CSR         0x0040  /* CAN Suspend Mode Request             */
-#define CCR         0x0080  /* CAN Configuration Mode Request       */
-
-/* CAN_STATUS Masks                                             */
-#define WT          0x0001  /* TX Warning Flag                  */
-#define WR          0x0002  /* RX Warning Flag                  */
-#define EP          0x0004  /* Error Passive Mode               */
-#define EBO         0x0008  /* Error Bus Off Mode               */
-#define CSA         0x0040  /* Suspend Mode Acknowledge         */
-#define CCA         0x0080  /* Configuration Mode Acknowledge   */
-#define MBPTR       0x1F00  /* Mailbox Pointer                  */
-#define TRM         0x4000  /* Transmit Mode                    */
-#define REC         0x8000  /* Receive Mode                     */
-
-/* CAN_CLOCK Masks                                  */
-#define BRP         0x03FF  /* Bit-Rate Pre-Scaler  */
-
-/* CAN_TIMING Masks                                         */
-#define TSEG1       0x000F  /* Time Segment 1               */
-#define TSEG2       0x0070  /* Time Segment 2               */
-#define SAM         0x0080  /* Sampling                     */
-#define SJW         0x0300  /* Synchronization Jump Width   */
-
-/* CAN_DEBUG Masks                                          */
-#define DEC         0x0001  /* Disable CAN Error Counters   */
-#define DRI         0x0002  /* Disable CAN RX Input         */
-#define DTO         0x0004  /* Disable CAN TX Output        */
-#define DIL         0x0008  /* Disable CAN Internal Loop    */
-#define MAA         0x0010  /* Mode Auto-Acknowledge Enable */
-#define MRB         0x0020  /* Mode Read Back Enable        */
-#define CDE         0x8000  /* CAN Debug Enable             */
-
-/* CAN_CEC Masks                                        */
-#define RXECNT      0x00FF  /* Receive Error Counter    */
-#define TXECNT      0xFF00  /* Transmit Error Counter   */
-
-/* CAN_INTR Masks                                           */
-#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt    */
-#define MBRIF       (MBRIRQ) /* legacy */
-#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt   */
-#define MBTIF       (MBTIRQ) /* legacy */
-#define GIRQ        0x0004  /* Global Interrupt             */
-#define SMACK       0x0008  /* Sleep Mode Acknowledge       */
-#define CANTX       0x0040  /* CAN TX Bus Value             */
-#define CANRX       0x0080  /* CAN RX Bus Value             */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks                                      */
-#define DFC         0xFFFF  /* Data Filtering Code (If Enabled) (ID0)       */
-#define EXTID_LO    0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0)   */
-#define EXTID_HI    0x0003  /* Upper 2 Bits of Extended Identifier (ID1)    */
-#define BASEID      0x1FFC  /* Base Identifier                              */
-#define IDE         0x2000  /* Identifier Extension                         */
-#define RTR         0x4000  /* Remote Frame Transmission Request            */
-#define AME         0x8000  /* Acceptance Mask Enable                       */
-
-/* CAN_MBxx_TIMESTAMP Masks                 */
-#define TSV         0xFFFF  /* Timestamp    */
-
-/* CAN_MBxx_LENGTH Masks                        */
-#define DLC         0x000F  /* Data Length Code */
-
-/* CAN_AMxxH and CAN_AMxxL Masks                                                */
-#define DFM         0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL)         */
-#define EXTID_LO    0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
-#define EXTID_HI    0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH)  */
-#define BASEID      0x1FFC  /* Base Identifier                                  */
-#define AMIDE       0x2000  /* Acceptance Mask ID Extension Enable              */
-#define FMD         0x4000  /* Full Mask Data Field Enable                      */
-#define FDF         0x8000  /* Filter On Data Field Enable                      */
-
-/* CAN_MC1 Masks                                    */
-#define MC0         0x0001  /* Enable Mailbox 0     */
-#define MC1         0x0002  /* Enable Mailbox 1     */
-#define MC2         0x0004  /* Enable Mailbox 2     */
-#define MC3         0x0008  /* Enable Mailbox 3     */
-#define MC4         0x0010  /* Enable Mailbox 4     */
-#define MC5         0x0020  /* Enable Mailbox 5     */
-#define MC6         0x0040  /* Enable Mailbox 6     */
-#define MC7         0x0080  /* Enable Mailbox 7     */
-#define MC8         0x0100  /* Enable Mailbox 8     */
-#define MC9         0x0200  /* Enable Mailbox 9     */
-#define MC10        0x0400  /* Enable Mailbox 10    */
-#define MC11        0x0800  /* Enable Mailbox 11    */
-#define MC12        0x1000  /* Enable Mailbox 12    */
-#define MC13        0x2000  /* Enable Mailbox 13    */
-#define MC14        0x4000  /* Enable Mailbox 14    */
-#define MC15        0x8000  /* Enable Mailbox 15    */
-
-/* CAN_MC2 Masks                                    */
-#define MC16        0x0001  /* Enable Mailbox 16    */
-#define MC17        0x0002  /* Enable Mailbox 17    */
-#define MC18        0x0004  /* Enable Mailbox 18    */
-#define MC19        0x0008  /* Enable Mailbox 19    */
-#define MC20        0x0010  /* Enable Mailbox 20    */
-#define MC21        0x0020  /* Enable Mailbox 21    */
-#define MC22        0x0040  /* Enable Mailbox 22    */
-#define MC23        0x0080  /* Enable Mailbox 23    */
-#define MC24        0x0100  /* Enable Mailbox 24    */
-#define MC25        0x0200  /* Enable Mailbox 25    */
-#define MC26        0x0400  /* Enable Mailbox 26    */
-#define MC27        0x0800  /* Enable Mailbox 27    */
-#define MC28        0x1000  /* Enable Mailbox 28    */
-#define MC29        0x2000  /* Enable Mailbox 29    */
-#define MC30        0x4000  /* Enable Mailbox 30    */
-#define MC31        0x8000  /* Enable Mailbox 31    */
-
-/* CAN_MD1 Masks                                                */
-#define MD0         0x0001  /* Enable Mailbox 0 For Receive     */
-#define MD1         0x0002  /* Enable Mailbox 1 For Receive     */
-#define MD2         0x0004  /* Enable Mailbox 2 For Receive     */
-#define MD3         0x0008  /* Enable Mailbox 3 For Receive     */
-#define MD4         0x0010  /* Enable Mailbox 4 For Receive     */
-#define MD5         0x0020  /* Enable Mailbox 5 For Receive     */
-#define MD6         0x0040  /* Enable Mailbox 6 For Receive     */
-#define MD7         0x0080  /* Enable Mailbox 7 For Receive     */
-#define MD8         0x0100  /* Enable Mailbox 8 For Receive     */
-#define MD9         0x0200  /* Enable Mailbox 9 For Receive     */
-#define MD10        0x0400  /* Enable Mailbox 10 For Receive    */
-#define MD11        0x0800  /* Enable Mailbox 11 For Receive    */
-#define MD12        0x1000  /* Enable Mailbox 12 For Receive    */
-#define MD13        0x2000  /* Enable Mailbox 13 For Receive    */
-#define MD14        0x4000  /* Enable Mailbox 14 For Receive    */
-#define MD15        0x8000  /* Enable Mailbox 15 For Receive    */
-
-/* CAN_MD2 Masks                                                */
-#define MD16        0x0001  /* Enable Mailbox 16 For Receive    */
-#define MD17        0x0002  /* Enable Mailbox 17 For Receive    */
-#define MD18        0x0004  /* Enable Mailbox 18 For Receive    */
-#define MD19        0x0008  /* Enable Mailbox 19 For Receive    */
-#define MD20        0x0010  /* Enable Mailbox 20 For Receive    */
-#define MD21        0x0020  /* Enable Mailbox 21 For Receive    */
-#define MD22        0x0040  /* Enable Mailbox 22 For Receive    */
-#define MD23        0x0080  /* Enable Mailbox 23 For Receive    */
-#define MD24        0x0100  /* Enable Mailbox 24 For Receive    */
-#define MD25        0x0200  /* Enable Mailbox 25 For Receive    */
-#define MD26        0x0400  /* Enable Mailbox 26 For Receive    */
-#define MD27        0x0800  /* Enable Mailbox 27 For Receive    */
-#define MD28        0x1000  /* Enable Mailbox 28 For Receive    */
-#define MD29        0x2000  /* Enable Mailbox 29 For Receive    */
-#define MD30        0x4000  /* Enable Mailbox 30 For Receive    */
-#define MD31        0x8000  /* Enable Mailbox 31 For Receive    */
-
-/* CAN_RMP1 Masks                                               */
-#define RMP0        0x0001  /* RX Message Pending In Mailbox 0  */
-#define RMP1        0x0002  /* RX Message Pending In Mailbox 1  */
-#define RMP2        0x0004  /* RX Message Pending In Mailbox 2  */
-#define RMP3        0x0008  /* RX Message Pending In Mailbox 3  */
-#define RMP4        0x0010  /* RX Message Pending In Mailbox 4  */
-#define RMP5        0x0020  /* RX Message Pending In Mailbox 5  */
-#define RMP6        0x0040  /* RX Message Pending In Mailbox 6  */
-#define RMP7        0x0080  /* RX Message Pending In Mailbox 7  */
-#define RMP8        0x0100  /* RX Message Pending In Mailbox 8  */
-#define RMP9        0x0200  /* RX Message Pending In Mailbox 9  */
-#define RMP10       0x0400  /* RX Message Pending In Mailbox 10 */
-#define RMP11       0x0800  /* RX Message Pending In Mailbox 11 */
-#define RMP12       0x1000  /* RX Message Pending In Mailbox 12 */
-#define RMP13       0x2000  /* RX Message Pending In Mailbox 13 */
-#define RMP14       0x4000  /* RX Message Pending In Mailbox 14 */
-#define RMP15       0x8000  /* RX Message Pending In Mailbox 15 */
-
-/* CAN_RMP2 Masks                                               */
-#define RMP16       0x0001  /* RX Message Pending In Mailbox 16 */
-#define RMP17       0x0002  /* RX Message Pending In Mailbox 17 */
-#define RMP18       0x0004  /* RX Message Pending In Mailbox 18 */
-#define RMP19       0x0008  /* RX Message Pending In Mailbox 19 */
-#define RMP20       0x0010  /* RX Message Pending In Mailbox 20 */
-#define RMP21       0x0020  /* RX Message Pending In Mailbox 21 */
-#define RMP22       0x0040  /* RX Message Pending In Mailbox 22 */
-#define RMP23       0x0080  /* RX Message Pending In Mailbox 23 */
-#define RMP24       0x0100  /* RX Message Pending In Mailbox 24 */
-#define RMP25       0x0200  /* RX Message Pending In Mailbox 25 */
-#define RMP26       0x0400  /* RX Message Pending In Mailbox 26 */
-#define RMP27       0x0800  /* RX Message Pending In Mailbox 27 */
-#define RMP28       0x1000  /* RX Message Pending In Mailbox 28 */
-#define RMP29       0x2000  /* RX Message Pending In Mailbox 29 */
-#define RMP30       0x4000  /* RX Message Pending In Mailbox 30 */
-#define RMP31       0x8000  /* RX Message Pending In Mailbox 31 */
-
-/* CAN_RML1 Masks                                               */
-#define RML0        0x0001  /* RX Message Lost In Mailbox 0     */
-#define RML1        0x0002  /* RX Message Lost In Mailbox 1     */
-#define RML2        0x0004  /* RX Message Lost In Mailbox 2     */
-#define RML3        0x0008  /* RX Message Lost In Mailbox 3     */
-#define RML4        0x0010  /* RX Message Lost In Mailbox 4     */
-#define RML5        0x0020  /* RX Message Lost In Mailbox 5     */
-#define RML6        0x0040  /* RX Message Lost In Mailbox 6     */
-#define RML7        0x0080  /* RX Message Lost In Mailbox 7     */
-#define RML8        0x0100  /* RX Message Lost In Mailbox 8     */
-#define RML9        0x0200  /* RX Message Lost In Mailbox 9     */
-#define RML10       0x0400  /* RX Message Lost In Mailbox 10    */
-#define RML11       0x0800  /* RX Message Lost In Mailbox 11    */
-#define RML12       0x1000  /* RX Message Lost In Mailbox 12    */
-#define RML13       0x2000  /* RX Message Lost In Mailbox 13    */
-#define RML14       0x4000  /* RX Message Lost In Mailbox 14    */
-#define RML15       0x8000  /* RX Message Lost In Mailbox 15    */
-
-/* CAN_RML2 Masks                                               */
-#define RML16       0x0001  /* RX Message Lost In Mailbox 16    */
-#define RML17       0x0002  /* RX Message Lost In Mailbox 17    */
-#define RML18       0x0004  /* RX Message Lost In Mailbox 18    */
-#define RML19       0x0008  /* RX Message Lost In Mailbox 19    */
-#define RML20       0x0010  /* RX Message Lost In Mailbox 20    */
-#define RML21       0x0020  /* RX Message Lost In Mailbox 21    */
-#define RML22       0x0040  /* RX Message Lost In Mailbox 22    */
-#define RML23       0x0080  /* RX Message Lost In Mailbox 23    */
-#define RML24       0x0100  /* RX Message Lost In Mailbox 24    */
-#define RML25       0x0200  /* RX Message Lost In Mailbox 25    */
-#define RML26       0x0400  /* RX Message Lost In Mailbox 26    */
-#define RML27       0x0800  /* RX Message Lost In Mailbox 27    */
-#define RML28       0x1000  /* RX Message Lost In Mailbox 28    */
-#define RML29       0x2000  /* RX Message Lost In Mailbox 29    */
-#define RML30       0x4000  /* RX Message Lost In Mailbox 30    */
-#define RML31       0x8000  /* RX Message Lost In Mailbox 31    */
-
-/* CAN_OPSS1 Masks                                                                              */
-#define OPSS0       0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0   */
-#define OPSS1       0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1   */
-#define OPSS2       0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2   */
-#define OPSS3       0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3   */
-#define OPSS4       0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4   */
-#define OPSS5       0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5   */
-#define OPSS6       0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6   */
-#define OPSS7       0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7   */
-#define OPSS8       0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8   */
-#define OPSS9       0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9   */
-#define OPSS10      0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10  */
-#define OPSS11      0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11  */
-#define OPSS12      0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12  */
-#define OPSS13      0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13  */
-#define OPSS14      0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14  */
-#define OPSS15      0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15  */
-
-/* CAN_OPSS2 Masks                                                                              */
-#define OPSS16      0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16  */
-#define OPSS17      0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17  */
-#define OPSS18      0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18  */
-#define OPSS19      0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19  */
-#define OPSS20      0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20  */
-#define OPSS21      0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21  */
-#define OPSS22      0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22  */
-#define OPSS23      0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23  */
-#define OPSS24      0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24  */
-#define OPSS25      0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25  */
-#define OPSS26      0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26  */
-#define OPSS27      0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27  */
-#define OPSS28      0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28  */
-#define OPSS29      0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29  */
-#define OPSS30      0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30  */
-#define OPSS31      0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31  */
-
-/* CAN_TRR1 Masks                                                       */
-#define TRR0        0x0001  /* Deny But Don't Lock Access To Mailbox 0  */
-#define TRR1        0x0002  /* Deny But Don't Lock Access To Mailbox 1  */
-#define TRR2        0x0004  /* Deny But Don't Lock Access To Mailbox 2  */
-#define TRR3        0x0008  /* Deny But Don't Lock Access To Mailbox 3  */
-#define TRR4        0x0010  /* Deny But Don't Lock Access To Mailbox 4  */
-#define TRR5        0x0020  /* Deny But Don't Lock Access To Mailbox 5  */
-#define TRR6        0x0040  /* Deny But Don't Lock Access To Mailbox 6  */
-#define TRR7        0x0080  /* Deny But Don't Lock Access To Mailbox 7  */
-#define TRR8        0x0100  /* Deny But Don't Lock Access To Mailbox 8  */
-#define TRR9        0x0200  /* Deny But Don't Lock Access To Mailbox 9  */
-#define TRR10       0x0400  /* Deny But Don't Lock Access To Mailbox 10 */
-#define TRR11       0x0800  /* Deny But Don't Lock Access To Mailbox 11 */
-#define TRR12       0x1000  /* Deny But Don't Lock Access To Mailbox 12 */
-#define TRR13       0x2000  /* Deny But Don't Lock Access To Mailbox 13 */
-#define TRR14       0x4000  /* Deny But Don't Lock Access To Mailbox 14 */
-#define TRR15       0x8000  /* Deny But Don't Lock Access To Mailbox 15 */
-
-/* CAN_TRR2 Masks                                                       */
-#define TRR16       0x0001  /* Deny But Don't Lock Access To Mailbox 16 */
-#define TRR17       0x0002  /* Deny But Don't Lock Access To Mailbox 17 */
-#define TRR18       0x0004  /* Deny But Don't Lock Access To Mailbox 18 */
-#define TRR19       0x0008  /* Deny But Don't Lock Access To Mailbox 19 */
-#define TRR20       0x0010  /* Deny But Don't Lock Access To Mailbox 20 */
-#define TRR21       0x0020  /* Deny But Don't Lock Access To Mailbox 21 */
-#define TRR22       0x0040  /* Deny But Don't Lock Access To Mailbox 22 */
-#define TRR23       0x0080  /* Deny But Don't Lock Access To Mailbox 23 */
-#define TRR24       0x0100  /* Deny But Don't Lock Access To Mailbox 24 */
-#define TRR25       0x0200  /* Deny But Don't Lock Access To Mailbox 25 */
-#define TRR26       0x0400  /* Deny But Don't Lock Access To Mailbox 26 */
-#define TRR27       0x0800  /* Deny But Don't Lock Access To Mailbox 27 */
-#define TRR28       0x1000  /* Deny But Don't Lock Access To Mailbox 28 */
-#define TRR29       0x2000  /* Deny But Don't Lock Access To Mailbox 29 */
-#define TRR30       0x4000  /* Deny But Don't Lock Access To Mailbox 30 */
-#define TRR31       0x8000  /* Deny But Don't Lock Access To Mailbox 31 */
-
-/* CAN_TRS1 Masks                                                   */
-#define TRS0        0x0001  /* Remote Frame Request For Mailbox 0   */
-#define TRS1        0x0002  /* Remote Frame Request For Mailbox 1   */
-#define TRS2        0x0004  /* Remote Frame Request For Mailbox 2   */
-#define TRS3        0x0008  /* Remote Frame Request For Mailbox 3   */
-#define TRS4        0x0010  /* Remote Frame Request For Mailbox 4   */
-#define TRS5        0x0020  /* Remote Frame Request For Mailbox 5   */
-#define TRS6        0x0040  /* Remote Frame Request For Mailbox 6   */
-#define TRS7        0x0080  /* Remote Frame Request For Mailbox 7   */
-#define TRS8        0x0100  /* Remote Frame Request For Mailbox 8   */
-#define TRS9        0x0200  /* Remote Frame Request For Mailbox 9   */
-#define TRS10       0x0400  /* Remote Frame Request For Mailbox 10  */
-#define TRS11       0x0800  /* Remote Frame Request For Mailbox 11  */
-#define TRS12       0x1000  /* Remote Frame Request For Mailbox 12  */
-#define TRS13       0x2000  /* Remote Frame Request For Mailbox 13  */
-#define TRS14       0x4000  /* Remote Frame Request For Mailbox 14  */
-#define TRS15       0x8000  /* Remote Frame Request For Mailbox 15  */
-
-/* CAN_TRS2 Masks                                                   */
-#define TRS16       0x0001  /* Remote Frame Request For Mailbox 16  */
-#define TRS17       0x0002  /* Remote Frame Request For Mailbox 17  */
-#define TRS18       0x0004  /* Remote Frame Request For Mailbox 18  */
-#define TRS19       0x0008  /* Remote Frame Request For Mailbox 19  */
-#define TRS20       0x0010  /* Remote Frame Request For Mailbox 20  */
-#define TRS21       0x0020  /* Remote Frame Request For Mailbox 21  */
-#define TRS22       0x0040  /* Remote Frame Request For Mailbox 22  */
-#define TRS23       0x0080  /* Remote Frame Request For Mailbox 23  */
-#define TRS24       0x0100  /* Remote Frame Request For Mailbox 24  */
-#define TRS25       0x0200  /* Remote Frame Request For Mailbox 25  */
-#define TRS26       0x0400  /* Remote Frame Request For Mailbox 26  */
-#define TRS27       0x0800  /* Remote Frame Request For Mailbox 27  */
-#define TRS28       0x1000  /* Remote Frame Request For Mailbox 28  */
-#define TRS29       0x2000  /* Remote Frame Request For Mailbox 29  */
-#define TRS30       0x4000  /* Remote Frame Request For Mailbox 30  */
-#define TRS31       0x8000  /* Remote Frame Request For Mailbox 31  */
-
-/* CAN_AA1 Masks                                                */
-#define AA0         0x0001  /* Aborted Message In Mailbox 0     */
-#define AA1         0x0002  /* Aborted Message In Mailbox 1     */
-#define AA2         0x0004  /* Aborted Message In Mailbox 2     */
-#define AA3         0x0008  /* Aborted Message In Mailbox 3     */
-#define AA4         0x0010  /* Aborted Message In Mailbox 4     */
-#define AA5         0x0020  /* Aborted Message In Mailbox 5     */
-#define AA6         0x0040  /* Aborted Message In Mailbox 6     */
-#define AA7         0x0080  /* Aborted Message In Mailbox 7     */
-#define AA8         0x0100  /* Aborted Message In Mailbox 8     */
-#define AA9         0x0200  /* Aborted Message In Mailbox 9     */
-#define AA10        0x0400  /* Aborted Message In Mailbox 10    */
-#define AA11        0x0800  /* Aborted Message In Mailbox 11    */
-#define AA12        0x1000  /* Aborted Message In Mailbox 12    */
-#define AA13        0x2000  /* Aborted Message In Mailbox 13    */
-#define AA14        0x4000  /* Aborted Message In Mailbox 14    */
-#define AA15        0x8000  /* Aborted Message In Mailbox 15    */
-
-/* CAN_AA2 Masks                                                */
-#define AA16        0x0001  /* Aborted Message In Mailbox 16    */
-#define AA17        0x0002  /* Aborted Message In Mailbox 17    */
-#define AA18        0x0004  /* Aborted Message In Mailbox 18    */
-#define AA19        0x0008  /* Aborted Message In Mailbox 19    */
-#define AA20        0x0010  /* Aborted Message In Mailbox 20    */
-#define AA21        0x0020  /* Aborted Message In Mailbox 21    */
-#define AA22        0x0040  /* Aborted Message In Mailbox 22    */
-#define AA23        0x0080  /* Aborted Message In Mailbox 23    */
-#define AA24        0x0100  /* Aborted Message In Mailbox 24    */
-#define AA25        0x0200  /* Aborted Message In Mailbox 25    */
-#define AA26        0x0400  /* Aborted Message In Mailbox 26    */
-#define AA27        0x0800  /* Aborted Message In Mailbox 27    */
-#define AA28        0x1000  /* Aborted Message In Mailbox 28    */
-#define AA29        0x2000  /* Aborted Message In Mailbox 29    */
-#define AA30        0x4000  /* Aborted Message In Mailbox 30    */
-#define AA31        0x8000  /* Aborted Message In Mailbox 31    */
-
-/* CAN_TA1 Masks                                                    */
-#define TA0         0x0001  /* Transmit Successful From Mailbox 0   */
-#define TA1         0x0002  /* Transmit Successful From Mailbox 1   */
-#define TA2         0x0004  /* Transmit Successful From Mailbox 2   */
-#define TA3         0x0008  /* Transmit Successful From Mailbox 3   */
-#define TA4         0x0010  /* Transmit Successful From Mailbox 4   */
-#define TA5         0x0020  /* Transmit Successful From Mailbox 5   */
-#define TA6         0x0040  /* Transmit Successful From Mailbox 6   */
-#define TA7         0x0080  /* Transmit Successful From Mailbox 7   */
-#define TA8         0x0100  /* Transmit Successful From Mailbox 8   */
-#define TA9         0x0200  /* Transmit Successful From Mailbox 9   */
-#define TA10        0x0400  /* Transmit Successful From Mailbox 10  */
-#define TA11        0x0800  /* Transmit Successful From Mailbox 11  */
-#define TA12        0x1000  /* Transmit Successful From Mailbox 12  */
-#define TA13        0x2000  /* Transmit Successful From Mailbox 13  */
-#define TA14        0x4000  /* Transmit Successful From Mailbox 14  */
-#define TA15        0x8000  /* Transmit Successful From Mailbox 15  */
-
-/* CAN_TA2 Masks                                                    */
-#define TA16        0x0001  /* Transmit Successful From Mailbox 16  */
-#define TA17        0x0002  /* Transmit Successful From Mailbox 17  */
-#define TA18        0x0004  /* Transmit Successful From Mailbox 18  */
-#define TA19        0x0008  /* Transmit Successful From Mailbox 19  */
-#define TA20        0x0010  /* Transmit Successful From Mailbox 20  */
-#define TA21        0x0020  /* Transmit Successful From Mailbox 21  */
-#define TA22        0x0040  /* Transmit Successful From Mailbox 22  */
-#define TA23        0x0080  /* Transmit Successful From Mailbox 23  */
-#define TA24        0x0100  /* Transmit Successful From Mailbox 24  */
-#define TA25        0x0200  /* Transmit Successful From Mailbox 25  */
-#define TA26        0x0400  /* Transmit Successful From Mailbox 26  */
-#define TA27        0x0800  /* Transmit Successful From Mailbox 27  */
-#define TA28        0x1000  /* Transmit Successful From Mailbox 28  */
-#define TA29        0x2000  /* Transmit Successful From Mailbox 29  */
-#define TA30        0x4000  /* Transmit Successful From Mailbox 30  */
-#define TA31        0x8000  /* Transmit Successful From Mailbox 31  */
-
-/* CAN_MBTD Masks                                               */
-#define TDPTR       0x001F  /* Mailbox To Temporarily Disable   */
-#define TDA         0x0040  /* Temporary Disable Acknowledge    */
-#define TDR         0x0080  /* Temporary Disable Request        */
-
-/* CAN_RFH1 Masks                                                                       */
-#define RFH0        0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0     */
-#define RFH1        0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1     */
-#define RFH2        0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2     */
-#define RFH3        0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3     */
-#define RFH4        0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4     */
-#define RFH5        0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5     */
-#define RFH6        0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6     */
-#define RFH7        0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7     */
-#define RFH8        0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8     */
-#define RFH9        0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9     */
-#define RFH10       0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10    */
-#define RFH11       0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11    */
-#define RFH12       0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12    */
-#define RFH13       0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13    */
-#define RFH14       0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14    */
-#define RFH15       0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15    */
-
-/* CAN_RFH2 Masks                                                                       */
-#define RFH16       0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16    */
-#define RFH17       0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17    */
-#define RFH18       0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18    */
-#define RFH19       0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19    */
-#define RFH20       0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20    */
-#define RFH21       0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21    */
-#define RFH22       0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22    */
-#define RFH23       0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23    */
-#define RFH24       0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24    */
-#define RFH25       0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25    */
-#define RFH26       0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26    */
-#define RFH27       0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27    */
-#define RFH28       0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28    */
-#define RFH29       0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29    */
-#define RFH30       0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30    */
-#define RFH31       0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31    */
-
-/* CAN_MBTIF1 Masks                                                 */
-#define MBTIF0      0x0001  /* TX Interrupt Active In Mailbox 0     */
-#define MBTIF1      0x0002  /* TX Interrupt Active In Mailbox 1     */
-#define MBTIF2      0x0004  /* TX Interrupt Active In Mailbox 2     */
-#define MBTIF3      0x0008  /* TX Interrupt Active In Mailbox 3     */
-#define MBTIF4      0x0010  /* TX Interrupt Active In Mailbox 4     */
-#define MBTIF5      0x0020  /* TX Interrupt Active In Mailbox 5     */
-#define MBTIF6      0x0040  /* TX Interrupt Active In Mailbox 6     */
-#define MBTIF7      0x0080  /* TX Interrupt Active In Mailbox 7     */
-#define MBTIF8      0x0100  /* TX Interrupt Active In Mailbox 8     */
-#define MBTIF9      0x0200  /* TX Interrupt Active In Mailbox 9     */
-#define MBTIF10     0x0400  /* TX Interrupt Active In Mailbox 10    */
-#define MBTIF11     0x0800  /* TX Interrupt Active In Mailbox 11    */
-#define MBTIF12     0x1000  /* TX Interrupt Active In Mailbox 12    */
-#define MBTIF13     0x2000  /* TX Interrupt Active In Mailbox 13    */
-#define MBTIF14     0x4000  /* TX Interrupt Active In Mailbox 14    */
-#define MBTIF15     0x8000  /* TX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBTIF2 Masks                                                 */
-#define MBTIF16     0x0001  /* TX Interrupt Active In Mailbox 16    */
-#define MBTIF17     0x0002  /* TX Interrupt Active In Mailbox 17    */
-#define MBTIF18     0x0004  /* TX Interrupt Active In Mailbox 18    */
-#define MBTIF19     0x0008  /* TX Interrupt Active In Mailbox 19    */
-#define MBTIF20     0x0010  /* TX Interrupt Active In Mailbox 20    */
-#define MBTIF21     0x0020  /* TX Interrupt Active In Mailbox 21    */
-#define MBTIF22     0x0040  /* TX Interrupt Active In Mailbox 22    */
-#define MBTIF23     0x0080  /* TX Interrupt Active In Mailbox 23    */
-#define MBTIF24     0x0100  /* TX Interrupt Active In Mailbox 24    */
-#define MBTIF25     0x0200  /* TX Interrupt Active In Mailbox 25    */
-#define MBTIF26     0x0400  /* TX Interrupt Active In Mailbox 26    */
-#define MBTIF27     0x0800  /* TX Interrupt Active In Mailbox 27    */
-#define MBTIF28     0x1000  /* TX Interrupt Active In Mailbox 28    */
-#define MBTIF29     0x2000  /* TX Interrupt Active In Mailbox 29    */
-#define MBTIF30     0x4000  /* TX Interrupt Active In Mailbox 30    */
-#define MBTIF31     0x8000  /* TX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBRIF1 Masks                                                 */
-#define MBRIF0      0x0001  /* RX Interrupt Active In Mailbox 0     */
-#define MBRIF1      0x0002  /* RX Interrupt Active In Mailbox 1     */
-#define MBRIF2      0x0004  /* RX Interrupt Active In Mailbox 2     */
-#define MBRIF3      0x0008  /* RX Interrupt Active In Mailbox 3     */
-#define MBRIF4      0x0010  /* RX Interrupt Active In Mailbox 4     */
-#define MBRIF5      0x0020  /* RX Interrupt Active In Mailbox 5     */
-#define MBRIF6      0x0040  /* RX Interrupt Active In Mailbox 6     */
-#define MBRIF7      0x0080  /* RX Interrupt Active In Mailbox 7     */
-#define MBRIF8      0x0100  /* RX Interrupt Active In Mailbox 8     */
-#define MBRIF9      0x0200  /* RX Interrupt Active In Mailbox 9     */
-#define MBRIF10     0x0400  /* RX Interrupt Active In Mailbox 10    */
-#define MBRIF11     0x0800  /* RX Interrupt Active In Mailbox 11    */
-#define MBRIF12     0x1000  /* RX Interrupt Active In Mailbox 12    */
-#define MBRIF13     0x2000  /* RX Interrupt Active In Mailbox 13    */
-#define MBRIF14     0x4000  /* RX Interrupt Active In Mailbox 14    */
-#define MBRIF15     0x8000  /* RX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBRIF2 Masks                                                 */
-#define MBRIF16     0x0001  /* RX Interrupt Active In Mailbox 16    */
-#define MBRIF17     0x0002  /* RX Interrupt Active In Mailbox 17    */
-#define MBRIF18     0x0004  /* RX Interrupt Active In Mailbox 18    */
-#define MBRIF19     0x0008  /* RX Interrupt Active In Mailbox 19    */
-#define MBRIF20     0x0010  /* RX Interrupt Active In Mailbox 20    */
-#define MBRIF21     0x0020  /* RX Interrupt Active In Mailbox 21    */
-#define MBRIF22     0x0040  /* RX Interrupt Active In Mailbox 22    */
-#define MBRIF23     0x0080  /* RX Interrupt Active In Mailbox 23    */
-#define MBRIF24     0x0100  /* RX Interrupt Active In Mailbox 24    */
-#define MBRIF25     0x0200  /* RX Interrupt Active In Mailbox 25    */
-#define MBRIF26     0x0400  /* RX Interrupt Active In Mailbox 26    */
-#define MBRIF27     0x0800  /* RX Interrupt Active In Mailbox 27    */
-#define MBRIF28     0x1000  /* RX Interrupt Active In Mailbox 28    */
-#define MBRIF29     0x2000  /* RX Interrupt Active In Mailbox 29    */
-#define MBRIF30     0x4000  /* RX Interrupt Active In Mailbox 30    */
-#define MBRIF31     0x8000  /* RX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBIM1 Masks                                              */
-#define MBIM0       0x0001  /* Enable Interrupt For Mailbox 0   */
-#define MBIM1       0x0002  /* Enable Interrupt For Mailbox 1   */
-#define MBIM2       0x0004  /* Enable Interrupt For Mailbox 2   */
-#define MBIM3       0x0008  /* Enable Interrupt For Mailbox 3   */
-#define MBIM4       0x0010  /* Enable Interrupt For Mailbox 4   */
-#define MBIM5       0x0020  /* Enable Interrupt For Mailbox 5   */
-#define MBIM6       0x0040  /* Enable Interrupt For Mailbox 6   */
-#define MBIM7       0x0080  /* Enable Interrupt For Mailbox 7   */
-#define MBIM8       0x0100  /* Enable Interrupt For Mailbox 8   */
-#define MBIM9       0x0200  /* Enable Interrupt For Mailbox 9   */
-#define MBIM10      0x0400  /* Enable Interrupt For Mailbox 10  */
-#define MBIM11      0x0800  /* Enable Interrupt For Mailbox 11  */
-#define MBIM12      0x1000  /* Enable Interrupt For Mailbox 12  */
-#define MBIM13      0x2000  /* Enable Interrupt For Mailbox 13  */
-#define MBIM14      0x4000  /* Enable Interrupt For Mailbox 14  */
-#define MBIM15      0x8000  /* Enable Interrupt For Mailbox 15  */
-
-/* CAN_MBIM2 Masks                                              */
-#define MBIM16      0x0001  /* Enable Interrupt For Mailbox 16  */
-#define MBIM17      0x0002  /* Enable Interrupt For Mailbox 17  */
-#define MBIM18      0x0004  /* Enable Interrupt For Mailbox 18  */
-#define MBIM19      0x0008  /* Enable Interrupt For Mailbox 19  */
-#define MBIM20      0x0010  /* Enable Interrupt For Mailbox 20  */
-#define MBIM21      0x0020  /* Enable Interrupt For Mailbox 21  */
-#define MBIM22      0x0040  /* Enable Interrupt For Mailbox 22  */
-#define MBIM23      0x0080  /* Enable Interrupt For Mailbox 23  */
-#define MBIM24      0x0100  /* Enable Interrupt For Mailbox 24  */
-#define MBIM25      0x0200  /* Enable Interrupt For Mailbox 25  */
-#define MBIM26      0x0400  /* Enable Interrupt For Mailbox 26  */
-#define MBIM27      0x0800  /* Enable Interrupt For Mailbox 27  */
-#define MBIM28      0x1000  /* Enable Interrupt For Mailbox 28  */
-#define MBIM29      0x2000  /* Enable Interrupt For Mailbox 29  */
-#define MBIM30      0x4000  /* Enable Interrupt For Mailbox 30  */
-#define MBIM31      0x8000  /* Enable Interrupt For Mailbox 31  */
-
-/* CAN_GIM Masks                                                                */
-#define EWTIM       0x0001  /* Enable TX Error Count Interrupt                  */
-#define EWRIM       0x0002  /* Enable RX Error Count Interrupt                  */
-#define EPIM        0x0004  /* Enable Error-Passive Mode Interrupt              */
-#define BOIM        0x0008  /* Enable Bus Off Interrupt                         */
-#define WUIM        0x0010  /* Enable Wake-Up Interrupt                         */
-#define UIAIM       0x0020  /* Enable Access To Unimplemented Address Interrupt */
-#define AAIM        0x0040  /* Enable Abort Acknowledge Interrupt               */
-#define RMLIM       0x0080  /* Enable RX Message Lost Interrupt                 */
-#define UCEIM       0x0100  /* Enable Universal Counter Overflow Interrupt      */
-#define EXTIM       0x0200  /* Enable External Trigger Output Interrupt         */
-#define ADIM        0x0400  /* Enable Access Denied Interrupt                   */
-
-/* CAN_GIS Masks                                                            */
-#define EWTIS       0x0001  /* TX Error Count IRQ Status                    */
-#define EWRIS       0x0002  /* RX Error Count IRQ Status                    */
-#define EPIS        0x0004  /* Error-Passive Mode IRQ Status                */
-#define BOIS        0x0008  /* Bus Off IRQ Status                           */
-#define WUIS        0x0010  /* Wake-Up IRQ Status                           */
-#define UIAIS       0x0020  /* Access To Unimplemented Address IRQ Status   */
-#define AAIS        0x0040  /* Abort Acknowledge IRQ Status                 */
-#define RMLIS       0x0080  /* RX Message Lost IRQ Status                   */
-#define UCEIS       0x0100  /* Universal Counter Overflow IRQ Status        */
-#define EXTIS       0x0200  /* External Trigger Output IRQ Status           */
-#define ADIS        0x0400  /* Access Denied IRQ Status                     */
-
-/* CAN_GIF Masks                                                            */
-#define EWTIF       0x0001  /* TX Error Count IRQ Flag                      */
-#define EWRIF       0x0002  /* RX Error Count IRQ Flag                      */
-#define EPIF        0x0004  /* Error-Passive Mode IRQ Flag                  */
-#define BOIF        0x0008  /* Bus Off IRQ Flag                             */
-#define WUIF        0x0010  /* Wake-Up IRQ Flag                             */
-#define UIAIF       0x0020  /* Access To Unimplemented Address IRQ Flag     */
-#define AAIF        0x0040  /* Abort Acknowledge IRQ Flag                   */
-#define RMLIF       0x0080  /* RX Message Lost IRQ Flag                     */
-#define UCEIF       0x0100  /* Universal Counter Overflow IRQ Flag          */
-#define EXTIF       0x0200  /* External Trigger Output IRQ Flag             */
-#define ADIF        0x0400  /* Access Denied IRQ Flag                       */
-
-/* CAN_UCCNF Masks                                                          */
-#define UCCNF       0x000F  /* Universal Counter Mode                       */
-#define UC_STAMP    0x0001  /*      Timestamp Mode                          */
-#define UC_WDOG     0x0002  /*      Watchdog Mode                           */
-#define UC_AUTOTX   0x0003  /*      Auto-Transmit Mode                      */
-#define UC_ERROR    0x0006  /*      CAN Error Frame Count                   */
-#define UC_OVER     0x0007  /*      CAN Overload Frame Count                */
-#define UC_LOST     0x0008  /*      Arbitration Lost During TX Count        */
-#define UC_AA       0x0009  /*      TX Abort Count                          */
-#define UC_TA       0x000A  /*      TX Successful Count                     */
-#define UC_REJECT   0x000B  /*      RX Message Rejected Count               */
-#define UC_RML      0x000C  /*      RX Message Lost Count                   */
-#define UC_RX       0x000D  /*      Total Successful RX Messages Count      */
-#define UC_RMP      0x000E  /*      Successful RX W/Matching ID Count       */
-#define UC_ALL      0x000F  /*      Correct Message On CAN Bus Line Count   */
-#define UCRC        0x0020  /* Universal Counter Reload/Clear               */
-#define UCCT        0x0040  /* Universal Counter CAN Trigger                */
-#define UCE         0x0080  /* Universal Counter Enable                     */
-
-/* CAN_ESR Masks                                        */
-#define ACKE        0x0004  /* Acknowledge Error        */
-#define SER         0x0008  /* Stuff Error              */
-#define CRCE        0x0010  /* CRC Error                */
-#define SA0         0x0020  /* Stuck At Dominant Error  */
-#define BEF         0x0040  /* Bit Error Flag           */
-#define FER         0x0080  /* Form Error Flag          */
-
-/* CAN_EWR Masks                                                */
-#define EWLREC      0x00FF  /* RX Error Count Limit (For EWRIS) */
-#define EWLTEC      0xFF00  /* TX Error Count Limit (For EWTIS) */
-
-
-/* ************  ADC Controller Module (ACM) MASKS  ***************/
-
-/* Bit masks for ACM_CTL */
-#define ACM_EN              0x0001
-#define ACM_TMR0_EN         0x0002
-#define ACM_TMR1_EN         0x0004
-#define ACM_TRG_SEL0        0x0018
-#define ACM_TRG_SEL1        0x0060
-#define ACM_TRG_POL0        0x0080
-#define ACM_TRG_POL1        0x0100
-#define ACM_CS_POL          0x0200
-#define ACM_CLK_POL         0x0400
-#define ACM_EPS             0xC000
-
-/* Bit masks for ACM_STAT */
-#define ACM_BSY             0x0001
-#define ACM_EMISS           0x0002
-#define ACM_ECOM            0x0004
-#define ACM_CEVNT           0x0078
-
-/* Bit masks for ACM_ES */
-#define ACM_ES0             0x0001
-#define ACM_ES1             0x0002
-#define ACM_ES2             0x0004
-#define ACM_ES3             0x0008
-#define ACM_ES4             0x0010
-#define ACM_ES5             0x0020
-#define ACM_ES6             0x0040
-#define ACM_ES7             0x0080
-#define ACM_ES8             0x0100
-#define ACM_ES9             0x0200
-#define ACM_ES10            0x0400
-#define ACM_ES11            0x0800
-#define ACM_ES12            0x1000
-#define ACM_ES13            0x2000
-#define ACM_ES14            0x4000
-#define ACM_ES15            0x8000
-
-/* Bit masks for ACM_IMSK */
-#define ACM_IE0             0x0001
-#define ACM_IE1             0x0002
-#define ACM_IE2             0x0004
-#define ACM_IE3             0x0008
-#define ACM_IE4             0x0010
-#define ACM_IE5             0x0020
-#define ACM_IE6             0x0040
-#define ACM_IE7             0x0080
-#define ACM_IE8             0x0100
-#define ACM_IE9             0x0200
-#define ACM_IE10            0x0400
-#define ACM_IE11            0x0800
-#define ACM_IE12            0x1000
-#define ACM_IE13            0x2000
-#define ACM_IE14            0x4000
-#define ACM_IE15            0x8000
-
-/* Bit masks for ACM_MS */
-#define ACM_EM0             0x0001
-#define ACM_EM1             0x0002
-#define ACM_EM2             0x0004
-#define ACM_EM3             0x0008
-#define ACM_EM4             0x0010
-#define ACM_EM5             0x0020
-#define ACM_EM6             0x0040
-#define ACM_EM7             0x0080
-#define ACM_EM8             0x0100
-#define ACM_EM9             0x0200
-#define ACM_EM10            0x0400
-#define ACM_EM11            0x0800
-#define ACM_EM12            0x1000
-#define ACM_EM13            0x2000
-#define ACM_EM14            0x4000
-#define ACM_EM15            0x8000
-
-/* Bit masks for ACM_EMSK */
-#define ACM_MIE0             0x0001
-#define ACM_MIE1             0x0002
-#define ACM_MIE2             0x0004
-#define ACM_MIE3             0x0008
-#define ACM_MIE4             0x0010
-#define ACM_MIE5             0x0020
-#define ACM_MIE6             0x0040
-#define ACM_MIE7             0x0080
-#define ACM_MIE8             0x0100
-#define ACM_MIE9             0x0200
-#define ACM_MIE10            0x0400
-#define ACM_MIE11            0x0800
-#define ACM_MIE12            0x1000
-#define ACM_MIE13            0x2000
-#define ACM_MIE14            0x4000
-#define ACM_MIE15            0x8000
-
-/* Bit masks for ACM_ER0 & ACM_ER1 */
-#define ACM_EVNT_EN          0x0001
-#define ACM_EVNT_PF          0x003E
-
-/* Bit masks for ACM_ET0 & ACM_ET1 */
-#define ACM_EVNT_TIME        0xFFFFFFFF
-
-/* Bit masks for ACM_TC0 */
-#define ACM_CLK_DIV          0x00FF
-#define ACM_SC               0xFF00
-
-/* Bit masks for ACM_TC1 */
-#define ACM_CSW              0x00FF
-#define ACM_HC               0x0F00
-#define ACM_ZC               0xF000
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF50x_H */
diff --git a/libgloss/bfin/include/defBF512.h b/libgloss/bfin/include/defBF512.h
deleted file mode 100644
index 183624b4d..000000000
--- a/libgloss/bfin/include/defBF512.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF512_H
-#define _DEF_BF512_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <defBF51x_base.h>
-
-#endif /* _DEF_BF512_H */
diff --git a/libgloss/bfin/include/defBF514.h b/libgloss/bfin/include/defBF514.h
deleted file mode 100644
index 36bf2e9c9..000000000
--- a/libgloss/bfin/include/defBF514.h
+++ /dev/null
@@ -1,490 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF514_H
-#define _DEF_BF514_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <defBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"macros violate rule 19.4")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
-
-/* RSI Registers */
-
-#define RSI_PWR_CONTROL			0xFFC03800		/* RSI Power Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PWR_CTL  			RSI_PWR_CONTROL	/* SDH Power Control */
-#define RSI_CLK_CONTROL			0xFFC03804		/* RSI Clock Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CLK_CTL  			RSI_CLK_CONTROL	/* SDH Clock Control */
-#define RSI_ARGUMENT			0xFFC03808		/* RSI Argument Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_ARGUMENT  			RSI_ARGUMENT	/* SDH Argument */
-#define RSI_COMMAND			0xFFC0380C		/* RSI Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_COMMAND  			RSI_COMMAND      	/* SDH Command */
-#define RSI_RESP_CMD			0xFFC03810		/* RSI Response Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESP_CMD  			RSI_RESP_CMD     	/* SDH Response Command */
-#define RSI_RESPONSE0			0xFFC03814		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE0  			RSI_RESPONSE0    	/* SDH Response0 */
-#define RSI_RESPONSE1			0xFFC03818		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE1  			RSI_RESPONSE1    	/* SDH Response1 */
-#define RSI_RESPONSE2			0xFFC0381C	/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE2  			RSI_RESPONSE2    	/* SDH Response2 */
-#define RSI_RESPONSE3			0xFFC03820		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE3  			RSI_RESPONSE3    	/* SDH Response3 */
-#define RSI_DATA_TIMER			0xFFC03824		/* RSI Data Timer Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_TIMER 			RSI_DATA_TIMER  	/* SDH Data Timer */
-#define RSI_DATA_LGTH			0xFFC03828		/* RSI Data Length Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_LGTH  			RSI_DATA_LGTH    	/* SDH Data Length */
-#define RSI_DATA_CONTROL		0xFFC0382C		/* RSI Data Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CTL  			RSI_DATA_CONTROL 	/* SDH Data Control */
-#define RSI_DATA_CNT			0xFFC03830		/* RSI Data Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CNT  			RSI_DATA_CNT     	/* SDH Data Counter */
-#define RSI_STATUS			0xFFC03834		/* RSI Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS  			RSI_STATUS       	/* SDH Status */
-#define RSI_STATUSCL			0xFFC03838		/* RSI Status Clear Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS_CLR  		RSI_STATUSCL     	/* SDH Status Clear */
-#define RSI_MASK0				0xFFC0383C		/* RSI Interrupt 0 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK0  			RSI_MASK0        	/* SDH Interrupt0 Mask */
-#define RSI_MASK1				0xFFC03840		/* RSI Interrupt 1 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK1  			RSI_MASK1        	/* SDH Interrupt1 Mask */
-#define RSI_FIFO_CNT			0xFFC03848		/* RSI FIFO Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO_CNT  			RSI_FIFO_CNT     	/* SDH FIFO Counter */
-#define RSI_CEATA_CONTROL		0xFFC0384C		/* RSI CEATA Register */
-#define RSI_FIFO				0xFFC03880		/* RSI Data FIFO Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO  			RSI_FIFO         	/* SDH Data FIFO */
-#define RSI_ESTAT				0xFFC038C0		/* RSI Exception Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_STATUS  			RSI_ESTAT        	/* SDH Exception Status */
-#define RSI_EMASK				0xFFC038C4		/* RSI Exception Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_MASK  			RSI_EMASK        	/* SDH Exception Mask */
-#define RSI_CONFIG			0xFFC038C8		/* RSI Configuration Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CFG  				RSI_CONFIG       	/* SDH Configuration */
-#define RSI_RD_WAIT_EN			0xFFC038CC		/* RSI Read Wait Enable Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RD_WAIT_EN  		RSI_RD_WAIT_EN   	/* SDH Read Wait Enable */
-#define RSI_PID0				0xFFC038D0		/* RSI Peripheral ID Register 0 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID0  			RSI_PID0         	/* SDH Peripheral Identification0 */
-#define RSI_PID1				0xFFC038D4		/* RSI Peripheral ID Register 1 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID1  			RSI_PID1         	/* SDH Peripheral Identification1 */
-#define RSI_PID2				0xFFC038D8		/* RSI Peripheral ID Register 2 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID2  			RSI_PID2         	/* SDH Peripheral Identification2 */
-#define RSI_PID3				0xFFC038DC		/* RSI Peripheral ID Register 3 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID3  			RSI_PID3         	/* SDH Peripheral Identification3 */
-/* RSI Registers */
-
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for RSI_PWR_CONTROL */
-#define                    PWR_ON  0x3        		/* Power On */
-#define                RSI_CMD_OD  0x40       		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 SD_CMD_OD  RSI_CMD_OD 		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nSD_CMD_OD  0x0
-/* legacy bit mask (below) provided for backwards code compatibility */
-#if 0
-#define                       TBD  0x3c       		/* TBD */
-#endif
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   ROD_CTL  0x80
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nROD_CTL  0x80
-
-
-/* Bit masks for RSI_CLK_CONTROL */
-#define                    CLKDIV  0xff           	/* MC_CLK Divisor */
-#define                    CLK_EN  0x100          	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CLK_E  CLK_EN         	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCLK_E  0x0
-#define                 PWR_SV_EN  0x200          	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  PWR_SV_E  PWR_SV_EN      	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400          	/* Bypass Divisor */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCLKDIV_BYPASS  0x0
-#define                  BUS_MODE  0x1800           /* Bus width selection */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  WIDE_BUS  0x0800    	/* Wide Bus Mode Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nWIDE_BUS  0x0
-
-
-/* Bit masks for RSI_COMMAND */
-#define                   CMD_IDX  0x3f           	/* Command Index */
-#define                CMD_RSP_EN  0x40           	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CMD_RSP  CMD_RSP_EN     	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_RSP  0x0
-#define               CMD_LRSP_EN  0x80           	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_L_RSP  CMD_LRSP_EN    	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_L_RSP  0x0
-#define                CMD_INT_EN  0x100          	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_INT_E  CMD_INT_EN     	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_INT_E  0x0
-#define               CMD_PEND_EN  0x200          	/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                CMD_PEND_E  CMD_PEND_EN		/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nCMD_PEND_E  0x0
-#define                    CMD_EN  0x400			/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CMD_E  CMD_EN          	/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCMD_E  0x0
-
-
-/* Bit masks for RSI_RESP_CMD */
-#define                  RESP_CMD  0x3f       		/* Response Command */
-
-/* Bit masks for RSI_DATA_LGTH */
-#define               DATA_LENGTH  0xffff       	/* Data Length */
-
-
-/* Bit masks for RSI_DATA_CONTROL */
-#define                   DATA_EN  0x1            	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     DTX_E  DATA_EN        	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nDTX_E  0x0
-#define                  DATA_DIR  0x2            	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   DTX_DIR  DATA_DIR      	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDTX_DIR  0x0
-#define                 DATA_MODE  0x4            	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  DTX_MODE  DATA_MODE      	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nDTX_MODE  0x0
-#define               DATA_DMA_EN  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 DTX_DMA_E  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nDTX_DMA_E  0x0
-#define             DATA_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              DTX_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-#define 		             CEATA_EN  0x100	      /* CE-ATA operation mode enable */
-#define 		         CEATA_CCS_EN  0x200	      /* CE-ATA CCS mode enable */
-
-/* Bit masks for RSI_DATA_CNT */
-#define               DATA_COUNT  0xffff       		/* Data Count */
-
-/* Bit masks for RSI_STATUS */
-#define              CMD_CRC_FAIL  0x1        		/* CMD CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        		/* Data CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        		/* CMD Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        		/* Data Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       		/* Transmit Underrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       		/* Receive Overrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       		/* CMD Response End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       		/* CMD Sent */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      		/* Data End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      		/* Start Bit Error */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      		/* Data Block End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      		/* CMD Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     		/* Transmit Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     		/* Receive Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     		/* Transmit FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     		/* Receive FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    		/* Transmit FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    		/* Receive FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    		/* Transmit FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    		/* Receive FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   		/* Transmit Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   		/* Receive Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for RSI_STATCL */
-#define         CMD_CRC_FAIL_STAT  0x1       		/* CMD CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        		/* Data CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        		/* CMD Time Out Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        		/* Data Time Out status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       		/* Transmit Underrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       		/* Receive Overrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       		/* CMD Response End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       		/* CMD Sent Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      		/* Data End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      		/* Start Bit Error Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      		/* Data Block End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for RSI_MASKx */
-#define         CMD_CRC_FAIL_MASK  0x1        		/* CMD CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        		/* Data CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        		/* CMD Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        		/* Data Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       		/* Transmit Underrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       		/* Receive Overrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       		/* CMD Response End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       		/* CMD Sent Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      		/* Data End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      		/* Start Bit Error Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      		/* Data Block End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      		/* CMD Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     		/* Transmit Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     		/* Receive Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     		/* Transmit FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     		/* Receive FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    		/* Transmit FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    		/* Receive FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    		/* Transmit FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    		/* Receive FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   		/* Transmit Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   		/* Receive Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for RSI_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff     		/* FIFO Count */
-
-/* Bit masks for RSI_CEATA_CONTROL */
-#define		  CEATA_TX_CCSD  0x1	    		/* Send CE-ATA CCSD sequence */
-
-/* Bit masks for RSI_ESTAT */
-#define              SDIO_INT_DET  0x2        		/* SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       		/* SD Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nSD_CARD_DET  0x0
-#define             CEATA_INT_DET  0x20
-
-/* Bit masks for RSI_EMASK */
-#define         SDIO_INT_DET_MASK  0x2                /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SDIO_MSK  SDIO_INT_DET_MASK  /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nSDIO_MSK  0x0
-#define          SD_CARD_DET_MASK  0x10               /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SCD_MASK  SD_CARD_DET_MASK   /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nSCD_MSK  0x0
-#define        CEATA_INT_DET_MASK  0x20
-
-
-/* Bit masks for RSI_CFG */
-/* Left in for backwards compatibility */
-#define                RSI_CLK_EN  0x1
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CLKS_EN  RSI_CLK_EN        	/* Clocks Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCLKS_EN  0x0
-#define                  SDIO4_EN  0x4        		/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      SD4E  SDIO4_EN        	/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     nSD4E  0x0
-#define                     MW_EN  0x8        		/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       MWE  MW_EN        	/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nMWE  0x0
-#define                   RSI_RST  0x10       		/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    SD_RST  RSI_RST       	/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nSD_RST  0x0
-#define                    PU_DAT  0x20       		/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PUP_SDDAT  PU_DAT       	/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPUP_SDDAT  0x0
-#define                   PU_DAT3  0x40       		/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                PUP_SDDAT3  PU_DAT3       	/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nPUP_SDDAT3  0x0
-#define                   PD_DAT3  0x80       		/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PD_SDDAT3  PD_DAT3       	/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPD_SDDAT3  0x0
-
-
-/* Bit masks for RSI_RD_WAIT_EN */
-#define			 SDIO_RWR  0x1             	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       RWR  SDIO_RWR        	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nRWR  0x0
-
-/* Bit masks for RSI_PIDx */
-#define                   RSI_PID  0xff			/* RSI Peripheral ID */
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF514_H */
diff --git a/libgloss/bfin/include/defBF516.h b/libgloss/bfin/include/defBF516.h
deleted file mode 100644
index 096bb489f..000000000
--- a/libgloss/bfin/include/defBF516.h
+++ /dev/null
@@ -1,936 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF516_H
-#define _DEF_BF516_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <defBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-
-/* RSI Registers */
-
-#define RSI_PWR_CONTROL			0xFFC03800		/* RSI Power Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PWR_CTL  			RSI_PWR_CONTROL	/* SDH Power Control */
-#define RSI_CLK_CONTROL			0xFFC03804		/* RSI Clock Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CLK_CTL  			RSI_CLK_CONTROL	/* SDH Clock Control */
-#define RSI_ARGUMENT			0xFFC03808		/* RSI Argument Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_ARGUMENT  			RSI_ARGUMENT	/* SDH Argument */
-#define RSI_COMMAND			0xFFC0380C		/* RSI Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_COMMAND  			RSI_COMMAND      	/* SDH Command */
-#define RSI_RESP_CMD			0xFFC03810		/* RSI Response Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESP_CMD  			RSI_RESP_CMD     	/* SDH Response Command */
-#define RSI_RESPONSE0			0xFFC03814		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE0  			RSI_RESPONSE0    	/* SDH Response0 */
-#define RSI_RESPONSE1			0xFFC03818		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE1  			RSI_RESPONSE1    	/* SDH Response1 */
-#define RSI_RESPONSE2			0xFFC0381C	/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE2  			RSI_RESPONSE2    	/* SDH Response2 */
-#define RSI_RESPONSE3			0xFFC03820		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE3  			RSI_RESPONSE3    	/* SDH Response3 */
-#define RSI_DATA_TIMER			0xFFC03824		/* RSI Data Timer Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_TIMER 			RSI_DATA_TIMER  	/* SDH Data Timer */
-#define RSI_DATA_LGTH			0xFFC03828		/* RSI Data Length Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_LGTH  			RSI_DATA_LGTH    	/* SDH Data Length */
-#define RSI_DATA_CONTROL		0xFFC0382C		/* RSI Data Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CTL  			RSI_DATA_CONTROL 	/* SDH Data Control */
-#define RSI_DATA_CNT			0xFFC03830		/* RSI Data Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CNT  			RSI_DATA_CNT     	/* SDH Data Counter */
-#define RSI_STATUS			0xFFC03834		/* RSI Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS  			RSI_STATUS       	/* SDH Status */
-#define RSI_STATUSCL			0xFFC03838		/* RSI Status Clear Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS_CLR  		RSI_STATUSCL     	/* SDH Status Clear */
-#define RSI_MASK0				0xFFC0383C		/* RSI Interrupt 0 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK0  			RSI_MASK0        	/* SDH Interrupt0 Mask */
-#define RSI_MASK1				0xFFC03840		/* RSI Interrupt 1 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK1  			RSI_MASK1        	/* SDH Interrupt1 Mask */
-#define RSI_FIFO_CNT			0xFFC03848		/* RSI FIFO Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO_CNT  			RSI_FIFO_CNT     	/* SDH FIFO Counter */
-#define RSI_CEATA_CONTROL		0xFFC0384C		/* RSI CEATA Register */
-#define RSI_FIFO				0xFFC03880		/* RSI Data FIFO Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO  			RSI_FIFO         	/* SDH Data FIFO */
-#define RSI_ESTAT				0xFFC038C0		/* RSI Exception Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_STATUS  			RSI_ESTAT        	/* SDH Exception Status */
-#define RSI_EMASK				0xFFC038C4		/* RSI Exception Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_MASK  			RSI_EMASK        	/* SDH Exception Mask */
-#define RSI_CONFIG			0xFFC038C8		/* RSI Configuration Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CFG  				RSI_CONFIG       	/* SDH Configuration */
-#define RSI_RD_WAIT_EN			0xFFC038CC		/* RSI Read Wait Enable Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RD_WAIT_EN  		RSI_RD_WAIT_EN   	/* SDH Read Wait Enable */
-#define RSI_PID0				0xFFC038D0		/* RSI Peripheral ID Register 0 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID0  			RSI_PID0         	/* SDH Peripheral Identification0 */
-#define RSI_PID1				0xFFC038D4		/* RSI Peripheral ID Register 1 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID1  			RSI_PID1         	/* SDH Peripheral Identification1 */
-#define RSI_PID2				0xFFC038D8		/* RSI Peripheral ID Register 2 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID2  			RSI_PID2         	/* SDH Peripheral Identification2 */
-#define RSI_PID3				0xFFC038DC		/* RSI Peripheral ID Register 3 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID3  			RSI_PID3         	/* SDH Peripheral Identification3 */
-/* RSI Registers */
-
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define	RE                 0x00000001     /* Receiver Enable                                    */
-#define	ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define	HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define	HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define	PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define	PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define	IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define	DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define	PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define	PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define	RAF                0x00001000     /* Receive-All Mode                                   */
-#define	TE                 0x00010000     /* Transmitter Enable                                 */
-#define	DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define	DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define	DC                 0x00080000     /* Deferral Check                                     */
-#define	BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define	BOLMT_10           0x00000000     /*		10-bit range                            */
-#define	BOLMT_8            0x00100000     /*		8-bit range                             */
-#define	BOLMT_4            0x00200000     /*		4-bit range                             */
-#define	BOLMT_1            0x00300000     /*		1-bit range                             */
-#define	DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define	LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define	RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define	RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define	FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define	LB                 0x08000000     /* Internal Loopback Enable                           */
-#define	DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define	STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define	STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define	STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define	STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define	REGAD              0x000007C0     /* STA Register Address                               */
-#define	PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#ifdef _MISRA_RULES
-#define	SET_REGAD(x) (((x)&0x1Fu)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1Fu)<< 11 )   /* Set PHY Device Address                             */
-#else
-#define	SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-#endif /* _MISRA_RULES */
-
-/* EMAC_STADAT Mask */
-
-#define	STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define	FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define	FLCE               0x00000002     /* Flow Control Enable                                */
-#define	PCF                0x00000004     /* Pass Control Frames                                */
-#define	BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define	FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#ifdef _MISRA_RULES
-#define	SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time                                   */
-#else
-#define	SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define	CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define	MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define	RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define	GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define	MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define	RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define	WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define	WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define	WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define	WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define	WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define	WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define	WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define	WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define	WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define	WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define	WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define	WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_OFF(x) (((x)&0xFFu)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFFu)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#else
-#define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#endif /* _MISRA_RULES */
-
-/* Set ALL Offsets */
-#define	SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define	WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define	WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#else
-#define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define	WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define	WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF2_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#else
-#define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSCTL Masks */
-
-#define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#ifdef _MISRA_RULES
-#define	SET_MDCDIV(x) (((x)&0x3Fu)<< 8)   /* Set MDC Clock Divisor                                 */
-#else
-#define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSTAT Masks */
-
-#define	PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define	MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define	RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define	TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define	WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define	RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define	TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define	STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define	RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define	RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define	RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define	RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define	RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define	RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define	RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define	RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define	RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define	RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define	RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define	RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define	RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define	RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define	RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define	RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define	RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define	RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define	RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define	RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define	RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define	TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define	TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define	TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define	TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define	TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define	TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define	TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define	TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define	TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define	TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define	TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define	TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define	TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define	TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define	TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define	RSTC              0x00000001    /* Reset All Counters                                     */
-#define	CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define	CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define	MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define	RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define	RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define	RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define	RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define	RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define	RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define	RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define	RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define	RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define	RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define	RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define	RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define	RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define	RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define	RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define	RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define	RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define	RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define	RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define	RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define	RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define	RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define	RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define	RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define	TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define	TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define	TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define	TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define	TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define	TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define	TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define	TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define	TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define	TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define	TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define	TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define	TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define	TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define	TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define	TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define	TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define	TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define	TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define	TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define	TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define	EMAC_PTP_CTL_EN	 0x1		  /* Block Enable								*/
-#define	EMAC_PTP_CTL_TL	 0x2		  /* Time Stamp Lock							*/
-#define	EMAC_PTP_CTL_CKS	 0xC		  /* Clock source for the PTP_TSYNC block				*/
-#define	EMAC_PTP_CTL_ASEN	 0x10		  /* Auxiliary Snapshot Enable					*/
-#define	EMAC_PTP_CTL_CKDIV 0x60		  /* Divider for the selected PTP_CLK output			*/
-#define	EMAC_PTP_CTL_PPSEN 0x80		  /* Pulse Per Second (PPS) Enable					*/
-#define	EMAC_PTP_CTL_EFTM	 0x100	  /* Ethernet Frame type field compare mask			*/
-#define	EMAC_PTP_CTL_IPVM	 0x200	  /* IP Version field compare mask					*/
-#define	EMAC_PTP_CTL_IPTM	 0x400	  /* IP Type Frame field (Layer 4 protocol) compare mask	*/
-#define	EMAC_PTP_CTL_UDPEM 0x800	  /* UDP Event port field compare mask				*/
-#define	EMAC_PTP_CTL_PTPCM 0x1000	  /* PTP Control field compare mask					*/
-#define	EMAC_PTP_CTL_CKOEN 0x2000	  /* Clock output Enable						*/
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define	EMAC_PTP_IE_ALIE	 0x1		  /* Alarm Feature and Interrupt Enable				*/
-#define	EMAC_PTP_IE_RXEIE	 0x2		  /* Receive Event Interrupt Enable					*/
-#define	EMAC_PTP_IE_RXGIE	 0x4		  /* Receive General Interrupt Enable				*/
-#define	EMAC_PTP_IE_TXIE	 0x8		  /* Transmit Interrupt Enable					*/
-#define	EMAC_PTP_IE_TXOVE	 0x10		  /* Transmit Overrun Error Interrupt Enable			*/
-#define	EMAC_PTP_IE_RXOVE	 0x20		  /* Receive Overrun Error Interrupt Enable			*/
-#define	EMAC_PTP_IE_ASIE	 0x40		  /* Auxiliary Snapshot Interrupt Enable				*/
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define	EMAC_PTP_ISTAT_ALS  0x1		  /* Alarm Status								*/
-#define	EMAC_PTP_ISTAT_RXEL 0x2		  /* Receive Event Interrupt Locked					*/
-#define	EMAC_PTP_ISTAT_RXGL 0x4		  /* Receive General Interrupt Locked				*/
-#define	EMAC_PTP_ISTAT_TXTL 0x8		  /* Transmit Snapshot Locked						*/
-#define	EMAC_PTP_ISTAT_RXOV 0x10	  /* Receive Snapshot Overrun Status				*/
-#define	EMAC_PTP_ISTAT_TXOV 0x20	  /* Transmit snapshot Overrun Status				*/
-#define	EMAC_PTP_ISTAT_ASL  0x40	  /* Auxiliary Snapshot Interrupt Status				*/
-
-
-/* Bit masks for RSI_PWR_CONTROL */
-#define                    PWR_ON  0x3        		/* Power On */
-#define                RSI_CMD_OD  0x40       		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 SD_CMD_OD  RSI_CMD_OD 		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nSD_CMD_OD  0x0
-/* legacy bit mask (below) provided for backwards code compatibility */
-#if 0
-#define                       TBD  0x3c       		/* TBD */
-#endif
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   ROD_CTL  0x80
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nROD_CTL  0x80
-
-
-/* Bit masks for RSI_CLK_CONTROL */
-#define                    CLKDIV  0xff           	/* MC_CLK Divisor */
-#define                    CLK_EN  0x100          	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CLK_E  CLK_EN         	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCLK_E  0x0
-#define                 PWR_SV_EN  0x200          	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  PWR_SV_E  PWR_SV_EN      	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400          	/* Bypass Divisor */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCLKDIV_BYPASS  0x0
-#define                  BUS_MODE  0x1800           /* Bus width selection */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  WIDE_BUS  0x0800    	/* Wide Bus Mode Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nWIDE_BUS  0x0
-
-
-/* Bit masks for RSI_COMMAND */
-#define                   CMD_IDX  0x3f           	/* Command Index */
-#define                CMD_RSP_EN  0x40           	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CMD_RSP  CMD_RSP_EN     	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_RSP  0x0
-#define               CMD_LRSP_EN  0x80           	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_L_RSP  CMD_LRSP_EN    	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_L_RSP  0x0
-#define                CMD_INT_EN  0x100          	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_INT_E  CMD_INT_EN     	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_INT_E  0x0
-#define               CMD_PEND_EN  0x200          	/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                CMD_PEND_E  CMD_PEND_EN		/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nCMD_PEND_E  0x0
-#define                    CMD_EN  0x400			/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CMD_E  CMD_EN          	/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCMD_E  0x0
-
-
-/* Bit masks for RSI_RESP_CMD */
-#define                  RESP_CMD  0x3f       		/* Response Command */
-
-/* Bit masks for RSI_DATA_LGTH */
-#define               DATA_LENGTH  0xffff       	/* Data Length */
-
-
-/* Bit masks for RSI_DATA_CONTROL */
-#define                   DATA_EN  0x1            	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     DTX_E  DATA_EN        	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nDTX_E  0x0
-#define                  DATA_DIR  0x2            	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   DTX_DIR  DATA_DIR      	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDTX_DIR  0x0
-#define                 DATA_MODE  0x4            	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  DTX_MODE  DATA_MODE      	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nDTX_MODE  0x0
-#define               DATA_DMA_EN  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 DTX_DMA_E  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nDTX_DMA_E  0x0
-#define             DATA_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              DTX_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-#define 		             CEATA_EN  0x100	      /* CE-ATA operation mode enable */
-#define 		         CEATA_CCS_EN  0x200	      /* CE-ATA CCS mode enable */
-
-/* Bit masks for RSI_DATA_CNT */
-#define               DATA_COUNT  0xffff       		/* Data Count */
-
-/* Bit masks for RSI_STATUS */
-#define              CMD_CRC_FAIL  0x1        		/* CMD CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        		/* Data CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        		/* CMD Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        		/* Data Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       		/* Transmit Underrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       		/* Receive Overrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       		/* CMD Response End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       		/* CMD Sent */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      		/* Data End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      		/* Start Bit Error */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      		/* Data Block End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      		/* CMD Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     		/* Transmit Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     		/* Receive Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     		/* Transmit FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     		/* Receive FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    		/* Transmit FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    		/* Receive FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    		/* Transmit FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    		/* Receive FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   		/* Transmit Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   		/* Receive Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for RSI_STATCL */
-
-#define         CMD_CRC_FAIL_STAT  0x1       		/* CMD CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        		/* Data CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        		/* CMD Time Out Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        		/* Data Time Out status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       		/* Transmit Underrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       		/* Receive Overrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       		/* CMD Response End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       		/* CMD Sent Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      		/* Data End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      		/* Start Bit Error Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      		/* Data Block End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for RSI_MASKx */
-
-#define         CMD_CRC_FAIL_MASK  0x1        		/* CMD CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        		/* Data CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        		/* CMD Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        		/* Data Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       		/* Transmit Underrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       		/* Receive Overrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       		/* CMD Response End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       		/* CMD Sent Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      		/* Data End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      		/* Start Bit Error Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      		/* Data Block End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      		/* CMD Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     		/* Transmit Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     		/* Receive Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     		/* Transmit FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     		/* Receive FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    		/* Transmit FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    		/* Receive FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    		/* Transmit FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    		/* Receive FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   		/* Transmit Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   		/* Receive Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for RSI_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff     		/* FIFO Count */
-
-/* Bit masks for RSI_CEATA_CONTROL */
-#define		  CEATA_TX_CCSD  0x1	    		/* Send CE-ATA CCSD sequence */
-
-/* Bit masks for RSI_ESTAT */
-#define              SDIO_INT_DET  0x2        		/* SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       		/* SD Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nSD_CARD_DET  0x0
-#define             CEATA_INT_DET  0x20
-
-/* Bit masks for RSI_EMASK */
-#define         SDIO_INT_DET_MASK  0x2                /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SDIO_MSK  SDIO_INT_DET_MASK  /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nSDIO_MSK  0x0
-#define          SD_CARD_DET_MASK  0x10               /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SCD_MASK  SD_CARD_DET_MASK   /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nSCD_MSK  0x0
-#define        CEATA_INT_DET_MASK  0x20
-
-
-/* Bit masks for SDH_CFG */
-
-/* Left in for backwards compatibility */
-#define                RSI_CLK_EN  0x1
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CLKS_EN  RSI_CLK_EN        	/* Clocks Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCLKS_EN  0x0
-#define                  SDIO4_EN  0x4        		/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      SD4E  SDIO4_EN        	/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     nSD4E  0x0
-#define                     MW_EN  0x8        		/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       MWE  MW_EN        	/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nMWE  0x0
-#define                   RSI_RST  0x10       		/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    SD_RST  RSI_RST       	/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nSD_RST  0x0
-#define                    PU_DAT  0x20       		/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PUP_SDDAT  PU_DAT       	/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPUP_SDDAT  0x0
-#define                   PU_DAT3  0x40       		/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                PUP_SDDAT3  PU_DAT3       	/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nPUP_SDDAT3  0x0
-#define                   PD_DAT3  0x80       		/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PD_SDDAT3  PD_DAT3       	/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPD_SDDAT3  0x0
-
-
-/* Bit masks for RSI_RD_WAIT_EN */
-#define			 SDIO_RWR  0x1             	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       RWR  SDIO_RWR        	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nRWR  0x0
-
-/* Bit masks for RSI_PIDx */
-#define                   RSI_PID  0xff			/* RSI Peripheral ID */
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF516_H */
diff --git a/libgloss/bfin/include/defBF518.h b/libgloss/bfin/include/defBF518.h
deleted file mode 100644
index c618ea69a..000000000
--- a/libgloss/bfin/include/defBF518.h
+++ /dev/null
@@ -1,962 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF518_H
-#define _DEF_BF518_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
-
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include <defBF51x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"macros not strictly following 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-/* EMAC PTP (IEEE 1588) */
-
-#define EMAC_PTP_CTL		  0xffc030a0	 /* PTP Block Control 						   */
-#define EMAC_PTP_IE		  0xffc030a4   	 /* PTP Block Interrupt Enable 				   */
-#define EMAC_PTP_ISTAT		  0xffc030a8       /* PTP Block Interrupt Status 				   */
-#define EMAC_PTP_FOFF		  0xffc030ac       /* PTP Filter offset Register 				   */
-#define EMAC_PTP_FV1		  0xffc030b0       /* PTP Filter Value Register 1 				   */
-#define EMAC_PTP_FV2		  0xffc030b4       /* PTP Filter Value Register 2 				   */
-#define EMAC_PTP_FV3		  0xffc030b8       /* PTP Filter Value Register 3 				   */
-#define EMAC_PTP_ADDEND		  0xffc030bc       /* PTP Addend for Frequency Compensation 		   */
-#define EMAC_PTP_ACCR		  0xffc030c0   	 /* PTP Accumulator for Frequency Compensation 		   */
-#define EMAC_PTP_OFFSET		  0xffc030c4   	 /* PTP Time Offset Register 					   */
-#define EMAC_PTP_TIMELO		  0xffc030c8   	 /* PTP Precision Clock Time Low 				   */
-#define EMAC_PTP_TIMEHI		  0xffc030cc   	 /* PTP Precision Clock Time High 				   */
-#define EMAC_PTP_RXSNAPLO	  0xffc030d0   	 /* PTP Receive Snapshot Register Low 			   */
-#define EMAC_PTP_RXSNAPHI	  0xffc030d4   	 /* PTP Receive Snapshot Register High 			   */
-#define EMAC_PTP_TXSNAPLO	  0xffc030d8   	 /* PTP Transmit Snapshot Register Low 			   */
-#define EMAC_PTP_TXSNAPHI	  0xffc030dc   	 /* PTP Transmit Snapshot Register High 			   */
-#define EMAC_PTP_ALARMLO	  0xffc030e0   	 /* PTP Alarm time Low 						   */
-#define EMAC_PTP_ALARMHI	  0xffc030e4   	 /* PTP Alarm time High 					   */
-#define EMAC_PTP_ID_OFF		  0xffc030e8   	 /* PTP Capture ID offset register 				   */
-#define EMAC_PTP_ID_SNAP	  0xffc030ec   	 /* PTP Capture ID register 					   */
-#define EMAC_PTP_PPS_STARTLOP	  0xffc030f0   	 /* PPS Start Time Low 						   */
-#define EMAC_PTP_PPS_STARTHIP	  0xffc030f4   	 /* PPS Start Time High						   */
-#define EMAC_PTP_PPS_PERIOD	  0xffc030f8   	 /* PPS Count Register						   */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-
-/* RSI Registers */
-
-#define RSI_PWR_CONTROL			0xFFC03800		/* RSI Power Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PWR_CTL  			RSI_PWR_CONTROL	/* SDH Power Control */
-#define RSI_CLK_CONTROL			0xFFC03804		/* RSI Clock Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CLK_CTL  			RSI_CLK_CONTROL	/* SDH Clock Control */
-#define RSI_ARGUMENT			0xFFC03808		/* RSI Argument Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_ARGUMENT  			RSI_ARGUMENT	/* SDH Argument */
-#define RSI_COMMAND			0xFFC0380C		/* RSI Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_COMMAND  			RSI_COMMAND      	/* SDH Command */
-#define RSI_RESP_CMD			0xFFC03810		/* RSI Response Command Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESP_CMD  			RSI_RESP_CMD     	/* SDH Response Command */
-#define RSI_RESPONSE0			0xFFC03814		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE0  			RSI_RESPONSE0    	/* SDH Response0 */
-#define RSI_RESPONSE1			0xFFC03818		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE1  			RSI_RESPONSE1    	/* SDH Response1 */
-#define RSI_RESPONSE2			0xFFC0381C	/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE2  			RSI_RESPONSE2    	/* SDH Response2 */
-#define RSI_RESPONSE3			0xFFC03820		/* RSI Response Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RESPONSE3  			RSI_RESPONSE3    	/* SDH Response3 */
-#define RSI_DATA_TIMER			0xFFC03824		/* RSI Data Timer Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_TIMER 			RSI_DATA_TIMER  	/* SDH Data Timer */
-#define RSI_DATA_LGTH			0xFFC03828		/* RSI Data Length Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_LGTH  			RSI_DATA_LGTH    	/* SDH Data Length */
-#define RSI_DATA_CONTROL		0xFFC0382C		/* RSI Data Control Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CTL  			RSI_DATA_CONTROL 	/* SDH Data Control */
-#define RSI_DATA_CNT			0xFFC03830		/* RSI Data Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_DATA_CNT  			RSI_DATA_CNT     	/* SDH Data Counter */
-#define RSI_STATUS			0xFFC03834		/* RSI Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS  			RSI_STATUS       	/* SDH Status */
-#define RSI_STATUSCL			0xFFC03838		/* RSI Status Clear Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_STATUS_CLR  		RSI_STATUSCL     	/* SDH Status Clear */
-#define RSI_MASK0				0xFFC0383C		/* RSI Interrupt 0 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK0  			RSI_MASK0        	/* SDH Interrupt0 Mask */
-#define RSI_MASK1				0xFFC03840		/* RSI Interrupt 1 Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_MASK1  			RSI_MASK1        	/* SDH Interrupt1 Mask */
-#define RSI_FIFO_CNT			0xFFC03848		/* RSI FIFO Counter Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO_CNT  			RSI_FIFO_CNT     	/* SDH FIFO Counter */
-#define RSI_CEATA_CONTROL		0xFFC0384C		/* RSI CEATA Register */
-#define RSI_FIFO				0xFFC03880		/* RSI Data FIFO Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_FIFO  			RSI_FIFO         	/* SDH Data FIFO */
-#define RSI_ESTAT				0xFFC038C0		/* RSI Exception Status Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_STATUS  			RSI_ESTAT        	/* SDH Exception Status */
-#define RSI_EMASK				0xFFC038C4		/* RSI Exception Mask Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_E_MASK  			RSI_EMASK        	/* SDH Exception Mask */
-#define RSI_CONFIG			0xFFC038C8		/* RSI Configuration Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_CFG  				RSI_CONFIG       	/* SDH Configuration */
-#define RSI_RD_WAIT_EN			0xFFC038CC		/* RSI Read Wait Enable Register */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_RD_WAIT_EN  		RSI_RD_WAIT_EN   	/* SDH Read Wait Enable */
-#define RSI_PID0				0xFFC038D0		/* RSI Peripheral ID Register 0 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID0  			RSI_PID0         	/* SDH Peripheral Identification0 */
-#define RSI_PID1				0xFFC038D4		/* RSI Peripheral ID Register 1 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID1  			RSI_PID1         	/* SDH Peripheral Identification1 */
-#define RSI_PID2				0xFFC038D8		/* RSI Peripheral ID Register 2 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID2  			RSI_PID2         	/* SDH Peripheral Identification2 */
-#define RSI_PID3				0xFFC038DC		/* RSI Peripheral ID Register 3 */
-/* legacy register name (below) provided for backwards code compatibility */
-#define SDH_PID3  			RSI_PID3         	/* SDH Peripheral Identification3 */
-/* RSI Registers */
-
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define	RE                 0x00000001     /* Receiver Enable                                    */
-#define	ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define	HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define	HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define	PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define	PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define	IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define	DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define	PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define	PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define	RAF                0x00001000     /* Receive-All Mode                                   */
-#define	TE                 0x00010000     /* Transmitter Enable                                 */
-#define	DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define	DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define	DC                 0x00080000     /* Deferral Check                                     */
-#define	BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define	BOLMT_10           0x00000000     /*		10-bit range                            */
-#define	BOLMT_8            0x00100000     /*		8-bit range                             */
-#define	BOLMT_4            0x00200000     /*		4-bit range                             */
-#define	BOLMT_1            0x00300000     /*		1-bit range                             */
-#define	DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define	LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define	RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define	RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define	FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define	LB                 0x08000000     /* Internal Loopback Enable                           */
-#define	DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define	STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define	STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define	STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define	STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define	REGAD              0x000007C0     /* STA Register Address                               */
-#define	PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#ifdef _MISRA_RULES
-#define	SET_REGAD(x) (((x)&0x1Fu)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1Fu)<< 11 )   /* Set PHY Device Address                             */
-#else
-#define	SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-#endif /* _MISRA_RULES */
-
-/* EMAC_STADAT Mask */
-
-#define	STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define	FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define	FLCE               0x00000002     /* Flow Control Enable                                */
-#define	PCF                0x00000004     /* Pass Control Frames                                */
-#define	BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define	FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#ifdef _MISRA_RULES
-#define	SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time                                   */
-#else
-#define	SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define	CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define	MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define	RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define	GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define	MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define	RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define	WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define	WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define	WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define	WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define	WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define	WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define	WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define	WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define	WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define	WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define	WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define	WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_OFF(x) (((x)&0xFFu)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFFu)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#else
-#define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#endif /* _MISRA_RULES */
-
-/* Set ALL Offsets */
-#define	SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define	WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define	WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#else
-#define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define	WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define	WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF2_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#else
-#define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSCTL Masks */
-
-#define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#ifdef _MISRA_RULES
-#define	SET_MDCDIV(x) (((x)&0x3Fu)<< 8)   /* Set MDC Clock Divisor                                 */
-#else
-#define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSTAT Masks */
-
-#define	PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define	MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define	RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define	TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define	WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define	RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define	TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define	STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define	RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define	RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define	RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define	RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define	RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define	RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define	RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define	RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define	RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define	RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define	RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define	RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define	RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define	RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define	RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define	RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define	RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define	RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define	RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define	RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define	RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define	TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define	TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define	TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define	TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define	TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define	TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define	TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define	TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define	TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define	TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define	TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define	TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define	TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define	TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define	TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define	RSTC              0x00000001    /* Reset All Counters                                     */
-#define	CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define	CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define	MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define	RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define	RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define	RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define	RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define	RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define	RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define	RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define	RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define	RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define	RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define	RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define	RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define	RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define	RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define	RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define	RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define	RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define	RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define	RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define	RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define	RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define	RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define	RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define	RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define	TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define	TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define	TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define	TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define	TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define	TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define	TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define	TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define	TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define	TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define	TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define	TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define	TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define	TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define	TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define	TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define	TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define	TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define	TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define	TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define	TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-
-/* Bit masks for EMAC_PTP_CTL */
-
-#define	EMAC_PTP_CTL_EN	 0x1		  /* Block Enable								*/
-#define	EMAC_PTP_CTL_TL	 0x2		  /* Time Stamp Lock							*/
-#define	EMAC_PTP_CTL_CKS	 0xC		  /* Clock source for the PTP_TSYNC block				*/
-#define	EMAC_PTP_CTL_ASEN	 0x10		  /* Auxiliary Snapshot Enable					*/
-#define	EMAC_PTP_CTL_CKDIV 0x60		  /* Divider for the selected PTP_CLK output			*/
-#define	EMAC_PTP_CTL_PPSEN 0x80		  /* Pulse Per Second (PPS) Enable					*/
-#define	EMAC_PTP_CTL_EFTM	 0x100	  /* Ethernet Frame type field compare mask			*/
-#define	EMAC_PTP_CTL_IPVM	 0x200	  /* IP Version field compare mask					*/
-#define	EMAC_PTP_CTL_IPTM	 0x400	  /* IP Type Frame field (Layer 4 protocol) compare mask	*/
-#define	EMAC_PTP_CTL_UDPEM 0x800	  /* UDP Event port field compare mask				*/
-#define	EMAC_PTP_CTL_PTPCM 0x1000	  /* PTP Control field compare mask					*/
-#define	EMAC_PTP_CTL_CKOEN 0x2000	  /* Clock output Enable						*/
-
-/* Bit masks for EMAC_PTP_IE */
-
-#define	EMAC_PTP_IE_ALIE	 0x1		  /* Alarm Feature and Interrupt Enable				*/
-#define	EMAC_PTP_IE_RXEIE	 0x2		  /* Receive Event Interrupt Enable					*/
-#define	EMAC_PTP_IE_RXGIE	 0x4		  /* Receive General Interrupt Enable				*/
-#define	EMAC_PTP_IE_TXIE	 0x8		  /* Transmit Interrupt Enable					*/
-#define	EMAC_PTP_IE_TXOVE	 0x10		  /* Transmit Overrun Error Interrupt Enable			*/
-#define	EMAC_PTP_IE_RXOVE	 0x20		  /* Receive Overrun Error Interrupt Enable			*/
-#define	EMAC_PTP_IE_ASIE	 0x40		  /* Auxiliary Snapshot Interrupt Enable				*/
-
-/* Bit masks for EMAC_PTP_ISTAT */
-
-#define	EMAC_PTP_ISTAT_ALS  0x1		  /* Alarm Status								*/
-#define	EMAC_PTP_ISTAT_RXEL 0x2		  /* Receive Event Interrupt Locked					*/
-#define	EMAC_PTP_ISTAT_RXGL 0x4		  /* Receive General Interrupt Locked				*/
-#define	EMAC_PTP_ISTAT_TXTL 0x8		  /* Transmit Snapshot Locked						*/
-#define	EMAC_PTP_ISTAT_RXOV 0x10	  /* Receive Snapshot Overrun Status				*/
-#define	EMAC_PTP_ISTAT_TXOV 0x20	  /* Transmit snapshot Overrun Status				*/
-#define	EMAC_PTP_ISTAT_ASL  0x40	  /* Auxiliary Snapshot Interrupt Status				*/
-
-
-/* Bit masks for RSI_PWR_CONTROL */
-#define                    PWR_ON  0x3        		/* Power On */
-#define                RSI_CMD_OD  0x40       		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 SD_CMD_OD  RSI_CMD_OD 		/* Open Drain Output */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nSD_CMD_OD  0x0
-/* legacy bit mask (below) provided for backwards code compatibility */
-#if 0
-#define                       TBD  0x3c       		/* TBD */
-#endif
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   ROD_CTL  0x80
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nROD_CTL  0x80
-
-
-/* Bit masks for RSI_CLK_CONTROL */
-#define                    CLKDIV  0xff           	/* MC_CLK Divisor */
-#define                    CLK_EN  0x100          	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CLK_E  CLK_EN         	/* MC_CLK Bus Clock Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCLK_E  0x0
-#define                 PWR_SV_EN  0x200          	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  PWR_SV_E  PWR_SV_EN      	/* Power Save Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400          	/* Bypass Divisor */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCLKDIV_BYPASS  0x0
-#define                  BUS_MODE  0x1800           /* Bus width selection */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  WIDE_BUS  0x0800    	/* Wide Bus Mode Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nWIDE_BUS  0x0
-
-
-/* Bit masks for RSI_COMMAND */
-#define                   CMD_IDX  0x3f           	/* Command Index */
-#define                CMD_RSP_EN  0x40           	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CMD_RSP  CMD_RSP_EN     	/* Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_RSP  0x0
-#define               CMD_LRSP_EN  0x80           	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_L_RSP  CMD_LRSP_EN    	/* Long Response */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_L_RSP  0x0
-#define                CMD_INT_EN  0x100          	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 CMD_INT_E  CMD_INT_EN     	/* Command Interrupt */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nCMD_INT_E  0x0
-#define               CMD_PEND_EN  0x200          	/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                CMD_PEND_E  CMD_PEND_EN		/* Command Pending */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nCMD_PEND_E  0x0
-#define                    CMD_EN  0x400			/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     CMD_E  CMD_EN          	/* Command Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nCMD_E  0x0
-
-
-/* Bit masks for RSI_RESP_CMD */
-#define                  RESP_CMD  0x3f       		/* Response Command */
-
-/* Bit masks for RSI_DATA_LGTH */
-#define               DATA_LENGTH  0xffff       	/* Data Length */
-
-
-/* Bit masks for RSI_DATA_CONTROL */
-#define                   DATA_EN  0x1            	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     DTX_E  DATA_EN        	/* Data Transfer Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    nDTX_E  0x0
-#define                  DATA_DIR  0x2            	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   DTX_DIR  DATA_DIR      	/* Data Transfer Direction */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDTX_DIR  0x0
-#define                 DATA_MODE  0x4            	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  DTX_MODE  DATA_MODE      	/* Data Transfer Mode */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nDTX_MODE  0x0
-#define               DATA_DMA_EN  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 DTX_DMA_E  0x8            	/* Data Transfer DMA Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nDTX_DMA_E  0x0
-#define             DATA_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              DTX_BLK_LGTH  0xf0           	/* Data Transfer Block Length */
-#define 		             CEATA_EN  0x100	      /* CE-ATA operation mode enable */
-#define 		         CEATA_CCS_EN  0x200	      /* CE-ATA CCS mode enable */
-
-/* Bit masks for RSI_DATA_CNT */
-#define               DATA_COUNT  0xffff       		/* Data Count */
-
-/* Bit masks for RSI_STATUS */
-#define              CMD_CRC_FAIL  0x1        		/* CMD CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        		/* Data CRC Fail */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        		/* CMD Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        		/* Data Time Out */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       		/* Transmit Underrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       		/* Receive Overrun */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       		/* CMD Response End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       		/* CMD Sent */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      		/* Data End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      		/* Start Bit Error */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      		/* Data Block End */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      		/* CMD Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     		/* Transmit Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     		/* Receive Active */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     		/* Transmit FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     		/* Receive FIFO Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    		/* Transmit FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    		/* Receive FIFO Full */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    		/* Transmit FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    		/* Receive FIFO Empty */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   		/* Transmit Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   		/* Receive Data Available */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for RSI_STATCL */
-
-#define         CMD_CRC_FAIL_STAT  0x1       		/* CMD CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        		/* Data CRC Fail Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        		/* CMD Time Out Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        		/* Data Time Out status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       		/* Transmit Underrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       		/* Receive Overrun Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       		/* CMD Response End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       		/* CMD Sent Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      		/* Data End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      		/* Start Bit Error Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      		/* Data Block End Status */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for RSI_MASKx */
-
-#define         CMD_CRC_FAIL_MASK  0x1        		/* CMD CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        		/* Data CRC Fail Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        		/* CMD Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        		/* Data Time Out Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       		/* Transmit Underrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       		/* Receive Overrun Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       		/* CMD Response End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       		/* CMD Sent Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      		/* Data End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      		/* Start Bit Error Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      		/* Data Block End Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      		/* CMD Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     		/* Transmit Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     		/* Receive Active Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     		/* Transmit FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     		/* Receive FIFO Status Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    		/* Transmit FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    		/* Receive FIFO Full Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    		/* Transmit FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    		/* Receive FIFO Empty Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   		/* Transmit Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   		/* Receive Data Available Mask */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for RSI_FIFO_CNT */
-#define                FIFO_COUNT  0x7fff     		/* FIFO Count */
-
-/* Bit masks for RSI_CEATA_CONTROL */
-#define		  CEATA_TX_CCSD  0x1	    		/* Send CE-ATA CCSD sequence */
-
-/* Bit masks for RSI_ESTAT */
-#define              SDIO_INT_DET  0x2        		/* SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       		/* SD Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define              nSD_CARD_DET  0x0
-#define             CEATA_INT_DET  0x20
-
-/* Bit masks for RSI_EMASK */
-#define         SDIO_INT_DET_MASK  0x2                /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SDIO_MSK  SDIO_INT_DET_MASK  /* Mask SDIO Int Detected */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 nSDIO_MSK  0x0
-#define          SD_CARD_DET_MASK  0x10               /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  SCD_MASK  SD_CARD_DET_MASK   /* Mask Card Detect */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nSCD_MSK  0x0
-#define        CEATA_INT_DET_MASK  0x20
-
-
-/* Bit masks for SDH_CFG */
-
-/* Left in for backwards compatibility */
-#define                RSI_CLK_EN  0x1
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   CLKS_EN  RSI_CLK_EN        	/* Clocks Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                  nCLKS_EN  0x0
-#define                  SDIO4_EN  0x4        		/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      SD4E  SDIO4_EN        	/* SDIO 4-Bit Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                     nSD4E  0x0
-#define                     MW_EN  0x8        		/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       MWE  MW_EN        	/* Moving Window Enable */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nMWE  0x0
-#define                   RSI_RST  0x10       		/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                    SD_RST  RSI_RST       	/* SDMMC Reset */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                   nSD_RST  0x0
-#define                    PU_DAT  0x20       		/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PUP_SDDAT  PU_DAT       	/* Pull-up SD_DAT */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPUP_SDDAT  0x0
-#define                   PU_DAT3  0x40       		/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                PUP_SDDAT3  PU_DAT3       	/* Pull-up SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define               nPUP_SDDAT3  0x0
-#define                   PD_DAT3  0x80       		/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                 PD_SDDAT3  PD_DAT3       	/* Pull-down SD_DAT3 */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                nPD_SDDAT3  0x0
-
-
-/* Bit masks for RSI_RD_WAIT_EN */
-#define			 SDIO_RWR  0x1             	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                       RWR  SDIO_RWR        	/* Read Wait Request */
-/* legacy bit mask (below) provided for backwards code compatibility */
-#define                      nRWR  0x0
-
-/* Bit masks for RSI_PIDx */
-#define                   RSI_PID  0xff			/* RSI Peripheral ID */
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF518_H */
diff --git a/libgloss/bfin/include/defBF51x_base.h b/libgloss/bfin/include/defBF51x_base.h
deleted file mode 100644
index 2cc069757..000000000
--- a/libgloss/bfin/include/defBF51x_base.h
+++ /dev/null
@@ -1,2016 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF51x_base.h
-**
-** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF51x peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _DEF_BF51X_H
-#define _DEF_BF51X_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-
-/* ************************************************************************************************************** */
-/*                           SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x                            */
-/* ************************************************************************************************************** */
-
-/* Clock and System Control		(0xFFC00000 - 0xFFC000FF)									*/
-#define PLL_CTL				0xFFC00000	/* PLL Control Register								*/
-#define PLL_DIV				0xFFC00004	/* PLL Divide Register								*/
-#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register					*/
-#define PLL_STAT				0xFFC0000C	/* PLL Status Register								*/
-#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register							*/
-#define CHIPID        			0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller 	(0xFFC00100 - 0xFFC001FF)									*/
-#define SWRST				0xFFC00100	/* Software Reset Register							*/
-#define SYSCR				0xFFC00104	/* System Configuration Register						*/
-
-#define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IMASK				SIC_IMASK0
-#define SIC_IAR0				0xFFC00110	/* Interrupt Assignment Register 0						*/
-#define SIC_IAR1				0xFFC00114	/* Interrupt Assignment Register 1						*/
-#define SIC_IAR2				0xFFC00118	/* Interrupt Assignment Register 2						*/
-#define SIC_IAR3				0xFFC0011C	/* Interrupt Assignment Register 3						*/
-#define SIC_ISR0				0xFFC00120	/* Interrupt Status Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_ISR				SIC_ISR0
-#define SIC_IWR0				0xFFC00124	/* Interrupt Wakeup Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IWR				SIC_IWR0
-
-/* SIC Additions to ADSP-BF51x 	(0xFFC0014C - 0xFFC00162) 									*/
-#define SIC_IMASK1                  0xFFC0014C  /* Interrupt Mask register of SIC2 						*/
-#define SIC_IAR4                    0xFFC00150  /* Interrupt Assignment register4						*/
-#define SIC_IAR5                    0xFFC00154  /* Interrupt Assignment register5 						*/
-#define SIC_IAR6                    0xFFC00158  /* Interrupt Assignment register6 						*/
-#define SIC_IAR7                    0xFFC0015C  /* Interrupt Assignment register7 						*/
-#define SIC_ISR1                    0xFFC00160  /* Interrupt Statur register 							*/
-#define SIC_IWR1                    0xFFC00164  /* Interrupt Wakeup register 							*/
-
-
-/* Watchdog Timer				(0xFFC00200 - 0xFFC002FF) 									*/
-#define WDOG_CTL				0xFFC00200	/* Watchdog Control Register							*/
-#define WDOG_CNT				0xFFC00204	/* Watchdog Count Register							*/
-#define WDOG_STAT				0xFFC00208	/* Watchdog Status Register							*/
-
-
-/* Real Time Clock 			(0xFFC00300 - 0xFFC003FF) 									*/
-#define RTC_STAT				0xFFC00300	/* RTC Status Register								*/
-#define RTC_ICTL				0xFFC00304	/* RTC Interrupt Control Register						*/
-#define RTC_ISTAT				0xFFC00308	/* RTC Interrupt Status Register						*/
-#define RTC_SWCNT				0xFFC0030C	/* RTC Stopwatch Count Register						*/
-#define RTC_ALARM				0xFFC00310	/* RTC Alarm Time Register							*/
-#define RTC_FAST				0xFFC00314	/* RTC Prescaler Enable Register						*/
-#define RTC_PREN				0xFFC00314	/* RTC Prescaler Enable Alternate Macro					*/
-
-
-/* UART0 Controller 			(0xFFC00400 - 0xFFC004FF) 									*/
-#define UART0_THR				0xFFC00400	/* Transmit Holding register							*/
-#define UART0_RBR				0xFFC00400	/* Receive Buffer register							*/
-#define UART0_DLL				0xFFC00400	/* Divisor Latch (Low-Byte)							*/
-#define UART0_IER				0xFFC00404	/* Interrupt Enable Register							*/
-#define UART0_DLH				0xFFC00404	/* Divisor Latch (High-Byte)							*/
-#define UART0_IIR				0xFFC00408	/* Interrupt Identification Register					*/
-#define UART0_LCR				0xFFC0040C	/* Line Control Register							*/
-#define UART0_MCR				0xFFC00410	/* Modem Control Register							*/
-#define UART0_LSR				0xFFC00414	/* Line Status Register								*/
-#define UART0_SCR				0xFFC0041C	/* SCR Scratch Register								*/
-#define UART0_GCTL			0xFFC00424	/* Global Control Register							*/
-
-
-/* SPI Controller				(0xFFC00500 - 0xFFC005FF) 									*/
-#define SPI0_CTL				0xFFC00500	/* SPI Control Register								*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_CTL				SPI0_CTL
-#define SPI0_FLG				0xFFC00504	/* SPI Flag register								*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_FLG				SPI0_FLG
-#define SPI0_STAT				0xFFC00508	/* SPI Status register								*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_STAT				SPI0_STAT
-#define SPI0_TDBR				0xFFC0050C	/* SPI Transmit Data Buffer Register					*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_TDBR				SPI0_TDBR
-#define SPI0_RDBR				0xFFC00510	/* SPI Receive Data Buffer Register						*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_RDBR				SPI0_RDBR
-#define SPI0_BAUD				0xFFC00514	/* SPI Baud rate Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_BAUD				SPI0_BAUD
-#define SPI0_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SPI_SHADOW			SPI0_SHADOW
-
-
-/* TIMER0-7 Registers 			(0xFFC00600 - 0xFFC006FF)									*/
-#define TIMER0_CONFIG			0xFFC00600	/* Timer 0 Configuration Register						*/
-#define TIMER0_COUNTER			0xFFC00604	/* Timer 0 Counter Register							*/
-#define TIMER0_PERIOD			0xFFC00608	/* Timer 0 Period Register							*/
-#define TIMER0_WIDTH			0xFFC0060C	/* Timer 0 Width Register							*/
-
-#define TIMER1_CONFIG			0xFFC00610	/* Timer 1 Configuration Register  						*/
-#define TIMER1_COUNTER			0xFFC00614	/* Timer 1 Counter Register        						*/
-#define TIMER1_PERIOD			0xFFC00618	/* Timer 1 Period Register         						*/
-#define TIMER1_WIDTH			0xFFC0061C	/* Timer 1 Width Register          						*/
-
-#define TIMER2_CONFIG			0xFFC00620	/* Timer 2 Configuration Register  						*/
-#define TIMER2_COUNTER			0xFFC00624	/* Timer 2 Counter Register        						*/
-#define TIMER2_PERIOD			0xFFC00628	/* Timer 2 Period Register         						*/
-#define TIMER2_WIDTH			0xFFC0062C	/* Timer 2 Width Register          						*/
-
-#define TIMER3_CONFIG			0xFFC00630	/* Timer 3 Configuration Register						*/
-#define TIMER3_COUNTER			0xFFC00634	/* Timer 3 Counter Register							*/
-#define TIMER3_PERIOD			0xFFC00638	/* Timer 3 Period Register							*/
-#define TIMER3_WIDTH			0xFFC0063C	/* Timer 3 Width Register							*/
-
-#define TIMER4_CONFIG			0xFFC00640	/* Timer 4 Configuration Register  						*/
-#define TIMER4_COUNTER			0xFFC00644	/* Timer 4 Counter Register        						*/
-#define TIMER4_PERIOD			0xFFC00648	/* Timer 4 Period Register         						*/
-#define TIMER4_WIDTH			0xFFC0064C	/* Timer 4 Width Register          						*/
-
-#define TIMER5_CONFIG			0xFFC00650	/* Timer 5 Configuration Register  						*/
-#define TIMER5_COUNTER			0xFFC00654	/* Timer 5 Counter Register        						*/
-#define TIMER5_PERIOD			0xFFC00658	/* Timer 5 Period Register         						*/
-#define TIMER5_WIDTH			0xFFC0065C	/* Timer 5 Width Register          						*/
-
-#define TIMER6_CONFIG			0xFFC00660	/* Timer 6 Configuration Register  						*/
-#define TIMER6_COUNTER			0xFFC00664	/* Timer 6 Counter Register        						*/
-#define TIMER6_PERIOD			0xFFC00668	/* Timer 6 Period Register         						*/
-#define TIMER6_WIDTH			0xFFC0066C	/* Timer 6 Width Register          						*/
-
-#define TIMER7_CONFIG			0xFFC00670	/* Timer 7 Configuration Register  						*/
-#define TIMER7_COUNTER			0xFFC00674	/* Timer 7 Counter Register        						*/
-#define TIMER7_PERIOD			0xFFC00678	/* Timer 7 Period Register         						*/
-#define TIMER7_WIDTH			0xFFC0067C	/* Timer 7 Width Register       						*/
-
-#define TIMER_ENABLE			0xFFC00680	/* Timer Enable Register							*/
-#define TIMER_DISABLE			0xFFC00684	/* Timer Disable Register							*/
-#define TIMER_STATUS			0xFFC00688	/* Timer Status Register							*/
-
-
-/* General Purpose I/O Port F 	(0xFFC00700 - 0xFFC007FF) 									*/
-#define PORTFIO				0xFFC00700	/* Port F I/O Pin State Specify Register					*/
-#define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register			*/
-#define PORTFIO_SET			0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register				*/
-#define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
-#define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register			*/
-#define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register				*/
-#define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register				*/
-#define PORTFIO_MASKA_TOGGLE		0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register			*/
-#define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register			*/
-#define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register				*/
-#define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register				*/
-#define PORTFIO_MASKB_TOGGLE		0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register			*/
-#define PORTFIO_DIR			0xFFC00730	/* Port F I/O Direction Register						*/
-#define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
-#define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register					*/
-#define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register					*/
-#define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
-
-
-/* SPORT0 Controller 			(0xFFC00800 - 0xFFC008FF) 									*/
-#define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register				*/
-#define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register				*/
-#define SPORT0_TCLKDIV			0xFFC00808	/* SPORT0 Transmit Clock Divider						*/
-#define SPORT0_TFSDIV			0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider					*/
-#define SPORT0_TX				0xFFC00810	/* SPORT0 TX Data Register							*/
-#define SPORT0_RX				0xFFC00818	/* SPORT0 RX Data Register							*/
-#define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register				*/
-#define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register				*/
-#define SPORT0_RCLKDIV			0xFFC00828	/* SPORT0 Receive Clock Divider						*/
-#define SPORT0_RFSDIV			0xFFC0082C	/* SPORT0 Receive Frame Sync Divider					*/
-#define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
-#define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register						*/
-#define SPORT0_MCMC1			0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1			*/
-#define SPORT0_MCMC2			0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2			*/
-#define SPORT0_MTCS0			0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0			*/
-#define SPORT0_MTCS1			0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1			*/
-#define SPORT0_MTCS2			0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2			*/
-#define SPORT0_MTCS3			0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3			*/
-#define SPORT0_MRCS0			0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0			*/
-#define SPORT0_MRCS1			0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1			*/
-#define SPORT0_MRCS2			0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2			*/
-#define SPORT0_MRCS3			0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3			*/
-
-
-/* SPORT1 Controller 			(0xFFC00900 - 0xFFC009FF) 									*/
-#define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register				*/
-#define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register				*/
-#define SPORT1_TCLKDIV			0xFFC00908	/* SPORT1 Transmit Clock Divider						*/
-#define SPORT1_TFSDIV			0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider					*/
-#define SPORT1_TX				0xFFC00910	/* SPORT1 TX Data Register							*/
-#define SPORT1_RX				0xFFC00918	/* SPORT1 RX Data Register							*/
-#define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register				*/
-#define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register				*/
-#define SPORT1_RCLKDIV			0xFFC00928	/* SPORT1 Receive Clock Divider						*/
-#define SPORT1_RFSDIV			0xFFC0092C	/* SPORT1 Receive Frame Sync Divider					*/
-#define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
-#define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register						*/
-#define SPORT1_MCMC1			0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1			*/
-#define SPORT1_MCMC2			0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2			*/
-#define SPORT1_MTCS0			0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0			*/
-#define SPORT1_MTCS1			0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1			*/
-#define SPORT1_MTCS2			0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2			*/
-#define SPORT1_MTCS3			0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3			*/
-#define SPORT1_MRCS0			0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0			*/
-#define SPORT1_MRCS1			0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1			*/
-#define SPORT1_MRCS2			0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2			*/
-#define SPORT1_MRCS3			0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3			*/
-
-
-/* External Bus Interface Unit 	(0xFFC00A00 - 0xFFC00AFF) 									*/
-#define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register				*/
-#define EBIU_AMBCTL0			0xFFC00A04	/* Asynchronous Memory Bank Control Register 0				*/
-#define EBIU_AMBCTL1			0xFFC00A08	/* Asynchronous Memory Bank Control Register 1				*/
-#define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register						*/
-#define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register						*/
-#define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register					*/
-#define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register							*/
-
-
-/* DMA Traffic Control Registers 	(0xFFC00B00 - 0xFFC00BFF)									*/
-#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register						*/
-#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register				*/
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility 					*/
-#define DMA_TCPER				0xFFC00B0C	/* Traffic Control Periods Register						*/
-#define DMA_TCCNT				0xFFC00B10	/* Traffic Control Current Counts Register				*/
-
-/* DMA Controller 			(0xFFC00C00 - 0xFFC00FFF) 									*/
-#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register			*/
-#define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
-#define DMA0_CONFIG			0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
-#define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
-#define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
-#define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
-#define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
-#define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register			*/
-#define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register					*/
-#define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
-#define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register					*/
-#define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register					*/
-#define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register					*/
-
-#define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register			*/
-#define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
-#define DMA1_CONFIG			0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
-#define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
-#define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
-#define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
-#define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
-#define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register			*/
-#define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register					*/
-#define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
-#define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register					*/
-#define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register					*/
-#define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register					*/
-
-#define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register			*/
-#define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
-#define DMA2_CONFIG			0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
-#define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
-#define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
-#define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
-#define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
-#define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register			*/
-#define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register					*/
-#define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
-#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register					*/
-#define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register					*/
-#define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register					*/
-
-#define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register			*/
-#define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
-#define DMA3_CONFIG			0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
-#define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
-#define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
-#define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
-#define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
-#define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register			*/
-#define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register					*/
-#define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
-#define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register					*/
-#define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register					*/
-#define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register					*/
-
-#define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register			*/
-#define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
-#define DMA4_CONFIG			0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
-#define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
-#define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
-#define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
-#define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
-#define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register			*/
-#define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register					*/
-#define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
-#define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register					*/
-#define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register					*/
-#define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register					*/
-
-#define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register			*/
-#define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
-#define DMA5_CONFIG			0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
-#define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
-#define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
-#define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
-#define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
-#define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register			*/
-#define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register					*/
-#define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
-#define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register					*/
-#define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register					*/
-#define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register					*/
-
-#define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register			*/
-#define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
-#define DMA6_CONFIG			0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
-#define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
-#define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
-#define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
-#define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
-#define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register			*/
-#define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register					*/
-#define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
-#define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register					*/
-#define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register					*/
-#define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register					*/
-
-#define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register			*/
-#define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
-#define DMA7_CONFIG			0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
-#define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
-#define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
-#define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
-#define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
-#define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register			*/
-#define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register					*/
-#define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
-#define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register					*/
-#define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register					*/
-#define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register					*/
-
-#define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register			*/
-#define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG			0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register			*/
-#define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register					*/
-#define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register					*/
-#define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register					*/
-#define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register					*/
-
-#define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register			*/
-#define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register					*/
-#define DMA9_CONFIG			0xFFC00E48	/* DMA Channel 9 Configuration Register					*/
-#define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register						*/
-#define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register						*/
-#define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register						*/
-#define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register						*/
-#define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register			*/
-#define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register					*/
-#define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register				*/
-#define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register					*/
-#define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register					*/
-#define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register					*/
-
-#define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register			*/
-#define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register					*/
-#define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register					*/
-#define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register						*/
-#define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register						*/
-#define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register						*/
-#define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register						*/
-#define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register			*/
-#define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register				*/
-#define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register				*/
-#define DMA10_PERIPHERAL_MAP		0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register					*/
-#define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register				*/
-#define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register				*/
-
-#define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register			*/
-#define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register					*/
-#define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register					*/
-#define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register						*/
-#define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register						*/
-#define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register						*/
-#define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register						*/
-#define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register			*/
-#define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register				*/
-#define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register				*/
-#define DMA11_PERIPHERAL_MAP		0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register					*/
-#define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register				*/
-#define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register				*/
-
-#define MDMA_D0_NEXT_DESC_PTR		0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register 	*/
-#define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register			*/
-#define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register			*/
-#define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register				*/
-#define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register			*/
-#define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register				*/
-#define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register			*/
-#define MDMA_D0_CURR_DESC_PTR		0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register*/
-#define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register 		*/
-#define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register		*/
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register  		*/
-#define MDMA_D0_CURR_X_COUNT		0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register		*/
-#define MDMA_D0_CURR_Y_COUNT		0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register		*/
-
-#define MDMA_S0_NEXT_DESC_PTR		0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register		*/
-#define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register			*/
-#define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register			*/
-#define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register				*/
-#define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register				*/
-#define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register				*/
-#define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register				*/
-#define MDMA_S0_CURR_DESC_PTR		0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register	*/
-#define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register			*/
-#define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register			*/
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register			*/
-#define MDMA_S0_CURR_X_COUNT		0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register			*/
-#define MDMA_S0_CURR_Y_COUNT		0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register			*/
-
-#define MDMA_D1_NEXT_DESC_PTR		0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register	*/
-#define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register			*/
-#define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register			*/
-#define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register				*/
-#define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register			*/
-#define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register				*/
-#define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register			*/
-#define MDMA_D1_CURR_DESC_PTR		0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register*/
-#define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register		*/
-#define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register		*/
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register		*/
-#define MDMA_D1_CURR_X_COUNT		0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register		*/
-#define MDMA_D1_CURR_Y_COUNT		0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register		*/
-
-#define MDMA_S1_NEXT_DESC_PTR		0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register		*/
-#define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register			*/
-#define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register			*/
-#define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register				*/
-#define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register				*/
-#define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register				*/
-#define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register				*/
-#define MDMA_S1_CURR_DESC_PTR		0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register	*/
-#define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register			*/
-#define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register			*/
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register			*/
-#define MDMA_S1_CURR_X_COUNT		0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register			*/
-#define MDMA_S1_CURR_Y_COUNT		0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register			*/
-
-
-/* Parallel Peripheral Interface 	(0xFFC01000 - 0xFFC010FF) 									*/
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register								*/
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register								*/
-#define PPI_COUNT				0xFFC01008	/* PPI Transfer Count Register						*/
-#define PPI_DELAY				0xFFC0100C	/* PPI Delay Count Register							*/
-#define PPI_FRAME				0xFFC01010	/* PPI Frame Length Register							*/
-
-
-/* Two-Wire Interface 			(0xFFC01400 - 0xFFC014FF)									*/
-#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register						*/
-#define TWI_CONTROL			0xFFC01404	/* TWI Control Register								*/
-#define TWI_SLAVE_CTL			0xFFC01408	/* Slave Mode Control Register						*/
-#define TWI_SLAVE_STAT			0xFFC0140C	/* Slave Mode Status Register							*/
-#define TWI_SLAVE_ADDR			0xFFC01410	/* Slave Mode Address Register						*/
-#define TWI_MASTER_CTL			0xFFC01414	/* Master Mode Control Register						*/
-#define TWI_MASTER_STAT			0xFFC01418	/* Master Mode Status Register						*/
-#define TWI_MASTER_ADDR			0xFFC0141C	/* Master Mode Address Register						*/
-#define TWI_INT_STAT			0xFFC01420	/* TWI Interrupt Status Register						*/
-#define TWI_INT_MASK			0xFFC01424	/* TWI Master Interrupt Mask Register					*/
-#define TWI_FIFO_CTL			0xFFC01428	/* FIFO Control Register							*/
-#define TWI_FIFO_STAT			0xFFC0142C	/* FIFO Status Register								*/
-#define TWI_XMT_DATA8			0xFFC01480	/* FIFO Transmit Data Single Byte Register				*/
-#define TWI_XMT_DATA16			0xFFC01484	/* FIFO Transmit Data Double Byte Register				*/
-#define TWI_RCV_DATA8			0xFFC01488	/* FIFO Receive Data Single Byte Register					*/
-#define TWI_RCV_DATA16			0xFFC0148C	/* FIFO Receive Data Double Byte Register					*/
-
-
-/* General Purpose I/O Port G 	(0xFFC01500 - 0xFFC015FF) 									*/
-#define PORTGIO				0xFFC01500	/* Port G I/O Pin State Specify Register					*/
-#define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register			*/
-#define PORTGIO_SET			0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register				*/
-#define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register					*/
-#define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register			*/
-#define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register				*/
-#define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register				*/
-#define PORTGIO_MASKA_TOGGLE		0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register			*/
-#define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register			*/
-#define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register				*/
-#define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register				*/
-#define PORTGIO_MASKB_TOGGLE		0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register			*/
-#define PORTGIO_DIR			0xFFC01530	/* Port G I/O Direction Register						*/
-#define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register					*/
-#define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register					*/
-#define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register					*/
-#define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register						*/
-
-
-/* General Purpose I/O Port H 	(0xFFC01700 - 0xFFC017FF) 									*/
-#define PORTHIO				0xFFC01700	/* Port H I/O Pin State Specify Register					*/
-#define PORTHIO_CLEAR			0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register			*/
-#define PORTHIO_SET			0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register				*/
-#define PORTHIO_TOGGLE			0xFFC0170C	/* Port H I/O Pin State Toggle Register					*/
-#define PORTHIO_MASKA			0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register			*/
-#define PORTHIO_MASKA_CLEAR		0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register				*/
-#define PORTHIO_MASKA_SET		0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register				*/
-#define PORTHIO_MASKA_TOGGLE		0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register			*/
-#define PORTHIO_MASKB			0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register			*/
-#define PORTHIO_MASKB_CLEAR		0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register				*/
-#define PORTHIO_MASKB_SET		0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register				*/
-#define PORTHIO_MASKB_TOGGLE		0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register			*/
-#define PORTHIO_DIR			0xFFC01730	/* Port H I/O Direction Register						*/
-#define PORTHIO_POLAR			0xFFC01734	/* Port H I/O Source Polarity Register					*/
-#define PORTHIO_EDGE			0xFFC01738	/* Port H I/O Source Sensitivity Register					*/
-#define PORTHIO_BOTH			0xFFC0173C	/* Port H I/O Set on BOTH Edges Register					*/
-#define PORTHIO_INEN			0xFFC01740	/* Port H I/O Input Enable Register						*/
-
-
-/* UART1 Controller			(0xFFC02000 - 0xFFC020FF)									*/
-#define UART1_THR				0xFFC02000	/* Transmit Holding register							*/
-#define UART1_RBR				0xFFC02000	/* Receive Buffer register							*/
-#define UART1_DLL				0xFFC02000	/* Divisor Latch (Low-Byte)							*/
-#define UART1_IER				0xFFC02004	/* Interrupt Enable Register							*/
-#define UART1_DLH				0xFFC02004	/* Divisor Latch (High-Byte)							*/
-#define UART1_IIR				0xFFC02008	/* Interrupt Identification Register					*/
-#define UART1_LCR				0xFFC0200C	/* Line Control Register							*/
-#define UART1_MCR				0xFFC02010	/* Modem Control Register							*/
-#define UART1_LSR				0xFFC02014	/* Line Status Register								*/
-#define UART1_SCR				0xFFC0201C	/* SCR Scratch Register								*/
-#define UART1_GCTL			0xFFC02024	/* Global Control Register							*/
-
-
-/* Pin Control Registers		(0xFFC03200 - 0xFFC032FF)									*/
-#define PORTF_FER				0xFFC03200	/* Port F Function Enable Register (Alternate/Flag*)			*/
-#define PORTG_FER				0xFFC03204	/* Port G Function Enable Register (Alternate/Flag*)			*/
-#define PORTH_FER				0xFFC03208	/* Port H Function Enable Register (Alternate/Flag*)			*/
-
-
-/* GPIO PIN mux 				(0xFFC03210 - OxFFC03288) 									*/
-#define PORTF_MUX               	0xFFC03210  /* Port F mux control 								*/
-#define PORTG_MUX               	0xFFC03214  /* Port G mux control 								*/
-#define PORTH_MUX               	0xFFC03218  /* Port H mux control 								*/
-#define PORTF_DRIVE             	0xFFC03220  /* Port F drive strength control 						*/
-#define PORTG_DRIVE             	0xFFC03224  /* Port G drive strength control 						*/
-#define PORTH_DRIVE             	0xFFC03228  /* Port H drive strength control 						*/
-#define PORTF_HYSTERESIS        	0xFFC03240  /* Port F Schmitt trigger control 						*/
-#define PORTG_HYSTERESIS        	0xFFC03244  /* Port G Schmitt trigger control 						*/
-#define PORTH_HYSTERESIS        	0xFFC03248  /* Port H Schmitt trigger control 						*/
-#define NONGPIO_DRIVE           	0xFFC03280  /* Misc Port drive strength control		 				*/
-#define NONGPIO_HYSTERESIS      	0xFFC03288  /* Misc Port Schmitt Trigger control					*/
-
-
-/* Handshake MDMA Registers		(0xFFC03300 - 0xFFC033FF)									*/
-#define HMDMA0_CONTROL			0xFFC03300	/* Handshake MDMA0 Control Register						*/
-#define HMDMA0_ECINIT			0xFFC03304	/* HMDMA0 Initial Edge Count Register					*/
-#define HMDMA0_BCINIT			0xFFC03308	/* HMDMA0 Initial Block Count Register					*/
-#define HMDMA0_ECURGENT			0xFFC0330C	/* HMDMA0 Urgent Edge Count Threshhold Register				*/
-#define HMDMA0_ECOVERFLOW		0xFFC03310	/* HMDMA0 Edge Count Overflow Interrupt Register			*/
-#define HMDMA0_ECOUNT			0xFFC03314	/* HMDMA0 Current Edge Count Register					*/
-#define HMDMA0_BCOUNT			0xFFC03318	/* HMDMA0 Current Block Count Register					*/
-
-#define HMDMA1_CONTROL			0xFFC03340	/* Handshake MDMA1 Control Register						*/
-#define HMDMA1_ECINIT			0xFFC03344	/* HMDMA1 Initial Edge Count Register					*/
-#define HMDMA1_BCINIT			0xFFC03348	/* HMDMA1 Initial Block Count Register					*/
-#define HMDMA1_ECURGENT			0xFFC0334C	/* HMDMA1 Urgent Edge Count Threshhold Register				*/
-#define HMDMA1_ECOVERFLOW		0xFFC03350	/* HMDMA1 Edge Count Overflow Interrupt Register			*/
-#define HMDMA1_ECOUNT			0xFFC03354	/* HMDMA1 Current Edge Count Register					*/
-#define HMDMA1_BCOUNT			0xFFC03358	/* HMDMA1 Current Block Count Register					*/
-
-
-/* SPI1 Controller 			(0xFFC03400 - 0xFFC034FF)									*/
-#define SPI1_CTL				0xFFC03400	/* SPI0 Control Register							*/
-#define SPI1_FLG				0xFFC03404	/* SPI0 Flag register								*/
-#define SPI1_STAT				0xFFC03408	/* SPI0 Status register								*/
-#define SPI1_TDBR				0xFFC0340C	/* SPI0 Transmit Data Buffer Register					*/
-#define SPI1_RDBR				0xFFC03410	/* SPI0 Receive Data Buffer Register					*/
-#define SPI1_BAUD				0xFFC03414	/* SPI0 Baud rate Register							*/
-#define SPI1_SHADOW			0xFFC03418	/* SPI0_RDBR Shadow Register							*/
-
-
-/* Counter Registers 			(0xFFC03500 - 0xFFC035FF)									*/
-#define CNT_CONFIG			0xFFC03500  /* Configuration Register 							*/
-#define CNT_IMASK				0xFFC03504  /* Interrupt Mask Register 							*/
-#define CNT_STATUS			0xFFC03508  /* Status Register 								*/
-#define CNT_COMMAND			0xFFC0350C  /* Command Register 								*/
-#define CNT_DEBOUNCE			0xFFC03510  /* Debounce Register 								*/
-#define CNT_COUNTER			0xFFC03514  /* Counter Register 								*/
-#define CNT_MAX				0xFFC03518  /* Boundry Value Register - max count					*/
-#define CNT_MIN				0xFFC0351C  /* Boundry Value Register - min count					*/
-
-
-/* OTP/FUSE Registers 			(0xFFC03600 - 0xFFC036FF)									*/
-#define OTP_CONTROL			0xFFC03600  /* OTPSEC Fuse Control  							*/
-#define OTP_BEN				0xFFC03604  /* OTPSEC Fuse Byte Enable 							*/
-#define OTP_STATUS			0xFFC03608  /* OTPSEC Fuse Status 								*/
-#define OTP_TIMING			0xFFC0360C  /* OTPSEC Fuse SCLK Divider 							*/
-
-/* Security Registers 																*/
-#define SECURE_SYSSWT			0xFFC03620  /* OTPSEC Secure System Switches 						*/
-#define SECURE_CONTROL			0xFFC03624  /* OTPSEC Secure Control							*/
-#define SECURE_STATUS			0xFFC03628  /* OTPSEC Secure Status 							*/
-
-/* OTP Read/Write Data Buffer Registers 													*/
-#define OTP_DATA0				0xFFC03680  /* OTP Read Write buffer 							*/
-#define OTP_DATA1  			0xFFC03684  /* OTP Read Write buffer 							*/
-#define OTP_DATA2  			0xFFC03688  /* OTP Read Write buffer 							*/
-#define OTP_DATA3  			0xFFC0368C  /* OTP Read Write buffer 							*/
-
-
-/* Motor Control PWM Registers 	(0xFFC03700 - 0xFFC037FF)									*/
-#define PWM_CTRL				0xFFC03700	/* PWM Control Register 							*/
-#define PWM_STAT				0xFFC03704	/* PWM Status Register 								*/
-#define PWM_TM				0xFFC03708	/* PWM Period Register 								*/
-#define PWM_DT 				0xFFC0370C	/* PWM Dead Time Register							*/
-#define PWM_GATE				0xFFC03710 	/* PWM Chopping Control								*/
-#define PWM_CHA				0xFFC03714	/* PWM Channel A Duty Control							*/
-#define PWM_CHB				0xFFC03718	/* PWM Channel B Duty Control							*/
-#define PWM_CHC				0xFFC0371C	/* PWM Channel C Duty Control							*/
-#define PWM_SEG				0xFFC03720	/* PWM Crossover and Output Enable						*/
-#define PWM_SYNCWT			0xFFC03724	/* PWM Sync pulse width control						*/
-#define PWM_CHAL				0xFFC03728	/* PWM Channel AL Duty Control (SR mode only)				*/
-#define PWM_CHBL				0xFFC0372C	/* PWM Channel BL Duty Control (SR mode only)				*/
-#define PWM_CHCL				0xFFC03730	/* PWM Channel CL Duty Control (SR mode only)				*/
-#define PWM_LSI				0xFFC03734  /* Low Side Invert (SR mode only)						*/
-#define PWM_STAT2				0xFFC03738	/* PWM Status Register								*/
-
-
-
-/******************************************************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**			Use these macros carefully, as any that do left shifts for field
-**			depositing will result in the lower order bits being destroyed.  Any
-**			macro that shifts left to properly position the bit-field should be
-**			used as part of an OR to initialize a register and NOT as a dynamic
-**			modifier UNLESS the lower order bits are saved and ORed back in when
-**			the macro is used.
-*******************************************************************************************************************/
-
-/************************************** PLL AND RESET MASKS *******************************************************/
-
-/* PLL_CTL Masks */
-#define DF					0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2						*/
-#define PLL_OFF				0x0002	/* PLL Not Powered								*/
-#define STOPCK				0x0008	/* Core Clock Off									*/
-#define PDWN				0x0020	/* Enter Deep Sleep Mode							*/
-#define IN_DELAY				0x0040	/* Add 200ps Delay To EBIU Input Latches					*/
-#define OUT_DELAY				0x0080	/* Add 200ps Delay To EBIU Output Signals					*/
-#define BYPASS				0x0100	/* Bypass the PLL									*/
-#define MSEL				0x7E00	/* Multiplier Select For CCLK/VCO Factors					*/
-
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x)	(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL					*/
-#else
-#define SET_MSEL(x)	(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL					*/
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL				0x000F	/* System Select									*/
-#define CSEL				0x0030	/* Core Select									*/
-#define CSEL_DIV1				0x0000	/* CCLK = VCO / 1									*/
-#define CSEL_DIV2				0x0010	/* CCLK = VCO / 2									*/
-#define CSEL_DIV4				0x0020	/* CCLK = VCO / 4									*/
-#define CSEL_DIV8				0x0030	/* CCLK = VCO / 8									*/
-
-/* PLL_DIV Macros	*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)			((x)&0xFu)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL					*/
-#else
-#define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL					*/
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks */
-#define FREQ				0x3000	/* Switching Oscillator Frequency For Regulator				*/
-#define HIBERNATE				0x0000	/* Powerdown/Bypass On-Board Regulation					*/
-
-#define VLEV				0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications */
-#define VLEV_085				0x0040	/* VLEV = 0.85 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_090				0x0050	/* VLEV = 0.90 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_095				0x0060	/* VLEV = 0.95 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_100				0x0070	/* VLEV = 1.00 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_105				0x0080	/* VLEV = 1.05 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_110				0x0090	/* VLEV = 1.10 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_115				0x00A0	/* VLEV = 1.15 V (See Datasheet for Regulator Tolerance)		*/
-#define VLEV_120				0x00B0	/* VLEV = 1.20 V (See Datasheet for Regulator Tolerance)		*/
-
-#define WAKE				0x0100	/* Enable RTC/Reset Wakeup From Hibernate					*/
-/* no USB WAKE UP */
-#define PHYWE				0x0400	/* Enable PHY Wakeup From Hibernate						*/
-#define CLKBUFOE				0x4000	/* CLKIN Buffer Output Enable							*/
-#define PHYCLKOE				CLKBUFOE	/* Alternative legacy name for the above 					*/
-#define SCKELOW				0x8000	/* Enable Drive CKE Low During Reset					*/
-
-/* PLL_STAT Masks	*/
-#define ACTIVE_PLLENABLED		0x0001	/* Processor In Active Mode With PLL Enabled				*/
-#define FULL_ON				0x0002	/* Processor In Full On Mode							*/
-#define ACTIVE_PLLDISABLED		0x0004	/* Processor In Active Mode With PLL Disabled				*/
-#define PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached						*/
-#define VSTAT				0x0080	/* Voltage Regulator Status: Regulator at programmed voltage */
-
-/* SWRST Masks */
-#define SYSTEM_RESET			0x0007	/* Initiates A System Software Reset					*/
-#define DOUBLE_FAULT			0x0008	/* Core Double Fault Causes Reset						*/
-#define RESET_DOUBLE			0x2000	/* SW Reset Generated By Core Double-Fault				*/
-#define RESET_WDOG			0x4000	/* SW Reset Generated By Watchdog Timer					*/
-#define RESET_SOFTWARE			0x8000	/* SW Reset Occurred Since Last Read Of SWRST				*/
-
-/* SYSCR Masks */
-#define BMODE_BYPASS        0x0000  /* No boot mode */
-#define BMODE_FLASH         0x0001  /* Use Boot ROM to load from 8-bit or 16-bit flash */
-#define BMODE_SPI0MEM_INT   0x0002  /* Boot from internal SPI0 memory */
-#define BMODE_SPI0MEM_EXT   0x0003  /* Boot from external SPI0 memory */
-#define BMODE_SPI0HOST      0x0004  /* Boot from SPI0 host (slave mode) */
-#define BMODE_OTPMEM        0x0005  /* Boot from OTP memory */
-#define BMODE_SDRAMMEM      0x0006  /* Boot from SDRAM memory (warm boot) */
-#define BMODE_UART0HOST     0x0007  /* Boot from UART0 host */
-#define BMODE               0x0007  /* Boot Mode. Mirror of BMODE Mode Pins */
-
-#define BCODE 				0x00F0
-#define BCODE_NORMAL 			0x0000 	/* normal boot, update PLL/VR, quickboot as by WURESET		*/
-#define BCODE_NOBOOT 			0x0010 	/* bypass boot, don't update PLL/VR 					*/
-#define BCODE_QUICKBOOT 		0x0020 	/* quick boot, overrule WURESET, don't update PLL/VR 			*/
-#define BCODE_ALLBOOT			0x0040 	/* no quick boot, overrule WURESET, don't update PLL/VR 		*/
-#define BCODE_FULLBOOT 			0x0060 	/* no quick boot, overrule WURESET, update PLL/VR 			*/
-
-#define WURESET 				0x1000 	/* wakeup event since last hardware reset			 		*/
-#define DFRESET 				0x2000 	/* recent reset was due to a double fault event 			*/
-#define WDRESET 				0x4000 	/* recent reset was due to a watchdog event 				*/
-#define SWRESET 				0x8000 	/* recent reset was issued by software 					*/
-
-/*********************************  SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/
-
-/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
-#define IRQ_PLL_WAKEUP			0x00000001	/* PLL Wakeup Interrupt			 					*/
-#define IRQ_DMA_ERR0   			0x00000002  /* Error Interrupt (DMA error 0 interrupt (generic)) 			*/
-#define IRQ_DMAR0      			0x00000004  /* DMAR0 Block (DMAR0 block interrupt) 					*/
-#define IRQ_DMAR1      			0x00000008  /* DMAR1 Block  (DMAR1 block interrupt) 					*/
-#define IRQ_DMAR0_ERR  			0x00000010  /* Error Interrupt (DMAR0 overflow error interrupt)  			*/
-#define IRQ_DMAR1_ERR  			0x00000020  /* Error Interrupt (DMAR1 overflow error interrupt)  			*/
-#define IRQ_PPI_ERR    			0x00000040  /* Error Interrupt (PPI error interrupt) 					*/
-#define IRQ_MAC_ERR    			0x00000080  /* Error Interrupt (MAC status interrupt) 				*/
-#define IRQ_SPORT0_ERR 			0x00000100  /* Error Interrupt (SPORT0 status interrupt) 				*/
-#define IRQ_SPORT1_ERR 			0x00000200  /* Error Interrupt (SPORT1 status interrupt) 				*/
-#define IRQ_PTP_ERR			0x00000400  /* Error Interrupt (PTP error interrupt)					*/
-
-#define IRQ_UART0_ERR 			0x00001000  /* Error Interrupt (UART0 status interrupt) 				*/
-#define IRQ_UART1_ERR  			0x00002000  /* Error Interrupt (UART1 status interrupt) 				*/
-#define IRQ_RTC		   		0x00004000  /* Real Time Clock Interrupt 							*/
-#define IRQ_DMA0	   			0x00008000  /* DMA channel 0 (PPI/NFC) Interrupt 					*/
-#define IRQ_DMA3	   			0x00010000  /* DMA Channel 3 (SPORT0 RX) Interrupt 					*/
-#define IRQ_DMA4	   			0x00020000  /* DMA Channel 4 (SPORT0 TX) Interrupt 					*/
-#define IRQ_DMA5	   			0x00040000  /* DMA Channel 5 (SPORT1 RX) Interrupt 					*/
-#define IRQ_DMA6	   			0x00080000  /* DMA Channel 6 (SPORT1 TX) Interrupt 		 			*/
-#define IRQ_TWI		   		0x00100000  /* TWI Interrupt									*/
-#define IRQ_DMA7	   			0x00200000  /* DMA Channel 7 (SPI) Interrupt 						*/
-#define IRQ_DMA8	   			0x00400000  /* DMA Channel 8 (UART0 RX) Interrupt 					*/
-#define IRQ_DMA9	   			0x00800000  /* DMA Channel 9 (UART0 TX) Interrupt 					*/
-#define IRQ_DMA10	   			0x01000000  /* DMA Channel 10 (UART1 RX) Interrupt 					*/
-#define IRQ_DMA11	   			0x02000000  /* DMA Channel 11 (UART1 TX) Interrupt 					*/
-#define IRQ_OTP	   			0x04000000  /* OTP Interrupt 									*/
-#define IRQ_CNT  	   			0x08000000  /* GP Counter Interrupt  							*/
-#define IRQ_DMA1	   			0x10000000  /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt				*/
-#define IRQ_PFA_PORTH  			0x20000000  /* PF Port H Interrupt A 							*/
-#define IRQ_DMA2	   			0x40000000  /* DMA Channel 2 (Ethernet TX/NFC) Interrupt 				*/
-#define IRQ_PFB_PORTH  			0x80000000  /* PF Port H  Interrupt B 							*/
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
-#define IRQ_TIMER0			0x00000001	/* Timer 0 Interrupt								*/
-#define IRQ_TIMER1			0x00000002	/* Timer 1 Interrupt 								*/
-#define IRQ_TIMER2			0x00000004	/* Timer 2 Interrupt 								*/
-#define IRQ_TIMER3			0x00000008	/* Timer 3 Interrupt 								*/
-#define IRQ_TIMER4			0x00000010	/* Timer 4 Interrupt 								*/
-#define IRQ_TIMER5			0x00000020	/* Timer 5 Interrupt 								*/
-#define IRQ_TIMER6			0x00000040	/* Timer 6 Interrupt 								*/
-#define IRQ_TIMER7			0x00000080	/* Timer 7 Interrupt 								*/
-#define IRQ_PFA_PORTG			0x00000100	/* PF Port G Interrupt A 							*/
-#define IRQ_PFB_PORTG			0x00000200	/* PF Port G Interrupt B		 					*/
-#define IRQ_DMA12				0x00000400	/* DMA Channels 12 (MDMA0 Destination) TX Interrupt			*/
-#define IRQ_DMA13				0x00000400	/* DMA Channels 13 (MDMA0 Source) RX Interrupt				*/
-#define IRQ_DMA14				0x00000800	/* DMA Channels 14 (MDMA1 Destination) TX Interrupt			*/
-#define IRQ_DMA15				0x00000800	/* DMA Channels 15 (MDMA1 Source) RX Interrupt 				*/
-#define IRQ_WDOG				0x00001000	/* Software Watchdog Timer Interrupt 					*/
-#define IRQ_PFA_PORTF			0x00002000	/* PF Port F Interrupt A		 					*/
-#define IRQ_PFB_PORTF			0x00004000	/* PF Port F Interrupt B 							*/
-#define IRQ_SPI0_ERR     		0x00008000  /* Error Interrupt (SPI0 status interrupt) 				*/
-#define IRQ_SPI1_ERR			0x00010000	/* Error Interrupt (SPI1 status interrupt)				*/
-
-#define IRQ_RSI_INT0			0x00080000	/* USB EINT interrupt 								*/
-#define IRQ_RSI_INT1			0x00100000	/* USB INT0 interrupt 								*/
-#define IRQ_PWM_TRIPINT			0x00200000	/* USB INT1 interrupt 								*/
-#define IRQ_PWM_SYNCINT			0x00400000	/* USB INT1 interrupt 								*/
-#define IRQ_PTP_STATINT			0x00800000	/* USB DMAINT interrupt								*/
-
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define IWR_DISABLE_ALL        	0x00000000	/* Wakeup Disable all peripherals 						*/
-#define IWR_ENABLE_ALL          	0xFFFFFFFF	/* Wakeup Enable all peripherals 						*/
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)           	(1 << (x))	/* Wakeup Enable Peripheral #x 						*/
-#define IWR_DISABLE(x)	 (0xFFFFFFFF^(1<<(x)))	/* Wakeup Disable Peripheral #x 						*/
-
-
-#ifdef _MISRA_RULES
-#define _MF15 	0xFu
-#define _MF7 	7u
-#else
-#define _MF15 	0xF
-#define _MF7 	7
-#endif /* _MISRA_RULES */
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #0 assigned IVG #x    */
-#define P1_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #1 assigned IVG #x    */
-#define P2_IVG(x)       ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #2 assigned IVG #x    */
-#define P3_IVG(x)       ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #3 assigned IVG #x    */
-#define P4_IVG(x)       ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x    */
-#define P5_IVG(x)       ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x    */
-#define P6_IVG(x)       ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x    */
-#define P7_IVG(x)       ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x    */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #8 assigned IVG #x    */
-#define P9_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #9 assigned IVG #x    */
-#define P10_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #10 assigned IVG #x   */
-#define P11_IVG(x)                                   /* Reserved                         */
-#define P12_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x   */
-#define P13_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x   */
-#define P14_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x   */
-#define P15_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x   */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #16 assigned IVG #x   */
-#define P17_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #17 assigned IVG #x   */
-#define P18_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #18 assigned IVG #x   */
-#define P19_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #19 assigned IVG #x   */
-#define P20_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x   */
-#define P21_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x   */
-#define P22_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x   */
-#define P23_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x   */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #24 assigned IVG #x   */
-#define P25_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #25 assigned IVG #x   */
-#define P26_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #26 assigned IVG #x   */
-#define P27_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #27 assigned IVG #x   */
-#define P28_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x   */
-#define P29_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x   */
-#define P30_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x   */
-#define P31_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x   */
-
-/* SIC_IAR4 Macros */
-#define P32_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #32 assigned IVG #x   */
-#define P33_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #33 assigned IVG #x   */
-#define P34_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #34 assigned IVG #x   */
-#define P35_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #35 assigned IVG #x   */
-#define P36_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x   */
-#define P37_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x   */
-#define P38_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x   */
-#define P39_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x   */
-
-/* SIC_IAR5 Macros */
-#define P40_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #40 assigned IVG #x   */
-#define P41_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #41 assigned IVG #x   */
-#define P42_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #42 assigned IVG #x   */
-#define P43_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #43 assigned IVG #x   */
-#define P44_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x   */
-#define P45_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x   */
-#define P46_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x   */
-#define P47_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x   */
-
-/* SIC_IAR6 Macros */
-#define P48_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #48 assigned IVG #x   */
-#define P49_IVG(x)                                   /* Reserved                         */
-#define P50_IVG(x)                                   /* Reserved                         */
-#define P51_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #51 assigned IVG #x   */
-#define P52_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x   */
-#define P53_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x   */
-#define P54_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x   */
-#define P55_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x   */
-
-/* SIC_IAR7 Macros */
-#define P56_IVG(x)                                   /* Reserved                         */
-#define P57_IVG(x)                                   /* Reserved                         */
-#define P58_IVG(x)                                   /* Reserved                         */
-#define P59_IVG(x)                                   /* Reserved                         */
-#define P60_IVG(x)                                   /* Reserved                         */
-#define P61_IVG(x)                                   /* Reserved                         */
-#define P62_IVG(x)                                   /* Reserved                         */
-#define P63_IVG(x)                                   /* Reserved                         */
-
-
-/* SIC_IMASK0 Masks*/
-#define SIC_UNMASK0_ALL 0x00000000        /* Unmask all peripheral interrupts */
-#define SIC_MASK0_ALL   0xFFFFF3FF        /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK0(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK0(x) (1 << ((x)&0x1F))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK0(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASK1 Masks*/
-#define SIC_UNMASK1_ALL 0x00000000        /* Unmask all peripheral interrupts */
-#define SIC_MASK1_ALL   0xFFFFFF          /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK1(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK1(x) (1 << ((x)&0x1F))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK1(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-
-/* SIC_IWR0 Masks*/
-#define IWR0_DISABLE_ALL 0x00000000       /* Wakeup Disable all peripherals   */
-#define IWR0_ENABLE_ALL  0xFFFFF3FF       /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR0_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR0_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR0_ENABLE(x)   (1 << ((x)&0x1F))  /* Wakeup Enable Peripheral #x   */
-#define IWR0_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR1 Masks*/
-#define IWR1_DISABLE_ALL 0x00000000       /* Wakeup Disable all peripherals   */
-#define IWR1_ENABLE_ALL  0xFFFFFF         /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR1_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR1_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /* Wakeup Disable Peripheral #x*/
-#else
-#define IWR1_ENABLE(x)   (1 << ((x)&0x1F))  /* Wakeup Enable Peripheral #x   */
-#define IWR1_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-
-/* ************************************** WATCHDOG TIMER MASKS ****************************************************/
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define WDEV(x)	     (((x)<<1) & 0x0006u)	/* event generated on roll over 						*/
-#else
-#define WDEV(x) 		(((x)<<1) & 0x0006)	/* event generated on roll over 						*/
-#endif /* _MISRA_RULES */
-
-#define WDEV_RESET			0x0000	/* generate reset event on roll over					*/
-#define WDEV_NMI 				0x0002 	/* generate NMI event on roll over 						*/
-#define WDEV_GPI 				0x0004 	/* generate GP IRQ on roll over 						*/
-#define WDEV_NONE 			0x0006	/* no event on roll over 							*/
-#define WDEN 				0x0FF0 	/* enable watchdog 								*/
-#define WDDIS 				0x0AD0 	/* disable watchdog 								*/
-#define WDRO 				0x8000 	/* watchdog rolled over latch 						*/
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-#define ICTL 				WDEV
-#define ENABLE_RESET 			WDEV_RESET
-#define WDOG_RESET 			WDEV_RESET
-#define ENABLE_NMI 			WDEV_NMI
-#define WDOG_NMI 				WDEV_NMI
-#define ENABLE_GPI 			WDEV_GPI
-#define WDOG_GPI 				WDEV_GPI
-#define DISABLE_EVT 			WDEV_NONE
-#define WDOG_NONE 			WDEV_NONE
-
-#define TMR_EN 				WDEN
-#define TMR_DIS 				WDDIS
-#define TRO 				WDRO
-#define ICTL_P0 				0x01
-#define ICTL_P1 				0x02
-#define TRO_P 				0x0F
-
-
-/* **************************************  REAL TIME CLOCK MASKS  *************************************************/
-
-/* RTC_STAT and RTC_ALARM Masks*/
-#define RTC_SEC				0x0000003F	/* Real-Time Clock Seconds							*/
-#define RTC_MIN				0x00000FC0	/* Real-Time Clock Minutes							*/
-#define RTC_HR				0x0001F000	/* Real-Time Clock Hours							*/
-#define RTC_DAY				0xFFFE0000	/* Real-Time Clock Days								*/
-
-/* RTC_ALARM Macro z=day y=hr x=min w=sec	*/
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)		((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)		((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* RTC_ICTL and RTC_ISTAT Masks*/
-#define STOPWATCH				0x0001 	/* Stopwatch Interrupt Enable							*/
-#define ALARM				0x0002 	/* Alarm Interrupt Enable							*/
-#define SECOND				0x0004 	/* Seconds (1 Hz) Interrupt Enable						*/
-#define MINUTE				0x0008 	/* Minutes Interrupt Enable							*/
-#define HOUR				0x0010 	/* Hours Interrupt Enable							*/
-#define DAY					0x0020 	/* 24 Hours (Days) Interrupt Enable						*/
-#define DAY_ALARM				0x0040 	/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable		*/
-#define WRITE_PENDING			0x4000 	/* Write Pending Status								*/
-#define WRITE_COMPLETE			0x8000 	/* Write Complete Interrupt Enable						*/
-
-/* RTC_FAST / RTC_PREN Mask */
-#define PREN				0x0001 	/* Enable Prescaler, RTC Runs @1 Hz						*/
-
-
-/* ************************************ UART CONTROLLER MASKS *****************************************************/
-
-/* UARTx_LCR Masks*/
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select 								*/
-#else
-#define WLS(x)		  (((x)-5) & 0x03)	/* Word Length Select 								*/
-#endif /* _MISRA_RULES */
-
-#define STB					0x04		/* Stop Bits									*/
-#define PEN					0x08		/* Parity Enable									*/
-#define EPS					0x10		/* Even Parity Select								*/
-#define STP					0x20		/* Stick Parity									*/
-#define SB					0x40		/* Set Break									*/
-#define DLAB				0x80		/* Divisor Latch Access								*/
-
-/* UARTx_MCR Mask	*/
-#define LOOP_ENA				0x10		/* Loopback Mode Enable 							*/
-#define LOOP_ENA_P			0x04
-
-/* UARTx_LSR Masks */
-#define DR					0x01		/* Data Ready									*/
-#define OE					0x02		/* Overrun Error									*/
-#define PE					0x04		/* Parity Error									*/
-#define FE					0x08		/* Framing Error									*/
-#define BI					0x10		/* Break Interrupt								*/
-#define THRE				0x20		/* THR Empty									*/
-#define TEMT				0x40		/* TSR and UART_THR Empty							*/
-
-/* UARTx_IER Masks*/
-#define ERBFI				0x01		/* Enable Receive Buffer Full Interrupt					*/
-#define ETBEI				0x02		/* Enable Transmit Buffer Empty Interrupt					*/
-#define ELSI				0x04		/* Enable RX Status Interrupt							*/
-
-/* UARTx_IIR Masks*/
-#define NINT				0x01		/* Pending Interrupt								*/
-#define STATUS				0x06		/* Highest Priority Pending Interrupt					*/
-
-/* UARTx_GCTL Masks*/
-#define UCEN				0x01		/* Enable UARTx Clocks								*/
-#define IREN				0x02		/* Enable IrDA Mode								*/
-#define TPOLC				0x04		/* IrDA TX Polarity Change							*/
-#define RPOLC				0x08		/* IrDA RX Polarity Change							*/
-#define FPE					0x10		/* Force Parity Error On Transmit						*/
-#define FFE					0x20		/* Force Framing Error On Transmit						*/
-
-/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
-#define UARTDLL                 	0x00FF	/* Divisor Latch Low Byte 							*/
-#define UARTDLH                	0xFF00	/* Divisor Latch High Byte 							*/
-
-
-/********************************  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ***************************************/
-
-/* SPI_CTL Masks*/
-#define TIMOD				0x0003	/* Transfer Initiate Mode							*/
-#define RDBR_CORE				0x0000	/* RDBR Read Initiates, IRQ When RDBR Full				*/
-#define TDBR_CORE				0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty				*/
-#define RDBR_DMA				0x0002	/* DMA Read, DMA Until FIFO Empty						*/
-#define TDBR_DMA				0x0003	/* DMA Write, DMA Until FIFO Full						*/
-#define SZ					0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*)				*/
-#define GM					0x0008	/* Get More (When RDBR Full, Overwrite/Discard*)			*/
-#define PSSE				0x0010	/* Slave-Select Input Enable							*/
-#define EMISO				0x0020	/* Enable MISO As Output							*/
-#define SIZE				0x0100	/* Size of Words (16/8* Bits)							*/
-#define LSBF				0x0200	/* LSB First									*/
-#define CPHA				0x0400	/* Clock Phase									*/
-#define CPOL				0x0800	/* Clock Polarity									*/
-#define MSTR				0x1000	/* Master/Slave*									*/
-#define WOM					0x2000	/* Write Open Drain Master							*/
-#define SPE					0x4000	/* SPI Enable									*/
-
-/* SPI_FLG Masks*/
-#define FLS1				0x0002	/* Enables SPI_FLOUT1 as SPI Slave-Select Output			*/
-#define FLS2				0x0004	/* Enables SPI_FLOUT2 as SPI Slave-Select Output			*/
-#define FLS3				0x0008	/* Enables SPI_FLOUT3 as SPI Slave-Select Output			*/
-#define FLS4				0x0010	/* Enables SPI_FLOUT4 as SPI Slave-Select Output			*/
-#define FLS5				0x0020	/* Enables SPI_FLOUT5 as SPI Slave-Select Output			*/
-#define FLS6				0x0040	/* Enables SPI_FLOUT6 as SPI Slave-Select Output			*/
-#define FLS7				0x0080	/* Enables SPI_FLOUT7 as SPI Slave-Select Output			*/
-#define FLG1				0xFDFF	/* Activates SPI_FLOUT1 							*/
-#define FLG2				0xFBFF	/* Activates SPI_FLOUT2								*/
-#define FLG3				0xF7FF	/* Activates SPI_FLOUT3								*/
-#define FLG4				0xEFFF	/* Activates SPI_FLOUT4								*/
-#define FLG5				0xDFFF	/* Activates SPI_FLOUT5								*/
-#define FLG6				0xBFFF	/* Activates SPI_FLOUT6								*/
-#define FLG7				0x7FFF	/* Activates SPI_FLOUT7								*/
-
-/* SPI_STAT Masks*/
-#define SPIF				0x0001	/* SPI Finished (Single-Word Transfer Complete)				*/
-#define MODF				0x0002	/* Mode Fault Error (Another Device Tried To Become Master)		*/
-#define TXE					0x0004	/* Transmission Error (Data Sent With No New Data In TDBR)		*/
-#define TXS					0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*)				*/
-#define RBSY				0x0010	/* Receive Error (Data Received With RDBR Full)				*/
-#define RXS					0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*)				*/
-#define TXCOL				0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/
-
-
-/***********************************  GENERAL PURPOSE TIMER MASKS  ************************************************/
-/* TIMER_ENABLE Masks*/
-#define TIMEN0				0x0001	/* Enable Timer 0									*/
-#define TIMEN1				0x0002	/* Enable Timer 1									*/
-#define TIMEN2				0x0004	/* Enable Timer 2									*/
-#define TIMEN3				0x0008	/* Enable Timer 3									*/
-#define TIMEN4				0x0010	/* Enable Timer 4									*/
-#define TIMEN5				0x0020	/* Enable Timer 5									*/
-#define TIMEN6				0x0040	/* Enable Timer 6									*/
-#define TIMEN7				0x0080	/* Enable Timer 7									*/
-
-/* TIMER_DISABLE Masks*/
-#define TIMDIS0				TIMEN0	/* Disable Timer 0								*/
-#define TIMDIS1				TIMEN1	/* Disable Timer 1								*/
-#define TIMDIS2				TIMEN2	/* Disable Timer 2								*/
-#define TIMDIS3				TIMEN3	/* Disable Timer 3								*/
-#define TIMDIS4				TIMEN4	/* Disable Timer 4								*/
-#define TIMDIS5				TIMEN5	/* Disable Timer 5								*/
-#define TIMDIS6				TIMEN6	/* Disable Timer 6								*/
-#define TIMDIS7				TIMEN7	/* Disable Timer 7								*/
-
-/* TIMER_STATUS Masks*/
-#define TIMIL0				0x00000001	/* Timer 0 Interrupt								*/
-#define TIMIL1				0x00000002	/* Timer 1 Interrupt								*/
-#define TIMIL2				0x00000004	/* Timer 2 Interrupt								*/
-#define TIMIL3				0x00000008	/* Timer 3 Interrupt								*/
-#define TOVF_ERR0				0x00000010	/* Timer 0 Counter Overflow							*/
-#define TOVF_ERR1				0x00000020	/* Timer 1 Counter Overflow							*/
-#define TOVF_ERR2				0x00000040	/* Timer 2 Counter Overflow							*/
-#define TOVF_ERR3				0x00000080	/* Timer 3 Counter Overflow							*/
-#define TRUN0				0x00001000	/* Timer 0 Slave Enable Status						*/
-#define TRUN1				0x00002000	/* Timer 1 Slave Enable Status						*/
-#define TRUN2				0x00004000	/* Timer 2 Slave Enable Status						*/
-#define TRUN3				0x00008000	/* Timer 3 Slave Enable Status						*/
-#define TIMIL4				0x00010000	/* Timer 4 Interrupt								*/
-#define TIMIL5				0x00020000	/* Timer 5 Interrupt								*/
-#define TIMIL6				0x00040000	/* Timer 6 Interrupt								*/
-#define TIMIL7				0x00080000	/* Timer 7 Interrupt								*/
-#define TOVF_ERR4				0x00100000	/* Timer 4 Counter Overflow							*/
-#define TOVF_ERR5				0x00200000	/* Timer 5 Counter Overflow							*/
-#define TOVF_ERR6				0x00400000	/* Timer 6 Counter Overflow							*/
-#define TOVF_ERR7				0x00800000	/* Timer 7 Counter Overflow							*/
-#define TRUN4				0x10000000	/* Timer 4 Slave Enable Status						*/
-#define TRUN5				0x20000000	/* Timer 5 Slave Enable Status						*/
-#define TRUN6				0x40000000	/* Timer 6 Slave Enable Status						*/
-#define TRUN7				0x80000000	/* Timer 7 Slave Enable Status						*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 			TOVF_ERR0
-#define TOVL_ERR1				TOVF_ERR1
-#define TOVL_ERR2 			TOVF_ERR2
-#define TOVL_ERR3 			TOVF_ERR3
-#define TOVL_ERR4 			TOVF_ERR4
-#define TOVL_ERR5 			TOVF_ERR5
-#define TOVL_ERR6 			TOVF_ERR6
-#define TOVL_ERR7 			TOVF_ERR7
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT				0x0001	/* Pulse-Width Modulation Output Mode					*/
-#define WDTH_CAP				0x0002	/* Width Capture Input Mode							*/
-#define EXT_CLK				0x0003	/* External Clock Mode								*/
-#define PULSE_HI				0x0004	/* Action Pulse (Positive/Negative*)					*/
-#define PERIOD_CNT			0x0008	/* Period Count									*/
-#define IRQ_ENA				0x0010	/* Interrupt Request Enable							*/
-#define TIN_SEL				0x0020	/* Timer Input Select								*/
-#define OUT_DIS				0x0040	/* Output Pad Disable								*/
-#define CLK_SEL				0x0080	/* Timer Clock Select								*/
-#define TOGGLE_HI				0x0100	/* PWM_OUT PULSE_HI Toggle Mode						*/
-#define EMU_RUN				0x0200	/* Emulation Behavior Select							*/
-#define ERR_TYP				0xC000	/* Error Type									*/
-
-
-/* *************************************   GPIO PORTS F, G, H MASKS  **********************************************/
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-/* Port F Masks */
-#define PF0					0x0001
-#define PF1					0x0002
-#define PF2					0x0004
-#define PF3					0x0008
-#define PF4					0x0010
-#define PF5					0x0020
-#define PF6					0x0040
-#define PF7					0x0080
-#define PF8					0x0100
-#define PF9					0x0200
-#define PF10				0x0400
-#define PF11				0x0800
-#define PF12				0x1000
-#define PF13				0x2000
-#define PF14				0x4000
-#define PF15				0x8000
-
-/* Port G Masks */
-#define PG0					0x0001
-#define PG1					0x0002
-#define PG2					0x0004
-#define PG3					0x0008
-#define PG4					0x0010
-#define PG5					0x0020
-#define PG6					0x0040
-#define PG7					0x0080
-#define PG8					0x0100
-#define PG9					0x0200
-#define PG10				0x0400
-#define PG11				0x0800
-#define PG12				0x1000
-#define PG13				0x2000
-#define PG14				0x4000
-#define PG15				0x8000
-
-/* Port H Masks */
-#define PH0					0x0001
-#define PH1					0x0002
-#define PH2					0x0004
-#define PH3					0x0008
-#define PH4					0x0010
-#define PH5					0x0020
-#define PH6					0x0040
-#define PH7					0x0080
-#define PH8					0x0100
-
-/* **************************************  SERIAL PORT MASKS  *****************************************************/
-/* SPORTx_TCR1 Masks */
-#define TSPEN				0x0001	/* Transmit Enable								*/
-#define ITCLK				0x0002	/* Internal Transmit Clock Select						*/
-#define DTYPE_NORM			0x0004	/* Data Format Normal								*/
-#define DTYPE_ULAW			0x0008	/* Compand Using u-Law								*/
-#define DTYPE_ALAW			0x000C	/* Compand Using A-Law								*/
-#define TLSBIT				0x0010	/* Transmit Bit Order								*/
-#define ITFS				0x0200	/* Internal Transmit Frame Sync Select					*/
-#define TFSR				0x0400	/* Transmit Frame Sync Required Select					*/
-#define DITFS				0x0800	/* Data-Independent Transmit Frame Sync Select				*/
-#define LTFS				0x1000	/* Low Transmit Frame Sync Select						*/
-#define LATFS				0x2000	/* Late Transmit Frame Sync Select						*/
-#define TCKFE				0x4000	/* Clock Falling Edge Select							*/
-
-/* SPORTx_TCR2 Masks and Macro */
-#ifdef _MISRA_RULES
-#define SLEN(x)				((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)						*/
-#else
-#define SLEN(x)				((x)&0x1F)	/* SPORT TX Word Length (2 - 31)						*/
-#endif /* _MISRA_RULES */
-
-#define TXSE				0x0100	/* TX Secondary Enable								*/
-#define TSFSE				0x0200	/* Transmit Stereo Frame Sync Enable					*/
-#define TRFST				0x0400	/* Left/Right Order (1 = Right Channel 1st)				*/
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN				0x0001	/* Receive Enable 								*/
-#define IRCLK				0x0002	/* Internal Receive Clock Select 						*/
-#define DTYPE_NORM			0x0004	/* Data Format Normal								*/
-#define DTYPE_ULAW			0x0008	/* Compand Using u-Law								*/
-#define DTYPE_ALAW			0x000C	/* Compand Using A-Law								*/
-#define RLSBIT				0x0010	/* Receive Bit Order								*/
-#define IRFS				0x0200	/* Internal Receive Frame Sync Select 					*/
-#define RFSR				0x0400	/* Receive Frame Sync Required Select 					*/
-#define LRFS				0x1000	/* Low Receive Frame Sync Select 						*/
-#define LARFS				0x2000	/* Late Receive Frame Sync Select 						*/
-#define RCKFE				0x4000	/* Clock Falling Edge Select 							*/
-
-/* SPORTx_RCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)				((x)&0x1Fu)	/* SPORT RX Word Length (2 - 31)						*/
-#else
-#define SLEN(x)				((x)&0x1F)	/* SPORT RX Word Length (2 - 31)						*/
-#endif /* _MISRA_RULES */
-
-#define RXSE				0x0100	/* RX Secondary Enable								*/
-#define RSFSE				0x0200	/* RX Stereo Frame Sync Enable						*/
-#define RRFST				0x0400	/* Right-First Data Order 							*/
-
-/* SPORTx_STAT Masks */
-#define RXNE				0x0001	/* Receive FIFO Not Empty Status						*/
-#define RUVF				0x0002	/* Sticky Receive Underflow Status						*/
-#define ROVF				0x0004	/* Sticky Receive Overflow Status						*/
-#define TXF					0x0008	/* Transmit FIFO Full Status							*/
-#define TUVF				0x0010	/* Sticky Transmit Underflow Status						*/
-#define TOVF				0x0020	/* Sticky Transmit Overflow Status						*/
-#define TXHRE				0x0040	/* Transmit Hold Register Empty						*/
-
-/* SPORTx_MCMC1 Macros */
-#ifdef _MISRA_RULES
-#define WOFF(x)		((x) & 0x3FFu) 		/* Multichannel Window Offset Field						*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/
-#define WSIZE(x)		(((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1				*/
-#else
-#define WOFF(x)		((x) & 0x3FF) 		/* Multichannel Window Offset Field						*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits								*/
-#define WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1					*/
-#endif /* _MISRA_RULES */
-
-/* SPORTx_MCMC2 Masks */
-#define REC_BYPASS			0x0000	/* Bypass Mode (No Clock Recovery)						*/
-#define REC_2FROM4			0x0002	/* Recover 2 MHz Clock from 4 MHz Clock					*/
-#define REC_8FROM16			0x0003	/* Recover 8 MHz Clock from 16 MHz Clock					*/
-#define MCDTXPE				0x0004 	/* Multichannel DMA Transmit Packing					*/
-#define MCDRXPE				0x0008 	/* Multichannel DMA Receive Packing						*/
-#define MCMEN				0x0010 	/* Multichannel Frame Mode Enable						*/
-#define FSDR				0x0080 	/* Multichannel Frame Sync to Data Relationship				*/
-#define MFD_0				0x0000	/* Multichannel Frame Delay = 0						*/
-#define MFD_1				0x1000	/* Multichannel Frame Delay = 1						*/
-#define MFD_2				0x2000	/* Multichannel Frame Delay = 2						*/
-#define MFD_3				0x3000	/* Multichannel Frame Delay = 3						*/
-#define MFD_4				0x4000	/* Multichannel Frame Delay = 4						*/
-#define MFD_5				0x5000	/* Multichannel Frame Delay = 5						*/
-#define MFD_6				0x6000	/* Multichannel Frame Delay = 6						*/
-#define MFD_7				0x7000	/* Multichannel Frame Delay = 7						*/
-#define MFD_8				0x8000	/* Multichannel Frame Delay = 8						*/
-#define MFD_9				0x9000	/* Multichannel Frame Delay = 9						*/
-#define MFD_10				0xA000	/* Multichannel Frame Delay = 10						*/
-#define MFD_11				0xB000	/* Multichannel Frame Delay = 11						*/
-#define MFD_12				0xC000	/* Multichannel Frame Delay = 12						*/
-#define MFD_13				0xD000	/* Multichannel Frame Delay = 13						*/
-#define MFD_14				0xE000	/* Multichannel Frame Delay = 14						*/
-#define MFD_15				0xF000	/* Multichannel Frame Delay = 15						*/
-
-
-/***********************************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ***************************************/
-
-/* EBIU_AMGCTL Masks */
-#define AMCKEN				0x0001	/* Enable CLKOUT									*/
-#define AMBEN           		0x000e      /* Async bank enable                          		      	*/
-#define AMBEN_NONE			0x0000	/* All Banks Disabled								*/
-#define AMBEN_B0				0x0002	/* Enable Async Memory Bank 0 only						*/
-#define AMBEN_B0_B1			0x0004	/* Enable Async Memory Banks 0 & 1 only					*/
-#define AMBEN_B0_B1_B2			0x0006	/* Enable Async Memory Banks 0, 1, and 2					*/
-#define AMBEN_ALL				0x0008	/* Enable Async Memory Banks (all) 0, 1, 2, and 3			*/
-#define CDPRIO 				0x0100	/* DMA has priority over core for for external accesses 		*/
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN				0x00000001  /* Bank 0 (B0) RDY Enable							*/
-#define B0RDYPOL				0x00000002  /* B0 RDY Active High								*/
-#define B0TT_1				0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle				*/
-#define B0TT_2				0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles			*/
-#define B0TT_3				0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles			*/
-#define B0TT_4				0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles			*/
-#define B0ST_1				0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle				*/
-#define B0ST_2				0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles				*/
-#define B0ST_3				0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles				*/
-#define B0ST_4				0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles				*/
-#define B0HT_1				0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle				*/
-#define B0HT_2				0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles			*/
-#define B0HT_3				0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles			*/
-#define B0HT_0				0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles			*/
-#define B0RAT_1				0x00000100  /* B0 Read Access Time = 1 cycle						*/
-#define B0RAT_2				0x00000200  /* B0 Read Access Time = 2 cycles						*/
-#define B0RAT_3				0x00000300  /* B0 Read Access Time = 3 cycles						*/
-#define B0RAT_4				0x00000400  /* B0 Read Access Time = 4 cycles						*/
-#define B0RAT_5				0x00000500  /* B0 Read Access Time = 5 cycles						*/
-#define B0RAT_6				0x00000600  /* B0 Read Access Time = 6 cycles						*/
-#define B0RAT_7				0x00000700  /* B0 Read Access Time = 7 cycles						*/
-#define B0RAT_8				0x00000800  /* B0 Read Access Time = 8 cycles						*/
-#define B0RAT_9				0x00000900  /* B0 Read Access Time = 9 cycles						*/
-#define B0RAT_10				0x00000A00  /* B0 Read Access Time = 10 cycles						*/
-#define B0RAT_11				0x00000B00  /* B0 Read Access Time = 11 cycles						*/
-#define B0RAT_12				0x00000C00  /* B0 Read Access Time = 12 cycles						*/
-#define B0RAT_13				0x00000D00  /* B0 Read Access Time = 13 cycles						*/
-#define B0RAT_14				0x00000E00  /* B0 Read Access Time = 14 cycles						*/
-#define B0RAT_15				0x00000F00  /* B0 Read Access Time = 15 cycles						*/
-#define B0WAT_1				0x00001000  /* B0 Write Access Time = 1 cycle						*/
-#define B0WAT_2				0x00002000  /* B0 Write Access Time = 2 cycles						*/
-#define B0WAT_3				0x00003000  /* B0 Write Access Time = 3 cycles						*/
-#define B0WAT_4				0x00004000  /* B0 Write Access Time = 4 cycles						*/
-#define B0WAT_5				0x00005000  /* B0 Write Access Time = 5 cycles						*/
-#define B0WAT_6				0x00006000  /* B0 Write Access Time = 6 cycles						*/
-#define B0WAT_7				0x00007000  /* B0 Write Access Time = 7 cycles						*/
-#define B0WAT_8				0x00008000  /* B0 Write Access Time = 8 cycles						*/
-#define B0WAT_9				0x00009000  /* B0 Write Access Time = 9 cycles						*/
-#define B0WAT_10				0x0000A000  /* B0 Write Access Time = 10 cycles						*/
-#define B0WAT_11				0x0000B000  /* B0 Write Access Time = 11 cycles						*/
-#define B0WAT_12				0x0000C000  /* B0 Write Access Time = 12 cycles						*/
-#define B0WAT_13				0x0000D000  /* B0 Write Access Time = 13 cycles						*/
-#define B0WAT_14				0x0000E000  /* B0 Write Access Time = 14 cycles						*/
-#define B0WAT_15				0x0000F000  /* B0 Write Access Time = 15 cycles						*/
-
-#define B1RDYEN				0x00010000  /* Bank 1 (B1) RDY Enable  		                     		*/
-#define B1RDYPOL				0x00020000  /* B1 RDY Active High               	            		*/
-#define B1TT_1				0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle 			*/
-#define B1TT_2				0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles			*/
-#define B1TT_3				0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles			*/
-#define B1TT_4				0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles			*/
-#define B1ST_1				0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle  			*/
-#define B1ST_2				0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles 			*/
-#define B1ST_3				0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles 			*/
-#define B1ST_4				0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles 			*/
-#define B1HT_1				0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle 			*/
-#define B1HT_2				0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles			*/
-#define B1HT_3				0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles			*/
-#define B1HT_0				0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles			*/
-#define B1RAT_1				0x01000000  /* B1 Read Access Time = 1 cycle						*/
-#define B1RAT_2				0x02000000  /* B1 Read Access Time = 2 cycles						*/
-#define B1RAT_3				0x03000000  /* B1 Read Access Time = 3 cycles						*/
-#define B1RAT_4				0x04000000  /* B1 Read Access Time = 4 cycles						*/
-#define B1RAT_5				0x05000000  /* B1 Read Access Time = 5 cycles						*/
-#define B1RAT_6				0x06000000  /* B1 Read Access Time = 6 cycles						*/
-#define B1RAT_7				0x07000000  /* B1 Read Access Time = 7 cycles						*/
-#define B1RAT_8				0x08000000  /* B1 Read Access Time = 8 cycles						*/
-#define B1RAT_9				0x09000000  /* B1 Read Access Time = 9 cycles						*/
-#define B1RAT_10				0x0A000000  /* B1 Read Access Time = 10 cycles						*/
-#define B1RAT_11				0x0B000000  /* B1 Read Access Time = 11 cycles						*/
-#define B1RAT_12				0x0C000000  /* B1 Read Access Time = 12 cycles						*/
-#define B1RAT_13				0x0D000000  /* B1 Read Access Time = 13 cycles						*/
-#define B1RAT_14				0x0E000000  /* B1 Read Access Time = 14 cycles						*/
-#define B1RAT_15				0x0F000000  /* B1 Read Access Time = 15 cycles						*/
-#define B1WAT_1				0x10000000  /* B1 Write Access Time = 1 cycle						*/
-#define B1WAT_2				0x20000000  /* B1 Write Access Time = 2 cycles						*/
-#define B1WAT_3				0x30000000  /* B1 Write Access Time = 3 cycles						*/
-#define B1WAT_4				0x40000000  /* B1 Write Access Time = 4 cycles						*/
-#define B1WAT_5				0x50000000  /* B1 Write Access Time = 5 cycles						*/
-#define B1WAT_6				0x60000000  /* B1 Write Access Time = 6 cycles						*/
-#define B1WAT_7				0x70000000  /* B1 Write Access Time = 7 cycles						*/
-#define B1WAT_8				0x80000000  /* B1 Write Access Time = 8 cycles						*/
-#define B1WAT_9				0x90000000  /* B1 Write Access Time = 9 cycles						*/
-#define B1WAT_10				0xA0000000  /* B1 Write Access Time = 10 cycles						*/
-#define B1WAT_11				0xB0000000  /* B1 Write Access Time = 11 cycles						*/
-#define B1WAT_12				0xC0000000  /* B1 Write Access Time = 12 cycles						*/
-#define B1WAT_13				0xD0000000  /* B1 Write Access Time = 13 cycles						*/
-#define B1WAT_14				0xE0000000  /* B1 Write Access Time = 14 cycles						*/
-#define B1WAT_15				0xF0000000  /* B1 Write Access Time = 15 cycles						*/
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN				0x00000001  /* Bank 2 (B2) RDY Enable							*/
-#define B2RDYPOL				0x00000002  /* B2 RDY Active High								*/
-#define B2TT_1				0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle				*/
-#define B2TT_2				0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles			*/
-#define B2TT_3				0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles			*/
-#define B2TT_4				0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles			*/
-#define B2ST_1				0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle				*/
-#define B2ST_2				0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles				*/
-#define B2ST_3				0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles				*/
-#define B2ST_4				0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles				*/
-#define B2HT_1				0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle				*/
-#define B2HT_2				0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles			*/
-#define B2HT_3				0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles			*/
-#define B2HT_0				0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles			*/
-#define B2RAT_1				0x00000100  /* B2 Read Access Time = 1 cycle						*/
-#define B2RAT_2				0x00000200  /* B2 Read Access Time = 2 cycles						*/
-#define B2RAT_3				0x00000300  /* B2 Read Access Time = 3 cycles						*/
-#define B2RAT_4				0x00000400  /* B2 Read Access Time = 4 cycles						*/
-#define B2RAT_5				0x00000500  /* B2 Read Access Time = 5 cycles						*/
-#define B2RAT_6				0x00000600  /* B2 Read Access Time = 6 cycles						*/
-#define B2RAT_7				0x00000700  /* B2 Read Access Time = 7 cycles						*/
-#define B2RAT_8				0x00000800  /* B2 Read Access Time = 8 cycles						*/
-#define B2RAT_9				0x00000900  /* B2 Read Access Time = 9 cycles						*/
-#define B2RAT_10				0x00000A00  /* B2 Read Access Time = 10 cycles						*/
-#define B2RAT_11				0x00000B00  /* B2 Read Access Time = 11 cycles						*/
-#define B2RAT_12				0x00000C00  /* B2 Read Access Time = 12 cycles						*/
-#define B2RAT_13				0x00000D00  /* B2 Read Access Time = 13 cycles						*/
-#define B2RAT_14				0x00000E00  /* B2 Read Access Time = 14 cycles						*/
-#define B2RAT_15				0x00000F00  /* B2 Read Access Time = 15 cycles						*/
-#define B2WAT_1				0x00001000  /* B2 Write Access Time = 1 cycle						*/
-#define B2WAT_2				0x00002000  /* B2 Write Access Time = 2 cycles						*/
-#define B2WAT_3				0x00003000  /* B2 Write Access Time = 3 cycles						*/
-#define B2WAT_4				0x00004000  /* B2 Write Access Time = 4 cycles						*/
-#define B2WAT_5				0x00005000  /* B2 Write Access Time = 5 cycles						*/
-#define B2WAT_6				0x00006000  /* B2 Write Access Time = 6 cycles						*/
-#define B2WAT_7				0x00007000  /* B2 Write Access Time = 7 cycles						*/
-#define B2WAT_8				0x00008000  /* B2 Write Access Time = 8 cycles						*/
-#define B2WAT_9				0x00009000  /* B2 Write Access Time = 9 cycles						*/
-#define B2WAT_10				0x0000A000  /* B2 Write Access Time = 10 cycles						*/
-#define B2WAT_11				0x0000B000  /* B2 Write Access Time = 11 cycles						*/
-#define B2WAT_12				0x0000C000  /* B2 Write Access Time = 12 cycles						*/
-#define B2WAT_13				0x0000D000  /* B2 Write Access Time = 13 cycles						*/
-#define B2WAT_14				0x0000E000  /* B2 Write Access Time = 14 cycles						*/
-#define B2WAT_15				0x0000F000  /* B2 Write Access Time = 15 cycles						*/
-
-#define B3RDYEN				0x00010000  /* Bank 3 (B3) RDY Enable							*/
-#define B3RDYPOL				0x00020000  /* B3 RDY Active High								*/
-#define B3TT_1				0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle				*/
-#define B3TT_2				0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles			*/
-#define B3TT_3				0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles			*/
-#define B3TT_4				0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles			*/
-#define B3ST_1				0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle				*/
-#define B3ST_2				0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles				*/
-#define B3ST_3				0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles				*/
-#define B3ST_4				0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles				*/
-#define B3HT_1				0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle				*/
-#define B3HT_2				0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles			*/
-#define B3HT_3				0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles			*/
-#define B3HT_0				0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles			*/
-#define B3RAT_1				0x01000000  /* B3 Read Access Time = 1 cycle						*/
-#define B3RAT_2				0x02000000  /* B3 Read Access Time = 2 cycles						*/
-#define B3RAT_3				0x03000000  /* B3 Read Access Time = 3 cycles						*/
-#define B3RAT_4				0x04000000  /* B3 Read Access Time = 4 cycles						*/
-#define B3RAT_5				0x05000000  /* B3 Read Access Time = 5 cycles						*/
-#define B3RAT_6				0x06000000  /* B3 Read Access Time = 6 cycles						*/
-#define B3RAT_7				0x07000000  /* B3 Read Access Time = 7 cycles						*/
-#define B3RAT_8				0x08000000  /* B3 Read Access Time = 8 cycles						*/
-#define B3RAT_9				0x09000000  /* B3 Read Access Time = 9 cycles						*/
-#define B3RAT_10				0x0A000000  /* B3 Read Access Time = 10 cycles						*/
-#define B3RAT_11				0x0B000000  /* B3 Read Access Time = 11 cycles						*/
-#define B3RAT_12				0x0C000000  /* B3 Read Access Time = 12 cycles						*/
-#define B3RAT_13				0x0D000000  /* B3 Read Access Time = 13 cycles						*/
-#define B3RAT_14				0x0E000000  /* B3 Read Access Time = 14 cycles						*/
-#define B3RAT_15				0x0F000000  /* B3 Read Access Time = 15 cycles						*/
-#define B3WAT_1				0x10000000  /* B3 Write Access Time = 1 cycle						*/
-#define B3WAT_2				0x20000000  /* B3 Write Access Time = 2 cycles						*/
-#define B3WAT_3				0x30000000  /* B3 Write Access Time = 3 cycles						*/
-#define B3WAT_4				0x40000000  /* B3 Write Access Time = 4 cycles						*/
-#define B3WAT_5				0x50000000  /* B3 Write Access Time = 5 cycles						*/
-#define B3WAT_6				0x60000000  /* B3 Write Access Time = 6 cycles						*/
-#define B3WAT_7				0x70000000  /* B3 Write Access Time = 7 cycles						*/
-#define B3WAT_8				0x80000000  /* B3 Write Access Time = 8 cycles						*/
-#define B3WAT_9				0x90000000  /* B3 Write Access Time = 9 cycles						*/
-#define B3WAT_10				0xA0000000  /* B3 Write Access Time = 10 cycles						*/
-#define B3WAT_11				0xB0000000  /* B3 Write Access Time = 11 cycles						*/
-#define B3WAT_12				0xC0000000  /* B3 Write Access Time = 12 cycles						*/
-#define B3WAT_13				0xD0000000  /* B3 Write Access Time = 13 cycles						*/
-#define B3WAT_14				0xE0000000  /* B3 Write Access Time = 14 cycles						*/
-#define B3WAT_15				0xF0000000  /* B3 Write Access Time = 15 cycles						*/
-
-
-/*****************************************  SDRAM CONTROLLER MASKS  ***********************************************/
-
-/* EBIU_SDGCTL Masks */
-#define CL 					0x0000000C	/* SDRAM CAS latency 								*/
-#define PASR 				0x00000030	/* SDRAM partial array self-refresh 					*/
-#define TRAS 				0x000003C0	/* SDRAM tRAS in SCLK cycles 							*/
-#define TRP 				0x00003800	/* SDRAM tRP in SCLK cycles 							*/
-#define TRCD 				0x00030000	/* SDRAM tRCD in SCLK cycles 							*/
-#define TWR 				0x00180000	/* SDRAM tWR in SCLK cycles 							*/
-
-#define SCTLE				0x00000001	/* Enable SDRAM Signals								*/
-#define CL_2				0x00000008	/* SDRAM CAS Latency = 2 cycles						*/
-#define CL_3				0x0000000C	/* SDRAM CAS Latency = 3 cycles						*/
-#define PASR_ALL				0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
-#define PASR_B0_B1			0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh			*/
-#define PASR_B0				0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
-#define TRAS_1				0x00000040	/* SDRAM tRAS = 1 cycle								*/
-#define TRAS_2				0x00000080	/* SDRAM tRAS = 2 cycles							*/
-#define TRAS_3				0x000000C0	/* SDRAM tRAS = 3 cycles							*/
-#define TRAS_4				0x00000100	/* SDRAM tRAS = 4 cycles							*/
-#define TRAS_5				0x00000140	/* SDRAM tRAS = 5 cycles							*/
-#define TRAS_6				0x00000180	/* SDRAM tRAS = 6 cycles							*/
-#define TRAS_7				0x000001C0	/* SDRAM tRAS = 7 cycles							*/
-#define TRAS_8				0x00000200	/* SDRAM tRAS = 8 cycles							*/
-#define TRAS_9				0x00000240	/* SDRAM tRAS = 9 cycles							*/
-#define TRAS_10				0x00000280	/* SDRAM tRAS = 10 cycles							*/
-#define TRAS_11				0x000002C0	/* SDRAM tRAS = 11 cycles							*/
-#define TRAS_12				0x00000300	/* SDRAM tRAS = 12 cycles							*/
-#define TRAS_13				0x00000340	/* SDRAM tRAS = 13 cycles							*/
-#define TRAS_14				0x00000380	/* SDRAM tRAS = 14 cycles							*/
-#define TRAS_15				0x000003C0	/* SDRAM tRAS = 15 cycles							*/
-#define TRP_1				0x00000800	/* SDRAM tRP = 1 cycle								*/
-#define TRP_2				0x00001000	/* SDRAM tRP = 2 cycles								*/
-#define TRP_3				0x00001800	/* SDRAM tRP = 3 cycles								*/
-#define TRP_4				0x00002000	/* SDRAM tRP = 4 cycles								*/
-#define TRP_5				0x00002800	/* SDRAM tRP = 5 cycles								*/
-#define TRP_6				0x00003000	/* SDRAM tRP = 6 cycles								*/
-#define TRP_7				0x00003800	/* SDRAM tRP = 7 cycles								*/
-#define TRCD_1				0x00008000	/* SDRAM tRCD = 1 cycle								*/
-#define TRCD_2				0x00010000	/* SDRAM tRCD = 2 cycles							*/
-#define TRCD_3				0x00018000	/* SDRAM tRCD = 3 cycles							*/
-#define TRCD_4				0x00020000	/* SDRAM tRCD = 4 cycles							*/
-#define TRCD_5				0x00028000	/* SDRAM tRCD = 5 cycles							*/
-#define TRCD_6				0x00030000	/* SDRAM tRCD = 6 cycles							*/
-#define TRCD_7				0x00038000	/* SDRAM tRCD = 7 cycles							*/
-#define TWR_1				0x00080000	/* SDRAM tWR = 1 cycle								*/
-#define TWR_2				0x00100000	/* SDRAM tWR = 2 cycles								*/
-#define TWR_3				0x00180000	/* SDRAM tWR = 3 cycles								*/
-#define PUPSD				0x00200000	/* Power-Up Start Delay (15 SCLK Cycles Delay)				*/
-#define PSM					0x00400000	/* Power-Up Sequence (Mode Register Before/After* Refresh)		*/
-#define PSS					0x00800000	/* Enable Power-Up Sequence on Next SDRAM Access			*/
-#define SRFS				0x01000000	/* Enable SDRAM Self-Refresh Mode						*/
-#define EBUFE				0x02000000	/* Enable External Buffering Timing						*/
-#define FBBRW				0x04000000	/* Enable Fast Back-To-Back Read To Write					*/
-#define EMREN				0x10000000	/* Extended Mode Register Enable						*/
-#define TCSR				0x20000000	/* Temp-Compensated Self-Refresh Value (85/45* Deg C)			*/
-#define CDDBG				0x40000000	/* Tristate SDRAM Controls During Bus Grant				*/
-
-/* EBIU_SDBCTL Masks */
-#define EBE					0x0001	/* Enable SDRAM External Bank							*/
-#define EBSZ_16				0x0000	/* SDRAM External Bank Size = 16MB						*/
-#define EBSZ_32				0x0002	/* SDRAM External Bank Size = 32MB						*/
-#define EBSZ_64				0x0004	/* SDRAM External Bank Size = 64MB						*/
-#define EBSZ_128				0x0006	/* SDRAM External Bank Size = 128MB						*/
-#define EBCAW_8				0x0000	/* SDRAM External Bank Column Address Width = 8 Bits			*/
-#define EBCAW_9				0x0010	/* SDRAM External Bank Column Address Width = 9 Bits			*/
-#define EBCAW_10				0x0020	/* SDRAM External Bank Column Address Width = 10 Bits			*/
-#define EBCAW_11				0x0030	/* SDRAM External Bank Column Address Width = 11 Bits			*/
-
-#define EBSZ				0x0006	/* SDRAM external bank size 							*/
-#define EBCAW				0x0030	/* SDRAM external bank column address width 				*/
-
-/* EBIU_SDSTAT Masks */
-#define SDCI				0x0001	/* SDRAM Controller Idle 							*/
-#define SDSRA				0x0002	/* SDRAM Self-Refresh Active							*/
-#define SDPUA				0x0004	/* SDRAM Power-Up Active 							*/
-#define SDRS				0x0008	/* SDRAM Will Power-Up On Next Access					*/
-#define SDEASE				0x0010	/* SDRAM EAB Sticky Error Status						*/
-#define BGSTAT				0x0020	/* Bus Grant Status								*/
-
-
-/****************************************  DMA CONTROLLER MASKS  **************************************************/
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN				0x0001	/* DMA Channel Enable								*/
-#define WNR					0x0002	/* Channel Direction (W/R*)							*/
-#define WDSIZE_8				0x0000	/* Transfer Word Size = 8							*/
-#define WDSIZE_16				0x0004	/* Transfer Word Size = 16							*/
-#define WDSIZE_32				0x0008	/* Transfer Word Size = 32							*/
-#define DMA2D				0x0010	/* DMA Mode (2D/1D*)								*/
-#define SYNC				0x0020	/* DMA Buffer Clear								*/
-#define DI_SEL				0x0040	/* Data Interrupt Timing Select						*/
-#define DI_EN				0x0080	/* Data Interrupt Enable							*/
-#define NDSIZE_0				0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)				*/
-#define NDSIZE_1				0x0100	/* Next Descriptor Size = 1							*/
-#define NDSIZE_2				0x0200	/* Next Descriptor Size = 2							*/
-#define NDSIZE_3				0x0300	/* Next Descriptor Size = 3							*/
-#define NDSIZE_4				0x0400	/* Next Descriptor Size = 4							*/
-#define NDSIZE_5				0x0500	/* Next Descriptor Size = 5							*/
-#define NDSIZE_6				0x0600	/* Next Descriptor Size = 6							*/
-#define NDSIZE_7				0x0700	/* Next Descriptor Size = 7							*/
-#define NDSIZE_8				0x0800	/* Next Descriptor Size = 8							*/
-#define NDSIZE_9				0x0900	/* Next Descriptor Size = 9							*/
-#define FLOW_STOP				0x0000	/* Stop Mode									*/
-#define FLOW_AUTO				0x1000	/* Autobuffer Mode								*/
-#define FLOW_ARRAY			0x4000	/* Descriptor Array Mode							*/
-#define FLOW_SMALL			0x6000	/* Small Model Descriptor List Mode						*/
-#define FLOW_LARGE			0x7000	/* Large Model Descriptor List Mode						*/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE				0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)			*/
-#define PMAP				0xF000	/* Peripheral Mapped To This Channel					*/
-#define PMAP_PPI				0x0000	/* PPI Port DMA									*/
-#define PMAP_EMACRX			0x1000	/* Ethernet Receive DMA								*/
-#define PMAP_EMACTX			0x2000	/* Ethernet Transmit DMA							*/
-#define PMAP_SPORT0RX			0x3000	/* SPORT0 Receive DMA								*/
-#define PMAP_SPORT0TX			0x4000	/* SPORT0 Transmit DMA								*/
-#define PMAP_RSI				0x4000	/* RSI DMA										*/
-#define PMAP_SPORT1RX			0x5000	/* SPORT1 Receive DMA								*/
-#define PMAP_SPI1				0x5000	/* SPI1 Transmit/Receive DMA							*/
-#define PMAP_SPORT1TX			0x6000	/* SPORT1 Transmit DMA								*/
-#define PMAP_SPI				0x7000	/* SPI DMA										*/
-#define PMAP_SPI0				0x7000	/* SPI0 DMA										*/
-#define PMAP_UART0RX			0x8000	/* UART0 Port Receive DMA							*/
-#define PMAP_UART0TX			0x9000	/* UART0 Port Transmit DMA							*/
-#define PMAP_UART1RX			0xA000	/* UART1 Port Receive DMA							*/
-#define PMAP_UART1TX			0xB000	/* UART1 Port Transmit DMA							*/
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE				0x0001	/* DMA Completion Interrupt Status						*/
-#define DMA_ERR				0x0002	/* DMA Error Interrupt Status							*/
-#define DFETCH				0x0004	/* DMA Descriptor Fetch Indicator						*/
-#define DMA_RUN				0x0008	/* DMA Channel Running Indicator						*/
-
-
-/*********************************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/
-
-/*  PPI_CONTROL Masks */
-#define PORT_EN				0x0001	/* PPI Port Enable								*/
-#define PORT_DIR				0x0002	/* PPI Port Direction								*/
-#define XFR_TYPE				0x000C	/* PPI Transfer Type								*/
-#define PORT_CFG				0x0030	/* PPI Port Configuration							*/
-#define FLD_SEL				0x0040	/* PPI Active Field Select							*/
-#define PACK_EN				0x0080	/* PPI Packing Mode								*/ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN				0x0200	/* PPI Skip Element Enable							*/
-#define SKIP_EO				0x0400	/* PPI Skip Even/Odd Elements							*/
-#define DLEN_8				0x0000	/* Data Length = 8 Bits								*/
-#define DLEN_10				0x0800	/* Data Length = 10 Bits							*/
-#define DLEN_11				0x1000	/* Data Length = 11 Bits							*/
-#define DLEN_12				0x1800	/* Data Length = 12 Bits							*/
-#define DLEN_13				0x2000	/* Data Length = 13 Bits							*/
-#define DLEN_14				0x2800	/* Data Length = 14 Bits							*/
-#define DLEN_15				0x3000	/* Data Length = 15 Bits							*/
-#define DLEN_16				0x3800	/* Data Length = 16 Bits							*/
-#define POLC				0x4000	/* PPI Clock Polarity								*/
-#define POLS				0x8000	/* PPI Frame Sync Polarity							*/
-
-/* PPI_STATUS Masks */
-#define LT_ERR_OVR			0x0100	/* Line Track Overflow Error							*/
-#define LT_ERR_UNDR			0x0200	/* Line Track Underflow Error							*/
-#define FLD					0x0400	/* Field Indicator								*/
-#define FT_ERR				0x0800	/* Frame Track Error								*/
-#define OVR					0x1000	/* FIFO Overflow Error								*/
-#define UNDR				0x2000	/* FIFO Underrun Error								*/
-#define ERR_DET				0x4000	/* Error Detected Indicator							*/
-#define ERR_NCOR				0x8000	/* Error Not Corrected Indicator						*/
-
-
-/***************************************  TWO-WIRE INTERFACE (TWI) MASKS  *****************************************/
-
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)				((x) & 0xFFu)/* Periods Clock Is Held Low							*/
-#define CLKHI(y)				(((y)&0xFFu)<<0x8)/* Periods Before New Clock Low					*/
-#else
-#define CLKLOW(x)				((x) & 0xFF)/* Periods Clock Is Held Low							*/
-#define CLKHI(y)				(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low					*/
-#endif /* _MISRA_RULES */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE				0x007F	/* SCLKs Per Internal Time Reference (10MHz)				*/
-#define TWI_ENA				0x0080	/* TWI Enable									*/
-#define SCCB				0x0200	/* SCCB Compatibility Enable							*/
-
-/* TWI_SLAVE_CTRL Masks */
-#define SEN					0x0001	/* Slave Enable									*/
-#define SADD_LEN				0x0002	/* Slave Address Length								*/
-#define STDVAL				0x0004	/* Slave Transmit Data Valid							*/
-#define NAK					0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer 			*/
-#define GEN					0x0010	/* General Call Adrress Matching Enabled					*/
-
-/* TWI_SLAVE_STAT Masks	*/
-#define SDIR				0x0001	/* Slave Transfer Direction (Transmit/Receive*)				*/
-#define GCALL				0x0002	/* General Call Indicator							*/
-
-/* TWI_MASTER_CTRL Masks */
-#define MEN					0x0001	/* Master Mode Enable								*/
-#define MADD_LEN				0x0002	/* Master Address Length							*/
-#define MDIR				0x0004	/* Master Transmit Direction (RX/TX*)					*/
-#define FAST				0x0008	/* Use Fast Mode Timing Specs							*/
-#define STOP				0x0010	/* Issue Stop Condition								*/
-#define RSTART				0x0020	/* Repeat Start or Stop* At End Of Transfer				*/
-#define DCNT				0x3FC0	/* Data Bytes To Transfer							*/
-#define SDAOVR				0x4000	/* Serial Data Override								*/
-#define SCLOVR				0x8000	/* Serial Clock Override							*/
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG				0x0001	/* Master Transfer In Progress						*/
-#define LOSTARB				0x0002	/* Lost Arbitration Indicator (Xfer Aborted)				*/
-#define ANAK				0x0004	/* Address Not Acknowledged							*/
-#define DNAK				0x0008	/* Data Not Acknowledged							*/
-#define BUFRDERR				0x0010	/* Buffer Read Error								*/
-#define BUFWRERR				0x0020	/* Buffer Write Error								*/
-#define SDASEN				0x0040	/* Serial Data Sense								*/
-#define SCLSEN				0x0080	/* Serial Clock Sense								*/
-#define BUSBUSY				0x0100	/* Bus Busy Indicator								*/
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT				0x0001	/* Slave Transfer Initiated							*/
-#define SCOMP				0x0002	/* Slave Transfer Complete							*/
-#define SERR				0x0004	/* Slave Transfer Error								*/
-#define SOVF				0x0008	/* Slave Overflow									*/
-#define MCOMP				0x0010	/* Master Transfer Complete							*/
-#define MERR				0x0020	/* Master Transfer Error							*/
-#define XMTSERV				0x0040	/* Transmit FIFO Service							*/
-#define RCVSERV				0x0080	/* Receive FIFO Service								*/
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH				0x0001	/* Transmit Buffer Flush							*/
-#define RCVFLUSH				0x0002	/* Receive Buffer Flush								*/
-#define XMTINTLEN				0x0004	/* Transmit Buffer Interrupt Length						*/
-#define RCVINTLEN				0x0008	/* Receive Buffer Interrupt Length						*/
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT				0x0003	/* Transmit FIFO Status								*/
-#define XMT_EMPTY				0x0000	/* Transmit FIFO Empty								*/
-#define XMT_HALF				0x0001	/* Transmit FIFO Has 1 Byte To Write					*/
-#define XMT_FULL				0x0003	/* Transmit FIFO Full (2 Bytes To Write)					*/
-
-#define RCVSTAT				0x000C	/* Receive FIFO Status								*/
-#define RCV_EMPTY				0x0000	/* Receive FIFO Empty								*/
-#define RCV_HALF				0x0004	/* Receive FIFO Has 1 Byte To Read						*/
-#define RCV_FULL				0x000C	/* Receive FIFO Full (2 Bytes To Read)					*/
-
-
-/*************************************  PIN CONTROL REGISTER MASKS  ***********************************************/
-
-/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
-
-
-/***********************************  HANDSHAKE DMA (HMDMA) MASKS  ************************************************/
-
-/* HMDMAx_CTL Masks */
-#define HMDMAEN				0x0001	/* Enable Handshake DMA 0/1							*/
-#define REP					0x0002	/* HMDMA Request Polarity							*/
-#define UTE					0x0004	/* Urgency Threshold Enable							*/
-#define OIE					0x0010	/* Overflow Interrupt Enable							*/
-#define BDIE				0x0020	/* Block Done Interrupt Enable						*/
-#define MBDI				0x0040	/* Mask Block Done IRQ If Pending ECNT					*/
-#define DRQ					0x0300	/* HMDMA Request Type								*/
-#define DRQ_NONE				0x0000	/* No Request									*/
-#define DRQ_SINGLE			0x0100	/* Channels Request Single							*/
-#define DRQ_MULTI				0x0200	/* Channels Request Multi (Default)						*/
-#define DRQ_URGENT			0x0300	/* Channels Request Multi Urgent						*/
-#define RBC					0x1000	/* Reload BCNT With IBCNT							*/
-#define PS					0x2000	/* HMDMA Pin Status								*/
-#define OI					0x4000	/* Overflow Interrupt Generated						*/
-#define BDI					0x8000	/* Block Done Interrupt Generated						*/
-
-/* entry addresses of the user-callable Boot ROM functions */
-#define _BOOTROM_RESET 				0xEF000000
-#define _BOOTROM_FINAL_INIT 			0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 		0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 		0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 		0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 		0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH	0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 	0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 	0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define CKELOW					SCKELOW
-
-
-/****************************************   COUNTER MASKS    ******************************************************/
-
-/* Bit masks for CNT_CONFIG */
-#define CNTE				0x1        /* Counter Enable 									*/
-#define nCNTE  				0x0
-#define DEBE  				0x2        /* Debounce Enable 								*/
-#define nDEBE  				0x0
-#define CDGINV  				0x10       /* CDG Pin Polarity Invert 							*/
-#define nCDGINV  				0x0
-#define CUDINV  				0x20       /* CUD Pin Polarity Invert 							*/
-#define nCUDINV  				0x0
-#define CZMINV  				0x40       /* CZM Pin Polarity Invert 							*/
-#define nCZMINV  				0x0
-#define CNTMODE  				0x700      /* Counter Operating Mode 							*/
-#define ZMZC  				0x800      /* CZM Zeroes Counter Enable 							*/
-#define nZMZC  				0x0
-#define BNDMODE  				0x3000     /* Boundary register Mode 							*/
-#define INPDIS  				0x8000     /* CUG and CDG Input Disable 							*/
-#define nINPDIS  				0x0
-
-/* Bit masks for CNT_IMASK */
-#define ICIE				0x1        /* Illegal Gray/Binary Code Interrupt Enable 				*/
-#define nICIE  				0x0
-#define UCIE  				0x2        /* Up count Interrupt Enable 							*/
-#define nUCIE  				0x0
-#define DCIE  				0x4        /* Down count Interrupt Enable 						*/
-#define nDCIE  				0x0
-#define MINCIE  				0x8        /* Min Count Interrupt Enable 							*/
-#define nMINCIE  				0x0
-#define MAXCIE  				0x10       /* Max Count Interrupt Enable 							*/
-#define nMAXCIE  				0x0
-#define COV31IE  				0x20       /* Bit 31 Overflow Interrupt Enable 						*/
-#define nCOV31IE  			0x0
-#define COV15IE  				0x40       /* Bit 15 Overflow Interrupt Enable 						*/
-#define nCOV15IE  			0x0
-#define CZEROIE  				0x80       /* Count to Zero Interrupt Enable 						*/
-#define nCZEROIE  			0x0
-#define CZMIE  				0x100      /* CZM Pin Interrupt Enable 							*/
-#define nCZMIE 				0x0
-#define CZMEIE  				0x200      /* CZM Error Interrupt Enable 							*/
-#define nCZMEIE  				0x0
-#define CZMZIE  				0x400      /* CZM Zeroes Counter Interrupt Enable 					*/
-#define nCZMZIE  				0x0
-
-/* Bit masks for CNT_STATUS */
-#define ICII  				0x1        /* Illegal Gray/Binary Code Interrupt Identifier 			*/
-#define nICII  				0x0
-#define UCII  				0x2        /* Up count Interrupt Identifier 						*/
-#define nUCII  				0x0
-#define DCII  				0x4        /* Down count Interrupt Identifier 						*/
-#define nDCII  				0x0
-#define MINCII  				0x8        /* Min Count Interrupt Identifier 						*/
-#define nMINCII  				0x0
-#define MAXCII  				0x10       /* Max Count Interrupt Identifier 						*/
-#define nMAXCII  				0x0
-#define COV31II  				0x20       /* Bit 31 Overflow Interrupt Identifier 					*/
-#define nCOV31II  			0x0
-#define COV15II  				0x40       /* Bit 15 Overflow Interrupt Identifier 					*/
-#define nCOV15II  			0x0
-#define CZEROII  				0x80       /* Count to Zero Interrupt Identifier 					*/
-#define nCZEROII  			0x0
-#define CZMII  				0x100      /* CZM Pin Interrupt Identifier 						*/
-#define nCZMII  				0x0
-#define CZMEII  				0x200      /* CZM Error Interrupt Identifier 						*/
-#define nCZMEII  				0x0
-#define CZMZII  				0x400      /* CZM Zeroes Counter Interrupt Identifier 				*/
-#define nCZMZII  				0x0
-
-/* Bit masks for CNT_COMMAND */
-#define W1LCNT  				0xf        /* Load Counter Register 							*/
-#define W1LMIN  				0xf0       /* Load Min Register 								*/
-#define W1LMAX  				0xf00      /* Load Max Register 								*/
-#define W1ZMONCE  			0x1000     /* Enable CZM Clear Counter Once 						*/
-#define nW1ZMONCE  			0x0
-
-/* Bit masks for CNT_DEBOUNCE */
-#define DPRESCALE				0xf        /* Load Counter Register 							*/
-
-
-/*************************************  SECURITY REGISTER MASKs  **************************************************/
-
-/* Bit masks for SECURE_SYSSWT */
-#define EMUDABL  				0x1        /* Emulation Disable. 								*/
-#define nEMUDABL  			0x0
-#define RSTDABL  				0x2        /* Reset Disable 									*/
-#define nRSTDABL  			0x0
-#define L1IDABL  				0x1c       /* L1 Instruction Memory Disable. 						*/
-#define L1DADABL  			0xe0       /* L1 Data Bank A Memory Disable. 						*/
-#define L1DBDABL  			0x700      /* L1 Data Bank B Memory Disable. 						*/
-#define DMA0OVR  				0x800      /* DMA0 Memory Access Override 						*/
-#define nDMA0OVR 				0x0
-#define DMA1OVR  				0x1000     /* DMA1 Memory Access Override 						*/
-#define nDMA1OVR  			0x0
-#define EMUOVR  				0x4000     /* Emulation Override 								*/
-#define nEMUOVR  				0x0
-#define OTPSEN  				0x8000     /* OTP Secrets Enable. 								*/
-#define nOTPSEN  				0x0
-
-/* Bit masks for SECURE_CONTROL */
-#define SECURE0  				0x1        /* SECURE 0 										*/
-#define nSECURE0  			0x0
-#define SECURE1  				0x2        /* SECURE 1 										*/
-#define nSECURE1  			0x0
-#define SECURE2  				0x4        /* SECURE 2 										*/
-#define nSECURE2  			0x0
-#define SECURE3  				0x8        /* SECURE 3 										*/
-#define nSECURE3  			0x0
-
-/* Bit masks for SECURE_STATUS */
-#define SECMODE  				0x3        /* Secured Mode Control State 							*/
-#define NMI  				0x4        /* Non Maskable Interrupt 							*/
-#define nNMI  				0x0
-#define AFVALID  				0x8        /* Authentication Firmware Valid 						*/
-#define nAFVALID  			0x0
-#define AFEXIT  				0x10       /* Authentication Firmware Exit 						*/
-#define nAFEXIT  				0x0
-#define SECSTAT  				0xe0       /* Secure Status 									*/
-
-
-/**********************************************  PWM Masks  *******************************************************/
-
-/* Bit masks for PWM_CTRL */
-#define PWM_EN				0x1		/* PWM Enable									*/
-#define PWM_SYNC_EN  			0X2	 	/* Enable Sync Enable								*/
-#define PWM_DBL  				0x4		/* Double Update Mode 								*/
-#define PWM_EXTSYNC			0x8		/* External Sync 									*/
-#define PWM_SYNCSEL  			0x10		/* External Sync Select								*/
-#define PWM_POLARITY			0x20		/* PWM Output Polarity 								*/
-#define PWM_SRMODE			0x40		/* PWM SR MODE 									*/
-#define PWMTRIPINT_EN			0x80		/* Trip Interrupt Enable 							*/
-#define PWMSYNCINT_EN			0x100		/* Sync Interrupt Enable 							*/
-#define PWMTRIP_DSBL			0x200	    	/* Trip Input Disable 								*/
-
-/* Bit masks for PWM_STAT */
-#define PWM_PHASE				0x1		/* PWM phase 									*/
-#define PWM_POL  				0x2		/* PWM polarity 									*/
-#define PWM_SR				0x4		/* PWM SR mode 									*/
-#define PWM_TRIP				0x8		/* PWM Trip mode 		 							*/
-#define PWM_TRIPINT			0x100		/* PWM Trip Interrupt 								*/
-#define PWM_SYNCINT			0x200		/* PWM Sync Interrupt								*/
-
-/* Bit masks for PWMGATE Register */
-
-#define CHOPHI				0x100		/* Gate Chopping Enable High Side 						*/
-#define CHOPLO				0x200		/* Gate Chopping Enable Low Side 						*/
-
-/* Bit masks for PWMSEG Register */
-
-#define CH_EN  				0x1		/* CH output Enable 								*/
-#define CL_EN  				0x2		/* CL output Enable 								*/
-#define BH_EN  				0x4		/* BH output Enable 								*/
-#define BL_EN  				0x8		/* BL output Enable								*/
-#define AH_EN  				0x10		/* AH output Enable 								*/
-#define AL_EN  				0x20		/* AL output Enable 								*/
-#define CHCL_XOVR  			0x40		/* Channel C output Crossover 						*/
-#define BHBL_XOVR  			0x80		/* Channel B output Crossover 						*/
-#define AHAL_XOVR  			0x100		/* Channel A output Crossover 						*/
-
-/* Bit masks for PWMLSI Register */
-#define PWM_SR_LSI_A			0x1		/* PWM SR Low Side Invert Channel A 					*/
-#define PWM_SR_LSI_B			0x2		/* PWM SR Low Side Invert Channel A 					*/
-#define PWM_SR_LSI_C			0x4		/* PWM SR Low Side Invert Channel A 					*/
-
-/* Bit masks for PWM_STAT2 Register */
-#define PWM_AL				0x1		/* pwm_al output signal for S/W observation 				*/
-#define PWM_AH				0x2		/* pwm_ah output signal for S/W observation 				*/
-#define PWM_BL				0x4		/* pwm_bl output signal for S/W observation 				*/
-#define PWM_BH				0x8		/* pwm_bh output signal for S/W observation 				*/
-#define PWM_CL				0x10		/* pwm_cl output signal for S/W observation 				*/
-#define PWM_CH				0x20		/* pwm_ch output signal for S/W observation 				*/
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF51x_H */
diff --git a/libgloss/bfin/include/defBF522.h b/libgloss/bfin/include/defBF522.h
deleted file mode 100644
index 67c3976ef..000000000
--- a/libgloss/bfin/include/defBF522.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-#endif /* _DEF_BF522_H */
diff --git a/libgloss/bfin/include/defBF523.h b/libgloss/bfin/include/defBF523.h
deleted file mode 100644
index fe1417293..000000000
--- a/libgloss/bfin/include/defBF523.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF523_H
-#define _DEF_BF523_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF523 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-#endif /* _DEF_BF523_H */
diff --git a/libgloss/bfin/include/defBF524.h b/libgloss/bfin/include/defBF524.h
deleted file mode 100644
index 2dc3182ff..000000000
--- a/libgloss/bfin/include/defBF524.h
+++ /dev/null
@@ -1,704 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF524_H
-#define _DEF_BF524_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF524 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-/* The following are the #defines needed by ADSP-BF524 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF524_H */
diff --git a/libgloss/bfin/include/defBF525.h b/libgloss/bfin/include/defBF525.h
deleted file mode 100644
index 563ac6663..000000000
--- a/libgloss/bfin/include/defBF525.h
+++ /dev/null
@@ -1,704 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/libgloss/bfin/include/defBF526.h b/libgloss/bfin/include/defBF526.h
deleted file mode 100644
index 64b72ed4f..000000000
--- a/libgloss/bfin/include/defBF526.h
+++ /dev/null
@@ -1,1121 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF526_H
-#define _DEF_BF526_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF526 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some acros violate rule 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF526 that are not in the common header */
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define	RE                 0x00000001     /* Receiver Enable                                    */
-#define	ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define	HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define	HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define	PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define	PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define	IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define	DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define	PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define	PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define	RAF                0x00001000     /* Receive-All Mode                                   */
-#define	TE                 0x00010000     /* Transmitter Enable                                 */
-#define	DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define	DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define	DC                 0x00080000     /* Deferral Check                                     */
-#define	BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define	BOLMT_10           0x00000000     /*		10-bit range                            */
-#define	BOLMT_8            0x00100000     /*		8-bit range                             */
-#define	BOLMT_4            0x00200000     /*		4-bit range                             */
-#define	BOLMT_1            0x00300000     /*		1-bit range                             */
-#define	DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define	LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define	RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define	RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define	FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define	LB                 0x08000000     /* Internal Loopback Enable                           */
-#define	DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define	STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define	STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define	STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define	STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define	REGAD              0x000007C0     /* STA Register Address                               */
-#define	PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#ifdef _MISRA_RULES
-#define	SET_REGAD(x) (((x)&0x1Fu)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1Fu)<< 11 )   /* Set PHY Device Address                             */
-#else
-#define	SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-#endif /* _MISRA_RULES */
-
-/* EMAC_STADAT Mask */
-
-#define	STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define	FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define	FLCE               0x00000002     /* Flow Control Enable                                */
-#define	PCF                0x00000004     /* Pass Control Frames                                */
-#define	BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define	FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#ifdef _MISRA_RULES
-#define	SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time                                   */
-#else
-#define	SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define	CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define	MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define	RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define	GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define	MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define	RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define	WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define	WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define	WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define	WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define	WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define	WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define	WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define	WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define	WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define	WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define	WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define	WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_OFF(x) (((x)&0xFFu)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFFu)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#else
-#define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#endif /* _MISRA_RULES */
-
-/* Set ALL Offsets */
-#define	SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define	WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define	WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#else
-#define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define	WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define	WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF2_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#else
-#define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSCTL Masks */
-
-#define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#ifdef _MISRA_RULES
-#define	SET_MDCDIV(x) (((x)&0x3Fu)<< 8)   /* Set MDC Clock Divisor                                 */
-#else
-#define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSTAT Masks */
-
-#define	PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define	MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define	RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define	TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define	WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define	RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define	TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define	STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define	RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define	RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define	RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define	RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define	RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define	RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define	RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define	RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define	RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define	RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define	RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define	RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define	RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define	RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define	RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define	RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define	RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define	RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define	RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define	RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define	RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define	TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define	TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define	TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define	TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define	TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define	TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define	TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define	TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define	TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define	TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define	TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define	TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define	TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define	TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define	TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define	RSTC              0x00000001    /* Reset All Counters                                     */
-#define	CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define	CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define	MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define	RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define	RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define	RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define	RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define	RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define	RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define	RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define	RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define	RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define	RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define	RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define	RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define	RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define	RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define	RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define	RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define	RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define	RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define	RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define	RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define	RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define	RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define	RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define	RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define	TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define	TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define	TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define	TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define	TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define	TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define	TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define	TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define	TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define	TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define	TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define	TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define	TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define	TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define	TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define	TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define	TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define	TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define	TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define	TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define	TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF526_H */
diff --git a/libgloss/bfin/include/defBF527.h b/libgloss/bfin/include/defBF527.h
deleted file mode 100644
index 1bf4d3939..000000000
--- a/libgloss/bfin/include/defBF527.h
+++ /dev/null
@@ -1,1121 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include <defBF52x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define	RE                 0x00000001     /* Receiver Enable                                    */
-#define	ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define	HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define	HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define	PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define	PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define	IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define	DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define	PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define	PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define	RAF                0x00001000     /* Receive-All Mode                                   */
-#define	TE                 0x00010000     /* Transmitter Enable                                 */
-#define	DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define	DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define	DC                 0x00080000     /* Deferral Check                                     */
-#define	BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define	BOLMT_10           0x00000000     /*		10-bit range                            */
-#define	BOLMT_8            0x00100000     /*		8-bit range                             */
-#define	BOLMT_4            0x00200000     /*		4-bit range                             */
-#define	BOLMT_1            0x00300000     /*		1-bit range                             */
-#define	DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define	LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define	RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define	RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define	FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define	LB                 0x08000000     /* Internal Loopback Enable                           */
-#define	DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define	STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define	STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define	STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define	STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define	REGAD              0x000007C0     /* STA Register Address                               */
-#define	PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#ifdef _MISRA_RULES
-#define	SET_REGAD(x) (((x)&0x1Fu)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1Fu)<< 11 )   /* Set PHY Device Address                             */
-#else
-#define	SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define	SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-#endif /* _MISRA_RULES */
-
-/* EMAC_STADAT Mask */
-
-#define	STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define	FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define	FLCE               0x00000002     /* Flow Control Enable                                */
-#define	PCF                0x00000004     /* Pass Control Frames                                */
-#define	BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define	FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#ifdef _MISRA_RULES
-#define	SET_FLCPAUSE(x) (((x)&0xFFFFu)<< 16) /* Set Pause Time                                   */
-#else
-#define	SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define	CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define	MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define	RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define	GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define	MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define	RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define	WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define	WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define	WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define	WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define	WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define	WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define	WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define	WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define	WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define	WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define	WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define	WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_OFF(x) (((x)&0xFFu)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFFu)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#else
-#define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-#endif /* _MISRA_RULES */
-
-/* Set ALL Offsets */
-#define	SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define	WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define	WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#else
-#define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define	WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define	WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#ifdef _MISRA_RULES
-#define	SET_WF2_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#else
-#define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSCTL Masks */
-
-#define	PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define	RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define	RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define	MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#ifdef _MISRA_RULES
-#define	SET_MDCDIV(x) (((x)&0x3Fu)<< 8)   /* Set MDC Clock Divisor                                 */
-#else
-#define	SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSTAT Masks */
-
-#define	PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define	MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define	RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define	TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define	WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define	RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define	TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define	STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define	RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define	RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define	RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define	RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define	RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define	RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define	RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define	RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define	RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define	RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define	RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define	RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define	RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define	RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define	RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define	RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define	RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define	RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define	RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define	RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define	RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define	TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define	TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define	TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define	TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define	TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define	TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define	TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define	TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define	TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define	TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define	TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define	TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define	TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define	TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define	TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define	RSTC              0x00000001    /* Reset All Counters                                     */
-#define	CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define	CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define	MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define	RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define	RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define	RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define	RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define	RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define	RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define	RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define	RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define	RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define	RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define	RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define	RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define	RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define	RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define	RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define	RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define	RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define	RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define	RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define	RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define	RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define	RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define	RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define	RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define	TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define	TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define	TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define	TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define	TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define	TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define	TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define	TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define	TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define	TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define	TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define	TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define	TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define	TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define	TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define	TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define	TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define	TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define	TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define	TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define	TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define	TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define	TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF527_H */
diff --git a/libgloss/bfin/include/defBF52x_base.h b/libgloss/bfin/include/defBF52x_base.h
deleted file mode 100644
index 6483d0f55..000000000
--- a/libgloss/bfin/include/defBF52x_base.h
+++ /dev/null
@@ -1,2101 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF52x_base.h
-**
-** Copyright (C) 2007-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _DEF_BF52X_H
-#define _DEF_BF52X_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
-#define PLL_CTL				0xFFC00000	/* PLL Control Register						*/
-#define PLL_DIV				0xFFC00004	/* PLL Divide Register						*/
-#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register		*/
-#define PLL_STAT			0xFFC0000C	/* PLL Status Register						*/
-#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register					*/
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
-#define SWRST				0xFFC00100	/* Software Reset Register					*/
-#define SYSCR				0xFFC00104	/* System Configuration Register			*/
-
-#define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register					*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IMASK			SIC_IMASK0
-
-#define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0			*/
-#define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1			*/
-#define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2			*/
-#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3			*/
-
-#define SIC_ISR0			0xFFC00120	/* Interrupt Status Register				*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_ISR				SIC_ISR0
-
-#define SIC_IWR0			0xFFC00124	/* Interrupt Wakeup Register				*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IWR				SIC_IWR0
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
-#define WDOG_CTL			0xFFC00200	/* Watchdog Control Register				*/
-#define WDOG_CNT			0xFFC00204	/* Watchdog Count Register					*/
-#define WDOG_STAT			0xFFC00208	/* Watchdog Status Register					*/
-
-
-/* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
-#define RTC_STAT			0xFFC00300	/* RTC Status Register						*/
-#define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register			*/
-#define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register			*/
-#define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register				*/
-#define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register					*/
-#define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register			*/
-#define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro		*/
-
-
-/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
-#define UART0_THR			0xFFC00400	/* Transmit Holding register				*/
-#define UART0_RBR			0xFFC00400	/* Receive Buffer register					*/
-#define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)					*/
-#define UART0_IER			0xFFC00404	/* Interrupt Enable Register				*/
-#define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)				*/
-#define UART0_IIR			0xFFC00408	/* Interrupt Identification Register		*/
-#define UART0_LCR			0xFFC0040C	/* Line Control Register					*/
-#define UART0_MCR			0xFFC00410	/* Modem Control Register					*/
-#define UART0_LSR			0xFFC00414	/* Line Status Register						*/
-#define UART0_SCR			0xFFC0041C	/* SCR Scratch Register						*/
-#define UART0_GCTL			0xFFC00424	/* Global Control Register					*/
-
-
-/* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/
-#define SPI_CTL				0xFFC00500	/* SPI Control Register						*/
-#define SPI_FLG				0xFFC00504	/* SPI Flag register						*/
-#define SPI_STAT			0xFFC00508	/* SPI Status register						*/
-#define SPI_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register		*/
-#define SPI_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register			*/
-#define SPI_BAUD			0xFFC00514	/* SPI Baud rate Register					*/
-#define SPI_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register					*/
-
-
-/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
-#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register			*/
-#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register					*/
-#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register					*/
-#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register					*/
-
-#define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register  			*/
-#define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register        			*/
-#define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register         			*/
-#define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register          			*/
-
-#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register  			*/
-#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register        			*/
-#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register         			*/
-#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register          			*/
-
-#define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register			*/
-#define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register					*/
-#define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register					*/
-#define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register					*/
-
-#define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register  			*/
-#define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register        			*/
-#define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register         			*/
-#define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register          			*/
-
-#define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register  			*/
-#define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register        			*/
-#define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register         			*/
-#define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register          			*/
-
-#define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register  			*/
-#define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register        			*/
-#define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register         			*/
-#define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register          			*/
-
-#define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register  			*/
-#define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register        			*/
-#define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register         			*/
-#define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/
-
-#define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register					*/
-#define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register					*/
-#define TIMER_STATUS		0xFFC00688	/* Timer Status Register					*/
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)												*/
-#define PORTFIO					0xFFC00700	/* Port F I/O Pin State Specify Register				*/
-#define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register		*/
-#define PORTFIO_SET				0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register			*/
-#define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
-#define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register	*/
-#define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register			*/
-#define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register			*/
-#define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register	*/
-#define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register			*/
-#define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register			*/
-#define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTFIO_DIR				0xFFC00730	/* Port F I/O Direction Register						*/
-#define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
-#define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register				*/
-#define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register				*/
-#define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
-
-
-/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)										*/
-#define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register			*/
-#define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register			*/
-#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider					*/
-#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider				*/
-#define SPORT0_TX			0xFFC00810	/* SPORT0 TX Data Register							*/
-#define SPORT0_RX			0xFFC00818	/* SPORT0 RX Data Register							*/
-#define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register			*/
-#define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register			*/
-#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider						*/
-#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider				*/
-#define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
-#define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register					*/
-#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1	*/
-#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2	*/
-#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0	*/
-#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1	*/
-#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2	*/
-#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3	*/
-#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0	*/
-#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1	*/
-#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2	*/
-#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3	*/
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)										*/
-#define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register			*/
-#define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register			*/
-#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider					*/
-#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider				*/
-#define SPORT1_TX			0xFFC00910	/* SPORT1 TX Data Register							*/
-#define SPORT1_RX			0xFFC00918	/* SPORT1 RX Data Register							*/
-#define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register			*/
-#define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register			*/
-#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider						*/
-#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider				*/
-#define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
-#define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register					*/
-#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1	*/
-#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2	*/
-#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0	*/
-#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1	*/
-#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2	*/
-#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3	*/
-#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0	*/
-#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1	*/
-#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2	*/
-#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3	*/
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)								*/
-#define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register	*/
-#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0	*/
-#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1	*/
-#define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register				*/
-#define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register					*/
-#define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register			*/
-#define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register						*/
-
-
-/* DMA Traffic Control Registers													*/
-#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
-#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER			0xFFC00B0C	/* Traffic Control Periods Register			*/
-#define DMA_TCCNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/
-#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/
-#define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
-#define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
-#define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
-#define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
-#define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
-#define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
-#define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register	*/
-#define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register				*/
-#define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
-#define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register				*/
-#define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register				*/
-#define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register				*/
-
-#define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register		*/
-#define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
-#define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
-#define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
-#define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
-#define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
-#define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
-#define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register	*/
-#define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register				*/
-#define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
-#define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register				*/
-#define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register				*/
-#define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register				*/
-
-#define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register		*/
-#define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
-#define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
-#define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
-#define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
-#define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
-#define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
-#define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register	*/
-#define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register				*/
-#define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
-#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register				*/
-#define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register				*/
-#define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register				*/
-
-#define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register		*/
-#define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
-#define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
-#define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
-#define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
-#define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
-#define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
-#define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register	*/
-#define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register				*/
-#define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
-#define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register				*/
-#define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register				*/
-#define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register				*/
-
-#define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register		*/
-#define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
-#define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
-#define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
-#define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
-#define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
-#define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
-#define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register	*/
-#define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register				*/
-#define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
-#define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register				*/
-#define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register				*/
-#define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register				*/
-
-#define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register		*/
-#define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
-#define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
-#define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
-#define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
-#define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
-#define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
-#define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register	*/
-#define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register				*/
-#define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
-#define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register				*/
-#define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register				*/
-#define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register				*/
-
-#define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register		*/
-#define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
-#define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
-#define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
-#define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
-#define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
-#define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
-#define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register	*/
-#define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register				*/
-#define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
-#define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register				*/
-#define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register				*/
-#define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register				*/
-
-#define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register		*/
-#define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
-#define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
-#define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
-#define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
-#define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
-#define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
-#define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register	*/
-#define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register				*/
-#define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
-#define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register				*/
-#define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register				*/
-#define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register				*/
-
-#define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
-#define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG				0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
-#define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register				*/
-#define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register				*/
-#define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register				*/
-#define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register				*/
-
-#define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
-#define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register					*/
-#define DMA9_CONFIG				0xFFC00E48	/* DMA Channel 9 Configuration Register					*/
-#define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register						*/
-#define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register						*/
-#define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register						*/
-#define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register						*/
-#define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
-#define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register				*/
-#define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register				*/
-#define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register				*/
-#define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register				*/
-#define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register				*/
-
-#define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
-#define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register				*/
-#define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register				*/
-#define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register						*/
-#define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register						*/
-#define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register						*/
-#define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register						*/
-#define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
-#define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register				*/
-#define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register				*/
-#define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register				*/
-#define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register				*/
-#define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register				*/
-
-#define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
-#define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register				*/
-#define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register				*/
-#define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register						*/
-#define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register						*/
-#define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register						*/
-#define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register						*/
-#define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
-#define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register				*/
-#define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register				*/
-#define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register				*/
-#define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register				*/
-#define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register				*/
-
-#define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register				*/
-#define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register				*/
-#define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register						*/
-#define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register					*/
-#define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register						*/
-#define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register					*/
-#define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register				*/
-#define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register				*/
-#define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register				*/
-#define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register			*/
-#define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register					*/
-#define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register					*/
-#define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register							*/
-#define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register							*/
-#define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register							*/
-#define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register							*/
-#define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register		*/
-#define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register					*/
-#define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register					*/
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register					*/
-#define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register					*/
-#define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register					*/
-
-#define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register				*/
-#define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register				*/
-#define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register						*/
-#define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register					*/
-#define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register						*/
-#define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register					*/
-#define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register				*/
-#define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register				*/
-#define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register				*/
-#define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register			*/
-#define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register					*/
-#define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register					*/
-#define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register							*/
-#define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register							*/
-#define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register							*/
-#define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register							*/
-#define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register		*/
-#define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register					*/
-#define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register					*/
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register					*/
-#define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register					*/
-#define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register					*/
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)				*/
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register			*/
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register			*/
-#define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register	*/
-#define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register		*/
-#define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register	*/
-
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
-#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register			*/
-#define TWI_CONTROL			0xFFC01404	/* TWI Control Register						*/
-#define TWI_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register				*/
-#define TWI_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register				*/
-#define TWI_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register				*/
-#define TWI_MASTER_CTL		0xFFC01414	/* Master Mode Control Register				*/
-#define TWI_MASTER_STAT		0xFFC01418	/* Master Mode Status Register				*/
-#define TWI_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register				*/
-#define TWI_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register			*/
-#define TWI_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register		*/
-#define TWI_FIFO_CTL		0xFFC01428	/* FIFO Control Register					*/
-#define TWI_FIFO_STAT		0xFFC0142C	/* FIFO Status Register						*/
-#define TWI_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register	*/
-#define TWI_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register	*/
-#define TWI_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register	*/
-#define TWI_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register	*/
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)												*/
-#define PORTGIO					0xFFC01500	/* Port G I/O Pin State Specify Register				*/
-#define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register		*/
-#define PORTGIO_SET				0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register			*/
-#define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register					*/
-#define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register	*/
-#define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register			*/
-#define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register			*/
-#define PORTGIO_MASKA_TOGGLE	0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register	*/
-#define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register			*/
-#define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register			*/
-#define PORTGIO_MASKB_TOGGLE	0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTGIO_DIR				0xFFC01530	/* Port G I/O Direction Register						*/
-#define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register					*/
-#define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register				*/
-#define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register				*/
-#define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register						*/
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)												*/
-#define PORTHIO					0xFFC01700	/* Port H I/O Pin State Specify Register				*/
-#define PORTHIO_CLEAR			0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register		*/
-#define PORTHIO_SET				0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register			*/
-#define PORTHIO_TOGGLE			0xFFC0170C	/* Port H I/O Pin State Toggle Register					*/
-#define PORTHIO_MASKA			0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register	*/
-#define PORTHIO_MASKA_CLEAR		0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register			*/
-#define PORTHIO_MASKA_SET		0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register			*/
-#define PORTHIO_MASKA_TOGGLE	0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTHIO_MASKB			0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register	*/
-#define PORTHIO_MASKB_CLEAR		0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register			*/
-#define PORTHIO_MASKB_SET		0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register			*/
-#define PORTHIO_MASKB_TOGGLE	0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTHIO_DIR				0xFFC01730	/* Port H I/O Direction Register						*/
-#define PORTHIO_POLAR			0xFFC01734	/* Port H I/O Source Polarity Register					*/
-#define PORTHIO_EDGE			0xFFC01738	/* Port H I/O Source Sensitivity Register				*/
-#define PORTHIO_BOTH			0xFFC0173C	/* Port H I/O Set on BOTH Edges Register				*/
-#define PORTHIO_INEN			0xFFC01740	/* Port H I/O Input Enable Register						*/
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define UART1_THR			0xFFC02000	/* Transmit Holding register			*/
-#define UART1_RBR			0xFFC02000	/* Receive Buffer register				*/
-#define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)				*/
-#define UART1_IER			0xFFC02004	/* Interrupt Enable Register			*/
-#define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)			*/
-#define UART1_IIR			0xFFC02008	/* Interrupt Identification Register	*/
-#define UART1_LCR			0xFFC0200C	/* Line Control Register				*/
-#define UART1_MCR			0xFFC02010	/* Modem Control Register				*/
-#define UART1_LSR			0xFFC02014	/* Line Status Register					*/
-#define UART1_SCR			0xFFC0201C	/* SCR Scratch Register					*/
-#define UART1_GCTL			0xFFC02024	/* Global Control Register				*/
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)											*/
-#define PORTF_FER			0xFFC03200	/* Port F Function Enable Register (Alternate/Flag*)	*/
-#define PORTG_FER			0xFFC03204	/* Port G Function Enable Register (Alternate/Flag*)	*/
-#define PORTH_FER			0xFFC03208	/* Port H Function Enable Register (Alternate/Flag*)	*/
-
-
-/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)										*/
-#define HMDMA0_CONTROL		0xFFC03300	/* Handshake MDMA0 Control Register					*/
-#define HMDMA0_ECINIT		0xFFC03304	/* HMDMA0 Initial Edge Count Register				*/
-#define HMDMA0_BCINIT		0xFFC03308	/* HMDMA0 Initial Block Count Register				*/
-#define HMDMA0_ECURGENT		0xFFC0330C	/* HMDMA0 Urgent Edge Count Threshhold Register		*/
-#define HMDMA0_ECOVERFLOW	0xFFC03310	/* HMDMA0 Edge Count Overflow Interrupt Register	*/
-#define HMDMA0_ECOUNT		0xFFC03314	/* HMDMA0 Current Edge Count Register				*/
-#define HMDMA0_BCOUNT		0xFFC03318	/* HMDMA0 Current Block Count Register				*/
-
-#define HMDMA1_CONTROL		0xFFC03340	/* Handshake MDMA1 Control Register					*/
-#define HMDMA1_ECINIT		0xFFC03344	/* HMDMA1 Initial Edge Count Register				*/
-#define HMDMA1_BCINIT		0xFFC03348	/* HMDMA1 Initial Block Count Register				*/
-#define HMDMA1_ECURGENT		0xFFC0334C	/* HMDMA1 Urgent Edge Count Threshhold Register		*/
-#define HMDMA1_ECOVERFLOW	0xFFC03350	/* HMDMA1 Edge Count Overflow Interrupt Register	*/
-#define HMDMA1_ECOUNT		0xFFC03354	/* HMDMA1 Current Edge Count Register				*/
-#define HMDMA1_BCOUNT		0xFFC03358	/* HMDMA1 Current Block Count Register				*/
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_HYSTERESIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE           0xFFC03280      /* Drive strength control for non-GPIO pins */
-#define NONGPIO_HYSTERESIS      0xFFC03288      /* Schmitt trigger control for non-GPIO pins */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks																	*/
-#define DF				0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
-#define PLL_OFF			0x0002	/* PLL Not Powered									*/
-#define STOPCK			0x0008	/* Core Clock Off									*/
-#define PDWN			0x0020	/* Enter Deep Sleep Mode							*/
-#define	IN_DELAY		0x0040	/* Add 200ps Delay To EBIU Input Latches			*/
-#define	OUT_DELAY		0x0080	/* Add 200ps Delay To EBIU Output Signals			*/
-#define BYPASS			0x0100	/* Bypass the PLL									*/
-#define	MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors			*/
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)			*/
-#ifdef _MISRA_RULES
-#define	SET_MSEL(x)		(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#else
-#define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks														*/
-#define SSEL			0x000F	/* System Select						*/
-#define	CSEL			0x0030	/* Core Select							*/
-#define CSEL_DIV1		0x0000	/* 		CCLK = VCO / 1					*/
-#define CSEL_DIV2		0x0010	/* 		CCLK = VCO / 2					*/
-#define	CSEL_DIV4		0x0020	/* 		CCLK = VCO / 4					*/
-#define	CSEL_DIV8		0x0030	/* 		CCLK = VCO / 8					*/
-/* PLL_DIV Macros														*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)		((x)&0xFu)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#else
-#define SET_SSEL(x)		((x)&0xF)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks																	*/
-#define	FREQ			0x3000	/* Switching Oscillator Frequency For Regulator	*/
-#define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
-
-#define	VLEV			0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications */
-#define	VLEV_085		0x0040	/*	VLEV = 0.85 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_090		0x0050	/*	VLEV = 0.90 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_095		0x0060	/*	VLEV = 0.95 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_100		0x0070	/*	VLEV = 1.00 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_105		0x0080	/*	VLEV = 1.05 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_110		0x0090	/*	VLEV = 1.10 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_115		0x00A0	/*	VLEV = 1.15 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_120		0x00B0	/*	VLEV = 1.20 V (See Datasheet for Regulator Tolerance)	*/
-
-#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
-#define	USBWE			0x0200	/* Enable USB Wakeup From Hibernate			*/
-#define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
-#define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
-#define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
-#define	SCKELOW			0x8000	/* Enable Drive CKE Low During Reset		*/
-
-/* PLL_STAT Masks																	*/
-#define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
-#define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
-#define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
-#define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
-#define	VSTAT				0x0080	/* Voltage Regulator Status: Regulator at programmed voltage */
-
-/* SWRST Masks																		*/
-#define SYSTEM_RESET		0x0007	/* Initiates A System Software Reset			*/
-#define	DOUBLE_FAULT		0x0008	/* Core Double Fault Causes Reset				*/
-#define RESET_DOUBLE		0x2000	/* SW Reset Generated By Core Double-Fault		*/
-#define RESET_WDOG			0x4000	/* SW Reset Generated By Watchdog Timer			*/
-#define RESET_SOFTWARE		0x8000	/* SW Reset Occurred Since Last Read Of SWRST	*/
-
-/* SYSCR Masks */
-
-#define BMODE_BYPASS        0x0000  /* Bypass boot ROM, execute from 16-bit external memory */
-#define BMODE_FLASH         0x0001  /* Use Boot ROM to load from 8-bit or 16-bit flash */
-#define BMODE_SPIMEM        0x0003  /* Boot from serial SPI memory */
-#define BMODE_SPIHOST       0x0004  /* Boot from SPI0 host (slave mode) */
-#define BMODE_TWIMEM        0x0005  /* Boot from serial TWI memory */
-#define BMODE_TWIHOST       0x0006  /* Boot from TWI0 host (slave mode) */
-#define BMODE_UART0HOST     0x0007  /* Boot from UART0 host */
-#define BMODE_UART1HOST     0x0008  /* Boot from UART1 host */
-#define BMODE_SDRAMMEM      0x000A  /* Boot from SDRAM memory (warm boot) */
-#define BMODE_OTPMEM        0x000B  /* Boot from OTP memory */
-#define BMODE_HOSTDMA_ACK   0x000E  /* Boot from 16-bit host DMA (ACK mode) */
-#define BMODE_HOSTDMA_INT   0x000F   /* Boot from 8-bit host DMA (INT mode) */
-#define BMODE 0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
-
-#define BCODE 0x00F0
-#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
-#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
-#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
-#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
-#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
-
-#define DCB1_PRIO 0x0100 /* DCB1 requests are urgent */
-#define DCB_ROT_PRIO 0x0200 /* enable rotating DCB priority */
-#define DEB1_PRIO 0x0400 /* DEB1 requests are urgent */
-#define DEB_ROT_PRIO 0x0800 /* enable rotating DEB priority */
-
-#define WURESET 0x1000 /* wakeup event since last hardware reset */
-#define DFRESET 0x2000 /* recent reset was due to a double fault event */
-#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
-#define SWRESET 0x8000 /* recent reset was issued by software */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0										*/
-#define IRQ_PLL_WAKEUP	0x00000001	/* PLL Wakeup Interrupt			 					*/
-
-#define IRQ_DMA_ERR0   0x00000002  /* Error Interrupt (DMA error 0 interrupt (generic)) */
-#define IRQ_DMAR0      0x00000004  /* DMAR0 Block (DMAR0 block interrupt) 				*/
-#define IRQ_DMAR1      0x00000008  /* DMAR1 Block  (DMAR1 block interrupt) 				*/
-#define IRQ_DMAR0_ERR  0x00000010  /* Error Interrupt (DMAR0 overflow error interrupt)  */
-#define IRQ_DMAR1_ERR  0x00000020  /* Error Interrupt (DMAR1 overflow error interrupt)  */
-#define IRQ_PPI_ERR    0x00000040  /* Error Interrupt (PPI error interrupt) 			*/
-#define IRQ_MAC_ERR    0x00000080  /* Error Interrupt (MAC status interrupt) 			*/
-#define IRQ_SPORT0_ERR 0x00000100  /* Error Interrupt (SPORT0 status interrupt) 		*/
-#define IRQ_SPORT1_ERR 0x00000200  /* Error Interrupt (SPORT1 status interrupt) 		*/
-#define IRQ_UART0_ERR  0x00001000  /* Error Interrupt (UART0 status interrupt) 			*/
-#define IRQ_UART1_ERR  0x00002000  /* Error Interrupt (UART1 status interrupt) 			*/
-#define IRQ_RTC		   0x00004000  /* Real Time Clock Interrupt 						*/
-#define IRQ_DMA0	   0x00008000  /* DMA channel 0 (PPI/NFC) Interrupt 				*/
-#define IRQ_DMA3	   0x00010000  /* DMA Channel 3 (SPORT0 RX) Interrupt 				*/
-#define IRQ_DMA4	   0x00020000  /* DMA Channel 4 (SPORT0 TX) Interrupt 				*/
-#define IRQ_DMA5	   0x00040000  /* DMA Channel 5 (SPORT1 RX) Interrupt 				*/
-#define IRQ_DMA6	   0x00080000  /* DMA Channel 6 (SPORT1 TX) Interrupt 		 		*/
-#define IRQ_TWI		   0x00100000  /* TWI Interrupt										*/
-#define IRQ_DMA7	   0x00200000  /* DMA Channel 7 (SPI) Interrupt 					*/
-#define IRQ_DMA8	   0x00400000  /* DMA Channel 8 (UART0 RX) Interrupt 				*/
-#define IRQ_DMA9	   0x00800000  /* DMA Channel 9 (UART0 TX) Interrupt 				*/
-#define IRQ_DMA10	   0x01000000  /* DMA Channel 10 (UART1 RX) Interrupt 				*/
-#define IRQ_DMA11	   0x02000000  /* DMA Channel 11 (UART1 TX) Interrupt 				*/
-#define IRQ_OTP	   0x04000000  /* OTP Interrupt 									*/
-#define IRQ_CNT  	   0x08000000  /* GP Counter Interrupt  							*/
-#define IRQ_DMA1	   0x10000000  /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt		*/
-#define IRQ_PFA_PORTH  0x20000000  /* PF Port H Interrupt A 							*/
-#define IRQ_DMA2	   0x40000000  /* DMA Channel 2 (Ethernet TX/NFC) Interrupt 		*/
-#define IRQ_PFB_PORTH  0x80000000  /* PF Port H  Interrupt B 							*/
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1									*/
-
-#define IRQ_TIMER0		0x00000001	/* Timer 0 Interrupt								*/
-#define IRQ_TIMER1		0x00000002	/* Timer 1 Interrupt 								*/
-#define IRQ_TIMER2		0x00000004	/* Timer 2 Interrupt 								*/
-#define IRQ_TIMER3		0x00000008	/* Timer 3 Interrupt 								*/
-#define IRQ_TIMER4		0x00000010	/* Timer 4 Interrupt 								*/
-#define IRQ_TIMER5		0x00000020	/* Timer 5 Interrupt 								*/
-#define IRQ_TIMER6		0x00000040	/* Timer 6 Interrupt 								*/
-#define IRQ_TIMER7		0x00000080	/* Timer 7 Interrupt 								*/
-#define IRQ_PFA_PORTG	0x00000100	/* PF Port G Interrupt A 							*/
-#define IRQ_PFB_PORTG	0x00000200	/* PF Port G Interrupt B		 					*/
-#define IRQ_DMA12		0x00000400	/* DMA Channels 12 (MDMA0 Destination) TX Interrupt	*/
-#define IRQ_DMA13		0x00000400	/* DMA Channels 13 (MDMA0 Source) RX Interrupt		*/
-#define IRQ_DMA14		0x00000800	/* DMA Channels 14 (MDMA1 Destination) TX Interrupt	*/
-#define IRQ_DMA15		0x00000800	/* DMA Channels 15 (MDMA1 Source) RX Interrupt 		*/
-#define IRQ_WDOG		0x00001000	/* Software Watchdog Timer Interrupt 				*/
-#define IRQ_PFA_PORTF	0x00002000	/* PF Port F Interrupt A		 					*/
-#define IRQ_PFB_PORTF	0x00004000	/* PF Port F Interrupt B 							*/
-#define IRQ_SPI_ERR     0x00008000  /* Error Interrupt (SPI status interrupt) 			*/
-#define IRQ_NAND_ERR	0x00010000	/* NAND error interrupt								*/
-#define IRQ_HOSTDP_STATUS	0x00020000	/* HOSTDP status interrupt  */
-#define IRQ_HOSTRD_DONE	0x00040000		/* Host Read Done interrupt */
-#define IRQ_USB_EINT	0x00080000	/* USB EINT interrupt 								*/
-#define IRQ_USB_INT0	0x00100000	/* USB INT0 interrupt 								*/
-#define IRQ_USB_INT1	0x00200000	/* USB INT1 interrupt 								*/
-#define IRQ_USB_INT2	0x00400000	/* USB INT1 interrupt 								*/
-#define IRQ_USB_DMAINT	0x00800000	/* USB DMAINT interrupt								*/
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define IWR_DISABLE_ALL   0x00000000   /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL    0xFFFFFFFF   /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)     (1 << (x))   /* Wakeup Enable Peripheral #x */
-#ifdef _MISRA_RULES
-#define IWR_DISABLE(x)    (0xFFFFFFFFu^(1<<(x)))/* Wakeup Disable Peripheral #x */
-#else
-#define IWR_DISABLE(x)    (0xFFFFFFFF^(1<<(x)))/* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #0 assigned IVG #x    */
-#define P1_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #1 assigned IVG #x    */
-#define P2_IVG(x)       ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #2 assigned IVG #x    */
-#define P3_IVG(x)       ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #3 assigned IVG #x    */
-#define P4_IVG(x)       ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #4 assigned IVG #x    */
-#define P5_IVG(x)       ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #5 assigned IVG #x    */
-#define P6_IVG(x)       ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #6 assigned IVG #x    */
-#define P7_IVG(x)       ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #7 assigned IVG #x    */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #8 assigned IVG #x    */
-#define P9_IVG(x)       ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #9 assigned IVG #x    */
-#define P10_IVG(x)                                   /* Reserved                         */
-#define P11_IVG(x)                                   /* Reserved                         */
-#define P12_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #12 assigned IVG #x   */
-#define P13_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #13 assigned IVG #x   */
-#define P14_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #14 assigned IVG #x   */
-#define P15_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #15 assigned IVG #x   */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #16 assigned IVG #x   */
-#define P17_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #17 assigned IVG #x   */
-#define P18_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #18 assigned IVG #x   */
-#define P19_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #19 assigned IVG #x   */
-#define P20_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #20 assigned IVG #x   */
-#define P21_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #21 assigned IVG #x   */
-#define P22_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #22 assigned IVG #x   */
-#define P23_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #23 assigned IVG #x   */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #24 assigned IVG #x   */
-#define P25_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #25 assigned IVG #x   */
-#define P26_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #26 assigned IVG #x   */
-#define P27_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #27 assigned IVG #x   */
-#define P28_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #28 assigned IVG #x   */
-#define P29_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #29 assigned IVG #x   */
-#define P30_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #30 assigned IVG #x   */
-#define P31_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #31 assigned IVG #x   */
-
-/* SIC_IAR4 Macros */
-#define P32_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #32 assigned IVG #x   */
-#define P33_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #33 assigned IVG #x   */
-#define P34_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #34 assigned IVG #x   */
-#define P35_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #35 assigned IVG #x   */
-#define P36_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #36 assigned IVG #x   */
-#define P37_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #37 assigned IVG #x   */
-#define P38_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #38 assigned IVG #x   */
-#define P39_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #39 assigned IVG #x   */
-
-/* SIC_IAR5 Macros */
-#define P40_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #40 assigned IVG #x   */
-#define P41_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #41 assigned IVG #x   */
-#define P42_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #42 assigned IVG #x   */
-#define P43_IVG(x)      ((((x)&_MF15)-_MF7) << 0xC)  /* Peripheral #43 assigned IVG #x   */
-#define P44_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #44 assigned IVG #x   */
-#define P45_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #45 assigned IVG #x   */
-#define P46_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #46 assigned IVG #x   */
-#define P47_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #47 assigned IVG #x   */
-
-/* SIC_IAR6 Macros */
-#define P48_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #48 assigned IVG #x   */
-#define P49_IVG(x)      ((((x)&_MF15)-_MF7) << 0x4)  /* Peripheral #49 assigned IVG #x   */
-#define P50_IVG(x)      ((((x)&_MF15)-_MF7) << 0x8)  /* Peripheral #50 assigned IVG #x   */
-#define P51_IVG(x)                                   /* Reserved                         */
-#define P52_IVG(x)      ((((x)&_MF15)-_MF7) << 0x10) /* Peripheral #52 assigned IVG #x   */
-#define P53_IVG(x)      ((((x)&_MF15)-_MF7) << 0x14) /* Peripheral #53 assigned IVG #x   */
-#define P54_IVG(x)      ((((x)&_MF15)-_MF7) << 0x18) /* Peripheral #54 assigned IVG #x   */
-#define P55_IVG(x)      ((((x)&_MF15)-_MF7) << 0x1C) /* Peripheral #55 assigned IVG #x   */
-
-/* SIC_IAR7 Macros */
-#define P56_IVG(x)                                   /* Reserved                         */
-#define P57_IVG(x)                                   /* Reserved                         */
-#define P58_IVG(x)                                   /* Reserved                         */
-#define P59_IVG(x)                                   /* Reserved                         */
-#define P60_IVG(x)                                   /* Reserved                         */
-#define P61_IVG(x)                                   /* Reserved                         */
-#define P62_IVG(x)                                   /* Reserved                         */
-#define P63_IVG(x)                                   /* Reserved                         */
-
-
-/* SIC_IMASK0 Masks*/
-#define SIC_UNMASK0_ALL 0x00000000        /* Unmask all peripheral interrupts */
-#define SIC_MASK0_ALL   0xFFFFF3FF        /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK0(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK0(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK0(x) (1 << ((x)&0x1F))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK0(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASK1 Masks*/
-#define SIC_UNMASK1_ALL 0x00000000        /* Unmask all peripheral interrupts */
-#define SIC_MASK1_ALL   0xFFFFFF          /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK1(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK1(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK1(x) (1 << ((x)&0x1F))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK1(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-
-/* SIC_IWR0 Masks*/
-#define IWR0_DISABLE_ALL 0x00000000       /* Wakeup Disable all peripherals   */
-#define IWR0_ENABLE_ALL  0xFFFFF3FF       /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR0_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR0_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR0_ENABLE(x)   (1 << ((x)&0x1F))  /* Wakeup Enable Peripheral #x   */
-#define IWR0_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR1 Masks*/
-#define IWR1_DISABLE_ALL 0x00000000       /* Wakeup Disable all peripherals   */
-#define IWR1_ENABLE_ALL  0xFFFFFF         /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR1_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR1_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /* Wakeup Disable Peripheral #x*/
-#else
-#define IWR1_ENABLE(x)   (1 << ((x)&0x1F))  /* Wakeup Enable Peripheral #x   */
-#define IWR1_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))/* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#ifdef _MISRA_RULES
-#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
-#else
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define TMR_DIS WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks										*/
-#define	RTC_SEC				0x0000003F	/* Real-Time Clock Seconds	*/
-#define	RTC_MIN				0x00000FC0	/* Real-Time Clock Minutes	*/
-#define	RTC_HR				0x0001F000	/* Real-Time Clock Hours	*/
-#define	RTC_DAY				0xFFFE0000	/* Real-Time Clock Days		*/
-
-/* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* RTC_ICTL and RTC_ISTAT Masks																		*/
-#define	STOPWATCH			0x0001		/* Stopwatch Interrupt Enable								*/
-#define	ALARM				0x0002		/* Alarm Interrupt Enable									*/
-#define	SECOND				0x0004		/* Seconds (1 Hz) Interrupt Enable							*/
-#define	MINUTE				0x0008		/* Minutes Interrupt Enable									*/
-#define	HOUR				0x0010		/* Hours Interrupt Enable									*/
-#define	DAY					0x0020		/* 24 Hours (Days) Interrupt Enable							*/
-#define	DAY_ALARM			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
-#define	WRITE_PENDING		0x4000		/* Write Pending Status										*/
-#define	WRITE_COMPLETE		0x8000		/* Write Complete Interrupt Enable							*/
-
-/* RTC_FAST / RTC_PREN Mask												*/
-#define PREN				0x0001	/* Enable Prescaler, RTC Runs @1 Hz	*/
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks												*/
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select */
-#else
-#define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB			0x04				/* Stop Bits			*/
-#define PEN			0x08				/* Parity Enable		*/
-#define EPS			0x10				/* Even Parity Select	*/
-#define STP			0x20				/* Stick Parity			*/
-#define SB			0x40				/* Set Break			*/
-#define DLAB		0x80				/* Divisor Latch Access	*/
-
-/* UARTx_MCR Mask										*/
-#define LOOP_ENA	0x10	/* Loopback Mode Enable */
-#define LOOP_ENA_P	0x04
-
-/* UARTx_LSR Masks										*/
-#define DR			0x01	/* Data Ready				*/
-#define OE			0x02	/* Overrun Error			*/
-#define PE			0x04	/* Parity Error				*/
-#define FE			0x08	/* Framing Error			*/
-#define BI			0x10	/* Break Interrupt			*/
-#define THRE		0x20	/* THR Empty				*/
-#define TEMT		0x40	/* TSR and UART_THR Empty	*/
-
-/* UARTx_IER Masks															*/
-#define ERBFI		0x01		/* Enable Receive Buffer Full Interrupt		*/
-#define ETBEI		0x02		/* Enable Transmit Buffer Empty Interrupt	*/
-#define ELSI		0x04		/* Enable RX Status Interrupt				*/
-
-/* UARTx_IIR Masks														*/
-#define NINT		0x01		/* Pending Interrupt					*/
-#define STATUS		0x06		/* Highest Priority Pending Interrupt	*/
-
-/* UARTx_GCTL Masks													*/
-#define UCEN		0x01		/* Enable UARTx Clocks				*/
-#define IREN		0x02		/* Enable IrDA Mode					*/
-#define TPOLC		0x04		/* IrDA TX Polarity Change			*/
-#define RPOLC		0x08		/* IrDA RX Polarity Change			*/
-#define FPE			0x10		/* Force Parity Error On Transmit	*/
-#define FFE			0x20		/* Force Framing Error On Transmit	*/
-
-/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
-#define UARTDLL   0x00FF   /* Divisor Latch Low Byte */
-#define UARTDLH   0xFF00   /* Divisor Latch High Byte */
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks																	*/
-#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/
-#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/
-#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/
-#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/
-#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/
-#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/
-#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/
-#define PSSE		0x0010		/* Slave-Select Input Enable						*/
-#define EMISO		0x0020		/* Enable MISO As Output							*/
-#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/
-#define LSBF		0x0200		/* LSB First										*/
-#define CPHA		0x0400		/* Clock Phase										*/
-#define CPOL		0x0800		/* Clock Polarity									*/
-#define MSTR		0x1000		/* Master/Slave*									*/
-#define WOM			0x2000		/* Write Open Drain Master							*/
-#define SPE			0x4000		/* SPI Enable										*/
-
-/* SPI_FLG Masks																	*/
-#define FLS1		0x0002		/* Enables SPI_FLOUT1 as SPI Slave-Select Output	*/
-#define FLS2		0x0004		/* Enables SPI_FLOUT2 as SPI Slave-Select Output	*/
-#define FLS3		0x0008		/* Enables SPI_FLOUT3 as SPI Slave-Select Output	*/
-#define FLS4		0x0010		/* Enables SPI_FLOUT4 as SPI Slave-Select Output	*/
-#define FLS5		0x0020		/* Enables SPI_FLOUT5 as SPI Slave-Select Output	*/
-#define FLS6		0x0040		/* Enables SPI_FLOUT6 as SPI Slave-Select Output	*/
-#define FLS7		0x0080		/* Enables SPI_FLOUT7 as SPI Slave-Select Output	*/
-#define FLG1		0xFDFF		/* Activates SPI_FLOUT1 							*/
-#define FLG2		0xFBFF		/* Activates SPI_FLOUT2								*/
-#define FLG3		0xF7FF		/* Activates SPI_FLOUT3								*/
-#define FLG4		0xEFFF		/* Activates SPI_FLOUT4								*/
-#define FLG5		0xDFFF		/* Activates SPI_FLOUT5								*/
-#define FLG6		0xBFFF		/* Activates SPI_FLOUT6								*/
-#define FLG7		0x7FFF		/* Activates SPI_FLOUT7								*/
-
-/* SPI_STAT Masks																				*/
-#define SPIF		0x0001		/* SPI Finished (Single-Word Transfer Complete)					*/
-#define MODF		0x0002		/* Mode Fault Error (Another Device Tried To Become Master)		*/
-#define TXE			0x0004		/* Transmission Error (Data Sent With No New Data In TDBR)		*/
-#define TXS			0x0008		/* SPI_TDBR Data Buffer Status (Full/Empty*)					*/
-#define RBSY		0x0010		/* Receive Error (Data Received With RDBR Full)					*/
-#define RXS			0x0020		/* SPI_RDBR Data Buffer Status (Full/Empty*)					*/
-#define TXCOL		0x0040		/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks													*/
-#define TIMEN0			0x0001		/* Enable Timer 0					*/
-#define TIMEN1			0x0002		/* Enable Timer 1					*/
-#define TIMEN2			0x0004		/* Enable Timer 2					*/
-#define TIMEN3			0x0008		/* Enable Timer 3					*/
-#define TIMEN4			0x0010		/* Enable Timer 4					*/
-#define TIMEN5			0x0020		/* Enable Timer 5					*/
-#define TIMEN6			0x0040		/* Enable Timer 6					*/
-#define TIMEN7			0x0080		/* Enable Timer 7					*/
-
-/* TIMER_DISABLE Masks													*/
-#define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
-#define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
-#define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
-#define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
-#define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
-#define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
-#define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
-#define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
-
-/* TIMER_STATUS Masks													*/
-#define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
-#define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
-#define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
-#define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
-#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
-#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
-#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
-#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
-#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
-#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
-#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
-#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
-#define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
-#define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
-#define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
-#define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
-#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
-#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
-#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
-#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
-#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
-#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
-#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
-#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks													*/
-#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
-#define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
-#define EXT_CLK			0x0003	/* External Clock Mode					*/
-#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
-#define PERIOD_CNT		0x0008	/* Period Count							*/
-#define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
-#define TIN_SEL			0x0020	/* Timer Input Select					*/
-#define OUT_DIS			0x0040	/* Output Pad Disable					*/
-#define CLK_SEL			0x0080	/* Timer Clock Select					*/
-#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
-#define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
-#define ERR_TYP			0xC000	/* Error Type							*/
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks 				*/
-/* Port F Masks 														*/
-#define PF0		0x0001
-#define PF1		0x0002
-#define PF2		0x0004
-#define PF3		0x0008
-#define PF4		0x0010
-#define PF5		0x0020
-#define PF6		0x0040
-#define PF7		0x0080
-#define PF8		0x0100
-#define PF9		0x0200
-#define PF10	0x0400
-#define PF11	0x0800
-#define PF12	0x1000
-#define PF13	0x2000
-#define PF14	0x4000
-#define PF15	0x8000
-
-/* Port G Masks															*/
-#define PG0		0x0001
-#define PG1		0x0002
-#define PG2		0x0004
-#define PG3		0x0008
-#define PG4		0x0010
-#define PG5		0x0020
-#define PG6		0x0040
-#define PG7		0x0080
-#define PG8		0x0100
-#define PG9		0x0200
-#define PG10	0x0400
-#define PG11	0x0800
-#define PG12	0x1000
-#define PG13	0x2000
-#define PG14	0x4000
-#define PG15	0x8000
-
-/* Port H Masks															*/
-#define PH0		0x0001
-#define PH1		0x0002
-#define PH2		0x0004
-#define PH3		0x0008
-#define PH4		0x0010
-#define PH5		0x0020
-#define PH6		0x0040
-#define PH7		0x0080
-#define PH8		0x0100
-#define PH9		0x0200
-#define PH10	0x0400
-#define PH11	0x0800
-#define PH12	0x1000
-#define PH13	0x2000
-#define PH14	0x4000
-#define PH15	0x8000
-
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks															*/
-#define TSPEN		0x0001		/* Transmit Enable								*/
-#define ITCLK		0x0002		/* Internal Transmit Clock Select				*/
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define TLSBIT		0x0010		/* Transmit Bit Order							*/
-#define ITFS		0x0200		/* Internal Transmit Frame Sync Select			*/
-#define TFSR		0x0400		/* Transmit Frame Sync Required Select			*/
-#define DITFS		0x0800		/* Data-Independent Transmit Frame Sync Select	*/
-#define LTFS		0x1000		/* Low Transmit Frame Sync Select				*/
-#define LATFS		0x2000		/* Late Transmit Frame Sync Select				*/
-#define TCKFE		0x4000		/* Clock Falling Edge Select					*/
-
-/* SPORTx_TCR2 Masks and Macro													*/
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-
-#define TXSE		0x0100		/* TX Secondary Enable							*/
-#define TSFSE		0x0200		/* Transmit Stereo Frame Sync Enable			*/
-#define TRFST		0x0400		/* Left/Right Order (1 = Right Channel 1st)		*/
-
-/* SPORTx_RCR1 Masks															*/
-#define RSPEN		0x0001		/* Receive Enable 								*/
-#define IRCLK		0x0002		/* Internal Receive Clock Select 				*/
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define RLSBIT		0x0010		/* Receive Bit Order							*/
-#define IRFS		0x0200		/* Internal Receive Frame Sync Select 			*/
-#define RFSR		0x0400		/* Receive Frame Sync Required Select 			*/
-#define LRFS		0x1000		/* Low Receive Frame Sync Select 				*/
-#define LARFS		0x2000		/* Late Receive Frame Sync Select 				*/
-#define RCKFE		0x4000		/* Clock Falling Edge Select 					*/
-
-/* SPORTx_RCR2 Masks															*/
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT RX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#define RXSE		0x0100		/* RX Secondary Enable							*/
-#define RSFSE		0x0200		/* RX Stereo Frame Sync Enable					*/
-#define RRFST		0x0400		/* Right-First Data Order 						*/
-
-/* SPORTx_STAT Masks															*/
-#define RXNE		0x0001		/* Receive FIFO Not Empty Status				*/
-#define RUVF		0x0002		/* Sticky Receive Underflow Status				*/
-#define ROVF		0x0004		/* Sticky Receive Overflow Status				*/
-#define TXF			0x0008		/* Transmit FIFO Full Status					*/
-#define TUVF		0x0010		/* Sticky Transmit Underflow Status				*/
-#define TOVF		0x0020		/* Sticky Transmit Overflow Status				*/
-#define TXHRE		0x0040		/* Transmit Hold Register Empty					*/
-
-/* SPORTx_MCMC1 Macros															*/
-#ifdef _MISRA_RULES
-#define WOFF(x)		((x) & 0x3FFu) 	/* Multichannel Window Offset Field			*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define WSIZE(x)	(((((x)>>0x3)-1u)&0xFu) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-
-#else
-#define WOFF(x)		((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-
-#endif /* _MISRA_RULES */
-
-/* SPORTx_MCMC2 Masks															*/
-#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/
-#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/
-#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/
-#define MCDTXPE		0x0004 		/* Multichannel DMA Transmit Packing			*/
-#define MCDRXPE		0x0008 		/* Multichannel DMA Receive Packing				*/
-#define MCMEN		0x0010 		/* Multichannel Frame Mode Enable				*/
-#define FSDR		0x0080 		/* Multichannel Frame Sync to Data Relationship	*/
-#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/
-#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/
-#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/
-#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/
-#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/
-#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/
-#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/
-#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/
-#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/
-#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/
-#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/
-#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/
-#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/
-#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/
-#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/
-#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks																	*/
-#define AMCKEN			0x0001		/* Enable CLKOUT									*/
-#define AMBEN           0x000e      /* Async bank enable                                */
-#define	AMBEN_NONE		0x0000		/* All Banks Disabled								*/
-#define AMBEN_B0		0x0002		/* Enable Async Memory Bank 0 only					*/
-#define AMBEN_B0_B1		0x0004		/* Enable Async Memory Banks 0 & 1 only				*/
-#define AMBEN_B0_B1_B2	0x0006		/* Enable Async Memory Banks 0, 1, and 2			*/
-#define AMBEN_ALL		0x0008		/* Enable Async Memory Banks (all) 0, 1, 2, and 3	*/
-#define CDPRIO                  0x0100        /* DMA has priority over core for for external accesses */
-
-/* EBIU_AMBCTL0 Masks																	*/
-#define B0RDYEN			0x00000001  /* Bank 0 (B0) RDY Enable							*/
-#define B0RDYPOL		0x00000002  /* B0 RDY Active High								*/
-#define B0TT_1			0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle		*/
-#define B0TT_2			0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles	*/
-#define B0TT_3			0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles	*/
-#define B0TT_4			0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles	*/
-#define B0ST_1			0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B0ST_2			0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B0ST_3			0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B0ST_4			0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B0HT_1			0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B0HT_2			0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B0HT_3			0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B0HT_0			0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B0RAT_1			0x00000100  /* B0 Read Access Time = 1 cycle					*/
-#define B0RAT_2			0x00000200  /* B0 Read Access Time = 2 cycles					*/
-#define B0RAT_3			0x00000300  /* B0 Read Access Time = 3 cycles					*/
-#define B0RAT_4			0x00000400  /* B0 Read Access Time = 4 cycles					*/
-#define B0RAT_5			0x00000500  /* B0 Read Access Time = 5 cycles					*/
-#define B0RAT_6			0x00000600  /* B0 Read Access Time = 6 cycles					*/
-#define B0RAT_7			0x00000700  /* B0 Read Access Time = 7 cycles					*/
-#define B0RAT_8			0x00000800  /* B0 Read Access Time = 8 cycles					*/
-#define B0RAT_9			0x00000900  /* B0 Read Access Time = 9 cycles					*/
-#define B0RAT_10		0x00000A00  /* B0 Read Access Time = 10 cycles					*/
-#define B0RAT_11		0x00000B00  /* B0 Read Access Time = 11 cycles					*/
-#define B0RAT_12		0x00000C00  /* B0 Read Access Time = 12 cycles					*/
-#define B0RAT_13		0x00000D00  /* B0 Read Access Time = 13 cycles					*/
-#define B0RAT_14		0x00000E00  /* B0 Read Access Time = 14 cycles					*/
-#define B0RAT_15		0x00000F00  /* B0 Read Access Time = 15 cycles					*/
-#define B0WAT_1			0x00001000  /* B0 Write Access Time = 1 cycle					*/
-#define B0WAT_2			0x00002000  /* B0 Write Access Time = 2 cycles					*/
-#define B0WAT_3			0x00003000  /* B0 Write Access Time = 3 cycles					*/
-#define B0WAT_4			0x00004000  /* B0 Write Access Time = 4 cycles					*/
-#define B0WAT_5			0x00005000  /* B0 Write Access Time = 5 cycles					*/
-#define B0WAT_6			0x00006000  /* B0 Write Access Time = 6 cycles					*/
-#define B0WAT_7			0x00007000  /* B0 Write Access Time = 7 cycles					*/
-#define B0WAT_8			0x00008000  /* B0 Write Access Time = 8 cycles					*/
-#define B0WAT_9			0x00009000  /* B0 Write Access Time = 9 cycles					*/
-#define B0WAT_10		0x0000A000  /* B0 Write Access Time = 10 cycles					*/
-#define B0WAT_11		0x0000B000  /* B0 Write Access Time = 11 cycles					*/
-#define B0WAT_12		0x0000C000  /* B0 Write Access Time = 12 cycles					*/
-#define B0WAT_13		0x0000D000  /* B0 Write Access Time = 13 cycles					*/
-#define B0WAT_14		0x0000E000  /* B0 Write Access Time = 14 cycles					*/
-#define B0WAT_15		0x0000F000  /* B0 Write Access Time = 15 cycles					*/
-
-#define B1RDYEN			0x00010000  /* Bank 1 (B1) RDY Enable                       	*/
-#define B1RDYPOL		0x00020000  /* B1 RDY Active High                           	*/
-#define B1TT_1			0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle 	*/
-#define B1TT_2			0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles	*/
-#define B1TT_3			0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles	*/
-#define B1TT_4			0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles	*/
-#define B1ST_1			0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle  	*/
-#define B1ST_2			0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles 	*/
-#define B1ST_3			0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles 	*/
-#define B1ST_4			0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles 	*/
-#define B1HT_1			0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle 	*/
-#define B1HT_2			0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B1HT_3			0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B1HT_0			0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B1RAT_1			0x01000000  /* B1 Read Access Time = 1 cycle					*/
-#define B1RAT_2			0x02000000  /* B1 Read Access Time = 2 cycles					*/
-#define B1RAT_3			0x03000000  /* B1 Read Access Time = 3 cycles					*/
-#define B1RAT_4			0x04000000  /* B1 Read Access Time = 4 cycles					*/
-#define B1RAT_5			0x05000000  /* B1 Read Access Time = 5 cycles					*/
-#define B1RAT_6			0x06000000  /* B1 Read Access Time = 6 cycles					*/
-#define B1RAT_7			0x07000000  /* B1 Read Access Time = 7 cycles					*/
-#define B1RAT_8			0x08000000  /* B1 Read Access Time = 8 cycles					*/
-#define B1RAT_9			0x09000000  /* B1 Read Access Time = 9 cycles					*/
-#define B1RAT_10		0x0A000000  /* B1 Read Access Time = 10 cycles					*/
-#define B1RAT_11		0x0B000000  /* B1 Read Access Time = 11 cycles					*/
-#define B1RAT_12		0x0C000000  /* B1 Read Access Time = 12 cycles					*/
-#define B1RAT_13		0x0D000000  /* B1 Read Access Time = 13 cycles					*/
-#define B1RAT_14		0x0E000000  /* B1 Read Access Time = 14 cycles					*/
-#define B1RAT_15		0x0F000000  /* B1 Read Access Time = 15 cycles					*/
-#define B1WAT_1			0x10000000  /* B1 Write Access Time = 1 cycle					*/
-#define B1WAT_2			0x20000000  /* B1 Write Access Time = 2 cycles					*/
-#define B1WAT_3			0x30000000  /* B1 Write Access Time = 3 cycles					*/
-#define B1WAT_4			0x40000000  /* B1 Write Access Time = 4 cycles					*/
-#define B1WAT_5			0x50000000  /* B1 Write Access Time = 5 cycles					*/
-#define B1WAT_6			0x60000000  /* B1 Write Access Time = 6 cycles					*/
-#define B1WAT_7			0x70000000  /* B1 Write Access Time = 7 cycles					*/
-#define B1WAT_8			0x80000000  /* B1 Write Access Time = 8 cycles					*/
-#define B1WAT_9			0x90000000  /* B1 Write Access Time = 9 cycles					*/
-#define B1WAT_10		0xA0000000  /* B1 Write Access Time = 10 cycles					*/
-#define B1WAT_11		0xB0000000  /* B1 Write Access Time = 11 cycles					*/
-#define B1WAT_12		0xC0000000  /* B1 Write Access Time = 12 cycles					*/
-#define B1WAT_13		0xD0000000  /* B1 Write Access Time = 13 cycles					*/
-#define B1WAT_14		0xE0000000  /* B1 Write Access Time = 14 cycles					*/
-#define B1WAT_15		0xF0000000  /* B1 Write Access Time = 15 cycles					*/
-
-/* EBIU_AMBCTL1 Masks																	*/
-#define B2RDYEN			0x00000001  /* Bank 2 (B2) RDY Enable							*/
-#define B2RDYPOL		0x00000002  /* B2 RDY Active High								*/
-#define B2TT_1			0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle		*/
-#define B2TT_2			0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles	*/
-#define B2TT_3			0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles	*/
-#define B2TT_4			0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles	*/
-#define B2ST_1			0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B2ST_2			0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B2ST_3			0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B2ST_4			0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B2HT_1			0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B2HT_2			0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B2HT_3			0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B2HT_0			0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B2RAT_1			0x00000100  /* B2 Read Access Time = 1 cycle					*/
-#define B2RAT_2			0x00000200  /* B2 Read Access Time = 2 cycles					*/
-#define B2RAT_3			0x00000300  /* B2 Read Access Time = 3 cycles					*/
-#define B2RAT_4			0x00000400  /* B2 Read Access Time = 4 cycles					*/
-#define B2RAT_5			0x00000500  /* B2 Read Access Time = 5 cycles					*/
-#define B2RAT_6			0x00000600  /* B2 Read Access Time = 6 cycles					*/
-#define B2RAT_7			0x00000700  /* B2 Read Access Time = 7 cycles					*/
-#define B2RAT_8			0x00000800  /* B2 Read Access Time = 8 cycles					*/
-#define B2RAT_9			0x00000900  /* B2 Read Access Time = 9 cycles					*/
-#define B2RAT_10		0x00000A00  /* B2 Read Access Time = 10 cycles					*/
-#define B2RAT_11		0x00000B00  /* B2 Read Access Time = 11 cycles					*/
-#define B2RAT_12		0x00000C00  /* B2 Read Access Time = 12 cycles					*/
-#define B2RAT_13		0x00000D00  /* B2 Read Access Time = 13 cycles					*/
-#define B2RAT_14		0x00000E00  /* B2 Read Access Time = 14 cycles					*/
-#define B2RAT_15		0x00000F00  /* B2 Read Access Time = 15 cycles					*/
-#define B2WAT_1			0x00001000  /* B2 Write Access Time = 1 cycle					*/
-#define B2WAT_2			0x00002000  /* B2 Write Access Time = 2 cycles					*/
-#define B2WAT_3			0x00003000  /* B2 Write Access Time = 3 cycles					*/
-#define B2WAT_4			0x00004000  /* B2 Write Access Time = 4 cycles					*/
-#define B2WAT_5			0x00005000  /* B2 Write Access Time = 5 cycles					*/
-#define B2WAT_6			0x00006000  /* B2 Write Access Time = 6 cycles					*/
-#define B2WAT_7			0x00007000  /* B2 Write Access Time = 7 cycles					*/
-#define B2WAT_8			0x00008000  /* B2 Write Access Time = 8 cycles					*/
-#define B2WAT_9			0x00009000  /* B2 Write Access Time = 9 cycles					*/
-#define B2WAT_10		0x0000A000  /* B2 Write Access Time = 10 cycles					*/
-#define B2WAT_11		0x0000B000  /* B2 Write Access Time = 11 cycles					*/
-#define B2WAT_12		0x0000C000  /* B2 Write Access Time = 12 cycles					*/
-#define B2WAT_13		0x0000D000  /* B2 Write Access Time = 13 cycles					*/
-#define B2WAT_14		0x0000E000  /* B2 Write Access Time = 14 cycles					*/
-#define B2WAT_15		0x0000F000  /* B2 Write Access Time = 15 cycles					*/
-
-#define B3RDYEN			0x00010000  /* Bank 3 (B3) RDY Enable							*/
-#define B3RDYPOL		0x00020000  /* B3 RDY Active High								*/
-#define B3TT_1			0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle		*/
-#define B3TT_2			0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles	*/
-#define B3TT_3			0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles	*/
-#define B3TT_4			0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles	*/
-#define B3ST_1			0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B3ST_2			0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B3ST_3			0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B3ST_4			0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B3HT_1			0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B3HT_2			0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B3HT_3			0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B3HT_0			0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B3RAT_1			0x01000000  /* B3 Read Access Time = 1 cycle					*/
-#define B3RAT_2			0x02000000  /* B3 Read Access Time = 2 cycles					*/
-#define B3RAT_3			0x03000000  /* B3 Read Access Time = 3 cycles					*/
-#define B3RAT_4			0x04000000  /* B3 Read Access Time = 4 cycles					*/
-#define B3RAT_5			0x05000000  /* B3 Read Access Time = 5 cycles					*/
-#define B3RAT_6			0x06000000  /* B3 Read Access Time = 6 cycles					*/
-#define B3RAT_7			0x07000000  /* B3 Read Access Time = 7 cycles					*/
-#define B3RAT_8			0x08000000  /* B3 Read Access Time = 8 cycles					*/
-#define B3RAT_9			0x09000000  /* B3 Read Access Time = 9 cycles					*/
-#define B3RAT_10		0x0A000000  /* B3 Read Access Time = 10 cycles					*/
-#define B3RAT_11		0x0B000000  /* B3 Read Access Time = 11 cycles					*/
-#define B3RAT_12		0x0C000000  /* B3 Read Access Time = 12 cycles					*/
-#define B3RAT_13		0x0D000000  /* B3 Read Access Time = 13 cycles					*/
-#define B3RAT_14		0x0E000000  /* B3 Read Access Time = 14 cycles					*/
-#define B3RAT_15		0x0F000000  /* B3 Read Access Time = 15 cycles					*/
-#define B3WAT_1			0x10000000  /* B3 Write Access Time = 1 cycle					*/
-#define B3WAT_2			0x20000000  /* B3 Write Access Time = 2 cycles					*/
-#define B3WAT_3			0x30000000  /* B3 Write Access Time = 3 cycles					*/
-#define B3WAT_4			0x40000000  /* B3 Write Access Time = 4 cycles					*/
-#define B3WAT_5			0x50000000  /* B3 Write Access Time = 5 cycles					*/
-#define B3WAT_6			0x60000000  /* B3 Write Access Time = 6 cycles					*/
-#define B3WAT_7			0x70000000  /* B3 Write Access Time = 7 cycles					*/
-#define B3WAT_8			0x80000000  /* B3 Write Access Time = 8 cycles					*/
-#define B3WAT_9			0x90000000  /* B3 Write Access Time = 9 cycles					*/
-#define B3WAT_10		0xA0000000  /* B3 Write Access Time = 10 cycles					*/
-#define B3WAT_11		0xB0000000  /* B3 Write Access Time = 11 cycles					*/
-#define B3WAT_12		0xC0000000  /* B3 Write Access Time = 12 cycles					*/
-#define B3WAT_13		0xD0000000  /* B3 Write Access Time = 13 cycles					*/
-#define B3WAT_14		0xE0000000  /* B3 Write Access Time = 14 cycles					*/
-#define B3WAT_15		0xF0000000  /* B3 Write Access Time = 15 cycles					*/
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks																			*/
-#define SCTLE			0x00000001	/* Enable SDRAM Signals										*/
-#define CL_2			0x00000008	/* SDRAM CAS Latency = 2 cycles								*/
-#define CL_3			0x0000000C	/* SDRAM CAS Latency = 3 cycles								*/
-/* EBIU_SDGCTL Masks */
-#define CL           0x0000000C  /* SDRAM CAS latency */
-#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
-#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh		*/
-#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
-#define PASR         0x00000030  /* SDRAM partial array self-refresh */
-#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle										*/
-#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles									*/
-#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles									*/
-#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles									*/
-#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles									*/
-#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles									*/
-#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles									*/
-#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles									*/
-#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles									*/
-#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles									*/
-#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles									*/
-#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles									*/
-#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles									*/
-#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles									*/
-#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles									*/
-#define TRAS         0x000003C0  /* SDRAM tRAS in SCLK cycles */
-#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle										*/
-#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles										*/
-#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles										*/
-#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles										*/
-#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles										*/
-#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles										*/
-#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles										*/
-#define TRP          0x00003800  /* SDRAM tRP in SCLK cycles */
-#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle										*/
-#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles									*/
-#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles									*/
-#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles									*/
-#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles									*/
-#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles									*/
-#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles									*/
-#define TRCD         0x00030000  /* SDRAM tRCD in SCLK cycles */
-#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle										*/
-#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles										*/
-#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles										*/
-#define TWR          0x00180000  /* SDRAM tWR in SCLK cycles */
-#define PUPSD			0x00200000	/* Power-Up Start Delay (15 SCLK Cycles Delay)				*/
-#define PSM				0x00400000	/* Power-Up Sequence (Mode Register Before/After* Refresh)	*/
-#define PSS				0x00800000	/* Enable Power-Up Sequence on Next SDRAM Access			*/
-#define SRFS			0x01000000	/* Enable SDRAM Self-Refresh Mode							*/
-#define EBUFE			0x02000000	/* Enable External Buffering Timing							*/
-#define FBBRW			0x04000000	/* Enable Fast Back-To-Back Read To Write					*/
-#define EMREN			0x10000000	/* Extended Mode Register Enable							*/
-#define TCSR			0x20000000	/* Temp-Compensated Self-Refresh Value (85/45* Deg C)		*/
-#define CDDBG			0x40000000	/* Tristate SDRAM Controls During Bus Grant					*/
-
-/* EBIU_SDBCTL Masks																		*/
-#define EBE				0x0001		/* Enable SDRAM External Bank							*/
-#define EBSZ_16			0x0000		/* SDRAM External Bank Size = 16MB	*/
-#define EBSZ_32			0x0002		/* SDRAM External Bank Size = 32MB	*/
-#define EBSZ_64			0x0004		/* SDRAM External Bank Size = 64MB	*/
-#define EBSZ_128		0x0006		/* SDRAM External Bank Size = 128MB		*/
-#define EBSZ         0x0006       /* SDRAM external bank size */
-#define EBCAW_8			0x0000		/* SDRAM External Bank Column Address Width = 8 Bits	*/
-#define EBCAW_9			0x0010		/* SDRAM External Bank Column Address Width = 9 Bits	*/
-#define EBCAW_10		0x0020		/* SDRAM External Bank Column Address Width = 10 Bits	*/
-#define EBCAW_11		0x0030		/* SDRAM External Bank Column Address Width = 11 Bits	*/
-#define EBCAW        0x0030      /* SDRAM external bank column address width */
-
-/* EBIU_SDSTAT Masks														*/
-#define SDCI			0x0001		/* SDRAM Controller Idle 				*/
-#define SDSRA			0x0002		/* SDRAM Self-Refresh Active			*/
-#define SDPUA			0x0004		/* SDRAM Power-Up Active 				*/
-#define SDRS			0x0008		/* SDRAM Will Power-Up On Next Access	*/
-#define SDEASE			0x0010		/* SDRAM EAB Sticky Error Status		*/
-#define BGSTAT			0x0020		/* Bus Grant Status						*/
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
-#define DMAEN			0x0001		/* DMA Channel Enable							*/
-#define WNR				0x0002		/* Channel Direction (W/R*)						*/
-#define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
-#define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
-#define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
-#define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
-#define SYNC			0x0020		/* DMA Buffer Clear								*/
-#define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
-#define DI_EN			0x0080		/* Data Interrupt Enable						*/
-#define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
-#define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
-#define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
-#define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
-#define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
-#define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
-#define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
-#define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
-#define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
-#define FLOW_STOP		0x0000		/* Stop Mode									*/
-#define FLOW_AUTO		0x1000		/* Autobuffer Mode								*/
-#define FLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
-#define FLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
-#define FLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
-#define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
-#define PMAP			0xF000	/* Peripheral Mapped To This Channel				*/
-#define PMAP_PPI		0x0000	/* 		PPI Port DMA								*/
-#define	PMAP_EMACRX		0x1000	/* 		Ethernet Receive DMA						*/
-#define PMAP_EMACTX		0x2000	/* 		Ethernet Transmit DMA						*/
-#define PMAP_SPORT0RX	0x3000	/* 		SPORT0 Receive DMA							*/
-#define PMAP_SPORT0TX	0x4000	/* 		SPORT0 Transmit DMA							*/
-#define PMAP_SPORT1RX	0x5000	/* 		SPORT1 Receive DMA							*/
-#define PMAP_SPORT1TX	0x6000	/* 		SPORT1 Transmit DMA							*/
-#define PMAP_SPI		0x7000	/* 		SPI Port DMA								*/
-#define PMAP_UART0RX	0x8000	/* 		UART0 Port Receive DMA						*/
-#define PMAP_UART0TX	0x9000	/* 		UART0 Port Transmit DMA						*/
-#define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
-#define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
-
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks													*/
-#define PORT_EN			0x0001		/* PPI Port Enable					*/
-#define PORT_DIR		0x0002		/* PPI Port Direction				*/
-#define XFR_TYPE		0x000C		/* PPI Transfer Type				*/
-#define PORT_CFG		0x0030		/* PPI Port Configuration			*/
-#define FLD_SEL			0x0040		/* PPI Active Field Select			*/
-#define PACK_EN			0x0080		/* PPI Packing Mode					*/
-/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN			0x0200		/* PPI Skip Element Enable			*/
-#define SKIP_EO			0x0400		/* PPI Skip Even/Odd Elements		*/
-#define DLEN_8			0x0000		/* Data Length = 8 Bits				*/
-#define DLEN_10			0x0800		/* Data Length = 10 Bits			*/
-#define DLEN_11			0x1000		/* Data Length = 11 Bits			*/
-#define DLEN_12			0x1800		/* Data Length = 12 Bits			*/
-#define DLEN_13			0x2000		/* Data Length = 13 Bits			*/
-#define DLEN_14			0x2800		/* Data Length = 14 Bits			*/
-#define DLEN_15			0x3000		/* Data Length = 15 Bits			*/
-#define DLEN_16			0x3800		/* Data Length = 16 Bits			*/
-#define POLC			0x4000		/* PPI Clock Polarity				*/
-#define POLS			0x8000		/* PPI Frame Sync Polarity			*/
-
-/* PPI_STATUS Masks														*/
-#define LT_ERR_OVR	0x0100		/* Line Track Overflow Error	*/
-#define LT_ERR_UNDR	0x0200		/* Line Track Underflow Error	*/
-#define FLD				0x0400		/* Field Indicator					*/
-#define FT_ERR			0x0800		/* Frame Track Error				*/
-#define OVR				0x1000		/* FIFO Overflow Error				*/
-#define UNDR			0x2000		/* FIFO Underrun Error				*/
-#define ERR_DET			0x4000		/* Error Detected Indicator			*/
-#define ERR_NCOR		0x8000		/* Error Not Corrected Indicator	*/
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#ifdef _MISRA_RULES
-#define	CLKLOW(x)	((x) & 0xFFu)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFFu)<<0x8)	/* Periods Before New Clock Low			*/
-#else
-#define	CLKLOW(x)	((x) & 0xFF)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low			*/
-#endif /* _MISRA_RULES */
-
-/* TWI_PRESCALE Masks															*/
-#define	PRESCALE	0x007F		/* SCLKs Per Internal Time Reference (10MHz)	*/
-#define	TWI_ENA		0x0080		/* TWI Enable									*/
-#define	SCCB		0x0200		/* SCCB Compatibility Enable					*/
-
-/* TWI_SLAVE_CTRL Masks															*/
-#define	SEN			0x0001		/* Slave Enable									*/
-#define	SADD_LEN	0x0002		/* Slave Address Length							*/
-#define	STDVAL		0x0004		/* Slave Transmit Data Valid					*/
-#define	NAK			0x0008		/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010		/* General Call Adrress Matching Enabled		*/
-
-/* TWI_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001		/* Slave Transfer Direction (Transmit/Receive*)	*/
-#define GCALL		0x0002		/* General Call Indicator						*/
-
-/* TWI_MASTER_CTRL Masks													*/
-#define	MEN			0x0001		/* Master Mode Enable						*/
-#define	MADD_LEN	0x0002		/* Master Address Length					*/
-#define	MDIR		0x0004		/* Master Transmit Direction (RX/TX*)		*/
-#define	FAST		0x0008		/* Use Fast Mode Timing Specs				*/
-#define	STOP		0x0010		/* Issue Stop Condition						*/
-#define	RSTART		0x0020		/* Repeat Start or Stop* At End Of Transfer	*/
-#define	DCNT		0x3FC0		/* Data Bytes To Transfer					*/
-#define	SDAOVR		0x4000		/* Serial Data Override						*/
-#define	SCLOVR		0x8000		/* Serial Clock Override					*/
-
-/* TWI_MASTER_STAT Masks														*/
-#define	MPROG		0x0001		/* Master Transfer In Progress					*/
-#define	LOSTARB		0x0002		/* Lost Arbitration Indicator (Xfer Aborted)	*/
-#define	ANAK		0x0004		/* Address Not Acknowledged						*/
-#define	DNAK		0x0008		/* Data Not Acknowledged						*/
-#define	BUFRDERR	0x0010		/* Buffer Read Error							*/
-#define	BUFWRERR	0x0020		/* Buffer Write Error							*/
-#define	SDASEN		0x0040		/* Serial Data Sense							*/
-#define	SCLSEN		0x0080		/* Serial Clock Sense							*/
-#define	BUSBUSY		0x0100		/* Bus Busy Indicator							*/
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks						*/
-#define	SINIT		0x0001		/* Slave Transfer Initiated	*/
-#define	SCOMP		0x0002		/* Slave Transfer Complete	*/
-#define	SERR		0x0004		/* Slave Transfer Error		*/
-#define	SOVF		0x0008		/* Slave Overflow			*/
-#define	MCOMP		0x0010		/* Master Transfer Complete	*/
-#define	MERR		0x0020		/* Master Transfer Error	*/
-#define	XMTSERV		0x0040		/* Transmit FIFO Service	*/
-#define	RCVSERV		0x0080		/* Receive FIFO Service		*/
-
-/* TWI_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001		/* Transmit Buffer Flush			*/
-#define	RCVFLUSH	0x0002		/* Receive Buffer Flush				*/
-#define	XMTINTLEN	0x0004		/* Transmit Buffer Interrupt Length	*/
-#define	RCVINTLEN	0x0008		/* Receive Buffer Interrupt Length	*/
-
-/* TWI_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003		/* Transmit FIFO Status							*/
-#define	XMT_EMPTY	0x0000		/* 		Transmit FIFO Empty						*/
-#define	XMT_HALF	0x0001		/* 		Transmit FIFO Has 1 Byte To Write		*/
-#define	XMT_FULL	0x0003		/* 		Transmit FIFO Full (2 Bytes To Write)	*/
-
-#define	RCVSTAT		0x000C		/* Receive FIFO Status							*/
-#define	RCV_EMPTY	0x0000		/* 		Receive FIFO Empty						*/
-#define	RCV_HALF	0x0004		/* 		Receive FIFO Has 1 Byte To Read			*/
-#define	RCV_FULL	0x000C		/* 		Receive FIFO Full (2 Bytes To Read)		*/
-
-
-/* Omit CAN masks from defBF534.h */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX deleted in VisualDSP++ 5.0 Update 3 */
-
-
-/*  ******************  HANDSHAKE DMA (HMDMA) MASKS  *********************/
-/* HMDMAx_CTL Masks														*/
-#define	HMDMAEN		0x0001	/* Enable Handshake DMA 0/1					*/
-#define	REP			0x0002	/* HMDMA Request Polarity					*/
-#define	UTE			0x0004	/* Urgency Threshold Enable					*/
-#define	OIE			0x0010	/* Overflow Interrupt Enable				*/
-#define	BDIE		0x0020	/* Block Done Interrupt Enable				*/
-#define	MBDI		0x0040	/* Mask Block Done IRQ If Pending ECNT		*/
-#define	DRQ			0x0300	/* HMDMA Request Type						*/
-#define	DRQ_NONE	0x0000	/* 		No Request							*/
-#define	DRQ_SINGLE	0x0100	/* 		Channels Request Single				*/
-#define	DRQ_MULTI	0x0200	/* 		Channels Request Multi (Default)	*/
-#define	DRQ_URGENT	0x0300	/* 		Channels Request Multi Urgent		*/
-#define	RBC			0x1000	/* Reload BCNT With IBCNT					*/
-#define	PS			0x2000	/* HMDMA Pin Status							*/
-#define	OI			0x4000	/* Overflow Interrupt Generated				*/
-#define	BDI			0x8000	/* Block Done Interrupt Generated			*/
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define	CKELOW		SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-#define               HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0
-#define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0
-#define               MASK_WBEDGE  0x4        /* Mask Write Buffer Edge Detect */
-#define              nMASK_WBEDGE  0x0
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0
-#define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF52X_H */
diff --git a/libgloss/bfin/include/defBF531.h b/libgloss/bfin/include/defBF531.h
deleted file mode 100644
index 9e490565c..000000000
--- a/libgloss/bfin/include/defBF531.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defBF531.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _DEFBF531_H
-#define _DEFBF531_H
-
-#include <defBF532.h>
-
-#endif /* _DEFBF531_H */
diff --git a/libgloss/bfin/include/defBF532.h b/libgloss/bfin/include/defBF532.h
deleted file mode 100644
index 64669beee..000000000
--- a/libgloss/bfin/include/defBF532.h
+++ /dev/null
@@ -1,1462 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defBF532.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-#if !defined(__ADSPLPBLACKFIN__)
-#warning defBF532.h should only be included for 532 compatible chips
-#endif
-/* include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/*// Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL			0xFFC00000  /* PLL Control register (16-bit) */
-#define PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
-#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT		0xFFC0000C  /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT		0xFFC00010  /* PLL Lock Count register (16-bit) */
-#define	CHIPID			0xFFC00014	/* Chip ID Register						*/
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST			0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR			0xFFC00104  /* System Configuration registe */
-#define SIC_IMASK		0xFFC0010C  /* Interrupt Mask Register */
-#define SIC_IAR0		0xFFC00110  /* Interrupt Assignment Register 0 */
-#define SIC_IAR1		0xFFC00114  /* Interrupt Assignment Register 1 */
-#define SIC_IAR2		0xFFC00118  /* Interrupt Assignment Register 2 */
-#define SIC_ISR			0xFFC00120  /* Interrupt Status Register */
-#define SIC_IWR			0xFFC00124  /* Interrupt Wakeup Register */
-
-
-/*// Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
-#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
-#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
-
-
-/*// Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT        0xFFC00300  /* RTC Status Register */
-#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
-#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
-#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
-#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
-#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
-#define RTC_PREN		0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR             0xFFC00400  /* Transmit Holding register */
-#define UART_RBR             0xFFC00400  /* Receive Buffer register */
-#define UART_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART_IER             0xFFC00404  /* Interrupt Enable Register */
-#define UART_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART_IIR             0xFFC00408  /* Interrupt Identification Register */
-#define UART_LCR             0xFFC0040C  /* Line Control Register */
-#define UART_MCR			 0xFFC00410  /* Modem Control Register */
-#define UART_LSR             0xFFC00414  /* Line Status Register */
-#define UART_SCR             0xFFC0041C  /* SCR Scratch Register */
-#define UART_GCTL      	     0xFFC00424  /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI_CTL               		0xFFC00500  /* SPI Control Register */
-#define SPI_FLG               		0xFFC00504  /* SPI Flag register */
-#define SPI_STAT              		0xFFC00508  /* SPI Status register */
-#define SPI_TDBR              		0xFFC0050C  /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR              		0xFFC00510  /* SPI Receive Data Buffer Register */
-#define SPI_BAUD              		0xFFC00514  /* SPI Baud rate Register */
-#define SPI_SHADOW            		0xFFC00518  /* SPI_RDBR Shadow Register */
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG          		0xFFC00600     /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER				0xFFC00604     /* Timer 0 Counter Register */
-#define TIMER0_PERIOD       		0xFFC00608     /* Timer 0 Period Register */
-#define TIMER0_WIDTH        		0xFFC0060C     /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG          		0xFFC00610  	/*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER         		0xFFC00614   	/*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD          		0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH           		0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG          		0xFFC00620  	/* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER         		0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD          		0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH           		0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE				0xFFC00640   	/* Timer Enable Register */
-#define TIMER_DISABLE				0xFFC00644   	/* Timer Disable Register */
-#define TIMER_STATUS				0xFFC00648   	/* Timer Status Register */
-
-
-/*// General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D	       			0xFFC00700  /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C             		0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S             		0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T					0xFFC0070C  /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D            		0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C            		0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S            		0xFFC00718  /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T            		0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D            		0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C            		0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S            		0xFFC00728  /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T            		0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                		0xFFC00730  /* Peripheral Flag Direction Register */
-#define FIO_POLAR              		0xFFC00734  /* Flag Source Polarity Register */
-#define FIO_EDGE               		0xFFC00738  /* Flag Source Sensitivity Register */
-#define FIO_BOTH               		0xFFC0073C  /* Flag Set on BOTH Edges Register */
-#define FIO_INEN					0xFFC00740  /* Flag Input Enable Register  */
-
-
-/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1     	 		0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2      	 		0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV        		0xFFC00808  /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV          		0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX	             	0xFFC00810  /* SPORT0 TX Data Register */
-#define SPORT0_RX	            	0xFFC00818  /* SPORT0 RX Data Register */
-#define SPORT0_RCR1      	 		0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2      	 		0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV        		0xFFC00828  /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV          		0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT            		0xFFC00830  /* SPORT0 Status Register */
-#define SPORT0_CHNL            		0xFFC00834  /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1           		0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2           		0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0           		0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1           		0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2           		0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3           		0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0           		0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1           		0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2           		0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3           		0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1     	 		0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2      	 		0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV        		0xFFC00908  /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV          		0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX	             	0xFFC00910  /* SPORT1 TX Data Register */
-#define SPORT1_RX	            	0xFFC00918  /* SPORT1 RX Data Register */
-#define SPORT1_RCR1      	 		0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2      	 		0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV        		0xFFC00928  /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV          		0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT            		0xFFC00930  /* SPORT1 Status Register */
-#define SPORT1_CHNL            		0xFFC00934  /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1           		0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2           		0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0           		0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1           		0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2           		0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3           		0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0           		0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1           		0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2           		0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3           		0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller  */
-#define EBIU_AMGCTL			0xFFC00A00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0		0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1		0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL			0xFFC00A10  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL			0xFFC00A14  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 			0xFFC00A18  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT			0xFFC00A1C  /* SDRAM Status Register */
-
-
-/* DMA Traffic controls */
-#define DMA_TC_PER 			0xFFC00B0C	/* Traffic Control Periods Register */
-#define DMA_TC_CNT 			0xFFC00B10	/* Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER 			0xFFC00B0C	/* Traffic Control Periods Register */
-#define DMA_TCCNT 			0xFFC00B10	/* Traffic Control Current Counts Register */
-
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG			0xFFC00C08	/* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG			0xFFC00C48	/* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR		0xFFC00C44	/* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT		0xFFC00C50	/* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT		0xFFC00C58	/* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY		0xFFC00C54	/* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY		0xFFC00C5C	/* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR	0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR		0xFFC00C64	/* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT	0xFFC00C70	/* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT	0xFFC00C78	/* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS		0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP	0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG			0xFFC00C88	/* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR	0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR		0xFFC00C84	/* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT		0xFFC00C90	/* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT		0xFFC00C98	/* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY		0xFFC00C94	/* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY		0xFFC00C9C	/* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR	0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR		0xFFC00CA4	/* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT	0xFFC00CB0	/* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT	0xFFC00CB8	/* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS		0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP	0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG			0xFFC00CC8	/* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR	0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR		0xFFC00CC4	/* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT		0xFFC00CD0	/* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT		0xFFC00CD8	/* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY		0xFFC00CD4	/* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY		0xFFC00CDC	/* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR	0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR		0xFFC00CE4	/* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT	0xFFC00CF0	/* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT	0xFFC00CF8	/* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS		0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP	0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG			0xFFC00D08	/* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR	0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR		0xFFC00D04	/* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT		0xFFC00D10	/* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT		0xFFC00D18	/* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY		0xFFC00D14	/* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY		0xFFC00D1C	/* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR	0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR		0xFFC00D24	/* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT	0xFFC00D30	/* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT	0xFFC00D38	/* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS		0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP	0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG			0xFFC00D48	/* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR	0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR		0xFFC00D44	/* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT		0xFFC00D50	/* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT		0xFFC00D58	/* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY		0xFFC00D54	/* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY		0xFFC00D5C	/* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR	0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR		0xFFC00D64	/* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT	0xFFC00D70	/* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT	0xFFC00D78	/* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS		0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP	0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG			0xFFC00D88	/* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR	0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR		0xFFC00D84	/* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT		0xFFC00D90	/* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT		0xFFC00D98	/* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY		0xFFC00D94	/* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY		0xFFC00D9C	/* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR	0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR		0xFFC00DA4	/* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT	0xFFC00DB0	/* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT	0xFFC00DB8	/* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS		0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP	0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG			0xFFC00DC8	/* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR		0xFFC00DC4	/* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT		0xFFC00DD0	/* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT		0xFFC00DD8	/* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY		0xFFC00DD4	/* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY		0xFFC00DDC	/* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR	0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR		0xFFC00DE4	/* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT	0xFFC00DF0	/* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT	0xFFC00DF8	/* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS		0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG			0xFFC00E88	/* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR		0xFFC00E84	/* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT			0xFFC00E90	/* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT			0xFFC00E98	/* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY		0xFFC00E94	/* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY		0xFFC00E9C	/* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR		0xFFC00EA4	/* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS		0xFFC00EA8	/* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG			0xFFC00EC8	/* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR		0xFFC00EC4	/* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT			0xFFC00ED0	/* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT			0xFFC00ED8	/* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY		0xFFC00ED4	/* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY		0xFFC00EDC	/* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR		0xFFC00EE4	/* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS		0xFFC00EE8	/* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG			0xFFC00E08	/* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR		0xFFC00E04	/* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT			0xFFC00E10	/* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT			0xFFC00E18	/* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY		0xFFC00E14	/* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY		0xFFC00E1C	/* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR		0xFFC00E24	/* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS		0xFFC00E28	/* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG			0xFFC00E48	/* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR		0xFFC00E44	/* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT			0xFFC00E50	/* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT			0xFFC00E58	/* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY		0xFFC00E54	/* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY		0xFFC00E5C	/* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR		0xFFC00E64	/* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS		0xFFC00E68	/* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA Stream 0 Source Peripheral Map Register */
-
-
-/*// Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register */
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register */
-#define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register */
-#define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register */
-#define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-/*// PLL_CTL Masks */
-#define MSEL                    0x7E00              /* Multiplier Select For CCLK/VCO Factors */
-#define SPORT_HYS               0x8000              /* Add 250mV of Hysteresis to SPORT Inputs */
-
-/* PLL_STAT Masks */
-#define VSTAT         0x0080  /* Voltage Regulator Status: Regulator at programmed voltage */
-#define CORE_IDLE     0x0040  /* processor is in the IDLE operating mode */
-#define SLEEP         0x0010  /* processor is in the Sleep operating mode */
-#define DEEP_SLEEP    0x0008  /* processor is in the Deep Sleep operating mode */
-
-#define PLL_CLKIN			0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2		0x0001  /* Pass CLKIN/2 to PLL */
-#define DF					0x0001	 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
-#define PLL_OFF				0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF			0x0008  /* Core clock off */
-#define STOPCK				0x0008	/* Core Clock Off									*/
-#define PDWN				0x0020  /* Put the PLL in a Deep Sleep state */
-
-#if !defined(__ADSPBF538__)
-/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
-# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
-#endif
-
-#define BYPASS				0x0100  /* Bypass the PLL */
-/* PLL_CTL Macros											*/
-#ifdef _MISRA_RULES
-#define	SET_MSEL(x)		(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#else
-#define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL				0x000F	/* System Select						*/
-#define	CSEL				0x0030	/* Core Select							*/
-
-#define SCLK_DIV(x)			(x)		/* SCLK = VCO / x */
-
-#define CCLK_DIV1			0x0000  /* CCLK = VCO / 1 */
-#define CCLK_DIV2			0x0010  /* CCLK = VCO / 2 */
-#define CCLK_DIV4			0x0020  /* CCLK = VCO / 4 */
-#define CCLK_DIV8			0x0030  /* CCLK = VCO / 8 */
-/* PLL_DIV Macros														*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)			((x)&0xFu)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#else
-#define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#endif /* _MISRA_RULES */
-
-/* PLL_STAT Masks																	*/
-#define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
-#define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
-#define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
-#define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
-
-/* VR_CTL Masks																	*/
-#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
-#define	HIBERNATE		0x0000	/* 	Powerdown/Bypass On-Board Regulation	*/
-#define	FREQ_333		0x0001	/* 	Switching Frequency Is 333 kHz			*/
-#define	FREQ_667		0x0002	/* 	Switching Frequency Is 667 kHz			*/
-#define	FREQ_1000		0x0003	/* 	Switching Frequency Is 1 MHz			*/
-
-#define GAIN			0x000C	/* Voltage Level Gain	*/
-#define	GAIN_5			0x0000	/* 	GAIN = 5		*/
-#define	GAIN_10			0x0004	/* 	GAIN = 10		*/
-#define	GAIN_20			0x0008	/* 	GAIN = 20		*/
-#define	GAIN_50			0x000C	/* 	GAIN = 50		*/
-
-#define	VLEV			0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications	*/
-#define	VLEV_085 		0x0060	/* 	VLEV = 0.85 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_090		0x0070	/* 	VLEV = 0.90 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_095		0x0080	/* 	VLEV = 0.95 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_100		0x0090	/* 	VLEV = 1.00 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_105		0x00A0	/* 	VLEV = 1.05 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_110		0x00B0	/* 	VLEV = 1.10 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_115		0x00C0	/* 	VLEV = 1.15 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_120		0x00D0	/* 	VLEV = 1.20 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_125		0x00E0	/* 	VLEV = 1.25 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_130		0x00F0	/* 	VLEV = 1.30 V (See Datasheet for Regulator Tolerance)	*/
-
-#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
-#define	SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* SWRST Mask */
-#define SYSTEM_RESET	0x0007	/* Initiates A System Software Reset			*/
-#define	DOUBLE_FAULT	0x0008	/* Core Double Fault Causes Reset				*/
-#define RESET_DOUBLE	0x2000	/* SW Reset Generated By Core Double-Fault		*/
-#define RESET_WDOG		0x4000	/* SW Reset Generated By Watchdog Timer			*/
-#define RESET_SOFTWARE	0x8000	/* SW Reset Occurred Since Last Read Of SWRST	*/
-
-/* SYSCR Masks																				*/
-#define BMODE_BYPASS  0x0000  /* Bypass boot ROM, execute from 16-bit external memory */
-#define BMODE_FLASH   0x0002  /* Use Boot ROM to load from 8-bit or 16-bit flash */
-#define BMODE_SPIHOST 0x0004  /* Boot from SPI0 host (slave mode) */
-#define BMODE_SPIMEM  0x0006  /* Boot from serial SPI memory */
-#define BMODE			0x0006	/* Boot Mode - Latched During HW Reset From Mode Pins	*/
-#define	NOBOOT			0x0010	/* Execute From L1 or ASYNC Bank 0 When BMODE = 0		*/
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define PLL_WAKEUP_IRQ	0x00000001      /* PLL Wakeup Interrupt Request */
-#define DMA_ERR_IRQ		0x00000002      /* DMA Controller Error Interrupt Request */
-#define PPI_ERR_IRQ		0x00000004      /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ	0x00000008      /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ	0x00000010      /* SPORT1 Error Interrupt Request */
-#define SPI_ERR_IRQ		0x00000020      /* SPI Error Interrupt Request */
-#define UART_ERR_IRQ	0x00000040      /* UART Error Interrupt Request */
-#define RTC_IRQ			0x00000080      /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ		0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ		0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ		0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ		0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ		0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ		0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ		0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ		0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ		0x00010000      /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ		0x00020000      /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ		0x00040000      /* Timer 2 Interrupt Request */
-#define PFA_IRQ			0x00080000      /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ			0x00100000      /* Programmable Flag Interrupt Request B */
-#define MDMA0_IRQ		0x00200000      /* MemDMA Stream 0 Interrupt Request */
-#define MDMA1_IRQ		0x00400000      /* MemDMA Stream 1 Interrupt Request */
-#define WDOG_IRQ		0x00800000      /* Software Watchdog Timer Interrupt Request */
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IAR0 Macros															*/
-#define P0_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #0 assigned IVG #x	*/
-#define P1_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #1 assigned IVG #x	*/
-#define P2_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #2 assigned IVG #x	*/
-#define P3_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #3 assigned IVG #x	*/
-#define P4_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #4 assigned IVG #x	*/
-#define P5_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #5 assigned IVG #x	*/
-#define P6_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #6 assigned IVG #x	*/
-#define P7_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #7 assigned IVG #x	*/
-
-/* SIC_IAR1 Macros															*/
-#define P8_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #8 assigned IVG #x	*/
-#define P9_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #9 assigned IVG #x	*/
-#define P10_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #10 assigned IVG #x	*/
-#define P11_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #11 assigned IVG #x	*/
-#define P12_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #12 assigned IVG #x	*/
-#define P13_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #13 assigned IVG #x	*/
-#define P14_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #14 assigned IVG #x	*/
-#define P15_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #15 assigned IVG #x	*/
-
-/* SIC_IAR2 Macros															*/
-#define P16_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #16 assigned IVG #x	*/
-#define P17_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #17 assigned IVG #x	*/
-#define P18_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #18 assigned IVG #x	*/
-#define P19_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #19 assigned IVG #x	*/
-#define P20_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #20 assigned IVG #x	*/
-#define P21_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #21 assigned IVG #x	*/
-#define P22_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #22 assigned IVG #x	*/
-#define P23_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #23 assigned IVG #x	*/
-
-/* SIC_IARx Macros */
-#ifdef _MISRA_RULES
-#define PX_IVG_CLR(x)  (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
-/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11);	// Clears IVG Level of Peripheral #11 */
-#define PX_IVG(x,y)     ((((y)-7u)&0xFu) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
-/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);	// Sets Peripheral #11 to IVG8 */
-#else
-#define PX_IVG_CLR(x)  (0xFFFFFFFF ^ (0xF << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
-/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11);	// Clears IVG Level of Peripheral #11 */
-#define PX_IVG(x,y)     ((((y)-7)&0xF) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
-/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);	// Sets Peripheral #11 to IVG8 */
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASK Masks*/
-#define SIC_UNMASK_ALL 0x00000000         /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL   0xFFFFFFFF         /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F))     /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR Masks*/
-#define IWR_DISABLE_ALL 0x00000000        /* Wakeup Disable all peripherals   */
-#define IWR_ENABLE_ALL  0xFFFFFFFF        /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#ifdef _MISRA_RULES
-#define WDEV(x)			(((x)<<1) & 0x0006u) 	/* event generated on roll over */
-#else
-#define WDEV(x)			(((x)<<1) & 0x0006) 	/* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET		0x0000 				/* generate reset event on roll over */
-#define WDEV_NMI		0x0002 				/* generate NMI event on roll over */
-#define WDEV_GPI		0x0004 				/* generate GP IRQ on roll over */
-#define WDEV_NONE		0x0006 				/* no event on roll over */
-#define WDEN			0x0FF0 				/* enable watchdog */
-#define WDDIS			0x0AD0 				/* disable watchdog */
-#define WDRO			0x8000 				/* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-#define ICTL WDEV
-#define ENABLE_RESET 	WDEV_RESET
-#define WDOG_RESET 		WDEV_RESET
-#define ENABLE_NMI 		WDEV_NMI
-#define WDOG_NMI 		WDEV_NMI
-#define ENABLE_GPI 		WDEV_GPI
-#define WDOG_GPI 		WDEV_GPI
-#define DISABLE_EVT 	WDEV_NONE
-#define WDOG_NONE 		WDEV_NONE
-
-#define TMR_EN 			WDEN
-#define WDOG_DISABLE	WDDIS
-#define TRO 			WDRO
-
-#define ICTL_P0			0x01
-#define ICTL_P1			0x02
-#define TRO_P			0x0F
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM register */
-#define	RTSEC		0x0000003F	/* Real-Time Clock Seconds */
-#define	RTMIN		0x00000FC0	/* Real-Time Clock Minutes */
-#define	RTHR		0x0001F000	/* Real-Time Clock Hours */
-#define	RTDAY		0xFFFE0000	/* Real-Time Clock Days */
-
-/* RTC_ICTL register */
-#define	SWIE		0x0001		/* Stopwatch Interrupt Enable */
-#define	AIE			0x0002		/* Alarm Interrupt Enable */
-#define	SIE			0x0004		/* Seconds (1 Hz) Interrupt Enable */
-#define	MIE			0x0008		/* Minutes Interrupt Enable */
-#define	HIE			0x0010		/* Hours Interrupt Enable */
-#define	DIE			0x0020		/* 24 Hours (Days) Interrupt Enable */
-#define	DAIE		0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define	WCIE		0x8000		/* Write Complete Interrupt Enable */
-
-/* RTC_ISTAT register */
-#define	SWEF		0x0001		/* Stopwatch Event Flag */
-#define	AEF			0x0002		/* Alarm Event Flag */
-#define	SEF			0x0004		/* Seconds (1 Hz) Event Flag */
-#define	MEF			0x0008		/* Minutes Event Flag */
-#define	HEF			0x0010		/* Hours Event Flag */
-#define	DEF			0x0020		/* 24 Hours (Days) Event Flag */
-#define	DAEF		0x0040		/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define	WPS			0x4000		/* Write Pending Status (RO) */
-#define	WCOM		0x8000		/* Write Complete */
-
-/*// RTC_FAST Mask (RTC_PREN Mask) */
-#define ENABLE_PRESCALE      0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
-#define PREN                 0x00000001
-         	/* ** Must be set after power-up for proper operation of RTC */
-
-/* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* Deprecated RTC_STAT and RTC_ALARM Masks										*/
-#define	RTC_SEC			RTSEC	/* Real-Time Clock Seconds	*/
-#define	RTC_MIN			RTMIN	/* Real-Time Clock Minutes	*/
-#define	RTC_HR			RTHR	/* Real-Time Clock Hours	*/
-#define	RTC_DAY			RTDAY	/* Real-Time Clock Days		*/
-
-/* Deprecated RTC_ICTL/RTC_ISTAT Masks																		*/
-#define	STOPWATCH		SWIE		/* Stopwatch Interrupt Enable								*/
-#define	ALARM			AIE		/* Alarm Interrupt Enable									*/
-#define	SECOND			SIE		/* Seconds (1 Hz) Interrupt Enable							*/
-#define	MINUTE			MIE		/* Minutes Interrupt Enable									*/
-#define	HOUR			HIE		/* Hours Interrupt Enable									*/
-#define	DAY				DIE		/* 24 Hours (Days) Interrupt Enable							*/
-#define	DAY_ALARM		DAIE		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
-#define	WRITE_COMPLETE	WCIE		/* Write Complete Interrupt Enable							*/
-
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-/* UART_LCR Register */
-
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select */
-#else
-#define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB			0x04				/* Stop Bits			*/
-#define PEN			0x08				/* Parity Enable		*/
-#define EPS			0x10				/* Even Parity Select	*/
-#define STP			0x20				/* Stick Parity			*/
-#define SB			0x40				/* Set Break			*/
-#define DLAB		0x80				/* Divisor Latch Access	*/
-
-#define DLAB_P		0x07
-#define SB_P		0x06
-#define STP_P		0x05
-#define EPS_P		0x04
-#define PEN_P		0x03
-#define STB_P		0x02
-#define WLS_P1		0x01
-#define WLS_P0		0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA	0x10		/* Loopback Mode Enable    */
-#define LOOP_ENA_P	0x04
-/* Deprecated UARTx_MCR Mask										*/
-
-/* UART_LSR Register */
-#define DR			0x01	/* Data Ready				*/
-#define OE			0x02	/* Overrun Error			*/
-#define PE			0x04	/* Parity Error				*/
-#define FE			0x08	/* Framing Error			*/
-#define BI			0x10	/* Break Interrupt			*/
-#define THRE		0x20	/* THR Empty				*/
-#define TEMT		0x40	/* TSR and UART_THR Empty	*/
-
-#define TEMP_P		0x06
-#define THRE_P		0x05
-#define BI_P		0x04
-#define FE_P		0x03
-#define PE_P		0x02
-#define OE_P		0x01
-#define DR_P		0x00
-
-/* UART_IER Register */
-#define ERBFI		0x01		/* Enable Receive Buffer Full Interrupt		*/
-#define ETBEI		0x02		/* Enable Transmit Buffer Empty Interrupt	*/
-#define ELSI		0x04		/* Enable RX Status Interrupt				*/
-
-#define ELSI_P		0x02
-#define ETBEI_P		0x01
-#define ERBFI_P		0x00
-
-/* UART_IIR Register */
-#ifdef _MISRA_RULES
-#define STATUS(x)	(((x) << 1) & 0x06u)
-#else
-#define STATUS(x)	(((x) << 1) & 0x06)
-#endif /* _MISRA_RULES */
-#define NINT		0x01
-#define STATUS_P1	0x02
-#define STATUS_P0	0x01
-#define NINT_P		0x00
-
-/* UART_GCTL Register */
-#define UCEN		0x01		/* Enable UARTx Clocks				*/
-#define IREN		0x02		/* Enable IrDA Mode					*/
-#define TPOLC		0x04		/* IrDA TX Polarity Change			*/
-#define RPOLC		0x08		/* IrDA RX Polarity Change			*/
-#define FPE			0x10		/* Force Parity Error On Transmit	*/
-#define FFE			0x20		/* Force Framing Error On Transmit	*/
-
-#define FFE_P		0x05
-#define FPE_P		0x04
-#define RPOLC_P		0x03
-#define TPOLC_P		0x02
-#define IREN_P		0x01
-#define UCEN_P		0x00
-
-
-/* **********  SERIAL PORT MASKS  ********************** */
-/* SPORTx_TCR1 Masks */
-#define TSPEN		0x0001  /* TX enable  */
-#define ITCLK		0x0002  /* Internal TX Clock Select  */
-#define TDTYPE		0x000C  /* TX Data Formatting Select */
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define TLSBIT		0x0010  /* TX Bit Order */
-#define ITFS		0x0200  /* Internal TX Frame Sync Select  */
-#define TFSR		0x0400  /* TX Frame Sync Required Select  */
-#define DITFS		0x0800  /* Data Independent TX Frame Sync Select  */
-#define LTFS		0x1000  /* Low TX Frame Sync Select  */
-#define LATFS		0x2000  /* Late TX Frame Sync Select  */
-#define TCKFE		0x4000  /* TX Clock Falling Edge Select  */
-/* SPORTx_RCR1 Deprecated Masks															*/
-#define TULAW		DTYPE_ULAW		/* Compand Using u-Law							*/
-#define TALAW		DTYPE_ALAW			/* Compand Using A-Law							*/
-
-/* SPORTx_TCR2 Masks */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
-    defined(__ADSPBF533__)
-# define SLEN		0x001F
-#else
-#ifdef _MISRA_RULES
-# define SLEN(x)		((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)				*/
-#else
-# define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#endif
-#define TXSE		0x0100  /*TX Secondary Enable */
-#define TSFSE		0x0200  /*TX Stereo Frame Sync Enable */
-#define TRFST		0x0400  /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN		0x0001  /* RX enable  */
-#define IRCLK		0x0002  /* Internal RX Clock Select  */
-#define RDTYPE		0x000C  /* RX Data Formatting Select */
-#define DTYPE_NORM	0x0000		/* no companding							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define RLSBIT		0x0010  /* RX Bit Order */
-#define IRFS		0x0200  /* Internal RX Frame Sync Select  */
-#define RFSR		0x0400  /* RX Frame Sync Required Select  */
-#define LRFS		0x1000  /* Low RX Frame Sync Select  */
-#define LARFS		0x2000  /* Late RX Frame Sync Select  */
-#define RCKFE		0x4000  /* RX Clock Falling Edge Select  */
-/* SPORTx_RCR1 Deprecated Masks															*/
-#define RULAW		DTYPE_ULAW		/* Compand Using u-Law							*/
-#define RALAW		DTYPE_ALAW			/* Compand Using A-Law							*/
-
-/* SPORTx_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE		0x0100  /*RX Secondary Enable */
-#define RSFSE		0x0200  /*RX Stereo Frame Sync Enable */
-#define RRFST		0x0400  /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE		0x0001		/*RX FIFO Not Empty Status */
-#define RUVF		0x0002  	/*RX Underflow Status */
-#define ROVF		0x0004		/*RX Overflow Status */
-#define TXF			0x0008		/*TX FIFO Full Status */
-#define TUVF		0x0010  	/*TX Underflow Status */
-#define TOVF		0x0020  	/*TX Overflow Status */
-#define TXHRE		0x0040  	/*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define WSIZE			0x0000F000 	/*Multichannel Window Size Field */
-#define WOFF			0x000003FF 	/*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros															*/
-#ifdef _MISRA_RULES
-#define SET_WOFF(x)		((x) & 0x3FFu) 	/* Multichannel Window Offset Field			*/
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define SET_WSIZE(x)	(((((x)>>0x3)-1u)&0xFu) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#else
-#define SET_WOFF(x)		((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define SET_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#endif /* _MISRA_RULES */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM		0x0003 	/*Multichannel Clock Recovery Mode */
-#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/
-#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/
-#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/
-#define MCDTXPE		0x0004 	/*Multichannel DMA Transmit Packing */
-#define MCDRXPE		0x0008 	/*Multichannel DMA Receive Packing */
-#define MCMEN		0x0010 	/*Multichannel Frame Mode Enable */
-#define FSDR		0x0080 	/*Multichannel Frame Sync to Data Relationship */
-#define MFD			0xF000 	/*Multichannel Frame Delay    */
-#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/
-#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/
-#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/
-#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/
-#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/
-#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/
-#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/
-#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/
-#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/
-#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/
-#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/
-#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/
-#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/
-#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/
-#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/
-#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/
-
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-/*//  PPI_CONTROL Masks         */
-#define PORT_EN		0x0001  /* PPI Port Enable  */
-#define PORT_DIR	0x0002  /* PPI Port Direction       */
-#define XFR_TYPE	0x000C  /* PPI Transfer Type  */
-#define PORT_CFG	0x0030  /* PPI Port Configuration */
-#define FLD_SEL		0x0040  /* PPI Active Field Select */
-#define PACK_EN		0x0080  /* PPI Packing Mode */
-/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define ALT_TIMING	0x0100  /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
-#define SKIP_EN		0x0200  /* PPI Skip Element Enable */
-#define SKIP_EO		0x0400  /* PPI Skip Even/Odd Elements */
-#define DLENGTH		0x3800  /* PPI Data Length  */
-#define DLEN_8		0x0	     /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10		0x0800		/* Data Length = 10 Bits			*/
-#define DLEN_11		0x1000		/* Data Length = 11 Bits			*/
-#define DLEN_12		0x1800		/* Data Length = 12 Bits			*/
-#define DLEN_13		0x2000		/* Data Length = 13 Bits			*/
-#define DLEN_14		0x2800		/* Data Length = 14 Bits			*/
-#define DLEN_15		0x3000		/* Data Length = 15 Bits			*/
-#define DLEN_16		0x3800		/* Data Length = 16 Bits			*/
-#ifdef _MISRA_RULES
-#define DLEN(x)		((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x)		((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL			0xC000  /* PPI Signal Polarities       */
-#define POLC		0x4000		/* PPI Clock Polarity				*/
-#define POLS		0x8000		/* PPI Frame Sync Polarity			*/
-
-
-/*// PPI_STATUS Masks                                          */
-#define FLD			0x0400  /* Field Indicator   */
-#define FT_ERR		0x0800  /* Frame Track Error */
-#define OVR			0x1000  /* FIFO Overflow Error */
-#define UNDR		0x2000  /* FIFO Underrun Error */
-#define ERR_DET		0x4000  /* Error Detected Indicator */
-#define ERR_NCOR	0x8000  /* Error Not Corrected Indicator */
-
-
-/* **********  DMA CONTROLLER MASKS  ***********************/
-/*//DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN		0x0001  /* Channel Enable */
-#define WNR			0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8	0x0000  /* Word Size 8 bits */
-#define WDSIZE_16	0x0004  /* Word Size 16 bits */
-#define WDSIZE_32	0x0008  /* Word Size 32 bits */
-#define DMA2D		0x0010  /* 2D/1D* Mode */
-#define RESTART		0x0020  /* Restart */
-#define DI_SEL		0x0040  /* Data Interrupt Select */
-#define DI_EN		0x0080  /* Data Interrupt Enable */
-#define NDSIZE		0x0900  /* Next Descriptor Size */
-#define NDSIZE_0	0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1	0x0100	/* Next Descriptor Size = 1						*/
-#define NDSIZE_2	0x0200	/* Next Descriptor Size = 2						*/
-#define NDSIZE_3	0x0300	/* Next Descriptor Size = 3						*/
-#define NDSIZE_4	0x0400	/* Next Descriptor Size = 4						*/
-#define NDSIZE_5	0x0500	/* Next Descriptor Size = 5						*/
-#define NDSIZE_6	0x0600	/* Next Descriptor Size = 6						*/
-#define NDSIZE_7	0x0700	/* Next Descriptor Size = 7						*/
-#define NDSIZE_8	0x0800	/* Next Descriptor Size = 8						*/
-#define NDSIZE_9	0x0900	/* Next Descriptor Size = 9						*/
-#define FLOW		0x7000  /* Flow Control */
-#define FLOW_STOP	0x0000	/* Stop Mode									*/
-#define FLOW_AUTO	0x1000	/* Autobuffer Mode								*/
-#define FLOW_ARRAY	0x4000	/* Descriptor Array Mode						*/
-#define FLOW_SMALL	0x6000	/* Small Model Descriptor List Mode				*/
-#define FLOW_LARGE	0x7000	/* Large Model Descriptor List Mode				*/
-
-#define DMAEN_P		0x0		/* Channel Enable */
-#define WNR_P		0x1		/* Channel Direction (W/R*) */
-#define DMA2D_P		0x4		/* 2D/1D* Mode */
-#define RESTART_P	0x5		/* Restart */
-#define DI_SEL_P	0x6		/* Data Interrupt Select */
-#define DI_EN_P		0x7		/* Data Interrupt Enable */
-
-/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE	0x0001	/* DMA Done Indicator */
-#define DMA_ERR		0x0002	/* DMA Error Indicator */
-#define DFETCH		0x0004	/* Descriptor Fetch Indicator */
-#define DMA_RUN		0x0008	/* DMA Running Indicator */
-
-#define DMA_DONE_P	0x0		/* DMA Done Indicator */
-#define DMA_ERR_P	0x1		/* DMA Error Indicator */
-#define DFETCH_P	0x2		/* Descriptor Fetch Indicator */
-#define DMA_RUN_P	0x3		/* DMA Running Indicator */
-
-/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE			0x0040	/* DMA Channel Type Indicator */
-#define CTYPE_P			0x6		/* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8			0x0080	/* DMA 8-bit Operation Indicator   */
-#define PCAP16			0x0100	/* DMA 16-bit Operation Indicator */
-#define PCAP32			0x0200	/* DMA 32-bit Operation Indicator */
-#define PCAPWR			0x0400	/* DMA Write Operation Indicator */
-#define PCAPRD			0x0800	/* DMA Read Operation Indicator */
-#define PMAP			0xF000	/* DMA Peripheral Map Field */
-
-#define PMAP_PPI		0x0000	/* PMAP PPI Port DMA */
-#define	PMAP_SPORT0RX	0x1000	/* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX	0x2000	/* PMAP SPORT0 Transmit DMA */
-#define	PMAP_SPORT1RX	0x3000	/* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX	0x4000	/* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI		0x5000	/* PMAP SPI DMA */
-#define PMAP_UARTRX		0x6000	/* PMAP UART Receive DMA */
-#define PMAP_UARTTX		0x7000	/* PMAP UART Transmit DMA */
-
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0			0x0001	/* Enable Timer 0	*/
-#define TIMEN1			0x0002	/* Enable Timer 1	*/
-#define TIMEN2			0x0004	/* Enable Timer 2	*/
-
-#define TIMEN0_P		0x00
-#define TIMEN1_P		0x01
-#define TIMEN2_P		0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0			0x0001	/* Disable Timer 0	*/
-#define TIMDIS1			0x0002	/* Disable Timer 1	*/
-#define TIMDIS2			0x0004	/* Disable Timer 2	*/
-
-#define TIMDIS0_P		0x00
-#define TIMDIS1_P		0x01
-#define TIMDIS2_P		0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0			0x0001	/* Timer 0 Interrupt			*/
-#define TIMIL1			0x0002	/* Timer 1 Interrupt			*/
-#define TIMIL2			0x0004	/* Timer 2 Interrupt			*/
-#define TOVF_ERR0		0x0010	/* Timer 0 Counter Overflow		*/
-#define TOVF_ERR1		0x0020	/* Timer 1 Counter Overflow		*/
-#define TOVF_ERR2		0x0040	/* Timer 2 Counter Overflow		*/
-#define TRUN0			0x1000	/* Timer 0 Slave Enable Status	*/
-#define TRUN1			0x2000	/* Timer 1 Slave Enable Status	*/
-#define TRUN2			0x4000	/* Timer 2 Slave Enable Status	*/
-
-#define TIMIL0_P		0x00
-#define TIMIL1_P		0x01
-#define TIMIL2_P		0x02
-#define TOVF_ERR0_P		0x04
-#define TOVF_ERR1_P		0x05
-#define TOVF_ERR2_P		0x06
-#define TRUN0_P			0x0C
-#define TRUN1_P			0x0D
-#define TRUN2_P			0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 		TOVF_ERR0
-#define TOVL_ERR1 		TOVF_ERR1
-#define TOVL_ERR2 		TOVF_ERR2
-#define TOVL_ERR0_P		TOVF_ERR0_P
-#define TOVL_ERR1_P 	TOVF_ERR1_P
-#define TOVL_ERR2_P 	TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT			0x0001
-#define WDTH_CAP		0x0002
-#define EXT_CLK			0x0003
-#define PULSE_HI		0x0004
-#define PERIOD_CNT		0x0008
-#define IRQ_ENA			0x0010
-#define TIN_SEL			0x0020
-#define OUT_DIS			0x0040
-#define CLK_SEL			0x0080
-#define TOGGLE_HI		0x0100
-#define EMU_RUN			0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x)		(((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x)		(((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0		0x00
-#define TMODE_P1		0x01
-#define PULSE_HI_P		0x02
-#define PERIOD_CNT_P	0x03
-#define IRQ_ENA_P		0x04
-#define TIN_SEL_P		0x05
-#define OUT_DIS_P		0x06
-#define CLK_SEL_P		0x07
-#define TOGGLE_HI_P		0x08
-#define EMU_RUN_P		0x09
-#define ERR_TYP_P0		0x0E
-#define ERR_TYP_P1		0x0F
-
-
-/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
-/*  Port F (Previously Flag I/O_ Masks */
-#define PF0			0x0001
-#define PF1			0x0002
-#define PF2			0x0004
-#define PF3			0x0008
-#define PF4			0x0010
-#define PF5			0x0020
-#define PF6			0x0040
-#define PF7			0x0080
-#define PF8			0x0100
-#define PF9			0x0200
-#define PF10		0x0400
-#define PF11		0x0800
-#define PF12		0x1000
-#define PF13		0x2000
-#define PF14		0x4000
-#define PF15		0x8000
-
-/*  PORT F BIT POSITIONS */
-#define PF0_P		0x0
-#define PF1_P		0x1
-#define PF2_P		0x2
-#define PF3_P		0x3
-#define PF4_P		0x4
-#define PF5_P		0x5
-#define PF6_P		0x6
-#define PF7_P		0x7
-#define PF8_P		0x8
-#define PF9_P		0x9
-#define PF10_P		0xA
-#define PF11_P		0xB
-#define PF12_P		0xC
-#define PF13_P		0xD
-#define PF14_P		0xE
-#define PF15_P		0xF
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-/* SPI_CTL Masks */
-#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/
-#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/
-#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/
-#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/
-#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/
-#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/
-#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/
-#define PSSE		0x0010		/* Slave-Select Input Enable						*/
-#define EMISO		0x0020		/* Enable MISO As Output							*/
-#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/
-#define LSBF		0x0200		/* LSB First										*/
-#define CPHA		0x0400		/* Clock Phase										*/
-#define CPOL		0x0800		/* Clock Polarity									*/
-#define MSTR		0x1000		/* Master/Slave*									*/
-#define WOM			0x2000		/* Write Open Drain Master							*/
-#define SPE			0x4000		/* SPI Enable										*/
-
-/* SPI_FLG Masks */
-#define FLS1	0x0002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2	0x0004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3	0x0008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4	0x0010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5	0x0020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6	0x0040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7	0x0080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-#define FLG1	0x0200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2	0x0400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3	0x0800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4	0x1000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5	0x2000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6	0x4000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7	0x8000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P	0x0001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P	0x0002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P	0x0003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P	0x0004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P	0x0005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P	0x0006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P	0x0007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P	0x0009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P	0x000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P	0x000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P	0x000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P	0x000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P	0x000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P	0x000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF	0x0001  /* Set (=1) when SPI single-word transfer complete */
-#define MODF	0x0002  /* Set (=1) in a master device when some other device tries to become master */
-#define TXE		0x0004  /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS		0x0008  /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY	0x0010  /* Set (=1) when data is received with RDBR full */
-#define RXS		0x0020  /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL	0x0040  /* When set (=1), corrupt data may have been transmitted  */
-
-/* SPIx_FLG Masks																	*/
-#define FLG1E	0xFDFF		/* Activates SPI_FLOUT1 							*/
-#define FLG2E	0xFBFF		/* Activates SPI_FLOUT2								*/
-#define FLG3E	0xF7FF		/* Activates SPI_FLOUT3								*/
-#define FLG4E	0xEFFF		/* Activates SPI_FLOUT4								*/
-#define FLG5E	0xDFFF		/* Activates SPI_FLOUT5								*/
-#define FLG6E	0xBFFF		/* Activates SPI_FLOUT6								*/
-#define FLG7E	0x7FFF		/* Activates SPI_FLOUT7								*/
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN			0x0001	/* Enable CLKOUT */
-#define	AMBEN_NONE		0x0000	/* All Banks Disabled								*/
-#define AMBEN_B0		0x0002	/* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1		0x0004	/* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2		0x0006	/* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL		0x0008	/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO                  0x0100      /* DMA has priority over core for for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P		0x0000	/* Enable CLKOUT */
-#define AMBEN_P0		0x0001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1		0x0002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2		0x0003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN			0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 		0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1			0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2			0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3			0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4			0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1			0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2			0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3			0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4			0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1			0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2			0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3			0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0			0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1			0x00000100  /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2			0x00000200  /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3			0x00000300  /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4			0x00000400  /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5			0x00000500  /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6			0x00000600  /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7			0x00000700  /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8			0x00000800  /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9			0x00000900  /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10		0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11		0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12		0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13		0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14		0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15		0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1			0x00001000  /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2			0x00002000  /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3			0x00003000  /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4			0x00004000  /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5			0x00005000  /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6			0x00006000  /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7			0x00007000  /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8			0x00008000  /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9			0x00009000  /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10		0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11		0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12		0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13		0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14		0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15		0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN			0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL		0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1			0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2			0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3			0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4			0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1			0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2			0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3			0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4			0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1			0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2			0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3			0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0			0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1			0x01000000  /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2			0x02000000  /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3			0x03000000  /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4			0x04000000  /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5			0x05000000  /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6			0x06000000  /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7			0x07000000  /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8			0x08000000  /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9			0x09000000  /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10		0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11		0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12		0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13		0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14		0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15		0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1			0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2			0x20000000  /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3			0x30000000  /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4			0x40000000  /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5			0x50000000  /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6			0x60000000  /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7			0x70000000  /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8			0x80000000  /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9			0x90000000  /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10		0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11		0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12		0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13		0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14		0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15		0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN			0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL		0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1			0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2			0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3			0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4			0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1			0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2			0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3			0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4			0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1			0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2			0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3			0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0			0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1			0x00000100  /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2			0x00000200  /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3			0x00000300  /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4			0x00000400  /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5			0x00000500  /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6			0x00000600  /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7			0x00000700  /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8			0x00000800  /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9			0x00000900  /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10		0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11		0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12		0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13		0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14		0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15		0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1			0x00001000  /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2			0x00002000  /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3			0x00003000  /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4			0x00004000  /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5			0x00005000  /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6			0x00006000  /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7			0x00007000  /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8			0x00008000  /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9			0x00009000  /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10		0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11		0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12		0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13		0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14		0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15		0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN			0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL		0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1			0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2			0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3			0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4			0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1			0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2			0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3			0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4			0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1			0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2			0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3			0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0			0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1			0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2			0x02000000  /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3			0x03000000  /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4			0x04000000  /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5			0x05000000  /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6			0x06000000  /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7			0x07000000  /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8			0x08000000  /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9			0x09000000  /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10		0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11		0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12		0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13		0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14		0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15		0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1			0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2			0x20000000  /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3			0x30000000  /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4			0x40000000  /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5			0x50000000  /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6			0x60000000  /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7			0x70000000  /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8			0x80000000  /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9			0x90000000  /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10		0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11		0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12		0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13		0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14		0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15		0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-/* EBIU_SDGCTL Masks */
-
-
-#define SCTLE			0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2			0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3			0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define CL           0x0000000C  /* SDRAM CAS latency */
-#define PFE				0x00000010 /* Enable SDRAM prefetch */
-#define PFP				0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
-#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh		*/
-#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
-#define PASR         0x00000030  /* SDRAM partial array self-refresh */
-#define TRAS_1			0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2			0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3			0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4			0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5			0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6			0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7			0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8			0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9			0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10			0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11			0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12			0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13			0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14			0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15			0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRAS            0x000003C0 /* SDRAM tRAS in SCLK cycles */
-#define TRP_1			0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2			0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3			0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4			0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5			0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6			0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7			0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRP          0x00003800 /* SDRAM tRP in SCLK cycles */
-#define TRCD_1			0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2			0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3			0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4			0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5			0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6			0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7			0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TRCD         0x00030000 /* SDRAM tRCD in SCLK cycles */
-#define TWR_1			0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2			0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3			0x00180000 /* SDRAM tWR = 3 cycles */
-#define TWR          0x00180000  /* SDRAM tWR in SCLK cycles */
-#define PUPSD			0x00200000 /*Power-up start delay */
-#define PSM				0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS				0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS			0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE			0x02000000 /* Enable external buffering timing */
-#define FBBRW			0x04000000 /* Fast back-to-back read write enable */
-#define EMREN			0x10000000 /* Extended mode register enable */
-#define TCSR			0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG			0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE				0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16		0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32		0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64		0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128		0x00000006 /* SDRAM external bank size = 128MB */
-#define EBCAW_8		0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBSZ         0x0006 /* SDRAM external bank size */
-#define EBCAW_9		0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10		0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11		0x00000030 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW        0x0030 /* SDRAM external bank column address width */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI			0x00000001 /* SDRAM controller is idle  */
-#define SDSRA			0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA			0x00000004 /* SDRAM power up active  */
-#define SDRS			0x00000008 /* SDRAM is in reset state */
-#define SDEASE			0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT			0x00000020 /* Bus granted */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF532_H */
diff --git a/libgloss/bfin/include/defBF533.h b/libgloss/bfin/include/defBF533.h
deleted file mode 100644
index c8100ec90..000000000
--- a/libgloss/bfin/include/defBF533.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defBF533.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _DEFBF533_H
-#define _DEFBF533_H
-
-#include <defBF532.h>
-
-#endif /* _DEFBF533_H */
diff --git a/libgloss/bfin/include/defBF534.h b/libgloss/bfin/include/defBF534.h
deleted file mode 100644
index b5ecc9518..000000000
--- a/libgloss/bfin/include/defBF534.h
+++ /dev/null
@@ -1,2733 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2004-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution")
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control	(0xFFC00000 - 0xFFC000FF)								*/
-#define PLL_CTL				0xFFC00000	/* PLL Control Register						*/
-#define PLL_DIV				0xFFC00004	/* PLL Divide Register						*/
-#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register		*/
-#define PLL_STAT			0xFFC0000C	/* PLL Status Register						*/
-#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register					*/
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)							*/
-#define SWRST				0xFFC00100	/* Software Reset Register					*/
-#define SYSCR				0xFFC00104	/* System Configuration Register			*/
-#define SIC_IMASK			0xFFC0010C	/* Interrupt Mask Register					*/
-#define SIC_IAR0			0xFFC00110	/* Interrupt Assignment Register 0			*/
-#define SIC_IAR1			0xFFC00114	/* Interrupt Assignment Register 1			*/
-#define SIC_IAR2			0xFFC00118	/* Interrupt Assignment Register 2			*/
-#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3			*/
-#define SIC_ISR				0xFFC00120	/* Interrupt Status Register				*/
-#define SIC_IWR				0xFFC00124	/* Interrupt Wakeup Register				*/
-
-
-/* Watchdog Timer			(0xFFC00200 - 0xFFC002FF)								*/
-#define WDOG_CTL			0xFFC00200	/* Watchdog Control Register				*/
-#define WDOG_CNT			0xFFC00204	/* Watchdog Count Register					*/
-#define WDOG_STAT			0xFFC00208	/* Watchdog Status Register					*/
-
-
-/* Real Time Clock		(0xFFC00300 - 0xFFC003FF)									*/
-#define RTC_STAT			0xFFC00300	/* RTC Status Register						*/
-#define RTC_ICTL			0xFFC00304	/* RTC Interrupt Control Register			*/
-#define RTC_ISTAT			0xFFC00308	/* RTC Interrupt Status Register			*/
-#define RTC_SWCNT			0xFFC0030C	/* RTC Stopwatch Count Register				*/
-#define RTC_ALARM			0xFFC00310	/* RTC Alarm Time Register					*/
-#define RTC_FAST			0xFFC00314	/* RTC Prescaler Enable Register			*/
-#define RTC_PREN			0xFFC00314	/* RTC Prescaler Enable Alternate Macro		*/
-
-
-/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)									*/
-#define UART0_THR			0xFFC00400	/* Transmit Holding register				*/
-#define UART0_RBR			0xFFC00400	/* Receive Buffer register					*/
-#define UART0_DLL			0xFFC00400	/* Divisor Latch (Low-Byte)					*/
-#define UART0_IER			0xFFC00404	/* Interrupt Enable Register				*/
-#define UART0_DLH			0xFFC00404	/* Divisor Latch (High-Byte)				*/
-#define UART0_IIR			0xFFC00408	/* Interrupt Identification Register		*/
-#define UART0_LCR			0xFFC0040C	/* Line Control Register					*/
-#define UART0_MCR			0xFFC00410	/* Modem Control Register					*/
-#define UART0_LSR			0xFFC00414	/* Line Status Register						*/
-#define UART0_SCR			0xFFC0041C	/* SCR Scratch Register						*/
-#define UART0_GCTL			0xFFC00424	/* Global Control Register					*/
-
-
-/* SPI Controller			(0xFFC00500 - 0xFFC005FF)								*/
-#define SPI_CTL				0xFFC00500	/* SPI Control Register						*/
-#define SPI_FLG				0xFFC00504	/* SPI Flag register						*/
-#define SPI_STAT			0xFFC00508	/* SPI Status register						*/
-#define SPI_TDBR			0xFFC0050C	/* SPI Transmit Data Buffer Register		*/
-#define SPI_RDBR			0xFFC00510	/* SPI Receive Data Buffer Register			*/
-#define SPI_BAUD			0xFFC00514	/* SPI Baud rate Register					*/
-#define SPI_SHADOW			0xFFC00518	/* SPI_RDBR Shadow Register					*/
-
-
-/* TIMER0-7 Registers		(0xFFC00600 - 0xFFC006FF)								*/
-#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register			*/
-#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register					*/
-#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register					*/
-#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register					*/
-
-#define TIMER1_CONFIG		0xFFC00610	/* Timer 1 Configuration Register  			*/
-#define TIMER1_COUNTER		0xFFC00614	/* Timer 1 Counter Register        			*/
-#define TIMER1_PERIOD		0xFFC00618	/* Timer 1 Period Register         			*/
-#define TIMER1_WIDTH		0xFFC0061C	/* Timer 1 Width Register          			*/
-
-#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register  			*/
-#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register        			*/
-#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register         			*/
-#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register          			*/
-
-#define TIMER3_CONFIG		0xFFC00630	/* Timer 3 Configuration Register			*/
-#define TIMER3_COUNTER		0xFFC00634	/* Timer 3 Counter Register					*/
-#define TIMER3_PERIOD		0xFFC00638	/* Timer 3 Period Register					*/
-#define TIMER3_WIDTH		0xFFC0063C	/* Timer 3 Width Register					*/
-
-#define TIMER4_CONFIG		0xFFC00640	/* Timer 4 Configuration Register  			*/
-#define TIMER4_COUNTER		0xFFC00644	/* Timer 4 Counter Register        			*/
-#define TIMER4_PERIOD		0xFFC00648	/* Timer 4 Period Register         			*/
-#define TIMER4_WIDTH		0xFFC0064C	/* Timer 4 Width Register          			*/
-
-#define TIMER5_CONFIG		0xFFC00650	/* Timer 5 Configuration Register  			*/
-#define TIMER5_COUNTER		0xFFC00654	/* Timer 5 Counter Register        			*/
-#define TIMER5_PERIOD		0xFFC00658	/* Timer 5 Period Register         			*/
-#define TIMER5_WIDTH		0xFFC0065C	/* Timer 5 Width Register          			*/
-
-#define TIMER6_CONFIG		0xFFC00660	/* Timer 6 Configuration Register  			*/
-#define TIMER6_COUNTER		0xFFC00664	/* Timer 6 Counter Register        			*/
-#define TIMER6_PERIOD		0xFFC00668	/* Timer 6 Period Register         			*/
-#define TIMER6_WIDTH		0xFFC0066C	/* Timer 6 Width Register          			*/
-
-#define TIMER7_CONFIG		0xFFC00670	/* Timer 7 Configuration Register  			*/
-#define TIMER7_COUNTER		0xFFC00674	/* Timer 7 Counter Register        			*/
-#define TIMER7_PERIOD		0xFFC00678	/* Timer 7 Period Register         			*/
-#define TIMER7_WIDTH		0xFFC0067C	/* Timer 7 Width Register       			*/
-
-#define TIMER_ENABLE		0xFFC00680	/* Timer Enable Register					*/
-#define TIMER_DISABLE		0xFFC00684	/* Timer Disable Register					*/
-#define TIMER_STATUS		0xFFC00688	/* Timer Status Register					*/
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)												*/
-#define PORTFIO					0xFFC00700	/* Port F I/O Pin State Specify Register				*/
-#define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register		*/
-#define PORTFIO_SET				0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register			*/
-#define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
-#define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register	*/
-#define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register			*/
-#define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register			*/
-#define PORTFIO_MASKA_TOGGLE	0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register	*/
-#define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register			*/
-#define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register			*/
-#define PORTFIO_MASKB_TOGGLE	0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTFIO_DIR				0xFFC00730	/* Port F I/O Direction Register						*/
-#define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
-#define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register				*/
-#define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register				*/
-#define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
-
-
-/* SPORT0 Controller		(0xFFC00800 - 0xFFC008FF)										*/
-#define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register			*/
-#define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register			*/
-#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider					*/
-#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider				*/
-#define SPORT0_TX			0xFFC00810	/* SPORT0 TX Data Register							*/
-#define SPORT0_RX			0xFFC00818	/* SPORT0 RX Data Register							*/
-#define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register			*/
-#define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register			*/
-#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider						*/
-#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider				*/
-#define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
-#define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register					*/
-#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1	*/
-#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2	*/
-#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0	*/
-#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1	*/
-#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2	*/
-#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3	*/
-#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0	*/
-#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1	*/
-#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2	*/
-#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3	*/
-
-
-/* SPORT1 Controller		(0xFFC00900 - 0xFFC009FF)										*/
-#define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register			*/
-#define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register			*/
-#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider					*/
-#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider				*/
-#define SPORT1_TX			0xFFC00910	/* SPORT1 TX Data Register							*/
-#define SPORT1_RX			0xFFC00918	/* SPORT1 RX Data Register							*/
-#define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register			*/
-#define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register			*/
-#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider						*/
-#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider				*/
-#define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
-#define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register					*/
-#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1	*/
-#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2	*/
-#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0	*/
-#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1	*/
-#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2	*/
-#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3	*/
-#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0	*/
-#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1	*/
-#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2	*/
-#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3	*/
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)								*/
-#define EBIU_AMGCTL			0xFFC00A00	/* Asynchronous Memory Global Control Register	*/
-#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0	*/
-#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1	*/
-#define EBIU_SDGCTL			0xFFC00A10	/* SDRAM Global Control Register				*/
-#define EBIU_SDBCTL			0xFFC00A14	/* SDRAM Bank Control Register					*/
-#define EBIU_SDRRC			0xFFC00A18	/* SDRAM Refresh Rate Control Register			*/
-#define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register						*/
-
-
-/* DMA Traffic Control Registers													*/
-#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/
-#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER			0xFFC00B0C	/* Traffic Control Periods Register			*/
-#define DMA_TCCNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/
-#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/
-#define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
-#define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
-#define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
-#define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
-#define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
-#define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
-#define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register	*/
-#define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register				*/
-#define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
-#define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register				*/
-#define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register				*/
-#define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register				*/
-
-#define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register		*/
-#define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
-#define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
-#define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
-#define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
-#define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
-#define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
-#define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register	*/
-#define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register				*/
-#define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
-#define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register				*/
-#define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register				*/
-#define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register				*/
-
-#define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register		*/
-#define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
-#define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
-#define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
-#define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
-#define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
-#define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
-#define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register	*/
-#define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register				*/
-#define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
-#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register				*/
-#define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register				*/
-#define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register				*/
-
-#define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register		*/
-#define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
-#define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
-#define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
-#define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
-#define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
-#define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
-#define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register	*/
-#define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register				*/
-#define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
-#define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register				*/
-#define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register				*/
-#define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register				*/
-
-#define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register		*/
-#define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
-#define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
-#define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
-#define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
-#define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
-#define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
-#define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register	*/
-#define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register				*/
-#define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
-#define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register				*/
-#define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register				*/
-#define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register				*/
-
-#define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register		*/
-#define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
-#define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
-#define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
-#define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
-#define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
-#define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
-#define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register	*/
-#define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register				*/
-#define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
-#define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register				*/
-#define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register				*/
-#define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register				*/
-
-#define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register		*/
-#define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
-#define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
-#define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
-#define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
-#define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
-#define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
-#define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register	*/
-#define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register				*/
-#define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
-#define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register				*/
-#define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register				*/
-#define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register				*/
-
-#define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register		*/
-#define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
-#define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
-#define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
-#define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
-#define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
-#define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
-#define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register	*/
-#define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register				*/
-#define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
-#define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register				*/
-#define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register				*/
-#define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register				*/
-
-#define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
-#define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG				0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
-#define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register				*/
-#define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register				*/
-#define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register				*/
-#define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register				*/
-
-#define DMA9_NEXT_DESC_PTR		0xFFC00E40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
-#define DMA9_START_ADDR			0xFFC00E44	/* DMA Channel 9 Start Address Register					*/
-#define DMA9_CONFIG				0xFFC00E48	/* DMA Channel 9 Configuration Register					*/
-#define DMA9_X_COUNT			0xFFC00E50	/* DMA Channel 9 X Count Register						*/
-#define DMA9_X_MODIFY			0xFFC00E54	/* DMA Channel 9 X Modify Register						*/
-#define DMA9_Y_COUNT			0xFFC00E58	/* DMA Channel 9 Y Count Register						*/
-#define DMA9_Y_MODIFY			0xFFC00E5C	/* DMA Channel 9 Y Modify Register						*/
-#define DMA9_CURR_DESC_PTR		0xFFC00E60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
-#define DMA9_CURR_ADDR			0xFFC00E64	/* DMA Channel 9 Current Address Register				*/
-#define DMA9_IRQ_STATUS			0xFFC00E68	/* DMA Channel 9 Interrupt/Status Register				*/
-#define DMA9_PERIPHERAL_MAP		0xFFC00E6C	/* DMA Channel 9 Peripheral Map Register				*/
-#define DMA9_CURR_X_COUNT		0xFFC00E70	/* DMA Channel 9 Current X Count Register				*/
-#define DMA9_CURR_Y_COUNT		0xFFC00E78	/* DMA Channel 9 Current Y Count Register				*/
-
-#define DMA10_NEXT_DESC_PTR		0xFFC00E80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
-#define DMA10_START_ADDR		0xFFC00E84	/* DMA Channel 10 Start Address Register				*/
-#define DMA10_CONFIG			0xFFC00E88	/* DMA Channel 10 Configuration Register				*/
-#define DMA10_X_COUNT			0xFFC00E90	/* DMA Channel 10 X Count Register						*/
-#define DMA10_X_MODIFY			0xFFC00E94	/* DMA Channel 10 X Modify Register						*/
-#define DMA10_Y_COUNT			0xFFC00E98	/* DMA Channel 10 Y Count Register						*/
-#define DMA10_Y_MODIFY			0xFFC00E9C	/* DMA Channel 10 Y Modify Register						*/
-#define DMA10_CURR_DESC_PTR		0xFFC00EA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
-#define DMA10_CURR_ADDR			0xFFC00EA4	/* DMA Channel 10 Current Address Register				*/
-#define DMA10_IRQ_STATUS		0xFFC00EA8	/* DMA Channel 10 Interrupt/Status Register				*/
-#define DMA10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA Channel 10 Peripheral Map Register				*/
-#define DMA10_CURR_X_COUNT		0xFFC00EB0	/* DMA Channel 10 Current X Count Register				*/
-#define DMA10_CURR_Y_COUNT		0xFFC00EB8	/* DMA Channel 10 Current Y Count Register				*/
-
-#define DMA11_NEXT_DESC_PTR		0xFFC00EC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
-#define DMA11_START_ADDR		0xFFC00EC4	/* DMA Channel 11 Start Address Register				*/
-#define DMA11_CONFIG			0xFFC00EC8	/* DMA Channel 11 Configuration Register				*/
-#define DMA11_X_COUNT			0xFFC00ED0	/* DMA Channel 11 X Count Register						*/
-#define DMA11_X_MODIFY			0xFFC00ED4	/* DMA Channel 11 X Modify Register						*/
-#define DMA11_Y_COUNT			0xFFC00ED8	/* DMA Channel 11 Y Count Register						*/
-#define DMA11_Y_MODIFY			0xFFC00EDC	/* DMA Channel 11 Y Modify Register						*/
-#define DMA11_CURR_DESC_PTR		0xFFC00EE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
-#define DMA11_CURR_ADDR			0xFFC00EE4	/* DMA Channel 11 Current Address Register				*/
-#define DMA11_IRQ_STATUS		0xFFC00EE8	/* DMA Channel 11 Interrupt/Status Register				*/
-#define DMA11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA Channel 11 Peripheral Map Register				*/
-#define DMA11_CURR_X_COUNT		0xFFC00EF0	/* DMA Channel 11 Current X Count Register				*/
-#define DMA11_CURR_Y_COUNT		0xFFC00EF8	/* DMA Channel 11 Current Y Count Register				*/
-
-#define MDMA_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register				*/
-#define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register				*/
-#define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register						*/
-#define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register					*/
-#define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register						*/
-#define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register					*/
-#define MDMA_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register				*/
-#define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register				*/
-#define MDMA_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register				*/
-#define MDMA_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register			*/
-#define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register					*/
-#define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register					*/
-#define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register							*/
-#define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register							*/
-#define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register							*/
-#define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register							*/
-#define MDMA_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register		*/
-#define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register					*/
-#define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register					*/
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register					*/
-#define MDMA_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register					*/
-#define MDMA_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register					*/
-
-#define MDMA_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register				*/
-#define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register				*/
-#define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register						*/
-#define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register					*/
-#define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register						*/
-#define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register					*/
-#define MDMA_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register				*/
-#define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register				*/
-#define MDMA_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register				*/
-#define MDMA_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register			*/
-#define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register					*/
-#define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register					*/
-#define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register							*/
-#define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register							*/
-#define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register							*/
-#define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register							*/
-#define MDMA_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register		*/
-#define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register					*/
-#define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register					*/
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register					*/
-#define MDMA_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register					*/
-#define MDMA_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register					*/
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)				*/
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register			*/
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register			*/
-#define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register	*/
-#define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register		*/
-#define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register	*/
-
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF)								*/
-#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register			*/
-#define TWI_CONTROL			0xFFC01404	/* TWI Control Register						*/
-#define TWI_SLAVE_CTL		0xFFC01408	/* Slave Mode Control Register				*/
-#define TWI_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register				*/
-#define TWI_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register				*/
-#define TWI_MASTER_CTL		0xFFC01414	/* Master Mode Control Register				*/
-#define TWI_MASTER_STAT		0xFFC01418	/* Master Mode Status Register				*/
-#define TWI_MASTER_ADDR		0xFFC0141C	/* Master Mode Address Register				*/
-#define TWI_INT_STAT		0xFFC01420	/* TWI Interrupt Status Register			*/
-#define TWI_INT_MASK		0xFFC01424	/* TWI Master Interrupt Mask Register		*/
-#define TWI_FIFO_CTL		0xFFC01428	/* FIFO Control Register					*/
-#define TWI_FIFO_STAT		0xFFC0142C	/* FIFO Status Register						*/
-#define TWI_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register	*/
-#define TWI_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register	*/
-#define TWI_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register	*/
-#define TWI_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register	*/
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)												*/
-#define PORTGIO					0xFFC01500	/* Port G I/O Pin State Specify Register				*/
-#define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register		*/
-#define PORTGIO_SET				0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register			*/
-#define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register					*/
-#define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register	*/
-#define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register			*/
-#define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register			*/
-#define PORTGIO_MASKA_TOGGLE	0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register	*/
-#define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register			*/
-#define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register			*/
-#define PORTGIO_MASKB_TOGGLE	0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTGIO_DIR				0xFFC01530	/* Port G I/O Direction Register						*/
-#define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register					*/
-#define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register				*/
-#define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register				*/
-#define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register						*/
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)												*/
-#define PORTHIO					0xFFC01700	/* Port H I/O Pin State Specify Register				*/
-#define PORTHIO_CLEAR			0xFFC01704	/* Port H I/O Peripheral Interrupt Clear Register		*/
-#define PORTHIO_SET				0xFFC01708	/* Port H I/O Peripheral Interrupt Set Register			*/
-#define PORTHIO_TOGGLE			0xFFC0170C	/* Port H I/O Pin State Toggle Register					*/
-#define PORTHIO_MASKA			0xFFC01710	/* Port H I/O Mask State Specify Interrupt A Register	*/
-#define PORTHIO_MASKA_CLEAR		0xFFC01714	/* Port H I/O Mask Disable Interrupt A Register			*/
-#define PORTHIO_MASKA_SET		0xFFC01718	/* Port H I/O Mask Enable Interrupt A Register			*/
-#define PORTHIO_MASKA_TOGGLE	0xFFC0171C	/* Port H I/O Mask Toggle Enable Interrupt A Register	*/
-#define PORTHIO_MASKB			0xFFC01720	/* Port H I/O Mask State Specify Interrupt B Register	*/
-#define PORTHIO_MASKB_CLEAR		0xFFC01724	/* Port H I/O Mask Disable Interrupt B Register			*/
-#define PORTHIO_MASKB_SET		0xFFC01728	/* Port H I/O Mask Enable Interrupt B Register			*/
-#define PORTHIO_MASKB_TOGGLE	0xFFC0172C	/* Port H I/O Mask Toggle Enable Interrupt B Register	*/
-#define PORTHIO_DIR				0xFFC01730	/* Port H I/O Direction Register						*/
-#define PORTHIO_POLAR			0xFFC01734	/* Port H I/O Source Polarity Register					*/
-#define PORTHIO_EDGE			0xFFC01738	/* Port H I/O Source Sensitivity Register				*/
-#define PORTHIO_BOTH			0xFFC0173C	/* Port H I/O Set on BOTH Edges Register				*/
-#define PORTHIO_INEN			0xFFC01740	/* Port H I/O Input Enable Register						*/
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define UART1_THR			0xFFC02000	/* Transmit Holding register			*/
-#define UART1_RBR			0xFFC02000	/* Receive Buffer register				*/
-#define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)				*/
-#define UART1_IER			0xFFC02004	/* Interrupt Enable Register			*/
-#define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)			*/
-#define UART1_IIR			0xFFC02008	/* Interrupt Identification Register	*/
-#define UART1_LCR			0xFFC0200C	/* Line Control Register				*/
-#define UART1_MCR			0xFFC02010	/* Modem Control Register				*/
-#define UART1_LSR			0xFFC02014	/* Line Status Register					*/
-#define UART1_SCR			0xFFC0201C	/* SCR Scratch Register					*/
-#define UART1_GCTL			0xFFC02024	/* Global Control Register				*/
-
-
-/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)										*/
-/* For Mailboxes 0-15																	*/
-#define CAN_MC1				0xFFC02A00	/* Mailbox config reg 1							*/
-#define CAN_MD1				0xFFC02A04	/* Mailbox direction reg 1						*/
-#define CAN_TRS1			0xFFC02A08	/* Transmit Request Set reg 1					*/
-#define CAN_TRR1			0xFFC02A0C	/* Transmit Request Reset reg 1					*/
-#define CAN_TA1				0xFFC02A10	/* Transmit Acknowledge reg 1					*/
-#define CAN_AA1				0xFFC02A14	/* Transmit Abort Acknowledge reg 1				*/
-#define CAN_RMP1			0xFFC02A18	/* Receive Message Pending reg 1				*/
-#define CAN_RML1			0xFFC02A1C	/* Receive Message Lost reg 1					*/
-#define CAN_MBTIF1			0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1		*/
-#define CAN_MBRIF1			0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1		*/
-#define CAN_MBIM1			0xFFC02A28	/* Mailbox Interrupt Mask reg 1					*/
-#define CAN_RFH1			0xFFC02A2C	/* Remote Frame Handling reg 1					*/
-#define CAN_OPSS1			0xFFC02A30	/* Overwrite Protection Single Shot Xmit reg 1	*/
-
-/* For Mailboxes 16-31   																*/
-#define CAN_MC2				0xFFC02A40	/* Mailbox config reg 2							*/
-#define CAN_MD2				0xFFC02A44	/* Mailbox direction reg 2						*/
-#define CAN_TRS2			0xFFC02A48	/* Transmit Request Set reg 2					*/
-#define CAN_TRR2			0xFFC02A4C	/* Transmit Request Reset reg 2					*/
-#define CAN_TA2				0xFFC02A50	/* Transmit Acknowledge reg 2					*/
-#define CAN_AA2				0xFFC02A54	/* Transmit Abort Acknowledge reg 2				*/
-#define CAN_RMP2			0xFFC02A58	/* Receive Message Pending reg 2				*/
-#define CAN_RML2			0xFFC02A5C	/* Receive Message Lost reg 2					*/
-#define CAN_MBTIF2			0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2		*/
-#define CAN_MBRIF2			0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2		*/
-#define CAN_MBIM2			0xFFC02A68	/* Mailbox Interrupt Mask reg 2					*/
-#define CAN_RFH2			0xFFC02A6C	/* Remote Frame Handling reg 2					*/
-#define CAN_OPSS2			0xFFC02A70	/* Overwrite Protection Single Shot Xmit reg 2	*/
-
-/* CAN Configuration, Control, and Status Registers										*/
-#define CAN_CLOCK			0xFFC02A80	/* Bit Timing Configuration register 0			*/
-#define CAN_TIMING			0xFFC02A84	/* Bit Timing Configuration register 1			*/
-#define CAN_DEBUG			0xFFC02A88	/* Debug Register								*/
-#define CAN_STATUS			0xFFC02A8C	/* Global Status Register						*/
-#define CAN_CEC				0xFFC02A90	/* Error Counter Register						*/
-#define CAN_GIS				0xFFC02A94	/* Global Interrupt Status Register				*/
-#define CAN_GIM				0xFFC02A98	/* Global Interrupt Mask Register				*/
-#define CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register				*/
-#define CAN_CONTROL			0xFFC02AA0	/* Master Control Register						*/
-#define CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register					*/
-#define CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature			*/
-#define CAN_EWR				0xFFC02AB0	/* Programmable Warning Level					*/
-#define CAN_ESR				0xFFC02AB4	/* Error Status Register						*/
-#define CAN_UCCNT			0xFFC02AC4	/* Universal Counter							*/
-#define CAN_UCRC			0xFFC02AC8	/* Universal Counter Reload/Capture	Register	*/
-#define CAN_UCCNF			0xFFC02ACC	/* Universal Counter Configuration Register		*/
-
-/* Mailbox Acceptance Masks 												*/
-#define CAN_AM00L			0xFFC02B00	/* Mailbox 0 Low Acceptance Mask	*/
-#define CAN_AM00H			0xFFC02B04	/* Mailbox 0 High Acceptance Mask	*/
-#define CAN_AM01L			0xFFC02B08	/* Mailbox 1 Low Acceptance Mask 	*/
-#define CAN_AM01H			0xFFC02B0C	/* Mailbox 1 High Acceptance Mask	*/
-#define CAN_AM02L			0xFFC02B10	/* Mailbox 2 Low Acceptance Mask 	*/
-#define CAN_AM02H			0xFFC02B14	/* Mailbox 2 High Acceptance Mask	*/
-#define CAN_AM03L			0xFFC02B18	/* Mailbox 3 Low Acceptance Mask 	*/
-#define CAN_AM03H			0xFFC02B1C	/* Mailbox 3 High Acceptance Mask	*/
-#define CAN_AM04L			0xFFC02B20	/* Mailbox 4 Low Acceptance Mask 	*/
-#define CAN_AM04H			0xFFC02B24	/* Mailbox 4 High Acceptance Mask	*/
-#define CAN_AM05L			0xFFC02B28	/* Mailbox 5 Low Acceptance Mask 	*/
-#define CAN_AM05H			0xFFC02B2C	/* Mailbox 5 High Acceptance Mask	*/
-#define CAN_AM06L			0xFFC02B30	/* Mailbox 6 Low Acceptance Mask 	*/
-#define CAN_AM06H			0xFFC02B34	/* Mailbox 6 High Acceptance Mask	*/
-#define CAN_AM07L			0xFFC02B38	/* Mailbox 7 Low Acceptance Mask 	*/
-#define CAN_AM07H			0xFFC02B3C	/* Mailbox 7 High Acceptance Mask	*/
-#define CAN_AM08L			0xFFC02B40	/* Mailbox 8 Low Acceptance Mask 	*/
-#define CAN_AM08H			0xFFC02B44	/* Mailbox 8 High Acceptance Mask	*/
-#define CAN_AM09L			0xFFC02B48	/* Mailbox 9 Low Acceptance Mask 	*/
-#define CAN_AM09H			0xFFC02B4C	/* Mailbox 9 High Acceptance Mask	*/
-#define CAN_AM10L			0xFFC02B50	/* Mailbox 10 Low Acceptance Mask 	*/
-#define CAN_AM10H			0xFFC02B54	/* Mailbox 10 High Acceptance Mask	*/
-#define CAN_AM11L			0xFFC02B58	/* Mailbox 11 Low Acceptance Mask 	*/
-#define CAN_AM11H			0xFFC02B5C	/* Mailbox 11 High Acceptance Mask	*/
-#define CAN_AM12L			0xFFC02B60	/* Mailbox 12 Low Acceptance Mask 	*/
-#define CAN_AM12H			0xFFC02B64	/* Mailbox 12 High Acceptance Mask	*/
-#define CAN_AM13L			0xFFC02B68	/* Mailbox 13 Low Acceptance Mask 	*/
-#define CAN_AM13H			0xFFC02B6C	/* Mailbox 13 High Acceptance Mask	*/
-#define CAN_AM14L			0xFFC02B70	/* Mailbox 14 Low Acceptance Mask 	*/
-#define CAN_AM14H			0xFFC02B74	/* Mailbox 14 High Acceptance Mask	*/
-#define CAN_AM15L			0xFFC02B78	/* Mailbox 15 Low Acceptance Mask 	*/
-#define CAN_AM15H			0xFFC02B7C	/* Mailbox 15 High Acceptance Mask	*/
-
-#define CAN_AM16L			0xFFC02B80	/* Mailbox 16 Low Acceptance Mask 	*/
-#define CAN_AM16H			0xFFC02B84	/* Mailbox 16 High Acceptance Mask	*/
-#define CAN_AM17L			0xFFC02B88	/* Mailbox 17 Low Acceptance Mask 	*/
-#define CAN_AM17H			0xFFC02B8C	/* Mailbox 17 High Acceptance Mask	*/
-#define CAN_AM18L			0xFFC02B90	/* Mailbox 18 Low Acceptance Mask 	*/
-#define CAN_AM18H			0xFFC02B94	/* Mailbox 18 High Acceptance Mask	*/
-#define CAN_AM19L			0xFFC02B98	/* Mailbox 19 Low Acceptance Mask 	*/
-#define CAN_AM19H			0xFFC02B9C	/* Mailbox 19 High Acceptance Mask	*/
-#define CAN_AM20L			0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask 	*/
-#define CAN_AM20H			0xFFC02BA4	/* Mailbox 20 High Acceptance Mask	*/
-#define CAN_AM21L			0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask 	*/
-#define CAN_AM21H			0xFFC02BAC	/* Mailbox 21 High Acceptance Mask	*/
-#define CAN_AM22L			0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask 	*/
-#define CAN_AM22H			0xFFC02BB4	/* Mailbox 22 High Acceptance Mask	*/
-#define CAN_AM23L			0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask 	*/
-#define CAN_AM23H			0xFFC02BBC	/* Mailbox 23 High Acceptance Mask	*/
-#define CAN_AM24L			0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask 	*/
-#define CAN_AM24H			0xFFC02BC4	/* Mailbox 24 High Acceptance Mask	*/
-#define CAN_AM25L			0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask 	*/
-#define CAN_AM25H			0xFFC02BCC	/* Mailbox 25 High Acceptance Mask	*/
-#define CAN_AM26L			0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask 	*/
-#define CAN_AM26H			0xFFC02BD4	/* Mailbox 26 High Acceptance Mask	*/
-#define CAN_AM27L			0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask 	*/
-#define CAN_AM27H			0xFFC02BDC	/* Mailbox 27 High Acceptance Mask	*/
-#define CAN_AM28L			0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask 	*/
-#define CAN_AM28H			0xFFC02BE4	/* Mailbox 28 High Acceptance Mask	*/
-#define CAN_AM29L			0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask 	*/
-#define CAN_AM29H			0xFFC02BEC	/* Mailbox 29 High Acceptance Mask	*/
-#define CAN_AM30L			0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask 	*/
-#define CAN_AM30H			0xFFC02BF4	/* Mailbox 30 High Acceptance Mask	*/
-#define CAN_AM31L			0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask 	*/
-#define CAN_AM31H			0xFFC02BFC	/* Mailbox 31 High Acceptance Mask	*/
-
-/* CAN Acceptance Mask Macros				*/
-#define CAN_AM_L(x)		(CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)		(CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers																*/
-#define CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0] Register	*/
-#define CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register	*/
-#define CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register	*/
-#define CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register	*/
-#define CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register		*/
-#define CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp Value Register		*/
-#define CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier Low Register		*/
-#define CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier High Register		*/
-
-#define CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0] Register 	*/
-#define CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register	*/
-#define CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register	*/
-#define CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register	*/
-#define CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register   	*/
-#define CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp Value Register   	*/
-#define CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier Low Register    	*/
-#define CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier High Register    	*/
-
-#define CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0] Register 	*/
-#define CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register	*/
-#define CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register	*/
-#define CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register	*/
-#define CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register   	*/
-#define CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp Value Register   	*/
-#define CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier Low Register     	*/
-#define CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier High Register    	*/
-
-#define CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0] Register 	*/
-#define CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register	*/
-#define CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register	*/
-#define CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register	*/
-#define CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register   	*/
-#define CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp Value Register   	*/
-#define CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier Low Register     	*/
-#define CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier High Register    	*/
-
-#define CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0] Register 	*/
-#define CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register	*/
-#define CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register	*/
-#define CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register	*/
-#define CAN_MB04_LENGTH		0xFFC02C90	/* Mailbox 4 Data Length Code Register   	*/
-#define CAN_MB04_TIMESTAMP	0xFFC02C94	/* Mailbox 4 Time Stamp Value Register   	*/
-#define CAN_MB04_ID0		0xFFC02C98	/* Mailbox 4 Identifier Low Register     	*/
-#define CAN_MB04_ID1		0xFFC02C9C	/* Mailbox 4 Identifier High Register    	*/
-
-#define CAN_MB05_DATA0		0xFFC02CA0	/* Mailbox 5 Data Word 0 [15:0] Register 	*/
-#define CAN_MB05_DATA1		0xFFC02CA4	/* Mailbox 5 Data Word 1 [31:16] Register	*/
-#define CAN_MB05_DATA2		0xFFC02CA8	/* Mailbox 5 Data Word 2 [47:32] Register	*/
-#define CAN_MB05_DATA3		0xFFC02CAC	/* Mailbox 5 Data Word 3 [63:48] Register	*/
-#define CAN_MB05_LENGTH		0xFFC02CB0	/* Mailbox 5 Data Length Code Register   	*/
-#define CAN_MB05_TIMESTAMP	0xFFC02CB4	/* Mailbox 5 Time Stamp Value Register   	*/
-#define CAN_MB05_ID0		0xFFC02CB8	/* Mailbox 5 Identifier Low Register     	*/
-#define CAN_MB05_ID1		0xFFC02CBC	/* Mailbox 5 Identifier High Register    	*/
-
-#define CAN_MB06_DATA0		0xFFC02CC0	/* Mailbox 6 Data Word 0 [15:0] Register 	*/
-#define CAN_MB06_DATA1		0xFFC02CC4	/* Mailbox 6 Data Word 1 [31:16] Register	*/
-#define CAN_MB06_DATA2		0xFFC02CC8	/* Mailbox 6 Data Word 2 [47:32] Register	*/
-#define CAN_MB06_DATA3		0xFFC02CCC	/* Mailbox 6 Data Word 3 [63:48] Register	*/
-#define CAN_MB06_LENGTH		0xFFC02CD0	/* Mailbox 6 Data Length Code Register   	*/
-#define CAN_MB06_TIMESTAMP	0xFFC02CD4	/* Mailbox 6 Time Stamp Value Register   	*/
-#define CAN_MB06_ID0		0xFFC02CD8	/* Mailbox 6 Identifier Low Register     	*/
-#define CAN_MB06_ID1		0xFFC02CDC	/* Mailbox 6 Identifier High Register    	*/
-
-#define CAN_MB07_DATA0		0xFFC02CE0	/* Mailbox 7 Data Word 0 [15:0] Register 	*/
-#define CAN_MB07_DATA1		0xFFC02CE4	/* Mailbox 7 Data Word 1 [31:16] Register	*/
-#define CAN_MB07_DATA2		0xFFC02CE8	/* Mailbox 7 Data Word 2 [47:32] Register	*/
-#define CAN_MB07_DATA3		0xFFC02CEC	/* Mailbox 7 Data Word 3 [63:48] Register	*/
-#define CAN_MB07_LENGTH		0xFFC02CF0	/* Mailbox 7 Data Length Code Register   	*/
-#define CAN_MB07_TIMESTAMP	0xFFC02CF4	/* Mailbox 7 Time Stamp Value Register   	*/
-#define CAN_MB07_ID0		0xFFC02CF8	/* Mailbox 7 Identifier Low Register     	*/
-#define CAN_MB07_ID1		0xFFC02CFC	/* Mailbox 7 Identifier High Register    	*/
-
-#define CAN_MB08_DATA0		0xFFC02D00	/* Mailbox 8 Data Word 0 [15:0] Register 	*/
-#define CAN_MB08_DATA1		0xFFC02D04	/* Mailbox 8 Data Word 1 [31:16] Register	*/
-#define CAN_MB08_DATA2		0xFFC02D08	/* Mailbox 8 Data Word 2 [47:32] Register	*/
-#define CAN_MB08_DATA3		0xFFC02D0C	/* Mailbox 8 Data Word 3 [63:48] Register	*/
-#define CAN_MB08_LENGTH		0xFFC02D10	/* Mailbox 8 Data Length Code Register   	*/
-#define CAN_MB08_TIMESTAMP	0xFFC02D14	/* Mailbox 8 Time Stamp Value Register   	*/
-#define CAN_MB08_ID0		0xFFC02D18	/* Mailbox 8 Identifier Low Register     	*/
-#define CAN_MB08_ID1		0xFFC02D1C	/* Mailbox 8 Identifier High Register    	*/
-
-#define CAN_MB09_DATA0		0xFFC02D20	/* Mailbox 9 Data Word 0 [15:0] Register 	*/
-#define CAN_MB09_DATA1		0xFFC02D24	/* Mailbox 9 Data Word 1 [31:16] Register	*/
-#define CAN_MB09_DATA2		0xFFC02D28	/* Mailbox 9 Data Word 2 [47:32] Register	*/
-#define CAN_MB09_DATA3		0xFFC02D2C	/* Mailbox 9 Data Word 3 [63:48] Register	*/
-#define CAN_MB09_LENGTH		0xFFC02D30	/* Mailbox 9 Data Length Code Register   	*/
-#define CAN_MB09_TIMESTAMP	0xFFC02D34	/* Mailbox 9 Time Stamp Value Register   	*/
-#define CAN_MB09_ID0		0xFFC02D38	/* Mailbox 9 Identifier Low Register     	*/
-#define CAN_MB09_ID1		0xFFC02D3C	/* Mailbox 9 Identifier High Register    	*/
-
-#define CAN_MB10_DATA0		0xFFC02D40	/* Mailbox 10 Data Word 0 [15:0] Register 	*/
-#define CAN_MB10_DATA1		0xFFC02D44	/* Mailbox 10 Data Word 1 [31:16] Register	*/
-#define CAN_MB10_DATA2		0xFFC02D48	/* Mailbox 10 Data Word 2 [47:32] Register	*/
-#define CAN_MB10_DATA3		0xFFC02D4C	/* Mailbox 10 Data Word 3 [63:48] Register	*/
-#define CAN_MB10_LENGTH		0xFFC02D50	/* Mailbox 10 Data Length Code Register   	*/
-#define CAN_MB10_TIMESTAMP	0xFFC02D54	/* Mailbox 10 Time Stamp Value Register   	*/
-#define CAN_MB10_ID0		0xFFC02D58	/* Mailbox 10 Identifier Low Register     	*/
-#define CAN_MB10_ID1		0xFFC02D5C	/* Mailbox 10 Identifier High Register    	*/
-
-#define CAN_MB11_DATA0		0xFFC02D60	/* Mailbox 11 Data Word 0 [15:0] Register 	*/
-#define CAN_MB11_DATA1		0xFFC02D64	/* Mailbox 11 Data Word 1 [31:16] Register	*/
-#define CAN_MB11_DATA2		0xFFC02D68	/* Mailbox 11 Data Word 2 [47:32] Register	*/
-#define CAN_MB11_DATA3		0xFFC02D6C	/* Mailbox 11 Data Word 3 [63:48] Register	*/
-#define CAN_MB11_LENGTH		0xFFC02D70	/* Mailbox 11 Data Length Code Register   	*/
-#define CAN_MB11_TIMESTAMP	0xFFC02D74	/* Mailbox 11 Time Stamp Value Register   	*/
-#define CAN_MB11_ID0		0xFFC02D78	/* Mailbox 11 Identifier Low Register     	*/
-#define CAN_MB11_ID1		0xFFC02D7C	/* Mailbox 11 Identifier High Register    	*/
-
-#define CAN_MB12_DATA0		0xFFC02D80	/* Mailbox 12 Data Word 0 [15:0] Register 	*/
-#define CAN_MB12_DATA1		0xFFC02D84	/* Mailbox 12 Data Word 1 [31:16] Register	*/
-#define CAN_MB12_DATA2		0xFFC02D88	/* Mailbox 12 Data Word 2 [47:32] Register	*/
-#define CAN_MB12_DATA3		0xFFC02D8C	/* Mailbox 12 Data Word 3 [63:48] Register	*/
-#define CAN_MB12_LENGTH		0xFFC02D90	/* Mailbox 12 Data Length Code Register   	*/
-#define CAN_MB12_TIMESTAMP	0xFFC02D94	/* Mailbox 12 Time Stamp Value Register   	*/
-#define CAN_MB12_ID0		0xFFC02D98	/* Mailbox 12 Identifier Low Register     	*/
-#define CAN_MB12_ID1		0xFFC02D9C	/* Mailbox 12 Identifier High Register    	*/
-
-#define CAN_MB13_DATA0		0xFFC02DA0	/* Mailbox 13 Data Word 0 [15:0] Register 	*/
-#define CAN_MB13_DATA1		0xFFC02DA4	/* Mailbox 13 Data Word 1 [31:16] Register	*/
-#define CAN_MB13_DATA2		0xFFC02DA8	/* Mailbox 13 Data Word 2 [47:32] Register	*/
-#define CAN_MB13_DATA3		0xFFC02DAC	/* Mailbox 13 Data Word 3 [63:48] Register	*/
-#define CAN_MB13_LENGTH		0xFFC02DB0	/* Mailbox 13 Data Length Code Register   	*/
-#define CAN_MB13_TIMESTAMP	0xFFC02DB4	/* Mailbox 13 Time Stamp Value Register   	*/
-#define CAN_MB13_ID0		0xFFC02DB8	/* Mailbox 13 Identifier Low Register     	*/
-#define CAN_MB13_ID1		0xFFC02DBC	/* Mailbox 13 Identifier High Register    	*/
-
-#define CAN_MB14_DATA0		0xFFC02DC0	/* Mailbox 14 Data Word 0 [15:0] Register 	*/
-#define CAN_MB14_DATA1		0xFFC02DC4	/* Mailbox 14 Data Word 1 [31:16] Register	*/
-#define CAN_MB14_DATA2		0xFFC02DC8	/* Mailbox 14 Data Word 2 [47:32] Register	*/
-#define CAN_MB14_DATA3		0xFFC02DCC	/* Mailbox 14 Data Word 3 [63:48] Register	*/
-#define CAN_MB14_LENGTH		0xFFC02DD0	/* Mailbox 14 Data Length Code Register   	*/
-#define CAN_MB14_TIMESTAMP	0xFFC02DD4	/* Mailbox 14 Time Stamp Value Register   	*/
-#define CAN_MB14_ID0		0xFFC02DD8	/* Mailbox 14 Identifier Low Register     	*/
-#define CAN_MB14_ID1		0xFFC02DDC	/* Mailbox 14 Identifier High Register    	*/
-
-#define CAN_MB15_DATA0		0xFFC02DE0	/* Mailbox 15 Data Word 0 [15:0] Register 	*/
-#define CAN_MB15_DATA1		0xFFC02DE4	/* Mailbox 15 Data Word 1 [31:16] Register	*/
-#define CAN_MB15_DATA2		0xFFC02DE8	/* Mailbox 15 Data Word 2 [47:32] Register	*/
-#define CAN_MB15_DATA3		0xFFC02DEC	/* Mailbox 15 Data Word 3 [63:48] Register	*/
-#define CAN_MB15_LENGTH		0xFFC02DF0	/* Mailbox 15 Data Length Code Register   	*/
-#define CAN_MB15_TIMESTAMP	0xFFC02DF4	/* Mailbox 15 Time Stamp Value Register   	*/
-#define CAN_MB15_ID0		0xFFC02DF8	/* Mailbox 15 Identifier Low Register     	*/
-#define CAN_MB15_ID1		0xFFC02DFC	/* Mailbox 15 Identifier High Register    	*/
-
-#define CAN_MB16_DATA0		0xFFC02E00	/* Mailbox 16 Data Word 0 [15:0] Register 	*/
-#define CAN_MB16_DATA1		0xFFC02E04	/* Mailbox 16 Data Word 1 [31:16] Register	*/
-#define CAN_MB16_DATA2		0xFFC02E08	/* Mailbox 16 Data Word 2 [47:32] Register	*/
-#define CAN_MB16_DATA3		0xFFC02E0C	/* Mailbox 16 Data Word 3 [63:48] Register	*/
-#define CAN_MB16_LENGTH		0xFFC02E10	/* Mailbox 16 Data Length Code Register   	*/
-#define CAN_MB16_TIMESTAMP	0xFFC02E14	/* Mailbox 16 Time Stamp Value Register   	*/
-#define CAN_MB16_ID0		0xFFC02E18	/* Mailbox 16 Identifier Low Register     	*/
-#define CAN_MB16_ID1		0xFFC02E1C	/* Mailbox 16 Identifier High Register    	*/
-
-#define CAN_MB17_DATA0		0xFFC02E20	/* Mailbox 17 Data Word 0 [15:0] Register 	*/
-#define CAN_MB17_DATA1		0xFFC02E24	/* Mailbox 17 Data Word 1 [31:16] Register	*/
-#define CAN_MB17_DATA2		0xFFC02E28	/* Mailbox 17 Data Word 2 [47:32] Register	*/
-#define CAN_MB17_DATA3		0xFFC02E2C	/* Mailbox 17 Data Word 3 [63:48] Register	*/
-#define CAN_MB17_LENGTH		0xFFC02E30	/* Mailbox 17 Data Length Code Register   	*/
-#define CAN_MB17_TIMESTAMP	0xFFC02E34	/* Mailbox 17 Time Stamp Value Register   	*/
-#define CAN_MB17_ID0		0xFFC02E38	/* Mailbox 17 Identifier Low Register     	*/
-#define CAN_MB17_ID1		0xFFC02E3C	/* Mailbox 17 Identifier High Register    	*/
-
-#define CAN_MB18_DATA0		0xFFC02E40	/* Mailbox 18 Data Word 0 [15:0] Register 	*/
-#define CAN_MB18_DATA1		0xFFC02E44	/* Mailbox 18 Data Word 1 [31:16] Register	*/
-#define CAN_MB18_DATA2		0xFFC02E48	/* Mailbox 18 Data Word 2 [47:32] Register	*/
-#define CAN_MB18_DATA3		0xFFC02E4C	/* Mailbox 18 Data Word 3 [63:48] Register	*/
-#define CAN_MB18_LENGTH		0xFFC02E50	/* Mailbox 18 Data Length Code Register   	*/
-#define CAN_MB18_TIMESTAMP	0xFFC02E54	/* Mailbox 18 Time Stamp Value Register   	*/
-#define CAN_MB18_ID0		0xFFC02E58	/* Mailbox 18 Identifier Low Register     	*/
-#define CAN_MB18_ID1		0xFFC02E5C	/* Mailbox 18 Identifier High Register    	*/
-
-#define CAN_MB19_DATA0		0xFFC02E60	/* Mailbox 19 Data Word 0 [15:0] Register 	*/
-#define CAN_MB19_DATA1		0xFFC02E64	/* Mailbox 19 Data Word 1 [31:16] Register	*/
-#define CAN_MB19_DATA2		0xFFC02E68	/* Mailbox 19 Data Word 2 [47:32] Register	*/
-#define CAN_MB19_DATA3		0xFFC02E6C	/* Mailbox 19 Data Word 3 [63:48] Register	*/
-#define CAN_MB19_LENGTH		0xFFC02E70	/* Mailbox 19 Data Length Code Register   	*/
-#define CAN_MB19_TIMESTAMP	0xFFC02E74	/* Mailbox 19 Time Stamp Value Register   	*/
-#define CAN_MB19_ID0		0xFFC02E78	/* Mailbox 19 Identifier Low Register     	*/
-#define CAN_MB19_ID1		0xFFC02E7C	/* Mailbox 19 Identifier High Register    	*/
-
-#define CAN_MB20_DATA0		0xFFC02E80	/* Mailbox 20 Data Word 0 [15:0] Register 	*/
-#define CAN_MB20_DATA1		0xFFC02E84	/* Mailbox 20 Data Word 1 [31:16] Register	*/
-#define CAN_MB20_DATA2		0xFFC02E88	/* Mailbox 20 Data Word 2 [47:32] Register	*/
-#define CAN_MB20_DATA3		0xFFC02E8C	/* Mailbox 20 Data Word 3 [63:48] Register	*/
-#define CAN_MB20_LENGTH		0xFFC02E90	/* Mailbox 20 Data Length Code Register   	*/
-#define CAN_MB20_TIMESTAMP	0xFFC02E94	/* Mailbox 20 Time Stamp Value Register   	*/
-#define CAN_MB20_ID0		0xFFC02E98	/* Mailbox 20 Identifier Low Register     	*/
-#define CAN_MB20_ID1		0xFFC02E9C	/* Mailbox 20 Identifier High Register    	*/
-
-#define CAN_MB21_DATA0		0xFFC02EA0	/* Mailbox 21 Data Word 0 [15:0] Register 	*/
-#define CAN_MB21_DATA1		0xFFC02EA4	/* Mailbox 21 Data Word 1 [31:16] Register	*/
-#define CAN_MB21_DATA2		0xFFC02EA8	/* Mailbox 21 Data Word 2 [47:32] Register	*/
-#define CAN_MB21_DATA3		0xFFC02EAC	/* Mailbox 21 Data Word 3 [63:48] Register	*/
-#define CAN_MB21_LENGTH		0xFFC02EB0	/* Mailbox 21 Data Length Code Register   	*/
-#define CAN_MB21_TIMESTAMP	0xFFC02EB4	/* Mailbox 21 Time Stamp Value Register   	*/
-#define CAN_MB21_ID0		0xFFC02EB8	/* Mailbox 21 Identifier Low Register     	*/
-#define CAN_MB21_ID1		0xFFC02EBC	/* Mailbox 21 Identifier High Register    	*/
-
-#define CAN_MB22_DATA0		0xFFC02EC0	/* Mailbox 22 Data Word 0 [15:0] Register 	*/
-#define CAN_MB22_DATA1		0xFFC02EC4	/* Mailbox 22 Data Word 1 [31:16] Register	*/
-#define CAN_MB22_DATA2		0xFFC02EC8	/* Mailbox 22 Data Word 2 [47:32] Register	*/
-#define CAN_MB22_DATA3		0xFFC02ECC	/* Mailbox 22 Data Word 3 [63:48] Register	*/
-#define CAN_MB22_LENGTH		0xFFC02ED0	/* Mailbox 22 Data Length Code Register   	*/
-#define CAN_MB22_TIMESTAMP	0xFFC02ED4	/* Mailbox 22 Time Stamp Value Register   	*/
-#define CAN_MB22_ID0		0xFFC02ED8	/* Mailbox 22 Identifier Low Register     	*/
-#define CAN_MB22_ID1		0xFFC02EDC	/* Mailbox 22 Identifier High Register    	*/
-
-#define CAN_MB23_DATA0		0xFFC02EE0	/* Mailbox 23 Data Word 0 [15:0] Register 	*/
-#define CAN_MB23_DATA1		0xFFC02EE4	/* Mailbox 23 Data Word 1 [31:16] Register	*/
-#define CAN_MB23_DATA2		0xFFC02EE8	/* Mailbox 23 Data Word 2 [47:32] Register	*/
-#define CAN_MB23_DATA3		0xFFC02EEC	/* Mailbox 23 Data Word 3 [63:48] Register	*/
-#define CAN_MB23_LENGTH		0xFFC02EF0	/* Mailbox 23 Data Length Code Register   	*/
-#define CAN_MB23_TIMESTAMP	0xFFC02EF4	/* Mailbox 23 Time Stamp Value Register   	*/
-#define CAN_MB23_ID0		0xFFC02EF8	/* Mailbox 23 Identifier Low Register     	*/
-#define CAN_MB23_ID1		0xFFC02EFC	/* Mailbox 23 Identifier High Register    	*/
-
-#define CAN_MB24_DATA0		0xFFC02F00	/* Mailbox 24 Data Word 0 [15:0] Register 	*/
-#define CAN_MB24_DATA1		0xFFC02F04	/* Mailbox 24 Data Word 1 [31:16] Register	*/
-#define CAN_MB24_DATA2		0xFFC02F08	/* Mailbox 24 Data Word 2 [47:32] Register	*/
-#define CAN_MB24_DATA3		0xFFC02F0C	/* Mailbox 24 Data Word 3 [63:48] Register	*/
-#define CAN_MB24_LENGTH		0xFFC02F10	/* Mailbox 24 Data Length Code Register   	*/
-#define CAN_MB24_TIMESTAMP	0xFFC02F14	/* Mailbox 24 Time Stamp Value Register   	*/
-#define CAN_MB24_ID0		0xFFC02F18	/* Mailbox 24 Identifier Low Register     	*/
-#define CAN_MB24_ID1		0xFFC02F1C	/* Mailbox 24 Identifier High Register    	*/
-
-#define CAN_MB25_DATA0		0xFFC02F20	/* Mailbox 25 Data Word 0 [15:0] Register 	*/
-#define CAN_MB25_DATA1		0xFFC02F24	/* Mailbox 25 Data Word 1 [31:16] Register	*/
-#define CAN_MB25_DATA2		0xFFC02F28	/* Mailbox 25 Data Word 2 [47:32] Register	*/
-#define CAN_MB25_DATA3		0xFFC02F2C	/* Mailbox 25 Data Word 3 [63:48] Register	*/
-#define CAN_MB25_LENGTH		0xFFC02F30	/* Mailbox 25 Data Length Code Register   	*/
-#define CAN_MB25_TIMESTAMP	0xFFC02F34	/* Mailbox 25 Time Stamp Value Register   	*/
-#define CAN_MB25_ID0		0xFFC02F38	/* Mailbox 25 Identifier Low Register     	*/
-#define CAN_MB25_ID1		0xFFC02F3C	/* Mailbox 25 Identifier High Register    	*/
-
-#define CAN_MB26_DATA0		0xFFC02F40	/* Mailbox 26 Data Word 0 [15:0] Register 	*/
-#define CAN_MB26_DATA1		0xFFC02F44	/* Mailbox 26 Data Word 1 [31:16] Register	*/
-#define CAN_MB26_DATA2		0xFFC02F48	/* Mailbox 26 Data Word 2 [47:32] Register	*/
-#define CAN_MB26_DATA3		0xFFC02F4C	/* Mailbox 26 Data Word 3 [63:48] Register	*/
-#define CAN_MB26_LENGTH		0xFFC02F50	/* Mailbox 26 Data Length Code Register   	*/
-#define CAN_MB26_TIMESTAMP	0xFFC02F54	/* Mailbox 26 Time Stamp Value Register   	*/
-#define CAN_MB26_ID0		0xFFC02F58	/* Mailbox 26 Identifier Low Register     	*/
-#define CAN_MB26_ID1		0xFFC02F5C	/* Mailbox 26 Identifier High Register    	*/
-
-#define CAN_MB27_DATA0		0xFFC02F60	/* Mailbox 27 Data Word 0 [15:0] Register 	*/
-#define CAN_MB27_DATA1		0xFFC02F64	/* Mailbox 27 Data Word 1 [31:16] Register	*/
-#define CAN_MB27_DATA2		0xFFC02F68	/* Mailbox 27 Data Word 2 [47:32] Register	*/
-#define CAN_MB27_DATA3		0xFFC02F6C	/* Mailbox 27 Data Word 3 [63:48] Register	*/
-#define CAN_MB27_LENGTH		0xFFC02F70	/* Mailbox 27 Data Length Code Register   	*/
-#define CAN_MB27_TIMESTAMP	0xFFC02F74	/* Mailbox 27 Time Stamp Value Register   	*/
-#define CAN_MB27_ID0		0xFFC02F78	/* Mailbox 27 Identifier Low Register     	*/
-#define CAN_MB27_ID1		0xFFC02F7C	/* Mailbox 27 Identifier High Register    	*/
-
-#define CAN_MB28_DATA0		0xFFC02F80	/* Mailbox 28 Data Word 0 [15:0] Register 	*/
-#define CAN_MB28_DATA1		0xFFC02F84	/* Mailbox 28 Data Word 1 [31:16] Register	*/
-#define CAN_MB28_DATA2		0xFFC02F88	/* Mailbox 28 Data Word 2 [47:32] Register	*/
-#define CAN_MB28_DATA3		0xFFC02F8C	/* Mailbox 28 Data Word 3 [63:48] Register	*/
-#define CAN_MB28_LENGTH		0xFFC02F90	/* Mailbox 28 Data Length Code Register   	*/
-#define CAN_MB28_TIMESTAMP	0xFFC02F94	/* Mailbox 28 Time Stamp Value Register   	*/
-#define CAN_MB28_ID0		0xFFC02F98	/* Mailbox 28 Identifier Low Register     	*/
-#define CAN_MB28_ID1		0xFFC02F9C	/* Mailbox 28 Identifier High Register    	*/
-
-#define CAN_MB29_DATA0		0xFFC02FA0	/* Mailbox 29 Data Word 0 [15:0] Register 	*/
-#define CAN_MB29_DATA1		0xFFC02FA4	/* Mailbox 29 Data Word 1 [31:16] Register	*/
-#define CAN_MB29_DATA2		0xFFC02FA8	/* Mailbox 29 Data Word 2 [47:32] Register	*/
-#define CAN_MB29_DATA3		0xFFC02FAC	/* Mailbox 29 Data Word 3 [63:48] Register	*/
-#define CAN_MB29_LENGTH		0xFFC02FB0	/* Mailbox 29 Data Length Code Register   	*/
-#define CAN_MB29_TIMESTAMP	0xFFC02FB4	/* Mailbox 29 Time Stamp Value Register   	*/
-#define CAN_MB29_ID0		0xFFC02FB8	/* Mailbox 29 Identifier Low Register     	*/
-#define CAN_MB29_ID1		0xFFC02FBC	/* Mailbox 29 Identifier High Register    	*/
-
-#define CAN_MB30_DATA0		0xFFC02FC0	/* Mailbox 30 Data Word 0 [15:0] Register 	*/
-#define CAN_MB30_DATA1		0xFFC02FC4	/* Mailbox 30 Data Word 1 [31:16] Register	*/
-#define CAN_MB30_DATA2		0xFFC02FC8	/* Mailbox 30 Data Word 2 [47:32] Register	*/
-#define CAN_MB30_DATA3		0xFFC02FCC	/* Mailbox 30 Data Word 3 [63:48] Register	*/
-#define CAN_MB30_LENGTH		0xFFC02FD0	/* Mailbox 30 Data Length Code Register   	*/
-#define CAN_MB30_TIMESTAMP	0xFFC02FD4	/* Mailbox 30 Time Stamp Value Register   	*/
-#define CAN_MB30_ID0		0xFFC02FD8	/* Mailbox 30 Identifier Low Register     	*/
-#define CAN_MB30_ID1		0xFFC02FDC	/* Mailbox 30 Identifier High Register    	*/
-
-#define CAN_MB31_DATA0		0xFFC02FE0	/* Mailbox 31 Data Word 0 [15:0] Register 	*/
-#define CAN_MB31_DATA1		0xFFC02FE4	/* Mailbox 31 Data Word 1 [31:16] Register	*/
-#define CAN_MB31_DATA2		0xFFC02FE8	/* Mailbox 31 Data Word 2 [47:32] Register	*/
-#define CAN_MB31_DATA3		0xFFC02FEC	/* Mailbox 31 Data Word 3 [63:48] Register	*/
-#define CAN_MB31_LENGTH		0xFFC02FF0	/* Mailbox 31 Data Length Code Register   	*/
-#define CAN_MB31_TIMESTAMP	0xFFC02FF4	/* Mailbox 31 Time Stamp Value Register   	*/
-#define CAN_MB31_ID0		0xFFC02FF8	/* Mailbox 31 Identifier Low Register     	*/
-#define CAN_MB31_ID1		0xFFC02FFC	/* Mailbox 31 Identifier High Register    	*/
-
-/* CAN Mailbox Area Macros				*/
-#define CAN_MB_ID1(x)		(CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)		(CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)	(CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)	(CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)		(CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)		(CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)		(CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)		(CAN_MB00_DATA0+((x)*0x20))
-
-
-/* Pin Control Registers	(0xFFC03200 - 0xFFC032FF)											*/
-#define PORTF_FER			0xFFC03200	/* Port F Function Enable Register (Alternate/Flag*)	*/
-#define PORTG_FER			0xFFC03204	/* Port G Function Enable Register (Alternate/Flag*)	*/
-#define PORTH_FER			0xFFC03208	/* Port H Function Enable Register (Alternate/Flag*)	*/
-#define PORT_MUX			0xFFC0320C	/* Port Multiplexer Control Register					*/
-
-
-/* Handshake MDMA Registers	(0xFFC03300 - 0xFFC033FF)										*/
-#define HMDMA0_CONTROL		0xFFC03300	/* Handshake MDMA0 Control Register					*/
-#define HMDMA0_ECINIT		0xFFC03304	/* HMDMA0 Initial Edge Count Register				*/
-#define HMDMA0_BCINIT		0xFFC03308	/* HMDMA0 Initial Block Count Register				*/
-#define HMDMA0_ECURGENT		0xFFC0330C	/* HMDMA0 Urgent Edge Count Threshhold Register		*/
-#define HMDMA0_ECOVERFLOW	0xFFC03310	/* HMDMA0 Edge Count Overflow Interrupt Register	*/
-#define HMDMA0_ECOUNT		0xFFC03314	/* HMDMA0 Current Edge Count Register				*/
-#define HMDMA0_BCOUNT		0xFFC03318	/* HMDMA0 Current Block Count Register				*/
-
-#define HMDMA1_CONTROL		0xFFC03340	/* Handshake MDMA1 Control Register					*/
-#define HMDMA1_ECINIT		0xFFC03344	/* HMDMA1 Initial Edge Count Register				*/
-#define HMDMA1_BCINIT		0xFFC03348	/* HMDMA1 Initial Block Count Register				*/
-#define HMDMA1_ECURGENT		0xFFC0334C	/* HMDMA1 Urgent Edge Count Threshhold Register		*/
-#define HMDMA1_ECOVERFLOW	0xFFC03350	/* HMDMA1 Edge Count Overflow Interrupt Register	*/
-#define HMDMA1_ECOUNT		0xFFC03354	/* HMDMA1 Current Edge Count Register				*/
-#define HMDMA1_BCOUNT		0xFFC03358	/* HMDMA1 Current Block Count Register				*/
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks																	*/
-#define DF				0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
-#define PLL_OFF			0x0002	/* PLL Not Powered									*/
-#define STOPCK			0x0008	/* Core Clock Off									*/
-#define PDWN			0x0020	/* Enter Deep Sleep Mode							*/
-#define	IN_DELAY		0x0040	/* Add 200ps Delay To EBIU Input Latches			*/
-#define	OUT_DELAY		0x0080	/* Add 200ps Delay To EBIU Output Signals			*/
-#define BYPASS			0x0100	/* Bypass the PLL									*/
-#define	MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors			*/
-#define SPORT_HYS               0x8000  /* Add 250mV of Hysteresis to SPORT Inputs */
-/* PLL_CTL Macros											*/
-#ifdef _MISRA_RULES
-#define	SET_MSEL(x)		(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#else
-#define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks														*/
-#define SSEL			0x000F	/* System Select						*/
-#define	CSEL			0x0030	/* Core Select							*/
-#define CSEL_DIV1		0x0000	/* 	CCLK = VCO / 1					*/
-#define CSEL_DIV2		0x0010	/* 	CCLK = VCO / 2					*/
-#define	CSEL_DIV4		0x0020	/* 	CCLK = VCO / 4					*/
-#define	CSEL_DIV8		0x0030	/* 	CCLK = VCO / 8					*/
-/* PLL_DIV Macros														*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)		((x)&0xFu)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#else
-#define SET_SSEL(x)		((x)&0xF)		/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks																	*/
-#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
-#define	HIBERNATE		0x0000	/* 	Powerdown/Bypass On-Board Regulation	*/
-#define	FREQ_333		0x0001	/* 	Switching Frequency Is 333 kHz			*/
-#define	FREQ_667		0x0002	/* 	Switching Frequency Is 667 kHz			*/
-#define	FREQ_1000		0x0003	/* 	Switching Frequency Is 1 MHz			*/
-
-#define GAIN			0x000C	/* Voltage Level Gain	*/
-#define	GAIN_5			0x0000	/* 	GAIN = 5		*/
-#define	GAIN_10			0x0004	/* 	GAIN = 10		*/
-#define	GAIN_20			0x0008	/* 	GAIN = 20		*/
-#define	GAIN_50			0x000C	/* 	GAIN = 50		*/
-
-#define	VLEV			0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications	*/
-#define	VLEV_085 		0x0060	/* 	VLEV = 0.85 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_090		0x0070	/* 	VLEV = 0.90 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_095		0x0080	/* 	VLEV = 0.95 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_100		0x0090	/* 	VLEV = 1.00 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_105		0x00A0	/* 	VLEV = 1.05 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_110		0x00B0	/* 	VLEV = 1.10 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_115		0x00C0	/* 	VLEV = 1.15 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_120		0x00D0	/* 	VLEV = 1.20 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_125		0x00E0	/* 	VLEV = 1.25 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_130		0x00F0	/* 	VLEV = 1.30 V (See Datasheet for Regulator Tolerance)	*/
-
-#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
-#define	CANWE			0x0200	/* Enable CAN Wakeup From Hibernate			*/
-#define	PHYWE			0x0400	/* Enable PHY Wakeup From Hibernate			*/
-#define	CLKBUFOE		0x4000	/* CLKIN Buffer Output Enable */
-#define	PHYCLKOE		CLKBUFOE	/* Alternative legacy name for the above */
-#define	SCKELOW		0x8000	/* Enable Drive CKE Low During Reset		*/
-
-/* PLL_STAT Masks																	*/
-#define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
-#define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
-#define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
-#define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
-
-/* SWRST Masks																		*/
-#define SYSTEM_RESET		0x0007	/* Initiates A System Software Reset			*/
-#define	DOUBLE_FAULT		0x0008	/* Core Double Fault Causes Reset				*/
-#define RESET_DOUBLE		0x2000	/* SW Reset Generated By Core Double-Fault		*/
-#define RESET_WDOG			0x4000	/* SW Reset Generated By Watchdog Timer			*/
-#define RESET_SOFTWARE		0x8000	/* SW Reset Occurred Since Last Read Of SWRST	*/
-
-/* SYSCR Masks																				*/
-/* SYSCR Masks */
-#define BMODE_BYPASS    0x0000   /* Bypass boot ROM, execute from 16-bit external memory */
-#define BMODE_FLASH     0x0001   /* Use Boot ROM to load from 8-bit or 16-bit flash */
-#define BMODE_SPIMEM    0x0003   /* Boot from serial SPI memory */
-#define BMODE_SPIHOST   0x0004   /* Boot from SPI0 host (slave mode) */
-#define BMODE_TWIMEM    0x0005   /* Boot from serial TWI memory */
-#define BMODE_TWIHOST   0x0006   /* Boot from TWI0 host (slave mode) */
-#define BMODE_UARTHOST  0x0007   /* Boot from UART0 host */
-#define BMODE				0x0007	/* Boot Mode - Latched During HW Reset From Mode Pins	*/
-#define	NOBOOT				0x0010	/* Execute From L1 or ASYNC Bank 0 When BMODE = 0		*/
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK										*/
-#define IRQ_PLL_WAKEUP	0x00000001	/* PLL Wakeup Interrupt			 					*/
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC			0x00000008	/* Real Time Clock Interrupt 						*/
-#define IRQ_DMA0		0x00000010	/* DMA Channel 0 (PPI) Interrupt 					*/
-#define IRQ_DMA3		0x00000020	/* DMA Channel 3 (SPORT0 RX) Interrupt 				*/
-#define IRQ_DMA4		0x00000040	/* DMA Channel 4 (SPORT0 TX) Interrupt 				*/
-#define IRQ_DMA5		0x00000080	/* DMA Channel 5 (SPORT1 RX) Interrupt 				*/
-
-#define IRQ_DMA6		0x00000100	/* DMA Channel 6 (SPORT1 TX) Interrupt 		 		*/
-#define IRQ_TWI			0x00000200	/* TWI Interrupt									*/
-#define IRQ_DMA7		0x00000400	/* DMA Channel 7 (SPI) Interrupt 					*/
-#define IRQ_DMA8		0x00000800	/* DMA Channel 8 (UART0 RX) Interrupt 				*/
-#define IRQ_DMA9		0x00001000	/* DMA Channel 9 (UART0 TX) Interrupt 				*/
-#define IRQ_DMA10		0x00002000	/* DMA Channel 10 (UART1 RX) Interrupt 				*/
-#define IRQ_DMA11		0x00004000	/* DMA Channel 11 (UART1 TX) Interrupt 				*/
-#define IRQ_CAN_RX		0x00008000	/* CAN Receive Interrupt 							*/
-
-#define IRQ_CAN_TX		0x00010000	/* CAN Transmit Interrupt  							*/
-#define IRQ_DMA1		0x00020000	/* DMA Channel 1 (Ethernet RX) Interrupt 			*/
-#define IRQ_PFA_PORTH	0x00020000	/* PF Port H (PF47:32) Interrupt A 					*/
-#define IRQ_DMA2		0x00040000	/* DMA Channel 2 (Ethernet TX) Interrupt 			*/
-#define IRQ_PFB_PORTH	0x00040000	/* PF Port H (PF47:32) Interrupt B 					*/
-#define IRQ_TIMER0		0x00080000	/* Timer 0 Interrupt								*/
-#define IRQ_TIMER1		0x00100000	/* Timer 1 Interrupt 								*/
-#define IRQ_TIMER2		0x00200000	/* Timer 2 Interrupt 								*/
-#define IRQ_TIMER3		0x00400000	/* Timer 3 Interrupt 								*/
-#define IRQ_TIMER4		0x00800000	/* Timer 4 Interrupt 								*/
-
-#define IRQ_TIMER5		0x01000000	/* Timer 5 Interrupt 								*/
-#define IRQ_TIMER6		0x02000000	/* Timer 6 Interrupt 								*/
-#define IRQ_TIMER7		0x04000000	/* Timer 7 Interrupt 								*/
-#define IRQ_PFA_PORTFG	0x08000000	/* PF Ports F&G (PF31:0) Interrupt A 				*/
-#define IRQ_PFB_PORTF	0x80000000	/* PF Port F (PF15:0) Interrupt B 					*/
-#define IRQ_DMA12		0x20000000	/* DMA Channels 12 (MDMA1 Source) RX Interrupt 		*/
-#define IRQ_DMA13		0x20000000	/* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14		0x40000000	/* DMA Channels 14 (MDMA0 Source) RX Interrupt 		*/
-#define IRQ_DMA15		0x40000000	/* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG		0x80000000	/* Software Watchdog Timer Interrupt 				*/
-#define IRQ_PFB_PORTG	0x10000000	/* PF Port G (PF31:16) Interrupt B 					*/
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IAR0 Macros															*/
-#define P0_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #0 assigned IVG #x 	*/
-#define P1_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #1 assigned IVG #x 	*/
-#define P2_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #2 assigned IVG #x 	*/
-#define P3_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #3 assigned IVG #x	*/
-#define P4_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #4 assigned IVG #x	*/
-#define P5_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #5 assigned IVG #x	*/
-#define P6_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #6 assigned IVG #x	*/
-#define P7_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #7 assigned IVG #x	*/
-
-/* SIC_IAR1 Macros															*/
-#define P8_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #8 assigned IVG #x 	*/
-#define P9_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #9 assigned IVG #x 	*/
-#define P10_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #10 assigned IVG #x	*/
-#define P11_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #11 assigned IVG #x 	*/
-#define P12_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #12 assigned IVG #x	*/
-#define P13_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #13 assigned IVG #x	*/
-#define P14_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #14 assigned IVG #x	*/
-#define P15_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #15 assigned IVG #x	*/
-
-/* SIC_IAR2 Macros															*/
-#define P16_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #16 assigned IVG #x	*/
-#define P17_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #17 assigned IVG #x	*/
-#define P18_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #18 assigned IVG #x	*/
-#define P19_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #19 assigned IVG #x	*/
-#define P20_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #20 assigned IVG #x	*/
-#define P21_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #21 assigned IVG #x	*/
-#define P22_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #22 assigned IVG #x	*/
-#define P23_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #23 assigned IVG #x	*/
-
-/* SIC_IAR3 Macros															*/
-#define P24_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #24 assigned IVG #x	*/
-#define P25_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #25 assigned IVG #x	*/
-#define P26_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #26 assigned IVG #x	*/
-#define P27_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #27 assigned IVG #x	*/
-#define P28_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #28 assigned IVG #x	*/
-#define P29_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #29 assigned IVG #x	*/
-#define P30_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #30 assigned IVG #x	*/
-#define P31_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #31 assigned IVG #x	*/
-
-/* SIC_IMASK Masks*/
-#define SIC_UNMASK_ALL 0x00000000         /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL   0xFFFFFFFF         /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F))     /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR Masks*/
-#define IWR_DISABLE_ALL 0x00000000        /* Wakeup Disable all peripherals   */
-#define IWR_ENABLE_ALL  0xFFFFFFFF        /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#ifdef _MISRA_RULES
-#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
-#else
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define WDOG_DISABLE  WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks										*/
-#define	RTC_SEC				0x0000003F	/* Real-Time Clock Seconds	*/
-#define	RTC_MIN				0x00000FC0	/* Real-Time Clock Minutes	*/
-#define	RTC_HR				0x0001F000	/* Real-Time Clock Hours	*/
-#define	RTC_DAY				0xFFFE0000	/* Real-Time Clock Days		*/
-
-/* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* RTC_ICTL and RTC_ISTAT Masks																		*/
-#define	STOPWATCH			0x0001		/* Stopwatch Interrupt Enable								*/
-#define	ALARM				0x0002		/* Alarm Interrupt Enable									*/
-#define	SECOND				0x0004		/* Seconds (1 Hz) Interrupt Enable							*/
-#define	MINUTE				0x0008		/* Minutes Interrupt Enable									*/
-#define	HOUR				0x0010		/* Hours Interrupt Enable									*/
-#define	DAY					0x0020		/* 24 Hours (Days) Interrupt Enable							*/
-#define	DAY_ALARM			0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
-#define	WRITE_PENDING		0x4000		/* Write Pending Status										*/
-#define	WRITE_COMPLETE		0x8000		/* Write Complete Interrupt Enable							*/
-
-/* RTC_FAST / RTC_PREN Mask												*/
-#define PREN				0x0001	/* Enable Prescaler, RTC Runs @1 Hz	*/
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks												*/
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select */
-#else
-#define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB			0x04				/* Stop Bits			*/
-#define PEN			0x08				/* Parity Enable		*/
-#define EPS			0x10				/* Even Parity Select	*/
-#define STP			0x20				/* Stick Parity			*/
-#define SB			0x40				/* Set Break			*/
-#define DLAB		0x80				/* Divisor Latch Access	*/
-
-/* UARTx_MCR Mask										*/
-#define LOOP_ENA	0x10	/* Loopback Mode Enable */
-#define LOOP_ENA_P	0x04
-
-/* UARTx_LSR Masks										*/
-#define DR			0x01	/* Data Ready				*/
-#define OE			0x02	/* Overrun Error			*/
-#define PE			0x04	/* Parity Error				*/
-#define FE			0x08	/* Framing Error			*/
-#define BI			0x10	/* Break Interrupt			*/
-#define THRE		0x20	/* THR Empty				*/
-#define TEMT		0x40	/* TSR and UART_THR Empty	*/
-
-/* UARTx_IER Masks															*/
-#define ERBFI		0x01		/* Enable Receive Buffer Full Interrupt		*/
-#define ETBEI		0x02		/* Enable Transmit Buffer Empty Interrupt	*/
-#define ELSI		0x04		/* Enable RX Status Interrupt				*/
-
-/* UARTx_IIR Masks														*/
-#define NINT		0x01		/* Pending Interrupt					*/
-#define STATUS		0x06		/* Highest Priority Pending Interrupt	*/
-
-/* UARTx_GCTL Masks													*/
-#define UCEN		0x01		/* Enable UARTx Clocks				*/
-#define IREN		0x02		/* Enable IrDA Mode					*/
-#define TPOLC		0x04		/* IrDA TX Polarity Change			*/
-#define RPOLC		0x08		/* IrDA RX Polarity Change			*/
-#define FPE			0x10		/* Force Parity Error On Transmit	*/
-#define FFE			0x20		/* Force Framing Error On Transmit	*/
-
-/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
-#define UARTDLL                 0x00FF              /* Divisor Latch Low Byte */
-#define UARTDLH                 0xFF00              /* Divisor Latch High Byte */
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks																	*/
-#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/
-#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/
-#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/
-#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/
-#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/
-#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/
-#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/
-#define PSSE		0x0010		/* Slave-Select Input Enable						*/
-#define EMISO		0x0020		/* Enable MISO As Output							*/
-#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/
-#define LSBF		0x0200		/* LSB First										*/
-#define CPHA		0x0400		/* Clock Phase										*/
-#define CPOL		0x0800		/* Clock Polarity									*/
-#define MSTR		0x1000		/* Master/Slave*									*/
-#define WOM			0x2000		/* Write Open Drain Master							*/
-#define SPE			0x4000		/* SPI Enable										*/
-
-/* SPI_FLG Masks																	*/
-#define FLS1		0x0002		/* Enables SPI_FLOUT1 as SPI Slave-Select Output	*/
-#define FLS2		0x0004		/* Enables SPI_FLOUT2 as SPI Slave-Select Output	*/
-#define FLS3		0x0008		/* Enables SPI_FLOUT3 as SPI Slave-Select Output	*/
-#define FLS4		0x0010		/* Enables SPI_FLOUT4 as SPI Slave-Select Output	*/
-#define FLS5		0x0020		/* Enables SPI_FLOUT5 as SPI Slave-Select Output	*/
-#define FLS6		0x0040		/* Enables SPI_FLOUT6 as SPI Slave-Select Output	*/
-#define FLS7		0x0080		/* Enables SPI_FLOUT7 as SPI Slave-Select Output	*/
-#define FLG1		0xFDFF		/* Activates SPI_FLOUT1 							*/
-#define FLG2		0xFBFF		/* Activates SPI_FLOUT2								*/
-#define FLG3		0xF7FF		/* Activates SPI_FLOUT3								*/
-#define FLG4		0xEFFF		/* Activates SPI_FLOUT4								*/
-#define FLG5		0xDFFF		/* Activates SPI_FLOUT5								*/
-#define FLG6		0xBFFF		/* Activates SPI_FLOUT6								*/
-#define FLG7		0x7FFF		/* Activates SPI_FLOUT7								*/
-
-/* SPI_STAT Masks																				*/
-#define SPIF		0x0001		/* SPI Finished (Single-Word Transfer Complete)					*/
-#define MODF		0x0002		/* Mode Fault Error (Another Device Tried To Become Master)		*/
-#define TXE			0x0004		/* Transmission Error (Data Sent With No New Data In TDBR)		*/
-#define TXS			0x0008		/* SPI_TDBR Data Buffer Status (Full/Empty*)					*/
-#define RBSY		0x0010		/* Receive Error (Data Received With RDBR Full)					*/
-#define RXS			0x0020		/* SPI_RDBR Data Buffer Status (Full/Empty*)					*/
-#define TXCOL		0x0040		/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks													*/
-#define TIMEN0			0x0001		/* Enable Timer 0					*/
-#define TIMEN1			0x0002		/* Enable Timer 1					*/
-#define TIMEN2			0x0004		/* Enable Timer 2					*/
-#define TIMEN3			0x0008		/* Enable Timer 3					*/
-#define TIMEN4			0x0010		/* Enable Timer 4					*/
-#define TIMEN5			0x0020		/* Enable Timer 5					*/
-#define TIMEN6			0x0040		/* Enable Timer 6					*/
-#define TIMEN7			0x0080		/* Enable Timer 7					*/
-
-/* TIMER_DISABLE Masks													*/
-#define TIMDIS0			TIMEN0		/* Disable Timer 0					*/
-#define TIMDIS1			TIMEN1		/* Disable Timer 1					*/
-#define TIMDIS2			TIMEN2		/* Disable Timer 2					*/
-#define TIMDIS3			TIMEN3		/* Disable Timer 3					*/
-#define TIMDIS4			TIMEN4		/* Disable Timer 4					*/
-#define TIMDIS5			TIMEN5		/* Disable Timer 5					*/
-#define TIMDIS6			TIMEN6		/* Disable Timer 6					*/
-#define TIMDIS7			TIMEN7		/* Disable Timer 7					*/
-
-/* TIMER_STATUS Masks													*/
-#define TIMIL0			0x00000001	/* Timer 0 Interrupt				*/
-#define TIMIL1			0x00000002	/* Timer 1 Interrupt				*/
-#define TIMIL2			0x00000004	/* Timer 2 Interrupt				*/
-#define TIMIL3			0x00000008	/* Timer 3 Interrupt				*/
-#define TOVF_ERR0		0x00000010	/* Timer 0 Counter Overflow			*/
-#define TOVF_ERR1		0x00000020	/* Timer 1 Counter Overflow			*/
-#define TOVF_ERR2		0x00000040	/* Timer 2 Counter Overflow			*/
-#define TOVF_ERR3		0x00000080	/* Timer 3 Counter Overflow			*/
-#define TRUN0			0x00001000	/* Timer 0 Slave Enable Status		*/
-#define TRUN1			0x00002000	/* Timer 1 Slave Enable Status		*/
-#define TRUN2			0x00004000	/* Timer 2 Slave Enable Status		*/
-#define TRUN3			0x00008000	/* Timer 3 Slave Enable Status		*/
-#define TIMIL4			0x00010000	/* Timer 4 Interrupt				*/
-#define TIMIL5			0x00020000	/* Timer 5 Interrupt				*/
-#define TIMIL6			0x00040000	/* Timer 6 Interrupt				*/
-#define TIMIL7			0x00080000	/* Timer 7 Interrupt				*/
-#define TOVF_ERR4		0x00100000	/* Timer 4 Counter Overflow			*/
-#define TOVF_ERR5		0x00200000	/* Timer 5 Counter Overflow			*/
-#define TOVF_ERR6		0x00400000	/* Timer 6 Counter Overflow			*/
-#define TOVF_ERR7		0x00800000	/* Timer 7 Counter Overflow			*/
-#define TRUN4			0x10000000	/* Timer 4 Slave Enable Status		*/
-#define TRUN5			0x20000000	/* Timer 5 Slave Enable Status		*/
-#define TRUN6			0x40000000	/* Timer 6 Slave Enable Status		*/
-#define TRUN7			0x80000000	/* Timer 7 Slave Enable Status		*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks													*/
-#define PWM_OUT			0x0001	/* Pulse-Width Modulation Output Mode	*/
-#define WDTH_CAP		0x0002	/* Width Capture Input Mode				*/
-#define EXT_CLK			0x0003	/* External Clock Mode					*/
-#define PULSE_HI		0x0004	/* Action Pulse (Positive/Negative*)	*/
-#define PERIOD_CNT		0x0008	/* Period Count							*/
-#define IRQ_ENA			0x0010	/* Interrupt Request Enable				*/
-#define TIN_SEL			0x0020	/* Timer Input Select					*/
-#define OUT_DIS			0x0040	/* Output Pad Disable					*/
-#define CLK_SEL			0x0080	/* Timer Clock Select					*/
-#define TOGGLE_HI		0x0100	/* PWM_OUT PULSE_HI Toggle Mode			*/
-#define EMU_RUN			0x0200	/* Emulation Behavior Select			*/
-#define ERR_TYP			0xC000	/* Error Type							*/
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks 				*/
-/* Port F Masks 														*/
-#define PF0		0x0001
-#define PF1		0x0002
-#define PF2		0x0004
-#define PF3		0x0008
-#define PF4		0x0010
-#define PF5		0x0020
-#define PF6		0x0040
-#define PF7		0x0080
-#define PF8		0x0100
-#define PF9		0x0200
-#define PF10	0x0400
-#define PF11	0x0800
-#define PF12	0x1000
-#define PF13	0x2000
-#define PF14	0x4000
-#define PF15	0x8000
-
-/* Port G Masks															*/
-#define PG0		0x0001
-#define PG1		0x0002
-#define PG2		0x0004
-#define PG3		0x0008
-#define PG4		0x0010
-#define PG5		0x0020
-#define PG6		0x0040
-#define PG7		0x0080
-#define PG8		0x0100
-#define PG9		0x0200
-#define PG10	0x0400
-#define PG11	0x0800
-#define PG12	0x1000
-#define PG13	0x2000
-#define PG14	0x4000
-#define PG15	0x8000
-
-/* Port H Masks															*/
-#define PH0		0x0001
-#define PH1		0x0002
-#define PH2		0x0004
-#define PH3		0x0008
-#define PH4		0x0010
-#define PH5		0x0020
-#define PH6		0x0040
-#define PH7		0x0080
-#define PH8		0x0100
-#define PH9		0x0200
-#define PH10	0x0400
-#define PH11	0x0800
-#define PH12	0x1000
-#define PH13	0x2000
-#define PH14	0x4000
-#define PH15	0x8000
-
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks															*/
-#define TSPEN		0x0001		/* Transmit Enable								*/
-#define ITCLK		0x0002		/* Internal Transmit Clock Select				*/
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define TLSBIT		0x0010		/* Transmit Bit Order							*/
-#define ITFS		0x0200		/* Internal Transmit Frame Sync Select			*/
-#define TFSR		0x0400		/* Transmit Frame Sync Required Select			*/
-#define DITFS		0x0800		/* Data-Independent Transmit Frame Sync Select	*/
-#define LTFS		0x1000		/* Low Transmit Frame Sync Select				*/
-#define LATFS		0x2000		/* Late Transmit Frame Sync Select				*/
-#define TCKFE		0x4000		/* Clock Falling Edge Select					*/
-
-/* SPORTx_TCR2 Masks and Macro													*/
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#define TXSE		0x0100		/* TX Secondary Enable							*/
-#define TSFSE		0x0200		/* Transmit Stereo Frame Sync Enable			*/
-#define TRFST		0x0400		/* Left/Right Order (1 = Right Channel 1st)		*/
-
-/* SPORTx_RCR1 Masks															*/
-#define RSPEN		0x0001		/* Receive Enable 								*/
-#define IRCLK		0x0002		/* Internal Receive Clock Select 				*/
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define RLSBIT		0x0010		/* Receive Bit Order							*/
-#define IRFS		0x0200		/* Internal Receive Frame Sync Select 			*/
-#define RFSR		0x0400		/* Receive Frame Sync Required Select 			*/
-#define LRFS		0x1000		/* Low Receive Frame Sync Select 				*/
-#define LARFS		0x2000		/* Late Receive Frame Sync Select 				*/
-#define RCKFE		0x4000		/* Clock Falling Edge Select 					*/
-
-/* SPORTx_RCR2 Masks															*/
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT RX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#define RXSE		0x0100		/* RX Secondary Enable							*/
-#define RSFSE		0x0200		/* RX Stereo Frame Sync Enable					*/
-#define RRFST		0x0400		/* Right-First Data Order 						*/
-
-/* SPORTx_STAT Masks															*/
-#define RXNE		0x0001		/* Receive FIFO Not Empty Status				*/
-#define RUVF		0x0002		/* Sticky Receive Underflow Status				*/
-#define ROVF		0x0004		/* Sticky Receive Overflow Status				*/
-#define TXF			0x0008		/* Transmit FIFO Full Status					*/
-#define TUVF		0x0010		/* Sticky Transmit Underflow Status				*/
-#define TOVF		0x0020		/* Sticky Transmit Overflow Status				*/
-#define TXHRE		0x0040		/* Transmit Hold Register Empty					*/
-
-/* SPORTx_MCMC1 Macros															*/
-#ifdef _MISRA_RULES
-#define WOFF(x)		((x) & 0x3FFu) 	/* Multichannel Window Offset Field			*/
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define WSIZE(x)	(((((x)>>0x3)-1u)&0xFu) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#else
-#define WOFF(x)		((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#endif /* _MISRA_RULES */
-
-/* SPORTx_MCMC2 Masks															*/
-#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/
-#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/
-#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/
-#define MCDTXPE		0x0004 		/* Multichannel DMA Transmit Packing			*/
-#define MCDRXPE		0x0008 		/* Multichannel DMA Receive Packing				*/
-#define MCMEN		0x0010 		/* Multichannel Frame Mode Enable				*/
-#define FSDR		0x0080 		/* Multichannel Frame Sync to Data Relationship	*/
-#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/
-#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/
-#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/
-#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/
-#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/
-#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/
-#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/
-#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/
-#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/
-#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/
-#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/
-#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/
-#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/
-#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/
-#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/
-#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks																	*/
-#define AMCKEN			0x0001		/* Enable CLKOUT									*/
-#define	AMBEN_NONE		0x0000		/* All Banks Disabled								*/
-#define AMBEN_B0		0x0002		/* Enable Async Memory Bank 0 only					*/
-#define AMBEN_B0_B1		0x0004		/* Enable Async Memory Banks 0 & 1 only				*/
-#define AMBEN_B0_B1_B2		0x0006		/* Enable Async Memory Banks 0, 1, and 2			*/
-#define AMBEN_ALL		0x0008		/* Enable Async Memory Banks (all) 0, 1, 2, and 3	*/
-#define CDPRIO                  0x0100      	/* DMA has priority over core for for external accesses */
-
-/* EBIU_AMBCTL0 Masks																	*/
-#define B0RDYEN			0x00000001  /* Bank 0 (B0) RDY Enable							*/
-#define B0RDYPOL		0x00000002  /* B0 RDY Active High								*/
-#define B0TT_1			0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle		*/
-#define B0TT_2			0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles	*/
-#define B0TT_3			0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles	*/
-#define B0TT_4			0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles	*/
-#define B0ST_1			0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B0ST_2			0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B0ST_3			0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B0ST_4			0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B0HT_1			0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B0HT_2			0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B0HT_3			0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B0HT_0			0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B0RAT_1			0x00000100  /* B0 Read Access Time = 1 cycle					*/
-#define B0RAT_2			0x00000200  /* B0 Read Access Time = 2 cycles					*/
-#define B0RAT_3			0x00000300  /* B0 Read Access Time = 3 cycles					*/
-#define B0RAT_4			0x00000400  /* B0 Read Access Time = 4 cycles					*/
-#define B0RAT_5			0x00000500  /* B0 Read Access Time = 5 cycles					*/
-#define B0RAT_6			0x00000600  /* B0 Read Access Time = 6 cycles					*/
-#define B0RAT_7			0x00000700  /* B0 Read Access Time = 7 cycles					*/
-#define B0RAT_8			0x00000800  /* B0 Read Access Time = 8 cycles					*/
-#define B0RAT_9			0x00000900  /* B0 Read Access Time = 9 cycles					*/
-#define B0RAT_10		0x00000A00  /* B0 Read Access Time = 10 cycles					*/
-#define B0RAT_11		0x00000B00  /* B0 Read Access Time = 11 cycles					*/
-#define B0RAT_12		0x00000C00  /* B0 Read Access Time = 12 cycles					*/
-#define B0RAT_13		0x00000D00  /* B0 Read Access Time = 13 cycles					*/
-#define B0RAT_14		0x00000E00  /* B0 Read Access Time = 14 cycles					*/
-#define B0RAT_15		0x00000F00  /* B0 Read Access Time = 15 cycles					*/
-#define B0WAT_1			0x00001000  /* B0 Write Access Time = 1 cycle					*/
-#define B0WAT_2			0x00002000  /* B0 Write Access Time = 2 cycles					*/
-#define B0WAT_3			0x00003000  /* B0 Write Access Time = 3 cycles					*/
-#define B0WAT_4			0x00004000  /* B0 Write Access Time = 4 cycles					*/
-#define B0WAT_5			0x00005000  /* B0 Write Access Time = 5 cycles					*/
-#define B0WAT_6			0x00006000  /* B0 Write Access Time = 6 cycles					*/
-#define B0WAT_7			0x00007000  /* B0 Write Access Time = 7 cycles					*/
-#define B0WAT_8			0x00008000  /* B0 Write Access Time = 8 cycles					*/
-#define B0WAT_9			0x00009000  /* B0 Write Access Time = 9 cycles					*/
-#define B0WAT_10		0x0000A000  /* B0 Write Access Time = 10 cycles					*/
-#define B0WAT_11		0x0000B000  /* B0 Write Access Time = 11 cycles					*/
-#define B0WAT_12		0x0000C000  /* B0 Write Access Time = 12 cycles					*/
-#define B0WAT_13		0x0000D000  /* B0 Write Access Time = 13 cycles					*/
-#define B0WAT_14		0x0000E000  /* B0 Write Access Time = 14 cycles					*/
-#define B0WAT_15		0x0000F000  /* B0 Write Access Time = 15 cycles					*/
-
-#define B1RDYEN			0x00010000  /* Bank 1 (B1) RDY Enable                       	*/
-#define B1RDYPOL		0x00020000  /* B1 RDY Active High                           	*/
-#define B1TT_1			0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle 	*/
-#define B1TT_2			0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles	*/
-#define B1TT_3			0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles	*/
-#define B1TT_4			0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles	*/
-#define B1ST_1			0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle  	*/
-#define B1ST_2			0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles 	*/
-#define B1ST_3			0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles 	*/
-#define B1ST_4			0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles 	*/
-#define B1HT_1			0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle 	*/
-#define B1HT_2			0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B1HT_3			0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B1HT_0			0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B1RAT_1			0x01000000  /* B1 Read Access Time = 1 cycle					*/
-#define B1RAT_2			0x02000000  /* B1 Read Access Time = 2 cycles					*/
-#define B1RAT_3			0x03000000  /* B1 Read Access Time = 3 cycles					*/
-#define B1RAT_4			0x04000000  /* B1 Read Access Time = 4 cycles					*/
-#define B1RAT_5			0x05000000  /* B1 Read Access Time = 5 cycles					*/
-#define B1RAT_6			0x06000000  /* B1 Read Access Time = 6 cycles					*/
-#define B1RAT_7			0x07000000  /* B1 Read Access Time = 7 cycles					*/
-#define B1RAT_8			0x08000000  /* B1 Read Access Time = 8 cycles					*/
-#define B1RAT_9			0x09000000  /* B1 Read Access Time = 9 cycles					*/
-#define B1RAT_10		0x0A000000  /* B1 Read Access Time = 10 cycles					*/
-#define B1RAT_11		0x0B000000  /* B1 Read Access Time = 11 cycles					*/
-#define B1RAT_12		0x0C000000  /* B1 Read Access Time = 12 cycles					*/
-#define B1RAT_13		0x0D000000  /* B1 Read Access Time = 13 cycles					*/
-#define B1RAT_14		0x0E000000  /* B1 Read Access Time = 14 cycles					*/
-#define B1RAT_15		0x0F000000  /* B1 Read Access Time = 15 cycles					*/
-#define B1WAT_1			0x10000000  /* B1 Write Access Time = 1 cycle					*/
-#define B1WAT_2			0x20000000  /* B1 Write Access Time = 2 cycles					*/
-#define B1WAT_3			0x30000000  /* B1 Write Access Time = 3 cycles					*/
-#define B1WAT_4			0x40000000  /* B1 Write Access Time = 4 cycles					*/
-#define B1WAT_5			0x50000000  /* B1 Write Access Time = 5 cycles					*/
-#define B1WAT_6			0x60000000  /* B1 Write Access Time = 6 cycles					*/
-#define B1WAT_7			0x70000000  /* B1 Write Access Time = 7 cycles					*/
-#define B1WAT_8			0x80000000  /* B1 Write Access Time = 8 cycles					*/
-#define B1WAT_9			0x90000000  /* B1 Write Access Time = 9 cycles					*/
-#define B1WAT_10		0xA0000000  /* B1 Write Access Time = 10 cycles					*/
-#define B1WAT_11		0xB0000000  /* B1 Write Access Time = 11 cycles					*/
-#define B1WAT_12		0xC0000000  /* B1 Write Access Time = 12 cycles					*/
-#define B1WAT_13		0xD0000000  /* B1 Write Access Time = 13 cycles					*/
-#define B1WAT_14		0xE0000000  /* B1 Write Access Time = 14 cycles					*/
-#define B1WAT_15		0xF0000000  /* B1 Write Access Time = 15 cycles					*/
-
-/* EBIU_AMBCTL1 Masks																	*/
-#define B2RDYEN			0x00000001  /* Bank 2 (B2) RDY Enable							*/
-#define B2RDYPOL		0x00000002  /* B2 RDY Active High								*/
-#define B2TT_1			0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle		*/
-#define B2TT_2			0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles	*/
-#define B2TT_3			0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles	*/
-#define B2TT_4			0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles	*/
-#define B2ST_1			0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B2ST_2			0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B2ST_3			0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B2ST_4			0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B2HT_1			0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B2HT_2			0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B2HT_3			0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B2HT_0			0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B2RAT_1			0x00000100  /* B2 Read Access Time = 1 cycle					*/
-#define B2RAT_2			0x00000200  /* B2 Read Access Time = 2 cycles					*/
-#define B2RAT_3			0x00000300  /* B2 Read Access Time = 3 cycles					*/
-#define B2RAT_4			0x00000400  /* B2 Read Access Time = 4 cycles					*/
-#define B2RAT_5			0x00000500  /* B2 Read Access Time = 5 cycles					*/
-#define B2RAT_6			0x00000600  /* B2 Read Access Time = 6 cycles					*/
-#define B2RAT_7			0x00000700  /* B2 Read Access Time = 7 cycles					*/
-#define B2RAT_8			0x00000800  /* B2 Read Access Time = 8 cycles					*/
-#define B2RAT_9			0x00000900  /* B2 Read Access Time = 9 cycles					*/
-#define B2RAT_10		0x00000A00  /* B2 Read Access Time = 10 cycles					*/
-#define B2RAT_11		0x00000B00  /* B2 Read Access Time = 11 cycles					*/
-#define B2RAT_12		0x00000C00  /* B2 Read Access Time = 12 cycles					*/
-#define B2RAT_13		0x00000D00  /* B2 Read Access Time = 13 cycles					*/
-#define B2RAT_14		0x00000E00  /* B2 Read Access Time = 14 cycles					*/
-#define B2RAT_15		0x00000F00  /* B2 Read Access Time = 15 cycles					*/
-#define B2WAT_1			0x00001000  /* B2 Write Access Time = 1 cycle					*/
-#define B2WAT_2			0x00002000  /* B2 Write Access Time = 2 cycles					*/
-#define B2WAT_3			0x00003000  /* B2 Write Access Time = 3 cycles					*/
-#define B2WAT_4			0x00004000  /* B2 Write Access Time = 4 cycles					*/
-#define B2WAT_5			0x00005000  /* B2 Write Access Time = 5 cycles					*/
-#define B2WAT_6			0x00006000  /* B2 Write Access Time = 6 cycles					*/
-#define B2WAT_7			0x00007000  /* B2 Write Access Time = 7 cycles					*/
-#define B2WAT_8			0x00008000  /* B2 Write Access Time = 8 cycles					*/
-#define B2WAT_9			0x00009000  /* B2 Write Access Time = 9 cycles					*/
-#define B2WAT_10		0x0000A000  /* B2 Write Access Time = 10 cycles					*/
-#define B2WAT_11		0x0000B000  /* B2 Write Access Time = 11 cycles					*/
-#define B2WAT_12		0x0000C000  /* B2 Write Access Time = 12 cycles					*/
-#define B2WAT_13		0x0000D000  /* B2 Write Access Time = 13 cycles					*/
-#define B2WAT_14		0x0000E000  /* B2 Write Access Time = 14 cycles					*/
-#define B2WAT_15		0x0000F000  /* B2 Write Access Time = 15 cycles					*/
-
-#define B3RDYEN			0x00010000  /* Bank 3 (B3) RDY Enable							*/
-#define B3RDYPOL		0x00020000  /* B3 RDY Active High								*/
-#define B3TT_1			0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle		*/
-#define B3TT_2			0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles	*/
-#define B3TT_3			0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles	*/
-#define B3TT_4			0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles	*/
-#define B3ST_1			0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle		*/
-#define B3ST_2			0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles		*/
-#define B3ST_3			0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles		*/
-#define B3ST_4			0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles		*/
-#define B3HT_1			0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle		*/
-#define B3HT_2			0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles	*/
-#define B3HT_3			0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles	*/
-#define B3HT_0			0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles	*/
-#define B3RAT_1			0x01000000  /* B3 Read Access Time = 1 cycle					*/
-#define B3RAT_2			0x02000000  /* B3 Read Access Time = 2 cycles					*/
-#define B3RAT_3			0x03000000  /* B3 Read Access Time = 3 cycles					*/
-#define B3RAT_4			0x04000000  /* B3 Read Access Time = 4 cycles					*/
-#define B3RAT_5			0x05000000  /* B3 Read Access Time = 5 cycles					*/
-#define B3RAT_6			0x06000000  /* B3 Read Access Time = 6 cycles					*/
-#define B3RAT_7			0x07000000  /* B3 Read Access Time = 7 cycles					*/
-#define B3RAT_8			0x08000000  /* B3 Read Access Time = 8 cycles					*/
-#define B3RAT_9			0x09000000  /* B3 Read Access Time = 9 cycles					*/
-#define B3RAT_10		0x0A000000  /* B3 Read Access Time = 10 cycles					*/
-#define B3RAT_11		0x0B000000  /* B3 Read Access Time = 11 cycles					*/
-#define B3RAT_12		0x0C000000  /* B3 Read Access Time = 12 cycles					*/
-#define B3RAT_13		0x0D000000  /* B3 Read Access Time = 13 cycles					*/
-#define B3RAT_14		0x0E000000  /* B3 Read Access Time = 14 cycles					*/
-#define B3RAT_15		0x0F000000  /* B3 Read Access Time = 15 cycles					*/
-#define B3WAT_1			0x10000000  /* B3 Write Access Time = 1 cycle					*/
-#define B3WAT_2			0x20000000  /* B3 Write Access Time = 2 cycles					*/
-#define B3WAT_3			0x30000000  /* B3 Write Access Time = 3 cycles					*/
-#define B3WAT_4			0x40000000  /* B3 Write Access Time = 4 cycles					*/
-#define B3WAT_5			0x50000000  /* B3 Write Access Time = 5 cycles					*/
-#define B3WAT_6			0x60000000  /* B3 Write Access Time = 6 cycles					*/
-#define B3WAT_7			0x70000000  /* B3 Write Access Time = 7 cycles					*/
-#define B3WAT_8			0x80000000  /* B3 Write Access Time = 8 cycles					*/
-#define B3WAT_9			0x90000000  /* B3 Write Access Time = 9 cycles					*/
-#define B3WAT_10		0xA0000000  /* B3 Write Access Time = 10 cycles					*/
-#define B3WAT_11		0xB0000000  /* B3 Write Access Time = 11 cycles					*/
-#define B3WAT_12		0xC0000000  /* B3 Write Access Time = 12 cycles					*/
-#define B3WAT_13		0xD0000000  /* B3 Write Access Time = 13 cycles					*/
-#define B3WAT_14		0xE0000000  /* B3 Write Access Time = 14 cycles					*/
-#define B3WAT_15		0xF0000000  /* B3 Write Access Time = 15 cycles					*/
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks																			*/
-
-#define SCTLE			0x00000001	/* Enable SDRAM Signals										*/
-#define CL_2			0x00000008	/* SDRAM CAS Latency = 2 cycles								*/
-#define CL_3			0x0000000C	/* SDRAM CAS Latency = 3 cycles								*/
-#define CL          0x0000000C  /* SDRAM CAS latency */
-#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
-#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh		*/
-#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
-#define PASR         0x00000030  /* SDRAM partial array self-refresh */
-#define TRAS_1			0x00000040	/* SDRAM tRAS = 1 cycle										*/
-#define TRAS_2			0x00000080	/* SDRAM tRAS = 2 cycles									*/
-#define TRAS_3			0x000000C0	/* SDRAM tRAS = 3 cycles									*/
-#define TRAS_4			0x00000100	/* SDRAM tRAS = 4 cycles									*/
-#define TRAS_5			0x00000140	/* SDRAM tRAS = 5 cycles									*/
-#define TRAS_6			0x00000180	/* SDRAM tRAS = 6 cycles									*/
-#define TRAS_7			0x000001C0	/* SDRAM tRAS = 7 cycles									*/
-#define TRAS_8			0x00000200	/* SDRAM tRAS = 8 cycles									*/
-#define TRAS_9			0x00000240	/* SDRAM tRAS = 9 cycles									*/
-#define TRAS_10			0x00000280	/* SDRAM tRAS = 10 cycles									*/
-#define TRAS_11			0x000002C0	/* SDRAM tRAS = 11 cycles									*/
-#define TRAS_12			0x00000300	/* SDRAM tRAS = 12 cycles									*/
-#define TRAS_13			0x00000340	/* SDRAM tRAS = 13 cycles									*/
-#define TRAS_14			0x00000380	/* SDRAM tRAS = 14 cycles									*/
-#define TRAS_15			0x000003C0	/* SDRAM tRAS = 15 cycles									*/
-#define TRAS         0x000003C0  /* SDRAM tRAS in SCLK cycles */
-#define TRP_1			0x00000800	/* SDRAM tRP = 1 cycle										*/
-#define TRP_2			0x00001000	/* SDRAM tRP = 2 cycles										*/
-#define TRP_3			0x00001800	/* SDRAM tRP = 3 cycles										*/
-#define TRP_4			0x00002000	/* SDRAM tRP = 4 cycles										*/
-#define TRP_5			0x00002800	/* SDRAM tRP = 5 cycles										*/
-#define TRP_6			0x00003000	/* SDRAM tRP = 6 cycles										*/
-#define TRP_7			0x00003800	/* SDRAM tRP = 7 cycles										*/
-#define TRP          0x00003800  /* SDRAM tRP in SCLK cycles */
-#define TRCD_1			0x00008000	/* SDRAM tRCD = 1 cycle										*/
-#define TRCD_2			0x00010000	/* SDRAM tRCD = 2 cycles									*/
-#define TRCD_3			0x00018000	/* SDRAM tRCD = 3 cycles									*/
-#define TRCD_4			0x00020000	/* SDRAM tRCD = 4 cycles									*/
-#define TRCD_5			0x00028000	/* SDRAM tRCD = 5 cycles									*/
-#define TRCD_6			0x00030000	/* SDRAM tRCD = 6 cycles									*/
-#define TRCD_7			0x00038000	/* SDRAM tRCD = 7 cycles									*/
-#define TRCD         0x00030000  /* SDRAM tRCD in SCLK cycles */
-#define TWR_1			0x00080000	/* SDRAM tWR = 1 cycle										*/
-#define TWR_2			0x00100000	/* SDRAM tWR = 2 cycles										*/
-#define TWR_3			0x00180000	/* SDRAM tWR = 3 cycles										*/
-#define TWR          0x00180000  /* SDRAM tWR in SCLK cycles */
-#define PUPSD			0x00200000	/* Power-Up Start Delay (15 SCLK Cycles Delay)				*/
-#define PSM				0x00400000	/* Power-Up Sequence (Mode Register Before/After* Refresh)	*/
-#define PSS				0x00800000	/* Enable Power-Up Sequence on Next SDRAM Access			*/
-#define SRFS			0x01000000	/* Enable SDRAM Self-Refresh Mode							*/
-#define EBUFE			0x02000000	/* Enable External Buffering Timing							*/
-#define FBBRW			0x04000000	/* Enable Fast Back-To-Back Read To Write					*/
-#define EMREN			0x10000000	/* Extended Mode Register Enable							*/
-#define TCSR			0x20000000	/* Temp-Compensated Self-Refresh Value (85/45* Deg C)		*/
-#define CDDBG			0x40000000	/* Tristate SDRAM Controls During Bus Grant					*/
-
-/* EBIU_SDBCTL Masks																		*/
-#define EBE				0x0001		/* Enable SDRAM External Bank							*/
-#define EBSZ_16			0x0000		/* SDRAM External Bank Size = 16MB	*/
-#define EBSZ_32			0x0002		/* SDRAM External Bank Size = 32MB	*/
-#define EBSZ_64			0x0004		/* SDRAM External Bank Size = 64MB	*/
-#define EBSZ_128		0x0006		/* SDRAM External Bank Size = 128MB		*/
-#define EBSZ         0x0006      /* SDRAM external bank size */
-
-#define EBCAW_8			0x0000		/* SDRAM External Bank Column Address Width = 8 Bits	*/
-#define EBCAW_9			0x0010		/* SDRAM External Bank Column Address Width = 9 Bits	*/
-#define EBCAW_10		0x0020		/* SDRAM External Bank Column Address Width = 10 Bits	*/
-#define EBCAW_11		0x0030		/* SDRAM External Bank Column Address Width = 11 Bits	*/
-#define EBCAW        0x0030      /* SDRAM external bank column address width */
-
-/* EBIU_SDSTAT Masks														*/
-#define SDCI			0x0001		/* SDRAM Controller Idle 				*/
-#define SDSRA			0x0002		/* SDRAM Self-Refresh Active			*/
-#define SDPUA			0x0004		/* SDRAM Power-Up Active 				*/
-#define SDRS			0x0008		/* SDRAM Will Power-Up On Next Access	*/
-#define SDEASE			0x0010		/* SDRAM EAB Sticky Error Status		*/
-#define BGSTAT			0x0020		/* Bus Grant Status						*/
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks												*/
-#define DMAEN			0x0001		/* DMA Channel Enable							*/
-#define WNR				0x0002		/* Channel Direction (W/R*)						*/
-#define WDSIZE_8		0x0000		/* Transfer Word Size = 8						*/
-#define WDSIZE_16		0x0004		/* Transfer Word Size = 16						*/
-#define WDSIZE_32		0x0008		/* Transfer Word Size = 32						*/
-#define DMA2D			0x0010		/* DMA Mode (2D/1D*)							*/
-#define SYNC			0x0020		/* DMA Buffer Clear								*/
-#define DI_SEL			0x0040		/* Data Interrupt Timing Select					*/
-#define DI_EN			0x0080		/* Data Interrupt Enable						*/
-#define NDSIZE_0		0x0000		/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1		0x0100		/* Next Descriptor Size = 1						*/
-#define NDSIZE_2		0x0200		/* Next Descriptor Size = 2						*/
-#define NDSIZE_3		0x0300		/* Next Descriptor Size = 3						*/
-#define NDSIZE_4		0x0400		/* Next Descriptor Size = 4						*/
-#define NDSIZE_5		0x0500		/* Next Descriptor Size = 5						*/
-#define NDSIZE_6		0x0600		/* Next Descriptor Size = 6						*/
-#define NDSIZE_7		0x0700		/* Next Descriptor Size = 7						*/
-#define NDSIZE_8		0x0800		/* Next Descriptor Size = 8						*/
-#define NDSIZE_9		0x0900		/* Next Descriptor Size = 9						*/
-#define FLOW_STOP		0x0000		/* Stop Mode									*/
-#define FLOW_AUTO		0x1000		/* Autobuffer Mode								*/
-#define FLOW_ARRAY		0x4000		/* Descriptor Array Mode						*/
-#define FLOW_SMALL		0x6000		/* Small Model Descriptor List Mode				*/
-#define FLOW_LARGE		0x7000		/* Large Model Descriptor List Mode				*/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks								*/
-#define CTYPE			0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)	*/
-#define PMAP			0xF000	/* Peripheral Mapped To This Channel				*/
-#define PMAP_PPI		0x0000	/* 		PPI Port DMA								*/
-#define	PMAP_EMACRX		0x1000	/* 		Ethernet Receive DMA						*/
-#define PMAP_EMACTX		0x2000	/* 		Ethernet Transmit DMA						*/
-#define PMAP_SPORT0RX	0x3000	/* 		SPORT0 Receive DMA							*/
-#define PMAP_SPORT0TX	0x4000	/* 		SPORT0 Transmit DMA							*/
-#define PMAP_SPORT1RX	0x5000	/* 		SPORT1 Receive DMA							*/
-#define PMAP_SPORT1TX	0x6000	/* 		SPORT1 Transmit DMA							*/
-#define PMAP_SPI		0x7000	/* 		SPI Port DMA								*/
-#define PMAP_UART0RX	0x8000	/* 		UART0 Port Receive DMA						*/
-#define PMAP_UART0TX	0x9000	/* 		UART0 Port Transmit DMA						*/
-#define	PMAP_UART1RX	0xA000	/* 		UART1 Port Receive DMA						*/
-#define	PMAP_UART1TX	0xB000	/* 		UART1 Port Transmit DMA						*/
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks						*/
-#define DMA_DONE		0x0001	/* DMA Completion Interrupt Status	*/
-#define DMA_ERR			0x0002	/* DMA Error Interrupt Status		*/
-#define DFETCH			0x0004	/* DMA Descriptor Fetch Indicator	*/
-#define DMA_RUN			0x0008	/* DMA Channel Running Indicator	*/
-
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks													*/
-#define PORT_EN			0x0001		/* PPI Port Enable					*/
-#define PORT_DIR		0x0002		/* PPI Port Direction				*/
-#define XFR_TYPE		0x000C		/* PPI Transfer Type				*/
-#define PORT_CFG		0x0030		/* PPI Port Configuration			*/
-#define FLD_SEL			0x0040		/* PPI Active Field Select			*/
-#define PACK_EN			0x0080		/* PPI Packing Mode					*/
-/* previous versions of defBF534.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN			0x0200		/* PPI Skip Element Enable			*/
-#define SKIP_EO			0x0400		/* PPI Skip Even/Odd Elements		*/
-#define DLEN_8			0x0000		/* Data Length = 8 Bits				*/
-#define DLEN_10			0x0800		/* Data Length = 10 Bits			*/
-#define DLEN_11			0x1000		/* Data Length = 11 Bits			*/
-#define DLEN_12			0x1800		/* Data Length = 12 Bits			*/
-#define DLEN_13			0x2000		/* Data Length = 13 Bits			*/
-#define DLEN_14			0x2800		/* Data Length = 14 Bits			*/
-#define DLEN_15			0x3000		/* Data Length = 15 Bits			*/
-#define DLEN_16			0x3800		/* Data Length = 16 Bits			*/
-#define POLC			0x4000		/* PPI Clock Polarity				*/
-#define POLS			0x8000		/* PPI Frame Sync Polarity			*/
-
-/* PPI_STATUS Masks														*/
-#define FLD				0x0400		/* Field Indicator					*/
-#define FT_ERR			0x0800		/* Frame Track Error				*/
-#define OVR				0x1000		/* FIFO Overflow Error				*/
-#define UNDR			0x2000		/* FIFO Underrun Error				*/
-#define ERR_DET			0x4000		/* Error Detected Indicator			*/
-#define ERR_NCOR		0x8000		/* Error Not Corrected Indicator	*/
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#ifdef _MISRA_RULES
-#define	CLKLOW(x)	((x) & 0xFFu)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFFu)<<0x8)	/* Periods Before New Clock Low			*/
-#else
-#define	CLKLOW(x)	((x) & 0xFF)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low			*/
-#endif /* _MISRA_RULES */
-
-/* TWI_PRESCALE Masks															*/
-#define	PRESCALE	0x007F		/* SCLKs Per Internal Time Reference (10MHz)	*/
-#define	TWI_ENA		0x0080		/* TWI Enable									*/
-#define	SCCB		0x0200		/* SCCB Compatibility Enable					*/
-
-/* TWI_SLAVE_CTRL Masks															*/
-#define	SEN			0x0001		/* Slave Enable									*/
-#define	SADD_LEN	0x0002		/* Slave Address Length							*/
-#define	STDVAL		0x0004		/* Slave Transmit Data Valid					*/
-#define	NAK			0x0008		/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010		/* General Call Adrress Matching Enabled		*/
-
-/* TWI_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001		/* Slave Transfer Direction (Transmit/Receive*)	*/
-#define GCALL		0x0002		/* General Call Indicator						*/
-
-/* TWI_MASTER_CTRL Masks													*/
-#define	MEN			0x0001		/* Master Mode Enable						*/
-#define	MADD_LEN	0x0002		/* Master Address Length					*/
-#define	MDIR		0x0004		/* Master Transmit Direction (RX/TX*)		*/
-#define	FAST		0x0008		/* Use Fast Mode Timing Specs				*/
-#define	STOP		0x0010		/* Issue Stop Condition						*/
-#define	RSTART		0x0020		/* Repeat Start or Stop* At End Of Transfer	*/
-#define	DCNT		0x3FC0		/* Data Bytes To Transfer					*/
-#define	SDAOVR		0x4000		/* Serial Data Override						*/
-#define	SCLOVR		0x8000		/* Serial Clock Override					*/
-
-/* TWI_MASTER_STAT Masks														*/
-#define	MPROG		0x0001		/* Master Transfer In Progress					*/
-#define	LOSTARB		0x0002		/* Lost Arbitration Indicator (Xfer Aborted)	*/
-#define	ANAK		0x0004		/* Address Not Acknowledged						*/
-#define	DNAK		0x0008		/* Data Not Acknowledged						*/
-#define	BUFRDERR	0x0010		/* Buffer Read Error							*/
-#define	BUFWRERR	0x0020		/* Buffer Write Error							*/
-#define	SDASEN		0x0040		/* Serial Data Sense							*/
-#define	SCLSEN		0x0080		/* Serial Clock Sense							*/
-#define	BUSBUSY		0x0100		/* Bus Busy Indicator							*/
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks						*/
-#define	SINIT		0x0001		/* Slave Transfer Initiated	*/
-#define	SCOMP		0x0002		/* Slave Transfer Complete	*/
-#define	SERR		0x0004		/* Slave Transfer Error		*/
-#define	SOVF		0x0008		/* Slave Overflow			*/
-#define	MCOMP		0x0010		/* Master Transfer Complete	*/
-#define	MERR		0x0020		/* Master Transfer Error	*/
-#define	XMTSERV		0x0040		/* Transmit FIFO Service	*/
-#define	RCVSERV		0x0080		/* Receive FIFO Service		*/
-
-/* TWI_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001		/* Transmit Buffer Flush			*/
-#define	RCVFLUSH	0x0002		/* Receive Buffer Flush				*/
-#define	XMTINTLEN	0x0004		/* Transmit Buffer Interrupt Length	*/
-#define	RCVINTLEN	0x0008		/* Receive Buffer Interrupt Length	*/
-
-/* TWI_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003		/* Transmit FIFO Status							*/
-#define	XMT_EMPTY	0x0000		/* 		Transmit FIFO Empty						*/
-#define	XMT_HALF	0x0001		/* 		Transmit FIFO Has 1 Byte To Write		*/
-#define	XMT_FULL	0x0003		/* 		Transmit FIFO Full (2 Bytes To Write)	*/
-
-#define	RCVSTAT		0x000C		/* Receive FIFO Status							*/
-#define	RCV_EMPTY	0x0000		/* 		Receive FIFO Empty						*/
-#define	RCV_HALF	0x0004		/* 		Receive FIFO Has 1 Byte To Read			*/
-#define	RCV_FULL	0x000C		/* 		Receive FIFO Full (2 Bytes To Read)		*/
-
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-/* CAN_CONTROL Masks												*/
-#define	SRS			0x0001	/* Software Reset						*/
-#define	DNM			0x0002	/* Device Net Mode						*/
-#define	ABO			0x0004	/* Auto-Bus On Enable					*/
-#define	WBA			0x0010	/* Wake-Up On CAN Bus Activity Enable	*/
-#define	SMR			0x0020	/* Sleep Mode Request					*/
-#define	CSR			0x0040	/* CAN Suspend Mode Request				*/
-#define	CCR			0x0080	/* CAN Configuration Mode Request		*/
-
-/* CAN_STATUS Masks												*/
-#define	WT			0x0001	/* TX Warning Flag					*/
-#define	WR			0x0002	/* RX Warning Flag					*/
-#define	EP			0x0004	/* Error Passive Mode				*/
-#define	EBO			0x0008	/* Error Bus Off Mode				*/
-#define	CSA			0x0040	/* Suspend Mode Acknowledge			*/
-#define	CCA			0x0080	/* Configuration Mode Acknowledge	*/
-#define	MBPTR		0x1F00	/* Mailbox Pointer					*/
-#define	TRM			0x4000	/* Transmit Mode					*/
-#define	REC			0x8000	/* Receive Mode						*/
-
-/* CAN_CLOCK Masks									*/
-#define	BRP			0x03FF	/* Bit-Rate Pre-Scaler	*/
-
-/* CAN_TIMING Masks											*/
-#define	TSEG1		0x000F	/* Time Segment 1				*/
-#define	TSEG2		0x0070	/* Time Segment 2				*/
-#define	SAM			0x0080	/* Sampling						*/
-#define	SJW			0x0300	/* Synchronization Jump Width	*/
-
-/* CAN_DEBUG Masks											*/
-#define	DEC			0x0001	/* Disable CAN Error Counters	*/
-#define	DRI			0x0002	/* Disable CAN RX Input			*/
-#define	DTO			0x0004	/* Disable CAN TX Output		*/
-#define	DIL			0x0008	/* Disable CAN Internal Loop	*/
-#define	MAA			0x0010	/* Mode Auto-Acknowledge Enable	*/
-#define	MRB			0x0020	/* Mode Read Back Enable		*/
-#define	CDE			0x8000	/* CAN Debug Enable				*/
-
-/* CAN_CEC Masks										*/
-#define	RXECNT		0x00FF	/* Receive Error Counter	*/
-#define	TXECNT		0xFF00	/* Transmit Error Counter	*/
-
-/* CAN_INTR Masks											*/
-#define	MBRIRQ	0x0001	/* Mailbox Receive Interrupt	*/
-#define	MBRIF		MBRIRQ	/* legacy */
-#define	MBTIRQ	0x0002	/* Mailbox Transmit Interrupt	*/
-#define	MBTIF		MBTIRQ	/* legacy */
-#define	GIRQ		0x0004	/* Global Interrupt				*/
-#define	SMACK		0x0008	/* Sleep Mode Acknowledge		*/
-#define	CANTX		0x0040	/* CAN TX Bus Value				*/
-#define	CANRX		0x0080	/* CAN RX Bus Value				*/
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks										*/
-#define DFC			0xFFFF	/* Data Filtering Code (If Enabled) (ID0)		*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (ID0)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (ID1)	*/
-#define	BASEID		0x1FFC	/* Base Identifier								*/
-#define	IDE			0x2000	/* Identifier Extension							*/
-#define	RTR			0x4000	/* Remote Frame Transmission Request			*/
-#define	AME			0x8000	/* Acceptance Mask Enable						*/
-
-/* CAN_MBxx_TIMESTAMP Masks					*/
-#define TSV			0xFFFF	/* Timestamp	*/
-
-/* CAN_MBxx_LENGTH Masks						*/
-#define DLC			0x000F	/* Data Length Code	*/
-
-/* CAN_AMxxH and CAN_AMxxL Masks												*/
-#define DFM			0xFFFF	/* Data Field Mask (If Enabled) (CAN_AMxxL)			*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (CAN_AMxxL)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (CAN_AMxxH)	*/
-#define	BASEID		0x1FFC	/* Base Identifier									*/
-#define	AMIDE		0x2000	/* Acceptance Mask ID Extension Enable				*/
-#define	FMD			0x4000	/* Full Mask Data Field Enable						*/
-#define	FDF			0x8000	/* Filter On Data Field Enable						*/
-
-/* CAN_MC1 Masks									*/
-#define	MC0			0x0001	/* Enable Mailbox 0		*/
-#define	MC1			0x0002	/* Enable Mailbox 1		*/
-#define	MC2			0x0004	/* Enable Mailbox 2		*/
-#define	MC3			0x0008	/* Enable Mailbox 3		*/
-#define	MC4			0x0010	/* Enable Mailbox 4		*/
-#define	MC5			0x0020	/* Enable Mailbox 5		*/
-#define	MC6			0x0040	/* Enable Mailbox 6		*/
-#define	MC7			0x0080	/* Enable Mailbox 7		*/
-#define	MC8			0x0100	/* Enable Mailbox 8		*/
-#define	MC9			0x0200	/* Enable Mailbox 9		*/
-#define	MC10		0x0400	/* Enable Mailbox 10	*/
-#define	MC11		0x0800	/* Enable Mailbox 11	*/
-#define	MC12		0x1000	/* Enable Mailbox 12	*/
-#define	MC13		0x2000	/* Enable Mailbox 13	*/
-#define	MC14		0x4000	/* Enable Mailbox 14	*/
-#define	MC15		0x8000	/* Enable Mailbox 15	*/
-
-/* CAN_MC2 Masks									*/
-#define	MC16		0x0001	/* Enable Mailbox 16	*/
-#define	MC17		0x0002	/* Enable Mailbox 17	*/
-#define	MC18		0x0004	/* Enable Mailbox 18	*/
-#define	MC19		0x0008	/* Enable Mailbox 19	*/
-#define	MC20		0x0010	/* Enable Mailbox 20	*/
-#define	MC21		0x0020	/* Enable Mailbox 21	*/
-#define	MC22		0x0040	/* Enable Mailbox 22	*/
-#define	MC23		0x0080	/* Enable Mailbox 23	*/
-#define	MC24		0x0100	/* Enable Mailbox 24	*/
-#define	MC25		0x0200	/* Enable Mailbox 25	*/
-#define	MC26		0x0400	/* Enable Mailbox 26	*/
-#define	MC27		0x0800	/* Enable Mailbox 27	*/
-#define	MC28		0x1000	/* Enable Mailbox 28	*/
-#define	MC29		0x2000	/* Enable Mailbox 29	*/
-#define	MC30		0x4000	/* Enable Mailbox 30	*/
-#define	MC31		0x8000	/* Enable Mailbox 31	*/
-
-/* CAN_MD1 Masks												*/
-#define	MD0			0x0001	/* Enable Mailbox 0 For Receive		*/
-#define	MD1			0x0002	/* Enable Mailbox 1 For Receive		*/
-#define	MD2			0x0004	/* Enable Mailbox 2 For Receive		*/
-#define	MD3			0x0008	/* Enable Mailbox 3 For Receive		*/
-#define	MD4			0x0010	/* Enable Mailbox 4 For Receive		*/
-#define	MD5			0x0020	/* Enable Mailbox 5 For Receive		*/
-#define	MD6			0x0040	/* Enable Mailbox 6 For Receive		*/
-#define	MD7			0x0080	/* Enable Mailbox 7 For Receive		*/
-#define	MD8			0x0100	/* Enable Mailbox 8 For Receive		*/
-#define	MD9			0x0200	/* Enable Mailbox 9 For Receive		*/
-#define	MD10		0x0400	/* Enable Mailbox 10 For Receive	*/
-#define	MD11		0x0800	/* Enable Mailbox 11 For Receive	*/
-#define	MD12		0x1000	/* Enable Mailbox 12 For Receive	*/
-#define	MD13		0x2000	/* Enable Mailbox 13 For Receive	*/
-#define	MD14		0x4000	/* Enable Mailbox 14 For Receive	*/
-#define	MD15		0x8000	/* Enable Mailbox 15 For Receive	*/
-
-/* CAN_MD2 Masks												*/
-#define	MD16		0x0001	/* Enable Mailbox 16 For Receive	*/
-#define	MD17		0x0002	/* Enable Mailbox 17 For Receive	*/
-#define	MD18		0x0004	/* Enable Mailbox 18 For Receive	*/
-#define	MD19		0x0008	/* Enable Mailbox 19 For Receive	*/
-#define	MD20		0x0010	/* Enable Mailbox 20 For Receive	*/
-#define	MD21		0x0020	/* Enable Mailbox 21 For Receive	*/
-#define	MD22		0x0040	/* Enable Mailbox 22 For Receive	*/
-#define	MD23		0x0080	/* Enable Mailbox 23 For Receive	*/
-#define	MD24		0x0100	/* Enable Mailbox 24 For Receive	*/
-#define	MD25		0x0200	/* Enable Mailbox 25 For Receive	*/
-#define	MD26		0x0400	/* Enable Mailbox 26 For Receive	*/
-#define	MD27		0x0800	/* Enable Mailbox 27 For Receive	*/
-#define	MD28		0x1000	/* Enable Mailbox 28 For Receive	*/
-#define	MD29		0x2000	/* Enable Mailbox 29 For Receive	*/
-#define	MD30		0x4000	/* Enable Mailbox 30 For Receive	*/
-#define	MD31		0x8000	/* Enable Mailbox 31 For Receive	*/
-
-/* CAN_RMP1 Masks												*/
-#define	RMP0		0x0001	/* RX Message Pending In Mailbox 0	*/
-#define	RMP1		0x0002	/* RX Message Pending In Mailbox 1	*/
-#define	RMP2		0x0004	/* RX Message Pending In Mailbox 2	*/
-#define	RMP3		0x0008	/* RX Message Pending In Mailbox 3	*/
-#define	RMP4		0x0010	/* RX Message Pending In Mailbox 4	*/
-#define	RMP5		0x0020	/* RX Message Pending In Mailbox 5	*/
-#define	RMP6		0x0040	/* RX Message Pending In Mailbox 6	*/
-#define	RMP7		0x0080	/* RX Message Pending In Mailbox 7	*/
-#define	RMP8		0x0100	/* RX Message Pending In Mailbox 8	*/
-#define	RMP9		0x0200	/* RX Message Pending In Mailbox 9	*/
-#define	RMP10		0x0400	/* RX Message Pending In Mailbox 10	*/
-#define	RMP11		0x0800	/* RX Message Pending In Mailbox 11	*/
-#define	RMP12		0x1000	/* RX Message Pending In Mailbox 12	*/
-#define	RMP13		0x2000	/* RX Message Pending In Mailbox 13	*/
-#define	RMP14		0x4000	/* RX Message Pending In Mailbox 14	*/
-#define	RMP15		0x8000	/* RX Message Pending In Mailbox 15	*/
-
-/* CAN_RMP2 Masks												*/
-#define	RMP16		0x0001	/* RX Message Pending In Mailbox 16	*/
-#define	RMP17		0x0002	/* RX Message Pending In Mailbox 17	*/
-#define	RMP18		0x0004	/* RX Message Pending In Mailbox 18	*/
-#define	RMP19		0x0008	/* RX Message Pending In Mailbox 19	*/
-#define	RMP20		0x0010	/* RX Message Pending In Mailbox 20	*/
-#define	RMP21		0x0020	/* RX Message Pending In Mailbox 21	*/
-#define	RMP22		0x0040	/* RX Message Pending In Mailbox 22	*/
-#define	RMP23		0x0080	/* RX Message Pending In Mailbox 23	*/
-#define	RMP24		0x0100	/* RX Message Pending In Mailbox 24	*/
-#define	RMP25		0x0200	/* RX Message Pending In Mailbox 25	*/
-#define	RMP26		0x0400	/* RX Message Pending In Mailbox 26	*/
-#define	RMP27		0x0800	/* RX Message Pending In Mailbox 27	*/
-#define	RMP28		0x1000	/* RX Message Pending In Mailbox 28	*/
-#define	RMP29		0x2000	/* RX Message Pending In Mailbox 29	*/
-#define	RMP30		0x4000	/* RX Message Pending In Mailbox 30	*/
-#define	RMP31		0x8000	/* RX Message Pending In Mailbox 31	*/
-
-/* CAN_RML1 Masks												*/
-#define	RML0		0x0001	/* RX Message Lost In Mailbox 0		*/
-#define	RML1		0x0002	/* RX Message Lost In Mailbox 1		*/
-#define	RML2		0x0004	/* RX Message Lost In Mailbox 2		*/
-#define	RML3		0x0008	/* RX Message Lost In Mailbox 3		*/
-#define	RML4		0x0010	/* RX Message Lost In Mailbox 4		*/
-#define	RML5		0x0020	/* RX Message Lost In Mailbox 5		*/
-#define	RML6		0x0040	/* RX Message Lost In Mailbox 6		*/
-#define	RML7		0x0080	/* RX Message Lost In Mailbox 7		*/
-#define	RML8		0x0100	/* RX Message Lost In Mailbox 8		*/
-#define	RML9		0x0200	/* RX Message Lost In Mailbox 9		*/
-#define	RML10		0x0400	/* RX Message Lost In Mailbox 10	*/
-#define	RML11		0x0800	/* RX Message Lost In Mailbox 11	*/
-#define	RML12		0x1000	/* RX Message Lost In Mailbox 12	*/
-#define	RML13		0x2000	/* RX Message Lost In Mailbox 13	*/
-#define	RML14		0x4000	/* RX Message Lost In Mailbox 14	*/
-#define	RML15		0x8000	/* RX Message Lost In Mailbox 15	*/
-
-/* CAN_RML2 Masks												*/
-#define	RML16		0x0001	/* RX Message Lost In Mailbox 16	*/
-#define	RML17		0x0002	/* RX Message Lost In Mailbox 17	*/
-#define	RML18		0x0004	/* RX Message Lost In Mailbox 18	*/
-#define	RML19		0x0008	/* RX Message Lost In Mailbox 19	*/
-#define	RML20		0x0010	/* RX Message Lost In Mailbox 20	*/
-#define	RML21		0x0020	/* RX Message Lost In Mailbox 21	*/
-#define	RML22		0x0040	/* RX Message Lost In Mailbox 22	*/
-#define	RML23		0x0080	/* RX Message Lost In Mailbox 23	*/
-#define	RML24		0x0100	/* RX Message Lost In Mailbox 24	*/
-#define	RML25		0x0200	/* RX Message Lost In Mailbox 25	*/
-#define	RML26		0x0400	/* RX Message Lost In Mailbox 26	*/
-#define	RML27		0x0800	/* RX Message Lost In Mailbox 27	*/
-#define	RML28		0x1000	/* RX Message Lost In Mailbox 28	*/
-#define	RML29		0x2000	/* RX Message Lost In Mailbox 29	*/
-#define	RML30		0x4000	/* RX Message Lost In Mailbox 30	*/
-#define	RML31		0x8000	/* RX Message Lost In Mailbox 31	*/
-
-/* CAN_OPSS1 Masks																				*/
-#define	OPSS0		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0	*/
-#define	OPSS1		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1	*/
-#define	OPSS2		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2	*/
-#define	OPSS3		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3	*/
-#define	OPSS4		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4	*/
-#define	OPSS5		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5	*/
-#define	OPSS6		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6	*/
-#define	OPSS7		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7	*/
-#define	OPSS8		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8	*/
-#define	OPSS9		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9	*/
-#define	OPSS10		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10	*/
-#define	OPSS11		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11	*/
-#define	OPSS12		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12	*/
-#define	OPSS13		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13	*/
-#define	OPSS14		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14	*/
-#define	OPSS15		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15	*/
-
-/* CAN_OPSS2 Masks																				*/
-#define	OPSS16		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16	*/
-#define	OPSS17		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17	*/
-#define	OPSS18		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18	*/
-#define	OPSS19		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19	*/
-#define	OPSS20		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20	*/
-#define	OPSS21		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21	*/
-#define	OPSS22		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22	*/
-#define	OPSS23		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23	*/
-#define	OPSS24		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24	*/
-#define	OPSS25		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25	*/
-#define	OPSS26		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26	*/
-#define	OPSS27		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27	*/
-#define	OPSS28		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28	*/
-#define	OPSS29		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29	*/
-#define	OPSS30		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30	*/
-#define	OPSS31		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31	*/
-
-/* CAN_TRR1 Masks														*/
-#define	TRR0		0x0001	/* Deny But Don't Lock Access To Mailbox 0	*/
-#define	TRR1		0x0002	/* Deny But Don't Lock Access To Mailbox 1	*/
-#define	TRR2		0x0004	/* Deny But Don't Lock Access To Mailbox 2	*/
-#define	TRR3		0x0008	/* Deny But Don't Lock Access To Mailbox 3	*/
-#define	TRR4		0x0010	/* Deny But Don't Lock Access To Mailbox 4	*/
-#define	TRR5		0x0020	/* Deny But Don't Lock Access To Mailbox 5	*/
-#define	TRR6		0x0040	/* Deny But Don't Lock Access To Mailbox 6	*/
-#define	TRR7		0x0080	/* Deny But Don't Lock Access To Mailbox 7	*/
-#define	TRR8		0x0100	/* Deny But Don't Lock Access To Mailbox 8	*/
-#define	TRR9		0x0200	/* Deny But Don't Lock Access To Mailbox 9	*/
-#define	TRR10		0x0400	/* Deny But Don't Lock Access To Mailbox 10	*/
-#define	TRR11		0x0800	/* Deny But Don't Lock Access To Mailbox 11	*/
-#define	TRR12		0x1000	/* Deny But Don't Lock Access To Mailbox 12	*/
-#define	TRR13		0x2000	/* Deny But Don't Lock Access To Mailbox 13	*/
-#define	TRR14		0x4000	/* Deny But Don't Lock Access To Mailbox 14	*/
-#define	TRR15		0x8000	/* Deny But Don't Lock Access To Mailbox 15	*/
-
-/* CAN_TRR2 Masks														*/
-#define	TRR16		0x0001	/* Deny But Don't Lock Access To Mailbox 16	*/
-#define	TRR17		0x0002	/* Deny But Don't Lock Access To Mailbox 17	*/
-#define	TRR18		0x0004	/* Deny But Don't Lock Access To Mailbox 18	*/
-#define	TRR19		0x0008	/* Deny But Don't Lock Access To Mailbox 19	*/
-#define	TRR20		0x0010	/* Deny But Don't Lock Access To Mailbox 20	*/
-#define	TRR21		0x0020	/* Deny But Don't Lock Access To Mailbox 21	*/
-#define	TRR22		0x0040	/* Deny But Don't Lock Access To Mailbox 22	*/
-#define	TRR23		0x0080	/* Deny But Don't Lock Access To Mailbox 23	*/
-#define	TRR24		0x0100	/* Deny But Don't Lock Access To Mailbox 24	*/
-#define	TRR25		0x0200	/* Deny But Don't Lock Access To Mailbox 25	*/
-#define	TRR26		0x0400	/* Deny But Don't Lock Access To Mailbox 26	*/
-#define	TRR27		0x0800	/* Deny But Don't Lock Access To Mailbox 27	*/
-#define	TRR28		0x1000	/* Deny But Don't Lock Access To Mailbox 28	*/
-#define	TRR29		0x2000	/* Deny But Don't Lock Access To Mailbox 29	*/
-#define	TRR30		0x4000	/* Deny But Don't Lock Access To Mailbox 30	*/
-#define	TRR31		0x8000	/* Deny But Don't Lock Access To Mailbox 31	*/
-
-/* CAN_TRS1 Masks													*/
-#define	TRS0		0x0001	/* Remote Frame Request For Mailbox 0	*/
-#define	TRS1		0x0002	/* Remote Frame Request For Mailbox 1	*/
-#define	TRS2		0x0004	/* Remote Frame Request For Mailbox 2	*/
-#define	TRS3		0x0008	/* Remote Frame Request For Mailbox 3	*/
-#define	TRS4		0x0010	/* Remote Frame Request For Mailbox 4	*/
-#define	TRS5		0x0020	/* Remote Frame Request For Mailbox 5	*/
-#define	TRS6		0x0040	/* Remote Frame Request For Mailbox 6	*/
-#define	TRS7		0x0080	/* Remote Frame Request For Mailbox 7	*/
-#define	TRS8		0x0100	/* Remote Frame Request For Mailbox 8	*/
-#define	TRS9		0x0200	/* Remote Frame Request For Mailbox 9	*/
-#define	TRS10		0x0400	/* Remote Frame Request For Mailbox 10	*/
-#define	TRS11		0x0800	/* Remote Frame Request For Mailbox 11	*/
-#define	TRS12		0x1000	/* Remote Frame Request For Mailbox 12	*/
-#define	TRS13		0x2000	/* Remote Frame Request For Mailbox 13	*/
-#define	TRS14		0x4000	/* Remote Frame Request For Mailbox 14	*/
-#define	TRS15		0x8000	/* Remote Frame Request For Mailbox 15	*/
-
-/* CAN_TRS2 Masks													*/
-#define	TRS16		0x0001	/* Remote Frame Request For Mailbox 16	*/
-#define	TRS17		0x0002	/* Remote Frame Request For Mailbox 17	*/
-#define	TRS18		0x0004	/* Remote Frame Request For Mailbox 18	*/
-#define	TRS19		0x0008	/* Remote Frame Request For Mailbox 19	*/
-#define	TRS20		0x0010	/* Remote Frame Request For Mailbox 20	*/
-#define	TRS21		0x0020	/* Remote Frame Request For Mailbox 21	*/
-#define	TRS22		0x0040	/* Remote Frame Request For Mailbox 22	*/
-#define	TRS23		0x0080	/* Remote Frame Request For Mailbox 23	*/
-#define	TRS24		0x0100	/* Remote Frame Request For Mailbox 24	*/
-#define	TRS25		0x0200	/* Remote Frame Request For Mailbox 25	*/
-#define	TRS26		0x0400	/* Remote Frame Request For Mailbox 26	*/
-#define	TRS27		0x0800	/* Remote Frame Request For Mailbox 27	*/
-#define	TRS28		0x1000	/* Remote Frame Request For Mailbox 28	*/
-#define	TRS29		0x2000	/* Remote Frame Request For Mailbox 29	*/
-#define	TRS30		0x4000	/* Remote Frame Request For Mailbox 30	*/
-#define	TRS31		0x8000	/* Remote Frame Request For Mailbox 31	*/
-
-/* CAN_AA1 Masks												*/
-#define	AA0			0x0001	/* Aborted Message In Mailbox 0		*/
-#define	AA1			0x0002	/* Aborted Message In Mailbox 1		*/
-#define	AA2			0x0004	/* Aborted Message In Mailbox 2		*/
-#define	AA3			0x0008	/* Aborted Message In Mailbox 3		*/
-#define	AA4			0x0010	/* Aborted Message In Mailbox 4		*/
-#define	AA5			0x0020	/* Aborted Message In Mailbox 5		*/
-#define	AA6			0x0040	/* Aborted Message In Mailbox 6		*/
-#define	AA7			0x0080	/* Aborted Message In Mailbox 7		*/
-#define	AA8			0x0100	/* Aborted Message In Mailbox 8		*/
-#define	AA9			0x0200	/* Aborted Message In Mailbox 9		*/
-#define	AA10		0x0400	/* Aborted Message In Mailbox 10	*/
-#define	AA11		0x0800	/* Aborted Message In Mailbox 11	*/
-#define	AA12		0x1000	/* Aborted Message In Mailbox 12	*/
-#define	AA13		0x2000	/* Aborted Message In Mailbox 13	*/
-#define	AA14		0x4000	/* Aborted Message In Mailbox 14	*/
-#define	AA15		0x8000	/* Aborted Message In Mailbox 15	*/
-
-/* CAN_AA2 Masks												*/
-#define	AA16		0x0001	/* Aborted Message In Mailbox 16	*/
-#define	AA17		0x0002	/* Aborted Message In Mailbox 17	*/
-#define	AA18		0x0004	/* Aborted Message In Mailbox 18	*/
-#define	AA19		0x0008	/* Aborted Message In Mailbox 19	*/
-#define	AA20		0x0010	/* Aborted Message In Mailbox 20	*/
-#define	AA21		0x0020	/* Aborted Message In Mailbox 21	*/
-#define	AA22		0x0040	/* Aborted Message In Mailbox 22	*/
-#define	AA23		0x0080	/* Aborted Message In Mailbox 23	*/
-#define	AA24		0x0100	/* Aborted Message In Mailbox 24	*/
-#define	AA25		0x0200	/* Aborted Message In Mailbox 25	*/
-#define	AA26		0x0400	/* Aborted Message In Mailbox 26	*/
-#define	AA27		0x0800	/* Aborted Message In Mailbox 27	*/
-#define	AA28		0x1000	/* Aborted Message In Mailbox 28	*/
-#define	AA29		0x2000	/* Aborted Message In Mailbox 29	*/
-#define	AA30		0x4000	/* Aborted Message In Mailbox 30	*/
-#define	AA31		0x8000	/* Aborted Message In Mailbox 31	*/
-
-/* CAN_TA1 Masks													*/
-#define	TA0			0x0001	/* Transmit Successful From Mailbox 0	*/
-#define	TA1			0x0002	/* Transmit Successful From Mailbox 1	*/
-#define	TA2			0x0004	/* Transmit Successful From Mailbox 2	*/
-#define	TA3			0x0008	/* Transmit Successful From Mailbox 3	*/
-#define	TA4			0x0010	/* Transmit Successful From Mailbox 4	*/
-#define	TA5			0x0020	/* Transmit Successful From Mailbox 5	*/
-#define	TA6			0x0040	/* Transmit Successful From Mailbox 6	*/
-#define	TA7			0x0080	/* Transmit Successful From Mailbox 7	*/
-#define	TA8			0x0100	/* Transmit Successful From Mailbox 8	*/
-#define	TA9			0x0200	/* Transmit Successful From Mailbox 9	*/
-#define	TA10		0x0400	/* Transmit Successful From Mailbox 10	*/
-#define	TA11		0x0800	/* Transmit Successful From Mailbox 11	*/
-#define	TA12		0x1000	/* Transmit Successful From Mailbox 12	*/
-#define	TA13		0x2000	/* Transmit Successful From Mailbox 13	*/
-#define	TA14		0x4000	/* Transmit Successful From Mailbox 14	*/
-#define	TA15		0x8000	/* Transmit Successful From Mailbox 15	*/
-
-/* CAN_TA2 Masks													*/
-#define	TA16		0x0001	/* Transmit Successful From Mailbox 16	*/
-#define	TA17		0x0002	/* Transmit Successful From Mailbox 17	*/
-#define	TA18		0x0004	/* Transmit Successful From Mailbox 18	*/
-#define	TA19		0x0008	/* Transmit Successful From Mailbox 19	*/
-#define	TA20		0x0010	/* Transmit Successful From Mailbox 20	*/
-#define	TA21		0x0020	/* Transmit Successful From Mailbox 21	*/
-#define	TA22		0x0040	/* Transmit Successful From Mailbox 22	*/
-#define	TA23		0x0080	/* Transmit Successful From Mailbox 23	*/
-#define	TA24		0x0100	/* Transmit Successful From Mailbox 24	*/
-#define	TA25		0x0200	/* Transmit Successful From Mailbox 25	*/
-#define	TA26		0x0400	/* Transmit Successful From Mailbox 26	*/
-#define	TA27		0x0800	/* Transmit Successful From Mailbox 27	*/
-#define	TA28		0x1000	/* Transmit Successful From Mailbox 28	*/
-#define	TA29		0x2000	/* Transmit Successful From Mailbox 29	*/
-#define	TA30		0x4000	/* Transmit Successful From Mailbox 30	*/
-#define	TA31		0x8000	/* Transmit Successful From Mailbox 31	*/
-
-/* CAN_MBTD Masks												*/
-#define TDPTR		0x001F	/* Mailbox To Temporarily Disable	*/
-#define	TDA			0x0040	/* Temporary Disable Acknowledge	*/
-#define	TDR			0x0080	/* Temporary Disable Request		*/
-
-/* CAN_RFH1 Masks																		*/
-#define	RFH0		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 0		*/
-#define	RFH1		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 1		*/
-#define	RFH2		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 2		*/
-#define	RFH3		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 3		*/
-#define	RFH4		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 4		*/
-#define	RFH5		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 5		*/
-#define	RFH6		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 6		*/
-#define	RFH7		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 7		*/
-#define	RFH8		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 8		*/
-#define	RFH9		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 9		*/
-#define	RFH10		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 10	*/
-#define	RFH11		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 11	*/
-#define	RFH12		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 12	*/
-#define	RFH13		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 13	*/
-#define	RFH14		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 14	*/
-#define	RFH15		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 15	*/
-
-/* CAN_RFH2 Masks																		*/
-#define	RFH16		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 16	*/
-#define	RFH17		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 17	*/
-#define	RFH18		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 18	*/
-#define	RFH19		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 19	*/
-#define	RFH20		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 20	*/
-#define	RFH21		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 21	*/
-#define	RFH22		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 22	*/
-#define	RFH23		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 23	*/
-#define	RFH24		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 24	*/
-#define	RFH25		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 25	*/
-#define	RFH26		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 26	*/
-#define	RFH27		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 27	*/
-#define	RFH28		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 28	*/
-#define	RFH29		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 29	*/
-#define	RFH30		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 30	*/
-#define	RFH31		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 31	*/
-
-/* CAN_MBTIF1 Masks													*/
-#define	MBTIF0		0x0001	/* TX Interrupt Active In Mailbox 0		*/
-#define	MBTIF1		0x0002	/* TX Interrupt Active In Mailbox 1		*/
-#define	MBTIF2		0x0004	/* TX Interrupt Active In Mailbox 2		*/
-#define	MBTIF3		0x0008	/* TX Interrupt Active In Mailbox 3		*/
-#define	MBTIF4		0x0010	/* TX Interrupt Active In Mailbox 4		*/
-#define	MBTIF5		0x0020	/* TX Interrupt Active In Mailbox 5		*/
-#define	MBTIF6		0x0040	/* TX Interrupt Active In Mailbox 6		*/
-#define	MBTIF7		0x0080	/* TX Interrupt Active In Mailbox 7		*/
-#define	MBTIF8		0x0100	/* TX Interrupt Active In Mailbox 8		*/
-#define	MBTIF9		0x0200	/* TX Interrupt Active In Mailbox 9		*/
-#define	MBTIF10		0x0400	/* TX Interrupt Active In Mailbox 10	*/
-#define	MBTIF11		0x0800	/* TX Interrupt Active In Mailbox 11	*/
-#define	MBTIF12		0x1000	/* TX Interrupt Active In Mailbox 12	*/
-#define	MBTIF13		0x2000	/* TX Interrupt Active In Mailbox 13	*/
-#define	MBTIF14		0x4000	/* TX Interrupt Active In Mailbox 14	*/
-#define	MBTIF15		0x8000	/* TX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBTIF2 Masks													*/
-#define	MBTIF16		0x0001	/* TX Interrupt Active In Mailbox 16	*/
-#define	MBTIF17		0x0002	/* TX Interrupt Active In Mailbox 17	*/
-#define	MBTIF18		0x0004	/* TX Interrupt Active In Mailbox 18	*/
-#define	MBTIF19		0x0008	/* TX Interrupt Active In Mailbox 19	*/
-#define	MBTIF20		0x0010	/* TX Interrupt Active In Mailbox 20	*/
-#define	MBTIF21		0x0020	/* TX Interrupt Active In Mailbox 21	*/
-#define	MBTIF22		0x0040	/* TX Interrupt Active In Mailbox 22	*/
-#define	MBTIF23		0x0080	/* TX Interrupt Active In Mailbox 23	*/
-#define	MBTIF24		0x0100	/* TX Interrupt Active In Mailbox 24	*/
-#define	MBTIF25		0x0200	/* TX Interrupt Active In Mailbox 25	*/
-#define	MBTIF26		0x0400	/* TX Interrupt Active In Mailbox 26	*/
-#define	MBTIF27		0x0800	/* TX Interrupt Active In Mailbox 27	*/
-#define	MBTIF28		0x1000	/* TX Interrupt Active In Mailbox 28	*/
-#define	MBTIF29		0x2000	/* TX Interrupt Active In Mailbox 29	*/
-#define	MBTIF30		0x4000	/* TX Interrupt Active In Mailbox 30	*/
-#define	MBTIF31		0x8000	/* TX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBRIF1 Masks													*/
-#define	MBRIF0		0x0001	/* RX Interrupt Active In Mailbox 0		*/
-#define	MBRIF1		0x0002	/* RX Interrupt Active In Mailbox 1		*/
-#define	MBRIF2		0x0004	/* RX Interrupt Active In Mailbox 2		*/
-#define	MBRIF3		0x0008	/* RX Interrupt Active In Mailbox 3		*/
-#define	MBRIF4		0x0010	/* RX Interrupt Active In Mailbox 4		*/
-#define	MBRIF5		0x0020	/* RX Interrupt Active In Mailbox 5		*/
-#define	MBRIF6		0x0040	/* RX Interrupt Active In Mailbox 6		*/
-#define	MBRIF7		0x0080	/* RX Interrupt Active In Mailbox 7		*/
-#define	MBRIF8		0x0100	/* RX Interrupt Active In Mailbox 8		*/
-#define	MBRIF9		0x0200	/* RX Interrupt Active In Mailbox 9		*/
-#define	MBRIF10		0x0400	/* RX Interrupt Active In Mailbox 10	*/
-#define	MBRIF11		0x0800	/* RX Interrupt Active In Mailbox 11	*/
-#define	MBRIF12		0x1000	/* RX Interrupt Active In Mailbox 12	*/
-#define	MBRIF13		0x2000	/* RX Interrupt Active In Mailbox 13	*/
-#define	MBRIF14		0x4000	/* RX Interrupt Active In Mailbox 14	*/
-#define	MBRIF15		0x8000	/* RX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBRIF2 Masks													*/
-#define	MBRIF16		0x0001	/* RX Interrupt Active In Mailbox 16	*/
-#define	MBRIF17		0x0002	/* RX Interrupt Active In Mailbox 17	*/
-#define	MBRIF18		0x0004	/* RX Interrupt Active In Mailbox 18	*/
-#define	MBRIF19		0x0008	/* RX Interrupt Active In Mailbox 19	*/
-#define	MBRIF20		0x0010	/* RX Interrupt Active In Mailbox 20	*/
-#define	MBRIF21		0x0020	/* RX Interrupt Active In Mailbox 21	*/
-#define	MBRIF22		0x0040	/* RX Interrupt Active In Mailbox 22	*/
-#define	MBRIF23		0x0080	/* RX Interrupt Active In Mailbox 23	*/
-#define	MBRIF24		0x0100	/* RX Interrupt Active In Mailbox 24	*/
-#define	MBRIF25		0x0200	/* RX Interrupt Active In Mailbox 25	*/
-#define	MBRIF26		0x0400	/* RX Interrupt Active In Mailbox 26	*/
-#define	MBRIF27		0x0800	/* RX Interrupt Active In Mailbox 27	*/
-#define	MBRIF28		0x1000	/* RX Interrupt Active In Mailbox 28	*/
-#define	MBRIF29		0x2000	/* RX Interrupt Active In Mailbox 29	*/
-#define	MBRIF30		0x4000	/* RX Interrupt Active In Mailbox 30	*/
-#define	MBRIF31		0x8000	/* RX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBIM1 Masks												*/
-#define	MBIM0		0x0001	/* Enable Interrupt For Mailbox 0	*/
-#define	MBIM1		0x0002	/* Enable Interrupt For Mailbox 1	*/
-#define	MBIM2		0x0004	/* Enable Interrupt For Mailbox 2	*/
-#define	MBIM3		0x0008	/* Enable Interrupt For Mailbox 3	*/
-#define	MBIM4		0x0010	/* Enable Interrupt For Mailbox 4	*/
-#define	MBIM5		0x0020	/* Enable Interrupt For Mailbox 5	*/
-#define	MBIM6		0x0040	/* Enable Interrupt For Mailbox 6	*/
-#define	MBIM7		0x0080	/* Enable Interrupt For Mailbox 7	*/
-#define	MBIM8		0x0100	/* Enable Interrupt For Mailbox 8	*/
-#define	MBIM9		0x0200	/* Enable Interrupt For Mailbox 9	*/
-#define	MBIM10		0x0400	/* Enable Interrupt For Mailbox 10	*/
-#define	MBIM11		0x0800	/* Enable Interrupt For Mailbox 11	*/
-#define	MBIM12		0x1000	/* Enable Interrupt For Mailbox 12	*/
-#define	MBIM13		0x2000	/* Enable Interrupt For Mailbox 13	*/
-#define	MBIM14		0x4000	/* Enable Interrupt For Mailbox 14	*/
-#define	MBIM15		0x8000	/* Enable Interrupt For Mailbox 15	*/
-
-/* CAN_MBIM2 Masks												*/
-#define	MBIM16		0x0001	/* Enable Interrupt For Mailbox 16	*/
-#define	MBIM17		0x0002	/* Enable Interrupt For Mailbox 17	*/
-#define	MBIM18		0x0004	/* Enable Interrupt For Mailbox 18	*/
-#define	MBIM19		0x0008	/* Enable Interrupt For Mailbox 19	*/
-#define	MBIM20		0x0010	/* Enable Interrupt For Mailbox 20	*/
-#define	MBIM21		0x0020	/* Enable Interrupt For Mailbox 21	*/
-#define	MBIM22		0x0040	/* Enable Interrupt For Mailbox 22	*/
-#define	MBIM23		0x0080	/* Enable Interrupt For Mailbox 23	*/
-#define	MBIM24		0x0100	/* Enable Interrupt For Mailbox 24	*/
-#define	MBIM25		0x0200	/* Enable Interrupt For Mailbox 25	*/
-#define	MBIM26		0x0400	/* Enable Interrupt For Mailbox 26	*/
-#define	MBIM27		0x0800	/* Enable Interrupt For Mailbox 27	*/
-#define	MBIM28		0x1000	/* Enable Interrupt For Mailbox 28	*/
-#define	MBIM29		0x2000	/* Enable Interrupt For Mailbox 29	*/
-#define	MBIM30		0x4000	/* Enable Interrupt For Mailbox 30	*/
-#define	MBIM31		0x8000	/* Enable Interrupt For Mailbox 31	*/
-
-/* CAN_GIM Masks																*/
-#define	EWTIM		0x0001	/* Enable TX Error Count Interrupt					*/
-#define	EWRIM		0x0002	/* Enable RX Error Count Interrupt					*/
-#define	EPIM		0x0004	/* Enable Error-Passive Mode Interrupt				*/
-#define	BOIM		0x0008	/* Enable Bus Off Interrupt							*/
-#define	WUIM		0x0010	/* Enable Wake-Up Interrupt							*/
-#define	UIAIM		0x0020	/* Enable Access To Unimplemented Address Interrupt	*/
-#define	AAIM		0x0040	/* Enable Abort Acknowledge Interrupt				*/
-#define	RMLIM		0x0080	/* Enable RX Message Lost Interrupt					*/
-#define	UCEIM		0x0100	/* Enable Universal Counter Overflow Interrupt		*/
-#define	EXTIM		0x0200	/* Enable External Trigger Output Interrupt			*/
-#define	ADIM		0x0400	/* Enable Access Denied Interrupt					*/
-
-/* CAN_GIS Masks															*/
-#define	EWTIS		0x0001	/* TX Error Count IRQ Status					*/
-#define	EWRIS		0x0002	/* RX Error Count IRQ Status					*/
-#define	EPIS		0x0004	/* Error-Passive Mode IRQ Status				*/
-#define	BOIS		0x0008	/* Bus Off IRQ Status							*/
-#define	WUIS		0x0010	/* Wake-Up IRQ Status							*/
-#define	UIAIS		0x0020	/* Access To Unimplemented Address IRQ Status	*/
-#define	AAIS		0x0040	/* Abort Acknowledge IRQ Status					*/
-#define	RMLIS		0x0080	/* RX Message Lost IRQ Status					*/
-#define	UCEIS		0x0100	/* Universal Counter Overflow IRQ Status		*/
-#define	EXTIS		0x0200	/* External Trigger Output IRQ Status			*/
-#define	ADIS		0x0400	/* Access Denied IRQ Status						*/
-
-/* CAN_GIF Masks															*/
-#define	EWTIF		0x0001	/* TX Error Count IRQ Flag						*/
-#define	EWRIF		0x0002	/* RX Error Count IRQ Flag						*/
-#define	EPIF		0x0004	/* Error-Passive Mode IRQ Flag					*/
-#define	BOIF		0x0008	/* Bus Off IRQ Flag								*/
-#define	WUIF		0x0010	/* Wake-Up IRQ Flag								*/
-#define	UIAIF		0x0020	/* Access To Unimplemented Address IRQ Flag		*/
-#define	AAIF		0x0040	/* Abort Acknowledge IRQ Flag					*/
-#define	RMLIF		0x0080	/* RX Message Lost IRQ Flag						*/
-#define	UCEIF		0x0100	/* Universal Counter Overflow IRQ Flag			*/
-#define	EXTIF		0x0200	/* External Trigger Output IRQ Flag				*/
-#define	ADIF		0x0400	/* Access Denied IRQ Flag						*/
-
-/* CAN_UCCNF Masks															*/
-#define	UCCNF		0x000F	/* Universal Counter Mode						*/
-#define UC_STAMP	0x0001	/* 		Timestamp Mode							*/
-#define UC_WDOG		0x0002	/* 		Watchdog Mode							*/
-#define UC_AUTOTX	0x0003	/* 		Auto-Transmit Mode						*/
-#define UC_ERROR	0x0006	/* 		CAN Error Frame Count					*/
-#define UC_OVER		0x0007	/* 		CAN Overload Frame Count				*/
-#define UC_LOST		0x0008	/* 		Arbitration Lost During TX Count		*/
-#define UC_AA		0x0009	/* 		TX Abort Count							*/
-#define UC_TA		0x000A	/* 		TX Successful Count						*/
-#define UC_REJECT	0x000B	/* 		RX Message Rejected Count				*/
-#define UC_RML		0x000C	/* 		RX Message Lost Count					*/
-#define UC_RX		0x000D	/* 		Total Successful RX Messages Count		*/
-#define UC_RMP		0x000E	/* 		Successful RX W/Matching ID Count		*/
-#define UC_ALL		0x000F	/* 		Correct Message On CAN Bus Line Count	*/
-#define	UCRC		0x0020	/* Universal Counter Reload/Clear				*/
-#define	UCCT		0x0040	/* Universal Counter CAN Trigger				*/
-#define	UCE			0x0080	/* Universal Counter Enable						*/
-
-/* CAN_ESR Masks										*/
-#define	ACKE		0x0004	/* Acknowledge Error		*/
-#define	SER			0x0008	/* Stuff Error				*/
-#define	CRCE		0x0010	/* CRC Error				*/
-#define	SA0			0x0020	/* Stuck At Dominant Error	*/
-#define	BEF			0x0040	/* Bit Error Flag			*/
-#define	FER			0x0080	/* Form Error Flag			*/
-
-/* CAN_EWR Masks												*/
-#define	EWLREC		0x00FF	/* RX Error Count Limit (For EWRIS)	*/
-#define	EWLTEC		0xFF00	/* TX Error Count Limit (For EWTIS)	*/
-
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks															*/
-#define	PJSE			0x0001			/* Port J SPI/SPORT Enable			*/
-#define	PJSE_SPORT		0x0000			/* 		Enable TFS0/DT0PRI			*/
-#define	PJSE_SPI		0x0001			/* 		Enable SPI_SSEL3:2			*/
-
-#ifdef _MISRA_RULES
-#define	PJCE(x)			(((x)&0x3u)<<1)	/* Port J CAN/SPI/SPORT Enable		*/
-#else
-#define	PJCE(x)			(((x)&0x3)<<1)	/* Port J CAN/SPI/SPORT Enable		*/
-#endif /* _MISRA_RULES */
-
-#define	PJCE_SPORT		0x0000			/* 		Enable DR0SEC/DT0SEC		*/
-#define	PJCE_CAN		0x0002			/* 		Enable CAN RX/TX			*/
-#define	PJCE_SPI		0x0004			/* 		Enable SPI_SSEL7			*/
-
-#define	PFDE			0x0008			/* Port F DMA Request Enable		*/
-#define	PFDE_UART		0x0000			/* 		Enable UART0 RX/TX			*/
-#define	PFDE_DMA		0x0008			/* 		Enable DMAR1:0				*/
-
-#define	PFTE			0x0010			/* Port F Timer Enable				*/
-#define	PFTE_UART		0x0000			/*		Enable UART1 RX/TX			*/
-#define	PFTE_TIMER		0x0010			/* 		Enable TMR7:6				*/
-
-#define	PFS6E			0x0020			/* Port F SPI SSEL 6 Enable			*/
-#define	PFS6E_TIMER		0x0000			/*		Enable TMR5					*/
-#define	PFS6E_SPI		0x0020			/* 		Enable SPI_SSEL6			*/
-
-#define	PFS5E			0x0040			/* Port F SPI SSEL 5 Enable			*/
-#define	PFS5E_TIMER		0x0000			/*		Enable TMR4					*/
-#define	PFS5E_SPI		0x0040			/* 		Enable SPI_SSEL5			*/
-
-#define	PFS4E			0x0080			/* Port F SPI SSEL 4 Enable			*/
-#define	PFS4E_TIMER		0x0000			/*		Enable TMR3					*/
-#define	PFS4E_SPI		0x0080			/* 		Enable SPI_SSEL4			*/
-
-#define	PFFE			0x0100			/* Port F PPI Frame Sync Enable		*/
-#define	PFFE_TIMER		0x0000			/* 		Enable TMR2					*/
-#define	PFFE_PPI		0x0100			/* 		Enable PPI FS3				*/
-
-#define	PGSE			0x0200			/* Port G SPORT1 Secondary Enable	*/
-#define	PGSE_PPI		0x0000			/* 		Enable PPI D9:8				*/
-#define	PGSE_SPORT		0x0200			/* 		Enable DR1SEC/DT1SEC		*/
-
-#define	PGRE			0x0400			/* Port G SPORT1 Receive Enable		*/
-#define	PGRE_PPI		0x0000			/* 		Enable PPI D12:10			*/
-#define	PGRE_SPORT		0x0400			/* 		Enable DR1PRI/RFS1/RSCLK1	*/
-
-#define	PGTE			0x0800			/* Port G SPORT1 Transmit Enable	*/
-#define	PGTE_PPI		0x0000			/* 		Enable PPI D15:13			*/
-#define	PGTE_SPORT		0x0800			/* 		Enable DT1PRI/TFS1/TSCLK1	*/
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks														*/
-#define	HMDMAEN		0x0001	/* Enable Handshake DMA 0/1					*/
-#define	REP			0x0002	/* HDMA Request Polarity					*/
-#define	UTE			0x0004	/* Urgency Threshold Enable					*/
-#define	OIE			0x0010	/* Overflow Interrupt Enable				*/
-#define	BDIE		0x0020	/* Block Done Interrupt Enable				*/
-#define	MBDI		0x0040	/* Mask Block Done IRQ If Pending ECNT		*/
-#define	DRQ			0x0300	/* HDMA Request Type						*/
-#define	DRQ_NONE	0x0000	/* 		No Request							*/
-#define	DRQ_SINGLE	0x0100	/* 		Channels Request Single				*/
-#define	DRQ_MULTI	0x0200	/* 		Channels Request Multi (Default)	*/
-#define	DRQ_URGENT	0x0300	/* 		Channels Request Multi Urgent		*/
-#define	RBC			0x1000	/* Reload BCNT With IBCNT					*/
-#define	PS			0x2000	/* HDMA Pin Status							*/
-#define	OI			0x4000	/* Overflow Interrupt Generated				*/
-#define	BDI			0x8000	/* Block Done Interrupt Generated			*/
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define	PGDE_UART   PFDE_UART
-#define	PGDE_DMA    PFDE_DMA
-#define	CKELOW		SCKELOW
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF534_H */
-
diff --git a/libgloss/bfin/include/defBF535.h b/libgloss/bfin/include/defBF535.h
deleted file mode 100644
index babae8c30..000000000
--- a/libgloss/bfin/include/defBF535.h
+++ /dev/null
@@ -1,1154 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defBF535.h
- *
- * (c) Copyright 2001-2008 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
-
-#ifndef _DEF_BF535_H
-#define _DEF_BF535_H
-
-#if defined(__ADSPLPBLACKFIN__)
-#warning defBF535.h should only be included for 535 compatible chips.
-#endif
-/* include all Core registers and bit definitions */
-#include <defblackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macro definitions not MISRA compliant")
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* Memory Map */
-/*********************************************************************************** */
-
-/* Core MMRs */
-#define COREMMR_BASE           0xFFE00000     /* Core MMRs */
-#define COREMMR_SIZE           0x200000       /* 2MB */
-
-/* System MMRs */
-#define SYSMMR_BASE            0xFFC00000     /* System MMRs */
-#define SYSMMR_SIZE            0x200000       /* 2MB */
-
-/* L1 cache/SRAM internal memory */
-#define L1_DATA_A		0xFF800000	/* L1 Data Bank A */
-#define L1_DATA_B		0xFF900000	/* L1 Data Bank B */
-#define L1_DATA_SIZE		0x4000		/*  16K */
-#define L1_CODE			0xFFA00000	/* L1 Code SRAM */
-#define L1_CODE_SIZE		0x4000		/*  16K */
-#define L1_SCRATCH		0xFFB00000	/* L1 Scratch SRAM */
-#define L1_SCRATCH_SIZE		0x1000		/*  4K */
-
-/* L2 SRAM external memory */
-#define L2_BASE			0xF0000000	/* L2 SRAM */
-#define L2_SIZE			0x40000		/*  256K */
-
-/* PCI Spaces */
-#define PCI_CONFIG_SPACE_PORT	0xEEFFFFFC	/* PCI config space reg */
-#define PCI_CONFIG_BASE		0xEEFFFF00	/* PCI config region */
-#define PCI_CONFIG_SIZE		0x10000		/*  64K */
-#define PCI_IO_BASE		0xEEFE0000	/* PCI I/O space */
-#define PCI_IO_SIZE		0x10000		/*  64K */
-#define PCI_MEM_BASE		0xE0000000	/* PCI Mem space */
-#define PCI_MEM_SIZE		0x8000000	/*  64K */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE	0x2C000000	/* Async Bank 3 */
-#define ASYNC_BANK3_SIZE	0x4000000	/*  64 MB */
-#define ASYNC_BANK2_BASE	0x28000000	/* Async Bank 2 */
-#define ASYNC_BANK2_SIZE	0x4000000	/*  64 MB */
-#define ASYNC_BANK1_BASE	0x24000000	/* Async Bank 1 */
-#define ASYNC_BANK1_SIZE	0x4000000	/*  64 MB */
-#define ASYNC_BANK0_BASE	0x20000000	/* Async Bank 0 */
-#define ASYNC_BANK0_SIZE	0x4000000	/*  64 MB */
-
-/* Sync DRAM Banks */
-#define SDRAM_BANK3_BASE	0x18000000	/* Sync Bank 3 */
-#define SDRAM_BANK2_BASE	0x10000000	/* Sync Bank 2 */
-#define SDRAM_BANK1_BASE	0x08000000	/* Sync Bank 1 */
-#define SDRAM_BANK0_BASE	0x00000000	/* Sync Bank 0 */
-
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF) */
-#define MISR_CTL               0xFFC00000     /* Control Register */
-#define MISR_RMISR0            0xFFC00004     /* coreL2[31:0] read bus */
-#define MISR_RMISR1            0xFFC00008     /* coreL2[63:32] read bus */
-#define MISR_RMISR2            0xFFC0000C     /* sysL2[31:0] read bus */
-#define MISR_WMISR0            0xFFC00010     /* coreL2[31:0] write bus */
-#define MISR_WMISR1            0xFFC00014     /* coreL2[63:32] write bus */
-#define MISR_WMISR2            0xFFC00018     /* sysL2[31:0] write bus */
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define PLL_CTL                0xFFC00400      /* PLL Control register (32-bit) */
-#define PLL_STAT               0xFFC00404      /* PLL Status register */
-#define PLL_LOCKCNT            0xFFC00406      /* PLL Lock Counter register */
-#define PLL_IOCKR              0xFFC00408      /* Peripheral Clock Enable register (32-bit) */
-#define PLL_IOCK               0xFFC00408      /* Peripheral Clock Enable register (32-bit) - alternate spelling */
-#define SWRST                  0xFFC00410      /* Software Reset Register */
-
-#define PLLCTL			PLL_CTL
-#define PLLSTAT			PLL_STAT
-#define LOCKCNT			PLL_LOCKCNT
-#define IOCKR			PLL_IOCKR
-
-#define SYSCR                  0xFFC00414      /* System Configuration register (RCSR) */
-
-/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
-#define CHIPID                 0xFFC048C0      /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define SIC_IAR0               0xFFC00C04  /* Interrupt Assignment Register 0 */
-#define SIC_IAR1               0xFFC00C08  /* Interrupt Assignment Register 1 */
-#define SIC_IAR2               0xFFC00C0C  /* Interrupt Assignment Register 2 */
-#define SIC_IMASK              0xFFC00C10  /* Interrupt Mask Register */
-#define SIC_ISR                0xFFC00C14  /* Interrupt Status Register */
-#define SIC_IWR                0xFFC00C18  /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define WDOGCTL                0xFFC01000  /* Watchdog Control Register */
-#define WDOGCNT                0xFFC01004  /* Watchdog Count Register */
-#define WDOGSTAT               0xFFC01008  /* Watchdog Status Register */
-
-#define WDOG_CTL		WDOGCTL
-#define WDOG_CNT		WDOGCNT
-#define WDOG_STAT		WDOGSTAT
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define RTCSTAT                0xFFC01400  /* RTC Status Register */
-#define RTCICTL                0xFFC01404  /* RTC Interrupt Control Register */
-#define RTCISTAT               0xFFC01408  /* RTC Interrupt Status Register */
-#define RTCSWCNT               0xFFC0140C  /* RTC Stopwatch Count Register */
-#define RTCALARM               0xFFC01410  /* RTC Alarm Time Register */
-#define RTCFAST                0xFFC01414  /* RTC Prescaler Control Register */
-
-#define RTC_STAT		RTCSTAT
-#define RTC_ICTL		RTCICTL
-#define RTC_ISTAT		RTCISTAT
-#define RTC_SWCNT		RTCSWCNT
-#define RTC_ALARM		RTCALARM
-#define RTC_FAST		RTCFAST
-
-/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
-#define UART0_THR              0xFFC01800  /* Transmit Holding register */
-#define UART0_RBR              0xFFC01800  /* Receive Buffer register */
-#define UART0_DLL              0xFFC01800  /* Divisor Latch (Low-Byte) */
-#define UART0_IER              0xFFC01802  /* Interrupt Enable Register */
-#define UART0_DLH              0xFFC01802  /* Divisor Latch (High-Byte) */
-#define UART0_IIR              0xFFC01804  /* Interrupt Identification Register */
-#define UART0_LCR              0xFFC01806  /* Line Control Register */
-#define UART0_MCR              0xFFC01808  /* Module Control Register */
-#define UART0_LSR              0xFFC0180A  /* Line Status Register */
-#define UART0_MSR              0xFFC0180C  /* MSR Modem Status Register */
-#define UART0_SCR              0xFFC0180E  /* SCR Scratch Register */
-#define UART0_IRCR             0xFFC01810  /* IRCR IrDA Control Register */
-#define UART0_CURR_PTR_RX      0xFFC01A00  /* UART -DMA RCV Current Pointer register */
-#define UART0_CONFIG_RX        0xFFC01A02  /* UART -RCV DMA Configuration register */
-#define UART0_START_ADDR_HI_RX 0xFFC01A04  /* UART -RCV DMA Start Page register */
-#define UART0_START_ADDR_LO_RX 0xFFC01A06  /* UART -RCV DMA Start Address register */
-#define UART0_COUNT_RX         0xFFC01A08  /* UART -RCV DMA Count register */
-#define UART0_NEXT_DESCR_RX    0xFFC01A0A  /* UART -RCV DMA Next Descriptor Pointer register */
-#define UART0_DESCR_RDY_RX     0xFFC01A0C  /* UART -RCV DMA Descriptor Ready */
-#define UART0_IRQSTAT_RX       0xFFC01A0E  /* UART -RCV DMA Interrupt Register */
-#define UART0_CURR_PTR_TX      0xFFC01B00  /* UART -XMT DMA Current Pointer register */
-#define UART0_CONFIG_TX        0xFFC01B02  /* UART -XMT DMA Configuration register */
-#define UART0_START_ADDR_HI_TX 0xFFC01B04  /* UART -XMT DMA Start Page register */
-#define UART0_START_ADDR_LO_TX 0xFFC01B06  /* UART -XMT DMA Start Address register */
-#define UART0_COUNT_TX         0xFFC01B08  /* UART -XMT DMA Count register */
-#define UART0_NEXT_DESCR_TX    0xFFC01B0A  /* UART -XMT DMA Next Descriptor Pointer register */
-#define UART0_DESCR_RDY_TX     0xFFC01B0C  /* UART -XMT DMA Descriptor Ready */
-#define UART0_IRQSTAT_TX       0xFFC01B0E  /* UART -XMT DMA Interrupt register */
-
-/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
-#define UART1_THR              0xFFC01C00  /* Transmit Holding register */
-#define UART1_RBR              0xFFC01C00  /* Receive Buffer register */
-#define UART1_DLL              0xFFC01C00  /* Divisor Latch (Low-Byte) */
-#define UART1_IER              0xFFC01C02  /* Interrupt Enable Register */
-#define UART1_DLH              0xFFC01C02  /* Divisor Latch (High-Byte) */
-#define UART1_IIR              0xFFC01C04  /* Interrupt Identification Register */
-#define UART1_LCR              0xFFC01C06  /* Line Control Register */
-#define UART1_MCR              0xFFC01C08  /* Module Control Register */
-#define UART1_LSR              0xFFC01C0A  /* Line Status Register */
-#define UART1_MSR              0xFFC01C0C  /* MSR Modem Status Register */
-#define UART1_SCR              0xFFC01C0E  /* SCR Scratch Register */
-#define UART1_CURR_PTR_RX      0xFFC01E00  /* UART -DMA RCV Current Pointer register */
-#define UART1_CONFIG_RX        0xFFC01E02  /* UART -RCV DMA Configuration register */
-#define UART1_START_ADDR_HI_RX 0xFFC01E04  /* UART -RCV DMA Start Page register */
-#define UART1_START_ADDR_LO_RX 0xFFC01E06  /* UART -RCV DMA Start Address register */
-#define UART1_COUNT_RX         0xFFC01E08  /* UART -RCV DMA Count register */
-#define UART1_NEXT_DESCR_RX    0xFFC01E0A  /* UART -RCV DMA Next Descriptor Pointer register */
-#define UART1_DESCR_RDY_RX     0xFFC01E0C  /* UART -RCV DMA Descriptor Ready */
-#define UART1_IRQSTAT_RX       0xFFC01E0E  /* UART -RCV DMA Interrupt Register */
-#define UART1_CURR_PTR_TX      0xFFC01F00  /* UART -XMT DMA Current Pointer register */
-#define UART1_CONFIG_TX        0xFFC01F02  /* UART -XMT DMA Configuration register */
-#define UART1_START_ADDR_HI_TX 0xFFC01F04  /* UART -XMT DMA Start Page register */
-#define UART1_START_ADDR_LO_TX 0xFFC01F06  /* UART -XMT DMA Start Address register */
-#define UART1_COUNT_TX         0xFFC01F08  /* UART -XMT DMA Count register */
-#define UART1_NEXT_DESCR_TX    0xFFC01F0A  /* UART -XMT DMA Next Descriptor Pointer register */
-#define UART1_DESCR_RDY_TX     0xFFC01F0C  /* UART -XMT DMA Descriptor Ready */
-#define UART1_IRQSTAT_TX       0xFFC01F0E  /* UART -XMT DMA Interrupt register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
-#define TIMER0_STATUS          0xFFC02000  /* Timer 0 Global Status and Sticky Register */
-#define TIMER0_CONFIG          0xFFC02002  /* Timer 0 configuration Register */
-#define TIMER0_COUNTER_LO      0xFFC02004  /* Timer 0 Counter Register (low word) */
-#define TIMER0_COUNTER_HI      0xFFC02006  /* Timer 0 Counter Register (high word) */
-#define TIMER0_PERIOD_LO       0xFFC02008  /* Timer 0 Period Register (low word) */
-#define TIMER0_PERIOD_HI       0xFFC0200A  /* Timer 0 Period Register (high word) */
-#define TIMER0_WIDTH_LO        0xFFC0200C  /* Timer 0 Width Register (low word) */
-#define TIMER0_WIDTH_HI        0xFFC0200E  /* Timer 0 Width Register (high word) */
-#define TIMER1_STATUS          0xFFC02010  /* Timer 1 Global Status and Sticky Register */
-#define TIMER1_CONFIG          0xFFC02012  /* Timer 1 configuration register */
-#define TIMER1_COUNTER_LO      0xFFC02014  /* Timer 1 Counter Register (low word) */
-#define TIMER1_COUNTER_HI      0xFFC02016  /* Timer 1 Counter Register (high word) */
-#define TIMER1_PERIOD_LO       0xFFC02018  /* Timer 1 Period Register (low word) */
-#define TIMER1_PERIOD_HI       0xFFC0201A  /* Timer 1 Period Register (high word) */
-#define TIMER1_WIDTH_LO        0xFFC0201C  /* Timer 1 Width Register (low word) */
-#define TIMER1_WIDTH_HI        0xFFC0201E  /* Timer 1 Width Register (high word) */
-#define TIMER2_STATUS          0xFFC02020  /* Timer 2 Global Status and Sticky Register */
-#define TIMER2_CONFIG          0xFFC02022  /* Timer 2 configuration register */
-#define TIMER2_COUNTER_LO      0xFFC02024  /* Timer 2 Counter Register (low word) */
-#define TIMER2_COUNTER_HI      0xFFC02026  /* Timer 2 Counter Register (high word) */
-#define TIMER2_PERIOD_LO       0xFFC02028  /* Timer 2 Period Register (low word) */
-#define TIMER2_PERIOD_HI       0xFFC0202A  /* Timer 2 Period Register (high word) */
-#define TIMER2_WIDTH_LO        0xFFC0202C  /* Timer 2 Width Register (low word) */
-#define TIMER2_WIDTH_HI        0xFFC0202E  /* Timer 2 Width Register (high word) */
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define FIO_DIR                0xFFC02400  /* Peripheral Flag Direction Register */
-#define FIO_FLAG_C             0xFFC02404  /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S             0xFFC02406  /* Peripheral Interrupt Flag Register (set) */
-#define FIO_MASKA_C            0xFFC02408  /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S            0xFFC0240A  /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKB_C            0xFFC0240C  /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S            0xFFC0240E  /* Flag Mask Interrupt B Register (set) */
-#define FIO_POLAR              0xFFC02410  /* Flag Source Polarity Register */
-#define FIO_EDGE               0xFFC02414  /* Flag Source Sensitivity Register */
-#define FIO_BOTH               0xFFC02418  /* Flag Set on BOTH Edges Register */
-
-/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
-#define SPORT0_TX_CONFIG       0xFFC02800  /* SPORT0 Transmit Configuration Register */
-#define SPORT0_RX_CONFIG       0xFFC02802  /* SPORT0 Receive Configuration Register */
-#define SPORT0_TX              0xFFC02804  /* SPORT0 TX transmit Register */
-#define SPORT0_RX              0xFFC02806  /* SPORT0 RX Receive register */
-#define SPORT0_TSCLKDIV        0xFFC02808  /* SPORT0 Transmit Serial Clock Divider */
-#define SPORT0_RSCLKDIV        0xFFC0280A  /* SPORT0 Receive Serial Clock Divider */
-#define SPORT0_TFSDIV          0xFFC0280C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_RFSDIV          0xFFC0280E  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT            0xFFC02810  /* SPORT0 Status Register */
-#define SPORT0_MTCS0           0xFFC02812  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS1           0xFFC02814  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS2           0xFFC02816  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS3           0xFFC02818  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS4           0xFFC0281A  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS5           0xFFC0281C  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS6           0xFFC0281E  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MTCS7           0xFFC02820  /* SPORT0 Multi-Channel Transmit Select Register */
-#define SPORT0_MRCS0           0xFFC02822  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS1           0xFFC02824  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS2           0xFFC02826  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS3           0xFFC02828  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS4           0xFFC0282A  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS5           0xFFC0282C  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS6           0xFFC0282E  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MRCS7           0xFFC02830  /* SPORT0 Multi-Channel Receive Select Register */
-#define SPORT0_MCMC1           0xFFC02832  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2           0xFFC02834  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_CURR_PTR_RX     0xFFC02A00  /* SPORT0 -RCV DMA Current Pointer */
-#define SPORT0_CONFIG_DMA_RX   0xFFC02A02  /* SPORT0 -RCV DMA Configuration */
-#define SPORT0_START_ADDR_HI_RX 0xFFC02A04 /* SPORT0 -RCV DMA Start Page */
-#define SPORT0_START_ADDR_LO_RX 0xFFC02A06 /* SPORT0 -RCV DMA Start Address */
-#define SPORT0_COUNT_RX        0xFFC02A08  /* SPORT0 -RCV DMA Count */
-#define SPORT0_NEXT_DESCR_RX   0xFFC02A0A  /* SPORT0 -RCV DMA Next Descriptor Pointer */
-#define SPORT0_DESCR_RDY_RX    0xFFC02A0C  /* SPORT0 -RCV DMA Descriptor Ready */
-#define SPORT0_IRQSTAT_RX      0xFFC02A0E  /* SPORT0 -RCV DMA Interrupt Register */
-#define SPORT0_CURR_PTR_TX     0xFFC02B00  /* SPORT0 -XMT DMA Current Pointer */
-#define SPORT0_CONFIG_DMA_TX   0xFFC02B02  /* SPORT0 -XMT DMA Configuration */
-#define SPORT0_START_ADDR_HI_TX 0xFFC02B04 /* SPORT0 -XMT DMA Start Page */
-#define SPORT0_START_ADDR_LO_TX 0xFFC02B06 /* SPORT0 -XMT DMA Start Address */
-#define SPORT0_COUNT_TX        0xFFC02B08  /* SPORT0 -XMT DMA Count */
-#define SPORT0_NEXT_DESCR_TX   0xFFC02B0A  /* SPORT0 -XMT DMA Next Descriptor Pointer */
-#define SPORT0_DESCR_RDY_TX    0xFFC02B0C  /* SPORT0 -XMT DMA Descriptor Ready */
-#define SPORT0_IRQSTAT_TX      0xFFC02B0E  /* SPORT0 -XMT DMA Interrupt Register */
-
-/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
-#define SPORT1_TX_CONFIG       0xFFC02C00  /* SPORT1 Transmit Configuration Register */
-#define SPORT1_RX_CONFIG       0xFFC02C02  /* SPORT1 Receive Configuration Register */
-#define SPORT1_TX              0xFFC02C04  /* SPORT1 TX transmit Register */
-#define SPORT1_RX              0xFFC02C06  /* SPORT1 RX Receive register */
-#define SPORT1_TSCLKDIV        0xFFC02C08  /* SPORT1 Transmit Serial Clock Divider */
-#define SPORT1_RSCLKDIV        0xFFC02C0A  /* SPORT1 Receive Serial Clock Divider */
-#define SPORT1_TFSDIV          0xFFC02C0C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_RFSDIV          0xFFC02C0E  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT            0xFFC02C10  /* SPORT1 Status Register */
-#define SPORT1_MTCS0           0xFFC02C12  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS1           0xFFC02C14  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS2           0xFFC02C16  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS3           0xFFC02C18  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS4           0xFFC02C1A  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS5           0xFFC02C1C  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS6           0xFFC02C1E  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MTCS7           0xFFC02C20  /* SPORT1 Multi-Channel Transmit Select Register */
-#define SPORT1_MRCS0           0xFFC02C22  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS1           0xFFC02C24  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS2           0xFFC02C26  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS3           0xFFC02C28  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS4           0xFFC02C2A  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS5           0xFFC02C2C  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS6           0xFFC02C2E  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MRCS7           0xFFC02C30  /* SPORT1 Multi-Channel Receive Select Register */
-#define SPORT1_MCMC1           0xFFC02C32  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2           0xFFC02C34  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_CURR_PTR_RX     0xFFC02E00  /* SPORT1 -RCV DMA Current Pointer */
-#define SPORT1_CONFIG_DMA_RX   0xFFC02E02  /* SPORT1 -RCV DMA Configuration */
-#define SPORT1_START_ADDR_HI_RX 0xFFC02E04 /* SPORT1 -RCV DMA Start Page */
-#define SPORT1_START_ADDR_LO_RX 0xFFC02E06 /* SPORT1 -RCV DMA Start Address */
-#define SPORT1_COUNT_RX        0xFFC02E08  /* SPORT1 -RCV DMA Count */
-#define SPORT1_NEXT_DESCR_RX   0xFFC02E0A  /* SPORT1 -RCV DMA Next Descriptor Pointer */
-#define SPORT1_DESCR_RDY_RX    0xFFC02E0C  /* SPORT1 -RCV DMA Descriptor Ready */
-#define SPORT1_IRQSTAT_RX      0xFFC02E0E  /* SPORT1 -RCV DMA Interrupt Register */
-#define SPORT1_CURR_PTR_TX     0xFFC02F00  /* SPORT1 -XMT DMA Current Pointer */
-#define SPORT1_CONFIG_DMA_TX   0xFFC02F02  /* SPORT1 -XMT DMA Configuration */
-#define SPORT1_START_ADDR_HI_TX 0xFFC02F04 /* SPORT1 -XMT DMA Start Page */
-#define SPORT1_START_ADDR_LO_TX 0xFFC02F06 /* SPORT1 -XMT DMA Start Address */
-#define SPORT1_COUNT_TX        0xFFC02F08  /* SPORT1 -XMT DMA Count */
-#define SPORT1_NEXT_DESCR_TX   0xFFC02F0A  /* SPORT1 -XMT DMA Next Descriptor Pointer */
-#define SPORT1_DESCR_RDY_TX    0xFFC02F0C  /* SPORT1 -XMT DMA Descriptor Ready */
-#define SPORT1_IRQSTAT_TX      0xFFC02F0E  /* SPORT1 -XMT DMA Interrupt Register */
-
-/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
-#define SPI0_CTL               0xFFC03000  /* SPI0 Control Register */
-#define SPI0_FLG               0xFFC03002  /* SPI0 Flag register */
-#define SPI0_ST                0xFFC03004  /* SPI0 Status register */
-#define SPI0_TDBR              0xFFC03006  /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR              0xFFC03008  /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD              0xFFC0300A  /* SPI0 Baud rate Register */
-#define SPI0_SHADOW            0xFFC0300C
-#define SPI0_CURR_PTR          0xFFC03200  /* SPI0 -DMA Current Pointer register */
-#define SPI0_CONFIG            0xFFC03202  /* SPI0 -DMA Configuration register */
-#define SPI0_START_ADDR_HI     0xFFC03204  /* SPI0 -DMA Start Page register */
-#define SPI0_START_ADDR_LO     0xFFC03206  /* SPI0 -DMA Start Address register */
-#define SPI0_COUNT             0xFFC03208  /* SPI0 -DMA Count register */
-#define SPI0_NEXT_DESCR        0xFFC0320A  /* SPI0 -DMA Next Descriptor Pointer */
-#define SPI0_DESCR_RDY         0xFFC0320C  /* SPI0 -DMA Descriptor Ready */
-#define SPI0_DMA_INT           0xFFC0320E  /* SPI0 -DMA Interrupt register */
-
-/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
-#define SPI1_CTL               0xFFC03400  /* SPI1 Control Register */
-#define SPI1_FLG               0xFFC03402  /* SPI1 Flag register */
-#define SPI1_ST                0xFFC03404  /* SPI1 Status register */
-#define SPI1_TDBR              0xFFC03406  /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR              0xFFC03408  /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD              0xFFC0340A  /* SPI1 Baud rate Register */
-#define SPI1_SHADOW            0xFFC0340C
-#define SPI1_CURR_PTR          0xFFC03600  /* SPI1 -DMA Current Pointer register */
-#define SPI1_CONFIG            0xFFC03602  /* SPI1 -DMA Configuration register */
-#define SPI1_START_ADDR_HI     0xFFC03604  /* SPI1 -DMA Start Page register */
-#define SPI1_START_ADDR_LO     0xFFC03606  /* SPI1 -DMA Start Address register */
-#define SPI1_COUNT             0xFFC03608  /* SPI1 -DMA Count register */
-#define SPI1_NEXT_DESCR        0xFFC0360A  /* SPI1 -DMA Next Descriptor Pointer */
-#define SPI1_DESCR_RDY         0xFFC0360C  /* SPI1 -DMA Descriptor Ready */
-#define SPI1_DMA_INT           0xFFC0360E  /* SPI1 -DMA Interrupt register */
-
-/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
-#define MDD_DCP                0xFFC03800  /* Current Pointer - Write Channel */
-#define MDD_DCFG               0xFFC03802  /* DMA Configuration - Write Channel */
-#define MDD_DSAH               0xFFC03804  /* Start Address Hi - Write Channel */
-#define MDD_DSAL               0xFFC03806  /* Start Address Lo - Write Channel */
-#define MDD_DCT                0xFFC03808  /* DMA Count - Write Channel */
-#define MDD_DND                0xFFC0380A  /* Next Descriptor Pointer - Write Channel */
-#define MDD_DDR                0xFFC0380C  /* Descriptor Ready - Write Channel */
-#define MDD_DI                 0xFFC0380E  /* DMA Interrupt - Write Channel */
-#define MDS_DCP                0xFFC03900  /* Current Pointer - Read Channel */
-#define MDS_DCFG               0xFFC03902  /* DMA Configuration - Read Channel */
-#define MDS_DSAH               0xFFC03904  /* Start Address Hi - Read Channel */
-#define MDS_DSAL               0xFFC03906  /* Start Address Lo - Read Channel */
-#define MDS_DCT                0xFFC03908  /* DMA Count - Read Channel */
-#define MDS_DND                0xFFC0390A  /* Next Descriptor Pointer - Read Channel */
-#define MDS_DDR                0xFFC0390C  /* Descriptor Ready - Read Channel */
-#define MDS_DI                 0xFFC0390E  /* DMA Interrupt - Read Channel */
-
-/* For backwards-compatibility with VDSP++3.0 and earlier code... */
-#define MDW_DCP                MDD_DCP
-#define MDW_DCFG               MDD_DCFG
-#define MDW_DSAH               MDD_DSAH
-#define MDW_DSAL               MDD_DSAL
-#define MDW_DCT                MDD_DCT
-#define MDW_DND                MDD_DND
-#define MDW_DDR                MDD_DDR
-#define MDW_DI                 MDD_DI
-#define MDR_DCP                MDS_DCP
-#define MDR_DCFG               MDS_DCFG
-#define MDR_DSAH               MDS_DSAH
-#define MDR_DSAL               MDS_DSAL
-#define MDR_DCT                MDS_DCT
-#define MDR_DND                MDS_DND
-#define MDR_DDR                MDS_DDR
-#define MDR_DI                 MDS_DI
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define EBIU_AMGCTL            0xFFC03C00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0           0xFFC03C04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1           0xFFC03C08  /* Asynchronous Memory Bank Control Register 1 */
-
-/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
-#define PCI_CTL                0xFFC04000  /* PCI Bridge Control */
-#define  PCI_CTL_HOST	 	 0x01
-#define  PCI_CTL_ENABPCI	 0x02
-#define  PCI_CTL_FASTBCK2BCK	 0x04
-#define  PCI_CTL_ENABINTA	 0x08
-#define  PCI_CTL_OUTPUTINTA	 0x10
-#define  PCI_CTL_ENABRST	 0x20
-#define  PCI_CTL_OUTPUTRST	 0x40
-
-
-#define PCI_STAT               0xFFC04004  /* PCI Bridge Status */
-#define   PCI_STAT_INTA	         0x0001
-#define   PCI_STAT_INTB	         0x0002
-#define   PCI_STAT_INTC	         0x0004
-#define   PCI_STAT_INTD	         0x0008
-#define   PCI_STAT_PARERR	 0x0010
-#define   PCI_STAT_FATERR	 0x0020
-#define   PCI_STAT_RESET	 0x0040
-#define   PCI_STAT_TXEMPTY	 0x0080
-#define   PCI_STAT_TXFULL	 0x0100
-#define   PCI_STAT_QUEFULL	 0x0200
-#define   PCI_STAT_MEMWRINV	 0x0400
-#define   PCI_STAT_INRDERR	 0x0800
-#define   PCI_STAT_INWRERR	 0x1000
-#define   PCI_STAT_INVEABACC	 0x2000
-#define   PCI_STAT_SYSERR	 0x4000
-
-#define PCI_ICTL               0xFFC04008  /* PCI Bridge Interrupt Control */
-#define   PCI_ICTL_INTA	         0x0001
-#define   PCI_ICTL_INTB	         0x0002
-#define   PCI_ICTL_INTC	         0x0004
-#define   PCI_ICTL_INTD	         0x0008
-#define   PCI_ICTL_PARERR	 0x0010
-#define   PCI_ICTL_FATERR	 0x0020
-#define   PCI_ICTL_RESET	 0x0040
-#define   PCI_ICTL_TXFULL	 0x0080
-#define   PCI_ICTL_MEMWRINV	 0x0400
-#define   PCI_ICTL_INRDERR	 0x0800
-#define   PCI_ICTL_INWRERR	 0x1000
-#define   PCI_ICTL_INVEABACC	 0x2000
-#define   PCI_ICTL_SYSERR	 0x4000
-
-#define PCI_MBAP               0xFFC0400C  /* PCI Memory Space Base Address Pointer [31:27] */
-#define PCI_IBAP               0xFFC04010  /* PCI IO Space Base Address Pointer */
-#define PCI_CBAP               0xFFC04014  /* PCI Config Space Base Address Port */
-#define PCI_TMBAP              0xFFC04018  /* PCI to BF535 Memory Base Address Pointer */
-#define PCI_TIBAP              0xFFC0401C  /* PCI to BF535 IO Base Address Pointer */
-
-/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
-#define PCI_DMBARM             0xEEFFFF00  /* PCI Device Memory Bar Mask */
-#define PCI_DIBARM             0xEEFFFF04  /* PCI Device IO Bar Mask */
-#define PCI_CFG_DIC            0xEEFFFF08  /* PCI Config Device ID */
-#define PCI_CFG_VIC            0xEEFFFF0C  /* PCI Config Vendor ID */
-#define PCI_CFG_STAT           0xEEFFFF10  /* PCI Config Status (Read-only) */
-#define PCI_CFG_CMD            0xEEFFFF14  /* PCI Config Command */
-#define PCI_CFG_CC             0xEEFFFF18  /* PCI Config Class Code */
-#define PCI_CFG_RID            0xEEFFFF1C  /* PCI Config Revision ID */
-#define PCI_CFG_BIST           0xEEFFFF20  /* PCI Config BIST */
-#define PCI_CFG_HT             0xEEFFFF24  /* PCI Config Header Type */
-#define PCI_CFG_MLT            0xEEFFFF28  /* PCI Config Memory Latency Timer */
-#define PCI_CFG_CLS            0xEEFFFF2C  /* PCI Config Cache Line Size */
-#define PCI_CFG_MBAR           0xEEFFFF30  /* PCI Config Memory Base Address Register */
-#define PCI_CFG_IBAR           0xEEFFFF34  /* PCI Config IO Base Address Register */
-#define PCI_CFG_SID            0xEEFFFF38  /* PCI Config Sub-system ID */
-#define PCI_CFG_SVID           0xEEFFFF3C  /* PCI Config Sub-system Vendor ID */
-#define PCI_CFG_MAXL           0xEEFFFF40  /* PCI Config Maximum Latency Cycles */
-#define PCI_CFG_MING           0xEEFFFF44  /* PCI Config Minimum Grant Cycles */
-#define PCI_CFG_IP             0xEEFFFF48  /* PCI Config Interrupt Pin */
-#define PCI_CFG_IL             0xEEFFFF4C  /* PCI Config Interrupt Line */
-#define PCI_HMCTL              0xEEFFFF50  /* PCI Blocking BAR Host Mode Control */
-
-#define  PCI_HMCTL_SYSMMRENAB	 0x1
-#define  PCI_HMCTL_L2ENAB	 0x2
-#define  PCI_HMCTL_ASYNCENAB	 0x4
-#define  PCI_HMCTL_ASYNCSIZE	 0x18	/* 00-64MB, 01-128MB, 10-192MB, 11-256MB */
-#define  PCI_HMCTL_SDRAMENAB	 0x20
-#define  PCI_HMCTL_SDRAMSIZE	 0x7C0	/* 0-32MB, 1-64MB, 2-96MB, 128MB, 160MB */
-
-/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
-#define USBD_ID                0xFFC04400  /* USB Device ID Register */
-#define USBD_FRM               0xFFC04402  /* Current USB Frame Number */
-#define USBD_FRMAT             0xFFC04404  /* Match value for USB frame number. */
-#define USBD_EPBUF             0xFFC04406  /* Enables Download of Configuration Into UDC Core */
-#define USBD_STAT              0xFFC04408  /* Returns USBD Module Status */
-#define USBD_CTRL              0xFFC0440A  /* Allows Configuration and Control of USBD Module. */
-#define USBD_GINTR             0xFFC0440C  /* Global Interrupt Register */
-#define USBD_GMASK             0xFFC0440E  /* Global Interrupt Register Mask */
-#define USBD_DMACFG            0xFFC04440  /* DMA Master Channel Configuration Register */
-#define USBD_DMABL             0xFFC04442  /* DMA Master Channel Base Address, Low */
-#define USBD_DMABH             0xFFC04444  /* DMA Master Channel Base Address, High */
-#define USBD_DMACT             0xFFC04446  /* DMA Master Channel Count Register */
-#define USBD_DMAIRQ            0xFFC04448  /* DMA Master Channel DMA Count Register */
-#define USBD_INTR0             0xFFC04480  /* USB Endpoint 0 Interrupt Register */
-#define USBD_MASK0             0xFFC04482  /* USB Endpoint 0 Mask Register */
-#define USBD_EPCFG0            0xFFC04484  /* USB Endpoint 0 Control Register */
-#define USBD_EPADR0            0xFFC04486  /* USB Endpoint 0 Address Offset Register */
-#define USBD_EPLEN0            0xFFC04488  /* USB Endpoint 0 Buffer Length Register */
-#define USBD_INTR1             0xFFC0448A  /* USB Endpoint 1 Interrupt Register */
-#define USBD_MASK1             0xFFC0448C  /* USB Endpoint 1 Mask Register */
-#define USBD_EPCFG1            0xFFC0448E  /* USB Endpoint 1 Control Register */
-#define USBD_EPADR1            0xFFC04490  /* USB Endpoint 1 Address Offset Register */
-#define USBD_EPLEN1            0xFFC04492  /* USB Endpoint 1 Buffer Length Register */
-#define USBD_INTR2             0xFFC04494  /* USB Endpoint 2 Interrupt Register */
-#define USBD_MASK2             0xFFC04496  /* USB Endpoint 2 Mask Register */
-#define USBD_EPCFG2            0xFFC04498  /* USB Endpoint 2 Control Register */
-#define USBD_EPADR2            0xFFC0449A  /* USB Endpoint 2 Address Offset Register */
-#define USBD_EPLEN2            0xFFC0449C  /* USB Endpoint 2 Buffer Length Register */
-#define USBD_INTR3             0xFFC0449E  /* USB Endpoint 3 Interrupt Register */
-#define USBD_MASK3             0xFFC044A0  /* USB Endpoint 3 Mask Register */
-#define USBD_EPCFG3            0xFFC044A2  /* USB Endpoint 3 Control Register */
-#define USBD_EPADR3            0xFFC044A4  /* USB Endpoint 3 Address Offset Register */
-#define USBD_EPLEN3            0xFFC044A6  /* USB Endpoint 3 Buffer Length Register */
-#define USBD_INTR4             0xFFC044A8  /* USB Endpoint 4 Interrupt Register */
-#define USBD_MASK4             0xFFC044AA  /* USB Endpoint 4 Mask Register */
-#define USBD_EPCFG4            0xFFC044AC  /* USB Endpoint 4 Control Register */
-#define USBD_EPADR4            0xFFC044AE  /* USB Endpoint 4 Address Offset Register */
-#define USBD_EPLEN4            0xFFC044B0  /* USB Endpoint 4 Buffer Length Register */
-#define USBD_INTR5             0xFFC044B2  /* USB Endpoint 5 Interrupt Register */
-#define USBD_MASK5             0xFFC044B4  /* USB Endpoint 5 Mask Register */
-#define USBD_EPCFG5            0xFFC044B6  /* USB Endpoint 5 Control Register */
-#define USBD_EPADR5            0xFFC044B8  /* USB Endpoint 5 Address Offset Register */
-#define USBD_EPLEN5            0xFFC044BA  /* USB Endpoint 5 Buffer Length Register */
-#define USBD_INTR6             0xFFC044BC  /* USB Endpoint 6 Interrupt Register */
-#define USBD_MASK6             0xFFC044BE  /* USB Endpoint 6 Mask Register */
-#define USBD_EPCFG6            0xFFC044C0  /* USB Endpoint 6 Control Register */
-#define USBD_EPADR6            0xFFC044C2  /* USB Endpoint 6 Address Offset Register */
-#define USBD_EPLEN6            0xFFC044C4  /* USB Endpoint 6 Buffer Length Register */
-#define USBD_INTR7             0xFFC044C6  /* USB Endpoint 7 Interrupt Register */
-#define USBD_MASK7             0xFFC044C8  /* USB Endpoint 7 Mask Register */
-#define USBD_EPCFG7            0xFFC044CA  /* USB Endpoint 7 Control Register */
-#define USBD_EPADR7            0xFFC044CC  /* USB Endpoint 7 Address Offset Register */
-#define USBD_EPLEN7            0xFFC044CE  /* USB Endpoint 7 Buffer Length Register */
-
-/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
-#define L1SBAR                 0xFFC04840  /* L1 SRAM Base Address Register */
-#define L1CSR                  0xFFC04844  /* L1 SRAM Control Initialization Register */
-#define DMA_DBP                0xFFC04880  /* Next Descriptor Base Pointer */
-#define DB_ACOMP               0xFFC04884  /* DMA Bus Address Comparator */
-#define DB_CCOMP               0xFFC04888  /* DMA Bus Control Comparator */
-
-#define DB_NDBP                DMA_DBP     /* Backward compatibility */
-
-#define L1_SBAR			L1SBAR
-#define L1_CSR			L1CSR
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define EBIU_SDGCTL            0xFFC04C00  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL            0xFFC04C04  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC             0xFFC04C0A  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT            0xFFC04C0E  /* SDRAM Status Register */
-
-/* PAB Reserved (0xFFC0 5000-0xFFDF FFFF) (**Reserved**) */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/*********************************************************************************** */
-
-/* PLLCTL Masks */
-#define PLL_CLKIN              0x00000000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         0x00000001  /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                0x00000002  /* Shut off PLL clocks */
-#define STOPCK_OFF             0x00000008  /* Core clock off */
-#define PDWN                   0x00000020  /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 0x00000100  /* Bypass the PLL */
-#define CCLK_DIV2              0x00000000  /* SCLK = CCLK / 2 */
-#define CCLK_DIV2_5            0x00010000  /* SCLK = CCLK / 2.5 */
-#define CCLK_DIV3              0x00020000  /* SCLK = CCLK / 3 */
-#define CCLK_DIV4              0x00030000  /* SCLK = CCLK / 4 */
-
-/* IOCKR Masks */
-#define IOCK_PCI               0x00000001  /* Enable PCI peripheral clock */
-#define IOCK_L2                0x00000002  /* Enable L2 memory peripheral clock */
-#define IOCK_EBIU              0x00000004  /* Enable EBIU controller peripheral clock */
-#define IOCK_GPIO              0x00000008  /* Enable GPIO peripheral clock */
-#define IOCK_MEMDMA            0x00000010  /* Enable MemDMA controller peripheral clock */
-#define IOCK_SPORT0            0x00000020  /* Enable SPORT0 controller peripheral clock */
-#define IOCK_SPORT1            0x00000040  /* Enable SPORT1 controller peripheral clock */
-#define IOCK_SPI0              0x00000080  /* Enable SPI0 controller peripheral clock */
-#define IOCK_SPI1              0x00000100  /* Enable SPI1 controller peripheral clock */
-#define IOCK_UART0             0x00000200  /* Enable UART0 controller peripheral clock */
-#define IOCK_UART1             0x00000400  /* Enable UART1 controller peripheral clock */
-#define IOCK_TIMER0            0x00000800  /* Enable TIMER0 peripheral clock */
-#define IOCK_TIMER1            0x00001000  /* Enable TIMER1 peripheral clock */
-#define IOCK_TIMER2            0x00002000  /* Enable TIMER2 peripheral clock */
-#define IOCK_USB               0x00004000  /* Enable USB peripheral clock */
-
-/* SWRST Mask */
-#define SYSTEM_RESET           0x00000007  /* Initiates a system software reset */
-
-/* System Interrupt Controller Masks (SIC_IAR0, SIC_IAR1, SIC_IAR2, SIC_IMASK, SIC_IWR) */
-/* SIC_IAR0 Masks */
-
-/* */
-#define P0_IVG7                0x00000000  /* Peripheral #0 assigned IVG7 */
-#define P0_IVG8                0x00000001  /* Peripheral #0 assigned IVG8 */
-#define P0_IVG9                0x00000002  /* Peripheral #0 assigned IVG9 */
-#define P0_IVG10               0x00000003  /* Peripheral #0 assigned IVG10 */
-#define P0_IVG11               0x00000004  /* Peripheral #0 assigned IVG11 */
-#define P0_IVG12               0x00000005  /* Peripheral #0 assigned IVG12 */
-#define P0_IVG13               0x00000006  /* Peripheral #0 assigned IVG13 */
-#define P0_IVG14               0x00000007  /* Peripheral #0 assigned IVG14 */
-#define P0_IVG15               0x00000008  /* Peripheral #0 assigned IVG15 */
-#define P1_IVG7                0x00000000  /* Peripheral #1 assigned IVG7 */
-#define P1_IVG8                0x00000010  /* Peripheral #1 assigned IVG8 */
-#define P1_IVG9                0x00000020  /* Peripheral #1 assigned IVG9 */
-#define P1_IVG10               0x00000030  /* Peripheral #1 assigned IVG10 */
-#define P1_IVG11               0x00000040  /* Peripheral #1 assigned IVG11 */
-#define P1_IVG12               0x00000050  /* Peripheral #1 assigned IVG12 */
-#define P1_IVG13               0x00000060  /* Peripheral #1 assigned IVG13 */
-#define P1_IVG14               0x00000070  /* Peripheral #1 assigned IVG14 */
-#define P1_IVG15               0x00000080  /* Peripheral #1 assigned IVG15 */
-#define P2_IVG7                0x00000000  /* Peripheral #2 assigned IVG7 */
-#define P2_IVG8                0x00000100  /* Peripheral #2 assigned IVG8 */
-#define P2_IVG9                0x00000200  /* Peripheral #2 assigned IVG9 */
-#define P2_IVG10               0x00000300  /* Peripheral #2 assigned IVG10 */
-#define P2_IVG11               0x00000400  /* Peripheral #2 assigned IVG11 */
-#define P2_IVG12               0x00000500  /* Peripheral #2 assigned IVG12 */
-#define P2_IVG13               0x00000600  /* Peripheral #2 assigned IVG13 */
-#define P2_IVG14               0x00000700  /* Peripheral #2 assigned IVG14 */
-#define P2_IVG15               0x00000800  /* Peripheral #2 assigned IVG15 */
-#define P3_IVG7                0x00000000  /* Peripheral #3 assigned IVG7 */
-#define P3_IVG8                0x00001000  /* Peripheral #3 assigned IVG8 */
-#define P3_IVG9                0x00002000  /* Peripheral #3 assigned IVG9 */
-#define P3_IVG10               0x00003000  /* Peripheral #3 assigned IVG10 */
-#define P3_IVG11               0x00004000  /* Peripheral #3 assigned IVG11 */
-#define P3_IVG12               0x00005000  /* Peripheral #3 assigned IVG12 */
-#define P3_IVG13               0x00006000  /* Peripheral #3 assigned IVG13 */
-#define P3_IVG14               0x00007000  /* Peripheral #3 assigned IVG14 */
-#define P3_IVG15               0x00008000  /* Peripheral #3 assigned IVG15 */
-#define P4_IVG7                0x00000000  /* Peripheral #4 assigned IVG7 */
-#define P4_IVG8                0x00010000  /* Peripheral #4 assigned IVG8 */
-#define P4_IVG9                0x00020000  /* Peripheral #4 assigned IVG9 */
-#define P4_IVG10               0x00030000  /* Peripheral #4 assigned IVG10 */
-#define P4_IVG11               0x00040000  /* Peripheral #4 assigned IVG11 */
-#define P4_IVG12               0x00050000  /* Peripheral #4 assigned IVG12 */
-#define P4_IVG13               0x00060000  /* Peripheral #4 assigned IVG13 */
-#define P4_IVG14               0x00070000  /* Peripheral #4 assigned IVG14 */
-#define P4_IVG15               0x00080000  /* Peripheral #4 assigned IVG15 */
-#define P5_IVG7                0x00000000  /* Peripheral #5 assigned IVG7 */
-#define P5_IVG8                0x00100000  /* Peripheral #5 assigned IVG8 */
-#define P5_IVG9                0x00200000  /* Peripheral #5 assigned IVG9 */
-#define P5_IVG10               0x00300000  /* Peripheral #5 assigned IVG10 */
-#define P5_IVG11               0x00400000  /* Peripheral #5 assigned IVG11 */
-#define P5_IVG12               0x00500000  /* Peripheral #5 assigned IVG12 */
-#define P5_IVG13               0x00600000  /* Peripheral #5 assigned IVG13 */
-#define P5_IVG14               0x00700000  /* Peripheral #5 assigned IVG14 */
-#define P5_IVG15               0x00800000  /* Peripheral #5 assigned IVG15 */
-#define P6_IVG7                0x00000000  /* Peripheral #6 assigned IVG7 */
-#define P6_IVG8                0x01000000  /* Peripheral #6 assigned IVG8 */
-#define P6_IVG9                0x02000000  /* Peripheral #6 assigned IVG9 */
-#define P6_IVG10               0x03000000  /* Peripheral #6 assigned IVG10 */
-#define P6_IVG11               0x04000000  /* Peripheral #6 assigned IVG11 */
-#define P6_IVG12               0x05000000  /* Peripheral #6 assigned IVG12 */
-#define P6_IVG13               0x06000000  /* Peripheral #6 assigned IVG13 */
-#define P6_IVG14               0x07000000  /* Peripheral #6 assigned IVG14 */
-#define P6_IVG15               0x08000000  /* Peripheral #6 assigned IVG15 */
-#define P7_IVG7                0x00000000  /* Peripheral #7 assigned IVG7 */
-#define P7_IVG8                0x10000000  /* Peripheral #7 assigned IVG8 */
-#define P7_IVG9                0x20000000  /* Peripheral #7 assigned IVG9 */
-#define P7_IVG10               0x30000000  /* Peripheral #7 assigned IVG10 */
-#define P7_IVG11               0x40000000  /* Peripheral #7 assigned IVG11 */
-#define P7_IVG12               0x50000000  /* Peripheral #7 assigned IVG12 */
-#define P7_IVG13               0x60000000  /* Peripheral #7 assigned IVG13 */
-#define P7_IVG14               0x70000000  /* Peripheral #7 assigned IVG14 */
-#define P7_IVG15               0x80000000  /* Peripheral #7 assigned IVG15 */
-
-/* SIC_IAR1 Masks */
-#define P8_IVG7                0x00000000  /* Peripheral #8 assigned IVG7 */
-#define P8_IVG8                0x00000001  /* Peripheral #8 assigned IVG8 */
-#define P8_IVG9                0x00000002  /* Peripheral #8 assigned IVG9 */
-#define P8_IVG10               0x00000003  /* Peripheral #8 assigned IVG10 */
-#define P8_IVG11               0x00000004  /* Peripheral #8 assigned IVG11 */
-#define P8_IVG12               0x00000005  /* Peripheral #8 assigned IVG12 */
-#define P8_IVG13               0x00000006  /* Peripheral #8 assigned IVG13 */
-#define P8_IVG14               0x00000007  /* Peripheral #8 assigned IVG14 */
-#define P8_IVG15               0x00000008  /* Peripheral #8 assigned IVG15 */
-#define P9_IVG7                0x00000000  /* Peripheral #9 assigned IVG7 */
-#define P9_IVG8                0x00000010  /* Peripheral #9 assigned IVG8 */
-#define P9_IVG9                0x00000020  /* Peripheral #9 assigned IVG9 */
-#define P9_IVG10               0x00000030  /* Peripheral #9 assigned IVG10 */
-#define P9_IVG11               0x00000040  /* Peripheral #9 assigned IVG11 */
-#define P9_IVG12               0x00000050  /* Peripheral #9 assigned IVG12 */
-#define P9_IVG13               0x00000060  /* Peripheral #9 assigned IVG13 */
-#define P9_IVG14               0x00000070  /* Peripheral #9 assigned IVG14 */
-#define P9_IVG15               0x00000080  /* Peripheral #9 assigned IVG15 */
-#define P10_IVG7               0x00000000  /* Peripheral #10 assigned IVG7 */
-#define P10_IVG8               0x00000100  /* Peripheral #10 assigned IVG8 */
-#define P10_IVG9               0x00000200  /* Peripheral #10 assigned IVG9 */
-#define P10_IVG10              0x00000300  /* Peripheral #10 assigned IVG10 */
-#define P10_IVG11              0x00000400  /* Peripheral #10 assigned IVG11 */
-#define P10_IVG12              0x00000500  /* Peripheral #10 assigned IVG12 */
-#define P10_IVG13              0x00000600  /* Peripheral #10 assigned IVG13 */
-#define P10_IVG14              0x00000700  /* Peripheral #10 assigned IVG14 */
-#define P10_IVG15              0x00000800  /* Peripheral #10 assigned IVG15 */
-#define P11_IVG7               0x00000000  /* Peripheral #11 assigned IVG7 */
-#define P11_IVG8               0x00001000  /* Peripheral #11 assigned IVG8 */
-#define P11_IVG9               0x00002000  /* Peripheral #11 assigned IVG9 */
-#define P11_IVG10              0x00003000  /* Peripheral #11 assigned IVG10 */
-#define P11_IVG11              0x00004000  /* Peripheral #11 assigned IVG11 */
-#define P11_IVG12              0x00005000  /* Peripheral #11 assigned IVG12 */
-#define P11_IVG13              0x00006000  /* Peripheral #11 assigned IVG13 */
-#define P11_IVG14              0x00007000  /* Peripheral #11 assigned IVG14 */
-#define P11_IVG15              0x00008000  /* Peripheral #11 assigned IVG15 */
-#define P12_IVG7               0x00000000  /* Peripheral #12 assigned IVG7 */
-#define P12_IVG8               0x00010000  /* Peripheral #12 assigned IVG8 */
-#define P12_IVG9               0x00020000  /* Peripheral #12 assigned IVG9 */
-#define P12_IVG10              0x00030000  /* Peripheral #12 assigned IVG10 */
-#define P12_IVG11              0x00040000  /* Peripheral #12 assigned IVG11 */
-#define P12_IVG12              0x00050000  /* Peripheral #12 assigned IVG12 */
-#define P12_IVG13              0x00060000  /* Peripheral #12 assigned IVG13 */
-#define P12_IVG14              0x00070000  /* Peripheral #12 assigned IVG14 */
-#define P12_IVG15              0x00080000  /* Peripheral #12 assigned IVG15 */
-#define P13_IVG7               0x00000000  /* Peripheral #13 assigned IVG7 */
-#define P13_IVG8               0x00100000  /* Peripheral #13 assigned IVG8 */
-#define P13_IVG9               0x00200000  /* Peripheral #13 assigned IVG9 */
-#define P13_IVG10              0x00300000  /* Peripheral #13 assigned IVG10 */
-#define P13_IVG11              0x00400000  /* Peripheral #13 assigned IVG11 */
-#define P13_IVG12              0x00500000  /* Peripheral #13 assigned IVG12 */
-#define P13_IVG13              0x00600000  /* Peripheral #13 assigned IVG13 */
-#define P13_IVG14              0x00700000  /* Peripheral #14 assigned IVG14 */
-#define P13_IVG15              0x00800000  /* Peripheral #14 assigned IVG15 */
-#define P14_IVG7               0x00000000  /* Peripheral #14 assigned IVG7 */
-#define P14_IVG8               0x01000000  /* Peripheral #14 assigned IVG8 */
-#define P14_IVG9               0x02000000  /* Peripheral #14 assigned IVG9 */
-#define P14_IVG10              0x03000000  /* Peripheral #14 assigned IVG10 */
-#define P14_IVG11              0x04000000  /* Peripheral #14 assigned IVG11 */
-#define P14_IVG12              0x05000000  /* Peripheral #14 assigned IVG12 */
-#define P14_IVG13              0x06000000  /* Peripheral #14 assigned IVG13 */
-#define P14_IVG14              0x07000000  /* Peripheral #14 assigned IVG14 */
-#define P14_IVG15              0x08000000  /* Peripheral #14 assigned IVG15 */
-#define P15_IVG7               0x00000000  /* Peripheral #15 assigned IVG7 */
-#define P15_IVG8               0x10000000  /* Peripheral #15 assigned IVG8 */
-#define P15_IVG9               0x20000000  /* Peripheral #15 assigned IVG9 */
-#define P15_IVG10              0x30000000  /* Peripheral #15 assigned IVG10 */
-#define P15_IVG11              0x40000000  /* Peripheral #15 assigned IVG11 */
-#define P15_IVG12              0x50000000  /* Peripheral #15 assigned IVG12 */
-#define P15_IVG13              0x60000000  /* Peripheral #15 assigned IVG13 */
-#define P15_IVG14              0x70000000  /* Peripheral #15 assigned IVG14 */
-#define P15_IVG15              0x80000000  /* Peripheral #15 assigned IVG15 */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG7               0x00000000  /* Peripheral #16 assigned IVG7 */
-#define P16_IVG8               0x00000001  /* Peripheral #16 assigned IVG8 */
-#define P16_IVG9               0x00000002  /* Peripheral #16 assigned IVG9 */
-#define P16_IVG10              0x00000003  /* Peripheral #16 assigned IVG10 */
-#define P16_IVG11              0x00000004  /* Peripheral #16 assigned IVG11 */
-#define P16_IVG12              0x00000005  /* Peripheral #16 assigned IVG12 */
-#define P16_IVG13              0x00000006  /* Peripheral #16 assigned IVG13 */
-#define P16_IVG14              0x00000007  /* Peripheral #16 assigned IVG14 */
-#define P16_IVG15              0x00000008  /* Peripheral #16 assigned IVG15 */
-#define P17_IVG7               0x00000000  /* Peripheral #17 assigned IVG7 */
-#define P17_IVG8               0x00000010  /* Peripheral #17 assigned IVG8 */
-#define P17_IVG9               0x00000020  /* Peripheral #17 assigned IVG9 */
-#define P17_IVG10              0x00000030  /* Peripheral #17 assigned IVG10 */
-#define P17_IVG11              0x00000040  /* Peripheral #17 assigned IVG11 */
-#define P17_IVG12              0x00000050  /* Peripheral #17 assigned IVG12 */
-#define P17_IVG13              0x00000060  /* Peripheral #17 assigned IVG13 */
-#define P17_IVG14              0x00000070  /* Peripheral #17 assigned IVG14 */
-#define P17_IVG15              0x00000080  /* Peripheral #17 assigned IVG15 */
-#define P18_IVG7               0x00000000  /* Peripheral #18 assigned IVG7 */
-#define P18_IVG8               0x00000100  /* Peripheral #18 assigned IVG8 */
-#define P18_IVG9               0x00000200  /* Peripheral #18 assigned IVG9 */
-#define P18_IVG10              0x00000300  /* Peripheral #18 assigned IVG10 */
-#define P18_IVG11              0x00000400  /* Peripheral #18 assigned IVG11 */
-#define P18_IVG12              0x00000500  /* Peripheral #18 assigned IVG12 */
-#define P18_IVG13              0x00000600  /* Peripheral #18 assigned IVG13 */
-#define P18_IVG14              0x00000700  /* Peripheral #18 assigned IVG14 */
-#define P18_IVG15              0x00000800  /* Peripheral #18 assigned IVG15 */
-#define P19_IVG7               0x00000000  /* Peripheral #19 assigned IVG7 */
-#define P19_IVG8               0x00001000  /* Peripheral #19 assigned IVG8 */
-#define P19_IVG9               0x00002000  /* Peripheral #19 assigned IVG9 */
-#define P19_IVG10              0x00003000  /* Peripheral #19 assigned IVG10 */
-#define P19_IVG11              0x00004000  /* Peripheral #19 assigned IVG11 */
-#define P19_IVG12              0x00005000  /* Peripheral #19 assigned IVG12 */
-#define P19_IVG13              0x00006000  /* Peripheral #19 assigned IVG13 */
-#define P19_IVG14              0x00007000  /* Peripheral #19 assigned IVG14 */
-#define P19_IVG15              0x00008000  /* Peripheral #19 assigned IVG15 */
-#define P20_IVG7               0x00000000  /* Peripheral #20 assigned IVG7 */
-#define P20_IVG8               0x00010000  /* Peripheral #20 assigned IVG8 */
-#define P20_IVG9               0x00020000  /* Peripheral #20 assigned IVG9 */
-#define P20_IVG10              0x00030000  /* Peripheral #20 assigned IVG10 */
-#define P20_IVG11              0x00040000  /* Peripheral #20 assigned IVG11 */
-#define P20_IVG12              0x00050000  /* Peripheral #20 assigned IVG12 */
-#define P20_IVG13              0x00060000  /* Peripheral #20 assigned IVG13 */
-#define P20_IVG14              0x00070000  /* Peripheral #20 assigned IVG14 */
-#define P20_IVG15              0x00080000  /* Peripheral #20 assigned IVG15 */
-/* */
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL         0x00000000  /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF  /* Mask all peripheral interrupts */
-#define SIC_MASK0              0x00000001  /* Mask Peripheral #0 interrupt  */
-#define SIC_MASK1              0x00000002  /* Mask Peripheral #1 interrupt  */
-#define SIC_MASK2              0x00000004  /* Mask Peripheral #2 interrupt  */
-#define SIC_MASK3              0x00000008  /* Mask Peripheral #3 interrupt  */
-#define SIC_MASK4              0x00000010  /* Mask Peripheral #4 interrupt  */
-#define SIC_MASK5              0x00000020  /* Mask Peripheral #5 interrupt  */
-#define SIC_MASK6              0x00000040  /* Mask Peripheral #6 interrupt  */
-#define SIC_MASK7              0x00000080  /* Mask Peripheral #7 interrupt  */
-#define SIC_MASK8              0x00000100  /* Mask Peripheral #8 interrupt  */
-#define SIC_MASK9              0x00000200  /* Mask Peripheral #9 interrupt  */
-#define SIC_MASK10             0x00000400  /* Mask Peripheral #10 interrupt  */
-#define SIC_MASK11             0x00000800  /* Mask Peripheral #11 interrupt  */
-#define SIC_MASK12             0x00001000  /* Mask Peripheral #12 interrupt  */
-#define SIC_MASK13             0x00002000  /* Mask Peripheral #13 interrupt  */
-#define SIC_MASK14             0x00004000  /* Mask Peripheral #14 interrupt  */
-#define SIC_MASK15             0x00008000  /* Mask Peripheral #15 interrupt  */
-#define SIC_MASK16             0x00010000  /* Mask Peripheral #16 interrupt  */
-#define SIC_MASK17             0x00020000  /* Mask Peripheral #17 interrupt  */
-#define SIC_MASK18             0x00040000  /* Mask Peripheral #18 interrupt */
-#define SIC_MASK19             0x00080000  /* Mask Peripheral #19 interrupt */
-#define SIC_MASK20             0x00100000  /* Mask Peripheral #20 interrupt */
-#define SIC_MASK_DFR           0x80000000  /* Mask Core Double Fault Reset */
-#define SIC_UNMASK0            0xFFFFFFFE  /* Unmask Peripheral #0 interrupt  */
-#define SIC_UNMASK1            0xFFFFFFFD  /* Unmask Peripheral #1 interrupt  */
-#define SIC_UNMASK2            0xFFFFFFFB  /* Unmask Peripheral #2 interrupt  */
-#define SIC_UNMASK3            0xFFFFFFF7  /* Unmask Peripheral #3 interrupt  */
-#define SIC_UNMASK4            0xFFFFFFEF  /* Unmask Peripheral #4 interrupt  */
-#define SIC_UNMASK5            0xFFFFFFDF  /* Unmask Peripheral #5 interrupt  */
-#define SIC_UNMASK6            0xFFFFFFBF  /* Unmask Peripheral #6 interrupt  */
-#define SIC_UNMASK7            0xFFFFFF7F  /* Unmask Peripheral #7 interrupt  */
-#define SIC_UNMASK8            0xFFFFFEFF  /* Unmask Peripheral #8 interrupt  */
-#define SIC_UNMASK9            0xFFFFFDFF  /* Unmask Peripheral #9 interrupt  */
-#define SIC_UNMASK10           0xFFFFFBFF  /* Unmask Peripheral #10 interrupt  */
-#define SIC_UNMASK11           0xFFFFF7FF  /* Unmask Peripheral #11 interrupt  */
-#define SIC_UNMASK12           0xFFFFEFFF  /* Unmask Peripheral #12 interrupt  */
-#define SIC_UNMASK13           0xFFFFDFFF  /* Unmask Peripheral #13 interrupt  */
-#define SIC_UNMASK14           0xFFFFBFFF  /* Unmask Peripheral #14 interrupt  */
-#define SIC_UNMASK15           0xFFFF7FFF  /* Unmask Peripheral #15 interrupt  */
-#define SIC_UNMASK16           0xFFFEFFFF  /* Unmask Peripheral #16 interrupt  */
-#define SIC_UNMASK17           0xFFFDFFFF  /* Unmask Peripheral #17 interrupt  */
-#define SIC_UNMASK18           0xFFFBFFFF  /* Unmask Peripheral #18 interrupt */
-#define SIC_UNMASK19           0xFFF7FFFF  /* Unmask Peripheral #19 interrupt */
-#define SIC_UNMASK20           0xFFEFFFFF  /* Unmask Peripheral #20 interrupt */
-#define SIC_UNMASK_DFR         0x7FFFFFFF  /* Unmask Core Double Fault Reset */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000  /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF  /* Wakeup Enable all peripherals */
-#define IWR_ENABLE0            0x00000001  /* Wakeup Enable Peripheral #0 */
-#define IWR_ENABLE1            0x00000002  /* Wakeup Enable Peripheral #1 */
-#define IWR_ENABLE2            0x00000004  /* Wakeup Enable Peripheral #2 */
-#define IWR_ENABLE3            0x00000008  /* Wakeup Enable Peripheral #3 */
-#define IWR_ENABLE4            0x00000010  /* Wakeup Enable Peripheral #4 */
-#define IWR_ENABLE5            0x00000020  /* Wakeup Enable Peripheral #5 */
-#define IWR_ENABLE6            0x00000040  /* Wakeup Enable Peripheral #6 */
-#define IWR_ENABLE7            0x00000080  /* Wakeup Enable Peripheral #7 */
-#define IWR_ENABLE8            0x00000100  /* Wakeup Enable Peripheral #8 */
-#define IWR_ENABLE9            0x00000200  /* Wakeup Enable Peripheral #9 */
-#define IWR_ENABLE10           0x00000400  /* Wakeup Enable Peripheral #10 */
-#define IWR_ENABLE11           0x00000800  /* Wakeup Enable Peripheral #11 */
-#define IWR_ENABLE12           0x00001000  /* Wakeup Enable Peripheral #12 */
-#define IWR_ENABLE13           0x00002000  /* Wakeup Enable Peripheral #13 */
-#define IWR_ENABLE14           0x00004000  /* Wakeup Enable Peripheral #14 */
-#define IWR_ENABLE15           0x00008000  /* Wakeup Enable Peripheral #15 */
-#define IWR_ENABLE16           0x00010000  /* Wakeup Enable Peripheral #16 */
-#define IWR_ENABLE17           0x00020000  /* Wakeup Enable Peripheral #17 */
-#define IWR_ENABLE18           0x00040000  /* Wakeup Enable Peripheral #18 */
-#define IWR_ENABLE19           0x00080000  /* Wakeup Enable Peripheral #19 */
-#define IWR_ENABLE20           0x00100000  /* Wakeup Enable Peripheral #20 */
-#define IWR_DISABLE0           0xFFFFFFFE  /* Wakeup Disable Peripheral #0 */
-#define IWR_DISABLE1           0xFFFFFFFD  /* Wakeup Disable Peripheral #1 */
-#define IWR_DISABLE2           0xFFFFFFFB  /* Wakeup Disable Peripheral #2 */
-#define IWR_DISABLE3           0xFFFFFFF7  /* Wakeup Disable Peripheral #3 */
-#define IWR_DISABLE4           0xFFFFFFEF  /* Wakeup Disable Peripheral #4 */
-#define IWR_DISABLE5           0xFFFFFFDF  /* Wakeup Disable Peripheral #5 */
-#define IWR_DISABLE6           0xFFFFFFBF  /* Wakeup Disable Peripheral #6 */
-#define IWR_DISABLE7           0xFFFFFF7F  /* Wakeup Disable Peripheral #7 */
-#define IWR_DISABLE8           0xFFFFFEFF  /* Wakeup Disable Peripheral #8 */
-#define IWR_DISABLE9           0xFFFFFDFF  /* Wakeup Disable Peripheral #9 */
-#define IWR_DISABLE10          0xFFFFFBFF  /* Wakeup Disable Peripheral #10 */
-#define IWR_DISABLE11          0xFFFFF7FF  /* Wakeup Disable Peripheral #11 */
-#define IWR_DISABLE12          0xFFFFEFFF  /* Wakeup Disable Peripheral #12 */
-#define IWR_DISABLE13          0xFFFFDFFF  /* Wakeup Disable Peripheral #13 */
-#define IWR_DISABLE14          0xFFFFBFFF  /* Wakeup Disable Peripheral #14 */
-#define IWR_DISABLE15          0xFFFF7FFF  /* Wakeup Disable Peripheral #15 */
-#define IWR_DISABLE16          0xFFFEFFFF  /* Wakeup Disable Peripheral #16 */
-#define IWR_DISABLE17          0xFFFDFFFF  /* Wakeup Disable Peripheral #17 */
-#define IWR_DISABLE18          0xFFFBFFFF  /* Wakeup Disable Peripheral #18 */
-#define IWR_DISABLE19          0xFFF7FFFF  /* Wakeup Disable Peripheral #19 */
-#define IWR_DISABLE20          0xFFEFFFFF  /* Wakeup Disable Peripheral #20 */
-
-/* WDOGCTL Masks */
-#define ENABLE_RESET           0x00000000  /* Set Watchdog Timer to generate reset */
-#define ENABLE_NMI             0x00000002  /* Set Watchdog Timer to generate non-maskable interrupt */
-#define ENABLE_GPI             0x00000004  /* Set Watchdog Timer to generate general-purpose interrupt */
-#define DISABLE_EVT            0x00000006  /* Disable Watchdog Timer interrupts */
-
-/* RTCFAST Mask */
-#define ENABLE_PRESCALE        0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
-          /* Must be set after power-up for proper operation of RTC */
-
-/* SPICTLx Masks */
-#define TIMOD                  0x00000003  /* Transfer initiation mode and interrupt generation */
-#define SZ                     0x00000004  /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008  /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010  /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020  /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100  /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200  /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400  /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800  /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000  /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000  /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000  /* SPI module enable (=1), disable (=0) */
-
-/* SPIFLGx Masks */
-#define FLS1                   0x00000002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPIFLGx Bit Positions */
-#define FLS1_P                 0x00000001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* AMGCTL Masks */
-#define AMCKEN                 0x00000001  /* Enable CLKOUT */
-#define AMBEN_B4               0x00000002  /* Enable Asynchronous Memory Bank 6 only */
-#define AMBEN_B4_B5            0x00000004  /* Enable Asynchronous Memory Banks 4 & 5 only */
-#define AMBEN_ALL              0x00000006  /* Enable Asynchronous Memory Banks (all) 4, 5, 6, and 7 */
-#define B4PEN                  0x00000010  /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
-#define B5PEN                  0x00000020  /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
-#define B6PEN                  0x00000040  /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
-#define B7PEN                  0x00000080  /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P               0x00000000  /* Enable CLKOUT */
-#define AMBEN_P0               0x00000001  /* Asynchronous Memory Enable, 00 - banks 4-7 disabled, 01 - bank 4 enabled */
-#define AMBEN_P1               0x00000002  /* Asynchronous Memory Enable, 10 - banks 4&5 enabled,  11 - banks 4-7 enabled */
-#define B4PEN_P                0x00000004  /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
-#define B5PEN_P                0x00000005  /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
-#define B6PEN_P                0x00000006  /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
-#define B7PEN_P                0x00000007  /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
-
-/* AMBCTL0 Masks */
-#define B4RDYEN                0x00000001  /* Bank 4 RDY Enable, 0=disable, 1=enable */
-#define B4RDYPOL               0x00000002  /* Bank 4 RDY Active high, 0=active low, 1=active high */
-#define B4TT_1                 0x00000004  /* Bank 4 Transition Time from Read to Write = 1 cycle */
-#define B4TT_2                 0x00000008  /* Bank 4 Transition Time from Read to Write = 2 cycles */
-#define B4TT_3                 0x0000000C  /* Bank 4 Transition Time from Read to Write = 3 cycles */
-#define B4TT_4                 0x00000000  /* Bank 4 Transition Time from Read to Write = 4 cycles */
-#define B4ST_1                 0x00000010  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B4ST_2                 0x00000020  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B4ST_3                 0x00000030  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B4ST_4                 0x00000000  /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B4HT_1                 0x00000040  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B4HT_2                 0x00000080  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B4HT_3                 0x000000C0  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B4HT_4                 0x00000000  /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
-#define B4RAT_1                0x00000100  /* Bank 4 Read Access Time = 1 cycle */
-#define B4RAT_2                0x00000200  /* Bank 4 Read Access Time = 2 cycles */
-#define B4RAT_3                0x00000300  /* Bank 4 Read Access Time = 3 cycles */
-#define B4RAT_4                0x00000400  /* Bank 4 Read Access Time = 4 cycles */
-#define B4RAT_5                0x00000500  /* Bank 4 Read Access Time = 5 cycles */
-#define B4RAT_6                0x00000600  /* Bank 4 Read Access Time = 6 cycles */
-#define B4RAT_7                0x00000700  /* Bank 4 Read Access Time = 7 cycles */
-#define B4RAT_8                0x00000800  /* Bank 4 Read Access Time = 8 cycles */
-#define B4RAT_9                0x00000900  /* Bank 4 Read Access Time = 9 cycles */
-#define B4RAT_10               0x00000A00  /* Bank 4 Read Access Time = 10 cycles */
-#define B4RAT_11               0x00000B00  /* Bank 4 Read Access Time = 11 cycles */
-#define B4RAT_12               0x00000C00  /* Bank 4 Read Access Time = 12 cycles */
-#define B4RAT_13               0x00000D00  /* Bank 4 Read Access Time = 13 cycles */
-#define B4RAT_14               0x00000E00  /* Bank 4 Read Access Time = 14 cycles */
-#define B4RAT_15               0x00000F00  /* Bank 4 Read Access Time = 15 cycles */
-#define B4WAT_1                0x00001000  /* Bank 4 Write Access Time = 1 cycle */
-#define B4WAT_2                0x00002000  /* Bank 4 Write Access Time = 2 cycles */
-#define B4WAT_3                0x00003000  /* Bank 4 Write Access Time = 3 cycles */
-#define B4WAT_4                0x00004000  /* Bank 4 Write Access Time = 4 cycles */
-#define B4WAT_5                0x00005000  /* Bank 4 Write Access Time = 5 cycles */
-#define B4WAT_6                0x00006000  /* Bank 4 Write Access Time = 6 cycles */
-#define B4WAT_7                0x00007000  /* Bank 4 Write Access Time = 7 cycles */
-#define B4WAT_8                0x00008000  /* Bank 4 Write Access Time = 8 cycles */
-#define B4WAT_9                0x00009000  /* Bank 4 Write Access Time = 9 cycles */
-#define B4WAT_10               0x0000A000  /* Bank 4 Write Access Time = 10 cycles */
-#define B4WAT_11               0x0000B000  /* Bank 4 Write Access Time = 11 cycles */
-#define B4WAT_12               0x0000C000  /* Bank 4 Write Access Time = 12 cycles */
-#define B4WAT_13               0x0000D000  /* Bank 4 Write Access Time = 13 cycles */
-#define B4WAT_14               0x0000E000  /* Bank 4 Write Access Time = 14 cycles */
-#define B4WAT_15               0x0000F000  /* Bank 4 Write Access Time = 15 cycles */
-#define B5RDYEN                0x00000001  /* Bank 5 RDY enable, 0=disable, 1=enable */
-#define B5RDYPOL               0x00000002  /* Bank 5 RDY Active high, 0=active low, 1=active high */
-#define B5TT_1                 0x00000004  /* Bank 5 Transition Time from Read to Write = 1 cycle */
-#define B5TT_2                 0x00000008  /* Bank 5 Transition Time from Read to Write = 2 cycles */
-#define B5TT_3                 0x0000000C  /* Bank 5 Transition Time from Read to Write = 3 cycles */
-#define B5TT_4                 0x00000000  /* Bank 5 Transition Time from Read to Write = 4 cycles */
-#define B5ST_1                 0x00000010  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B5ST_2                 0x00000020  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B5ST_3                 0x00000030  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B5ST_4                 0x00000000  /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B5HT_1                 0x00000040  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B5HT_2                 0x00000080  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B5HT_3                 0x000000C0  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B5HT_4                 0x00000000  /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
-#define B5RAT_1                0x00000100  /* Bank 5 Read Access Time = 1 cycle */
-#define B5RAT_2                0x00000200  /* Bank 5 Read Access Time = 2 cycles */
-#define B5RAT_3                0x00000300  /* Bank 5 Read Access Time = 3 cycles */
-#define B5RAT_4                0x00000400  /* Bank 5 Read Access Time = 4 cycles */
-#define B5RAT_5                0x00000500  /* Bank 5 Read Access Time = 5 cycles */
-#define B5RAT_6                0x00000600  /* Bank 5 Read Access Time = 6 cycles */
-#define B5RAT_7                0x00000700  /* Bank 5 Read Access Time = 7 cycles */
-#define B5RAT_8                0x00000800  /* Bank 5 Read Access Time = 8 cycles */
-#define B5RAT_9                0x00000900  /* Bank 5 Read Access Time = 9 cycles */
-#define B5RAT_10               0x00000A00  /* Bank 5 Read Access Time = 10 cycles */
-#define B5RAT_11               0x00000B00  /* Bank 5 Read Access Time = 11 cycles */
-#define B5RAT_12               0x00000C00  /* Bank 5 Read Access Time = 12 cycles */
-#define B5RAT_13               0x00000D00  /* Bank 5 Read Access Time = 13 cycles */
-#define B5RAT_14               0x00000E00  /* Bank 5 Read Access Time = 14 cycles */
-#define B5RAT_15               0x00000F00  /* Bank 5 Read Access Time = 15 cycles */
-#define B5WAT_1                0x00001000  /* Bank 5 Write Access Time = 1 cycle */
-#define B5WAT_2                0x00002000  /* Bank 5 Write Access Time = 2 cycles */
-#define B5WAT_3                0x00003000  /* Bank 5 Write Access Time = 3 cycles */
-#define B5WAT_4                0x00004000  /* Bank 5 Write Access Time = 4 cycles */
-#define B5WAT_5                0x00005000  /* Bank 5 Write Access Time = 5 cycles */
-#define B5WAT_6                0x00006000  /* Bank 5 Write Access Time = 6 cycles */
-#define B5WAT_7                0x00007000  /* Bank 5 Write Access Time = 7 cycles */
-#define B5WAT_8                0x00008000  /* Bank 5 Write Access Time = 8 cycles */
-#define B5WAT_9                0x00009000  /* Bank 5 Write Access Time = 9 cycles */
-#define B5WAT_10               0x0000A000  /* Bank 5 Write Access Time = 10 cycles */
-#define B5WAT_11               0x0000B000  /* Bank 5 Write Access Time = 11 cycles */
-#define B5WAT_12               0x0000C000  /* Bank 5 Write Access Time = 12 cycles */
-#define B5WAT_13               0x0000D000  /* Bank 5 Write Access Time = 13 cycles */
-#define B5WAT_14               0x0000E000  /* Bank 5 Write Access Time = 14 cycles */
-#define B5WAT_15               0x0000F000  /* Bank 5 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B6RDYEN                0x00000001  /* Bank 6 RDY Enable, 0=disable, 1=enable */
-#define B6RDYPOL               0x00000002  /* Bank 6 RDY Active high, 0=active low, 1=active high */
-#define B6TT_1                 0x00000004  /* Bank 6 Transition Time from Read to Write = 1 cycle */
-#define B6TT_2                 0x00000008  /* Bank 6 Transition Time from Read to Write = 2 cycles */
-#define B6TT_3                 0x0000000C  /* Bank 6 Transition Time from Read to Write = 3 cycles */
-#define B6TT_4                 0x00000000  /* Bank 6 Transition Time from Read to Write = 4 cycles */
-#define B6ST_1                 0x00000010  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B6ST_2                 0x00000020  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B6ST_3                 0x00000030  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B6ST_4                 0x00000000  /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B6HT_1                 0x00000040  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B6HT_2                 0x00000080  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B6HT_3                 0x000000C0  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B6HT_4                 0x00000000  /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
-#define B6RAT_1                0x00000100  /* Bank 6 Read Access Time = 1 cycle */
-#define B6RAT_2                0x00000200  /* Bank 6 Read Access Time = 2 cycles */
-#define B6RAT_3                0x00000300  /* Bank 6 Read Access Time = 3 cycles */
-#define B6RAT_4                0x00000400  /* Bank 6 Read Access Time = 4 cycles */
-#define B6RAT_5                0x00000500  /* Bank 6 Read Access Time = 5 cycles */
-#define B6RAT_6                0x00000600  /* Bank 6 Read Access Time = 6 cycles */
-#define B6RAT_7                0x00000700  /* Bank 6 Read Access Time = 7 cycles */
-#define B6RAT_8                0x00000800  /* Bank 6 Read Access Time = 8 cycles */
-#define B6RAT_9                0x00000900  /* Bank 6 Read Access Time = 9 cycles */
-#define B6RAT_10               0x00000A00  /* Bank 6 Read Access Time = 10 cycles */
-#define B6RAT_11               0x00000B00  /* Bank 6 Read Access Time = 11 cycles */
-#define B6RAT_12               0x00000C00  /* Bank 6 Read Access Time = 12 cycles */
-#define B6RAT_13               0x00000D00  /* Bank 6 Read Access Time = 13 cycles */
-#define B6RAT_14               0x00000E00  /* Bank 6 Read Access Time = 14 cycles */
-#define B6RAT_15               0x00000F00  /* Bank 6 Read Access Time = 15 cycles */
-#define B6WAT_1                0x00001000  /* Bank 6 Write Access Time = 1 cycle */
-#define B6WAT_2                0x00002000  /* Bank 6 Write Access Time = 2 cycles */
-#define B6WAT_3                0x00003000  /* Bank 6 Write Access Time = 3 cycles */
-#define B6WAT_4                0x00004000  /* Bank 6 Write Access Time = 4 cycles */
-#define B6WAT_5                0x00005000  /* Bank 6 Write Access Time = 5 cycles */
-#define B6WAT_6                0x00006000  /* Bank 6 Write Access Time = 6 cycles */
-#define B6WAT_7                0x00007000  /* Bank 6 Write Access Time = 7 cycles */
-#define B6WAT_8                0x00008000  /* Bank 6 Write Access Time = 8 cycles */
-#define B6WAT_9                0x00009000  /* Bank 6 Write Access Time = 9 cycles */
-#define B6WAT_10               0x0000A000  /* Bank 6 Write Access Time = 10 cycles */
-#define B6WAT_11               0x0000B000  /* Bank 6 Write Access Time = 11 cycles */
-#define B6WAT_12               0x0000C000  /* Bank 6 Write Access Time = 12 cycles */
-#define B6WAT_13               0x0000D000  /* Bank 6 Write Access Time = 13 cycles */
-#define B6WAT_14               0x0000E000  /* Bank 6 Write Access Time = 14 cycles */
-#define B6WAT_15               0x0000F000  /* Bank 6 Write Access Time = 15 cycles */
-#define B7RDYEN                0x00000001  /* Bank 7 RDY enable, 0=disable, 1=enable */
-#define B7RDYPOL               0x00000002  /* Bank 7 RDY Active high, 0=active low, 1=active high */
-#define B7TT_1                 0x00000004  /* Bank 7 Transition Time from Read to Write = 1 cycle */
-#define B7TT_2                 0x00000008  /* Bank 7 Transition Time from Read to Write = 2 cycles */
-#define B7TT_3                 0x0000000C  /* Bank 7 Transition Time from Read to Write = 3 cycles */
-#define B7TT_4                 0x00000000  /* Bank 7 Transition Time from Read to Write = 4 cycles */
-#define B7ST_1                 0x00000010  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B7ST_2                 0x00000020  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B7ST_3                 0x00000030  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B7ST_4                 0x00000000  /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B7HT_1                 0x00000040  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B7HT_2                 0x00000080  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B7HT_3                 0x000000C0  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B7HT_4                 0x00000000  /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
-#define B7RAT_1                0x00000100  /* Bank 7 Read Access Time = 1 cycle */
-#define B7RAT_2                0x00000200  /* Bank 7 Read Access Time = 2 cycles */
-#define B7RAT_3                0x00000300  /* Bank 7 Read Access Time = 3 cycles */
-#define B7RAT_4                0x00000400  /* Bank 7 Read Access Time = 4 cycles */
-#define B7RAT_5                0x00000500  /* Bank 7 Read Access Time = 5 cycles */
-#define B7RAT_6                0x00000600  /* Bank 7 Read Access Time = 6 cycles */
-#define B7RAT_7                0x00000700  /* Bank 7 Read Access Time = 7 cycles */
-#define B7RAT_8                0x00000800  /* Bank 7 Read Access Time = 8 cycles */
-#define B7RAT_9                0x00000900  /* Bank 7 Read Access Time = 9 cycles */
-#define B7RAT_10               0x00000A00  /* Bank 7 Read Access Time = 10 cycles */
-#define B7RAT_11               0x00000B00  /* Bank 7 Read Access Time = 11 cycles */
-#define B7RAT_12               0x00000C00  /* Bank 7 Read Access Time = 12 cycles */
-#define B7RAT_13               0x00000D00  /* Bank 7 Read Access Time = 13 cycles */
-#define B7RAT_14               0x00000E00  /* Bank 7 Read Access Time = 14 cycles */
-#define B7RAT_15               0x00000F00  /* Bank 7 Read Access Time = 15 cycles */
-#define B7WAT_1                0x00001000  /* Bank 7 Write Access Time = 1 cycle */
-#define B7WAT_2                0x00002000  /* Bank 7 Write Access Time = 2 cycles */
-#define B7WAT_3                0x00003000  /* Bank 7 Write Access Time = 3 cycles */
-#define B7WAT_4                0x00004000  /* Bank 7 Write Access Time = 4 cycles */
-#define B7WAT_5                0x00005000  /* Bank 7 Write Access Time = 5 cycles */
-#define B7WAT_6                0x00006000  /* Bank 7 Write Access Time = 6 cycles */
-#define B7WAT_7                0x00007000  /* Bank 7 Write Access Time = 7 cycles */
-#define B7WAT_8                0x00008000  /* Bank 7 Write Access Time = 8 cycles */
-#define B7WAT_9                0x00009000  /* Bank 7 Write Access Time = 9 cycles */
-#define B7WAT_10               0x0000A000  /* Bank 7 Write Access Time = 10 cycles */
-#define B7WAT_11               0x0000B000  /* Bank 7 Write Access Time = 11 cycles */
-#define B7WAT_12               0x0000C000  /* Bank 7 Write Access Time = 12 cycles */
-#define B7WAT_13               0x0000D000  /* Bank 7 Write Access Time = 13 cycles */
-#define B7WAT_14               0x0000E000  /* Bank 7 Write Access Time = 14 cycles */
-#define B7WAT_15               0x0000F000  /* Bank 7 Write Access Time = 15 cycles */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* __DEF_BF535_H */
diff --git a/libgloss/bfin/include/defBF536.h b/libgloss/bfin/include/defBF536.h
deleted file mode 100644
index 93aaf6725..000000000
--- a/libgloss/bfin/include/defBF536.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2005 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF536_H
-#define _DEF_BF536_H
-
-/* Identical MMR Space To BF537 Processor */
-#include <defBF537.h>
-
-#endif /* _DEF_BF536_H */
-
diff --git a/libgloss/bfin/include/defBF537.h b/libgloss/bfin/include/defBF537.h
deleted file mode 100644
index 29fa7e934..000000000
--- a/libgloss/bfin/include/defBF537.h
+++ /dev/null
@@ -1,441 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2004-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* Include all MMR and bit defines common to BF534 */
-#include <defBF534.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#pragma diag(suppress:misra_rule_19_11)
-#endif /* _MISRA_RULES */
-
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller	(0xFFC03000 - 0xFFC031FF)										*/
-#define	EMAC_OPMODE			0xFFC03000	/* Operating Mode Register								*/
-#define EMAC_ADDRLO			0xFFC03004	/* Address Low (32 LSBs) Register						*/
-#define EMAC_ADDRHI			0xFFC03008	/* Address High (16 MSBs) Register						*/
-#define EMAC_HASHLO			0xFFC0300C	/* Multicast Hash Table Low (Bins 31-0) Register		*/
-#define EMAC_HASHHI			0xFFC03010	/* Multicast Hash Table High (Bins 63-32) Register		*/
-#define EMAC_STAADD			0xFFC03014	/* Station Management Address Register					*/
-#define EMAC_STADAT			0xFFC03018	/* Station Management Data Register 					*/
-#define EMAC_FLC			0xFFC0301C	/* Flow Control Register								*/
-#define EMAC_VLAN1			0xFFC03020	/* VLAN1 Tag Register									*/
-#define EMAC_VLAN2			0xFFC03024	/* VLAN2 Tag Register									*/
-#define EMAC_WKUP_CTL		0xFFC0302C	/* Wake-Up Control/Status Register						*/
-#define EMAC_WKUP_FFMSK0	0xFFC03030	/* Wake-Up Frame Filter 0 Byte Mask Register			*/
-#define EMAC_WKUP_FFMSK1	0xFFC03034	/* Wake-Up Frame Filter 1 Byte Mask Register			*/
-#define EMAC_WKUP_FFMSK2	0xFFC03038	/* Wake-Up Frame Filter 2 Byte Mask Register			*/
-#define EMAC_WKUP_FFMSK3	0xFFC0303C	/* Wake-Up Frame Filter 3 Byte Mask Register			*/
-#define EMAC_WKUP_FFCMD		0xFFC03040	/* Wake-Up Frame Filter Commands Register				*/
-#define EMAC_WKUP_FFOFF		0xFFC03044	/* Wake-Up Frame Filter Offsets Register				*/
-#define EMAC_WKUP_FFCRC0	0xFFC03048	/* Wake-Up Frame Filter 0,1 CRC-16 Register				*/
-#define EMAC_WKUP_FFCRC1	0xFFC0304C	/* Wake-Up Frame Filter 2,3 CRC-16 Register				*/
-
-#define	EMAC_SYSCTL			0xFFC03060	/* EMAC System Control Register							*/
-#define EMAC_SYSTAT			0xFFC03064	/* EMAC System Status Register							*/
-#define EMAC_RX_STAT		0xFFC03068	/* RX Current Frame Status Register						*/
-#define EMAC_RX_STKY		0xFFC0306C	/* RX Sticky Frame Status Register						*/
-#define EMAC_RX_IRQE		0xFFC03070	/* RX Frame Status Interrupt Enables Register			*/
-#define EMAC_TX_STAT		0xFFC03074	/* TX Current Frame Status Register						*/
-#define EMAC_TX_STKY		0xFFC03078	/* TX Sticky Frame Status Register						*/
-#define EMAC_TX_IRQE		0xFFC0307C	/* TX Frame Status Interrupt Enables Register			*/
-
-#define EMAC_MMC_CTL		0xFFC03080	/* MMC Counter Control Register							*/
-#define EMAC_MMC_RIRQS		0xFFC03084	/* MMC RX Interrupt Status Register						*/
-#define EMAC_MMC_RIRQE		0xFFC03088	/* MMC RX Interrupt Enables Register					*/
-#define EMAC_MMC_TIRQS		0xFFC0308C	/* MMC TX Interrupt Status Register						*/
-#define EMAC_MMC_TIRQE		0xFFC03090	/* MMC TX Interrupt Enables Register					*/
-
-#define EMAC_RXC_OK			0xFFC03100	/* RX Frame Successful Count							*/
-#define EMAC_RXC_FCS		0xFFC03104	/* RX Frame FCS Failure Count							*/
-#define EMAC_RXC_ALIGN		0xFFC03108	/* RX Alignment Error Count								*/
-#define EMAC_RXC_OCTET		0xFFC0310C	/* RX Octets Successfully Received Count				*/
-#define EMAC_RXC_DMAOVF		0xFFC03110	/* Internal MAC Sublayer Error RX Frame Count			*/
-#define EMAC_RXC_UNICST		0xFFC03114	/* Unicast RX Frame Count								*/
-#define EMAC_RXC_MULTI		0xFFC03118	/* Multicast RX Frame Count								*/
-#define EMAC_RXC_BROAD		0xFFC0311C	/* Broadcast RX Frame Count								*/
-#define EMAC_RXC_LNERRI		0xFFC03120	/* RX Frame In Range Error Count						*/
-#define EMAC_RXC_LNERRO		0xFFC03124	/* RX Frame Out Of Range Error Count					*/
-#define EMAC_RXC_LONG		0xFFC03128	/* RX Frame Too Long Count								*/
-#define EMAC_RXC_MACCTL		0xFFC0312C	/* MAC Control RX Frame Count							*/
-#define EMAC_RXC_OPCODE		0xFFC03130	/* Unsupported Op-Code RX Frame Count					*/
-#define EMAC_RXC_PAUSE		0xFFC03134	/* MAC Control Pause RX Frame Count						*/
-#define EMAC_RXC_ALLFRM		0xFFC03138	/* Overall RX Frame Count								*/
-#define EMAC_RXC_ALLOCT		0xFFC0313C	/* Overall RX Octet Count								*/
-#define EMAC_RXC_TYPED		0xFFC03140	/* Type/Length Consistent RX Frame Count 				*/
-#define EMAC_RXC_SHORT		0xFFC03144	/* RX Frame Fragment Count - Byte Count x < 64			*/
-#define EMAC_RXC_EQ64		0xFFC03148	/* Good RX Frame Count - Byte Count x = 64				*/
-#define EMAC_RXC_LT128		0xFFC0314C	/* Good RX Frame Count - Byte Count  64 < x < 128		*/
-#define EMAC_RXC_LT256		0xFFC03150	/* Good RX Frame Count - Byte Count 128 <= x < 256		*/
-#define EMAC_RXC_LT512		0xFFC03154	/* Good RX Frame Count - Byte Count 256 <= x < 512		*/
-#define EMAC_RXC_LT1024		0xFFC03158	/* Good RX Frame Count - Byte Count 512 <= x < 1024		*/
-#define EMAC_RXC_GE1024		0xFFC0315C	/* Good RX Frame Count - Byte Count x >= 1024			*/
-
-#define EMAC_TXC_OK			0xFFC03180	/* TX Frame Successful Count							*/
-#define EMAC_TXC_1COL		0xFFC03184	/* TX Frames Successful After Single Collision Count	*/
-#define EMAC_TXC_GT1COL		0xFFC03188	/* TX Frames Successful After Multiple Collisions Count	*/
-#define EMAC_TXC_OCTET		0xFFC0318C	/* TX Octets Successfully Received Count				*/
-#define EMAC_TXC_DEFER		0xFFC03190	/* TX Frame Delayed Due To Busy Count					*/
-#define EMAC_TXC_LATECL		0xFFC03194	/* Late TX Collisions Count								*/
-#define EMAC_TXC_XS_COL		0xFFC03198	/* TX Frame Failed Due To Excessive Collisions Count	*/
-#define EMAC_TXC_DMAUND		0xFFC0319C	/* Internal MAC Sublayer Error TX Frame Count			*/
-#define EMAC_TXC_CRSERR		0xFFC031A0	/* Carrier Sense Deasserted During TX Frame Count		*/
-#define EMAC_TXC_UNICST		0xFFC031A4	/* Unicast TX Frame Count								*/
-#define EMAC_TXC_MULTI		0xFFC031A8	/* Multicast TX Frame Count								*/
-#define EMAC_TXC_BROAD		0xFFC031AC	/* Broadcast TX Frame Count								*/
-#define EMAC_TXC_XS_DFR		0xFFC031B0	/* TX Frames With Excessive Deferral Count				*/
-#define EMAC_TXC_MACCTL		0xFFC031B4	/* MAC Control TX Frame Count							*/
-#define EMAC_TXC_ALLFRM		0xFFC031B8	/* Overall TX Frame Count								*/
-#define EMAC_TXC_ALLOCT		0xFFC031BC	/* Overall TX Octet Count								*/
-#define EMAC_TXC_EQ64		0xFFC031C0	/* Good TX Frame Count - Byte Count x = 64				*/
-#define EMAC_TXC_LT128		0xFFC031C4	/* Good TX Frame Count - Byte Count  64 < x < 128		*/
-#define EMAC_TXC_LT256		0xFFC031C8	/* Good TX Frame Count - Byte Count 128 <= x < 256		*/
-#define EMAC_TXC_LT512		0xFFC031CC	/* Good TX Frame Count - Byte Count 256 <= x < 512		*/
-#define EMAC_TXC_LT1024		0xFFC031D0	/* Good TX Frame Count - Byte Count 512 <= x < 1024		*/
-#define EMAC_TXC_GE1024		0xFFC031D4	/* Good TX Frame Count - Byte Count x >= 1024			*/
-#define EMAC_TXC_ABORT		0xFFC031D8	/* Total TX Frames Aborted Count						*/
-
-/* Listing for IEEE-Supported Count Registers																	*/
-#define FramesReceivedOK				EMAC_RXC_OK		/* RX Frame Successful Count							*/
-#define FrameCheckSequenceErrors		EMAC_RXC_FCS	/* RX Frame FCS Failure Count							*/
-#define AlignmentErrors					EMAC_RXC_ALIGN	/* RX Alignment Error Count								*/
-#define OctetsReceivedOK				EMAC_RXC_OCTET	/* RX Octets Successfully Received Count				*/
-#define FramesLostDueToIntMACRcvError	EMAC_RXC_DMAOVF	/* Internal MAC Sublayer Error RX Frame Count			*/
-#define UnicastFramesReceivedOK			EMAC_RXC_UNICST	/* Unicast RX Frame Count								*/
-#define MulticastFramesReceivedOK		EMAC_RXC_MULTI	/* Multicast RX Frame Count								*/
-#define BroadcastFramesReceivedOK		EMAC_RXC_BROAD	/* Broadcast RX Frame Count								*/
-#define InRangeLengthErrors				EMAC_RXC_LNERRI	/* RX Frame In Range Error Count						*/
-#define OutOfRangeLengthField			EMAC_RXC_LNERRO	/* RX Frame Out Of Range Error Count					*/
-#define FrameTooLongErrors				EMAC_RXC_LONG	/* RX Frame Too Long Count								*/
-#define MACControlFramesReceived		EMAC_RXC_MACCTL	/* MAC Control RX Frame Count							*/
-#define UnsupportedOpcodesReceived		EMAC_RXC_OPCODE	/* Unsupported Op-Code RX Frame Count					*/
-#define PAUSEMACCtrlFramesReceived		EMAC_RXC_PAUSE	/* MAC Control Pause RX Frame Count						*/
-#define FramesReceivedAll				EMAC_RXC_ALLFRM	/* Overall RX Frame Count								*/
-#define OctetsReceivedAll				EMAC_RXC_ALLOCT	/* Overall RX Octet Count								*/
-#define TypedFramesReceived				EMAC_RXC_TYPED	/* Type/Length Consistent RX Frame Count 				*/
-#define FramesLenLt64Received			EMAC_RXC_SHORT	/* RX Frame Fragment Count - Byte Count x < 64			*/
-#define FramesLenEq64Received			EMAC_RXC_EQ64	/* Good RX Frame Count - Byte Count x = 64				*/
-#define FramesLen65_127Received			EMAC_RXC_LT128	/* Good RX Frame Count - Byte Count  64 < x < 128		*/
-#define FramesLen128_255Received		EMAC_RXC_LT256	/* Good RX Frame Count - Byte Count 128 <= x < 256		*/
-#define FramesLen256_511Received		EMAC_RXC_LT512	/* Good RX Frame Count - Byte Count 256 <= x < 512		*/
-#define FramesLen512_1023Received		EMAC_RXC_LT1024	/* Good RX Frame Count - Byte Count 512 <= x < 1024		*/
-#define FramesLen1024_MaxReceived		EMAC_RXC_GE1024	/* Good RX Frame Count - Byte Count x >= 1024			*/
-
-#define FramesTransmittedOK				EMAC_TXC_OK		/* TX Frame Successful Count							*/
-#define SingleCollisionFrames			EMAC_TXC_1COL	/* TX Frames Successful After Single Collision Count	*/
-#define MultipleCollisionFrames			EMAC_TXC_GT1COL	/* TX Frames Successful After Multiple Collisions Count	*/
-#define OctetsTransmittedOK				EMAC_TXC_OCTET	/* TX Octets Successfully Received Count				*/
-#define FramesWithDeferredXmissions		EMAC_TXC_DEFER	/* TX Frame Delayed Due To Busy Count					*/
-#define LateCollisions					EMAC_TXC_LATECL	/* Late TX Collisions Count								*/
-#define FramesAbortedDueToXSColls		EMAC_TXC_XS_COL	/* TX Frame Failed Due To Excessive Collisions Count	*/
-#define FramesLostDueToIntMacXmitError	EMAC_TXC_DMAUND	/* Internal MAC Sublayer Error TX Frame Count			*/
-#define CarrierSenseErrors				EMAC_TXC_CRSERR	/* Carrier Sense Deasserted During TX Frame Count		*/
-#define UnicastFramesXmittedOK			EMAC_TXC_UNICST	/* Unicast TX Frame Count								*/
-#define MulticastFramesXmittedOK		EMAC_TXC_MULTI	/* Multicast TX Frame Count								*/
-#define BroadcastFramesXmittedOK		EMAC_TXC_BROAD	/* Broadcast TX Frame Count								*/
-#define FramesWithExcessiveDeferral		EMAC_TXC_XS_DFR	/* TX Frames With Excessive Deferral Count				*/
-#define MACControlFramesTransmitted		EMAC_TXC_MACCTL	/* MAC Control TX Frame Count							*/
-#define FramesTransmittedAll			EMAC_TXC_ALLFRM	/* Overall TX Frame Count								*/
-#define OctetsTransmittedAll			EMAC_TXC_ALLOCT	/* Overall TX Octet Count								*/
-#define FramesLenEq64Transmitted		EMAC_TXC_EQ64	/* Good TX Frame Count - Byte Count x = 64				*/
-#define FramesLen65_127Transmitted		EMAC_TXC_LT128	/* Good TX Frame Count - Byte Count  64 < x < 128		*/
-#define FramesLen128_255Transmitted		EMAC_TXC_LT256	/* Good TX Frame Count - Byte Count 128 <= x < 256		*/
-#define FramesLen256_511Transmitted		EMAC_TXC_LT512	/* Good TX Frame Count - Byte Count 256 <= x < 512		*/
-#define FramesLen512_1023Transmitted	EMAC_TXC_LT1024	/* Good TX Frame Count - Byte Count 512 <= x < 1024		*/
-#define FramesLen1024_MaxTransmitted	EMAC_TXC_GE1024	/* Good TX Frame Count - Byte Count x >= 1024			*/
-#define TxAbortedFrames					EMAC_TXC_ABORT	/* Total TX Frames Aborted Count						*/
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**				Use these macros carefully, as any that do left shifts for field
-**				depositing will result in the lower order bits being destroyed.  Any
-**				macro that shifts left to properly position the bit-field should be
-**				used as part of an OR to initialize a register and NOT as a dynamic
-**				modifier UNLESS the lower order bits are saved and ORed back in when
-**				the macro is used.
-*************************************************************************************/
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-/* EMAC_OPMODE Masks																*/
-#define	RE			0x00000001	/* Receiver Enable									*/
-#define	ASTP		0x00000002	/* Enable Automatic Pad Stripping On RX Frames		*/
-#define	HU			0x00000010	/* Hash Filter Unicast Address						*/
-#define	HM			0x00000020	/* Hash Filter Multicast Address					*/
-#define	PAM			0x00000040	/* Pass-All-Multicast Mode Enable					*/
-#define	PR			0x00000080	/* Promiscuous Mode Enable							*/
-#define	IFE			0x00000100	/* Inverse Filtering Enable							*/
-#define	DBF			0x00000200	/* Disable Broadcast Frame Reception				*/
-#define	PBF			0x00000400	/* Pass Bad Frames Enable							*/
-#define	PSF			0x00000800	/* Pass Short Frames Enable							*/
-#define	RAF			0x00001000	/* Receive-All Mode									*/
-#define	TE			0x00010000	/* Transmitter Enable								*/
-#define	DTXPAD		0x00020000	/* Disable Automatic TX Padding						*/
-#define	DTXCRC		0x00040000	/* Disable Automatic TX CRC Generation				*/
-#define	DC			0x00080000	/* Deferral Check									*/
-#define	BOLMT		0x00300000	/* Back-Off Limit 									*/
-#define	BOLMT_10	0x00000000	/*		10-bit range								*/
-#define	BOLMT_8		0x00100000	/*		8-bit range									*/
-#define	BOLMT_4		0x00200000	/*		4-bit range									*/
-#define	BOLMT_1		0x00300000	/*		1-bit range									*/
-#define	DRTY		0x00400000	/* Disable TX Retry On Collision					*/
-#define	LCTRE		0x00800000	/* Enable TX Retry On Late Collision				*/
-#define	RMII		0x01000000	/* RMII/MII* Mode									*/
-#define	RMII_10		0x02000000	/* Speed Select for RMII Port (10MBit/100MBit*)		*/
-#define	FDMODE		0x04000000	/* Duplex Mode Enable (Full/Half*)					*/
-#define	LB			0x08000000	/* Internal Loopback Enable							*/
-#define	DRO			0x10000000	/* Disable Receive Own Frames (Half-Duplex Mode)	*/
-
-/* EMAC_STAADD Masks																*/
-#define	STABUSY		0x00000001	/* Initiate Station Mgt Reg Access / STA Busy Stat	*/
-#define	STAOP		0x00000002	/* Station Management Operation Code (Write/Read*)	*/
-#define	STADISPRE	0x00000004	/* Disable Preamble Generation						*/
-#define	STAIE		0x00000008	/* Station Mgt. Transfer Done Interrupt Enable		*/
-#define	REGAD		0x000007C0	/* STA Register Address								*/
-#define	PHYAD		0x0000F800	/* PHY Device Address								*/
-
-#ifdef _MISRA_RULES
-#define	SET_REGAD(x)	(((x)&0x1Fu)<<  6 )	/* Set STA Register Address				*/
-#define	SET_PHYAD(x)	(((x)&0x1Fu)<< 11 )	/* Set PHY Device Address				*/
-#else
-#define	SET_REGAD(x)	(((x)&0x1F)<<  6 )	/* Set STA Register Address				*/
-#define	SET_PHYAD(x)	(((x)&0x1F)<< 11 )	/* Set PHY Device Address				*/
-#endif /* _MISRA_RULES */
-
-/* EMAC_STADAT Mask											*/
-#define	STADATA		0x0000FFFF	/* Station Management Data	*/
-
-/* EMAC_FLC Masks																	*/
-#define	FLCBUSY		0x00000001	/* Send Flow Ctrl Frame / Flow Ctrl Busy Status		*/
-#define	FLCE		0x00000002	/* Flow Control Enable								*/
-#define	PCF			0x00000004	/* Pass Control Frames								*/
-#define	BKPRSEN		0x00000008	/* Enable Backpressure								*/
-#define	FLCPAUSE	0xFFFF0000	/* Pause Time										*/
-
-#ifdef _MISRA_RULES
-#define	SET_FLCPAUSE(x)	(((x)&0xFFFFu)<< 16)	/* Set Pause Time						*/
-#else
-#define	SET_FLCPAUSE(x)	(((x)&0xFFFF)<< 16)	/* Set Pause Time						*/
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_CTL Masks																*/
-#define	CAPWKFRM	0x00000001	/* Capture Wake-Up Frames							*/
-#define	MPKE		0x00000002	/* Magic Packet Enable								*/
-#define	RWKE		0x00000004	/* Remote Wake-Up Frame Enable						*/
-#define	GUWKE		0x00000008	/* Global Unicast Wake Enable						*/
-#define	MPKS		0x00000020	/* Magic Packet Received Status						*/
-#define	RWKS		0x00000F00	/* Wake-Up Frame Received Status, Filters 3:0		*/
-
-/* EMAC_WKUP_FFCMD Masks															*/
-#define	WF0_E		0x00000001	/* Enable Wake-Up Filter 0							*/
-#define	WF0_T		0x00000008	/* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)	*/
-#define	WF1_E		0x00000100	/* Enable Wake-Up Filter 1							*/
-#define	WF1_T		0x00000800	/* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)	*/
-#define	WF2_E		0x00010000	/* Enable Wake-Up Filter 2							*/
-#define	WF2_T		0x00080000	/* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)	*/
-#define	WF3_E		0x01000000	/* Enable Wake-Up Filter 3							*/
-#define	WF3_T		0x08000000	/* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)	*/
-
-/* EMAC_WKUP_FFOFF Masks															*/
-#define	WF0_OFF		0x000000FF	/* Wake-Up Filter 0 Pattern Offset					*/
-#define	WF1_OFF		0x0000FF00	/* Wake-Up Filter 1 Pattern Offset					*/
-#define	WF2_OFF		0x00FF0000	/* Wake-Up Filter 2 Pattern Offset					*/
-#define	WF3_OFF		0xFF000000	/* Wake-Up Filter 3 Pattern Offset					*/
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_OFF(x) (((x)&0xFFu)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset		*/
-#define	SET_WF1_OFF(x) (((x)&0xFFu)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset		*/
-#define	SET_WF2_OFF(x) (((x)&0xFFu)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset		*/
-#define	SET_WF3_OFF(x) (((x)&0xFFu)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset		*/
-#else
-#define	SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset		*/
-#define	SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset		*/
-#define	SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset		*/
-#define	SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset		*/
-#endif /* _MISRA_RULES */
-
-/* Set ALL Offsets																	*/
-#define	SET_WF_OFFS(x0,x1,x2,x3) 	(SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks															*/
-#define	WF0_CRC		0x0000FFFF	/* Wake-Up Filter 0 Pattern CRC						*/
-#define	WF1_CRC		0xFFFF0000	/* Wake-Up Filter 1 Pattern CRC						*/
-
-#ifdef _MISRA_RULES
-#define	SET_WF0_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 0 Target CRC		*/
-#define	SET_WF1_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 1 Target CRC		*/
-#else
-#define	SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC		*/
-#define	SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC		*/
-#endif /* _MISRA_RULES */
-
-/* EMAC_WKUP_FFCRC1 Masks															*/
-#define	WF2_CRC		0x0000FFFF	/* Wake-Up Filter 2 Pattern CRC						*/
-#define	WF3_CRC		0xFFFF0000	/* Wake-Up Filter 3 Pattern CRC						*/
-
-#ifdef _MISRA_RULES
-#define	SET_WF2_CRC(x) (((x)&0xFFFFu)<<   0 ) /* Set Wake-Up Filter 2 Target CRC		*/
-#define	SET_WF3_CRC(x) (((x)&0xFFFFu)<<  16 ) /* Set Wake-Up Filter 3 Target CRC		*/
-#else
-#define	SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC		*/
-#define	SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC		*/
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSCTL Masks																*/
-#define	PHYIE		0x00000001	/* PHY_INT Interrupt Enable							*/
-#define	RXDWA		0x00000002	/* Receive Frame DMA Word Alignment (Odd/Even*)		*/
-#define	RXCKS		0x00000004	/* Enable RX Frame TCP/UDP Checksum Computation		*/
-#define	MDCDIV		0x00003F00	/* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]		*/
-#if !defined(__SILICON_REVISION__) || (__SILICON_REVISION__>0x2)
-/* In BF536/7 revs. 0.0, 0.1 and 0.2, this bit was reserved */
-#define TXDWA 0x00000010  /* Transmit Frame DMA Word Alignment(Even/Odd*) */
-#endif
-#ifdef _MISRA_RULES
-#define	SET_MDCDIV(x)	(((x)&0x3Fu)<< 8)	/* Set MDC Clock Divisor				*/
-#else
-#define	SET_MDCDIV(x)	(((x)&0x3F)<< 8)	/* Set MDC Clock Divisor				*/
-#endif /* _MISRA_RULES */
-
-/* EMAC_SYSTAT Masks															*/
-#define	PHYINT		0x00000001	/* PHY_INT Interrupt Status						*/
-#define	MMCINT		0x00000002	/* MMC Counter Interrupt Status					*/
-#define	RXFSINT		0x00000004	/* RX Frame-Status Interrupt Status				*/
-#define	TXFSINT		0x00000008	/* TX Frame-Status Interrupt Status				*/
-#define	WAKEDET		0x00000010	/* Wake-Up Detected Status						*/
-#define	RXDMAERR	0x00000020	/* RX DMA Direction Error Status				*/
-#define	TXDMAERR	0x00000040	/* TX DMA Direction Error Status				*/
-#define	STMDONE		0x00000080	/* Station Mgt. Transfer Done Interrupt Status	*/
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks							*/
-#define	RX_FRLEN	0x000007FF	/* Frame Length In Bytes						*/
-#define	RX_COMP		0x00001000	/* RX Frame Complete							*/
-#define	RX_OK		0x00002000	/* RX Frame Received With No Errors				*/
-#define	RX_LONG		0x00004000	/* RX Frame Too Long Error						*/
-#define	RX_ALIGN	0x00008000	/* RX Frame Alignment Error						*/
-#define	RX_CRC		0x00010000	/* RX Frame CRC Error							*/
-#define	RX_LEN		0x00020000	/* RX Frame Length Error						*/
-#define	RX_FRAG		0x00040000	/* RX Frame Fragment Error						*/
-#define	RX_ADDR		0x00080000	/* RX Frame Address Filter Failed Error			*/
-#define	RX_DMAO		0x00100000	/* RX Frame DMA Overrun Error					*/
-#define	RX_PHY		0x00200000	/* RX Frame PHY Error							*/
-#define	RX_LATE		0x00400000	/* RX Frame Late Collision Error				*/
-#define	RX_RANGE	0x00800000	/* RX Frame Length Field Out of Range Error		*/
-#define	RX_MULTI	0x01000000	/* RX Multicast Frame Indicator					*/
-#define	RX_BROAD	0x02000000	/* RX Broadcast Frame Indicator					*/
-#define	RX_CTL		0x04000000	/* RX Control Frame Indicator					*/
-#define	RX_UCTL		0x08000000	/* Unsupported RX Control Frame Indicator		*/
-#define	RX_TYPE		0x10000000	/* RX Typed Frame Indicator						*/
-#define	RX_VLAN1	0x20000000	/* RX VLAN1 Frame Indicator						*/
-#define	RX_VLAN2	0x40000000	/* RX VLAN2 Frame Indicator						*/
-#define	RX_ACCEPT	0x80000000	/* RX Frame Accepted Indicator					*/
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks							*/
-#define	TX_COMP		0x00000001	/* TX Frame Complete							*/
-#define	TX_OK		0x00000002	/* TX Frame Sent With No Errors					*/
-#define	TX_ECOLL	0x00000004	/* TX Frame Excessive Collision Error			*/
-#define	TX_LATE		0x00000008	/* TX Frame Late Collision Error				*/
-#define	TX_DMAU		0x00000010	/* TX Frame DMA Underrun Error (STAT)			*/
-#define	TX_MACE		0x00000010	/* Internal MAC Error Detected (STKY and IRQE)	*/
-#define	TX_EDEFER	0x00000020	/* TX Frame Excessive Deferral Error			*/
-#define	TX_BROAD	0x00000040	/* TX Broadcast Frame Indicator					*/
-#define	TX_MULTI	0x00000080	/* TX Multicast Frame Indicator					*/
-#define	TX_CCNT		0x00000F00	/* TX Frame Collision Count						*/
-#define	TX_DEFER	0x00001000	/* TX Frame Deferred Indicator					*/
-#define	TX_CRS		0x00002000	/* TX Frame Carrier Sense Not Asserted Error	*/
-#define	TX_LOSS		0x00004000	/* TX Frame Carrier Lost During TX Error		*/
-#define	TX_RETRY	0x00008000	/* TX Frame Successful After Retry				*/
-#define	TX_FRLEN	0x07FF0000	/* TX Frame Length (Bytes)						*/
-
-/* EMAC_MMC_CTL Masks															*/
-#define	RSTC		0x00000001	/* Reset All Counters							*/
-#define	CROLL		0x00000002	/* Counter Roll-Over Enable						*/
-#define	CCOR		0x00000004	/* Counter Clear-On-Read Mode Enable			*/
-#define	MMCE		0x00000008	/* Enable MMC Counter Operation					*/
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks											*/
-#define	RX_OK_CNT		0x00000001	/* RX Frames Received With No Errors			*/
-#define	RX_FCS_CNT		0x00000002	/* RX Frames W/Frame Check Sequence Errors		*/
-#define	RX_ALIGN_CNT	0x00000004	/* RX Frames With Alignment Errors				*/
-#define	RX_OCTET_CNT	0x00000008	/* RX Octets Received OK						*/
-#define	RX_LOST_CNT		0x00000010	/* RX Frames Lost Due To Internal MAC RX Error	*/
-#define	RX_UNI_CNT		0x00000020	/* Unicast RX Frames Received OK 				*/
-#define	RX_MULTI_CNT	0x00000040	/* Multicast RX Frames Received OK				*/
-#define	RX_BROAD_CNT	0x00000080	/* Broadcast RX Frames Received OK				*/
-#define	RX_IRL_CNT		0x00000100	/* RX Frames With In-Range Length Errors		*/
-#define	RX_ORL_CNT		0x00000200	/* RX Frames With Out-Of-Range Length Errors	*/
-#define	RX_LONG_CNT		0x00000400	/* RX Frames With Frame Too Long Errors			*/
-#define	RX_MACCTL_CNT	0x00000800	/* MAC Control RX Frames Received				*/
-#define	RX_OPCODE_CTL	0x00001000	/* Unsupported Op-Code RX Frames Received		*/
-#define	RX_PAUSE_CNT	0x00002000	/* PAUSEMAC Control RX Frames Received			*/
-#define	RX_ALLF_CNT		0x00004000	/* All RX Frames Received						*/
-#define	RX_ALLO_CNT		0x00008000	/* All RX Octets Received						*/
-#define	RX_TYPED_CNT	0x00010000	/* Typed RX Frames Received						*/
-#define	RX_SHORT_CNT	0x00020000	/* RX Frame Fragments (< 64 Bytes) Received		*/
-#define	RX_EQ64_CNT		0x00040000	/* 64-Byte RX Frames Received					*/
-#define	RX_LT128_CNT	0x00080000	/* 65-127-Byte RX Frames Received				*/
-#define	RX_LT256_CNT	0x00100000	/* 128-255-Byte RX Frames Received				*/
-#define	RX_LT512_CNT	0x00200000	/* 256-511-Byte RX Frames Received				*/
-#define	RX_LT1024_CNT	0x00400000	/* 512-1023-Byte RX Frames Received				*/
-#define	RX_GE1024_CNT	0x00800000	/* 1024-Max-Byte RX Frames Received				*/
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks											*/
-#define	TX_OK_CNT		0x00000001	/* TX Frames Sent OK							*/
-#define	TX_SCOLL_CNT	0x00000002	/* TX Frames With Single Collisions				*/
-#define	TX_MCOLL_CNT	0x00000004	/* TX Frames With Multiple Collisions			*/
-#define	TX_OCTET_CNT	0x00000008	/* TX Octets Sent OK							*/
-#define	TX_DEFER_CNT	0x00000010	/* TX Frames With Deferred Transmission			*/
-#define	TX_LATE_CNT		0x00000020	/* TX Frames With Late Collisions				*/
-#define	TX_ABORTC_CNT	0x00000040	/* TX Frames Aborted Due To Excess Collisions	*/
-#define	TX_LOST_CNT		0x00000080	/* TX Frames Lost Due To Internal MAC TX Error	*/
-#define	TX_CRS_CNT		0x00000100	/* TX Frames With Carrier Sense Errors			*/
-#define	TX_UNI_CNT		0x00000200	/* Unicast TX Frames Sent						*/
-#define	TX_MULTI_CNT	0x00000400	/* Multicast TX Frames Sent						*/
-#define	TX_BROAD_CNT	0x00000800	/* Broadcast TX Frames Sent						*/
-#define	TX_EXDEF_CTL	0x00001000	/* TX Frames With Excessive Deferral			*/
-#define	TX_MACCTL_CNT	0x00002000	/* MAC Control TX Frames Sent					*/
-#define	TX_ALLF_CNT		0x00004000	/* All TX Frames Sent							*/
-#define	TX_ALLO_CNT		0x00008000	/* All TX Octets Sent							*/
-#define	TX_EQ64_CNT		0x00010000	/* 64-Byte TX Frames Sent						*/
-#define	TX_LT128_CNT	0x00020000	/* 65-127-Byte TX Frames Sent					*/
-#define	TX_LT256_CNT	0x00040000	/* 128-255-Byte TX Frames Sent					*/
-#define	TX_LT512_CNT	0x00080000	/* 256-511-Byte TX Frames Sent					*/
-#define	TX_LT1024_CNT	0x00100000	/* 512-1023-Byte TX Frames Sent					*/
-#define	TX_GE1024_CNT	0x00200000	/* 1024-Max-Byte TX Frames Sent					*/
-#define	TX_ABORT_CNT	0x00400000	/* TX Frames Aborted							*/
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF537_H */
-
diff --git a/libgloss/bfin/include/defBF538.h b/libgloss/bfin/include/defBF538.h
deleted file mode 100644
index 2757a04b3..000000000
--- a/libgloss/bfin/include/defBF538.h
+++ /dev/null
@@ -1,1948 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
-**
-** defBF538.h
-**
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-*************************************************************************/
-
-/*
-** This include file contains a list of macro "defines" to enable the
-** programmer to use symbolic names for ADSP-BF538 peripherals.
-*/
-
-#ifndef _DEF_BF538_H
-#define _DEF_BF538_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* Include all System registers and bit definitions common to ADSP-BF532 */
-#include <defBF532.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_6)
-#pragma diag(suppress:misra_rule_19_7)
-#endif /* _MISRA_RULES */
-
-
-/********************************************************************************
- * System MMR Register Map
- ********************************************************************************/
-/* Define MMR Space for Additional BF538 Peripherals */
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)						*/
-/* SIC0 on ADSP-BF538 Is Same As SIC on ADSP-BF532		*/
-#define SIC_IMASK0			SIC_IMASK	/* Interrupt Mask Register 0			*/
-#define SIC_ISR0			SIC_ISR	/* Interrupt Status Register 0			*/
-#define SIC_IWR0			SIC_IWR	/* Interrupt Wakeup Register 0			*/
-
-/* Add SIC1 MMRs for ADSP-BF538 Processors		*/
-#define SIC_IMASK1			0xFFC00128	/* Interrupt Mask Register 1			*/
-#define SIC_ISR1			0xFFC0012C	/* Interrupt Status Register 1			*/
-#define SIC_IWR1			0xFFC00130	/* Interrupt Wakeup Register 1			*/
-
-/* Add SIC1 Interrupt Sources for ADSP-BF538 Processors		*/
-#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3		*/
-#define SIC_IAR4			0xFFC00134	/* Interrupt Assignment Register 4		*/
-#define SIC_IAR5			0xFFC00138	/* Interrupt Assignment Register 5		*/
-#define SIC_IAR6			0xFFC0013C	/* Interrupt Assignment Register 6		*/
-
-
-/* UART0 Controller		(0xFFC00400 - 0xFFC004FF)								*/
-/* UART0 on ADSP-BF538 Is Same As UART on ADSP-BF532	*/
-#define UART0_THR			UART_THR	/* Transmit Holding register			*/
-#define UART0_RBR			UART_RBR	/* Receive Buffer register				*/
-#define UART0_DLL			UART_DLL	/* Divisor Latch (Low-Byte)				*/
-#define UART0_IER			UART_IER	/* Interrupt Enable Register			*/
-#define UART0_DLH			UART_DLH	/* Divisor Latch (High-Byte)			*/
-#define UART0_IIR			UART_IIR	/* Interrupt Identification Register	*/
-#define UART0_LCR			UART_LCR	/* Line Control Register				*/
-#define UART0_MCR			UART_MCR	/* Modem Control Register				*/
-#define UART0_LSR			UART_LSR	/* Line Status Register					*/
-#define UART0_SCR			UART_SCR	/* SCR Scratch Register					*/
-#define UART0_GCTL			UART_GCTL	/* Global Control Register				*/
-
-
-/* SPI0 Controller		(0xFFC00500 - 0xFFC005FF)								*/
-/* SPI0 on ADSP-BF538 Is Same As SPI on ADSP-BF532	*/
-#define SPI0_CTL			SPI_CTL	/* SPI0 Control Register				*/
-#define SPI0_FLG			SPI_FLG	/* SPI0 Flag register					*/
-#define SPI0_STAT			SPI_STAT	/* SPI0 Status register					*/
-#define SPI0_TDBR			SPI_TDBR	/* SPI0 Transmit Data Buffer Register	*/
-#define SPI0_RDBR			SPI_RDBR	/* SPI0 Receive Data Buffer Register	*/
-#define SPI0_BAUD			SPI_BAUD	/* SPI0 Baud rate Register				*/
-#define SPI0_SHADOW			SPI_SHADOW	/* SPI0_RDBR Shadow Register			*/
-
-
-/* General-Purpose Port F	(0xFFC00700 - 0xFFC007FF)										*/
-/* ADSP-BF538 Refers to FIO as GPIO Port F */
-#define PORTFIO					FIO_FLAG_D	/* GPIO Port F Pin State Specify Register				*/
-#define PORTFIO_CLEAR			FIO_FLAG_C	/* Peripheral Interrupt GPIO Clear Register		*/
-#define PORTFIO_SET				FIO_FLAG_S	/* Peripheral Interrupt GPIO Set Register		*/
-#define PORTFIO_TOGGLE			FIO_FLAG_T	/* GPIO Port F Pin State Toggle Register				*/
-#define PORTFIO_MASKA			FIO_MASKA_D	/* GPIO Port F Mask State Specify Interrupt A Register	*/
-#define PORTFIO_MASKA_CLEAR		FIO_MASKA_C	/* GPIO Port F Mask Disable Interrupt A Register		*/
-#define PORTFIO_MASKA_SET		FIO_MASKA_S	/* GPIO Port F Mask Enable Interrupt A Register		*/
-#define PORTFIO_MASKA_TOGGLE	FIO_MASKA_T	/* GPIO Port F Mask Toggle Enable Interrupt A Register	*/
-#define PORTFIO_MASKB			FIO_MASKB_D	/* GPIO Port F Mask State Specify Interrupt B Register	*/
-#define PORTFIO_MASKB_CLEAR		FIO_MASKB_C	/* GPIO Port F Mask Disable Interrupt B Register		*/
-#define PORTFIO_MASKB_SET		FIO_MASKB_S	/* GPIO Port F Mask Enable Interrupt B Register		*/
-#define PORTFIO_MASKB_TOGGLE	FIO_MASKB_T	/* GPIO Port F Mask Toggle Enable Interrupt B Register	*/
-#define PORTFIO_DIR				FIO_DIR	/* GPIO Port F Direction Register			*/
-#define PORTFIO_POLAR			FIO_POLAR	/* GPIO Port F Source Polarity Register				*/
-#define PORTFIO_EDGE			FIO_EDGE	/* GPIO Port F Source Sensitivity Register				*/
-#define PORTFIO_BOTH			FIO_BOTH	/* GPIO Port F Set on BOTH Edges Register				*/
-#define PORTFIO_INEN			FIO_INEN	/* GPIO Port F Input Enable Register					*/
-
-
-/* DMA0 Test Registers (0xFFC00B00 - 0xFFC00BFF)										*/
-/* ADSP-BF538 DMA0 Controller Is Same As ADSP-BF532 DMA Controller	*/
-#define DMAC0_TC_PER 			0xFFC00B0C	/* Traffic Control Periods Register */
-#define DMAC0_TC_CNT 			0xFFC00B10	/* Traffic Control Current Counts Register */
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA0_TC_PER				DMAC0_TC_PER	/* Traffic Control Periods Register			*/
-#define DMA0_TC_CNT				DMAC0_TC_CNT	/* Traffic Control Current Counts Register	*/
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA0_TCPER				DMA0_TC_PER	/* Traffic Control Periods Register			*/
-#define DMA0_TCCNT				DMA0_TC_CNT	/* Traffic Control Current Counts Register	*/
-
-/* ADSP-BF538 Must Enumerate Memory DMA Channels By Controller */
-#define MDMA0_D0_NEXT_DESC_PTR	MDMA_D0_NEXT_DESC_PTR	/* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA0_D0_START_ADDR		MDMA_D0_START_ADDR	/* MemDMA0 Stream 0 Destination Start Address Register				*/
-#define MDMA0_D0_CONFIG			MDMA_D0_CONFIG	/* MemDMA0 Stream 0 Destination Configuration Register				*/
-#define MDMA0_D0_X_COUNT		MDMA_D0_X_COUNT	/* MemDMA0 Stream 0 Destination X Count Register						*/
-#define MDMA0_D0_X_MODIFY		MDMA_D0_X_MODIFY	/* MemDMA0 Stream 0 Destination X Modify Register					*/
-#define MDMA0_D0_Y_COUNT		MDMA_D0_Y_COUNT	/* MemDMA0 Stream 0 Destination Y Count Register						*/
-#define MDMA0_D0_Y_MODIFY		MDMA_D0_Y_MODIFY	/* MemDMA0 Stream 0 Destination Y Modify Register					*/
-#define MDMA0_D0_CURR_DESC_PTR	MDMA_D0_CURR_DESC_PTR	/* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA0_D0_CURR_ADDR		MDMA_D0_CURR_ADDR	/* MemDMA0 Stream 0 Destination Current Address Register				*/
-#define MDMA0_D0_IRQ_STATUS		MDMA_D0_IRQ_STATUS	/* MemDMA0 Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA0_D0_PERIPHERAL_MAP	MDMA_D0_PERIPHERAL_MAP	/* MemDMA0 Stream 0 Destination Peripheral Map Register				*/
-#define MDMA0_D0_CURR_X_COUNT	MDMA_D0_CURR_X_COUNT	/* MemDMA0 Stream 0 Destination Current X Count Register				*/
-#define MDMA0_D0_CURR_Y_COUNT	MDMA_D0_CURR_Y_COUNT	/* MemDMA0 Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA0_S0_NEXT_DESC_PTR	MDMA_S0_NEXT_DESC_PTR	/* MemDMA0 Stream 0 Source Next Descriptor Pointer Register		*/
-#define MDMA0_S0_START_ADDR		MDMA_S0_START_ADDR	/* MemDMA0 Stream 0 Source Start Address Register				*/
-#define MDMA0_S0_CONFIG			MDMA_S0_CONFIG	/* MemDMA0 Stream 0 Source Configuration Register				*/
-#define MDMA0_S0_X_COUNT		MDMA_S0_X_COUNT	/* MemDMA Stream 0 Source X Count Register						*/
-#define MDMA0_S0_X_MODIFY		MDMA_S0_X_MODIFY	/* MemDMA0 Stream 0 Source X Modify Register					*/
-#define MDMA0_S0_Y_COUNT		MDMA_S0_Y_COUNT	/* MemDMA0 Stream 0 Source Y Count Register						*/
-#define MDMA0_S0_Y_MODIFY		MDMA_S0_Y_MODIFY	/* MemDMA0 Stream 0 Source Y Modify Register					*/
-#define MDMA0_S0_CURR_DESC_PTR	MDMA_S0_CURR_DESC_PTR	/* MemDMA0 Stream 0 Source Current Descriptor Pointer Register	*/
-#define MDMA0_S0_CURR_ADDR		MDMA_S0_CURR_ADDR	/* MemDMA0 Stream 0 Source Current Address Register				*/
-#define MDMA0_S0_IRQ_STATUS		MDMA_S0_IRQ_STATUS	/* MemDMA0 Stream 0 Source Interrupt/Status Register			*/
-#define MDMA0_S0_PERIPHERAL_MAP	MDMA_S0_PERIPHERAL_MAP	/* MemDMA0 Stream 0 Source Peripheral Map Register				*/
-#define MDMA0_S0_CURR_X_COUNT	MDMA_S0_CURR_X_COUNT	/* MemDMA0 Stream 0 Source Current X Count Register				*/
-#define MDMA0_S0_CURR_Y_COUNT	MDMA_S0_CURR_Y_COUNT	/* MemDMA0 Stream 0 Source Current Y Count Register				*/
-
-#define MDMA0_D1_NEXT_DESC_PTR	MDMA_D1_NEXT_DESC_PTR	/* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA0_D1_START_ADDR		MDMA_D1_START_ADDR	/* MemDMA0 Stream 1 Destination Start Address Register				*/
-#define MDMA0_D1_CONFIG			MDMA_D1_CONFIG	/* MemDMA0 Stream 1 Destination Configuration Register				*/
-#define MDMA0_D1_X_COUNT		MDMA_D1_X_COUNT	/* MemDMA0 Stream 1 Destination X Count Register						*/
-#define MDMA0_D1_X_MODIFY		MDMA_D1_X_MODIFY	/* MemDMA0 Stream 1 Destination X Modify Register					*/
-#define MDMA0_D1_Y_COUNT		MDMA_D1_Y_COUNT	/* MemDMA0 Stream 1 Destination Y Count Register						*/
-#define MDMA0_D1_Y_MODIFY		MDMA_D1_Y_MODIFY	/* MemDMA0 Stream 1 Destination Y Modify Register					*/
-#define MDMA0_D1_CURR_DESC_PTR	MDMA_D1_CURR_DESC_PTR	/* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA0_D1_CURR_ADDR		MDMA_D1_CURR_ADDR	/* MemDMA0 Stream 1 Destination Current Address Register				*/
-#define MDMA0_D1_IRQ_STATUS		MDMA_D1_IRQ_STATUS	/* MemDMA0 Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA0_D1_PERIPHERAL_MAP	MDMA_D1_PERIPHERAL_MAP	/* MemDMA0 Stream 1 Destination Peripheral Map Register				*/
-#define MDMA0_D1_CURR_X_COUNT	MDMA_D1_CURR_X_COUNT	/* MemDMA0 Stream 1 Destination Current X Count Register				*/
-#define MDMA0_D1_CURR_Y_COUNT	MDMA_D1_CURR_Y_COUNT	/* MemDMA0 Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA0_S1_NEXT_DESC_PTR	MDMA_S1_NEXT_DESC_PTR	/* MemDMA0 Stream 1 Source Next Descriptor Pointer Register		*/
-#define MDMA0_S1_START_ADDR		MDMA_S1_START_ADDR	/* MemDMA0 Stream 1 Source Start Address Register				*/
-#define MDMA0_S1_CONFIG			MDMA_S1_CONFIG	/* MemDMA0 Stream 1 Source Configuration Register				*/
-#define MDMA0_S1_X_COUNT		MDMA_S1_X_COUNT	/* MemDMA0 Stream 1 Source X Count Register						*/
-#define MDMA0_S1_X_MODIFY		MDMA_S1_X_MODIFY	/* MemDMA0 Stream 1 Source X Modify Register					*/
-#define MDMA0_S1_Y_COUNT		MDMA_S1_Y_COUNT	/* MemDMA0 Stream 1 Source Y Count Register						*/
-#define MDMA0_S1_Y_MODIFY		MDMA_S1_Y_MODIFY	/* MemDMA0 Stream 1 Source Y Modify Register					*/
-#define MDMA0_S1_CURR_DESC_PTR	MDMA_S1_CURR_DESC_PTR	/* MemDMA0 Stream 1 Source Current Descriptor Pointer Register	*/
-#define MDMA0_S1_CURR_ADDR		MDMA_S1_CURR_ADDR	/* MemDMA0 Stream 1 Source Current Address Register				*/
-#define MDMA0_S1_IRQ_STATUS		MDMA_S1_IRQ_STATUS	/* MemDMA0 Stream 1 Source Interrupt/Status Register			*/
-#define MDMA0_S1_PERIPHERAL_MAP	MDMA_S1_PERIPHERAL_MAP	/* MemDMA0 Stream 1 Source Peripheral Map Register				*/
-#define MDMA0_S1_CURR_X_COUNT	MDMA_S1_CURR_X_COUNT	/* MemDMA0 Stream 1 Source Current X Count Register				*/
-#define MDMA0_S1_CURR_Y_COUNT	MDMA_S1_CURR_Y_COUNT	/* MemDMA0 Stream 1 Source Current Y Count Register				*/
-
-
-/* Two-Wire Interface 0	(0xFFC01400 - 0xFFC014FF)										*/
-#define TWI0_CLKDIV			0xFFC01400	/* Serial Clock Divider Register				*/
-#define TWI0_CONTROL		0xFFC01404	/* TWI0 Master Internal Time Reference Register	*/
-#define TWI0_SLAVE_CTRL		0xFFC01408	/* Slave Mode Control Register					*/
-#define TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register					*/
-#define TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register					*/
-#define TWI0_MASTER_CTRL	0xFFC01414	/* Master Mode Control Register					*/
-#define TWI0_MASTER_STAT	0xFFC01418	/* Master Mode Status Register					*/
-#define TWI0_MASTER_ADDR	0xFFC0141C	/* Master Mode Address Register					*/
-#define TWI0_INT_STAT		0xFFC01420	/* TWI0 Master Interrupt Register				*/
-#define TWI0_INT_MASK		0xFFC01424	/* TWI0 Master Interrupt Mask Register			*/
-#define TWI0_FIFO_CTRL		0xFFC01428	/* FIFO Control Register						*/
-#define TWI0_FIFO_STAT		0xFFC0142C	/* FIFO Status Register							*/
-#define TWI0_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register		*/
-#define TWI0_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register		*/
-#define TWI0_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register		*/
-#define TWI0_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register		*/
-
-
-/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)								*/
-/* Port C */
-#define PORTCIO_FER			0xFFC01500	/* GPIO Pin Port C Configuration Register	*/
-#define PORTCIO				0xFFC01510	/* GPIO Pin Port C Data Register			*/
-#define PORTCIO_CLEAR		0xFFC01520	/* Clear GPIO Pin Port C Register			*/
-#define PORTCIO_SET			0xFFC01530	/* Set GPIO Pin Port C Register				*/
-#define PORTCIO_TOGGLE		0xFFC01540	/* Toggle GPIO Pin Port C Register			*/
-#define PORTCIO_DIR			0xFFC01550	/* GPIO Pin Port C Direction Register		*/
-#define PORTCIO_INEN		0xFFC01560	/* GPIO Pin Port C Input Enable Register	*/
-
-/* Port D */
-#define PORTDIO_FER			0xFFC01504	/* GPIO Pin Port D Configuration Register	*/
-#define PORTDIO				0xFFC01514	/* GPIO Pin Port D Data Register			*/
-#define PORTDIO_CLEAR		0xFFC01524	/* Clear GPIO Pin Port D Register			*/
-#define PORTDIO_SET			0xFFC01534	/* Set GPIO Pin Port D Register				*/
-#define PORTDIO_TOGGLE		0xFFC01544	/* Toggle GPIO Pin Port D Register			*/
-#define PORTDIO_DIR			0xFFC01554	/* GPIO Pin Port D Direction Register		*/
-#define PORTDIO_INEN		0xFFC01564	/* GPIO Pin Port D Input Enable Register	*/
-
-/* Port E */
-#define PORTEIO_FER			0xFFC01508	/* GPIO Pin Port E Configuration Register	*/
-#define PORTEIO				0xFFC01518	/* GPIO Pin Port E Data Register			*/
-#define PORTEIO_CLEAR		0xFFC01528	/* Clear GPIO Pin Port E Register			*/
-#define PORTEIO_SET			0xFFC01538	/* Set GPIO Pin Port E Register				*/
-#define PORTEIO_TOGGLE		0xFFC01548	/* Toggle GPIO Pin Port E Register			*/
-#define PORTEIO_DIR			0xFFC01558	/* GPIO Pin Port E Direction Register		*/
-#define PORTEIO_INEN		0xFFC01568	/* GPIO Pin Port E Input Enable Register	*/
-
-
-/* ADSP-BF538 Adds DMA1 Controller	*/
-/* DMA1 Test Registers (0xFFC01B00 - 0xFFC01BFF)										*/
-#define DMAC1_TC_PER				0xFFC01B0C	/* Traffic Control Periods Register			*/
-#define DMAC1_TC_CNT				0xFFC01B10	/* Traffic Control Current Counts Register	*/
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA1_TC_PER				DMAC1_TC_PER	/* Traffic Control Periods Register			*/
-#define DMA1_TC_CNT				DMAC1_TC_CNT	/* Traffic Control Current Counts Register	*/
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA1_TCPER				DMA1_TC_PER	/* Traffic Control Periods Register			*/
-#define DMA1_TCCNT				DMA1_TC_CNT	/* Traffic Control Current Counts Register	*/
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)														*/
-#define DMA8_NEXT_DESC_PTR		0xFFC01C00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
-#define DMA8_START_ADDR			0xFFC01C04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG				0xFFC01C08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC01C10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC01C14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC01C18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC01C1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC01C20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
-#define DMA8_CURR_ADDR			0xFFC01C24	/* DMA Channel 8 Current Address Register				*/
-#define DMA8_IRQ_STATUS			0xFFC01C28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC01C2C	/* DMA Channel 8 Peripheral Map Register				*/
-#define DMA8_CURR_X_COUNT		0xFFC01C30	/* DMA Channel 8 Current X Count Register				*/
-#define DMA8_CURR_Y_COUNT		0xFFC01C38	/* DMA Channel 8 Current Y Count Register				*/
-
-#define DMA9_NEXT_DESC_PTR		0xFFC01C40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
-#define DMA9_START_ADDR			0xFFC01C44	/* DMA Channel 9 Start Address Register					*/
-#define DMA9_CONFIG				0xFFC01C48	/* DMA Channel 9 Configuration Register					*/
-#define DMA9_X_COUNT			0xFFC01C50	/* DMA Channel 9 X Count Register						*/
-#define DMA9_X_MODIFY			0xFFC01C54	/* DMA Channel 9 X Modify Register						*/
-#define DMA9_Y_COUNT			0xFFC01C58	/* DMA Channel 9 Y Count Register						*/
-#define DMA9_Y_MODIFY			0xFFC01C5C	/* DMA Channel 9 Y Modify Register						*/
-#define DMA9_CURR_DESC_PTR		0xFFC01C60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
-#define DMA9_CURR_ADDR			0xFFC01C64	/* DMA Channel 9 Current Address Register				*/
-#define DMA9_IRQ_STATUS			0xFFC01C68	/* DMA Channel 9 Interrupt/Status Register				*/
-#define DMA9_PERIPHERAL_MAP		0xFFC01C6C	/* DMA Channel 9 Peripheral Map Register				*/
-#define DMA9_CURR_X_COUNT		0xFFC01C70	/* DMA Channel 9 Current X Count Register				*/
-#define DMA9_CURR_Y_COUNT		0xFFC01C78	/* DMA Channel 9 Current Y Count Register				*/
-
-#define DMA10_NEXT_DESC_PTR		0xFFC01C80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
-#define DMA10_START_ADDR		0xFFC01C84	/* DMA Channel 10 Start Address Register				*/
-#define DMA10_CONFIG			0xFFC01C88	/* DMA Channel 10 Configuration Register				*/
-#define DMA10_X_COUNT			0xFFC01C90	/* DMA Channel 10 X Count Register						*/
-#define DMA10_X_MODIFY			0xFFC01C94	/* DMA Channel 10 X Modify Register						*/
-#define DMA10_Y_COUNT			0xFFC01C98	/* DMA Channel 10 Y Count Register						*/
-#define DMA10_Y_MODIFY			0xFFC01C9C	/* DMA Channel 10 Y Modify Register						*/
-#define DMA10_CURR_DESC_PTR		0xFFC01CA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
-#define DMA10_CURR_ADDR			0xFFC01CA4	/* DMA Channel 10 Current Address Register				*/
-#define DMA10_IRQ_STATUS		0xFFC01CA8	/* DMA Channel 10 Interrupt/Status Register				*/
-#define DMA10_PERIPHERAL_MAP	0xFFC01CAC	/* DMA Channel 10 Peripheral Map Register				*/
-#define DMA10_CURR_X_COUNT		0xFFC01CB0	/* DMA Channel 10 Current X Count Register				*/
-#define DMA10_CURR_Y_COUNT		0xFFC01CB8	/* DMA Channel 10 Current Y Count Register				*/
-
-#define DMA11_NEXT_DESC_PTR		0xFFC01CC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
-#define DMA11_START_ADDR		0xFFC01CC4	/* DMA Channel 11 Start Address Register				*/
-#define DMA11_CONFIG			0xFFC01CC8	/* DMA Channel 11 Configuration Register				*/
-#define DMA11_X_COUNT			0xFFC01CD0	/* DMA Channel 11 X Count Register						*/
-#define DMA11_X_MODIFY			0xFFC01CD4	/* DMA Channel 11 X Modify Register						*/
-#define DMA11_Y_COUNT			0xFFC01CD8	/* DMA Channel 11 Y Count Register						*/
-#define DMA11_Y_MODIFY			0xFFC01CDC	/* DMA Channel 11 Y Modify Register						*/
-#define DMA11_CURR_DESC_PTR		0xFFC01CE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
-#define DMA11_CURR_ADDR			0xFFC01CE4	/* DMA Channel 11 Current Address Register				*/
-#define DMA11_IRQ_STATUS		0xFFC01CE8	/* DMA Channel 11 Interrupt/Status Register				*/
-#define DMA11_PERIPHERAL_MAP	0xFFC01CEC	/* DMA Channel 11 Peripheral Map Register				*/
-#define DMA11_CURR_X_COUNT		0xFFC01CF0	/* DMA Channel 11 Current X Count Register				*/
-#define DMA11_CURR_Y_COUNT		0xFFC01CF8	/* DMA Channel 11 Current Y Count Register				*/
-
-#define DMA12_NEXT_DESC_PTR		0xFFC01D00	/* DMA Channel 12 Next Descriptor Pointer Register		*/
-#define DMA12_START_ADDR		0xFFC01D04	/* DMA Channel 12 Start Address Register				*/
-#define DMA12_CONFIG			0xFFC01D08	/* DMA Channel 12 Configuration Register				*/
-#define DMA12_X_COUNT			0xFFC01D10	/* DMA Channel 12 X Count Register						*/
-#define DMA12_X_MODIFY			0xFFC01D14	/* DMA Channel 12 X Modify Register						*/
-#define DMA12_Y_COUNT			0xFFC01D18	/* DMA Channel 12 Y Count Register						*/
-#define DMA12_Y_MODIFY			0xFFC01D1C	/* DMA Channel 12 Y Modify Register						*/
-#define DMA12_CURR_DESC_PTR		0xFFC01D20	/* DMA Channel 12 Current Descriptor Pointer Register	*/
-#define DMA12_CURR_ADDR			0xFFC01D24	/* DMA Channel 12 Current Address Register				*/
-#define DMA12_IRQ_STATUS		0xFFC01D28	/* DMA Channel 12 Interrupt/Status Register				*/
-#define DMA12_PERIPHERAL_MAP	0xFFC01D2C	/* DMA Channel 12 Peripheral Map Register				*/
-#define DMA12_CURR_X_COUNT		0xFFC01D30	/* DMA Channel 12 Current X Count Register				*/
-#define DMA12_CURR_Y_COUNT		0xFFC01D38	/* DMA Channel 12 Current Y Count Register				*/
-
-#define DMA13_NEXT_DESC_PTR		0xFFC01D40	/* DMA Channel 13 Next Descriptor Pointer Register		*/
-#define DMA13_START_ADDR		0xFFC01D44	/* DMA Channel 13 Start Address Register				*/
-#define DMA13_CONFIG			0xFFC01D48	/* DMA Channel 13 Configuration Register				*/
-#define DMA13_X_COUNT			0xFFC01D50	/* DMA Channel 13 X Count Register						*/
-#define DMA13_X_MODIFY			0xFFC01D54	/* DMA Channel 13 X Modify Register						*/
-#define DMA13_Y_COUNT			0xFFC01D58	/* DMA Channel 13 Y Count Register						*/
-#define DMA13_Y_MODIFY			0xFFC01D5C	/* DMA Channel 13 Y Modify Register						*/
-#define DMA13_CURR_DESC_PTR		0xFFC01D60	/* DMA Channel 13 Current Descriptor Pointer Register	*/
-#define DMA13_CURR_ADDR			0xFFC01D64	/* DMA Channel 13 Current Address Register				*/
-#define DMA13_IRQ_STATUS		0xFFC01D68	/* DMA Channel 13 Interrupt/Status Register				*/
-#define DMA13_PERIPHERAL_MAP	0xFFC01D6C	/* DMA Channel 13 Peripheral Map Register				*/
-#define DMA13_CURR_X_COUNT		0xFFC01D70	/* DMA Channel 13 Current X Count Register				*/
-#define DMA13_CURR_Y_COUNT		0xFFC01D78	/* DMA Channel 13 Current Y Count Register				*/
-
-#define DMA14_NEXT_DESC_PTR		0xFFC01D80	/* DMA Channel 14 Next Descriptor Pointer Register		*/
-#define DMA14_START_ADDR		0xFFC01D84	/* DMA Channel 14 Start Address Register				*/
-#define DMA14_CONFIG			0xFFC01D88	/* DMA Channel 14 Configuration Register				*/
-#define DMA14_X_COUNT			0xFFC01D90	/* DMA Channel 14 X Count Register						*/
-#define DMA14_X_MODIFY			0xFFC01D94	/* DMA Channel 14 X Modify Register						*/
-#define DMA14_Y_COUNT			0xFFC01D98	/* DMA Channel 14 Y Count Register						*/
-#define DMA14_Y_MODIFY			0xFFC01D9C	/* DMA Channel 14 Y Modify Register						*/
-#define DMA14_CURR_DESC_PTR		0xFFC01DA0	/* DMA Channel 14 Current Descriptor Pointer Register	*/
-#define DMA14_CURR_ADDR			0xFFC01DA4	/* DMA Channel 14 Current Address Register				*/
-#define DMA14_IRQ_STATUS		0xFFC01DA8	/* DMA Channel 14 Interrupt/Status Register				*/
-#define DMA14_PERIPHERAL_MAP	0xFFC01DAC	/* DMA Channel 14 Peripheral Map Register				*/
-#define DMA14_CURR_X_COUNT		0xFFC01DB0	/* DMA Channel 14 Current X Count Register				*/
-#define DMA14_CURR_Y_COUNT		0xFFC01DB8	/* DMA Channel 14 Current Y Count Register				*/
-
-#define DMA15_NEXT_DESC_PTR		0xFFC01DC0	/* DMA Channel 15 Next Descriptor Pointer Register		*/
-#define DMA15_START_ADDR		0xFFC01DC4	/* DMA Channel 15 Start Address Register				*/
-#define DMA15_CONFIG			0xFFC01DC8	/* DMA Channel 15 Configuration Register				*/
-#define DMA15_X_COUNT			0xFFC01DD0	/* DMA Channel 15 X Count Register						*/
-#define DMA15_X_MODIFY			0xFFC01DD4	/* DMA Channel 15 X Modify Register						*/
-#define DMA15_Y_COUNT			0xFFC01DD8	/* DMA Channel 15 Y Count Register						*/
-#define DMA15_Y_MODIFY			0xFFC01DDC	/* DMA Channel 15 Y Modify Register						*/
-#define DMA15_CURR_DESC_PTR		0xFFC01DE0	/* DMA Channel 15 Current Descriptor Pointer Register	*/
-#define DMA15_CURR_ADDR			0xFFC01DE4	/* DMA Channel 15 Current Address Register				*/
-#define DMA15_IRQ_STATUS		0xFFC01DE8	/* DMA Channel 15 Interrupt/Status Register				*/
-#define DMA15_PERIPHERAL_MAP	0xFFC01DEC	/* DMA Channel 15 Peripheral Map Register				*/
-#define DMA15_CURR_X_COUNT		0xFFC01DF0	/* DMA Channel 15 Current X Count Register				*/
-#define DMA15_CURR_Y_COUNT		0xFFC01DF8	/* DMA Channel 15 Current Y Count Register				*/
-
-#define DMA16_NEXT_DESC_PTR		0xFFC01E00	/* DMA Channel 16 Next Descriptor Pointer Register		*/
-#define DMA16_START_ADDR		0xFFC01E04	/* DMA Channel 16 Start Address Register				*/
-#define DMA16_CONFIG			0xFFC01E08	/* DMA Channel 16 Configuration Register				*/
-#define DMA16_X_COUNT			0xFFC01E10	/* DMA Channel 16 X Count Register						*/
-#define DMA16_X_MODIFY			0xFFC01E14	/* DMA Channel 16 X Modify Register						*/
-#define DMA16_Y_COUNT			0xFFC01E18	/* DMA Channel 16 Y Count Register						*/
-#define DMA16_Y_MODIFY			0xFFC01E1C	/* DMA Channel 16 Y Modify Register						*/
-#define DMA16_CURR_DESC_PTR		0xFFC01E20	/* DMA Channel 16 Current Descriptor Pointer Register	*/
-#define DMA16_CURR_ADDR			0xFFC01E24	/* DMA Channel 16 Current Address Register				*/
-#define DMA16_IRQ_STATUS		0xFFC01E28	/* DMA Channel 16 Interrupt/Status Register				*/
-#define DMA16_PERIPHERAL_MAP	0xFFC01E2C	/* DMA Channel 16 Peripheral Map Register				*/
-#define DMA16_CURR_X_COUNT		0xFFC01E30	/* DMA Channel 16 Current X Count Register				*/
-#define DMA16_CURR_Y_COUNT		0xFFC01E38	/* DMA Channel 16 Current Y Count Register				*/
-
-#define DMA17_NEXT_DESC_PTR		0xFFC01E40	/* DMA Channel 17 Next Descriptor Pointer Register		*/
-#define DMA17_START_ADDR		0xFFC01E44	/* DMA Channel 17 Start Address Register				*/
-#define DMA17_CONFIG			0xFFC01E48	/* DMA Channel 17 Configuration Register				*/
-#define DMA17_X_COUNT			0xFFC01E50	/* DMA Channel 17 X Count Register						*/
-#define DMA17_X_MODIFY			0xFFC01E54	/* DMA Channel 17 X Modify Register						*/
-#define DMA17_Y_COUNT			0xFFC01E58	/* DMA Channel 17 Y Count Register						*/
-#define DMA17_Y_MODIFY			0xFFC01E5C	/* DMA Channel 17 Y Modify Register						*/
-#define DMA17_CURR_DESC_PTR		0xFFC01E60	/* DMA Channel 17 Current Descriptor Pointer Register	*/
-#define DMA17_CURR_ADDR			0xFFC01E64	/* DMA Channel 17 Current Address Register				*/
-#define DMA17_IRQ_STATUS		0xFFC01E68	/* DMA Channel 17 Interrupt/Status Register				*/
-#define DMA17_PERIPHERAL_MAP	0xFFC01E6C	/* DMA Channel 17 Peripheral Map Register				*/
-#define DMA17_CURR_X_COUNT		0xFFC01E70	/* DMA Channel 17 Current X Count Register				*/
-#define DMA17_CURR_Y_COUNT		0xFFC01E78	/* DMA Channel 17 Current Y Count Register				*/
-
-#define DMA18_NEXT_DESC_PTR		0xFFC01E80	/* DMA Channel 18 Next Descriptor Pointer Register		*/
-#define DMA18_START_ADDR		0xFFC01E84	/* DMA Channel 18 Start Address Register				*/
-#define DMA18_CONFIG			0xFFC01E88	/* DMA Channel 18 Configuration Register				*/
-#define DMA18_X_COUNT			0xFFC01E90	/* DMA Channel 18 X Count Register						*/
-#define DMA18_X_MODIFY			0xFFC01E94	/* DMA Channel 18 X Modify Register						*/
-#define DMA18_Y_COUNT			0xFFC01E98	/* DMA Channel 18 Y Count Register						*/
-#define DMA18_Y_MODIFY			0xFFC01E9C	/* DMA Channel 18 Y Modify Register						*/
-#define DMA18_CURR_DESC_PTR		0xFFC01EA0	/* DMA Channel 18 Current Descriptor Pointer Register	*/
-#define DMA18_CURR_ADDR			0xFFC01EA4	/* DMA Channel 18 Current Address Register				*/
-#define DMA18_IRQ_STATUS		0xFFC01EA8	/* DMA Channel 18 Interrupt/Status Register				*/
-#define DMA18_PERIPHERAL_MAP	0xFFC01EAC	/* DMA Channel 18 Peripheral Map Register				*/
-#define DMA18_CURR_X_COUNT		0xFFC01EB0	/* DMA Channel 18 Current X Count Register				*/
-#define DMA18_CURR_Y_COUNT		0xFFC01EB8	/* DMA Channel 18 Current Y Count Register				*/
-
-#define DMA19_NEXT_DESC_PTR		0xFFC01EC0	/* DMA Channel 19 Next Descriptor Pointer Register		*/
-#define DMA19_START_ADDR		0xFFC01EC4	/* DMA Channel 19 Start Address Register				*/
-#define DMA19_CONFIG			0xFFC01EC8	/* DMA Channel 19 Configuration Register				*/
-#define DMA19_X_COUNT			0xFFC01ED0	/* DMA Channel 19 X Count Register						*/
-#define DMA19_X_MODIFY			0xFFC01ED4	/* DMA Channel 19 X Modify Register						*/
-#define DMA19_Y_COUNT			0xFFC01ED8	/* DMA Channel 19 Y Count Register						*/
-#define DMA19_Y_MODIFY			0xFFC01EDC	/* DMA Channel 19 Y Modify Register						*/
-#define DMA19_CURR_DESC_PTR		0xFFC01EE0	/* DMA Channel 19 Current Descriptor Pointer Register	*/
-#define DMA19_CURR_ADDR			0xFFC01EE4	/* DMA Channel 19 Current Address Register				*/
-#define DMA19_IRQ_STATUS		0xFFC01EE8	/* DMA Channel 19 Interrupt/Status Register				*/
-#define DMA19_PERIPHERAL_MAP	0xFFC01EEC	/* DMA Channel 19 Peripheral Map Register				*/
-#define DMA19_CURR_X_COUNT		0xFFC01EF0	/* DMA Channel 19 Current X Count Register				*/
-#define DMA19_CURR_Y_COUNT		0xFFC01EF8	/* DMA Channel 19 Current Y Count Register				*/
-
-#define MDMA1_D0_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA1_D0_START_ADDR		0xFFC01F04	/* MemDMA1 Stream 0 Destination Start Address Register				*/
-#define MDMA1_D0_CONFIG			0xFFC01F08	/* MemDMA1 Stream 0 Destination Configuration Register				*/
-#define MDMA1_D0_X_COUNT		0xFFC01F10	/* MemDMA1 Stream 0 Destination X Count Register						*/
-#define MDMA1_D0_X_MODIFY		0xFFC01F14	/* MemDMA1 Stream 0 Destination X Modify Register					*/
-#define MDMA1_D0_Y_COUNT		0xFFC01F18	/* MemDMA1 Stream 0 Destination Y Count Register						*/
-#define MDMA1_D0_Y_MODIFY		0xFFC01F1C	/* MemDMA1 Stream 0 Destination Y Modify Register					*/
-#define MDMA1_D0_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA1_D0_CURR_ADDR		0xFFC01F24	/* MemDMA1 Stream 0 Destination Current Address Register				*/
-#define MDMA1_D0_IRQ_STATUS		0xFFC01F28	/* MemDMA1 Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA1_D0_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination Peripheral Map Register				*/
-#define MDMA1_D0_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Destination Current X Count Register				*/
-#define MDMA1_D0_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA1_S0_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next Descriptor Pointer Register			*/
-#define MDMA1_S0_START_ADDR		0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address Register					*/
-#define MDMA1_S0_CONFIG			0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration Register					*/
-#define MDMA1_S0_X_COUNT		0xFFC01F50	/* MemDMA1 Stream 0 Source X Count Register							*/
-#define MDMA1_S0_X_MODIFY		0xFFC01F54	/* MemDMA1 Stream 0 Source X Modify Register							*/
-#define MDMA1_S0_Y_COUNT		0xFFC01F58	/* MemDMA1 Stream 0 Source Y Count Register							*/
-#define MDMA1_S0_Y_MODIFY		0xFFC01F5C	/* MemDMA1 Stream 0 Source Y Modify Register							*/
-#define MDMA1_S0_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Pointer Register		*/
-#define MDMA1_S0_CURR_ADDR		0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address Register					*/
-#define MDMA1_S0_IRQ_STATUS		0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status Register					*/
-#define MDMA1_S0_PERIPHERAL_MAP	0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map Register					*/
-#define MDMA1_S0_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current X Count Register					*/
-#define MDMA1_S0_CURR_Y_COUNT	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Y Count Register					*/
-
-#define MDMA1_D1_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA1_D1_START_ADDR		0xFFC01F84	/* MemDMA1 Stream 1 Destination Start Address Register				*/
-#define MDMA1_D1_CONFIG			0xFFC01F88	/* MemDMA1 Stream 1 Destination Configuration Register				*/
-#define MDMA1_D1_X_COUNT		0xFFC01F90	/* MemDMA1 Stream 1 Destination X Count Register						*/
-#define MDMA1_D1_X_MODIFY		0xFFC01F94	/* MemDMA1 Stream 1 Destination X Modify Register					*/
-#define MDMA1_D1_Y_COUNT		0xFFC01F98	/* MemDMA1 Stream 1 Destination Y Count Register						*/
-#define MDMA1_D1_Y_MODIFY		0xFFC01F9C	/* MemDMA1 Stream 1 Destination Y Modify Register					*/
-#define MDMA1_D1_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA1_D1_CURR_ADDR		0xFFC01FA4	/* MemDMA1 Stream 1 Destination Current Address Register				*/
-#define MDMA1_D1_IRQ_STATUS		0xFFC01FA8	/* MemDMA1 Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA1_D1_PERIPHERAL_MAP	0xFFC01FAC	/* MemDMA1 Stream 1 Destination Peripheral Map Register				*/
-#define MDMA1_D1_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Destination Current X Count Register				*/
-#define MDMA1_D1_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA1_S1_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next Descriptor Pointer Register			*/
-#define MDMA1_S1_START_ADDR		0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address Register					*/
-#define MDMA1_S1_CONFIG			0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration Register					*/
-#define MDMA1_S1_X_COUNT		0xFFC01FD0	/* MemDMA1 Stream 1 Source X Count Register							*/
-#define MDMA1_S1_X_MODIFY		0xFFC01FD4	/* MemDMA1 Stream 1 Source X Modify Register							*/
-#define MDMA1_S1_Y_COUNT		0xFFC01FD8	/* MemDMA1 Stream 1 Source Y Count Register							*/
-#define MDMA1_S1_Y_MODIFY		0xFFC01FDC	/* MemDMA1 Stream 1 Source Y Modify Register							*/
-#define MDMA1_S1_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Pointer Register		*/
-#define MDMA1_S1_CURR_ADDR		0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address Register					*/
-#define MDMA1_S1_IRQ_STATUS		0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status Register					*/
-#define MDMA1_S1_PERIPHERAL_MAP	0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map Register					*/
-#define MDMA1_S1_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current X Count Register					*/
-#define MDMA1_S1_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Y Count Register					*/
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define UART1_THR			0xFFC02000	/* Transmit Holding register			*/
-#define UART1_RBR			0xFFC02000	/* Receive Buffer register				*/
-#define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)				*/
-#define UART1_IER			0xFFC02004	/* Interrupt Enable Register			*/
-#define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)			*/
-#define UART1_IIR			0xFFC02008	/* Interrupt Identification Register	*/
-#define UART1_LCR			0xFFC0200C	/* Line Control Register				*/
-#define UART1_MCR			0xFFC02010	/* Modem Control Register				*/
-#define UART1_LSR			0xFFC02014	/* Line Status Register					*/
-#define UART1_SCR			0xFFC0201C	/* SCR Scratch Register					*/
-#define UART1_GCTL			0xFFC02024	/* Global Control Register				*/
-
-
-/* UART2 Controller		(0xFFC02100 - 0xFFC021FF)								*/
-#define UART2_THR			0xFFC02100	/* Transmit Holding register			*/
-#define UART2_RBR			0xFFC02100	/* Receive Buffer register				*/
-#define UART2_DLL			0xFFC02100	/* Divisor Latch (Low-Byte)				*/
-#define UART2_IER			0xFFC02104	/* Interrupt Enable Register			*/
-#define UART2_DLH			0xFFC02104	/* Divisor Latch (High-Byte)			*/
-#define UART2_IIR			0xFFC02108	/* Interrupt Identification Register	*/
-#define UART2_LCR			0xFFC0210C	/* Line Control Register				*/
-#define UART2_MCR			0xFFC02110	/* Modem Control Register				*/
-#define UART2_LSR			0xFFC02114	/* Line Status Register					*/
-#define UART2_SCR			0xFFC0211C	/* SCR Scratch Register					*/
-#define UART2_GCTL			0xFFC02124	/* Global Control Register				*/
-
-
-/* Two-Wire Interface 1	(0xFFC02200 - 0xFFC022FF)										*/
-#define TWI1_CLKDIV			0xFFC02200	/* Serial Clock Divider Register				*/
-#define TWI1_CONTROL		0xFFC02204	/* TWI1 Master Internal Time Reference Register	*/
-#define TWI1_SLAVE_CTRL		0xFFC02208	/* Slave Mode Control Register					*/
-#define TWI1_SLAVE_STAT		0xFFC0220C	/* Slave Mode Status Register					*/
-#define TWI1_SLAVE_ADDR		0xFFC02210	/* Slave Mode Address Register					*/
-#define TWI1_MASTER_CTRL	0xFFC02214	/* Master Mode Control Register					*/
-#define TWI1_MASTER_STAT	0xFFC02218	/* Master Mode Status Register					*/
-#define TWI1_MASTER_ADDR	0xFFC0221C	/* Master Mode Address Register					*/
-#define TWI1_INT_STAT		0xFFC02220	/* TWI1 Master Interrupt Register				*/
-#define TWI1_INT_MASK		0xFFC02224	/* TWI1 Master Interrupt Mask Register			*/
-#define TWI1_FIFO_CTRL		0xFFC02228	/* FIFO Control Register						*/
-#define TWI1_FIFO_STAT		0xFFC0222C	/* FIFO Status Register							*/
-#define TWI1_XMT_DATA8		0xFFC02280	/* FIFO Transmit Data Single Byte Register		*/
-#define TWI1_XMT_DATA16		0xFFC02284	/* FIFO Transmit Data Double Byte Register		*/
-#define TWI1_RCV_DATA8		0xFFC02288	/* FIFO Receive Data Single Byte Register		*/
-#define TWI1_RCV_DATA16		0xFFC0228C	/* FIFO Receive Data Double Byte Register		*/
-
-
-/* SPI1 Controller		(0xFFC02300 - 0xFFC023FF)								*/
-#define SPI1_CTL			0xFFC02300  /* SPI1 Control Register				*/
-#define SPI1_FLG			0xFFC02304  /* SPI1 Flag register					*/
-#define SPI1_STAT			0xFFC02308  /* SPI1 Status register					*/
-#define SPI1_TDBR			0xFFC0230C  /* SPI1 Transmit Data Buffer Register	*/
-#define SPI1_RDBR			0xFFC02310  /* SPI1 Receive Data Buffer Register	*/
-#define SPI1_BAUD			0xFFC02314  /* SPI1 Baud rate Register				*/
-#define SPI1_SHADOW			0xFFC02318  /* SPI1_RDBR Shadow Register			*/
-
-
-/* SPI2 Controller		(0xFFC02400 - 0xFFC024FF)								*/
-#define SPI2_CTL			0xFFC02400  /* SPI2 Control Register				*/
-#define SPI2_FLG			0xFFC02404  /* SPI2 Flag register					*/
-#define SPI2_STAT			0xFFC02408  /* SPI2 Status register					*/
-#define SPI2_TDBR			0xFFC0240C  /* SPI2 Transmit Data Buffer Register	*/
-#define SPI2_RDBR			0xFFC02410  /* SPI2 Receive Data Buffer Register	*/
-#define SPI2_BAUD			0xFFC02414  /* SPI2 Baud rate Register				*/
-#define SPI2_SHADOW			0xFFC02418  /* SPI2_RDBR Shadow Register			*/
-
-
-/* SPORT2 Controller		(0xFFC02500 - 0xFFC025FF)										*/
-#define SPORT2_TCR1			0xFFC02500	/* SPORT2 Transmit Configuration 1 Register			*/
-#define SPORT2_TCR2			0xFFC02504	/* SPORT2 Transmit Configuration 2 Register			*/
-#define SPORT2_TCLKDIV		0xFFC02508	/* SPORT2 Transmit Clock Divider					*/
-#define SPORT2_TFSDIV		0xFFC0250C	/* SPORT2 Transmit Frame Sync Divider				*/
-#define SPORT2_TX			0xFFC02510	/* SPORT2 TX Data Register							*/
-#define SPORT2_RX			0xFFC02518	/* SPORT2 RX Data Register							*/
-#define SPORT2_RCR1			0xFFC02520	/* SPORT2 Transmit Configuration 1 Register			*/
-#define SPORT2_RCR2			0xFFC02524	/* SPORT2 Transmit Configuration 2 Register			*/
-#define SPORT2_RCLKDIV		0xFFC02528	/* SPORT2 Receive Clock Divider						*/
-#define SPORT2_RFSDIV		0xFFC0252C	/* SPORT2 Receive Frame Sync Divider				*/
-#define SPORT2_STAT			0xFFC02530	/* SPORT2 Status Register							*/
-#define SPORT2_CHNL			0xFFC02534	/* SPORT2 Current Channel Register					*/
-#define SPORT2_MCMC1		0xFFC02538	/* SPORT2 Multi-Channel Configuration Register 1	*/
-#define SPORT2_MCMC2		0xFFC0253C	/* SPORT2 Multi-Channel Configuration Register 2	*/
-#define SPORT2_MTCS0		0xFFC02540	/* SPORT2 Multi-Channel Transmit Select Register 0	*/
-#define SPORT2_MTCS1		0xFFC02544	/* SPORT2 Multi-Channel Transmit Select Register 1	*/
-#define SPORT2_MTCS2		0xFFC02548	/* SPORT2 Multi-Channel Transmit Select Register 2	*/
-#define SPORT2_MTCS3		0xFFC0254C	/* SPORT2 Multi-Channel Transmit Select Register 3	*/
-#define SPORT2_MRCS0		0xFFC02550	/* SPORT2 Multi-Channel Receive Select Register 0	*/
-#define SPORT2_MRCS1		0xFFC02554	/* SPORT2 Multi-Channel Receive Select Register 1	*/
-#define SPORT2_MRCS2		0xFFC02558	/* SPORT2 Multi-Channel Receive Select Register 2	*/
-#define SPORT2_MRCS3		0xFFC0255C	/* SPORT2 Multi-Channel Receive Select Register 3	*/
-
-
-/* SPORT3 Controller		(0xFFC02600 - 0xFFC026FF)										*/
-#define SPORT3_TCR1			0xFFC02600	/* SPORT3 Transmit Configuration 1 Register			*/
-#define SPORT3_TCR2			0xFFC02604	/* SPORT3 Transmit Configuration 2 Register			*/
-#define SPORT3_TCLKDIV		0xFFC02608	/* SPORT3 Transmit Clock Divider					*/
-#define SPORT3_TFSDIV		0xFFC0260C	/* SPORT3 Transmit Frame Sync Divider				*/
-#define SPORT3_TX			0xFFC02610	/* SPORT3 TX Data Register							*/
-#define SPORT3_RX			0xFFC02618	/* SPORT3 RX Data Register							*/
-#define SPORT3_RCR1			0xFFC02620	/* SPORT3 Transmit Configuration 1 Register			*/
-#define SPORT3_RCR2			0xFFC02624	/* SPORT3 Transmit Configuration 2 Register			*/
-#define SPORT3_RCLKDIV		0xFFC02628	/* SPORT3 Receive Clock Divider						*/
-#define SPORT3_RFSDIV		0xFFC0262C	/* SPORT3 Receive Frame Sync Divider				*/
-#define SPORT3_STAT			0xFFC02630	/* SPORT3 Status Register							*/
-#define SPORT3_CHNL			0xFFC02634	/* SPORT3 Current Channel Register					*/
-#define SPORT3_MCMC1		0xFFC02638	/* SPORT3 Multi-Channel Configuration Register 1	*/
-#define SPORT3_MCMC2		0xFFC0263C	/* SPORT3 Multi-Channel Configuration Register 2	*/
-#define SPORT3_MTCS0		0xFFC02640	/* SPORT3 Multi-Channel Transmit Select Register 0	*/
-#define SPORT3_MTCS1		0xFFC02644	/* SPORT3 Multi-Channel Transmit Select Register 1	*/
-#define SPORT3_MTCS2		0xFFC02648	/* SPORT3 Multi-Channel Transmit Select Register 2	*/
-#define SPORT3_MTCS3		0xFFC0264C	/* SPORT3 Multi-Channel Transmit Select Register 3	*/
-#define SPORT3_MRCS0		0xFFC02650	/* SPORT3 Multi-Channel Receive Select Register 0	*/
-#define SPORT3_MRCS1		0xFFC02654	/* SPORT3 Multi-Channel Receive Select Register 1	*/
-#define SPORT3_MRCS2		0xFFC02658	/* SPORT3 Multi-Channel Receive Select Register 2	*/
-#define SPORT3_MRCS3		0xFFC0265C	/* SPORT3 Multi-Channel Receive Select Register 3	*/
-
-
-/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)											*/
-/* For Mailboxes 0-15																		*/
-#define CAN_MC1				0xFFC02A00	/* Mailbox config reg 1								*/
-#define CAN_MD1				0xFFC02A04	/* Mailbox direction reg 1							*/
-#define CAN_TRS1			0xFFC02A08	/* Transmit Request Set reg 1						*/
-#define CAN_TRR1			0xFFC02A0C	/* Transmit Request Reset reg 1						*/
-#define CAN_TA1				0xFFC02A10	/* Transmit Acknowledge reg 1						*/
-#define CAN_AA1				0xFFC02A14	/* Transmit Abort Acknowledge reg 1					*/
-#define CAN_RMP1			0xFFC02A18	/* Receive Message Pending reg 1					*/
-#define CAN_RML1			0xFFC02A1C	/* Receive Message Lost reg 1						*/
-#define CAN_MBTIF1			0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1			*/
-#define CAN_MBRIF1			0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1			*/
-#define CAN_MBIM1			0xFFC02A28	/* Mailbox Interrupt Mask reg 1						*/
-#define CAN_RFH1			0xFFC02A2C	/* Remote Frame Handling reg 1						*/
-#define CAN_OPSS1			0xFFC02A30	/* Overwrite Protection Single Shot Xmission reg 1	*/
-
-/* For Mailboxes 16-31   																	*/
-#define CAN_MC2				0xFFC02A40	/* Mailbox config reg 2								*/
-#define CAN_MD2				0xFFC02A44	/* Mailbox direction reg 2							*/
-#define CAN_TRS2			0xFFC02A48	/* Transmit Request Set reg 2						*/
-#define CAN_TRR2			0xFFC02A4C	/* Transmit Request Reset reg 2						*/
-#define CAN_TA2				0xFFC02A50	/* Transmit Acknowledge reg 2						*/
-#define CAN_AA2				0xFFC02A54	/* Transmit Abort Acknowledge reg 2					*/
-#define CAN_RMP2			0xFFC02A58	/* Receive Message Pending reg 2					*/
-#define CAN_RML2			0xFFC02A5C	/* Receive Message Lost reg 2						*/
-#define CAN_MBTIF2			0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2			*/
-#define CAN_MBRIF2			0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2			*/
-#define CAN_MBIM2			0xFFC02A68	/* Mailbox Interrupt Mask reg 2						*/
-#define CAN_RFH2			0xFFC02A6C	/* Remote Frame Handling reg 2						*/
-#define CAN_OPSS2			0xFFC02A70	/* Overwrite Protection Single Shot Xmission reg 2	*/
-
-#define CAN_CLOCK			0xFFC02A80	/* Bit Timing Configuration register 0				*/
-#define CAN_TIMING			0xFFC02A84	/* Bit Timing Configuration register 1				*/
-#define CAN_DEBUG			0xFFC02A88	/* Debug Register									*/
-#define CAN_STATUS			0xFFC02A8C	/* Global Status Register							*/
-#define CAN_CEC				0xFFC02A90	/* Error Counter Register							*/
-#define CAN_GIS				0xFFC02A94	/* Global Interrupt Status Register					*/
-#define CAN_GIM				0xFFC02A98	/* Global Interrupt Mask Register					*/
-#define CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register					*/
-#define CAN_CONTROL			0xFFC02AA0	/* Master Control Register							*/
-#define CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register						*/
-#define CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature				*/
-#define CAN_EWR				0xFFC02AB0	/* Programmable Warning Level						*/
-#define CAN_ESR				0xFFC02AB4	/* Error Status Register							*/
-#define CAN_UCCNT			0xFFC02AC4	/* Universal Counter								*/
-#define CAN_UCRC			0xFFC02AC8	/* Universal Counter Reload/Capture Register			*/
-#define CAN_UCCNF			0xFFC02ACC	/* Universal Counter Configuration Register			*/
-
-/* Mailbox Acceptance Masks 												*/
-#define CAN_AM00L			0xFFC02B00	/* Mailbox 0 Low Acceptance Mask	*/
-#define CAN_AM00H			0xFFC02B04	/* Mailbox 0 High Acceptance Mask	*/
-#define CAN_AM01L			0xFFC02B08	/* Mailbox 1 Low Acceptance Mask	*/
-#define CAN_AM01H			0xFFC02B0C	/* Mailbox 1 High Acceptance Mask	*/
-#define CAN_AM02L			0xFFC02B10	/* Mailbox 2 Low Acceptance Mask 	*/
-#define CAN_AM02H			0xFFC02B14	/* Mailbox 2 High Acceptance Mask	*/
-#define CAN_AM03L			0xFFC02B18	/* Mailbox 3 Low Acceptance Mask 	*/
-#define CAN_AM03H			0xFFC02B1C	/* Mailbox 3 High Acceptance Mask	*/
-#define CAN_AM04L			0xFFC02B20	/* Mailbox 4 Low Acceptance Mask 	*/
-#define CAN_AM04H			0xFFC02B24	/* Mailbox 4 High Acceptance Mask	*/
-#define CAN_AM05L			0xFFC02B28	/* Mailbox 5 Low Acceptance Mask 	*/
-#define CAN_AM05H			0xFFC02B2C	/* Mailbox 5 High Acceptance Mask	*/
-#define CAN_AM06L			0xFFC02B30	/* Mailbox 6 Low Acceptance Mask 	*/
-#define CAN_AM06H			0xFFC02B34	/* Mailbox 6 High Acceptance Mask	*/
-#define CAN_AM07L			0xFFC02B38	/* Mailbox 7 Low Acceptance Mask 	*/
-#define CAN_AM07H			0xFFC02B3C	/* Mailbox 7 High Acceptance Mask	*/
-#define CAN_AM08L			0xFFC02B40	/* Mailbox 8 Low Acceptance Mask 	*/
-#define CAN_AM08H			0xFFC02B44	/* Mailbox 8 High Acceptance Mask	*/
-#define CAN_AM09L			0xFFC02B48	/* Mailbox 9 Low Acceptance Mask 	*/
-#define CAN_AM09H			0xFFC02B4C	/* Mailbox 9 High Acceptance Mask	*/
-#define CAN_AM10L			0xFFC02B50	/* Mailbox 10 Low Acceptance Mask 	*/
-#define CAN_AM10H			0xFFC02B54	/* Mailbox 10 High Acceptance Mask	*/
-#define CAN_AM11L			0xFFC02B58	/* Mailbox 11 Low Acceptance Mask 	*/
-#define CAN_AM11H			0xFFC02B5C	/* Mailbox 11 High Acceptance Mask	*/
-#define CAN_AM12L			0xFFC02B60	/* Mailbox 12 Low Acceptance Mask 	*/
-#define CAN_AM12H			0xFFC02B64	/* Mailbox 12 High Acceptance Mask	*/
-#define CAN_AM13L			0xFFC02B68	/* Mailbox 13 Low Acceptance Mask 	*/
-#define CAN_AM13H			0xFFC02B6C	/* Mailbox 13 High Acceptance Mask	*/
-#define CAN_AM14L			0xFFC02B70	/* Mailbox 14 Low Acceptance Mask 	*/
-#define CAN_AM14H			0xFFC02B74	/* Mailbox 14 High Acceptance Mask	*/
-#define CAN_AM15L			0xFFC02B78	/* Mailbox 15 Low Acceptance Mask 	*/
-#define CAN_AM15H			0xFFC02B7C	/* Mailbox 15 High Acceptance Mask	*/
-
-#define CAN_AM16L			0xFFC02B80	/* Mailbox 16 Low Acceptance Mask 	*/
-#define CAN_AM16H			0xFFC02B84	/* Mailbox 16 High Acceptance Mask	*/
-#define CAN_AM17L			0xFFC02B88	/* Mailbox 17 Low Acceptance Mask 	*/
-#define CAN_AM17H			0xFFC02B8C	/* Mailbox 17 High Acceptance Mask	*/
-#define CAN_AM18L			0xFFC02B90	/* Mailbox 18 Low Acceptance Mask 	*/
-#define CAN_AM18H			0xFFC02B94	/* Mailbox 18 High Acceptance Mask	*/
-#define CAN_AM19L			0xFFC02B98	/* Mailbox 19 Low Acceptance Mask 	*/
-#define CAN_AM19H			0xFFC02B9C	/* Mailbox 19 High Acceptance Mask	*/
-#define CAN_AM20L			0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask 	*/
-#define CAN_AM20H			0xFFC02BA4	/* Mailbox 20 High Acceptance Mask	*/
-#define CAN_AM21L			0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask 	*/
-#define CAN_AM21H			0xFFC02BAC	/* Mailbox 21 High Acceptance Mask	*/
-#define CAN_AM22L			0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask 	*/
-#define CAN_AM22H			0xFFC02BB4	/* Mailbox 22 High Acceptance Mask	*/
-#define CAN_AM23L			0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask 	*/
-#define CAN_AM23H			0xFFC02BBC	/* Mailbox 23 High Acceptance Mask	*/
-#define CAN_AM24L			0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask 	*/
-#define CAN_AM24H			0xFFC02BC4	/* Mailbox 24 High Acceptance Mask	*/
-#define CAN_AM25L			0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask 	*/
-#define CAN_AM25H			0xFFC02BCC	/* Mailbox 25 High Acceptance Mask	*/
-#define CAN_AM26L			0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask 	*/
-#define CAN_AM26H			0xFFC02BD4	/* Mailbox 26 High Acceptance Mask	*/
-#define CAN_AM27L			0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask 	*/
-#define CAN_AM27H			0xFFC02BDC	/* Mailbox 27 High Acceptance Mask	*/
-#define CAN_AM28L			0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask 	*/
-#define CAN_AM28H			0xFFC02BE4	/* Mailbox 28 High Acceptance Mask	*/
-#define CAN_AM29L			0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask 	*/
-#define CAN_AM29H			0xFFC02BEC	/* Mailbox 29 High Acceptance Mask	*/
-#define CAN_AM30L			0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask 	*/
-#define CAN_AM30H			0xFFC02BF4	/* Mailbox 30 High Acceptance Mask	*/
-#define CAN_AM31L			0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask 	*/
-#define CAN_AM31H			0xFFC02BFC	/* Mailbox 31 High Acceptance Mask	*/
-
-/* CAN Acceptance Mask Macros				*/
-#define CAN_AM_L(x)			(CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)			(CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers																*/
-#define CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0] Register	*/
-#define CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register	*/
-#define CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register	*/
-#define CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register	*/
-#define CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register		*/
-#define CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp Value Register		*/
-#define CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier Low Register		*/
-#define CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier High Register		*/
-
-#define CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0] Register	*/
-#define CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register	*/
-#define CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register	*/
-#define CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register	*/
-#define CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register		*/
-#define CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp Value Register		*/
-#define CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier Low Register		*/
-#define CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier High Register		*/
-
-#define CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0] Register	*/
-#define CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register	*/
-#define CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register	*/
-#define CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register	*/
-#define CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register		*/
-#define CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp Value Register		*/
-#define CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier Low Register		*/
-#define CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier High Register		*/
-
-#define CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0] Register	*/
-#define CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register	*/
-#define CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register	*/
-#define CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register	*/
-#define CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register		*/
-#define CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp Value Register		*/
-#define CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier Low Register		*/
-#define CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier High Register		*/
-
-#define CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0] Register	*/
-#define CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register	*/
-#define CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register	*/
-#define CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register	*/
-#define CAN_MB04_LENGTH		0xFFC02C90	/* Mailbox 4 Data Length Code Register		*/
-#define CAN_MB04_TIMESTAMP	0xFFC02C94	/* Mailbox 4 Time Stamp Value Register		*/
-#define CAN_MB04_ID0		0xFFC02C98	/* Mailbox 4 Identifier Low Register		*/
-#define CAN_MB04_ID1		0xFFC02C9C	/* Mailbox 4 Identifier High Register		*/
-
-#define CAN_MB05_DATA0		0xFFC02CA0	/* Mailbox 5 Data Word 0 [15:0] Register	*/
-#define CAN_MB05_DATA1		0xFFC02CA4	/* Mailbox 5 Data Word 1 [31:16] Register	*/
-#define CAN_MB05_DATA2		0xFFC02CA8	/* Mailbox 5 Data Word 2 [47:32] Register	*/
-#define CAN_MB05_DATA3		0xFFC02CAC	/* Mailbox 5 Data Word 3 [63:48] Register	*/
-#define CAN_MB05_LENGTH		0xFFC02CB0	/* Mailbox 5 Data Length Code Register		*/
-#define CAN_MB05_TIMESTAMP	0xFFC02CB4	/* Mailbox 5 Time Stamp Value Register		*/
-#define CAN_MB05_ID0		0xFFC02CB8	/* Mailbox 5 Identifier Low Register		*/
-#define CAN_MB05_ID1		0xFFC02CBC	/* Mailbox 5 Identifier High Register		*/
-
-#define CAN_MB06_DATA0		0xFFC02CC0	/* Mailbox 6 Data Word 0 [15:0] Register	*/
-#define CAN_MB06_DATA1		0xFFC02CC4	/* Mailbox 6 Data Word 1 [31:16] Register	*/
-#define CAN_MB06_DATA2		0xFFC02CC8	/* Mailbox 6 Data Word 2 [47:32] Register	*/
-#define CAN_MB06_DATA3		0xFFC02CCC	/* Mailbox 6 Data Word 3 [63:48] Register	*/
-#define CAN_MB06_LENGTH		0xFFC02CD0	/* Mailbox 6 Data Length Code Register		*/
-#define CAN_MB06_TIMESTAMP	0xFFC02CD4	/* Mailbox 6 Time Stamp Value Register		*/
-#define CAN_MB06_ID0		0xFFC02CD8	/* Mailbox 6 Identifier Low Register		*/
-#define CAN_MB06_ID1		0xFFC02CDC	/* Mailbox 6 Identifier High Register		*/
-
-#define CAN_MB07_DATA0		0xFFC02CE0	/* Mailbox 7 Data Word 0 [15:0] Register	*/
-#define CAN_MB07_DATA1		0xFFC02CE4	/* Mailbox 7 Data Word 1 [31:16] Register	*/
-#define CAN_MB07_DATA2		0xFFC02CE8	/* Mailbox 7 Data Word 2 [47:32] Register	*/
-#define CAN_MB07_DATA3		0xFFC02CEC	/* Mailbox 7 Data Word 3 [63:48] Register	*/
-#define CAN_MB07_LENGTH		0xFFC02CF0	/* Mailbox 7 Data Length Code Register		*/
-#define CAN_MB07_TIMESTAMP	0xFFC02CF4	/* Mailbox 7 Time Stamp Value Register		*/
-#define CAN_MB07_ID0		0xFFC02CF8	/* Mailbox 7 Identifier Low Register		*/
-#define CAN_MB07_ID1		0xFFC02CFC	/* Mailbox 7 Identifier High Register		*/
-
-#define CAN_MB08_DATA0		0xFFC02D00	/* Mailbox 8 Data Word 0 [15:0] Register	*/
-#define CAN_MB08_DATA1		0xFFC02D04	/* Mailbox 8 Data Word 1 [31:16] Register	*/
-#define CAN_MB08_DATA2		0xFFC02D08	/* Mailbox 8 Data Word 2 [47:32] Register	*/
-#define CAN_MB08_DATA3		0xFFC02D0C	/* Mailbox 8 Data Word 3 [63:48] Register	*/
-#define CAN_MB08_LENGTH		0xFFC02D10	/* Mailbox 8 Data Length Code Register		*/
-#define CAN_MB08_TIMESTAMP	0xFFC02D14	/* Mailbox 8 Time Stamp Value Register		*/
-#define CAN_MB08_ID0		0xFFC02D18	/* Mailbox 8 Identifier Low Register		*/
-#define CAN_MB08_ID1		0xFFC02D1C	/* Mailbox 8 Identifier High Register		*/
-
-#define CAN_MB09_DATA0		0xFFC02D20	/* Mailbox 9 Data Word 0 [15:0] Register	*/
-#define CAN_MB09_DATA1		0xFFC02D24	/* Mailbox 9 Data Word 1 [31:16] Register	*/
-#define CAN_MB09_DATA2		0xFFC02D28	/* Mailbox 9 Data Word 2 [47:32] Register	*/
-#define CAN_MB09_DATA3		0xFFC02D2C	/* Mailbox 9 Data Word 3 [63:48] Register	*/
-#define CAN_MB09_LENGTH		0xFFC02D30	/* Mailbox 9 Data Length Code Register		*/
-#define CAN_MB09_TIMESTAMP	0xFFC02D34	/* Mailbox 9 Time Stamp Value Register		*/
-#define CAN_MB09_ID0		0xFFC02D38	/* Mailbox 9 Identifier Low Register		*/
-#define CAN_MB09_ID1		0xFFC02D3C	/* Mailbox 9 Identifier High Register		*/
-
-#define CAN_MB10_DATA0		0xFFC02D40	/* Mailbox 10 Data Word 0 [15:0] Register	*/
-#define CAN_MB10_DATA1		0xFFC02D44	/* Mailbox 10 Data Word 1 [31:16] Register	*/
-#define CAN_MB10_DATA2		0xFFC02D48	/* Mailbox 10 Data Word 2 [47:32] Register	*/
-#define CAN_MB10_DATA3		0xFFC02D4C	/* Mailbox 10 Data Word 3 [63:48] Register	*/
-#define CAN_MB10_LENGTH		0xFFC02D50	/* Mailbox 10 Data Length Code Register		*/
-#define CAN_MB10_TIMESTAMP	0xFFC02D54	/* Mailbox 10 Time Stamp Value Register		*/
-#define CAN_MB10_ID0		0xFFC02D58	/* Mailbox 10 Identifier Low Register		*/
-#define CAN_MB10_ID1		0xFFC02D5C	/* Mailbox 10 Identifier High Register		*/
-
-#define CAN_MB11_DATA0		0xFFC02D60	/* Mailbox 11 Data Word 0 [15:0] Register	*/
-#define CAN_MB11_DATA1		0xFFC02D64	/* Mailbox 11 Data Word 1 [31:16] Register	*/
-#define CAN_MB11_DATA2		0xFFC02D68	/* Mailbox 11 Data Word 2 [47:32] Register	*/
-#define CAN_MB11_DATA3		0xFFC02D6C	/* Mailbox 11 Data Word 3 [63:48] Register	*/
-#define CAN_MB11_LENGTH		0xFFC02D70	/* Mailbox 11 Data Length Code Register		*/
-#define CAN_MB11_TIMESTAMP	0xFFC02D74	/* Mailbox 11 Time Stamp Value Register		*/
-#define CAN_MB11_ID0		0xFFC02D78	/* Mailbox 11 Identifier Low Register		*/
-#define CAN_MB11_ID1		0xFFC02D7C	/* Mailbox 11 Identifier High Register		*/
-
-#define CAN_MB12_DATA0		0xFFC02D80	/* Mailbox 12 Data Word 0 [15:0] Register	*/
-#define CAN_MB12_DATA1		0xFFC02D84	/* Mailbox 12 Data Word 1 [31:16] Register	*/
-#define CAN_MB12_DATA2		0xFFC02D88	/* Mailbox 12 Data Word 2 [47:32] Register	*/
-#define CAN_MB12_DATA3		0xFFC02D8C	/* Mailbox 12 Data Word 3 [63:48] Register	*/
-#define CAN_MB12_LENGTH		0xFFC02D90	/* Mailbox 12 Data Length Code Register		*/
-#define CAN_MB12_TIMESTAMP	0xFFC02D94	/* Mailbox 12 Time Stamp Value Register		*/
-#define CAN_MB12_ID0		0xFFC02D98	/* Mailbox 12 Identifier Low Register		*/
-#define CAN_MB12_ID1		0xFFC02D9C	/* Mailbox 12 Identifier High Register		*/
-
-#define CAN_MB13_DATA0		0xFFC02DA0	/* Mailbox 13 Data Word 0 [15:0] Register	*/
-#define CAN_MB13_DATA1		0xFFC02DA4	/* Mailbox 13 Data Word 1 [31:16] Register	*/
-#define CAN_MB13_DATA2		0xFFC02DA8	/* Mailbox 13 Data Word 2 [47:32] Register	*/
-#define CAN_MB13_DATA3		0xFFC02DAC	/* Mailbox 13 Data Word 3 [63:48] Register	*/
-#define CAN_MB13_LENGTH		0xFFC02DB0	/* Mailbox 13 Data Length Code Register		*/
-#define CAN_MB13_TIMESTAMP	0xFFC02DB4	/* Mailbox 13 Time Stamp Value Register		*/
-#define CAN_MB13_ID0		0xFFC02DB8	/* Mailbox 13 Identifier Low Register		*/
-#define CAN_MB13_ID1		0xFFC02DBC	/* Mailbox 13 Identifier High Register		*/
-
-#define CAN_MB14_DATA0		0xFFC02DC0	/* Mailbox 14 Data Word 0 [15:0] Register	*/
-#define CAN_MB14_DATA1		0xFFC02DC4	/* Mailbox 14 Data Word 1 [31:16] Register	*/
-#define CAN_MB14_DATA2		0xFFC02DC8	/* Mailbox 14 Data Word 2 [47:32] Register	*/
-#define CAN_MB14_DATA3		0xFFC02DCC	/* Mailbox 14 Data Word 3 [63:48] Register	*/
-#define CAN_MB14_LENGTH		0xFFC02DD0	/* Mailbox 14 Data Length Code Register		*/
-#define CAN_MB14_TIMESTAMP	0xFFC02DD4	/* Mailbox 14 Time Stamp Value Register		*/
-#define CAN_MB14_ID0		0xFFC02DD8	/* Mailbox 14 Identifier Low Register		*/
-#define CAN_MB14_ID1		0xFFC02DDC	/* Mailbox 14 Identifier High Register		*/
-
-#define CAN_MB15_DATA0		0xFFC02DE0	/* Mailbox 15 Data Word 0 [15:0] Register	*/
-#define CAN_MB15_DATA1		0xFFC02DE4	/* Mailbox 15 Data Word 1 [31:16] Register	*/
-#define CAN_MB15_DATA2		0xFFC02DE8	/* Mailbox 15 Data Word 2 [47:32] Register	*/
-#define CAN_MB15_DATA3		0xFFC02DEC	/* Mailbox 15 Data Word 3 [63:48] Register	*/
-#define CAN_MB15_LENGTH		0xFFC02DF0	/* Mailbox 15 Data Length Code Register		*/
-#define CAN_MB15_TIMESTAMP	0xFFC02DF4	/* Mailbox 15 Time Stamp Value Register		*/
-#define CAN_MB15_ID0		0xFFC02DF8	/* Mailbox 15 Identifier Low Register		*/
-#define CAN_MB15_ID1		0xFFC02DFC	/* Mailbox 15 Identifier High Register		*/
-
-#define CAN_MB16_DATA0		0xFFC02E00	/* Mailbox 16 Data Word 0 [15:0] Register	*/
-#define CAN_MB16_DATA1		0xFFC02E04	/* Mailbox 16 Data Word 1 [31:16] Register	*/
-#define CAN_MB16_DATA2		0xFFC02E08	/* Mailbox 16 Data Word 2 [47:32] Register	*/
-#define CAN_MB16_DATA3		0xFFC02E0C	/* Mailbox 16 Data Word 3 [63:48] Register	*/
-#define CAN_MB16_LENGTH		0xFFC02E10	/* Mailbox 16 Data Length Code Register		*/
-#define CAN_MB16_TIMESTAMP	0xFFC02E14	/* Mailbox 16 Time Stamp Value Register		*/
-#define CAN_MB16_ID0		0xFFC02E18	/* Mailbox 16 Identifier Low Register		*/
-#define CAN_MB16_ID1		0xFFC02E1C	/* Mailbox 16 Identifier High Register		*/
-
-#define CAN_MB17_DATA0		0xFFC02E20	/* Mailbox 17 Data Word 0 [15:0] Register	*/
-#define CAN_MB17_DATA1		0xFFC02E24	/* Mailbox 17 Data Word 1 [31:16] Register	*/
-#define CAN_MB17_DATA2		0xFFC02E28	/* Mailbox 17 Data Word 2 [47:32] Register	*/
-#define CAN_MB17_DATA3		0xFFC02E2C	/* Mailbox 17 Data Word 3 [63:48] Register	*/
-#define CAN_MB17_LENGTH		0xFFC02E30	/* Mailbox 17 Data Length Code Register		*/
-#define CAN_MB17_TIMESTAMP	0xFFC02E34	/* Mailbox 17 Time Stamp Value Register		*/
-#define CAN_MB17_ID0		0xFFC02E38	/* Mailbox 17 Identifier Low Register		*/
-#define CAN_MB17_ID1		0xFFC02E3C	/* Mailbox 17 Identifier High Register		*/
-
-#define CAN_MB18_DATA0		0xFFC02E40	/* Mailbox 18 Data Word 0 [15:0] Register	*/
-#define CAN_MB18_DATA1		0xFFC02E44	/* Mailbox 18 Data Word 1 [31:16] Register	*/
-#define CAN_MB18_DATA2		0xFFC02E48	/* Mailbox 18 Data Word 2 [47:32] Register	*/
-#define CAN_MB18_DATA3		0xFFC02E4C	/* Mailbox 18 Data Word 3 [63:48] Register	*/
-#define CAN_MB18_LENGTH		0xFFC02E50	/* Mailbox 18 Data Length Code Register		*/
-#define CAN_MB18_TIMESTAMP	0xFFC02E54	/* Mailbox 18 Time Stamp Value Register		*/
-#define CAN_MB18_ID0		0xFFC02E58	/* Mailbox 18 Identifier Low Register		*/
-#define CAN_MB18_ID1		0xFFC02E5C	/* Mailbox 18 Identifier High Register		*/
-
-#define CAN_MB19_DATA0		0xFFC02E60	/* Mailbox 19 Data Word 0 [15:0] Register	*/
-#define CAN_MB19_DATA1		0xFFC02E64	/* Mailbox 19 Data Word 1 [31:16] Register	*/
-#define CAN_MB19_DATA2		0xFFC02E68	/* Mailbox 19 Data Word 2 [47:32] Register	*/
-#define CAN_MB19_DATA3		0xFFC02E6C	/* Mailbox 19 Data Word 3 [63:48] Register	*/
-#define CAN_MB19_LENGTH		0xFFC02E70	/* Mailbox 19 Data Length Code Register		*/
-#define CAN_MB19_TIMESTAMP	0xFFC02E74	/* Mailbox 19 Time Stamp Value Register		*/
-#define CAN_MB19_ID0		0xFFC02E78	/* Mailbox 19 Identifier Low Register		*/
-#define CAN_MB19_ID1		0xFFC02E7C	/* Mailbox 19 Identifier High Register		*/
-
-#define CAN_MB20_DATA0		0xFFC02E80	/* Mailbox 20 Data Word 0 [15:0] Register	*/
-#define CAN_MB20_DATA1		0xFFC02E84	/* Mailbox 20 Data Word 1 [31:16] Register	*/
-#define CAN_MB20_DATA2		0xFFC02E88	/* Mailbox 20 Data Word 2 [47:32] Register	*/
-#define CAN_MB20_DATA3		0xFFC02E8C	/* Mailbox 20 Data Word 3 [63:48] Register	*/
-#define CAN_MB20_LENGTH		0xFFC02E90	/* Mailbox 20 Data Length Code Register		*/
-#define CAN_MB20_TIMESTAMP	0xFFC02E94	/* Mailbox 20 Time Stamp Value Register		*/
-#define CAN_MB20_ID0		0xFFC02E98	/* Mailbox 20 Identifier Low Register		*/
-#define CAN_MB20_ID1		0xFFC02E9C	/* Mailbox 20 Identifier High Register		*/
-
-#define CAN_MB21_DATA0		0xFFC02EA0	/* Mailbox 21 Data Word 0 [15:0] Register	*/
-#define CAN_MB21_DATA1		0xFFC02EA4	/* Mailbox 21 Data Word 1 [31:16] Register	*/
-#define CAN_MB21_DATA2		0xFFC02EA8	/* Mailbox 21 Data Word 2 [47:32] Register	*/
-#define CAN_MB21_DATA3		0xFFC02EAC	/* Mailbox 21 Data Word 3 [63:48] Register	*/
-#define CAN_MB21_LENGTH		0xFFC02EB0	/* Mailbox 21 Data Length Code Register		*/
-#define CAN_MB21_TIMESTAMP	0xFFC02EB4	/* Mailbox 21 Time Stamp Value Register		*/
-#define CAN_MB21_ID0		0xFFC02EB8	/* Mailbox 21 Identifier Low Register		*/
-#define CAN_MB21_ID1		0xFFC02EBC	/* Mailbox 21 Identifier High Register		*/
-
-#define CAN_MB22_DATA0		0xFFC02EC0	/* Mailbox 22 Data Word 0 [15:0] Register	*/
-#define CAN_MB22_DATA1		0xFFC02EC4	/* Mailbox 22 Data Word 1 [31:16] Register	*/
-#define CAN_MB22_DATA2		0xFFC02EC8	/* Mailbox 22 Data Word 2 [47:32] Register	*/
-#define CAN_MB22_DATA3		0xFFC02ECC	/* Mailbox 22 Data Word 3 [63:48] Register	*/
-#define CAN_MB22_LENGTH		0xFFC02ED0	/* Mailbox 22 Data Length Code Register		*/
-#define CAN_MB22_TIMESTAMP	0xFFC02ED4	/* Mailbox 22 Time Stamp Value Register		*/
-#define CAN_MB22_ID0		0xFFC02ED8	/* Mailbox 22 Identifier Low Register		*/
-#define CAN_MB22_ID1		0xFFC02EDC	/* Mailbox 22 Identifier High Register		*/
-
-#define CAN_MB23_DATA0		0xFFC02EE0	/* Mailbox 23 Data Word 0 [15:0] Register	*/
-#define CAN_MB23_DATA1		0xFFC02EE4	/* Mailbox 23 Data Word 1 [31:16] Register	*/
-#define CAN_MB23_DATA2		0xFFC02EE8	/* Mailbox 23 Data Word 2 [47:32] Register	*/
-#define CAN_MB23_DATA3		0xFFC02EEC	/* Mailbox 23 Data Word 3 [63:48] Register	*/
-#define CAN_MB23_LENGTH		0xFFC02EF0	/* Mailbox 23 Data Length Code Register		*/
-#define CAN_MB23_TIMESTAMP	0xFFC02EF4	/* Mailbox 23 Time Stamp Value Register		*/
-#define CAN_MB23_ID0		0xFFC02EF8	/* Mailbox 23 Identifier Low Register		*/
-#define CAN_MB23_ID1		0xFFC02EFC	/* Mailbox 23 Identifier High Register		*/
-
-#define CAN_MB24_DATA0		0xFFC02F00	/* Mailbox 24 Data Word 0 [15:0] Register	*/
-#define CAN_MB24_DATA1		0xFFC02F04	/* Mailbox 24 Data Word 1 [31:16] Register	*/
-#define CAN_MB24_DATA2		0xFFC02F08	/* Mailbox 24 Data Word 2 [47:32] Register	*/
-#define CAN_MB24_DATA3		0xFFC02F0C	/* Mailbox 24 Data Word 3 [63:48] Register	*/
-#define CAN_MB24_LENGTH		0xFFC02F10	/* Mailbox 24 Data Length Code Register		*/
-#define CAN_MB24_TIMESTAMP	0xFFC02F14	/* Mailbox 24 Time Stamp Value Register		*/
-#define CAN_MB24_ID0		0xFFC02F18	/* Mailbox 24 Identifier Low Register		*/
-#define CAN_MB24_ID1		0xFFC02F1C	/* Mailbox 24 Identifier High Register		*/
-
-#define CAN_MB25_DATA0		0xFFC02F20	/* Mailbox 25 Data Word 0 [15:0] Register	*/
-#define CAN_MB25_DATA1		0xFFC02F24	/* Mailbox 25 Data Word 1 [31:16] Register	*/
-#define CAN_MB25_DATA2		0xFFC02F28	/* Mailbox 25 Data Word 2 [47:32] Register	*/
-#define CAN_MB25_DATA3		0xFFC02F2C	/* Mailbox 25 Data Word 3 [63:48] Register	*/
-#define CAN_MB25_LENGTH		0xFFC02F30	/* Mailbox 25 Data Length Code Register		*/
-#define CAN_MB25_TIMESTAMP	0xFFC02F34	/* Mailbox 25 Time Stamp Value Register		*/
-#define CAN_MB25_ID0		0xFFC02F38	/* Mailbox 25 Identifier Low Register		*/
-#define CAN_MB25_ID1		0xFFC02F3C	/* Mailbox 25 Identifier High Register		*/
-
-#define CAN_MB26_DATA0		0xFFC02F40	/* Mailbox 26 Data Word 0 [15:0] Register	*/
-#define CAN_MB26_DATA1		0xFFC02F44	/* Mailbox 26 Data Word 1 [31:16] Register	*/
-#define CAN_MB26_DATA2		0xFFC02F48	/* Mailbox 26 Data Word 2 [47:32] Register	*/
-#define CAN_MB26_DATA3		0xFFC02F4C	/* Mailbox 26 Data Word 3 [63:48] Register	*/
-#define CAN_MB26_LENGTH		0xFFC02F50	/* Mailbox 26 Data Length Code Register		*/
-#define CAN_MB26_TIMESTAMP	0xFFC02F54	/* Mailbox 26 Time Stamp Value Register		*/
-#define CAN_MB26_ID0		0xFFC02F58	/* Mailbox 26 Identifier Low Register		*/
-#define CAN_MB26_ID1		0xFFC02F5C	/* Mailbox 26 Identifier High Register		*/
-
-#define CAN_MB27_DATA0		0xFFC02F60	/* Mailbox 27 Data Word 0 [15:0] Register	*/
-#define CAN_MB27_DATA1		0xFFC02F64	/* Mailbox 27 Data Word 1 [31:16] Register	*/
-#define CAN_MB27_DATA2		0xFFC02F68	/* Mailbox 27 Data Word 2 [47:32] Register	*/
-#define CAN_MB27_DATA3		0xFFC02F6C	/* Mailbox 27 Data Word 3 [63:48] Register	*/
-#define CAN_MB27_LENGTH		0xFFC02F70	/* Mailbox 27 Data Length Code Register		*/
-#define CAN_MB27_TIMESTAMP	0xFFC02F74	/* Mailbox 27 Time Stamp Value Register		*/
-#define CAN_MB27_ID0		0xFFC02F78	/* Mailbox 27 Identifier Low Register		*/
-#define CAN_MB27_ID1		0xFFC02F7C	/* Mailbox 27 Identifier High Register		*/
-
-#define CAN_MB28_DATA0		0xFFC02F80	/* Mailbox 28 Data Word 0 [15:0] Register	*/
-#define CAN_MB28_DATA1		0xFFC02F84	/* Mailbox 28 Data Word 1 [31:16] Register	*/
-#define CAN_MB28_DATA2		0xFFC02F88	/* Mailbox 28 Data Word 2 [47:32] Register	*/
-#define CAN_MB28_DATA3		0xFFC02F8C	/* Mailbox 28 Data Word 3 [63:48] Register	*/
-#define CAN_MB28_LENGTH		0xFFC02F90	/* Mailbox 28 Data Length Code Register		*/
-#define CAN_MB28_TIMESTAMP	0xFFC02F94	/* Mailbox 28 Time Stamp Value Register		*/
-#define CAN_MB28_ID0		0xFFC02F98	/* Mailbox 28 Identifier Low Register		*/
-#define CAN_MB28_ID1		0xFFC02F9C	/* Mailbox 28 Identifier High Register		*/
-
-#define CAN_MB29_DATA0		0xFFC02FA0	/* Mailbox 29 Data Word 0 [15:0] Register	*/
-#define CAN_MB29_DATA1		0xFFC02FA4	/* Mailbox 29 Data Word 1 [31:16] Register	*/
-#define CAN_MB29_DATA2		0xFFC02FA8	/* Mailbox 29 Data Word 2 [47:32] Register	*/
-#define CAN_MB29_DATA3		0xFFC02FAC	/* Mailbox 29 Data Word 3 [63:48] Register	*/
-#define CAN_MB29_LENGTH		0xFFC02FB0	/* Mailbox 29 Data Length Code Register		*/
-#define CAN_MB29_TIMESTAMP	0xFFC02FB4	/* Mailbox 29 Time Stamp Value Register		*/
-#define CAN_MB29_ID0		0xFFC02FB8	/* Mailbox 29 Identifier Low Register		*/
-#define CAN_MB29_ID1		0xFFC02FBC	/* Mailbox 29 Identifier High Register		*/
-
-#define CAN_MB30_DATA0		0xFFC02FC0	/* Mailbox 30 Data Word 0 [15:0] Register	*/
-#define CAN_MB30_DATA1		0xFFC02FC4	/* Mailbox 30 Data Word 1 [31:16] Register	*/
-#define CAN_MB30_DATA2		0xFFC02FC8	/* Mailbox 30 Data Word 2 [47:32] Register	*/
-#define CAN_MB30_DATA3		0xFFC02FCC	/* Mailbox 30 Data Word 3 [63:48] Register	*/
-#define CAN_MB30_LENGTH		0xFFC02FD0	/* Mailbox 30 Data Length Code Register		*/
-#define CAN_MB30_TIMESTAMP	0xFFC02FD4	/* Mailbox 30 Time Stamp Value Register		*/
-#define CAN_MB30_ID0		0xFFC02FD8	/* Mailbox 30 Identifier Low Register		*/
-#define CAN_MB30_ID1		0xFFC02FDC	/* Mailbox 30 Identifier High Register		*/
-
-#define CAN_MB31_DATA0		0xFFC02FE0	/* Mailbox 31 Data Word 0 [15:0] Register	*/
-#define CAN_MB31_DATA1		0xFFC02FE4	/* Mailbox 31 Data Word 1 [31:16] Register	*/
-#define CAN_MB31_DATA2		0xFFC02FE8	/* Mailbox 31 Data Word 2 [47:32] Register	*/
-#define CAN_MB31_DATA3		0xFFC02FEC	/* Mailbox 31 Data Word 3 [63:48] Register	*/
-#define CAN_MB31_LENGTH		0xFFC02FF0	/* Mailbox 31 Data Length Code Register		*/
-#define CAN_MB31_TIMESTAMP	0xFFC02FF4	/* Mailbox 31 Time Stamp Value Register		*/
-#define CAN_MB31_ID0		0xFFC02FF8	/* Mailbox 31 Identifier Low Register		*/
-#define CAN_MB31_ID1		0xFFC02FFC	/* Mailbox 31 Identifier High Register		*/
-
-/* CAN Mailbox Area Macros				*/
-#define CAN_MB_ID1(x)		(CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)		(CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)	(CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)	(CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)		(CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)		(CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)		(CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)		(CAN_MB00_DATA0+((x)*0x20))
-
-
-/************************************************************************************
-** System MMR Register Bits And Macros
-*************************************************************************************
-**/
-
-/* ********************* PLL AND RESET MASKS ****************************************/
-
-/* PLL_CTL Masks (IN_DELAY and OUT_DELAY bit field definitions differ from BF533/BF532/BF531) */
-#define MSEL                    0x7E00              /* Multiplier Select For CCLK/VCO Factors */
-#define IN_DELAY			0x0014  /* EBIU Input Delay Select */
-#define OUT_DELAY			0x00C0  /* EBIU Output Delay Select */
-
-#ifdef _MISRA_RULES
-#define SET_OUT_DELAY(x)	(((x)&0x03u) << 0x6)
-#define SET_IN_DELAY(x)		((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
-#else
-#define SET_OUT_DELAY(x)	(((x)&0x03) << 0x6)
-#define SET_IN_DELAY(x)		((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks	(Additional WakeUp Events) */
-#define	CANWE				0x0200	/* Enable CAN Wakeup From Hibernate */
-#define	GPWE				0x0400	/* Enable General-Purpose Wakeup From Hibernate */
-
-
-/* **********************  SYSTEM INTERRUPT CONTROLLER MASKS **********************	*/
-/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0            */
-#define DMAC0_ERR_IRQ		0x00000002	/* DMA Controller 0 Error Interrupt Request */
-#define SPI0_ERR_IRQ		0x00000020	/* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ		0x00000040	/* UART0 Error Interrupt Request */
-#define MDMA0_0_IRQ			0x00200000	/* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ			0x00400000	/* MemDMA0 Stream 1 Interrupt Request */
-#define DMAC1_ERR_IRQ		0x01000000	/* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ		0x02000000	/* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ		0x04000000	/* SPORT3 Error Interrupt Request */
-#define SPI1_ERR_IRQ		0x10000000	/* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ		0x20000000	/* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ		0x40000000	/* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ		0x80000000	/* UART2 Error Interrupt Request */
-
-#define DMA0_ERR_IRQ		DMAC0_ERR_IRQ	/* legacy */
-#define DMA1_ERR_IRQ		DMAC1_ERR_IRQ	/* legacy */
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1								*/
-#define CAN_ERR_IRQ			0x00000001	/* CAN Error Interrupt Request */
-#define DMA8_IRQ			0x00000002	/* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ			0x00000004	/* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ			0x00000008	/* DMA Channel 10 (SPORT3 RX) Interrupt Request	*/
-#define DMA11_IRQ			0x00000010	/* DMA Channel 11 (SPORT3 TX) Interrupt Request	*/
-#define DMA12_IRQ			0x00000020	/* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ			0x00000040	/* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ			0x00000080	/* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ			0x00000100	/* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ			0x00000200	/* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ			0x00000400	/* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ			0x00000800	/* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ			0x00001000	/* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ			0x00002000	/* TWI0 Interrupt Request */
-#define TWI1_IRQ			0x00004000	/* TWI1 Interrupt Request */
-#define CAN_RX_IRQ			0x00008000	/* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ			0x00010000	/* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ			0x00020000	/* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ			0x00040000	/* MemDMA1 Stream 1 Interrupt Request */
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-/* SIC_IAR3 Macros															*/
-#define P24_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #24 assigned IVG #x	*/
-#define P25_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #25 assigned IVG #x	*/
-#define P26_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #26 assigned IVG #x	*/
-#define P27_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #27 assigned IVG #x	*/
-#define P28_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #28 assigned IVG #x	*/
-#define P29_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #29 assigned IVG #x	*/
-#define P30_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #30 assigned IVG #x	*/
-#define P31_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #31 assigned IVG #x	*/
-
-/* SIC_IAR4 Macros															*/
-#define P32_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #32 assigned IVG #x	*/
-#define P33_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #33 assigned IVG #x	*/
-#define P34_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #34 assigned IVG #x	*/
-#define P35_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #35 assigned IVG #x	*/
-#define P36_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #36 assigned IVG #x	*/
-#define P37_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #37 assigned IVG #x	*/
-#define P38_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #38 assigned IVG #x	*/
-#define P39_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #39 assigned IVG #x	*/
-
-/* SIC_IAR5 Macros															*/
-#define P40_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #40 assigned IVG #x	*/
-#define P41_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #41 assigned IVG #x	*/
-#define P42_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #42 assigned IVG #x	*/
-#define P43_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #43 assigned IVG #x	*/
-#define P44_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #44 assigned IVG #x	*/
-#define P45_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #45 assigned IVG #x	*/
-#define P46_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #46 assigned IVG #x	*/
-#define P47_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #47 assigned IVG #x	*/
-
-/* SIC_IAR6 Macros															*/
-#define P48_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #48 assigned IVG #x	*/
-#define P49_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #49 assigned IVG #x	*/
-#define P50_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #50 assigned IVG #x	*/
-#define P51_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #51 assigned IVG #x	*/
-#define P52_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #52 assigned IVG #x	*/
-#define P53_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #53 assigned IVG #x	*/
-#define P54_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #54 assigned IVG #x	*/
-#define P55_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #55 assigned IVG #x	*/
-
-
-/*******************   GPIO MASKS  *********************/
-/* Port C Masks */
-#define PC0		0x0001
-#define PC1		0x0002
-#define PC4		0x0010
-#define PC5		0x0020
-#define PC6		0x0040
-#define PC7		0x0080
-#define PC8		0x0100
-#define PC9		0x0200
-/* Port C Bit Positions */
-#define PC0_P	0x0
-#define PC1_P	0x1
-#define PC4_P	0x4
-#define PC5_P	0x5
-#define PC6_P	0x6
-#define PC7_P	0x7
-#define PC8_P	0x8
-#define PC9_P	0x9
-
-/* Port D */
-#define PD0		0x0001
-#define PD1		0x0002
-#define PD2		0x0004
-#define PD3		0x0008
-#define PD4		0x0010
-#define PD5		0x0020
-#define PD6		0x0040
-#define PD7		0x0080
-#define PD8		0x0100
-#define PD9		0x0200
-#define PD10	0x0400
-#define PD11	0x0800
-#define PD12	0x1000
-#define PD13	0x2000
-#define PD14	0x4000
-#define PD15	0x8000
-/* Port D Bit Positions */
-#define PD0_P	0x0
-#define PD1_P	0x1
-#define PD2_P	0x2
-#define PD3_P	0x3
-#define PD4_P	0x4
-#define PD5_P	0x5
-#define PD6_P	0x6
-#define PD7_P	0x7
-#define PD8_P	0x8
-#define PD9_P	0x9
-#define PD10_P	0xA
-#define PD11_P	0xB
-#define PD12_P	0xC
-#define PD13_P	0xD
-#define PD14_P	0xE
-#define PD15_P	0xF
-
-/* Port E */
-#define PE0		0x0001
-#define PE1		0x0002
-#define PE2		0x0004
-#define PE3		0x0008
-#define PE4		0x0010
-#define PE5		0x0020
-#define PE6		0x0040
-#define PE7		0x0080
-#define PE8		0x0100
-#define PE9		0x0200
-#define PE10	0x0400
-#define PE11	0x0800
-#define PE12	0x1000
-#define PE13	0x2000
-#define PE14	0x4000
-#define PE15	0x8000
-/* Port E Bit Positions */
-#define PE0_P	0x0
-#define PE1_P	0x1
-#define PE2_P	0x2
-#define PE3_P	0x3
-#define PE4_P	0x4
-#define PE5_P	0x5
-#define PE6_P	0x6
-#define PE7_P	0x7
-#define PE8_P	0x8
-#define PE9_P	0x9
-#define PE10_P	0xA
-#define PE11_P	0xB
-#define PE12_P	0xC
-#define PE13_P	0xD
-#define PE14_P	0xE
-#define PE15_P	0xF
-
-
-/* ****************  DMA CONTROLLER 0 (DMAC0) MASKS  ***************************/
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_SPI0           PMAP_SPI  /* PMAP SPI0 DMA */
-#define PMAP_UART0RX        PMAP_UARTRX  /* PMAP UART0 Receive DMA */
-#define PMAP_UART0TX        PMAP_UARTTX  /* PMAP UART0 Transmit DMA */
-
-/* ****************  DMA CONTROLLER 1 (DMAC1) MASKS  ***************************/
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
-#define	PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
-#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
-#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
-#define	PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
-
-/* EBIU_SDBCTL Masks		*/
-#define EBSZ      0x0006   /* SDRAM external bank size */
-#define EBCAW     0x0030   /* SDRAM external bank column address width */
-
-/* EBIU_SDGCTL Masks */
-#define CL        0x0000000C  /* SDRAM CAS latency */
-#define PASR      0x00000030  /* SDRAM partial array self-refresh */
-#define TRAS      0x000003C0  /* SDRAM tRAS in SCLK cycles */
-#define TRP       0x00003800  /* SDRAM tRP in SCLK cycles */
-#define TRCD      0x00030000  /* SDRAM tRCD in SCLK cycles */
-#define TWR       0x00180000  /* SDRAM tWR in SCLK cycles */
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#ifdef _MISRA_RULES
-#define	CLKLOW(x)	((x) & 0xFFu)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFFu)<<0x8)	/* Periods Before New Clock Low			*/
-#else
-#define	CLKLOW(x)	((x) & 0xFF)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low			*/
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks															*/
-#define	PRESCALE	0x007F		/* SCLKs Per Internal Time Reference (10MHz)	*/
-#define	TWI_ENA		0x0080		/* TWI Enable									*/
-#define	SCCB		0x0200		/* SCCB Compatibility Enable					*/
-
-/* TWIx_SLAVE_CTRL Masks															*/
-#define	SEN			0x0001		/* Slave Enable									*/
-#define	SADD_LEN	0x0002		/* Slave Address Length							*/
-#define	STDVAL		0x0004		/* Slave Transmit Data Valid					*/
-#define	NAK			0x0008		/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010		/* General Call Adrress Matching Enabled		*/
-
-/* TWIx_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001		/* Slave Transfer Direction (Transmit/Receive*)	*/
-#define GCALL		0x0002		/* General Call Indicator						*/
-
-/* TWIx_MASTER_CTRL Masks													*/
-#define	MEN			0x0001		/* Master Mode Enable						*/
-#define	MADD_LEN	0x0002		/* Master Address Length					*/
-#define	MDIR		0x0004		/* Master Transmit Direction (RX/TX*)		*/
-#define	FAST		0x0008		/* Use Fast Mode Timing Specs				*/
-#define	STOP		0x0010		/* Issue Stop Condition						*/
-#define	RSTART		0x0020		/* Repeat Start or Stop* At End Of Transfer	*/
-#define	DCNT		0x3FC0		/* Data Bytes To Transfer					*/
-#define	SDAOVR		0x4000		/* Serial Data Override						*/
-#define	SCLOVR		0x8000		/* Serial Clock Override					*/
-
-/* TWIx_MASTER_STAT Masks														*/
-#define	MPROG		0x0001		/* Master Transfer In Progress					*/
-#define	LOSTARB		0x0002		/* Lost Arbitration Indicator (Xfer Aborted)	*/
-#define	ANAK		0x0004		/* Address Not Acknowledged						*/
-#define	DNAK		0x0008		/* Data Not Acknowledged						*/
-#define	BUFRDERR	0x0010		/* Buffer Read Error							*/
-#define	BUFWRERR	0x0020		/* Buffer Write Error							*/
-#define	SDASEN		0x0040		/* Serial Data Sense							*/
-#define	SCLSEN		0x0080		/* Serial Clock Sense							*/
-#define	BUSBUSY		0x0100		/* Bus Busy Indicator							*/
-
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks						*/
-#define	SINIT		0x0001		/* Slave Transfer Initiated	*/
-#define	SCOMP		0x0002		/* Slave Transfer Complete	*/
-#define	SERR		0x0004		/* Slave Transfer Error		*/
-#define	SOVF		0x0008		/* Slave Overflow			*/
-#define	MCOMP		0x0010		/* Master Transfer Complete	*/
-#define	MERR		0x0020		/* Master Transfer Error	*/
-#define	XMTSERV		0x0040		/* Transmit FIFO Service	*/
-#define	RCVSERV		0x0080		/* Receive FIFO Service		*/
-
-/* TWIx_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001		/* Transmit Buffer Flush			*/
-#define	RCVFLUSH	0x0002		/* Receive Buffer Flush				*/
-#define	XMTINTLEN	0x0004		/* Transmit Buffer Interrupt Length	*/
-#define	RCVINTLEN	0x0008		/* Receive Buffer Interrupt Length	*/
-
-/* TWIx_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003		/* Transmit FIFO Status							*/
-#define	XMT_EMPTY	0x0000		/* 		Transmit FIFO Empty						*/
-#define	XMT_HALF	0x0001		/* 		Transmit FIFO Has 1 Byte To Write		*/
-#define	XMT_FULL	0x0003		/* 		Transmit FIFO Full (2 Bytes To Write)	*/
-
-#define	RCVSTAT		0x000C		/* Receive FIFO Status							*/
-#define	RCV_EMPTY	0x0000		/* 		Receive FIFO Empty						*/
-#define	RCV_HALF	0x0004		/* 		Receive FIFO Has 1 Byte To Read			*/
-#define	RCV_FULL	0x000C		/* 		Receive FIFO Full (2 Bytes To Read)		*/
-
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-/* CAN_CONTROL Masks												*/
-#define	SRS			0x0001	/* Software Reset						*/
-#define	DNM			0x0002	/* Device Net Mode						*/
-#define	ABO			0x0004	/* Auto-Bus On Enable					*/
-#define	WBA			0x0010	/* Wake-Up On CAN Bus Activity Enable	*/
-#define	SMR			0x0020	/* Sleep Mode Request					*/
-#define	CSR			0x0040	/* CAN Suspend Mode Request				*/
-#define	CCR			0x0080	/* CAN Configuration Mode Request		*/
-
-/* CAN_STATUS Masks												*/
-#define	WT			0x0001	/* TX Warning Flag					*/
-#define	WR			0x0002	/* RX Warning Flag					*/
-#define	EP			0x0004	/* Error Passive Mode				*/
-#define	EBO			0x0008	/* Error Bus Off Mode				*/
-#define	CSA			0x0040	/* Suspend Mode Acknowledge			*/
-#define	CCA			0x0080	/* Configuration Mode Acknowledge	*/
-#define	MBPTR		0x1F00	/* Mailbox Pointer					*/
-#define	TRM			0x4000	/* Transmit Mode					*/
-#define	REC			0x8000	/* Receive Mode						*/
-
-/* CAN_CLOCK Masks									*/
-#define	BRP			0x03FF	/* Bit-Rate Pre-Scaler	*/
-
-/* CAN_TIMING Masks											*/
-#define	TSEG1		0x000F	/* Time Segment 1				*/
-#define	TSEG2		0x0070	/* Time Segment 2				*/
-#define	SAM			0x0080	/* Sampling						*/
-#define	SJW			0x0300	/* Synchronization Jump Width	*/
-
-/* CAN_DEBUG Masks											*/
-#define	DEC			0x0001	/* Disable CAN Error Counters	*/
-#define	DRI			0x0002	/* Disable CAN RX Input			*/
-#define	DTO			0x0004	/* Disable CAN TX Output		*/
-#define	DIL			0x0008	/* Disable CAN Internal Loop	*/
-#define	MAA			0x0010	/* Mode Auto-Acknowledge Enable	*/
-#define	MRB			0x0020	/* Mode Read Back Enable		*/
-#define	CDE			0x8000	/* CAN Debug Enable				*/
-
-/* CAN_CEC Masks										*/
-#define	RXECNT		0x00FF	/* Receive Error Counter	*/
-#define	TXECNT		0xFF00	/* Transmit Error Counter	*/
-
-/* CAN_INTR Masks											*/
-#define	MBRIRQ	0x0001	/* Mailbox Receive Interrupt	*/
-#define	MBRIF		MBRIRQ	/* legacy */
-#define	MBTIRQ	0x0002	/* Mailbox Transmit Interrupt	*/
-#define	MBTIF		MBTIRQ	/* legacy */
-#define	GIRQ		0x0004	/* Global Interrupt				*/
-#define	SMACK		0x0008	/* Sleep Mode Acknowledge		*/
-#define	CANTX		0x0040	/* CAN TX Bus Value				*/
-#define	CANRX		0x0080	/* CAN RX Bus Value				*/
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks										*/
-#define DFC			0xFFFF	/* Data Filtering Code (If Enabled) (ID0)		*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (ID0)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (ID1)	*/
-#define	BASEID		0x1FFC	/* Base Identifier								*/
-#define	IDE			0x2000	/* Identifier Extension							*/
-#define	RTR			0x4000	/* Remote Frame Transmission Request			*/
-#define	AME			0x8000	/* Acceptance Mask Enable						*/
-
-/* CAN_MBxx_TIMESTAMP Masks					*/
-#define TSV			0xFFFF	/* Timestamp	*/
-
-/* CAN_MBxx_LENGTH Masks						*/
-#define DLC			0x000F	/* Data Length Code	*/
-
-/* CAN_AMxxH and CAN_AMxxL Masks												*/
-#define DFM			0xFFFF	/* Data Field Mask (If Enabled) (CAN_AMxxL)			*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (CAN_AMxxL)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (CAN_AMxxH)	*/
-#define	BASEID		0x1FFC	/* Base Identifier									*/
-#define	AMIDE		0x2000	/* Acceptance Mask ID Extension Enable				*/
-#define	FMD			0x4000	/* Full Mask Data Field Enable						*/
-#define	FDF			0x8000	/* Filter On Data Field Enable						*/
-
-/* CAN_MC1 Masks									*/
-#define	MC0			0x0001	/* Enable Mailbox 0		*/
-#define	MC1			0x0002	/* Enable Mailbox 1		*/
-#define	MC2			0x0004	/* Enable Mailbox 2		*/
-#define	MC3			0x0008	/* Enable Mailbox 3		*/
-#define	MC4			0x0010	/* Enable Mailbox 4		*/
-#define	MC5			0x0020	/* Enable Mailbox 5		*/
-#define	MC6			0x0040	/* Enable Mailbox 6		*/
-#define	MC7			0x0080	/* Enable Mailbox 7		*/
-#define	MC8			0x0100	/* Enable Mailbox 8		*/
-#define	MC9			0x0200	/* Enable Mailbox 9		*/
-#define	MC10		0x0400	/* Enable Mailbox 10	*/
-#define	MC11		0x0800	/* Enable Mailbox 11	*/
-#define	MC12		0x1000	/* Enable Mailbox 12	*/
-#define	MC13		0x2000	/* Enable Mailbox 13	*/
-#define	MC14		0x4000	/* Enable Mailbox 14	*/
-#define	MC15		0x8000	/* Enable Mailbox 15	*/
-
-/* CAN_MC2 Masks									*/
-#define	MC16		0x0001	/* Enable Mailbox 16	*/
-#define	MC17		0x0002	/* Enable Mailbox 17	*/
-#define	MC18		0x0004	/* Enable Mailbox 18	*/
-#define	MC19		0x0008	/* Enable Mailbox 19	*/
-#define	MC20		0x0010	/* Enable Mailbox 20	*/
-#define	MC21		0x0020	/* Enable Mailbox 21	*/
-#define	MC22		0x0040	/* Enable Mailbox 22	*/
-#define	MC23		0x0080	/* Enable Mailbox 23	*/
-#define	MC24		0x0100	/* Enable Mailbox 24	*/
-#define	MC25		0x0200	/* Enable Mailbox 25	*/
-#define	MC26		0x0400	/* Enable Mailbox 26	*/
-#define	MC27		0x0800	/* Enable Mailbox 27	*/
-#define	MC28		0x1000	/* Enable Mailbox 28	*/
-#define	MC29		0x2000	/* Enable Mailbox 29	*/
-#define	MC30		0x4000	/* Enable Mailbox 30	*/
-#define	MC31		0x8000	/* Enable Mailbox 31	*/
-
-/* CAN_MD1 Masks												*/
-#define	MD0			0x0001	/* Enable Mailbox 0 For Receive		*/
-#define	MD1			0x0002	/* Enable Mailbox 1 For Receive		*/
-#define	MD2			0x0004	/* Enable Mailbox 2 For Receive		*/
-#define	MD3			0x0008	/* Enable Mailbox 3 For Receive		*/
-#define	MD4			0x0010	/* Enable Mailbox 4 For Receive		*/
-#define	MD5			0x0020	/* Enable Mailbox 5 For Receive		*/
-#define	MD6			0x0040	/* Enable Mailbox 6 For Receive		*/
-#define	MD7			0x0080	/* Enable Mailbox 7 For Receive		*/
-#define	MD8			0x0100	/* Enable Mailbox 8 For Receive		*/
-#define	MD9			0x0200	/* Enable Mailbox 9 For Receive		*/
-#define	MD10		0x0400	/* Enable Mailbox 10 For Receive	*/
-#define	MD11		0x0800	/* Enable Mailbox 11 For Receive	*/
-#define	MD12		0x1000	/* Enable Mailbox 12 For Receive	*/
-#define	MD13		0x2000	/* Enable Mailbox 13 For Receive	*/
-#define	MD14		0x4000	/* Enable Mailbox 14 For Receive	*/
-#define	MD15		0x8000	/* Enable Mailbox 15 For Receive	*/
-
-/* CAN_MD2 Masks												*/
-#define	MD16		0x0001	/* Enable Mailbox 16 For Receive	*/
-#define	MD17		0x0002	/* Enable Mailbox 17 For Receive	*/
-#define	MD18		0x0004	/* Enable Mailbox 18 For Receive	*/
-#define	MD19		0x0008	/* Enable Mailbox 19 For Receive	*/
-#define	MD20		0x0010	/* Enable Mailbox 20 For Receive	*/
-#define	MD21		0x0020	/* Enable Mailbox 21 For Receive	*/
-#define	MD22		0x0040	/* Enable Mailbox 22 For Receive	*/
-#define	MD23		0x0080	/* Enable Mailbox 23 For Receive	*/
-#define	MD24		0x0100	/* Enable Mailbox 24 For Receive	*/
-#define	MD25		0x0200	/* Enable Mailbox 25 For Receive	*/
-#define	MD26		0x0400	/* Enable Mailbox 26 For Receive	*/
-#define	MD27		0x0800	/* Enable Mailbox 27 For Receive	*/
-#define	MD28		0x1000	/* Enable Mailbox 28 For Receive	*/
-#define	MD29		0x2000	/* Enable Mailbox 29 For Receive	*/
-#define	MD30		0x4000	/* Enable Mailbox 30 For Receive	*/
-#define	MD31		0x8000	/* Enable Mailbox 31 For Receive	*/
-
-/* CAN_RMP1 Masks												*/
-#define	RMP0		0x0001	/* RX Message Pending In Mailbox 0	*/
-#define	RMP1		0x0002	/* RX Message Pending In Mailbox 1	*/
-#define	RMP2		0x0004	/* RX Message Pending In Mailbox 2	*/
-#define	RMP3		0x0008	/* RX Message Pending In Mailbox 3	*/
-#define	RMP4		0x0010	/* RX Message Pending In Mailbox 4	*/
-#define	RMP5		0x0020	/* RX Message Pending In Mailbox 5	*/
-#define	RMP6		0x0040	/* RX Message Pending In Mailbox 6	*/
-#define	RMP7		0x0080	/* RX Message Pending In Mailbox 7	*/
-#define	RMP8		0x0100	/* RX Message Pending In Mailbox 8	*/
-#define	RMP9		0x0200	/* RX Message Pending In Mailbox 9	*/
-#define	RMP10		0x0400	/* RX Message Pending In Mailbox 10	*/
-#define	RMP11		0x0800	/* RX Message Pending In Mailbox 11	*/
-#define	RMP12		0x1000	/* RX Message Pending In Mailbox 12	*/
-#define	RMP13		0x2000	/* RX Message Pending In Mailbox 13	*/
-#define	RMP14		0x4000	/* RX Message Pending In Mailbox 14	*/
-#define	RMP15		0x8000	/* RX Message Pending In Mailbox 15	*/
-
-/* CAN_RMP2 Masks												*/
-#define	RMP16		0x0001	/* RX Message Pending In Mailbox 16	*/
-#define	RMP17		0x0002	/* RX Message Pending In Mailbox 17	*/
-#define	RMP18		0x0004	/* RX Message Pending In Mailbox 18	*/
-#define	RMP19		0x0008	/* RX Message Pending In Mailbox 19	*/
-#define	RMP20		0x0010	/* RX Message Pending In Mailbox 20	*/
-#define	RMP21		0x0020	/* RX Message Pending In Mailbox 21	*/
-#define	RMP22		0x0040	/* RX Message Pending In Mailbox 22	*/
-#define	RMP23		0x0080	/* RX Message Pending In Mailbox 23	*/
-#define	RMP24		0x0100	/* RX Message Pending In Mailbox 24	*/
-#define	RMP25		0x0200	/* RX Message Pending In Mailbox 25	*/
-#define	RMP26		0x0400	/* RX Message Pending In Mailbox 26	*/
-#define	RMP27		0x0800	/* RX Message Pending In Mailbox 27	*/
-#define	RMP28		0x1000	/* RX Message Pending In Mailbox 28	*/
-#define	RMP29		0x2000	/* RX Message Pending In Mailbox 29	*/
-#define	RMP30		0x4000	/* RX Message Pending In Mailbox 30	*/
-#define	RMP31		0x8000	/* RX Message Pending In Mailbox 31	*/
-
-/* CAN_RML1 Masks												*/
-#define	RML0		0x0001	/* RX Message Lost In Mailbox 0		*/
-#define	RML1		0x0002	/* RX Message Lost In Mailbox 1		*/
-#define	RML2		0x0004	/* RX Message Lost In Mailbox 2		*/
-#define	RML3		0x0008	/* RX Message Lost In Mailbox 3		*/
-#define	RML4		0x0010	/* RX Message Lost In Mailbox 4		*/
-#define	RML5		0x0020	/* RX Message Lost In Mailbox 5		*/
-#define	RML6		0x0040	/* RX Message Lost In Mailbox 6		*/
-#define	RML7		0x0080	/* RX Message Lost In Mailbox 7		*/
-#define	RML8		0x0100	/* RX Message Lost In Mailbox 8		*/
-#define	RML9		0x0200	/* RX Message Lost In Mailbox 9		*/
-#define	RML10		0x0400	/* RX Message Lost In Mailbox 10	*/
-#define	RML11		0x0800	/* RX Message Lost In Mailbox 11	*/
-#define	RML12		0x1000	/* RX Message Lost In Mailbox 12	*/
-#define	RML13		0x2000	/* RX Message Lost In Mailbox 13	*/
-#define	RML14		0x4000	/* RX Message Lost In Mailbox 14	*/
-#define	RML15		0x8000	/* RX Message Lost In Mailbox 15	*/
-
-/* CAN_RML2 Masks												*/
-#define	RML16		0x0001	/* RX Message Lost In Mailbox 16	*/
-#define	RML17		0x0002	/* RX Message Lost In Mailbox 17	*/
-#define	RML18		0x0004	/* RX Message Lost In Mailbox 18	*/
-#define	RML19		0x0008	/* RX Message Lost In Mailbox 19	*/
-#define	RML20		0x0010	/* RX Message Lost In Mailbox 20	*/
-#define	RML21		0x0020	/* RX Message Lost In Mailbox 21	*/
-#define	RML22		0x0040	/* RX Message Lost In Mailbox 22	*/
-#define	RML23		0x0080	/* RX Message Lost In Mailbox 23	*/
-#define	RML24		0x0100	/* RX Message Lost In Mailbox 24	*/
-#define	RML25		0x0200	/* RX Message Lost In Mailbox 25	*/
-#define	RML26		0x0400	/* RX Message Lost In Mailbox 26	*/
-#define	RML27		0x0800	/* RX Message Lost In Mailbox 27	*/
-#define	RML28		0x1000	/* RX Message Lost In Mailbox 28	*/
-#define	RML29		0x2000	/* RX Message Lost In Mailbox 29	*/
-#define	RML30		0x4000	/* RX Message Lost In Mailbox 30	*/
-#define	RML31		0x8000	/* RX Message Lost In Mailbox 31	*/
-
-/* CAN_OPSS1 Masks																				*/
-#define	OPSS0		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0	*/
-#define	OPSS1		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1	*/
-#define	OPSS2		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2	*/
-#define	OPSS3		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3	*/
-#define	OPSS4		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4	*/
-#define	OPSS5		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5	*/
-#define	OPSS6		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6	*/
-#define	OPSS7		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7	*/
-#define	OPSS8		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8	*/
-#define	OPSS9		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9	*/
-#define	OPSS10		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10	*/
-#define	OPSS11		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11	*/
-#define	OPSS12		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12	*/
-#define	OPSS13		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13	*/
-#define	OPSS14		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14	*/
-#define	OPSS15		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15	*/
-
-/* CAN_OPSS2 Masks																				*/
-#define	OPSS16		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16	*/
-#define	OPSS17		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17	*/
-#define	OPSS18		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18	*/
-#define	OPSS19		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19	*/
-#define	OPSS20		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20	*/
-#define	OPSS21		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21	*/
-#define	OPSS22		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22	*/
-#define	OPSS23		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23	*/
-#define	OPSS24		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24	*/
-#define	OPSS25		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25	*/
-#define	OPSS26		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26	*/
-#define	OPSS27		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27	*/
-#define	OPSS28		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28	*/
-#define	OPSS29		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29	*/
-#define	OPSS30		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30	*/
-#define	OPSS31		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31	*/
-
-/* CAN_TRR1 Masks														*/
-#define	TRR0		0x0001	/* Deny But Don't Lock Access To Mailbox 0	*/
-#define	TRR1		0x0002	/* Deny But Don't Lock Access To Mailbox 1	*/
-#define	TRR2		0x0004	/* Deny But Don't Lock Access To Mailbox 2	*/
-#define	TRR3		0x0008	/* Deny But Don't Lock Access To Mailbox 3	*/
-#define	TRR4		0x0010	/* Deny But Don't Lock Access To Mailbox 4	*/
-#define	TRR5		0x0020	/* Deny But Don't Lock Access To Mailbox 5	*/
-#define	TRR6		0x0040	/* Deny But Don't Lock Access To Mailbox 6	*/
-#define	TRR7		0x0080	/* Deny But Don't Lock Access To Mailbox 7	*/
-#define	TRR8		0x0100	/* Deny But Don't Lock Access To Mailbox 8	*/
-#define	TRR9		0x0200	/* Deny But Don't Lock Access To Mailbox 9	*/
-#define	TRR10		0x0400	/* Deny But Don't Lock Access To Mailbox 10	*/
-#define	TRR11		0x0800	/* Deny But Don't Lock Access To Mailbox 11	*/
-#define	TRR12		0x1000	/* Deny But Don't Lock Access To Mailbox 12	*/
-#define	TRR13		0x2000	/* Deny But Don't Lock Access To Mailbox 13	*/
-#define	TRR14		0x4000	/* Deny But Don't Lock Access To Mailbox 14	*/
-#define	TRR15		0x8000	/* Deny But Don't Lock Access To Mailbox 15	*/
-
-/* CAN_TRR2 Masks														*/
-#define	TRR16		0x0001	/* Deny But Don't Lock Access To Mailbox 16	*/
-#define	TRR17		0x0002	/* Deny But Don't Lock Access To Mailbox 17	*/
-#define	TRR18		0x0004	/* Deny But Don't Lock Access To Mailbox 18	*/
-#define	TRR19		0x0008	/* Deny But Don't Lock Access To Mailbox 19	*/
-#define	TRR20		0x0010	/* Deny But Don't Lock Access To Mailbox 20	*/
-#define	TRR21		0x0020	/* Deny But Don't Lock Access To Mailbox 21	*/
-#define	TRR22		0x0040	/* Deny But Don't Lock Access To Mailbox 22	*/
-#define	TRR23		0x0080	/* Deny But Don't Lock Access To Mailbox 23	*/
-#define	TRR24		0x0100	/* Deny But Don't Lock Access To Mailbox 24	*/
-#define	TRR25		0x0200	/* Deny But Don't Lock Access To Mailbox 25	*/
-#define	TRR26		0x0400	/* Deny But Don't Lock Access To Mailbox 26	*/
-#define	TRR27		0x0800	/* Deny But Don't Lock Access To Mailbox 27	*/
-#define	TRR28		0x1000	/* Deny But Don't Lock Access To Mailbox 28	*/
-#define	TRR29		0x2000	/* Deny But Don't Lock Access To Mailbox 29	*/
-#define	TRR30		0x4000	/* Deny But Don't Lock Access To Mailbox 30	*/
-#define	TRR31		0x8000	/* Deny But Don't Lock Access To Mailbox 31	*/
-
-/* CAN_TRS1 Masks													*/
-#define	TRS0		0x0001	/* Remote Frame Request For Mailbox 0	*/
-#define	TRS1		0x0002	/* Remote Frame Request For Mailbox 1	*/
-#define	TRS2		0x0004	/* Remote Frame Request For Mailbox 2	*/
-#define	TRS3		0x0008	/* Remote Frame Request For Mailbox 3	*/
-#define	TRS4		0x0010	/* Remote Frame Request For Mailbox 4	*/
-#define	TRS5		0x0020	/* Remote Frame Request For Mailbox 5	*/
-#define	TRS6		0x0040	/* Remote Frame Request For Mailbox 6	*/
-#define	TRS7		0x0080	/* Remote Frame Request For Mailbox 7	*/
-#define	TRS8		0x0100	/* Remote Frame Request For Mailbox 8	*/
-#define	TRS9		0x0200	/* Remote Frame Request For Mailbox 9	*/
-#define	TRS10		0x0400	/* Remote Frame Request For Mailbox 10	*/
-#define	TRS11		0x0800	/* Remote Frame Request For Mailbox 11	*/
-#define	TRS12		0x1000	/* Remote Frame Request For Mailbox 12	*/
-#define	TRS13		0x2000	/* Remote Frame Request For Mailbox 13	*/
-#define	TRS14		0x4000	/* Remote Frame Request For Mailbox 14	*/
-#define	TRS15		0x8000	/* Remote Frame Request For Mailbox 15	*/
-
-/* CAN_TRS2 Masks													*/
-#define	TRS16		0x0001	/* Remote Frame Request For Mailbox 16	*/
-#define	TRS17		0x0002	/* Remote Frame Request For Mailbox 17	*/
-#define	TRS18		0x0004	/* Remote Frame Request For Mailbox 18	*/
-#define	TRS19		0x0008	/* Remote Frame Request For Mailbox 19	*/
-#define	TRS20		0x0010	/* Remote Frame Request For Mailbox 20	*/
-#define	TRS21		0x0020	/* Remote Frame Request For Mailbox 21	*/
-#define	TRS22		0x0040	/* Remote Frame Request For Mailbox 22	*/
-#define	TRS23		0x0080	/* Remote Frame Request For Mailbox 23	*/
-#define	TRS24		0x0100	/* Remote Frame Request For Mailbox 24	*/
-#define	TRS25		0x0200	/* Remote Frame Request For Mailbox 25	*/
-#define	TRS26		0x0400	/* Remote Frame Request For Mailbox 26	*/
-#define	TRS27		0x0800	/* Remote Frame Request For Mailbox 27	*/
-#define	TRS28		0x1000	/* Remote Frame Request For Mailbox 28	*/
-#define	TRS29		0x2000	/* Remote Frame Request For Mailbox 29	*/
-#define	TRS30		0x4000	/* Remote Frame Request For Mailbox 30	*/
-#define	TRS31		0x8000	/* Remote Frame Request For Mailbox 31	*/
-
-/* CAN_AA1 Masks												*/
-#define	AA0			0x0001	/* Aborted Message In Mailbox 0		*/
-#define	AA1			0x0002	/* Aborted Message In Mailbox 1		*/
-#define	AA2			0x0004	/* Aborted Message In Mailbox 2		*/
-#define	AA3			0x0008	/* Aborted Message In Mailbox 3		*/
-#define	AA4			0x0010	/* Aborted Message In Mailbox 4		*/
-#define	AA5			0x0020	/* Aborted Message In Mailbox 5		*/
-#define	AA6			0x0040	/* Aborted Message In Mailbox 6		*/
-#define	AA7			0x0080	/* Aborted Message In Mailbox 7		*/
-#define	AA8			0x0100	/* Aborted Message In Mailbox 8		*/
-#define	AA9			0x0200	/* Aborted Message In Mailbox 9		*/
-#define	AA10		0x0400	/* Aborted Message In Mailbox 10	*/
-#define	AA11		0x0800	/* Aborted Message In Mailbox 11	*/
-#define	AA12		0x1000	/* Aborted Message In Mailbox 12	*/
-#define	AA13		0x2000	/* Aborted Message In Mailbox 13	*/
-#define	AA14		0x4000	/* Aborted Message In Mailbox 14	*/
-#define	AA15		0x8000	/* Aborted Message In Mailbox 15	*/
-
-/* CAN_AA2 Masks												*/
-#define	AA16		0x0001	/* Aborted Message In Mailbox 16	*/
-#define	AA17		0x0002	/* Aborted Message In Mailbox 17	*/
-#define	AA18		0x0004	/* Aborted Message In Mailbox 18	*/
-#define	AA19		0x0008	/* Aborted Message In Mailbox 19	*/
-#define	AA20		0x0010	/* Aborted Message In Mailbox 20	*/
-#define	AA21		0x0020	/* Aborted Message In Mailbox 21	*/
-#define	AA22		0x0040	/* Aborted Message In Mailbox 22	*/
-#define	AA23		0x0080	/* Aborted Message In Mailbox 23	*/
-#define	AA24		0x0100	/* Aborted Message In Mailbox 24	*/
-#define	AA25		0x0200	/* Aborted Message In Mailbox 25	*/
-#define	AA26		0x0400	/* Aborted Message In Mailbox 26	*/
-#define	AA27		0x0800	/* Aborted Message In Mailbox 27	*/
-#define	AA28		0x1000	/* Aborted Message In Mailbox 28	*/
-#define	AA29		0x2000	/* Aborted Message In Mailbox 29	*/
-#define	AA30		0x4000	/* Aborted Message In Mailbox 30	*/
-#define	AA31		0x8000	/* Aborted Message In Mailbox 31	*/
-
-/* CAN_TA1 Masks													*/
-#define	TA0			0x0001	/* Transmit Successful From Mailbox 0	*/
-#define	TA1			0x0002	/* Transmit Successful From Mailbox 1	*/
-#define	TA2			0x0004	/* Transmit Successful From Mailbox 2	*/
-#define	TA3			0x0008	/* Transmit Successful From Mailbox 3	*/
-#define	TA4			0x0010	/* Transmit Successful From Mailbox 4	*/
-#define	TA5			0x0020	/* Transmit Successful From Mailbox 5	*/
-#define	TA6			0x0040	/* Transmit Successful From Mailbox 6	*/
-#define	TA7			0x0080	/* Transmit Successful From Mailbox 7	*/
-#define	TA8			0x0100	/* Transmit Successful From Mailbox 8	*/
-#define	TA9			0x0200	/* Transmit Successful From Mailbox 9	*/
-#define	TA10		0x0400	/* Transmit Successful From Mailbox 10	*/
-#define	TA11		0x0800	/* Transmit Successful From Mailbox 11	*/
-#define	TA12		0x1000	/* Transmit Successful From Mailbox 12	*/
-#define	TA13		0x2000	/* Transmit Successful From Mailbox 13	*/
-#define	TA14		0x4000	/* Transmit Successful From Mailbox 14	*/
-#define	TA15		0x8000	/* Transmit Successful From Mailbox 15	*/
-
-/* CAN_TA2 Masks													*/
-#define	TA16		0x0001	/* Transmit Successful From Mailbox 16	*/
-#define	TA17		0x0002	/* Transmit Successful From Mailbox 17	*/
-#define	TA18		0x0004	/* Transmit Successful From Mailbox 18	*/
-#define	TA19		0x0008	/* Transmit Successful From Mailbox 19	*/
-#define	TA20		0x0010	/* Transmit Successful From Mailbox 20	*/
-#define	TA21		0x0020	/* Transmit Successful From Mailbox 21	*/
-#define	TA22		0x0040	/* Transmit Successful From Mailbox 22	*/
-#define	TA23		0x0080	/* Transmit Successful From Mailbox 23	*/
-#define	TA24		0x0100	/* Transmit Successful From Mailbox 24	*/
-#define	TA25		0x0200	/* Transmit Successful From Mailbox 25	*/
-#define	TA26		0x0400	/* Transmit Successful From Mailbox 26	*/
-#define	TA27		0x0800	/* Transmit Successful From Mailbox 27	*/
-#define	TA28		0x1000	/* Transmit Successful From Mailbox 28	*/
-#define	TA29		0x2000	/* Transmit Successful From Mailbox 29	*/
-#define	TA30		0x4000	/* Transmit Successful From Mailbox 30	*/
-#define	TA31		0x8000	/* Transmit Successful From Mailbox 31	*/
-
-/* CAN_MBTD Masks												*/
-#define TDPTR		0x001F	/* Mailbox To Temporarily Disable	*/
-#define	TDA			0x0040	/* Temporary Disable Acknowledge	*/
-#define	TDR			0x0080	/* Temporary Disable Request		*/
-
-/* CAN_RFH1 Masks																		*/
-#define	RFH0		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 0		*/
-#define	RFH1		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 1		*/
-#define	RFH2		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 2		*/
-#define	RFH3		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 3		*/
-#define	RFH4		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 4		*/
-#define	RFH5		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 5		*/
-#define	RFH6		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 6		*/
-#define	RFH7		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 7		*/
-#define	RFH8		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 8		*/
-#define	RFH9		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 9		*/
-#define	RFH10		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 10	*/
-#define	RFH11		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 11	*/
-#define	RFH12		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 12	*/
-#define	RFH13		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 13	*/
-#define	RFH14		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 14	*/
-#define	RFH15		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 15	*/
-
-/* CAN_RFH2 Masks																		*/
-#define	RFH16		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 16	*/
-#define	RFH17		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 17	*/
-#define	RFH18		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 18	*/
-#define	RFH19		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 19	*/
-#define	RFH20		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 20	*/
-#define	RFH21		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 21	*/
-#define	RFH22		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 22	*/
-#define	RFH23		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 23	*/
-#define	RFH24		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 24	*/
-#define	RFH25		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 25	*/
-#define	RFH26		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 26	*/
-#define	RFH27		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 27	*/
-#define	RFH28		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 28	*/
-#define	RFH29		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 29	*/
-#define	RFH30		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 30	*/
-#define	RFH31		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 31	*/
-
-/* CAN_MBTIF1 Masks													*/
-#define	MBTIF0		0x0001	/* TX Interrupt Active In Mailbox 0		*/
-#define	MBTIF1		0x0002	/* TX Interrupt Active In Mailbox 1		*/
-#define	MBTIF2		0x0004	/* TX Interrupt Active In Mailbox 2		*/
-#define	MBTIF3		0x0008	/* TX Interrupt Active In Mailbox 3		*/
-#define	MBTIF4		0x0010	/* TX Interrupt Active In Mailbox 4		*/
-#define	MBTIF5		0x0020	/* TX Interrupt Active In Mailbox 5		*/
-#define	MBTIF6		0x0040	/* TX Interrupt Active In Mailbox 6		*/
-#define	MBTIF7		0x0080	/* TX Interrupt Active In Mailbox 7		*/
-#define	MBTIF8		0x0100	/* TX Interrupt Active In Mailbox 8		*/
-#define	MBTIF9		0x0200	/* TX Interrupt Active In Mailbox 9		*/
-#define	MBTIF10		0x0400	/* TX Interrupt Active In Mailbox 10	*/
-#define	MBTIF11		0x0800	/* TX Interrupt Active In Mailbox 11	*/
-#define	MBTIF12		0x1000	/* TX Interrupt Active In Mailbox 12	*/
-#define	MBTIF13		0x2000	/* TX Interrupt Active In Mailbox 13	*/
-#define	MBTIF14		0x4000	/* TX Interrupt Active In Mailbox 14	*/
-#define	MBTIF15		0x8000	/* TX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBTIF2 Masks													*/
-#define	MBTIF16		0x0001	/* TX Interrupt Active In Mailbox 16	*/
-#define	MBTIF17		0x0002	/* TX Interrupt Active In Mailbox 17	*/
-#define	MBTIF18		0x0004	/* TX Interrupt Active In Mailbox 18	*/
-#define	MBTIF19		0x0008	/* TX Interrupt Active In Mailbox 19	*/
-#define	MBTIF20		0x0010	/* TX Interrupt Active In Mailbox 20	*/
-#define	MBTIF21		0x0020	/* TX Interrupt Active In Mailbox 21	*/
-#define	MBTIF22		0x0040	/* TX Interrupt Active In Mailbox 22	*/
-#define	MBTIF23		0x0080	/* TX Interrupt Active In Mailbox 23	*/
-#define	MBTIF24		0x0100	/* TX Interrupt Active In Mailbox 24	*/
-#define	MBTIF25		0x0200	/* TX Interrupt Active In Mailbox 25	*/
-#define	MBTIF26		0x0400	/* TX Interrupt Active In Mailbox 26	*/
-#define	MBTIF27		0x0800	/* TX Interrupt Active In Mailbox 27	*/
-#define	MBTIF28		0x1000	/* TX Interrupt Active In Mailbox 28	*/
-#define	MBTIF29		0x2000	/* TX Interrupt Active In Mailbox 29	*/
-#define	MBTIF30		0x4000	/* TX Interrupt Active In Mailbox 30	*/
-#define	MBTIF31		0x8000	/* TX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBRIF1 Masks													*/
-#define	MBRIF0		0x0001	/* RX Interrupt Active In Mailbox 0		*/
-#define	MBRIF1		0x0002	/* RX Interrupt Active In Mailbox 1		*/
-#define	MBRIF2		0x0004	/* RX Interrupt Active In Mailbox 2		*/
-#define	MBRIF3		0x0008	/* RX Interrupt Active In Mailbox 3		*/
-#define	MBRIF4		0x0010	/* RX Interrupt Active In Mailbox 4		*/
-#define	MBRIF5		0x0020	/* RX Interrupt Active In Mailbox 5		*/
-#define	MBRIF6		0x0040	/* RX Interrupt Active In Mailbox 6		*/
-#define	MBRIF7		0x0080	/* RX Interrupt Active In Mailbox 7		*/
-#define	MBRIF8		0x0100	/* RX Interrupt Active In Mailbox 8		*/
-#define	MBRIF9		0x0200	/* RX Interrupt Active In Mailbox 9		*/
-#define	MBRIF10		0x0400	/* RX Interrupt Active In Mailbox 10	*/
-#define	MBRIF11		0x0800	/* RX Interrupt Active In Mailbox 11	*/
-#define	MBRIF12		0x1000	/* RX Interrupt Active In Mailbox 12	*/
-#define	MBRIF13		0x2000	/* RX Interrupt Active In Mailbox 13	*/
-#define	MBRIF14		0x4000	/* RX Interrupt Active In Mailbox 14	*/
-#define	MBRIF15		0x8000	/* RX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBRIF2 Masks													*/
-#define	MBRIF16		0x0001	/* RX Interrupt Active In Mailbox 16	*/
-#define	MBRIF17		0x0002	/* RX Interrupt Active In Mailbox 17	*/
-#define	MBRIF18		0x0004	/* RX Interrupt Active In Mailbox 18	*/
-#define	MBRIF19		0x0008	/* RX Interrupt Active In Mailbox 19	*/
-#define	MBRIF20		0x0010	/* RX Interrupt Active In Mailbox 20	*/
-#define	MBRIF21		0x0020	/* RX Interrupt Active In Mailbox 21	*/
-#define	MBRIF22		0x0040	/* RX Interrupt Active In Mailbox 22	*/
-#define	MBRIF23		0x0080	/* RX Interrupt Active In Mailbox 23	*/
-#define	MBRIF24		0x0100	/* RX Interrupt Active In Mailbox 24	*/
-#define	MBRIF25		0x0200	/* RX Interrupt Active In Mailbox 25	*/
-#define	MBRIF26		0x0400	/* RX Interrupt Active In Mailbox 26	*/
-#define	MBRIF27		0x0800	/* RX Interrupt Active In Mailbox 27	*/
-#define	MBRIF28		0x1000	/* RX Interrupt Active In Mailbox 28	*/
-#define	MBRIF29		0x2000	/* RX Interrupt Active In Mailbox 29	*/
-#define	MBRIF30		0x4000	/* RX Interrupt Active In Mailbox 30	*/
-#define	MBRIF31		0x8000	/* RX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBIM1 Masks												*/
-#define	MBIM0		0x0001	/* Enable Interrupt For Mailbox 0	*/
-#define	MBIM1		0x0002	/* Enable Interrupt For Mailbox 1	*/
-#define	MBIM2		0x0004	/* Enable Interrupt For Mailbox 2	*/
-#define	MBIM3		0x0008	/* Enable Interrupt For Mailbox 3	*/
-#define	MBIM4		0x0010	/* Enable Interrupt For Mailbox 4	*/
-#define	MBIM5		0x0020	/* Enable Interrupt For Mailbox 5	*/
-#define	MBIM6		0x0040	/* Enable Interrupt For Mailbox 6	*/
-#define	MBIM7		0x0080	/* Enable Interrupt For Mailbox 7	*/
-#define	MBIM8		0x0100	/* Enable Interrupt For Mailbox 8	*/
-#define	MBIM9		0x0200	/* Enable Interrupt For Mailbox 9	*/
-#define	MBIM10		0x0400	/* Enable Interrupt For Mailbox 10	*/
-#define	MBIM11		0x0800	/* Enable Interrupt For Mailbox 11	*/
-#define	MBIM12		0x1000	/* Enable Interrupt For Mailbox 12	*/
-#define	MBIM13		0x2000	/* Enable Interrupt For Mailbox 13	*/
-#define	MBIM14		0x4000	/* Enable Interrupt For Mailbox 14	*/
-#define	MBIM15		0x8000	/* Enable Interrupt For Mailbox 15	*/
-
-/* CAN_MBIM2 Masks												*/
-#define	MBIM16		0x0001	/* Enable Interrupt For Mailbox 16	*/
-#define	MBIM17		0x0002	/* Enable Interrupt For Mailbox 17	*/
-#define	MBIM18		0x0004	/* Enable Interrupt For Mailbox 18	*/
-#define	MBIM19		0x0008	/* Enable Interrupt For Mailbox 19	*/
-#define	MBIM20		0x0010	/* Enable Interrupt For Mailbox 20	*/
-#define	MBIM21		0x0020	/* Enable Interrupt For Mailbox 21	*/
-#define	MBIM22		0x0040	/* Enable Interrupt For Mailbox 22	*/
-#define	MBIM23		0x0080	/* Enable Interrupt For Mailbox 23	*/
-#define	MBIM24		0x0100	/* Enable Interrupt For Mailbox 24	*/
-#define	MBIM25		0x0200	/* Enable Interrupt For Mailbox 25	*/
-#define	MBIM26		0x0400	/* Enable Interrupt For Mailbox 26	*/
-#define	MBIM27		0x0800	/* Enable Interrupt For Mailbox 27	*/
-#define	MBIM28		0x1000	/* Enable Interrupt For Mailbox 28	*/
-#define	MBIM29		0x2000	/* Enable Interrupt For Mailbox 29	*/
-#define	MBIM30		0x4000	/* Enable Interrupt For Mailbox 30	*/
-#define	MBIM31		0x8000	/* Enable Interrupt For Mailbox 31	*/
-
-/* CAN_GIM Masks																*/
-#define	EWTIM		0x0001	/* Enable TX Error Count Interrupt					*/
-#define	EWRIM		0x0002	/* Enable RX Error Count Interrupt					*/
-#define	EPIM		0x0004	/* Enable Error-Passive Mode Interrupt				*/
-#define	BOIM		0x0008	/* Enable Bus Off Interrupt							*/
-#define	WUIM		0x0010	/* Enable Wake-Up Interrupt							*/
-#define	UIAIM		0x0020	/* Enable Access To Unimplemented Address Interrupt	*/
-#define	AAIM		0x0040	/* Enable Abort Acknowledge Interrupt				*/
-#define	RMLIM		0x0080	/* Enable RX Message Lost Interrupt					*/
-#define	UCEIM		0x0100	/* Enable Universal Counter Overflow Interrupt		*/
-#define	EXTIM		0x0200	/* Enable External Trigger Output Interrupt			*/
-#define	ADIM		0x0400	/* Enable Access Denied Interrupt					*/
-
-/* CAN_GIS Masks															*/
-#define	EWTIS		0x0001	/* TX Error Count IRQ Status					*/
-#define	EWRIS		0x0002	/* RX Error Count IRQ Status					*/
-#define	EPIS		0x0004	/* Error-Passive Mode IRQ Status				*/
-#define	BOIS		0x0008	/* Bus Off IRQ Status							*/
-#define	WUIS		0x0010	/* Wake-Up IRQ Status							*/
-#define	UIAIS		0x0020	/* Access To Unimplemented Address IRQ Status	*/
-#define	AAIS		0x0040	/* Abort Acknowledge IRQ Status					*/
-#define	RMLIS		0x0080	/* RX Message Lost IRQ Status					*/
-#define	UCEIS		0x0100	/* Universal Counter Overflow IRQ Status		*/
-#define	EXTIS		0x0200	/* External Trigger Output IRQ Status			*/
-#define	ADIS		0x0400	/* Access Denied IRQ Status						*/
-
-/* CAN_GIF Masks															*/
-#define	EWTIF		0x0001	/* TX Error Count IRQ Flag						*/
-#define	EWRIF		0x0002	/* RX Error Count IRQ Flag						*/
-#define	EPIF		0x0004	/* Error-Passive Mode IRQ Flag					*/
-#define	BOIF		0x0008	/* Bus Off IRQ Flag								*/
-#define	WUIF		0x0010	/* Wake-Up IRQ Flag								*/
-#define	UIAIF		0x0020	/* Access To Unimplemented Address IRQ Flag		*/
-#define	AAIF		0x0040	/* Abort Acknowledge IRQ Flag					*/
-#define	RMLIF		0x0080	/* RX Message Lost IRQ Flag						*/
-#define	UCEIF		0x0100	/* Universal Counter Overflow IRQ Flag			*/
-#define	EXTIF		0x0200	/* External Trigger Output IRQ Flag				*/
-#define	ADIF		0x0400	/* Access Denied IRQ Flag						*/
-
-/* CAN_UCCNF Masks															*/
-#define	UCCNF		0x000F	/* Universal Counter Mode						*/
-#define UC_STAMP	0x0001	/* 		Timestamp Mode							*/
-#define UC_WDOG		0x0002	/* 		Watchdog Mode							*/
-#define UC_AUTOTX	0x0003	/* 		Auto-Transmit Mode						*/
-#define UC_ERROR	0x0006	/* 		CAN Error Frame Count					*/
-#define UC_OVER		0x0007	/* 		CAN Overload Frame Count				*/
-#define UC_LOST		0x0008	/* 		Arbitration Lost During TX Count		*/
-#define UC_AA		0x0009	/* 		TX Abort Count							*/
-#define UC_TA		0x000A	/* 		TX Successful Count						*/
-#define UC_REJECT	0x000B	/* 		RX Message Rejected Count				*/
-#define UC_RML		0x000C	/* 		RX Message Lost Count					*/
-#define UC_RX		0x000D	/* 		Total Successful RX Messages Count		*/
-#define UC_RMP		0x000E	/* 		Successful RX W/Matching ID Count		*/
-#define UC_ALL		0x000F	/* 		Correct Message On CAN Bus Line Count	*/
-#define	UCRC		0x0020	/* Universal Counter Reload/Clear				*/
-#define	UCCT		0x0040	/* Universal Counter CAN Trigger				*/
-#define	UCE			0x0080	/* Universal Counter Enable						*/
-
-/* CAN_ESR Masks										*/
-#define	ACKE		0x0004	/* Acknowledge Error		*/
-#define	SER			0x0008	/* Stuff Error				*/
-#define	CRCE		0x0010	/* CRC Error				*/
-#define	SA0			0x0020	/* Stuck At Dominant Error	*/
-#define	BEF			0x0040	/* Bit Error Flag			*/
-#define	FER			0x0080	/* Form Error Flag			*/
-
-/* CAN_EWR Masks												*/
-#define	EWLREC		0x00FF	/* RX Error Count Limit (For EWRIS)	*/
-#define	EWLTEC		0xFF00	/* TX Error Count Limit (For EWTIS)	*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define CAN_CNF          CAN_DEBUG
-#define TWI0_PRESCALE    TWI0_CONTROL
-#define TWI0_INT_SRC     TWI0_INT_STAT
-#define TWI0_INT_ENABLE  TWI0_INT_MASK
-#define TWI1_PRESCALE     TWI1_CONTROL
-#define TWI1_INT_SRC      TWI1_INT_STAT
-#define TWI1_INT_ENABLE   TWI1_INT_MASK
-#define TOVL_ERR0        TOVF_ERR0
-#define TOVL_ERR1        TOVF_ERR1
-#define TOVL_ERR2        TOVF_ERR2
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF538_H */
diff --git a/libgloss/bfin/include/defBF539.h b/libgloss/bfin/include/defBF539.h
deleted file mode 100644
index daae30223..000000000
--- a/libgloss/bfin/include/defBF539.h
+++ /dev/null
@@ -1,4344 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for Stirling peripherals.
-**
-*/
-#ifndef _DEF_BF539_H
-#define _DEF_BF539_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL			0xFFC00000  /* PLL Control register (16-bit) */
-#define PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
-#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT		0xFFC0000C  /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT		0xFFC00010  /* PLL Lock Count register (16-bit) */
-#define	CHIPID			0xFFC00014	/* Chip ID Register						*/
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST			0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR			0xFFC00104  /* System Configuration registe */
-#define SIC_IMASK0		0xFFC0010C  /* Interrupt Mask Register */
-#define SIC_IAR0		0xFFC00110  /* Interrupt Assignment Register 0 */
-#define SIC_IAR1		0xFFC00114  /* Interrupt Assignment Register 1 */
-#define SIC_IAR2		0xFFC00118  /* Interrupt Assignment Register 2 */
-#define SIC_IAR3			0xFFC0011C	/* Interrupt Assignment Register 3		*/
-#define SIC_ISR0			0xFFC00120  /* Interrupt Status Register */
-#define SIC_IWR0			0xFFC00124  /* Interrupt Wakeup Register */
-#define SIC_IMASK1			0xFFC00128	/* Interrupt Mask Register 1			*/
-#define SIC_ISR1			0xFFC0012C	/* Interrupt Status Register 1			*/
-#define SIC_IWR1			0xFFC00130	/* Interrupt Wakeup Register 1			*/
-#define SIC_IAR4			0xFFC00134	/* Interrupt Assignment Register 4		*/
-#define SIC_IAR5			0xFFC00138	/* Interrupt Assignment Register 5		*/
-#define SIC_IAR6			0xFFC0013C	/* Interrupt Assignment Register 6		*/
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
-#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
-#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT        0xFFC00300  /* RTC Status Register */
-#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
-#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
-#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
-#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
-#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
-#define RTC_PREN		0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR             0xFFC00400  /* Transmit Holding register */
-#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
-#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
-#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
-#define UART0_LCR             0xFFC0040C  /* Line Control Register */
-#define UART0_MCR			 0xFFC00410  /* Modem Control Register */
-#define UART0_LSR             0xFFC00414  /* Line Status Register */
-#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
-#define UART0_GCTL      	     0xFFC00424  /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_CTL               		0xFFC00500  /* SPI0 Control Register */
-#define SPI0_FLG               		0xFFC00504  /* SPI0 Flag register */
-#define SPI0_STAT              		0xFFC00508  /* SPI0 Status register */
-#define SPI0_TDBR              		0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR              		0xFFC00510  /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD              		0xFFC00514  /* SPI0 Baud rate Register */
-#define SPI0_SHADOW            		0xFFC00518  /* SPI0_RDBR Shadow Register */
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG          		0xFFC00600     /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER				0xFFC00604     /* Timer 0 Counter Register */
-#define TIMER0_PERIOD       		0xFFC00608     /* Timer 0 Period Register */
-#define TIMER0_WIDTH        		0xFFC0060C     /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG          		0xFFC00610  	/*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER         		0xFFC00614   	/*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD          		0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH           		0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG          		0xFFC00620  	/* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER         		0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD          		0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH           		0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE				0xFFC00640   	/* Timer Enable Register */
-#define TIMER_DISABLE				0xFFC00644   	/* Timer Disable Register */
-#define TIMER_STATUS				0xFFC00648   	/* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D	       			0xFFC00700  /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C             		0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S             		0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T					0xFFC0070C  /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D            		0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C            		0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S            		0xFFC00718  /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T            		0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D            		0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C            		0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S            		0xFFC00728  /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T            		0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                		0xFFC00730  /* Peripheral Flag Direction Register */
-#define FIO_POLAR              		0xFFC00734  /* Flag Source Polarity Register */
-#define FIO_EDGE               		0xFFC00738  /* Flag Source Sensitivity Register */
-#define FIO_BOTH               		0xFFC0073C  /* Flag Set on BOTH Edges Register */
-#define FIO_INEN					0xFFC00740  /* Flag Input Enable Register  */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1     	 		0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2      	 		0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV        		0xFFC00808  /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV          		0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX	             	0xFFC00810  /* SPORT0 TX Data Register */
-#define SPORT0_RX	            	0xFFC00818  /* SPORT0 RX Data Register */
-#define SPORT0_RCR1      	 		0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2      	 		0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV        		0xFFC00828  /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV          		0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT            		0xFFC00830  /* SPORT0 Status Register */
-#define SPORT0_CHNL            		0xFFC00834  /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1           		0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2           		0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0           		0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1           		0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2           		0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3           		0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0           		0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1           		0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2           		0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3           		0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1     	 		0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2      	 		0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV        		0xFFC00908  /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV          		0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX	             	0xFFC00910  /* SPORT1 TX Data Register */
-#define SPORT1_RX	            	0xFFC00918  /* SPORT1 RX Data Register */
-#define SPORT1_RCR1      	 		0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2      	 		0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV        		0xFFC00928  /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV          		0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT            		0xFFC00930  /* SPORT1 Status Register */
-#define SPORT1_CHNL            		0xFFC00934  /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1           		0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2           		0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0           		0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1           		0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2           		0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3           		0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0           		0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1           		0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2           		0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3           		0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller  */
-#define EBIU_AMGCTL			0xFFC00A00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0		0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1		0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL			0xFFC00A10  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL			0xFFC00A14  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 			0xFFC00A18  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT			0xFFC00A1C  /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER 			0xFFC00B0C	/* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT 			0xFFC00B10	/* DMA Controller 0 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA0_TCPER 		        DMAC0_TC_PER
-#define DMA0_TCCNT 		 	DMAC0_TC_CNT
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)														*/
-
-#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/
-#define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
-#define DMA0_CONFIG				0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
-#define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
-#define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
-#define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
-#define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
-#define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register	*/
-#define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register				*/
-#define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
-#define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register				*/
-#define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register				*/
-#define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register				*/
-
-#define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register		*/
-#define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
-#define DMA1_CONFIG				0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
-#define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
-#define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
-#define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
-#define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
-#define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register	*/
-#define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register				*/
-#define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
-#define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register				*/
-#define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register				*/
-#define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register				*/
-
-#define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register		*/
-#define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
-#define DMA2_CONFIG				0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
-#define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
-#define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
-#define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
-#define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
-#define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register	*/
-#define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register				*/
-#define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
-#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register				*/
-#define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register				*/
-#define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register				*/
-
-#define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register		*/
-#define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
-#define DMA3_CONFIG				0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
-#define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
-#define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
-#define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
-#define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
-#define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register	*/
-#define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register				*/
-#define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
-#define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register				*/
-#define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register				*/
-#define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register				*/
-
-#define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register		*/
-#define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
-#define DMA4_CONFIG				0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
-#define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
-#define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
-#define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
-#define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
-#define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register	*/
-#define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register				*/
-#define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
-#define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register				*/
-#define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register				*/
-#define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register				*/
-
-#define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register		*/
-#define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
-#define DMA5_CONFIG				0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
-#define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
-#define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
-#define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
-#define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
-#define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register	*/
-#define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register				*/
-#define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
-#define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register				*/
-#define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register				*/
-#define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register				*/
-
-#define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register		*/
-#define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
-#define DMA6_CONFIG				0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
-#define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
-#define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
-#define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
-#define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
-#define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register	*/
-#define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register				*/
-#define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
-#define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register				*/
-#define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register				*/
-#define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register				*/
-
-#define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register		*/
-#define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
-#define DMA7_CONFIG				0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
-#define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
-#define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
-#define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
-#define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
-#define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register	*/
-#define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register				*/
-#define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
-#define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register				*/
-#define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register				*/
-#define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register				*/
-
-#define MDMA0_D0_NEXT_DESC_PTR	0xFFC00E00	/* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA0_D0_START_ADDR		0xFFC00E04	/* MemDMA0 Stream 0 Destination Start Address Register				*/
-#define MDMA0_D0_CONFIG			0xFFC00E08	/* MemDMA0 Stream 0 Destination Configuration Register				*/
-#define MDMA0_D0_X_COUNT		0xFFC00E10	/* MemDMA0 Stream 0 Destination X Count Register						*/
-#define MDMA0_D0_X_MODIFY		0xFFC00E14	/* MemDMA0 Stream 0 Destination X Modify Register					*/
-#define MDMA0_D0_Y_COUNT		0xFFC00E18	/* MemDMA0 Stream 0 Destination Y Count Register						*/
-#define MDMA0_D0_Y_MODIFY		0xFFC00E1C	/* MemDMA0 Stream 0 Destination Y Modify Register					*/
-#define MDMA0_D0_CURR_DESC_PTR	0xFFC00E20	/* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA0_D0_CURR_ADDR		0xFFC00E24	/* MemDMA0 Stream 0 Destination Current Address Register				*/
-#define MDMA0_D0_IRQ_STATUS		0xFFC00E28	/* MemDMA0 Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA0_D0_PERIPHERAL_MAP	0xFFC00E2C	/* MemDMA0 Stream 0 Destination Peripheral Map Register				*/
-#define MDMA0_D0_CURR_X_COUNT	0xFFC00E30	/* MemDMA0 Stream 0 Destination Current X Count Register				*/
-#define MDMA0_D0_CURR_Y_COUNT	0xFFC00E38	/* MemDMA0 Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA0_S0_NEXT_DESC_PTR	0xFFC00E40	/* MemDMA0 Stream 0 Source Next Descriptor Pointer Register			*/
-#define MDMA0_S0_START_ADDR		0xFFC00E44	/* MemDMA0 Stream 0 Source Start Address Register					*/
-#define MDMA0_S0_CONFIG			0xFFC00E48	/* MemDMA0 Stream 0 Source Configuration Register					*/
-#define MDMA0_S0_X_COUNT		0xFFC00E50	/* MemDMA0 Stream 0 Source X Count Register							*/
-#define MDMA0_S0_X_MODIFY		0xFFC00E54	/* MemDMA0 Stream 0 Source X Modify Register							*/
-#define MDMA0_S0_Y_COUNT		0xFFC00E58	/* MemDMA0 Stream 0 Source Y Count Register							*/
-#define MDMA0_S0_Y_MODIFY		0xFFC00E5C	/* MemDMA0 Stream 0 Source Y Modify Register							*/
-#define MDMA0_S0_CURR_DESC_PTR	0xFFC00E60	/* MemDMA0 Stream 0 Source Current Descriptor Pointer Register		*/
-#define MDMA0_S0_CURR_ADDR		0xFFC00E64	/* MemDMA0 Stream 0 Source Current Address Register					*/
-#define MDMA0_S0_IRQ_STATUS		0xFFC00E68	/* MemDMA0 Stream 0 Source Interrupt/Status Register					*/
-#define MDMA0_S0_PERIPHERAL_MAP	0xFFC00E6C	/* MemDMA0 Stream 0 Source Peripheral Map Register					*/
-#define MDMA0_S0_CURR_X_COUNT	0xFFC00E70	/* MemDMA0 Stream 0 Source Current X Count Register					*/
-#define MDMA0_S0_CURR_Y_COUNT	0xFFC00E78	/* MemDMA0 Stream 0 Source Current Y Count Register					*/
-
-#define MDMA0_D1_NEXT_DESC_PTR	0xFFC00E80	/* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA0_D1_START_ADDR		0xFFC00E84	/* MemDMA0 Stream 1 Destination Start Address Register				*/
-#define MDMA0_D1_CONFIG			0xFFC00E88	/* MemDMA0 Stream 1 Destination Configuration Register				*/
-#define MDMA0_D1_X_COUNT		0xFFC00E90	/* MemDMA0 Stream 1 Destination X Count Register						*/
-#define MDMA0_D1_X_MODIFY		0xFFC00E94	/* MemDMA0 Stream 1 Destination X Modify Register					*/
-#define MDMA0_D1_Y_COUNT		0xFFC00E98	/* MemDMA0 Stream 1 Destination Y Count Register						*/
-#define MDMA0_D1_Y_MODIFY		0xFFC00E9C	/* MemDMA0 Stream 1 Destination Y Modify Register					*/
-#define MDMA0_D1_CURR_DESC_PTR	0xFFC00EA0	/* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA0_D1_CURR_ADDR		0xFFC00EA4	/* MemDMA0 Stream 1 Destination Current Address Register				*/
-#define MDMA0_D1_IRQ_STATUS		0xFFC00EA8	/* MemDMA0 Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA0_D1_PERIPHERAL_MAP	0xFFC00EAC	/* MemDMA0 Stream 1 Destination Peripheral Map Register				*/
-#define MDMA0_D1_CURR_X_COUNT	0xFFC00EB0	/* MemDMA0 Stream 1 Destination Current X Count Register				*/
-#define MDMA0_D1_CURR_Y_COUNT	0xFFC00EB8	/* MemDMA0 Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA0_S1_NEXT_DESC_PTR	0xFFC00EC0	/* MemDMA0 Stream 1 Source Next Descriptor Pointer Register			*/
-#define MDMA0_S1_START_ADDR		0xFFC00EC4	/* MemDMA0 Stream 1 Source Start Address Register					*/
-#define MDMA0_S1_CONFIG			0xFFC00EC8	/* MemDMA0 Stream 1 Source Configuration Register					*/
-#define MDMA0_S1_X_COUNT		0xFFC00ED0	/* MemDMA0 Stream 1 Source X Count Register							*/
-#define MDMA0_S1_X_MODIFY		0xFFC00ED4	/* MemDMA0 Stream 1 Source X Modify Register							*/
-#define MDMA0_S1_Y_COUNT		0xFFC00ED8	/* MemDMA0 Stream 1 Source Y Count Register							*/
-#define MDMA0_S1_Y_MODIFY		0xFFC00EDC	/* MemDMA0 Stream 1 Source Y Modify Register							*/
-#define MDMA0_S1_CURR_DESC_PTR	0xFFC00EE0	/* MemDMA0 Stream 1 Source Current Descriptor Pointer Register		*/
-#define MDMA0_S1_CURR_ADDR		0xFFC00EE4	/* MemDMA0 Stream 1 Source Current Address Register					*/
-#define MDMA0_S1_IRQ_STATUS		0xFFC00EE8	/* MemDMA0 Stream 1 Source Interrupt/Status Register					*/
-#define MDMA0_S1_PERIPHERAL_MAP	0xFFC00EEC	/* MemDMA0 Stream 1 Source Peripheral Map Register					*/
-#define MDMA0_S1_CURR_X_COUNT	0xFFC00EF0	/* MemDMA0 Stream 1 Source Current X Count Register					*/
-#define MDMA0_S1_CURR_Y_COUNT	0xFFC00EF8	/* MemDMA0 Stream 1 Source Current Y Count Register					*/
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register */
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register */
-#define PPI_COUNT			0xFFC01008	/* PPI Transfer Count Register */
-#define PPI_DELAY			0xFFC0100C	/* PPI Delay Count Register */
-#define PPI_FRAME			0xFFC01010	/* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0	(0xFFC01400 - 0xFFC014FF)										*/
-#define TWI0_CLKDIV			0xFFC01400	/* Serial Clock Divider Register				*/
-#define TWI0_CONTROL		0xFFC01404	/* TWI0 Master Internal Time Reference Register	*/
-#define TWI0_SLAVE_CTRL		0xFFC01408	/* Slave Mode Control Register					*/
-#define TWI0_SLAVE_STAT		0xFFC0140C	/* Slave Mode Status Register					*/
-#define TWI0_SLAVE_ADDR		0xFFC01410	/* Slave Mode Address Register					*/
-#define TWI0_MASTER_CTRL	0xFFC01414	/* Master Mode Control Register					*/
-#define TWI0_MASTER_STAT	0xFFC01418	/* Master Mode Status Register					*/
-#define TWI0_MASTER_ADDR	0xFFC0141C	/* Master Mode Address Register					*/
-#define TWI0_INT_STAT		0xFFC01420	/* TWI0 Master Interrupt Register				*/
-#define TWI0_INT_MASK		0xFFC01424	/* TWI0 Master Interrupt Mask Register			*/
-#define TWI0_FIFO_CTRL		0xFFC01428	/* FIFO Control Register						*/
-#define TWI0_FIFO_STAT		0xFFC0142C	/* FIFO Status Register							*/
-#define TWI0_XMT_DATA8		0xFFC01480	/* FIFO Transmit Data Single Byte Register		*/
-#define TWI0_XMT_DATA16		0xFFC01484	/* FIFO Transmit Data Double Byte Register		*/
-#define TWI0_RCV_DATA8		0xFFC01488	/* FIFO Receive Data Single Byte Register		*/
-#define TWI0_RCV_DATA16		0xFFC0148C	/* FIFO Receive Data Double Byte Register		*/
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE    TWI0_CONTROL
-#define TWI0_INT_SRC     TWI0_INT_STAT
-#define TWI0_INT_ENABLE  TWI0_INT_MASK
-
-
-/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)								*/
-
-/* GPIO Port C Register Names */
-#define GPIO_C_CNFG			0xFFC01500	/* GPIO Pin Port C Configuration Register	*/
-#define GPIO_C_D			0xFFC01510	/* GPIO Pin Port C Data Register			*/
-#define GPIO_C_C			0xFFC01520	/* Clear GPIO Pin Port C Register			*/
-#define GPIO_C_S			0xFFC01530	/* Set GPIO Pin Port C Register				*/
-#define GPIO_C_T			0xFFC01540	/* Toggle GPIO Pin Port C Register			*/
-#define GPIO_C_DIR			0xFFC01550	/* GPIO Pin Port C Direction Register		*/
-#define GPIO_C_INEN			0xFFC01560	/* GPIO Pin Port C Input Enable Register	*/
-
-/* GPIO Port D Register Names */
-#define GPIO_D_CNFG			0xFFC01504	/* GPIO Pin Port D Configuration Register	*/
-#define GPIO_D_D			0xFFC01514	/* GPIO Pin Port D Data Register			*/
-#define GPIO_D_C			0xFFC01524	/* Clear GPIO Pin Port D Register			*/
-#define GPIO_D_S			0xFFC01534	/* Set GPIO Pin Port D Register				*/
-#define GPIO_D_T			0xFFC01544	/* Toggle GPIO Pin Port D Register			*/
-#define GPIO_D_DIR			0xFFC01554	/* GPIO Pin Port D Direction Register		*/
-#define GPIO_D_INEN			0xFFC01564	/* GPIO Pin Port D Input Enable Register	*/
-
-/* GPIO Port E Register Names */
-#define GPIO_E_CNFG			0xFFC01508	/* GPIO Pin Port E Configuration Register	*/
-#define GPIO_E_D			0xFFC01518	/* GPIO Pin Port E Data Register			*/
-#define GPIO_E_C			0xFFC01528	/* Clear GPIO Pin Port E Register			*/
-#define GPIO_E_S			0xFFC01538	/* Set GPIO Pin Port E Register				*/
-#define GPIO_E_T			0xFFC01548	/* Toggle GPIO Pin Port E Register			*/
-#define GPIO_E_DIR			0xFFC01558	/* GPIO Pin Port E Direction Register		*/
-#define GPIO_E_INEN			0xFFC01568	/* GPIO Pin Port E Input Enable Register	*/
-
-/* Deprecate old macros */
-#define GPIO_C_DAT GPIO_C_D
-#define GPIO_C_CLR GPIO_C_C
-#define GPIO_C_SET GPIO_C_S
-#define GPIO_C_TGL GPIO_C_T
-
-#define GPIO_D_DAT GPIO_D_D
-#define GPIO_D_CLR GPIO_D_C
-#define GPIO_D_SET GPIO_D_S
-#define GPIO_D_TGL GPIO_D_T
-
-#define GPIO_E_DAT GPIO_E_D
-#define GPIO_E_CLR GPIO_E_C
-#define GPIO_E_SET GPIO_E_S
-#define GPIO_E_TGL GPIO_E_T
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER			0xFFC01B0C	/* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT			0xFFC01B10	/* DMA Controller 1 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA1_TCPER			DMAC1_TC_PER
-#define DMA1_TCCNT			DMAC1_TC_CNT
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)														*/
-#define DMA8_NEXT_DESC_PTR		0xFFC01C00	/* DMA Channel 8 Next Descriptor Pointer Register		*/
-#define DMA8_START_ADDR			0xFFC01C04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG				0xFFC01C08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC01C10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC01C14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC01C18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC01C1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC01C20	/* DMA Channel 8 Current Descriptor Pointer Register	*/
-#define DMA8_CURR_ADDR			0xFFC01C24	/* DMA Channel 8 Current Address Register				*/
-#define DMA8_IRQ_STATUS			0xFFC01C28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC01C2C	/* DMA Channel 8 Peripheral Map Register				*/
-#define DMA8_CURR_X_COUNT		0xFFC01C30	/* DMA Channel 8 Current X Count Register				*/
-#define DMA8_CURR_Y_COUNT		0xFFC01C38	/* DMA Channel 8 Current Y Count Register				*/
-
-#define DMA9_NEXT_DESC_PTR		0xFFC01C40	/* DMA Channel 9 Next Descriptor Pointer Register		*/
-#define DMA9_START_ADDR			0xFFC01C44	/* DMA Channel 9 Start Address Register					*/
-#define DMA9_CONFIG				0xFFC01C48	/* DMA Channel 9 Configuration Register					*/
-#define DMA9_X_COUNT			0xFFC01C50	/* DMA Channel 9 X Count Register						*/
-#define DMA9_X_MODIFY			0xFFC01C54	/* DMA Channel 9 X Modify Register						*/
-#define DMA9_Y_COUNT			0xFFC01C58	/* DMA Channel 9 Y Count Register						*/
-#define DMA9_Y_MODIFY			0xFFC01C5C	/* DMA Channel 9 Y Modify Register						*/
-#define DMA9_CURR_DESC_PTR		0xFFC01C60	/* DMA Channel 9 Current Descriptor Pointer Register	*/
-#define DMA9_CURR_ADDR			0xFFC01C64	/* DMA Channel 9 Current Address Register				*/
-#define DMA9_IRQ_STATUS			0xFFC01C68	/* DMA Channel 9 Interrupt/Status Register				*/
-#define DMA9_PERIPHERAL_MAP		0xFFC01C6C	/* DMA Channel 9 Peripheral Map Register				*/
-#define DMA9_CURR_X_COUNT		0xFFC01C70	/* DMA Channel 9 Current X Count Register				*/
-#define DMA9_CURR_Y_COUNT		0xFFC01C78	/* DMA Channel 9 Current Y Count Register				*/
-
-#define DMA10_NEXT_DESC_PTR		0xFFC01C80	/* DMA Channel 10 Next Descriptor Pointer Register		*/
-#define DMA10_START_ADDR		0xFFC01C84	/* DMA Channel 10 Start Address Register				*/
-#define DMA10_CONFIG			0xFFC01C88	/* DMA Channel 10 Configuration Register				*/
-#define DMA10_X_COUNT			0xFFC01C90	/* DMA Channel 10 X Count Register						*/
-#define DMA10_X_MODIFY			0xFFC01C94	/* DMA Channel 10 X Modify Register						*/
-#define DMA10_Y_COUNT			0xFFC01C98	/* DMA Channel 10 Y Count Register						*/
-#define DMA10_Y_MODIFY			0xFFC01C9C	/* DMA Channel 10 Y Modify Register						*/
-#define DMA10_CURR_DESC_PTR		0xFFC01CA0	/* DMA Channel 10 Current Descriptor Pointer Register	*/
-#define DMA10_CURR_ADDR			0xFFC01CA4	/* DMA Channel 10 Current Address Register				*/
-#define DMA10_IRQ_STATUS		0xFFC01CA8	/* DMA Channel 10 Interrupt/Status Register				*/
-#define DMA10_PERIPHERAL_MAP	0xFFC01CAC	/* DMA Channel 10 Peripheral Map Register				*/
-#define DMA10_CURR_X_COUNT		0xFFC01CB0	/* DMA Channel 10 Current X Count Register				*/
-#define DMA10_CURR_Y_COUNT		0xFFC01CB8	/* DMA Channel 10 Current Y Count Register				*/
-
-#define DMA11_NEXT_DESC_PTR		0xFFC01CC0	/* DMA Channel 11 Next Descriptor Pointer Register		*/
-#define DMA11_START_ADDR		0xFFC01CC4	/* DMA Channel 11 Start Address Register				*/
-#define DMA11_CONFIG			0xFFC01CC8	/* DMA Channel 11 Configuration Register				*/
-#define DMA11_X_COUNT			0xFFC01CD0	/* DMA Channel 11 X Count Register						*/
-#define DMA11_X_MODIFY			0xFFC01CD4	/* DMA Channel 11 X Modify Register						*/
-#define DMA11_Y_COUNT			0xFFC01CD8	/* DMA Channel 11 Y Count Register						*/
-#define DMA11_Y_MODIFY			0xFFC01CDC	/* DMA Channel 11 Y Modify Register						*/
-#define DMA11_CURR_DESC_PTR		0xFFC01CE0	/* DMA Channel 11 Current Descriptor Pointer Register	*/
-#define DMA11_CURR_ADDR			0xFFC01CE4	/* DMA Channel 11 Current Address Register				*/
-#define DMA11_IRQ_STATUS		0xFFC01CE8	/* DMA Channel 11 Interrupt/Status Register				*/
-#define DMA11_PERIPHERAL_MAP	0xFFC01CEC	/* DMA Channel 11 Peripheral Map Register				*/
-#define DMA11_CURR_X_COUNT		0xFFC01CF0	/* DMA Channel 11 Current X Count Register				*/
-#define DMA11_CURR_Y_COUNT		0xFFC01CF8	/* DMA Channel 11 Current Y Count Register				*/
-
-#define DMA12_NEXT_DESC_PTR		0xFFC01D00	/* DMA Channel 12 Next Descriptor Pointer Register		*/
-#define DMA12_START_ADDR		0xFFC01D04	/* DMA Channel 12 Start Address Register				*/
-#define DMA12_CONFIG			0xFFC01D08	/* DMA Channel 12 Configuration Register				*/
-#define DMA12_X_COUNT			0xFFC01D10	/* DMA Channel 12 X Count Register						*/
-#define DMA12_X_MODIFY			0xFFC01D14	/* DMA Channel 12 X Modify Register						*/
-#define DMA12_Y_COUNT			0xFFC01D18	/* DMA Channel 12 Y Count Register						*/
-#define DMA12_Y_MODIFY			0xFFC01D1C	/* DMA Channel 12 Y Modify Register						*/
-#define DMA12_CURR_DESC_PTR		0xFFC01D20	/* DMA Channel 12 Current Descriptor Pointer Register	*/
-#define DMA12_CURR_ADDR			0xFFC01D24	/* DMA Channel 12 Current Address Register				*/
-#define DMA12_IRQ_STATUS		0xFFC01D28	/* DMA Channel 12 Interrupt/Status Register				*/
-#define DMA12_PERIPHERAL_MAP	0xFFC01D2C	/* DMA Channel 12 Peripheral Map Register				*/
-#define DMA12_CURR_X_COUNT		0xFFC01D30	/* DMA Channel 12 Current X Count Register				*/
-#define DMA12_CURR_Y_COUNT		0xFFC01D38	/* DMA Channel 12 Current Y Count Register				*/
-
-#define DMA13_NEXT_DESC_PTR		0xFFC01D40	/* DMA Channel 13 Next Descriptor Pointer Register		*/
-#define DMA13_START_ADDR		0xFFC01D44	/* DMA Channel 13 Start Address Register				*/
-#define DMA13_CONFIG			0xFFC01D48	/* DMA Channel 13 Configuration Register				*/
-#define DMA13_X_COUNT			0xFFC01D50	/* DMA Channel 13 X Count Register						*/
-#define DMA13_X_MODIFY			0xFFC01D54	/* DMA Channel 13 X Modify Register						*/
-#define DMA13_Y_COUNT			0xFFC01D58	/* DMA Channel 13 Y Count Register						*/
-#define DMA13_Y_MODIFY			0xFFC01D5C	/* DMA Channel 13 Y Modify Register						*/
-#define DMA13_CURR_DESC_PTR		0xFFC01D60	/* DMA Channel 13 Current Descriptor Pointer Register	*/
-#define DMA13_CURR_ADDR			0xFFC01D64	/* DMA Channel 13 Current Address Register				*/
-#define DMA13_IRQ_STATUS		0xFFC01D68	/* DMA Channel 13 Interrupt/Status Register				*/
-#define DMA13_PERIPHERAL_MAP	0xFFC01D6C	/* DMA Channel 13 Peripheral Map Register				*/
-#define DMA13_CURR_X_COUNT		0xFFC01D70	/* DMA Channel 13 Current X Count Register				*/
-#define DMA13_CURR_Y_COUNT		0xFFC01D78	/* DMA Channel 13 Current Y Count Register				*/
-
-#define DMA14_NEXT_DESC_PTR		0xFFC01D80	/* DMA Channel 14 Next Descriptor Pointer Register		*/
-#define DMA14_START_ADDR		0xFFC01D84	/* DMA Channel 14 Start Address Register				*/
-#define DMA14_CONFIG			0xFFC01D88	/* DMA Channel 14 Configuration Register				*/
-#define DMA14_X_COUNT			0xFFC01D90	/* DMA Channel 14 X Count Register						*/
-#define DMA14_X_MODIFY			0xFFC01D94	/* DMA Channel 14 X Modify Register						*/
-#define DMA14_Y_COUNT			0xFFC01D98	/* DMA Channel 14 Y Count Register						*/
-#define DMA14_Y_MODIFY			0xFFC01D9C	/* DMA Channel 14 Y Modify Register						*/
-#define DMA14_CURR_DESC_PTR		0xFFC01DA0	/* DMA Channel 14 Current Descriptor Pointer Register	*/
-#define DMA14_CURR_ADDR			0xFFC01DA4	/* DMA Channel 14 Current Address Register				*/
-#define DMA14_IRQ_STATUS		0xFFC01DA8	/* DMA Channel 14 Interrupt/Status Register				*/
-#define DMA14_PERIPHERAL_MAP	0xFFC01DAC	/* DMA Channel 14 Peripheral Map Register				*/
-#define DMA14_CURR_X_COUNT		0xFFC01DB0	/* DMA Channel 14 Current X Count Register				*/
-#define DMA14_CURR_Y_COUNT		0xFFC01DB8	/* DMA Channel 14 Current Y Count Register				*/
-
-#define DMA15_NEXT_DESC_PTR		0xFFC01DC0	/* DMA Channel 15 Next Descriptor Pointer Register		*/
-#define DMA15_START_ADDR		0xFFC01DC4	/* DMA Channel 15 Start Address Register				*/
-#define DMA15_CONFIG			0xFFC01DC8	/* DMA Channel 15 Configuration Register				*/
-#define DMA15_X_COUNT			0xFFC01DD0	/* DMA Channel 15 X Count Register						*/
-#define DMA15_X_MODIFY			0xFFC01DD4	/* DMA Channel 15 X Modify Register						*/
-#define DMA15_Y_COUNT			0xFFC01DD8	/* DMA Channel 15 Y Count Register						*/
-#define DMA15_Y_MODIFY			0xFFC01DDC	/* DMA Channel 15 Y Modify Register						*/
-#define DMA15_CURR_DESC_PTR		0xFFC01DE0	/* DMA Channel 15 Current Descriptor Pointer Register	*/
-#define DMA15_CURR_ADDR			0xFFC01DE4	/* DMA Channel 15 Current Address Register				*/
-#define DMA15_IRQ_STATUS		0xFFC01DE8	/* DMA Channel 15 Interrupt/Status Register				*/
-#define DMA15_PERIPHERAL_MAP	0xFFC01DEC	/* DMA Channel 15 Peripheral Map Register				*/
-#define DMA15_CURR_X_COUNT		0xFFC01DF0	/* DMA Channel 15 Current X Count Register				*/
-#define DMA15_CURR_Y_COUNT		0xFFC01DF8	/* DMA Channel 15 Current Y Count Register				*/
-
-#define DMA16_NEXT_DESC_PTR		0xFFC01E00	/* DMA Channel 16 Next Descriptor Pointer Register		*/
-#define DMA16_START_ADDR		0xFFC01E04	/* DMA Channel 16 Start Address Register				*/
-#define DMA16_CONFIG			0xFFC01E08	/* DMA Channel 16 Configuration Register				*/
-#define DMA16_X_COUNT			0xFFC01E10	/* DMA Channel 16 X Count Register						*/
-#define DMA16_X_MODIFY			0xFFC01E14	/* DMA Channel 16 X Modify Register						*/
-#define DMA16_Y_COUNT			0xFFC01E18	/* DMA Channel 16 Y Count Register						*/
-#define DMA16_Y_MODIFY			0xFFC01E1C	/* DMA Channel 16 Y Modify Register						*/
-#define DMA16_CURR_DESC_PTR		0xFFC01E20	/* DMA Channel 16 Current Descriptor Pointer Register	*/
-#define DMA16_CURR_ADDR			0xFFC01E24	/* DMA Channel 16 Current Address Register				*/
-#define DMA16_IRQ_STATUS		0xFFC01E28	/* DMA Channel 16 Interrupt/Status Register				*/
-#define DMA16_PERIPHERAL_MAP	0xFFC01E2C	/* DMA Channel 16 Peripheral Map Register				*/
-#define DMA16_CURR_X_COUNT		0xFFC01E30	/* DMA Channel 16 Current X Count Register				*/
-#define DMA16_CURR_Y_COUNT		0xFFC01E38	/* DMA Channel 16 Current Y Count Register				*/
-
-#define DMA17_NEXT_DESC_PTR		0xFFC01E40	/* DMA Channel 17 Next Descriptor Pointer Register		*/
-#define DMA17_START_ADDR		0xFFC01E44	/* DMA Channel 17 Start Address Register				*/
-#define DMA17_CONFIG			0xFFC01E48	/* DMA Channel 17 Configuration Register				*/
-#define DMA17_X_COUNT			0xFFC01E50	/* DMA Channel 17 X Count Register						*/
-#define DMA17_X_MODIFY			0xFFC01E54	/* DMA Channel 17 X Modify Register						*/
-#define DMA17_Y_COUNT			0xFFC01E58	/* DMA Channel 17 Y Count Register						*/
-#define DMA17_Y_MODIFY			0xFFC01E5C	/* DMA Channel 17 Y Modify Register						*/
-#define DMA17_CURR_DESC_PTR		0xFFC01E60	/* DMA Channel 17 Current Descriptor Pointer Register	*/
-#define DMA17_CURR_ADDR			0xFFC01E64	/* DMA Channel 17 Current Address Register				*/
-#define DMA17_IRQ_STATUS		0xFFC01E68	/* DMA Channel 17 Interrupt/Status Register				*/
-#define DMA17_PERIPHERAL_MAP	0xFFC01E6C	/* DMA Channel 17 Peripheral Map Register				*/
-#define DMA17_CURR_X_COUNT		0xFFC01E70	/* DMA Channel 17 Current X Count Register				*/
-#define DMA17_CURR_Y_COUNT		0xFFC01E78	/* DMA Channel 17 Current Y Count Register				*/
-
-#define DMA18_NEXT_DESC_PTR		0xFFC01E80	/* DMA Channel 18 Next Descriptor Pointer Register		*/
-#define DMA18_START_ADDR		0xFFC01E84	/* DMA Channel 18 Start Address Register				*/
-#define DMA18_CONFIG			0xFFC01E88	/* DMA Channel 18 Configuration Register				*/
-#define DMA18_X_COUNT			0xFFC01E90	/* DMA Channel 18 X Count Register						*/
-#define DMA18_X_MODIFY			0xFFC01E94	/* DMA Channel 18 X Modify Register						*/
-#define DMA18_Y_COUNT			0xFFC01E98	/* DMA Channel 18 Y Count Register						*/
-#define DMA18_Y_MODIFY			0xFFC01E9C	/* DMA Channel 18 Y Modify Register						*/
-#define DMA18_CURR_DESC_PTR		0xFFC01EA0	/* DMA Channel 18 Current Descriptor Pointer Register	*/
-#define DMA18_CURR_ADDR			0xFFC01EA4	/* DMA Channel 18 Current Address Register				*/
-#define DMA18_IRQ_STATUS		0xFFC01EA8	/* DMA Channel 18 Interrupt/Status Register				*/
-#define DMA18_PERIPHERAL_MAP	0xFFC01EAC	/* DMA Channel 18 Peripheral Map Register				*/
-#define DMA18_CURR_X_COUNT		0xFFC01EB0	/* DMA Channel 18 Current X Count Register				*/
-#define DMA18_CURR_Y_COUNT		0xFFC01EB8	/* DMA Channel 18 Current Y Count Register				*/
-
-#define DMA19_NEXT_DESC_PTR		0xFFC01EC0	/* DMA Channel 19 Next Descriptor Pointer Register		*/
-#define DMA19_START_ADDR		0xFFC01EC4	/* DMA Channel 19 Start Address Register				*/
-#define DMA19_CONFIG			0xFFC01EC8	/* DMA Channel 19 Configuration Register				*/
-#define DMA19_X_COUNT			0xFFC01ED0	/* DMA Channel 19 X Count Register						*/
-#define DMA19_X_MODIFY			0xFFC01ED4	/* DMA Channel 19 X Modify Register						*/
-#define DMA19_Y_COUNT			0xFFC01ED8	/* DMA Channel 19 Y Count Register						*/
-#define DMA19_Y_MODIFY			0xFFC01EDC	/* DMA Channel 19 Y Modify Register						*/
-#define DMA19_CURR_DESC_PTR		0xFFC01EE0	/* DMA Channel 19 Current Descriptor Pointer Register	*/
-#define DMA19_CURR_ADDR			0xFFC01EE4	/* DMA Channel 19 Current Address Register				*/
-#define DMA19_IRQ_STATUS		0xFFC01EE8	/* DMA Channel 19 Interrupt/Status Register				*/
-#define DMA19_PERIPHERAL_MAP	0xFFC01EEC	/* DMA Channel 19 Peripheral Map Register				*/
-#define DMA19_CURR_X_COUNT		0xFFC01EF0	/* DMA Channel 19 Current X Count Register				*/
-#define DMA19_CURR_Y_COUNT		0xFFC01EF8	/* DMA Channel 19 Current Y Count Register				*/
-
-#define MDMA1_D0_NEXT_DESC_PTR	0xFFC01F00	/* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register		*/
-#define MDMA1_D0_START_ADDR		0xFFC01F04	/* MemDMA1 Stream 0 Destination Start Address Register				*/
-#define MDMA1_D0_CONFIG			0xFFC01F08	/* MemDMA1 Stream 0 Destination Configuration Register				*/
-#define MDMA1_D0_X_COUNT		0xFFC01F10	/* MemDMA1 Stream 0 Destination X Count Register						*/
-#define MDMA1_D0_X_MODIFY		0xFFC01F14	/* MemDMA1 Stream 0 Destination X Modify Register					*/
-#define MDMA1_D0_Y_COUNT		0xFFC01F18	/* MemDMA1 Stream 0 Destination Y Count Register						*/
-#define MDMA1_D0_Y_MODIFY		0xFFC01F1C	/* MemDMA1 Stream 0 Destination Y Modify Register					*/
-#define MDMA1_D0_CURR_DESC_PTR	0xFFC01F20	/* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register	*/
-#define MDMA1_D0_CURR_ADDR		0xFFC01F24	/* MemDMA1 Stream 0 Destination Current Address Register				*/
-#define MDMA1_D0_IRQ_STATUS		0xFFC01F28	/* MemDMA1 Stream 0 Destination Interrupt/Status Register			*/
-#define MDMA1_D0_PERIPHERAL_MAP	0xFFC01F2C	/* MemDMA1 Stream 0 Destination Peripheral Map Register				*/
-#define MDMA1_D0_CURR_X_COUNT	0xFFC01F30	/* MemDMA1 Stream 0 Destination Current X Count Register				*/
-#define MDMA1_D0_CURR_Y_COUNT	0xFFC01F38	/* MemDMA1 Stream 0 Destination Current Y Count Register				*/
-
-#define MDMA1_S0_NEXT_DESC_PTR	0xFFC01F40	/* MemDMA1 Stream 0 Source Next Descriptor Pointer Register			*/
-#define MDMA1_S0_START_ADDR		0xFFC01F44	/* MemDMA1 Stream 0 Source Start Address Register					*/
-#define MDMA1_S0_CONFIG			0xFFC01F48	/* MemDMA1 Stream 0 Source Configuration Register					*/
-#define MDMA1_S0_X_COUNT		0xFFC01F50	/* MemDMA1 Stream 0 Source X Count Register							*/
-#define MDMA1_S0_X_MODIFY		0xFFC01F54	/* MemDMA1 Stream 0 Source X Modify Register							*/
-#define MDMA1_S0_Y_COUNT		0xFFC01F58	/* MemDMA1 Stream 0 Source Y Count Register							*/
-#define MDMA1_S0_Y_MODIFY		0xFFC01F5C	/* MemDMA1 Stream 0 Source Y Modify Register							*/
-#define MDMA1_S0_CURR_DESC_PTR	0xFFC01F60	/* MemDMA1 Stream 0 Source Current Descriptor Pointer Register		*/
-#define MDMA1_S0_CURR_ADDR		0xFFC01F64	/* MemDMA1 Stream 0 Source Current Address Register					*/
-#define MDMA1_S0_IRQ_STATUS		0xFFC01F68	/* MemDMA1 Stream 0 Source Interrupt/Status Register					*/
-#define MDMA1_S0_PERIPHERAL_MAP	0xFFC01F6C	/* MemDMA1 Stream 0 Source Peripheral Map Register					*/
-#define MDMA1_S0_CURR_X_COUNT	0xFFC01F70	/* MemDMA1 Stream 0 Source Current X Count Register					*/
-#define MDMA1_S0_CURR_Y_COUNT	0xFFC01F78	/* MemDMA1 Stream 0 Source Current Y Count Register					*/
-
-#define MDMA1_D1_NEXT_DESC_PTR	0xFFC01F80	/* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register		*/
-#define MDMA1_D1_START_ADDR		0xFFC01F84	/* MemDMA1 Stream 1 Destination Start Address Register				*/
-#define MDMA1_D1_CONFIG			0xFFC01F88	/* MemDMA1 Stream 1 Destination Configuration Register				*/
-#define MDMA1_D1_X_COUNT		0xFFC01F90	/* MemDMA1 Stream 1 Destination X Count Register						*/
-#define MDMA1_D1_X_MODIFY		0xFFC01F94	/* MemDMA1 Stream 1 Destination X Modify Register					*/
-#define MDMA1_D1_Y_COUNT		0xFFC01F98	/* MemDMA1 Stream 1 Destination Y Count Register						*/
-#define MDMA1_D1_Y_MODIFY		0xFFC01F9C	/* MemDMA1 Stream 1 Destination Y Modify Register					*/
-#define MDMA1_D1_CURR_DESC_PTR	0xFFC01FA0	/* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register	*/
-#define MDMA1_D1_CURR_ADDR		0xFFC01FA4	/* MemDMA1 Stream 1 Destination Current Address Register				*/
-#define MDMA1_D1_IRQ_STATUS		0xFFC01FA8	/* MemDMA1 Stream 1 Destination Interrupt/Status Register			*/
-#define MDMA1_D1_PERIPHERAL_MAP	0xFFC01FAC	/* MemDMA1 Stream 1 Destination Peripheral Map Register				*/
-#define MDMA1_D1_CURR_X_COUNT	0xFFC01FB0	/* MemDMA1 Stream 1 Destination Current X Count Register				*/
-#define MDMA1_D1_CURR_Y_COUNT	0xFFC01FB8	/* MemDMA1 Stream 1 Destination Current Y Count Register				*/
-
-#define MDMA1_S1_NEXT_DESC_PTR	0xFFC01FC0	/* MemDMA1 Stream 1 Source Next Descriptor Pointer Register			*/
-#define MDMA1_S1_START_ADDR		0xFFC01FC4	/* MemDMA1 Stream 1 Source Start Address Register					*/
-#define MDMA1_S1_CONFIG			0xFFC01FC8	/* MemDMA1 Stream 1 Source Configuration Register					*/
-#define MDMA1_S1_X_COUNT		0xFFC01FD0	/* MemDMA1 Stream 1 Source X Count Register							*/
-#define MDMA1_S1_X_MODIFY		0xFFC01FD4	/* MemDMA1 Stream 1 Source X Modify Register							*/
-#define MDMA1_S1_Y_COUNT		0xFFC01FD8	/* MemDMA1 Stream 1 Source Y Count Register							*/
-#define MDMA1_S1_Y_MODIFY		0xFFC01FDC	/* MemDMA1 Stream 1 Source Y Modify Register							*/
-#define MDMA1_S1_CURR_DESC_PTR	0xFFC01FE0	/* MemDMA1 Stream 1 Source Current Descriptor Pointer Register		*/
-#define MDMA1_S1_CURR_ADDR		0xFFC01FE4	/* MemDMA1 Stream 1 Source Current Address Register					*/
-#define MDMA1_S1_IRQ_STATUS		0xFFC01FE8	/* MemDMA1 Stream 1 Source Interrupt/Status Register					*/
-#define MDMA1_S1_PERIPHERAL_MAP	0xFFC01FEC	/* MemDMA1 Stream 1 Source Peripheral Map Register					*/
-#define MDMA1_S1_CURR_X_COUNT	0xFFC01FF0	/* MemDMA1 Stream 1 Source Current X Count Register					*/
-#define MDMA1_S1_CURR_Y_COUNT	0xFFC01FF8	/* MemDMA1 Stream 1 Source Current Y Count Register					*/
-
-
-/* UART1 Controller		(0xFFC02000 - 0xFFC020FF)								*/
-#define UART1_THR			0xFFC02000	/* Transmit Holding register			*/
-#define UART1_RBR			0xFFC02000	/* Receive Buffer register				*/
-#define UART1_DLL			0xFFC02000	/* Divisor Latch (Low-Byte)				*/
-#define UART1_IER			0xFFC02004	/* Interrupt Enable Register			*/
-#define UART1_DLH			0xFFC02004	/* Divisor Latch (High-Byte)			*/
-#define UART1_IIR			0xFFC02008	/* Interrupt Identification Register	*/
-#define UART1_LCR			0xFFC0200C	/* Line Control Register				*/
-#define UART1_MCR			0xFFC02010	/* Modem Control Register				*/
-#define UART1_LSR			0xFFC02014	/* Line Status Register					*/
-#define UART1_SCR			0xFFC0201C	/* SCR Scratch Register					*/
-#define UART1_GCTL			0xFFC02024	/* Global Control Register				*/
-
-
-/* UART2 Controller		(0xFFC02100 - 0xFFC021FF)								*/
-#define UART2_THR			0xFFC02100	/* Transmit Holding register			*/
-#define UART2_RBR			0xFFC02100	/* Receive Buffer register				*/
-#define UART2_DLL			0xFFC02100	/* Divisor Latch (Low-Byte)				*/
-#define UART2_IER			0xFFC02104	/* Interrupt Enable Register			*/
-#define UART2_DLH			0xFFC02104	/* Divisor Latch (High-Byte)			*/
-#define UART2_IIR			0xFFC02108	/* Interrupt Identification Register	*/
-#define UART2_LCR			0xFFC0210C	/* Line Control Register				*/
-#define UART2_MCR			0xFFC02110	/* Modem Control Register				*/
-#define UART2_LSR			0xFFC02114	/* Line Status Register					*/
-#define UART2_SCR			0xFFC0211C	/* SCR Scratch Register					*/
-#define UART2_GCTL			0xFFC02124	/* Global Control Register				*/
-
-
-/* Two-Wire Interface 1	(0xFFC02200 - 0xFFC022FF)										*/
-#define TWI1_CLKDIV			0xFFC02200	/* Serial Clock Divider Register				*/
-#define TWI1_CONTROL		0xFFC02204	/* TWI1 Master Internal Time Reference Register	*/
-#define TWI1_SLAVE_CTRL		0xFFC02208	/* Slave Mode Control Register					*/
-#define TWI1_SLAVE_STAT		0xFFC0220C	/* Slave Mode Status Register					*/
-#define TWI1_SLAVE_ADDR		0xFFC02210	/* Slave Mode Address Register					*/
-#define TWI1_MASTER_CTRL	0xFFC02214	/* Master Mode Control Register					*/
-#define TWI1_MASTER_STAT	0xFFC02218	/* Master Mode Status Register					*/
-#define TWI1_MASTER_ADDR	0xFFC0221C	/* Master Mode Address Register					*/
-#define TWI1_INT_STAT		0xFFC02220	/* TWI1 Master Interrupt Register				*/
-#define TWI1_INT_MASK		0xFFC02224	/* TWI1 Master Interrupt Mask Register			*/
-#define TWI1_FIFO_CTRL		0xFFC02228	/* FIFO Control Register						*/
-#define TWI1_FIFO_STAT		0xFFC0222C	/* FIFO Status Register							*/
-#define TWI1_XMT_DATA8		0xFFC02280	/* FIFO Transmit Data Single Byte Register		*/
-#define TWI1_XMT_DATA16		0xFFC02284	/* FIFO Transmit Data Double Byte Register		*/
-#define TWI1_RCV_DATA8		0xFFC02288	/* FIFO Receive Data Single Byte Register		*/
-#define TWI1_RCV_DATA16		0xFFC0228C	/* FIFO Receive Data Double Byte Register		*/
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE     TWI1_CONTROL
-#define TWI1_INT_SRC      TWI1_INT_STAT
-#define TWI1_INT_ENABLE   TWI1_INT_MASK
-
-
-/* SPI1 Controller		(0xFFC02300 - 0xFFC023FF)								*/
-#define SPI1_CTL			0xFFC02300  /* SPI1 Control Register				*/
-#define SPI1_FLG			0xFFC02304  /* SPI1 Flag register					*/
-#define SPI1_STAT			0xFFC02308  /* SPI1 Status register					*/
-#define SPI1_TDBR			0xFFC0230C  /* SPI1 Transmit Data Buffer Register	*/
-#define SPI1_RDBR			0xFFC02310  /* SPI1 Receive Data Buffer Register	*/
-#define SPI1_BAUD			0xFFC02314  /* SPI1 Baud rate Register				*/
-#define SPI1_SHADOW			0xFFC02318  /* SPI1_RDBR Shadow Register			*/
-
-
-/* SPI2 Controller		(0xFFC02400 - 0xFFC024FF)								*/
-#define SPI2_CTL			0xFFC02400  /* SPI2 Control Register				*/
-#define SPI2_FLG			0xFFC02404  /* SPI2 Flag register					*/
-#define SPI2_STAT			0xFFC02408  /* SPI2 Status register					*/
-#define SPI2_TDBR			0xFFC0240C  /* SPI2 Transmit Data Buffer Register	*/
-#define SPI2_RDBR			0xFFC02410  /* SPI2 Receive Data Buffer Register	*/
-#define SPI2_BAUD			0xFFC02414  /* SPI2 Baud rate Register				*/
-#define SPI2_SHADOW			0xFFC02418  /* SPI2_RDBR Shadow Register			*/
-
-
-/* SPORT2 Controller		(0xFFC02500 - 0xFFC025FF)										*/
-#define SPORT2_TCR1			0xFFC02500	/* SPORT2 Transmit Configuration 1 Register			*/
-#define SPORT2_TCR2			0xFFC02504	/* SPORT2 Transmit Configuration 2 Register			*/
-#define SPORT2_TCLKDIV		0xFFC02508	/* SPORT2 Transmit Clock Divider					*/
-#define SPORT2_TFSDIV		0xFFC0250C	/* SPORT2 Transmit Frame Sync Divider				*/
-#define SPORT2_TX			0xFFC02510	/* SPORT2 TX Data Register							*/
-#define SPORT2_RX			0xFFC02518	/* SPORT2 RX Data Register							*/
-#define SPORT2_RCR1			0xFFC02520	/* SPORT2 Transmit Configuration 1 Register			*/
-#define SPORT2_RCR2			0xFFC02524	/* SPORT2 Transmit Configuration 2 Register			*/
-#define SPORT2_RCLKDIV		0xFFC02528	/* SPORT2 Receive Clock Divider						*/
-#define SPORT2_RFSDIV		0xFFC0252C	/* SPORT2 Receive Frame Sync Divider				*/
-#define SPORT2_STAT			0xFFC02530	/* SPORT2 Status Register							*/
-#define SPORT2_CHNL			0xFFC02534	/* SPORT2 Current Channel Register					*/
-#define SPORT2_MCMC1		0xFFC02538	/* SPORT2 Multi-Channel Configuration Register 1	*/
-#define SPORT2_MCMC2		0xFFC0253C	/* SPORT2 Multi-Channel Configuration Register 2	*/
-#define SPORT2_MTCS0		0xFFC02540	/* SPORT2 Multi-Channel Transmit Select Register 0	*/
-#define SPORT2_MTCS1		0xFFC02544	/* SPORT2 Multi-Channel Transmit Select Register 1	*/
-#define SPORT2_MTCS2		0xFFC02548	/* SPORT2 Multi-Channel Transmit Select Register 2	*/
-#define SPORT2_MTCS3		0xFFC0254C	/* SPORT2 Multi-Channel Transmit Select Register 3	*/
-#define SPORT2_MRCS0		0xFFC02550	/* SPORT2 Multi-Channel Receive Select Register 0	*/
-#define SPORT2_MRCS1		0xFFC02554	/* SPORT2 Multi-Channel Receive Select Register 1	*/
-#define SPORT2_MRCS2		0xFFC02558	/* SPORT2 Multi-Channel Receive Select Register 2	*/
-#define SPORT2_MRCS3		0xFFC0255C	/* SPORT2 Multi-Channel Receive Select Register 3	*/
-
-
-/* SPORT3 Controller		(0xFFC02600 - 0xFFC026FF)										*/
-#define SPORT3_TCR1			0xFFC02600	/* SPORT3 Transmit Configuration 1 Register			*/
-#define SPORT3_TCR2			0xFFC02604	/* SPORT3 Transmit Configuration 2 Register			*/
-#define SPORT3_TCLKDIV		0xFFC02608	/* SPORT3 Transmit Clock Divider					*/
-#define SPORT3_TFSDIV		0xFFC0260C	/* SPORT3 Transmit Frame Sync Divider				*/
-#define SPORT3_TX			0xFFC02610	/* SPORT3 TX Data Register							*/
-#define SPORT3_RX			0xFFC02618	/* SPORT3 RX Data Register							*/
-#define SPORT3_RCR1			0xFFC02620	/* SPORT3 Transmit Configuration 1 Register			*/
-#define SPORT3_RCR2			0xFFC02624	/* SPORT3 Transmit Configuration 2 Register			*/
-#define SPORT3_RCLKDIV		0xFFC02628	/* SPORT3 Receive Clock Divider						*/
-#define SPORT3_RFSDIV		0xFFC0262C	/* SPORT3 Receive Frame Sync Divider				*/
-#define SPORT3_STAT			0xFFC02630	/* SPORT3 Status Register							*/
-#define SPORT3_CHNL			0xFFC02634	/* SPORT3 Current Channel Register					*/
-#define SPORT3_MCMC1		0xFFC02638	/* SPORT3 Multi-Channel Configuration Register 1	*/
-#define SPORT3_MCMC2		0xFFC0263C	/* SPORT3 Multi-Channel Configuration Register 2	*/
-#define SPORT3_MTCS0		0xFFC02640	/* SPORT3 Multi-Channel Transmit Select Register 0	*/
-#define SPORT3_MTCS1		0xFFC02644	/* SPORT3 Multi-Channel Transmit Select Register 1	*/
-#define SPORT3_MTCS2		0xFFC02648	/* SPORT3 Multi-Channel Transmit Select Register 2	*/
-#define SPORT3_MTCS3		0xFFC0264C	/* SPORT3 Multi-Channel Transmit Select Register 3	*/
-#define SPORT3_MRCS0		0xFFC02650	/* SPORT3 Multi-Channel Receive Select Register 0	*/
-#define SPORT3_MRCS1		0xFFC02654	/* SPORT3 Multi-Channel Receive Select Register 1	*/
-#define SPORT3_MRCS2		0xFFC02658	/* SPORT3 Multi-Channel Receive Select Register 2	*/
-#define SPORT3_MRCS3		0xFFC0265C	/* SPORT3 Multi-Channel Receive Select Register 3	*/
-
-
-/* Media Transceiver (MXVR)   (0xFFC02700 - 0xFFC028FF) */
-
-#define MXVR_CONFIG           0xFFC02700  /* MXVR Configuration Register */
-#define MXVR_PLL_CTL_0        0xFFC02704  /* MXVR Phase Lock Loop Control Register 0 */
-
-#define MXVR_STATE_0          0xFFC02708  /* MXVR State Register 0 */
-#define MXVR_STATE_1          0xFFC0270C  /* MXVR State Register 1 */
-
-#define MXVR_INT_STAT_0       0xFFC02710  /* MXVR Interrupt Status Register 0 */
-#define MXVR_INT_STAT_1       0xFFC02714  /* MXVR Interrupt Status Register 1 */
-
-#define MXVR_INT_EN_0         0xFFC02718  /* MXVR Interrupt Enable Register 0 */
-#define MXVR_INT_EN_1         0xFFC0271C  /* MXVR Interrupt Enable Register 1 */
-
-#define MXVR_POSITION         0xFFC02720  /* MXVR Node Position Register */
-#define MXVR_MAX_POSITION     0xFFC02724  /* MXVR Maximum Node Position Register */
-
-#define MXVR_DELAY            0xFFC02728  /* MXVR Node Frame Delay Register */
-#define MXVR_MAX_DELAY        0xFFC0272C  /* MXVR Maximum Node Frame Delay Register */
-
-#define MXVR_LADDR            0xFFC02730  /* MXVR Logical Address Register */
-#define MXVR_GADDR            0xFFC02734  /* MXVR Group Address Register */
-#define MXVR_AADDR            0xFFC02738  /* MXVR Alternate Address Register */
-
-#define MXVR_ALLOC_0          0xFFC0273C  /* MXVR Allocation Table Register 0 */
-#define MXVR_ALLOC_1          0xFFC02740  /* MXVR Allocation Table Register 1 */
-#define MXVR_ALLOC_2          0xFFC02744  /* MXVR Allocation Table Register 2 */
-#define MXVR_ALLOC_3          0xFFC02748  /* MXVR Allocation Table Register 3 */
-#define MXVR_ALLOC_4          0xFFC0274C  /* MXVR Allocation Table Register 4 */
-#define MXVR_ALLOC_5          0xFFC02750  /* MXVR Allocation Table Register 5 */
-#define MXVR_ALLOC_6          0xFFC02754  /* MXVR Allocation Table Register 6 */
-#define MXVR_ALLOC_7          0xFFC02758  /* MXVR Allocation Table Register 7 */
-#define MXVR_ALLOC_8          0xFFC0275C  /* MXVR Allocation Table Register 8 */
-#define MXVR_ALLOC_9          0xFFC02760  /* MXVR Allocation Table Register 9 */
-#define MXVR_ALLOC_10         0xFFC02764  /* MXVR Allocation Table Register 10 */
-#define MXVR_ALLOC_11         0xFFC02768  /* MXVR Allocation Table Register 11 */
-#define MXVR_ALLOC_12         0xFFC0276C  /* MXVR Allocation Table Register 12 */
-#define MXVR_ALLOC_13         0xFFC02770  /* MXVR Allocation Table Register 13 */
-#define MXVR_ALLOC_14         0xFFC02774  /* MXVR Allocation Table Register 14 */
-
-#define MXVR_SYNC_LCHAN_0     0xFFC02778  /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define MXVR_SYNC_LCHAN_1     0xFFC0277C  /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define MXVR_SYNC_LCHAN_2     0xFFC02780  /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define MXVR_SYNC_LCHAN_3     0xFFC02784  /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define MXVR_SYNC_LCHAN_4     0xFFC02788  /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define MXVR_SYNC_LCHAN_5     0xFFC0278C  /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define MXVR_SYNC_LCHAN_6     0xFFC02790  /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define MXVR_SYNC_LCHAN_7     0xFFC02794  /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-#define MXVR_DMA0_CONFIG      0xFFC02798  /* MXVR Sync Data DMA0 Config Register */
-#define MXVR_DMA0_START_ADDR  0xFFC0279C  /* MXVR Sync Data DMA0 Start Address Register */
-#define MXVR_DMA0_COUNT       0xFFC027A0  /* MXVR Sync Data DMA0 Loop Count Register */
-#define MXVR_DMA0_CURR_ADDR   0xFFC027A4  /* MXVR Sync Data DMA0 Current Address Register */
-#define MXVR_DMA0_CURR_COUNT  0xFFC027A8  /* MXVR Sync Data DMA0 Current Loop Count Register */
-
-#define MXVR_DMA1_CONFIG      0xFFC027AC  /* MXVR Sync Data DMA1 Config Register */
-#define MXVR_DMA1_START_ADDR  0xFFC027B0  /* MXVR Sync Data DMA1 Start Address Register */
-#define MXVR_DMA1_COUNT       0xFFC027B4  /* MXVR Sync Data DMA1 Loop Count Register */
-#define MXVR_DMA1_CURR_ADDR   0xFFC027B8  /* MXVR Sync Data DMA1 Current Address Register */
-#define MXVR_DMA1_CURR_COUNT  0xFFC027BC  /* MXVR Sync Data DMA1 Current Loop Count Register */
-
-#define MXVR_DMA2_CONFIG      0xFFC027C0  /* MXVR Sync Data DMA2 Config Register */
-#define MXVR_DMA2_START_ADDR  0xFFC027C4  /* MXVR Sync Data DMA2 Start Address Register */
-#define MXVR_DMA2_COUNT       0xFFC027C8  /* MXVR Sync Data DMA2 Loop Count Register */
-#define MXVR_DMA2_CURR_ADDR   0xFFC027CC  /* MXVR Sync Data DMA2 Current Address Register */
-#define MXVR_DMA2_CURR_COUNT  0xFFC027D0  /* MXVR Sync Data DMA2 Current Loop Count Register */
-
-#define MXVR_DMA3_CONFIG      0xFFC027D4  /* MXVR Sync Data DMA3 Config Register */
-#define MXVR_DMA3_START_ADDR  0xFFC027D8  /* MXVR Sync Data DMA3 Start Address Register */
-#define MXVR_DMA3_COUNT       0xFFC027DC  /* MXVR Sync Data DMA3 Loop Count Register */
-#define MXVR_DMA3_CURR_ADDR   0xFFC027E0  /* MXVR Sync Data DMA3 Current Address Register */
-#define MXVR_DMA3_CURR_COUNT  0xFFC027E4  /* MXVR Sync Data DMA3 Current Loop Count Register */
-
-#define MXVR_DMA4_CONFIG      0xFFC027E8  /* MXVR Sync Data DMA4 Config Register */
-#define MXVR_DMA4_START_ADDR  0xFFC027EC  /* MXVR Sync Data DMA4 Start Address Register */
-#define MXVR_DMA4_COUNT       0xFFC027F0  /* MXVR Sync Data DMA4 Loop Count Register */
-#define MXVR_DMA4_CURR_ADDR   0xFFC027F4  /* MXVR Sync Data DMA4 Current Address Register */
-#define MXVR_DMA4_CURR_COUNT  0xFFC027F8  /* MXVR Sync Data DMA4 Current Loop Count Register */
-
-#define MXVR_DMA5_CONFIG      0xFFC027FC  /* MXVR Sync Data DMA5 Config Register */
-#define MXVR_DMA5_START_ADDR  0xFFC02800  /* MXVR Sync Data DMA5 Start Address Register */
-#define MXVR_DMA5_COUNT       0xFFC02804  /* MXVR Sync Data DMA5 Loop Count Register */
-#define MXVR_DMA5_CURR_ADDR   0xFFC02808  /* MXVR Sync Data DMA5 Current Address Register */
-#define MXVR_DMA5_CURR_COUNT  0xFFC0280C  /* MXVR Sync Data DMA5 Current Loop Count Register */
-
-#define MXVR_DMA6_CONFIG      0xFFC02810  /* MXVR Sync Data DMA6 Config Register */
-#define MXVR_DMA6_START_ADDR  0xFFC02814  /* MXVR Sync Data DMA6 Start Address Register */
-#define MXVR_DMA6_COUNT       0xFFC02818  /* MXVR Sync Data DMA6 Loop Count Register */
-#define MXVR_DMA6_CURR_ADDR   0xFFC0281C  /* MXVR Sync Data DMA6 Current Address Register */
-#define MXVR_DMA6_CURR_COUNT  0xFFC02820  /* MXVR Sync Data DMA6 Current Loop Count Register */
-
-#define MXVR_DMA7_CONFIG      0xFFC02824  /* MXVR Sync Data DMA7 Config Register */
-#define MXVR_DMA7_START_ADDR  0xFFC02828  /* MXVR Sync Data DMA7 Start Address Register */
-#define MXVR_DMA7_COUNT       0xFFC0282C  /* MXVR Sync Data DMA7 Loop Count Register */
-#define MXVR_DMA7_CURR_ADDR   0xFFC02830  /* MXVR Sync Data DMA7 Current Address Register */
-#define MXVR_DMA7_CURR_COUNT  0xFFC02834  /* MXVR Sync Data DMA7 Current Loop Count Register */
-
-#define MXVR_AP_CTL           0xFFC02838  /* MXVR Async Packet Control Register */
-#define MXVR_APRB_START_ADDR  0xFFC0283C  /* MXVR Async Packet RX Buffer Start Addr Register */
-#define MXVR_APRB_CURR_ADDR   0xFFC02840  /* MXVR Async Packet RX Buffer Current Addr Register */
-#define MXVR_APTB_START_ADDR  0xFFC02844  /* MXVR Async Packet TX Buffer Start Addr Register */
-#define MXVR_APTB_CURR_ADDR   0xFFC02848  /* MXVR Async Packet TX Buffer Current Addr Register */
-
-#define MXVR_CM_CTL           0xFFC0284C  /* MXVR Control Message Control Register */
-#define MXVR_CMRB_START_ADDR  0xFFC02850  /* MXVR Control Message RX Buffer Start Addr Register */
-#define MXVR_CMRB_CURR_ADDR   0xFFC02854  /* MXVR Control Message RX Buffer Current Address */
-#define MXVR_CMTB_START_ADDR  0xFFC02858  /* MXVR Control Message TX Buffer Start Addr Register */
-#define MXVR_CMTB_CURR_ADDR   0xFFC0285C  /* MXVR Control Message TX Buffer Current Address */
-
-#define MXVR_RRDB_START_ADDR  0xFFC02860  /* MXVR Remote Read Buffer Start Addr Register */
-#define MXVR_RRDB_CURR_ADDR   0xFFC02864  /* MXVR Remote Read Buffer Current Addr Register */
-
-#define MXVR_PAT_DATA_0       0xFFC02868  /* MXVR Pattern Data Register 0 */
-#define MXVR_PAT_EN_0         0xFFC0286C  /* MXVR Pattern Enable Register 0 */
-#define MXVR_PAT_DATA_1       0xFFC02870  /* MXVR Pattern Data Register 1 */
-#define MXVR_PAT_EN_1         0xFFC02874  /* MXVR Pattern Enable Register 1 */
-
-#define MXVR_FRAME_CNT_0      0xFFC02878  /* MXVR Frame Counter 0 */
-#define MXVR_FRAME_CNT_1      0xFFC0287C  /* MXVR Frame Counter 1 */
-
-#define MXVR_ROUTING_0        0xFFC02880  /* MXVR Routing Table Register 0 */
-#define MXVR_ROUTING_1        0xFFC02884  /* MXVR Routing Table Register 1 */
-#define MXVR_ROUTING_2        0xFFC02888  /* MXVR Routing Table Register 2 */
-#define MXVR_ROUTING_3        0xFFC0288C  /* MXVR Routing Table Register 3 */
-#define MXVR_ROUTING_4        0xFFC02890  /* MXVR Routing Table Register 4 */
-#define MXVR_ROUTING_5        0xFFC02894  /* MXVR Routing Table Register 5 */
-#define MXVR_ROUTING_6        0xFFC02898  /* MXVR Routing Table Register 6 */
-#define MXVR_ROUTING_7        0xFFC0289C  /* MXVR Routing Table Register 7 */
-#define MXVR_ROUTING_8        0xFFC028A0  /* MXVR Routing Table Register 8 */
-#define MXVR_ROUTING_9        0xFFC028A4  /* MXVR Routing Table Register 9 */
-#define MXVR_ROUTING_10       0xFFC028A8  /* MXVR Routing Table Register 10 */
-#define MXVR_ROUTING_11       0xFFC028AC  /* MXVR Routing Table Register 11 */
-#define MXVR_ROUTING_12       0xFFC028B0  /* MXVR Routing Table Register 12 */
-#define MXVR_ROUTING_13       0xFFC028B4  /* MXVR Routing Table Register 13 */
-#define MXVR_ROUTING_14       0xFFC028B8  /* MXVR Routing Table Register 14 */
-
-#define MXVR_PLL_CTL_1        0xFFC028BC  /* MXVR Phase Lock Loop Control Register 1 */
-#define MXVR_BLOCK_CNT        0xFFC028C0  /* MXVR Block Counter */
-#define MXVR_PLL_CTL_2        0xFFC028C4  /* MXVR Phase Lock Loop Control Register 2 */
-
-
-/* CAN Controller		(0xFFC02A00 - 0xFFC02FFF)											*/
-/* For Mailboxes 0-15																		*/
-#define CAN_MC1				0xFFC02A00	/* Mailbox config reg 1								*/
-#define CAN_MD1				0xFFC02A04	/* Mailbox direction reg 1							*/
-#define CAN_TRS1			0xFFC02A08	/* Transmit Request Set reg 1						*/
-#define CAN_TRR1			0xFFC02A0C	/* Transmit Request Reset reg 1						*/
-#define CAN_TA1				0xFFC02A10	/* Transmit Acknowledge reg 1						*/
-#define CAN_AA1				0xFFC02A14	/* Transmit Abort Acknowledge reg 1					*/
-#define CAN_RMP1			0xFFC02A18	/* Receive Message Pending reg 1					*/
-#define CAN_RML1			0xFFC02A1C	/* Receive Message Lost reg 1						*/
-#define CAN_MBTIF1			0xFFC02A20	/* Mailbox Transmit Interrupt Flag reg 1			*/
-#define CAN_MBRIF1			0xFFC02A24	/* Mailbox Receive  Interrupt Flag reg 1			*/
-#define CAN_MBIM1			0xFFC02A28	/* Mailbox Interrupt Mask reg 1						*/
-#define CAN_RFH1			0xFFC02A2C	/* Remote Frame Handling reg 1						*/
-#define CAN_OPSS1			0xFFC02A30	/* Overwrite Protection Single Shot Xmission reg 1	*/
-
-/* For Mailboxes 16-31   																	*/
-#define CAN_MC2				0xFFC02A40	/* Mailbox config reg 2								*/
-#define CAN_MD2				0xFFC02A44	/* Mailbox direction reg 2							*/
-#define CAN_TRS2			0xFFC02A48	/* Transmit Request Set reg 2						*/
-#define CAN_TRR2			0xFFC02A4C	/* Transmit Request Reset reg 2						*/
-#define CAN_TA2				0xFFC02A50	/* Transmit Acknowledge reg 2						*/
-#define CAN_AA2				0xFFC02A54	/* Transmit Abort Acknowledge reg 2					*/
-#define CAN_RMP2			0xFFC02A58	/* Receive Message Pending reg 2					*/
-#define CAN_RML2			0xFFC02A5C	/* Receive Message Lost reg 2						*/
-#define CAN_MBTIF2			0xFFC02A60	/* Mailbox Transmit Interrupt Flag reg 2			*/
-#define CAN_MBRIF2			0xFFC02A64	/* Mailbox Receive  Interrupt Flag reg 2			*/
-#define CAN_MBIM2			0xFFC02A68	/* Mailbox Interrupt Mask reg 2						*/
-#define CAN_RFH2			0xFFC02A6C	/* Remote Frame Handling reg 2						*/
-#define CAN_OPSS2			0xFFC02A70	/* Overwrite Protection Single Shot Xmission reg 2	*/
-
-#define CAN_CLOCK			0xFFC02A80	/* Bit Timing Configuration register 0				*/
-#define CAN_TIMING			0xFFC02A84	/* Bit Timing Configuration register 1				*/
-
-#define CAN_DEBUG			0xFFC02A88	/* Debug Register									*/
-/* the following is for backwards compatibility */
-#define CAN_CNF          CAN_DEBUG
-
-#define CAN_STATUS			0xFFC02A8C	/* Global Status Register							*/
-#define CAN_CEC				0xFFC02A90	/* Error Counter Register							*/
-#define CAN_GIS				0xFFC02A94	/* Global Interrupt Status Register					*/
-#define CAN_GIM				0xFFC02A98	/* Global Interrupt Mask Register					*/
-#define CAN_GIF				0xFFC02A9C	/* Global Interrupt Flag Register					*/
-#define CAN_CONTROL			0xFFC02AA0	/* Master Control Register							*/
-#define CAN_INTR			0xFFC02AA4	/* Interrupt Pending Register						*/
-#define CAN_MBTD			0xFFC02AAC	/* Mailbox Temporary Disable Feature				*/
-#define CAN_EWR				0xFFC02AB0	/* Programmable Warning Level						*/
-#define CAN_ESR				0xFFC02AB4	/* Error Status Register							*/
-#define CAN_UCCNT			0xFFC02AC4	/* Universal Counter								*/
-#define CAN_UCRC			0xFFC02AC8	/* Universal Counter Reload/Capture Register    */
-#define CAN_UCCNF			0xFFC02ACC	/* Universal Counter Configuration Register			*/
-
-/* Mailbox Acceptance Masks 												*/
-#define CAN_AM00L			0xFFC02B00	/* Mailbox 0 Low Acceptance Mask	*/
-#define CAN_AM00H			0xFFC02B04	/* Mailbox 0 High Acceptance Mask	*/
-#define CAN_AM01L			0xFFC02B08	/* Mailbox 1 Low Acceptance Mask	*/
-#define CAN_AM01H			0xFFC02B0C	/* Mailbox 1 High Acceptance Mask	*/
-#define CAN_AM02L			0xFFC02B10	/* Mailbox 2 Low Acceptance Mask 	*/
-#define CAN_AM02H			0xFFC02B14	/* Mailbox 2 High Acceptance Mask	*/
-#define CAN_AM03L			0xFFC02B18	/* Mailbox 3 Low Acceptance Mask 	*/
-#define CAN_AM03H			0xFFC02B1C	/* Mailbox 3 High Acceptance Mask	*/
-#define CAN_AM04L			0xFFC02B20	/* Mailbox 4 Low Acceptance Mask 	*/
-#define CAN_AM04H			0xFFC02B24	/* Mailbox 4 High Acceptance Mask	*/
-#define CAN_AM05L			0xFFC02B28	/* Mailbox 5 Low Acceptance Mask 	*/
-#define CAN_AM05H			0xFFC02B2C	/* Mailbox 5 High Acceptance Mask	*/
-#define CAN_AM06L			0xFFC02B30	/* Mailbox 6 Low Acceptance Mask 	*/
-#define CAN_AM06H			0xFFC02B34	/* Mailbox 6 High Acceptance Mask	*/
-#define CAN_AM07L			0xFFC02B38	/* Mailbox 7 Low Acceptance Mask 	*/
-#define CAN_AM07H			0xFFC02B3C	/* Mailbox 7 High Acceptance Mask	*/
-#define CAN_AM08L			0xFFC02B40	/* Mailbox 8 Low Acceptance Mask 	*/
-#define CAN_AM08H			0xFFC02B44	/* Mailbox 8 High Acceptance Mask	*/
-#define CAN_AM09L			0xFFC02B48	/* Mailbox 9 Low Acceptance Mask 	*/
-#define CAN_AM09H			0xFFC02B4C	/* Mailbox 9 High Acceptance Mask	*/
-#define CAN_AM10L			0xFFC02B50	/* Mailbox 10 Low Acceptance Mask 	*/
-#define CAN_AM10H			0xFFC02B54	/* Mailbox 10 High Acceptance Mask	*/
-#define CAN_AM11L			0xFFC02B58	/* Mailbox 11 Low Acceptance Mask 	*/
-#define CAN_AM11H			0xFFC02B5C	/* Mailbox 11 High Acceptance Mask	*/
-#define CAN_AM12L			0xFFC02B60	/* Mailbox 12 Low Acceptance Mask 	*/
-#define CAN_AM12H			0xFFC02B64	/* Mailbox 12 High Acceptance Mask	*/
-#define CAN_AM13L			0xFFC02B68	/* Mailbox 13 Low Acceptance Mask 	*/
-#define CAN_AM13H			0xFFC02B6C	/* Mailbox 13 High Acceptance Mask	*/
-#define CAN_AM14L			0xFFC02B70	/* Mailbox 14 Low Acceptance Mask 	*/
-#define CAN_AM14H			0xFFC02B74	/* Mailbox 14 High Acceptance Mask	*/
-#define CAN_AM15L			0xFFC02B78	/* Mailbox 15 Low Acceptance Mask 	*/
-#define CAN_AM15H			0xFFC02B7C	/* Mailbox 15 High Acceptance Mask	*/
-
-#define CAN_AM16L			0xFFC02B80	/* Mailbox 16 Low Acceptance Mask 	*/
-#define CAN_AM16H			0xFFC02B84	/* Mailbox 16 High Acceptance Mask	*/
-#define CAN_AM17L			0xFFC02B88	/* Mailbox 17 Low Acceptance Mask 	*/
-#define CAN_AM17H			0xFFC02B8C	/* Mailbox 17 High Acceptance Mask	*/
-#define CAN_AM18L			0xFFC02B90	/* Mailbox 18 Low Acceptance Mask 	*/
-#define CAN_AM18H			0xFFC02B94	/* Mailbox 18 High Acceptance Mask	*/
-#define CAN_AM19L			0xFFC02B98	/* Mailbox 19 Low Acceptance Mask 	*/
-#define CAN_AM19H			0xFFC02B9C	/* Mailbox 19 High Acceptance Mask	*/
-#define CAN_AM20L			0xFFC02BA0	/* Mailbox 20 Low Acceptance Mask 	*/
-#define CAN_AM20H			0xFFC02BA4	/* Mailbox 20 High Acceptance Mask	*/
-#define CAN_AM21L			0xFFC02BA8	/* Mailbox 21 Low Acceptance Mask 	*/
-#define CAN_AM21H			0xFFC02BAC	/* Mailbox 21 High Acceptance Mask	*/
-#define CAN_AM22L			0xFFC02BB0	/* Mailbox 22 Low Acceptance Mask 	*/
-#define CAN_AM22H			0xFFC02BB4	/* Mailbox 22 High Acceptance Mask	*/
-#define CAN_AM23L			0xFFC02BB8	/* Mailbox 23 Low Acceptance Mask 	*/
-#define CAN_AM23H			0xFFC02BBC	/* Mailbox 23 High Acceptance Mask	*/
-#define CAN_AM24L			0xFFC02BC0	/* Mailbox 24 Low Acceptance Mask 	*/
-#define CAN_AM24H			0xFFC02BC4	/* Mailbox 24 High Acceptance Mask	*/
-#define CAN_AM25L			0xFFC02BC8	/* Mailbox 25 Low Acceptance Mask 	*/
-#define CAN_AM25H			0xFFC02BCC	/* Mailbox 25 High Acceptance Mask	*/
-#define CAN_AM26L			0xFFC02BD0	/* Mailbox 26 Low Acceptance Mask 	*/
-#define CAN_AM26H			0xFFC02BD4	/* Mailbox 26 High Acceptance Mask	*/
-#define CAN_AM27L			0xFFC02BD8	/* Mailbox 27 Low Acceptance Mask 	*/
-#define CAN_AM27H			0xFFC02BDC	/* Mailbox 27 High Acceptance Mask	*/
-#define CAN_AM28L			0xFFC02BE0	/* Mailbox 28 Low Acceptance Mask 	*/
-#define CAN_AM28H			0xFFC02BE4	/* Mailbox 28 High Acceptance Mask	*/
-#define CAN_AM29L			0xFFC02BE8	/* Mailbox 29 Low Acceptance Mask 	*/
-#define CAN_AM29H			0xFFC02BEC	/* Mailbox 29 High Acceptance Mask	*/
-#define CAN_AM30L			0xFFC02BF0	/* Mailbox 30 Low Acceptance Mask 	*/
-#define CAN_AM30H			0xFFC02BF4	/* Mailbox 30 High Acceptance Mask	*/
-#define CAN_AM31L			0xFFC02BF8	/* Mailbox 31 Low Acceptance Mask 	*/
-#define CAN_AM31H			0xFFC02BFC	/* Mailbox 31 High Acceptance Mask	*/
-
-/* CAN Acceptance Mask Macros				*/
-#define CAN_AM_L(x)			(CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)			(CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers																*/
-#define CAN_MB00_DATA0		0xFFC02C00	/* Mailbox 0 Data Word 0 [15:0] Register	*/
-#define CAN_MB00_DATA1		0xFFC02C04	/* Mailbox 0 Data Word 1 [31:16] Register	*/
-#define CAN_MB00_DATA2		0xFFC02C08	/* Mailbox 0 Data Word 2 [47:32] Register	*/
-#define CAN_MB00_DATA3		0xFFC02C0C	/* Mailbox 0 Data Word 3 [63:48] Register	*/
-#define CAN_MB00_LENGTH		0xFFC02C10	/* Mailbox 0 Data Length Code Register		*/
-#define CAN_MB00_TIMESTAMP	0xFFC02C14	/* Mailbox 0 Time Stamp Value Register		*/
-#define CAN_MB00_ID0		0xFFC02C18	/* Mailbox 0 Identifier Low Register		*/
-#define CAN_MB00_ID1		0xFFC02C1C	/* Mailbox 0 Identifier High Register		*/
-
-#define CAN_MB01_DATA0		0xFFC02C20	/* Mailbox 1 Data Word 0 [15:0] Register	*/
-#define CAN_MB01_DATA1		0xFFC02C24	/* Mailbox 1 Data Word 1 [31:16] Register	*/
-#define CAN_MB01_DATA2		0xFFC02C28	/* Mailbox 1 Data Word 2 [47:32] Register	*/
-#define CAN_MB01_DATA3		0xFFC02C2C	/* Mailbox 1 Data Word 3 [63:48] Register	*/
-#define CAN_MB01_LENGTH		0xFFC02C30	/* Mailbox 1 Data Length Code Register		*/
-#define CAN_MB01_TIMESTAMP	0xFFC02C34	/* Mailbox 1 Time Stamp Value Register		*/
-#define CAN_MB01_ID0		0xFFC02C38	/* Mailbox 1 Identifier Low Register		*/
-#define CAN_MB01_ID1		0xFFC02C3C	/* Mailbox 1 Identifier High Register		*/
-
-#define CAN_MB02_DATA0		0xFFC02C40	/* Mailbox 2 Data Word 0 [15:0] Register	*/
-#define CAN_MB02_DATA1		0xFFC02C44	/* Mailbox 2 Data Word 1 [31:16] Register	*/
-#define CAN_MB02_DATA2		0xFFC02C48	/* Mailbox 2 Data Word 2 [47:32] Register	*/
-#define CAN_MB02_DATA3		0xFFC02C4C	/* Mailbox 2 Data Word 3 [63:48] Register	*/
-#define CAN_MB02_LENGTH		0xFFC02C50	/* Mailbox 2 Data Length Code Register		*/
-#define CAN_MB02_TIMESTAMP	0xFFC02C54	/* Mailbox 2 Time Stamp Value Register		*/
-#define CAN_MB02_ID0		0xFFC02C58	/* Mailbox 2 Identifier Low Register		*/
-#define CAN_MB02_ID1		0xFFC02C5C	/* Mailbox 2 Identifier High Register		*/
-
-#define CAN_MB03_DATA0		0xFFC02C60	/* Mailbox 3 Data Word 0 [15:0] Register	*/
-#define CAN_MB03_DATA1		0xFFC02C64	/* Mailbox 3 Data Word 1 [31:16] Register	*/
-#define CAN_MB03_DATA2		0xFFC02C68	/* Mailbox 3 Data Word 2 [47:32] Register	*/
-#define CAN_MB03_DATA3		0xFFC02C6C	/* Mailbox 3 Data Word 3 [63:48] Register	*/
-#define CAN_MB03_LENGTH		0xFFC02C70	/* Mailbox 3 Data Length Code Register		*/
-#define CAN_MB03_TIMESTAMP	0xFFC02C74	/* Mailbox 3 Time Stamp Value Register		*/
-#define CAN_MB03_ID0		0xFFC02C78	/* Mailbox 3 Identifier Low Register		*/
-#define CAN_MB03_ID1		0xFFC02C7C	/* Mailbox 3 Identifier High Register		*/
-
-#define CAN_MB04_DATA0		0xFFC02C80	/* Mailbox 4 Data Word 0 [15:0] Register	*/
-#define CAN_MB04_DATA1		0xFFC02C84	/* Mailbox 4 Data Word 1 [31:16] Register	*/
-#define CAN_MB04_DATA2		0xFFC02C88	/* Mailbox 4 Data Word 2 [47:32] Register	*/
-#define CAN_MB04_DATA3		0xFFC02C8C	/* Mailbox 4 Data Word 3 [63:48] Register	*/
-#define CAN_MB04_LENGTH		0xFFC02C90	/* Mailbox 4 Data Length Code Register		*/
-#define CAN_MB04_TIMESTAMP	0xFFC02C94	/* Mailbox 4 Time Stamp Value Register		*/
-#define CAN_MB04_ID0		0xFFC02C98	/* Mailbox 4 Identifier Low Register		*/
-#define CAN_MB04_ID1		0xFFC02C9C	/* Mailbox 4 Identifier High Register		*/
-
-#define CAN_MB05_DATA0		0xFFC02CA0	/* Mailbox 5 Data Word 0 [15:0] Register	*/
-#define CAN_MB05_DATA1		0xFFC02CA4	/* Mailbox 5 Data Word 1 [31:16] Register	*/
-#define CAN_MB05_DATA2		0xFFC02CA8	/* Mailbox 5 Data Word 2 [47:32] Register	*/
-#define CAN_MB05_DATA3		0xFFC02CAC	/* Mailbox 5 Data Word 3 [63:48] Register	*/
-#define CAN_MB05_LENGTH		0xFFC02CB0	/* Mailbox 5 Data Length Code Register		*/
-#define CAN_MB05_TIMESTAMP	0xFFC02CB4	/* Mailbox 5 Time Stamp Value Register		*/
-#define CAN_MB05_ID0		0xFFC02CB8	/* Mailbox 5 Identifier Low Register		*/
-#define CAN_MB05_ID1		0xFFC02CBC	/* Mailbox 5 Identifier High Register		*/
-
-#define CAN_MB06_DATA0		0xFFC02CC0	/* Mailbox 6 Data Word 0 [15:0] Register	*/
-#define CAN_MB06_DATA1		0xFFC02CC4	/* Mailbox 6 Data Word 1 [31:16] Register	*/
-#define CAN_MB06_DATA2		0xFFC02CC8	/* Mailbox 6 Data Word 2 [47:32] Register	*/
-#define CAN_MB06_DATA3		0xFFC02CCC	/* Mailbox 6 Data Word 3 [63:48] Register	*/
-#define CAN_MB06_LENGTH		0xFFC02CD0	/* Mailbox 6 Data Length Code Register		*/
-#define CAN_MB06_TIMESTAMP	0xFFC02CD4	/* Mailbox 6 Time Stamp Value Register		*/
-#define CAN_MB06_ID0		0xFFC02CD8	/* Mailbox 6 Identifier Low Register		*/
-#define CAN_MB06_ID1		0xFFC02CDC	/* Mailbox 6 Identifier High Register		*/
-
-#define CAN_MB07_DATA0		0xFFC02CE0	/* Mailbox 7 Data Word 0 [15:0] Register	*/
-#define CAN_MB07_DATA1		0xFFC02CE4	/* Mailbox 7 Data Word 1 [31:16] Register	*/
-#define CAN_MB07_DATA2		0xFFC02CE8	/* Mailbox 7 Data Word 2 [47:32] Register	*/
-#define CAN_MB07_DATA3		0xFFC02CEC	/* Mailbox 7 Data Word 3 [63:48] Register	*/
-#define CAN_MB07_LENGTH		0xFFC02CF0	/* Mailbox 7 Data Length Code Register		*/
-#define CAN_MB07_TIMESTAMP	0xFFC02CF4	/* Mailbox 7 Time Stamp Value Register		*/
-#define CAN_MB07_ID0		0xFFC02CF8	/* Mailbox 7 Identifier Low Register		*/
-#define CAN_MB07_ID1		0xFFC02CFC	/* Mailbox 7 Identifier High Register		*/
-
-#define CAN_MB08_DATA0		0xFFC02D00	/* Mailbox 8 Data Word 0 [15:0] Register	*/
-#define CAN_MB08_DATA1		0xFFC02D04	/* Mailbox 8 Data Word 1 [31:16] Register	*/
-#define CAN_MB08_DATA2		0xFFC02D08	/* Mailbox 8 Data Word 2 [47:32] Register	*/
-#define CAN_MB08_DATA3		0xFFC02D0C	/* Mailbox 8 Data Word 3 [63:48] Register	*/
-#define CAN_MB08_LENGTH		0xFFC02D10	/* Mailbox 8 Data Length Code Register		*/
-#define CAN_MB08_TIMESTAMP	0xFFC02D14	/* Mailbox 8 Time Stamp Value Register		*/
-#define CAN_MB08_ID0		0xFFC02D18	/* Mailbox 8 Identifier Low Register		*/
-#define CAN_MB08_ID1		0xFFC02D1C	/* Mailbox 8 Identifier High Register		*/
-
-#define CAN_MB09_DATA0		0xFFC02D20	/* Mailbox 9 Data Word 0 [15:0] Register	*/
-#define CAN_MB09_DATA1		0xFFC02D24	/* Mailbox 9 Data Word 1 [31:16] Register	*/
-#define CAN_MB09_DATA2		0xFFC02D28	/* Mailbox 9 Data Word 2 [47:32] Register	*/
-#define CAN_MB09_DATA3		0xFFC02D2C	/* Mailbox 9 Data Word 3 [63:48] Register	*/
-#define CAN_MB09_LENGTH		0xFFC02D30	/* Mailbox 9 Data Length Code Register		*/
-#define CAN_MB09_TIMESTAMP	0xFFC02D34	/* Mailbox 9 Time Stamp Value Register		*/
-#define CAN_MB09_ID0		0xFFC02D38	/* Mailbox 9 Identifier Low Register		*/
-#define CAN_MB09_ID1		0xFFC02D3C	/* Mailbox 9 Identifier High Register		*/
-
-#define CAN_MB10_DATA0		0xFFC02D40	/* Mailbox 10 Data Word 0 [15:0] Register	*/
-#define CAN_MB10_DATA1		0xFFC02D44	/* Mailbox 10 Data Word 1 [31:16] Register	*/
-#define CAN_MB10_DATA2		0xFFC02D48	/* Mailbox 10 Data Word 2 [47:32] Register	*/
-#define CAN_MB10_DATA3		0xFFC02D4C	/* Mailbox 10 Data Word 3 [63:48] Register	*/
-#define CAN_MB10_LENGTH		0xFFC02D50	/* Mailbox 10 Data Length Code Register		*/
-#define CAN_MB10_TIMESTAMP	0xFFC02D54	/* Mailbox 10 Time Stamp Value Register		*/
-#define CAN_MB10_ID0		0xFFC02D58	/* Mailbox 10 Identifier Low Register		*/
-#define CAN_MB10_ID1		0xFFC02D5C	/* Mailbox 10 Identifier High Register		*/
-
-#define CAN_MB11_DATA0		0xFFC02D60	/* Mailbox 11 Data Word 0 [15:0] Register	*/
-#define CAN_MB11_DATA1		0xFFC02D64	/* Mailbox 11 Data Word 1 [31:16] Register	*/
-#define CAN_MB11_DATA2		0xFFC02D68	/* Mailbox 11 Data Word 2 [47:32] Register	*/
-#define CAN_MB11_DATA3		0xFFC02D6C	/* Mailbox 11 Data Word 3 [63:48] Register	*/
-#define CAN_MB11_LENGTH		0xFFC02D70	/* Mailbox 11 Data Length Code Register		*/
-#define CAN_MB11_TIMESTAMP	0xFFC02D74	/* Mailbox 11 Time Stamp Value Register		*/
-#define CAN_MB11_ID0		0xFFC02D78	/* Mailbox 11 Identifier Low Register		*/
-#define CAN_MB11_ID1		0xFFC02D7C	/* Mailbox 11 Identifier High Register		*/
-
-#define CAN_MB12_DATA0		0xFFC02D80	/* Mailbox 12 Data Word 0 [15:0] Register	*/
-#define CAN_MB12_DATA1		0xFFC02D84	/* Mailbox 12 Data Word 1 [31:16] Register	*/
-#define CAN_MB12_DATA2		0xFFC02D88	/* Mailbox 12 Data Word 2 [47:32] Register	*/
-#define CAN_MB12_DATA3		0xFFC02D8C	/* Mailbox 12 Data Word 3 [63:48] Register	*/
-#define CAN_MB12_LENGTH		0xFFC02D90	/* Mailbox 12 Data Length Code Register		*/
-#define CAN_MB12_TIMESTAMP	0xFFC02D94	/* Mailbox 12 Time Stamp Value Register		*/
-#define CAN_MB12_ID0		0xFFC02D98	/* Mailbox 12 Identifier Low Register		*/
-#define CAN_MB12_ID1		0xFFC02D9C	/* Mailbox 12 Identifier High Register		*/
-
-#define CAN_MB13_DATA0		0xFFC02DA0	/* Mailbox 13 Data Word 0 [15:0] Register	*/
-#define CAN_MB13_DATA1		0xFFC02DA4	/* Mailbox 13 Data Word 1 [31:16] Register	*/
-#define CAN_MB13_DATA2		0xFFC02DA8	/* Mailbox 13 Data Word 2 [47:32] Register	*/
-#define CAN_MB13_DATA3		0xFFC02DAC	/* Mailbox 13 Data Word 3 [63:48] Register	*/
-#define CAN_MB13_LENGTH		0xFFC02DB0	/* Mailbox 13 Data Length Code Register		*/
-#define CAN_MB13_TIMESTAMP	0xFFC02DB4	/* Mailbox 13 Time Stamp Value Register		*/
-#define CAN_MB13_ID0		0xFFC02DB8	/* Mailbox 13 Identifier Low Register		*/
-#define CAN_MB13_ID1		0xFFC02DBC	/* Mailbox 13 Identifier High Register		*/
-
-#define CAN_MB14_DATA0		0xFFC02DC0	/* Mailbox 14 Data Word 0 [15:0] Register	*/
-#define CAN_MB14_DATA1		0xFFC02DC4	/* Mailbox 14 Data Word 1 [31:16] Register	*/
-#define CAN_MB14_DATA2		0xFFC02DC8	/* Mailbox 14 Data Word 2 [47:32] Register	*/
-#define CAN_MB14_DATA3		0xFFC02DCC	/* Mailbox 14 Data Word 3 [63:48] Register	*/
-#define CAN_MB14_LENGTH		0xFFC02DD0	/* Mailbox 14 Data Length Code Register		*/
-#define CAN_MB14_TIMESTAMP	0xFFC02DD4	/* Mailbox 14 Time Stamp Value Register		*/
-#define CAN_MB14_ID0		0xFFC02DD8	/* Mailbox 14 Identifier Low Register		*/
-#define CAN_MB14_ID1		0xFFC02DDC	/* Mailbox 14 Identifier High Register		*/
-
-#define CAN_MB15_DATA0		0xFFC02DE0	/* Mailbox 15 Data Word 0 [15:0] Register	*/
-#define CAN_MB15_DATA1		0xFFC02DE4	/* Mailbox 15 Data Word 1 [31:16] Register	*/
-#define CAN_MB15_DATA2		0xFFC02DE8	/* Mailbox 15 Data Word 2 [47:32] Register	*/
-#define CAN_MB15_DATA3		0xFFC02DEC	/* Mailbox 15 Data Word 3 [63:48] Register	*/
-#define CAN_MB15_LENGTH		0xFFC02DF0	/* Mailbox 15 Data Length Code Register		*/
-#define CAN_MB15_TIMESTAMP	0xFFC02DF4	/* Mailbox 15 Time Stamp Value Register		*/
-#define CAN_MB15_ID0		0xFFC02DF8	/* Mailbox 15 Identifier Low Register		*/
-#define CAN_MB15_ID1		0xFFC02DFC	/* Mailbox 15 Identifier High Register		*/
-
-#define CAN_MB16_DATA0		0xFFC02E00	/* Mailbox 16 Data Word 0 [15:0] Register	*/
-#define CAN_MB16_DATA1		0xFFC02E04	/* Mailbox 16 Data Word 1 [31:16] Register	*/
-#define CAN_MB16_DATA2		0xFFC02E08	/* Mailbox 16 Data Word 2 [47:32] Register	*/
-#define CAN_MB16_DATA3		0xFFC02E0C	/* Mailbox 16 Data Word 3 [63:48] Register	*/
-#define CAN_MB16_LENGTH		0xFFC02E10	/* Mailbox 16 Data Length Code Register		*/
-#define CAN_MB16_TIMESTAMP	0xFFC02E14	/* Mailbox 16 Time Stamp Value Register		*/
-#define CAN_MB16_ID0		0xFFC02E18	/* Mailbox 16 Identifier Low Register		*/
-#define CAN_MB16_ID1		0xFFC02E1C	/* Mailbox 16 Identifier High Register		*/
-
-#define CAN_MB17_DATA0		0xFFC02E20	/* Mailbox 17 Data Word 0 [15:0] Register	*/
-#define CAN_MB17_DATA1		0xFFC02E24	/* Mailbox 17 Data Word 1 [31:16] Register	*/
-#define CAN_MB17_DATA2		0xFFC02E28	/* Mailbox 17 Data Word 2 [47:32] Register	*/
-#define CAN_MB17_DATA3		0xFFC02E2C	/* Mailbox 17 Data Word 3 [63:48] Register	*/
-#define CAN_MB17_LENGTH		0xFFC02E30	/* Mailbox 17 Data Length Code Register		*/
-#define CAN_MB17_TIMESTAMP	0xFFC02E34	/* Mailbox 17 Time Stamp Value Register		*/
-#define CAN_MB17_ID0		0xFFC02E38	/* Mailbox 17 Identifier Low Register		*/
-#define CAN_MB17_ID1		0xFFC02E3C	/* Mailbox 17 Identifier High Register		*/
-
-#define CAN_MB18_DATA0		0xFFC02E40	/* Mailbox 18 Data Word 0 [15:0] Register	*/
-#define CAN_MB18_DATA1		0xFFC02E44	/* Mailbox 18 Data Word 1 [31:16] Register	*/
-#define CAN_MB18_DATA2		0xFFC02E48	/* Mailbox 18 Data Word 2 [47:32] Register	*/
-#define CAN_MB18_DATA3		0xFFC02E4C	/* Mailbox 18 Data Word 3 [63:48] Register	*/
-#define CAN_MB18_LENGTH		0xFFC02E50	/* Mailbox 18 Data Length Code Register		*/
-#define CAN_MB18_TIMESTAMP	0xFFC02E54	/* Mailbox 18 Time Stamp Value Register		*/
-#define CAN_MB18_ID0		0xFFC02E58	/* Mailbox 18 Identifier Low Register		*/
-#define CAN_MB18_ID1		0xFFC02E5C	/* Mailbox 18 Identifier High Register		*/
-
-#define CAN_MB19_DATA0		0xFFC02E60	/* Mailbox 19 Data Word 0 [15:0] Register	*/
-#define CAN_MB19_DATA1		0xFFC02E64	/* Mailbox 19 Data Word 1 [31:16] Register	*/
-#define CAN_MB19_DATA2		0xFFC02E68	/* Mailbox 19 Data Word 2 [47:32] Register	*/
-#define CAN_MB19_DATA3		0xFFC02E6C	/* Mailbox 19 Data Word 3 [63:48] Register	*/
-#define CAN_MB19_LENGTH		0xFFC02E70	/* Mailbox 19 Data Length Code Register		*/
-#define CAN_MB19_TIMESTAMP	0xFFC02E74	/* Mailbox 19 Time Stamp Value Register		*/
-#define CAN_MB19_ID0		0xFFC02E78	/* Mailbox 19 Identifier Low Register		*/
-#define CAN_MB19_ID1		0xFFC02E7C	/* Mailbox 19 Identifier High Register		*/
-
-#define CAN_MB20_DATA0		0xFFC02E80	/* Mailbox 20 Data Word 0 [15:0] Register	*/
-#define CAN_MB20_DATA1		0xFFC02E84	/* Mailbox 20 Data Word 1 [31:16] Register	*/
-#define CAN_MB20_DATA2		0xFFC02E88	/* Mailbox 20 Data Word 2 [47:32] Register	*/
-#define CAN_MB20_DATA3		0xFFC02E8C	/* Mailbox 20 Data Word 3 [63:48] Register	*/
-#define CAN_MB20_LENGTH		0xFFC02E90	/* Mailbox 20 Data Length Code Register		*/
-#define CAN_MB20_TIMESTAMP	0xFFC02E94	/* Mailbox 20 Time Stamp Value Register		*/
-#define CAN_MB20_ID0		0xFFC02E98	/* Mailbox 20 Identifier Low Register		*/
-#define CAN_MB20_ID1		0xFFC02E9C	/* Mailbox 20 Identifier High Register		*/
-
-#define CAN_MB21_DATA0		0xFFC02EA0	/* Mailbox 21 Data Word 0 [15:0] Register	*/
-#define CAN_MB21_DATA1		0xFFC02EA4	/* Mailbox 21 Data Word 1 [31:16] Register	*/
-#define CAN_MB21_DATA2		0xFFC02EA8	/* Mailbox 21 Data Word 2 [47:32] Register	*/
-#define CAN_MB21_DATA3		0xFFC02EAC	/* Mailbox 21 Data Word 3 [63:48] Register	*/
-#define CAN_MB21_LENGTH		0xFFC02EB0	/* Mailbox 21 Data Length Code Register		*/
-#define CAN_MB21_TIMESTAMP	0xFFC02EB4	/* Mailbox 21 Time Stamp Value Register		*/
-#define CAN_MB21_ID0		0xFFC02EB8	/* Mailbox 21 Identifier Low Register		*/
-#define CAN_MB21_ID1		0xFFC02EBC	/* Mailbox 21 Identifier High Register		*/
-
-#define CAN_MB22_DATA0		0xFFC02EC0	/* Mailbox 22 Data Word 0 [15:0] Register	*/
-#define CAN_MB22_DATA1		0xFFC02EC4	/* Mailbox 22 Data Word 1 [31:16] Register	*/
-#define CAN_MB22_DATA2		0xFFC02EC8	/* Mailbox 22 Data Word 2 [47:32] Register	*/
-#define CAN_MB22_DATA3		0xFFC02ECC	/* Mailbox 22 Data Word 3 [63:48] Register	*/
-#define CAN_MB22_LENGTH		0xFFC02ED0	/* Mailbox 22 Data Length Code Register		*/
-#define CAN_MB22_TIMESTAMP	0xFFC02ED4	/* Mailbox 22 Time Stamp Value Register		*/
-#define CAN_MB22_ID0		0xFFC02ED8	/* Mailbox 22 Identifier Low Register		*/
-#define CAN_MB22_ID1		0xFFC02EDC	/* Mailbox 22 Identifier High Register		*/
-
-#define CAN_MB23_DATA0		0xFFC02EE0	/* Mailbox 23 Data Word 0 [15:0] Register	*/
-#define CAN_MB23_DATA1		0xFFC02EE4	/* Mailbox 23 Data Word 1 [31:16] Register	*/
-#define CAN_MB23_DATA2		0xFFC02EE8	/* Mailbox 23 Data Word 2 [47:32] Register	*/
-#define CAN_MB23_DATA3		0xFFC02EEC	/* Mailbox 23 Data Word 3 [63:48] Register	*/
-#define CAN_MB23_LENGTH		0xFFC02EF0	/* Mailbox 23 Data Length Code Register		*/
-#define CAN_MB23_TIMESTAMP	0xFFC02EF4	/* Mailbox 23 Time Stamp Value Register		*/
-#define CAN_MB23_ID0		0xFFC02EF8	/* Mailbox 23 Identifier Low Register		*/
-#define CAN_MB23_ID1		0xFFC02EFC	/* Mailbox 23 Identifier High Register		*/
-
-#define CAN_MB24_DATA0		0xFFC02F00	/* Mailbox 24 Data Word 0 [15:0] Register	*/
-#define CAN_MB24_DATA1		0xFFC02F04	/* Mailbox 24 Data Word 1 [31:16] Register	*/
-#define CAN_MB24_DATA2		0xFFC02F08	/* Mailbox 24 Data Word 2 [47:32] Register	*/
-#define CAN_MB24_DATA3		0xFFC02F0C	/* Mailbox 24 Data Word 3 [63:48] Register	*/
-#define CAN_MB24_LENGTH		0xFFC02F10	/* Mailbox 24 Data Length Code Register		*/
-#define CAN_MB24_TIMESTAMP	0xFFC02F14	/* Mailbox 24 Time Stamp Value Register		*/
-#define CAN_MB24_ID0		0xFFC02F18	/* Mailbox 24 Identifier Low Register		*/
-#define CAN_MB24_ID1		0xFFC02F1C	/* Mailbox 24 Identifier High Register		*/
-
-#define CAN_MB25_DATA0		0xFFC02F20	/* Mailbox 25 Data Word 0 [15:0] Register	*/
-#define CAN_MB25_DATA1		0xFFC02F24	/* Mailbox 25 Data Word 1 [31:16] Register	*/
-#define CAN_MB25_DATA2		0xFFC02F28	/* Mailbox 25 Data Word 2 [47:32] Register	*/
-#define CAN_MB25_DATA3		0xFFC02F2C	/* Mailbox 25 Data Word 3 [63:48] Register	*/
-#define CAN_MB25_LENGTH		0xFFC02F30	/* Mailbox 25 Data Length Code Register		*/
-#define CAN_MB25_TIMESTAMP	0xFFC02F34	/* Mailbox 25 Time Stamp Value Register		*/
-#define CAN_MB25_ID0		0xFFC02F38	/* Mailbox 25 Identifier Low Register		*/
-#define CAN_MB25_ID1		0xFFC02F3C	/* Mailbox 25 Identifier High Register		*/
-
-#define CAN_MB26_DATA0		0xFFC02F40	/* Mailbox 26 Data Word 0 [15:0] Register	*/
-#define CAN_MB26_DATA1		0xFFC02F44	/* Mailbox 26 Data Word 1 [31:16] Register	*/
-#define CAN_MB26_DATA2		0xFFC02F48	/* Mailbox 26 Data Word 2 [47:32] Register	*/
-#define CAN_MB26_DATA3		0xFFC02F4C	/* Mailbox 26 Data Word 3 [63:48] Register	*/
-#define CAN_MB26_LENGTH		0xFFC02F50	/* Mailbox 26 Data Length Code Register		*/
-#define CAN_MB26_TIMESTAMP	0xFFC02F54	/* Mailbox 26 Time Stamp Value Register		*/
-#define CAN_MB26_ID0		0xFFC02F58	/* Mailbox 26 Identifier Low Register		*/
-#define CAN_MB26_ID1		0xFFC02F5C	/* Mailbox 26 Identifier High Register		*/
-
-#define CAN_MB27_DATA0		0xFFC02F60	/* Mailbox 27 Data Word 0 [15:0] Register	*/
-#define CAN_MB27_DATA1		0xFFC02F64	/* Mailbox 27 Data Word 1 [31:16] Register	*/
-#define CAN_MB27_DATA2		0xFFC02F68	/* Mailbox 27 Data Word 2 [47:32] Register	*/
-#define CAN_MB27_DATA3		0xFFC02F6C	/* Mailbox 27 Data Word 3 [63:48] Register	*/
-#define CAN_MB27_LENGTH		0xFFC02F70	/* Mailbox 27 Data Length Code Register		*/
-#define CAN_MB27_TIMESTAMP	0xFFC02F74	/* Mailbox 27 Time Stamp Value Register		*/
-#define CAN_MB27_ID0		0xFFC02F78	/* Mailbox 27 Identifier Low Register		*/
-#define CAN_MB27_ID1		0xFFC02F7C	/* Mailbox 27 Identifier High Register		*/
-
-#define CAN_MB28_DATA0		0xFFC02F80	/* Mailbox 28 Data Word 0 [15:0] Register	*/
-#define CAN_MB28_DATA1		0xFFC02F84	/* Mailbox 28 Data Word 1 [31:16] Register	*/
-#define CAN_MB28_DATA2		0xFFC02F88	/* Mailbox 28 Data Word 2 [47:32] Register	*/
-#define CAN_MB28_DATA3		0xFFC02F8C	/* Mailbox 28 Data Word 3 [63:48] Register	*/
-#define CAN_MB28_LENGTH		0xFFC02F90	/* Mailbox 28 Data Length Code Register		*/
-#define CAN_MB28_TIMESTAMP	0xFFC02F94	/* Mailbox 28 Time Stamp Value Register		*/
-#define CAN_MB28_ID0		0xFFC02F98	/* Mailbox 28 Identifier Low Register		*/
-#define CAN_MB28_ID1		0xFFC02F9C	/* Mailbox 28 Identifier High Register		*/
-
-#define CAN_MB29_DATA0		0xFFC02FA0	/* Mailbox 29 Data Word 0 [15:0] Register	*/
-#define CAN_MB29_DATA1		0xFFC02FA4	/* Mailbox 29 Data Word 1 [31:16] Register	*/
-#define CAN_MB29_DATA2		0xFFC02FA8	/* Mailbox 29 Data Word 2 [47:32] Register	*/
-#define CAN_MB29_DATA3		0xFFC02FAC	/* Mailbox 29 Data Word 3 [63:48] Register	*/
-#define CAN_MB29_LENGTH		0xFFC02FB0	/* Mailbox 29 Data Length Code Register		*/
-#define CAN_MB29_TIMESTAMP	0xFFC02FB4	/* Mailbox 29 Time Stamp Value Register		*/
-#define CAN_MB29_ID0		0xFFC02FB8	/* Mailbox 29 Identifier Low Register		*/
-#define CAN_MB29_ID1		0xFFC02FBC	/* Mailbox 29 Identifier High Register		*/
-
-#define CAN_MB30_DATA0		0xFFC02FC0	/* Mailbox 30 Data Word 0 [15:0] Register	*/
-#define CAN_MB30_DATA1		0xFFC02FC4	/* Mailbox 30 Data Word 1 [31:16] Register	*/
-#define CAN_MB30_DATA2		0xFFC02FC8	/* Mailbox 30 Data Word 2 [47:32] Register	*/
-#define CAN_MB30_DATA3		0xFFC02FCC	/* Mailbox 30 Data Word 3 [63:48] Register	*/
-#define CAN_MB30_LENGTH		0xFFC02FD0	/* Mailbox 30 Data Length Code Register		*/
-#define CAN_MB30_TIMESTAMP	0xFFC02FD4	/* Mailbox 30 Time Stamp Value Register		*/
-#define CAN_MB30_ID0		0xFFC02FD8	/* Mailbox 30 Identifier Low Register		*/
-#define CAN_MB30_ID1		0xFFC02FDC	/* Mailbox 30 Identifier High Register		*/
-
-#define CAN_MB31_DATA0		0xFFC02FE0	/* Mailbox 31 Data Word 0 [15:0] Register	*/
-#define CAN_MB31_DATA1		0xFFC02FE4	/* Mailbox 31 Data Word 1 [31:16] Register	*/
-#define CAN_MB31_DATA2		0xFFC02FE8	/* Mailbox 31 Data Word 2 [47:32] Register	*/
-#define CAN_MB31_DATA3		0xFFC02FEC	/* Mailbox 31 Data Word 3 [63:48] Register	*/
-#define CAN_MB31_LENGTH		0xFFC02FF0	/* Mailbox 31 Data Length Code Register		*/
-#define CAN_MB31_TIMESTAMP	0xFFC02FF4	/* Mailbox 31 Time Stamp Value Register		*/
-#define CAN_MB31_ID0		0xFFC02FF8	/* Mailbox 31 Identifier Low Register		*/
-#define CAN_MB31_ID1		0xFFC02FFC	/* Mailbox 31 Identifier High Register		*/
-
-/* CAN Mailbox Area Macros				*/
-#define CAN_MB_ID1(x)		(CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)		(CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)	(CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)	(CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)		(CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)		(CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)		(CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)		(CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-/* PLL_CTL Masks */
-#define PLL_CLKIN			0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2		0x0001  /* Pass CLKIN/2 to PLL */
-#define DF					0x0001	 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2					*/
-#define PLL_OFF				0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF			0x0008  /* Core clock off */
-#define STOPCK				0x0008	/* Core Clock Off									*/
-#define PDWN				0x0020  /* Put the PLL in a Deep Sleep state */
-#define	IN_DELAY			0x0014	/* EBIU Input Delay Select			*/
-#define	OUT_DELAY			0x00C0	/* EBIU Output Delay Select			*/
-#define BYPASS				0x0100  /* Bypass the PLL */
-#define	MSEL			0x7E00	/* Multiplier Select For CCLK/VCO Factors			*/
-
-/* PLL_CTL Macros 											*/
-#ifdef _MISRA_RULES
-#define	SET_MSEL(x)		(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#define SET_OUT_DELAY(x)	(((x)&0x03u) << 0x6)
-#define SET_IN_DELAY(x)		((((x)&0x02u) << 0x3) | (((x)&0x01u) << 0x2))
-#else
-#define	SET_MSEL(x)		(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL		*/
-#define SET_OUT_DELAY(x)	(((x)&0x03) << 0x6)
-#define SET_IN_DELAY(x)		((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL				0x000F	/* System Select						*/
-#define	CSEL				0x0030	/* Core Select							*/
-#define CSEL_DIV1		0x0000	/* 		CCLK = VCO / 1					*/
-#define CSEL_DIV2		0x0010	/* 		CCLK = VCO / 2					*/
-#define	CSEL_DIV4		0x0020	/* 		CCLK = VCO / 4					*/
-#define	CSEL_DIV8		0x0030	/* 		CCLK = VCO / 8					*/
-
-#define SCLK_DIV(x)			(x)		/* SCLK = VCO / x */
-
-#define CCLK_DIV1			0x0000  /* CCLK = VCO / 1 */
-#define CCLK_DIV2			0x0010  /* CCLK = VCO / 2 */
-#define CCLK_DIV4			0x0020  /* CCLK = VCO / 4 */
-#define CCLK_DIV8			0x0030  /* CCLK = VCO / 8 */
-
-/* PLL_DIV Macros														*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)			((x)&0xFu)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#else
-#define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL	*/
-#endif /* _MISRA_RULES */
-
-/* PLL_STAT Masks																	*/
-#define ACTIVE_PLLENABLED	0x0001	/* Processor In Active Mode With PLL Enabled	*/
-#define	FULL_ON				0x0002	/* Processor In Full On Mode					*/
-#define ACTIVE_PLLDISABLED	0x0004	/* Processor In Active Mode With PLL Disabled	*/
-#define	PLL_LOCKED			0x0020	/* PLL_LOCKCNT Has Been Reached					*/
-
-/* VR_CTL Masks																	*/
-#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
-#define	HIBERNATE		0x0000	/* 		Powerdown/Bypass On-Board Regulation	*/
-#define	FREQ_333		0x0001	/* 		Switching Frequency Is 333 kHz			*/
-#define	FREQ_667		0x0002	/* 		Switching Frequency Is 667 kHz			*/
-#define	FREQ_1000		0x0003	/* 		Switching Frequency Is 1 MHz			*/
-
-#define GAIN			0x000C	/* Voltage Level Gain	*/
-#define	GAIN_5			0x0000	/* 		GAIN = 5		*/
-#define	GAIN_10			0x0004	/* 		GAIN = 10		*/
-#define	GAIN_20			0x0008	/* 		GAIN = 20		*/
-#define	GAIN_50			0x000C	/* 		GAIN = 50		*/
-
-#define	VLEV			0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications	*/
-#define	VLEV_100		0x0090	/* 	VLEV = 1.00 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_105		0x00A0	/* 	VLEV = 1.05 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_110		0x00B0	/* 	VLEV = 1.10 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_115		0x00C0	/* 	VLEV = 1.15 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_120		0x00D0	/* 	VLEV = 1.20 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_125		0x00E0	/* 	VLEV = 1.25 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_130		0x00F0	/* 	VLEV = 1.30 V (See Datasheet for Regulator Tolerance)	*/
-
-#define	WAKE			0x0100	/* Enable RTC/Reset Wakeup From Hibernate	*/
-#define	CANWE			0x0200	/* Enable CAN Wakeup From Hibernate */
-#define	MXVRWE			0x0400	/* Enable MXVR Wakeup From Hibernate	*/
-#define	SCKELOW			0x8000	/* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* SWRST Mask */
-#define SYSTEM_RESET	0x0007	/* Initiates A System Software Reset			*/
-#define	DOUBLE_FAULT	0x0008	/* Core Double Fault Causes Reset				*/
-#define RESET_DOUBLE	0x2000	/* SW Reset Generated By Core Double-Fault		*/
-#define RESET_WDOG		0x4000	/* SW Reset Generated By Watchdog Timer			*/
-#define RESET_SOFTWARE	0x8000	/* SW Reset Occurred Since Last Read Of SWRST	*/
-
-/* SYSCR Masks																				*/
-#define BMODE			0x0006	/* Boot Mode - Latched During HW Reset From Mode Pins	*/
-#define	NOBOOT			0x0010	/* Execute From L1 or ASYNC Bank 0 When BMODE = 0		*/
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ	        0x00000001      /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ		0x00000002      /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ		0x00000004      /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ	        0x00000008      /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ	        0x00000010      /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ		0x00000020      /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ	        0x00000040      /* UART0 Error Interrupt Request */
-#define RTC_IRQ			0x00000080      /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ		0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ		0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ		0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ		0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ		0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ		0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ		0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ		0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ		0x00010000      /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ		0x00020000      /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ		0x00040000      /* Timer 2 Interrupt Request */
-#define PFA_IRQ			0x00080000      /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ			0x00100000      /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ		0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ		0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ		0x00800000      /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ		0x01000000	/* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ		0x02000000	/* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ		0x04000000	/* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ   	        0x08000000      /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ		0x10000000	/* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ		0x20000000	/* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ		0x40000000	/* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ		0x80000000	/* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ		DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ		DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1								*/
-#define CAN_ERR_IRQ			0x00000001	/* CAN Error Interrupt Request */
-#define DMA8_IRQ			0x00000002	/* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ			0x00000004	/* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ			0x00000008	/* DMA Channel 10 (SPORT3 RX) Interrupt Request	*/
-#define DMA11_IRQ			0x00000010	/* DMA Channel 11 (SPORT3 TX) Interrupt Request	*/
-#define DMA12_IRQ			0x00000020	/* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ			0x00000040	/* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ			0x00000080	/* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ			0x00000100	/* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ			0x00000200	/* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ			0x00000400	/* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ			0x00000800	/* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ			0x00001000	/* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ			0x00002000	/* TWI0 Interrupt Request */
-#define TWI1_IRQ			0x00004000	/* TWI1 Interrupt Request */
-#define CAN_RX_IRQ			0x00008000	/* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ			0x00010000	/* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ			0x00020000	/* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ			0x00040000	/* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ 	                0x00080000      /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ   	                0x00100000      /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ   	                0x00200000      /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ		MDMA1_0_IRQ
-#define MDMA1_IRQ		MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IAR0 Macros															*/
-#define P0_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #0 assigned IVG #x	*/
-#define P1_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #1 assigned IVG #x	*/
-#define P2_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #2 assigned IVG #x	*/
-#define P3_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #3 assigned IVG #x	*/
-#define P4_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #4 assigned IVG #x	*/
-#define P5_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #5 assigned IVG #x	*/
-#define P6_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #6 assigned IVG #x	*/
-#define P7_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #7 assigned IVG #x	*/
-
-/* SIC_IAR1 Macros															*/
-#define P8_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #8 assigned IVG #x	*/
-#define P9_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #9 assigned IVG #x	*/
-#define P10_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #10 assigned IVG #x	*/
-#define P11_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #11 assigned IVG #x	*/
-#define P12_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #12 assigned IVG #x	*/
-#define P13_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #13 assigned IVG #x	*/
-#define P14_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #14 assigned IVG #x	*/
-#define P15_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #15 assigned IVG #x	*/
-
-/* SIC_IAR2 Macros															*/
-#define P16_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #16 assigned IVG #x	*/
-#define P17_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #17 assigned IVG #x	*/
-#define P18_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #18 assigned IVG #x	*/
-#define P19_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #19 assigned IVG #x	*/
-#define P20_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #20 assigned IVG #x	*/
-#define P21_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #21 assigned IVG #x	*/
-#define P22_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #22 assigned IVG #x	*/
-#define P23_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #23 assigned IVG #x	*/
-
-/* SIC_IAR3 Macros															*/
-#define P24_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #24 assigned IVG #x	*/
-#define P25_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #25 assigned IVG #x	*/
-#define P26_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #26 assigned IVG #x	*/
-#define P27_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #27 assigned IVG #x	*/
-#define P28_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #28 assigned IVG #x	*/
-#define P29_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #29 assigned IVG #x	*/
-#define P30_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #30 assigned IVG #x	*/
-#define P31_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #31 assigned IVG #x	*/
-
-/* SIC_IAR4 Macros															*/
-#define P32_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #32 assigned IVG #x	*/
-#define P33_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #33 assigned IVG #x	*/
-#define P34_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #34 assigned IVG #x	*/
-#define P35_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #35 assigned IVG #x	*/
-#define P36_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #36 assigned IVG #x	*/
-#define P37_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #37 assigned IVG #x	*/
-#define P38_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #38 assigned IVG #x	*/
-#define P39_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #39 assigned IVG #x	*/
-
-/* SIC_IAR5 Macros															*/
-#define P40_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #40 assigned IVG #x	*/
-#define P41_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #41 assigned IVG #x	*/
-#define P42_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #42 assigned IVG #x	*/
-#define P43_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #43 assigned IVG #x	*/
-#define P44_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #44 assigned IVG #x	*/
-#define P45_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #45 assigned IVG #x	*/
-#define P46_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #46 assigned IVG #x	*/
-#define P47_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #47 assigned IVG #x	*/
-
-/* SIC_IAR6 Macros															*/
-#define P48_IVG(x)		(((x)-_MF7)&_MF15)			/* Peripheral #48 assigned IVG #x	*/
-#define P49_IVG(x)		(((x)-_MF7)&_MF15) << 0x4	/* Peripheral #49 assigned IVG #x	*/
-#define P50_IVG(x)		(((x)-_MF7)&_MF15) << 0x8	/* Peripheral #50 assigned IVG #x	*/
-#define P51_IVG(x)		(((x)-_MF7)&_MF15) << 0xC	/* Peripheral #51 assigned IVG #x	*/
-#define P52_IVG(x)		(((x)-_MF7)&_MF15) << 0x10	/* Peripheral #52 assigned IVG #x	*/
-#define P53_IVG(x)		(((x)-_MF7)&_MF15) << 0x14	/* Peripheral #53 assigned IVG #x	*/
-#define P54_IVG(x)		(((x)-_MF7)&_MF15) << 0x18	/* Peripheral #54 assigned IVG #x	*/
-#define P55_IVG(x)		(((x)-_MF7)&_MF15) << 0x1C	/* Peripheral #55 assigned IVG #x	*/
-
-/* SIC_IARx Macros */
-
-#ifdef _MISRA_RULES
-#define PX_IVG_CLR(x)  (0xFFFFFFFFu ^ (0xFu << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
-/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11);	// Clears IVG Level of Peripheral #11 */
-#define PX_IVG(x,y)     ((((y)-7u)&0xFu) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
-/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);	// Sets Peripheral #11 to IVG8 */
-#else
-#define PX_IVG_CLR(x)  (0xFFFFFFFF ^ (0xF << (((x)%8)*4)))  /* Clear IVG Select for Peripheral #x */
-/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11);	// Clears IVG Level of Peripheral #11 */
-#define PX_IVG(x,y)     ((((y)-7)&0xF) << (((x)%8)*4))      /* Set IVG Select to #y for Peripheral #x */
-/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8);	// Sets Peripheral #11 to IVG8 */
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks*/
-#define SIC_UNMASK_ALL 0x00000000         /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL   0xFFFFFFFF         /* Mask all peripheral interrupts   */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F))     /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks*/
-#define IWR_DISABLE_ALL 0x00000000        /* Wakeup Disable all peripherals   */
-#define IWR_ENABLE_ALL  0xFFFFFFFF        /* Wakeup Enable all peripherals    */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define WDEV(x)			(((x)<<1) & 0x0006u) 	/* event generated on roll over */
-#else
-#define WDEV(x)			(((x)<<1) & 0x0006) 	/* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET		0x0000 				/* generate reset event on roll over */
-#define WDEV_NMI		0x0002 				/* generate NMI event on roll over */
-#define WDEV_GPI		0x0004 				/* generate GP IRQ on roll over */
-#define WDEV_NONE		0x0006 				/* no event on roll over */
-#define WDEN			0x0FF0 				/* enable watchdog */
-#define WDDIS			0x0AD0 				/* disable watchdog */
-#define WDRO			0x8000 				/* watchdog rolled over latch */
-
-/* deprecated WDOG_CTL Register Masks for legacy code */
-#define ICTL WDEV
-#define ENABLE_RESET 	WDEV_RESET
-#define WDOG_RESET 		WDEV_RESET
-#define ENABLE_NMI 		WDEV_NMI
-#define WDOG_NMI 		WDEV_NMI
-#define ENABLE_GPI 		WDEV_GPI
-#define WDOG_GPI 		WDEV_GPI
-#define DISABLE_EVT 	WDEV_NONE
-#define WDOG_NONE 		WDEV_NONE
-
-#define TMR_EN 			WDEN
-#define WDOG_DISABLE		WDDIS
-#define TRO 			WDRO
-
-#define ICTL_P0			0x01
-#define ICTL_P1			0x02
-#define TRO_P			0x0F
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM register */
-#define	RTSEC		0x0000003F	/* Real-Time Clock Seconds */
-#define	RTMIN		0x00000FC0	/* Real-Time Clock Minutes */
-#define	RTHR		0x0001F000	/* Real-Time Clock Hours */
-#define	RTDAY		0xFFFE0000	/* Real-Time Clock Days */
-
-/* RTC_ICTL register */
-#define	SWIE		0x0001		/* Stopwatch Interrupt Enable */
-#define	AIE			0x0002		/* Alarm Interrupt Enable */
-#define	SIE			0x0004		/* Seconds (1 Hz) Interrupt Enable */
-#define	MIE			0x0008		/* Minutes Interrupt Enable */
-#define	HIE			0x0010		/* Hours Interrupt Enable */
-#define	DIE			0x0020		/* 24 Hours (Days) Interrupt Enable */
-#define	DAIE		0x0040		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
-#define	WCIE		0x8000		/* Write Complete Interrupt Enable */
-
-/* RTC_ISTAT register */
-#define	SWEF		0x0001		/* Stopwatch Event Flag */
-#define	AEF			0x0002		/* Alarm Event Flag */
-#define	SEF			0x0004		/* Seconds (1 Hz) Event Flag */
-#define	MEF			0x0008		/* Minutes Event Flag */
-#define	HEF			0x0010		/* Hours Event Flag */
-#define	DEF			0x0020		/* 24 Hours (Days) Event Flag */
-#define	DAEF		0x0040		/* Day Alarm (Day, Hour, Minute, Second) Event Flag */
-#define	WPS			0x4000		/* Write Pending Status (RO) */
-#define	WCOM		0x8000		/* Write Complete */
-
-/* RTC_FAST Mask (RTC_PREN Mask) */
-#define ENABLE_PRESCALE      0x00000001  /* Enable prescaler so RTC runs at 1 Hz */
-#define PREN                 0x00000001
-         	/* ** Must be set after power-up for proper operation of RTC */
-
-/* RTC_ALARM Macro			z=day		y=hr	x=min	w=sec		*/
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)	((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* Deprecated RTC_STAT and RTC_ALARM Masks										*/
-#define	RTC_SEC			RTSEC	/* Real-Time Clock Seconds	*/
-#define	RTC_MIN			RTMIN	/* Real-Time Clock Minutes	*/
-#define	RTC_HR			RTHR	/* Real-Time Clock Hours	*/
-#define	RTC_DAY			RTDAY	/* Real-Time Clock Days		*/
-
-/* Deprecated RTC_ICTL/RTC_ISTAT Masks																		*/
-#define	STOPWATCH		SWIE		/* Stopwatch Interrupt Enable								*/
-#define	ALARM			AIE		/* Alarm Interrupt Enable									*/
-#define	SECOND			SIE		/* Seconds (1 Hz) Interrupt Enable							*/
-#define	MINUTE			MIE		/* Minutes Interrupt Enable									*/
-#define	HOUR			HIE		/* Hours Interrupt Enable									*/
-#define	DAY				DIE		/* 24 Hours (Days) Interrupt Enable							*/
-#define	DAY_ALARM		DAIE		/* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable	*/
-#define	WRITE_COMPLETE	WCIE		/* Write Complete Interrupt Enable							*/
-
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-/* UARTx_LCR Register */
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select */
-#else
-#define WLS(x)		(((x)-5) & 0x03)	/* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB			0x04				/* Stop Bits			*/
-#define PEN			0x08				/* Parity Enable		*/
-#define EPS			0x10				/* Even Parity Select	*/
-#define STP			0x20				/* Stick Parity			*/
-#define SB			0x40				/* Set Break			*/
-#define DLAB		0x80				/* Divisor Latch Access	*/
-
-#define DLAB_P		0x07
-#define SB_P		0x06
-#define STP_P		0x05
-#define EPS_P		0x04
-#define PEN_P		0x03
-#define STB_P		0x02
-#define WLS_P1		0x01
-#define WLS_P0		0x00
-
-/* UARTx_MCR Register */
-#define LOOP_ENA	0x10	/* Loopback Mode Enable */
-#define LOOP_ENA_P	0x04
-/* Deprecated UARTx_MCR Mask										*/
-
-/* UARTx_LSR Register */
-#define DR			0x01	/* Data Ready				*/
-#define OE			0x02	/* Overrun Error			*/
-#define PE			0x04	/* Parity Error				*/
-#define FE			0x08	/* Framing Error			*/
-#define BI			0x10	/* Break Interrupt			*/
-#define THRE		0x20	/* THR Empty				*/
-#define TEMT		0x40	/* TSR and UART_THR Empty	*/
-
-#define TEMP_P		0x06
-#define THRE_P		0x05
-#define BI_P		0x04
-#define FE_P		0x03
-#define PE_P		0x02
-#define OE_P		0x01
-#define DR_P		0x00
-
-/* UARTx_IER Register */
-#define ERBFI		0x01		/* Enable Receive Buffer Full Interrupt		*/
-#define ETBEI		0x02		/* Enable Transmit Buffer Empty Interrupt	*/
-#define ELSI		0x04		/* Enable RX Status Interrupt				*/
-
-#define ELSI_P		0x02
-#define ETBEI_P		0x01
-#define ERBFI_P		0x00
-
-/* UARTx_IIR Register */
-#ifdef _MISRA_RULES
-#define STATUS(x)	(((x) << 1) & 0x06u)
-#else
-#define STATUS(x)	(((x) << 1) & 0x06)
-#endif /* _MISRA_RULES */
-#define NINT		0x01
-#define STATUS_P1	0x02
-#define STATUS_P0	0x01
-#define NINT_P		0x00
-
-/* UARTx_GCTL Register */
-#define UCEN		0x01		/* Enable UARTx Clocks				*/
-#define IREN		0x02		/* Enable IrDA Mode					*/
-#define TPOLC		0x04		/* IrDA TX Polarity Change			*/
-#define RPOLC		0x08		/* IrDA RX Polarity Change			*/
-#define FPE			0x10		/* Force Parity Error On Transmit	*/
-#define FFE			0x20		/* Force Framing Error On Transmit	*/
-
-#define FFE_P		0x05
-#define FPE_P		0x04
-#define RPOLC_P		0x03
-#define TPOLC_P		0x02
-#define IREN_P		0x01
-#define UCEN_P		0x00
-
-
-/* **********  SERIAL PORT MASKS  ********************** */
-/* SPORTx_TCR1 Masks */
-#define TSPEN		0x0001  /* TX enable  */
-#define ITCLK		0x0002  /* Internal TX Clock Select  */
-#define TDTYPE		0x000C  /* TX Data Formatting Select */
-#define DTYPE_NORM	0x0000		/* Data Format Normal							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define TLSBIT		0x0010  /* TX Bit Order */
-#define ITFS		0x0200  /* Internal TX Frame Sync Select  */
-#define TFSR		0x0400  /* TX Frame Sync Required Select  */
-#define DITFS		0x0800  /* Data Independent TX Frame Sync Select  */
-#define LTFS		0x1000  /* Low TX Frame Sync Select  */
-#define LATFS		0x2000  /* Late TX Frame Sync Select  */
-#define TCKFE		0x4000  /* TX Clock Falling Edge Select  */
-/* SPORTx_RCR1 Deprecated Masks															*/
-#define TULAW		DTYPE_ULAW		/* Compand Using u-Law							*/
-#define TALAW		DTYPE_ALAW			/* Compand Using A-Law							*/
-
-/* SPORTx_TCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT TX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#define TXSE		0x0100  /*TX Secondary Enable */
-#define TSFSE		0x0200  /*TX Stereo Frame Sync Enable */
-#define TRFST		0x0400  /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN		0x0001  /* RX enable  */
-#define IRCLK		0x0002  /* Internal RX Clock Select  */
-#define RDTYPE		0x000C  /* RX Data Formatting Select */
-#define DTYPE_NORM	0x0000		/* no companding							*/
-#define DTYPE_ULAW	0x0008		/* Compand Using u-Law							*/
-#define DTYPE_ALAW	0x000C		/* Compand Using A-Law							*/
-#define RLSBIT		0x0010  /* RX Bit Order */
-#define IRFS		0x0200  /* Internal RX Frame Sync Select  */
-#define RFSR		0x0400  /* RX Frame Sync Required Select  */
-#define LRFS		0x1000  /* Low RX Frame Sync Select  */
-#define LARFS		0x2000  /* Late RX Frame Sync Select  */
-#define RCKFE		0x4000  /* RX Clock Falling Edge Select  */
-/* SPORTx_RCR1 Deprecated Masks															*/
-#define RULAW		DTYPE_ULAW		/* Compand Using u-Law							*/
-#define RALAW		DTYPE_ALAW			/* Compand Using A-Law							*/
-
-/* SPORTx_RCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)		((x)&0x1Fu)	/* SPORT RX Word Length (2 - 31)				*/
-#else
-#define SLEN(x)		((x)&0x1F)	/* SPORT RX Word Length (2 - 31)				*/
-#endif /* _MISRA_RULES */
-#define RXSE		0x0100  /*RX Secondary Enable */
-#define RSFSE		0x0200  /*RX Stereo Frame Sync Enable */
-#define RRFST		0x0400  /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE		0x0001		/*RX FIFO Not Empty Status */
-#define RUVF		0x0002  	/*RX Underflow Status */
-#define ROVF		0x0004		/*RX Overflow Status */
-#define TXF			0x0008		/*TX FIFO Full Status */
-#define TUVF		0x0010  	/*TX Underflow Status */
-#define TOVF		0x0020  	/*TX Overflow Status */
-#define TXHRE		0x0040  	/*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define WSIZE			0x0000F000 	/*Multichannel Window Size Field */
-#define WOFF			0x000003FF 	/*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros															*/
-#ifdef _MISRA_RULES
-#define SET_WOFF(x)		((x) & 0x3FFu) 	/* Multichannel Window Offset Field			*/
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define SET_WSIZE(x)	(((((x)>>0x3)-1u)&0xFu) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#else
-#define SET_WOFF(x)		((x) & 0x3FF) 	/* Multichannel Window Offset Field			*/
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits						*/
-#define SET_WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1	*/
-#endif /* _MISRA_RULES */
-
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM		0x0003 	/*Multichannel Clock Recovery Mode */
-#define REC_BYPASS	0x0000		/* Bypass Mode (No Clock Recovery)				*/
-#define REC_2FROM4	0x0002		/* Recover 2 MHz Clock from 4 MHz Clock			*/
-#define REC_8FROM16	0x0003		/* Recover 8 MHz Clock from 16 MHz Clock		*/
-#define MCDTXPE		0x0004 	/*Multichannel DMA Transmit Packing */
-#define MCDRXPE		0x0008 	/*Multichannel DMA Receive Packing */
-#define MCMEN		0x0010 	/*Multichannel Frame Mode Enable */
-#define FSDR		0x0080 	/*Multichannel Frame Sync to Data Relationship */
-#define MFD			0xF000 	/*Multichannel Frame Delay    */
-#define MFD_0		0x0000		/* Multichannel Frame Delay = 0					*/
-#define MFD_1		0x1000		/* Multichannel Frame Delay = 1					*/
-#define MFD_2		0x2000		/* Multichannel Frame Delay = 2					*/
-#define MFD_3		0x3000		/* Multichannel Frame Delay = 3					*/
-#define MFD_4		0x4000		/* Multichannel Frame Delay = 4					*/
-#define MFD_5		0x5000		/* Multichannel Frame Delay = 5					*/
-#define MFD_6		0x6000		/* Multichannel Frame Delay = 6					*/
-#define MFD_7		0x7000		/* Multichannel Frame Delay = 7					*/
-#define MFD_8		0x8000		/* Multichannel Frame Delay = 8					*/
-#define MFD_9		0x9000		/* Multichannel Frame Delay = 9					*/
-#define MFD_10		0xA000		/* Multichannel Frame Delay = 10				*/
-#define MFD_11		0xB000		/* Multichannel Frame Delay = 11				*/
-#define MFD_12		0xC000		/* Multichannel Frame Delay = 12				*/
-#define MFD_13		0xD000		/* Multichannel Frame Delay = 13				*/
-#define MFD_14		0xE000		/* Multichannel Frame Delay = 14				*/
-#define MFD_15		0xF000		/* Multichannel Frame Delay = 15				*/
-
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-/*  PPI_CONTROL Masks         */
-#define PORT_EN		0x0001  /* PPI Port Enable  */
-#define PORT_DIR	0x0002  /* PPI Port Direction       */
-#define XFR_TYPE	0x000C  /* PPI Transfer Type  */
-#define PORT_CFG	0x0030  /* PPI Port Configuration */
-#define FLD_SEL		0x0040  /* PPI Active Field Select */
-#define PACK_EN		0x0080  /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN		0x0200  /* PPI Skip Element Enable */
-#define SKIP_EO		0x0400  /* PPI Skip Even/Odd Elements */
-#define DLENGTH		0x3800  /* PPI Data Length  */
-#define DLEN_8		0x0	     /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10		0x0800		/* Data Length = 10 Bits			*/
-#define DLEN_11		0x1000		/* Data Length = 11 Bits			*/
-#define DLEN_12		0x1800		/* Data Length = 12 Bits			*/
-#define DLEN_13		0x2000		/* Data Length = 13 Bits			*/
-#define DLEN_14		0x2800		/* Data Length = 14 Bits			*/
-#define DLEN_15		0x3000		/* Data Length = 15 Bits			*/
-#define DLEN_16		0x3800		/* Data Length = 16 Bits			*/
-#ifdef _MISRA_RULES
-#define DLEN(x)		((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x)		((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL			0xC000  /* PPI Signal Polarities       */
-#define POLC		0x4000		/* PPI Clock Polarity				*/
-#define POLS		0x8000		/* PPI Frame Sync Polarity			*/
-
-
-/* PPI_STATUS Masks                                          */
-#define FLD			0x0400  /* Field Indicator   */
-#define FT_ERR		0x0800  /* Frame Track Error */
-#define OVR			0x1000  /* FIFO Overflow Error */
-#define UNDR		0x2000  /* FIFO Underrun Error */
-#define ERR_DET		0x4000  /* Error Detected Indicator */
-#define ERR_NCOR	0x8000  /* Error Not Corrected Indicator */
-
-
-/* **********  DMA CONTROLLER MASKS  ***********************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN		0x0001  /* Channel Enable */
-#define WNR			0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8	0x0000  /* Word Size 8 bits */
-#define WDSIZE_16	0x0004  /* Word Size 16 bits */
-#define WDSIZE_32	0x0008  /* Word Size 32 bits */
-#define DMA2D		0x0010  /* 2D/1D* Mode */
-#define RESTART		0x0020  /* Restart */
-#define DI_SEL		0x0040  /* Data Interrupt Select */
-#define DI_EN		0x0080  /* Data Interrupt Enable */
-#define NDSIZE		0x0900  /* Next Descriptor Size */
-#define NDSIZE_0	0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)	*/
-#define NDSIZE_1	0x0100	/* Next Descriptor Size = 1						*/
-#define NDSIZE_2	0x0200	/* Next Descriptor Size = 2						*/
-#define NDSIZE_3	0x0300	/* Next Descriptor Size = 3						*/
-#define NDSIZE_4	0x0400	/* Next Descriptor Size = 4						*/
-#define NDSIZE_5	0x0500	/* Next Descriptor Size = 5						*/
-#define NDSIZE_6	0x0600	/* Next Descriptor Size = 6						*/
-#define NDSIZE_7	0x0700	/* Next Descriptor Size = 7						*/
-#define NDSIZE_8	0x0800	/* Next Descriptor Size = 8						*/
-#define NDSIZE_9	0x0900	/* Next Descriptor Size = 9						*/
-#define FLOW		0x7000  /* Flow Control */
-#define FLOW_STOP	0x0000	/* Stop Mode									*/
-#define FLOW_AUTO	0x1000	/* Autobuffer Mode								*/
-#define FLOW_ARRAY	0x4000	/* Descriptor Array Mode						*/
-#define FLOW_SMALL	0x6000	/* Small Model Descriptor List Mode				*/
-#define FLOW_LARGE	0x7000	/* Large Model Descriptor List Mode				*/
-
-#define DMAEN_P		0x0		/* Channel Enable */
-#define WNR_P		0x1		/* Channel Direction (W/R*) */
-#define DMA2D_P		0x4		/* 2D/1D* Mode */
-#define RESTART_P	0x5		/* Restart */
-#define DI_SEL_P	0x6		/* Data Interrupt Select */
-#define DI_EN_P		0x7		/* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE	0x0001	/* DMA Done Indicator */
-#define DMA_ERR		0x0002	/* DMA Error Indicator */
-#define DFETCH		0x0004	/* Descriptor Fetch Indicator */
-#define DMA_RUN		0x0008	/* DMA Running Indicator */
-
-#define DMA_DONE_P	0x0		/* DMA Done Indicator */
-#define DMA_ERR_P	0x1		/* DMA Error Indicator */
-#define DFETCH_P	0x2		/* Descriptor Fetch Indicator */
-#define DMA_RUN_P	0x3		/* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE			0x0040	/* DMA Channel Type Indicator */
-#define CTYPE_P			0x6		/* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8			0x0080	/* DMA 8-bit Operation Indicator   */
-#define PCAP16			0x0100	/* DMA 16-bit Operation Indicator */
-#define PCAP32			0x0200	/* DMA 32-bit Operation Indicator */
-#define PCAPWR			0x0400	/* DMA Write Operation Indicator */
-#define PCAPRD			0x0800	/* DMA Read Operation Indicator */
-#define PMAP			0xF000	/* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI		0x0000	/* PMAP PPI Port DMA */
-#define	PMAP_SPORT0RX	0x1000	/* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX	0x2000	/* PMAP SPORT0 Transmit DMA */
-#define	PMAP_SPORT1RX	0x3000	/* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX	0x4000	/* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0		0x5000	/* PMAP SPI DMA */
-#define PMAP_UART0RX		0x6000	/* PMAP UART Receive DMA */
-#define PMAP_UART0TX		0x7000	/* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
-#define	PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
-#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
-#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
-#define	PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
-
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0			0x0001	/* Enable Timer 0	*/
-#define TIMEN1			0x0002	/* Enable Timer 1	*/
-#define TIMEN2			0x0004	/* Enable Timer 2	*/
-
-#define TIMEN0_P		0x00
-#define TIMEN1_P		0x01
-#define TIMEN2_P		0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0			0x0001	/* Disable Timer 0	*/
-#define TIMDIS1			0x0002	/* Disable Timer 1	*/
-#define TIMDIS2			0x0004	/* Disable Timer 2	*/
-
-#define TIMDIS0_P		0x00
-#define TIMDIS1_P		0x01
-#define TIMDIS2_P		0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0			0x0001	/* Timer 0 Interrupt			*/
-#define TIMIL1			0x0002	/* Timer 1 Interrupt			*/
-#define TIMIL2			0x0004	/* Timer 2 Interrupt			*/
-#define TOVF_ERR0		0x0010	/* Timer 0 Counter Overflow		*/
-#define TOVF_ERR1		0x0020	/* Timer 1 Counter Overflow		*/
-#define TOVF_ERR2		0x0040	/* Timer 2 Counter Overflow		*/
-#define TRUN0			0x1000	/* Timer 0 Slave Enable Status	*/
-#define TRUN1			0x2000	/* Timer 1 Slave Enable Status	*/
-#define TRUN2			0x4000	/* Timer 2 Slave Enable Status	*/
-
-#define TIMIL0_P		0x00
-#define TIMIL1_P		0x01
-#define TIMIL2_P		0x02
-#define TOVF_ERR0_P		0x04
-#define TOVF_ERR1_P		0x05
-#define TOVF_ERR2_P		0x06
-#define TRUN0_P			0x0C
-#define TRUN1_P			0x0D
-#define TRUN2_P			0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 		TOVF_ERR0
-#define TOVL_ERR1 		TOVF_ERR1
-#define TOVL_ERR2 		TOVF_ERR2
-#define TOVL_ERR0_P		TOVF_ERR0_P
-#define TOVL_ERR1_P 	TOVF_ERR1_P
-#define TOVL_ERR2_P 	TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT			0x0001
-#define WDTH_CAP		0x0002
-#define EXT_CLK			0x0003
-#define PULSE_HI		0x0004
-#define PERIOD_CNT		0x0008
-#define IRQ_ENA			0x0010
-#define TIN_SEL			0x0020
-#define OUT_DIS			0x0040
-#define CLK_SEL			0x0080
-#define TOGGLE_HI		0x0100
-#define EMU_RUN			0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x)		(((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x)		(((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0		0x00
-#define TMODE_P1		0x01
-#define PULSE_HI_P		0x02
-#define PERIOD_CNT_P	0x03
-#define IRQ_ENA_P		0x04
-#define TIN_SEL_P		0x05
-#define OUT_DIS_P		0x06
-#define CLK_SEL_P		0x07
-#define TOGGLE_HI_P		0x08
-#define EMU_RUN_P		0x09
-#define ERR_TYP_P0		0x0E
-#define ERR_TYP_P1		0x0F
-
-
-/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
-/*  Flag I/O (FIO_) Masks */
-#define PF0			0x0001
-#define PF1			0x0002
-#define PF2			0x0004
-#define PF3			0x0008
-#define PF4			0x0010
-#define PF5			0x0020
-#define PF6			0x0040
-#define PF7			0x0080
-#define PF8			0x0100
-#define PF9			0x0200
-#define PF10		0x0400
-#define PF11		0x0800
-#define PF12		0x1000
-#define PF13		0x2000
-#define PF14		0x4000
-#define PF15		0x8000
-
-/*  PORT F BIT POSITIONS */
-#define PF0_P		0x0
-#define PF1_P		0x1
-#define PF2_P		0x2
-#define PF3_P		0x3
-#define PF4_P		0x4
-#define PF5_P		0x5
-#define PF6_P		0x6
-#define PF7_P		0x7
-#define PF8_P		0x8
-#define PF9_P		0x9
-#define PF10_P		0xA
-#define PF11_P		0xB
-#define PF12_P		0xC
-#define PF13_P		0xD
-#define PF14_P		0xE
-#define PF15_P		0xF
-
-
-/*******************   GPIO MASKS  *********************/
-/* Port C Masks */
-#define PC0		0x0001
-#define PC1		0x0002
-#define PC4		0x0010
-#define PC5		0x0020
-#define PC6		0x0040
-#define PC7		0x0080
-#define PC8		0x0100
-#define PC9		0x0200
-/* Port C Bit Positions */
-#define PC0_P	0x0
-#define PC1_P	0x1
-#define PC4_P	0x4
-#define PC5_P	0x5
-#define PC6_P	0x6
-#define PC7_P	0x7
-#define PC8_P	0x8
-#define PC9_P	0x9
-
-/* Port D */
-#define PD0		0x0001
-#define PD1		0x0002
-#define PD2		0x0004
-#define PD3		0x0008
-#define PD4		0x0010
-#define PD5		0x0020
-#define PD6		0x0040
-#define PD7		0x0080
-#define PD8		0x0100
-#define PD9		0x0200
-#define PD10	0x0400
-#define PD11	0x0800
-#define PD12	0x1000
-#define PD13	0x2000
-#define PD14	0x4000
-#define PD15	0x8000
-/* Port D Bit Positions */
-#define PD0_P	0x0
-#define PD1_P	0x1
-#define PD2_P	0x2
-#define PD3_P	0x3
-#define PD4_P	0x4
-#define PD5_P	0x5
-#define PD6_P	0x6
-#define PD7_P	0x7
-#define PD8_P	0x8
-#define PD9_P	0x9
-#define PD10_P	0xA
-#define PD11_P	0xB
-#define PD12_P	0xC
-#define PD13_P	0xD
-#define PD14_P	0xE
-#define PD15_P	0xF
-
-/* Port E */
-#define PE0		0x0001
-#define PE1		0x0002
-#define PE2		0x0004
-#define PE3		0x0008
-#define PE4		0x0010
-#define PE5		0x0020
-#define PE6		0x0040
-#define PE7		0x0080
-#define PE8		0x0100
-#define PE9		0x0200
-#define PE10	0x0400
-#define PE11	0x0800
-#define PE12	0x1000
-#define PE13	0x2000
-#define PE14	0x4000
-#define PE15	0x8000
-/* Port E Bit Positions */
-#define PE0_P	0x0
-#define PE1_P	0x1
-#define PE2_P	0x2
-#define PE3_P	0x3
-#define PE4_P	0x4
-#define PE5_P	0x5
-#define PE6_P	0x6
-#define PE7_P	0x7
-#define PE8_P	0x8
-#define PE9_P	0x9
-#define PE10_P	0xA
-#define PE11_P	0xB
-#define PE12_P	0xC
-#define PE13_P	0xD
-#define PE14_P	0xE
-#define PE15_P	0xF
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-/* SPIx_CTL Masks */
-#define	TIMOD		0x0003		/* Transfer Initiate Mode							*/
-#define RDBR_CORE	0x0000		/* 		RDBR Read Initiates, IRQ When RDBR Full		*/
-#define	TDBR_CORE	0x0001		/* 		TDBR Write Initiates, IRQ When TDBR Empty	*/
-#define RDBR_DMA	0x0002		/* 		DMA Read, DMA Until FIFO Empty				*/
-#define TDBR_DMA	0x0003		/* 		DMA Write, DMA Until FIFO Full				*/
-#define SZ			0x0004		/* Send Zero (When TDBR Empty, Send Zero/Last*)		*/
-#define GM			0x0008		/* Get More (When RDBR Full, Overwrite/Discard*)	*/
-#define PSSE		0x0010		/* Slave-Select Input Enable						*/
-#define EMISO		0x0020		/* Enable MISO As Output							*/
-#define SIZE		0x0100		/* Size of Words (16/8* Bits)						*/
-#define LSBF		0x0200		/* LSB First										*/
-#define CPHA		0x0400		/* Clock Phase										*/
-#define CPOL		0x0800		/* Clock Polarity									*/
-#define MSTR		0x1000		/* Master/Slave*									*/
-#define WOM			0x2000		/* Write Open Drain Master							*/
-#define SPE			0x4000		/* SPI Enable										*/
-
-/* SPIx_FLG Masks */
-#define FLS1	0x0002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2	0x0004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3	0x0008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4	0x0010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5	0x0020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6	0x0040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7	0x0080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-#define FLG1	0x0200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2	0x0400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3	0x0800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4	0x1000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5	0x2000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6	0x4000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7	0x8000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPIx_FLG Bit Positions */
-#define FLS1_P	0x0001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P	0x0002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P	0x0003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P	0x0004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P	0x0005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P	0x0006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P	0x0007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P	0x0009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P	0x000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P	0x000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P	0x000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P	0x000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P	0x000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P	0x000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPIx_STAT Masks */
-#define SPIF	0x0001  /* Set (=1) when SPI single-word transfer complete */
-#define MODF	0x0002  /* Set (=1) in a master device when some other device tries to become master */
-#define TXE		0x0004  /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS		0x0008  /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY	0x0010  /* Set (=1) when data is received with RDBR full */
-#define RXS		0x0020  /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL	0x0040  /* When set (=1), corrupt data may have been transmitted  */
-
-/* SPIx_FLG Masks																	*/
-#define FLG1E	0xFDFF		/* Activates SPI_FLOUT1 							*/
-#define FLG2E	0xFBFF		/* Activates SPI_FLOUT2								*/
-#define FLG3E	0xF7FF		/* Activates SPI_FLOUT3								*/
-#define FLG4E	0xEFFF		/* Activates SPI_FLOUT4								*/
-#define FLG5E	0xDFFF		/* Activates SPI_FLOUT5								*/
-#define FLG6E	0xBFFF		/* Activates SPI_FLOUT6								*/
-#define FLG7E	0x7FFF		/* Activates SPI_FLOUT7								*/
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN          0x0001  /* Enable CLKOUT */
-#define	AMBEN_NONE      0x0000  /* All Banks Disabled */
-#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO          0x0100  /* DMA has priority over core for for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P		0x0000	/* Enable CLKOUT */
-#define AMBEN_P0		0x0001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1		0x0002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2		0x0003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN			0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 		0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1			0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2			0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3			0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4			0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1			0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2			0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3			0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4			0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1			0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2			0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3			0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0			0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1			0x00000100  /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2			0x00000200  /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3			0x00000300  /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4			0x00000400  /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5			0x00000500  /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6			0x00000600  /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7			0x00000700  /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8			0x00000800  /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9			0x00000900  /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10		0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11		0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12		0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13		0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14		0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15		0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1			0x00001000  /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2			0x00002000  /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3			0x00003000  /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4			0x00004000  /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5			0x00005000  /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6			0x00006000  /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7			0x00007000  /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8			0x00008000  /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9			0x00009000  /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10		0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11		0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12		0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13		0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14		0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15		0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN			0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL		0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1			0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2			0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3			0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4			0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1			0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2			0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3			0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4			0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1			0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2			0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3			0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0			0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1			0x01000000  /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2			0x02000000  /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3			0x03000000  /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4			0x04000000  /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5			0x05000000  /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6			0x06000000  /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7			0x07000000  /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8			0x08000000  /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9			0x09000000  /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10		0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11		0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12		0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13		0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14		0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15		0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1			0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2			0x20000000  /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3			0x30000000  /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4			0x40000000  /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5			0x50000000  /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6			0x60000000  /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7			0x70000000  /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8			0x80000000  /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9			0x90000000  /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10		0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11		0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12		0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13		0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14		0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15		0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN			0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL		0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1			0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2			0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3			0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4			0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1			0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2			0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3			0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4			0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1			0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2			0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3			0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0			0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1			0x00000100  /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2			0x00000200  /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3			0x00000300  /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4			0x00000400  /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5			0x00000500  /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6			0x00000600  /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7			0x00000700  /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8			0x00000800  /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9			0x00000900  /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10		0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11		0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12		0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13		0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14		0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15		0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1			0x00001000  /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2			0x00002000  /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3			0x00003000  /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4			0x00004000  /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5			0x00005000  /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6			0x00006000  /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7			0x00007000  /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8			0x00008000  /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9			0x00009000  /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10		0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11		0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12		0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13		0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14		0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15		0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN			0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL		0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1			0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2			0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3			0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4			0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1			0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2			0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3			0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4			0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1			0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2			0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3			0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0			0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1			0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2			0x02000000  /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3			0x03000000  /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4			0x04000000  /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5			0x05000000  /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6			0x06000000  /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7			0x07000000  /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8			0x08000000  /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9			0x09000000  /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10		0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11		0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12		0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13		0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14		0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15		0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1			0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2			0x20000000  /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3			0x30000000  /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4			0x40000000  /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5			0x50000000  /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6			0x60000000  /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7			0x70000000  /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8			0x80000000  /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9			0x90000000  /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10		0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11		0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12		0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13		0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14		0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15		0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE			0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2			0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3			0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE				0x00000010 /* Enable SDRAM prefetch */
-#define PFP				0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL		0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh				*/
-#define PASR_B0_B1		0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh		*/
-#define PASR_B0			0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh			*/
-#define TRAS_1			0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2			0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3			0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4			0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5			0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6			0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7			0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8			0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9			0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10			0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11			0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12			0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13			0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14			0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15			0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1			0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2			0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3			0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4			0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5			0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6			0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7			0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1			0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2			0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3			0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4			0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5			0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6			0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7			0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1			0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2			0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3			0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD			0x00200000 /*Power-up start delay */
-#define PSM				0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS				0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS			0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE			0x02000000 /* Enable external buffering timing */
-#define FBBRW			0x04000000 /* Fast back-to-back read write enable */
-#define EMREN			0x10000000 /* Extended mode register enable */
-#define TCSR			0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG			0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE				0x0001 /* Enable SDRAM external bank */
-#define EBSZ_16		0x0000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32		0x0002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64		0x0004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128		0x0006 /* SDRAM external bank size = 128MB */
-#define EBSZ    		0x0006 /* SDRAM external bank size */
-#define EBCAW_8		0x0000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9		0x0010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10		0x0020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11		0x0030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI			0x00000001 /* SDRAM controller is idle  */
-#define SDSRA			0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA			0x00000004 /* SDRAM power up active  */
-#define SDRS			0x00000008 /* SDRAM is in reset state */
-#define SDEASE			0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT			0x00000020 /* Bus granted */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  )				*/
-#ifdef _MISRA_RULES
-#define	CLKLOW(x)	((x) & 0xFFu)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFFu)<<0x8)	/* Periods Before New Clock Low			*/
-#else
-#define	CLKLOW(x)	((x) & 0xFF)		/* Periods Clock Is Held Low			*/
-#define CLKHI(y)	(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low			*/
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks															*/
-#define	PRESCALE	0x007F		/* SCLKs Per Internal Time Reference (10MHz)	*/
-#define	TWI_ENA		0x0080		/* TWI Enable									*/
-#define	SCCB		0x0200		/* SCCB Compatibility Enable					*/
-
-/* TWIx_SLAVE_CTRL Masks															*/
-#define	SEN			0x0001		/* Slave Enable									*/
-#define	SADD_LEN	0x0002		/* Slave Address Length							*/
-#define	STDVAL		0x0004		/* Slave Transmit Data Valid					*/
-#define	NAK			0x0008		/* NAK/ACK* Generated At Conclusion Of Transfer */
-#define	GEN			0x0010		/* General Call Adrress Matching Enabled		*/
-
-/* TWIx_SLAVE_STAT Masks															*/
-#define	SDIR		0x0001		/* Slave Transfer Direction (Transmit/Receive*)	*/
-#define GCALL		0x0002		/* General Call Indicator						*/
-
-/* TWIx_MASTER_CTRL Masks													*/
-#define	MEN			0x0001		/* Master Mode Enable						*/
-#define	MADD_LEN	0x0002		/* Master Address Length					*/
-#define	MDIR		0x0004		/* Master Transmit Direction (RX/TX*)		*/
-#define	FAST		0x0008		/* Use Fast Mode Timing Specs				*/
-#define	STOP		0x0010		/* Issue Stop Condition						*/
-#define	RSTART		0x0020		/* Repeat Start or Stop* At End Of Transfer	*/
-#define	DCNT		0x3FC0		/* Data Bytes To Transfer					*/
-#define	SDAOVR		0x4000		/* Serial Data Override						*/
-#define	SCLOVR		0x8000		/* Serial Clock Override					*/
-
-/* TWIx_MASTER_STAT Masks														*/
-#define	MPROG		0x0001		/* Master Transfer In Progress					*/
-#define	LOSTARB		0x0002		/* Lost Arbitration Indicator (Xfer Aborted)	*/
-#define	ANAK		0x0004		/* Address Not Acknowledged						*/
-#define	DNAK		0x0008		/* Data Not Acknowledged						*/
-#define	BUFRDERR	0x0010		/* Buffer Read Error							*/
-#define	BUFWRERR	0x0020		/* Buffer Write Error							*/
-#define	SDASEN		0x0040		/* Serial Data Sense							*/
-#define	SCLSEN		0x0080		/* Serial Clock Sense							*/
-#define	BUSBUSY		0x0100		/* Bus Busy Indicator							*/
-
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks						*/
-#define	SINIT		0x0001		/* Slave Transfer Initiated	*/
-#define	SCOMP		0x0002		/* Slave Transfer Complete	*/
-#define	SERR		0x0004		/* Slave Transfer Error		*/
-#define	SOVF		0x0008		/* Slave Overflow			*/
-#define	MCOMP		0x0010		/* Master Transfer Complete	*/
-#define	MERR		0x0020		/* Master Transfer Error	*/
-#define	XMTSERV		0x0040		/* Transmit FIFO Service	*/
-#define	RCVSERV		0x0080		/* Receive FIFO Service		*/
-
-/* TWIx_FIFO_CTRL Masks												*/
-#define	XMTFLUSH	0x0001		/* Transmit Buffer Flush			*/
-#define	RCVFLUSH	0x0002		/* Receive Buffer Flush				*/
-#define	XMTINTLEN	0x0004		/* Transmit Buffer Interrupt Length	*/
-#define	RCVINTLEN	0x0008		/* Receive Buffer Interrupt Length	*/
-
-/* TWIx_FIFO_STAT Masks															*/
-#define	XMTSTAT		0x0003		/* Transmit FIFO Status							*/
-#define	XMT_EMPTY	0x0000		/* 		Transmit FIFO Empty						*/
-#define	XMT_HALF	0x0001		/* 		Transmit FIFO Has 1 Byte To Write		*/
-#define	XMT_FULL	0x0003		/* 		Transmit FIFO Full (2 Bytes To Write)	*/
-
-#define	RCVSTAT		0x000C		/* Receive FIFO Status							*/
-#define	RCV_EMPTY	0x0000		/* 		Receive FIFO Empty						*/
-#define	RCV_HALF	0x0004		/* 		Receive FIFO Has 1 Byte To Read			*/
-#define	RCV_FULL	0x000C		/* 		Receive FIFO Full (2 Bytes To Read)		*/
-
-
-/********************************* MXVR MASKS ****************************************/
-
-/* MXVR_CONFIG Masks */
-
-#define MXVREN    0x00000001lu
-#define MMSM      0x00000002lu
-#define ACTIVE    0x00000004lu
-#define SDELAY    0x00000008lu
-#define NCMRXEN   0x00000010lu
-#define RWRRXEN   0x00000020lu
-#define MTXEN     0x00000040lu
-#define MTXON     0x00000080lu /*legacy*/
-#define MTXONB    0x00000080lu
-#define EPARITY   0x00000100lu
-#define MSB       0x00001E00lu
-#define APRXEN    0x00002000lu
-#define WAKEUP    0x00004000lu
-#define LMECH     0x00008000lu
-
-#ifdef _MISRA_RULES
-#define SET_MSB(x)     (((x)&0xFu) << 0x9)
-#else
-#define SET_MSB(x)     (((x)&0xF) << 0x9)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_0 Masks */
-
-#define MXTALCEN  0x00000001lu
-#define MXTALFEN  0x00000002lu
-#define MPLLMS    0x00000008lu
-#define MXTALMUL  0x00000030lu
-#define MPLLEN    0x00000040lu
-#define MPLLEN0   0x00000040lu /* legacy */
-#define MPLLEN1   0x00000080lu /* legacy */
-#define MMCLKEN   0x00000100lu
-#define MMCLKMUL  0x00001E00lu
-#define MPLLRSTB  0x00002000lu
-#define MPLLRSTB0 0x00002000lu /* legacy */
-#define MPLLRSTB1 0x00004000lu /* legacy */
-#define MBCLKEN   0x00010000lu
-#define MBCLKDIV  0x001E0000lu
-#define MPLLCDR   0x00200000lu
-#define MPLLCDR0  0x00200000lu /* legacy */
-#define MPLLCDR1  0x00400000lu /* legacy */
-#define INVRX     0x00800000lu
-#define MFSEN     0x01000000lu
-#define MFSDIV    0x1E000000lu
-#define MFSSEL    0x60000000lu
-#define MFSSYNC   0x80000000lu
-
-#define MXTALMUL_256FS   0x00000000lu /* legacy */
-#define MXTALMUL_384FS   0x00000010lu /* legacy */
-#define MXTALMUL_512FS   0x00000020lu /* legacy */
-#define MXTALMUL_1024FS  0x00000030lu
-
-#define MMCLKMUL_1024FS  0x00000000lu
-#define MMCLKMUL_512FS   0x00000200lu
-#define MMCLKMUL_256FS   0x00000400lu
-#define MMCLKMUL_128FS   0x00000600lu
-#define MMCLKMUL_64FS    0x00000800lu
-#define MMCLKMUL_32FS    0x00000A00lu
-#define MMCLKMUL_16FS    0x00000C00lu
-#define MMCLKMUL_8FS     0x00000E00lu
-#define MMCLKMUL_4FS     0x00001000lu
-#define MMCLKMUL_2FS     0x00001200lu
-#define MMCLKMUL_1FS     0x00001400lu
-#define MMCLKMUL_1536FS  0x00001A00lu
-#define MMCLKMUL_768FS   0x00001C00lu
-#define MMCLKMUL_384FS   0x00001E00lu
-
-#define MBCLKDIV_DIV2    0x00020000lu
-#define MBCLKDIV_DIV4    0x00040000lu
-#define MBCLKDIV_DIV8    0x00060000lu
-#define MBCLKDIV_DIV16   0x00080000lu
-#define MBCLKDIV_DIV32   0x000A0000lu
-#define MBCLKDIV_DIV64   0x000C0000lu
-#define MBCLKDIV_DIV128  0x000E0000lu
-#define MBCLKDIV_DIV256  0x00100000lu
-#define MBCLKDIV_DIV512  0x00120000lu
-#define MBCLKDIV_DIV1024 0x00140000lu
-
-#define MFSDIV_DIV2      0x02000000lu
-#define MFSDIV_DIV4      0x04000000lu
-#define MFSDIV_DIV8      0x06000000lu
-#define MFSDIV_DIV16     0x08000000lu
-#define MFSDIV_DIV32     0x0A000000lu
-#define MFSDIV_DIV64     0x0C000000lu
-#define MFSDIV_DIV128    0x0E000000lu
-#define MFSDIV_DIV256    0x10000000lu
-#define MFSDIV_DIV512    0x12000000lu
-#define MFSDIV_DIV1024   0x14000000lu
-
-#define MFSSEL_CLOCK     0x00000000lu
-#define MFSSEL_PULSE_HI  0x20000000lu
-#define MFSSEL_PULSE_LO  0x40000000lu
-
-
-/* MXVR_PLL_CTL_1 Masks */
-
-#define MSTO       0x00000001lu
-#define MSTO0      0x00000001lu /* legacy */
-#define MHOGGD     0x00000004lu
-#define MHOGGD0    0x00000004lu /* legacy */
-#define MHOGGD1    0x00000008lu /* legacy */
-#define MSHAPEREN  0x00000010lu
-#define MSHAPEREN0 0x00000010lu /* legacy */
-#define MSHAPEREN1 0x00000020lu /* legacy */
-#define MPLLCNTEN  0x00008000lu
-#define MPLLCNT    0xFFFF0000lu
-
-#ifdef _MISRA_RULES
-#define SET_MPLLCNT(x)     (((x)&0xFFFFu) << 0x10)
-#else
-#define SET_MPLLCNT(x)     (((x)&0xFFFF) << 0x10)
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_PLL_CTL_2 Masks */
-
-#define MSHAPERSEL 0x00000007lu
-#define MCPSEL     0x000000E0lu
-
-#ifdef _MISRA_RULES
-#define SET_MSHAPERSEL(x)   (   (x) & 0x0007u )
-#define SET_MCPSEL(x)       ( ( (x) & 0x0007u ) << 0x5 )
-#else
-#define SET_MSHAPERSEL(x)   (   (x) & 0x0007 )
-#define SET_MCPSEL(x)       ( ( (x) & 0x0007 ) << 0x5 )
-#endif /* _MISRA_RULES */
-
-
-/* MXVR_INT_STAT_0 Masks */
-
-#define NI2A  0x00000001lu
-#define NA2I  0x00000002lu
-#define SBU2L 0x00000004lu
-#define SBL2U 0x00000008lu
-#define PRU   0x00000010lu
-#define MPRU  0x00000020lu
-#define DRU   0x00000040lu
-#define MDRU  0x00000080lu
-#define SBU   0x00000100lu
-#define ATU   0x00000200lu
-#define FCZ0  0x00000400lu
-#define FCZ1  0x00000800lu
-#define PERR  0x00001000lu
-#define MH2L  0x00002000lu
-#define ML2H  0x00004000lu
-#define WUP   0x00008000lu
-#define FU2L  0x00010000lu
-#define FL2U  0x00020000lu
-#define BU2L  0x00040000lu
-#define BL2U  0x00080000lu
-#define PCZ   0x00400000lu
-#define FERR  0x00800000lu
-#define CMR   0x01000000lu
-#define CMROF 0x02000000lu
-#define CMTS  0x04000000lu
-#define CMTC  0x08000000lu
-#define RWRC  0x10000000lu
-#define BCZ   0x20000000lu
-#define BMERR 0x40000000lu
-#define DERR  0x80000000lu
-
-
-/* MXVR_INT_EN_0 Masks */
-
-#define NI2AEN  NI2A
-#define NA2IEN  NA2I
-#define SBU2LEN SBU2L
-#define SBL2UEN SBL2U
-#define PRUEN   PRU
-#define MPRUEN  MPRU
-#define DRUEN   DRU
-#define MDRUEN  MDRU
-#define SBUEN   SBU
-#define ATUEN   ATU
-#define FCZ0EN  FCZ0
-#define FCZ1EN  FCZ1
-#define PERREN  PERR
-#define MH2LEN  MH2L
-#define ML2HEN  ML2H
-#define WUPEN   WUP
-#define FU2LEN  FU2L
-#define FL2UEN  FL2U
-#define BU2LEN  BU2L
-#define BL2UEN  BL2U
-#define PCZEN   PCZ
-#define FERREN  FERR
-#define CMREN   CMR
-#define CMROFEN CMROF
-#define CMTSEN  CMTS
-#define CMTCEN  CMTC
-#define RWRCEN  RWRC
-#define BCZEN   BCZ
-#define BMERREN BMERR
-#define DERREN  DERR
-
-
-/* MXVR_INT_STAT_1 Masks */
-
-#define APR   0x00000004lu
-#define APROF 0x00000008lu
-#define APTS  0x00000040lu
-#define APTC  0x00000080lu
-#define APRCE 0x00000400lu
-#define APRPE 0x00000800lu
-
-#define HDONE0 0x00000001lu
-#define DONE0  0x00000002lu
-#define HDONE1 0x00000010lu
-#define DONE1  0x00000020lu
-#define HDONE2 0x00000100lu
-#define DONE2  0x00000200lu
-#define HDONE3 0x00001000lu
-#define DONE3  0x00002000lu
-#define HDONE4 0x00010000lu
-#define DONE4  0x00020000lu
-#define HDONE5 0x00100000lu
-#define DONE5  0x00200000lu
-#define HDONE6 0x01000000lu
-#define DONE6  0x02000000lu
-#define HDONE7 0x10000000lu
-#define DONE7  0x20000000lu
-
-#define DONEX(x) (0x00000002 << (4 * (x)))
-#define HDONEX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_INT_EN_1 Masks */
-
-#define APREN   APR
-#define APROFEN APROF
-#define APTSEN  APTS
-#define APTCEN  APTC
-#define APRCEEN APRCE
-#define APRPEEN APRPE
-
-#define HDONEEN0 HDONE0
-#define DONEEN0  DONE0
-#define HDONEEN1 HDONE1
-#define DONEEN1  DONE1
-#define HDONEEN2 HDONE2
-#define DONEEN2  DONE2
-#define HDONEEN3 HDONE3
-#define DONEEN3  DONE3
-#define HDONEEN4 HDONE4
-#define DONEEN4  DONE4
-#define HDONEEN5 HDONE5
-#define DONEEN5  DONE5
-#define HDONEEN6 HDONE6
-#define DONEEN6  DONE6
-#define HDONEEN7 HDONE7
-#define DONEEN7  DONE7
-
-#define DONEENX(x) (0x00000002 << (4 * (x)))
-#define HDONEENX(x) (0x00000001 << (4 * (x)))
-
-
-/* MXVR_STATE_0 Masks */
-
-#define NACT     0x00000001lu
-#define SBLOCK   0x00000002lu
-#define PFDLOCK  0x00000004lu
-#define PFDLOCK0 0x00000004lu /* legacy */
-#define PDD      0x00000008lu
-#define PDD0     0x00000008lu /* legacy */
-#define PVCO     0x00000010lu
-#define PVCO0    0x00000010lu /* legacy */
-#define PFDLOCK1 0x00000020lu /* legacy */
-#define PDD1     0x00000040lu /* legacy */
-#define PVCO1    0x00000080lu /* legacy */
-#define APBSY    0x00000100lu
-#define APARB    0x00000200lu
-#define APTX     0x00000400lu
-#define APRX     0x00000800lu
-#define CMBSY    0x00001000lu
-#define CMARB    0x00002000lu
-#define CMTX     0x00004000lu
-#define CMRX     0x00008000lu
-#define MRXONB   0x00010000lu
-#define RGSIP    0x00020000lu
-#define DALIP    0x00040000lu
-#define ALIP     0x00080000lu
-#define RRDIP    0x00100000lu
-#define RWRIP    0x00200000lu
-#define FLOCK    0x00400000lu
-#define BLOCK    0x00800000lu
-#define RSB      0x0F000000lu
-#define DERRNUM  0xF0000000lu
-
-
-/* MXVR_STATE_1 Masks */
-
-#define STXNUMB     0x0000000Flu
-#define SRXNUMB     0x000000F0lu
-#define APCONT      0x00000100lu
-#define DMAACTIVEX  0x00FF0000lu
-#define DMAACTIVE0  0x00010000lu
-#define DMAACTIVE1  0x00020000lu
-#define DMAACTIVE2  0x00040000lu
-#define DMAACTIVE3  0x00080000lu
-#define DMAACTIVE4  0x00100000lu
-#define DMAACTIVE5  0x00200000lu
-#define DMAACTIVE6  0x00400000lu
-#define DMAACTIVE7  0x00800000lu
-#define DMAPMENX    0xFF000000lu
-#define DMAPMEN0    0x01000000lu
-#define DMAPMEN1    0x02000000lu
-#define DMAPMEN2    0x04000000lu
-#define DMAPMEN3    0x08000000lu
-#define DMAPMEN4    0x10000000lu
-#define DMAPMEN5    0x20000000lu
-#define DMAPMEN6    0x40000000lu
-#define DMAPMEN7    0x80000000lu
-
-
-/* MXVR_POSITION Masks */
-
-#define PVALID       0x8000
-#define POSITION     0x003F
-
-
-/* MXVR_MAX_POSITION Masks */
-
-#define MPVALID      0x8000
-#define MPOSITION    0x003F
-
-
-/* MXVR_DELAY Masks */
-
-#define DVALID       0x8000
-#define DELAY        0x003F
-
-
-/* MXVR_MAX_DELAY Masks */
-
-#define MDVALID      0x8000
-#define MDELAY       0x003F
-
-
-/* MXVR_LADDR Masks */
-
-#define LVALID       0x80000000lu
-#define LADDR        0x0000FFFFlu
-
-
-/* MXVR_GADDR Masks */
-
-#define GVALID       0x8000
-#define GADDRL       0x00FF
-
-
-/* MXVR_AADDR Masks */
-
-#define AVALID       0x80000000lu
-#define AADDR        0x0000FFFFlu
-
-
-/* MXVR_ALLOC_0 Masks */
-
-#define CIU0         0x00000080lu
-#define CIU1         0x00008000lu
-#define CIU2         0x00800000lu
-#define CIU3         0x80000000lu
-
-#define CL0          0x0000007Flu
-#define CL1          0x00007F00lu
-#define CL2          0x007F0000lu
-#define CL3          0x7F000000lu
-
-
-/* MXVR_ALLOC_1 Masks */
-
-#define CIU4         0x00000080lu
-#define CIU5         0x00008000lu
-#define CIU6         0x00800000lu
-#define CIU7         0x80000000lu
-
-#define CL4          0x0000007Flu
-#define CL5          0x00007F00lu
-#define CL6          0x007F0000lu
-#define CL7          0x7F000000lu
-
-
-/* MXVR_ALLOC_2 Masks */
-
-#define CIU8         0x00000080lu
-#define CIU9         0x00008000lu
-#define CIU10        0x00800000lu
-#define CIU11        0x80000000lu
-
-#define CL8          0x0000007Flu
-#define CL9          0x00007F00lu
-#define CL10         0x007F0000lu
-#define CL11         0x7F000000lu
-
-
-/* MXVR_ALLOC_3 Masks */
-
-#define CIU12        0x00000080lu
-#define CIU13        0x00008000lu
-#define CIU14        0x00800000lu
-#define CIU15        0x80000000lu
-
-#define CL12         0x0000007Flu
-#define CL13         0x00007F00lu
-#define CL14         0x007F0000lu
-#define CL15         0x7F000000lu
-
-
-/* MXVR_ALLOC_4 Masks */
-
-#define CIU16        0x00000080lu
-#define CIU17        0x00008000lu
-#define CIU18        0x00800000lu
-#define CIU19        0x80000000lu
-
-#define CL16         0x0000007Flu
-#define CL17         0x00007F00lu
-#define CL18         0x007F0000lu
-#define CL19         0x7F000000lu
-
-
-/* MXVR_ALLOC_5 Masks */
-
-#define CIU20        0x00000080lu
-#define CIU21        0x00008000lu
-#define CIU22        0x00800000lu
-#define CIU23        0x80000000lu
-
-#define CL20         0x0000007Flu
-#define CL21         0x00007F00lu
-#define CL22         0x007F0000lu
-#define CL23         0x7F000000lu
-
-
-/* MXVR_ALLOC_6 Masks */
-
-#define CIU24        0x00000080lu
-#define CIU25        0x00008000lu
-#define CIU26        0x00800000lu
-#define CIU27        0x80000000lu
-
-#define CL24         0x0000007Flu
-#define CL25         0x00007F00lu
-#define CL26         0x007F0000lu
-#define CL27         0x7F000000lu
-
-
-/* MXVR_ALLOC_7 Masks */
-
-#define CIU28        0x00000080lu
-#define CIU29        0x00008000lu
-#define CIU30        0x00800000lu
-#define CIU31        0x80000000lu
-
-#define CL28         0x0000007Flu
-#define CL29         0x00007F00lu
-#define CL30         0x007F0000lu
-#define CL31         0x7F000000lu
-
-
-/* MXVR_ALLOC_8 Masks */
-
-#define CIU32        0x00000080lu
-#define CIU33        0x00008000lu
-#define CIU34        0x00800000lu
-#define CIU35        0x80000000lu
-
-#define CL32         0x0000007Flu
-#define CL33         0x00007F00lu
-#define CL34         0x007F0000lu
-#define CL35         0x7F000000lu
-
-
-/* MXVR_ALLOC_9 Masks */
-
-#define CIU36        0x00000080lu
-#define CIU37        0x00008000lu
-#define CIU38        0x00800000lu
-#define CIU39        0x80000000lu
-
-#define CL36         0x0000007Flu
-#define CL37         0x00007F00lu
-#define CL38         0x007F0000lu
-#define CL39         0x7F000000lu
-
-
-/* MXVR_ALLOC_10 Masks */
-
-#define CIU40        0x00000080lu
-#define CIU41        0x00008000lu
-#define CIU42        0x00800000lu
-#define CIU43        0x80000000lu
-
-#define CL40         0x0000007Flu
-#define CL41         0x00007F00lu
-#define CL42         0x007F0000lu
-#define CL43         0x7F000000lu
-
-
-/* MXVR_ALLOC_11 Masks */
-
-#define CIU44        0x00000080lu
-#define CIU45        0x00008000lu
-#define CIU46        0x00800000lu
-#define CIU47        0x80000000lu
-
-#define CL44         0x0000007Flu
-#define CL45         0x00007F00lu
-#define CL46         0x007F0000lu
-#define CL47         0x7F000000lu
-
-
-/* MXVR_ALLOC_12 Masks */
-
-#define CIU48        0x00000080lu
-#define CIU49        0x00008000lu
-#define CIU50        0x00800000lu
-#define CIU51        0x80000000lu
-
-#define CL48         0x0000007Flu
-#define CL49         0x00007F00lu
-#define CL50         0x007F0000lu
-#define CL51         0x7F000000lu
-
-
-/* MXVR_ALLOC_13 Masks */
-
-#define CIU52        0x00000080lu
-#define CIU53        0x00008000lu
-#define CIU54        0x00800000lu
-#define CIU55        0x80000000lu
-
-#define CL52         0x0000007Flu
-#define CL53         0x00007F00lu
-#define CL54         0x007F0000lu
-#define CL55         0x7F000000lu
-
-
-/* MXVR_ALLOC_14 Masks */
-
-#define CIU56        0x00000080lu
-#define CIU57        0x00008000lu
-#define CIU58        0x00800000lu
-#define CIU59        0x80000000lu
-
-#define CL56         0x0000007Flu
-#define CL57         0x00007F00lu
-#define CL58         0x007F0000lu
-#define CL59         0x7F000000lu
-
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-
-/* MXVR_DMAx_CONFIG Masks */
-
-#define MDMAEN      0x00000001lu
-#define DD          0x00000002lu
-#define LCHAN       0x000003C0lu
-#define BITSWAPEN   0x00000400lu
-#define BYSWAPEN    0x00000800lu
-#define MFLOW       0x00007000lu
-#define FIXEDPM     0x00080000lu
-#define STARTPAT    0x00300000lu
-#define STOPPAT     0x00C00000lu
-#define COUNTPOS    0x1C000000lu
-
-#define DD_TX       0x00000000lu
-#define DD_RX       0x00000002lu
-
-#define LCHAN_0     0x00000000lu
-#define LCHAN_1     0x00000040lu
-#define LCHAN_2     0x00000080lu
-#define LCHAN_3     0x000000C0lu
-#define LCHAN_4     0x00000100lu
-#define LCHAN_5     0x00000140lu
-#define LCHAN_6     0x00000180lu
-#define LCHAN_7     0x000001C0lu
-
-#define MFLOW_STOP  0x00000000lu
-#define MFLOW_AUTO  0x00001000lu
-#define MFLOW_PVC   0x00002000lu
-#define MFLOW_PSS   0x00003000lu
-#define MFLOW_PFC   0x00004000lu
-
-#define STARTPAT_0  0x00000000lu
-#define STARTPAT_1  0x00100000lu
-
-#define STOPPAT_0   0x00000000lu
-#define STOPPAT_1   0x00400000lu
-
-#define COUNTPOS_0  0x00000000lu
-#define COUNTPOS_1  0x04000000lu
-#define COUNTPOS_2  0x08000000lu
-#define COUNTPOS_3  0x0C000000lu
-#define COUNTPOS_4  0x10000000lu
-#define COUNTPOS_5  0x14000000lu
-#define COUNTPOS_6  0x18000000lu
-#define COUNTPOS_7  0x1C000000lu
-
-
-/* MXVR_AP_CTL Masks */
-
-#define STARTAP    0x00000001lu
-#define CANCELAP   0x00000002lu
-#define RESETAP    0x00000004lu
-#define APRBE0     0x00004000lu
-#define APRBE1     0x00008000lu
-#define APRBEX     0x0000C000lu
-
-
-/* MXVR_CM_CTL Masks */
-
-#define STARTCM    0x00000001lu
-#define CANCELCM   0x00000002lu
-#define CMRBEX     0xFFFF0000lu
-#define CMRBE0     0x00010000lu
-#define CMRBE1     0x00020000lu
-#define CMRBE2     0x00040000lu
-#define CMRBE3     0x00080000lu
-#define CMRBE4     0x00100000lu
-#define CMRBE5     0x00200000lu
-#define CMRBE6     0x00400000lu
-#define CMRBE7     0x00800000lu
-#define CMRBE8     0x01000000lu
-#define CMRBE9     0x02000000lu
-#define CMRBE10    0x04000000lu
-#define CMRBE11    0x08000000lu
-#define CMRBE12    0x10000000lu
-#define CMRBE13    0x20000000lu
-#define CMRBE14    0x40000000lu
-#define CMRBE15    0x80000000lu
-
-
-/* MXVR_PAT_DATA_x Masks */
-
-#define MATCH_DATA_0 0x000000FFlu
-#define MATCH_DATA_1 0x0000FF00lu
-#define MATCH_DATA_2 0x00FF0000lu
-#define MATCH_DATA_3 0xFF000000lu
-
-
-
-/* MXVR_PAT_EN_x Masks */
-
-#define MATCH_EN_0_0 0x00000001lu
-#define MATCH_EN_0_1 0x00000002lu
-#define MATCH_EN_0_2 0x00000004lu
-#define MATCH_EN_0_3 0x00000008lu
-#define MATCH_EN_0_4 0x00000010lu
-#define MATCH_EN_0_5 0x00000020lu
-#define MATCH_EN_0_6 0x00000040lu
-#define MATCH_EN_0_7 0x00000080lu
-
-#define MATCH_EN_1_0 0x00000100lu
-#define MATCH_EN_1_1 0x00000200lu
-#define MATCH_EN_1_2 0x00000400lu
-#define MATCH_EN_1_3 0x00000800lu
-#define MATCH_EN_1_4 0x00001000lu
-#define MATCH_EN_1_5 0x00002000lu
-#define MATCH_EN_1_6 0x00004000lu
-#define MATCH_EN_1_7 0x00008000lu
-
-#define MATCH_EN_2_0 0x00010000lu
-#define MATCH_EN_2_1 0x00020000lu
-#define MATCH_EN_2_2 0x00040000lu
-#define MATCH_EN_2_3 0x00080000lu
-#define MATCH_EN_2_4 0x00100000lu
-#define MATCH_EN_2_5 0x00200000lu
-#define MATCH_EN_2_6 0x00400000lu
-#define MATCH_EN_2_7 0x00800000lu
-
-#define MATCH_EN_3_0 0x01000000lu
-#define MATCH_EN_3_1 0x02000000lu
-#define MATCH_EN_3_2 0x04000000lu
-#define MATCH_EN_3_3 0x08000000lu
-#define MATCH_EN_3_4 0x10000000lu
-#define MATCH_EN_3_5 0x20000000lu
-#define MATCH_EN_3_6 0x40000000lu
-#define MATCH_EN_3_7 0x80000000lu
-
-
-/* MXVR_ROUTING_0 Masks */
-
-#define MUTE_CH0        0x00000080lu
-#define MUTE_CH1        0x00008000lu
-#define MUTE_CH2        0x00800000lu
-#define MUTE_CH3        0x80000000lu
-
-#define TX_CH0          0x0000007Flu
-#define TX_CH1          0x00007F00lu
-#define TX_CH2          0x007F0000lu
-#define TX_CH3          0x7F000000lu
-
-
-/* MXVR_ROUTING_1 Masks */
-
-#define MUTE_CH4        0x00000080lu
-#define MUTE_CH5        0x00008000lu
-#define MUTE_CH6        0x00800000lu
-#define MUTE_CH7        0x80000000lu
-
-#define TX_CH4          0x0000007Flu
-#define TX_CH5          0x00007F00lu
-#define TX_CH6          0x007F0000lu
-#define TX_CH7          0x7F000000lu
-
-
-/* MXVR_ROUTING_2 Masks */
-
-#define MUTE_CH8        0x00000080lu
-#define MUTE_CH9        0x00008000lu
-#define MUTE_CH10       0x00800000lu
-#define MUTE_CH11       0x80000000lu
-
-#define TX_CH8          0x0000007Flu
-#define TX_CH9          0x00007F00lu
-#define TX_CH10         0x007F0000lu
-#define TX_CH11         0x7F000000lu
-
-/* MXVR_ROUTING_3 Masks */
-
-#define MUTE_CH12       0x00000080lu
-#define MUTE_CH13       0x00008000lu
-#define MUTE_CH14       0x00800000lu
-#define MUTE_CH15       0x80000000lu
-
-#define TX_CH12         0x0000007Flu
-#define TX_CH13         0x00007F00lu
-#define TX_CH14         0x007F0000lu
-#define TX_CH15         0x7F000000lu
-
-
-/* MXVR_ROUTING_4 Masks */
-
-#define MUTE_CH16       0x00000080lu
-#define MUTE_CH17       0x00008000lu
-#define MUTE_CH18       0x00800000lu
-#define MUTE_CH19       0x80000000lu
-
-#define TX_CH16         0x0000007Flu
-#define TX_CH17         0x00007F00lu
-#define TX_CH18         0x007F0000lu
-#define TX_CH19         0x7F000000lu
-
-
-/* MXVR_ROUTING_5 Masks */
-
-#define MUTE_CH20       0x00000080lu
-#define MUTE_CH21       0x00008000lu
-#define MUTE_CH22       0x00800000lu
-#define MUTE_CH23       0x80000000lu
-
-#define TX_CH20         0x0000007Flu
-#define TX_CH21         0x00007F00lu
-#define TX_CH22         0x007F0000lu
-#define TX_CH23         0x7F000000lu
-
-
-/* MXVR_ROUTING_6 Masks */
-
-#define MUTE_CH24       0x00000080lu
-#define MUTE_CH25       0x00008000lu
-#define MUTE_CH26       0x00800000lu
-#define MUTE_CH27       0x80000000lu
-
-#define TX_CH24         0x0000007Flu
-#define TX_CH25         0x00007F00lu
-#define TX_CH26         0x007F0000lu
-#define TX_CH27         0x7F000000lu
-
-
-/* MXVR_ROUTING_7 Masks */
-
-#define MUTE_CH28       0x00000080lu
-#define MUTE_CH29       0x00008000lu
-#define MUTE_CH30       0x00800000lu
-#define MUTE_CH31       0x80000000lu
-
-#define TX_CH28         0x0000007Flu
-#define TX_CH29         0x00007F00lu
-#define TX_CH30         0x007F0000lu
-#define TX_CH31         0x7F000000lu
-
-
-/* MXVR_ROUTING_8 Masks */
-
-#define MUTE_CH32       0x00000080lu
-#define MUTE_CH33       0x00008000lu
-#define MUTE_CH34       0x00800000lu
-#define MUTE_CH35       0x80000000lu
-
-#define TX_CH32         0x0000007Flu
-#define TX_CH33         0x00007F00lu
-#define TX_CH34         0x007F0000lu
-#define TX_CH35         0x7F000000lu
-
-
-/* MXVR_ROUTING_9 Masks */
-
-#define MUTE_CH36       0x00000080lu
-#define MUTE_CH37       0x00008000lu
-#define MUTE_CH38       0x00800000lu
-#define MUTE_CH39       0x80000000lu
-
-#define TX_CH36         0x0000007Flu
-#define TX_CH37         0x00007F00lu
-#define TX_CH38         0x007F0000lu
-#define TX_CH39         0x7F000000lu
-
-
-/* MXVR_ROUTING_10 Masks */
-
-#define MUTE_CH40       0x00000080lu
-#define MUTE_CH41       0x00008000lu
-#define MUTE_CH42       0x00800000lu
-#define MUTE_CH43       0x80000000lu
-
-#define TX_CH40         0x0000007Flu
-#define TX_CH41         0x00007F00lu
-#define TX_CH42         0x007F0000lu
-#define TX_CH43         0x7F000000lu
-
-
-/* MXVR_ROUTING_11 Masks */
-
-#define MUTE_CH44       0x00000080lu
-#define MUTE_CH45       0x00008000lu
-#define MUTE_CH46       0x00800000lu
-#define MUTE_CH47       0x80000000lu
-
-#define TX_CH44         0x0000007Flu
-#define TX_CH45         0x00007F00lu
-#define TX_CH46         0x007F0000lu
-#define TX_CH47         0x7F000000lu
-
-
-/* MXVR_ROUTING_12 Masks */
-
-#define MUTE_CH48       0x00000080lu
-#define MUTE_CH49       0x00008000lu
-#define MUTE_CH50       0x00800000lu
-#define MUTE_CH51       0x80000000lu
-
-#define TX_CH48         0x0000007Flu
-#define TX_CH49         0x00007F00lu
-#define TX_CH50         0x007F0000lu
-#define TX_CH51         0x7F000000lu
-
-
-/* MXVR_ROUTING_13 Masks */
-
-#define MUTE_CH52       0x00000080lu
-#define MUTE_CH53       0x00008000lu
-#define MUTE_CH54       0x00800000lu
-#define MUTE_CH55       0x80000000lu
-
-#define TX_CH52         0x0000007Flu
-#define TX_CH53         0x00007F00lu
-#define TX_CH54         0x007F0000lu
-#define TX_CH55         0x7F000000lu
-
-
-/* MXVR_ROUTING_14 Masks */
-
-#define MUTE_CH56       0x00000080lu
-#define MUTE_CH57       0x00008000lu
-#define MUTE_CH58       0x00800000lu
-#define MUTE_CH59       0x80000000lu
-
-#define TX_CH56         0x0000007Flu
-#define TX_CH57         0x00007F00lu
-#define TX_CH58         0x007F0000lu
-#define TX_CH59         0x7F000000lu
-
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-/* CAN_CONTROL Masks												*/
-#define	SRS			0x0001	/* Software Reset						*/
-#define	DNM			0x0002	/* Device Net Mode						*/
-#define	ABO			0x0004	/* Auto-Bus On Enable					*/
-#define	WBA			0x0010	/* Wake-Up On CAN Bus Activity Enable	*/
-#define	SMR			0x0020	/* Sleep Mode Request					*/
-#define	CSR			0x0040	/* CAN Suspend Mode Request				*/
-#define	CCR			0x0080	/* CAN Configuration Mode Request		*/
-
-/* CAN_STATUS Masks												*/
-#define	WT			0x0001	/* TX Warning Flag					*/
-#define	WR			0x0002	/* RX Warning Flag					*/
-#define	EP			0x0004	/* Error Passive Mode				*/
-#define	EBO			0x0008	/* Error Bus Off Mode				*/
-#define	CSA			0x0040	/* Suspend Mode Acknowledge			*/
-#define	CCA			0x0080	/* Configuration Mode Acknowledge	*/
-#define	MBPTR		0x1F00	/* Mailbox Pointer					*/
-#define	TRM			0x4000	/* Transmit Mode					*/
-#define	REC			0x8000	/* Receive Mode						*/
-
-/* CAN_CLOCK Masks									*/
-#define	BRP			0x03FF	/* Bit-Rate Pre-Scaler	*/
-
-/* CAN_TIMING Masks											*/
-#define	TSEG1		0x000F	/* Time Segment 1				*/
-#define	TSEG2		0x0070	/* Time Segment 2				*/
-#define	SAM			0x0080	/* Sampling						*/
-#define	SJW			0x0300	/* Synchronization Jump Width	*/
-
-/* CAN_DEBUG Masks											*/
-#define	DEC			0x0001	/* Disable CAN Error Counters	*/
-#define	DRI			0x0002	/* Disable CAN RX Input			*/
-#define	DTO			0x0004	/* Disable CAN TX Output		*/
-#define	DIL			0x0008	/* Disable CAN Internal Loop	*/
-#define	MAA			0x0010	/* Mode Auto-Acknowledge Enable	*/
-#define	MRB			0x0020	/* Mode Read Back Enable		*/
-#define	CDE			0x8000	/* CAN Debug Enable				*/
-
-/* CAN_CEC Masks										*/
-#define	RXECNT		0x00FF	/* Receive Error Counter	*/
-#define	TXECNT		0xFF00	/* Transmit Error Counter	*/
-
-/* CAN_INTR Masks											*/
-#define	MBRIRQ	0x0001	/* Mailbox Receive Interrupt	*/
-#define	MBRIF		MBRIRQ	/* legacy */
-#define	MBTIRQ	0x0002	/* Mailbox Transmit Interrupt	*/
-#define	MBTIF		MBTIRQ	/* legacy */
-#define	GIRQ		0x0004	/* Global Interrupt				*/
-#define	SMACK		0x0008	/* Sleep Mode Acknowledge		*/
-#define	CANTX		0x0040	/* CAN TX Bus Value				*/
-#define	CANRX		0x0080	/* CAN RX Bus Value				*/
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks										*/
-#define DFC			0xFFFF	/* Data Filtering Code (If Enabled) (ID0)		*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (ID0)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (ID1)	*/
-#define	BASEID		0x1FFC	/* Base Identifier								*/
-#define	IDE			0x2000	/* Identifier Extension							*/
-#define	RTR			0x4000	/* Remote Frame Transmission Request			*/
-#define	AME			0x8000	/* Acceptance Mask Enable						*/
-
-/* CAN_MBxx_TIMESTAMP Masks					*/
-#define TSV			0xFFFF	/* Timestamp	*/
-
-/* CAN_MBxx_LENGTH Masks						*/
-#define DLC			0x000F	/* Data Length Code	*/
-
-/* CAN_AMxxH and CAN_AMxxL Masks												*/
-#define DFM			0xFFFF	/* Data Field Mask (If Enabled) (CAN_AMxxL)			*/
-#define	EXTID_LO	0xFFFF	/* Lower 16 Bits of Extended Identifier (CAN_AMxxL)	*/
-#define	EXTID_HI	0x0003	/* Upper 2 Bits of Extended Identifier (CAN_AMxxH)	*/
-#define	BASEID		0x1FFC	/* Base Identifier									*/
-#define	AMIDE		0x2000	/* Acceptance Mask ID Extension Enable				*/
-#define	FMD			0x4000	/* Full Mask Data Field Enable						*/
-#define	FDF			0x8000	/* Filter On Data Field Enable						*/
-
-/* CAN_MC1 Masks									*/
-#define	MC0			0x0001	/* Enable Mailbox 0		*/
-#define	MC1			0x0002	/* Enable Mailbox 1		*/
-#define	MC2			0x0004	/* Enable Mailbox 2		*/
-#define	MC3			0x0008	/* Enable Mailbox 3		*/
-#define	MC4			0x0010	/* Enable Mailbox 4		*/
-#define	MC5			0x0020	/* Enable Mailbox 5		*/
-#define	MC6			0x0040	/* Enable Mailbox 6		*/
-#define	MC7			0x0080	/* Enable Mailbox 7		*/
-#define	MC8			0x0100	/* Enable Mailbox 8		*/
-#define	MC9			0x0200	/* Enable Mailbox 9		*/
-#define	MC10		0x0400	/* Enable Mailbox 10	*/
-#define	MC11		0x0800	/* Enable Mailbox 11	*/
-#define	MC12		0x1000	/* Enable Mailbox 12	*/
-#define	MC13		0x2000	/* Enable Mailbox 13	*/
-#define	MC14		0x4000	/* Enable Mailbox 14	*/
-#define	MC15		0x8000	/* Enable Mailbox 15	*/
-
-/* CAN_MC2 Masks									*/
-#define	MC16		0x0001	/* Enable Mailbox 16	*/
-#define	MC17		0x0002	/* Enable Mailbox 17	*/
-#define	MC18		0x0004	/* Enable Mailbox 18	*/
-#define	MC19		0x0008	/* Enable Mailbox 19	*/
-#define	MC20		0x0010	/* Enable Mailbox 20	*/
-#define	MC21		0x0020	/* Enable Mailbox 21	*/
-#define	MC22		0x0040	/* Enable Mailbox 22	*/
-#define	MC23		0x0080	/* Enable Mailbox 23	*/
-#define	MC24		0x0100	/* Enable Mailbox 24	*/
-#define	MC25		0x0200	/* Enable Mailbox 25	*/
-#define	MC26		0x0400	/* Enable Mailbox 26	*/
-#define	MC27		0x0800	/* Enable Mailbox 27	*/
-#define	MC28		0x1000	/* Enable Mailbox 28	*/
-#define	MC29		0x2000	/* Enable Mailbox 29	*/
-#define	MC30		0x4000	/* Enable Mailbox 30	*/
-#define	MC31		0x8000	/* Enable Mailbox 31	*/
-
-/* CAN_MD1 Masks												*/
-#define	MD0			0x0001	/* Enable Mailbox 0 For Receive		*/
-#define	MD1			0x0002	/* Enable Mailbox 1 For Receive		*/
-#define	MD2			0x0004	/* Enable Mailbox 2 For Receive		*/
-#define	MD3			0x0008	/* Enable Mailbox 3 For Receive		*/
-#define	MD4			0x0010	/* Enable Mailbox 4 For Receive		*/
-#define	MD5			0x0020	/* Enable Mailbox 5 For Receive		*/
-#define	MD6			0x0040	/* Enable Mailbox 6 For Receive		*/
-#define	MD7			0x0080	/* Enable Mailbox 7 For Receive		*/
-#define	MD8			0x0100	/* Enable Mailbox 8 For Receive		*/
-#define	MD9			0x0200	/* Enable Mailbox 9 For Receive		*/
-#define	MD10		0x0400	/* Enable Mailbox 10 For Receive	*/
-#define	MD11		0x0800	/* Enable Mailbox 11 For Receive	*/
-#define	MD12		0x1000	/* Enable Mailbox 12 For Receive	*/
-#define	MD13		0x2000	/* Enable Mailbox 13 For Receive	*/
-#define	MD14		0x4000	/* Enable Mailbox 14 For Receive	*/
-#define	MD15		0x8000	/* Enable Mailbox 15 For Receive	*/
-
-/* CAN_MD2 Masks												*/
-#define	MD16		0x0001	/* Enable Mailbox 16 For Receive	*/
-#define	MD17		0x0002	/* Enable Mailbox 17 For Receive	*/
-#define	MD18		0x0004	/* Enable Mailbox 18 For Receive	*/
-#define	MD19		0x0008	/* Enable Mailbox 19 For Receive	*/
-#define	MD20		0x0010	/* Enable Mailbox 20 For Receive	*/
-#define	MD21		0x0020	/* Enable Mailbox 21 For Receive	*/
-#define	MD22		0x0040	/* Enable Mailbox 22 For Receive	*/
-#define	MD23		0x0080	/* Enable Mailbox 23 For Receive	*/
-#define	MD24		0x0100	/* Enable Mailbox 24 For Receive	*/
-#define	MD25		0x0200	/* Enable Mailbox 25 For Receive	*/
-#define	MD26		0x0400	/* Enable Mailbox 26 For Receive	*/
-#define	MD27		0x0800	/* Enable Mailbox 27 For Receive	*/
-#define	MD28		0x1000	/* Enable Mailbox 28 For Receive	*/
-#define	MD29		0x2000	/* Enable Mailbox 29 For Receive	*/
-#define	MD30		0x4000	/* Enable Mailbox 30 For Receive	*/
-#define	MD31		0x8000	/* Enable Mailbox 31 For Receive	*/
-
-/* CAN_RMP1 Masks												*/
-#define	RMP0		0x0001	/* RX Message Pending In Mailbox 0	*/
-#define	RMP1		0x0002	/* RX Message Pending In Mailbox 1	*/
-#define	RMP2		0x0004	/* RX Message Pending In Mailbox 2	*/
-#define	RMP3		0x0008	/* RX Message Pending In Mailbox 3	*/
-#define	RMP4		0x0010	/* RX Message Pending In Mailbox 4	*/
-#define	RMP5		0x0020	/* RX Message Pending In Mailbox 5	*/
-#define	RMP6		0x0040	/* RX Message Pending In Mailbox 6	*/
-#define	RMP7		0x0080	/* RX Message Pending In Mailbox 7	*/
-#define	RMP8		0x0100	/* RX Message Pending In Mailbox 8	*/
-#define	RMP9		0x0200	/* RX Message Pending In Mailbox 9	*/
-#define	RMP10		0x0400	/* RX Message Pending In Mailbox 10	*/
-#define	RMP11		0x0800	/* RX Message Pending In Mailbox 11	*/
-#define	RMP12		0x1000	/* RX Message Pending In Mailbox 12	*/
-#define	RMP13		0x2000	/* RX Message Pending In Mailbox 13	*/
-#define	RMP14		0x4000	/* RX Message Pending In Mailbox 14	*/
-#define	RMP15		0x8000	/* RX Message Pending In Mailbox 15	*/
-
-/* CAN_RMP2 Masks												*/
-#define	RMP16		0x0001	/* RX Message Pending In Mailbox 16	*/
-#define	RMP17		0x0002	/* RX Message Pending In Mailbox 17	*/
-#define	RMP18		0x0004	/* RX Message Pending In Mailbox 18	*/
-#define	RMP19		0x0008	/* RX Message Pending In Mailbox 19	*/
-#define	RMP20		0x0010	/* RX Message Pending In Mailbox 20	*/
-#define	RMP21		0x0020	/* RX Message Pending In Mailbox 21	*/
-#define	RMP22		0x0040	/* RX Message Pending In Mailbox 22	*/
-#define	RMP23		0x0080	/* RX Message Pending In Mailbox 23	*/
-#define	RMP24		0x0100	/* RX Message Pending In Mailbox 24	*/
-#define	RMP25		0x0200	/* RX Message Pending In Mailbox 25	*/
-#define	RMP26		0x0400	/* RX Message Pending In Mailbox 26	*/
-#define	RMP27		0x0800	/* RX Message Pending In Mailbox 27	*/
-#define	RMP28		0x1000	/* RX Message Pending In Mailbox 28	*/
-#define	RMP29		0x2000	/* RX Message Pending In Mailbox 29	*/
-#define	RMP30		0x4000	/* RX Message Pending In Mailbox 30	*/
-#define	RMP31		0x8000	/* RX Message Pending In Mailbox 31	*/
-
-/* CAN_RML1 Masks												*/
-#define	RML0		0x0001	/* RX Message Lost In Mailbox 0		*/
-#define	RML1		0x0002	/* RX Message Lost In Mailbox 1		*/
-#define	RML2		0x0004	/* RX Message Lost In Mailbox 2		*/
-#define	RML3		0x0008	/* RX Message Lost In Mailbox 3		*/
-#define	RML4		0x0010	/* RX Message Lost In Mailbox 4		*/
-#define	RML5		0x0020	/* RX Message Lost In Mailbox 5		*/
-#define	RML6		0x0040	/* RX Message Lost In Mailbox 6		*/
-#define	RML7		0x0080	/* RX Message Lost In Mailbox 7		*/
-#define	RML8		0x0100	/* RX Message Lost In Mailbox 8		*/
-#define	RML9		0x0200	/* RX Message Lost In Mailbox 9		*/
-#define	RML10		0x0400	/* RX Message Lost In Mailbox 10	*/
-#define	RML11		0x0800	/* RX Message Lost In Mailbox 11	*/
-#define	RML12		0x1000	/* RX Message Lost In Mailbox 12	*/
-#define	RML13		0x2000	/* RX Message Lost In Mailbox 13	*/
-#define	RML14		0x4000	/* RX Message Lost In Mailbox 14	*/
-#define	RML15		0x8000	/* RX Message Lost In Mailbox 15	*/
-
-/* CAN_RML2 Masks												*/
-#define	RML16		0x0001	/* RX Message Lost In Mailbox 16	*/
-#define	RML17		0x0002	/* RX Message Lost In Mailbox 17	*/
-#define	RML18		0x0004	/* RX Message Lost In Mailbox 18	*/
-#define	RML19		0x0008	/* RX Message Lost In Mailbox 19	*/
-#define	RML20		0x0010	/* RX Message Lost In Mailbox 20	*/
-#define	RML21		0x0020	/* RX Message Lost In Mailbox 21	*/
-#define	RML22		0x0040	/* RX Message Lost In Mailbox 22	*/
-#define	RML23		0x0080	/* RX Message Lost In Mailbox 23	*/
-#define	RML24		0x0100	/* RX Message Lost In Mailbox 24	*/
-#define	RML25		0x0200	/* RX Message Lost In Mailbox 25	*/
-#define	RML26		0x0400	/* RX Message Lost In Mailbox 26	*/
-#define	RML27		0x0800	/* RX Message Lost In Mailbox 27	*/
-#define	RML28		0x1000	/* RX Message Lost In Mailbox 28	*/
-#define	RML29		0x2000	/* RX Message Lost In Mailbox 29	*/
-#define	RML30		0x4000	/* RX Message Lost In Mailbox 30	*/
-#define	RML31		0x8000	/* RX Message Lost In Mailbox 31	*/
-
-/* CAN_OPSS1 Masks																				*/
-#define	OPSS0		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0	*/
-#define	OPSS1		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1	*/
-#define	OPSS2		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2	*/
-#define	OPSS3		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3	*/
-#define	OPSS4		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4	*/
-#define	OPSS5		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5	*/
-#define	OPSS6		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6	*/
-#define	OPSS7		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7	*/
-#define	OPSS8		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8	*/
-#define	OPSS9		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9	*/
-#define	OPSS10		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10	*/
-#define	OPSS11		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11	*/
-#define	OPSS12		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12	*/
-#define	OPSS13		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13	*/
-#define	OPSS14		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14	*/
-#define	OPSS15		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15	*/
-
-/* CAN_OPSS2 Masks																				*/
-#define	OPSS16		0x0001	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16	*/
-#define	OPSS17		0x0002	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17	*/
-#define	OPSS18		0x0004	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18	*/
-#define	OPSS19		0x0008	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19	*/
-#define	OPSS20		0x0010	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20	*/
-#define	OPSS21		0x0020	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21	*/
-#define	OPSS22		0x0040	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22	*/
-#define	OPSS23		0x0080	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23	*/
-#define	OPSS24		0x0100	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24	*/
-#define	OPSS25		0x0200	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25	*/
-#define	OPSS26		0x0400	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26	*/
-#define	OPSS27		0x0800	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27	*/
-#define	OPSS28		0x1000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28	*/
-#define	OPSS29		0x2000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29	*/
-#define	OPSS30		0x4000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30	*/
-#define	OPSS31		0x8000	/* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31	*/
-
-/* CAN_TRR1 Masks														*/
-#define	TRR0		0x0001	/* Deny But Don't Lock Access To Mailbox 0	*/
-#define	TRR1		0x0002	/* Deny But Don't Lock Access To Mailbox 1	*/
-#define	TRR2		0x0004	/* Deny But Don't Lock Access To Mailbox 2	*/
-#define	TRR3		0x0008	/* Deny But Don't Lock Access To Mailbox 3	*/
-#define	TRR4		0x0010	/* Deny But Don't Lock Access To Mailbox 4	*/
-#define	TRR5		0x0020	/* Deny But Don't Lock Access To Mailbox 5	*/
-#define	TRR6		0x0040	/* Deny But Don't Lock Access To Mailbox 6	*/
-#define	TRR7		0x0080	/* Deny But Don't Lock Access To Mailbox 7	*/
-#define	TRR8		0x0100	/* Deny But Don't Lock Access To Mailbox 8	*/
-#define	TRR9		0x0200	/* Deny But Don't Lock Access To Mailbox 9	*/
-#define	TRR10		0x0400	/* Deny But Don't Lock Access To Mailbox 10	*/
-#define	TRR11		0x0800	/* Deny But Don't Lock Access To Mailbox 11	*/
-#define	TRR12		0x1000	/* Deny But Don't Lock Access To Mailbox 12	*/
-#define	TRR13		0x2000	/* Deny But Don't Lock Access To Mailbox 13	*/
-#define	TRR14		0x4000	/* Deny But Don't Lock Access To Mailbox 14	*/
-#define	TRR15		0x8000	/* Deny But Don't Lock Access To Mailbox 15	*/
-
-/* CAN_TRR2 Masks														*/
-#define	TRR16		0x0001	/* Deny But Don't Lock Access To Mailbox 16	*/
-#define	TRR17		0x0002	/* Deny But Don't Lock Access To Mailbox 17	*/
-#define	TRR18		0x0004	/* Deny But Don't Lock Access To Mailbox 18	*/
-#define	TRR19		0x0008	/* Deny But Don't Lock Access To Mailbox 19	*/
-#define	TRR20		0x0010	/* Deny But Don't Lock Access To Mailbox 20	*/
-#define	TRR21		0x0020	/* Deny But Don't Lock Access To Mailbox 21	*/
-#define	TRR22		0x0040	/* Deny But Don't Lock Access To Mailbox 22	*/
-#define	TRR23		0x0080	/* Deny But Don't Lock Access To Mailbox 23	*/
-#define	TRR24		0x0100	/* Deny But Don't Lock Access To Mailbox 24	*/
-#define	TRR25		0x0200	/* Deny But Don't Lock Access To Mailbox 25	*/
-#define	TRR26		0x0400	/* Deny But Don't Lock Access To Mailbox 26	*/
-#define	TRR27		0x0800	/* Deny But Don't Lock Access To Mailbox 27	*/
-#define	TRR28		0x1000	/* Deny But Don't Lock Access To Mailbox 28	*/
-#define	TRR29		0x2000	/* Deny But Don't Lock Access To Mailbox 29	*/
-#define	TRR30		0x4000	/* Deny But Don't Lock Access To Mailbox 30	*/
-#define	TRR31		0x8000	/* Deny But Don't Lock Access To Mailbox 31	*/
-
-/* CAN_TRS1 Masks													*/
-#define	TRS0		0x0001	/* Remote Frame Request For Mailbox 0	*/
-#define	TRS1		0x0002	/* Remote Frame Request For Mailbox 1	*/
-#define	TRS2		0x0004	/* Remote Frame Request For Mailbox 2	*/
-#define	TRS3		0x0008	/* Remote Frame Request For Mailbox 3	*/
-#define	TRS4		0x0010	/* Remote Frame Request For Mailbox 4	*/
-#define	TRS5		0x0020	/* Remote Frame Request For Mailbox 5	*/
-#define	TRS6		0x0040	/* Remote Frame Request For Mailbox 6	*/
-#define	TRS7		0x0080	/* Remote Frame Request For Mailbox 7	*/
-#define	TRS8		0x0100	/* Remote Frame Request For Mailbox 8	*/
-#define	TRS9		0x0200	/* Remote Frame Request For Mailbox 9	*/
-#define	TRS10		0x0400	/* Remote Frame Request For Mailbox 10	*/
-#define	TRS11		0x0800	/* Remote Frame Request For Mailbox 11	*/
-#define	TRS12		0x1000	/* Remote Frame Request For Mailbox 12	*/
-#define	TRS13		0x2000	/* Remote Frame Request For Mailbox 13	*/
-#define	TRS14		0x4000	/* Remote Frame Request For Mailbox 14	*/
-#define	TRS15		0x8000	/* Remote Frame Request For Mailbox 15	*/
-
-/* CAN_TRS2 Masks													*/
-#define	TRS16		0x0001	/* Remote Frame Request For Mailbox 16	*/
-#define	TRS17		0x0002	/* Remote Frame Request For Mailbox 17	*/
-#define	TRS18		0x0004	/* Remote Frame Request For Mailbox 18	*/
-#define	TRS19		0x0008	/* Remote Frame Request For Mailbox 19	*/
-#define	TRS20		0x0010	/* Remote Frame Request For Mailbox 20	*/
-#define	TRS21		0x0020	/* Remote Frame Request For Mailbox 21	*/
-#define	TRS22		0x0040	/* Remote Frame Request For Mailbox 22	*/
-#define	TRS23		0x0080	/* Remote Frame Request For Mailbox 23	*/
-#define	TRS24		0x0100	/* Remote Frame Request For Mailbox 24	*/
-#define	TRS25		0x0200	/* Remote Frame Request For Mailbox 25	*/
-#define	TRS26		0x0400	/* Remote Frame Request For Mailbox 26	*/
-#define	TRS27		0x0800	/* Remote Frame Request For Mailbox 27	*/
-#define	TRS28		0x1000	/* Remote Frame Request For Mailbox 28	*/
-#define	TRS29		0x2000	/* Remote Frame Request For Mailbox 29	*/
-#define	TRS30		0x4000	/* Remote Frame Request For Mailbox 30	*/
-#define	TRS31		0x8000	/* Remote Frame Request For Mailbox 31	*/
-
-/* CAN_AA1 Masks												*/
-#define	AA0			0x0001	/* Aborted Message In Mailbox 0		*/
-#define	AA1			0x0002	/* Aborted Message In Mailbox 1		*/
-#define	AA2			0x0004	/* Aborted Message In Mailbox 2		*/
-#define	AA3			0x0008	/* Aborted Message In Mailbox 3		*/
-#define	AA4			0x0010	/* Aborted Message In Mailbox 4		*/
-#define	AA5			0x0020	/* Aborted Message In Mailbox 5		*/
-#define	AA6			0x0040	/* Aborted Message In Mailbox 6		*/
-#define	AA7			0x0080	/* Aborted Message In Mailbox 7		*/
-#define	AA8			0x0100	/* Aborted Message In Mailbox 8		*/
-#define	AA9			0x0200	/* Aborted Message In Mailbox 9		*/
-#define	AA10		0x0400	/* Aborted Message In Mailbox 10	*/
-#define	AA11		0x0800	/* Aborted Message In Mailbox 11	*/
-#define	AA12		0x1000	/* Aborted Message In Mailbox 12	*/
-#define	AA13		0x2000	/* Aborted Message In Mailbox 13	*/
-#define	AA14		0x4000	/* Aborted Message In Mailbox 14	*/
-#define	AA15		0x8000	/* Aborted Message In Mailbox 15	*/
-
-/* CAN_AA2 Masks												*/
-#define	AA16		0x0001	/* Aborted Message In Mailbox 16	*/
-#define	AA17		0x0002	/* Aborted Message In Mailbox 17	*/
-#define	AA18		0x0004	/* Aborted Message In Mailbox 18	*/
-#define	AA19		0x0008	/* Aborted Message In Mailbox 19	*/
-#define	AA20		0x0010	/* Aborted Message In Mailbox 20	*/
-#define	AA21		0x0020	/* Aborted Message In Mailbox 21	*/
-#define	AA22		0x0040	/* Aborted Message In Mailbox 22	*/
-#define	AA23		0x0080	/* Aborted Message In Mailbox 23	*/
-#define	AA24		0x0100	/* Aborted Message In Mailbox 24	*/
-#define	AA25		0x0200	/* Aborted Message In Mailbox 25	*/
-#define	AA26		0x0400	/* Aborted Message In Mailbox 26	*/
-#define	AA27		0x0800	/* Aborted Message In Mailbox 27	*/
-#define	AA28		0x1000	/* Aborted Message In Mailbox 28	*/
-#define	AA29		0x2000	/* Aborted Message In Mailbox 29	*/
-#define	AA30		0x4000	/* Aborted Message In Mailbox 30	*/
-#define	AA31		0x8000	/* Aborted Message In Mailbox 31	*/
-
-/* CAN_TA1 Masks													*/
-#define	TA0			0x0001	/* Transmit Successful From Mailbox 0	*/
-#define	TA1			0x0002	/* Transmit Successful From Mailbox 1	*/
-#define	TA2			0x0004	/* Transmit Successful From Mailbox 2	*/
-#define	TA3			0x0008	/* Transmit Successful From Mailbox 3	*/
-#define	TA4			0x0010	/* Transmit Successful From Mailbox 4	*/
-#define	TA5			0x0020	/* Transmit Successful From Mailbox 5	*/
-#define	TA6			0x0040	/* Transmit Successful From Mailbox 6	*/
-#define	TA7			0x0080	/* Transmit Successful From Mailbox 7	*/
-#define	TA8			0x0100	/* Transmit Successful From Mailbox 8	*/
-#define	TA9			0x0200	/* Transmit Successful From Mailbox 9	*/
-#define	TA10		0x0400	/* Transmit Successful From Mailbox 10	*/
-#define	TA11		0x0800	/* Transmit Successful From Mailbox 11	*/
-#define	TA12		0x1000	/* Transmit Successful From Mailbox 12	*/
-#define	TA13		0x2000	/* Transmit Successful From Mailbox 13	*/
-#define	TA14		0x4000	/* Transmit Successful From Mailbox 14	*/
-#define	TA15		0x8000	/* Transmit Successful From Mailbox 15	*/
-
-/* CAN_TA2 Masks													*/
-#define	TA16		0x0001	/* Transmit Successful From Mailbox 16	*/
-#define	TA17		0x0002	/* Transmit Successful From Mailbox 17	*/
-#define	TA18		0x0004	/* Transmit Successful From Mailbox 18	*/
-#define	TA19		0x0008	/* Transmit Successful From Mailbox 19	*/
-#define	TA20		0x0010	/* Transmit Successful From Mailbox 20	*/
-#define	TA21		0x0020	/* Transmit Successful From Mailbox 21	*/
-#define	TA22		0x0040	/* Transmit Successful From Mailbox 22	*/
-#define	TA23		0x0080	/* Transmit Successful From Mailbox 23	*/
-#define	TA24		0x0100	/* Transmit Successful From Mailbox 24	*/
-#define	TA25		0x0200	/* Transmit Successful From Mailbox 25	*/
-#define	TA26		0x0400	/* Transmit Successful From Mailbox 26	*/
-#define	TA27		0x0800	/* Transmit Successful From Mailbox 27	*/
-#define	TA28		0x1000	/* Transmit Successful From Mailbox 28	*/
-#define	TA29		0x2000	/* Transmit Successful From Mailbox 29	*/
-#define	TA30		0x4000	/* Transmit Successful From Mailbox 30	*/
-#define	TA31		0x8000	/* Transmit Successful From Mailbox 31	*/
-
-/* CAN_MBTD Masks												*/
-#define TDPTR		0x001F	/* Mailbox To Temporarily Disable	*/
-#define	TDA			0x0040	/* Temporary Disable Acknowledge	*/
-#define	TDR			0x0080	/* Temporary Disable Request		*/
-
-/* CAN_RFH1 Masks																		*/
-#define	RFH0		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 0		*/
-#define	RFH1		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 1		*/
-#define	RFH2		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 2		*/
-#define	RFH3		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 3		*/
-#define	RFH4		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 4		*/
-#define	RFH5		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 5		*/
-#define	RFH6		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 6		*/
-#define	RFH7		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 7		*/
-#define	RFH8		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 8		*/
-#define	RFH9		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 9		*/
-#define	RFH10		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 10	*/
-#define	RFH11		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 11	*/
-#define	RFH12		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 12	*/
-#define	RFH13		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 13	*/
-#define	RFH14		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 14	*/
-#define	RFH15		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 15	*/
-
-/* CAN_RFH2 Masks																		*/
-#define	RFH16		0x0001	/* Enable Automatic Remote Frame Handling For Mailbox 16	*/
-#define	RFH17		0x0002	/* Enable Automatic Remote Frame Handling For Mailbox 17	*/
-#define	RFH18		0x0004	/* Enable Automatic Remote Frame Handling For Mailbox 18	*/
-#define	RFH19		0x0008	/* Enable Automatic Remote Frame Handling For Mailbox 19	*/
-#define	RFH20		0x0010	/* Enable Automatic Remote Frame Handling For Mailbox 20	*/
-#define	RFH21		0x0020	/* Enable Automatic Remote Frame Handling For Mailbox 21	*/
-#define	RFH22		0x0040	/* Enable Automatic Remote Frame Handling For Mailbox 22	*/
-#define	RFH23		0x0080	/* Enable Automatic Remote Frame Handling For Mailbox 23	*/
-#define	RFH24		0x0100	/* Enable Automatic Remote Frame Handling For Mailbox 24	*/
-#define	RFH25		0x0200	/* Enable Automatic Remote Frame Handling For Mailbox 25	*/
-#define	RFH26		0x0400	/* Enable Automatic Remote Frame Handling For Mailbox 26	*/
-#define	RFH27		0x0800	/* Enable Automatic Remote Frame Handling For Mailbox 27	*/
-#define	RFH28		0x1000	/* Enable Automatic Remote Frame Handling For Mailbox 28	*/
-#define	RFH29		0x2000	/* Enable Automatic Remote Frame Handling For Mailbox 29	*/
-#define	RFH30		0x4000	/* Enable Automatic Remote Frame Handling For Mailbox 30	*/
-#define	RFH31		0x8000	/* Enable Automatic Remote Frame Handling For Mailbox 31	*/
-
-/* CAN_MBTIF1 Masks													*/
-#define	MBTIF0		0x0001	/* TX Interrupt Active In Mailbox 0		*/
-#define	MBTIF1		0x0002	/* TX Interrupt Active In Mailbox 1		*/
-#define	MBTIF2		0x0004	/* TX Interrupt Active In Mailbox 2		*/
-#define	MBTIF3		0x0008	/* TX Interrupt Active In Mailbox 3		*/
-#define	MBTIF4		0x0010	/* TX Interrupt Active In Mailbox 4		*/
-#define	MBTIF5		0x0020	/* TX Interrupt Active In Mailbox 5		*/
-#define	MBTIF6		0x0040	/* TX Interrupt Active In Mailbox 6		*/
-#define	MBTIF7		0x0080	/* TX Interrupt Active In Mailbox 7		*/
-#define	MBTIF8		0x0100	/* TX Interrupt Active In Mailbox 8		*/
-#define	MBTIF9		0x0200	/* TX Interrupt Active In Mailbox 9		*/
-#define	MBTIF10		0x0400	/* TX Interrupt Active In Mailbox 10	*/
-#define	MBTIF11		0x0800	/* TX Interrupt Active In Mailbox 11	*/
-#define	MBTIF12		0x1000	/* TX Interrupt Active In Mailbox 12	*/
-#define	MBTIF13		0x2000	/* TX Interrupt Active In Mailbox 13	*/
-#define	MBTIF14		0x4000	/* TX Interrupt Active In Mailbox 14	*/
-#define	MBTIF15		0x8000	/* TX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBTIF2 Masks													*/
-#define	MBTIF16		0x0001	/* TX Interrupt Active In Mailbox 16	*/
-#define	MBTIF17		0x0002	/* TX Interrupt Active In Mailbox 17	*/
-#define	MBTIF18		0x0004	/* TX Interrupt Active In Mailbox 18	*/
-#define	MBTIF19		0x0008	/* TX Interrupt Active In Mailbox 19	*/
-#define	MBTIF20		0x0010	/* TX Interrupt Active In Mailbox 20	*/
-#define	MBTIF21		0x0020	/* TX Interrupt Active In Mailbox 21	*/
-#define	MBTIF22		0x0040	/* TX Interrupt Active In Mailbox 22	*/
-#define	MBTIF23		0x0080	/* TX Interrupt Active In Mailbox 23	*/
-#define	MBTIF24		0x0100	/* TX Interrupt Active In Mailbox 24	*/
-#define	MBTIF25		0x0200	/* TX Interrupt Active In Mailbox 25	*/
-#define	MBTIF26		0x0400	/* TX Interrupt Active In Mailbox 26	*/
-#define	MBTIF27		0x0800	/* TX Interrupt Active In Mailbox 27	*/
-#define	MBTIF28		0x1000	/* TX Interrupt Active In Mailbox 28	*/
-#define	MBTIF29		0x2000	/* TX Interrupt Active In Mailbox 29	*/
-#define	MBTIF30		0x4000	/* TX Interrupt Active In Mailbox 30	*/
-#define	MBTIF31		0x8000	/* TX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBRIF1 Masks													*/
-#define	MBRIF0		0x0001	/* RX Interrupt Active In Mailbox 0		*/
-#define	MBRIF1		0x0002	/* RX Interrupt Active In Mailbox 1		*/
-#define	MBRIF2		0x0004	/* RX Interrupt Active In Mailbox 2		*/
-#define	MBRIF3		0x0008	/* RX Interrupt Active In Mailbox 3		*/
-#define	MBRIF4		0x0010	/* RX Interrupt Active In Mailbox 4		*/
-#define	MBRIF5		0x0020	/* RX Interrupt Active In Mailbox 5		*/
-#define	MBRIF6		0x0040	/* RX Interrupt Active In Mailbox 6		*/
-#define	MBRIF7		0x0080	/* RX Interrupt Active In Mailbox 7		*/
-#define	MBRIF8		0x0100	/* RX Interrupt Active In Mailbox 8		*/
-#define	MBRIF9		0x0200	/* RX Interrupt Active In Mailbox 9		*/
-#define	MBRIF10		0x0400	/* RX Interrupt Active In Mailbox 10	*/
-#define	MBRIF11		0x0800	/* RX Interrupt Active In Mailbox 11	*/
-#define	MBRIF12		0x1000	/* RX Interrupt Active In Mailbox 12	*/
-#define	MBRIF13		0x2000	/* RX Interrupt Active In Mailbox 13	*/
-#define	MBRIF14		0x4000	/* RX Interrupt Active In Mailbox 14	*/
-#define	MBRIF15		0x8000	/* RX Interrupt Active In Mailbox 15	*/
-
-/* CAN_MBRIF2 Masks													*/
-#define	MBRIF16		0x0001	/* RX Interrupt Active In Mailbox 16	*/
-#define	MBRIF17		0x0002	/* RX Interrupt Active In Mailbox 17	*/
-#define	MBRIF18		0x0004	/* RX Interrupt Active In Mailbox 18	*/
-#define	MBRIF19		0x0008	/* RX Interrupt Active In Mailbox 19	*/
-#define	MBRIF20		0x0010	/* RX Interrupt Active In Mailbox 20	*/
-#define	MBRIF21		0x0020	/* RX Interrupt Active In Mailbox 21	*/
-#define	MBRIF22		0x0040	/* RX Interrupt Active In Mailbox 22	*/
-#define	MBRIF23		0x0080	/* RX Interrupt Active In Mailbox 23	*/
-#define	MBRIF24		0x0100	/* RX Interrupt Active In Mailbox 24	*/
-#define	MBRIF25		0x0200	/* RX Interrupt Active In Mailbox 25	*/
-#define	MBRIF26		0x0400	/* RX Interrupt Active In Mailbox 26	*/
-#define	MBRIF27		0x0800	/* RX Interrupt Active In Mailbox 27	*/
-#define	MBRIF28		0x1000	/* RX Interrupt Active In Mailbox 28	*/
-#define	MBRIF29		0x2000	/* RX Interrupt Active In Mailbox 29	*/
-#define	MBRIF30		0x4000	/* RX Interrupt Active In Mailbox 30	*/
-#define	MBRIF31		0x8000	/* RX Interrupt Active In Mailbox 31	*/
-
-/* CAN_MBIM1 Masks												*/
-#define	MBIM0		0x0001	/* Enable Interrupt For Mailbox 0	*/
-#define	MBIM1		0x0002	/* Enable Interrupt For Mailbox 1	*/
-#define	MBIM2		0x0004	/* Enable Interrupt For Mailbox 2	*/
-#define	MBIM3		0x0008	/* Enable Interrupt For Mailbox 3	*/
-#define	MBIM4		0x0010	/* Enable Interrupt For Mailbox 4	*/
-#define	MBIM5		0x0020	/* Enable Interrupt For Mailbox 5	*/
-#define	MBIM6		0x0040	/* Enable Interrupt For Mailbox 6	*/
-#define	MBIM7		0x0080	/* Enable Interrupt For Mailbox 7	*/
-#define	MBIM8		0x0100	/* Enable Interrupt For Mailbox 8	*/
-#define	MBIM9		0x0200	/* Enable Interrupt For Mailbox 9	*/
-#define	MBIM10		0x0400	/* Enable Interrupt For Mailbox 10	*/
-#define	MBIM11		0x0800	/* Enable Interrupt For Mailbox 11	*/
-#define	MBIM12		0x1000	/* Enable Interrupt For Mailbox 12	*/
-#define	MBIM13		0x2000	/* Enable Interrupt For Mailbox 13	*/
-#define	MBIM14		0x4000	/* Enable Interrupt For Mailbox 14	*/
-#define	MBIM15		0x8000	/* Enable Interrupt For Mailbox 15	*/
-
-/* CAN_MBIM2 Masks												*/
-#define	MBIM16		0x0001	/* Enable Interrupt For Mailbox 16	*/
-#define	MBIM17		0x0002	/* Enable Interrupt For Mailbox 17	*/
-#define	MBIM18		0x0004	/* Enable Interrupt For Mailbox 18	*/
-#define	MBIM19		0x0008	/* Enable Interrupt For Mailbox 19	*/
-#define	MBIM20		0x0010	/* Enable Interrupt For Mailbox 20	*/
-#define	MBIM21		0x0020	/* Enable Interrupt For Mailbox 21	*/
-#define	MBIM22		0x0040	/* Enable Interrupt For Mailbox 22	*/
-#define	MBIM23		0x0080	/* Enable Interrupt For Mailbox 23	*/
-#define	MBIM24		0x0100	/* Enable Interrupt For Mailbox 24	*/
-#define	MBIM25		0x0200	/* Enable Interrupt For Mailbox 25	*/
-#define	MBIM26		0x0400	/* Enable Interrupt For Mailbox 26	*/
-#define	MBIM27		0x0800	/* Enable Interrupt For Mailbox 27	*/
-#define	MBIM28		0x1000	/* Enable Interrupt For Mailbox 28	*/
-#define	MBIM29		0x2000	/* Enable Interrupt For Mailbox 29	*/
-#define	MBIM30		0x4000	/* Enable Interrupt For Mailbox 30	*/
-#define	MBIM31		0x8000	/* Enable Interrupt For Mailbox 31	*/
-
-/* CAN_GIM Masks																*/
-#define	EWTIM		0x0001	/* Enable TX Error Count Interrupt					*/
-#define	EWRIM		0x0002	/* Enable RX Error Count Interrupt					*/
-#define	EPIM		0x0004	/* Enable Error-Passive Mode Interrupt				*/
-#define	BOIM		0x0008	/* Enable Bus Off Interrupt							*/
-#define	WUIM		0x0010	/* Enable Wake-Up Interrupt							*/
-#define	UIAIM		0x0020	/* Enable Access To Unimplemented Address Interrupt	*/
-#define	AAIM		0x0040	/* Enable Abort Acknowledge Interrupt				*/
-#define	RMLIM		0x0080	/* Enable RX Message Lost Interrupt					*/
-#define	UCEIM		0x0100	/* Enable Universal Counter Overflow Interrupt		*/
-#define	EXTIM		0x0200	/* Enable External Trigger Output Interrupt			*/
-#define	ADIM		0x0400	/* Enable Access Denied Interrupt					*/
-
-/* CAN_GIS Masks															*/
-#define	EWTIS		0x0001	/* TX Error Count IRQ Status					*/
-#define	EWRIS		0x0002	/* RX Error Count IRQ Status					*/
-#define	EPIS		0x0004	/* Error-Passive Mode IRQ Status				*/
-#define	BOIS		0x0008	/* Bus Off IRQ Status							*/
-#define	WUIS		0x0010	/* Wake-Up IRQ Status							*/
-#define	UIAIS		0x0020	/* Access To Unimplemented Address IRQ Status	*/
-#define	AAIS		0x0040	/* Abort Acknowledge IRQ Status					*/
-#define	RMLIS		0x0080	/* RX Message Lost IRQ Status					*/
-#define	UCEIS		0x0100	/* Universal Counter Overflow IRQ Status		*/
-#define	EXTIS		0x0200	/* External Trigger Output IRQ Status			*/
-#define	ADIS		0x0400	/* Access Denied IRQ Status						*/
-
-/* CAN_GIF Masks															*/
-#define	EWTIF		0x0001	/* TX Error Count IRQ Flag						*/
-#define	EWRIF		0x0002	/* RX Error Count IRQ Flag						*/
-#define	EPIF		0x0004	/* Error-Passive Mode IRQ Flag					*/
-#define	BOIF		0x0008	/* Bus Off IRQ Flag								*/
-#define	WUIF		0x0010	/* Wake-Up IRQ Flag								*/
-#define	UIAIF		0x0020	/* Access To Unimplemented Address IRQ Flag		*/
-#define	AAIF		0x0040	/* Abort Acknowledge IRQ Flag					*/
-#define	RMLIF		0x0080	/* RX Message Lost IRQ Flag						*/
-#define	UCEIF		0x0100	/* Universal Counter Overflow IRQ Flag			*/
-#define	EXTIF		0x0200	/* External Trigger Output IRQ Flag				*/
-#define	ADIF		0x0400	/* Access Denied IRQ Flag						*/
-
-/* CAN_UCCNF Masks															*/
-#define	UCCNF		0x000F	/* Universal Counter Mode						*/
-#define UC_STAMP	0x0001	/* 		Timestamp Mode							*/
-#define UC_WDOG		0x0002	/* 		Watchdog Mode							*/
-#define UC_AUTOTX	0x0003	/* 		Auto-Transmit Mode						*/
-#define UC_ERROR	0x0006	/* 		CAN Error Frame Count					*/
-#define UC_OVER		0x0007	/* 		CAN Overload Frame Count				*/
-#define UC_LOST		0x0008	/* 		Arbitration Lost During TX Count		*/
-#define UC_AA		0x0009	/* 		TX Abort Count							*/
-#define UC_TA		0x000A	/* 		TX Successful Count						*/
-#define UC_REJECT	0x000B	/* 		RX Message Rejected Count				*/
-#define UC_RML		0x000C	/* 		RX Message Lost Count					*/
-#define UC_RX		0x000D	/* 		Total Successful RX Messages Count		*/
-#define UC_RMP		0x000E	/* 		Successful RX W/Matching ID Count		*/
-#define UC_ALL		0x000F	/* 		Correct Message On CAN Bus Line Count	*/
-#define	UCRC		0x0020	/* Universal Counter Reload/Clear				*/
-#define	UCCT		0x0040	/* Universal Counter CAN Trigger				*/
-#define	UCE			0x0080	/* Universal Counter Enable						*/
-
-/* CAN_ESR Masks										*/
-#define	ACKE		0x0004	/* Acknowledge Error		*/
-#define	SER			0x0008	/* Stuff Error				*/
-#define	CRCE		0x0010	/* CRC Error				*/
-#define	SA0			0x0020	/* Stuck At Dominant Error	*/
-#define	BEF			0x0040	/* Bit Error Flag			*/
-#define	FER			0x0080	/* Form Error Flag			*/
-
-/* CAN_EWR Masks												*/
-#define	EWLREC		0x00FF	/* RX Error Count Limit (For EWRIS)	*/
-#define	EWLTEC		0xFF00	/* TX Error Count Limit (For EWTIS)	*/
-
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF539_H */
diff --git a/libgloss/bfin/include/defBF542.h b/libgloss/bfin/include/defBF542.h
deleted file mode 100644
index be1e57dd1..000000000
--- a/libgloss/bfin/include/defBF542.h
+++ /dev/null
@@ -1,1238 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF542.h
-**
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
-#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
-#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
-
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-#ifdef _MISRA_RULES
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#else
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-#ifdef _MISRA_RULES
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
-#else
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-#ifdef _MISRA_RULES
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
-#else
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0
-#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
-#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
-#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
-#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0
-#define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0
-#define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF542_H */
diff --git a/libgloss/bfin/include/defBF542M.h b/libgloss/bfin/include/defBF542M.h
deleted file mode 100644
index ea38f827d..000000000
--- a/libgloss/bfin/include/defBF542M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF542M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps directly onto the def file for BF542, unless
-** anything is required to change for the M derivative.
-**
-**/
-
-#ifndef _DEF_BF542M_H
-#define _DEF_BF542M_H
-
-#include <defBF542.h>
-
-#endif /* _DEF_BF542M_H */
diff --git a/libgloss/bfin/include/defBF544.h b/libgloss/bfin/include/defBF544.h
deleted file mode 100644
index 681f042bd..000000000
--- a/libgloss/bfin/include/defBF544.h
+++ /dev/null
@@ -1,714 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF544.h
-**
-** Copyright (C) 2006-2007 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* Universal Counter Reload/Capture Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#endif /* _DEF_BF544_H */
diff --git a/libgloss/bfin/include/defBF544M.h b/libgloss/bfin/include/defBF544M.h
deleted file mode 100644
index c61640a35..000000000
--- a/libgloss/bfin/include/defBF544M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF544M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps directly onto the def file for BF544, unless
-** anything is required to change for the M derivative.
-**
-**/
-
-#ifndef _DEF_BF544M_H
-#define _DEF_BF544M_H
-
-#include <defBF544.h>
-
-#endif /* _DEF_BF544M_H */
diff --git a/libgloss/bfin/include/defBF547.h b/libgloss/bfin/include/defBF547.h
deleted file mode 100644
index d87a96c04..000000000
--- a/libgloss/bfin/include/defBF547.h
+++ /dev/null
@@ -1,1575 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF547.h
-**
-** Copyright (C) 2007-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF547_H
-#define _DEF_BF547_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4 ")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_THR  0xffc02128   /* Transmit Hold Register */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
-#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
-#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
-
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-#ifdef _MISRA_RULES
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#else
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-#ifdef _MISRA_RULES
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#else
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-#ifdef _MISRA_RULES
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#else
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0
-#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
-#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
-#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
-#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0
-#define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0
-#define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF547_H */
diff --git a/libgloss/bfin/include/defBF547M.h b/libgloss/bfin/include/defBF547M.h
deleted file mode 100644
index 6c8cc506f..000000000
--- a/libgloss/bfin/include/defBF547M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF547M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps directly onto the def file for BF547, unless
-** anything is required to change for the M derivative.
-**
-**/
-
-#ifndef _DEF_BF547M_H
-#define _DEF_BF547M_H
-
-#include <defBF547.h>
-
-#endif /* _DEF_BF5447M_H */
diff --git a/libgloss/bfin/include/defBF548.h b/libgloss/bfin/include/defBF548.h
deleted file mode 100644
index e804f64e2..000000000
--- a/libgloss/bfin/include/defBF548.h
+++ /dev/null
@@ -1,1957 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF548.h
-**
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4:"some macros violate rule 19.4")
-#pragma diag(suppress:misra_rule_19_7:"Allow function-like macros ")
-#endif /* _MISRA_RULES */
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_THR  0xffc02128   /* Transmit Hold Register */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* Universal Counter Reload/Capture Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
-#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
-#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
-
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-#ifdef _MISRA_RULES
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#else
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-#ifdef _MISRA_RULES
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#else
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-#ifdef _MISRA_RULES
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#else
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0
-#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
-#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
-#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
-#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0
-#define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0
-#define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF548_H */
diff --git a/libgloss/bfin/include/defBF548M.h b/libgloss/bfin/include/defBF548M.h
deleted file mode 100644
index 4a09dcacc..000000000
--- a/libgloss/bfin/include/defBF548M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF548M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps directly onto the def file for BF548, unless
-** anything is required to change for the M derivative.
-**
-**/
-
-#ifndef _DEF_BF548M_H
-#define _DEF_BF548M_H
-
-#include <defBF548.h>
-
-#endif /* _DEF_BF548M_H */
diff --git a/libgloss/bfin/include/defBF549.h b/libgloss/bfin/include/defBF549.h
deleted file mode 100644
index 28e2664e1..000000000
--- a/libgloss/bfin/include/defBF549.h
+++ /dev/null
@@ -1,3476 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF549.h
-**
-** Copyright (C) 2006-2008 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for register-access and bit-manipulation.
-**
-**/
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#endif /* _MISRA_RULES */
-
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include <defBF54x_base.h>
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_THR  0xffc02128   /* Transmit Hold Register */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                   TWI1_SLAVE_CTL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                  TWI1_MASTER_CTL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                    TWI1_FIFO_CTL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* MXVR Registers */
-
-#define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
-#define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
-#define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
-#define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
-#define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
-#define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
-#define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
-#define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
-#define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
-#define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
-#define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
-#define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
-#define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
-#define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
-#define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
-#define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
-#define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
-#define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
-#define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
-#define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
-#define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
-#define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
-#define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
-#define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
-#define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
-#define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
-#define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
-#define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
-#define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
-#define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
-#define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
-#define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
-#define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
-#define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
-#define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
-#define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
-#define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
-#define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
-#define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
-#define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
-#define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
-#define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
-#define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
-#define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
-#define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
-#define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
-#define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
-#define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
-#define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
-#define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
-#define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
-#define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
-#define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
-#define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
-#define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
-#define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
-#define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
-#define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
-#define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
-#define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
-#define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
-#define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
-#define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
-#define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
-#define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
-#define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
-#define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
-#define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
-#define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
-#define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
-#define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
-#define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
-#define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
-#define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
-#define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
-#define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
-#define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
-#define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
-#define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
-#define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
-#define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
-#define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
-#define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
-#define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
-#define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
-#define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
-#define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
-#define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
-#define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
-#define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
-#define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
-#define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* Universal Counter Reload/Capture Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOSTDP Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOSTDP Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOSTDP Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  nPIXC_EN  0x0
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                 nOVR_A_EN  0x0
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                 nOVR_B_EN  0x0
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                 nIMG_FORM  0x0
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                 nOVR_FORM  0x0
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                 nOUT_FORM  0x0
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                  nUDS_MOD  0x0
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                    nTC_EN  0x0
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define               nOVR_INT_EN  0x0
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define               nFRM_INT_EN  0x0
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define             nOVR_INT_STAT  0x0
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-#define             nFRM_INT_STAT  0x0
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nRY_MULT4  0x0
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nGU_MULT4  0x0
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-#define                 nBV_MULT4  0x0
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                 HOSTDP_EN  0x1        /* HOSTDP Enable */
-#define                nHOSTDP_EN  0x0
-#define                HOSTDP_END  0x2        /* Host Endianess */
-#define               nHOSTDP_END  0x0
-#define          HOSTDP_DATA_SIZE  0x4        /* Data Size */
-#define         nHOSTDP_DATA_SIZE  0x0
-#define                HOSTDP_RST  0x8        /* HOSTDP Reset */
-#define               nHOSTDP_RST  0x0
-#define                  HRDY_OVR  0x20       /* HRDY Override */
-#define                 nHRDY_OVR  0x0
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                 nINT_MODE  0x0
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                    nBT_EN  0x0
-#define                       EHW  0x100      /* Enable Host Write */
-#define                      nEHW  0x0
-#define                       EHR  0x200      /* Enable Host Read */
-#define                      nEHR  0x0
-#define                       BDR  0x400      /* Burst DMA Requests */
-#define                      nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                   DMA_RDY  0x1        /* DMA Ready */
-#define                  nDMA_RDY  0x0
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 nFIFOFULL  0x0
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                nFIFOEMPTY  0x0
-#define                 DMA_CMPLT  0x8        /* DMA Complete */
-#define                nDMA_CMPLT  0x0
-#define                      HSHK  0x10       /* Host Handshake */
-#define                     nHSHK  0x0
-#define               HOSTDP_TOUT  0x20       /* HOSTDP Timeout */
-#define              nHOSTDP_TOUT  0x0
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                     nHIRQ  0x0
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               nALLOW_CNFG  0x0
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                  nDMA_DIR  0x0
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-#define                      nBTE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* HOSTDP Timeout count */
-
-/* Bit masks for MXVR_CONFIG */
-
-#define                    MXVREN  0x1        /* MXVR Enable */
-#define                   nMXVREN  0x0
-#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                     nMMSM  0x0
-#define                    ACTIVE  0x4        /* Active Mode */
-#define                   nACTIVE  0x0
-#define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   nSDELAY  0x0
-#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                  nNCMRXEN  0x0
-#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                  nRWRRXEN  0x0
-#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    nMTXEN  0x0
-#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   nMTXONB  0x0
-#define                   EPARITY  0x100      /* Even Parity Select */
-#define                  nEPARITY  0x0
-#define                       MSB  0x1e00     /* Master Synchronous Boundary */
-#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                   nAPRXEN  0x0
-#define                    WAKEUP  0x4000     /* Wake-Up */
-#define                   nWAKEUP  0x0
-#define                     LMECH  0x8000     /* Lock Mechanism Select */
-#define                    nLMECH  0x0
-
-/* Bit masks for MXVR_STATE_0 */
-
-#define                      NACT  0x1        /* Network Activity */
-#define                     nNACT  0x0
-#define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   nSBLOCK  0x0
-#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
-#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
-#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                    nAPBSY  0x0
-#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                    nAPARB  0x0
-#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                     nAPTX  0x0
-#define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     nAPRX  0x0
-#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                    nCMBSY  0x0
-#define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                    nCMARB  0x0
-#define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                     nCMTX  0x0
-#define                      CMRX  0x8000     /* Receiving Control Message */
-#define                     nCMRX  0x0
-#define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                   nMRXONB  0x0
-#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                    nRGSIP  0x0
-#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                    nDALIP  0x0
-#define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     nALIP  0x0
-#define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                    nRRDIP  0x0
-#define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                    nRWRIP  0x0
-#define                     FLOCK  0x400000   /* Frame Lock */
-#define                    nFLOCK  0x0
-#define                     BLOCK  0x800000   /* Block Lock */
-#define                    nBLOCK  0x0
-#define                       RSB  0xf000000  /* Received Synchronous Boundary */
-#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
-
-/* Bit masks for MXVR_STATE_1 */
-
-#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
-#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
-#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                   nAPCONT  0x0
-#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
-#define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define               nDMAACTIVE0  0x0
-#define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define               nDMAACTIVE1  0x0
-#define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define               nDMAACTIVE2  0x0
-#define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define               nDMAACTIVE3  0x0
-#define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define               nDMAACTIVE4  0x0
-#define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define               nDMAACTIVE5  0x0
-#define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define               nDMAACTIVE6  0x0
-#define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define               nDMAACTIVE7  0x0
-#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                 nDMAPMEN0  0x0
-#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                 nDMAPMEN1  0x0
-#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                 nDMAPMEN2  0x0
-#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                 nDMAPMEN3  0x0
-#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                 nDMAPMEN4  0x0
-#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                 nDMAPMEN5  0x0
-#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                 nDMAPMEN6  0x0
-#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-#define                 nDMAPMEN7  0x0
-
-/* Bit masks for MXVR_INT_STAT_0 */
-
-#define                      NI2A  0x1        /* Network Inactive to Active */
-#define                     nNI2A  0x0
-#define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     nNA2I  0x0
-#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                    nSBU2L  0x0
-#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                    nSBL2U  0x0
-#define                       PRU  0x10       /* Position Register Updated */
-#define                      nPRU  0x0
-#define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                     nMPRU  0x0
-#define                       DRU  0x40       /* Delay Register Updated */
-#define                      nDRU  0x0
-#define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                     nMDRU  0x0
-#define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                      nSBU  0x0
-#define                       ATU  0x200      /* Allocation Table Updated */
-#define                      nATU  0x0
-#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                     nFCZ0  0x0
-#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                     nFCZ1  0x0
-#define                      PERR  0x1000     /* Parity Error */
-#define                     nPERR  0x0
-#define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                     nMH2L  0x0
-#define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                     nML2H  0x0
-#define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      nWUP  0x0
-#define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                     nFU2L  0x0
-#define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                     nFL2U  0x0
-#define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                     nBU2L  0x0
-#define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     nBL2U  0x0
-#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                    nOBERR  0x0
-#define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                      nPFL  0x0
-#define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      nSCZ  0x0
-#define                      FERR  0x800000   /* FIFO Error */
-#define                     nFERR  0x0
-#define                       CMR  0x1000000  /* Control Message Received */
-#define                      nCMR  0x0
-#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                    nCMROF  0x0
-#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                     nCMTS  0x0
-#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                     nCMTC  0x0
-#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                     nRWRC  0x0
-#define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                      nBCZ  0x0
-#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                    nBMERR  0x0
-#define                      DERR  0x80000000 /* DMA Error */
-#define                     nDERR  0x0
-
-/* Bit masks for MXVR_INT_STAT_1 */
-
-#define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                   nHDONE0  0x0
-#define                     DONE0  0x2        /* DMA0 Done */
-#define                    nDONE0  0x0
-#define                       APR  0x4        /* Asynchronous Packet Received */
-#define                      nAPR  0x0
-#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    nAPROF  0x0
-#define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                   nHDONE1  0x0
-#define                     DONE1  0x20       /* DMA1 Done */
-#define                    nDONE1  0x0
-#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                     nAPTS  0x0
-#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                     nAPTC  0x0
-#define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                   nHDONE2  0x0
-#define                     DONE2  0x200      /* DMA2 Done */
-#define                    nDONE2  0x0
-#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                    nAPRCE  0x0
-#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    nAPRPE  0x0
-#define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                   nHDONE3  0x0
-#define                     DONE3  0x2000     /* DMA3 Done */
-#define                    nDONE3  0x0
-#define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                   nHDONE4  0x0
-#define                     DONE4  0x20000    /* DMA4 Done */
-#define                    nDONE4  0x0
-#define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                   nHDONE5  0x0
-#define                     DONE5  0x200000   /* DMA5 Done */
-#define                    nDONE5  0x0
-#define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                   nHDONE6  0x0
-#define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    nDONE6  0x0
-#define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                   nHDONE7  0x0
-#define                     DONE7  0x20000000 /* DMA7 Done */
-#define                    nDONE7  0x0
-
-/* Bit masks for MXVR_INT_EN_0 */
-
-#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                   nNI2AEN  0x0
-#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   nNA2IEN  0x0
-#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                  nSBU2LEN  0x0
-#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                  nSBL2UEN  0x0
-#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    nPRUEN  0x0
-#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                   nMPRUEN  0x0
-#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    nDRUEN  0x0
-#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                   nMDRUEN  0x0
-#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                    nSBUEN  0x0
-#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    nATUEN  0x0
-#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                   nFCZ0EN  0x0
-#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                   nFCZ1EN  0x0
-#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                   nPERREN  0x0
-#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                   nMH2LEN  0x0
-#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                   nML2HEN  0x0
-#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    nWUPEN  0x0
-#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                   nFU2LEN  0x0
-#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                   nFL2UEN  0x0
-#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                   nBU2LEN  0x0
-#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   nBL2UEN  0x0
-#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                  nOBERREN  0x0
-#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                    nPFLEN  0x0
-#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    nSCZEN  0x0
-#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                   nFERREN  0x0
-#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                    nCMREN  0x0
-#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                  nCMROFEN  0x0
-#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nCMTSEN  0x0
-#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nCMTCEN  0x0
-#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                   nRWRCEN  0x0
-#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                    nBCZEN  0x0
-#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                  nBMERREN  0x0
-#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-#define                   nDERREN  0x0
-
-/* Bit masks for MXVR_INT_EN_1 */
-
-#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                 nHDONEEN0  0x0
-#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                  nDONEEN0  0x0
-#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                    nAPREN  0x0
-#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  nAPROFEN  0x0
-#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                 nHDONEEN1  0x0
-#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                  nDONEEN1  0x0
-#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                   nAPTSEN  0x0
-#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                   nAPTCEN  0x0
-#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                 nHDONEEN2  0x0
-#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                  nDONEEN2  0x0
-#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                  nAPRCEEN  0x0
-#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  nAPRPEEN  0x0
-#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                 nHDONEEN3  0x0
-#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  nDONEEN3  0x0
-#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                 nHDONEEN4  0x0
-#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  nDONEEN4  0x0
-#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                 nHDONEEN5  0x0
-#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  nDONEEN5  0x0
-#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                 nHDONEEN6  0x0
-#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  nDONEEN6  0x0
-#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                 nHDONEEN7  0x0
-#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-#define                  nDONEEN7  0x0
-
-/* Bit masks for MXVR_POSITION */
-
-#define                  POSITION  0x3f       /* Node Position */
-#define                    PVALID  0x8000     /* Node Position Valid */
-#define                   nPVALID  0x0
-
-/* Bit masks for MXVR_MAX_POSITION */
-
-#define                 MPOSITION  0x3f       /* Maximum Node Position */
-#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-#define                  nMPVALID  0x0
-
-/* Bit masks for MXVR_DELAY */
-
-#define                     DELAY  0x3f       /* Node Frame Delay */
-#define                    DVALID  0x8000     /* Node Frame Delay Valid */
-#define                   nDVALID  0x0
-
-/* Bit masks for MXVR_MAX_DELAY */
-
-#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
-#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-#define                  nMDVALID  0x0
-
-/* Bit masks for MXVR_LADDR */
-
-#define                     LADDR  0xffff     /* Logical Address */
-#define                    LVALID  0x80000000 /* Logical Address Valid */
-#define                   nLVALID  0x0
-
-/* Bit masks for MXVR_GADDR */
-
-#define                    GADDRL  0xff       /* Group Address Lower Byte */
-#define                    GVALID  0x8000     /* Group Address Valid */
-#define                   nGVALID  0x0
-
-/* Bit masks for MXVR_AADDR */
-
-#define                     AADDR  0xffff     /* Alternate Address */
-#define                    AVALID  0x80000000 /* Alternate Address Valid */
-#define                   nAVALID  0x0
-
-/* Bit masks for MXVR_ALLOC_0 */
-
-#define                       CL0  0x7f       /* Channel 0 Connection Label */
-#define                      CIU0  0x80       /* Channel 0 In Use */
-#define                     nCIU0  0x0
-#define                       CL1  0x7f00     /* Channel 0 Connection Label */
-#define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                     nCIU1  0x0
-#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
-#define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                     nCIU2  0x0
-#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
-#define                      CIU3  0x80000000 /* Channel 0 In Use */
-#define                     nCIU3  0x0
-
-/* Bit masks for MXVR_ALLOC_1 */
-
-#define                       CL4  0x7f       /* Channel 4 Connection Label */
-#define                      CIU4  0x80       /* Channel 4 In Use */
-#define                     nCIU4  0x0
-#define                       CL5  0x7f00     /* Channel 5 Connection Label */
-#define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                     nCIU5  0x0
-#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
-#define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                     nCIU6  0x0
-#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
-#define                      CIU7  0x80000000 /* Channel 7 In Use */
-#define                     nCIU7  0x0
-
-/* Bit masks for MXVR_ALLOC_2 */
-
-#define                       CL8  0x7f       /* Channel 8 Connection Label */
-#define                      CIU8  0x80       /* Channel 8 In Use */
-#define                     nCIU8  0x0
-#define                       CL9  0x7f00     /* Channel 9 Connection Label */
-#define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                     nCIU9  0x0
-#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
-#define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                    nCIU10  0x0
-#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
-#define                     CIU11  0x80000000 /* Channel 11 In Use */
-#define                    nCIU11  0x0
-
-/* Bit masks for MXVR_ALLOC_3 */
-
-#define                      CL12  0x7f       /* Channel 12 Connection Label */
-#define                     CIU12  0x80       /* Channel 12 In Use */
-#define                    nCIU12  0x0
-#define                      CL13  0x7f00     /* Channel 13 Connection Label */
-#define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                    nCIU13  0x0
-#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
-#define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                    nCIU14  0x0
-#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
-#define                     CIU15  0x80000000 /* Channel 15 In Use */
-#define                    nCIU15  0x0
-
-/* Bit masks for MXVR_ALLOC_4 */
-
-#define                      CL16  0x7f       /* Channel 16 Connection Label */
-#define                     CIU16  0x80       /* Channel 16 In Use */
-#define                    nCIU16  0x0
-#define                      CL17  0x7f00     /* Channel 17 Connection Label */
-#define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                    nCIU17  0x0
-#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
-#define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                    nCIU18  0x0
-#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
-#define                     CIU19  0x80000000 /* Channel 19 In Use */
-#define                    nCIU19  0x0
-
-/* Bit masks for MXVR_ALLOC_5 */
-
-#define                      CL20  0x7f       /* Channel 20 Connection Label */
-#define                     CIU20  0x80       /* Channel 20 In Use */
-#define                    nCIU20  0x0
-#define                      CL21  0x7f00     /* Channel 21 Connection Label */
-#define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                    nCIU21  0x0
-#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
-#define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                    nCIU22  0x0
-#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
-#define                     CIU23  0x80000000 /* Channel 23 In Use */
-#define                    nCIU23  0x0
-
-/* Bit masks for MXVR_ALLOC_6 */
-
-#define                      CL24  0x7f       /* Channel 24 Connection Label */
-#define                     CIU24  0x80       /* Channel 24 In Use */
-#define                    nCIU24  0x0
-#define                      CL25  0x7f00     /* Channel 25 Connection Label */
-#define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                    nCIU25  0x0
-#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
-#define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                    nCIU26  0x0
-#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
-#define                     CIU27  0x80000000 /* Channel 27 In Use */
-#define                    nCIU27  0x0
-
-/* Bit masks for MXVR_ALLOC_7 */
-
-#define                      CL28  0x7f       /* Channel 28 Connection Label */
-#define                     CIU28  0x80       /* Channel 28 In Use */
-#define                    nCIU28  0x0
-#define                      CL29  0x7f00     /* Channel 29 Connection Label */
-#define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                    nCIU29  0x0
-#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
-#define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                    nCIU30  0x0
-#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
-#define                     CIU31  0x80000000 /* Channel 31 In Use */
-#define                    nCIU31  0x0
-
-/* Bit masks for MXVR_ALLOC_8 */
-
-#define                      CL32  0x7f       /* Channel 32 Connection Label */
-#define                     CIU32  0x80       /* Channel 32 In Use */
-#define                    nCIU32  0x0
-#define                      CL33  0x7f00     /* Channel 33 Connection Label */
-#define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                    nCIU33  0x0
-#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
-#define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                    nCIU34  0x0
-#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
-#define                     CIU35  0x80000000 /* Channel 35 In Use */
-#define                    nCIU35  0x0
-
-/* Bit masks for MXVR_ALLOC_9 */
-
-#define                      CL36  0x7f       /* Channel 36 Connection Label */
-#define                     CIU36  0x80       /* Channel 36 In Use */
-#define                    nCIU36  0x0
-#define                      CL37  0x7f00     /* Channel 37 Connection Label */
-#define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                    nCIU37  0x0
-#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
-#define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                    nCIU38  0x0
-#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
-#define                     CIU39  0x80000000 /* Channel 39 In Use */
-#define                    nCIU39  0x0
-
-/* Bit masks for MXVR_ALLOC_10 */
-
-#define                      CL40  0x7f       /* Channel 40 Connection Label */
-#define                     CIU40  0x80       /* Channel 40 In Use */
-#define                    nCIU40  0x0
-#define                      CL41  0x7f00     /* Channel 41 Connection Label */
-#define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                    nCIU41  0x0
-#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
-#define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                    nCIU42  0x0
-#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
-#define                     CIU43  0x80000000 /* Channel 43 In Use */
-#define                    nCIU43  0x0
-
-/* Bit masks for MXVR_ALLOC_11 */
-
-#define                      CL44  0x7f       /* Channel 44 Connection Label */
-#define                     CIU44  0x80       /* Channel 44 In Use */
-#define                    nCIU44  0x0
-#define                      CL45  0x7f00     /* Channel 45 Connection Label */
-#define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                    nCIU45  0x0
-#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
-#define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                    nCIU46  0x0
-#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
-#define                     CIU47  0x80000000 /* Channel 47 In Use */
-#define                    nCIU47  0x0
-
-/* Bit masks for MXVR_ALLOC_12 */
-
-#define                      CL48  0x7f       /* Channel 48 Connection Label */
-#define                     CIU48  0x80       /* Channel 48 In Use */
-#define                    nCIU48  0x0
-#define                      CL49  0x7f00     /* Channel 49 Connection Label */
-#define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                    nCIU49  0x0
-#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
-#define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                    nCIU50  0x0
-#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
-#define                     CIU51  0x80000000 /* Channel 51 In Use */
-#define                    nCIU51  0x0
-
-/* Bit masks for MXVR_ALLOC_13 */
-
-#define                      CL52  0x7f       /* Channel 52 Connection Label */
-#define                     CIU52  0x80       /* Channel 52 In Use */
-#define                    nCIU52  0x0
-#define                      CL53  0x7f00     /* Channel 53 Connection Label */
-#define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                    nCIU53  0x0
-#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
-#define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                    nCIU54  0x0
-#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
-#define                     CIU55  0x80000000 /* Channel 55 In Use */
-#define                    nCIU55  0x0
-
-/* Bit masks for MXVR_ALLOC_14 */
-
-#define                      CL56  0x7f       /* Channel 56 Connection Label */
-#define                     CIU56  0x80       /* Channel 56 In Use */
-#define                    nCIU56  0x0
-#define                      CL57  0x7f00     /* Channel 57 Connection Label */
-#define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                    nCIU57  0x0
-#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
-#define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                    nCIU58  0x0
-#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
-#define                     CIU59  0x80000000 /* Channel 59 In Use */
-#define                    nCIU59  0x0
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-/* Bit masks for MXVR_DMAx_CONFIG */
-
-#define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                   nMDMAEN  0x0
-#define                        DD  0x2        /* DMA Channel Direction */
-#define                       nDD  0x0
-#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                nBY4SWAPEN  0x0
-#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
-#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                nBITSWAPEN  0x0
-#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                nBY2SWAPEN  0x0
-#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
-#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  nFIXEDPM  0x0
-#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
-#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
-#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
-
-/* Bit masks for MXVR_AP_CTL */
-
-#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  nSTARTAP  0x0
-#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                 nCANCELAP  0x0
-#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                  nRESETAP  0x0
-#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                   nAPRBE0  0x0
-#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-#define                   nAPRBE1  0x0
-
-/* Bit masks for MXVR_APRB_START_ADDR */
-
-#define           APRB_START_ADDR  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
-
-/* Bit masks for MXVR_APRB_CURR_ADDR */
-
-#define            APRB_CURR_ADDR  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
-
-/* Bit masks for MXVR_APTB_START_ADDR */
-
-#define           APTB_START_ADDR  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_APTB_CURR_ADDR */
-
-#define            APTB_CURR_ADDR  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_CM_CTL */
-
-#define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  nSTARTCM  0x0
-#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                 nCANCELCM  0x0
-#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                   nCMRBE0  0x0
-#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                   nCMRBE1  0x0
-#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                   nCMRBE2  0x0
-#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                   nCMRBE3  0x0
-#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                   nCMRBE4  0x0
-#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                   nCMRBE5  0x0
-#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                   nCMRBE6  0x0
-#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                   nCMRBE7  0x0
-#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                   nCMRBE8  0x0
-#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   nCMRBE9  0x0
-#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                  nCMRBE10  0x0
-#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                  nCMRBE11  0x0
-#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                  nCMRBE12  0x0
-#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                  nCMRBE13  0x0
-#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                  nCMRBE14  0x0
-#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-#define                  nCMRBE15  0x0
-
-/* Bit masks for MXVR_CMRB_START_ADDR */
-
-#define           CMRB_START_ADDR  0x1fffffe  /* Control Message Receive Buffer Start Address */
-
-/* Bit masks for MXVR_CMRB_CURR_ADDR */
-
-#define            CMRB_CURR_ADDR  0xffffffff /* Control Message Receive Buffer Current Address */
-
-/* Bit masks for MXVR_CMTB_START_ADDR */
-
-#define           CMTB_START_ADDR  0x1fffffe  /* Control Message Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_CMTB_CURR_ADDR */
-
-#define            CMTB_CURR_ADDR  0xffffffff /* Control Message Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_RRDB_START_ADDR */
-
-#define           RRDB_START_ADDR  0x1fffffe  /* Remote Read Buffer Start Address */
-
-/* Bit masks for MXVR_RRDB_CURR_ADDR */
-
-#define            RRDB_CURR_ADDR  0xffffffff /* Remote Read Buffer Current Address */
-
-/* Bit masks for MXVR_PAT_DATAx */
-
-#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
-#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
-#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
-#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
-
-/* Bit masks for MXVR_PAT_EN_0 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0
-
-/* Bit masks for MXVR_PAT_EN_1 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define             nMATCH_EN_0_0  0x0
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define             nMATCH_EN_0_1  0x0
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define             nMATCH_EN_0_2  0x0
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define             nMATCH_EN_0_3  0x0
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define             nMATCH_EN_0_4  0x0
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define             nMATCH_EN_0_5  0x0
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define             nMATCH_EN_0_6  0x0
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define             nMATCH_EN_0_7  0x0
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define             nMATCH_EN_1_0  0x0
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define             nMATCH_EN_1_1  0x0
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define             nMATCH_EN_1_2  0x0
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define             nMATCH_EN_1_3  0x0
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define             nMATCH_EN_1_4  0x0
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define             nMATCH_EN_1_5  0x0
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define             nMATCH_EN_1_6  0x0
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define             nMATCH_EN_1_7  0x0
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define             nMATCH_EN_2_0  0x0
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define             nMATCH_EN_2_1  0x0
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define             nMATCH_EN_2_2  0x0
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define             nMATCH_EN_2_3  0x0
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define             nMATCH_EN_2_4  0x0
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define             nMATCH_EN_2_5  0x0
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define             nMATCH_EN_2_6  0x0
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define             nMATCH_EN_2_7  0x0
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define             nMATCH_EN_3_0  0x0
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define             nMATCH_EN_3_1  0x0
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define             nMATCH_EN_3_2  0x0
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define             nMATCH_EN_3_3  0x0
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define             nMATCH_EN_3_4  0x0
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define             nMATCH_EN_3_5  0x0
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define             nMATCH_EN_3_6  0x0
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-#define             nMATCH_EN_3_7  0x0
-
-/* Bit masks for MXVR_FRAME_CNT_0 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_FRAME_CNT_1 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_ROUTING_0 */
-
-#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
-#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                 nMUTE_CH0  0x0
-#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
-#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                 nMUTE_CH1  0x0
-#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
-#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                 nMUTE_CH2  0x0
-#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
-#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-#define                 nMUTE_CH3  0x0
-
-/* Bit masks for MXVR_ROUTING_1 */
-
-#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
-#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                 nMUTE_CH4  0x0
-#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
-#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                 nMUTE_CH5  0x0
-#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
-#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                 nMUTE_CH6  0x0
-#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
-#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-#define                 nMUTE_CH7  0x0
-
-/* Bit masks for MXVR_ROUTING_2 */
-
-#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
-#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                 nMUTE_CH8  0x0
-#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
-#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                 nMUTE_CH9  0x0
-#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
-#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                nMUTE_CH10  0x0
-#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
-#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-#define                nMUTE_CH11  0x0
-
-/* Bit masks for MXVR_ROUTING_3 */
-
-#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
-#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                nMUTE_CH12  0x0
-#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
-#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                nMUTE_CH13  0x0
-#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
-#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                nMUTE_CH14  0x0
-#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
-#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-#define                nMUTE_CH15  0x0
-
-/* Bit masks for MXVR_ROUTING_4 */
-
-#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
-#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                nMUTE_CH16  0x0
-#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
-#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                nMUTE_CH17  0x0
-#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
-#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                nMUTE_CH18  0x0
-#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
-#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-#define                nMUTE_CH19  0x0
-
-/* Bit masks for MXVR_ROUTING_5 */
-
-#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
-#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                nMUTE_CH20  0x0
-#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
-#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                nMUTE_CH21  0x0
-#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
-#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                nMUTE_CH22  0x0
-#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
-#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-#define                nMUTE_CH23  0x0
-
-/* Bit masks for MXVR_ROUTING_6 */
-
-#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
-#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                nMUTE_CH24  0x0
-#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
-#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                nMUTE_CH25  0x0
-#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
-#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                nMUTE_CH26  0x0
-#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
-#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-#define                nMUTE_CH27  0x0
-
-/* Bit masks for MXVR_ROUTING_7 */
-
-#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
-#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                nMUTE_CH28  0x0
-#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
-#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                nMUTE_CH29  0x0
-#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
-#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                nMUTE_CH30  0x0
-#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
-#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-#define                nMUTE_CH31  0x0
-
-/* Bit masks for MXVR_ROUTING_8 */
-
-#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
-#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                nMUTE_CH32  0x0
-#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
-#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                nMUTE_CH33  0x0
-#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
-#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                nMUTE_CH34  0x0
-#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
-#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-#define                nMUTE_CH35  0x0
-
-/* Bit masks for MXVR_ROUTING_9 */
-
-#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
-#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                nMUTE_CH36  0x0
-#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
-#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                nMUTE_CH37  0x0
-#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
-#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                nMUTE_CH38  0x0
-#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
-#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-#define                nMUTE_CH39  0x0
-
-/* Bit masks for MXVR_ROUTING_10 */
-
-#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
-#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                nMUTE_CH40  0x0
-#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
-#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                nMUTE_CH41  0x0
-#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
-#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                nMUTE_CH42  0x0
-#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
-#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-#define                nMUTE_CH43  0x0
-
-/* Bit masks for MXVR_ROUTING_11 */
-
-#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
-#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                nMUTE_CH44  0x0
-#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
-#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                nMUTE_CH45  0x0
-#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
-#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                nMUTE_CH46  0x0
-#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
-#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-#define                nMUTE_CH47  0x0
-
-/* Bit masks for MXVR_ROUTING_12 */
-
-#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
-#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                nMUTE_CH48  0x0
-#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
-#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                nMUTE_CH49  0x0
-#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
-#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                nMUTE_CH50  0x0
-#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
-#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-#define                nMUTE_CH51  0x0
-
-/* Bit masks for MXVR_ROUTING_13 */
-
-#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
-#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                nMUTE_CH52  0x0
-#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
-#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                nMUTE_CH53  0x0
-#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
-#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                nMUTE_CH54  0x0
-#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
-#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-#define                nMUTE_CH55  0x0
-
-/* Bit masks for MXVR_ROUTING_14 */
-
-#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
-#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                nMUTE_CH56  0x0
-#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
-#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                nMUTE_CH57  0x0
-#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
-#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                nMUTE_CH58  0x0
-#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
-#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-#define                nMUTE_CH59  0x0
-
-/* Bit masks for MXVR_BLOCK_CNT */
-
-#define                      BCNT  0xffff     /* Block Count */
-
-/* Bit masks for MXVR_CLK_CTL */
-
-#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                 nMXTALCEN  0x0
-#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                 nMXTALFEN  0x0
-#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
-#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                 nCLKX3SEL  0x0
-#define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  nMMCLKEN  0x0
-#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
-#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
-#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  nMBCLKEN  0x0
-#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
-#define                     INVRX  0x800000   /* Invert Receive Data */
-#define                    nINVRX  0x0
-#define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    nMFSEN  0x0
-#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
-#define                    MFSSEL  0x60000000 /* Frame Sync Select */
-#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-#define                  nMFSSYNC  0x0
-
-/* Bit masks for MXVR_CDRPLL_CTL */
-
-#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                  nCDRSMEN  0x0
-#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                  nCDRRSTB  0x0
-#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                  nCDRSVCO  0x0
-#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                  nCDRMODE  0x0
-#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
-#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
-#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
-#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                 nCDRSHPEN  0x0
-#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_FMPLL_CTL */
-
-#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                   nFMSMEN  0x0
-#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                   nFMRSTB  0x0
-#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                   nFMSVCO  0x0
-#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
-#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
-#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_PIN_CTL */
-
-#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                 nMTXONBOD  0x0
-#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                  nMTXONBG  0x0
-#define                     MFSOE  0x10       /* MFS Output Enable */
-#define                    nMFSOE  0x0
-#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                 nMFSGPSEL  0x0
-#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-#define                 nMFSGPDAT  0x0
-
-/* Bit masks for MXVR_SCLK_CNT */
-
-#define                      SCNT  0xffff     /* System Clock Count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define                  nKPAD_EN  0x0
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define             nKPAD_IRQMODE  0x0        /* Interrupt Disabled */
-#define           KPAD_IRQMODE_SK  0x2        /* Single key (single row, single column) press interrupt enable */
-#define           KPAD_IRQMODE_MK  0x4        /* Single key press multiple key press interrupt enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-
-#ifdef _MISRA_RULES
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7u)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7u)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#else
-#define         SET_KPAD_ROWEN(x)  (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
-#define         SET_KPAD_COLEN(x)  (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-#ifdef _MISRA_RULES
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3Fu)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#else
-#define      SET_KPAD_PRESCALE(x)  ((x)&0x3F)   /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
-#endif /* MISRA_RULES */
-
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-#ifdef _MISRA_RULES
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFFu)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFFu)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#else
-#define    SET_KPAD_DBON_SCALE(x)  ((x)&0xFF)   /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
-#define  SET_KPAD_COLDRV_SCALE(x)  (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define                 nKPAD_IRQ  0x0
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-#define             nKPAD_PRESSED  0x0
-#define               KPAD_NO_KEY  0x0        /* No Keypress Status*/
-#define           KPAD_SINGLE_KEY  0x2        /* Single Keypress Status */
-#define            KPAD_MKSROWCOL  0x4        /* Multiple Keypress in the same row or column Status */
-#define            KPAD_MKMROWCOL  0x6        /* Multiple Keypress in the same multiple rows and multiple columns Status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-#define          nKPAD_SOFTEVAL_E  0x0
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                  nCMD_RSP  0x0
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                nCMD_L_RSP  0x0
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                nCMD_INT_E  0x0
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define               nCMD_PEND_E  0x0
-#define                     CMD_E  0x400      /* Command Enable */
-#define                    nCMD_E  0x0
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                nSD_CMD_OD  0x0
-#define                   ROD_CTL  0x80       /* Rod Control */
-#define                  nROD_CTL  0x0
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                    nCLK_E  0x0
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define                 nPWR_SV_E  0x0
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define            nCLKDIV_BYPASS  0x0
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-#define                 nWIDE_BUS  0x0
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                    nDTX_E  0x0
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  nDTX_DIR  0x0
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 nDTX_MODE  0x0
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define                nDTX_DMA_E  0x0
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define             nCMD_CRC_FAIL  0x0
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define             nDAT_CRC_FAIL  0x0
-#define               CMD_TIMEOUT  0x4        /* CMD Time Out */
-#define              nCMD_TIMEOUT  0x0
-#define               DAT_TIMEOUT  0x8        /* Data Time Out */
-#define              nDAT_TIMEOUT  0x0
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define              nTX_UNDERRUN  0x0
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define               nRX_OVERRUN  0x0
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define             nCMD_RESP_END  0x0
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                 nCMD_SENT  0x0
-#define                   DAT_END  0x100      /* Data End */
-#define                  nDAT_END  0x0
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define            nSTART_BIT_ERR  0x0
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define              nDAT_BLK_END  0x0
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                  nCMD_ACT  0x0
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                   nTX_ACT  0x0
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define                   nRX_ACT  0x0
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define             nTX_FIFO_STAT  0x0
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define             nRX_FIFO_STAT  0x0
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define             nTX_FIFO_FULL  0x0
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define             nRX_FIFO_FULL  0x0
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define             nTX_FIFO_ZERO  0x0
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define              nRX_DAT_ZERO  0x0
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               nTX_DAT_RDY  0x0
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-#define              nRX_FIFO_RDY  0x0
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define        nCMD_CRC_FAIL_STAT  0x0
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define        nDAT_CRC_FAIL_STAT  0x0
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define         nCMD_TIMEOUT_STAT  0x0
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define         nDAT_TIMEOUT_STAT  0x0
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define         nTX_UNDERRUN_STAT  0x0
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define          nRX_OVERRUN_STAT  0x0
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define        nCMD_RESP_END_STAT  0x0
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define            nCMD_SENT_STAT  0x0
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define             nDAT_END_STAT  0x0
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define       nSTART_BIT_ERR_STAT  0x0
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-#define         nDAT_BLK_END_STAT  0x0
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define        nCMD_CRC_FAIL_MASK  0x0
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define        nDAT_CRC_FAIL_MASK  0x0
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define         nCMD_TIMEOUT_MASK  0x0
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define         nDAT_TIMEOUT_MASK  0x0
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define         nTX_UNDERRUN_MASK  0x0
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define          nRX_OVERRUN_MASK  0x0
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define        nCMD_RESP_END_MASK  0x0
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define            nCMD_SENT_MASK  0x0
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define             nDAT_END_MASK  0x0
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define       nSTART_BIT_ERR_MASK  0x0
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define         nDAT_BLK_END_MASK  0x0
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define             nCMD_ACT_MASK  0x0
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define              nTX_ACT_MASK  0x0
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define              nRX_ACT_MASK  0x0
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define        nTX_FIFO_STAT_MASK  0x0
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define        nRX_FIFO_STAT_MASK  0x0
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define        nTX_FIFO_FULL_MASK  0x0
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define        nRX_FIFO_FULL_MASK  0x0
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define        nTX_FIFO_ZERO_MASK  0x0
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define         nRX_DAT_ZERO_MASK  0x0
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          nTX_DAT_RDY_MASK  0x0
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-#define         nRX_FIFO_RDY_MASK  0x0
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define             nSDIO_INT_DET  0x0
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-#define              nSD_CARD_DET  0x0
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                 nSDIO_MSK  0x0
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-#define                  nSCD_MSK  0x0
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                  nCLKS_EN  0x0
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                     nSD4E  0x0
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                      nMWE  0x0
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                   nSD_RST  0x0
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                nPUP_SDDAT  0x0
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define               nPUP_SDDAT3  0x0
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-#define                nPD_SDDAT3  0x0
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-#define                      nRWR  0x0
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define                nPIO_START  0x0
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define              nMULTI_START  0x0
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define              nULTRA_START  0x0
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                 nXFER_DIR  0x0
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                 nIORDY_EN  0x0
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define               nFIFO_FLUSH  0x0
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                 nSOFT_RST  0x0
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                  nDEV_RST  0x0
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               nTFRCNT_RST  0x0
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define              nEND_ON_TERM  0x0
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define              nPIO_USE_DMA  0x0
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define              nPIO_XFER_ON  0x0
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define            nMULTI_XFER_ON  0x0
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define            nULTRA_XFER_ON  0x0
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define       nATAPI_DEV_INT_MASK  0x0
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define            nPIO_DONE_MASK  0x0
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          nMULTI_DONE_MASK  0x0
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         nUDMAIN_DONE_MASK  0x0
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define        nUDMAOUT_DONE_MASK  0x0
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define      nHOST_TERM_XFER_MASK  0x0
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          nMULTI_TERM_MASK  0x0
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         nUDMAIN_TERM_MASK  0x0
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-#define        nUDMAOUT_TERM_MASK  0x0
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define            nATAPI_DEV_INT  0x0
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define             nPIO_DONE_INT  0x0
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           nMULTI_DONE_INT  0x0
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          nUDMAIN_DONE_INT  0x0
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define         nUDMAOUT_DONE_INT  0x0
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define       nHOST_TERM_XFER_INT  0x0
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           nMULTI_TERM_INT  0x0
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          nUDMAIN_TERM_INT  0x0
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-#define         nUDMAOUT_TERM_INT  0x0
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define               nATAPI_INTR  0x0
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define               nATAPI_DASP  0x0
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define               nATAPI_CS0N  0x0
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define               nATAPI_CS1N  0x0
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             nATAPI_DMAREQ  0x0
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define            nATAPI_DMAACKN  0x0
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define              nATAPI_DIOWN  0x0
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define              nATAPI_DIORN  0x0
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-#define              nATAPI_IORDY  0x0
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-#define          nATAPI_HOST_TERM  0x0
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                   nTIMEN8  0x0
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   nTIMEN9  0x0
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-#define                  nTIMEN10  0x0
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                  nTIMDIS8  0x0
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  nTIMDIS9  0x0
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-#define                 nTIMDIS10  0x0
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                   nTIMIL8  0x0
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   nTIMIL9  0x0
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                  nTIMIL10  0x0
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                nTOVF_ERR8  0x0
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                nTOVF_ERR9  0x0
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define               nTOVF_ERR10  0x0
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                    nTRUN8  0x0
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    nTRUN9  0x0
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-#define                   nTRUN10  0x0
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* ************************ */
-/*   MXVR Address Offsets   */
-/* ************************ */
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-/* **************** */
-/*   MXVR Macros    */
-/* **************** */
-
-/* MXVR_CONFIG Macros */
-
-#ifdef _MISRA_RULES
-#define SET_MSB(x)       ( ( (x) & 0xFu  ) << 9)
-#else
-#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
-#endif /* _MISRA_RULES */
-
-/* MXVR_INT_STAT_1 Macros */
-
-#define DONEX(x)         (0x00000002 << (4 * (x)))
-#define HDONEX(x)        (0x00000001 << (4 * (x)))
-
-/* MXVR_INT_EN_1 Macros */
-
-#define DONEENX(x)       (0x00000002 << (4 * (x)))
-#define HDONEENX(x)      (0x00000001 << (4 * (x)))
-
-/* MXVR_CDRPLL_CTL Macros */
-
-#ifdef _MISRA_RULES
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3Fu ) << 16)
-#else
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
-#endif /* _MISRA_RULES */
-
-/* MXVR_FMPLL_CTL Macros */
-
-#ifdef _MISRA_RULES
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFFu ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFFu ) << 24)
-#else
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
-#endif /* _MISRA_RULES */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF549_H */
diff --git a/libgloss/bfin/include/defBF549M.h b/libgloss/bfin/include/defBF549M.h
deleted file mode 100644
index 306345d0e..000000000
--- a/libgloss/bfin/include/defBF549M.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF549M.h
-**
-** Copyright (C) 2008-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This file just maps directly onto the def file for BF549, unless
-** anything is required to change for the M derivative.
-**
-**/
-
-#ifndef _DEF_BF549M_H
-#define _DEF_BF549M_H
-
-#include <defBF549.h>
-
-#endif /* _DEF_BF549M_H */
diff --git a/libgloss/bfin/include/defBF54x_base.h b/libgloss/bfin/include/defBF54x_base.h
deleted file mode 100644
index 62d11d6fd..000000000
--- a/libgloss/bfin/include/defBF54x_base.h
+++ /dev/null
@@ -1,5701 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF54x_base.h
-**
-** Copyright (C) 2006-2009 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF54x peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_1:"ADI Header allows long identifiers")
-#pragma diag(suppress:misra_rule_19_4:"ADI header allows any substitution text")
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function macros")
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define                          PLL_CTL  0xffc00000   /* PLL Control Register */
-#define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
-#define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
-#define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
-#define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define                           CHIPID  0xffc00014
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define                            SWRST  0xffc00100   /* Software Reset Register */
-#define                            SYSCR  0xffc00104   /* System Configuration register */
-
-/* SIC Registers */
-
-#define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
-#define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
-#define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
-#define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
-#define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
-#define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
-#define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
-#define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
-#define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
-#define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
-#define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
-#define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
-#define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
-#define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
-#define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
-#define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
-#define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
-#define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
-#define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
-#define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
-#define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
-#define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
-#define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define                         RTC_STAT  0xffc00300   /* RTC Status Register */
-#define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
-#define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
-#define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
-#define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
-#define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
-#define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
-#define                       UART0_GCTL  0xffc00408   /* Global Control Register */
-#define                        UART0_LCR  0xffc0040c   /* Line Control Register */
-#define                        UART0_MCR  0xffc00410   /* Modem Control Register */
-#define                        UART0_LSR  0xffc00414   /* Line Status Register */
-#define                        UART0_MSR  0xffc00418   /* Modem Status Register */
-#define                        UART0_SCR  0xffc0041c   /* Scratch Register */
-#define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
-#define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
-#define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
-#define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
-#define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
-#define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
-#define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
-#define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
-#define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
-#define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
-#define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
-#define                   TWI0_SLAVE_CTL  0xffc00708   /* TWI Slave Mode Control Register */
-#define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
-#define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
-#define                  TWI0_MASTER_CTL  0xffc00714   /* TWI Master Mode Control Register */
-#define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
-#define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
-#define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
-#define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
-#define                    TWI0_FIFO_CTL  0xffc00728   /* TWI FIFO Control Register */
-#define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
-#define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
-#define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
-#define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
-#define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
-#define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
-#define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
-#define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
-#define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
-#define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
-#define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
-#define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
-#define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
-#define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
-#define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
-#define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
-#define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
-#define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
-#define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
-#define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
-#define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
-#define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
-#define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
-#define                     EBIU_AMBCTL0  0xffc00a04   /* Asynchronous Memory Bank Control Register */
-#define                     EBIU_AMBCTL1  0xffc00a08   /* Asynchronous Memory Bank Control Register */
-#define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
-#define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
-#define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
-#define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
-#define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
-#define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
-#define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
-#define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
-#define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
-#define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
-#define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
-#define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
-#define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
-#define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
-#define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
-#define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
-#define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
-#define                     EBIU_DDRBRC7  0xffc00a7c   /* DDR Bank7 Read Count Register */
-#define                     EBIU_DDRBWC0  0xffc00a80   /* DDR Bank0 Write Count Register */
-#define                     EBIU_DDRBWC1  0xffc00a84   /* DDR Bank1 Write Count Register */
-#define                     EBIU_DDRBWC2  0xffc00a88   /* DDR Bank2 Write Count Register */
-#define                     EBIU_DDRBWC3  0xffc00a8c   /* DDR Bank3 Write Count Register */
-#define                     EBIU_DDRBWC4  0xffc00a90   /* DDR Bank4 Write Count Register */
-#define                     EBIU_DDRBWC5  0xffc00a94   /* DDR Bank5 Write Count Register */
-#define                     EBIU_DDRBWC6  0xffc00a98   /* DDR Bank6 Write Count Register */
-#define                     EBIU_DDRBWC7  0xffc00a9c   /* DDR Bank7 Write Count Register */
-#define                     EBIU_DDRACCT  0xffc00aa0   /* DDR Activation Count Register */
-#define                     EBIU_DDRTACT  0xffc00aa8   /* DDR Turn Around Count Register */
-#define                     EBIU_DDRARCT  0xffc00aac   /* DDR Auto-refresh Count Register */
-#define                      EBIU_DDRGC0  0xffc00ab0   /* DDR Grant Count 0 Register */
-#define                      EBIU_DDRGC1  0xffc00ab4   /* DDR Grant Count 1 Register */
-#define                      EBIU_DDRGC2  0xffc00ab8   /* DDR Grant Count 2 Register */
-#define                      EBIU_DDRGC3  0xffc00abc   /* DDR Grant Count 3 Register */
-#define                     EBIU_DDRMCEN  0xffc00ac0   /* DDR Metrics Counter Enable Register */
-#define                     EBIU_DDRMCCL  0xffc00ac4   /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
-#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define               DMA0_NEXT_DESC_PTR  0xffc00c00   /* DMA Channel 0 Next Descriptor Pointer Register */
-#define                  DMA0_START_ADDR  0xffc00c04   /* DMA Channel 0 Start Address Register */
-#define                      DMA0_CONFIG  0xffc00c08   /* DMA Channel 0 Configuration Register */
-#define                     DMA0_X_COUNT  0xffc00c10   /* DMA Channel 0 X Count Register */
-#define                    DMA0_X_MODIFY  0xffc00c14   /* DMA Channel 0 X Modify Register */
-#define                     DMA0_Y_COUNT  0xffc00c18   /* DMA Channel 0 Y Count Register */
-#define                    DMA0_Y_MODIFY  0xffc00c1c   /* DMA Channel 0 Y Modify Register */
-#define               DMA0_CURR_DESC_PTR  0xffc00c20   /* DMA Channel 0 Current Descriptor Pointer Register */
-#define                   DMA0_CURR_ADDR  0xffc00c24   /* DMA Channel 0 Current Address Register */
-#define                  DMA0_IRQ_STATUS  0xffc00c28   /* DMA Channel 0 Interrupt/Status Register */
-#define              DMA0_PERIPHERAL_MAP  0xffc00c2c   /* DMA Channel 0 Peripheral Map Register */
-#define                DMA0_CURR_X_COUNT  0xffc00c30   /* DMA Channel 0 Current X Count Register */
-#define                DMA0_CURR_Y_COUNT  0xffc00c38   /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define               DMA1_NEXT_DESC_PTR  0xffc00c40   /* DMA Channel 1 Next Descriptor Pointer Register */
-#define                  DMA1_START_ADDR  0xffc00c44   /* DMA Channel 1 Start Address Register */
-#define                      DMA1_CONFIG  0xffc00c48   /* DMA Channel 1 Configuration Register */
-#define                     DMA1_X_COUNT  0xffc00c50   /* DMA Channel 1 X Count Register */
-#define                    DMA1_X_MODIFY  0xffc00c54   /* DMA Channel 1 X Modify Register */
-#define                     DMA1_Y_COUNT  0xffc00c58   /* DMA Channel 1 Y Count Register */
-#define                    DMA1_Y_MODIFY  0xffc00c5c   /* DMA Channel 1 Y Modify Register */
-#define               DMA1_CURR_DESC_PTR  0xffc00c60   /* DMA Channel 1 Current Descriptor Pointer Register */
-#define                   DMA1_CURR_ADDR  0xffc00c64   /* DMA Channel 1 Current Address Register */
-#define                  DMA1_IRQ_STATUS  0xffc00c68   /* DMA Channel 1 Interrupt/Status Register */
-#define              DMA1_PERIPHERAL_MAP  0xffc00c6c   /* DMA Channel 1 Peripheral Map Register */
-#define                DMA1_CURR_X_COUNT  0xffc00c70   /* DMA Channel 1 Current X Count Register */
-#define                DMA1_CURR_Y_COUNT  0xffc00c78   /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define               DMA2_NEXT_DESC_PTR  0xffc00c80   /* DMA Channel 2 Next Descriptor Pointer Register */
-#define                  DMA2_START_ADDR  0xffc00c84   /* DMA Channel 2 Start Address Register */
-#define                      DMA2_CONFIG  0xffc00c88   /* DMA Channel 2 Configuration Register */
-#define                     DMA2_X_COUNT  0xffc00c90   /* DMA Channel 2 X Count Register */
-#define                    DMA2_X_MODIFY  0xffc00c94   /* DMA Channel 2 X Modify Register */
-#define                     DMA2_Y_COUNT  0xffc00c98   /* DMA Channel 2 Y Count Register */
-#define                    DMA2_Y_MODIFY  0xffc00c9c   /* DMA Channel 2 Y Modify Register */
-#define               DMA2_CURR_DESC_PTR  0xffc00ca0   /* DMA Channel 2 Current Descriptor Pointer Register */
-#define                   DMA2_CURR_ADDR  0xffc00ca4   /* DMA Channel 2 Current Address Register */
-#define                  DMA2_IRQ_STATUS  0xffc00ca8   /* DMA Channel 2 Interrupt/Status Register */
-#define              DMA2_PERIPHERAL_MAP  0xffc00cac   /* DMA Channel 2 Peripheral Map Register */
-#define                DMA2_CURR_X_COUNT  0xffc00cb0   /* DMA Channel 2 Current X Count Register */
-#define                DMA2_CURR_Y_COUNT  0xffc00cb8   /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define               DMA3_NEXT_DESC_PTR  0xffc00cc0   /* DMA Channel 3 Next Descriptor Pointer Register */
-#define                  DMA3_START_ADDR  0xffc00cc4   /* DMA Channel 3 Start Address Register */
-#define                      DMA3_CONFIG  0xffc00cc8   /* DMA Channel 3 Configuration Register */
-#define                     DMA3_X_COUNT  0xffc00cd0   /* DMA Channel 3 X Count Register */
-#define                    DMA3_X_MODIFY  0xffc00cd4   /* DMA Channel 3 X Modify Register */
-#define                     DMA3_Y_COUNT  0xffc00cd8   /* DMA Channel 3 Y Count Register */
-#define                    DMA3_Y_MODIFY  0xffc00cdc   /* DMA Channel 3 Y Modify Register */
-#define               DMA3_CURR_DESC_PTR  0xffc00ce0   /* DMA Channel 3 Current Descriptor Pointer Register */
-#define                   DMA3_CURR_ADDR  0xffc00ce4   /* DMA Channel 3 Current Address Register */
-#define                  DMA3_IRQ_STATUS  0xffc00ce8   /* DMA Channel 3 Interrupt/Status Register */
-#define              DMA3_PERIPHERAL_MAP  0xffc00cec   /* DMA Channel 3 Peripheral Map Register */
-#define                DMA3_CURR_X_COUNT  0xffc00cf0   /* DMA Channel 3 Current X Count Register */
-#define                DMA3_CURR_Y_COUNT  0xffc00cf8   /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define               DMA4_NEXT_DESC_PTR  0xffc00d00   /* DMA Channel 4 Next Descriptor Pointer Register */
-#define                  DMA4_START_ADDR  0xffc00d04   /* DMA Channel 4 Start Address Register */
-#define                      DMA4_CONFIG  0xffc00d08   /* DMA Channel 4 Configuration Register */
-#define                     DMA4_X_COUNT  0xffc00d10   /* DMA Channel 4 X Count Register */
-#define                    DMA4_X_MODIFY  0xffc00d14   /* DMA Channel 4 X Modify Register */
-#define                     DMA4_Y_COUNT  0xffc00d18   /* DMA Channel 4 Y Count Register */
-#define                    DMA4_Y_MODIFY  0xffc00d1c   /* DMA Channel 4 Y Modify Register */
-#define               DMA4_CURR_DESC_PTR  0xffc00d20   /* DMA Channel 4 Current Descriptor Pointer Register */
-#define                   DMA4_CURR_ADDR  0xffc00d24   /* DMA Channel 4 Current Address Register */
-#define                  DMA4_IRQ_STATUS  0xffc00d28   /* DMA Channel 4 Interrupt/Status Register */
-#define              DMA4_PERIPHERAL_MAP  0xffc00d2c   /* DMA Channel 4 Peripheral Map Register */
-#define                DMA4_CURR_X_COUNT  0xffc00d30   /* DMA Channel 4 Current X Count Register */
-#define                DMA4_CURR_Y_COUNT  0xffc00d38   /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define               DMA5_NEXT_DESC_PTR  0xffc00d40   /* DMA Channel 5 Next Descriptor Pointer Register */
-#define                  DMA5_START_ADDR  0xffc00d44   /* DMA Channel 5 Start Address Register */
-#define                      DMA5_CONFIG  0xffc00d48   /* DMA Channel 5 Configuration Register */
-#define                     DMA5_X_COUNT  0xffc00d50   /* DMA Channel 5 X Count Register */
-#define                    DMA5_X_MODIFY  0xffc00d54   /* DMA Channel 5 X Modify Register */
-#define                     DMA5_Y_COUNT  0xffc00d58   /* DMA Channel 5 Y Count Register */
-#define                    DMA5_Y_MODIFY  0xffc00d5c   /* DMA Channel 5 Y Modify Register */
-#define               DMA5_CURR_DESC_PTR  0xffc00d60   /* DMA Channel 5 Current Descriptor Pointer Register */
-#define                   DMA5_CURR_ADDR  0xffc00d64   /* DMA Channel 5 Current Address Register */
-#define                  DMA5_IRQ_STATUS  0xffc00d68   /* DMA Channel 5 Interrupt/Status Register */
-#define              DMA5_PERIPHERAL_MAP  0xffc00d6c   /* DMA Channel 5 Peripheral Map Register */
-#define                DMA5_CURR_X_COUNT  0xffc00d70   /* DMA Channel 5 Current X Count Register */
-#define                DMA5_CURR_Y_COUNT  0xffc00d78   /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define               DMA6_NEXT_DESC_PTR  0xffc00d80   /* DMA Channel 6 Next Descriptor Pointer Register */
-#define                  DMA6_START_ADDR  0xffc00d84   /* DMA Channel 6 Start Address Register */
-#define                      DMA6_CONFIG  0xffc00d88   /* DMA Channel 6 Configuration Register */
-#define                     DMA6_X_COUNT  0xffc00d90   /* DMA Channel 6 X Count Register */
-#define                    DMA6_X_MODIFY  0xffc00d94   /* DMA Channel 6 X Modify Register */
-#define                     DMA6_Y_COUNT  0xffc00d98   /* DMA Channel 6 Y Count Register */
-#define                    DMA6_Y_MODIFY  0xffc00d9c   /* DMA Channel 6 Y Modify Register */
-#define               DMA6_CURR_DESC_PTR  0xffc00da0   /* DMA Channel 6 Current Descriptor Pointer Register */
-#define                   DMA6_CURR_ADDR  0xffc00da4   /* DMA Channel 6 Current Address Register */
-#define                  DMA6_IRQ_STATUS  0xffc00da8   /* DMA Channel 6 Interrupt/Status Register */
-#define              DMA6_PERIPHERAL_MAP  0xffc00dac   /* DMA Channel 6 Peripheral Map Register */
-#define                DMA6_CURR_X_COUNT  0xffc00db0   /* DMA Channel 6 Current X Count Register */
-#define                DMA6_CURR_Y_COUNT  0xffc00db8   /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define               DMA7_NEXT_DESC_PTR  0xffc00dc0   /* DMA Channel 7 Next Descriptor Pointer Register */
-#define                  DMA7_START_ADDR  0xffc00dc4   /* DMA Channel 7 Start Address Register */
-#define                      DMA7_CONFIG  0xffc00dc8   /* DMA Channel 7 Configuration Register */
-#define                     DMA7_X_COUNT  0xffc00dd0   /* DMA Channel 7 X Count Register */
-#define                    DMA7_X_MODIFY  0xffc00dd4   /* DMA Channel 7 X Modify Register */
-#define                     DMA7_Y_COUNT  0xffc00dd8   /* DMA Channel 7 Y Count Register */
-#define                    DMA7_Y_MODIFY  0xffc00ddc   /* DMA Channel 7 Y Modify Register */
-#define               DMA7_CURR_DESC_PTR  0xffc00de0   /* DMA Channel 7 Current Descriptor Pointer Register */
-#define                   DMA7_CURR_ADDR  0xffc00de4   /* DMA Channel 7 Current Address Register */
-#define                  DMA7_IRQ_STATUS  0xffc00de8   /* DMA Channel 7 Interrupt/Status Register */
-#define              DMA7_PERIPHERAL_MAP  0xffc00dec   /* DMA Channel 7 Peripheral Map Register */
-#define                DMA7_CURR_X_COUNT  0xffc00df0   /* DMA Channel 7 Current X Count Register */
-#define                DMA7_CURR_Y_COUNT  0xffc00df8   /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define               DMA8_NEXT_DESC_PTR  0xffc00e00   /* DMA Channel 8 Next Descriptor Pointer Register */
-#define                  DMA8_START_ADDR  0xffc00e04   /* DMA Channel 8 Start Address Register */
-#define                      DMA8_CONFIG  0xffc00e08   /* DMA Channel 8 Configuration Register */
-#define                     DMA8_X_COUNT  0xffc00e10   /* DMA Channel 8 X Count Register */
-#define                    DMA8_X_MODIFY  0xffc00e14   /* DMA Channel 8 X Modify Register */
-#define                     DMA8_Y_COUNT  0xffc00e18   /* DMA Channel 8 Y Count Register */
-#define                    DMA8_Y_MODIFY  0xffc00e1c   /* DMA Channel 8 Y Modify Register */
-#define               DMA8_CURR_DESC_PTR  0xffc00e20   /* DMA Channel 8 Current Descriptor Pointer Register */
-#define                   DMA8_CURR_ADDR  0xffc00e24   /* DMA Channel 8 Current Address Register */
-#define                  DMA8_IRQ_STATUS  0xffc00e28   /* DMA Channel 8 Interrupt/Status Register */
-#define              DMA8_PERIPHERAL_MAP  0xffc00e2c   /* DMA Channel 8 Peripheral Map Register */
-#define                DMA8_CURR_X_COUNT  0xffc00e30   /* DMA Channel 8 Current X Count Register */
-#define                DMA8_CURR_Y_COUNT  0xffc00e38   /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define               DMA9_NEXT_DESC_PTR  0xffc00e40   /* DMA Channel 9 Next Descriptor Pointer Register */
-#define                  DMA9_START_ADDR  0xffc00e44   /* DMA Channel 9 Start Address Register */
-#define                      DMA9_CONFIG  0xffc00e48   /* DMA Channel 9 Configuration Register */
-#define                     DMA9_X_COUNT  0xffc00e50   /* DMA Channel 9 X Count Register */
-#define                    DMA9_X_MODIFY  0xffc00e54   /* DMA Channel 9 X Modify Register */
-#define                     DMA9_Y_COUNT  0xffc00e58   /* DMA Channel 9 Y Count Register */
-#define                    DMA9_Y_MODIFY  0xffc00e5c   /* DMA Channel 9 Y Modify Register */
-#define               DMA9_CURR_DESC_PTR  0xffc00e60   /* DMA Channel 9 Current Descriptor Pointer Register */
-#define                   DMA9_CURR_ADDR  0xffc00e64   /* DMA Channel 9 Current Address Register */
-#define                  DMA9_IRQ_STATUS  0xffc00e68   /* DMA Channel 9 Interrupt/Status Register */
-#define              DMA9_PERIPHERAL_MAP  0xffc00e6c   /* DMA Channel 9 Peripheral Map Register */
-#define                DMA9_CURR_X_COUNT  0xffc00e70   /* DMA Channel 9 Current X Count Register */
-#define                DMA9_CURR_Y_COUNT  0xffc00e78   /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define              DMA10_NEXT_DESC_PTR  0xffc00e80   /* DMA Channel 10 Next Descriptor Pointer Register */
-#define                 DMA10_START_ADDR  0xffc00e84   /* DMA Channel 10 Start Address Register */
-#define                     DMA10_CONFIG  0xffc00e88   /* DMA Channel 10 Configuration Register */
-#define                    DMA10_X_COUNT  0xffc00e90   /* DMA Channel 10 X Count Register */
-#define                   DMA10_X_MODIFY  0xffc00e94   /* DMA Channel 10 X Modify Register */
-#define                    DMA10_Y_COUNT  0xffc00e98   /* DMA Channel 10 Y Count Register */
-#define                   DMA10_Y_MODIFY  0xffc00e9c   /* DMA Channel 10 Y Modify Register */
-#define              DMA10_CURR_DESC_PTR  0xffc00ea0   /* DMA Channel 10 Current Descriptor Pointer Register */
-#define                  DMA10_CURR_ADDR  0xffc00ea4   /* DMA Channel 10 Current Address Register */
-#define                 DMA10_IRQ_STATUS  0xffc00ea8   /* DMA Channel 10 Interrupt/Status Register */
-#define             DMA10_PERIPHERAL_MAP  0xffc00eac   /* DMA Channel 10 Peripheral Map Register */
-#define               DMA10_CURR_X_COUNT  0xffc00eb0   /* DMA Channel 10 Current X Count Register */
-#define               DMA10_CURR_Y_COUNT  0xffc00eb8   /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define              DMA11_NEXT_DESC_PTR  0xffc00ec0   /* DMA Channel 11 Next Descriptor Pointer Register */
-#define                 DMA11_START_ADDR  0xffc00ec4   /* DMA Channel 11 Start Address Register */
-#define                     DMA11_CONFIG  0xffc00ec8   /* DMA Channel 11 Configuration Register */
-#define                    DMA11_X_COUNT  0xffc00ed0   /* DMA Channel 11 X Count Register */
-#define                   DMA11_X_MODIFY  0xffc00ed4   /* DMA Channel 11 X Modify Register */
-#define                    DMA11_Y_COUNT  0xffc00ed8   /* DMA Channel 11 Y Count Register */
-#define                   DMA11_Y_MODIFY  0xffc00edc   /* DMA Channel 11 Y Modify Register */
-#define              DMA11_CURR_DESC_PTR  0xffc00ee0   /* DMA Channel 11 Current Descriptor Pointer Register */
-#define                  DMA11_CURR_ADDR  0xffc00ee4   /* DMA Channel 11 Current Address Register */
-#define                 DMA11_IRQ_STATUS  0xffc00ee8   /* DMA Channel 11 Interrupt/Status Register */
-#define             DMA11_PERIPHERAL_MAP  0xffc00eec   /* DMA Channel 11 Peripheral Map Register */
-#define               DMA11_CURR_X_COUNT  0xffc00ef0   /* DMA Channel 11 Current X Count Register */
-#define               DMA11_CURR_Y_COUNT  0xffc00ef8   /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define            MDMA_D0_NEXT_DESC_PTR  0xffc00f00   /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define               MDMA_D0_START_ADDR  0xffc00f04   /* Memory DMA Stream 0 Destination Start Address Register */
-#define                   MDMA_D0_CONFIG  0xffc00f08   /* Memory DMA Stream 0 Destination Configuration Register */
-#define                  MDMA_D0_X_COUNT  0xffc00f10   /* Memory DMA Stream 0 Destination X Count Register */
-#define                 MDMA_D0_X_MODIFY  0xffc00f14   /* Memory DMA Stream 0 Destination X Modify Register */
-#define                  MDMA_D0_Y_COUNT  0xffc00f18   /* Memory DMA Stream 0 Destination Y Count Register */
-#define                 MDMA_D0_Y_MODIFY  0xffc00f1c   /* Memory DMA Stream 0 Destination Y Modify Register */
-#define            MDMA_D0_CURR_DESC_PTR  0xffc00f20   /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define                MDMA_D0_CURR_ADDR  0xffc00f24   /* Memory DMA Stream 0 Destination Current Address Register */
-#define               MDMA_D0_IRQ_STATUS  0xffc00f28   /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define           MDMA_D0_PERIPHERAL_MAP  0xffc00f2c   /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define             MDMA_D0_CURR_X_COUNT  0xffc00f30   /* Memory DMA Stream 0 Destination Current X Count Register */
-#define             MDMA_D0_CURR_Y_COUNT  0xffc00f38   /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define            MDMA_S0_NEXT_DESC_PTR  0xffc00f40   /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define               MDMA_S0_START_ADDR  0xffc00f44   /* Memory DMA Stream 0 Source Start Address Register */
-#define                   MDMA_S0_CONFIG  0xffc00f48   /* Memory DMA Stream 0 Source Configuration Register */
-#define                  MDMA_S0_X_COUNT  0xffc00f50   /* Memory DMA Stream 0 Source X Count Register */
-#define                 MDMA_S0_X_MODIFY  0xffc00f54   /* Memory DMA Stream 0 Source X Modify Register */
-#define                  MDMA_S0_Y_COUNT  0xffc00f58   /* Memory DMA Stream 0 Source Y Count Register */
-#define                 MDMA_S0_Y_MODIFY  0xffc00f5c   /* Memory DMA Stream 0 Source Y Modify Register */
-#define            MDMA_S0_CURR_DESC_PTR  0xffc00f60   /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define                MDMA_S0_CURR_ADDR  0xffc00f64   /* Memory DMA Stream 0 Source Current Address Register */
-#define               MDMA_S0_IRQ_STATUS  0xffc00f68   /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define           MDMA_S0_PERIPHERAL_MAP  0xffc00f6c   /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define             MDMA_S0_CURR_X_COUNT  0xffc00f70   /* Memory DMA Stream 0 Source Current X Count Register */
-#define             MDMA_S0_CURR_Y_COUNT  0xffc00f78   /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define            MDMA_D1_NEXT_DESC_PTR  0xffc00f80   /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define               MDMA_D1_START_ADDR  0xffc00f84   /* Memory DMA Stream 1 Destination Start Address Register */
-#define                   MDMA_D1_CONFIG  0xffc00f88   /* Memory DMA Stream 1 Destination Configuration Register */
-#define                  MDMA_D1_X_COUNT  0xffc00f90   /* Memory DMA Stream 1 Destination X Count Register */
-#define                 MDMA_D1_X_MODIFY  0xffc00f94   /* Memory DMA Stream 1 Destination X Modify Register */
-#define                  MDMA_D1_Y_COUNT  0xffc00f98   /* Memory DMA Stream 1 Destination Y Count Register */
-#define                 MDMA_D1_Y_MODIFY  0xffc00f9c   /* Memory DMA Stream 1 Destination Y Modify Register */
-#define            MDMA_D1_CURR_DESC_PTR  0xffc00fa0   /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define                MDMA_D1_CURR_ADDR  0xffc00fa4   /* Memory DMA Stream 1 Destination Current Address Register */
-#define               MDMA_D1_IRQ_STATUS  0xffc00fa8   /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define           MDMA_D1_PERIPHERAL_MAP  0xffc00fac   /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define             MDMA_D1_CURR_X_COUNT  0xffc00fb0   /* Memory DMA Stream 1 Destination Current X Count Register */
-#define             MDMA_D1_CURR_Y_COUNT  0xffc00fb8   /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define            MDMA_S1_NEXT_DESC_PTR  0xffc00fc0   /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define               MDMA_S1_START_ADDR  0xffc00fc4   /* Memory DMA Stream 1 Source Start Address Register */
-#define                   MDMA_S1_CONFIG  0xffc00fc8   /* Memory DMA Stream 1 Source Configuration Register */
-#define                  MDMA_S1_X_COUNT  0xffc00fd0   /* Memory DMA Stream 1 Source X Count Register */
-#define                 MDMA_S1_X_MODIFY  0xffc00fd4   /* Memory DMA Stream 1 Source X Modify Register */
-#define                  MDMA_S1_Y_COUNT  0xffc00fd8   /* Memory DMA Stream 1 Source Y Count Register */
-#define                 MDMA_S1_Y_MODIFY  0xffc00fdc   /* Memory DMA Stream 1 Source Y Modify Register */
-#define            MDMA_S1_CURR_DESC_PTR  0xffc00fe0   /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define                MDMA_S1_CURR_ADDR  0xffc00fe4   /* Memory DMA Stream 1 Source Current Address Register */
-#define               MDMA_S1_IRQ_STATUS  0xffc00fe8   /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define           MDMA_S1_PERIPHERAL_MAP  0xffc00fec   /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define             MDMA_S1_CURR_X_COUNT  0xffc00ff0   /* Memory DMA Stream 1 Source Current X Count Register */
-#define             MDMA_S1_CURR_Y_COUNT  0xffc00ff8   /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define                     EPPI1_STATUS  0xffc01300   /* EPPI1 Status Register */
-#define                     EPPI1_HCOUNT  0xffc01304   /* EPPI1 Horizontal Transfer Count Register */
-#define                     EPPI1_HDELAY  0xffc01308   /* EPPI1 Horizontal Delay Count Register */
-#define                     EPPI1_VCOUNT  0xffc0130c   /* EPPI1 Vertical Transfer Count Register */
-#define                     EPPI1_VDELAY  0xffc01310   /* EPPI1 Vertical Delay Count Register */
-#define                      EPPI1_FRAME  0xffc01314   /* EPPI1 Lines per Frame Register */
-#define                       EPPI1_LINE  0xffc01318   /* EPPI1 Samples per Line Register */
-#define                     EPPI1_CLKDIV  0xffc0131c   /* EPPI1 Clock Divide Register */
-#define                    EPPI1_CONTROL  0xffc01320   /* EPPI1 Control Register */
-#define                   EPPI1_FS1W_HBL  0xffc01324   /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI1_FS1P_AVPL  0xffc01328   /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define                   EPPI1_FS2W_LVB  0xffc0132c   /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define                  EPPI1_FS2P_LAVF  0xffc01330   /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define                       EPPI1_CLIP  0xffc01334   /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define                   PINT0_MASK_SET  0xffc01400   /* Pin Interrupt 0 Mask Set Register */
-#define                 PINT0_MASK_CLEAR  0xffc01404   /* Pin Interrupt 0 Mask Clear Register */
-#define                    PINT0_REQUEST  0xffc01408   /* Pin Interrupt 0 Interrupt Request Register */
-#define                     PINT0_ASSIGN  0xffc0140c   /* Pin Interrupt 0 Port Assign Register */
-#define                   PINT0_EDGE_SET  0xffc01410   /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define                 PINT0_EDGE_CLEAR  0xffc01414   /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define                 PINT0_INVERT_SET  0xffc01418   /* Pin Interrupt 0 Inversion Set Register */
-#define               PINT0_INVERT_CLEAR  0xffc0141c   /* Pin Interrupt 0 Inversion Clear Register */
-#define                   PINT0_PINSTATE  0xffc01420   /* Pin Interrupt 0 Pin Status Register */
-#define                      PINT0_LATCH  0xffc01424   /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define                   PINT1_MASK_SET  0xffc01430   /* Pin Interrupt 1 Mask Set Register */
-#define                 PINT1_MASK_CLEAR  0xffc01434   /* Pin Interrupt 1 Mask Clear Register */
-#define                    PINT1_REQUEST  0xffc01438   /* Pin Interrupt 1 Interrupt Request Register */
-#define                     PINT1_ASSIGN  0xffc0143c   /* Pin Interrupt 1 Port Assign Register */
-#define                   PINT1_EDGE_SET  0xffc01440   /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define                 PINT1_EDGE_CLEAR  0xffc01444   /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define                 PINT1_INVERT_SET  0xffc01448   /* Pin Interrupt 1 Inversion Set Register */
-#define               PINT1_INVERT_CLEAR  0xffc0144c   /* Pin Interrupt 1 Inversion Clear Register */
-#define                   PINT1_PINSTATE  0xffc01450   /* Pin Interrupt 1 Pin Status Register */
-#define                      PINT1_LATCH  0xffc01454   /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define                   PINT2_MASK_SET  0xffc01460   /* Pin Interrupt 2 Mask Set Register */
-#define                 PINT2_MASK_CLEAR  0xffc01464   /* Pin Interrupt 2 Mask Clear Register */
-#define                    PINT2_REQUEST  0xffc01468   /* Pin Interrupt 2 Interrupt Request Register */
-#define                     PINT2_ASSIGN  0xffc0146c   /* Pin Interrupt 2 Port Assign Register */
-#define                   PINT2_EDGE_SET  0xffc01470   /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define                 PINT2_EDGE_CLEAR  0xffc01474   /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define                 PINT2_INVERT_SET  0xffc01478   /* Pin Interrupt 2 Inversion Set Register */
-#define               PINT2_INVERT_CLEAR  0xffc0147c   /* Pin Interrupt 2 Inversion Clear Register */
-#define                   PINT2_PINSTATE  0xffc01480   /* Pin Interrupt 2 Pin Status Register */
-#define                      PINT2_LATCH  0xffc01484   /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define                   PINT3_MASK_SET  0xffc01490   /* Pin Interrupt 3 Mask Set Register */
-#define                 PINT3_MASK_CLEAR  0xffc01494   /* Pin Interrupt 3 Mask Clear Register */
-#define                    PINT3_REQUEST  0xffc01498   /* Pin Interrupt 3 Interrupt Request Register */
-#define                     PINT3_ASSIGN  0xffc0149c   /* Pin Interrupt 3 Port Assign Register */
-#define                   PINT3_EDGE_SET  0xffc014a0   /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define                 PINT3_EDGE_CLEAR  0xffc014a4   /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define                 PINT3_INVERT_SET  0xffc014a8   /* Pin Interrupt 3 Inversion Set Register */
-#define               PINT3_INVERT_CLEAR  0xffc014ac   /* Pin Interrupt 3 Inversion Clear Register */
-#define                   PINT3_PINSTATE  0xffc014b0   /* Pin Interrupt 3 Pin Status Register */
-#define                      PINT3_LATCH  0xffc014b4   /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define                        PORTA_FER  0xffc014c0   /* Function Enable Register */
-#define                            PORTA  0xffc014c4   /* GPIO Data Register */
-#define                        PORTA_SET  0xffc014c8   /* GPIO Data Set Register */
-#define                      PORTA_CLEAR  0xffc014cc   /* GPIO Data Clear Register */
-#define                    PORTA_DIR_SET  0xffc014d0   /* GPIO Direction Set Register */
-#define                  PORTA_DIR_CLEAR  0xffc014d4   /* GPIO Direction Clear Register */
-#define                       PORTA_INEN  0xffc014d8   /* GPIO Input Enable Register */
-#define                        PORTA_MUX  0xffc014dc   /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define                        PORTB_FER  0xffc014e0   /* Function Enable Register */
-#define                            PORTB  0xffc014e4   /* GPIO Data Register */
-#define                        PORTB_SET  0xffc014e8   /* GPIO Data Set Register */
-#define                      PORTB_CLEAR  0xffc014ec   /* GPIO Data Clear Register */
-#define                    PORTB_DIR_SET  0xffc014f0   /* GPIO Direction Set Register */
-#define                  PORTB_DIR_CLEAR  0xffc014f4   /* GPIO Direction Clear Register */
-#define                       PORTB_INEN  0xffc014f8   /* GPIO Input Enable Register */
-#define                        PORTB_MUX  0xffc014fc   /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define                        PORTC_FER  0xffc01500   /* Function Enable Register */
-#define                            PORTC  0xffc01504   /* GPIO Data Register */
-#define                        PORTC_SET  0xffc01508   /* GPIO Data Set Register */
-#define                      PORTC_CLEAR  0xffc0150c   /* GPIO Data Clear Register */
-#define                    PORTC_DIR_SET  0xffc01510   /* GPIO Direction Set Register */
-#define                  PORTC_DIR_CLEAR  0xffc01514   /* GPIO Direction Clear Register */
-#define                       PORTC_INEN  0xffc01518   /* GPIO Input Enable Register */
-#define                        PORTC_MUX  0xffc0151c   /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define                        PORTD_FER  0xffc01520   /* Function Enable Register */
-#define                            PORTD  0xffc01524   /* GPIO Data Register */
-#define                        PORTD_SET  0xffc01528   /* GPIO Data Set Register */
-#define                      PORTD_CLEAR  0xffc0152c   /* GPIO Data Clear Register */
-#define                    PORTD_DIR_SET  0xffc01530   /* GPIO Direction Set Register */
-#define                  PORTD_DIR_CLEAR  0xffc01534   /* GPIO Direction Clear Register */
-#define                       PORTD_INEN  0xffc01538   /* GPIO Input Enable Register */
-#define                        PORTD_MUX  0xffc0153c   /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define                        PORTE_FER  0xffc01540   /* Function Enable Register */
-#define                            PORTE  0xffc01544   /* GPIO Data Register */
-#define                        PORTE_SET  0xffc01548   /* GPIO Data Set Register */
-#define                      PORTE_CLEAR  0xffc0154c   /* GPIO Data Clear Register */
-#define                    PORTE_DIR_SET  0xffc01550   /* GPIO Direction Set Register */
-#define                  PORTE_DIR_CLEAR  0xffc01554   /* GPIO Direction Clear Register */
-#define                       PORTE_INEN  0xffc01558   /* GPIO Input Enable Register */
-#define                        PORTE_MUX  0xffc0155c   /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define                        PORTF_FER  0xffc01560   /* Function Enable Register */
-#define                            PORTF  0xffc01564   /* GPIO Data Register */
-#define                        PORTF_SET  0xffc01568   /* GPIO Data Set Register */
-#define                      PORTF_CLEAR  0xffc0156c   /* GPIO Data Clear Register */
-#define                    PORTF_DIR_SET  0xffc01570   /* GPIO Direction Set Register */
-#define                  PORTF_DIR_CLEAR  0xffc01574   /* GPIO Direction Clear Register */
-#define                       PORTF_INEN  0xffc01578   /* GPIO Input Enable Register */
-#define                        PORTF_MUX  0xffc0157c   /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define                        PORTG_FER  0xffc01580   /* Function Enable Register */
-#define                            PORTG  0xffc01584   /* GPIO Data Register */
-#define                        PORTG_SET  0xffc01588   /* GPIO Data Set Register */
-#define                      PORTG_CLEAR  0xffc0158c   /* GPIO Data Clear Register */
-#define                    PORTG_DIR_SET  0xffc01590   /* GPIO Direction Set Register */
-#define                  PORTG_DIR_CLEAR  0xffc01594   /* GPIO Direction Clear Register */
-#define                       PORTG_INEN  0xffc01598   /* GPIO Input Enable Register */
-#define                        PORTG_MUX  0xffc0159c   /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define                        PORTH_FER  0xffc015a0   /* Function Enable Register */
-#define                            PORTH  0xffc015a4   /* GPIO Data Register */
-#define                        PORTH_SET  0xffc015a8   /* GPIO Data Set Register */
-#define                      PORTH_CLEAR  0xffc015ac   /* GPIO Data Clear Register */
-#define                    PORTH_DIR_SET  0xffc015b0   /* GPIO Direction Set Register */
-#define                  PORTH_DIR_CLEAR  0xffc015b4   /* GPIO Direction Clear Register */
-#define                       PORTH_INEN  0xffc015b8   /* GPIO Input Enable Register */
-#define                        PORTH_MUX  0xffc015bc   /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define                        PORTI_FER  0xffc015c0   /* Function Enable Register */
-#define                            PORTI  0xffc015c4   /* GPIO Data Register */
-#define                        PORTI_SET  0xffc015c8   /* GPIO Data Set Register */
-#define                      PORTI_CLEAR  0xffc015cc   /* GPIO Data Clear Register */
-#define                    PORTI_DIR_SET  0xffc015d0   /* GPIO Direction Set Register */
-#define                  PORTI_DIR_CLEAR  0xffc015d4   /* GPIO Direction Clear Register */
-#define                       PORTI_INEN  0xffc015d8   /* GPIO Input Enable Register */
-#define                        PORTI_MUX  0xffc015dc   /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define                        PORTJ_FER  0xffc015e0   /* Function Enable Register */
-#define                            PORTJ  0xffc015e4   /* GPIO Data Register */
-#define                        PORTJ_SET  0xffc015e8   /* GPIO Data Set Register */
-#define                      PORTJ_CLEAR  0xffc015ec   /* GPIO Data Clear Register */
-#define                    PORTJ_DIR_SET  0xffc015f0   /* GPIO Direction Set Register */
-#define                  PORTJ_DIR_CLEAR  0xffc015f4   /* GPIO Direction Clear Register */
-#define                       PORTJ_INEN  0xffc015f8   /* GPIO Input Enable Register */
-#define                        PORTJ_MUX  0xffc015fc   /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define                    TIMER0_CONFIG  0xffc01600   /* Timer 0 Configuration Register */
-#define                   TIMER0_COUNTER  0xffc01604   /* Timer 0 Counter Register */
-#define                    TIMER0_PERIOD  0xffc01608   /* Timer 0 Period Register */
-#define                     TIMER0_WIDTH  0xffc0160c   /* Timer 0 Width Register */
-#define                    TIMER1_CONFIG  0xffc01610   /* Timer 1 Configuration Register */
-#define                   TIMER1_COUNTER  0xffc01614   /* Timer 1 Counter Register */
-#define                    TIMER1_PERIOD  0xffc01618   /* Timer 1 Period Register */
-#define                     TIMER1_WIDTH  0xffc0161c   /* Timer 1 Width Register */
-#define                    TIMER2_CONFIG  0xffc01620   /* Timer 2 Configuration Register */
-#define                   TIMER2_COUNTER  0xffc01624   /* Timer 2 Counter Register */
-#define                    TIMER2_PERIOD  0xffc01628   /* Timer 2 Period Register */
-#define                     TIMER2_WIDTH  0xffc0162c   /* Timer 2 Width Register */
-#define                    TIMER3_CONFIG  0xffc01630   /* Timer 3 Configuration Register */
-#define                   TIMER3_COUNTER  0xffc01634   /* Timer 3 Counter Register */
-#define                    TIMER3_PERIOD  0xffc01638   /* Timer 3 Period Register */
-#define                     TIMER3_WIDTH  0xffc0163c   /* Timer 3 Width Register */
-#define                    TIMER4_CONFIG  0xffc01640   /* Timer 4 Configuration Register */
-#define                   TIMER4_COUNTER  0xffc01644   /* Timer 4 Counter Register */
-#define                    TIMER4_PERIOD  0xffc01648   /* Timer 4 Period Register */
-#define                     TIMER4_WIDTH  0xffc0164c   /* Timer 4 Width Register */
-#define                    TIMER5_CONFIG  0xffc01650   /* Timer 5 Configuration Register */
-#define                   TIMER5_COUNTER  0xffc01654   /* Timer 5 Counter Register */
-#define                    TIMER5_PERIOD  0xffc01658   /* Timer 5 Period Register */
-#define                     TIMER5_WIDTH  0xffc0165c   /* Timer 5 Width Register */
-#define                    TIMER6_CONFIG  0xffc01660   /* Timer 6 Configuration Register */
-#define                   TIMER6_COUNTER  0xffc01664   /* Timer 6 Counter Register */
-#define                    TIMER6_PERIOD  0xffc01668   /* Timer 6 Period Register */
-#define                     TIMER6_WIDTH  0xffc0166c   /* Timer 6 Width Register */
-#define                    TIMER7_CONFIG  0xffc01670   /* Timer 7 Configuration Register */
-#define                   TIMER7_COUNTER  0xffc01674   /* Timer 7 Counter Register */
-#define                    TIMER7_PERIOD  0xffc01678   /* Timer 7 Period Register */
-#define                     TIMER7_WIDTH  0xffc0167c   /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define                    TIMER_ENABLE0  0xffc01680   /* Timer Group of 8 Enable Register */
-#define                   TIMER_DISABLE0  0xffc01684   /* Timer Group of 8 Disable Register */
-#define                    TIMER_STATUS0  0xffc01688   /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
-#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define              DMA12_NEXT_DESC_PTR  0xffc01c00   /* DMA Channel 12 Next Descriptor Pointer Register */
-#define                 DMA12_START_ADDR  0xffc01c04   /* DMA Channel 12 Start Address Register */
-#define                     DMA12_CONFIG  0xffc01c08   /* DMA Channel 12 Configuration Register */
-#define                    DMA12_X_COUNT  0xffc01c10   /* DMA Channel 12 X Count Register */
-#define                   DMA12_X_MODIFY  0xffc01c14   /* DMA Channel 12 X Modify Register */
-#define                    DMA12_Y_COUNT  0xffc01c18   /* DMA Channel 12 Y Count Register */
-#define                   DMA12_Y_MODIFY  0xffc01c1c   /* DMA Channel 12 Y Modify Register */
-#define              DMA12_CURR_DESC_PTR  0xffc01c20   /* DMA Channel 12 Current Descriptor Pointer Register */
-#define                  DMA12_CURR_ADDR  0xffc01c24   /* DMA Channel 12 Current Address Register */
-#define                 DMA12_IRQ_STATUS  0xffc01c28   /* DMA Channel 12 Interrupt/Status Register */
-#define             DMA12_PERIPHERAL_MAP  0xffc01c2c   /* DMA Channel 12 Peripheral Map Register */
-#define               DMA12_CURR_X_COUNT  0xffc01c30   /* DMA Channel 12 Current X Count Register */
-#define               DMA12_CURR_Y_COUNT  0xffc01c38   /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define              DMA13_NEXT_DESC_PTR  0xffc01c40   /* DMA Channel 13 Next Descriptor Pointer Register */
-#define                 DMA13_START_ADDR  0xffc01c44   /* DMA Channel 13 Start Address Register */
-#define                     DMA13_CONFIG  0xffc01c48   /* DMA Channel 13 Configuration Register */
-#define                    DMA13_X_COUNT  0xffc01c50   /* DMA Channel 13 X Count Register */
-#define                   DMA13_X_MODIFY  0xffc01c54   /* DMA Channel 13 X Modify Register */
-#define                    DMA13_Y_COUNT  0xffc01c58   /* DMA Channel 13 Y Count Register */
-#define                   DMA13_Y_MODIFY  0xffc01c5c   /* DMA Channel 13 Y Modify Register */
-#define              DMA13_CURR_DESC_PTR  0xffc01c60   /* DMA Channel 13 Current Descriptor Pointer Register */
-#define                  DMA13_CURR_ADDR  0xffc01c64   /* DMA Channel 13 Current Address Register */
-#define                 DMA13_IRQ_STATUS  0xffc01c68   /* DMA Channel 13 Interrupt/Status Register */
-#define             DMA13_PERIPHERAL_MAP  0xffc01c6c   /* DMA Channel 13 Peripheral Map Register */
-#define               DMA13_CURR_X_COUNT  0xffc01c70   /* DMA Channel 13 Current X Count Register */
-#define               DMA13_CURR_Y_COUNT  0xffc01c78   /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define              DMA14_NEXT_DESC_PTR  0xffc01c80   /* DMA Channel 14 Next Descriptor Pointer Register */
-#define                 DMA14_START_ADDR  0xffc01c84   /* DMA Channel 14 Start Address Register */
-#define                     DMA14_CONFIG  0xffc01c88   /* DMA Channel 14 Configuration Register */
-#define                    DMA14_X_COUNT  0xffc01c90   /* DMA Channel 14 X Count Register */
-#define                   DMA14_X_MODIFY  0xffc01c94   /* DMA Channel 14 X Modify Register */
-#define                    DMA14_Y_COUNT  0xffc01c98   /* DMA Channel 14 Y Count Register */
-#define                   DMA14_Y_MODIFY  0xffc01c9c   /* DMA Channel 14 Y Modify Register */
-#define              DMA14_CURR_DESC_PTR  0xffc01ca0   /* DMA Channel 14 Current Descriptor Pointer Register */
-#define                  DMA14_CURR_ADDR  0xffc01ca4   /* DMA Channel 14 Current Address Register */
-#define                 DMA14_IRQ_STATUS  0xffc01ca8   /* DMA Channel 14 Interrupt/Status Register */
-#define             DMA14_PERIPHERAL_MAP  0xffc01cac   /* DMA Channel 14 Peripheral Map Register */
-#define               DMA14_CURR_X_COUNT  0xffc01cb0   /* DMA Channel 14 Current X Count Register */
-#define               DMA14_CURR_Y_COUNT  0xffc01cb8   /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define              DMA15_NEXT_DESC_PTR  0xffc01cc0   /* DMA Channel 15 Next Descriptor Pointer Register */
-#define                 DMA15_START_ADDR  0xffc01cc4   /* DMA Channel 15 Start Address Register */
-#define                     DMA15_CONFIG  0xffc01cc8   /* DMA Channel 15 Configuration Register */
-#define                    DMA15_X_COUNT  0xffc01cd0   /* DMA Channel 15 X Count Register */
-#define                   DMA15_X_MODIFY  0xffc01cd4   /* DMA Channel 15 X Modify Register */
-#define                    DMA15_Y_COUNT  0xffc01cd8   /* DMA Channel 15 Y Count Register */
-#define                   DMA15_Y_MODIFY  0xffc01cdc   /* DMA Channel 15 Y Modify Register */
-#define              DMA15_CURR_DESC_PTR  0xffc01ce0   /* DMA Channel 15 Current Descriptor Pointer Register */
-#define                  DMA15_CURR_ADDR  0xffc01ce4   /* DMA Channel 15 Current Address Register */
-#define                 DMA15_IRQ_STATUS  0xffc01ce8   /* DMA Channel 15 Interrupt/Status Register */
-#define             DMA15_PERIPHERAL_MAP  0xffc01cec   /* DMA Channel 15 Peripheral Map Register */
-#define               DMA15_CURR_X_COUNT  0xffc01cf0   /* DMA Channel 15 Current X Count Register */
-#define               DMA15_CURR_Y_COUNT  0xffc01cf8   /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define              DMA16_NEXT_DESC_PTR  0xffc01d00   /* DMA Channel 16 Next Descriptor Pointer Register */
-#define                 DMA16_START_ADDR  0xffc01d04   /* DMA Channel 16 Start Address Register */
-#define                     DMA16_CONFIG  0xffc01d08   /* DMA Channel 16 Configuration Register */
-#define                    DMA16_X_COUNT  0xffc01d10   /* DMA Channel 16 X Count Register */
-#define                   DMA16_X_MODIFY  0xffc01d14   /* DMA Channel 16 X Modify Register */
-#define                    DMA16_Y_COUNT  0xffc01d18   /* DMA Channel 16 Y Count Register */
-#define                   DMA16_Y_MODIFY  0xffc01d1c   /* DMA Channel 16 Y Modify Register */
-#define              DMA16_CURR_DESC_PTR  0xffc01d20   /* DMA Channel 16 Current Descriptor Pointer Register */
-#define                  DMA16_CURR_ADDR  0xffc01d24   /* DMA Channel 16 Current Address Register */
-#define                 DMA16_IRQ_STATUS  0xffc01d28   /* DMA Channel 16 Interrupt/Status Register */
-#define             DMA16_PERIPHERAL_MAP  0xffc01d2c   /* DMA Channel 16 Peripheral Map Register */
-#define               DMA16_CURR_X_COUNT  0xffc01d30   /* DMA Channel 16 Current X Count Register */
-#define               DMA16_CURR_Y_COUNT  0xffc01d38   /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define              DMA17_NEXT_DESC_PTR  0xffc01d40   /* DMA Channel 17 Next Descriptor Pointer Register */
-#define                 DMA17_START_ADDR  0xffc01d44   /* DMA Channel 17 Start Address Register */
-#define                     DMA17_CONFIG  0xffc01d48   /* DMA Channel 17 Configuration Register */
-#define                    DMA17_X_COUNT  0xffc01d50   /* DMA Channel 17 X Count Register */
-#define                   DMA17_X_MODIFY  0xffc01d54   /* DMA Channel 17 X Modify Register */
-#define                    DMA17_Y_COUNT  0xffc01d58   /* DMA Channel 17 Y Count Register */
-#define                   DMA17_Y_MODIFY  0xffc01d5c   /* DMA Channel 17 Y Modify Register */
-#define              DMA17_CURR_DESC_PTR  0xffc01d60   /* DMA Channel 17 Current Descriptor Pointer Register */
-#define                  DMA17_CURR_ADDR  0xffc01d64   /* DMA Channel 17 Current Address Register */
-#define                 DMA17_IRQ_STATUS  0xffc01d68   /* DMA Channel 17 Interrupt/Status Register */
-#define             DMA17_PERIPHERAL_MAP  0xffc01d6c   /* DMA Channel 17 Peripheral Map Register */
-#define               DMA17_CURR_X_COUNT  0xffc01d70   /* DMA Channel 17 Current X Count Register */
-#define               DMA17_CURR_Y_COUNT  0xffc01d78   /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define              DMA18_NEXT_DESC_PTR  0xffc01d80   /* DMA Channel 18 Next Descriptor Pointer Register */
-#define                 DMA18_START_ADDR  0xffc01d84   /* DMA Channel 18 Start Address Register */
-#define                     DMA18_CONFIG  0xffc01d88   /* DMA Channel 18 Configuration Register */
-#define                    DMA18_X_COUNT  0xffc01d90   /* DMA Channel 18 X Count Register */
-#define                   DMA18_X_MODIFY  0xffc01d94   /* DMA Channel 18 X Modify Register */
-#define                    DMA18_Y_COUNT  0xffc01d98   /* DMA Channel 18 Y Count Register */
-#define                   DMA18_Y_MODIFY  0xffc01d9c   /* DMA Channel 18 Y Modify Register */
-#define              DMA18_CURR_DESC_PTR  0xffc01da0   /* DMA Channel 18 Current Descriptor Pointer Register */
-#define                  DMA18_CURR_ADDR  0xffc01da4   /* DMA Channel 18 Current Address Register */
-#define                 DMA18_IRQ_STATUS  0xffc01da8   /* DMA Channel 18 Interrupt/Status Register */
-#define             DMA18_PERIPHERAL_MAP  0xffc01dac   /* DMA Channel 18 Peripheral Map Register */
-#define               DMA18_CURR_X_COUNT  0xffc01db0   /* DMA Channel 18 Current X Count Register */
-#define               DMA18_CURR_Y_COUNT  0xffc01db8   /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define              DMA19_NEXT_DESC_PTR  0xffc01dc0   /* DMA Channel 19 Next Descriptor Pointer Register */
-#define                 DMA19_START_ADDR  0xffc01dc4   /* DMA Channel 19 Start Address Register */
-#define                     DMA19_CONFIG  0xffc01dc8   /* DMA Channel 19 Configuration Register */
-#define                    DMA19_X_COUNT  0xffc01dd0   /* DMA Channel 19 X Count Register */
-#define                   DMA19_X_MODIFY  0xffc01dd4   /* DMA Channel 19 X Modify Register */
-#define                    DMA19_Y_COUNT  0xffc01dd8   /* DMA Channel 19 Y Count Register */
-#define                   DMA19_Y_MODIFY  0xffc01ddc   /* DMA Channel 19 Y Modify Register */
-#define              DMA19_CURR_DESC_PTR  0xffc01de0   /* DMA Channel 19 Current Descriptor Pointer Register */
-#define                  DMA19_CURR_ADDR  0xffc01de4   /* DMA Channel 19 Current Address Register */
-#define                 DMA19_IRQ_STATUS  0xffc01de8   /* DMA Channel 19 Interrupt/Status Register */
-#define             DMA19_PERIPHERAL_MAP  0xffc01dec   /* DMA Channel 19 Peripheral Map Register */
-#define               DMA19_CURR_X_COUNT  0xffc01df0   /* DMA Channel 19 Current X Count Register */
-#define               DMA19_CURR_Y_COUNT  0xffc01df8   /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define              DMA20_NEXT_DESC_PTR  0xffc01e00   /* DMA Channel 20 Next Descriptor Pointer Register */
-#define                 DMA20_START_ADDR  0xffc01e04   /* DMA Channel 20 Start Address Register */
-#define                     DMA20_CONFIG  0xffc01e08   /* DMA Channel 20 Configuration Register */
-#define                    DMA20_X_COUNT  0xffc01e10   /* DMA Channel 20 X Count Register */
-#define                   DMA20_X_MODIFY  0xffc01e14   /* DMA Channel 20 X Modify Register */
-#define                    DMA20_Y_COUNT  0xffc01e18   /* DMA Channel 20 Y Count Register */
-#define                   DMA20_Y_MODIFY  0xffc01e1c   /* DMA Channel 20 Y Modify Register */
-#define              DMA20_CURR_DESC_PTR  0xffc01e20   /* DMA Channel 20 Current Descriptor Pointer Register */
-#define                  DMA20_CURR_ADDR  0xffc01e24   /* DMA Channel 20 Current Address Register */
-#define                 DMA20_IRQ_STATUS  0xffc01e28   /* DMA Channel 20 Interrupt/Status Register */
-#define             DMA20_PERIPHERAL_MAP  0xffc01e2c   /* DMA Channel 20 Peripheral Map Register */
-#define               DMA20_CURR_X_COUNT  0xffc01e30   /* DMA Channel 20 Current X Count Register */
-#define               DMA20_CURR_Y_COUNT  0xffc01e38   /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define              DMA21_NEXT_DESC_PTR  0xffc01e40   /* DMA Channel 21 Next Descriptor Pointer Register */
-#define                 DMA21_START_ADDR  0xffc01e44   /* DMA Channel 21 Start Address Register */
-#define                     DMA21_CONFIG  0xffc01e48   /* DMA Channel 21 Configuration Register */
-#define                    DMA21_X_COUNT  0xffc01e50   /* DMA Channel 21 X Count Register */
-#define                   DMA21_X_MODIFY  0xffc01e54   /* DMA Channel 21 X Modify Register */
-#define                    DMA21_Y_COUNT  0xffc01e58   /* DMA Channel 21 Y Count Register */
-#define                   DMA21_Y_MODIFY  0xffc01e5c   /* DMA Channel 21 Y Modify Register */
-#define              DMA21_CURR_DESC_PTR  0xffc01e60   /* DMA Channel 21 Current Descriptor Pointer Register */
-#define                  DMA21_CURR_ADDR  0xffc01e64   /* DMA Channel 21 Current Address Register */
-#define                 DMA21_IRQ_STATUS  0xffc01e68   /* DMA Channel 21 Interrupt/Status Register */
-#define             DMA21_PERIPHERAL_MAP  0xffc01e6c   /* DMA Channel 21 Peripheral Map Register */
-#define               DMA21_CURR_X_COUNT  0xffc01e70   /* DMA Channel 21 Current X Count Register */
-#define               DMA21_CURR_Y_COUNT  0xffc01e78   /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define              DMA22_NEXT_DESC_PTR  0xffc01e80   /* DMA Channel 22 Next Descriptor Pointer Register */
-#define                 DMA22_START_ADDR  0xffc01e84   /* DMA Channel 22 Start Address Register */
-#define                     DMA22_CONFIG  0xffc01e88   /* DMA Channel 22 Configuration Register */
-#define                    DMA22_X_COUNT  0xffc01e90   /* DMA Channel 22 X Count Register */
-#define                   DMA22_X_MODIFY  0xffc01e94   /* DMA Channel 22 X Modify Register */
-#define                    DMA22_Y_COUNT  0xffc01e98   /* DMA Channel 22 Y Count Register */
-#define                   DMA22_Y_MODIFY  0xffc01e9c   /* DMA Channel 22 Y Modify Register */
-#define              DMA22_CURR_DESC_PTR  0xffc01ea0   /* DMA Channel 22 Current Descriptor Pointer Register */
-#define                  DMA22_CURR_ADDR  0xffc01ea4   /* DMA Channel 22 Current Address Register */
-#define                 DMA22_IRQ_STATUS  0xffc01ea8   /* DMA Channel 22 Interrupt/Status Register */
-#define             DMA22_PERIPHERAL_MAP  0xffc01eac   /* DMA Channel 22 Peripheral Map Register */
-#define               DMA22_CURR_X_COUNT  0xffc01eb0   /* DMA Channel 22 Current X Count Register */
-#define               DMA22_CURR_Y_COUNT  0xffc01eb8   /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define              DMA23_NEXT_DESC_PTR  0xffc01ec0   /* DMA Channel 23 Next Descriptor Pointer Register */
-#define                 DMA23_START_ADDR  0xffc01ec4   /* DMA Channel 23 Start Address Register */
-#define                     DMA23_CONFIG  0xffc01ec8   /* DMA Channel 23 Configuration Register */
-#define                    DMA23_X_COUNT  0xffc01ed0   /* DMA Channel 23 X Count Register */
-#define                   DMA23_X_MODIFY  0xffc01ed4   /* DMA Channel 23 X Modify Register */
-#define                    DMA23_Y_COUNT  0xffc01ed8   /* DMA Channel 23 Y Count Register */
-#define                   DMA23_Y_MODIFY  0xffc01edc   /* DMA Channel 23 Y Modify Register */
-#define              DMA23_CURR_DESC_PTR  0xffc01ee0   /* DMA Channel 23 Current Descriptor Pointer Register */
-#define                  DMA23_CURR_ADDR  0xffc01ee4   /* DMA Channel 23 Current Address Register */
-#define                 DMA23_IRQ_STATUS  0xffc01ee8   /* DMA Channel 23 Interrupt/Status Register */
-#define             DMA23_PERIPHERAL_MAP  0xffc01eec   /* DMA Channel 23 Peripheral Map Register */
-#define               DMA23_CURR_X_COUNT  0xffc01ef0   /* DMA Channel 23 Current X Count Register */
-#define               DMA23_CURR_Y_COUNT  0xffc01ef8   /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define            MDMA_D2_NEXT_DESC_PTR  0xffc01f00   /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define               MDMA_D2_START_ADDR  0xffc01f04   /* Memory DMA Stream 2 Destination Start Address Register */
-#define                   MDMA_D2_CONFIG  0xffc01f08   /* Memory DMA Stream 2 Destination Configuration Register */
-#define                  MDMA_D2_X_COUNT  0xffc01f10   /* Memory DMA Stream 2 Destination X Count Register */
-#define                 MDMA_D2_X_MODIFY  0xffc01f14   /* Memory DMA Stream 2 Destination X Modify Register */
-#define                  MDMA_D2_Y_COUNT  0xffc01f18   /* Memory DMA Stream 2 Destination Y Count Register */
-#define                 MDMA_D2_Y_MODIFY  0xffc01f1c   /* Memory DMA Stream 2 Destination Y Modify Register */
-#define            MDMA_D2_CURR_DESC_PTR  0xffc01f20   /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define                MDMA_D2_CURR_ADDR  0xffc01f24   /* Memory DMA Stream 2 Destination Current Address Register */
-#define               MDMA_D2_IRQ_STATUS  0xffc01f28   /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define           MDMA_D2_PERIPHERAL_MAP  0xffc01f2c   /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define             MDMA_D2_CURR_X_COUNT  0xffc01f30   /* Memory DMA Stream 2 Destination Current X Count Register */
-#define             MDMA_D2_CURR_Y_COUNT  0xffc01f38   /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define            MDMA_S2_NEXT_DESC_PTR  0xffc01f40   /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define               MDMA_S2_START_ADDR  0xffc01f44   /* Memory DMA Stream 2 Source Start Address Register */
-#define                   MDMA_S2_CONFIG  0xffc01f48   /* Memory DMA Stream 2 Source Configuration Register */
-#define                  MDMA_S2_X_COUNT  0xffc01f50   /* Memory DMA Stream 2 Source X Count Register */
-#define                 MDMA_S2_X_MODIFY  0xffc01f54   /* Memory DMA Stream 2 Source X Modify Register */
-#define                  MDMA_S2_Y_COUNT  0xffc01f58   /* Memory DMA Stream 2 Source Y Count Register */
-#define                 MDMA_S2_Y_MODIFY  0xffc01f5c   /* Memory DMA Stream 2 Source Y Modify Register */
-#define            MDMA_S2_CURR_DESC_PTR  0xffc01f60   /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define                MDMA_S2_CURR_ADDR  0xffc01f64   /* Memory DMA Stream 2 Source Current Address Register */
-#define               MDMA_S2_IRQ_STATUS  0xffc01f68   /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define           MDMA_S2_PERIPHERAL_MAP  0xffc01f6c   /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define             MDMA_S2_CURR_X_COUNT  0xffc01f70   /* Memory DMA Stream 2 Source Current X Count Register */
-#define             MDMA_S2_CURR_Y_COUNT  0xffc01f78   /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define            MDMA_D3_NEXT_DESC_PTR  0xffc01f80   /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define               MDMA_D3_START_ADDR  0xffc01f84   /* Memory DMA Stream 3 Destination Start Address Register */
-#define                   MDMA_D3_CONFIG  0xffc01f88   /* Memory DMA Stream 3 Destination Configuration Register */
-#define                  MDMA_D3_X_COUNT  0xffc01f90   /* Memory DMA Stream 3 Destination X Count Register */
-#define                 MDMA_D3_X_MODIFY  0xffc01f94   /* Memory DMA Stream 3 Destination X Modify Register */
-#define                  MDMA_D3_Y_COUNT  0xffc01f98   /* Memory DMA Stream 3 Destination Y Count Register */
-#define                 MDMA_D3_Y_MODIFY  0xffc01f9c   /* Memory DMA Stream 3 Destination Y Modify Register */
-#define            MDMA_D3_CURR_DESC_PTR  0xffc01fa0   /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define                MDMA_D3_CURR_ADDR  0xffc01fa4   /* Memory DMA Stream 3 Destination Current Address Register */
-#define               MDMA_D3_IRQ_STATUS  0xffc01fa8   /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define           MDMA_D3_PERIPHERAL_MAP  0xffc01fac   /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define             MDMA_D3_CURR_X_COUNT  0xffc01fb0   /* Memory DMA Stream 3 Destination Current X Count Register */
-#define             MDMA_D3_CURR_Y_COUNT  0xffc01fb8   /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define            MDMA_S3_NEXT_DESC_PTR  0xffc01fc0   /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define               MDMA_S3_START_ADDR  0xffc01fc4   /* Memory DMA Stream 3 Source Start Address Register */
-#define                   MDMA_S3_CONFIG  0xffc01fc8   /* Memory DMA Stream 3 Source Configuration Register */
-#define                  MDMA_S3_X_COUNT  0xffc01fd0   /* Memory DMA Stream 3 Source X Count Register */
-#define                 MDMA_S3_X_MODIFY  0xffc01fd4   /* Memory DMA Stream 3 Source X Modify Register */
-#define                  MDMA_S3_Y_COUNT  0xffc01fd8   /* Memory DMA Stream 3 Source Y Count Register */
-#define                 MDMA_S3_Y_MODIFY  0xffc01fdc   /* Memory DMA Stream 3 Source Y Modify Register */
-#define            MDMA_S3_CURR_DESC_PTR  0xffc01fe0   /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define                MDMA_S3_CURR_ADDR  0xffc01fe4   /* Memory DMA Stream 3 Source Current Address Register */
-#define               MDMA_S3_IRQ_STATUS  0xffc01fe8   /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define           MDMA_S3_PERIPHERAL_MAP  0xffc01fec   /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define             MDMA_S3_CURR_X_COUNT  0xffc01ff0   /* Memory DMA Stream 3 Source Current X Count Register */
-#define             MDMA_S3_CURR_Y_COUNT  0xffc01ff8   /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define                        UART1_DLL  0xffc02000   /* Divisor Latch Low Byte */
-#define                        UART1_DLH  0xffc02004   /* Divisor Latch High Byte */
-#define                       UART1_GCTL  0xffc02008   /* Global Control Register */
-#define                        UART1_LCR  0xffc0200c   /* Line Control Register */
-#define                        UART1_MCR  0xffc02010   /* Modem Control Register */
-#define                        UART1_LSR  0xffc02014   /* Line Status Register */
-#define                        UART1_MSR  0xffc02018   /* Modem Status Register */
-#define                        UART1_SCR  0xffc0201c   /* Scratch Register */
-#define                    UART1_IER_SET  0xffc02020   /* Interrupt Enable Register Set */
-#define                  UART1_IER_CLEAR  0xffc02024   /* Interrupt Enable Register Clear */
-#define                        UART1_THR  0xffc02028   /* Transmit Hold Register */
-#define                        UART1_RBR  0xffc0202c   /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
-#define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
-#define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
-#define                        SPI1_TDBR  0xffc0230c   /* SPI1 Transmit Data Buffer Register */
-#define                        SPI1_RDBR  0xffc02310   /* SPI1 Receive Data Buffer Register */
-#define                        SPI1_BAUD  0xffc02314   /* SPI1 Baud Rate Register */
-#define                      SPI1_SHADOW  0xffc02318   /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define                      SPORT2_TCR1  0xffc02500   /* SPORT2 Transmit Configuration 1 Register */
-#define                      SPORT2_TCR2  0xffc02504   /* SPORT2 Transmit Configuration 2 Register */
-#define                   SPORT2_TCLKDIV  0xffc02508   /* SPORT2 Transmit Serial Clock Divider Register */
-#define                    SPORT2_TFSDIV  0xffc0250c   /* SPORT2 Transmit Frame Sync Divider Register */
-#define                        SPORT2_TX  0xffc02510   /* SPORT2 Transmit Data Register */
-#define                        SPORT2_RX  0xffc02518   /* SPORT2 Receive Data Register */
-#define                      SPORT2_RCR1  0xffc02520   /* SPORT2 Receive Configuration 1 Register */
-#define                      SPORT2_RCR2  0xffc02524   /* SPORT2 Receive Configuration 2 Register */
-#define                   SPORT2_RCLKDIV  0xffc02528   /* SPORT2 Receive Serial Clock Divider Register */
-#define                    SPORT2_RFSDIV  0xffc0252c   /* SPORT2 Receive Frame Sync Divider Register */
-#define                      SPORT2_STAT  0xffc02530   /* SPORT2 Status Register */
-#define                      SPORT2_CHNL  0xffc02534   /* SPORT2 Current Channel Register */
-#define                     SPORT2_MCMC1  0xffc02538   /* SPORT2 Multi channel Configuration Register 1 */
-#define                     SPORT2_MCMC2  0xffc0253c   /* SPORT2 Multi channel Configuration Register 2 */
-#define                     SPORT2_MTCS0  0xffc02540   /* SPORT2 Multi channel Transmit Select Register 0 */
-#define                     SPORT2_MTCS1  0xffc02544   /* SPORT2 Multi channel Transmit Select Register 1 */
-#define                     SPORT2_MTCS2  0xffc02548   /* SPORT2 Multi channel Transmit Select Register 2 */
-#define                     SPORT2_MTCS3  0xffc0254c   /* SPORT2 Multi channel Transmit Select Register 3 */
-#define                     SPORT2_MRCS0  0xffc02550   /* SPORT2 Multi channel Receive Select Register 0 */
-#define                     SPORT2_MRCS1  0xffc02554   /* SPORT2 Multi channel Receive Select Register 1 */
-#define                     SPORT2_MRCS2  0xffc02558   /* SPORT2 Multi channel Receive Select Register 2 */
-#define                     SPORT2_MRCS3  0xffc0255c   /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define                      SPORT3_TCR1  0xffc02600   /* SPORT3 Transmit Configuration 1 Register */
-#define                      SPORT3_TCR2  0xffc02604   /* SPORT3 Transmit Configuration 2 Register */
-#define                   SPORT3_TCLKDIV  0xffc02608   /* SPORT3 Transmit Serial Clock Divider Register */
-#define                    SPORT3_TFSDIV  0xffc0260c   /* SPORT3 Transmit Frame Sync Divider Register */
-#define                        SPORT3_TX  0xffc02610   /* SPORT3 Transmit Data Register */
-#define                        SPORT3_RX  0xffc02618   /* SPORT3 Receive Data Register */
-#define                      SPORT3_RCR1  0xffc02620   /* SPORT3 Receive Configuration 1 Register */
-#define                      SPORT3_RCR2  0xffc02624   /* SPORT3 Receive Configuration 2 Register */
-#define                   SPORT3_RCLKDIV  0xffc02628   /* SPORT3 Receive Serial Clock Divider Register */
-#define                    SPORT3_RFSDIV  0xffc0262c   /* SPORT3 Receive Frame Sync Divider Register */
-#define                      SPORT3_STAT  0xffc02630   /* SPORT3 Status Register */
-#define                      SPORT3_CHNL  0xffc02634   /* SPORT3 Current Channel Register */
-#define                     SPORT3_MCMC1  0xffc02638   /* SPORT3 Multi channel Configuration Register 1 */
-#define                     SPORT3_MCMC2  0xffc0263c   /* SPORT3 Multi channel Configuration Register 2 */
-#define                     SPORT3_MTCS0  0xffc02640   /* SPORT3 Multi channel Transmit Select Register 0 */
-#define                     SPORT3_MTCS1  0xffc02644   /* SPORT3 Multi channel Transmit Select Register 1 */
-#define                     SPORT3_MTCS2  0xffc02648   /* SPORT3 Multi channel Transmit Select Register 2 */
-#define                     SPORT3_MTCS3  0xffc0264c   /* SPORT3 Multi channel Transmit Select Register 3 */
-#define                     SPORT3_MRCS0  0xffc02650   /* SPORT3 Multi channel Receive Select Register 0 */
-#define                     SPORT3_MRCS1  0xffc02654   /* SPORT3 Multi channel Receive Select Register 1 */
-#define                     SPORT3_MRCS2  0xffc02658   /* SPORT3 Multi channel Receive Select Register 2 */
-#define                     SPORT3_MRCS3  0xffc0265c   /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define                     EPPI2_STATUS  0xffc02900   /* EPPI2 Status Register */
-#define                     EPPI2_HCOUNT  0xffc02904   /* EPPI2 Horizontal Transfer Count Register */
-#define                     EPPI2_HDELAY  0xffc02908   /* EPPI2 Horizontal Delay Count Register */
-#define                     EPPI2_VCOUNT  0xffc0290c   /* EPPI2 Vertical Transfer Count Register */
-#define                     EPPI2_VDELAY  0xffc02910   /* EPPI2 Vertical Delay Count Register */
-#define                      EPPI2_FRAME  0xffc02914   /* EPPI2 Lines per Frame Register */
-#define                       EPPI2_LINE  0xffc02918   /* EPPI2 Samples per Line Register */
-#define                     EPPI2_CLKDIV  0xffc0291c   /* EPPI2 Clock Divide Register */
-#define                    EPPI2_CONTROL  0xffc02920   /* EPPI2 Control Register */
-#define                   EPPI2_FS1W_HBL  0xffc02924   /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI2_FS1P_AVPL  0xffc02928   /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define                   EPPI2_FS2W_LVB  0xffc0292c   /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define                  EPPI2_FS2P_LAVF  0xffc02930   /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define                       EPPI2_CLIP  0xffc02934   /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define                         CAN0_MC1  0xffc02a00   /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define                         CAN0_MD1  0xffc02a04   /* CAN Controller 0 Mailbox Direction Register 1 */
-#define                        CAN0_TRS1  0xffc02a08   /* CAN Controller 0 Transmit Request Set Register 1 */
-#define                        CAN0_TRR1  0xffc02a0c   /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define                         CAN0_TA1  0xffc02a10   /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define                         CAN0_AA1  0xffc02a14   /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define                        CAN0_RMP1  0xffc02a18   /* CAN Controller 0 Receive Message Pending Register 1 */
-#define                        CAN0_RML1  0xffc02a1c   /* CAN Controller 0 Receive Message Lost Register 1 */
-#define                      CAN0_MBTIF1  0xffc02a20   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN0_MBRIF1  0xffc02a24   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN0_MBIM1  0xffc02a28   /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define                        CAN0_RFH1  0xffc02a2c   /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define                       CAN0_OPSS1  0xffc02a30   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define                         CAN0_MC2  0xffc02a40   /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define                         CAN0_MD2  0xffc02a44   /* CAN Controller 0 Mailbox Direction Register 2 */
-#define                        CAN0_TRS2  0xffc02a48   /* CAN Controller 0 Transmit Request Set Register 2 */
-#define                        CAN0_TRR2  0xffc02a4c   /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define                         CAN0_TA2  0xffc02a50   /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define                         CAN0_AA2  0xffc02a54   /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define                        CAN0_RMP2  0xffc02a58   /* CAN Controller 0 Receive Message Pending Register 2 */
-#define                        CAN0_RML2  0xffc02a5c   /* CAN Controller 0 Receive Message Lost Register 2 */
-#define                      CAN0_MBTIF2  0xffc02a60   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN0_MBRIF2  0xffc02a64   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN0_MBIM2  0xffc02a68   /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define                        CAN0_RFH2  0xffc02a6c   /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define                       CAN0_OPSS2  0xffc02a70   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define                       CAN0_CLOCK  0xffc02a80   /* CAN Controller 0 Clock Register */
-#define                      CAN0_TIMING  0xffc02a84   /* CAN Controller 0 Timing Register */
-#define                       CAN0_DEBUG  0xffc02a88   /* CAN Controller 0 Debug Register */
-#define                      CAN0_STATUS  0xffc02a8c   /* CAN Controller 0 Global Status Register */
-#define                         CAN0_CEC  0xffc02a90   /* CAN Controller 0 Error Counter Register */
-#define                         CAN0_GIS  0xffc02a94   /* CAN Controller 0 Global Interrupt Status Register */
-#define                         CAN0_GIM  0xffc02a98   /* CAN Controller 0 Global Interrupt Mask Register */
-#define                         CAN0_GIF  0xffc02a9c   /* CAN Controller 0 Global Interrupt Flag Register */
-#define                     CAN0_CONTROL  0xffc02aa0   /* CAN Controller 0 Master Control Register */
-#define                        CAN0_INTR  0xffc02aa4   /* CAN Controller 0 Interrupt Pending Register */
-#define                        CAN0_MBTD  0xffc02aac   /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define                         CAN0_EWR  0xffc02ab0   /* CAN Controller 0 Programmable Warning Level Register */
-#define                         CAN0_ESR  0xffc02ab4   /* CAN Controller 0 Error Status Register */
-#define                       CAN0_UCCNT  0xffc02ac4   /* CAN Controller 0 Universal Counter Register */
-#define                        CAN0_UCRC  0xffc02ac8   /* Universal Counter Reload/Capture Register */
-#define                       CAN0_UCCNF  0xffc02acc   /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM00L  0xffc02b00   /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN0_AM00H  0xffc02b04   /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN0_AM01L  0xffc02b08   /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN0_AM01H  0xffc02b0c   /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN0_AM02L  0xffc02b10   /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN0_AM02H  0xffc02b14   /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN0_AM03L  0xffc02b18   /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN0_AM03H  0xffc02b1c   /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN0_AM04L  0xffc02b20   /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN0_AM04H  0xffc02b24   /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN0_AM05L  0xffc02b28   /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN0_AM05H  0xffc02b2c   /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN0_AM06L  0xffc02b30   /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN0_AM06H  0xffc02b34   /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN0_AM07L  0xffc02b38   /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN0_AM07H  0xffc02b3c   /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN0_AM08L  0xffc02b40   /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN0_AM08H  0xffc02b44   /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN0_AM09L  0xffc02b48   /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN0_AM09H  0xffc02b4c   /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN0_AM10L  0xffc02b50   /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN0_AM10H  0xffc02b54   /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN0_AM11L  0xffc02b58   /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN0_AM11H  0xffc02b5c   /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN0_AM12L  0xffc02b60   /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN0_AM12H  0xffc02b64   /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN0_AM13L  0xffc02b68   /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN0_AM13H  0xffc02b6c   /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN0_AM14L  0xffc02b70   /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN0_AM14H  0xffc02b74   /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN0_AM15L  0xffc02b78   /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN0_AM15H  0xffc02b7c   /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM16L  0xffc02b80   /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN0_AM16H  0xffc02b84   /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN0_AM17L  0xffc02b88   /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN0_AM17H  0xffc02b8c   /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN0_AM18L  0xffc02b90   /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN0_AM18H  0xffc02b94   /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN0_AM19L  0xffc02b98   /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN0_AM19H  0xffc02b9c   /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN0_AM20L  0xffc02ba0   /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN0_AM20H  0xffc02ba4   /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN0_AM21L  0xffc02ba8   /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN0_AM21H  0xffc02bac   /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN0_AM22L  0xffc02bb0   /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN0_AM22H  0xffc02bb4   /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN0_AM23L  0xffc02bb8   /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN0_AM23H  0xffc02bbc   /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN0_AM24L  0xffc02bc0   /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN0_AM24H  0xffc02bc4   /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN0_AM25L  0xffc02bc8   /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN0_AM25H  0xffc02bcc   /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN0_AM26L  0xffc02bd0   /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN0_AM26H  0xffc02bd4   /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN0_AM27L  0xffc02bd8   /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN0_AM27H  0xffc02bdc   /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN0_AM28L  0xffc02be0   /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN0_AM28H  0xffc02be4   /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN0_AM29L  0xffc02be8   /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN0_AM29H  0xffc02bec   /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN0_AM30L  0xffc02bf0   /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN0_AM30H  0xffc02bf4   /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN0_AM31L  0xffc02bf8   /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN0_AM31H  0xffc02bfc   /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB00_DATA0  0xffc02c00   /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define                  CAN0_MB00_DATA1  0xffc02c04   /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define                  CAN0_MB00_DATA2  0xffc02c08   /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define                  CAN0_MB00_DATA3  0xffc02c0c   /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define                 CAN0_MB00_LENGTH  0xffc02c10   /* CAN Controller 0 Mailbox 0 Length Register */
-#define              CAN0_MB00_TIMESTAMP  0xffc02c14   /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define                    CAN0_MB00_ID0  0xffc02c18   /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define                    CAN0_MB00_ID1  0xffc02c1c   /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define                  CAN0_MB01_DATA0  0xffc02c20   /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define                  CAN0_MB01_DATA1  0xffc02c24   /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define                  CAN0_MB01_DATA2  0xffc02c28   /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define                  CAN0_MB01_DATA3  0xffc02c2c   /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define                 CAN0_MB01_LENGTH  0xffc02c30   /* CAN Controller 0 Mailbox 1 Length Register */
-#define              CAN0_MB01_TIMESTAMP  0xffc02c34   /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define                    CAN0_MB01_ID0  0xffc02c38   /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define                    CAN0_MB01_ID1  0xffc02c3c   /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define                  CAN0_MB02_DATA0  0xffc02c40   /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define                  CAN0_MB02_DATA1  0xffc02c44   /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define                  CAN0_MB02_DATA2  0xffc02c48   /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define                  CAN0_MB02_DATA3  0xffc02c4c   /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define                 CAN0_MB02_LENGTH  0xffc02c50   /* CAN Controller 0 Mailbox 2 Length Register */
-#define              CAN0_MB02_TIMESTAMP  0xffc02c54   /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define                    CAN0_MB02_ID0  0xffc02c58   /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define                    CAN0_MB02_ID1  0xffc02c5c   /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define                  CAN0_MB03_DATA0  0xffc02c60   /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define                  CAN0_MB03_DATA1  0xffc02c64   /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define                  CAN0_MB03_DATA2  0xffc02c68   /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define                  CAN0_MB03_DATA3  0xffc02c6c   /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define                 CAN0_MB03_LENGTH  0xffc02c70   /* CAN Controller 0 Mailbox 3 Length Register */
-#define              CAN0_MB03_TIMESTAMP  0xffc02c74   /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define                    CAN0_MB03_ID0  0xffc02c78   /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define                    CAN0_MB03_ID1  0xffc02c7c   /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define                  CAN0_MB04_DATA0  0xffc02c80   /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define                  CAN0_MB04_DATA1  0xffc02c84   /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define                  CAN0_MB04_DATA2  0xffc02c88   /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define                  CAN0_MB04_DATA3  0xffc02c8c   /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define                 CAN0_MB04_LENGTH  0xffc02c90   /* CAN Controller 0 Mailbox 4 Length Register */
-#define              CAN0_MB04_TIMESTAMP  0xffc02c94   /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define                    CAN0_MB04_ID0  0xffc02c98   /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define                    CAN0_MB04_ID1  0xffc02c9c   /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define                  CAN0_MB05_DATA0  0xffc02ca0   /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define                  CAN0_MB05_DATA1  0xffc02ca4   /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define                  CAN0_MB05_DATA2  0xffc02ca8   /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define                  CAN0_MB05_DATA3  0xffc02cac   /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define                 CAN0_MB05_LENGTH  0xffc02cb0   /* CAN Controller 0 Mailbox 5 Length Register */
-#define              CAN0_MB05_TIMESTAMP  0xffc02cb4   /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define                    CAN0_MB05_ID0  0xffc02cb8   /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define                    CAN0_MB05_ID1  0xffc02cbc   /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define                  CAN0_MB06_DATA0  0xffc02cc0   /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define                  CAN0_MB06_DATA1  0xffc02cc4   /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define                  CAN0_MB06_DATA2  0xffc02cc8   /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define                  CAN0_MB06_DATA3  0xffc02ccc   /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define                 CAN0_MB06_LENGTH  0xffc02cd0   /* CAN Controller 0 Mailbox 6 Length Register */
-#define              CAN0_MB06_TIMESTAMP  0xffc02cd4   /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define                    CAN0_MB06_ID0  0xffc02cd8   /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define                    CAN0_MB06_ID1  0xffc02cdc   /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define                  CAN0_MB07_DATA0  0xffc02ce0   /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define                  CAN0_MB07_DATA1  0xffc02ce4   /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define                  CAN0_MB07_DATA2  0xffc02ce8   /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define                  CAN0_MB07_DATA3  0xffc02cec   /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define                 CAN0_MB07_LENGTH  0xffc02cf0   /* CAN Controller 0 Mailbox 7 Length Register */
-#define              CAN0_MB07_TIMESTAMP  0xffc02cf4   /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define                    CAN0_MB07_ID0  0xffc02cf8   /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define                    CAN0_MB07_ID1  0xffc02cfc   /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define                  CAN0_MB08_DATA0  0xffc02d00   /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define                  CAN0_MB08_DATA1  0xffc02d04   /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define                  CAN0_MB08_DATA2  0xffc02d08   /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define                  CAN0_MB08_DATA3  0xffc02d0c   /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define                 CAN0_MB08_LENGTH  0xffc02d10   /* CAN Controller 0 Mailbox 8 Length Register */
-#define              CAN0_MB08_TIMESTAMP  0xffc02d14   /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define                    CAN0_MB08_ID0  0xffc02d18   /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define                    CAN0_MB08_ID1  0xffc02d1c   /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define                  CAN0_MB09_DATA0  0xffc02d20   /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define                  CAN0_MB09_DATA1  0xffc02d24   /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define                  CAN0_MB09_DATA2  0xffc02d28   /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define                  CAN0_MB09_DATA3  0xffc02d2c   /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define                 CAN0_MB09_LENGTH  0xffc02d30   /* CAN Controller 0 Mailbox 9 Length Register */
-#define              CAN0_MB09_TIMESTAMP  0xffc02d34   /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define                    CAN0_MB09_ID0  0xffc02d38   /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define                    CAN0_MB09_ID1  0xffc02d3c   /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define                  CAN0_MB10_DATA0  0xffc02d40   /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define                  CAN0_MB10_DATA1  0xffc02d44   /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define                  CAN0_MB10_DATA2  0xffc02d48   /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define                  CAN0_MB10_DATA3  0xffc02d4c   /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define                 CAN0_MB10_LENGTH  0xffc02d50   /* CAN Controller 0 Mailbox 10 Length Register */
-#define              CAN0_MB10_TIMESTAMP  0xffc02d54   /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define                    CAN0_MB10_ID0  0xffc02d58   /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define                    CAN0_MB10_ID1  0xffc02d5c   /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define                  CAN0_MB11_DATA0  0xffc02d60   /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define                  CAN0_MB11_DATA1  0xffc02d64   /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define                  CAN0_MB11_DATA2  0xffc02d68   /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define                  CAN0_MB11_DATA3  0xffc02d6c   /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define                 CAN0_MB11_LENGTH  0xffc02d70   /* CAN Controller 0 Mailbox 11 Length Register */
-#define              CAN0_MB11_TIMESTAMP  0xffc02d74   /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define                    CAN0_MB11_ID0  0xffc02d78   /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define                    CAN0_MB11_ID1  0xffc02d7c   /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define                  CAN0_MB12_DATA0  0xffc02d80   /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define                  CAN0_MB12_DATA1  0xffc02d84   /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define                  CAN0_MB12_DATA2  0xffc02d88   /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define                  CAN0_MB12_DATA3  0xffc02d8c   /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define                 CAN0_MB12_LENGTH  0xffc02d90   /* CAN Controller 0 Mailbox 12 Length Register */
-#define              CAN0_MB12_TIMESTAMP  0xffc02d94   /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define                    CAN0_MB12_ID0  0xffc02d98   /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define                    CAN0_MB12_ID1  0xffc02d9c   /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define                  CAN0_MB13_DATA0  0xffc02da0   /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define                  CAN0_MB13_DATA1  0xffc02da4   /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define                  CAN0_MB13_DATA2  0xffc02da8   /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define                  CAN0_MB13_DATA3  0xffc02dac   /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define                 CAN0_MB13_LENGTH  0xffc02db0   /* CAN Controller 0 Mailbox 13 Length Register */
-#define              CAN0_MB13_TIMESTAMP  0xffc02db4   /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define                    CAN0_MB13_ID0  0xffc02db8   /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define                    CAN0_MB13_ID1  0xffc02dbc   /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define                  CAN0_MB14_DATA0  0xffc02dc0   /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define                  CAN0_MB14_DATA1  0xffc02dc4   /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define                  CAN0_MB14_DATA2  0xffc02dc8   /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define                  CAN0_MB14_DATA3  0xffc02dcc   /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define                 CAN0_MB14_LENGTH  0xffc02dd0   /* CAN Controller 0 Mailbox 14 Length Register */
-#define              CAN0_MB14_TIMESTAMP  0xffc02dd4   /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define                    CAN0_MB14_ID0  0xffc02dd8   /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define                    CAN0_MB14_ID1  0xffc02ddc   /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define                  CAN0_MB15_DATA0  0xffc02de0   /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define                  CAN0_MB15_DATA1  0xffc02de4   /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define                  CAN0_MB15_DATA2  0xffc02de8   /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define                  CAN0_MB15_DATA3  0xffc02dec   /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define                 CAN0_MB15_LENGTH  0xffc02df0   /* CAN Controller 0 Mailbox 15 Length Register */
-#define              CAN0_MB15_TIMESTAMP  0xffc02df4   /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define                    CAN0_MB15_ID0  0xffc02df8   /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define                    CAN0_MB15_ID1  0xffc02dfc   /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB16_DATA0  0xffc02e00   /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define                  CAN0_MB16_DATA1  0xffc02e04   /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define                  CAN0_MB16_DATA2  0xffc02e08   /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define                  CAN0_MB16_DATA3  0xffc02e0c   /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define                 CAN0_MB16_LENGTH  0xffc02e10   /* CAN Controller 0 Mailbox 16 Length Register */
-#define              CAN0_MB16_TIMESTAMP  0xffc02e14   /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define                    CAN0_MB16_ID0  0xffc02e18   /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define                    CAN0_MB16_ID1  0xffc02e1c   /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define                  CAN0_MB17_DATA0  0xffc02e20   /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define                  CAN0_MB17_DATA1  0xffc02e24   /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define                  CAN0_MB17_DATA2  0xffc02e28   /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define                  CAN0_MB17_DATA3  0xffc02e2c   /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define                 CAN0_MB17_LENGTH  0xffc02e30   /* CAN Controller 0 Mailbox 17 Length Register */
-#define              CAN0_MB17_TIMESTAMP  0xffc02e34   /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define                    CAN0_MB17_ID0  0xffc02e38   /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define                    CAN0_MB17_ID1  0xffc02e3c   /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define                  CAN0_MB18_DATA0  0xffc02e40   /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define                  CAN0_MB18_DATA1  0xffc02e44   /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define                  CAN0_MB18_DATA2  0xffc02e48   /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define                  CAN0_MB18_DATA3  0xffc02e4c   /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define                 CAN0_MB18_LENGTH  0xffc02e50   /* CAN Controller 0 Mailbox 18 Length Register */
-#define              CAN0_MB18_TIMESTAMP  0xffc02e54   /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define                    CAN0_MB18_ID0  0xffc02e58   /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define                    CAN0_MB18_ID1  0xffc02e5c   /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define                  CAN0_MB19_DATA0  0xffc02e60   /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define                  CAN0_MB19_DATA1  0xffc02e64   /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define                  CAN0_MB19_DATA2  0xffc02e68   /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define                  CAN0_MB19_DATA3  0xffc02e6c   /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define                 CAN0_MB19_LENGTH  0xffc02e70   /* CAN Controller 0 Mailbox 19 Length Register */
-#define              CAN0_MB19_TIMESTAMP  0xffc02e74   /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define                    CAN0_MB19_ID0  0xffc02e78   /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define                    CAN0_MB19_ID1  0xffc02e7c   /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define                  CAN0_MB20_DATA0  0xffc02e80   /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define                  CAN0_MB20_DATA1  0xffc02e84   /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define                  CAN0_MB20_DATA2  0xffc02e88   /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define                  CAN0_MB20_DATA3  0xffc02e8c   /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define                 CAN0_MB20_LENGTH  0xffc02e90   /* CAN Controller 0 Mailbox 20 Length Register */
-#define              CAN0_MB20_TIMESTAMP  0xffc02e94   /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define                    CAN0_MB20_ID0  0xffc02e98   /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define                    CAN0_MB20_ID1  0xffc02e9c   /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define                  CAN0_MB21_DATA0  0xffc02ea0   /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define                  CAN0_MB21_DATA1  0xffc02ea4   /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define                  CAN0_MB21_DATA2  0xffc02ea8   /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define                  CAN0_MB21_DATA3  0xffc02eac   /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define                 CAN0_MB21_LENGTH  0xffc02eb0   /* CAN Controller 0 Mailbox 21 Length Register */
-#define              CAN0_MB21_TIMESTAMP  0xffc02eb4   /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define                    CAN0_MB21_ID0  0xffc02eb8   /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define                    CAN0_MB21_ID1  0xffc02ebc   /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define                  CAN0_MB22_DATA0  0xffc02ec0   /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define                  CAN0_MB22_DATA1  0xffc02ec4   /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define                  CAN0_MB22_DATA2  0xffc02ec8   /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define                  CAN0_MB22_DATA3  0xffc02ecc   /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define                 CAN0_MB22_LENGTH  0xffc02ed0   /* CAN Controller 0 Mailbox 22 Length Register */
-#define              CAN0_MB22_TIMESTAMP  0xffc02ed4   /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define                    CAN0_MB22_ID0  0xffc02ed8   /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define                    CAN0_MB22_ID1  0xffc02edc   /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define                  CAN0_MB23_DATA0  0xffc02ee0   /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define                  CAN0_MB23_DATA1  0xffc02ee4   /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define                  CAN0_MB23_DATA2  0xffc02ee8   /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define                  CAN0_MB23_DATA3  0xffc02eec   /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define                 CAN0_MB23_LENGTH  0xffc02ef0   /* CAN Controller 0 Mailbox 23 Length Register */
-#define              CAN0_MB23_TIMESTAMP  0xffc02ef4   /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define                    CAN0_MB23_ID0  0xffc02ef8   /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define                    CAN0_MB23_ID1  0xffc02efc   /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define                  CAN0_MB24_DATA0  0xffc02f00   /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define                  CAN0_MB24_DATA1  0xffc02f04   /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define                  CAN0_MB24_DATA2  0xffc02f08   /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define                  CAN0_MB24_DATA3  0xffc02f0c   /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define                 CAN0_MB24_LENGTH  0xffc02f10   /* CAN Controller 0 Mailbox 24 Length Register */
-#define              CAN0_MB24_TIMESTAMP  0xffc02f14   /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define                    CAN0_MB24_ID0  0xffc02f18   /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define                    CAN0_MB24_ID1  0xffc02f1c   /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define                  CAN0_MB25_DATA0  0xffc02f20   /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define                  CAN0_MB25_DATA1  0xffc02f24   /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define                  CAN0_MB25_DATA2  0xffc02f28   /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define                  CAN0_MB25_DATA3  0xffc02f2c   /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define                 CAN0_MB25_LENGTH  0xffc02f30   /* CAN Controller 0 Mailbox 25 Length Register */
-#define              CAN0_MB25_TIMESTAMP  0xffc02f34   /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define                    CAN0_MB25_ID0  0xffc02f38   /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define                    CAN0_MB25_ID1  0xffc02f3c   /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define                  CAN0_MB26_DATA0  0xffc02f40   /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define                  CAN0_MB26_DATA1  0xffc02f44   /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define                  CAN0_MB26_DATA2  0xffc02f48   /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define                  CAN0_MB26_DATA3  0xffc02f4c   /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define                 CAN0_MB26_LENGTH  0xffc02f50   /* CAN Controller 0 Mailbox 26 Length Register */
-#define              CAN0_MB26_TIMESTAMP  0xffc02f54   /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define                    CAN0_MB26_ID0  0xffc02f58   /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define                    CAN0_MB26_ID1  0xffc02f5c   /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define                  CAN0_MB27_DATA0  0xffc02f60   /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define                  CAN0_MB27_DATA1  0xffc02f64   /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define                  CAN0_MB27_DATA2  0xffc02f68   /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define                  CAN0_MB27_DATA3  0xffc02f6c   /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define                 CAN0_MB27_LENGTH  0xffc02f70   /* CAN Controller 0 Mailbox 27 Length Register */
-#define              CAN0_MB27_TIMESTAMP  0xffc02f74   /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define                    CAN0_MB27_ID0  0xffc02f78   /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define                    CAN0_MB27_ID1  0xffc02f7c   /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define                  CAN0_MB28_DATA0  0xffc02f80   /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define                  CAN0_MB28_DATA1  0xffc02f84   /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define                  CAN0_MB28_DATA2  0xffc02f88   /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define                  CAN0_MB28_DATA3  0xffc02f8c   /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define                 CAN0_MB28_LENGTH  0xffc02f90   /* CAN Controller 0 Mailbox 28 Length Register */
-#define              CAN0_MB28_TIMESTAMP  0xffc02f94   /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define                    CAN0_MB28_ID0  0xffc02f98   /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define                    CAN0_MB28_ID1  0xffc02f9c   /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define                  CAN0_MB29_DATA0  0xffc02fa0   /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define                  CAN0_MB29_DATA1  0xffc02fa4   /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define                  CAN0_MB29_DATA2  0xffc02fa8   /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define                  CAN0_MB29_DATA3  0xffc02fac   /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define                 CAN0_MB29_LENGTH  0xffc02fb0   /* CAN Controller 0 Mailbox 29 Length Register */
-#define              CAN0_MB29_TIMESTAMP  0xffc02fb4   /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define                    CAN0_MB29_ID0  0xffc02fb8   /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define                    CAN0_MB29_ID1  0xffc02fbc   /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define                  CAN0_MB30_DATA0  0xffc02fc0   /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define                  CAN0_MB30_DATA1  0xffc02fc4   /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define                  CAN0_MB30_DATA2  0xffc02fc8   /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define                  CAN0_MB30_DATA3  0xffc02fcc   /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define                 CAN0_MB30_LENGTH  0xffc02fd0   /* CAN Controller 0 Mailbox 30 Length Register */
-#define              CAN0_MB30_TIMESTAMP  0xffc02fd4   /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define                    CAN0_MB30_ID0  0xffc02fd8   /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define                    CAN0_MB30_ID1  0xffc02fdc   /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define                  CAN0_MB31_DATA0  0xffc02fe0   /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define                  CAN0_MB31_DATA1  0xffc02fe4   /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define                  CAN0_MB31_DATA2  0xffc02fe8   /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define                  CAN0_MB31_DATA3  0xffc02fec   /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define                 CAN0_MB31_LENGTH  0xffc02ff0   /* CAN Controller 0 Mailbox 31 Length Register */
-#define              CAN0_MB31_TIMESTAMP  0xffc02ff4   /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define                    CAN0_MB31_ID0  0xffc02ff8   /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define                    CAN0_MB31_ID1  0xffc02ffc   /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03b00   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03b04   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03b08   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc03b0c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03b10   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03b14   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03b18   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc03b1c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03b20   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03b24   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03b28   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc03b2c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03b40   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03b44   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03b48   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc03b4c   /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc04200   /* Configuration Register */
-#define                        CNT_IMASK  0xffc04204   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc04208   /* Status Register */
-#define                      CNT_COMMAND  0xffc0420c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc04210   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc04214   /* Counter Register */
-#define                          CNT_MAX  0xffc04218   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0421c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc04300   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc04304   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc04308   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0430c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc04320   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc04324   /* Secure Control */
-#define                    SECURE_STATUS  0xffc04328   /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define                    DMAC1_PERIMUX  0xffc04340   /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc04380   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc04384   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc04388   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0438c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for SIC_IAR0 */
-
-#define            IRQ_PLL_WAKEUP  0x1        /* PLL Wakeup */
-#define           nIRQ_PLL_WAKEUP  0x0
-
-/* Below is an alternate name that matches the 54x HRM and previous defBF532.h header,
-   above matches previous defBF534.h header */
-#define            PLL_WAKEUP_IRQ  0x1        /* PLL Wakeup Interrupt Request */
-#define           nPLL_WAKEUP_IRQ  0x0
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define              IRQ_DMA0_ERR  0x2        /* DMA Controller 0 Error */
-#define             nIRQ_DMA0_ERR  0x0
-#define             IRQ_EPPI0_ERR  0x4        /* EPPI0 Error */
-#define            nIRQ_EPPI0_ERR  0x0
-#define            IRQ_SPORT0_ERR  0x8        /* SPORT0 Error */
-#define           nIRQ_SPORT0_ERR  0x0
-#define            IRQ_SPORT1_ERR  0x10       /* SPORT1 Error */
-#define           nIRQ_SPORT1_ERR  0x0
-#define              IRQ_SPI0_ERR  0x20       /* SPI0 Error */
-#define             nIRQ_SPI0_ERR  0x0
-#define             IRQ_UART0_ERR  0x40       /* UART0 Error */
-#define            nIRQ_UART0_ERR  0x0
-#define                   IRQ_RTC  0x80       /* Real-Time Clock */
-#define                  nIRQ_RTC  0x0
-#define                 IRQ_DMA12  0x100      /* DMA Channel 12 */
-#define                nIRQ_DMA12  0x0
-#define                  IRQ_DMA0  0x200      /* DMA Channel 0 */
-#define                 nIRQ_DMA0  0x0
-#define                  IRQ_DMA1  0x400      /* DMA Channel 1 */
-#define                 nIRQ_DMA1  0x0
-#define                  IRQ_DMA2  0x800      /* DMA Channel 2 */
-#define                 nIRQ_DMA2  0x0
-#define                  IRQ_DMA3  0x1000     /* DMA Channel 3 */
-#define                 nIRQ_DMA3  0x0
-#define                  IRQ_DMA4  0x2000     /* DMA Channel 4 */
-#define                 nIRQ_DMA4  0x0
-#define                  IRQ_DMA6  0x4000     /* DMA Channel 6 */
-#define                 nIRQ_DMA6  0x0
-#define                  IRQ_DMA7  0x8000     /* DMA Channel 7 */
-#define                 nIRQ_DMA7  0x0
-#define                 IRQ_PINT0  0x80000    /* Pin Interrupt 0 */
-#define                nIRQ_PINT0  0x0
-#define                 IRQ_PINT1  0x100000   /* Pin Interrupt 1 */
-#define                nIRQ_PINT1  0x0
-#define                 IRQ_MDMA0  0x200000   /* Memory DMA Stream 0 */
-#define                nIRQ_MDMA0  0x0
-#define                 IRQ_MDMA1  0x400000   /* Memory DMA Stream 1 */
-#define                nIRQ_MDMA1  0x0
-#define                  IRQ_WDOG  0x800000   /* Watchdog Timer */
-#define                 nIRQ_WDOG  0x0
-#define              IRQ_DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
-#define             nIRQ_DMA1_ERR  0x0
-#define            IRQ_SPORT2_ERR  0x2000000  /* SPORT2 Error */
-#define           nIRQ_SPORT2_ERR  0x0
-#define            IRQ_SPORT3_ERR  0x4000000  /* SPORT3 Error */
-#define           nIRQ_SPORT3_ERR  0x0
-#define               IRQ_MXVR_SD  0x8000000  /* MXVR Synchronous Data */
-#define              nIRQ_MXVR_SD  0x0
-#define              IRQ_SPI1_ERR  0x10000000 /* SPI1 Error */
-#define             nIRQ_SPI1_ERR  0x0
-#define              IRQ_SPI2_ERR  0x20000000 /* SPI2 Error */
-#define             nIRQ_SPI2_ERR  0x0
-#define             IRQ_UART1_ERR  0x40000000 /* UART1 Error */
-#define            nIRQ_UART1_ERR  0x0
-#define             IRQ_UART2_ERR  0x80000000 /* UART2 Error */
-#define            nIRQ_UART2_ERR  0x0
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define              IRQ_CAN0_ERR  0x1        /* CAN0 Error */
-#define             nIRQ_CAN0_ERR  0x0
-#define                 IRQ_DMA18  0x2        /* DMA Channel 18 */
-#define                nIRQ_DMA18  0x0
-#define                 IRQ_DMA19  0x4        /* DMA Channel 19 */
-#define                nIRQ_DMA19  0x0
-#define                 IRQ_DMA20  0x8        /* DMA Channel 20 */
-#define                nIRQ_DMA20  0x0
-#define                 IRQ_DMA21  0x10       /* DMA Channel 21 */
-#define                nIRQ_DMA21  0x0
-#define                 IRQ_DMA13  0x20       /* DMA Channel 13 */
-#define                nIRQ_DMA13  0x0
-#define                 IRQ_DMA14  0x40       /* DMA Channel 14 */
-#define                nIRQ_DMA14  0x0
-#define                  IRQ_DMA5  0x80       /* DMA Channel 5 */
-#define                 nIRQ_DMA5  0x0
-#define                 IRQ_DMA23  0x100      /* DMA Channel 23 */
-#define                nIRQ_DMA23  0x0
-#define                  IRQ_DMA8  0x200      /* DMA Channel 8 */
-#define                 nIRQ_DMA8  0x0
-#define                  IRQ_DMA9  0x400      /* DMA Channel 9 */
-#define                 nIRQ_DMA9  0x0
-#define                 IRQ_DMA10  0x800      /* DMA Channel 10 */
-#define                nIRQ_DMA10  0x0
-#define                 IRQ_DMA11  0x1000     /* DMA Channel 11 */
-#define                nIRQ_DMA11  0x0
-#define                  IRQ_TWI0  0x2000     /* TWI0 */
-#define                 nIRQ_TWI0  0x0
-#define                  IRQ_TWI1  0x4000     /* TWI1 */
-#define                 nIRQ_TWI1  0x0
-#define               IRQ_CAN0_RX  0x8000     /* CAN0 Receive */
-#define              nIRQ_CAN0_RX  0x0
-#define               IRQ_CAN0_TX  0x10000    /* CAN0 Transmit */
-#define              nIRQ_CAN0_TX  0x0
-#define                 IRQ_MDMA2  0x20000    /* Memory DMA Stream 0 */
-#define                nIRQ_MDMA2  0x0
-#define                 IRQ_MDMA3  0x40000    /* Memory DMA Stream 1 */
-#define                nIRQ_MDMA3  0x0
-#define             IRQ_MXVR_STAT  0x80000    /* MXVR Status */
-#define            nIRQ_MXVR_STAT  0x0
-#define               IRQ_MXVR_CM  0x100000   /* MXVR Control Message */
-#define              nIRQ_MXVR_CM  0x0
-#define               IRQ_MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
-#define              nIRQ_MXVR_AP  0x0
-#define             IRQ_EPPI1_ERR  0x400000   /* EPPI1 Error */
-#define            nIRQ_EPPI1_ERR  0x0
-#define             IRQ_EPPI2_ERR  0x800000   /* EPPI2 Error */
-#define            nIRQ_EPPI2_ERR  0x0
-#define             IRQ_UART3_ERR  0x1000000  /* UART3 Error */
-#define            nIRQ_UART3_ERR  0x0
-#define         IRQ_HOSTDP_STATUS  0x2000000  /* Host DMA Port Error */
-#define        nIRQ_HOSTDP_STATUS  0x0
-#define               IRQ_USB_ERR  0x4000000  /* USB Error */
-#define              nIRQ_USB_ERR  0x0
-#define              IRQ_PIXC_ERR  0x8000000  /* Pixel Compositor Error */
-#define             nIRQ_PIXC_ERR  0x0
-#define               IRQ_NFC_ERR  0x10000000 /* Nand Flash Controller Error */
-#define              nIRQ_NFC_ERR  0x0
-#define             IRQ_ATAPI_ERR  0x20000000 /* ATAPI Error */
-#define            nIRQ_ATAPI_ERR  0x0
-#define              IRQ_CAN1_ERR  0x40000000 /* CAN1 Error */
-#define             nIRQ_CAN1_ERR  0x0
-#define             IRQ_DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
-#define            nIRQ_DMAR0_ERR  0x0
-#define             IRQ_DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
-#define            nIRQ_DMAR1_ERR  0x0
-#define                 IRQ_DMAR0  0x80000000 /* DMAR0 Block */
-#define                nIRQ_DMAR0  0x0
-#define                 IRQ_DMAR1  0x80000000 /* DMAR1 Block */
-#define                nIRQ_DMAR1  0x0
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define                 IRQ_DMA15  0x1        /* DMA Channel 15 */
-#define                nIRQ_DMA15  0x0
-#define                 IRQ_DMA16  0x2        /* DMA Channel 16 */
-#define                nIRQ_DMA16  0x0
-#define                 IRQ_DMA17  0x4        /* DMA Channel 17 */
-#define                nIRQ_DMA17  0x0
-#define                 IRQ_DMA22  0x8        /* DMA Channel 22 */
-#define                nIRQ_DMA22  0x0
-#define                   IRQ_CNT  0x10       /* Counter */
-#define                  nIRQ_CNT  0x0
-#define                   IRQ_KEY  0x20       /* Keypad */
-#define                  nIRQ_KEY  0x0
-#define               IRQ_CAN1_RX  0x40       /* CAN1 Receive */
-#define              nIRQ_CAN1_RX  0x0
-#define               IRQ_CAN1_TX  0x80       /* CAN1 Transmit */
-#define              nIRQ_CAN1_TX  0x0
-#define             IRQ_SDH_MASK0  0x100      /* SDH Mask 0 */
-#define            nIRQ_SDH_MASK0  0x0
-#define             IRQ_SDH_MASK1  0x200      /* SDH Mask 1 */
-#define            nIRQ_SDH_MASK1  0x0
-#define              IRQ_USB_EINT  0x400      /* USB Exception */
-#define             nIRQ_USB_EINT  0x0
-#define              IRQ_USB_INT0  0x800      /* USB Interrupt 0 */
-#define             nIRQ_USB_INT0  0x0
-#define              IRQ_USB_INT1  0x1000     /* USB Interrupt 1 */
-#define             nIRQ_USB_INT1  0x0
-#define              IRQ_USB_INT2  0x2000     /* USB Interrupt 2 */
-#define             nIRQ_USB_INT2  0x0
-#define            IRQ_USB_DMAINT  0x4000     /* USB DMA */
-#define           nIRQ_USB_DMAINT  0x0
-#define                   IRQ_OTP  0x8000     /* OTP Access Complete */
-#define                  nIRQ_OTP  0x0
-#define                IRQ_TIMER0  0x400000   /* Timer 0 */
-#define               nIRQ_TIMER0  0x0
-#define                IRQ_TIMER1  0x800000   /* Timer 1 */
-#define               nIRQ_TIMER1  0x0
-#define                IRQ_TIMER2  0x1000000  /* Timer 2 */
-#define               nIRQ_TIMER2  0x0
-#define                IRQ_TIMER3  0x2000000  /* Timer 3 */
-#define               nIRQ_TIMER3  0x0
-#define                IRQ_TIMER4  0x4000000  /* Timer 4 */
-#define               nIRQ_TIMER4  0x0
-#define                IRQ_TIMER5  0x8000000  /* Timer 5 */
-#define               nIRQ_TIMER5  0x0
-#define                IRQ_TIMER6  0x10000000 /* Timer 6 */
-#define               nIRQ_TIMER6  0x0
-#define                IRQ_TIMER7  0x20000000 /* Timer 7 */
-#define               nIRQ_TIMER7  0x0
-#define                 IRQ_PINT2  0x40000000 /* Pin Interrupt 2 */
-#define                nIRQ_PINT2  0x0
-#define                 IRQ_PINT3  0x80000000 /* Pin Interrupt 3 */
-#define                nIRQ_PINT3  0x0
-
-/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
-
-#define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                    nDMAEN  0x0
-#define                       WNR  0x2        /* DMA Direction */
-#define                      nWNR  0x0
-#define                    WDSIZE  0xc        /* Transfer Word Size */
-#define                     DMA2D  0x10       /* DMA Mode */
-#define                    nDMA2D  0x0
-#define                      SYNC  0x20       /* Work Unit Transitions */
-#define                     nSYNC  0x0
-#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                   nDI_SEL  0x0
-#define                     DI_EN  0x80       /* Data Interrupt Enable */
-#define                    nDI_EN  0x0
-#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
-#define                      FLOW  0xf000     /* Next Operation */
-
-/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                 nDMA_DONE  0x0
-#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                  nDMA_ERR  0x0
-#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   nDFETCH  0x0
-#define                   DMA_RUN  0x8        /* DMA Channel Running */
-#define                  nDMA_RUN  0x0
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                     CTYPE  0x40       /* DMA Channel Type */
-#define                    nCTYPE  0x0
-#define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TCPER */
-
-#define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
-#define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
-#define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
-#define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TCCNT */
-
-#define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
-#define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
-#define         DAB_TRAFFIC_COUNT  0x700      /* DAB Traffic Control Count */
-#define    MDMA_ROUND_ROBIN_COUNT  0xf800     /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
-#define                  nPMUXSDH  0x0
-
-/* Bit masks for EBIU_AMGCTL */
-
-#define                    AMCKEN  0x1        /* Async Memory Enable */
-#define                   nAMCKEN  0x0
-#define                     AMBEN  0xe        /* Async bank enable */
-
-/* EBIU_AMGCTL Masks (AMCKEN) */
-#define CDPRIO                  0x0100        /* DMA has priority over core for for external accesses */
-
-/* EBIU_AMGCTL Masks (AMBEN) */
-#define AMBEN_NONE              0x0000        /* All Banks Disabled */
-#define AMBEN_B0                0x0002        /* Enable Async Memory Bank 0 only */
-#define AMBEN_B0_B1             0x0004        /* Enable Async Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2          0x0006        /* Enable Async Memory Banks 0, 1, and 2 */
-#define AMBEN_B0_B1_B2_B3       0x0008        /* Enable Async Memory Banks 0, 1,  2 and 3 */
-#define AMBEN_ALL               0x0008        /* Enable All Async Memory Banks */
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
-#define                  nB0RDYEN  0x0
-#define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
-#define                 nB0RDYPOL  0x0
-#define                      B0TT  0xc        /* Bank 0 transition time */
-#define                      B0ST  0x30       /* Bank 0 Setup time */
-#define                      B0HT  0xc0       /* Bank 0 Hold time */
-#define                     B0RAT  0xf00      /* Bank 0 Read access time */
-#define                     B0WAT  0xf000     /* Bank 0 write access time */
-#define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
-#define                  nB1RDYEN  0x0
-#define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
-#define                 nB1RDYPOL  0x0
-#define                      B1TT  0xc0000    /* Bank 1 transition time */
-#define                      B1ST  0x300000   /* Bank 1 Setup time */
-#define                      B1HT  0xc00000   /* Bank 1 Hold time */
-#define                     B1RAT  0xf000000  /* Bank 1 Read access time */
-#define                     B1WAT  0xf0000000 /* Bank 1 write access time */
-
-/* EBIU_AMBCTL0 Macros */
-#ifdef _MISRA_RULES
-#define SET_B1WAT(x)            (((x)&0xFu) << 28)   /* B1 Write Access Time = x cycles */
-#define SET_B1RAT(x)            (((x)&0xFu) << 24)   /* B1 Read Access Time = x cycles */
-#define SET_B1HT(x)             (((x)&0x3u) << 22)   /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B1ST(x)             (((x)&0x3u) << 20)   /* B1 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B1TT(x)             (((x)&0x3u) << 18)   /* B1 Transition Time (Read to Write) = x cycles */
-
-#define SET_B0WAT(x)            (((x)&0xFu) << 12)   /* B0 Write Access Time = x cycles */
-#define SET_B0RAT(x)            (((x)&0xFu) << 8)    /* B0 Read Access Time = x cycles */
-#define SET_B0HT(x)             (((x)&0x3u) << 6)    /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B0ST(x)             (((x)&0x3u) << 4)    /* B0 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B0TT(x)             (((x)&0x3u) << 2)    /* B0 Transition Time (Read to Write) = x cycles */
-#else
-#define SET_B1WAT(x)            (((x)&0xF) << 28)   /* B1 Write Access Time = x cycles */
-#define SET_B1RAT(x)            (((x)&0xF) << 24)   /* B1 Read Access Time = x cycles */
-#define SET_B1HT(x)             (((x)&0x3) << 22)   /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B1ST(x)             (((x)&0x3) << 20)   /* B1 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B1TT(x)             (((x)&0x3) << 18)   /* B1 Transition Time (Read to Write) = x cycles */
-
-#define SET_B0WAT(x)            (((x)&0xF) << 12)   /* B0 Write Access Time = x cycles */
-#define SET_B0RAT(x)            (((x)&0xF) << 8)    /* B0 Read Access Time = x cycles */
-#define SET_B0HT(x)             (((x)&0x3) << 6)    /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B0ST(x)             (((x)&0x3) << 4)    /* B0 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B0TT(x)             (((x)&0x3) << 2)    /* B0 Transition Time (Read to Write) = x cycles */
-#endif /* _MISRA_RULES */
-
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
-#define                  nB2RDYEN  0x0
-#define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
-#define                 nB2RDYPOL  0x0
-#define                      B2TT  0xc        /* Bank 2 transition time */
-#define                      B2ST  0x30       /* Bank 2 Setup time */
-#define                      B2HT  0xc0       /* Bank 2 Hold time */
-#define                     B2RAT  0xf00      /* Bank 2 Read access time */
-#define                     B2WAT  0xf000     /* Bank 2 write access time */
-#define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
-#define                  nB3RDYEN  0x0
-#define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
-#define                 nB3RDYPOL  0x0
-#define                      B3TT  0xc0000    /* Bank 3 transition time */
-#define                      B3ST  0x300000   /* Bank 3 Setup time */
-#define                      B3HT  0xc00000   /* Bank 3 Hold time */
-#define                     B3RAT  0xf000000  /* Bank 3 Read access time */
-#define                     B3WAT  0xf0000000 /* Bank 3 write access time */
-
-/* EBIU_AMBCTL1 Macros */
-#ifdef _MISRA_RULES
-#define SET_B3WAT(x)            (((x)&0xFu) << 28)   /* B3 Write Access Time = x cycles */
-#define SET_B3RAT(x)            (((x)&0xFu) << 24)   /* B3 Read Access Time = x cycles */
-#define SET_B3HT(x)             (((x)&0x3u) << 22)   /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B3ST(x)             (((x)&0x3u) << 20)   /* B3 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B3TT(x)             (((x)&0x3u) << 18)   /* B3 Transition Time (Read to Write) = x cycles */
-
-#define SET_B2WAT(x)            (((x)&0xFu) << 12)   /* B2 Write Access Time = x cycles */
-#define SET_B2RAT(x)            (((x)&0xFu) << 8)    /* B2 Read Access Time = x cycles */
-#define SET_B2HT(x)             (((x)&0x3u) << 6)    /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B2ST(x)             (((x)&0x3u) << 4)    /* B2 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B2TT(x)             (((x)&0x3u) << 2)    /* B2 Transition Time (Read to Write) = x cycles */
-#else
-#define SET_B3WAT(x)            (((x)&0xF) << 28)   /* B3 Write Access Time = x cycles */
-#define SET_B3RAT(x)            (((x)&0xF) << 24)   /* B3 Read Access Time = x cycles */
-#define SET_B3HT(x)             (((x)&0x3) << 22)   /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B3ST(x)             (((x)&0x3) << 20)   /* B3 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B3TT(x)             (((x)&0x3) << 18)   /* B3 Transition Time (Read to Write) = x cycles */
-
-#define SET_B2WAT(x)            (((x)&0xF) << 12)   /* B2 Write Access Time = x cycles */
-#define SET_B2RAT(x)            (((x)&0xF) << 8)    /* B2 Read Access Time = x cycles */
-#define SET_B2HT(x)             (((x)&0x3) << 6)    /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
-#define SET_B2ST(x)             (((x)&0x3) << 4)    /* B2 Setup Time (AOE to Read/Write) = x cycle */
-#define SET_B2TT(x)             (((x)&0x3) << 2)    /* B2 Transition Time (Read to Write) = x cycles */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define                  AMSB0CTL  0x3        /* Async Memory Bank 0 select */
-#define                  AMSB1CTL  0xc        /* Async Memory Bank 1 select */
-#define                  AMSB2CTL  0x30       /* Async Memory Bank 2 select */
-#define                  AMSB3CTL  0xc0       /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define                    B0MODE  0x3        /* Async Memory Bank 0 Access Mode */
-#define                    B1MODE  0xc        /* Async Memory Bank 1 Access Mode */
-#define                    B2MODE  0x30       /* Async Memory Bank 2 Access Mode */
-#define                    B3MODE  0xc0       /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_MODE (BOMODE) */
-#define B0MODE_ASYNC            0x00000000          /* Bank 0 Access Mode - 00 - Asynchronous Mode */
-#define B0MODE_FLASH            0x00000001          /* Bank 0 Access Mode - 01 - Asynchronous Flash Mode */
-#define B0MODE_PAGE             0x00000002          /* Bank 0 Access Mode - 10 - Asynchronous Page Mode */
-#define B0MODE_BURST            0x00000003          /* Bank 0 Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* Bit masks for EBIU_MODE (B1MODE) */
-#define B1MODE_ASYNC            0x00000000          /* Bank 1 Access Mode - 00 - Asynchronous Mode */
-#define B1MODE_FLASH            0x00000004          /* Bank 1 Access Mode - 01 - Asynchronous Flash Mode */
-#define B1MODE_PAGE             0x00000008          /* Bank 1 Access Mode - 10 - Asynchronous Page Mode */
-#define B1MODE_BURST            0x0000000C          /* Bank 1 Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* Bit masks for EBIU_MODE (B2MODE) */
-#define B2MODE_ASYNC            0x00000000          /* Bank 2 Access Mode - 00 - Asynchronous Mode */
-#define B2MODE_FLASH            0x00000010          /* Bank 2 Access Mode - 01 - Asynchronous Flash Mode */
-#define B2MODE_PAGE             0x00000020          /* Bank 2 Access Mode - 10 - Asynchronous Page Mode */
-#define B2MODE_BURST            0x00000030          /* Bank 2 Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* Bit masks for EBIU_MODE (B3MODE) */
-#define B3MODE_ASYNC            0x00000000          /* Bank 3 Access Mode - 00 - Asynchronous Mode */
-#define B3MODE_FLASH            0x00000040          /* Bank 3 Access Mode - 01 - Asynchronous Flash Mode */
-#define B3MODE_PAGE             0x00000080          /* Bank 3 Access Mode - 10 - Asynchronous Page Mode */
-#define B3MODE_BURST            0x000000C0          /* Bank 3 Access Mode - 11 - Synchronous (Burst) Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define               TESTSETLOCK  0x1        /* Test set lock */
-#define              nTESTSETLOCK  0x0
-#define                      BCLK  0x6        /* Burst clock frequency */
-#define                      PGWS  0x38       /* Page wait states */
-#define                      PGSZ  0x40       /* Page size */
-#define                     nPGSZ  0x0
-#define                      RDDL  0x380      /* Read data delay */
-
-/* Bit masks for EBIU_FCTL (BCLK) */
-#define BCLK2                   0x00000002          /* Burst clock frequency: 01 - SCLK/2 */
-#define BCLK3                   0x00000004          /* Burst clock frequency: 10 - SCLK/3 */
-#define BCLK4                   0x00000006          /* Burst clock frequency: 11 - SCLK/4 */
-
-/* Macros for EBIU_FCTL */
-#ifdef _MISRA_RULES
-#define SET_PGWS(x)             (((x)&0x7u) << 0x3)  /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
-#else
-#define SET_PGWS(x)             (((x)&0x7) << 0x3)  /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
-#endif /* _MISRA_RULES */
-                                                    /* Burst clock frequency: 00 - Reserved */
-/* Bit masks for EBIU_ARBSTAT */
-
-#define                   ARBSTAT  0x1        /* Arbitration status */
-#define                  nARBSTAT  0x0
-#define                    BGSTAT  0x2        /* Bus grant status */
-#define                   nBGSTAT  0x0
-
-/* Bit masks for EBIU_DDRCTL0 */
-#define                     TREFI  0x3fff     /* Refresh Interval */
-#define                      TRFC  0x3c000    /* Auto-refresh command period */
-#define                       TRP  0x3c0000   /* Pre charge-to-active command period */
-#define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
-#define                       TRC  0x3c000000 /* Active-to-active time */
-
-/* Macros for EBIU_DDRCTL0 */
-#ifdef _MISRA_RULES
-#define SET_tRC(x)              (((x)&0xFu) << 26)   /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
-#define SET_tRAS(x)             (((x)&0xFu) << 22)   /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
-#define SET_tRP(x)              (((x)&0xFu) << 18)   /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
-#define SET_tRFC(x)             (((x)&0xFu) << 14)   /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
-#define SET_tREFI(x)            ((x)&0x3FFFu)        /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
-#else
-#define SET_tRC(x)              (((x)&0xF) << 26)   /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
-#define SET_tRAS(x)             (((x)&0xF) << 22)   /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
-#define SET_tRP(x)              (((x)&0xF) << 18)   /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
-#define SET_tRFC(x)             (((x)&0xF) << 14)   /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
-#define SET_tREFI(x)            ((x)&0x3FFF)        /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define                      TRCD  0xf        /* Active-to-Read/write delay */
-#define                       MRD  0xf0       /* Mode register set to active */
-#define                       TWR  0x300      /* Write Recovery time */
-#define               DDRDATWIDTH  0x3000     /* DDR data width */
-#define                  EXTBANKS  0xc000     /* External banks */
-#define               DDRDEVWIDTH  0x30000    /* DDR device width */
-#define                DDRDEVSIZE  0xc0000    /* DDR device size */
-#define                     TWWTR  0xf0000000 /* Write-to-read delay */
-
-/* Alternate names that match BF54x HRM */
-#define              DDR_DATWIDTH  0x3000     /* DDR data width */
-#define              DDR_DEVWIDTH  0x30000    /* DDR device width */
-#define               DDR_DEVSIZE  0xc0000    /* DDR device size */
-
-/* Masks for EBIU_DDRCTL1 (DDRDATWIDTH) [in HRM: DDR_DATWIDTH] */
-#define DDR_DATAWIDTH           0x00002000          /* DDR_DATWIDTH Total DDR Data Width (16-bit Only) */
-
-/* Masks for EBIU_DDRCTL1 (EXTBANKS) */
-#define CS0                     0x00000000          /* EXTBANKS External Banks[15:14] */
-#define CS0_CS1                 0x00004000          /* default */
-
-/* Masks for EBIU_DDRCTL1 (DDRDEVWIDTH) [in HRM: DDR_DEVWIDTH] */
-#define DDR_DEVWIDTH_4          0x00000000          /* DDR_DRVWIDTH DDR Device Width[17:16] */
-#define DDR_DEVWIDTH_8          0x00010000
-#define DDR_DEVWIDTH_16         0x00020000          /* default */
-
-/* Masks for EBIU_DDRCTL1 (DDRDEVSIZE) [in HRM: DDR_DEVSIZE] */
-#define DDR_DEVSIZE_512         0x00000000          /* DDR_DEVSIZE DDR Device Size[19:18] */
-#define DDR_DEVSIZE_64          0x00040000
-#define DDR_DEVSIZE_128         0x00080000
-#define DDR_DEVSIZE_256         0x000C0000
-
-/* Macros for EBIU_DDRCTL1 */
-#ifdef _MISRA_RULES
-#define SET_tWTR(x)             (((x)&0xFu) << 28)   /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
-#define SET_tWR(x)              (((x)&0x3u) << 8)    /* tWR Write Recovery Time[9:8] */
-#define SET_tMRD(x)             (((x)&0xFu) << 4)    /* tMRD Mode register set to active[7:4] */
-#define SET_tRCD(x)             ((x)&0xFu)           /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
-#else
-#define SET_tWTR(x)             (((x)&0xF) << 28)   /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
-#define SET_tWR(x)              (((x)&0x3) << 8)    /* tWR Write Recovery Time[9:8] */
-#define SET_tMRD(x)             (((x)&0xF) << 4)    /* tMRD Mode register set to active[7:4] */
-#define SET_tRCD(x)             ((x)&0xF)           /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for EBIU_DDRCTL2 */
-#define               BURSTLENGTH  0x7        /* Burst length */
-#define                CASLATENCY  0x70       /* CAS latency */
-#define                  DLLRESET  0x100      /* DLL Reset */
-#define                 nDLLRESET  0x0
-#define                      REGE  0x1000     /* Register mode enable */
-#define                     nREGE  0x0
-
-/* Masks for EBIU_DDRCTL2 (BURSTLENGTH) */
-#define BURSTLENGTH1            0x00000001          /* BURSTLENGTH Burst length[2:0] - 001 : Read Only value is set to a burst length of 2 */
-
-/* Masks for EBIU_DDRCTL2 (CASLATENCY) */
-/* CASLATENCY CAS Latency[6:4] - The number of clock cycles from assertion of read/write signal to SDRAM until first valid data on output from SDRAM. */
-#define CASLATENCY15            0x00000050          /* 101 : 1.5 */
-#define CASLATENCY2             0x00000020          /* 010 : 2 (Default) */
-#define CASLATENCY25            0x00000060          /* 110 : 2.5 */
-#define CASLATENCY3             0x00000030          /* 011 : 3 */
-
-/* Masks for EBIU_DDRCTL2 (DLLRESET) */
-#define DLL                     0x00000001          /* 0: Enable DLL */
-#define nDLL                    0x0                 /* 0: Disable DLL (Default) */
-#define DS                      0x00000002          /* Defaults to 1 ( Reduced Strength). This is the ONLY value supported */
-#define nDS                     0x0
-
-/* Bit masks for EBIU_DDRCTL3 */
-#define                      PASR  0x7        /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-#define                DEB0_PFLEN  0x3        /* Pre fetch length for DEB0 accesses */
-#define                DEB1_PFLEN  0xc        /* Pre fetch length for DEB1 accesses */
-#define                DEB2_PFLEN  0x30       /* Pre fetch length for DEB2 accesses */
-#define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
-#define               DEB0_URGENT  0x1000     /* DEB0 Urgent */
-#define              nDEB0_URGENT  0x0
-#define               DEB1_URGENT  0x2000     /* DEB1 Urgent */
-#define              nDEB1_URGENT  0x0
-#define               DEB2_URGENT  0x4000     /* DEB2 Urgent */
-#define              nDEB2_URGENT  0x0
-
-/* Bit masks for EBIU_DDRQUE (DEB0_PFLEN) */
-/* DEB0_PFLEN[1:0] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
-#define DEB0_PFLEN0             0x00000000          /* 00 - (Single Access) */
-#define DEB0_PFLEN4             0x00000001          /* 01 - 4 Half-words (Default) */
-#define DEB0_PFLEN8             0x00000002          /* 10 - 8 Half-words */
-#define DEB0_PFLEN16            0x00000003          /* 11 - 16Half-words */
-/* performs, 16 bit read to DDR controller. Second edge is not used. */
-
-/* Bit masks for EBIU_DDRQUE (DEB1_PFLEN) */
-/* DEB1_PFLEN[3:2] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
-#define DEB1_PFLEN0             0x00000000          /* 00 - (Single Access) */
-#define DEB1_PFLEN4             0x00000004          /* 01 - 4 Half-words (Default) */
-#define DEB1_PFLEN8             0x00000008          /* 10 - 8 Half-words */
-#define DEB1_PFLEN16            0x0000000C          /* 11 - 16Half-words */
-/* performs, 16 bit read to DDR controller. Second edge is not used. */
-
-/* Bit masks for EBIU_DDRQUE (DEB2_PFLEN) */
-/* DEB2_PFLEN[5:4] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
-#define DEB2_PFLEN0             0x00000000          /* 00 - (Single Access) */
-#define DEB2_PFLEN4             0x00000010          /* 01 - 4 Half-words (Default) */
-#define DEB2_PFLEN8             0x00000020          /* 10 - 8 Half-words */
-#define DEB2_PFLEN16            0x00000030          /* 11 - 16Half-words */
-/* performs, 16 bit read to DDR controller. Second edge is not used. */
-
-/* Bit masks for EBIU_DDRQUE (DEB_ARB_PRIORITY) */
-/* DEB_ARB_PRIORITY[10:8] - Arbitration Priority between all DEB buses for External DDR Memory: */
-#define DEB_ARB_PRIORITY0       0x00000000          /* 000 : DEB0>DEB1>DEB2 */
-#define DEB_ARB_PRIORITY1       0x00000100          /* 001 : DEB1>DEB0>DEB2 (Default) */
-#define DEB_ARB_PRIORITY2       0x00000200          /* 010 : DEB2>DEB0>DEB1 */
-/* In addition the following fixed order of arbitration is maintained:
-1. Core Lock Access
-2. Urgent DMA Access
-3. Core Access
-4. Normal DMA Access
-5. Prefetch Reads */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define                DEB1_ERROR  0x1        /* DEB1 Error */
-#define               nDEB1_ERROR  0x0
-#define                DEB2_ERROR  0x2        /* DEB2 Error */
-#define               nDEB2_ERROR  0x0
-#define                DEB3_ERROR  0x4        /* DEB3 Error */
-#define               nDEB3_ERROR  0x0
-#define                CORE_ERROR  0x8        /* Core error */
-#define               nCORE_ERROR  0x0
-#define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
-#define               nDEB_MERROR  0x0
-#define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
-#define              nDEB2_MERROR  0x0
-#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
-#define              nDEB3_MERROR  0x0
-#define               CORE_MERROR  0x80       /* Core Error (2nd) */
-#define              nCORE_MERROR  0x0
-
-/* Bit masks for EBIU_ERRADD */
-
-#define             ERROR_ADDRESS  0xffffffff /* Error Address */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define                 DDRSRESET  0x1        /* DDR soft reset */
-#define                nDDRSRESET  0x0
-#define               PFTCHSRESET  0x4        /* DDR prefetch reset */
-#define              nPFTCHSRESET  0x0
-#define                     SRREQ  0x8        /* Self-refresh request */
-#define                    nSRREQ  0x0
-#define                     SRACK  0x10       /* Self-refresh acknowledge */
-#define                    nSRACK  0x0
-
-/* Bit masks for EBIU_DDRBRC0 */
-
-#define                      BRC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC1 */
-
-#define                      BRC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC2 */
-
-#define                      BRC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC3 */
-
-#define                      BRC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC4 */
-
-#define                      BRC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC5 */
-
-#define                      BRC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC6 */
-
-#define                      BRC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC7 */
-
-#define                      BRC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC0 */
-
-#define                      BWC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC1 */
-
-#define                      BWC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC2 */
-
-#define                      BWC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC3 */
-
-#define                      BWC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC4 */
-
-#define                      BWC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC5 */
-
-#define                      BWC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC6 */
-
-#define                      BWC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC7 */
-
-#define                      BWC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRACCT */
-
-#define                      ACCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRTACT */
-
-#define                      TECT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRARCT */
-
-#define                      ARCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC0 */
-
-#define                       GC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC1 */
-
-#define                       GC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC2 */
-
-#define                       GC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC3 */
-
-#define                       GC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
-#define               nB0WCENABLE  0x0
-#define                B1WCENABLE  0x2        /* Bank 1 write count enable */
-#define               nB1WCENABLE  0x0
-#define                B2WCENABLE  0x4        /* Bank 2 write count enable */
-#define               nB2WCENABLE  0x0
-#define                B3WCENABLE  0x8        /* Bank 3 write count enable */
-#define               nB3WCENABLE  0x0
-#define                B4WCENABLE  0x10       /* Bank 4 write count enable */
-#define               nB4WCENABLE  0x0
-#define                B5WCENABLE  0x20       /* Bank 5 write count enable */
-#define               nB5WCENABLE  0x0
-#define                B6WCENABLE  0x40       /* Bank 6 write count enable */
-#define               nB6WCENABLE  0x0
-#define                B7WCENABLE  0x80       /* Bank 7 write count enable */
-#define               nB7WCENABLE  0x0
-#define                B0RCENABLE  0x100      /* Bank 0 read count enable */
-#define               nB0RCENABLE  0x0
-#define                B1RCENABLE  0x200      /* Bank 1 read count enable */
-#define               nB1RCENABLE  0x0
-#define                B2RCENABLE  0x400      /* Bank 2 read count enable */
-#define               nB2RCENABLE  0x0
-#define                B3RCENABLE  0x800      /* Bank 3 read count enable */
-#define               nB3RCENABLE  0x0
-#define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
-#define               nB4RCENABLE  0x0
-#define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
-#define               nB5RCENABLE  0x0
-#define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
-#define               nB6RCENABLE  0x0
-#define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
-#define               nB7RCENABLE  0x0
-#define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
-#define            nROWACTCENABLE  0x0
-#define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
-#define               nRWTCENABLE  0x0
-#define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
-#define                nARCENABLE  0x0
-#define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
-#define                nGC0ENABLE  0x0
-#define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
-#define                nGC1ENABLE  0x0
-#define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
-#define                nGC2ENABLE  0x0
-#define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
-#define                nGC3ENABLE  0x0
-#define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define                 CB0WCOUNT  0x1        /* Clear write count 0 */
-#define                nCB0WCOUNT  0x0
-#define                 CB1WCOUNT  0x2        /* Clear write count 1 */
-#define                nCB1WCOUNT  0x0
-#define                 CB2WCOUNT  0x4        /* Clear write count 2 */
-#define                nCB2WCOUNT  0x0
-#define                 CB3WCOUNT  0x8        /* Clear write count 3 */
-#define                nCB3WCOUNT  0x0
-#define                 CB4WCOUNT  0x10       /* Clear write count 4 */
-#define                nCB4WCOUNT  0x0
-#define                 CB5WCOUNT  0x20       /* Clear write count 5 */
-#define                nCB5WCOUNT  0x0
-#define                 CB6WCOUNT  0x40       /* Clear write count 6 */
-#define                nCB6WCOUNT  0x0
-#define                 CB7WCOUNT  0x80       /* Clear write count 7 */
-#define                nCB7WCOUNT  0x0
-#define                  CBRCOUNT  0x100      /* Clear read count 0 */
-#define                 nCBRCOUNT  0x0
-#define                 CB1RCOUNT  0x200      /* Clear read count 1 */
-#define                nCB1RCOUNT  0x0
-#define                 CB2RCOUNT  0x400      /* Clear read count 2 */
-#define                nCB2RCOUNT  0x0
-#define                 CB3RCOUNT  0x800      /* Clear read count 3 */
-#define                nCB3RCOUNT  0x0
-#define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
-#define                nCB4RCOUNT  0x0
-#define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
-#define                nCB5RCOUNT  0x0
-#define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
-#define                nCB6RCOUNT  0x0
-#define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
-#define                nCB7RCOUNT  0x0
-#define                  CRACOUNT  0x10000    /* Clear row activation count */
-#define                 nCRACOUNT  0x0
-#define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
-#define               nCRWTACOUNT  0x0
-#define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
-#define                 nCARCOUNT  0x0
-#define                  CG0COUNT  0x100000   /* Clear grant count 0 */
-#define                 nCG0COUNT  0x0
-#define                  CG1COUNT  0x200000   /* Clear grant count 1 */
-#define                 nCG1COUNT  0x0
-#define                  CG2COUNT  0x400000   /* Clear grant count 2 */
-#define                 nCG2COUNT  0x0
-#define                  CG3COUNT  0x800000   /* Clear grant count 3 */
-#define                 nCG3COUNT  0x0
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define                       Px0  0x1        /* GPIO 0 */
-#define                      nPx0  0x0
-#define                       Px1  0x2        /* GPIO 1 */
-#define                      nPx1  0x0
-#define                       Px2  0x4        /* GPIO 2 */
-#define                      nPx2  0x0
-#define                       Px3  0x8        /* GPIO 3 */
-#define                      nPx3  0x0
-#define                       Px4  0x10       /* GPIO 4 */
-#define                      nPx4  0x0
-#define                       Px5  0x20       /* GPIO 5 */
-#define                      nPx5  0x0
-#define                       Px6  0x40       /* GPIO 6 */
-#define                      nPx6  0x0
-#define                       Px7  0x80       /* GPIO 7 */
-#define                      nPx7  0x0
-#define                       Px8  0x100      /* GPIO 8 */
-#define                      nPx8  0x0
-#define                       Px9  0x200      /* GPIO 9 */
-#define                      nPx9  0x0
-#define                      Px10  0x400      /* GPIO 10 */
-#define                     nPx10  0x0
-#define                      Px11  0x800      /* GPIO 11 */
-#define                     nPx11  0x0
-#define                      Px12  0x1000     /* GPIO 12 */
-#define                     nPx12  0x0
-#define                      Px13  0x2000     /* GPIO 13 */
-#define                     nPx13  0x0
-#define                      Px14  0x4000     /* GPIO 14 */
-#define                     nPx14  0x0
-#define                      Px15  0x8000     /* GPIO 15 */
-#define                     nPx15  0x0
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define                      PxM0  0x3        /* GPIO Mux 0 */
-#define                      PxM1  0xc        /* GPIO Mux 1 */
-#define                      PxM2  0x30       /* GPIO Mux 2 */
-#define                      PxM3  0xc0       /* GPIO Mux 3 */
-#define                      PxM4  0x300      /* GPIO Mux 4 */
-#define                      PxM5  0xc00      /* GPIO Mux 5 */
-#define                      PxM6  0x3000     /* GPIO Mux 6 */
-#define                      PxM7  0xc000     /* GPIO Mux 7 */
-#define                      PxM8  0x30000    /* GPIO Mux 8 */
-#define                      PxM9  0xc0000    /* GPIO Mux 9 */
-#define                     PxM10  0x300000   /* GPIO Mux 10 */
-#define                     PxM11  0xc00000   /* GPIO Mux 11 */
-#define                     PxM12  0x3000000  /* GPIO Mux 12 */
-#define                     PxM13  0xc000000  /* GPIO Mux 13 */
-#define                     PxM14  0x30000000 /* GPIO Mux 14 */
-#define                     PxM15  0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define                       IB0  0x1        /* Interrupt Bit 0 */
-#define                      nIB0  0x0
-#define                       IB1  0x2        /* Interrupt Bit 1 */
-#define                      nIB1  0x0
-#define                       IB2  0x4        /* Interrupt Bit 2 */
-#define                      nIB2  0x0
-#define                       IB3  0x8        /* Interrupt Bit 3 */
-#define                      nIB3  0x0
-#define                       IB4  0x10       /* Interrupt Bit 4 */
-#define                      nIB4  0x0
-#define                       IB5  0x20       /* Interrupt Bit 5 */
-#define                      nIB5  0x0
-#define                       IB6  0x40       /* Interrupt Bit 6 */
-#define                      nIB6  0x0
-#define                       IB7  0x80       /* Interrupt Bit 7 */
-#define                      nIB7  0x0
-#define                       IB8  0x100      /* Interrupt Bit 8 */
-#define                      nIB8  0x0
-#define                       IB9  0x200      /* Interrupt Bit 9 */
-#define                      nIB9  0x0
-#define                      IB10  0x400      /* Interrupt Bit 10 */
-#define                     nIB10  0x0
-#define                      IB11  0x800      /* Interrupt Bit 11 */
-#define                     nIB11  0x0
-#define                      IB12  0x1000     /* Interrupt Bit 12 */
-#define                     nIB12  0x0
-#define                      IB13  0x2000     /* Interrupt Bit 13 */
-#define                     nIB13  0x0
-#define                      IB14  0x4000     /* Interrupt Bit 14 */
-#define                     nIB14  0x0
-#define                      IB15  0x8000     /* Interrupt Bit 15 */
-#define                     nIB15  0x0
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define                     TMODE  0x3        /* Timer Mode */
-#define                  PULSE_HI  0x4        /* Pulse Polarity */
-#define                 nPULSE_HI  0x0
-#define                PERIOD_CNT  0x8        /* Period Count */
-#define               nPERIOD_CNT  0x0
-#define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
-#define                  nIRQ_ENA  0x0
-#define                   TIN_SEL  0x20       /* Timer Input Select */
-#define                  nTIN_SEL  0x0
-#define                   OUT_DIS  0x40       /* Output Pad Disable */
-#define                  nOUT_DIS  0x0
-#define                   CLK_SEL  0x80       /* Timer Clock Select */
-#define                  nCLK_SEL  0x0
-#define                 TOGGLE_HI  0x100      /* Toggle Mode */
-#define                nTOGGLE_HI  0x0
-#define                   EMU_RUN  0x200      /* Emulation Behavior Select */
-#define                  nEMU_RUN  0x0
-#define                   ERR_TYP  0xc000     /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define                    TIMEN0  0x1        /* Timer 0 Enable */
-#define                   nTIMEN0  0x0
-#define                    TIMEN1  0x2        /* Timer 1 Enable */
-#define                   nTIMEN1  0x0
-#define                    TIMEN2  0x4        /* Timer 2 Enable */
-#define                   nTIMEN2  0x0
-#define                    TIMEN3  0x8        /* Timer 3 Enable */
-#define                   nTIMEN3  0x0
-#define                    TIMEN4  0x10       /* Timer 4 Enable */
-#define                   nTIMEN4  0x0
-#define                    TIMEN5  0x20       /* Timer 5 Enable */
-#define                   nTIMEN5  0x0
-#define                    TIMEN6  0x40       /* Timer 6 Enable */
-#define                   nTIMEN6  0x0
-#define                    TIMEN7  0x80       /* Timer 7 Enable */
-#define                   nTIMEN7  0x0
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define                   TIMDIS0  0x1        /* Timer 0 Disable */
-#define                  nTIMDIS0  0x0
-#define                   TIMDIS1  0x2        /* Timer 1 Disable */
-#define                  nTIMDIS1  0x0
-#define                   TIMDIS2  0x4        /* Timer 2 Disable */
-#define                  nTIMDIS2  0x0
-#define                   TIMDIS3  0x8        /* Timer 3 Disable */
-#define                  nTIMDIS3  0x0
-#define                   TIMDIS4  0x10       /* Timer 4 Disable */
-#define                  nTIMDIS4  0x0
-#define                   TIMDIS5  0x20       /* Timer 5 Disable */
-#define                  nTIMDIS5  0x0
-#define                   TIMDIS6  0x40       /* Timer 6 Disable */
-#define                  nTIMDIS6  0x0
-#define                   TIMDIS7  0x80       /* Timer 7 Disable */
-#define                  nTIMDIS7  0x0
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define                    TIMIL0  0x1        /* Timer 0 Interrupt */
-#define                   nTIMIL0  0x0
-#define                    TIMIL1  0x2        /* Timer 1 Interrupt */
-#define                   nTIMIL1  0x0
-#define                    TIMIL2  0x4        /* Timer 2 Interrupt */
-#define                   nTIMIL2  0x0
-#define                    TIMIL3  0x8        /* Timer 3 Interrupt */
-#define                   nTIMIL3  0x0
-#define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
-#define                nTOVF_ERR0  0x0
-#define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
-#define                nTOVF_ERR1  0x0
-#define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
-#define                nTOVF_ERR2  0x0
-#define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
-#define                nTOVF_ERR3  0x0
-#define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
-#define                    nTRUN0  0x0
-#define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
-#define                    nTRUN1  0x0
-#define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
-#define                    nTRUN2  0x0
-#define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
-#define                    nTRUN3  0x0
-#define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
-#define                   nTIMIL4  0x0
-#define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
-#define                   nTIMIL5  0x0
-#define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
-#define                   nTIMIL6  0x0
-#define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
-#define                   nTIMIL7  0x0
-#define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
-#define                nTOVF_ERR4  0x0
-#define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
-#define                nTOVF_ERR5  0x0
-#define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
-#define                nTOVF_ERR6  0x0
-#define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
-#define                nTOVF_ERR7  0x0
-#define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
-#define                    nTRUN4  0x0
-#define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
-#define                    nTRUN5  0x0
-#define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
-#define                    nTRUN6  0x0
-#define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
-#define                    nTRUN7  0x0
-
-/* Bit masks for WDOG_CTL */
-
-#define                      WDEV  0x6        /* Watchdog Event */
-#define                      WDEN  0xff0      /* Watchdog Enable */
-#define                      WDRO  0x8000     /* Watchdog Rolled Over */
-#define                     nWDRO  0x0
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for RTC_STAT */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
-
-/* Bit masks for RTC_ICTL */
-
-#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
-#define nSTOPWATCH_INTERRUPT_ENABLE  0x0
-#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
-#define   nALARM_INTERRUPT_ENABLE  0x0
-#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
-#define nSECONDS_INTERRUPT_ENABLE  0x0
-#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
-#define nMINUTES_INTERRUPT_ENABLE  0x0
-#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
-#define   nHOURS_INTERRUPT_ENABLE  0x0
-#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
-#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x0
-#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
-#define nDAY_ALARM_INTERRUPT_ENABLE  0x0
-#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
-#define nWRITE_COMPLETE_INTERRUPT_ENABLE  0x0
-
-/* Bit masks for RTC_ISTAT */
-
-#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
-#define     nSTOPWATCH_EVENT_FLAG  0x0
-#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
-#define         nALARM_EVENT_FLAG  0x0
-#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
-#define       nSECONDS_EVENT_FLAG  0x0
-#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
-#define       nMINUTES_EVENT_FLAG  0x0
-#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
-#define         nHOURS_EVENT_FLAG  0x0
-#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
-#define nTWENTY_FOUR_HOURS_EVENT_FLAG  0x0
-#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
-#define     nDAY_ALARM_EVENT_FLAG  0x0
-#define     WRITE_PENDING_STATUS  0x4000     /* Write Pending Status */
-#define    nWRITE_PENDING_STATUS  0x0
-#define            WRITE_COMPLETE  0x8000     /* Write Complete */
-#define           nWRITE_COMPLETE  0x0
-
-/* Bit masks for RTC_SWCNT */
-
-#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
-
-/* Bit masks for RTC_ALARM */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define                       DAY  0xfffe0000 /* Day */
-
-/* Bit masks for RTC_PREN */
-
-#define                      PREN  0x1        /* Prescaler Enable */
-#define                     nPREN  0x0
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for PLL_DIV */
-
-#define                      CSEL  0x30       /* Core Select */
-#define                      SSEL  0xf        /* System Select */
-
-/* PLL_DIV Masks (CSEL) */
-#define CSEL_DIV1               0x0000              /* CCLK = VCO / 1 */
-#define CSEL_DIV2               0x0010              /* CCLK = VCO / 2 */
-#define CSEL_DIV4               0x0020              /* CCLK = VCO / 4 */
-#define CSEL_DIV8               0x0030              /* CCLK = VCO / 8 */
-
-/* PLL_DIV Macros */
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)             ((x)&0xFu)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#else
-#define SET_SSEL(x)             ((x)&0xF)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for PLL_CTL */
-
-#define                      MSEL  0x7e00     /* Multiplier Select */
-#define                    BYPASS  0x100      /* PLL Bypass Enable */
-#define                   nBYPASS  0x0
-#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
-#define             nOUTPUT_DELAY  0x0
-#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
-#define              nINPUT_DELAY  0x0
-#define                      PDWN  0x20       /* Power Down */
-#define                     nPDWN  0x0
-#define                    STOPCK  0x8        /* Stop Clock */
-#define                   nSTOPCK  0x0
-#define                   PLL_OFF  0x2        /* Disable PLL */
-#define                  nPLL_OFF  0x0
-#define                        DF  0x1        /* Divide Frequency */
-#define                       nDF  0x0
-
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x)             (((x)&0x3Fu) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#else
-#define SET_MSEL(x)             (((x)&0x3F) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#endif /* _MISRA_RULES */
-
-/* Bit masks for PLL_STAT */
-
-#define                PLL_LOCKED  0x20       /* PLL Locked Status */
-#define               nPLL_LOCKED  0x0
-#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
-#define       nACTIVE_PLLDISABLED  0x0
-#define                   FULL_ON  0x2        /* Full-On Mode */
-#define                  nFULL_ON  0x0
-#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
-#define        nACTIVE_PLLENABLED  0x0
-#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
-#define                    nRTCWS  0x0
-#define                     CANWS  0x800      /* CAN Wake-Up Status */
-#define                    nCANWS  0x0
-#define                     USBWS  0x2000     /* USB Wake-Up Status */
-#define                    nUSBWS  0x0
-#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
-#define                   nKPADWS  0x0
-#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
-#define                    nROTWS  0x0
-#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
-#define                     nGPWS  0x0
-
-/* Bit masks for VR_CTL */
-
-#define                      FREQ  0x3        /* Regulator Switching Frequency */
-#define                      GAIN  0xc        /* Voltage Output Level Gain */
-#define                      VLEV  0xf0       /* Internal Voltage Level */
-#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
-#define                  nSCKELOW  0x0
-#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
-#define                     nWAKE  0x0
-#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
-#define                    nCANWE  0x0
-#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
-#define                     nGPWE  0x0
-#define                     USBWE  0x800      /* USB Wake-Up Enable */
-#define                    nUSBWE  0x0
-#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
-#define                   nKPADWE  0x0
-#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
-#define                    nROTWE  0x0
-#define 		 CLKBUFOE  0x4000     /* CLKIN Buffer Output Enable */
-#define 		nCLKBUFOE  0x0
-
-/* VR_CTL Masks (FREQ) */
-#define HIBERNATE               0x0000              /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333                0x0001              /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002              /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003              /* Switching Frequency Is 1 MHz */
-
-/* VR_CTL Masks (GAIN) */
-
-#define GAIN_5                  0x0000              /* GAIN = 5 */
-#define GAIN_10                 0x0004              /* GAIN = 10 */
-#define GAIN_20                 0x0008              /* GAIN = 20 */
-#define GAIN_50                 0x000C              /* GAIN = 50 */
-
-/* VR_CTL Masks (VLEV) */
-
-#define VLEV_085                0x0060              /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070              /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080              /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090              /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0              /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0              /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0              /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0              /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0              /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0              /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0
-#define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0
-#define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0
-#define               MASK_WBEDGE  0x4        /* Mask Write Buffer Edge Detect */
-#define              nMASK_WBEDGE  0x0
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0
-#define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-/* Bit masks for CAN0_CONTROL */
-
-#define                       SRS  0x1        /* Software Reset */
-#define                      nSRS  0x0
-#define                       DNM  0x2        /* DeviceNet Mode */
-#define                      nDNM  0x0
-#define                       ABO  0x4        /* Auto Bus On */
-#define                      nABO  0x0
-#define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
-#define                      nWBA  0x0
-#define                       SMR  0x20       /* Sleep Mode Request */
-#define                      nSMR  0x0
-#define                       CSR  0x40       /* CAN Suspend Mode Request */
-#define                      nCSR  0x0
-#define                       CCR  0x80       /* CAN Configuration Mode Request */
-#define                      nCCR  0x0
-
-/* Bit masks for CAN0_STATUS */
-
-#define                        WT  0x1        /* CAN Transmit Warning Flag */
-#define                       nWT  0x0
-#define                        WR  0x2        /* CAN Receive Warning Flag */
-#define                       nWR  0x0
-#define                        EP  0x4        /* CAN Error Passive Mode */
-#define                       nEP  0x0
-#define                       EBO  0x8        /* CAN Error Bus Off Mode */
-#define                      nEBO  0x0
-#define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
-#define                      nCSA  0x0
-#define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
-#define                      nCCA  0x0
-#define                     MBPTR  0x1f00     /* Mailbox Pointer */
-#define                       TRM  0x4000     /* Transmit Mode Status */
-#define                      nTRM  0x0
-#define                       REC  0x8000     /* Receive Mode Status */
-#define                      nREC  0x0
-
-/* Bit masks for CAN0_DEBUG */
-
-#define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
-#define                      nDEC  0x0
-#define                       DRI  0x2        /* Disable CANRX Input Pin */
-#define                      nDRI  0x0
-#define                       DTO  0x4        /* Disable CANTX Output Pin */
-#define                      nDTO  0x0
-#define                       DIL  0x8        /* Disable Internal Loop */
-#define                      nDIL  0x0
-#define                       MAA  0x10       /* Mode Auto-Acknowledge */
-#define                      nMAA  0x0
-#define                       MRB  0x20       /* Mode Read Back */
-#define                      nMRB  0x0
-#define                       CDE  0x8000     /* CAN Debug Mode Enable */
-#define                      nCDE  0x0
-
-/* Bit masks for CAN0_CLOCK */
-
-#define                       BRP  0x3ff      /* CAN Bit Rate Prescaler */
-
-/* Bit masks for CAN0_TIMING */
-
-#define                       SJW  0x300      /* Synchronization Jump Width */
-#define                       SAM  0x80       /* Sampling */
-#define                      nSAM  0x0
-#define                     TSEG2  0x70       /* Time Segment 2 */
-#define                     TSEG1  0xf        /* Time Segment 1 */
-
-/* Bit masks for CAN0_INTR */
-
-#define                     CANRX  0x80       /* Serial Input From Transceiver */
-#define                    nCANRX  0x0
-#define                     CANTX  0x40       /* Serial Output To Transceiver */
-#define                    nCANTX  0x0
-#define                     SMACK  0x8        /* Sleep Mode Acknowledge */
-#define                    nSMACK  0x0
-#define                      GIRQ  0x4        /* Global Interrupt Request Status */
-#define                     nGIRQ  0x0
-#define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
-#define                   nMBTIRQ  0x0
-#define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
-#define                   nMBRIRQ  0x0
-
-/* Bit masks for CAN0_GIM */
-
-#define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
-#define                    nEWTIM  0x0
-#define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
-#define                    nEWRIM  0x0
-#define                      EPIM  0x4        /* Error Passive Interrupt Mask */
-#define                     nEPIM  0x0
-#define                      BOIM  0x8        /* Bus Off Interrupt Mask */
-#define                     nBOIM  0x0
-#define                      WUIM  0x10       /* Wakeup Interrupt Mask */
-#define                     nWUIM  0x0
-#define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
-#define                    nUIAIM  0x0
-#define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
-#define                     nAAIM  0x0
-#define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
-#define                    nRMLIM  0x0
-#define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
-#define                    nUCEIM  0x0
-#define                      ADIM  0x400      /* Access Denied Interrupt Mask */
-#define                     nADIM  0x0
-
-/* Bit masks for CAN0_GIS */
-
-#define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
-#define                    nEWTIS  0x0
-#define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
-#define                    nEWRIS  0x0
-#define                      EPIS  0x4        /* Error Passive Interrupt Status */
-#define                     nEPIS  0x0
-#define                      BOIS  0x8        /* Bus Off Interrupt Status */
-#define                     nBOIS  0x0
-#define                      WUIS  0x10       /* Wakeup Interrupt Status */
-#define                     nWUIS  0x0
-#define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
-#define                    nUIAIS  0x0
-#define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
-#define                     nAAIS  0x0
-#define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
-#define                    nRMLIS  0x0
-#define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
-#define                    nUCEIS  0x0
-#define                      ADIS  0x400      /* Access Denied Interrupt Status */
-#define                     nADIS  0x0
-
-/* Bit masks for CAN0_GIF */
-
-#define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
-#define                    nEWTIF  0x0
-#define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
-#define                    nEWRIF  0x0
-#define                      EPIF  0x4        /* Error Passive Interrupt Flag */
-#define                     nEPIF  0x0
-#define                      BOIF  0x8        /* Bus Off Interrupt Flag */
-#define                     nBOIF  0x0
-#define                      WUIF  0x10       /* Wakeup Interrupt Flag */
-#define                     nWUIF  0x0
-#define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
-#define                    nUIAIF  0x0
-#define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
-#define                     nAAIF  0x0
-#define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
-#define                    nRMLIF  0x0
-#define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
-#define                    nUCEIF  0x0
-#define                      ADIF  0x400      /* Access Denied Interrupt Flag */
-#define                     nADIF  0x0
-
-/* Bit masks for CAN0_MBTD */
-
-#define                       TDR  0x80       /* Temporary Disable Request */
-#define                      nTDR  0x0
-#define                       TDA  0x40       /* Temporary Disable Acknowledge */
-#define                      nTDA  0x0
-#define                     TDPTR  0x1f       /* Temporary Disable Pointer */
-
-/* Bit masks for CAN0_UCCNF */
-
-#define                     UCCNF  0xf        /* Universal Counter Configuration */
-#define                      UCRC  0x20       /* Universal Counter Reload/Clear */
-#define                     nUCRC  0x0
-#define                      UCCT  0x40       /* Universal Counter CAN Trigger */
-#define                     nUCCT  0x0
-#define                       UCE  0x80       /* Universal Counter Enable */
-#define                      nUCE  0x0
-
-/* Bit masks for CAN0_UCCNT */
-
-#define                     UCCNT  0xffff     /* Universal Counter Count Value */
-
-/* Bit masks for CAN0_UCRC */
-
-#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
-
-/* Bit masks for CAN0_CEC */
-
-#define                    RXECNT  0xff       /* Receive Error Counter */
-#define                    TXECNT  0xff00     /* Transmit Error Counter */
-
-/* Bit masks for CAN0_ESR */
-
-#define                       FER  0x80       /* Form Error */
-#define                      nFER  0x0
-#define                       BEF  0x40       /* Bit Error Flag */
-#define                      nBEF  0x0
-#define                       SA0  0x20       /* Stuck At Dominant */
-#define                      nSA0  0x0
-#define                      CRCE  0x10       /* CRC Error */
-#define                     nCRCE  0x0
-#define                       SER  0x8        /* Stuff Bit Error */
-#define                      nSER  0x0
-#define                      ACKE  0x4        /* Acknowledge Error */
-#define                     nACKE  0x0
-
-/* Bit masks for CAN0_EWR */
-
-#define                    EWLTEC  0xff00     /* Transmit Error Warning Limit */
-#define                    EWLREC  0xff       /* Receive Error Warning Limit */
-
-/* Bit masks for CAN0_AMxx_H */
-
-#define                       FDF  0x8000     /* Filter On Data Field */
-#define                      nFDF  0x0
-#define                       FMD  0x4000     /* Full Mask Data */
-#define                      nFMD  0x0
-#define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
-#define                    nAMIDE  0x0
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_AMxx_L */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_ID1 */
-
-#define                       AME  0x8000     /* Acceptance Mask Enable */
-#define                      nAME  0x0
-#define                       RTR  0x4000     /* Remote Transmission Request */
-#define                      nRTR  0x0
-#define                       IDE  0x2000     /* Identifier Extension */
-#define                      nIDE  0x0
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_MBxx_ID0 */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_TIMESTAMP */
-
-#define                       TSV  0xffff     /* Time Stamp Value */
-
-/* Bit masks for CAN0_MBxx_LENGTH */
-
-#define                       DLC  0xf        /* Data Length Code */
-
-/* Bit masks for CAN0_MBxx_DATA3 */
-
-#define                 CAN_BYTE0  0xff00     /* Data Field Byte 0 */
-#define                 CAN_BYTE1  0xff       /* Data Field Byte 1 */
-
-/* Bit masks for CAN0_MBxx_DATA2 */
-
-#define                 CAN_BYTE2  0xff00     /* Data Field Byte 2 */
-#define                 CAN_BYTE3  0xff       /* Data Field Byte 3 */
-
-/* Bit masks for CAN0_MBxx_DATA1 */
-
-#define                 CAN_BYTE4  0xff00     /* Data Field Byte 4 */
-#define                 CAN_BYTE5  0xff       /* Data Field Byte 5 */
-
-/* Bit masks for CAN0_MBxx_DATA0 */
-
-#define                 CAN_BYTE6  0xff00     /* Data Field Byte 6 */
-#define                 CAN_BYTE7  0xff       /* Data Field Byte 7 */
-
-/* Bit masks for CAN0_MC1 */
-
-#define                       MC0  0x1        /* Mailbox 0 Enable */
-#define                      nMC0  0x0
-#define                       MC1  0x2        /* Mailbox 1 Enable */
-#define                      nMC1  0x0
-#define                       MC2  0x4        /* Mailbox 2 Enable */
-#define                      nMC2  0x0
-#define                       MC3  0x8        /* Mailbox 3 Enable */
-#define                      nMC3  0x0
-#define                       MC4  0x10       /* Mailbox 4 Enable */
-#define                      nMC4  0x0
-#define                       MC5  0x20       /* Mailbox 5 Enable */
-#define                      nMC5  0x0
-#define                       MC6  0x40       /* Mailbox 6 Enable */
-#define                      nMC6  0x0
-#define                       MC7  0x80       /* Mailbox 7 Enable */
-#define                      nMC7  0x0
-#define                       MC8  0x100      /* Mailbox 8 Enable */
-#define                      nMC8  0x0
-#define                       MC9  0x200      /* Mailbox 9 Enable */
-#define                      nMC9  0x0
-#define                      MC10  0x400      /* Mailbox 10 Enable */
-#define                     nMC10  0x0
-#define                      MC11  0x800      /* Mailbox 11 Enable */
-#define                     nMC11  0x0
-#define                      MC12  0x1000     /* Mailbox 12 Enable */
-#define                     nMC12  0x0
-#define                      MC13  0x2000     /* Mailbox 13 Enable */
-#define                     nMC13  0x0
-#define                      MC14  0x4000     /* Mailbox 14 Enable */
-#define                     nMC14  0x0
-#define                      MC15  0x8000     /* Mailbox 15 Enable */
-#define                     nMC15  0x0
-
-/* Bit masks for CAN0_MC2 */
-
-#define                      MC16  0x1        /* Mailbox 16 Enable */
-#define                     nMC16  0x0
-#define                      MC17  0x2        /* Mailbox 17 Enable */
-#define                     nMC17  0x0
-#define                      MC18  0x4        /* Mailbox 18 Enable */
-#define                     nMC18  0x0
-#define                      MC19  0x8        /* Mailbox 19 Enable */
-#define                     nMC19  0x0
-#define                      MC20  0x10       /* Mailbox 20 Enable */
-#define                     nMC20  0x0
-#define                      MC21  0x20       /* Mailbox 21 Enable */
-#define                     nMC21  0x0
-#define                      MC22  0x40       /* Mailbox 22 Enable */
-#define                     nMC22  0x0
-#define                      MC23  0x80       /* Mailbox 23 Enable */
-#define                     nMC23  0x0
-#define                      MC24  0x100      /* Mailbox 24 Enable */
-#define                     nMC24  0x0
-#define                      MC25  0x200      /* Mailbox 25 Enable */
-#define                     nMC25  0x0
-#define                      MC26  0x400      /* Mailbox 26 Enable */
-#define                     nMC26  0x0
-#define                      MC27  0x800      /* Mailbox 27 Enable */
-#define                     nMC27  0x0
-#define                      MC28  0x1000     /* Mailbox 28 Enable */
-#define                     nMC28  0x0
-#define                      MC29  0x2000     /* Mailbox 29 Enable */
-#define                     nMC29  0x0
-#define                      MC30  0x4000     /* Mailbox 30 Enable */
-#define                     nMC30  0x0
-#define                      MC31  0x8000     /* Mailbox 31 Enable */
-#define                     nMC31  0x0
-
-/* Bit masks for CAN0_MD1 */
-
-#define                       MD0  0x1        /* Mailbox 0 Receive Enable */
-#define                      nMD0  0x0
-#define                       MD1  0x2        /* Mailbox 1 Receive Enable */
-#define                      nMD1  0x0
-#define                       MD2  0x4        /* Mailbox 2 Receive Enable */
-#define                      nMD2  0x0
-#define                       MD3  0x8        /* Mailbox 3 Receive Enable */
-#define                      nMD3  0x0
-#define                       MD4  0x10       /* Mailbox 4 Receive Enable */
-#define                      nMD4  0x0
-#define                       MD5  0x20       /* Mailbox 5 Receive Enable */
-#define                      nMD5  0x0
-#define                       MD6  0x40       /* Mailbox 6 Receive Enable */
-#define                      nMD6  0x0
-#define                       MD7  0x80       /* Mailbox 7 Receive Enable */
-#define                      nMD7  0x0
-#define                       MD8  0x100      /* Mailbox 8 Receive Enable */
-#define                      nMD8  0x0
-#define                       MD9  0x200      /* Mailbox 9 Receive Enable */
-#define                      nMD9  0x0
-#define                      MD10  0x400      /* Mailbox 10 Receive Enable */
-#define                     nMD10  0x0
-#define                      MD11  0x800      /* Mailbox 11 Receive Enable */
-#define                     nMD11  0x0
-#define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
-#define                     nMD12  0x0
-#define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
-#define                     nMD13  0x0
-#define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
-#define                     nMD14  0x0
-#define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
-#define                     nMD15  0x0
-
-/* Bit masks for CAN0_MD2 */
-
-#define                      MD16  0x1        /* Mailbox 16 Receive Enable */
-#define                     nMD16  0x0
-#define                      MD17  0x2        /* Mailbox 17 Receive Enable */
-#define                     nMD17  0x0
-#define                      MD18  0x4        /* Mailbox 18 Receive Enable */
-#define                     nMD18  0x0
-#define                      MD19  0x8        /* Mailbox 19 Receive Enable */
-#define                     nMD19  0x0
-#define                      MD20  0x10       /* Mailbox 20 Receive Enable */
-#define                     nMD20  0x0
-#define                      MD21  0x20       /* Mailbox 21 Receive Enable */
-#define                     nMD21  0x0
-#define                      MD22  0x40       /* Mailbox 22 Receive Enable */
-#define                     nMD22  0x0
-#define                      MD23  0x80       /* Mailbox 23 Receive Enable */
-#define                     nMD23  0x0
-#define                      MD24  0x100      /* Mailbox 24 Receive Enable */
-#define                     nMD24  0x0
-#define                      MD25  0x200      /* Mailbox 25 Receive Enable */
-#define                     nMD25  0x0
-#define                      MD26  0x400      /* Mailbox 26 Receive Enable */
-#define                     nMD26  0x0
-#define                      MD27  0x800      /* Mailbox 27 Receive Enable */
-#define                     nMD27  0x0
-#define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
-#define                     nMD28  0x0
-#define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
-#define                     nMD29  0x0
-#define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
-#define                     nMD30  0x0
-#define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
-#define                     nMD31  0x0
-
-/* Bit masks for CAN0_RMP1 */
-
-#define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
-#define                     nRMP0  0x0
-#define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
-#define                     nRMP1  0x0
-#define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
-#define                     nRMP2  0x0
-#define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
-#define                     nRMP3  0x0
-#define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
-#define                     nRMP4  0x0
-#define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
-#define                     nRMP5  0x0
-#define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
-#define                     nRMP6  0x0
-#define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
-#define                     nRMP7  0x0
-#define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
-#define                     nRMP8  0x0
-#define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
-#define                     nRMP9  0x0
-#define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
-#define                    nRMP10  0x0
-#define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
-#define                    nRMP11  0x0
-#define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
-#define                    nRMP12  0x0
-#define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
-#define                    nRMP13  0x0
-#define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
-#define                    nRMP14  0x0
-#define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
-#define                    nRMP15  0x0
-
-/* Bit masks for CAN0_RMP2 */
-
-#define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
-#define                    nRMP16  0x0
-#define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
-#define                    nRMP17  0x0
-#define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
-#define                    nRMP18  0x0
-#define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
-#define                    nRMP19  0x0
-#define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
-#define                    nRMP20  0x0
-#define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
-#define                    nRMP21  0x0
-#define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
-#define                    nRMP22  0x0
-#define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
-#define                    nRMP23  0x0
-#define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
-#define                    nRMP24  0x0
-#define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
-#define                    nRMP25  0x0
-#define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
-#define                    nRMP26  0x0
-#define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
-#define                    nRMP27  0x0
-#define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
-#define                    nRMP28  0x0
-#define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
-#define                    nRMP29  0x0
-#define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
-#define                    nRMP30  0x0
-#define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
-#define                    nRMP31  0x0
-
-/* Bit masks for CAN0_RML1 */
-
-#define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
-#define                     nRML0  0x0
-#define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
-#define                     nRML1  0x0
-#define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
-#define                     nRML2  0x0
-#define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
-#define                     nRML3  0x0
-#define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
-#define                     nRML4  0x0
-#define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
-#define                     nRML5  0x0
-#define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
-#define                     nRML6  0x0
-#define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
-#define                     nRML7  0x0
-#define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
-#define                     nRML8  0x0
-#define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
-#define                     nRML9  0x0
-#define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
-#define                    nRML10  0x0
-#define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
-#define                    nRML11  0x0
-#define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
-#define                    nRML12  0x0
-#define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
-#define                    nRML13  0x0
-#define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
-#define                    nRML14  0x0
-#define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
-#define                    nRML15  0x0
-
-/* Bit masks for CAN0_RML2 */
-
-#define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
-#define                    nRML16  0x0
-#define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
-#define                    nRML17  0x0
-#define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
-#define                    nRML18  0x0
-#define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
-#define                    nRML19  0x0
-#define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
-#define                    nRML20  0x0
-#define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
-#define                    nRML21  0x0
-#define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
-#define                    nRML22  0x0
-#define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
-#define                    nRML23  0x0
-#define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
-#define                    nRML24  0x0
-#define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
-#define                    nRML25  0x0
-#define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
-#define                    nRML26  0x0
-#define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
-#define                    nRML27  0x0
-#define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
-#define                    nRML28  0x0
-#define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
-#define                    nRML29  0x0
-#define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
-#define                    nRML30  0x0
-#define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
-#define                    nRML31  0x0
-
-/* Bit masks for CAN0_OPSS1 */
-
-#define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS0  0x0
-#define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS1  0x0
-#define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS2  0x0
-#define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS3  0x0
-#define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS4  0x0
-#define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS5  0x0
-#define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS6  0x0
-#define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS7  0x0
-#define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS8  0x0
-#define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    nOPSS9  0x0
-#define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS10  0x0
-#define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS11  0x0
-#define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS12  0x0
-#define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS13  0x0
-#define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS14  0x0
-#define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS15  0x0
-
-/* Bit masks for CAN0_OPSS2 */
-
-#define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS16  0x0
-#define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS17  0x0
-#define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS18  0x0
-#define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS19  0x0
-#define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS20  0x0
-#define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS21  0x0
-#define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS22  0x0
-#define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS23  0x0
-#define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS24  0x0
-#define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS25  0x0
-#define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS26  0x0
-#define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS27  0x0
-#define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS28  0x0
-#define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS29  0x0
-#define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS30  0x0
-#define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-#define                   nOPSS31  0x0
-
-/* Bit masks for CAN0_TRS1 */
-
-#define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
-#define                     nTRS0  0x0
-#define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
-#define                     nTRS1  0x0
-#define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
-#define                     nTRS2  0x0
-#define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
-#define                     nTRS3  0x0
-#define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
-#define                     nTRS4  0x0
-#define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
-#define                     nTRS5  0x0
-#define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
-#define                     nTRS6  0x0
-#define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
-#define                     nTRS7  0x0
-#define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
-#define                     nTRS8  0x0
-#define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
-#define                     nTRS9  0x0
-#define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
-#define                    nTRS10  0x0
-#define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
-#define                    nTRS11  0x0
-#define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
-#define                    nTRS12  0x0
-#define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
-#define                    nTRS13  0x0
-#define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
-#define                    nTRS14  0x0
-#define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
-#define                    nTRS15  0x0
-
-/* Bit masks for CAN0_TRS2 */
-
-#define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
-#define                    nTRS16  0x0
-#define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
-#define                    nTRS17  0x0
-#define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
-#define                    nTRS18  0x0
-#define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
-#define                    nTRS19  0x0
-#define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
-#define                    nTRS20  0x0
-#define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
-#define                    nTRS21  0x0
-#define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
-#define                    nTRS22  0x0
-#define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
-#define                    nTRS23  0x0
-#define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
-#define                    nTRS24  0x0
-#define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
-#define                    nTRS25  0x0
-#define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
-#define                    nTRS26  0x0
-#define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
-#define                    nTRS27  0x0
-#define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
-#define                    nTRS28  0x0
-#define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
-#define                    nTRS29  0x0
-#define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
-#define                    nTRS30  0x0
-#define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
-#define                    nTRS31  0x0
-
-/* Bit masks for CAN0_TRR1 */
-
-#define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
-#define                     nTRR0  0x0
-#define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
-#define                     nTRR1  0x0
-#define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
-#define                     nTRR2  0x0
-#define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
-#define                     nTRR3  0x0
-#define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
-#define                     nTRR4  0x0
-#define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
-#define                     nTRR5  0x0
-#define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
-#define                     nTRR6  0x0
-#define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
-#define                     nTRR7  0x0
-#define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
-#define                     nTRR8  0x0
-#define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
-#define                     nTRR9  0x0
-#define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
-#define                    nTRR10  0x0
-#define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
-#define                    nTRR11  0x0
-#define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
-#define                    nTRR12  0x0
-#define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
-#define                    nTRR13  0x0
-#define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
-#define                    nTRR14  0x0
-#define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
-#define                    nTRR15  0x0
-
-/* Bit masks for CAN0_TRR2 */
-
-#define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
-#define                    nTRR16  0x0
-#define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
-#define                    nTRR17  0x0
-#define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
-#define                    nTRR18  0x0
-#define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
-#define                    nTRR19  0x0
-#define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
-#define                    nTRR20  0x0
-#define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
-#define                    nTRR21  0x0
-#define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
-#define                    nTRR22  0x0
-#define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
-#define                    nTRR23  0x0
-#define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
-#define                    nTRR24  0x0
-#define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
-#define                    nTRR25  0x0
-#define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
-#define                    nTRR26  0x0
-#define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
-#define                    nTRR27  0x0
-#define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
-#define                    nTRR28  0x0
-#define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
-#define                    nTRR29  0x0
-#define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
-#define                    nTRR30  0x0
-#define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
-#define                    nTRR31  0x0
-
-/* Bit masks for CAN0_AA1 */
-
-#define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
-#define                      nAA0  0x0
-#define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
-#define                      nAA1  0x0
-#define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
-#define                      nAA2  0x0
-#define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
-#define                      nAA3  0x0
-#define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
-#define                      nAA4  0x0
-#define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
-#define                      nAA5  0x0
-#define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
-#define                      nAA6  0x0
-#define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
-#define                      nAA7  0x0
-#define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
-#define                      nAA8  0x0
-#define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
-#define                      nAA9  0x0
-#define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
-#define                     nAA10  0x0
-#define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
-#define                     nAA11  0x0
-#define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
-#define                     nAA12  0x0
-#define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
-#define                     nAA13  0x0
-#define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
-#define                     nAA14  0x0
-#define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
-#define                     nAA15  0x0
-
-/* Bit masks for CAN0_AA2 */
-
-#define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
-#define                     nAA16  0x0
-#define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
-#define                     nAA17  0x0
-#define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
-#define                     nAA18  0x0
-#define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
-#define                     nAA19  0x0
-#define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
-#define                     nAA20  0x0
-#define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
-#define                     nAA21  0x0
-#define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
-#define                     nAA22  0x0
-#define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
-#define                     nAA23  0x0
-#define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
-#define                     nAA24  0x0
-#define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
-#define                     nAA25  0x0
-#define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
-#define                     nAA26  0x0
-#define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
-#define                     nAA27  0x0
-#define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
-#define                     nAA28  0x0
-#define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
-#define                     nAA29  0x0
-#define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
-#define                     nAA30  0x0
-#define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
-#define                     nAA31  0x0
-
-/* Bit masks for CAN0_TA1 */
-
-#define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
-#define                      nTA0  0x0
-#define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
-#define                      nTA1  0x0
-#define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
-#define                      nTA2  0x0
-#define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
-#define                      nTA3  0x0
-#define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
-#define                      nTA4  0x0
-#define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
-#define                      nTA5  0x0
-#define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
-#define                      nTA6  0x0
-#define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
-#define                      nTA7  0x0
-#define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
-#define                      nTA8  0x0
-#define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
-#define                      nTA9  0x0
-#define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
-#define                     nTA10  0x0
-#define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
-#define                     nTA11  0x0
-#define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
-#define                     nTA12  0x0
-#define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
-#define                     nTA13  0x0
-#define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
-#define                     nTA14  0x0
-#define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
-#define                     nTA15  0x0
-
-/* Bit masks for CAN0_TA2 */
-
-#define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
-#define                     nTA16  0x0
-#define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
-#define                     nTA17  0x0
-#define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
-#define                     nTA18  0x0
-#define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
-#define                     nTA19  0x0
-#define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
-#define                     nTA20  0x0
-#define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
-#define                     nTA21  0x0
-#define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
-#define                     nTA22  0x0
-#define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
-#define                     nTA23  0x0
-#define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
-#define                     nTA24  0x0
-#define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
-#define                     nTA25  0x0
-#define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
-#define                     nTA26  0x0
-#define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
-#define                     nTA27  0x0
-#define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
-#define                     nTA28  0x0
-#define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
-#define                     nTA29  0x0
-#define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
-#define                     nTA30  0x0
-#define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
-#define                     nTA31  0x0
-
-/* Bit masks for CAN0_RFH1 */
-
-#define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
-#define                     nRFH0  0x0
-#define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
-#define                     nRFH1  0x0
-#define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
-#define                     nRFH2  0x0
-#define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
-#define                     nRFH3  0x0
-#define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
-#define                     nRFH4  0x0
-#define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
-#define                     nRFH5  0x0
-#define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
-#define                     nRFH6  0x0
-#define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
-#define                     nRFH7  0x0
-#define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
-#define                     nRFH8  0x0
-#define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
-#define                     nRFH9  0x0
-#define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
-#define                    nRFH10  0x0
-#define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
-#define                    nRFH11  0x0
-#define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
-#define                    nRFH12  0x0
-#define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
-#define                    nRFH13  0x0
-#define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
-#define                    nRFH14  0x0
-#define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
-#define                    nRFH15  0x0
-
-/* Bit masks for CAN0_RFH2 */
-
-#define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
-#define                    nRFH16  0x0
-#define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
-#define                    nRFH17  0x0
-#define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
-#define                    nRFH18  0x0
-#define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
-#define                    nRFH19  0x0
-#define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
-#define                    nRFH20  0x0
-#define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
-#define                    nRFH21  0x0
-#define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
-#define                    nRFH22  0x0
-#define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
-#define                    nRFH23  0x0
-#define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
-#define                    nRFH24  0x0
-#define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
-#define                    nRFH25  0x0
-#define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
-#define                    nRFH26  0x0
-#define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
-#define                    nRFH27  0x0
-#define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
-#define                    nRFH28  0x0
-#define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
-#define                    nRFH29  0x0
-#define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
-#define                    nRFH30  0x0
-#define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
-#define                    nRFH31  0x0
-
-/* Bit masks for CAN0_MBIM1 */
-
-#define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
-#define                    nMBIM0  0x0
-#define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
-#define                    nMBIM1  0x0
-#define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
-#define                    nMBIM2  0x0
-#define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
-#define                    nMBIM3  0x0
-#define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
-#define                    nMBIM4  0x0
-#define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
-#define                    nMBIM5  0x0
-#define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
-#define                    nMBIM6  0x0
-#define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
-#define                    nMBIM7  0x0
-#define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
-#define                    nMBIM8  0x0
-#define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
-#define                    nMBIM9  0x0
-#define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
-#define                   nMBIM10  0x0
-#define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
-#define                   nMBIM11  0x0
-#define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
-#define                   nMBIM12  0x0
-#define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
-#define                   nMBIM13  0x0
-#define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
-#define                   nMBIM14  0x0
-#define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
-#define                   nMBIM15  0x0
-
-/* Bit masks for CAN0_MBIM2 */
-
-#define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
-#define                   nMBIM16  0x0
-#define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
-#define                   nMBIM17  0x0
-#define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
-#define                   nMBIM18  0x0
-#define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
-#define                   nMBIM19  0x0
-#define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
-#define                   nMBIM20  0x0
-#define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
-#define                   nMBIM21  0x0
-#define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
-#define                   nMBIM22  0x0
-#define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
-#define                   nMBIM23  0x0
-#define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
-#define                   nMBIM24  0x0
-#define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
-#define                   nMBIM25  0x0
-#define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
-#define                   nMBIM26  0x0
-#define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
-#define                   nMBIM27  0x0
-#define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
-#define                   nMBIM28  0x0
-#define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
-#define                   nMBIM29  0x0
-#define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
-#define                   nMBIM30  0x0
-#define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
-#define                   nMBIM31  0x0
-
-/* Bit masks for CAN0_MBTIF1 */
-
-#define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF0  0x0
-#define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF1  0x0
-#define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF2  0x0
-#define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF3  0x0
-#define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF4  0x0
-#define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF5  0x0
-#define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF6  0x0
-#define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF7  0x0
-#define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF8  0x0
-#define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define                   nMBTIF9  0x0
-#define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF10  0x0
-#define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF11  0x0
-#define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF12  0x0
-#define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF13  0x0
-#define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF14  0x0
-#define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF15  0x0
-
-/* Bit masks for CAN0_MBTIF2 */
-
-#define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF16  0x0
-#define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF17  0x0
-#define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF18  0x0
-#define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF19  0x0
-#define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF20  0x0
-#define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF21  0x0
-#define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF22  0x0
-#define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF23  0x0
-#define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF24  0x0
-#define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF25  0x0
-#define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF26  0x0
-#define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF27  0x0
-#define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF28  0x0
-#define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF29  0x0
-#define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF30  0x0
-#define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-#define                  nMBTIF31  0x0
-
-/* Bit masks for CAN0_MBRIF1 */
-
-#define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF0  0x0
-#define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF1  0x0
-#define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF2  0x0
-#define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF3  0x0
-#define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF4  0x0
-#define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF5  0x0
-#define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF6  0x0
-#define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF7  0x0
-#define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF8  0x0
-#define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define                   nMBRIF9  0x0
-#define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF10  0x0
-#define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF11  0x0
-#define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF12  0x0
-#define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF13  0x0
-#define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF14  0x0
-#define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF15  0x0
-
-/* Bit masks for CAN0_MBRIF2 */
-
-#define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF16  0x0
-#define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF17  0x0
-#define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF18  0x0
-#define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF19  0x0
-#define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF20  0x0
-#define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF21  0x0
-#define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF22  0x0
-#define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF23  0x0
-#define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF24  0x0
-#define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF25  0x0
-#define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF26  0x0
-#define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF27  0x0
-#define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF28  0x0
-#define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF29  0x0
-#define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF30  0x0
-#define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
-#define                  nMBRIF31  0x0
-
-/* Bit masks for EPPIx_STATUS */
-
-#define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
-#define                nCFIFO_ERR  0x0
-#define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
-#define                nYFIFO_ERR  0x0
-#define                 LTERR_OVR  0x4        /* Line Track Overflow */
-#define                nLTERR_OVR  0x0
-#define                LTERR_UNDR  0x8        /* Line Track Underflow */
-#define               nLTERR_UNDR  0x0
-#define                 FTERR_OVR  0x10       /* Frame Track Overflow */
-#define                nFTERR_OVR  0x0
-#define                FTERR_UNDR  0x20       /* Frame Track Underflow */
-#define               nFTERR_UNDR  0x0
-#define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
-#define                 nERR_NCOR  0x0
-#define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
-#define                  nDMA1URQ  0x0
-#define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
-#define                  nDMA0URQ  0x0
-#define                   ERR_DET  0x4000     /* Preamble Error Detected */
-#define                  nERR_DET  0x0
-#define                       FLD  0x8000     /* Field */
-#define                      nFLD  0x0
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define                   EPPI_EN  0x1        /* Enable */
-#define                  nEPPI_EN  0x0
-#define                  EPPI_DIR  0x2        /* Direction */
-#define                 nEPPI_DIR  0x0
-#define                  XFR_TYPE  0xc        /* Operating Mode */
-#define                    FS_CFG  0x30       /* Frame Sync Configuration */
-#define                   FLD_SEL  0x40       /* Field Select/Trigger */
-#define                  nFLD_SEL  0x0
-#define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
-#define                 nITU_TYPE  0x0
-#define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
-#define                 nBLANKGEN  0x0
-#define                   ICLKGEN  0x200      /* Internal Clock Generation */
-#define                  nICLKGEN  0x0
-#define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
-#define                   nIFSGEN  0x0
-#define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
-#define                      POLS  0x6000     /* Frame Sync Polarity */
-#define                      DLEN  0x38000    /* Data Length */
-#define                   SKIP_EN  0x40000    /* Skip Enable */
-#define                  nSKIP_EN  0x0
-#define                   SKIP_EO  0x80000    /* Skip Even or Odd */
-#define                  nSKIP_EO  0x0
-#define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
-#define                   nPACKEN  0x0
-#define                    SWAPEN  0x200000   /* Swap Enable */
-#define                   nSWAPEN  0x0
-#define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
-#define                 nSIGN_EXT  0x0
-#define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
-#define            nSPLT_EVEN_ODD  0x0
-#define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
-#define              nSUBSPLT_ODD  0x0
-#define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
-#define                   nDMACFG  0x0
-#define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
-#define               nRGB_FMT_EN  0x0
-#define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
-#define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
-#define                   F1VB_AD  0xff00     /* Vertical Blanking after Field 1 Active Data */
-#define                   F2VB_BD  0xff0000   /* Vertical Blanking before Field 2 Active Data */
-#define                   F2VB_AD  0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define                    F1_ACT  0xffff     /* Number of Lines of Active Data in Field 1 */
-#define                    F2_ACT  0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define                   LOW_ODD  0xff       /* Lower Limit for Odd Bytes (Chroma) */
-#define                  HIGH_ODD  0xff00     /* Upper Limit for Odd Bytes (Chroma) */
-#define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
-#define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-/* Bit masks for SPIx_BAUD */
-
-#define                  SPI_BAUD  0xffff     /* Baud Rate */
-
-/* Bit masks for SPIx_CTL */
-
-#define                       SPE  0x4000     /* SPI Enable */
-#define                      nSPE  0x0
-#define                       WOM  0x2000     /* Write Open Drain Master */
-#define                      nWOM  0x0
-#define                      MSTR  0x1000     /* Master Mode */
-#define                     nMSTR  0x0
-#define                      CPOL  0x800      /* Clock Polarity */
-#define                     nCPOL  0x0
-#define                      CPHA  0x400      /* Clock Phase */
-#define                     nCPHA  0x0
-#define                      LSBF  0x200      /* LSB First */
-#define                     nLSBF  0x0
-#define                      SIZE  0x100      /* Size of Words */
-#define                     nSIZE  0x0
-#define                     EMISO  0x20       /* Enable MISO Output */
-#define                    nEMISO  0x0
-#define                      PSSE  0x10       /* Slave-Select Enable */
-#define                     nPSSE  0x0
-#define                        GM  0x8        /* Get More Data */
-#define                       nGM  0x0
-#define                        SZ  0x4        /* Send Zero */
-#define                       nSZ  0x0
-#define                     TIMOD  0x3        /* Transfer Initiation Mode */
-
-/* Bit masks for SPIx_FLG */
-
-#define                      FLS1  0x2        /* Slave Select Enable 1 */
-#define                     nFLS1  0x0
-#define                      FLS2  0x4        /* Slave Select Enable 2 */
-#define                     nFLS2  0x0
-#define                      FLS3  0x8        /* Slave Select Enable 3 */
-#define                     nFLS3  0x0
-#define                      FLG1  0x200      /* Slave Select Value 1 */
-#define                     nFLG1  0x0
-#define                      FLG2  0x400      /* Slave Select Value 2 */
-#define                     nFLG2  0x0
-#define                      FLG3  0x800      /* Slave Select Value 3 */
-#define                     nFLG3  0x0
-
-/* Bit masks for SPIx_STAT */
-
-#define                     TXCOL  0x40       /* Transmit Collision Error */
-#define                    nTXCOL  0x0
-#define                       RXS  0x20       /* RDBR Data Buffer Status */
-#define                      nRXS  0x0
-#define                      RBSY  0x10       /* Receive Error */
-#define                     nRBSY  0x0
-#define                       TXS  0x8        /* TDBR Data Buffer Status */
-#define                      nTXS  0x0
-#define                       TXE  0x4        /* Transmission Error */
-#define                      nTXE  0x0
-#define                      MODF  0x2        /* Mode Fault Error */
-#define                     nMODF  0x0
-#define                      SPIF  0x1        /* SPI Finished */
-#define                     nSPIF  0x0
-
-/* Bit masks for SPIx_TDBR */
-
-#define                      TDBR  0xffff     /* Transmit Data Buffer */
-
-/* Bit masks for SPIx_RDBR */
-
-#define                      RDBR  0xffff     /* Receive Data Buffer */
-
-/* Bit masks for SPIx_SHADOW */
-
-#define                    SHADOW  0xffff     /* RDBR Shadow */
-
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final     */
-/* ones for the Moab processors ... bz 1/19/2007    */
-/* ************************************************ */
-
-/* Bit masks for TWIx_CONTROL */
-
-#define                  PRESCALE  0x7f       /* Prescale Value */
-#define                   TWI_ENA  0x80       /* TWI Enable */
-#define                  nTWI_ENA  0x0
-#define                      SCCB  0x200      /* Serial Camera Control Bus */
-#define                     nSCCB  0x0
-
-/* Bit maskes for TWIx_CLKDIV */
-
-#define                    CLKLOW  0xff       /* Clock Low */
-#define                     CLKHI  0xff00     /* Clock High */
-
-/* Bit maskes for TWIx_SLAVE_CTL */
-
-#define                       SEN  0x1        /* Slave Enable */
-#define                      nSEN  0x0
-#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                   nSTDVAL  0x0
-#define                       NAK  0x8        /* Not Acknowledge */
-#define                      nNAK  0x0
-#define                       GEN  0x10       /* General Call Enable */
-#define                      nGEN  0x0
-
-/* Bit maskes for TWIx_SLAVE_ADDR */
-
-#define                     SADDR  0x7f       /* Slave Mode Address */
-
-/* Bit maskes for TWIx_SLAVE_STAT */
-
-#define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     nSDIR  0x0
-#define                     GCALL  0x2        /* General Call */
-#define                    nGCALL  0x0
-
-/* Bit maskes for TWIx_MASTER_CTL */
-
-#define                       MEN  0x1        /* Master Mode Enable */
-#define                      nMEN  0x0
-#define                      MDIR  0x4        /* Master Transfer Direction */
-#define                     nMDIR  0x0
-#define                      FAST  0x8        /* Fast Mode */
-#define                     nFAST  0x0
-#define                      STOP  0x10       /* Issue Stop Condition */
-#define                     nSTOP  0x0
-#define                    RSTART  0x20       /* Repeat Start */
-#define                   nRSTART  0x0
-#define                      DCNT  0x3fc0     /* Data Transfer Count */
-#define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                   nSDAOVR  0x0
-#define                    SCLOVR  0x8000     /* Serial Clock Override */
-#define                   nSCLOVR  0x0
-
-/* Bit maskes for TWIx_MASTER_ADDR */
-
-#define                     MADDR  0x7f       /* Master Mode Address */
-
-/* Bit maskes for TWIx_MASTER_STAT */
-
-#define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                    nMPROG  0x0
-#define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                  nLOSTARB  0x0
-#define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                     nANAK  0x0
-#define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                     nDNAK  0x0
-#define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                 nBUFRDERR  0x0
-#define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                 nBUFWRERR  0x0
-#define                    SDASEN  0x40       /* Serial Data Sense */
-#define                   nSDASEN  0x0
-#define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   nSCLSEN  0x0
-#define                   BUSBUSY  0x100      /* Bus Busy */
-#define                  nBUSBUSY  0x0
-
-/* Bit maskes for TWIx_FIFO_CTL */
-
-#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                 nXMTFLUSH  0x0
-#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 nRCVFLUSH  0x0
-#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                nXMTINTLEN  0x0
-#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-#define                nRCVINTLEN  0x0
-
-/* Bit maskes for TWIx_FIFO_STAT */
-
-#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
-#define                   RCVSTAT  0xc        /* Receive FIFO Status */
-
-/* Bit maskes for TWIx_INT_MASK */
-
-#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                   nSINITM  0x0
-#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                   nSCOMPM  0x0
-#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                    nSERRM  0x0
-#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    nSOVFM  0x0
-#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                   nMCOMPM  0x0
-#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                    nMERRM  0x0
-#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                 nXMTSERVM  0x0
-#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-#define                 nRCVSERVM  0x0
-
-/* Bit maskes for TWIx_INT_STAT */
-
-#define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                    nSINIT  0x0
-#define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                    nSCOMP  0x0
-#define                      SERR  0x4        /* Slave Transfer Error */
-#define                     nSERR  0x0
-#define                      SOVF  0x8        /* Slave Overflow */
-#define                     nSOVF  0x0
-#define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                    nMCOMP  0x0
-#define                      MERR  0x20       /* Master Transfer Error */
-#define                     nMERR  0x0
-#define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                  nXMTSERV  0x0
-#define                   RCVSERV  0x80       /* Receive FIFO Service */
-#define                  nRCVSERV  0x0
-
-/* Bit maskes for TWIx_XMT_DATA8 */
-
-#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_XMT_DATA16 */
-
-#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA8 */
-
-#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA16 */
-
-#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
-
-/* Bit masks for SPORTx_TCR1 */
-
-#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
-#define                    nTCKFE  0x0
-#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
-#define                    nLATFS  0x0
-#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
-#define                     nLTFS  0x0
-#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
-#define                    nDITFS  0x0
-#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
-#define                     nTFSR  0x0
-#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
-#define                     nITFS  0x0
-#define                    TLSBIT  0x10       /* Transmit Bit Order */
-#define                   nTLSBIT  0x0
-#define                    TDTYPE  0xc        /* Data Formatting Type Select */
-#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
-#define                    nITCLK  0x0
-#define                     TSPEN  0x1        /* Transmit Enable */
-#define                    nTSPEN  0x0
-
-/* Bit masks for SPORTx_TCR2 */
-
-#define                     TRFST  0x400      /* Left/Right Order */
-#define                    nTRFST  0x0
-#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
-#define                    nTSFSE  0x0
-#define                      TXSE  0x100      /* TxSEC Enable */
-#define                     nTXSE  0x0
-#define                    SLEN_T  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_RCR1 */
-
-#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
-#define                    nRCKFE  0x0
-#define                     LARFS  0x2000     /* Late Receive Frame Sync */
-#define                    nLARFS  0x0
-#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
-#define                     nLRFS  0x0
-#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
-#define                     nRFSR  0x0
-#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
-#define                     nIRFS  0x0
-#define                    RLSBIT  0x10       /* Receive Bit Order */
-#define                   nRLSBIT  0x0
-#define                    RDTYPE  0xc        /* Data Formatting Type Select */
-#define                     IRCLK  0x2        /* Internal Receive Clock Select */
-#define                    nIRCLK  0x0
-#define                     RSPEN  0x1        /* Receive Enable */
-#define                    nRSPEN  0x0
-
-/* Bit masks for SPORTx_RCR2 */
-
-#define                     RRFST  0x400      /* Left/Right Order */
-#define                    nRRFST  0x0
-#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
-#define                    nRSFSE  0x0
-#define                      RXSE  0x100      /* RxSEC Enable */
-#define                     nRXSE  0x0
-#define                    SLEN_R  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_STAT */
-
-#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
-#define                    nTXHRE  0x0
-#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
-#define                     nTOVF  0x0
-#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
-#define                     nTUVF  0x0
-#define                       TXF  0x8        /* Transmit FIFO Full Status */
-#define                      nTXF  0x0
-#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
-#define                     nROVF  0x0
-#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
-#define                     nRUVF  0x0
-#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
-#define                     nRXNE  0x0
-
-/* Bit masks for SPORTx_MCMC1 */
-
-#define                     WSIZE  0xf000     /* Window Size */
-#define                      WOFF  0x3ff      /* Windows Offset */
-
-/* Bit masks for SPORTx_MCMC2 */
-
-#define                       MFD  0xf000     /* Multi channel Frame Delay */
-#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                     nFSDR  0x0
-#define                     MCMEN  0x10       /* Multi channel Frame Mode Enable */
-#define                    nMCMEN  0x0
-#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
-#define                  nMCDRXPE  0x0
-#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
-#define                  nMCDTXPE  0x0
-#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
-
-/* Bit masks for SPORTx_CHNL */
-
-#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
-
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                      nSTB  0x0
-#define                       PEN  0x8        /* Parity Enable */
-#define                      nPEN  0x0
-#define                       EPS  0x10       /* Even Parity Select */
-#define                      nEPS  0x0
-#define                       STP  0x20       /* Sticky Parity */
-#define                      nSTP  0x0
-#define                        SB  0x40       /* Set Break */
-#define                       nSB  0x0
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                     nXOFF  0x0
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                     nMRTS  0x0
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                     nRFIT  0x0
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                     nRFRT  0x0
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                 nLOOP_ENA  0x0
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                    nFCPOL  0x0
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                     nARTS  0x0
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-#define                     nACTS  0x0
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                       nDR  0x0
-#define                        OE  0x2        /* Overrun Error */
-#define                       nOE  0x0
-#define                        PE  0x4        /* Parity Error */
-#define                       nPE  0x0
-#define                        FE  0x8        /* Framing Error */
-#define                       nFE  0x0
-#define                        BI  0x10       /* Break Interrupt */
-#define                       nBI  0x0
-#define                      THRE  0x20       /* THR Empty */
-#define                     nTHRE  0x0
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                     nTEMT  0x0
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-#define                      nTFI  0x0
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                     nSCTS  0x0
-#define                       CTS  0x10       /* Clear To Send */
-#define                      nCTS  0x0
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-#define                     nRFCS  0x0
-
-/* Bit masks for UARTx_IER_SET and UARTx_IER_CLEAR */
-
-#define                     ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                    nERBFI  0x0
-#define                     ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    nETBEI  0x0
-#define                      ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                     nELSI  0x0
-#define                     EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                    nEDSSI  0x0
-#define                    EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                   nEDTPTI  0x0
-#define                      ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                     nETFI  0x0
-#define                     ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-#define                    nERFCI  0x0
-
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                     nUCEN  0x0
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     nIREN  0x0
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                    nTPOLC  0x0
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                    nRPOLC  0x0
-#define                       FPE  0x10       /* Force Parity Error */
-#define                      nFPE  0x0
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      nFFE  0x0
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     nEDBO  0x0
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-#define                    nEGLSI  0x0
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                  nHMDMAEN  0x0
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                      nREP  0x0
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                      nUTE  0x0
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      nOIE  0x0
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                     nBDIE  0x0
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                     nMBDI  0x0
-#define                       SND  0x80       /* Source/Not Destination */
-#define                      nSND  0x0
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                      nRBC  0x0
-#define                        PS  0x2000     /* Pin Status */
-#define                       nPS  0x0
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       nOI  0x0
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-#define                      nBDI  0x0
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* SYSCR Masks */
-#define BMODE             0x000F /* Boot Mode. Mirror of BMODE Mode Pins */
-#define BMODE_NOBOOT      0x0000 /* The processor does not boot. Rather, the boot kernel executes an IDLE instruction. */
-#define BMODE_FLASH       0x0001 /* Boot from 8-bit or 16-bit external flash memory */
-#define BMODE_FIFO        0x0002 /* Boot from 16-bit asynchronous FIFO */
-#define BMODE_SPIMEM      0x0003 /* Boot from serial SPI memory */
-#define BMODE_SPIHOST     0x0004 /* Boot from SPI0 host (slave mode) */
-#define BMODE_TWIMEM      0x0005 /* Boot from serial TWI memory */
-#define BMODE_TWIHOST     0x0006 /* Boot from TWI0 host (slave mode) */
-#define BMODE_UARTHOST    0x0007 /* Boot from UART host */
-#define BMODE_UART1HOST   0x0007 /* Boot from UART1 host */
-#define BMODE_SDRAMMEM    0x000A /* Boot from SDRAM memory (warm boot) */
-#define BMODE_OTPMEM      0x000B /* Boot from OTP memory */
-#define BMODE_NAND        0x000D /* Boot from 8- and 16-bit NAND flash */
-#define BMODE_HOSTDMA_ACK 0x000E /* Boot from 16-bit host DMA (ACK mode) */
-#define BMODE_HOSTDMA_INT 0x000F /* Boot from 8-bit host DMA (INT mode) */
-
-#define NOBOOT 0x0030 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-#define BCODE 0x00F0
-#define BCODE_NORMAL 0x0000 /* normal boot, update PLL/VR, quickboot as by WURESET */
-#define BCODE_NOBOOT 0x0010 /* bypass boot, don't update PLL/VR */
-#define BCODE_QUICKBOOT 0x0020 /* quick boot, overrule WURESET, don't update PLL/VR */
-#define BCODE_ALLBOOT 0x0040 /* no quick boot, overrule WURESET, don't update PLL/VR */
-#define BCODE_FULLBOOT 0x0060 /* no quick boot, overrule WURESET, update PLL/VR */
-
-#define CDMAPRIO 0x0100 /* DMA1 gets higher priority than DMA0 to L1 memory */
-#define L2DMAPRIO 0x0200 /* DMA1 gets higher priority than DMA0 to L2 memory */
-
-#define WURESET 0x1000 /* wakeup event since last hardware reset */
-#define DFRESET 0x2000 /* recent reset was due to a double fault event */
-#define WDRESET 0x4000 /* recent reset was due to a watchdog event */
-#define SWRESET 0x8000 /* recent reset was issued by software */
-
-/* CNT_COMMAND bit field options */
-
-#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
-#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
-#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
-
-#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
-#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
-#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
-
-#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
-#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
-#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
-
-/* CNT_CONFIG bit field options */
-
-#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
-#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
-#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
-#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
-#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
-
-#define BNDMODE_COMP     0x0000  /* boundary compare mode */
-#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
-#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
-#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT  0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK  0x0003
-
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR,
-PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
-PORTA_FER registers
-*/
-
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR,
-PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
-PORTB_FER registers
-*/
-
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-
-
-/* PORT C Bit Definitions for the registers
-PORTC, PORTC_SET, PORTC_CLEAR,
-PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
-PORTC_FER registers
-*/
-
-
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR,
-PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
-PORTD_FER registers
-*/
-
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR,
-PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
-PORTE_FER registers
-*/
-
-
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR,
-PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
-PORTF_FER registers
-*/
-
-
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR,
-PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
-PORTG_FER registers
-*/
-
-
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR,
-PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
-PORTH_FER registers
-*/
-
-
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR,
-PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
-PORTI_FER registers
-*/
-
-
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR,
-PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
-PORTJ_FER registers
-*/
-
-
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#ifdef _MISRA_RULES
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
-    ((((b15)&3u) << 30) | \
-     (((b14)&3u) << 28) | \
-     (((b13)&3u) << 26) | \
-     (((b12)&3u) << 24) | \
-     (((b11)&3u) << 22) | \
-     (((b10)&3u) << 20) | \
-     (((b9) &3u) << 18) | \
-     (((b8) &3u) << 16) | \
-     (((b7) &3u) << 14) | \
-     (((b6) &3u) << 12) | \
-     (((b5) &3u) << 10) | \
-     (((b4) &3u) << 8)  | \
-     (((b3) &3u) << 6)  | \
-     (((b2) &3u) << 4)  | \
-     (((b1) &3u) << 2)  | \
-     (((b0) &3u)))
-#else
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
-    ((((b15)&3) << 30) | \
-     (((b14)&3) << 28) | \
-     (((b13)&3) << 26) | \
-     (((b12)&3) << 24) | \
-     (((b11)&3) << 22) | \
-     (((b10)&3) << 20) | \
-     (((b9) &3) << 18) | \
-     (((b8) &3) << 16) | \
-     (((b7) &3) << 14) | \
-     (((b6) &3) << 12) | \
-     (((b5) &3) << 10) | \
-     (((b4) &3) << 8)  | \
-     (((b3) &3) << 6)  | \
-     (((b2) &3) << 4)  | \
-     (((b1) &3) << 2)  | \
-     (((b0) &3)))
-#endif /* _MISRA_RULES */
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF     /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00     /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000     /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000     /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-
-/* for legacy compatibility */
-
-#ifdef _MISRA_RULES
-#define WLS(x)  (((x)-5u) & 0x03u) /* Word Length Select */
-#else
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#endif /* _MISRA_RULES */
-#define W1LMAX_MAX W1LMAX_MIN
-#define EBIU_AMCBCTL0 EBIU_AMBCTL0
-#define EBIU_AMCBCTL1 EBIU_AMBCTL1
-#define PINT0_IRQ PINT0_REQUEST
-#define PINT1_IRQ PINT1_REQUEST
-#define PINT2_IRQ PINT2_REQUEST
-#define PINT3_IRQ PINT3_REQUEST
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                */
-#define WDSIZE_8        0x0000          /* Transfer Word Size = 8 */
-#define WDSIZE_16       0x0004          /* Transfer Word Size = 16 */
-#define WDSIZE_32       0x0008          /* Transfer Word Size = 32 */
-#define NDSIZE_0        0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1        0x0100          /* Next Descriptor Size = 1 */
-#define NDSIZE_2        0x0200          /* Next Descriptor Size = 2 */
-#define NDSIZE_3        0x0300          /* Next Descriptor Size = 3 */
-#define NDSIZE_4        0x0400          /* Next Descriptor Size = 4 */
-#define NDSIZE_5        0x0500          /* Next Descriptor Size = 5 */
-#define NDSIZE_6        0x0600          /* Next Descriptor Size = 6 */
-#define NDSIZE_7        0x0700          /* Next Descriptor Size = 7 */
-#define NDSIZE_8        0x0800          /* Next Descriptor Size = 8 */
-#define NDSIZE_9        0x0900          /* Next Descriptor Size = 9 */
-
-#ifdef _MISRA_RULES
-#define SET_NDSIZE(x)   (((x)&0xFu)<<8)
-#else
-#define SET_NDSIZE(x)   (((x)&0xF)<<8)
-#endif
-                                        /* NDSIZE[3:0] (Flex Descriptor Size)
-                                            Size of next descriptor
-                                            0000 - Required if in Stop or Autobuffer mode
-                                            0001 - 1001 - Descriptor size
-                                            1010 - 1111 - Reserved */
-#define FLOW_STOP       0x0000          /* Stop Mode */
-#define FLOW_AUTO       0x1000          /* Autobuffer Mode */
-#define FLOW_ARRAY      0x4000          /* Descriptor Array Mode */
-#define FLOW_SMALL      0x6000          /* Small Model Descriptor List Mode */
-#define FLOW_LARGE      0x7000          /* Large Model Descriptor List Mode */
-
-
-/* ********************* PLL AND RESET MASKS ************************ */
-/* SWRST Mask */
-#define SYSTEM_RESET    0x0007          /* Initiates A System Software Reset */
-#define DOUBLE_FAULT    0x0008          /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE    0x2000          /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG      0x4000          /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE  0x8000          /* SW Reset Occurred Since Last Read Of SWRST */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET,
-PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER */
-
-#define nPA0 0x0
-#define nPA1 0x0
-#define nPA2 0x0
-#define nPA3 0x0
-#define nPA4 0x0
-#define nPA5 0x0
-#define nPA6 0x0
-#define nPA7 0x0
-#define nPA8 0x0
-#define nPA9 0x0
-#define nPA10 0x0
-#define nPA11 0x0
-#define nPA12 0x0
-#define nPA13 0x0
-#define nPA14 0x0
-#define nPA15 0x0
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET,
-PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER */
-
-#define nPB0 0x0
-#define nPB1 0x0
-#define nPB2 0x0
-#define nPB3 0x0
-#define nPB4 0x0
-#define nPB5 0x0
-#define nPB6 0x0
-#define nPB7 0x0
-#define nPB8 0x0
-#define nPB9 0x0
-#define nPB10 0x0
-#define nPB11 0x0
-#define nPB12 0x0
-#define nPB13 0x0
-#define nPB14 0x0
-#define nPB15 0x0
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET,
-PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER */
-
-#define nPD0 0x0
-#define nPD1 0x0
-#define nPD2 0x0
-#define nPD3 0x0
-#define nPD4 0x0
-#define nPD5 0x0
-#define nPD6 0x0
-#define nPD7 0x0
-#define nPD8 0x0
-#define nPD9 0x0
-#define nPD10 0x0
-#define nPD11 0x0
-#define nPD12 0x0
-#define nPD13 0x0
-#define nPD14 0x0
-#define nPD15 0x0
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET,
-PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER */
-
-#define nPE0 0x0
-#define nPE1 0x0
-#define nPE2 0x0
-#define nPE3 0x0
-#define nPE4 0x0
-#define nPE5 0x0
-#define nPE6 0x0
-#define nPE7 0x0
-#define nPE8 0x0
-#define nPE9 0x0
-#define nPE10 0x0
-#define nPE11 0x0
-#define nPE12 0x0
-#define nPE13 0x0
-#define nPE14 0x0
-#define nPE15 0x0
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET,
-PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER */
-
-#define nPF0 0x0
-#define nPF1 0x0
-#define nPF2 0x0
-#define nPF3 0x0
-#define nPF4 0x0
-#define nPF5 0x0
-#define nPF6 0x0
-#define nPF7 0x0
-#define nPF8 0x0
-#define nPF9 0x0
-#define nPF10 0x0
-#define nPF11 0x0
-#define nPF12 0x0
-#define nPF13 0x0
-#define nPF14 0x0
-#define nPF15 0x0
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET,
-PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER */
-#define nPG0 0x0
-#define nPG1 0x0
-#define nPG2 0x0
-#define nPG3 0x0
-#define nPG4 0x0
-#define nPG5 0x0
-#define nPG6 0x0
-#define nPG7 0x0
-#define nPG8 0x0
-#define nPG9 0x0
-#define nPG10 0x0
-#define nPG11 0x0
-#define nPG12 0x0
-#define nPG13 0x0
-#define nPG14 0x0
-#define nPG15 0x0
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET,
-PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER */
-#define nPH0 0x0
-#define nPH1 0x0
-#define nPH2 0x0
-#define nPH3 0x0
-#define nPH4 0x0
-#define nPH5 0x0
-#define nPH6 0x0
-#define nPH7 0x0
-#define nPH8 0x0
-#define nPH9 0x0
-#define nPH10 0x0
-#define nPH11 0x0
-#define nPH12 0x0
-#define nPH13 0x0
-#define nPH14 0x0
-#define nPH15 0x0
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET,
-PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER */
-#define nPI0 0x0
-#define nPI1 0x0
-#define nPI2 0x0
-#define nPI3 0x0
-#define nPI4 0x0
-#define nPI5 0x0
-#define nPI6 0x0
-#define nPI7 0x0
-#define nPI8 0x0
-#define nPI9 0x0
-#define nPI10 0x0
-#define nPI11 0x0
-#define nPI12 0x0
-#define nPI13 0x0
-#define nPI14 0x0
-#define nPI15 0x0
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET,
-PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER */
-#define nPJ0 0x0
-#define nPJ1 0x0
-#define nPJ2 0x0
-#define nPJ3 0x0
-#define nPJ4 0x0
-#define nPJ5 0x0
-#define nPJ6 0x0
-#define nPJ7 0x0
-#define nPJ8 0x0
-#define nPJ9 0x0
-#define nPJ10 0x0
-#define nPJ11 0x0
-#define nPJ12 0x0
-#define nPJ13 0x0
-#define nPJ14 0x0
-#define nPJ15 0x0
-
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                     */
-
-/* SIC_IMASKx Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
-#define SIC_UNMASK_ALL 0x00000000         /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL   0xFFFFFFFF         /* Mask all peripheral interrupts   */
-
-/* SIC_IMASKx Macros */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F))     /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000        /* Wakeup Disable all peripherals   */
-#define IWR_ENABLE_ALL  0xFFFFFFFF        /* Wakeup Enable all peripherals    */
-
-/* SIC_IWR Macros */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-#define PIVG(PNr, IVGNr) ( (IVGNr) - 7) << ( ((PNr)%8) * 4) /* Peripheral #PNr assigned IVG #IVGNr  */
-/* Rx.L = lo(PIVG(62,10)); */
-/* Rx.H = hi(PIVG(62,10)); */
-/* PNr = 0 to 95 */
-/* IVGNr = 7 to 15 */
-
-/* SIC_IAR0 Macros */
-#define P0_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #0 assigned IVG #x    */
-#define P1_IVG(x)       (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #1 assigned IVG #x    */
-#define P2_IVG(x)       (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #2 assigned IVG #x    */
-#define P3_IVG(x)       (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #3 assigned IVG #x    */
-#define P4_IVG(x)       (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #4 assigned IVG #x    */
-#define P5_IVG(x)       (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #5 assigned IVG #x    */
-#define P6_IVG(x)       (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #6 assigned IVG #x    */
-#define P7_IVG(x)       (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #7 assigned IVG #x    */
-
-/* SIC_IAR1 Macros */
-#define P8_IVG(x)       (((x)&_MF15)-_MF7)           /* Peripheral #8 assigned IVG #x    */
-#define P9_IVG(x)       (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #9 assigned IVG #x    */
-#define P10_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #10 assigned IVG #x   */
-#define P11_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #11 assigned IVG #x   */
-#define P12_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #12 assigned IVG #x   */
-#define P13_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #13 assigned IVG #x   */
-#define P14_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #14 assigned IVG #x   */
-#define P15_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #15 assigned IVG #x   */
-
-/* SIC_IAR2 Macros */
-#define P16_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #16 assigned IVG #x   */
-#define P17_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #17 assigned IVG #x   */
-#define P18_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #18 assigned IVG #x   */
-#define P19_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #19 assigned IVG #x   */
-#define P20_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #20 assigned IVG #x   */
-#define P21_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #21 assigned IVG #x   */
-#define P22_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #22 assigned IVG #x   */
-#define P23_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #23 assigned IVG #x   */
-
-/* SIC_IAR3 Macros */
-#define P24_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #24 assigned IVG #x   */
-#define P25_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #25 assigned IVG #x   */
-#define P26_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #26 assigned IVG #x   */
-#define P27_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #27 assigned IVG #x   */
-#define P28_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #28 assigned IVG #x   */
-#define P29_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #29 assigned IVG #x   */
-#define P30_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #30 assigned IVG #x   */
-#define P31_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #31 assigned IVG #x   */
-
-/* SIC_IAR4 Macros */
-#define P32_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #32 assigned IVG #x   */
-#define P33_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #33 assigned IVG #x   */
-#define P34_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #34 assigned IVG #x   */
-#define P35_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #35 assigned IVG #x   */
-#define P36_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #36 assigned IVG #x   */
-#define P37_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #37 assigned IVG #x   */
-#define P38_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #38 assigned IVG #x   */
-#define P39_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #39 assigned IVG #x   */
-
-/* SIC_IAR4 Macros */
-#define P40_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #40 assigned IVG #x   */
-#define P41_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #41 assigned IVG #x   */
-#define P42_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #42 assigned IVG #x   */
-#define P43_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #43 assigned IVG #x   */
-#define P44_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #44 assigned IVG #x   */
-#define P45_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #45 assigned IVG #x   */
-#define P46_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #46 assigned IVG #x   */
-#define P47_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #47 assigned IVG #x   */
-
-/* SIC_IAR5 Macros */
-#define P48_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #48 assigned IVG #x   */
-#define P49_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #49 assigned IVG #x   */
-#define P50_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #50 assigned IVG #x   */
-#define P51_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #51 assigned IVG #x   */
-#define P52_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #52 assigned IVG #x   */
-#define P53_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #53 assigned IVG #x   */
-#define P54_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #54 assigned IVG #x   */
-#define P55_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #55 assigned IVG #x   */
-
-/* SIC_IAR5 Macros */
-#define P56_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #56 assigned IVG #x   */
-#define P57_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #57 assigned IVG #x   */
-#define P58_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #58 assigned IVG #x   */
-#define P59_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #59 assigned IVG #x   */
-#define P60_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #60 assigned IVG #x   */
-#define P61_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #61 assigned IVG #x   */
-#define P62_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #62 assigned IVG #x   */
-#define P63_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #63 assigned IVG #x   */
-
-/* SIC_IAR6 Macros */
-#define P64_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #64 assigned IVG #x   */
-#define P65_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #65 assigned IVG #x   */
-#define P66_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #66 assigned IVG #x   */
-#define P67_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #67 assigned IVG #x   */
-#define P68_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #68 assigned IVG #x   */
-#define P69_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #69 assigned IVG #x   */
-#define P70_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #70 assigned IVG #x   */
-#define P71_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #71 assigned IVG #x   */
-
-/* SIC_IAR7 Macros */
-#define P72_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #72 assigned IVG #x   */
-#define P73_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #73 assigned IVG #x   */
-#define P74_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #74 assigned IVG #x   */
-#define P75_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #75 assigned IVG #x   */
-#define P76_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #76 assigned IVG #x   */
-#define P77_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #77 assigned IVG #x   */
-#define P78_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #78 assigned IVG #x   */
-#define P79_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #79 assigned IVG #x   */
-
-/* SIC_IAR8 Macros */
-#define P80_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #80 assigned IVG #x   */
-#define P81_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #81 assigned IVG #x   */
-#define P82_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #82 assigned IVG #x   */
-#define P83_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #83 assigned IVG #x   */
-#define P84_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #84 assigned IVG #x   */
-#define P85_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #85 assigned IVG #x   */
-#define P86_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #86 assigned IVG #x   */
-#define P87_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #87 assigned IVG #x   */
-
-/* SIC_IAR9 Macros */
-#define P88_IVG(x)      (((x)&_MF15)-_MF7)           /* Peripheral #88 assigned IVG #x   */
-#define P89_IVG(x)      (((x)&_MF15)-_MF7) << 0x4    /* Peripheral #89 assigned IVG #x   */
-#define P90_IVG(x)      (((x)&_MF15)-_MF7) << 0x8    /* Peripheral #90 assigned IVG #x   */
-#define P91_IVG(x)      (((x)&_MF15)-_MF7) << 0xC    /* Peripheral #91 assigned IVG #x   */
-#define P92_IVG(x)      (((x)&_MF15)-_MF7) << 0x10   /* Peripheral #92 assigned IVG #x   */
-#define P93_IVG(x)      (((x)&_MF15)-_MF7) << 0x14   /* Peripheral #93 assigned IVG #x   */
-#define P94_IVG(x)      (((x)&_MF15)-_MF7) << 0x18   /* Peripheral #94 assigned IVG #x   */
-#define P95_IVG(x)      (((x)&_MF15)-_MF7) << 0x1C   /* Peripheral #95 assigned IVG #x   */
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-
-/* Bit masks for SPIx_CTL */
-#define RDBR_CORE   0x0         /* RDBR Read Initiates, IRQ when RDBR Full */
-#define TDBR_CORE   0x1         /* TDBR Write Initiates, IRQ when TDBR Empty */
-#define RDBR_DMA    0x2         /* DMA Read, DMA Until FIFO Empty */
-#define TDBR_DMA    0x3         /* DMA Write, DMA Until FIFO Full */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-
-/* Bit macros for TWIx_CONTROL */
-#define SET_TWI_PRESCALE(x)     ( (x) & PRESCALE )
-#define SET_TWI_DCNT(x)         ( ((x) << 0x6) & DCNT )
-
-/* Bit masks for TWIx_INT_MASK */
-#define SCLIM       0x8000      /* Serial Clock Interrupt */
-#define nSCLIM      0x0
-#define SDAIM       0x4000      /* Serial Data Interrupt */
-#define nSDAIM      0x0
-
-/* Bit masks for TWIx_INT_STAT */
-#define SCLI        0x8000      /* Serial Clock Interrupt */
-#define nSCLI       0x0
-#define SDAI        0x4000      /* Serial Data Interrupt */
-#define nSDAI       0x0
-
-/* Bit macros for TWIx_MASTER_ADDR */
-#define SET_TWI_ADDR(x)         ( (x) & 0x7F )
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define SET_WDEV(x)     (((x)<<1) & 0x0006u)     /* event generated on roll over */
-#else
-#define SET_WDEV(x)     (((x)<<1) & 0x0006)     /* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET      0x0000                  /* generate reset event on roll over */
-#define nWDEV_RESET     0x0
-#define WDEV_NMI        0x0002                  /* generate NMI event on roll over */
-#define nWDEV_NMI       0x0
-#define WDEV_GPI        0x0004                  /* generate GP IRQ on roll over */
-#define nWDEV_GPI       0x0
-#define WDEV_NONE       0x0006                  /* no event on roll over */
-#define WDDIS           0x0AD0                  /* disable watchdog */
-
-/* RTC_SWCNT (RTC stopwatch count) Macros */
-#define SET_SWCNT(x)    (x)
-
-/* RTC_PREN Register Masks */
-#define ENABLE_PRESCALE             PREN        /* Enable prescaler so RTC runs at 1 Hz */
-
-/* RTC_ALARM Macro: z=day, y=hr, x=min, w=sec */
-#ifdef _MISRA_RULES
-#define SET_ALARM(z,y,x,w)  ((((z)&0x7FFFu)<<0x11)|(((y)&0x1Fu)<<0xC)|(((x)&0x3Fu)<<0x6)|((w)&0x3Fu))
-#else
-#define SET_ALARM(z,y,x,w)  ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-#endif /* _MISRA_RULES */
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
-#define UARTDLL      0x00FF   /* Divisor Latch Low Byte */
-#define UARTDLH      0xFF00   /* Divisor Latch High Byte */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* CNT_COMMAND bit field options */
-#define nW1LCNT_ZERO    0x0
-#define nW1LCNT_MIN     0x0
-#define nW1LCNT_MAX     0x0
-
-#define nW1LMIN_ZERO    0x0
-#define nW1LMIN_CNT     0x0
-#define nW1LMIN_MAX     0x0
-
-#define nW1LMAX_ZERO    0x0
-#define nW1LMAX_CNT     0x0
-#define nW1LMAX_MIN     0x0
-
-#define W1ZMONCE        0x1000          /* write on to enable single zero marker. clear CNT_COUNT action (W1A/R) */
-#define nW1ZMONCE       0x0
-
-/* Bit macros for CNT_DEBOUNCE */
-#ifdef _MISRA_RULES
-#define SET_DPRESCALE(x)   ((x)&0x7u)    /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
-#else
-#define SET_DPRESCALE(x)   ((x)&0x7)    /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
-#endif /* _MISRA_RULES */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define                     MCMEM  MCMEN
-#define                    nMCMEM  0x0
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF54X_H */
-
diff --git a/libgloss/bfin/include/defBF561.h b/libgloss/bfin/include/defBF561.h
deleted file mode 100644
index 38786b342..000000000
--- a/libgloss/bfin/include/defBF561.h
+++ /dev/null
@@ -1,1865 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defBF561.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-
-#if !defined(__ADSPBF561__)
-#warning defBF561.h should only be included for BF561 chip.
-#endif
-/* include all Core registers and bit definitions */
-#include <def_LPBlackfin.h>
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
-#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
-#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock Count register (16-bit) */
-#define CHIPID                  0xFFC00014      /* Device ID Register */
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SICA_SWRST              0xFFC00100      /* Software Reset register */
-#define SICA_SYSCR              0xFFC00104      /* System Reset Configuration register */
-#define SICA_RVECT              0xFFC00108      /* SIC Reset Vector Address Register */
-#define SICA_IMASK              0xFFC0010C      /* SIC Interrupt Mask register 0 - hack to fix old tests */
-#define SICA_IMASK0             0xFFC0010C      /* SIC Interrupt Mask register 0 */
-#define SICA_IMASK1             0xFFC00110      /* SIC Interrupt Mask register 1 */
-#define SICA_IAR0               0xFFC00124      /* SIC Interrupt Assignment Register 0 */
-#define SICA_IAR1               0xFFC00128      /* SIC Interrupt Assignment Register 1 */
-#define SICA_IAR2               0xFFC0012C      /* SIC Interrupt Assignment Register 2 */
-#define SICA_IAR3               0xFFC00130      /* SIC Interrupt Assignment Register 3 */
-#define SICA_IAR4               0xFFC00134      /* SIC Interrupt Assignment Register 4 */
-#define SICA_IAR5               0xFFC00138      /* SIC Interrupt Assignment Register 5 */
-#define SICA_IAR6               0xFFC0013C      /* SIC Interrupt Assignment Register 6 */
-#define SICA_IAR7               0xFFC00140      /* SIC Interrupt Assignment Register 7 */
-#define SICA_ISR0               0xFFC00114      /* SIC Interrupt Status register 0 */
-#define SICA_ISR1               0xFFC00118      /* SIC Interrupt Status register 1 */
-#define SICA_IWR0               0xFFC0011C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICA_IWR1               0xFFC00120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST              0xFFC01100      /* reserved */
-#define SICB_SYSCR              0xFFC01104      /* reserved */
-#define SICB_RVECT              0xFFC01108      /* SIC Reset Vector Address Register */
-#define SICB_IMASK0             0xFFC0110C      /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1             0xFFC01110      /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0               0xFFC01124      /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1               0xFFC01128      /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2               0xFFC0112C      /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3               0xFFC01130      /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4               0xFFC01134      /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5               0xFFC01138      /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6               0xFFC0113C      /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7               0xFFC01140      /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0               0xFFC01114      /* SIC Interrupt Status register 0 */
-#define SICB_ISR1               0xFFC01118      /* SIC Interrupt Status register 1 */
-#define SICB_IWR0               0xFFC0111C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1               0xFFC01120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL 				0xFFC00200 		/* Watchdog Control register */
-#define WDOGA_CNT 				0xFFC00204 		/* Watchdog Count register */
-#define WDOGA_STAT 				0xFFC00208 		/* Watchdog Status register */
-
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL 				0xFFC01200 		/* Watchdog Control register */
-#define WDOGB_CNT 				0xFFC01204 		/* Watchdog Count register */
-#define WDOGB_STAT 				0xFFC01208 		/* Watchdog Status register */
-
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR             	0xFFC00400  /* Transmit Holding register */
-#define UART_RBR             	0xFFC00400  /* Receive Buffer register */
-#define UART_DLL              	0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART_IER              	0xFFC00404  /* Interrupt Enable Register */
-#define UART_DLH              	0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART_IIR              	0xFFC00408  /* Interrupt Identification Register */
-#define UART_LCR              	0xFFC0040C  /* Line Control Register */
-#define UART_MCR			 	0xFFC00410  /* Modem Control Register */
-#define UART_LSR              	0xFFC00414  /* Line Status Register */
-#define UART_SCR              	0xFFC0041C  /* SCR Scratch Register */
-#define UART_GCTL      	      	0xFFC00424  /* Global Control Register */
-
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI_CTL               		0xFFC00500  /* SPI Control Register */
-#define SPI_FLG               		0xFFC00504  /* SPI Flag register */
-#define SPI_STAT              		0xFFC00508  /* SPI Status register */
-#define SPI_TDBR              		0xFFC0050C  /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR              		0xFFC00510  /* SPI Receive Data Buffer Register */
-#define SPI_BAUD              		0xFFC00514  /* SPI Baud rate Register */
-#define SPI_SHADOW            		0xFFC00518  /* SPI_RDBR Shadow Register */
-
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG 				0xFFC00600 /* Timer0 Configuration register */
-#define TIMER0_COUNTER 				0xFFC00604 /* Timer0 Counter register */
-#define TIMER0_PERIOD 				0xFFC00608 /* Timer0 Period register */
-#define TIMER0_WIDTH 				0xFFC0060C /* Timer0 Width register */
-
-#define TIMER1_CONFIG 				0xFFC00610 /* Timer1 Configuration register */
-#define TIMER1_COUNTER 				0xFFC00614 /* Timer1 Counter register */
-#define TIMER1_PERIOD 				0xFFC00618 /* Timer1 Period register */
-#define TIMER1_WIDTH 				0xFFC0061C /* Timer1 Width register */
-
-#define TIMER2_CONFIG 				0xFFC00620 /* Timer2 Configuration register */
-#define TIMER2_COUNTER 				0xFFC00624 /* Timer2 Counter register */
-#define TIMER2_PERIOD 				0xFFC00628 /* Timer2 Period register */
-#define TIMER2_WIDTH 				0xFFC0062C /* Timer2 Width register */
-
-#define TIMER3_CONFIG 				0xFFC00630 /* Timer3 Configuration register */
-#define TIMER3_COUNTER 				0xFFC00634 /* Timer3 Counter register */
-#define TIMER3_PERIOD 				0xFFC00638 /* Timer3 Period register */
-#define TIMER3_WIDTH 				0xFFC0063C /* Timer3 Width register */
-
-#define TIMER4_CONFIG 				0xFFC00640 /* Timer4 Configuration register */
-#define TIMER4_COUNTER 				0xFFC00644 /* Timer4 Counter register */
-#define TIMER4_PERIOD 				0xFFC00648 /* Timer4 Period register */
-#define TIMER4_WIDTH 				0xFFC0064C /* Timer4 Width register */
-
-#define TIMER5_CONFIG 				0xFFC00650 /* Timer5 Configuration register */
-#define TIMER5_COUNTER 				0xFFC00654 /* Timer5 Counter register */
-#define TIMER5_PERIOD 				0xFFC00658 /* Timer5 Period register */
-#define TIMER5_WIDTH 				0xFFC0065C /* Timer5 Width register */
-
-#define TIMER6_CONFIG 				0xFFC00660 /* Timer6 Configuration register */
-#define TIMER6_COUNTER 				0xFFC00664 /* Timer6 Counter register */
-#define TIMER6_PERIOD 				0xFFC00668 /* Timer6 Period register */
-#define TIMER6_WIDTH 				0xFFC0066C /* Timer6 Width register */
-
-#define TIMER7_CONFIG 				0xFFC00670 /* Timer7 Configuration register */
-#define TIMER7_COUNTER 				0xFFC00674 /* Timer7 Counter register */
-#define TIMER7_PERIOD 				0xFFC00678 /* Timer7 Period register */
-#define TIMER7_WIDTH 				0xFFC0067C /* Timer7 Width register */
-
-#define TMRS8_ENABLE 				0xFFC00680 /* Timer Enable Register */
-#define TMRS8_DISABLE 				0xFFC00684 /* Timer Disable register */
-#define TMRS8_STATUS 				0xFFC00688 /* Timer Status register */
-
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG 				0xFFC01600 /* Timer8 Configuration register */
-#define TIMER8_COUNTER 				0xFFC01604 /* Timer8 Counter register */
-#define TIMER8_PERIOD 				0xFFC01608 /* Timer8 Period register */
-#define TIMER8_WIDTH 				0xFFC0160C /* Timer8 Width register */
-
-#define TIMER9_CONFIG 				0xFFC01610 /* Timer9 Configuration register */
-#define TIMER9_COUNTER 				0xFFC01614 /* Timer9 Counter register */
-#define TIMER9_PERIOD 				0xFFC01618 /* Timer9 Period register */
-#define TIMER9_WIDTH 				0xFFC0161C /* Timer9 Width register */
-
-#define TIMER10_CONFIG 				0xFFC01620 /* Timer10 Configuration register */
-#define TIMER10_COUNTER 			0xFFC01624 /* Timer10 Counter register */
-#define TIMER10_PERIOD 				0xFFC01628 /* Timer10 Period register */
-#define TIMER10_WIDTH 				0xFFC0162C /* Timer10 Width register */
-
-#define TIMER11_CONFIG 				0xFFC01630 /* Timer11 Configuration register */
-#define TIMER11_COUNTER 			0xFFC01634 /* Timer11 Counter register */
-#define TIMER11_PERIOD 				0xFFC01638 /* Timer11 Period register */
-#define TIMER11_WIDTH 				0xFFC0163C /* Timer11 Width register */
-
-#define TMRS4_ENABLE 				0xFFC01640 /* Timer Enable Register */
-#define TMRS4_DISABLE 				0xFFC01644 /* Timer Disable register */
-#define TMRS4_STATUS 				0xFFC01648 /* Timer Status register */
-
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D 				0xFFC00700 /* Flag Data register */
-#define FIO0_FLAG_C 				0xFFC00704 /* Flag Clear register */
-#define FIO0_FLAG_S 				0xFFC00708 /* Flag Set register */
-#define FIO0_FLAG_T 				0xFFC0070C /* Flag Toggle register */
-#define FIO0_MASKA_D 				0xFFC00710 /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C 				0xFFC00714 /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S 				0xFFC00718 /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T 				0xFFC0071C /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D 				0xFFC00720 /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C 				0xFFC00724 /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S 				0xFFC00728 /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T 				0xFFC0072C /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR 					0xFFC00730 /* Flag Direction register */
-#define FIO0_POLAR 					0xFFC00734 /* Flag Polarity register */
-#define FIO0_EDGE 					0xFFC00738 /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH 					0xFFC0073C /* Flag Set on Both Edges register */
-#define FIO0_INEN 					0xFFC00740 /* Flag Input Enable register */
-
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D 				0xFFC01500 /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C 				0xFFC01504 /* Flag Clear register */
-#define FIO1_FLAG_S 				0xFFC01508 /* Flag Set register */
-#define FIO1_FLAG_T 				0xFFC0150C /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D 				0xFFC01510 /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C 				0xFFC01514 /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S 				0xFFC01518 /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T 				0xFFC0151C /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D 				0xFFC01520 /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C 				0xFFC01524 /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S 				0xFFC01528 /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T 				0xFFC0152C /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR 					0xFFC01530 /* Flag Direction register */
-#define FIO1_POLAR 					0xFFC01534 /* Flag Polarity register */
-#define FIO1_EDGE 					0xFFC01538 /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH 					0xFFC0153C /* Flag Set on Both Edges register */
-#define FIO1_INEN 					0xFFC01540 /* Flag Input Enable register */
-
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D 				0xFFC01700 /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C 				0xFFC01704 /* Flag Clear register */
-#define FIO2_FLAG_S 				0xFFC01708 /* Flag Set register */
-#define FIO2_FLAG_T 				0xFFC0170C /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D 				0xFFC01710 /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C 				0xFFC01714 /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S 				0xFFC01718 /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T 				0xFFC0171C /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D 				0xFFC01720 /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C 				0xFFC01724 /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S 				0xFFC01728 /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T 				0xFFC0172C /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR 					0xFFC01730 /* Flag Direction register */
-#define FIO2_POLAR 					0xFFC01734 /* Flag Polarity register */
-#define FIO2_EDGE 					0xFFC01738 /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH 					0xFFC0173C /* Flag Set on Both Edges register */
-#define FIO2_INEN 					0xFFC01740 /* Flag Input Enable register */
-
-
-/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1     	 	0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2      	 	0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV        		0xFFC00808  /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV          		0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX	             	0xFFC00810  /* SPORT0 TX Data Register */
-#define SPORT0_RX	            	0xFFC00818  /* SPORT0 RX Data Register */
-#define SPORT0_RCR1      	 		0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2      	 		0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV        		0xFFC00828  /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV          		0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT            		0xFFC00830  /* SPORT0 Status Register */
-#define SPORT0_CHNL            		0xFFC00834  /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1           		0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2           		0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0           		0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1           		0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2           		0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3           		0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0           		0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1           		0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2           		0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3           		0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1     	 		0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2      	 		0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV        		0xFFC00908  /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV          		0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX	             	0xFFC00910  /* SPORT1 TX Data Register */
-#define SPORT1_RX	            	0xFFC00918  /* SPORT1 RX Data Register */
-#define SPORT1_RCR1      	 		0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2      	 		0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV        		0xFFC00928  /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV          		0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT            		0xFFC00930  /* SPORT1 Status Register */
-#define SPORT1_CHNL            		0xFFC00934  /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1           		0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2           		0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0           		0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1           		0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2           		0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3           		0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0           		0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1           		0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2           		0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3           		0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* Asynchronous Memory Controller - External Bus Interface Unit  */
-#define EBIU_AMGCTL					0xFFC00A00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0				0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1				0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
-
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL					0xFFC00A10  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL					0xFFC00A14  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC 					0xFFC00A18  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT					0xFFC00A1C  /* SDRAM Status Register */
-
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL 				0xFFC01000 /* PPI0 Control register */
-#define PPI0_STATUS 				0xFFC01004 /* PPI0 Status register */
-#define PPI0_COUNT 					0xFFC01008 /* PPI0 Transfer Count register */
-#define PPI0_DELAY 					0xFFC0100C /* PPI0 Delay Count register */
-#define PPI0_FRAME 					0xFFC01010 /* PPI0 Frame Length register */
-
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL 				0xFFC01300 /* PPI1 Control register */
-#define PPI1_STATUS 				0xFFC01304 /* PPI1 Status register */
-#define PPI1_COUNT 					0xFFC01308 /* PPI1 Transfer Count register */
-#define PPI1_DELAY 					0xFFC0130C /* PPI1 Delay Count register */
-#define PPI1_FRAME 					0xFFC01310 /* PPI1 Frame Length register */
-
-
-/*DMA traffic control registers */
-#define	DMA1_TC_PER  0xFFC01B0C	/* Traffic control periods */
-#define	DMA1_TC_CNT  0xFFC01B10	/* Traffic control current counts */
-#define	DMA2_TC_PER  0xFFC00B0C	/* Traffic control periods */
-#define	DMA2_TC_CNT  0xFFC00B10	/* Traffic control current counts	 */
-
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
-
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
-
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
-
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN              	0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         	0x0001  /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                	0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF             	0x0008  /* Core clock off */
-#define ALT_TIMING		0x0010  /* Enable Alternate PPI Timing */
-#define PDWN                   	0x0020  /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 	0x0100  /* Bypass the PLL */
-#define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors */
-#define IN_DELAY                0x0040  /* Add 200ps Delay on EBIU Inputs */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay on EBIU Outputs */
-#define SPORT_HYS               0x8000  /* Add 250mV Hysteresis to SPORT Inputs */
-
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x)    (((x)&0x3Fu) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#else
-#define SET_MSEL(x)    (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL         0x000F      /* System Select */
-#define CSEL         0x0030      /* Core Select */
-#define SCLK_DIV(x)  (x)		   /* SCLK = VCO / x */
-
-/* PLL_DIV Macros */
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)  ((x)&0xFu)    /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#else
-#define SET_SSEL(x)  ((x)&0xF)    /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
-#endif /* _MISRA_RULES */
-
-/* PLL_STAT Macros */
-#define VSTAT       0x0080   /* Voltage Regulator Status: Regulator at programmed voltage */
-#define CORE_IDLE   0x0040   /* processor is in the IDLE operating mode */
-#define PLL_LOCKED  0x0020   /* PLL_LOCKCNT Has Been Reached */
-#define SLEEP       0x0010   /* processor is in the Sleep operating mode */
-#define DEEP_SLEEP  0x0008   /* processor is in the Deep Sleep operating mode */
-#define ACTIVE_PLLDISABLED   0x0004   /* Processor In Active Mode With PLL Disabled */
-#define FULL_ON               0x0002  /* Processor In Full On Mode */
-#define ACTIVE_PLLENABLED     0x0001              /* Processor In Active Mode With PLL Enabled */
-
-
-#define CCLK_DIV1              0x00000000  /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010  /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020  /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030  /* CCLK = VCO / 8 */
-
-/* SWRST Mask */
-#define SYSTEM_RESET           0x0007  /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_A      0x0800  /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B      0x1000  /* SWRST Core B Double Fault */
-#define SWRST_WDT_B		       0x2000  /* SWRST Watchdog B */
-#define SWRST_WDT_A		       0x4000  /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x8000  /* SWRST Status */
-
-/* VR_CTL Masks																	*/
-#define	FREQ			0x0003	/* Switching Oscillator Frequency For Regulator	*/
-#define	HIBERNATE		0x0000	/* 	Powerdown/Bypass On-Board Regulation	*/
-#define	FREQ_333		0x0001	/* 	Switching Frequency Is 333 kHz			*/
-#define	FREQ_667		0x0002	/* 	Switching Frequency Is 667 kHz			*/
-#define	FREQ_1000		0x0003	/* 	Switching Frequency Is 1 MHz			*/
-#define  WAKE        0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
-#define  SCKELOW     0x8000  /* Enable Drive CKE Low During Reset */
-
-
-#define GAIN			0x000C	/* Voltage Level Gain	*/
-#define	GAIN_5			0x0000	/* 	GAIN = 5		*/
-#define	GAIN_10			0x0004	/* 	GAIN = 10		*/
-#define	GAIN_20			0x0008	/* 	GAIN = 20		*/
-#define	GAIN_50			0x000C	/* 	GAIN = 50		*/
-
-#define	VLEV			0x00F0	/* Internal Voltage Level - Only Program Values Within Specifications	*/
-#define	VLEV_085 		0x0060	/* 	VLEV = 0.85 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_090		0x0070	/* 	VLEV = 0.90 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_095		0x0080	/* 	VLEV = 0.95 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_100		0x0090	/* 	VLEV = 1.00 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_105		0x00A0	/* 	VLEV = 1.05 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_110		0x00B0	/* 	VLEV = 1.10 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_115		0x00C0	/* 	VLEV = 1.15 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_120		0x00D0	/* 	VLEV = 1.20 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_125		0x00E0	/* 	VLEV = 1.25 V (See Datasheet for Regulator Tolerance)	*/
-#define	VLEV_130		0x00F0	/* 	VLEV = 1.30 V (See Datasheet for Regulator Tolerance)	*/
-
-/* SYSCR Masks */
-#define BMODE_BYPASS  0x0000  /* Bypass boot ROM, execute from 16-bit external memory */
-#define BMODE_FLASH   0x0001  /* Use Boot ROM to load from 8-bit or 16-bit flash */
-#define BMODE_SPIHOST 0x0002  /* Boot from SPI0 host (slave mode) */
-#define BMODE_SPIMEM  0x0003  /* Boot from serial SPI memory */
-
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks	 */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15   */
-#define Peripheral_IVG(Per_number, IVG_number)    \
-				( (IVG_number) -7) << ( ((Per_number)%8) *4) 	   /* Peripheral #Per_number assigned IVG #IVG_number  */
-																   /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
-																   /*        r0.h = hi(Peripheral_IVG(62, 10)); */
-
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
-#define SIC_UNMASK_ALL 0x00000000         /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL   0xFFFFFFFF         /* Mask all peripheral interrupts   */
-
-/* SIC_IMASKx Macros */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x) ((int32_t)1 << ((x)&0x1Fu))  /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Unmask Peripheral #x interrupt*/
-#else
-#define SIC_MASK(x) (1 << ((x)&0x1F))     /* Mask Peripheral #x interrupt  */
-#define SIC_UNMASK(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL 0x00000000        /* Wakeup Disable all peripherals   */
-#define IWR_ENABLE_ALL  0xFFFFFFFF        /* Wakeup Enable all peripherals    */
-
-/* SIC_IWR Macros */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   ((int32_t)1 << ((x)&0x1Fu))  /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ ((uint32_t)1 << ((x)&0x1Fu)))  /*Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x   */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))  /* Wakeup Disable Peripheral #x  */
-#endif /* _MISRA_RULES */
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define PLL_WAKEUP_IRQ      0x00000001      /* PLL Wakeup Interrupt Request */
-#define IRQ_PLL_WAKEUP      0x00000001      /* PLL Wakeup Interrupt Request */
-
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#ifdef _MISRA_RULES
-#define WDEV(x) (((x)<<1) & 0x0006u) /* event generated on roll over */
-#else
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#endif /* _MISRA_RULES */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define WDOG_DISABLE  WDDIS
-#define TRO WDRO
-
-
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB	0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN	0x08
-#define STB	0x04
-#ifdef _MISRA_RULES
-#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */
-#else
-#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
-#endif /* _MISRA_RULES */
-
-#define DLAB_P	0x07
-#define SB_P	0x06
-#define STP_P	0x05
-#define EPS_P	0x04
-#define PEN_P	0x03
-#define STB_P	0x02
-#define WLS_P1	0x01
-#define WLS_P0	0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA	0x10	/* Loopback Mode Enable */
-#define LOOP_ENA_P	0x04
-
-/* UART_LSR Register */
-#define TEMT	0x40
-#define THRE	0x20
-#define BI	0x10
-#define FE	0x08
-#define PE	0x04
-#define OE	0x02
-#define DR	0x01
-
-#define TEMP_P	0x06
-#define THRE_P	0x05
-#define BI_P	0x04
-#define FE_P	0x03
-#define PE_P	0x02
-#define OE_P	0x01
-#define DR_P	0x00
-
-/* UART_IER Register */
-#define ELSI	0x04
-#define ETBEI	0x02
-#define ERBFI	0x01
-
-#define ELSI_P	0x02
-#define ETBEI_P	0x01
-#define ERBFI_P	0x00
-
-/* UART_IIR Register */
-#ifdef _MISRA_RULES
-#define STATUS(x)	(((x) << 1) & 0x06u)
-#else
-#define STATUS(x)	(((x) << 1) & 0x06)
-#endif /* _MISRA_RULES */
-#define NINT		0x01
-#define STATUS_P1	0x02
-#define STATUS_P0	0x01
-#define NINT_P		0x00
-
-/* UART_GCTL Register */
-#define FFE	0x20
-#define FPE	0x10
-#define RPOLC	0x08
-#define TPOLC	0x04
-#define IREN	0x02
-#define UCEN	0x01
-
-#define FFE_P	0x05
-#define FPE_P	0x04
-#define RPOLC_P	0x03
-#define TPOLC_P	0x02
-#define IREN_P	0x01
-#define UCEN_P	0x00
-
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001  /* TX enable  */
-#define ITCLK    0x0002  /* Internal TX Clock Select  */
-#define TDTYPE   0x000C  /* TX Data Formatting Select */
-#define TLSBIT   0x0010  /* TX Bit Order */
-#define ITFS     0x0200  /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400  /* TX Frame Sync Required Select  */
-#define DITFS    0x0800  /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000  /* Low TX Frame Sync Select  */
-#define LATFS    0x2000  /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000  /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN	    0x001F  /*TX Word Length  */
-#define TXSE        0x0100  /*TX Secondary Enable */
-#define TSFSE       0x0200  /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400  /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001  /* RX enable  */
-#define IRCLK    0x0002  /* Internal RX Clock Select  */
-#define RDTYPE   0x000C  /* RX Data Formatting Select */
-#define RULAW    0x0008  /* u-Law enable  */
-#define RALAW    0x000C  /* A-Law enable  */
-#define RLSBIT   0x0010  /* RX Bit Order */
-#define IRFS     0x0200  /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400  /* RX Frame Sync Required Select  */
-#define LRFS     0x1000  /* Low RX Frame Sync Select  */
-#define LARFS    0x2000  /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000  /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN	    0x001F  /*RX Word Length  */
-#define RXSE        0x0100  /*RX Secondary Enable */
-#define RSFSE       0x0200  /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400  /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE		0x0001		/*RX FIFO Not Empty Status */
-#define RUVF	    	0x0002  	/*RX Underflow Status */
-#define ROVF		0x0004		/*RX Overflow Status */
-#define TXF		0x0008		/*TX FIFO Full Status */
-#define TUVF         	0x0010  	/*TX Underflow Status */
-#define TOVF         	0x0020  	/*TX Overflow Status */
-#define TXHRE        	0x0040  	/*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define WSIZE		0x0000F000 	/*Multichannel Window Size Field */
-#define WOFF		0x000003FF 	/*Multichannel Window Offset Field */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM		0x00000003 	/*Multichannel Clock Recovery Mode */
-#define MCDTXPE		0x00000004 	/*Multichannel DMA Transmit Packing */
-#define MCDRXPE		0x00000008 	/*Multichannel DMA Receive Packing */
-#define MCMEN		0x00000010 	/*Multichannel Frame Mode Enable */
-#define FSDR		0x00000080 	/*Multichannel Frame Sync to Data Relationship */
-#define MFD		0x0000F000 	/*Multichannel Frame Delay    */
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-
-/*//  PPI_CONTROL Masks         */
-#define PORT_EN              0x00000001  /* PPI Port Enable  */
-#define PORT_DIR             0x00000002  /* PPI Port Direction       */
-#define XFR_TYPE             0x0000000C  /* PPI Transfer Type  */
-#define PORT_CFG             0x00000030  /* PPI Port Configuration */
-#define FLD_SEL              0x00000040  /* PPI Active Field Select */
-#define PACK_EN              0x00000080  /* PPI Packing Mode */
-#define DMA32                0x00000100  /* PPI 32-bit DMA Enable */
-#define SKIP_EN              0x00000200  /* PPI Skip Element Enable */
-#define SKIP_EO              0x00000400  /* PPI Skip Even/Odd Elements */
-#define DLENGTH              0x00003800  /* PPI Data Length  */
-#define DLEN_8		     0x0	     /* PPI Data Length mask for DLEN=8 */
-#ifdef _MISRA_RULES
-#define DLEN(x)	((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x)	((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL                  0x0000C000  /* PPI Signal Polarities       */
-
-
-/*// PPI_STATUS Masks                                          */
-#define FLD	             0x00000400  /* Field Indicator   */
-#define FT_ERR	             0x00000800  /* Frame Track Error */
-#define OVR	             0x00001000  /* FIFO Overflow Error */
-#define UNDR	             0x00002000  /* FIFO Underrun Error */
-#define ERR_DET	      	     0x00004000  /* Error Detected Indicator */
-#define ERR_NCOR	     0x00008000  /* Error Not Corrected Indicator */
-
-/* **********  DMA CONTROLLER MASKS  *********************8 */
-
-/*//DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
-#define DMAEN	        0x00000001  /* Channel Enable */
-#define WNR	   	0x00000002  /* Channel Direction (W/R*) */
-#define WDSIZE_8	0x00000000  /* Word Size 8 bits */
-#define WDSIZE_16	0x00000004  /* Word Size 16 bits */
-#define WDSIZE_32	0x00000008  /* Word Size 32 bits */
-#define DMA2D	        0x00000010  /* 2D/1D* Mode */
-#define RESTART         0x00000020  /* Restart */
-#define DI_SEL	        0x00000040  /* Data Interrupt Select */
-#define DI_EN	        0x00000080  /* Data Interrupt Enable */
-#define NDSIZE	        0x00000900  /* Next Descriptor Size */
-#define FLOW	        0x00007000  /* Flow Control */
-
-
-#define DMAEN_P	            	0  /* Channel Enable */
-#define WNR_P	            	1  /* Channel Direction (W/R*) */
-#define DMA2D_P	        	4  /* 2D/1D* Mode */
-#define RESTART_P	      	5  /* Restart */
-#define DI_SEL_P	     	6  /* Data Interrupt Select */
-#define DI_EN_P	            	7  /* Data Interrupt Enable */
-
-/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE		0x00000001  /* DMA Done Indicator */
-#define DMA_ERR	        	0x00000002  /* DMA Error Indicator */
-#define DFETCH	            	0x00000004  /* Descriptor Fetch Indicator */
-#define DMA_RUN	            	0x00000008  /* DMA Running Indicator */
-
-#define DMA_DONE_P	    	0  /* DMA Done Indicator */
-#define DMA_ERR_P     		1 /* DMA Error Indicator */
-#define DFETCH_P     		2  /* Descriptor Fetch Indicator */
-#define DMA_RUN_P     		3  /* DMA Running Indicator */
-
-/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE	            0x00000040  /* DMA Channel Type Indicator */
-#define CTYPE_P             6       /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8	            0x00000080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16	            0x00000100  /* DMA 16-bit Operation Indicator */
-#define PCAP32	            0x00000200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR	            0x00000400  /* DMA Write Operation Indicator */
-#define PCAPRD	            0x00000800  /* DMA Read Operation Indicator */
-#define PMAP	            0x00007000  /* DMA Peripheral Map Field */
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0	0x0001
-#define TIMEN1	0x0002
-#define TIMEN2	0x0004
-#define TIMEN3	0x0008
-#define TIMEN4	0x0010
-#define TIMEN5	0x0020
-#define TIMEN6	0x0040
-#define TIMEN7	0x0080
-#define TIMEN8	0x0001
-#define TIMEN9	0x0002
-#define TIMEN10	0x0004
-#define TIMEN11	0x0008
-
-#define TIMEN0_P	0x00
-#define TIMEN1_P	0x01
-#define TIMEN2_P	0x02
-#define TIMEN3_P	0x03
-#define TIMEN4_P	0x04
-#define TIMEN5_P	0x05
-#define TIMEN6_P	0x06
-#define TIMEN7_P	0x07
-#define TIMEN8_P	0x00
-#define TIMEN9_P	0x01
-#define TIMEN10_P	0x02
-#define TIMEN11_P	0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0		0x0001
-#define TIMDIS1		0x0002
-#define TIMDIS2		0x0004
-#define TIMDIS3		0x0008
-#define TIMDIS4		0x0010
-#define TIMDIS5		0x0020
-#define TIMDIS6		0x0040
-#define TIMDIS7		0x0080
-#define TIMDIS8		0x0001
-#define TIMDIS9		0x0002
-#define TIMDIS10	0x0004
-#define TIMDIS11	0x0008
-
-#define TIMDIS0_P	0x00
-#define TIMDIS1_P	0x01
-#define TIMDIS2_P	0x02
-#define TIMDIS3_P	0x03
-#define TIMDIS4_P	0x04
-#define TIMDIS5_P	0x05
-#define TIMDIS6_P	0x06
-#define TIMDIS7_P	0x07
-#define TIMDIS8_P	0x00
-#define TIMDIS9_P	0x01
-#define TIMDIS10_P	0x02
-#define TIMDIS11_P	0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0		0x00000001
-#define TIMIL1		0x00000002
-#define TIMIL2		0x00000004
-#define TIMIL3		0x00000008
-#define TIMIL4		0x00010000
-#define TIMIL5		0x00020000
-#define TIMIL6		0x00040000
-#define TIMIL7		0x00080000
-#define TIMIL8		0x0001
-#define TIMIL9		0x0002
-#define TIMIL10		0x0004
-#define TIMIL11		0x0008
-#define TOVF_ERR0	0x00000010
-#define TOVF_ERR1	0x00000020
-#define TOVF_ERR2	0x00000040
-#define TOVF_ERR3	0x00000080
-#define TOVF_ERR4	0x00100000
-#define TOVF_ERR5	0x00200000
-#define TOVF_ERR6	0x00400000
-#define TOVF_ERR7	0x00800000
-#define TOVF_ERR8	0x0010
-#define TOVF_ERR9	0x0020
-#define TOVF_ERR10	0x0040
-#define TOVF_ERR11	0x0080
-#define TRUN0		0x00001000
-#define TRUN1		0x00002000
-#define TRUN2		0x00004000
-#define TRUN3		0x00008000
-#define TRUN4		0x10000000
-#define TRUN5		0x20000000
-#define TRUN6		0x40000000
-#define TRUN7		0x80000000
-#define TRUN8		0x1000
-#define TRUN9		0x2000
-#define TRUN10		0x4000
-#define TRUN11		0x8000
-
-#define TIMIL0_P	0x00
-#define TIMIL1_P	0x01
-#define TIMIL2_P	0x02
-#define TIMIL3_P	0x03
-#define TIMIL4_P	0x10
-#define TIMIL5_P	0x11
-#define TIMIL6_P	0x12
-#define TIMIL7_P	0x13
-#define TIMIL8_P	0x00
-#define TIMIL9_P	0x01
-#define TIMIL10_P	0x02
-#define TIMIL11_P	0x03
-#define TOVF_ERR0_P	0x04
-#define TOVF_ERR1_P	0x05
-#define TOVF_ERR2_P	0x06
-#define TOVF_ERR3_P	0x07
-#define TOVF_ERR4_P	0x14
-#define TOVF_ERR5_P	0x15
-#define TOVF_ERR6_P	0x16
-#define TOVF_ERR7_P	0x17
-#define TOVF_ERR8_P	0x04
-#define TOVF_ERR9_P	0x05
-#define TOVF_ERR10_P	0x06
-#define TOVF_ERR11_P	0x07
-#define TRUN0_P		0x0C
-#define TRUN1_P		0x0D
-#define TRUN2_P		0x0E
-#define TRUN3_P		0x0F
-#define TRUN4_P		0x1C
-#define TRUN5_P		0x1D
-#define TRUN6_P		0x1E
-#define TRUN7_P		0x1F
-#define TRUN8_P		0x0C
-#define TRUN9_P		0x0D
-#define TRUN10_P	0x0E
-#define TRUN11_P	0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT		0x0001
-#define WDTH_CAP	0x0002
-#define EXT_CLK		0x0003
-#define PULSE_HI	0x0004
-#define PERIOD_CNT	0x0008
-#define IRQ_ENA		0x0010
-#define TIN_SEL		0x0020
-#define OUT_DIS		0x0040
-#define CLK_SEL		0x0080
-#define TOGGLE_HI	0x0100
-#define EMU_RUN		0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x)	(((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x)	(((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0		0x00
-#define TMODE_P1		0x01
-#define PULSE_HI_P		0x02
-#define PERIOD_CNT_P		0x03
-#define IRQ_ENA_P		0x04
-#define TIN_SEL_P		0x05
-#define OUT_DIS_P		0x06
-#define CLK_SEL_P		0x07
-#define TOGGLE_HI_P		0x08
-#define EMU_RUN_P		0x09
-#define ERR_TYP_P0		0x0E
-#define ERR_TYP_P1		0x0F
-
-
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-
-/*// SPI_CTL Masks */
-#define TIMOD                  0x00000003  /* Transfer initiation mode and interrupt generation */
-#define SZ                     0x00000004  /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008  /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010  /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020  /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100  /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200  /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400  /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800  /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000  /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000  /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000  /* SPI module enable (=1), disable (=0) */
-
-/*// SPI_FLG Masks */
-#define FLS1                   0x00000002  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/*// SPI_FLG Bit Positions */
-#define FLS1_P                 0x00000001  /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002  /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003  /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004  /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005  /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006  /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007  /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009  /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A  /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B  /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C  /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D  /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E  /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F  /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/*// SPI_STAT Masks */
-#define SPIF                   0x00000001  /* Set (=1) when SPI single-word transfer complete */
-#define MODF                   0x00000002  /* Set (=1) in a master device when some other device tries to become master */
-#define TXE                    0x00000004  /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS                    0x00000008  /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY                   0x00000010  /* Set (=1) when data is received with RDBR full */
-#define RXS                    0x00000020  /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL                  0x00000040  /* When set (=1), corrupt data may have been transmitted  */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN			0x0001  /* Enable CLKOUT */
-#define AMBEN_B0		0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1		0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2	0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL		0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN			0x0010  /* Enable 16-bit packing Bank 0  */
-#define B1_PEN			0x0020  /* Enable 16-bit packing Bank 1  */
-#define B2_PEN			0x0040  /* Enable 16-bit packing Bank 2  */
-#define B3_PEN			0x0080  /* Enable 16-bit packing Bank 3  */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P		0x0000  /* Enable CLKOUT */
-#define AMBEN_P0		0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1		0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2		0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P		0x0004  /* Enable 16-bit packing Bank 0  */
-#define B1_PEN_P		0x0005  /* Enable 16-bit packing Bank 1  */
-#define B2_PEN_P		0x0006  /* Enable 16-bit packing Bank 2  */
-#define B3_PEN_P		0x0007  /* Enable 16-bit packing Bank 3  */
-#define CDPRIO                  0x0100  /* DMA has priority over core for for external accesses */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN	0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1	0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2	0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3	0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4	0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1	0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2	0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3	0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4	0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1	0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2	0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3	0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0	0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1			0x00000100  /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2			0x00000200  /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3			0x00000300  /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4			0x00000400  /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5			0x00000500  /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6			0x00000600  /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7			0x00000700  /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8			0x00000800  /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9			0x00000900  /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10		0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11		0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12		0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13		0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14		0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15		0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1			0x00001000  /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2			0x00002000  /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3			0x00003000  /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4			0x00004000  /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5			0x00005000  /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6			0x00006000  /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7			0x00007000  /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8			0x00008000  /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9			0x00009000  /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10		0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11		0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12		0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13		0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14		0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15		0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN			0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL		0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1			0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2			0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3			0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4			0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1			0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2			0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3			0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4			0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1			0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2			0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3			0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0			0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1			0x01000000  /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2			0x02000000  /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3			0x03000000  /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4			0x04000000  /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5			0x05000000  /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6			0x06000000  /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7			0x07000000  /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8			0x08000000  /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9			0x09000000  /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10		0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11		0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12		0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13		0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14		0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15		0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1			0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2			0x20000000  /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3			0x30000000  /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4			0x40000000  /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5			0x50000000  /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6			0x60000000  /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7			0x70000000  /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8			0x80000000  /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9			0x90000000  /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10		0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11		0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12		0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13		0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14		0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15		0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN			0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL		0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1			0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2			0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3			0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4			0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1			0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2			0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3			0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4			0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1			0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2			0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3			0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0			0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1			0x00000100  /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2			0x00000200  /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3			0x00000300  /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4			0x00000400  /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5			0x00000500  /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6			0x00000600  /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7			0x00000700  /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8			0x00000800  /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9			0x00000900  /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10		0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11		0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12		0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13		0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14		0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15		0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1			0x00001000  /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2			0x00002000  /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3			0x00003000  /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4			0x00004000  /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5			0x00005000  /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6			0x00006000  /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7			0x00007000  /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8			0x00008000  /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9			0x00009000  /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10		0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11		0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12		0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13		0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14		0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15		0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN			0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL		0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1			0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2			0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3			0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4			0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1			0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2			0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3			0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4			0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1			0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2			0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3			0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0			0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1			0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2			0x02000000  /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3			0x03000000  /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4			0x04000000  /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5			0x05000000  /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6			0x06000000  /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7			0x07000000  /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8			0x08000000  /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9			0x09000000  /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10		0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11		0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12		0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13		0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14		0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15		0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1			0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2			0x20000000  /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3			0x30000000  /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4			0x40000000  /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5			0x50000000  /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6			0x60000000  /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7			0x70000000  /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8			0x80000000  /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9			0x90000000  /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10		0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11		0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12		0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13		0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14		0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15		0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define PASR_ALL                0x00000000          /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1              0x00000010          /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0                 0x00000020          /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define SCTLE			0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2			0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3			0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define CL           0x0000000C /* SDRAM CAS latency */
-#define PFE			0x00000010 /* Enable SDRAM prefetch */
-#define PFP			0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR      0x00000030 /* SDRAM partial array self-refresh */
-#define TRAS_1			0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2			0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3			0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4			0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5			0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6			0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7			0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8			0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9			0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10			0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11			0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12			0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13			0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14			0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15			0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRAS            0x000003C0 /* SDRAM tRAS in SCLK cycles */
-#define TRP_1			0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2			0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3			0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4			0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5			0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6			0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7			0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRP          0x00003800 /* SDRAM tRP in SCLK cycles */
-#define TRCD_1			0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2			0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3			0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4			0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5			0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6			0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7			0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TRCD         0x00030000 /* SDRAM tRCD in SCLK cycles */
-#define TWR_1			0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2			0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3			0x00180000 /* SDRAM tWR = 3 cycles */
-#define TWR          0x00180000 /* SDRAM tWR in SCLK cycles */
-#define PUPSD			0x00200000 /*Power-up start delay */
-#define PSM			0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS				0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS			0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE			0x02000000 /* Enable external buffering timing */
-#define FBBRW			0x04000000 /* Fast back-to-back read write enable */
-#define EMREN			0x10000000 /* Extended mode register enable */
-#define TCSR			0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG			0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBSZ            0x000E    /* SDRAM external bank size */
-#define EBCAW           0x0030    /* SDRAM external bank column address width */
-#define EB0_E				0x00000001 /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16			0x00000000 /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32			0x00000002 /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64			0x00000004 /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128			0x00000006 /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8			0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9			0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10			0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11			0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E				0x00000100 /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16			0x00000000 /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32			0x00000200 /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64			0x00000400 /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128			0x00000600 /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8			0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9			0x00001000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10			0x00002000 /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11			0x00003000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E				0x00010000 /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16			0x00000000 /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32			0x00020000 /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64			0x00040000 /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128			0x00060000 /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8			0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9			0x00100000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10			0x00200000 /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11			0x00300000 /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E				0x01000000 /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16			0x00000000 /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32			0x02000000 /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64			0x04000000 /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128			0x06000000 /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8			0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9			0x10000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10			0x20000000 /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11			0x30000000 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI			0x00000001 /* SDRAM controller is idle  */
-#define SDSRA			0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA			0x00000004 /* SDRAM power up active  */
-#define SDRS			0x00000008 /* SDRAM is in reset state */
-#define SDEASE		    0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT			0x00000020 /* Bus granted */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF561_H */
diff --git a/libgloss/bfin/include/defBF592-A.h b/libgloss/bfin/include/defBF592-A.h
deleted file mode 100644
index b8151440b..000000000
--- a/libgloss/bfin/include/defBF592-A.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the ADSP-BF592-A peripherals.
-**
-** Copyright (C) 2009 Analog Devices Inc., All Rights Reserved.
-*/
-
-#ifndef _DEF_BF592A_H
-#define _DEF_BF592A_H
-
-/* include the core specific definitions */
-#include <def_LPBlackfin.h>
-
-/* include the family common definitions */
-#include <defBF59x_base.h>
-
-#endif /* _DEF_BF592A_H */
diff --git a/libgloss/bfin/include/defBF59x_base.h b/libgloss/bfin/include/defBF59x_base.h
deleted file mode 100644
index 4e419f40a..000000000
--- a/libgloss/bfin/include/defBF59x_base.h
+++ /dev/null
@@ -1,1111 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** defBF59x_base.h
-**
-** Copyright (C) 2009-2010 Analog Devices Inc., All Rights Reserved.
-**
-************************************************************************************
-**
-** This include file contains a list of macro "defines" to enable the programmer
-** to use symbolic names for the registers common to the ADSP-BF59x peripherals.
-**
-************************************************************************************
-** System MMR Register Map
-************************************************************************************/
-
-#ifndef _DEF_BF59x_H
-#define _DEF_BF59x_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#include <stdint.h>
-#endif /* _MISRA_RULES */
-
-
-/* ************************************************************************************************************** */
-/*                           SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF59x                            */
-/* ************************************************************************************************************** */
-
-/* Clock and System Control		(0xFFC00000 - 0xFFC000FF)									*/
-#define PLL_CTL				0xFFC00000	/* PLL Control Register								*/
-#define PLL_DIV				0xFFC00004	/* PLL Divide Register								*/
-#define VR_CTL				0xFFC00008	/* Voltage Regulator Control Register					*/
-#define PLL_STAT				0xFFC0000C	/* PLL Status Register								*/
-#define PLL_LOCKCNT			0xFFC00010	/* PLL Lock Count Register							*/
-#define CHIPID        			0xFFC00014  /* Device ID Register */
-#define AUX_REVID      			0xFFC00108  /* Auxiliary Revision ID Register */
-
-/* System Interrupt Controller 	(0xFFC00100 - 0xFFC001FF)									*/
-#define SWRST				0xFFC00100	/* Software Reset Register							*/
-#define SYSCR				0xFFC00104	/* System Configuration Register						*/
-
-#define SIC_IMASK0			0xFFC0010C	/* Interrupt Mask Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IMASK				SIC_IMASK0
-#define SIC_IAR0				0xFFC00110	/* Interrupt Assignment Register 0						*/
-#define SIC_IAR1				0xFFC00114	/* Interrupt Assignment Register 1						*/
-#define SIC_IAR2				0xFFC00118	/* Interrupt Assignment Register 2						*/
-#define SIC_IAR3				0xFFC0011C	/* Interrupt Assignment Register 3						*/
-#define SIC_ISR0				0xFFC00120	/* Interrupt Status Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_ISR				SIC_ISR0
-#define SIC_IWR0				0xFFC00124	/* Interrupt Wakeup Register							*/
-/* legacy register name (below) provided for backwards code compatibility */
-#define SIC_IWR				SIC_IWR0
-
-/* Watchdog Timer				(0xFFC00200 - 0xFFC002FF) 									*/
-#define WDOG_CTL				0xFFC00200	/* Watchdog Control Register							*/
-#define WDOG_CNT				0xFFC00204	/* Watchdog Count Register							*/
-#define WDOG_STAT				0xFFC00208	/* Watchdog Status Register							*/
-
-/* UART0 Controller 			(0xFFC00400 - 0xFFC004FF) 									*/
-#define UART0_THR				0xFFC00400	/* Transmit Holding register							*/
-#define UART0_RBR				0xFFC00400	/* Receive Buffer register							*/
-#define UART0_DLL				0xFFC00400	/* Divisor Latch (Low-Byte)							*/
-#define UART0_IER				0xFFC00404	/* Interrupt Enable Register							*/
-#define UART0_DLH				0xFFC00404	/* Divisor Latch (High-Byte)							*/
-#define UART0_IIR				0xFFC00408	/* Interrupt Identification Register					*/
-#define UART0_LCR				0xFFC0040C	/* Line Control Register							*/
-#define UART0_MCR				0xFFC00410	/* Modem Control Register							*/
-#define UART0_LSR				0xFFC00414	/* Line Status Register								*/
-#define UART0_SCR				0xFFC0041C	/* SCR Scratch Register								*/
-#define UART0_GCTL				0xFFC00424	/* Global Control Register							*/
-
-
-/* SPI0 Controller				(0xFFC00500 - 0xFFC005FF) 									*/
-#define SPI0_CTL				0xFFC00500	/* SPI0 Control Register								*/
-#define SPI0_FLG				0xFFC00504	/* SPI0 Flag register								*/
-#define SPI0_STAT				0xFFC00508	/* SPI0 Status register								*/
-#define SPI0_TDBR				0xFFC0050C	/* SPI0 Transmit Data Buffer Register					*/
-#define SPI0_RDBR				0xFFC00510	/* SPI0 Receive Data Buffer Register						*/
-#define SPI0_BAUD				0xFFC00514	/* SPI0 Baud rate Register							*/
-#define SPI0_SHADOW				0xFFC00518	/* SPI0_RDBR Shadow Register							*/
-
-/* SPI1 Controller 				(0xFFC01300 - 0xFFC013FF)									*/
-#define SPI1_CTL				0xFFC01300	/* SPI1 Control Register							*/
-#define SPI1_FLG				0xFFC01304	/* SPI1 Flag register								*/
-#define SPI1_STAT				0xFFC01308	/* SPI1 Status register								*/
-#define SPI1_TDBR				0xFFC0130C	/* SPI1 Transmit Data Buffer Register					*/
-#define SPI1_RDBR				0xFFC01310	/* SPI1 Receive Data Buffer Register					*/
-#define SPI1_BAUD				0xFFC01314	/* SPI1 Baud rate Register							*/
-#define SPI1_SHADOW				0xFFC01318	/* SPI1_RDBR Shadow Register							*/
-
-
-/* TIMER0-2 Registers 			(0xFFC00600 - 0xFFC006FF)									*/
-#define TIMER0_CONFIG			0xFFC00600	/* Timer 0 Configuration Register						*/
-#define TIMER0_COUNTER			0xFFC00604	/* Timer 0 Counter Register							*/
-#define TIMER0_PERIOD			0xFFC00608	/* Timer 0 Period Register							*/
-#define TIMER0_WIDTH			0xFFC0060C	/* Timer 0 Width Register							*/
-
-#define TIMER1_CONFIG			0xFFC00610	/* Timer 1 Configuration Register  						*/
-#define TIMER1_COUNTER			0xFFC00614	/* Timer 1 Counter Register        						*/
-#define TIMER1_PERIOD			0xFFC00618	/* Timer 1 Period Register         						*/
-#define TIMER1_WIDTH			0xFFC0061C	/* Timer 1 Width Register          						*/
-
-#define TIMER2_CONFIG			0xFFC00620	/* Timer 2 Configuration Register  						*/
-#define TIMER2_COUNTER			0xFFC00624	/* Timer 2 Counter Register        						*/
-#define TIMER2_PERIOD			0xFFC00628	/* Timer 2 Period Register         						*/
-#define TIMER2_WIDTH			0xFFC0062C	/* Timer 2 Width Register          						*/
-
-#define TIMER_ENABLE			0xFFC00640	/* Timer Enable Register							*/
-#define TIMER_DISABLE			0xFFC00644	/* Timer Disable Register							*/
-#define TIMER_STATUS			0xFFC00648	/* Timer Status Register							*/
-
-
-/* General Purpose I/O Port F 	(0xFFC00700 - 0xFFC007FF) 									*/
-#define PORTFIO				0xFFC00700	/* Port F I/O Pin State Specify Register					*/
-#define PORTFIO_CLEAR			0xFFC00704	/* Port F I/O Peripheral Interrupt Clear Register			*/
-#define PORTFIO_SET			0xFFC00708	/* Port F I/O Peripheral Interrupt Set Register				*/
-#define PORTFIO_TOGGLE			0xFFC0070C	/* Port F I/O Pin State Toggle Register					*/
-#define PORTFIO_MASKA			0xFFC00710	/* Port F I/O Mask State Specify Interrupt A Register			*/
-#define PORTFIO_MASKA_CLEAR		0xFFC00714	/* Port F I/O Mask Disable Interrupt A Register				*/
-#define PORTFIO_MASKA_SET		0xFFC00718	/* Port F I/O Mask Enable Interrupt A Register				*/
-#define PORTFIO_MASKA_TOGGLE		0xFFC0071C	/* Port F I/O Mask Toggle Enable Interrupt A Register			*/
-#define PORTFIO_MASKB			0xFFC00720	/* Port F I/O Mask State Specify Interrupt B Register			*/
-#define PORTFIO_MASKB_CLEAR		0xFFC00724	/* Port F I/O Mask Disable Interrupt B Register				*/
-#define PORTFIO_MASKB_SET		0xFFC00728	/* Port F I/O Mask Enable Interrupt B Register				*/
-#define PORTFIO_MASKB_TOGGLE		0xFFC0072C	/* Port F I/O Mask Toggle Enable Interrupt B Register			*/
-#define PORTFIO_DIR			0xFFC00730	/* Port F I/O Direction Register						*/
-#define PORTFIO_POLAR			0xFFC00734	/* Port F I/O Source Polarity Register					*/
-#define PORTFIO_EDGE			0xFFC00738	/* Port F I/O Source Sensitivity Register					*/
-#define PORTFIO_BOTH			0xFFC0073C	/* Port F I/O Set on BOTH Edges Register					*/
-#define PORTFIO_INEN			0xFFC00740	/* Port F I/O Input Enable Register 					*/
-
-/* General Purpose I/O Port G 	(0xFFC01500 - 0xFFC015FF) 									*/
-#define PORTGIO				0xFFC01500	/* Port G I/O Pin State Specify Register					*/
-#define PORTGIO_CLEAR			0xFFC01504	/* Port G I/O Peripheral Interrupt Clear Register			*/
-#define PORTGIO_SET			0xFFC01508	/* Port G I/O Peripheral Interrupt Set Register				*/
-#define PORTGIO_TOGGLE			0xFFC0150C	/* Port G I/O Pin State Toggle Register					*/
-#define PORTGIO_MASKA			0xFFC01510	/* Port G I/O Mask State Specify Interrupt A Register			*/
-#define PORTGIO_MASKA_CLEAR		0xFFC01514	/* Port G I/O Mask Disable Interrupt A Register				*/
-#define PORTGIO_MASKA_SET		0xFFC01518	/* Port G I/O Mask Enable Interrupt A Register				*/
-#define PORTGIO_MASKA_TOGGLE		0xFFC0151C	/* Port G I/O Mask Toggle Enable Interrupt A Register			*/
-#define PORTGIO_MASKB			0xFFC01520	/* Port G I/O Mask State Specify Interrupt B Register			*/
-#define PORTGIO_MASKB_CLEAR		0xFFC01524	/* Port G I/O Mask Disable Interrupt B Register				*/
-#define PORTGIO_MASKB_SET		0xFFC01528	/* Port G I/O Mask Enable Interrupt B Register				*/
-#define PORTGIO_MASKB_TOGGLE		0xFFC0152C	/* Port G I/O Mask Toggle Enable Interrupt B Register			*/
-#define PORTGIO_DIR			0xFFC01530	/* Port G I/O Direction Register						*/
-#define PORTGIO_POLAR			0xFFC01534	/* Port G I/O Source Polarity Register					*/
-#define PORTGIO_EDGE			0xFFC01538	/* Port G I/O Source Sensitivity Register					*/
-#define PORTGIO_BOTH			0xFFC0153C	/* Port G I/O Set on BOTH Edges Register					*/
-#define PORTGIO_INEN			0xFFC01540	/* Port G I/O Input Enable Register						*/
-
-
-/* Pin Control Registers		(0xFFC01100 - 0xFFC01208)													*/
-#define PORTF_FER				0xFFC01100	/* Port F Function Enable Register (Alternate/Flag*)			*/
-#define PORTF_MUX               0xFFC01104  /* Port F mux control 											*/
-#define PORTF_PADCTL        	0xFFC01108  /* Port F pad control 								*/
-#define PORTG_FER				0xFFC01200	/* Port G Function Enable Register (Alternate/Flag*)			*/
-#define PORTG_MUX               0xFFC01204  /* Port G mux control											*/
-#define PORTG_PADCTL        	0xFFC01208  /* Port G pad control 								*/
-
-/* SPORT Clock Gating			(0xFFC0120C)												*/
-#define SPORT_GATECLK			0xFFC0120C	/* SPORT Clock Gating Control Register				*/
-
-
-/* SPORT0 Controller 			(0xFFC00800 - 0xFFC008FF) 									*/
-#define SPORT0_TCR1			0xFFC00800	/* SPORT0 Transmit Configuration 1 Register				*/
-#define SPORT0_TCR2			0xFFC00804	/* SPORT0 Transmit Configuration 2 Register				*/
-#define SPORT0_TCLKDIV			0xFFC00808	/* SPORT0 Transmit Clock Divider						*/
-#define SPORT0_TFSDIV			0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider					*/
-#define SPORT0_TX				0xFFC00810	/* SPORT0 TX Data Register							*/
-#define SPORT0_RX				0xFFC00818	/* SPORT0 RX Data Register							*/
-#define SPORT0_RCR1			0xFFC00820	/* SPORT0 Transmit Configuration 1 Register				*/
-#define SPORT0_RCR2			0xFFC00824	/* SPORT0 Transmit Configuration 2 Register				*/
-#define SPORT0_RCLKDIV			0xFFC00828	/* SPORT0 Receive Clock Divider						*/
-#define SPORT0_RFSDIV			0xFFC0082C	/* SPORT0 Receive Frame Sync Divider					*/
-#define SPORT0_STAT			0xFFC00830	/* SPORT0 Status Register							*/
-#define SPORT0_CHNL			0xFFC00834	/* SPORT0 Current Channel Register						*/
-#define SPORT0_MCMC1			0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1			*/
-#define SPORT0_MCMC2			0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2			*/
-#define SPORT0_MTCS0			0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0			*/
-#define SPORT0_MTCS1			0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1			*/
-#define SPORT0_MTCS2			0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2			*/
-#define SPORT0_MTCS3			0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3			*/
-#define SPORT0_MRCS0			0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0			*/
-#define SPORT0_MRCS1			0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1			*/
-#define SPORT0_MRCS2			0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2			*/
-#define SPORT0_MRCS3			0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3			*/
-
-
-/* SPORT1 Controller 			(0xFFC00900 - 0xFFC009FF) 									*/
-#define SPORT1_TCR1			0xFFC00900	/* SPORT1 Transmit Configuration 1 Register				*/
-#define SPORT1_TCR2			0xFFC00904	/* SPORT1 Transmit Configuration 2 Register				*/
-#define SPORT1_TCLKDIV			0xFFC00908	/* SPORT1 Transmit Clock Divider						*/
-#define SPORT1_TFSDIV			0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider					*/
-#define SPORT1_TX				0xFFC00910	/* SPORT1 TX Data Register							*/
-#define SPORT1_RX				0xFFC00918	/* SPORT1 RX Data Register							*/
-#define SPORT1_RCR1			0xFFC00920	/* SPORT1 Transmit Configuration 1 Register				*/
-#define SPORT1_RCR2			0xFFC00924	/* SPORT1 Transmit Configuration 2 Register				*/
-#define SPORT1_RCLKDIV			0xFFC00928	/* SPORT1 Receive Clock Divider						*/
-#define SPORT1_RFSDIV			0xFFC0092C	/* SPORT1 Receive Frame Sync Divider					*/
-#define SPORT1_STAT			0xFFC00930	/* SPORT1 Status Register							*/
-#define SPORT1_CHNL			0xFFC00934	/* SPORT1 Current Channel Register						*/
-#define SPORT1_MCMC1			0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1			*/
-#define SPORT1_MCMC2			0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2			*/
-#define SPORT1_MTCS0			0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0			*/
-#define SPORT1_MTCS1			0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1			*/
-#define SPORT1_MTCS2			0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2			*/
-#define SPORT1_MTCS3			0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3			*/
-#define SPORT1_MRCS0			0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0			*/
-#define SPORT1_MRCS1			0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1			*/
-#define SPORT1_MRCS2			0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2			*/
-#define SPORT1_MRCS3			0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3			*/
-
-/* DMA Traffic Control Registers 	(0xFFC00B00 - 0xFFC00BFF)									*/
-#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register						*/
-#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register				*/
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility 					*/
-#define DMA_TCPER				0xFFC00B0C	/* Traffic Control Periods Register						*/
-#define DMA_TCCNT				0xFFC00B10	/* Traffic Control Current Counts Register				*/
-
-/* DMA Controller 			(0xFFC00C00 - 0xFFC00FFF) 									*/
-#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register			*/
-#define DMA0_START_ADDR			0xFFC00C04	/* DMA Channel 0 Start Address Register					*/
-#define DMA0_CONFIG			0xFFC00C08	/* DMA Channel 0 Configuration Register					*/
-#define DMA0_X_COUNT			0xFFC00C10	/* DMA Channel 0 X Count Register						*/
-#define DMA0_X_MODIFY			0xFFC00C14	/* DMA Channel 0 X Modify Register						*/
-#define DMA0_Y_COUNT			0xFFC00C18	/* DMA Channel 0 Y Count Register						*/
-#define DMA0_Y_MODIFY			0xFFC00C1C	/* DMA Channel 0 Y Modify Register						*/
-#define DMA0_CURR_DESC_PTR		0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register			*/
-#define DMA0_CURR_ADDR			0xFFC00C24	/* DMA Channel 0 Current Address Register					*/
-#define DMA0_IRQ_STATUS			0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register				*/
-#define DMA0_PERIPHERAL_MAP		0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register					*/
-#define DMA0_CURR_X_COUNT		0xFFC00C30	/* DMA Channel 0 Current X Count Register					*/
-#define DMA0_CURR_Y_COUNT		0xFFC00C38	/* DMA Channel 0 Current Y Count Register					*/
-
-#define DMA1_NEXT_DESC_PTR		0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register			*/
-#define DMA1_START_ADDR			0xFFC00C44	/* DMA Channel 1 Start Address Register					*/
-#define DMA1_CONFIG			0xFFC00C48	/* DMA Channel 1 Configuration Register					*/
-#define DMA1_X_COUNT			0xFFC00C50	/* DMA Channel 1 X Count Register						*/
-#define DMA1_X_MODIFY			0xFFC00C54	/* DMA Channel 1 X Modify Register						*/
-#define DMA1_Y_COUNT			0xFFC00C58	/* DMA Channel 1 Y Count Register						*/
-#define DMA1_Y_MODIFY			0xFFC00C5C	/* DMA Channel 1 Y Modify Register						*/
-#define DMA1_CURR_DESC_PTR		0xFFC00C60	/* DMA Channel 1 Current Descriptor Pointer Register			*/
-#define DMA1_CURR_ADDR			0xFFC00C64	/* DMA Channel 1 Current Address Register					*/
-#define DMA1_IRQ_STATUS			0xFFC00C68	/* DMA Channel 1 Interrupt/Status Register				*/
-#define DMA1_PERIPHERAL_MAP		0xFFC00C6C	/* DMA Channel 1 Peripheral Map Register					*/
-#define DMA1_CURR_X_COUNT		0xFFC00C70	/* DMA Channel 1 Current X Count Register					*/
-#define DMA1_CURR_Y_COUNT		0xFFC00C78	/* DMA Channel 1 Current Y Count Register					*/
-
-#define DMA2_NEXT_DESC_PTR		0xFFC00C80	/* DMA Channel 2 Next Descriptor Pointer Register			*/
-#define DMA2_START_ADDR			0xFFC00C84	/* DMA Channel 2 Start Address Register					*/
-#define DMA2_CONFIG			0xFFC00C88	/* DMA Channel 2 Configuration Register					*/
-#define DMA2_X_COUNT			0xFFC00C90	/* DMA Channel 2 X Count Register						*/
-#define DMA2_X_MODIFY			0xFFC00C94	/* DMA Channel 2 X Modify Register						*/
-#define DMA2_Y_COUNT			0xFFC00C98	/* DMA Channel 2 Y Count Register						*/
-#define DMA2_Y_MODIFY			0xFFC00C9C	/* DMA Channel 2 Y Modify Register						*/
-#define DMA2_CURR_DESC_PTR		0xFFC00CA0	/* DMA Channel 2 Current Descriptor Pointer Register			*/
-#define DMA2_CURR_ADDR			0xFFC00CA4	/* DMA Channel 2 Current Address Register					*/
-#define DMA2_IRQ_STATUS			0xFFC00CA8	/* DMA Channel 2 Interrupt/Status Register				*/
-#define DMA2_PERIPHERAL_MAP		0xFFC00CAC	/* DMA Channel 2 Peripheral Map Register					*/
-#define DMA2_CURR_X_COUNT		0xFFC00CB0	/* DMA Channel 2 Current X Count Register					*/
-#define DMA2_CURR_Y_COUNT		0xFFC00CB8	/* DMA Channel 2 Current Y Count Register					*/
-
-#define DMA3_NEXT_DESC_PTR		0xFFC00CC0	/* DMA Channel 3 Next Descriptor Pointer Register			*/
-#define DMA3_START_ADDR			0xFFC00CC4	/* DMA Channel 3 Start Address Register					*/
-#define DMA3_CONFIG			0xFFC00CC8	/* DMA Channel 3 Configuration Register					*/
-#define DMA3_X_COUNT			0xFFC00CD0	/* DMA Channel 3 X Count Register						*/
-#define DMA3_X_MODIFY			0xFFC00CD4	/* DMA Channel 3 X Modify Register						*/
-#define DMA3_Y_COUNT			0xFFC00CD8	/* DMA Channel 3 Y Count Register						*/
-#define DMA3_Y_MODIFY			0xFFC00CDC	/* DMA Channel 3 Y Modify Register						*/
-#define DMA3_CURR_DESC_PTR		0xFFC00CE0	/* DMA Channel 3 Current Descriptor Pointer Register			*/
-#define DMA3_CURR_ADDR			0xFFC00CE4	/* DMA Channel 3 Current Address Register					*/
-#define DMA3_IRQ_STATUS			0xFFC00CE8	/* DMA Channel 3 Interrupt/Status Register				*/
-#define DMA3_PERIPHERAL_MAP		0xFFC00CEC	/* DMA Channel 3 Peripheral Map Register					*/
-#define DMA3_CURR_X_COUNT		0xFFC00CF0	/* DMA Channel 3 Current X Count Register					*/
-#define DMA3_CURR_Y_COUNT		0xFFC00CF8	/* DMA Channel 3 Current Y Count Register					*/
-
-#define DMA4_NEXT_DESC_PTR		0xFFC00D00	/* DMA Channel 4 Next Descriptor Pointer Register			*/
-#define DMA4_START_ADDR			0xFFC00D04	/* DMA Channel 4 Start Address Register					*/
-#define DMA4_CONFIG			0xFFC00D08	/* DMA Channel 4 Configuration Register					*/
-#define DMA4_X_COUNT			0xFFC00D10	/* DMA Channel 4 X Count Register						*/
-#define DMA4_X_MODIFY			0xFFC00D14	/* DMA Channel 4 X Modify Register						*/
-#define DMA4_Y_COUNT			0xFFC00D18	/* DMA Channel 4 Y Count Register						*/
-#define DMA4_Y_MODIFY			0xFFC00D1C	/* DMA Channel 4 Y Modify Register						*/
-#define DMA4_CURR_DESC_PTR		0xFFC00D20	/* DMA Channel 4 Current Descriptor Pointer Register			*/
-#define DMA4_CURR_ADDR			0xFFC00D24	/* DMA Channel 4 Current Address Register					*/
-#define DMA4_IRQ_STATUS			0xFFC00D28	/* DMA Channel 4 Interrupt/Status Register				*/
-#define DMA4_PERIPHERAL_MAP		0xFFC00D2C	/* DMA Channel 4 Peripheral Map Register					*/
-#define DMA4_CURR_X_COUNT		0xFFC00D30	/* DMA Channel 4 Current X Count Register					*/
-#define DMA4_CURR_Y_COUNT		0xFFC00D38	/* DMA Channel 4 Current Y Count Register					*/
-
-#define DMA5_NEXT_DESC_PTR		0xFFC00D40	/* DMA Channel 5 Next Descriptor Pointer Register			*/
-#define DMA5_START_ADDR			0xFFC00D44	/* DMA Channel 5 Start Address Register					*/
-#define DMA5_CONFIG			0xFFC00D48	/* DMA Channel 5 Configuration Register					*/
-#define DMA5_X_COUNT			0xFFC00D50	/* DMA Channel 5 X Count Register						*/
-#define DMA5_X_MODIFY			0xFFC00D54	/* DMA Channel 5 X Modify Register						*/
-#define DMA5_Y_COUNT			0xFFC00D58	/* DMA Channel 5 Y Count Register						*/
-#define DMA5_Y_MODIFY			0xFFC00D5C	/* DMA Channel 5 Y Modify Register						*/
-#define DMA5_CURR_DESC_PTR		0xFFC00D60	/* DMA Channel 5 Current Descriptor Pointer Register			*/
-#define DMA5_CURR_ADDR			0xFFC00D64	/* DMA Channel 5 Current Address Register					*/
-#define DMA5_IRQ_STATUS			0xFFC00D68	/* DMA Channel 5 Interrupt/Status Register				*/
-#define DMA5_PERIPHERAL_MAP		0xFFC00D6C	/* DMA Channel 5 Peripheral Map Register					*/
-#define DMA5_CURR_X_COUNT		0xFFC00D70	/* DMA Channel 5 Current X Count Register					*/
-#define DMA5_CURR_Y_COUNT		0xFFC00D78	/* DMA Channel 5 Current Y Count Register					*/
-
-#define DMA6_NEXT_DESC_PTR		0xFFC00D80	/* DMA Channel 6 Next Descriptor Pointer Register			*/
-#define DMA6_START_ADDR			0xFFC00D84	/* DMA Channel 6 Start Address Register					*/
-#define DMA6_CONFIG			0xFFC00D88	/* DMA Channel 6 Configuration Register					*/
-#define DMA6_X_COUNT			0xFFC00D90	/* DMA Channel 6 X Count Register						*/
-#define DMA6_X_MODIFY			0xFFC00D94	/* DMA Channel 6 X Modify Register						*/
-#define DMA6_Y_COUNT			0xFFC00D98	/* DMA Channel 6 Y Count Register						*/
-#define DMA6_Y_MODIFY			0xFFC00D9C	/* DMA Channel 6 Y Modify Register						*/
-#define DMA6_CURR_DESC_PTR		0xFFC00DA0	/* DMA Channel 6 Current Descriptor Pointer Register			*/
-#define DMA6_CURR_ADDR			0xFFC00DA4	/* DMA Channel 6 Current Address Register					*/
-#define DMA6_IRQ_STATUS			0xFFC00DA8	/* DMA Channel 6 Interrupt/Status Register				*/
-#define DMA6_PERIPHERAL_MAP		0xFFC00DAC	/* DMA Channel 6 Peripheral Map Register					*/
-#define DMA6_CURR_X_COUNT		0xFFC00DB0	/* DMA Channel 6 Current X Count Register					*/
-#define DMA6_CURR_Y_COUNT		0xFFC00DB8	/* DMA Channel 6 Current Y Count Register					*/
-
-#define DMA7_NEXT_DESC_PTR		0xFFC00DC0	/* DMA Channel 7 Next Descriptor Pointer Register			*/
-#define DMA7_START_ADDR			0xFFC00DC4	/* DMA Channel 7 Start Address Register					*/
-#define DMA7_CONFIG			0xFFC00DC8	/* DMA Channel 7 Configuration Register					*/
-#define DMA7_X_COUNT			0xFFC00DD0	/* DMA Channel 7 X Count Register						*/
-#define DMA7_X_MODIFY			0xFFC00DD4	/* DMA Channel 7 X Modify Register						*/
-#define DMA7_Y_COUNT			0xFFC00DD8	/* DMA Channel 7 Y Count Register						*/
-#define DMA7_Y_MODIFY			0xFFC00DDC	/* DMA Channel 7 Y Modify Register						*/
-#define DMA7_CURR_DESC_PTR		0xFFC00DE0	/* DMA Channel 7 Current Descriptor Pointer Register			*/
-#define DMA7_CURR_ADDR			0xFFC00DE4	/* DMA Channel 7 Current Address Register					*/
-#define DMA7_IRQ_STATUS			0xFFC00DE8	/* DMA Channel 7 Interrupt/Status Register				*/
-#define DMA7_PERIPHERAL_MAP		0xFFC00DEC	/* DMA Channel 7 Peripheral Map Register					*/
-#define DMA7_CURR_X_COUNT		0xFFC00DF0	/* DMA Channel 7 Current X Count Register					*/
-#define DMA7_CURR_Y_COUNT		0xFFC00DF8	/* DMA Channel 7 Current Y Count Register					*/
-
-#define DMA8_NEXT_DESC_PTR		0xFFC00E00	/* DMA Channel 8 Next Descriptor Pointer Register			*/
-#define DMA8_START_ADDR			0xFFC00E04	/* DMA Channel 8 Start Address Register					*/
-#define DMA8_CONFIG			0xFFC00E08	/* DMA Channel 8 Configuration Register					*/
-#define DMA8_X_COUNT			0xFFC00E10	/* DMA Channel 8 X Count Register						*/
-#define DMA8_X_MODIFY			0xFFC00E14	/* DMA Channel 8 X Modify Register						*/
-#define DMA8_Y_COUNT			0xFFC00E18	/* DMA Channel 8 Y Count Register						*/
-#define DMA8_Y_MODIFY			0xFFC00E1C	/* DMA Channel 8 Y Modify Register						*/
-#define DMA8_CURR_DESC_PTR		0xFFC00E20	/* DMA Channel 8 Current Descriptor Pointer Register			*/
-#define DMA8_CURR_ADDR			0xFFC00E24	/* DMA Channel 8 Current Address Register					*/
-#define DMA8_IRQ_STATUS			0xFFC00E28	/* DMA Channel 8 Interrupt/Status Register				*/
-#define DMA8_PERIPHERAL_MAP		0xFFC00E2C	/* DMA Channel 8 Peripheral Map Register					*/
-#define DMA8_CURR_X_COUNT		0xFFC00E30	/* DMA Channel 8 Current X Count Register					*/
-#define DMA8_CURR_Y_COUNT		0xFFC00E38	/* DMA Channel 8 Current Y Count Register					*/
-
-#define MDMA_D0_NEXT_DESC_PTR		0xFFC00F00	/* MemDMA Stream 0 Destination Next Descriptor Pointer Register 	*/
-#define MDMA_D0_START_ADDR		0xFFC00F04	/* MemDMA Stream 0 Destination Start Address Register			*/
-#define MDMA_D0_CONFIG			0xFFC00F08	/* MemDMA Stream 0 Destination Configuration Register			*/
-#define MDMA_D0_X_COUNT			0xFFC00F10	/* MemDMA Stream 0 Destination X Count Register				*/
-#define MDMA_D0_X_MODIFY		0xFFC00F14	/* MemDMA Stream 0 Destination X Modify Register			*/
-#define MDMA_D0_Y_COUNT			0xFFC00F18	/* MemDMA Stream 0 Destination Y Count Register				*/
-#define MDMA_D0_Y_MODIFY		0xFFC00F1C	/* MemDMA Stream 0 Destination Y Modify Register			*/
-#define MDMA_D0_CURR_DESC_PTR		0xFFC00F20	/* MemDMA Stream 0 Destination Current Descriptor Pointer Register*/
-#define MDMA_D0_CURR_ADDR		0xFFC00F24	/* MemDMA Stream 0 Destination Current Address Register 		*/
-#define MDMA_D0_IRQ_STATUS		0xFFC00F28	/* MemDMA Stream 0 Destination Interrupt/Status Register		*/
-#define MDMA_D0_PERIPHERAL_MAP	0xFFC00F2C	/* MemDMA Stream 0 Destination Peripheral Map Register  		*/
-#define MDMA_D0_CURR_X_COUNT		0xFFC00F30	/* MemDMA Stream 0 Destination Current X Count Register		*/
-#define MDMA_D0_CURR_Y_COUNT		0xFFC00F38	/* MemDMA Stream 0 Destination Current Y Count Register		*/
-
-#define MDMA_S0_NEXT_DESC_PTR		0xFFC00F40	/* MemDMA Stream 0 Source Next Descriptor Pointer Register		*/
-#define MDMA_S0_START_ADDR		0xFFC00F44	/* MemDMA Stream 0 Source Start Address Register			*/
-#define MDMA_S0_CONFIG			0xFFC00F48	/* MemDMA Stream 0 Source Configuration Register			*/
-#define MDMA_S0_X_COUNT			0xFFC00F50	/* MemDMA Stream 0 Source X Count Register				*/
-#define MDMA_S0_X_MODIFY		0xFFC00F54	/* MemDMA Stream 0 Source X Modify Register				*/
-#define MDMA_S0_Y_COUNT			0xFFC00F58	/* MemDMA Stream 0 Source Y Count Register				*/
-#define MDMA_S0_Y_MODIFY		0xFFC00F5C	/* MemDMA Stream 0 Source Y Modify Register				*/
-#define MDMA_S0_CURR_DESC_PTR		0xFFC00F60	/* MemDMA Stream 0 Source Current Descriptor Pointer Register	*/
-#define MDMA_S0_CURR_ADDR		0xFFC00F64	/* MemDMA Stream 0 Source Current Address Register			*/
-#define MDMA_S0_IRQ_STATUS		0xFFC00F68	/* MemDMA Stream 0 Source Interrupt/Status Register			*/
-#define MDMA_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA Stream 0 Source Peripheral Map Register			*/
-#define MDMA_S0_CURR_X_COUNT		0xFFC00F70	/* MemDMA Stream 0 Source Current X Count Register			*/
-#define MDMA_S0_CURR_Y_COUNT		0xFFC00F78	/* MemDMA Stream 0 Source Current Y Count Register			*/
-
-#define MDMA_D1_NEXT_DESC_PTR		0xFFC00F80	/* MemDMA Stream 1 Destination Next Descriptor Pointer Register	*/
-#define MDMA_D1_START_ADDR		0xFFC00F84	/* MemDMA Stream 1 Destination Start Address Register			*/
-#define MDMA_D1_CONFIG			0xFFC00F88	/* MemDMA Stream 1 Destination Configuration Register			*/
-#define MDMA_D1_X_COUNT			0xFFC00F90	/* MemDMA Stream 1 Destination X Count Register				*/
-#define MDMA_D1_X_MODIFY		0xFFC00F94	/* MemDMA Stream 1 Destination X Modify Register			*/
-#define MDMA_D1_Y_COUNT			0xFFC00F98	/* MemDMA Stream 1 Destination Y Count Register				*/
-#define MDMA_D1_Y_MODIFY		0xFFC00F9C	/* MemDMA Stream 1 Destination Y Modify Register			*/
-#define MDMA_D1_CURR_DESC_PTR		0xFFC00FA0	/* MemDMA Stream 1 Destination Current Descriptor Pointer Register*/
-#define MDMA_D1_CURR_ADDR		0xFFC00FA4	/* MemDMA Stream 1 Destination Current Address Register		*/
-#define MDMA_D1_IRQ_STATUS		0xFFC00FA8	/* MemDMA Stream 1 Destination Interrupt/Status Register		*/
-#define MDMA_D1_PERIPHERAL_MAP	0xFFC00FAC	/* MemDMA Stream 1 Destination Peripheral Map Register		*/
-#define MDMA_D1_CURR_X_COUNT		0xFFC00FB0	/* MemDMA Stream 1 Destination Current X Count Register		*/
-#define MDMA_D1_CURR_Y_COUNT		0xFFC00FB8	/* MemDMA Stream 1 Destination Current Y Count Register		*/
-
-#define MDMA_S1_NEXT_DESC_PTR		0xFFC00FC0	/* MemDMA Stream 1 Source Next Descriptor Pointer Register		*/
-#define MDMA_S1_START_ADDR		0xFFC00FC4	/* MemDMA Stream 1 Source Start Address Register			*/
-#define MDMA_S1_CONFIG			0xFFC00FC8	/* MemDMA Stream 1 Source Configuration Register			*/
-#define MDMA_S1_X_COUNT			0xFFC00FD0	/* MemDMA Stream 1 Source X Count Register				*/
-#define MDMA_S1_X_MODIFY		0xFFC00FD4	/* MemDMA Stream 1 Source X Modify Register				*/
-#define MDMA_S1_Y_COUNT			0xFFC00FD8	/* MemDMA Stream 1 Source Y Count Register				*/
-#define MDMA_S1_Y_MODIFY		0xFFC00FDC	/* MemDMA Stream 1 Source Y Modify Register				*/
-#define MDMA_S1_CURR_DESC_PTR		0xFFC00FE0	/* MemDMA Stream 1 Source Current Descriptor Pointer Register	*/
-#define MDMA_S1_CURR_ADDR		0xFFC00FE4	/* MemDMA Stream 1 Source Current Address Register			*/
-#define MDMA_S1_IRQ_STATUS		0xFFC00FE8	/* MemDMA Stream 1 Source Interrupt/Status Register			*/
-#define MDMA_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA Stream 1 Source Peripheral Map Register			*/
-#define MDMA_S1_CURR_X_COUNT		0xFFC00FF0	/* MemDMA Stream 1 Source Current X Count Register			*/
-#define MDMA_S1_CURR_Y_COUNT		0xFFC00FF8	/* MemDMA Stream 1 Source Current Y Count Register			*/
-
-
-/* Parallel Peripheral Interface 	(0xFFC01000 - 0xFFC010FF) 									*/
-#define PPI_CONTROL			0xFFC01000	/* PPI Control Register								*/
-#define PPI_STATUS			0xFFC01004	/* PPI Status Register								*/
-#define PPI_COUNT				0xFFC01008	/* PPI Transfer Count Register						*/
-#define PPI_DELAY				0xFFC0100C	/* PPI Delay Count Register							*/
-#define PPI_FRAME				0xFFC01010	/* PPI Frame Length Register							*/
-
-
-/* Two-Wire Interface 			(0xFFC01400 - 0xFFC014FF)									*/
-#define TWI_CLKDIV			0xFFC01400	/* Serial Clock Divider Register						*/
-#define TWI_CONTROL			0xFFC01404	/* TWI Control Register								*/
-#define TWI_SLAVE_CTL			0xFFC01408	/* Slave Mode Control Register						*/
-#define TWI_SLAVE_STAT			0xFFC0140C	/* Slave Mode Status Register							*/
-#define TWI_SLAVE_ADDR			0xFFC01410	/* Slave Mode Address Register						*/
-#define TWI_MASTER_CTL			0xFFC01414	/* Master Mode Control Register						*/
-#define TWI_MASTER_STAT			0xFFC01418	/* Master Mode Status Register						*/
-#define TWI_MASTER_ADDR			0xFFC0141C	/* Master Mode Address Register						*/
-#define TWI_INT_STAT			0xFFC01420	/* TWI Interrupt Status Register						*/
-#define TWI_INT_MASK			0xFFC01424	/* TWI Master Interrupt Mask Register					*/
-#define TWI_FIFO_CTL			0xFFC01428	/* FIFO Control Register							*/
-#define TWI_FIFO_STAT			0xFFC0142C	/* FIFO Status Register								*/
-#define TWI_XMT_DATA8			0xFFC01480	/* FIFO Transmit Data Single Byte Register				*/
-#define TWI_XMT_DATA16			0xFFC01484	/* FIFO Transmit Data Double Byte Register				*/
-#define TWI_RCV_DATA8			0xFFC01488	/* FIFO Receive Data Single Byte Register					*/
-#define TWI_RCV_DATA16			0xFFC0148C	/* FIFO Receive Data Double Byte Register					*/
-
-
-/******************************************************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:	All macros are intended to make C and Assembly code more readable.
-**			Use these macros carefully, as any that do left shifts for field
-**			depositing will result in the lower order bits being destroyed.  Any
-**			macro that shifts left to properly position the bit-field should be
-**			used as part of an OR to initialize a register and NOT as a dynamic
-**			modifier UNLESS the lower order bits are saved and ORed back in when
-**			the macro is used.
-*******************************************************************************************************************/
-
-/************************************** PLL AND RESET MASKS *******************************************************/
-
-/* PLL_CTL Masks */
-#define DF					0x0001	/* 0: PLL = CLKIN, 1: PLL = CLKIN/2						*/
-#define PLL_OFF				0x0002	/* PLL Not Powered								*/
-#define STOPCK				0x0008	/* Core Clock Off									*/
-#define PDWN				0x0020	/* Enter Deep Sleep Mode							*/
-#define BYPASS				0x0100	/* Bypass the PLL									*/
-#define MSEL				0x7E00	/* Multiplier Select For CCLK/VCO Factors					*/
-
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
-#ifdef _MISRA_RULES
-#define SET_MSEL(x)	(((x)&0x3Fu) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL					*/
-#else
-#define SET_MSEL(x)	(((x)&0x3F) << 0x9)	/* Set MSEL = 0-63 --> VCO = CLKIN*MSEL					*/
-#endif /* _MISRA_RULES */
-
-/* PLL_DIV Masks */
-#define SSEL				0x000F	/* System Select									*/
-#define CSEL				0x0030	/* Core Select									*/
-#define CSEL_DIV1				0x0000	/* CCLK = VCO / 1									*/
-#define CSEL_DIV2				0x0010	/* CCLK = VCO / 2									*/
-#define CSEL_DIV4				0x0020	/* CCLK = VCO / 4									*/
-#define CSEL_DIV8				0x0030	/* CCLK = VCO / 8									*/
-
-/* PLL_DIV Macros	*/
-#ifdef _MISRA_RULES
-#define SET_SSEL(x)			((x)&0xFu)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL					*/
-#else
-#define SET_SSEL(x)			((x)&0xF)	/* Set SSEL = 0-15 --> SCLK = VCO/SSEL					*/
-#endif /* _MISRA_RULES */
-
-/* VR_CTL Masks */
-#define WAKE_EN0				0x0100	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN0 signal		*/
-#define WAKE_EN1				0x0200	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN1 signal		*/
-#define WAKE_EN2				0x0400	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN2 signal		*/
-#define WAKE_EN3				0x0800	/* Enable Wakeup From Hibernate/Deep Sleep on the WAKEN3 signal		*/
-#define HIBERNATEB				0x1000	/* Bit mask for HIBERNATEB								*/
-#define HIBERNATE				0x0000	/* Deasserts EXT_WAKE in order to enter hibernate mode			*/
-#define EXTCLK_SEL				0x2000	/* Selects SCLK for the EXTCLK signal						*/
-#define EXTCLK_OE				0x4000	/* Output enable for the EXTCLK signal						*/
-#define WAKE_POLARITY			0x8000	/* Make wakeups active-high								*/
-
-/* PLL_STAT Masks	*/
-#define ACTIVE_PLLENABLED		0x0001	/* Processor In Active Mode With PLL Enabled				*/
-#define FULL_ON					0x0002	/* Processor In Full On Mode							*/
-#define ACTIVE_PLLDISABLED		0x0004	/* Processor In Active Mode With PLL Disabled				*/
-#define PLL_LOCKED				0x0020	/* PLL_LOCKCNT Has Been Reached						*/
-
-/* SWRST Masks */
-#define SYSTEM_RESET			0x0007	/* Initiates A System Software Reset					*/
-#define DOUBLE_FAULT			0x0008	/* Core Double Fault Causes Reset						*/
-#define RESET_DOUBLE			0x2000	/* SW Reset Generated By Core Double-Fault				*/
-#define RESET_WDOG				0x4000	/* SW Reset Generated By Watchdog Timer					*/
-#define RESET_SOFTWARE			0x8000	/* SW Reset Occurred Since Last Read Of SWRST				*/
-
-/* SYSCR Masks */
-#define BMODE_IDLE        		0x0000	/* Bypass boot ROM, go to idle 		*/
-#define BMODE_SPI1MEM           0x0002	/* Boot from serial SPI1 memory 						*/
-#define BMODE_SPI1HOST          0x0003	/* Boot from SPI1 host (slave mode) 					*/
-#define BMODE_SPI0MEM           0x0004	/* Boot from serial SPI0 memory 						*/
-#define BMODE_PPI        		0x0005	/* Boot from PPI Port 							*/
-#define BMODE_L1ROM         	0x0006	/* Boot from internal L1 ROM					*/
-#define BMODE_UART0HOST        	0x0007	/* Boot from UART0 host 							*/
-#define BMODE 					0x0007 	/* Boot Mode. Mirror of BMODE Mode Pins 					*/
-
-#define BCODE 					0x00F0
-#define BCODE_NORMAL 			0x0000 	/* normal boot, update PLL/VR, quickboot as by WURESET		*/
-#define BCODE_NOBOOT 			0x0010 	/* bypass boot, don't update PLL/VR 					*/
-#define BCODE_QUICKBOOT 		0x0020 	/* quick boot, overrule WURESET, don't update PLL/VR 			*/
-#define BCODE_ALLBOOT			0x0040 	/* no quick boot, overrule WURESET, don't update PLL/VR 		*/
-#define BCODE_FULLBOOT 			0x0060 	/* no quick boot, overrule WURESET, update PLL/VR 			*/
-
-#define WURESET 				0x1000 	/* wakeup event since last hardware reset			 		*/
-#define DFRESET 				0x2000 	/* recent reset was due to a double fault event 			*/
-#define WDRESET 				0x4000 	/* recent reset was due to a watchdog event 				*/
-#define SWRESET 				0x8000 	/* recent reset was issued by software 					*/
-
-/*********************************  SYSTEM INTERRUPT CONTROLLER MASKS *********************************************/
-/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
-#define IRQ_PLL_WAKEUP			0x00000001	/* PLL Wakeup Interrupt			 					*/
-#define IRQ_DMA_ERR0   			0x00000002  /* Error Interrupt (DMA error 0 interrupt (generic)) 			*/
-#define IRQ_PPI_ERR    			0x00000004  /* Error Interrupt (PPI error interrupt) 					*/
-#define IRQ_SPORT0_ERR 			0x00000008  /* Error Interrupt (SPORT0 status interrupt) 				*/
-#define IRQ_SPORT1_ERR 			0x00000010  /* Error Interrupt (SPORT1 status interrupt) 				*/
-#define IRQ_SPI0_ERR     		0x00000020  /* Error Interrupt (SPI0 status interrupt) 				*/
-#define IRQ_SPI1_ERR			0x00000040	/* Error Interrupt (SPI1 status interrupt)				*/
-#define IRQ_UART0_ERR 			0x00000080  /* Error Interrupt (UART0 status interrupt) 				*/
-#define IRQ_DMA0	   			0x00000100  /* DMA channel 0 (PPI) Interrupt 					*/
-#define IRQ_DMA1	   			0x00000200  /* DMA Channel 1 (SPORT0 RX) Interrupt				*/
-#define IRQ_DMA2	   			0x00000400  /* DMA Channel 2 (SPORT0 TX) Interrupt 				*/
-#define IRQ_DMA3	   			0x00000800  /* DMA Channel 3 (SPORT1 RX) Interrupt 					*/
-#define IRQ_DMA4	   			0x00001000  /* DMA Channel 4 (SPORT1 TX) Interrupt 					*/
-#define IRQ_DMA5	   			0x00002000  /* DMA Channel 5 (SPI0) Interrupt 					*/
-#define IRQ_DMA6	   			0x00004000  /* DMA Channel 6 (SPI1) Interrupt 		 			*/
-#define IRQ_DMA7	   			0x00008000  /* DMA Channel 7 (UART0 RX) Interrupt 						*/
-#define IRQ_DMA8	   			0x00010000  /* DMA Channel 8 (UART0 TX) Interrupt 					*/
-#define IRQ_PFA_PORTF			0x00020000	/* PF Port F Interrupt A		 					*/
-#define IRQ_PFB_PORTF			0x00040000	/* PF Port F Interrupt B 							*/
-#define IRQ_TIMER0				0x00080000	/* Timer 0 Interrupt								*/
-#define IRQ_TIMER1				0x00100000	/* Timer 1 Interrupt 								*/
-#define IRQ_TIMER2				0x00200000	/* Timer 2 Interrupt 								*/
-#define IRQ_PFA_PORTG			0x00400000	/* PF Port G Interrupt A 							*/
-#define IRQ_PFB_PORTG			0x00800000	/* PF Port G Interrupt B		 					*/
-#define IRQ_TWI			   		0x01000000  /* TWI Interrupt									*/
-#define IRQ_DMA12				0x20000000	/* DMA Channels 12 (MDMA0 Destination) TX Interrupt			*/
-#define IRQ_DMA13				0x20000000	/* DMA Channels 13 (MDMA0 Source) RX Interrupt				*/
-#define IRQ_DMA14				0x40000000	/* DMA Channels 14 (MDMA1 Destination) TX Interrupt			*/
-#define IRQ_DMA15				0x40000000	/* DMA Channels 15 (MDMA1 Source) RX Interrupt 				*/
-#define IRQ_WDOG				0x80000000	/* Software Watchdog Timer Interrupt 					*/
-
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
-#define IWR_DISABLE_ALL        	0x00000000	/* Wakeup Disable all peripherals 						*/
-#define IWR_ENABLE_ALL          	0xFFFFFFFF	/* Wakeup Enable all peripherals 						*/
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)           	(1 << (x))	/* Wakeup Enable Peripheral #x 						*/
-#define IWR_DISABLE(x)	 (0xFFFFFFFF^(1<<(x)))	/* Wakeup Disable Peripheral #x 						*/
-
-
-#ifdef _MISRA_RULES
-#define _MF15 	0xFu
-#define _MF7 	7u
-#else
-#define _MF15 	0xF
-#define _MF7 	7
-#endif /* _MISRA_RULES */
-
-
-/* SIC_IAR0 Macros*/
-#define P0_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #0 assigned IVG #x 	*/
-#define P1_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #1 assigned IVG #x 	*/
-#define P2_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #2 assigned IVG #x 	*/
-#define P3_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #3 assigned IVG #x	*/
-#define P4_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #4 assigned IVG #x	*/
-#define P5_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #5 assigned IVG #x	*/
-#define P6_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #6 assigned IVG #x	*/
-#define P7_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #7 assigned IVG #x	*/
-
-/* SIC_IAR1 Macros*/
-#define P8_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #8 assigned IVG #x 	*/
-#define P9_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #9 assigned IVG #x 	*/
-#define P10_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #10 assigned IVG #x 	*/
-#define P11_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #11 assigned IVG #x	*/
-#define P12_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #12 assigned IVG #x	*/
-#define P13_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #13 assigned IVG #x	*/
-#define P14_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #14 assigned IVG #x	*/
-#define P15_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #15 assigned IVG #x	*/
-
-/* SIC_IAR2 Macros*/
-#define P16_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #16 assigned IVG #x 	*/
-#define P17_IVG(x)		(((x)&_MF15)-_MF7) << 0x4	/* Peripheral #17 assigned IVG #x 	*/
-#define P18_IVG(x)		(((x)&_MF15)-_MF7) << 0x8	/* Peripheral #18 assigned IVG #x 	*/
-#define P19_IVG(x)		(((x)&_MF15)-_MF7) << 0xC	/* Peripheral #19 assigned IVG #x	*/
-#define P20_IVG(x)		(((x)&_MF15)-_MF7) << 0x10	/* Peripheral #20 assigned IVG #x	*/
-#define P21_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #21 assigned IVG #x	*/
-#define P22_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #22 assigned IVG #x	*/
-#define P23_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #23 assigned IVG #x	*/
-
-/* SIC_IAR3 Macros*/
-#define P24_IVG(x)		(((x)&_MF15)-_MF7)			/* Peripheral #24 assigned IVG #x 	*/
-#define P29_IVG(x)		(((x)&_MF15)-_MF7) << 0x14	/* Peripheral #29 assigned IVG #x	*/
-#define P30_IVG(x)		(((x)&_MF15)-_MF7) << 0x18	/* Peripheral #30 assigned IVG #x	*/
-#define P31_IVG(x)		(((x)&_MF15)-_MF7) << 0x1C	/* Peripheral #31 assigned IVG #x	*/
-
-
-/* SIC_IMASK0 Masks*/
-#define SIC_UNMASK0_ALL 0x00000000        /* Unmask all peripheral interrupts */
-#define SIC_MASK0_ALL   0xE1FFFFFF        /* Mask all peripheral interrupts   */
-
-/* SIC_IWR0 Masks*/
-#define IWR0_DISABLE_ALL 0x00000000       /* Wakeup Disable all peripherals   */
-#define IWR0_ENABLE_ALL  0xE1FFFFFF       /* Wakeup Enable all peripherals    */
-
-
-/* ************************************** WATCHDOG TIMER MASKS ****************************************************/
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-#ifdef _MISRA_RULES
-#define WDEV(x)	     (((x)<<1) & 0x0006u)	/* event generated on roll over 						*/
-#else
-#define WDEV(x) 		(((x)<<1) & 0x0006)	/* event generated on roll over 						*/
-#endif /* _MISRA_RULES */
-
-#define WDEV_RESET			0x0000	/* generate reset event on roll over					*/
-#define WDEV_NMI 				0x0002 	/* generate NMI event on roll over 						*/
-#define WDEV_GPI 				0x0004 	/* generate GP IRQ on roll over 						*/
-#define WDEV_NONE 			0x0006	/* no event on roll over 							*/
-#define WDEN 				0x0FF0 	/* enable watchdog 								*/
-#define WDDIS 				0x0AD0 	/* disable watchdog 								*/
-#define WDRO 				0x8000 	/* watchdog rolled over latch 						*/
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-#define ICTL 				WDEV
-#define ENABLE_RESET 			WDEV_RESET
-#define WDOG_RESET 			WDEV_RESET
-#define ENABLE_NMI 			WDEV_NMI
-#define WDOG_NMI 				WDEV_NMI
-#define ENABLE_GPI 			WDEV_GPI
-#define WDOG_GPI 				WDEV_GPI
-#define DISABLE_EVT 			WDEV_NONE
-#define WDOG_NONE 			WDEV_NONE
-
-#define TMR_EN 				WDEN
-#define TMR_DIS 				WDDIS
-#define TRO 				WDRO
-#define ICTL_P0 				0x01
-#define ICTL_P1 				0x02
-#define TRO_P 				0x0F
-
-
-/* ************************************ UART CONTROLLER MASKS *****************************************************/
-
-/* UARTx_LCR Masks*/
-#ifdef _MISRA_RULES
-#define WLS(x)		(((x)-5u) & 0x03u)	/* Word Length Select 								*/
-#else
-#define WLS(x)		  (((x)-5) & 0x03)	/* Word Length Select 								*/
-#endif /* _MISRA_RULES */
-
-#define STB					0x04		/* Stop Bits									*/
-#define PEN					0x08		/* Parity Enable									*/
-#define EPS					0x10		/* Even Parity Select								*/
-#define STP					0x20		/* Stick Parity									*/
-#define SB					0x40		/* Set Break									*/
-#define DLAB				0x80		/* Divisor Latch Access								*/
-
-/* UARTx_MCR Mask	*/
-#define LOOP_ENA				0x10		/* Loopback Mode Enable 							*/
-
-/* UARTx_LSR Masks */
-#define DR					0x01		/* Data Ready									*/
-#define OE					0x02		/* Overrun Error									*/
-#define PE					0x04		/* Parity Error									*/
-#define FE					0x08		/* Framing Error									*/
-#define BI					0x10		/* Break Interrupt								*/
-#define THRE				0x20		/* THR Empty									*/
-#define TEMT				0x40		/* TSR and UART_THR Empty							*/
-
-/* UARTx_IER Masks*/
-#define ERBFI				0x01		/* Enable Receive Buffer Full Interrupt					*/
-#define ETBEI				0x02		/* Enable Transmit Buffer Empty Interrupt					*/
-#define ELSI				0x04		/* Enable RX Status Interrupt							*/
-
-/* UARTx_IIR Masks*/
-#define NINT				0x01		/* Pending Interrupt								*/
-#define STATUS				0x06		/* Highest Priority Pending Interrupt					*/
-
-/* UARTx_GCTL Masks*/
-#define UCEN				0x01		/* Enable UARTx Clocks								*/
-#define IREN				0x02		/* Enable IrDA Mode								*/
-#define TPOLC				0x04		/* IrDA TX Polarity Change							*/
-#define RPOLC				0x08		/* IrDA RX Polarity Change							*/
-#define FPE					0x10		/* Force Parity Error On Transmit						*/
-#define FFE					0x20		/* Force Framing Error On Transmit						*/
-
-/* Bit masks for UART Divisor Latch Registers: UARTx_DLL & UARTx_DLH */
-#define UARTDLL                 	0x00FF	/* Divisor Latch Low Byte 							*/
-#define UARTDLH                	0xFF00	/* Divisor Latch High Byte 							*/
-
-
-/********************************  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ***************************************/
-
-/* SPIx_CTL Masks*/
-#define TIMOD				0x0003	/* Transfer Initiate Mode							*/
-#define RDBR_CORE				0x0000	/* RDBR Read Initiates, IRQ When RDBR Full				*/
-#define TDBR_CORE				0x0001	/* TDBR Write Initiates, IRQ When TDBR Empty				*/
-#define RDBR_DMA				0x0002	/* DMA Read, DMA Until FIFO Empty						*/
-#define TDBR_DMA				0x0003	/* DMA Write, DMA Until FIFO Full						*/
-#define SZ					0x0004	/* Send Zero (When TDBR Empty, Send Zero/Last*)				*/
-#define GM					0x0008	/* Get More (When RDBR Full, Overwrite/Discard*)			*/
-#define PSSE				0x0010	/* Slave-Select Input Enable							*/
-#define EMISO				0x0020	/* Enable MISO As Output							*/
-#define SIZE				0x0100	/* Size of Words (16/8* Bits)							*/
-#define LSBF				0x0200	/* LSB First									*/
-#define CPHA				0x0400	/* Clock Phase									*/
-#define CPOL				0x0800	/* Clock Polarity									*/
-#define MSTR				0x1000	/* Master/Slave*									*/
-#define WOM					0x2000	/* Write Open Drain Master							*/
-#define SPE					0x4000	/* SPI Enable									*/
-
-/* SPIx_FLG Masks*/
-#define FLS1				0x0002	/* Enables SPI_FLOUT1 as SPI Slave-Select Output			*/
-#define FLS2				0x0004	/* Enables SPI_FLOUT2 as SPI Slave-Select Output			*/
-#define FLS3				0x0008	/* Enables SPI_FLOUT3 as SPI Slave-Select Output			*/
-#define FLS4				0x0010	/* Enables SPI_FLOUT4 as SPI Slave-Select Output			*/
-#define FLS5				0x0020	/* Enables SPI_FLOUT5 as SPI Slave-Select Output			*/
-#define FLS6				0x0040	/* Enables SPI_FLOUT6 as SPI Slave-Select Output			*/
-#define FLS7				0x0080	/* Enables SPI_FLOUT7 as SPI Slave-Select Output			*/
-#define FLG1				0xFDFF	/* Activates SPI_FLOUT1 							*/
-#define FLG2				0xFBFF	/* Activates SPI_FLOUT2								*/
-#define FLG3				0xF7FF	/* Activates SPI_FLOUT3								*/
-#define FLG4				0xEFFF	/* Activates SPI_FLOUT4								*/
-#define FLG5				0xDFFF	/* Activates SPI_FLOUT5								*/
-#define FLG6				0xBFFF	/* Activates SPI_FLOUT6								*/
-#define FLG7				0x7FFF	/* Activates SPI_FLOUT7								*/
-
-/* SPIx_STAT Masks*/
-#define SPIF				0x0001	/* SPI Finished (Single-Word Transfer Complete)				*/
-#define MODF				0x0002	/* Mode Fault Error (Another Device Tried To Become Master)		*/
-#define TXE					0x0004	/* Transmission Error (Data Sent With No New Data In TDBR)		*/
-#define TXS					0x0008	/* SPI_TDBR Data Buffer Status (Full/Empty*)				*/
-#define RBSY				0x0010	/* Receive Error (Data Received With RDBR Full)				*/
-#define RXS					0x0020	/* SPI_RDBR Data Buffer Status (Full/Empty*)				*/
-#define TXCOL				0x0040	/* Transmit Collision Error (Corrupt Data May Have Been Sent)	*/
-
-
-/***********************************  GENERAL PURPOSE TIMER MASKS  ************************************************/
-/* TIMER_ENABLE Masks*/
-#define TIMEN0				0x0001	/* Enable Timer 0									*/
-#define TIMEN1				0x0002	/* Enable Timer 1									*/
-#define TIMEN2				0x0004	/* Enable Timer 2									*/
-
-/* TIMER_DISABLE Masks*/
-#define TIMDIS0				TIMEN0	/* Disable Timer 0								*/
-#define TIMDIS1				TIMEN1	/* Disable Timer 1								*/
-#define TIMDIS2				TIMEN2	/* Disable Timer 2								*/
-
-/* TIMER_STATUS Masks*/
-#define TIMIL0				0x00000001	/* Timer 0 Interrupt								*/
-#define TIMIL1				0x00000002	/* Timer 1 Interrupt								*/
-#define TIMIL2				0x00000004	/* Timer 2 Interrupt								*/
-#define TOVF_ERR0				0x00000010	/* Timer 0 Counter Overflow							*/
-#define TOVF_ERR1				0x00000020	/* Timer 1 Counter Overflow							*/
-#define TOVF_ERR2				0x00000040	/* Timer 2 Counter Overflow							*/
-#define TRUN0				0x00001000	/* Timer 0 Slave Enable Status						*/
-#define TRUN1				0x00002000	/* Timer 1 Slave Enable Status						*/
-#define TRUN2				0x00004000	/* Timer 2 Slave Enable Status						*/
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 			TOVF_ERR0
-#define TOVL_ERR1				TOVF_ERR1
-#define TOVL_ERR2 			TOVF_ERR2
-
-/* TIMERx_CONFIG Masks */
-#define PWM_OUT				0x0001	/* Pulse-Width Modulation Output Mode					*/
-#define WDTH_CAP				0x0002	/* Width Capture Input Mode							*/
-#define EXT_CLK				0x0003	/* External Clock Mode								*/
-#define PULSE_HI				0x0004	/* Action Pulse (Positive/Negative*)					*/
-#define PERIOD_CNT			0x0008	/* Period Count									*/
-#define IRQ_ENA				0x0010	/* Interrupt Request Enable							*/
-#define TIN_SEL				0x0020	/* Timer Input Select								*/
-#define OUT_DIS				0x0040	/* Output Pad Disable								*/
-#define CLK_SEL				0x0080	/* Timer Clock Select								*/
-#define TOGGLE_HI				0x0100	/* PWM_OUT PULSE_HI Toggle Mode						*/
-#define EMU_RUN				0x0200	/* Emulation Behavior Select							*/
-#define ERR_TYP				0xC000	/* Error Type									*/
-
-
-/* *************************************   GPIO PORTS F, G MASKS  **********************************************/
-
-/*  General Purpose IO Masks */
-/* Port F Masks */
-#define PF0					0x0001
-#define PF1					0x0002
-#define PF2					0x0004
-#define PF3					0x0008
-#define PF4					0x0010
-#define PF5					0x0020
-#define PF6					0x0040
-#define PF7					0x0080
-#define PF8					0x0100
-#define PF9					0x0200
-#define PF10				0x0400
-#define PF11				0x0800
-#define PF12				0x1000
-#define PF13				0x2000
-#define PF14				0x4000
-#define PF15				0x8000
-
-/* Port G Masks */
-#define PG0					0x0001
-#define PG1					0x0002
-#define PG2					0x0004
-#define PG3					0x0008
-#define PG4					0x0010
-#define PG5					0x0020
-#define PG6					0x0040
-#define PG7					0x0080
-#define PG8					0x0100
-#define PG9					0x0200
-#define PG10				0x0400
-#define PG11				0x0800
-#define PG12				0x1000
-#define PG13				0x2000
-#define PG14				0x4000
-#define PG15				0x8000
-
-/* **************************************  SERIAL PORT MASKS  *****************************************************/
-/* SPORT_GATECLK Masks */
-#define SPORT0_GATECLK_EN				0x0001	/* SPORT0 Clock Gating Enable							*/
-#define SPORT0_GATECLK_MODE				0x0002	/* SPORT0 Clock Gating Mode						*/
-#define SPORT0_GATECLK_STATE			0x0004	/* SPORT0 Clock Gating State								*/
-#define SPORT1_GATECLK_EN				0x0010	/* SPORT1 Clock Gating Enable							*/
-#define SPORT1_GATECLK_MODE				0x0020	/* SPORT1 Clock Gating Mode						*/
-#define SPORT1_GATECLK_STATE			0x0040	/* SPORT1 Clock Gating State								*/
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN				0x0001	/* Transmit Enable								*/
-#define ITCLK				0x0002	/* Internal Transmit Clock Select						*/
-#define DTYPE_NORM			0x0004	/* Data Format Normal								*/
-#define DTYPE_ULAW			0x0008	/* Compand Using u-Law								*/
-#define DTYPE_ALAW			0x000C	/* Compand Using A-Law								*/
-#define TLSBIT				0x0010	/* Transmit Bit Order								*/
-#define ITFS				0x0200	/* Internal Transmit Frame Sync Select					*/
-#define TFSR				0x0400	/* Transmit Frame Sync Required Select					*/
-#define DITFS				0x0800	/* Data-Independent Transmit Frame Sync Select				*/
-#define LTFS				0x1000	/* Low Transmit Frame Sync Select						*/
-#define LATFS				0x2000	/* Late Transmit Frame Sync Select						*/
-#define TCKFE				0x4000	/* Clock Falling Edge Select							*/
-
-/* SPORTx_TCR2 Masks and Macro */
-#ifdef _MISRA_RULES
-#define SLEN(x)				((x)&0x1Fu)	/* SPORT TX Word Length (2 - 31)						*/
-#else
-#define SLEN(x)				((x)&0x1F)	/* SPORT TX Word Length (2 - 31)						*/
-#endif /* _MISRA_RULES */
-
-#define TXSE				0x0100	/* TX Secondary Enable								*/
-#define TSFSE				0x0200	/* Transmit Stereo Frame Sync Enable					*/
-#define TRFST				0x0400	/* Left/Right Order (1 = Right Channel 1st)				*/
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN				0x0001	/* Receive Enable 								*/
-#define IRCLK				0x0002	/* Internal Receive Clock Select 						*/
-#define DTYPE_NORM			0x0004	/* Data Format Normal								*/
-#define DTYPE_ULAW			0x0008	/* Compand Using u-Law								*/
-#define DTYPE_ALAW			0x000C	/* Compand Using A-Law								*/
-#define RLSBIT				0x0010	/* Receive Bit Order								*/
-#define IRFS				0x0200	/* Internal Receive Frame Sync Select 					*/
-#define RFSR				0x0400	/* Receive Frame Sync Required Select 					*/
-#define LRFS				0x1000	/* Low Receive Frame Sync Select 						*/
-#define LARFS				0x2000	/* Late Receive Frame Sync Select 						*/
-#define RCKFE				0x4000	/* Clock Falling Edge Select 							*/
-
-/* SPORTx_RCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)				((x)&0x1Fu)	/* SPORT RX Word Length (2 - 31)						*/
-#else
-#define SLEN(x)				((x)&0x1F)	/* SPORT RX Word Length (2 - 31)						*/
-#endif /* _MISRA_RULES */
-
-#define RXSE				0x0100	/* RX Secondary Enable								*/
-#define RSFSE				0x0200	/* RX Stereo Frame Sync Enable						*/
-#define RRFST				0x0400	/* Right-First Data Order 							*/
-
-/* SPORTx_STAT Masks */
-#define RXNE				0x0001	/* Receive FIFO Not Empty Status						*/
-#define RUVF				0x0002	/* Sticky Receive Underflow Status						*/
-#define ROVF				0x0004	/* Sticky Receive Overflow Status						*/
-#define TXF					0x0008	/* Transmit FIFO Full Status							*/
-#define TUVF				0x0010	/* Sticky Transmit Underflow Status						*/
-#define TOVF				0x0020	/* Sticky Transmit Overflow Status						*/
-#define TXHRE				0x0040	/* Transmit Hold Register Empty						*/
-
-/* SPORTx_MCMC1 Macros */
-#ifdef _MISRA_RULES
-#define WOFF(x)		((x) & 0x3FFu) 		/* Multichannel Window Offset Field						*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits*/
-#define WSIZE(x)		(((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1				*/
-#else
-#define WOFF(x)		((x) & 0x3FF) 		/* Multichannel Window Offset Field						*/
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits								*/
-#define WSIZE(x)	(((((x)>>0x3)-1)&0xF) << 0xC)	/* Multichannel Window Size = (x/8)-1					*/
-#endif /* _MISRA_RULES */
-
-/* SPORTx_MCMC2 Masks */
-#define REC_BYPASS			0x0000	/* Bypass Mode (No Clock Recovery)						*/
-#define REC_2FROM4			0x0002	/* Recover 2 MHz Clock from 4 MHz Clock					*/
-#define REC_8FROM16			0x0003	/* Recover 8 MHz Clock from 16 MHz Clock					*/
-#define MCDTXPE				0x0004 	/* Multichannel DMA Transmit Packing					*/
-#define MCDRXPE				0x0008 	/* Multichannel DMA Receive Packing						*/
-#define MCMEN				0x0010 	/* Multichannel Frame Mode Enable						*/
-#define FSDR				0x0080 	/* Multichannel Frame Sync to Data Relationship				*/
-#define MFD_0				0x0000	/* Multichannel Frame Delay = 0						*/
-#define MFD_1				0x1000	/* Multichannel Frame Delay = 1						*/
-#define MFD_2				0x2000	/* Multichannel Frame Delay = 2						*/
-#define MFD_3				0x3000	/* Multichannel Frame Delay = 3						*/
-#define MFD_4				0x4000	/* Multichannel Frame Delay = 4						*/
-#define MFD_5				0x5000	/* Multichannel Frame Delay = 5						*/
-#define MFD_6				0x6000	/* Multichannel Frame Delay = 6						*/
-#define MFD_7				0x7000	/* Multichannel Frame Delay = 7						*/
-#define MFD_8				0x8000	/* Multichannel Frame Delay = 8						*/
-#define MFD_9				0x9000	/* Multichannel Frame Delay = 9						*/
-#define MFD_10				0xA000	/* Multichannel Frame Delay = 10						*/
-#define MFD_11				0xB000	/* Multichannel Frame Delay = 11						*/
-#define MFD_12				0xC000	/* Multichannel Frame Delay = 12						*/
-#define MFD_13				0xD000	/* Multichannel Frame Delay = 13						*/
-#define MFD_14				0xE000	/* Multichannel Frame Delay = 14						*/
-#define MFD_15				0xF000	/* Multichannel Frame Delay = 15						*/
-
-
-/****************************************  DMA CONTROLLER MASKS  **************************************************/
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN				0x0001	/* DMA Channel Enable								*/
-#define WNR					0x0002	/* Channel Direction (W/R*)							*/
-#define WDSIZE_8				0x0000	/* Transfer Word Size = 8							*/
-#define WDSIZE_16				0x0004	/* Transfer Word Size = 16							*/
-#define WDSIZE_32				0x0008	/* Transfer Word Size = 32							*/
-#define DMA2D				0x0010	/* DMA Mode (2D/1D*)								*/
-#define SYNC				0x0020	/* DMA Buffer Clear								*/
-#define DI_SEL				0x0040	/* Data Interrupt Timing Select						*/
-#define DI_EN				0x0080	/* Data Interrupt Enable							*/
-#define NDSIZE_0				0x0000	/* Next Descriptor Size = 0 (Stop/Autobuffer)				*/
-#define NDSIZE_1				0x0100	/* Next Descriptor Size = 1							*/
-#define NDSIZE_2				0x0200	/* Next Descriptor Size = 2							*/
-#define NDSIZE_3				0x0300	/* Next Descriptor Size = 3							*/
-#define NDSIZE_4				0x0400	/* Next Descriptor Size = 4							*/
-#define NDSIZE_5				0x0500	/* Next Descriptor Size = 5							*/
-#define NDSIZE_6				0x0600	/* Next Descriptor Size = 6							*/
-#define NDSIZE_7				0x0700	/* Next Descriptor Size = 7							*/
-#define NDSIZE_8				0x0800	/* Next Descriptor Size = 8							*/
-#define NDSIZE_9				0x0900	/* Next Descriptor Size = 9							*/
-#define FLOW_STOP				0x0000	/* Stop Mode									*/
-#define FLOW_AUTO				0x1000	/* Autobuffer Mode								*/
-#define FLOW_ARRAY			0x4000	/* Descriptor Array Mode							*/
-#define FLOW_SMALL			0x6000	/* Small Model Descriptor List Mode						*/
-#define FLOW_LARGE			0x7000	/* Large Model Descriptor List Mode						*/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE				0x0040	/* DMA Channel Type Indicator (Memory/Peripheral*)			*/
-#define PMAP				0xF000	/* Peripheral Mapped To This Channel					*/
-#define PMAP_PPI				0x0000	/* PPI Port DMA									*/
-#define PMAP_SPORT0RX			0x1000	/* SPORT0 Receive DMA								*/
-#define PMAP_SPORT0TX			0x2000	/* SPORT0 Transmit DMA								*/
-#define PMAP_SPORT1RX			0x3000	/* SPORT1 Receive DMA								*/
-#define PMAP_SPORT1TX			0x4000	/* SPORT1 Transmit DMA								*/
-#define PMAP_SPI0				0x5000	/* SPI0 Transmit/Receive DMA								*/
-#define PMAP_SPI1				0x6000	/* SPI1 Transmit/Receive DMA							*/
-#define PMAP_UART0RX			0x7000	/* UART0 Port Receive DMA							*/
-#define PMAP_UART0TX			0x8000	/* UART0 Port Transmit DMA							*/
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-#define DMA_DONE				0x0001	/* DMA Completion Interrupt Status						*/
-#define DMA_ERR				0x0002	/* DMA Error Interrupt Status							*/
-#define DFETCH				0x0004	/* DMA Descriptor Fetch Indicator						*/
-#define DMA_RUN				0x0008	/* DMA Channel Running Indicator						*/
-
-
-/*********************************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************************************/
-
-/*  PPI_CONTROL Masks */
-#define PORT_EN				0x0001	/* PPI Port Enable								*/
-#define PORT_DIR				0x0002	/* PPI Port Direction								*/
-#define XFR_TYPE				0x000C	/* PPI Transfer Type								*/
-#define PORT_CFG				0x0030	/* PPI Port Configuration							*/
-#define FLD_SEL				0x0040	/* PPI Active Field Select							*/
-#define PACK_EN				0x0080	/* PPI Packing Mode								*/ /* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN				0x0200	/* PPI Skip Element Enable							*/
-#define SKIP_EO				0x0400	/* PPI Skip Even/Odd Elements							*/
-#define DLEN_8				0x0000	/* Data Length = 8 Bits								*/
-#define DLEN_10				0x0800	/* Data Length = 10 Bits							*/
-#define DLEN_11				0x1000	/* Data Length = 11 Bits							*/
-#define DLEN_12				0x1800	/* Data Length = 12 Bits							*/
-#define DLEN_13				0x2000	/* Data Length = 13 Bits							*/
-#define DLEN_14				0x2800	/* Data Length = 14 Bits							*/
-#define DLEN_15				0x3000	/* Data Length = 15 Bits							*/
-#define DLEN_16				0x3800	/* Data Length = 16 Bits							*/
-#define POLC				0x4000	/* PPI Clock Polarity								*/
-#define POLS				0x8000	/* PPI Frame Sync Polarity							*/
-
-/* PPI_STATUS Masks */
-#define LT_ERR_OVR			0x0100	/* Line Track Overflow Error							*/
-#define LT_ERR_UNDR			0x0200	/* Line Track Underflow Error							*/
-#define FLD					0x0400	/* Field Indicator								*/
-#define FT_ERR				0x0800	/* Frame Track Error								*/
-#define OVR					0x1000	/* FIFO Overflow Error								*/
-#define UNDR				0x2000	/* FIFO Underrun Error								*/
-#define ERR_DET				0x4000	/* Error Detected Indicator							*/
-#define ERR_NCOR				0x8000	/* Error Not Corrected Indicator						*/
-
-
-/***************************************  TWO-WIRE INTERFACE (TWI) MASKS  *****************************************/
-
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)				((x) & 0xFFu)/* Periods Clock Is Held Low							*/
-#define CLKHI(y)				(((y)&0xFFu)<<0x8)/* Periods Before New Clock Low					*/
-#else
-#define CLKLOW(x)				((x) & 0xFF)/* Periods Clock Is Held Low							*/
-#define CLKHI(y)				(((y)&0xFF)<<0x8)	/* Periods Before New Clock Low					*/
-#endif /* _MISRA_RULES */
-
-/* TWI_PRESCALE Masks */
-#define PRESCALE				0x007F	/* SCLKs Per Internal Time Reference (10MHz)				*/
-#define TWI_ENA				0x0080	/* TWI Enable									*/
-#define SCCB				0x0200	/* SCCB Compatibility Enable							*/
-
-/* TWI_SLAVE_CTRL Masks */
-#define SEN					0x0001	/* Slave Enable									*/
-#define SADD_LEN				0x0002	/* Slave Address Length								*/
-#define STDVAL				0x0004	/* Slave Transmit Data Valid							*/
-#define NAK					0x0008	/* NAK/ACK* Generated At Conclusion Of Transfer 			*/
-#define GEN					0x0010	/* General Call Adrress Matching Enabled					*/
-
-/* TWI_SLAVE_STAT Masks	*/
-#define SDIR				0x0001	/* Slave Transfer Direction (Transmit/Receive*)				*/
-#define GCALL				0x0002	/* General Call Indicator							*/
-
-/* TWI_MASTER_CTRL Masks */
-#define MEN					0x0001	/* Master Mode Enable								*/
-#define MADD_LEN				0x0002	/* Master Address Length							*/
-#define MDIR				0x0004	/* Master Transmit Direction (RX/TX*)					*/
-#define FAST				0x0008	/* Use Fast Mode Timing Specs							*/
-#define STOP				0x0010	/* Issue Stop Condition								*/
-#define RSTART				0x0020	/* Repeat Start or Stop* At End Of Transfer				*/
-#define DCNT				0x3FC0	/* Data Bytes To Transfer							*/
-#define SDAOVR				0x4000	/* Serial Data Override								*/
-#define SCLOVR				0x8000	/* Serial Clock Override							*/
-
-/* TWI_MASTER_STAT Masks */
-#define MPROG				0x0001	/* Master Transfer In Progress						*/
-#define LOSTARB				0x0002	/* Lost Arbitration Indicator (Xfer Aborted)				*/
-#define ANAK				0x0004	/* Address Not Acknowledged							*/
-#define DNAK				0x0008	/* Data Not Acknowledged							*/
-#define BUFRDERR				0x0010	/* Buffer Read Error								*/
-#define BUFWRERR				0x0020	/* Buffer Write Error								*/
-#define SDASEN				0x0040	/* Serial Data Sense								*/
-#define SCLSEN				0x0080	/* Serial Clock Sense								*/
-#define BUSBUSY				0x0100	/* Bus Busy Indicator								*/
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
-#define SINIT				0x0001	/* Slave Transfer Initiated							*/
-#define SCOMP				0x0002	/* Slave Transfer Complete							*/
-#define SERR				0x0004	/* Slave Transfer Error								*/
-#define SOVF				0x0008	/* Slave Overflow									*/
-#define MCOMP				0x0010	/* Master Transfer Complete							*/
-#define MERR				0x0020	/* Master Transfer Error							*/
-#define XMTSERV				0x0040	/* Transmit FIFO Service							*/
-#define RCVSERV				0x0080	/* Receive FIFO Service								*/
-
-/* TWI_FIFO_CTRL Masks */
-#define XMTFLUSH				0x0001	/* Transmit Buffer Flush							*/
-#define RCVFLUSH				0x0002	/* Receive Buffer Flush								*/
-#define XMTINTLEN				0x0004	/* Transmit Buffer Interrupt Length						*/
-#define RCVINTLEN				0x0008	/* Receive Buffer Interrupt Length						*/
-
-/* TWI_FIFO_STAT Masks */
-#define XMTSTAT				0x0003	/* Transmit FIFO Status								*/
-#define XMT_EMPTY				0x0000	/* Transmit FIFO Empty								*/
-#define XMT_HALF				0x0001	/* Transmit FIFO Has 1 Byte To Write					*/
-#define XMT_FULL				0x0003	/* Transmit FIFO Full (2 Bytes To Write)					*/
-
-#define RCVSTAT				0x000C	/* Receive FIFO Status								*/
-#define RCV_EMPTY				0x0000	/* Receive FIFO Empty								*/
-#define RCV_HALF				0x0004	/* Receive FIFO Has 1 Byte To Read						*/
-#define RCV_FULL				0x000C	/* Receive FIFO Full (2 Bytes To Read)					*/
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BF59x_H */
diff --git a/libgloss/bfin/include/defBF606.h b/libgloss/bfin/include/defBF606.h
deleted file mode 100644
index 94e49a422..000000000
--- a/libgloss/bfin/include/defBF606.h
+++ /dev/null
@@ -1,17724 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* ================================================================================
-
-     Project      :   ADSP-BF606
-     File         :   defBF606.h
-     Description  :   Register Definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ================================================================================ */
-
-#ifndef _DEF_BF606_H
-#define _DEF_BF606_H
-
-#if defined (_MISRA_RULES)
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
-#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
-#endif /* _MISRA_RULES */
-
-/* do not add casts to literal constants in assembly code */
-#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
-#define _ADI_MSK( mask, type ) (mask) /* Make a bitmask */
-#else
-#define _ADI_MSK( mask, type ) ((type)(mask)) /* Make a bitmask */
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#ifndef __ADI_GENERATED_DEF_HEADERS__
-#define __ADI_GENERATED_DEF_HEADERS__    1
-#endif
-
-/* MMR modules defined for the ADSP-BF606 */
-
-#define __ADI_HAS_SYS__           1
-#define __ADI_HAS_SIMENV__        1
-#define __ADI_HAS_CNT__           1
-#define __ADI_HAS_RSI__           1
-#define __ADI_HAS_CAN__           1
-#define __ADI_HAS_LP__            1
-#define __ADI_HAS_TIMER__         1
-#define __ADI_HAS_CRC__           1
-#define __ADI_HAS_TWI__           1
-#define __ADI_HAS_UART__          1
-#define __ADI_HAS_PORT__          1
-#define __ADI_HAS_PADS__          1
-#define __ADI_HAS_PINT__          1
-#define __ADI_HAS_SMC__           1
-#define __ADI_HAS_WDOG__          1
-#define __ADI_HAS_EPPI__          1
-#define __ADI_HAS_PWM__           1
-#define __ADI_HAS_VID__           1
-#define __ADI_HAS_SWU__           1
-#define __ADI_HAS_SDU__           1
-#define __ADI_HAS_EMAC__          1
-#define __ADI_HAS_SPORT__         1
-#define __ADI_HAS_SPI__           1
-#define __ADI_HAS_DMA__           1
-#define __ADI_HAS_ACM__           1
-#define __ADI_HAS_DMC__           1
-#define __ADI_HAS_SCB__           1
-#define __ADI_HAS_L2CTL__         1
-#define __ADI_HAS_SEC__           1
-#define __ADI_HAS_TRU__           1
-#define __ADI_HAS_RCU__           1
-#define __ADI_HAS_SPU__           1
-#define __ADI_HAS_CGU__           1
-#define __ADI_HAS_DPM__           1
-#define __ADI_HAS_EFS__           1
-#define __ADI_HAS_USB__           1
-#define __ADI_HAS_L1DM__          1
-#define __ADI_HAS_L1IM__          1
-#define __ADI_HAS_ICU__           1
-#define __ADI_HAS_TMR__           1
-#define __ADI_HAS_DBG__           1
-#define __ADI_HAS_TB__            1
-#define __ADI_HAS_WP__            1
-#define __ADI_HAS_PF__            1
-
-/* =========================
-        REGFILE
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ASTAT                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ASTAT_VS                        25                               /* Sticky version of ASTAT_V */
-#define BITP_ASTAT_V                         24                               /* Overflow Flag */
-#define BITP_ASTAT_AV1S                      19                               /* Sticky Overflow Flag 1 */
-#define BITP_ASTAT_AV1                       18                               /* Overflow Flag 1 */
-#define BITP_ASTAT_AV0S                      17                               /* Sticky Overflow Flag 0 */
-#define BITP_ASTAT_AV0                       16                               /* Overflow Flag 0 */
-#define BITP_ASTAT_AC1                       13                               /* Carry Flag 1 */
-#define BITP_ASTAT_AC0                       12                               /* Carry Flag 0 */
-#define BITP_ASTAT_RND_MOD                    8                               /* Rounding Mode */
-#define BITP_ASTAT_AQ                         6                               /* Quotient Bit */
-#define BITP_ASTAT_CC                         5                               /* Condition Code */
-#define BITP_ASTAT_V_COPY                     3                               /* Overflow Flag */
-#define BITP_ASTAT_AC0_COPY                   2                               /* Carry Flag 0 */
-#define BITP_ASTAT_AN                         1                               /* Negative Flag */
-#define BITP_ASTAT_AZ                         0                               /* Zero Flag */
-#define BITM_ASTAT_VS                        (_ADI_MSK(0x02000000,uint32_t))  /* Sticky version of ASTAT_V */
-#define BITM_ASTAT_V                         (_ADI_MSK(0x01000000,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AV1S                      (_ADI_MSK(0x00080000,uint32_t))  /* Sticky Overflow Flag 1 */
-#define BITM_ASTAT_AV1                       (_ADI_MSK(0x00040000,uint32_t))  /* Overflow Flag 1 */
-#define BITM_ASTAT_AV0S                      (_ADI_MSK(0x00020000,uint32_t))  /* Sticky Overflow Flag 0 */
-#define BITM_ASTAT_AV0                       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow Flag 0 */
-#define BITM_ASTAT_AC1                       (_ADI_MSK(0x00002000,uint32_t))  /* Carry Flag 1 */
-#define BITM_ASTAT_AC0                       (_ADI_MSK(0x00001000,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_RND_MOD                   (_ADI_MSK(0x00000100,uint32_t))  /* Rounding Mode */
-#define BITM_ASTAT_AQ                        (_ADI_MSK(0x00000040,uint32_t))  /* Quotient Bit */
-#define BITM_ASTAT_CC                        (_ADI_MSK(0x00000020,uint32_t))  /* Condition Code */
-#define BITM_ASTAT_V_COPY                    (_ADI_MSK(0x00000008,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AC0_COPY                  (_ADI_MSK(0x00000004,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_AN                        (_ADI_MSK(0x00000002,uint32_t))  /* Negative Flag */
-#define BITM_ASTAT_AZ                        (_ADI_MSK(0x00000001,uint32_t))  /* Zero Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LT                                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LT_ADDR                          1                               /* Loop Top Address */
-#define BITP_LT_LSB                           0
-#define BITM_LT_ADDR                         (_ADI_MSK(0xFFFFFFFE,uint32_t))  /* Loop Top Address */
-#define BITM_LT_LSB                          (_ADI_MSK(0x00000001,uint32_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEQSTAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEQSTAT_NSPECABT                19                               /* Nonspeculative access was aborted */
-#define BITP_SEQSTAT_HWERRCAUSE              14                               /* Holds cause of last hardware error generated by the core */
-#define BITP_SEQSTAT_SFTRESET                13                               /* Indicates whether the last reset was a software reset */
-#define BITP_SEQSTAT_ITESTABT                12                               /* ITEST_COMMAND was aborted */
-#define BITP_SEQSTAT_DTESTABT                11                               /* DTEST_COMMAND was aborted */
-#define BITP_SEQSTAT_SYSNMI                  10                               /* System NMI Input Active */
-#define BITP_SEQSTAT_PEIC                     9                               /* Parity Error on Instruction L1 Read for Core */
-#define BITP_SEQSTAT_PEDC                     8                               /* Parity Error on Data L1 Read for Core */
-#define BITP_SEQSTAT_PEIX                     7                               /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_PEDX                     6                               /* Parity Error on Data L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_EXCAUSE                  0                               /* Holds cause of last-executed exception */
-#define BITM_SEQSTAT_NSPECABT                (_ADI_MSK(0x00080000,uint32_t))  /* Nonspeculative access was aborted */
-#define BITM_SEQSTAT_HWERRCAUSE              (_ADI_MSK(0x0007C000,uint32_t))  /* Holds cause of last hardware error generated by the core */
-#define BITM_SEQSTAT_SFTRESET                (_ADI_MSK(0x00002000,uint32_t))  /* Indicates whether the last reset was a software reset */
-#define BITM_SEQSTAT_ITESTABT                (_ADI_MSK(0x00001000,uint32_t))  /* ITEST_COMMAND was aborted */
-#define BITM_SEQSTAT_DTESTABT                (_ADI_MSK(0x00000800,uint32_t))  /* DTEST_COMMAND was aborted */
-#define BITM_SEQSTAT_SYSNMI                  (_ADI_MSK(0x00000400,uint32_t))  /* System NMI Input Active */
-#define BITM_SEQSTAT_PEIC                    (_ADI_MSK(0x00000200,uint32_t))  /* Parity Error on Instruction L1 Read for Core */
-#define BITM_SEQSTAT_PEDC                    (_ADI_MSK(0x00000100,uint32_t))  /* Parity Error on Data L1 Read for Core */
-#define BITM_SEQSTAT_PEIX                    (_ADI_MSK(0x00000080,uint32_t))  /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITM_SEQSTAT_PEDX                    (_ADI_MSK(0x00000040,uint32_t))  /* Parity Error on Data L1 Read for L2 Transfer */
-
-#define BITM_SEQSTAT_EXCAUSE                 (_ADI_MSK(0x0000003F,uint32_t))  /* Holds cause of last-executed exception */
-#define ENUM_SEQSTAT_EXINST                  (_ADI_MSK(0x00000000,uint32_t))  /* EXCAUSE: EXCPT Instruction */
-#define ENUM_SEQSTAT_SSTEP                   (_ADI_MSK(0x00000010,uint32_t))  /* EXCAUSE: Single Step */
-#define ENUM_SEQSTAT_EMUTROV                 (_ADI_MSK(0x00000011,uint32_t))  /* EXCAUSE: Trace Buffer */
-#define ENUM_SEQSTAT_UNDEFINST               (_ADI_MSK(0x00000021,uint32_t))  /* EXCAUSE: Undefined Instruction */
-#define ENUM_SEQSTAT_ILLCOMB                 (_ADI_MSK(0x00000022,uint32_t))  /* EXCAUSE: Illegal Combination */
-#define ENUM_SEQSTAT_DAGPROTVIOL             (_ADI_MSK(0x00000023,uint32_t))  /* EXCAUSE: DAG Protection Violation */
-#define ENUM_SEQSTAT_DAGALGN                 (_ADI_MSK(0x00000024,uint32_t))  /* EXCAUSE: DAG Misaligned Access */
-#define ENUM_SEQSTAT_UNRECOVER               (_ADI_MSK(0x00000025,uint32_t))  /* EXCAUSE: Unrecoverable Event */
-#define ENUM_SEQSTAT_DAGCPLBMISS             (_ADI_MSK(0x00000026,uint32_t))  /* EXCAUSE: DAG CPLB Miss */
-#define ENUM_SEQSTAT_DAGMCPLBH               (_ADI_MSK(0x00000027,uint32_t))  /* EXCAUSE: DAG Multiple CPLB Hits */
-#define ENUM_SEQSTAT_EMUWPMATCH              (_ADI_MSK(0x00000028,uint32_t))  /* EXCAUSE: Watchpoint Match */
-#define ENUM_SEQSTAT_IFALGN                  (_ADI_MSK(0x0000002A,uint32_t))  /* EXCAUSE: I-Fetch Misaligned Access */
-#define ENUM_SEQSTAT_IFPROTVIOL              (_ADI_MSK(0x0000002B,uint32_t))  /* EXCAUSE: I-Fetch Protection Violation */
-#define ENUM_SEQSTAT_IFCPLBMISS              (_ADI_MSK(0x0000002C,uint32_t))  /* EXCAUSE: I-Fetch CPLB Miss */
-#define ENUM_SEQSTAT_IFMCPLBH                (_ADI_MSK(0x0000002D,uint32_t))  /* EXCAUSE: I-Fetch Multiple CPLB Hits */
-#define ENUM_SEQSTAT_PROTVIOL                (_ADI_MSK(0x0000002E,uint32_t))  /* EXCAUSE: Illegal use superv. res */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SYSCFG                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SYSCFG_SNEN                      2                               /* Self-Nesting Interrupt Enable */
-#define BITP_SYSCFG_CCEN                      1                               /* Enable cycle counter */
-#define BITP_SYSCFG_SSSTEP                    0                               /* Supervisor single step */
-#define BITM_SYSCFG_SNEN                     (_ADI_MSK(0x00000004,uint32_t))  /* Self-Nesting Interrupt Enable */
-#define BITM_SYSCFG_CCEN                     (_ADI_MSK(0x00000002,uint32_t))  /* Enable cycle counter */
-#define BITM_SYSCFG_SSSTEP                   (_ADI_MSK(0x00000001,uint32_t))  /* Supervisor single step */
-
-/* ==================================================
-        CNT Registers
-   ================================================== */
-
-/* =========================
-        CNT0
-   ========================= */
-#define REG_CNT0_CFG                    0xFFC00400         /* CNT0 Configuration Register */
-#define REG_CNT0_IMSK                   0xFFC00404         /* CNT0 Interrupt Mask Register */
-#define REG_CNT0_STAT                   0xFFC00408         /* CNT0 Status Register */
-#define REG_CNT0_CMD                    0xFFC0040C         /* CNT0 Command Register */
-#define REG_CNT0_DEBNCE                 0xFFC00410         /* CNT0 Debounce Register */
-#define REG_CNT0_CNTR                   0xFFC00414         /* CNT0 Counter Register */
-#define REG_CNT0_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
-#define REG_CNT0_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
-
-/* =========================
-        CNT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CFG_INPDIS                  15                               /* CUD and CDG Pin Input Disable */
-#define BITP_CNT_CFG_BNDMODE                 12                               /* Boundary Register Mode */
-#define BITP_CNT_CFG_ZMZC                    11                               /* CZM Zeroes Counter Enable */
-#define BITP_CNT_CFG_CNTMODE                  8                               /* Counter Operating Mode */
-#define BITP_CNT_CFG_CZMINV                   6                               /* CZM Pin Polarity Invert */
-#define BITP_CNT_CFG_CUDINV                   5                               /* CUD Pin Polarity Invert */
-#define BITP_CNT_CFG_CDGINV                   4                               /* CDG Pin Polarity Invert */
-#define BITP_CNT_CFG_DEBEN                    1                               /* Debounce Enable */
-#define BITP_CNT_CFG_EN                       0                               /* Counter Enable */
-
-#define BITM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* CUD and CDG Pin Input Disable */
-#define ENUM_CNT_CFG_NO_INPDIS               (_ADI_MSK(0x00000000,uint16_t))  /* INPDIS: Enable */
-#define ENUM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* INPDIS: Pin Input Disable */
-
-#define BITM_CNT_CFG_BNDMODE                 (_ADI_MSK(0x00003000,uint16_t))  /* Boundary Register Mode */
-#define ENUM_CNT_CFG_BNDMODE_BNDCOMP         (_ADI_MSK(0x00000000,uint16_t))  /* BNDMODE: BND_COMP */
-#define ENUM_CNT_CFG_BNDMODE_BINENC          (_ADI_MSK(0x00001000,uint16_t))  /* BNDMODE: BIN_ENC */
-#define ENUM_CNT_CFG_BNDMODE_BNDCAPT         (_ADI_MSK(0x00002000,uint16_t))  /* BNDMODE: BND_CAPT */
-#define ENUM_CNT_CFG_BNDMODE_BNDAEXT         (_ADI_MSK(0x00003000,uint16_t))  /* BNDMODE: BND_AEXT */
-
-#define BITM_CNT_CFG_ZMZC                    (_ADI_MSK(0x00000800,uint16_t))  /* CZM Zeroes Counter Enable */
-#define ENUM_CNT_CFG_ZMZC_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* ZMZC: Disable */
-#define ENUM_CNT_CFG_ZMZC_EN                 (_ADI_MSK(0x00000800,uint16_t))  /* ZMZC: Enable */
-
-#define BITM_CNT_CFG_CNTMODE                 (_ADI_MSK(0x00000700,uint16_t))  /* Counter Operating Mode */
-#define ENUM_CNT_CFG_CNTMODE_QUADENC         (_ADI_MSK(0x00000000,uint16_t))  /* CNTMODE: QUAD_ENC */
-#define ENUM_CNT_CFG_CNTMODE_BINENC          (_ADI_MSK(0x00000100,uint16_t))  /* CNTMODE: BIN_ENC */
-#define ENUM_CNT_CFG_CNTMODE_UDCNT           (_ADI_MSK(0x00000200,uint16_t))  /* CNTMODE: UD_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRCNT          (_ADI_MSK(0x00000400,uint16_t))  /* CNTMODE: DIR_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRTMR          (_ADI_MSK(0x00000500,uint16_t))  /* CNTMODE: DIR_TMR */
-
-#define BITM_CNT_CFG_CZMINV                  (_ADI_MSK(0x00000040,uint16_t))  /* CZM Pin Polarity Invert */
-#define ENUM_CNT_CFG_CZMINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CZMINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CZMINV_ALO              (_ADI_MSK(0x00000040,uint16_t))  /* CZMINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CUDINV                  (_ADI_MSK(0x00000020,uint16_t))  /* CUD Pin Polarity Invert */
-#define ENUM_CNT_CFG_CUDINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CUDINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CUDINV_ALO              (_ADI_MSK(0x00000020,uint16_t))  /* CUDINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CDGINV                  (_ADI_MSK(0x00000010,uint16_t))  /* CDG Pin Polarity Invert */
-#define ENUM_CNT_CFG_CDGINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CDGINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CDGINV_ALO              (_ADI_MSK(0x00000010,uint16_t))  /* CDGINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* Debounce Enable */
-#define ENUM_CNT_CFG_DEBDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* DEBEN: Disable */
-#define ENUM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* DEBEN: Enable */
-
-#define BITM_CNT_CFG_EN                      (_ADI_MSK(0x00000001,uint16_t))  /* Counter Enable */
-#define ENUM_CNT_CFG_CNTDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Counter Disable */
-#define ENUM_CNT_CFG_CNTEN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Counter Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_IMSK_CZMZ                   10                               /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define BITP_CNT_IMSK_CZME                    9                               /* Zero Marker Error Interrupt Enable */
-#define BITP_CNT_IMSK_CZM                     8                               /* CZM Pin / Pushbutton Interrupt Enable */
-#define BITP_CNT_IMSK_CZERO                   7                               /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define BITP_CNT_IMSK_COV15                   6                               /* Bit 15 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_COV31                   5                               /* Bit 31 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_MAXC                    4                               /* Max Count Interrupt Enable */
-#define BITP_CNT_IMSK_MINC                    3                               /* Min Count Interrupt Enable */
-#define BITP_CNT_IMSK_DC                      2                               /* Downcount Interrupt enable */
-#define BITP_CNT_IMSK_UC                      1                               /* Upcount Interrupt Enable */
-#define BITP_CNT_IMSK_IC                      0                               /* Illegal Gray/Binary Code Interrupt Enable */
-
-#define BITM_CNT_IMSK_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define ENUM_CNT_IMSK_CZMZ_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZMZ: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZMZ_UMSK              (_ADI_MSK(0x00000400,uint16_t))  /* CZMZ: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error Interrupt Enable */
-#define ENUM_CNT_IMSK_CZME_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZME: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZME_UMSK              (_ADI_MSK(0x00000200,uint16_t))  /* CZME: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin / Pushbutton Interrupt Enable */
-#define ENUM_CNT_IMSK_CZM_MSK                (_ADI_MSK(0x00000000,uint16_t))  /* CZM: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZM_UMSK               (_ADI_MSK(0x00000100,uint16_t))  /* CZM: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define ENUM_CNT_IMSK_CZERO_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* CZERO: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZERO_UMSK             (_ADI_MSK(0x00000080,uint16_t))  /* CZERO: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV15_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV15: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV15_UMSK             (_ADI_MSK(0x00000040,uint16_t))  /* COV15: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV31_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV31: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV31_UMSK             (_ADI_MSK(0x00000020,uint16_t))  /* COV31: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MAXC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MAXC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MAXC_UMSK              (_ADI_MSK(0x00000010,uint16_t))  /* MAXC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MINC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MINC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MINC_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* MINC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount Interrupt enable */
-#define ENUM_CNT_IMSK_DC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* DC: Mask Interrupt */
-#define ENUM_CNT_IMSK_DC_UMSK                (_ADI_MSK(0x00000004,uint16_t))  /* DC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount Interrupt Enable */
-#define ENUM_CNT_IMSK_UC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* UC: Mask Interrupt */
-#define ENUM_CNT_IMSK_UC_UMSK                (_ADI_MSK(0x00000002,uint16_t))  /* UC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal Gray/Binary Code Interrupt Enable */
-#define ENUM_CNT_IMSK_IC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* IC: Mask Interrupt */
-#define ENUM_CNT_IMSK_IC_UMSK                (_ADI_MSK(0x00000001,uint16_t))  /* IC: Unmask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_STAT_CZMZ                   10                               /* Counter Zeroed By Zero Marker interrupt */
-#define BITP_CNT_STAT_CZME                    9                               /* Zero Marker Error interrupt */
-#define BITP_CNT_STAT_CZM                     8                               /* CZM Pin/Pushbutton interrupt */
-#define BITP_CNT_STAT_CZERO                   7                               /* CNT_CNTR Counts To Zero interrupt */
-#define BITP_CNT_STAT_COV15                   6                               /* Bit 15 overflow interrupt */
-#define BITP_CNT_STAT_COV31                   5                               /* Bit 31 overflow interrupt */
-#define BITP_CNT_STAT_MAXC                    4                               /* Max interrupt */
-#define BITP_CNT_STAT_MINC                    3                               /* Min interrupt */
-#define BITP_CNT_STAT_DC                      2                               /* Downcount interrupt */
-#define BITP_CNT_STAT_UC                      1                               /* Upcount interrupt */
-#define BITP_CNT_STAT_IC                      0                               /* Illegal gray/binary code interrupt */
-#define BITM_CNT_STAT_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed By Zero Marker interrupt */
-#define BITM_CNT_STAT_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error interrupt */
-#define BITM_CNT_STAT_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin/Pushbutton interrupt */
-#define BITM_CNT_STAT_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero interrupt */
-#define BITM_CNT_STAT_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 overflow interrupt */
-#define BITM_CNT_STAT_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 overflow interrupt */
-#define BITM_CNT_STAT_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max interrupt */
-#define BITM_CNT_STAT_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min interrupt */
-#define BITM_CNT_STAT_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount interrupt */
-#define BITM_CNT_STAT_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount interrupt */
-#define BITM_CNT_STAT_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal gray/binary code interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CMD_W1ZMONCE                12                               /* Write 1 Zero Marker Clear Once Enable */
-#define BITP_CNT_CMD_W1LMAXMIN               10                               /* Write 1 MAX copy from MIN */
-#define BITP_CNT_CMD_W1LMAXCNT                9                               /* Write 1 MAX capture from CNTR */
-#define BITP_CNT_CMD_W1LMAXZERO               8                               /* Write 1 MAX to zero */
-#define BITP_CNT_CMD_W1LMINMAX                7                               /* Write 1 MIN copy from MAX */
-#define BITP_CNT_CMD_W1LMINCNT                5                               /* Write 1 MIN capture from CNTR */
-#define BITP_CNT_CMD_W1LMINZERO               4                               /* Write 1 MIN to zero */
-#define BITP_CNT_CMD_W1LCNTMAX                3                               /* Write 1 CNTR load from MAX */
-#define BITP_CNT_CMD_W1LCNTMIN                2                               /* Write 1 CNTR load from MIN */
-#define BITP_CNT_CMD_W1LCNTZERO               0                               /* Write 1 CNTR to zero */
-#define BITM_CNT_CMD_W1ZMONCE                (_ADI_MSK(0x00001000,uint16_t))  /* Write 1 Zero Marker Clear Once Enable */
-#define BITM_CNT_CMD_W1LMAXMIN               (_ADI_MSK(0x00000400,uint16_t))  /* Write 1 MAX copy from MIN */
-#define BITM_CNT_CMD_W1LMAXCNT               (_ADI_MSK(0x00000200,uint16_t))  /* Write 1 MAX capture from CNTR */
-#define BITM_CNT_CMD_W1LMAXZERO              (_ADI_MSK(0x00000100,uint16_t))  /* Write 1 MAX to zero */
-#define BITM_CNT_CMD_W1LMINMAX               (_ADI_MSK(0x00000080,uint16_t))  /* Write 1 MIN copy from MAX */
-#define BITM_CNT_CMD_W1LMINCNT               (_ADI_MSK(0x00000020,uint16_t))  /* Write 1 MIN capture from CNTR */
-#define BITM_CNT_CMD_W1LMINZERO              (_ADI_MSK(0x00000010,uint16_t))  /* Write 1 MIN to zero */
-#define BITM_CNT_CMD_W1LCNTMAX               (_ADI_MSK(0x00000008,uint16_t))  /* Write 1 CNTR load from MAX */
-#define BITM_CNT_CMD_W1LCNTMIN               (_ADI_MSK(0x00000004,uint16_t))  /* Write 1 CNTR load from MIN */
-#define BITM_CNT_CMD_W1LCNTZERO              (_ADI_MSK(0x00000001,uint16_t))  /* Write 1 CNTR to zero */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_DEBNCE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_DEBNCE_DPRESCALE             0                               /* Debounce Prescale */
-#define BITM_CNT_DEBNCE_DPRESCALE            (_ADI_MSK(0x0000001F,uint16_t))  /* Debounce Prescale */
-
-/* ==================================================
-        RSI Registers
-   ================================================== */
-
-/* =========================
-        RSI0
-   ========================= */
-#define REG_RSI0_CTL                    0xFFC00604         /* RSI0 Control Register */
-#define REG_RSI0_ARG                    0xFFC00608         /* RSI0 Argument Register */
-#define REG_RSI0_CMD                    0xFFC0060C         /* RSI0 Command Register */
-#define REG_RSI0_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
-#define REG_RSI0_RESP0                  0xFFC00614         /* RSI0 Response 0 Register */
-#define REG_RSI0_RESP1                  0xFFC00618         /* RSI0 Response 1 Register */
-#define REG_RSI0_RESP2                  0xFFC0061C         /* RSI0 Response 2 Register */
-#define REG_RSI0_RESP3                  0xFFC00620         /* RSI0 Response 3 Register */
-#define REG_RSI0_DATA_TMR               0xFFC00624         /* RSI0 Data Timer Register */
-#define REG_RSI0_DATA_LEN               0xFFC00628         /* RSI0 Data Length Register */
-#define REG_RSI0_DATA_CTL               0xFFC0062C         /* RSI0 Data Control Register */
-#define REG_RSI0_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
-#define REG_RSI0_XFRSTAT                0xFFC00634         /* RSI0 Status Register */
-#define REG_RSI0_XFRSTAT_CLR            0xFFC00638         /* RSI0 Status Clear Register */
-#define REG_RSI0_XFR_IMSK0              0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
-#define REG_RSI0_XFR_IMSK1              0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
-#define REG_RSI0_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
-#define REG_RSI0_CEATA                  0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
-#define REG_RSI0_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
-#define REG_RSI0_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
-#define REG_RSI0_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
-#define REG_RSI0_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
-#define REG_RSI0_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
-#define REG_RSI0_STAT0                  0xFFC006C0         /* RSI0 Exception Status Register */
-#define REG_RSI0_IMSK0                  0xFFC006C4         /* RSI0 Exception Mask Register */
-#define REG_RSI0_CFG                    0xFFC006C8         /* RSI0 Configuration Register */
-#define REG_RSI0_RD_WAIT                0xFFC006CC         /* RSI0 Read Wait Enable Register */
-#define REG_RSI0_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
-
-/* =========================
-        RSI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CTL_CARDTYPE                13                               /* Type of Card */
-#define BITP_RSI_CTL_BUSWID                  11                               /* Wide Bus Mode Enable */
-#define BITP_RSI_CTL_BYPASS                  10                               /* Bypass clock divisor */
-#define BITP_RSI_CTL_PWRSAVE                  9                               /* Power Save Enable */
-#define BITP_RSI_CTL_CLKEN                    8                               /* RSI_CLK Bus Clock Enable */
-#define BITP_RSI_CTL_CLKDIV                   0                               /* RSI_CLK Divisor */
-#define BITM_RSI_CTL_CARDTYPE                (_ADI_MSK(0x0000E000,uint16_t))  /* Type of Card */
-#define BITM_RSI_CTL_BUSWID                  (_ADI_MSK(0x00001800,uint16_t))  /* Wide Bus Mode Enable */
-#define BITM_RSI_CTL_BYPASS                  (_ADI_MSK(0x00000400,uint16_t))  /* Bypass clock divisor */
-#define BITM_RSI_CTL_PWRSAVE                 (_ADI_MSK(0x00000200,uint16_t))  /* Power Save Enable */
-#define BITM_RSI_CTL_CLKEN                   (_ADI_MSK(0x00000100,uint16_t))  /* RSI_CLK Bus Clock Enable */
-#define BITM_RSI_CTL_CLKDIV                  (_ADI_MSK(0x000000FF,uint16_t))  /* RSI_CLK Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CMD_CHKBUSY                 12                               /* Check Busy Condition */
-#define BITP_RSI_CMD_CRCDIS                  11                               /* Disable CRC Check */
-#define BITP_RSI_CMD_EN                      10                               /* Command Enable */
-#define BITP_RSI_CMD_PNDEN                    9                               /* Command Pending enabled */
-#define BITP_RSI_CMD_IEN                      8                               /* Command Interrupt Enabled */
-#define BITP_RSI_CMD_LRSP                     7                               /* Long Response */
-#define BITP_RSI_CMD_RSP                      6                               /* Response */
-#define BITP_RSI_CMD_IDX                      0                               /* Command Index */
-#define BITM_RSI_CMD_CHKBUSY                 (_ADI_MSK(0x00001000,uint16_t))  /* Check Busy Condition */
-#define BITM_RSI_CMD_CRCDIS                  (_ADI_MSK(0x00000800,uint16_t))  /* Disable CRC Check */
-#define BITM_RSI_CMD_EN                      (_ADI_MSK(0x00000400,uint16_t))  /* Command Enable */
-#define BITM_RSI_CMD_PNDEN                   (_ADI_MSK(0x00000200,uint16_t))  /* Command Pending enabled */
-#define BITM_RSI_CMD_IEN                     (_ADI_MSK(0x00000100,uint16_t))  /* Command Interrupt Enabled */
-#define BITM_RSI_CMD_LRSP                    (_ADI_MSK(0x00000080,uint16_t))  /* Long Response */
-#define BITM_RSI_CMD_RSP                     (_ADI_MSK(0x00000040,uint16_t))  /* Response */
-#define BITM_RSI_CMD_IDX                     (_ADI_MSK(0x0000003F,uint16_t))  /* Command Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RESP_CMD                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RESP_CMD_VALUE               0                               /* Response Command */
-#define BITM_RSI_RESP_CMD_VALUE              (_ADI_MSK(0x0000003F,uint16_t))  /* Response Command */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_DATA_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_DATA_CTL_CEATAIEN            9                               /* Ceata Command Completion Interrupt Enable */
-#define BITP_RSI_DATA_CTL_CEATAMODE           8                               /* Ceata Mode enable */
-#define BITP_RSI_DATA_CTL_DMAEN               3                               /* Data Transfer DMA Enable */
-#define BITP_RSI_DATA_CTL_DATMODE             2                               /* Data Transfer Mode */
-#define BITP_RSI_DATA_CTL_DATDIR              1                               /* Data Transfer Direction */
-#define BITP_RSI_DATA_CTL_DATEN               0                               /* Data Transfer Enable */
-#define BITM_RSI_DATA_CTL_CEATAIEN           (_ADI_MSK(0x00000200,uint16_t))  /* Ceata Command Completion Interrupt Enable */
-#define BITM_RSI_DATA_CTL_CEATAMODE          (_ADI_MSK(0x00000100,uint16_t))  /* Ceata Mode enable */
-#define BITM_RSI_DATA_CTL_DMAEN              (_ADI_MSK(0x00000008,uint16_t))  /* Data Transfer DMA Enable */
-#define BITM_RSI_DATA_CTL_DATMODE            (_ADI_MSK(0x00000004,uint16_t))  /* Data Transfer Mode */
-#define BITM_RSI_DATA_CTL_DATDIR             (_ADI_MSK(0x00000002,uint16_t))  /* Data Transfer Direction */
-#define BITM_RSI_DATA_CTL_DATEN              (_ADI_MSK(0x00000001,uint16_t))  /* Data Transfer Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_RXFIFORDY           21                               /* Receive FIFO Available */
-#define BITP_RSI_XFRSTAT_TXFIFORDY           20                               /* Transmit FIFO Available */
-#define BITP_RSI_XFRSTAT_RXFIFOZERO          19                               /* Receive FIFO Empty */
-#define BITP_RSI_XFRSTAT_TXFIFOZERO          18                               /* Transmit FIFO Empty */
-#define BITP_RSI_XFRSTAT_RXFIFOFULL          17                               /* Receive FIFO Full */
-#define BITP_RSI_XFRSTAT_TXFIFOFULL          16                               /* Transmit FIFO Full */
-#define BITP_RSI_XFRSTAT_RXFIFOSTAT          15                               /* Receive FIFO Status */
-#define BITP_RSI_XFRSTAT_TXFIFOSTAT          14                               /* Transmit FIFO Status */
-#define BITP_RSI_XFRSTAT_RXACT               13                               /* Receive Active */
-#define BITP_RSI_XFRSTAT_TXACT               12                               /* Transmit Active */
-#define BITP_RSI_XFRSTAT_CMDACT              11                               /* Command Active */
-#define BITP_RSI_XFRSTAT_DATBLKEND           10                               /* Data Block End */
-#define BITP_RSI_XFRSTAT_SBITERR              9                               /* Start Bit Error */
-#define BITP_RSI_XFRSTAT_DATEND               8                               /* Data End */
-#define BITP_RSI_XFRSTAT_CMDSENT              7                               /* Command Sent */
-#define BITP_RSI_XFRSTAT_RESPEND              6                               /* Command Response End */
-#define BITP_RSI_XFRSTAT_RXOVER               5                               /* Receive Over run */
-#define BITP_RSI_XFRSTAT_TXUNDR               4                               /* Transmit Under run */
-#define BITP_RSI_XFRSTAT_DATTO                3                               /* Data Timeout */
-#define BITP_RSI_XFRSTAT_CMDTO                2                               /* CMD Timeout */
-#define BITP_RSI_XFRSTAT_DATCRCFAIL           1                               /* Data CRC Fail */
-#define BITP_RSI_XFRSTAT_CMDCRCFAIL           0                               /* CMD CRC Fail */
-#define BITM_RSI_XFRSTAT_RXFIFORDY           (_ADI_MSK(0x00200000,uint32_t))  /* Receive FIFO Available */
-#define BITM_RSI_XFRSTAT_TXFIFORDY           (_ADI_MSK(0x00100000,uint32_t))  /* Transmit FIFO Available */
-#define BITM_RSI_XFRSTAT_RXFIFOZERO          (_ADI_MSK(0x00080000,uint32_t))  /* Receive FIFO Empty */
-#define BITM_RSI_XFRSTAT_TXFIFOZERO          (_ADI_MSK(0x00040000,uint32_t))  /* Transmit FIFO Empty */
-#define BITM_RSI_XFRSTAT_RXFIFOFULL          (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Full */
-#define BITM_RSI_XFRSTAT_TXFIFOFULL          (_ADI_MSK(0x00010000,uint32_t))  /* Transmit FIFO Full */
-#define BITM_RSI_XFRSTAT_RXFIFOSTAT          (_ADI_MSK(0x00008000,uint32_t))  /* Receive FIFO Status */
-#define BITM_RSI_XFRSTAT_TXFIFOSTAT          (_ADI_MSK(0x00004000,uint32_t))  /* Transmit FIFO Status */
-#define BITM_RSI_XFRSTAT_RXACT               (_ADI_MSK(0x00002000,uint32_t))  /* Receive Active */
-#define BITM_RSI_XFRSTAT_TXACT               (_ADI_MSK(0x00001000,uint32_t))  /* Transmit Active */
-#define BITM_RSI_XFRSTAT_CMDACT              (_ADI_MSK(0x00000800,uint32_t))  /* Command Active */
-#define BITM_RSI_XFRSTAT_DATBLKEND           (_ADI_MSK(0x00000400,uint32_t))  /* Data Block End */
-#define BITM_RSI_XFRSTAT_SBITERR             (_ADI_MSK(0x00000200,uint32_t))  /* Start Bit Error */
-#define BITM_RSI_XFRSTAT_DATEND              (_ADI_MSK(0x00000100,uint32_t))  /* Data End */
-#define BITM_RSI_XFRSTAT_CMDSENT             (_ADI_MSK(0x00000080,uint32_t))  /* Command Sent */
-#define BITM_RSI_XFRSTAT_RESPEND             (_ADI_MSK(0x00000040,uint32_t))  /* Command Response End */
-#define BITM_RSI_XFRSTAT_RXOVER              (_ADI_MSK(0x00000020,uint32_t))  /* Receive Over run */
-#define BITM_RSI_XFRSTAT_TXUNDR              (_ADI_MSK(0x00000010,uint32_t))  /* Transmit Under run */
-#define BITM_RSI_XFRSTAT_DATTO               (_ADI_MSK(0x00000008,uint32_t))  /* Data Timeout */
-#define BITM_RSI_XFRSTAT_CMDTO               (_ADI_MSK(0x00000004,uint32_t))  /* CMD Timeout */
-#define BITM_RSI_XFRSTAT_DATCRCFAIL          (_ADI_MSK(0x00000002,uint32_t))  /* Data CRC Fail */
-#define BITM_RSI_XFRSTAT_CMDCRCFAIL          (_ADI_MSK(0x00000001,uint32_t))  /* CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT_CLR                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_CLR_DATBLKEND       10                               /* Data Block End Status */
-#define BITP_RSI_XFRSTAT_CLR_STRTBITERR       9                               /* Start Bit Error Status */
-#define BITP_RSI_XFRSTAT_CLR_DATEND           8                               /* Data End Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDSENT          7                               /* Command Sent Status */
-#define BITP_RSI_XFRSTAT_CLR_RESPEND          6                               /* Command Response End Status */
-#define BITP_RSI_XFRSTAT_CLR_RXOVER           5                               /* Receive Over run Status */
-#define BITP_RSI_XFRSTAT_CLR_TXUNDR           4                               /* Transmit Under run Status */
-#define BITP_RSI_XFRSTAT_CLR_DATTO            3                               /* Data Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDTO            2                               /* CMD Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_DATCRCFAIL       1                               /* Data CRC Fail Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDCRCFAIL       0                               /* CMD CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_DATBLKEND       (_ADI_MSK(0x00000400,uint16_t))  /* Data Block End Status */
-#define BITM_RSI_XFRSTAT_CLR_STRTBITERR      (_ADI_MSK(0x00000200,uint16_t))  /* Start Bit Error Status */
-#define BITM_RSI_XFRSTAT_CLR_DATEND          (_ADI_MSK(0x00000100,uint16_t))  /* Data End Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDSENT         (_ADI_MSK(0x00000080,uint16_t))  /* Command Sent Status */
-#define BITM_RSI_XFRSTAT_CLR_RESPEND         (_ADI_MSK(0x00000040,uint16_t))  /* Command Response End Status */
-#define BITM_RSI_XFRSTAT_CLR_RXOVER          (_ADI_MSK(0x00000020,uint16_t))  /* Receive Over run Status */
-#define BITM_RSI_XFRSTAT_CLR_TXUNDR          (_ADI_MSK(0x00000010,uint16_t))  /* Transmit Under run Status */
-#define BITM_RSI_XFRSTAT_CLR_DATTO           (_ADI_MSK(0x00000008,uint16_t))  /* Data Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDTO           (_ADI_MSK(0x00000004,uint16_t))  /* CMD Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_DATCRCFAIL      (_ADI_MSK(0x00000002,uint16_t))  /* Data CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDCRCFAIL      (_ADI_MSK(0x00000001,uint16_t))  /* CMD CRC Fail Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK0_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK0_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK0_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK0_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK0_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK0_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK0_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK0_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK0_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK0_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK0_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK0_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK0_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK0_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK0_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK0_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK0_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK0_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK0_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK0_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK0_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK0_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK0_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK0_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK0_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK0_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK0_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK0_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK0_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK0_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK0_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK0_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK0_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK0_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK0_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK0_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK0_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK0_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK0_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK0_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK1_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK1_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK1_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK1_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK1_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK1_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK1_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK1_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK1_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK1_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK1_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK1_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK1_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK1_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK1_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK1_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK1_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK1_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK1_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK1_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK1_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK1_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK1_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK1_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK1_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK1_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK1_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK1_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK1_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK1_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK1_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK1_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK1_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK1_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK1_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK1_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK1_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK1_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK1_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK1_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_FIFO_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_FIFO_CNT_VALUE               0                               /* FIFO Count */
-#define BITM_RSI_FIFO_CNT_VALUE              (_ADI_MSK(0x00007FFF,uint16_t))  /* FIFO Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CEATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CEATA_INT_DIS                0                               /* CEATA Disable Interrupt */
-#define BITM_RSI_CEATA_INT_DIS               (_ADI_MSK(0x00000001,uint32_t))  /* CEATA Disable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BOOT_TCNTR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BOOT_TCNTR_HOLD              8                               /* Boot Hold Time */
-#define BITP_RSI_BOOT_TCNTR_SETUP             0                               /* Boot Setup Time */
-#define BITM_RSI_BOOT_TCNTR_HOLD             (_ADI_MSK(0x0000FF00,uint16_t))  /* Boot Hold Time */
-#define BITM_RSI_BOOT_TCNTR_SETUP            (_ADI_MSK(0x000000FF,uint16_t))  /* Boot Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BLKSZ                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BLKSZ_VALUE                  0                               /* Size of Each Block of Data */
-#define BITM_RSI_BLKSZ_VALUE                 (_ADI_MSK(0x00001FFF,uint16_t))  /* Size of Each Block of Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_STAT0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_STAT0_BUSYMODE              31                               /* Card is in Busy mode */
-#define BITP_RSI_STAT0_SLPMODE               30                               /* Card in Sleep Mode */
-#define BITP_RSI_STAT0_CARDRDY               17                               /* Card Ready */
-#define BITP_RSI_STAT0_SLPWKPTOUT            16                               /* Sleep Wakeup Timer Expired */
-#define BITP_RSI_STAT0_WKPDONE               15                               /* Card Entered Standby state */
-#define BITP_RSI_STAT0_SLPDONE               14                               /* Card Entered Sleep State */
-#define BITP_RSI_STAT0_BACKDONE              13                               /* Correct Boot Ack is received */
-#define BITP_RSI_STAT0_BACKBAD               12                               /* Boot Ack received is corrupted */
-#define BITP_RSI_STAT0_BACKTO                11                               /* Boot Acknowledge Timeout */
-#define BITP_RSI_STAT0_BDATTO                10                               /* Boot Data Timeout */
-#define BITP_RSI_STAT0_BHOLDEXP               9                               /* Boot Hold Time Expiry */
-#define BITP_RSI_STAT0_BSETUPEXP              8                               /* Boot Setup Time Expiry */
-#define BITP_RSI_STAT0_CEATAINT               5                               /* CEATA Interrupt */
-#define BITP_RSI_STAT0_SDCARD                 4                               /* SD Card Detected */
-#define BITP_RSI_STAT0_SDIOINT                1                               /* SDIO Interrupt */
-#define BITM_RSI_STAT0_BUSYMODE              (_ADI_MSK(0x80000000,uint32_t))  /* Card is in Busy mode */
-#define BITM_RSI_STAT0_SLPMODE               (_ADI_MSK(0x40000000,uint32_t))  /* Card in Sleep Mode */
-#define BITM_RSI_STAT0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Card Ready */
-#define BITM_RSI_STAT0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Sleep Wakeup Timer Expired */
-#define BITM_RSI_STAT0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Card Entered Standby state */
-#define BITM_RSI_STAT0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Card Entered Sleep State */
-#define BITM_RSI_STAT0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Correct Boot Ack is received */
-#define BITM_RSI_STAT0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Boot Ack received is corrupted */
-#define BITM_RSI_STAT0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Boot Acknowledge Timeout */
-#define BITM_RSI_STAT0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Boot Data Timeout */
-#define BITM_RSI_STAT0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Boot Hold Time Expiry */
-#define BITM_RSI_STAT0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Boot Setup Time Expiry */
-#define BITM_RSI_STAT0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* CEATA Interrupt */
-#define BITM_RSI_STAT0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* SD Card Detected */
-#define BITM_RSI_STAT0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_IMSK0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_IMSK0_CARDRDY               17                               /* Mask Interrupt for Card Ready */
-#define BITP_RSI_IMSK0_SLPWKPTOUT            16                               /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITP_RSI_IMSK0_WKPDONE               15                               /* Mask Interrupt for Card Entered Standby state */
-#define BITP_RSI_IMSK0_SLPDONE               14                               /* Mask Interrupt for Card Entered Sleep State */
-#define BITP_RSI_IMSK0_BACKDONE              13                               /* Mask Interrupt for Correct Boot Ack is received */
-#define BITP_RSI_IMSK0_BACKBAD               12                               /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITP_RSI_IMSK0_BACKTO                11                               /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITP_RSI_IMSK0_BDATTO                10                               /* Mask Interrupt for Boot Data Timeout */
-#define BITP_RSI_IMSK0_BHOLDEXP               9                               /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITP_RSI_IMSK0_BSETUPEXP              8                               /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITP_RSI_IMSK0_CEATAINT               5                               /* Mask CEATA Interrupt */
-#define BITP_RSI_IMSK0_SDCARD                 4                               /* Mask Interrupt for SD Card Detected */
-#define BITP_RSI_IMSK0_SDIOINT                1                               /* Mask SDIO Interrupt */
-#define BITM_RSI_IMSK0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Mask Interrupt for Card Ready */
-#define BITM_RSI_IMSK0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITM_RSI_IMSK0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Mask Interrupt for Card Entered Standby state */
-#define BITM_RSI_IMSK0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Mask Interrupt for Card Entered Sleep State */
-#define BITM_RSI_IMSK0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Mask Interrupt for Correct Boot Ack is received */
-#define BITM_RSI_IMSK0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITM_RSI_IMSK0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITM_RSI_IMSK0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Mask Interrupt for Boot Data Timeout */
-#define BITM_RSI_IMSK0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITM_RSI_IMSK0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITM_RSI_IMSK0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* Mask CEATA Interrupt */
-#define BITM_RSI_IMSK0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* Mask Interrupt for SD Card Detected */
-#define BITM_RSI_IMSK0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* Mask SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CFG_BACKEN                  14                               /* Boot Acknowledge enabled */
-#define BITP_RSI_CFG_MMCBMODE                13                               /* MMC Boot Mode select */
-#define BITP_RSI_CFG_MMCBEN                  12                               /* MMC Boot Enabled */
-#define BITP_RSI_CFG_OPENDRAIN               11                               /* MC_CMD Output Control */
-#define BITP_RSI_CFG_PWRON                    9                               /* 11 - RSI Enabled */
-#define BITP_RSI_CFG_IEBYPDIS                 8                               /* Disabled IE Bypass */
-#define BITP_RSI_CFG_DAT3PUP                  6                               /* Pull-Up SD_DAT3 */
-#define BITP_RSI_CFG_DATPUP                   5                               /* Pull-Up SD_DAT */
-#define BITP_RSI_CFG_RST                      4                               /* SDMMC Reset */
-#define BITP_RSI_CFG_MWINEN                   3                               /* Moving Window Enable */
-#define BITP_RSI_CFG_SD4EN                    2                               /* SDIO 4-Bit Enable */
-#define BITP_RSI_CFG_CLKSEN                   0                               /* Clocks Enable */
-#define BITM_RSI_CFG_BACKEN                  (_ADI_MSK(0x00004000,uint16_t))  /* Boot Acknowledge enabled */
-#define BITM_RSI_CFG_MMCBMODE                (_ADI_MSK(0x00002000,uint16_t))  /* MMC Boot Mode select */
-#define BITM_RSI_CFG_MMCBEN                  (_ADI_MSK(0x00001000,uint16_t))  /* MMC Boot Enabled */
-#define BITM_RSI_CFG_OPENDRAIN               (_ADI_MSK(0x00000800,uint16_t))  /* MC_CMD Output Control */
-#define BITM_RSI_CFG_PWRON                   (_ADI_MSK(0x00000600,uint16_t))  /* 11 - RSI Enabled */
-#define BITM_RSI_CFG_IEBYPDIS                (_ADI_MSK(0x00000100,uint16_t))  /* Disabled IE Bypass */
-#define BITM_RSI_CFG_DAT3PUP                 (_ADI_MSK(0x00000040,uint16_t))  /* Pull-Up SD_DAT3 */
-#define BITM_RSI_CFG_DATPUP                  (_ADI_MSK(0x00000020,uint16_t))  /* Pull-Up SD_DAT */
-#define BITM_RSI_CFG_RST                     (_ADI_MSK(0x00000010,uint16_t))  /* SDMMC Reset */
-#define BITM_RSI_CFG_MWINEN                  (_ADI_MSK(0x00000008,uint16_t))  /* Moving Window Enable */
-#define BITM_RSI_CFG_SD4EN                   (_ADI_MSK(0x00000004,uint16_t))  /* SDIO 4-Bit Enable */
-#define BITM_RSI_CFG_CLKSEN                  (_ADI_MSK(0x00000001,uint16_t))  /* Clocks Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RD_WAIT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RD_WAIT_REQUEST              0                               /* Read Wait Request */
-#define BITM_RSI_RD_WAIT_REQUEST             (_ADI_MSK(0x00000001,uint16_t))  /* Read Wait Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID0                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID0_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID0_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID1_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID1_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID2_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID2_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID3                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID3_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID3_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ==================================================
-        Controller Area Network Registers
-   ================================================== */
-
-/* =========================
-        CAN0
-   ========================= */
-#define REG_CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration 1 Register */
-#define REG_CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction 1 Register */
-#define REG_CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set 1 Register */
-#define REG_CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset 1 Register */
-#define REG_CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge 1 Register */
-#define REG_CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge 1 Register */
-#define REG_CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending 1 Register */
-#define REG_CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost 1 Register */
-#define REG_CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define REG_CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define REG_CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define REG_CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling 1 Register */
-#define REG_CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define REG_CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration 2 Register */
-#define REG_CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction 2 Register */
-#define REG_CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set 2 Register */
-#define REG_CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset 2 Register */
-#define REG_CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge 2 Register */
-#define REG_CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge 2 Register */
-#define REG_CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending 2 Register */
-#define REG_CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost 2 Register */
-#define REG_CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define REG_CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define REG_CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define REG_CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling 2 Register */
-#define REG_CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define REG_CAN0_CLK                    0xFFC00A80         /* CAN0 Clock Register */
-#define REG_CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
-#define REG_CAN0_DBG                    0xFFC00A88         /* CAN0 Debug Register */
-#define REG_CAN0_STAT                   0xFFC00A8C         /* CAN0 Status Register */
-#define REG_CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
-#define REG_CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status Register */
-#define REG_CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask Register */
-#define REG_CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag Register */
-#define REG_CAN0_CTL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
-#define REG_CAN0_INT                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
-#define REG_CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
-#define REG_CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
-#define REG_CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
-#define REG_CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
-#define REG_CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
-#define REG_CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
-#define REG_CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox ID 1 Register */
-
-/* =========================
-        CAN
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC1_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD1_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS1_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR1_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA1_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA1_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP1_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML1_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF1_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF1_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM1_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH1_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS1_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC2_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD2_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS2_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR2_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA2_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA2_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP2_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML2_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF2_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF2_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM2_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH2_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS2_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CLK_BRP                      0                               /* Bit Rate Prescaler */
-#define BITM_CAN_CLK_BRP                     (_ADI_MSK(0x000003FF,uint16_t))  /* Bit Rate Prescaler */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TIMING                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TIMING_SJW                   8                               /* Synchronization Jump Width */
-#define BITP_CAN_TIMING_SAM                   7                               /* Sampling */
-#define BITP_CAN_TIMING_TSEG2                 4                               /* Time Segment 2 */
-#define BITP_CAN_TIMING_TSEG1                 0                               /* Time Segment 1 */
-#define BITM_CAN_TIMING_SJW                  (_ADI_MSK(0x00000300,uint16_t))  /* Synchronization Jump Width */
-#define BITM_CAN_TIMING_SAM                  (_ADI_MSK(0x00000080,uint16_t))  /* Sampling */
-#define BITM_CAN_TIMING_TSEG2                (_ADI_MSK(0x00000070,uint16_t))  /* Time Segment 2 */
-#define BITM_CAN_TIMING_TSEG1                (_ADI_MSK(0x0000000F,uint16_t))  /* Time Segment 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_DBG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_DBG_CDE                     15                               /* CAN Debug Mode Enable */
-#define BITP_CAN_DBG_MRB                      5                               /* Mode Read Back */
-#define BITP_CAN_DBG_MAA                      4                               /* Mode Auto Acknowledge */
-#define BITP_CAN_DBG_DIL                      3                               /* Disable Internal Loop */
-#define BITP_CAN_DBG_DTO                      2                               /* Disable Tx Output Pin */
-#define BITP_CAN_DBG_DRI                      1                               /* Disable Receive Input Pin */
-#define BITP_CAN_DBG_DEC                      0                               /* Disable Transmit and Receive Error Counters */
-#define BITM_CAN_DBG_CDE                     (_ADI_MSK(0x00008000,uint16_t))  /* CAN Debug Mode Enable */
-#define BITM_CAN_DBG_MRB                     (_ADI_MSK(0x00000020,uint16_t))  /* Mode Read Back */
-#define BITM_CAN_DBG_MAA                     (_ADI_MSK(0x00000010,uint16_t))  /* Mode Auto Acknowledge */
-#define BITM_CAN_DBG_DIL                     (_ADI_MSK(0x00000008,uint16_t))  /* Disable Internal Loop */
-#define BITM_CAN_DBG_DTO                     (_ADI_MSK(0x00000004,uint16_t))  /* Disable Tx Output Pin */
-#define BITM_CAN_DBG_DRI                     (_ADI_MSK(0x00000002,uint16_t))  /* Disable Receive Input Pin */
-#define BITM_CAN_DBG_DEC                     (_ADI_MSK(0x00000001,uint16_t))  /* Disable Transmit and Receive Error Counters */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_STAT_REC                    15                               /* Receive Mode */
-#define BITP_CAN_STAT_TRM                    14                               /* Transmit Mode */
-#define BITP_CAN_STAT_MBPTR                   8                               /* Mailbox Pointer */
-#define BITP_CAN_STAT_CCA                     7                               /* CAN Configuration Mode Acknowledge */
-#define BITP_CAN_STAT_CSA                     6                               /* CAN Suspend Mode Acknowledge */
-#define BITP_CAN_STAT_EBO                     3                               /* CAN Error Bus Off Mode */
-#define BITP_CAN_STAT_EP                      2                               /* CAN Error Passive Mode */
-#define BITP_CAN_STAT_WR                      1                               /* CAN Receive Warning Flag */
-#define BITP_CAN_STAT_WT                      0                               /* CAN Transmit Warning Flag */
-#define BITM_CAN_STAT_REC                    (_ADI_MSK(0x00008000,uint16_t))  /* Receive Mode */
-#define BITM_CAN_STAT_TRM                    (_ADI_MSK(0x00004000,uint16_t))  /* Transmit Mode */
-#define BITM_CAN_STAT_MBPTR                  (_ADI_MSK(0x00001F00,uint16_t))  /* Mailbox Pointer */
-#define BITM_CAN_STAT_CCA                    (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Acknowledge */
-#define BITM_CAN_STAT_CSA                    (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Acknowledge */
-#define BITM_CAN_STAT_EBO                    (_ADI_MSK(0x00000008,uint16_t))  /* CAN Error Bus Off Mode */
-#define BITM_CAN_STAT_EP                     (_ADI_MSK(0x00000004,uint16_t))  /* CAN Error Passive Mode */
-#define BITM_CAN_STAT_WR                     (_ADI_MSK(0x00000002,uint16_t))  /* CAN Receive Warning Flag */
-#define BITM_CAN_STAT_WT                     (_ADI_MSK(0x00000001,uint16_t))  /* CAN Transmit Warning Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CEC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CEC_TXECNT                   8                               /* Transmit Error Counter */
-#define BITP_CAN_CEC_RXECNT                   0                               /* Receive Error Counter */
-#define BITM_CAN_CEC_TXECNT                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Counter */
-#define BITM_CAN_CEC_RXECNT                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Counter */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIS                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIS_ADIS                    10                               /* Access Denied Interrupt Status */
-#define BITP_CAN_GIS_UCEIS                    8                               /* Universal Counter Exceeded Interrupt Status */
-#define BITP_CAN_GIS_RMLIS                    7                               /* Receive Message Lost Interrupt Status */
-#define BITP_CAN_GIS_AAIS                     6                               /* Abort Acknowledge Interrupt Status */
-#define BITP_CAN_GIS_UIAIS                    5                               /* Unimplemented Address Interrupt Status */
-#define BITP_CAN_GIS_WUIS                     4                               /* Wake Up Interrupt Status */
-#define BITP_CAN_GIS_BOIS                     3                               /* Bus Off Interrupt Status */
-#define BITP_CAN_GIS_EPIS                     2                               /* Error Passive Interrupt Status */
-#define BITP_CAN_GIS_EWRIS                    1                               /* Error Warning Receive  Interrupt Status */
-#define BITP_CAN_GIS_EWTIS                    0                               /* Error Warning Transmit Interrupt Status */
-#define BITM_CAN_GIS_ADIS                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Status */
-#define BITM_CAN_GIS_UCEIS                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Status */
-#define BITM_CAN_GIS_RMLIS                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Status */
-#define BITM_CAN_GIS_AAIS                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Status */
-#define BITM_CAN_GIS_UIAIS                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Status */
-#define BITM_CAN_GIS_WUIS                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Status */
-#define BITM_CAN_GIS_BOIS                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Status */
-#define BITM_CAN_GIS_EPIS                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Status */
-#define BITM_CAN_GIS_EWRIS                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive  Interrupt Status */
-#define BITM_CAN_GIS_EWTIS                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIM                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIM_ADIM                    10                               /* Access Denied Interrupt Mask */
-#define BITP_CAN_GIM_UCEIM                    8                               /* Universal Counter Exceeded Interrupt Mask */
-#define BITP_CAN_GIM_RMLIM                    7                               /* Receive Message Lost Interrupt Mask */
-#define BITP_CAN_GIM_AAIM                     6                               /* Abort Acknowledge Interrupt Mask */
-#define BITP_CAN_GIM_UIAIM                    5                               /* Unimplemented Address Interrupt Mask */
-#define BITP_CAN_GIM_WUIM                     4                               /* Wake Up Interrupt Mask */
-#define BITP_CAN_GIM_BOIM                     3                               /* Bus Off Interrupt Mask */
-#define BITP_CAN_GIM_EPIM                     2                               /* Error Passive Interrupt Mask */
-#define BITP_CAN_GIM_EWRIM                    1                               /* Error Warning Receive Interrupt Mask */
-#define BITP_CAN_GIM_EWTIM                    0                               /* Error Warning Transmit Interrupt Mask */
-#define BITM_CAN_GIM_ADIM                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Mask */
-#define BITM_CAN_GIM_UCEIM                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Mask */
-#define BITM_CAN_GIM_RMLIM                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Mask */
-#define BITM_CAN_GIM_AAIM                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Mask */
-#define BITM_CAN_GIM_UIAIM                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Mask */
-#define BITM_CAN_GIM_WUIM                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Mask */
-#define BITM_CAN_GIM_BOIM                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Mask */
-#define BITM_CAN_GIM_EPIM                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Mask */
-#define BITM_CAN_GIM_EWRIM                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Mask */
-#define BITM_CAN_GIM_EWTIM                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIF                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIF_ADIF                    10                               /* Access Denied Interrupt Flag */
-#define BITP_CAN_GIF_UCEIF                    8                               /* Universal Counter Exceeded Interrupt Flag */
-#define BITP_CAN_GIF_RMLIF                    7                               /* Receive Message Lost Interrupt Flag */
-#define BITP_CAN_GIF_AAIF                     6                               /* Abort Acknowledge Interrupt Flag */
-#define BITP_CAN_GIF_UIAIF                    5                               /* Unimplemented Address Interrupt Flag */
-#define BITP_CAN_GIF_WUIF                     4                               /* Wake Up Interrupt Flag */
-#define BITP_CAN_GIF_BOIF                     3                               /* Bus Off Interrupt Flag */
-#define BITP_CAN_GIF_EPIF                     2                               /* Error Passive Interrupt Flag */
-#define BITP_CAN_GIF_EWRIF                    1                               /* Error Warning Receive Interrupt Flag */
-#define BITP_CAN_GIF_EWTIF                    0                               /* Error Warning Transmit Interrupt Flag */
-#define BITM_CAN_GIF_ADIF                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Flag */
-#define BITM_CAN_GIF_UCEIF                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Flag */
-#define BITM_CAN_GIF_RMLIF                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Flag */
-#define BITM_CAN_GIF_AAIF                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Flag */
-#define BITM_CAN_GIF_UIAIF                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Flag */
-#define BITM_CAN_GIF_WUIF                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Flag */
-#define BITM_CAN_GIF_BOIF                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Flag */
-#define BITM_CAN_GIF_EPIF                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Flag */
-#define BITM_CAN_GIF_EWRIF                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Flag */
-#define BITM_CAN_GIF_EWTIF                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CTL_CCR                      7                               /* CAN Configuration Mode Request */
-#define BITP_CAN_CTL_CSR                      6                               /* CAN Suspend Mode Request */
-#define BITP_CAN_CTL_SMR                      5                               /* Sleep Mode Request */
-#define BITP_CAN_CTL_WBA                      4                               /* Wake Up on CAN Bus Activity */
-#define BITP_CAN_CTL_ABO                      2                               /* Auto Bus On */
-#define BITP_CAN_CTL_DNM                      1                               /* Device Net Mode */
-#define BITP_CAN_CTL_SRS                      0                               /* Software Reset */
-#define BITM_CAN_CTL_CCR                     (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Request */
-#define BITM_CAN_CTL_CSR                     (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Request */
-#define BITM_CAN_CTL_SMR                     (_ADI_MSK(0x00000020,uint16_t))  /* Sleep Mode Request */
-#define BITM_CAN_CTL_WBA                     (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up on CAN Bus Activity */
-#define BITM_CAN_CTL_ABO                     (_ADI_MSK(0x00000004,uint16_t))  /* Auto Bus On */
-#define BITM_CAN_CTL_DNM                     (_ADI_MSK(0x00000002,uint16_t))  /* Device Net Mode */
-#define BITM_CAN_CTL_SRS                     (_ADI_MSK(0x00000001,uint16_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_INT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_INT_CANRX                    7                               /* Serial Input From Transceiver */
-#define BITP_CAN_INT_CANTX                    6                               /* Serial Input To Transceiver */
-#define BITP_CAN_INT_SMACK                    3                               /* Sleep Mode Acknowledge */
-#define BITP_CAN_INT_GIRQ                     2                               /* Global CAN Interrupt Output */
-#define BITP_CAN_INT_MBTIRQ                   1                               /* Mailbox Transmit Interrupt Output */
-#define BITP_CAN_INT_MBRIRQ                   0                               /* Mailbox Receive Interrupt Output */
-#define BITM_CAN_INT_CANRX                   (_ADI_MSK(0x00000080,uint16_t))  /* Serial Input From Transceiver */
-#define BITM_CAN_INT_CANTX                   (_ADI_MSK(0x00000040,uint16_t))  /* Serial Input To Transceiver */
-#define BITM_CAN_INT_SMACK                   (_ADI_MSK(0x00000008,uint16_t))  /* Sleep Mode Acknowledge */
-#define BITM_CAN_INT_GIRQ                    (_ADI_MSK(0x00000004,uint16_t))  /* Global CAN Interrupt Output */
-#define BITM_CAN_INT_MBTIRQ                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox Transmit Interrupt Output */
-#define BITM_CAN_INT_MBRIRQ                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox Receive Interrupt Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTD_TDR                     7                               /* Temporary Disable Request */
-#define BITP_CAN_MBTD_TDA                     6                               /* Temporary Disable Acknowledge */
-#define BITP_CAN_MBTD_TDPTR                   0                               /* Temporary Disable Pointer */
-#define BITM_CAN_MBTD_TDR                    (_ADI_MSK(0x00000080,uint16_t))  /* Temporary Disable Request */
-#define BITM_CAN_MBTD_TDA                    (_ADI_MSK(0x00000040,uint16_t))  /* Temporary Disable Acknowledge */
-#define BITM_CAN_MBTD_TDPTR                  (_ADI_MSK(0x0000001F,uint16_t))  /* Temporary Disable Pointer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_EWR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_EWR_EWLTEC                   8                               /* Transmit Error Warning Limit */
-#define BITP_CAN_EWR_EWLREC                   0                               /* Receive Error Warning Limit */
-#define BITM_CAN_EWR_EWLTEC                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Warning Limit */
-#define BITM_CAN_EWR_EWLREC                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Warning Limit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_ESR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_ESR_FER                      7                               /* Form Error */
-#define BITP_CAN_ESR_BEF                      6                               /* Bit Error Flag */
-#define BITP_CAN_ESR_SAO                      5                               /* Stuck at Dominant */
-#define BITP_CAN_ESR_CRCE                     4                               /* CRC Error */
-#define BITP_CAN_ESR_SER                      3                               /* Stuff Bit Error */
-#define BITP_CAN_ESR_ACKE                     2                               /* Acknowledge Error */
-#define BITM_CAN_ESR_FER                     (_ADI_MSK(0x00000080,uint16_t))  /* Form Error */
-#define BITM_CAN_ESR_BEF                     (_ADI_MSK(0x00000040,uint16_t))  /* Bit Error Flag */
-#define BITM_CAN_ESR_SAO                     (_ADI_MSK(0x00000020,uint16_t))  /* Stuck at Dominant */
-#define BITM_CAN_ESR_CRCE                    (_ADI_MSK(0x00000010,uint16_t))  /* CRC Error */
-#define BITM_CAN_ESR_SER                     (_ADI_MSK(0x00000008,uint16_t))  /* Stuff Bit Error */
-#define BITM_CAN_ESR_ACKE                    (_ADI_MSK(0x00000004,uint16_t))  /* Acknowledge Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_UCCNF                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_UCCNF_UCE                    7                               /* Universal Counter Enable */
-#define BITP_CAN_UCCNF_UCCT                   6                               /* Universal Counter CAN Trigger */
-#define BITP_CAN_UCCNF_UCRC                   5                               /* Universal Counter Reload/Clear */
-#define BITP_CAN_UCCNF_UCCNF                  0                               /* Universal Counter Configuration */
-#define BITM_CAN_UCCNF_UCE                   (_ADI_MSK(0x00000080,uint16_t))  /* Universal Counter Enable */
-#define BITM_CAN_UCCNF_UCCT                  (_ADI_MSK(0x00000040,uint16_t))  /* Universal Counter CAN Trigger */
-#define BITM_CAN_UCCNF_UCRC                  (_ADI_MSK(0x00000020,uint16_t))  /* Universal Counter Reload/Clear */
-#define BITM_CAN_UCCNF_UCCNF                 (_ADI_MSK(0x0000000F,uint16_t))  /* Universal Counter Configuration */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AMnH                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AMH_FDF                     15                               /* Filter on Delay Field */
-#define BITP_CAN_AMH_FMD                     14                               /* Full Mask Data */
-#define BITP_CAN_AMH_AMIDE                   13                               /* Acceptance Mask Identifier Extension */
-#define BITP_CAN_AMH_BASEID                   2                               /* Base Identifier */
-#define BITP_CAN_AMH_EXTID                    0                               /* Extended Identifier */
-#define BITM_CAN_AMH_FDF                     (_ADI_MSK(0x00008000,uint16_t))  /* Filter on Delay Field */
-#define BITM_CAN_AMH_FMD                     (_ADI_MSK(0x00004000,uint16_t))  /* Full Mask Data */
-#define BITM_CAN_AMH_AMIDE                   (_ADI_MSK(0x00002000,uint16_t))  /* Acceptance Mask Identifier Extension */
-#define BITM_CAN_AMH_BASEID                  (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_AMH_EXTID                   (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA0_DFB6                8                               /* Data Field Byte 6 */
-#define BITP_CAN_MB_DATA0_DFB7                0                               /* Data Field Byte 7 */
-#define BITM_CAN_MB_DATA0_DFB6               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 6 */
-#define BITM_CAN_MB_DATA0_DFB7               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 7 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA1_DFB4                8                               /* Data Field Byte 4 */
-#define BITP_CAN_MB_DATA1_DFB5                0                               /* Data Field Byte 5 */
-#define BITM_CAN_MB_DATA1_DFB4               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 4 */
-#define BITM_CAN_MB_DATA1_DFB5               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 5 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA2                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA2_DFB2                8                               /* Data Field Byte 2 */
-#define BITP_CAN_MB_DATA2_DFB3                0                               /* Data Field Byte 3 */
-#define BITM_CAN_MB_DATA2_DFB2               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 2 */
-#define BITM_CAN_MB_DATA2_DFB3               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 3 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA3                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA3_DFB0                8                               /* Data Field Byte 0 */
-#define BITP_CAN_MB_DATA3_DFB1                0                               /* Data Field Byte 1 */
-#define BITM_CAN_MB_DATA3_DFB0               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 0 */
-#define BITM_CAN_MB_DATA3_DFB1               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_LENGTH                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_LENGTH_DLC                0                               /* Data Length Code */
-#define BITM_CAN_MB_LENGTH_DLC               (_ADI_MSK(0x0000000F,uint16_t))  /* Data Length Code */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_ID1                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_ID1_AME                  15                               /* Acceptance Mask Enable */
-#define BITP_CAN_MB_ID1_RTR                  14                               /* Remote Transmission Request */
-#define BITP_CAN_MB_ID1_IDE                  13                               /* Identifier Extension */
-#define BITP_CAN_MB_ID1_BASEID                2                               /* Base Identifier */
-#define BITP_CAN_MB_ID1_EXTID                 0                               /* Extended Identifier */
-#define BITM_CAN_MB_ID1_AME                  (_ADI_MSK(0x00008000,uint16_t))  /* Acceptance Mask Enable */
-#define BITM_CAN_MB_ID1_RTR                  (_ADI_MSK(0x00004000,uint16_t))  /* Remote Transmission Request */
-#define BITM_CAN_MB_ID1_IDE                  (_ADI_MSK(0x00002000,uint16_t))  /* Identifier Extension */
-#define BITM_CAN_MB_ID1_BASEID               (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_MB_ID1_EXTID                (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ==================================================
-        Link Port Registers
-   ================================================== */
-
-/* =========================
-        LP0
-   ========================= */
-#define REG_LP0_CTL                     0xFFC01000         /* LP0 Control Register */
-#define REG_LP0_STAT                    0xFFC01004         /* LP0 Status Register */
-#define REG_LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
-#define REG_LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
-#define REG_LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
-#define REG_LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
-#define REG_LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP1
-   ========================= */
-#define REG_LP1_CTL                     0xFFC01100         /* LP1 Control Register */
-#define REG_LP1_STAT                    0xFFC01104         /* LP1 Status Register */
-#define REG_LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
-#define REG_LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
-#define REG_LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
-#define REG_LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
-#define REG_LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP2
-   ========================= */
-#define REG_LP2_CTL                     0xFFC01200         /* LP2 Control Register */
-#define REG_LP2_STAT                    0xFFC01204         /* LP2 Status Register */
-#define REG_LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
-#define REG_LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
-#define REG_LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
-#define REG_LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
-#define REG_LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP3
-   ========================= */
-#define REG_LP3_CTL                     0xFFC01300         /* LP3 Control Register */
-#define REG_LP3_STAT                    0xFFC01304         /* LP3 Status Register */
-#define REG_LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
-#define REG_LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
-#define REG_LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
-#define REG_LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
-#define REG_LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_CTL                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_CTL_ITMSK                    11                               /* Receive FIFO Overflow Interrupt Mask */
-#define BITP_LP_CTL_RRQMSK                    9                               /* Receive Request Interrupt Mask */
-#define BITP_LP_CTL_TRQMSK                    8                               /* Transmit Request Interrupt Mask */
-#define BITP_LP_CTL_TRAN                      3                               /* Transfer Direction */
-#define BITP_LP_CTL_EN                        0                               /* Enable */
-
-#define BITM_LP_CTL_ITMSK                    (_ADI_MSK(0x00000800,uint32_t))  /* Receive FIFO Overflow Interrupt Mask */
-#define ENUM_LP_CTL_RX_OVF_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* ITMSK: Mask */
-#define ENUM_LP_CTL_RX_OVF_EN                (_ADI_MSK(0x00000800,uint32_t))  /* ITMSK: Unmask */
-
-#define BITM_LP_CTL_RRQMSK                   (_ADI_MSK(0x00000200,uint32_t))  /* Receive Request Interrupt Mask */
-#define ENUM_LP_CTL_RRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* RRQMSK: Mask */
-#define ENUM_LP_CTL_RRQ_EN                   (_ADI_MSK(0x00000200,uint32_t))  /* RRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRQMSK                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Request Interrupt Mask */
-#define ENUM_LP_CTL_TRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* TRQMSK: Mask */
-#define ENUM_LP_CTL_TRQ_EN                   (_ADI_MSK(0x00000100,uint32_t))  /* TRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRAN                     (_ADI_MSK(0x00000008,uint32_t))  /* Transfer Direction */
-#define ENUM_LP_CTL_RX                       (_ADI_MSK(0x00000000,uint32_t))  /* TRAN: Receive */
-#define ENUM_LP_CTL_TX                       (_ADI_MSK(0x00000008,uint32_t))  /* TRAN: Transmit */
-
-#define BITM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_LP_CTL_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable   linkport */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_STAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_STAT_LPBS                     8                               /* Bus Status */
-#define BITP_LP_STAT_LERR                     7                               /* Buffer Pack Error Status */
-#define BITP_LP_STAT_FFST                     4                               /* FIFO Status */
-#define BITP_LP_STAT_LPIT                     3                               /* Receive FIFO Overflow Interrupt */
-#define BITP_LP_STAT_LRRQ                     1                               /* Receive Request */
-#define BITP_LP_STAT_LTRQ                     0                               /* Transmit Request */
-
-#define BITM_LP_STAT_LPBS                    (_ADI_MSK(0x00000100,uint32_t))  /* Bus Status */
-#define ENUM_LP_STAT_IDLE                    (_ADI_MSK(0x00000000,uint32_t))  /* LPBS: Bus is Idle */
-#define ENUM_LP_STAT_BUSY                    (_ADI_MSK(0x00000100,uint32_t))  /* LPBS: Bus Busy */
-
-#define BITM_LP_STAT_LERR                    (_ADI_MSK(0x00000080,uint32_t))  /* Buffer Pack Error Status */
-#define ENUM_LP_STAT_PACK_DONE               (_ADI_MSK(0x00000000,uint32_t))  /* LERR: Packing Complete */
-#define ENUM_LP_STAT_PACK_PROG               (_ADI_MSK(0x00000080,uint32_t))  /* LERR: Packing Incomplete */
-
-#define BITM_LP_STAT_FFST                    (_ADI_MSK(0x00000070,uint32_t))  /* FIFO Status */
-#define ENUM_LP_STAT_RX0_TX0                 (_ADI_MSK(0x00000000,uint32_t))  /* FFST: TX - Empty; RX -Empty */
-#define ENUM_LP_STAT_RX1_TXR                 (_ADI_MSK(0x00000010,uint32_t))  /* FFST: TX - reserved ; RX - One Word */
-#define ENUM_LP_STAT_RX2_TXR                 (_ADI_MSK(0x00000020,uint32_t))  /* FFST: TX - reserved; RX - Two Word */
-#define ENUM_LP_STAT_RX3_TXR                 (_ADI_MSK(0x00000030,uint32_t))  /* FFST: TX - reserved; RX - Three Word */
-#define ENUM_LP_STAT_RX4_TX1                 (_ADI_MSK(0x00000040,uint32_t))  /* FFST: TX - One Word; RX - Four word */
-#define ENUM_LP_STAT_RXR1_TXR1               (_ADI_MSK(0x00000050,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define ENUM_LP_STAT_RXR2_TXR2               (_ADI_MSK(0x00000060,uint32_t))  /* FFST: TX - FIFO Full; RX - Reserved */
-#define ENUM_LP_STAT_RXR3_TXR3               (_ADI_MSK(0x00000070,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define BITM_LP_STAT_LPIT                    (_ADI_MSK(0x00000008,uint32_t))  /* Receive FIFO Overflow Interrupt */
-#define BITM_LP_STAT_LRRQ                    (_ADI_MSK(0x00000002,uint32_t))  /* Receive Request */
-#define BITM_LP_STAT_LTRQ                    (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_DIV                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_DIV_VALUE                     0                               /* Divisor Value */
-#define BITM_LP_DIV_VALUE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Divisor Value */
-
-/* ==================================================
-        General Purpose Timer Block Registers
-   ================================================== */
-
-/* =========================
-        TIMER0
-   ========================= */
-#define REG_TIMER0_REVID                0xFFC01400         /* TIMER0 Revision ID Register */
-#define REG_TIMER0_RUN                  0xFFC01404         /* TIMER0 Run Register */
-#define REG_TIMER0_RUN_SET              0xFFC01408         /* TIMER0 Run Set Register */
-#define REG_TIMER0_RUN_CLR              0xFFC0140C         /* TIMER0 Run Clear Register */
-#define REG_TIMER0_STOP_CFG             0xFFC01410         /* TIMER0 Stop Configuration Register */
-#define REG_TIMER0_STOP_CFG_SET         0xFFC01414         /* TIMER0 Stop Configuration Set Register */
-#define REG_TIMER0_STOP_CFG_CLR         0xFFC01418         /* TIMER0 Stop Configuration Clear Register */
-#define REG_TIMER0_DATA_IMSK            0xFFC0141C         /* TIMER0 Data Interrupt Mask Register */
-#define REG_TIMER0_STAT_IMSK            0xFFC01420         /* TIMER0 Status Interrupt Mask Register */
-#define REG_TIMER0_TRG_MSK              0xFFC01424         /* TIMER0 Trigger Master Mask Register */
-#define REG_TIMER0_TRG_IE               0xFFC01428         /* TIMER0 Trigger Slave Enable Register */
-#define REG_TIMER0_DATA_ILAT            0xFFC0142C         /* TIMER0 Data Interrupt Latch Register */
-#define REG_TIMER0_STAT_ILAT            0xFFC01430         /* TIMER0 Status Interrupt Latch Register */
-#define REG_TIMER0_ERR_TYPE             0xFFC01434         /* TIMER0 Error Type Status Register */
-#define REG_TIMER0_BCAST_PER            0xFFC01438         /* TIMER0 Broadcast Period Register */
-#define REG_TIMER0_BCAST_WID            0xFFC0143C         /* TIMER0 Broadcast Width Register */
-#define REG_TIMER0_BCAST_DLY            0xFFC01440         /* TIMER0 Broadcast Delay Register */
-#define REG_TIMER0_TMR0_CFG             0xFFC01460         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR1_CFG             0xFFC01480         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR2_CFG             0xFFC014A0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR3_CFG             0xFFC014C0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR4_CFG             0xFFC014E0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR5_CFG             0xFFC01500         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR6_CFG             0xFFC01520         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR7_CFG             0xFFC01540         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR0_CNT             0xFFC01464         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR1_CNT             0xFFC01484         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR2_CNT             0xFFC014A4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR3_CNT             0xFFC014C4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR4_CNT             0xFFC014E4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR5_CNT             0xFFC01504         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR6_CNT             0xFFC01524         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR7_CNT             0xFFC01544         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR0_PER             0xFFC01468         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR1_PER             0xFFC01488         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR2_PER             0xFFC014A8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR3_PER             0xFFC014C8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR4_PER             0xFFC014E8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR5_PER             0xFFC01508         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR6_PER             0xFFC01528         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR7_PER             0xFFC01548         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR0_WID             0xFFC0146C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR1_WID             0xFFC0148C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR2_WID             0xFFC014AC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR3_WID             0xFFC014CC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR4_WID             0xFFC014EC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR5_WID             0xFFC0150C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR6_WID             0xFFC0152C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR7_WID             0xFFC0154C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR0_DLY             0xFFC01470         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR1_DLY             0xFFC01490         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR2_DLY             0xFFC014B0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR3_DLY             0xFFC014D0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR4_DLY             0xFFC014F0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR5_DLY             0xFFC01510         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR6_DLY             0xFFC01530         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR7_DLY             0xFFC01550         /* TIMER0 Timer n Delay Register */
-
-/* =========================
-        TIMER
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_REVID                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_REVID_MAJOR                4                               /* Major Revision ID */
-#define BITP_TIMER_REVID_REV                  0                               /* Incremental Revision ID */
-#define BITM_TIMER_REVID_MAJOR               (_ADI_MSK(0x000000F0,uint16_t))  /* Major Revision ID */
-#define BITM_TIMER_REVID_REV                 (_ADI_MSK(0x0000000F,uint16_t))  /* Incremental Revision ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_TMR00                  0                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR01                  1                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR02                  2                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR03                  3                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR04                  4                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR05                  5                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR06                  6                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR07                  7                               /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR00                 (_ADI_MSK(0x00000001,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR01                 (_ADI_MSK(0x00000002,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR02                 (_ADI_MSK(0x00000004,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR03                 (_ADI_MSK(0x00000008,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR04                 (_ADI_MSK(0x00000010,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR05                 (_ADI_MSK(0x00000020,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR06                 (_ADI_MSK(0x00000040,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR07                 (_ADI_MSK(0x00000080,uint16_t))  /* Start/Stop Timer n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_SET_TMR00              0                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR01              1                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR02              2                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR03              3                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR04              4                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR05              5                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR06              6                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR07              7                               /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_CLR_TMR00              0                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR01              1                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR02              2                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR03              3                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR04              4                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR05              5                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR06              6                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR07              7                               /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_TMR00             0                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR01             1                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR02             2                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR03             3                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR04             4                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR05             5                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR06             6                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR07             7                               /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR00            (_ADI_MSK(0x00000001,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR01            (_ADI_MSK(0x00000002,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR02            (_ADI_MSK(0x00000004,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR03            (_ADI_MSK(0x00000008,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR04            (_ADI_MSK(0x00000010,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR05            (_ADI_MSK(0x00000020,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR06            (_ADI_MSK(0x00000040,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR07            (_ADI_MSK(0x00000080,uint16_t))  /* Stop Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_SET                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_SET_TMR00         0                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR01         1                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR02         2                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR03         3                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR04         4                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR05         5                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR06         6                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR07         7                               /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_CLR                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_CLR_TMR00         0                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR01         1                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR02         2                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR03         3                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR04         4                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR05         5                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR06         6                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR07         7                               /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_IMSK_TMR00            0                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR01            1                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR02            2                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR03            3                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR04            4                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR05            5                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR06            6                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR07            7                               /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_IMSK_TMR00            0                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR01            1                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR02            2                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR03            3                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR04            4                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR05            5                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR06            6                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR07            7                               /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_MSK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_MSK_TMR00              0                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR01              1                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR02              2                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR03              3                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR04              4                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR05              5                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR06              6                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR07              7                               /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Output Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_IE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_IE_TMR00               0                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR01               1                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR02               2                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR03               3                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR04               4                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR05               5                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR06               6                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR07               7                               /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR00              (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR01              (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR02              (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR03              (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR04              (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR05              (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR06              (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR07              (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_ILAT_TMR00            0                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR01            1                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR02            2                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR03            3                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR04            4                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR05            5                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR06            6                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR07            7                               /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_ILAT_TMR00            0                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR01            1                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR02            2                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR03            3                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR04            4                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR05            5                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR06            6                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR07            7                               /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_ERR_TYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_ERR_TYPE_TERR7            14                               /* Error type for Timer 7 */
-#define BITP_TIMER_ERR_TYPE_TERR6            12                               /* Error type for Timer 6 */
-#define BITP_TIMER_ERR_TYPE_TERR5            10                               /* Error type for Timer 5 */
-#define BITP_TIMER_ERR_TYPE_TERR4             8                               /* Error type for Timer 4 */
-#define BITP_TIMER_ERR_TYPE_TERR3             6                               /* Error type for Timer 3 */
-#define BITP_TIMER_ERR_TYPE_TERR2             4                               /* Error type for Timer 2 */
-#define BITP_TIMER_ERR_TYPE_TERR1             2                               /* Error type for Timer 1 */
-#define BITP_TIMER_ERR_TYPE_TERR0             0                               /* Error type for Timer 0 */
-
-#define BITM_TIMER_ERR_TYPE_TERR7            (_ADI_MSK(0x0000C000,uint32_t))  /* Error type for Timer 7 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR7          (_ADI_MSK(0x00000000,uint32_t))  /* TERR7: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF7          (_ADI_MSK(0x00004000,uint32_t))  /* TERR7: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG7          (_ADI_MSK(0x00008000,uint32_t))  /* TERR7: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG7        (_ADI_MSK(0x0000C000,uint32_t))  /* TERR7: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR6            (_ADI_MSK(0x00003000,uint32_t))  /* Error type for Timer 6 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR6          (_ADI_MSK(0x00000000,uint32_t))  /* TERR6: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF6          (_ADI_MSK(0x00001000,uint32_t))  /* TERR6: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG6          (_ADI_MSK(0x00002000,uint32_t))  /* TERR6: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG6        (_ADI_MSK(0x00003000,uint32_t))  /* TERR6: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR5            (_ADI_MSK(0x00000C00,uint32_t))  /* Error type for Timer 5 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR5          (_ADI_MSK(0x00000000,uint32_t))  /* TERR5: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF5          (_ADI_MSK(0x00000400,uint32_t))  /* TERR5: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG5          (_ADI_MSK(0x00000800,uint32_t))  /* TERR5: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG5        (_ADI_MSK(0x00000C00,uint32_t))  /* TERR5: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR4            (_ADI_MSK(0x00000300,uint32_t))  /* Error type for Timer 4 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR4          (_ADI_MSK(0x00000000,uint32_t))  /* TERR4: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF4          (_ADI_MSK(0x00000100,uint32_t))  /* TERR4: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG4          (_ADI_MSK(0x00000200,uint32_t))  /* TERR4: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG4        (_ADI_MSK(0x00000300,uint32_t))  /* TERR4: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR3            (_ADI_MSK(0x000000C0,uint32_t))  /* Error type for Timer 3 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR3          (_ADI_MSK(0x00000000,uint32_t))  /* TERR3: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF3          (_ADI_MSK(0x00000040,uint32_t))  /* TERR3: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG3          (_ADI_MSK(0x00000080,uint32_t))  /* TERR3: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG3        (_ADI_MSK(0x000000C0,uint32_t))  /* TERR3: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR2            (_ADI_MSK(0x00000030,uint32_t))  /* Error type for Timer 2 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR2          (_ADI_MSK(0x00000000,uint32_t))  /* TERR2: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF2          (_ADI_MSK(0x00000010,uint32_t))  /* TERR2: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG2          (_ADI_MSK(0x00000020,uint32_t))  /* TERR2: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG2        (_ADI_MSK(0x00000030,uint32_t))  /* TERR2: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR1            (_ADI_MSK(0x0000000C,uint32_t))  /* Error type for Timer 1 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR1          (_ADI_MSK(0x00000000,uint32_t))  /* TERR1: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF1          (_ADI_MSK(0x00000004,uint32_t))  /* TERR1: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG1          (_ADI_MSK(0x00000008,uint32_t))  /* TERR1: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG1        (_ADI_MSK(0x0000000C,uint32_t))  /* TERR1: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR0            (_ADI_MSK(0x00000003,uint32_t))  /* Error type for Timer 0 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR0          (_ADI_MSK(0x00000000,uint32_t))  /* TERR0: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF0          (_ADI_MSK(0x00000001,uint32_t))  /* TERR0: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG0          (_ADI_MSK(0x00000002,uint32_t))  /* TERR0: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG0        (_ADI_MSK(0x00000003,uint32_t))  /* TERR0: WID or DLY Register Programming Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TMR_CFG                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TMR_CFG_EMURUN            15                               /* Run Timer (Counter) During Emulation */
-#define BITP_TIMER_TMR_CFG_BPEREN            14                               /* Broadcast Period Enable */
-#define BITP_TIMER_TMR_CFG_BWIDEN            13                               /* Broadcast Width Enable */
-#define BITP_TIMER_TMR_CFG_BDLYEN            12                               /* Broadcast Delay Enable */
-#define BITP_TIMER_TMR_CFG_OUTDIS            11                               /* Output Disable */
-#define BITP_TIMER_TMR_CFG_TINSEL            10                               /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define BITP_TIMER_TMR_CFG_CLKSEL             8                               /* Clock Select */
-#define BITP_TIMER_TMR_CFG_PULSEHI            7                               /* Polarity Response Select */
-#define BITP_TIMER_TMR_CFG_SLAVETRIG          6                               /* Slave Trigger Response */
-#define BITP_TIMER_TMR_CFG_IRQMODE            4                               /* Interrupt Modes */
-#define BITP_TIMER_TMR_CFG_TMODE              0                               /* Timer Mode Select */
-
-#define BITM_TIMER_TMR_CFG_EMURUN            (_ADI_MSK(0x00008000,uint16_t))  /* Run Timer (Counter) During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_NOCNT         (_ADI_MSK(0x00000000,uint16_t))  /* EMURUN: Stop Timer During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_CNT           (_ADI_MSK(0x00008000,uint16_t))  /* EMURUN: Run Timer During Emulation */
-
-#define BITM_TIMER_TMR_CFG_BPEREN            (_ADI_MSK(0x00004000,uint16_t))  /* Broadcast Period Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BPEREN: Disable Broadcast to PER Register */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_EN       (_ADI_MSK(0x00004000,uint16_t))  /* BPEREN: Enable Broadcast to PER Register */
-
-#define BITM_TIMER_TMR_CFG_BWIDEN            (_ADI_MSK(0x00002000,uint16_t))  /* Broadcast Width Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BWIDEN: Disable Broadcast to WID Register */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_EN       (_ADI_MSK(0x00002000,uint16_t))  /* BWIDEN: Enable Broadcast to WID Register */
-
-#define BITM_TIMER_TMR_CFG_BDLYEN            (_ADI_MSK(0x00001000,uint16_t))  /* Broadcast Delay Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BDLYEN: Disable Broadcast to DLY Register */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_EN       (_ADI_MSK(0x00001000,uint16_t))  /* BDLYEN: Enable Broadcast to DLY Register */
-
-#define BITM_TIMER_TMR_CFG_OUTDIS            (_ADI_MSK(0x00000800,uint16_t))  /* Output Disable */
-#define ENUM_TIMER_TMR_CFG_PADOUT_EN         (_ADI_MSK(0x00000000,uint16_t))  /* OUTDIS: Enable TMR pin output buffer */
-#define ENUM_TIMER_TMR_CFG_PADOUT_DIS        (_ADI_MSK(0x00000800,uint16_t))  /* OUTDIS: Disable TMR pin output buffer */
-
-#define BITM_TIMER_TMR_CFG_TINSEL            (_ADI_MSK(0x00000400,uint16_t))  /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define ENUM_TIMER_TMR_CFG_TINSEL_TMR        (_ADI_MSK(0x00000000,uint16_t))  /* TINSEL: Use TMR pin input */
-#define ENUM_TIMER_TMR_CFG_TINSEL_AUX        (_ADI_MSK(0x00000400,uint16_t))  /* TINSEL: Use TMR Alternate Capture Input */
-
-#define BITM_TIMER_TMR_CFG_CLKSEL            (_ADI_MSK(0x00000300,uint16_t))  /* Clock Select */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_SCLK       (_ADI_MSK(0x00000000,uint16_t))  /* CLKSEL: Use SCLK */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT0       (_ADI_MSK(0x00000100,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK0 as the TMR clock */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT1       (_ADI_MSK(0x00000300,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK1 as the TMR clock */
-
-#define BITM_TIMER_TMR_CFG_PULSEHI           (_ADI_MSK(0x00000080,uint16_t))  /* Polarity Response Select */
-#define ENUM_TIMER_TMR_CFG_NEG_EDGE          (_ADI_MSK(0x00000000,uint16_t))  /* PULSEHI: Negative Response/Pulse */
-#define ENUM_TIMER_TMR_CFG_POS_EDGE          (_ADI_MSK(0x00000080,uint16_t))  /* PULSEHI: Positive  Response/Pulse */
-
-#define BITM_TIMER_TMR_CFG_SLAVETRIG         (_ADI_MSK(0x00000040,uint16_t))  /* Slave Trigger Response */
-#define ENUM_TIMER_TMR_CFG_TRIGSTOP          (_ADI_MSK(0x00000000,uint16_t))  /* SLAVETRIG: Pulse stops timer if it is running */
-#define ENUM_TIMER_TMR_CFG_TRIGSTART         (_ADI_MSK(0x00000040,uint16_t))  /* SLAVETRIG: Pulse starts timer if it is stopped */
-
-#define BITM_TIMER_TMR_CFG_IRQMODE           (_ADI_MSK(0x00000030,uint16_t))  /* Interrupt Modes */
-#define ENUM_TIMER_TMR_CFG_IRQMODE0          (_ADI_MSK(0x00000000,uint16_t))  /* IRQMODE: Active Edge Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE1          (_ADI_MSK(0x00000010,uint16_t))  /* IRQMODE: Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE2          (_ADI_MSK(0x00000020,uint16_t))  /* IRQMODE: Width Plus Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE3          (_ADI_MSK(0x00000030,uint16_t))  /* IRQMODE: Period Expired Mode */
-
-#define BITM_TIMER_TMR_CFG_TMODE             (_ADI_MSK(0x0000000F,uint16_t))  /* Timer Mode Select */
-#define ENUM_TIMER_TMR_CFG_IDLE_MODE         (_ADI_MSK(0x00000000,uint16_t))  /* TMODE: Idle Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP0_MODE      (_ADI_MSK(0x0000000A,uint16_t))  /* TMODE: Width Capture Asserted Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP1_MODE      (_ADI_MSK(0x0000000B,uint16_t))  /* TMODE: Width Capture Deasserted Mode */
-#define ENUM_TIMER_TMR_CFG_PWMCONT_MODE      (_ADI_MSK(0x0000000C,uint16_t))  /* TMODE: Continuous PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_PWMSING_MODE      (_ADI_MSK(0x0000000D,uint16_t))  /* TMODE: Single pulse PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_EXTCLK_MODE       (_ADI_MSK(0x0000000E,uint16_t))  /* TMODE: EXTCLK mode */
-#define ENUM_TIMER_TMR_CFG_PININT_MODE       (_ADI_MSK(0x0000000F,uint16_t))  /* TMODE: PININT (pin interrupt) mode */
-#define ENUM_TIMER_TMR_CFG_WDPER_MODE        (_ADI_MSK(0x00000008,uint16_t))  /* TMODE: Period Watchdog Mode */
-#define ENUM_TIMER_TMR_CFG_WDWID_MODE        (_ADI_MSK(0x00000009,uint16_t))  /* TMODE: Width Watchdog Mode */
-
-/* ==================================================
-        Cyclic Redundancy Check Unit Registers
-   ================================================== */
-
-/* =========================
-        CRC0
-   ========================= */
-#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
-#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 Data Compare Register */
-#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 Data FIFO Register */
-#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 Data Count Capture Register */
-#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 CRC Final Result Register */
-#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 CRC Current Result Register */
-#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
-
-/* =========================
-        CRC1
-   ========================= */
-#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
-#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 Data Compare Register */
-#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 Data FIFO Register */
-#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 Data Count Capture Register */
-#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 CRC Final Result Register */
-#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 CRC Current Result Register */
-#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
-
-/* =========================
-        CRC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_CTL_CMPMIRR                 22                               /* COMPARE Register Mirroring */
-#define BITP_CRC_CTL_POLYMIRR                21                               /* Polynomial Register Mirroring */
-#define BITP_CRC_CTL_RSLTMIRR                20                               /* Result Register Mirroring */
-#define BITP_CRC_CTL_FDSEL                   19                               /* FIFO Data Select */
-#define BITP_CRC_CTL_W16SWP                  18                               /* Word16 Swapping */
-#define BITP_CRC_CTL_BYTMIRR                 17                               /* Byte Mirroring */
-#define BITP_CRC_CTL_BITMIRR                 16                               /* Bit Mirroring */
-#define BITP_CRC_CTL_IRRSTALL                13                               /* Intermediate Result Ready Stall */
-#define BITP_CRC_CTL_OBRSTALL                12                               /* Output Buffer Ready Stall */
-#define BITP_CRC_CTL_AUTOCLRF                 9                               /* Auto Clear to One */
-#define BITP_CRC_CTL_AUTOCLRZ                 8                               /* Auto Clear to Zero */
-#define BITP_CRC_CTL_OPMODE                   4                               /* Operation Mode */
-#define BITP_CRC_CTL_BLKEN                    0                               /* Block Enable */
-#define BITM_CRC_CTL_CMPMIRR                 (_ADI_MSK(0x00400000,uint32_t))  /* COMPARE Register Mirroring */
-#define BITM_CRC_CTL_POLYMIRR                (_ADI_MSK(0x00200000,uint32_t))  /* Polynomial Register Mirroring */
-#define BITM_CRC_CTL_RSLTMIRR                (_ADI_MSK(0x00100000,uint32_t))  /* Result Register Mirroring */
-#define BITM_CRC_CTL_FDSEL                   (_ADI_MSK(0x00080000,uint32_t))  /* FIFO Data Select */
-#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK(0x00040000,uint32_t))  /* Word16 Swapping */
-#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK(0x00020000,uint32_t))  /* Byte Mirroring */
-#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK(0x00010000,uint32_t))  /* Bit Mirroring */
-#define BITM_CRC_CTL_IRRSTALL                (_ADI_MSK(0x00002000,uint32_t))  /* Intermediate Result Ready Stall */
-#define BITM_CRC_CTL_OBRSTALL                (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Ready Stall */
-#define BITM_CRC_CTL_AUTOCLRF                (_ADI_MSK(0x00000200,uint32_t))  /* Auto Clear to One */
-#define BITM_CRC_CTL_AUTOCLRZ                (_ADI_MSK(0x00000100,uint32_t))  /* Auto Clear to Zero */
-#define BITM_CRC_CTL_OPMODE                  (_ADI_MSK(0x000000F0,uint32_t))  /* Operation Mode */
-#define BITM_CRC_CTL_BLKEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Block Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_DCNTEXP                 4                               /* Data Count Expired (Status) Interrupt Enable */
-#define BITP_CRC_INEN_CMPERR                  1                               /* Compare Error Interrupt Enable */
-
-#define BITM_CRC_INEN_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable */
-#define ENUM_CRC_INEN_DCNTEXP_MSK            (_ADI_MSK(0x00000000,uint32_t))  /* DCNTEXP: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_DCNTEXP_UMSK           (_ADI_MSK(0x00000010,uint32_t))  /* DCNTEXP: Enable (unmask) interrupt */
-
-#define BITM_CRC_INEN_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable */
-#define ENUM_CRC_INEN_CMPERR_MSK             (_ADI_MSK(0x00000000,uint32_t))  /* CMPERR: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_CMPERR_UMSK            (_ADI_MSK(0x00000002,uint32_t))  /* CMPERR: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_SET_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITP_CRC_INEN_SET_CMPERR              1                               /* Compare Error Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_CLR_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITP_CRC_INEN_CLR_CMPERR              1                               /* Compare Error Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_STAT_FSTAT                  20                               /* FIFO Status */
-#define BITP_CRC_STAT_LUTDONE                19                               /* Look Up Table Done */
-#define BITP_CRC_STAT_IRR                    18                               /* Intermediate Result Ready */
-#define BITP_CRC_STAT_OBR                    17                               /* Output Buffer Ready */
-#define BITP_CRC_STAT_IBR                    16                               /* Input Buffer Ready */
-#define BITP_CRC_STAT_DCNTEXP                 4                               /* Data Count Expired */
-#define BITP_CRC_STAT_CMPERR                  1                               /* Compare Error */
-#define BITM_CRC_STAT_FSTAT                  (_ADI_MSK(0x00700000,uint32_t))  /* FIFO Status */
-#define BITM_CRC_STAT_LUTDONE                (_ADI_MSK(0x00080000,uint32_t))  /* Look Up Table Done */
-#define BITM_CRC_STAT_IRR                    (_ADI_MSK(0x00040000,uint32_t))  /* Intermediate Result Ready */
-#define BITM_CRC_STAT_OBR                    (_ADI_MSK(0x00020000,uint32_t))  /* Output Buffer Ready */
-#define BITM_CRC_STAT_IBR                    (_ADI_MSK(0x00010000,uint32_t))  /* Input Buffer Ready */
-#define BITM_CRC_STAT_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired */
-#define BITM_CRC_STAT_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_REVID_MAJOR                  4                               /* Major Revision ID */
-#define BITP_CRC_REVID_REV                    0                               /* Incremental Revision ID */
-#define BITM_CRC_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Revision ID */
-#define BITM_CRC_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Revision ID */
-
-/* ==================================================
-        2-Wire Interface Registers
-   ================================================== */
-
-/* =========================
-        TWI0
-   ========================= */
-#define REG_TWI0_CLKDIV                 0xFFC01E00         /* TWI0 SCL Clock Divider Register */
-#define REG_TWI0_CTL                    0xFFC01E04         /* TWI0 Control Register */
-#define REG_TWI0_SLVCTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
-#define REG_TWI0_SLVSTAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
-#define REG_TWI0_SLVADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
-#define REG_TWI0_MSTRCTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
-#define REG_TWI0_MSTRSTAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
-#define REG_TWI0_MSTRADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
-#define REG_TWI0_ISTAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
-#define REG_TWI0_IMSK                   0xFFC01E24         /* TWI0 Interrupt Mask Register */
-#define REG_TWI0_FIFOCTL                0xFFC01E28         /* TWI0 FIFO Control Register */
-#define REG_TWI0_FIFOSTAT               0xFFC01E2C         /* TWI0 FIFO Status Register */
-#define REG_TWI0_TXDATA8                0xFFC01E80         /* TWI0 Tx Data Single-Byte Register */
-#define REG_TWI0_TXDATA16               0xFFC01E84         /* TWI0 Tx Data Double-Byte Register */
-#define REG_TWI0_RXDATA8                0xFFC01E88         /* TWI0 Rx Data Single-Byte Register */
-#define REG_TWI0_RXDATA16               0xFFC01E8C         /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI1
-   ========================= */
-#define REG_TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider Register */
-#define REG_TWI1_CTL                    0xFFC01F04         /* TWI1 Control Register */
-#define REG_TWI1_SLVCTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
-#define REG_TWI1_SLVSTAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
-#define REG_TWI1_SLVADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
-#define REG_TWI1_MSTRCTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
-#define REG_TWI1_MSTRSTAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
-#define REG_TWI1_MSTRADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
-#define REG_TWI1_ISTAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
-#define REG_TWI1_IMSK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
-#define REG_TWI1_FIFOCTL                0xFFC01F28         /* TWI1 FIFO Control Register */
-#define REG_TWI1_FIFOSTAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
-#define REG_TWI1_TXDATA8                0xFFC01F80         /* TWI1 Tx Data Single-Byte Register */
-#define REG_TWI1_TXDATA16               0xFFC01F84         /* TWI1 Tx Data Double-Byte Register */
-#define REG_TWI1_RXDATA8                0xFFC01F88         /* TWI1 Rx Data Single-Byte Register */
-#define REG_TWI1_RXDATA16               0xFFC01F8C         /* TWI1 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CLKDIV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CLKDIV_CLKHI                 8                               /* SCL Clock High Periods */
-#define BITP_TWI_CLKDIV_CLKLO                 0                               /* SCL Clock Low Periods */
-#define BITM_TWI_CLKDIV_CLKHI                (_ADI_MSK(0x0000FF00,uint16_t))  /* SCL Clock High Periods */
-#define BITM_TWI_CLKDIV_CLKLO                (_ADI_MSK(0x000000FF,uint16_t))  /* SCL Clock Low Periods */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CTL_SCCB                     9                               /* SCCB Compatibility */
-#define BITP_TWI_CTL_EN                       7                               /* Enable Module */
-#define BITP_TWI_CTL_PRESCALE                 0                               /* SCLK Prescale Value */
-
-#define BITM_TWI_CTL_SCCB                    (_ADI_MSK(0x00000200,uint16_t))  /* SCCB Compatibility */
-#define ENUM_TWI_CTL_SCCB_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* SCCB: Disable SCCB compatibility */
-#define ENUM_TWI_CTL_SCCB_EN                 (_ADI_MSK(0x00000200,uint16_t))  /* SCCB: Enable SCCB compatibility */
-
-#define BITM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* Enable Module */
-#define ENUM_TWI_CTL_DIS                     (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* EN: Enable */
-#define BITM_TWI_CTL_PRESCALE                (_ADI_MSK(0x0000007F,uint16_t))  /* SCLK Prescale Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVCTL_GEN                   4                               /* General Call Enable */
-#define BITP_TWI_SLVCTL_NAK                   3                               /* Not Acknowledge */
-#define BITP_TWI_SLVCTL_TDVAL                 2                               /* Transmit Data Valid for Slave */
-#define BITP_TWI_SLVCTL_EN                    0                               /* Enable Slave Mode */
-
-#define BITM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* General Call Enable */
-#define ENUM_TWI_SLVCTL_GDIS                 (_ADI_MSK(0x00000000,uint16_t))  /* GEN: Disable General Call Matching */
-#define ENUM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* GEN: Enable General Call Matching */
-
-#define BITM_TWI_SLVCTL_NAK                  (_ADI_MSK(0x00000008,uint16_t))  /* Not Acknowledge */
-#define ENUM_TWI_SLVCTL_ACKGEN               (_ADI_MSK(0x00000000,uint16_t))  /* NAK: Generate ACK */
-#define ENUM_TWI_SLVCTL_NAKGEN               (_ADI_MSK(0x00000008,uint16_t))  /* NAK: Generate NAK */
-
-#define BITM_TWI_SLVCTL_TDVAL                (_ADI_MSK(0x00000004,uint16_t))  /* Transmit Data Valid for Slave */
-#define ENUM_TWI_SLVCTL_INVALID              (_ADI_MSK(0x00000000,uint16_t))  /* TDVAL: Data Invalid for Slave Tx */
-#define ENUM_TWI_SLVCTL_VALID                (_ADI_MSK(0x00000004,uint16_t))  /* TDVAL: Data Valid for Slave Tx */
-
-#define BITM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* Enable Slave Mode */
-#define ENUM_TWI_SLVCTL_DIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVSTAT_GCALL                1                               /* General Call */
-#define BITP_TWI_SLVSTAT_DIR                  0                               /* Transfer Direction for Slave */
-
-#define BITM_TWI_SLVSTAT_GCALL               (_ADI_MSK(0x00000002,uint16_t))  /* General Call */
-#define ENUM_TWI_SLVSTAT_NO                  (_ADI_MSK(0x00000000,uint16_t))  /* GCALL: Not a General Call Address */
-#define ENUM_TWI_SLVSTAT_YES                 (_ADI_MSK(0x00000002,uint16_t))  /* GCALL: General Call Address */
-
-#define BITM_TWI_SLVSTAT_DIR                 (_ADI_MSK(0x00000001,uint16_t))  /* Transfer Direction for Slave */
-#define ENUM_TWI_SLVSTAT_RX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Slave Receive */
-#define ENUM_TWI_SLVSTAT_TX                  (_ADI_MSK(0x00000001,uint16_t))  /* DIR: Slave Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVADDR_ADDR                 0                               /* Slave Mode Address */
-#define BITM_TWI_SLVADDR_ADDR                (_ADI_MSK(0x0000007F,uint16_t))  /* Slave Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRCTL_SCLOVR              15                               /* Serial Clock Override */
-#define BITP_TWI_MSTRCTL_SDAOVR              14                               /* Serial Data Override */
-#define BITP_TWI_MSTRCTL_DCNT                 6                               /* Data Transfer Count */
-#define BITP_TWI_MSTRCTL_RSTART               5                               /* Repeat Start */
-#define BITP_TWI_MSTRCTL_STOP                 4                               /* Issue Stop Condition */
-#define BITP_TWI_MSTRCTL_FAST                 3                               /* Fast Mode */
-#define BITP_TWI_MSTRCTL_DIR                  2                               /* Transfer Direction for Master */
-#define BITP_TWI_MSTRCTL_EN                   0                               /* Enable Master Mode */
-
-#define BITM_TWI_MSTRCTL_SCLOVR              (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Override */
-#define ENUM_TWI_MSTRCTL_SCLNORM             (_ADI_MSK(0x00000000,uint16_t))  /* SCLOVR: Permit Normal SCL Operation */
-#define ENUM_TWI_MSTRCTL_SCLOVER             (_ADI_MSK(0x00008000,uint16_t))  /* SCLOVR: Override Normal SCL Operation */
-
-#define BITM_TWI_MSTRCTL_SDAOVR              (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Override */
-#define ENUM_TWI_MSTRCTL_SDANORM             (_ADI_MSK(0x00000000,uint16_t))  /* SDAOVR: Permit Normal SDA Operation */
-#define ENUM_TWI_MSTRCTL_SDAOVER             (_ADI_MSK(0x00004000,uint16_t))  /* SDAOVR: Override Normal SDA Operation */
-#define BITM_TWI_MSTRCTL_DCNT                (_ADI_MSK(0x00003FC0,uint16_t))  /* Data Transfer Count */
-
-#define BITM_TWI_MSTRCTL_RSTART              (_ADI_MSK(0x00000020,uint16_t))  /* Repeat Start */
-#define ENUM_TWI_MSTRCTL_END                 (_ADI_MSK(0x00000000,uint16_t))  /* RSTART: Disable Repeat Start */
-#define ENUM_TWI_MSTRCTL_RPT                 (_ADI_MSK(0x00000020,uint16_t))  /* RSTART: Enable Repeat Start */
-
-#define BITM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* Issue Stop Condition */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* STOP: Permit Normal Operation */
-#define ENUM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* STOP: Issue Stop */
-
-#define BITM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* Fast Mode */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* FAST: Select Standard Mode */
-#define ENUM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* FAST: Select Fast Mode */
-
-#define BITM_TWI_MSTRCTL_DIR                 (_ADI_MSK(0x00000004,uint16_t))  /* Transfer Direction for Master */
-#define ENUM_TWI_MSTRCTL_TX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Master Transmit */
-#define ENUM_TWI_MSTRCTL_RX                  (_ADI_MSK(0x00000004,uint16_t))  /* DIR: Master Receive */
-
-#define BITM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* Enable Master Mode */
-#define ENUM_TWI_MSTRCTL_DIS                 (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRSTAT_BUSBUSY             8                               /* Bus Busy */
-#define BITP_TWI_MSTRSTAT_SCLSEN              7                               /* Serial Clock Sense */
-#define BITP_TWI_MSTRSTAT_SDASEN              6                               /* Serial Data Sense */
-#define BITP_TWI_MSTRSTAT_BUFWRERR            5                               /* Buffer Write Error */
-#define BITP_TWI_MSTRSTAT_BUFRDERR            4                               /* Buffer Read Error */
-#define BITP_TWI_MSTRSTAT_DNAK                3                               /* Data Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_ANAK                2                               /* Address Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_LOSTARB             1                               /* Lost Arbitration */
-#define BITP_TWI_MSTRSTAT_MPROG               0                               /* Master Transfer in Progress */
-
-#define BITM_TWI_MSTRSTAT_BUSBUSY            (_ADI_MSK(0x00000100,uint16_t))  /* Bus Busy */
-#define ENUM_TWI_MSTRSTAT_FREE               (_ADI_MSK(0x00000000,uint16_t))  /* BUSBUSY: Bus Free */
-#define ENUM_TWI_MSTRSTAT_BUSY               (_ADI_MSK(0x00000100,uint16_t))  /* BUSBUSY: Bus Busy */
-
-#define BITM_TWI_MSTRSTAT_SCLSEN             (_ADI_MSK(0x00000080,uint16_t))  /* Serial Clock Sense */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SCLSEN: SCL Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_YES         (_ADI_MSK(0x00000080,uint16_t))  /* SCLSEN: SCL Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_SDASEN             (_ADI_MSK(0x00000040,uint16_t))  /* Serial Data Sense */
-#define ENUM_TWI_MSTRSTAT_SDASEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SDASEN: SDA Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SDASEN_YES         (_ADI_MSK(0x00000040,uint16_t))  /* SDASEN: SDA Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_BUFWRERR           (_ADI_MSK(0x00000020,uint16_t))  /* Buffer Write Error */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFWRERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_YES       (_ADI_MSK(0x00000020,uint16_t))  /* BUFWRERR: Buffer Write Error */
-
-#define BITM_TWI_MSTRSTAT_BUFRDERR           (_ADI_MSK(0x00000010,uint16_t))  /* Buffer Read Error */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFRDERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_YES       (_ADI_MSK(0x00000010,uint16_t))  /* BUFRDERR: Buffer Read Error */
-
-#define BITM_TWI_MSTRSTAT_DNAK               (_ADI_MSK(0x00000008,uint16_t))  /* Data Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_DNAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* DNAK: No Status */
-#define ENUM_TWI_MSTRSTAT_DNAK_YES           (_ADI_MSK(0x00000008,uint16_t))  /* DNAK: Data NAK */
-
-#define BITM_TWI_MSTRSTAT_ANAK               (_ADI_MSK(0x00000004,uint16_t))  /* Address Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_ANAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* ANAK: No Status */
-#define ENUM_TWI_MSTRSTAT_ANAK_YES           (_ADI_MSK(0x00000004,uint16_t))  /* ANAK: Address NAK */
-
-#define BITM_TWI_MSTRSTAT_LOSTARB            (_ADI_MSK(0x00000002,uint16_t))  /* Lost Arbitration */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_NO         (_ADI_MSK(0x00000000,uint16_t))  /* LOSTARB: No Status */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_YES        (_ADI_MSK(0x00000002,uint16_t))  /* LOSTARB: Lost Arbitration */
-
-#define BITM_TWI_MSTRSTAT_MPROG              (_ADI_MSK(0x00000001,uint16_t))  /* Master Transfer in Progress */
-#define ENUM_TWI_MSTRSTAT_MPROG_NO           (_ADI_MSK(0x00000000,uint16_t))  /* MPROG: No Status */
-#define ENUM_TWI_MSTRSTAT_MPROG_YES          (_ADI_MSK(0x00000001,uint16_t))  /* MPROG: Master Transfer in Progress */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRADDR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRADDR_ADDR                0                               /* Master Mode Address */
-#define BITM_TWI_MSTRADDR_ADDR               (_ADI_MSK(0x0000007F,uint16_t))  /* Master Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_ISTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_ISTAT_SCLI                  15                               /* Serial Clock Interrupt */
-#define BITP_TWI_ISTAT_SDAI                  14                               /* Serial Data Interrupt */
-#define BITP_TWI_ISTAT_RXSERV                 7                               /* Rx FIFO Service */
-#define BITP_TWI_ISTAT_TXSERV                 6                               /* Tx FIFO Service */
-#define BITP_TWI_ISTAT_MERR                   5                               /* Master Transfer Error */
-#define BITP_TWI_ISTAT_MCOMP                  4                               /* Master Transfer Complete */
-#define BITP_TWI_ISTAT_SOVF                   3                               /* Slave Overflow */
-#define BITP_TWI_ISTAT_SERR                   2                               /* Slave Transfer Error */
-#define BITP_TWI_ISTAT_SCOMP                  1                               /* Slave Transfer Complete */
-#define BITP_TWI_ISTAT_SINIT                  0                               /* Slave Transfer Initiated */
-
-#define BITM_TWI_ISTAT_SCLI                  (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: No Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_YES              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SDAI                  (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: No Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_YES              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_RXSERV                (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service */
-#define ENUM_TWI_ISTAT_RXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_RXSERV_YES            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_TXSERV                (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service */
-#define ENUM_TWI_ISTAT_TXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_TXSERV_YES            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MERR                  (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error */
-#define ENUM_TWI_ISTAT_MERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: No Interrupt */
-#define ENUM_TWI_ISTAT_MERR_YES              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MCOMP                 (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete */
-#define ENUM_TWI_ISTAT_MCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_MCOMP_YES             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SOVF                  (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow */
-#define ENUM_TWI_ISTAT_SOVF_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: No Interrupt */
-#define ENUM_TWI_ISTAT_SOVF_YES              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SERR                  (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error */
-#define ENUM_TWI_ISTAT_SERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: No Interrupt */
-#define ENUM_TWI_ISTAT_SERR_YES              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SCOMP                 (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete */
-#define ENUM_TWI_ISTAT_SCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_SCOMP_YES             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SINIT                 (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated */
-#define ENUM_TWI_ISTAT_SINIT_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: No Interrupt */
-#define ENUM_TWI_ISTAT_SINIT_YES             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Interrupt Detected */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_IMSK_SCLI                   15                               /* Serial Clock Interrupt Mask */
-#define BITP_TWI_IMSK_SDAI                   14                               /* Serial Data Interrupt Mask */
-#define BITP_TWI_IMSK_RXSERV                  7                               /* Rx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_TXSERV                  6                               /* Tx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_MERR                    5                               /* Master Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_MCOMP                   4                               /* Master Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SOVF                    3                               /* Slave Overflow Interrupt Mask */
-#define BITP_TWI_IMSK_SERR                    2                               /* Slave Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_SCOMP                   1                               /* Slave Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SINIT                   0                               /* Slave Transfer Initiated Interrupt Mask */
-
-#define BITM_TWI_IMSK_SCLI                   (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt Mask */
-#define ENUM_TWI_IMSK_SCLI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCLI_UMSK              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SDAI                   (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt Mask */
-#define ENUM_TWI_IMSK_SDAI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SDAI_UMSK              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_RXSERV                 (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_RXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_RXSERV_UMSK            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_TXSERV                 (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_TXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_TXSERV_UMSK            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MERR                   (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_MERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MERR_UMSK              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MCOMP                  (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_MCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MCOMP_UMSK             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SOVF                   (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow Interrupt Mask */
-#define ENUM_TWI_IMSK_SOVF_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SOVF_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SERR                   (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_SERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SERR_UMSK              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SCOMP                  (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_SCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCOMP_UMSK             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SINIT                  (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated Interrupt Mask */
-#define ENUM_TWI_IMSK_SINIT_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SINIT_UMSK             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Unmask (Enable) Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOCTL_RXILEN               3                               /* Rx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_TXILEN               2                               /* Tx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_RXFLUSH              1                               /* Rx Buffer Flush */
-#define BITP_TWI_FIFOCTL_TXFLUSH              0                               /* Tx Buffer Flush */
-
-#define BITM_TWI_FIFOCTL_RXILEN              (_ADI_MSK(0x00000008,uint16_t))  /* Rx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_RXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* RXILEN: RXSERVI on 1 or 2 Bytes in FIFO */
-#define ENUM_TWI_FIFOCTL_RXTWOBYTE           (_ADI_MSK(0x00000008,uint16_t))  /* RXILEN: RXSERVI on 2 Bytes in FIFO */
-
-#define BITM_TWI_FIFOCTL_TXILEN              (_ADI_MSK(0x00000004,uint16_t))  /* Tx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_TXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* TXILEN: TXSERVI on 1 Byte of FIFO Empty */
-#define ENUM_TWI_FIFOCTL_TXTWOBYTE           (_ADI_MSK(0x00000004,uint16_t))  /* TXILEN: TXSERVI on 2 Bytes of FIFO Empty */
-
-#define BITM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* Rx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_RXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* RXFLUSH: Normal Operation of Rx Buffer */
-#define ENUM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* RXFLUSH: Flush Rx Buffer */
-
-#define BITM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* Tx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_TXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* TXFLUSH: Normal Operation of Tx Buffer */
-#define ENUM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* TXFLUSH: Flush Tx Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOSTAT_RXSTAT              2                               /* Rx FIFO Status */
-#define BITP_TWI_FIFOSTAT_TXSTAT              0                               /* Tx FIFO Status */
-#define BITM_TWI_FIFOSTAT_RXSTAT             (_ADI_MSK(0x0000000C,uint16_t))  /* Rx FIFO Status */
-#define BITM_TWI_FIFOSTAT_TXSTAT             (_ADI_MSK(0x00000003,uint16_t))  /* Tx FIFO Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_TXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_TXDATA8_VALUE                0                               /* Tx Data 8-Bit Value */
-#define BITM_TWI_TXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Tx Data 8-Bit Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_RXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_RXDATA8_VALUE                0                               /* Rx Data 8-Bit Value */
-#define BITM_TWI_RXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Rx Data 8-Bit Value */
-
-/* ==================================================
-        UART Registers
-   ================================================== */
-
-/* =========================
-        UART0
-   ========================= */
-#define REG_UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
-#define REG_UART0_CTL                   0xFFC02004         /* UART0 Control Register */
-#define REG_UART0_STAT                  0xFFC02008         /* UART0 Status Register */
-#define REG_UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
-#define REG_UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
-#define REG_UART0_IMSK                  0xFFC02014         /* UART0 Interrupt Mask Register */
-#define REG_UART0_IMSK_SET              0xFFC02018         /* UART0 Interrupt Mask Set Register */
-#define REG_UART0_IMSK_CLR              0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
-#define REG_UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
-#define REG_UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
-#define REG_UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
-#define REG_UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
-#define REG_UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
-#define REG_UART0_TXCNT                 0xFFC02034         /* UART0 Transmit Counter Register */
-#define REG_UART0_RXCNT                 0xFFC02038         /* UART0 Receive Counter Register */
-
-/* =========================
-        UART1
-   ========================= */
-#define REG_UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
-#define REG_UART1_CTL                   0xFFC02404         /* UART1 Control Register */
-#define REG_UART1_STAT                  0xFFC02408         /* UART1 Status Register */
-#define REG_UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
-#define REG_UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
-#define REG_UART1_IMSK                  0xFFC02414         /* UART1 Interrupt Mask Register */
-#define REG_UART1_IMSK_SET              0xFFC02418         /* UART1 Interrupt Mask Set Register */
-#define REG_UART1_IMSK_CLR              0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
-#define REG_UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
-#define REG_UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
-#define REG_UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
-#define REG_UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
-#define REG_UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
-#define REG_UART1_TXCNT                 0xFFC02434         /* UART1 Transmit Counter Register */
-#define REG_UART1_RXCNT                 0xFFC02438         /* UART1 Receive Counter Register */
-
-/* =========================
-        UART
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_REVID_MAJOR                 4                               /* Major Version */
-#define BITP_UART_REVID_REV                   0                               /* Incremental Version */
-#define BITM_UART_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version */
-#define BITM_UART_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CTL_RFRT                   30                               /* Receive FIFO RTS Threshold */
-#define BITP_UART_CTL_RFIT                   29                               /* Receive FIFO IRQ Threshold */
-#define BITP_UART_CTL_ACTS                   28                               /* Automatic CTS */
-#define BITP_UART_CTL_ARTS                   27                               /* Automatic RTS */
-#define BITP_UART_CTL_XOFF                   26                               /* Transmitter off */
-#define BITP_UART_CTL_MRTS                   25                               /* Manual Request to Send */
-#define BITP_UART_CTL_TPOLC                  24                               /* IrDA TX Polarity Change */
-#define BITP_UART_CTL_RPOLC                  23                               /* IrDA RX Polarity Change */
-#define BITP_UART_CTL_FCPOL                  22                               /* Flow Control Pin Polarity */
-#define BITP_UART_CTL_SB                     19                               /* Set Break */
-#define BITP_UART_CTL_FFE                    18                               /* Force Framing Error on Transmit */
-#define BITP_UART_CTL_FPE                    17                               /* Force Parity Error on Transmit */
-#define BITP_UART_CTL_STP                    16                               /* Sticky Parity */
-#define BITP_UART_CTL_EPS                    15                               /* Even Parity Select */
-#define BITP_UART_CTL_PEN                    14                               /* Parity Enable */
-#define BITP_UART_CTL_STBH                   13                               /* Stop Bits (Half Bit Time) */
-#define BITP_UART_CTL_STB                    12                               /* Stop Bits */
-#define BITP_UART_CTL_WLS                     8                               /* Word Length Select */
-#define BITP_UART_CTL_MOD                     4                               /* Mode of Operation */
-#define BITP_UART_CTL_LOOP_EN                 1                               /* Loopback Enable */
-#define BITP_UART_CTL_EN                      0                               /* Enable UART */
-
-#define BITM_UART_CTL_RFRT                   (_ADI_MSK(0x40000000,uint32_t))  /* Receive FIFO RTS Threshold */
-#define ENUM_UART_CTL_RX_RTS_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 4; assert if <= 4 */
-#define ENUM_UART_CTL_RX_RTS_TH7             (_ADI_MSK(0x40000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 7; assert if <= 7 */
-
-#define BITM_UART_CTL_RFIT                   (_ADI_MSK(0x20000000,uint32_t))  /* Receive FIFO IRQ Threshold */
-#define ENUM_UART_CTL_RX_IRQ_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 4 */
-#define ENUM_UART_CTL_RX_IRQ_TH7             (_ADI_MSK(0x20000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 7 */
-
-#define BITM_UART_CTL_ACTS                   (_ADI_MSK(0x10000000,uint32_t))  /* Automatic CTS */
-#define ENUM_UART_CTL_CTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ACTS: Disable TX handshaking protocol */
-#define ENUM_UART_CTL_CTS_AUTO               (_ADI_MSK(0x10000000,uint32_t))  /* ACTS: Enable TX handshaking protocol */
-
-#define BITM_UART_CTL_ARTS                   (_ADI_MSK(0x08000000,uint32_t))  /* Automatic RTS */
-#define ENUM_UART_CTL_RTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ARTS: Disable RX handshaking protocol. */
-#define ENUM_UART_CTL_RTS_AUTO               (_ADI_MSK(0x08000000,uint32_t))  /* ARTS: Enable RX handshaking protocol. */
-
-#define BITM_UART_CTL_XOFF                   (_ADI_MSK(0x04000000,uint32_t))  /* Transmitter off */
-#define ENUM_UART_CTL_TX_ON                  (_ADI_MSK(0x00000000,uint32_t))  /* XOFF: Transmission ON, if ACTS=0 */
-#define ENUM_UART_CTL_TX_OFF                 (_ADI_MSK(0x04000000,uint32_t))  /* XOFF: Transmission OFF, if ACTS=0 */
-
-#define BITM_UART_CTL_MRTS                   (_ADI_MSK(0x02000000,uint32_t))  /* Manual Request to Send */
-#define ENUM_UART_CTL_RTS_DEASSERT           (_ADI_MSK(0x00000000,uint32_t))  /* MRTS: De-assert RTS pin when ARTS=0 */
-#define ENUM_UART_CTL_RTS_ASSERT             (_ADI_MSK(0x02000000,uint32_t))  /* MRTS: Assert RTS pin  when ARTS=0 */
-
-#define BITM_UART_CTL_TPOLC                  (_ADI_MSK(0x01000000,uint32_t))  /* IrDA TX Polarity Change */
-#define ENUM_UART_CTL_TPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* TPOLC: Active-low TX polarity setting */
-#define ENUM_UART_CTL_TPOLC_HI               (_ADI_MSK(0x01000000,uint32_t))  /* TPOLC: Active-high TX polarity setting */
-
-#define BITM_UART_CTL_RPOLC                  (_ADI_MSK(0x00800000,uint32_t))  /* IrDA RX Polarity Change */
-#define ENUM_UART_CTL_RPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RPOLC: Active-low RX polarity setting */
-#define ENUM_UART_CTL_RPOLC_HI               (_ADI_MSK(0x00800000,uint32_t))  /* RPOLC: Active-high RX polarity setting */
-
-#define BITM_UART_CTL_FCPOL                  (_ADI_MSK(0x00400000,uint32_t))  /* Flow Control Pin Polarity */
-#define ENUM_UART_CTL_FCPOL_LO               (_ADI_MSK(0x00000000,uint32_t))  /* FCPOL: Active low CTS/RTS */
-#define ENUM_UART_CTL_FCPOL_HI               (_ADI_MSK(0x00400000,uint32_t))  /* FCPOL: Active high CTS/RTS */
-
-#define BITM_UART_CTL_SB                     (_ADI_MSK(0x00080000,uint32_t))  /* Set Break */
-#define ENUM_UART_CTL_NORM_BREAK             (_ADI_MSK(0x00000000,uint32_t))  /* SB: No force */
-#define ENUM_UART_CTL_FORCE_BREAK            (_ADI_MSK(0x00080000,uint32_t))  /* SB: Force TX pin to 0 */
-
-#define BITM_UART_CTL_FFE                    (_ADI_MSK(0x00040000,uint32_t))  /* Force Framing Error on Transmit */
-#define ENUM_UART_CTL_NORM_FRM_ERR           (_ADI_MSK(0x00000000,uint32_t))  /* FFE: Normal operation */
-#define ENUM_UART_CTL_FORCE_FRM_ERR          (_ADI_MSK(0x00040000,uint32_t))  /* FFE: Force error */
-
-#define BITM_UART_CTL_FPE                    (_ADI_MSK(0x00020000,uint32_t))  /* Force Parity Error on Transmit */
-#define ENUM_UART_CTL_NORM_PARITY_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FPE: Normal operation */
-#define ENUM_UART_CTL_FORCE_PARITY_ERR       (_ADI_MSK(0x00020000,uint32_t))  /* FPE: Force parity error */
-
-#define BITM_UART_CTL_STP                    (_ADI_MSK(0x00010000,uint32_t))  /* Sticky Parity */
-#define ENUM_UART_CTL_NORM_PARITY            (_ADI_MSK(0x00000000,uint32_t))  /* STP: No Forced Parity */
-#define ENUM_UART_CTL_STICKY_PARITY          (_ADI_MSK(0x00010000,uint32_t))  /* STP: Force (Stick) Parity to Defined Value (if PEN=1) */
-
-#define BITM_UART_CTL_EPS                    (_ADI_MSK(0x00008000,uint32_t))  /* Even Parity Select */
-#define ENUM_UART_CTL_ODD_PARITY             (_ADI_MSK(0x00000000,uint32_t))  /* EPS: Odd parity */
-#define ENUM_UART_CTL_EVEN_PARITY            (_ADI_MSK(0x00008000,uint32_t))  /* EPS: Even parity */
-
-#define BITM_UART_CTL_PEN                    (_ADI_MSK(0x00004000,uint32_t))  /* Parity Enable */
-#define ENUM_UART_CTL_PARITY_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* PEN: Disable */
-#define ENUM_UART_CTL_PARITY_EN              (_ADI_MSK(0x00004000,uint32_t))  /* PEN: Enable parity transmit and check */
-
-#define BITM_UART_CTL_STBH                   (_ADI_MSK(0x00002000,uint32_t))  /* Stop Bits (Half Bit Time) */
-#define ENUM_UART_CTL_NO_EXTRA_STBH          (_ADI_MSK(0x00000000,uint32_t))  /* STBH: 0 half-bit-time stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STBH           (_ADI_MSK(0x00002000,uint32_t))  /* STBH: 1 half-bit-time stop bit */
-
-#define BITM_UART_CTL_STB                    (_ADI_MSK(0x00001000,uint32_t))  /* Stop Bits */
-#define ENUM_UART_CTL_NO_EXTRA_STB           (_ADI_MSK(0x00000000,uint32_t))  /* STB: 1 stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STB            (_ADI_MSK(0x00001000,uint32_t))  /* STB: 2 stop bits */
-
-#define BITM_UART_CTL_WLS                    (_ADI_MSK(0x00000300,uint32_t))  /* Word Length Select */
-#define ENUM_UART_CTL_WL5BITS                (_ADI_MSK(0x00000000,uint32_t))  /* WLS: 5-bit Word */
-#define ENUM_UART_CTL_WL6BITS                (_ADI_MSK(0x00000100,uint32_t))  /* WLS: 6-bit Word */
-#define ENUM_UART_CTL_WL7BITS                (_ADI_MSK(0x00000200,uint32_t))  /* WLS: 7-bit Word */
-#define ENUM_UART_CTL_WL8BITS                (_ADI_MSK(0x00000300,uint32_t))  /* WLS: 8-bit Word */
-
-#define BITM_UART_CTL_MOD                    (_ADI_MSK(0x00000030,uint32_t))  /* Mode of Operation */
-#define ENUM_UART_CTL_UART_MODE              (_ADI_MSK(0x00000000,uint32_t))  /* MOD: UART Mode */
-#define ENUM_UART_CTL_MDB_MODE               (_ADI_MSK(0x00000010,uint32_t))  /* MOD: MDB Mode */
-#define ENUM_UART_CTL_IRDA_MODE              (_ADI_MSK(0x00000020,uint32_t))  /* MOD: IrDA SIR Mode */
-
-#define BITM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* Loopback Enable */
-#define ENUM_UART_CTL_LOOP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* LOOP_EN: Disable */
-#define ENUM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* LOOP_EN: Enable */
-
-#define BITM_UART_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable UART */
-#define ENUM_UART_CTL_CLK_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_UART_CTL_CLK_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_STAT_RFCS                  17                               /* Receive FIFO Count Status */
-#define BITP_UART_STAT_CTS                   16                               /* Clear to Send */
-#define BITP_UART_STAT_SCTS                  12                               /* Sticky CTS */
-#define BITP_UART_STAT_RO                    11                               /* Reception On-going */
-#define BITP_UART_STAT_ADDR                  10                               /* Address Bit Status */
-#define BITP_UART_STAT_ASTKY                  9                               /* Address Sticky */
-#define BITP_UART_STAT_TFI                    8                               /* Transmission Finished Indicator */
-#define BITP_UART_STAT_TEMT                   7                               /* TSR and THR Empty */
-#define BITP_UART_STAT_THRE                   5                               /* Transmit Hold Register Empty */
-#define BITP_UART_STAT_BI                     4                               /* Break Indicator */
-#define BITP_UART_STAT_FE                     3                               /* Framing Error */
-#define BITP_UART_STAT_PE                     2                               /* Parity Error */
-#define BITP_UART_STAT_OE                     1                               /* Overrun Error */
-#define BITP_UART_STAT_DR                     0                               /* Data Ready */
-
-#define BITM_UART_STAT_RFCS                  (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Count Status */
-#define ENUM_UART_STAT_RFCS_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RFCS: RX FIFO has less than 4 (7) entries when RFIT=0 (1) */
-#define ENUM_UART_STAT_RFCS_HI               (_ADI_MSK(0x00020000,uint32_t))  /* RFCS: RX FIFO has at least 4 (7) entries when RFIT=0 (1) */
-
-#define BITM_UART_STAT_CTS                   (_ADI_MSK(0x00010000,uint32_t))  /* Clear to Send */
-#define ENUM_UART_STAT_CTS_LO                (_ADI_MSK(0x00000000,uint32_t))  /* CTS: Not clear to send (External device not ready to receive) */
-#define ENUM_UART_STAT_CTS_HI                (_ADI_MSK(0x00010000,uint32_t))  /* CTS: Clear to send (External device ready to receive) */
-
-#define BITM_UART_STAT_SCTS                  (_ADI_MSK(0x00001000,uint32_t))  /* Sticky CTS */
-#define ENUM_UART_STAT_CTS_LO_STKY           (_ADI_MSK(0x00000000,uint32_t))  /* SCTS: CTS has not transitioned from low to high */
-#define ENUM_UART_STAT_CTS_HI_STKY           (_ADI_MSK(0x00001000,uint32_t))  /* SCTS: CTS has transitioned from low to high */
-
-#define BITM_UART_STAT_RO                    (_ADI_MSK(0x00000800,uint32_t))  /* Reception On-going */
-#define ENUM_UART_STAT_NO_RX_PROGRESS        (_ADI_MSK(0x00000000,uint32_t))  /* RO: No data reception in progress */
-#define ENUM_UART_STAT_RX_PROGRESS           (_ADI_MSK(0x00000800,uint32_t))  /* RO: Data reception in progress */
-
-#define BITM_UART_STAT_ADDR                  (_ADI_MSK(0x00000400,uint32_t))  /* Address Bit Status */
-#define ENUM_UART_STAT_ADDR_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ADDR: Address bit is low */
-#define ENUM_UART_STAT_ADDR_HI               (_ADI_MSK(0x00000400,uint32_t))  /* ADDR: Address bit is high */
-
-#define BITM_UART_STAT_ASTKY                 (_ADI_MSK(0x00000200,uint32_t))  /* Address Sticky */
-#define ENUM_UART_STAT_ADDR_LO_STKY          (_ADI_MSK(0x00000000,uint32_t))  /* ASTKY: ADDR bit has not been set */
-#define ENUM_UART_STAT_ADDR_HI_STKY          (_ADI_MSK(0x00000200,uint32_t))  /* ASTKY: ADDR bit has been set */
-
-#define BITM_UART_STAT_TFI                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmission Finished Indicator */
-#define ENUM_UART_STAT_TX_NOT_DONE           (_ADI_MSK(0x00000000,uint32_t))  /* TFI: TEMT did not transition from 0 to 1 */
-#define ENUM_UART_STAT_TX_DONE               (_ADI_MSK(0x00000100,uint32_t))  /* TFI: TEMT transition from 0 to 1 */
-
-#define BITM_UART_STAT_TEMT                  (_ADI_MSK(0x00000080,uint32_t))  /* TSR and THR Empty */
-#define ENUM_UART_STAT_TX_NOT_EMPTY          (_ADI_MSK(0x00000000,uint32_t))  /* TEMT: Not empty TSR/THR */
-#define ENUM_UART_STAT_TX_EMPTY              (_ADI_MSK(0x00000080,uint32_t))  /* TEMT: TSR/THR Empty */
-
-#define BITM_UART_STAT_THRE                  (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Hold Register Empty */
-#define ENUM_UART_STAT_THR_NOT_EMPTY         (_ADI_MSK(0x00000000,uint32_t))  /* THRE: Not empty THR/TAIP */
-#define ENUM_UART_STAT_THR_EMPTY             (_ADI_MSK(0x00000020,uint32_t))  /* THRE: Empty THR/TAIP */
-
-#define BITM_UART_STAT_BI                    (_ADI_MSK(0x00000010,uint32_t))  /* Break Indicator */
-#define ENUM_UART_STAT_NO_BREAK_INT          (_ADI_MSK(0x00000000,uint32_t))  /* BI: No break interrupt */
-#define ENUM_UART_STAT_BREAK_INT             (_ADI_MSK(0x00000010,uint32_t))  /* BI: Break interrupt */
-
-#define BITM_UART_STAT_FE                    (_ADI_MSK(0x00000008,uint32_t))  /* Framing Error */
-#define ENUM_UART_STAT_NO_FRAMING_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FE: No error */
-#define ENUM_UART_STAT_FRAMING_ERR           (_ADI_MSK(0x00000008,uint32_t))  /* FE: Invalid stop bit error */
-
-#define BITM_UART_STAT_PE                    (_ADI_MSK(0x00000004,uint32_t))  /* Parity Error */
-#define ENUM_UART_STAT_NO_PARITY_ERR         (_ADI_MSK(0x00000000,uint32_t))  /* PE: No parity error */
-#define ENUM_UART_STAT_PARITY_ERR            (_ADI_MSK(0x00000004,uint32_t))  /* PE: Parity error */
-
-#define BITM_UART_STAT_OE                    (_ADI_MSK(0x00000002,uint32_t))  /* Overrun Error */
-#define ENUM_UART_STAT_NO_OVR_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* OE: No overrun */
-#define ENUM_UART_STAT_OVR_ERR               (_ADI_MSK(0x00000002,uint32_t))  /* OE: Overrun error */
-
-#define BITM_UART_STAT_DR                    (_ADI_MSK(0x00000001,uint32_t))  /* Data Ready */
-#define ENUM_UART_STAT_NO_DATA               (_ADI_MSK(0x00000000,uint32_t))  /* DR: No new data */
-#define ENUM_UART_STAT_NEW_DATA              (_ADI_MSK(0x00000001,uint32_t))  /* DR: New data in RBR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_SCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_SCR_VALUE                   0                               /* Stored 8-bit Data */
-#define BITM_UART_SCR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Stored 8-bit Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CLK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CLK_EDBO                   31                               /* Enable Divide By One */
-#define BITP_UART_CLK_DIV                     0                               /* Divisor */
-
-#define BITM_UART_CLK_EDBO                   (_ADI_MSK(0x80000000,uint32_t))  /* Enable Divide By One */
-#define ENUM_UART_CLK_DIS_DIV_BY_ONE         (_ADI_MSK(0x00000000,uint32_t))  /* EDBO: Bit clock prescaler = 16 */
-#define ENUM_UART_CLK_EN_DIV_BY_ONE          (_ADI_MSK(0x80000000,uint32_t))  /* EDBO: Bit clock prescaler = 1 */
-#define BITM_UART_CLK_DIV                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_ETXS                   9                               /* Enable TX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ERXS                   8                               /* Enable RX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_EAWI                   7                               /* Enable Address Word Interrupt Mask Status */
-#define BITP_UART_IMSK_ERFCI                  6                               /* Enable Receive FIFO Count Interrupt Mask Status */
-#define BITP_UART_IMSK_ETFI                   5                               /* Enable Transmission Finished Interrupt Mask Status */
-#define BITP_UART_IMSK_EDTPTI                 4                               /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define BITP_UART_IMSK_EDSSI                  3                               /* Enable Modem Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ELSI                   2                               /* Enable Line Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ETBEI                  1                               /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define BITP_UART_IMSK_ERBFI                  0                               /* Enable Receive Buffer Full Interrupt Mask Status */
-
-#define BITM_UART_IMSK_ETXS                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Status */
-#define ENUM_UART_ETXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETXS: Interrupt is masked */
-#define ENUM_UART_ETXS_HI                    (_ADI_MSK(0x00000200,uint32_t))  /* ETXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERXS                  (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Status */
-#define ENUM_UART_ERXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ERXS: Interrupt is masked */
-#define ENUM_UART_ERXS_HI                    (_ADI_MSK(0x00000100,uint32_t))  /* ERXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EAWI                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Status */
-#define ENUM_UART_EAWI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* EAWI: Interrupt is masked */
-#define ENUM_UART_EAWI_HI                    (_ADI_MSK(0x00000080,uint32_t))  /* EAWI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERFCI                 (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Status */
-#define ENUM_UART_ERFCI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERFCI: Interrupt is masked */
-#define ENUM_UART_ERFCI_HI                   (_ADI_MSK(0x00000040,uint32_t))  /* ERFCI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETFI                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Status */
-#define ENUM_UART_ETFI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETFI: Interrupt is masked */
-#define ENUM_UART_ETFI_HI                    (_ADI_MSK(0x00000020,uint32_t))  /* ETFI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDTPTI                (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define ENUM_UART_EDTPTI_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* EDTPTI: Interrupt is masked */
-#define ENUM_UART_EDTPTI_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* EDTPTI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDSSI                 (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Status */
-#define ENUM_UART_EDSSI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* EDSSI: Interrupt is masked */
-#define ENUM_UART_EDSSI_HI                   (_ADI_MSK(0x00000008,uint32_t))  /* EDSSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ELSI                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Status */
-#define ENUM_UART_ELSI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ELSI: Interrupt is masked */
-#define ENUM_UART_ELSI_HI                    (_ADI_MSK(0x00000004,uint32_t))  /* ELSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETBEI                 (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define ENUM_UART_ETBEI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ETBEI: Interrupt is masked */
-#define ENUM_UART_ETBEI_HI                   (_ADI_MSK(0x00000002,uint32_t))  /* ETBEI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERBFI                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Status */
-#define ENUM_UART_ERBFI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERBFI: Interrupt is masked */
-#define ENUM_UART_ERBFI_HI                   (_ADI_MSK(0x00000001,uint32_t))  /* ERBFI: Interrupt is unmasked */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_SET_ETXS               9                               /* Enable TX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERXS               8                               /* Enable RX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EAWI               7                               /* Enable Address Word Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDSSI              3                               /* Enable Modem Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ELSI               2                               /* Enable Line Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* The fields and enumerations for UART_IMSK_SET are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_SET_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_CLR_ETXS               9                               /* Enable TX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERXS               8                               /* Enable RX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EAWI               7                               /* Enable Address Word Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDSSI              3                               /* Enable Modem Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ELSI               2                               /* Enable Line Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* The fields and enumerations for UART_IMSK_CLR are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_CLR_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RBR_VALUE                   0                               /* 8-bit data */
-#define BITM_UART_RBR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_THR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_THR_VALUE                   0                               /* 8 bit data */
-#define BITM_UART_THR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8 bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TAIP                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TAIP_VALUE                  0                               /* 8-bit data */
-#define BITM_UART_TAIP_VALUE                 (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TSR_VALUE                   0                               /* Contents of TSR */
-#define BITM_UART_TSR_VALUE                  (_ADI_MSK(0x000007FF,uint32_t))  /* Contents of TSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RSR_VALUE                   0                               /* Contents of RSR */
-#define BITM_UART_RSR_VALUE                  (_ADI_MSK(0x000003FF,uint32_t))  /* Contents of RSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_TXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_RXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ==================================================
-        General Purpose Input/Output Registers
-   ================================================== */
-
-/* =========================
-        PORTA
-   ========================= */
-#define REG_PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
-#define REG_PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
-#define REG_PORTA_FER_CLR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
-#define REG_PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
-#define REG_PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
-#define REG_PORTA_DATA_CLR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
-#define REG_PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
-#define REG_PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
-#define REG_PORTA_DIR_CLR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
-#define REG_PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
-#define REG_PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
-#define REG_PORTA_INEN_CLR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
-#define REG_PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
-#define REG_PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
-#define REG_PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Polarity Invert Register */
-#define REG_PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Polarity Invert Set Register */
-#define REG_PORTA_POL_CLR               0xFFC03040         /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
-#define REG_PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
-
-/* =========================
-        PORTB
-   ========================= */
-#define REG_PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
-#define REG_PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
-#define REG_PORTB_FER_CLR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
-#define REG_PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
-#define REG_PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
-#define REG_PORTB_DATA_CLR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
-#define REG_PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
-#define REG_PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
-#define REG_PORTB_DIR_CLR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
-#define REG_PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
-#define REG_PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
-#define REG_PORTB_INEN_CLR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
-#define REG_PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
-#define REG_PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
-#define REG_PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Polarity Invert Register */
-#define REG_PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Polarity Invert Set Register */
-#define REG_PORTB_POL_CLR               0xFFC030C0         /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
-#define REG_PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
-
-/* =========================
-        PORTC
-   ========================= */
-#define REG_PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
-#define REG_PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
-#define REG_PORTC_FER_CLR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
-#define REG_PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
-#define REG_PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
-#define REG_PORTC_DATA_CLR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
-#define REG_PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
-#define REG_PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
-#define REG_PORTC_DIR_CLR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
-#define REG_PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
-#define REG_PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
-#define REG_PORTC_INEN_CLR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
-#define REG_PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
-#define REG_PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
-#define REG_PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Polarity Invert Register */
-#define REG_PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Polarity Invert Set Register */
-#define REG_PORTC_POL_CLR               0xFFC03140         /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
-#define REG_PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
-
-/* =========================
-        PORTD
-   ========================= */
-#define REG_PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
-#define REG_PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
-#define REG_PORTD_FER_CLR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
-#define REG_PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
-#define REG_PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
-#define REG_PORTD_DATA_CLR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
-#define REG_PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
-#define REG_PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
-#define REG_PORTD_DIR_CLR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
-#define REG_PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
-#define REG_PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
-#define REG_PORTD_INEN_CLR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
-#define REG_PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
-#define REG_PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
-#define REG_PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Polarity Invert Register */
-#define REG_PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Polarity Invert Set Register */
-#define REG_PORTD_POL_CLR               0xFFC031C0         /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
-#define REG_PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
-
-/* =========================
-        PORTE
-   ========================= */
-#define REG_PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
-#define REG_PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
-#define REG_PORTE_FER_CLR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
-#define REG_PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
-#define REG_PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
-#define REG_PORTE_DATA_CLR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
-#define REG_PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
-#define REG_PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
-#define REG_PORTE_DIR_CLR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
-#define REG_PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
-#define REG_PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
-#define REG_PORTE_INEN_CLR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
-#define REG_PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
-#define REG_PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
-#define REG_PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Polarity Invert Register */
-#define REG_PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Polarity Invert Set Register */
-#define REG_PORTE_POL_CLR               0xFFC03240         /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
-#define REG_PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
-
-/* =========================
-        PORTF
-   ========================= */
-#define REG_PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
-#define REG_PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
-#define REG_PORTF_FER_CLR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
-#define REG_PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
-#define REG_PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
-#define REG_PORTF_DATA_CLR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
-#define REG_PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
-#define REG_PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
-#define REG_PORTF_DIR_CLR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
-#define REG_PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
-#define REG_PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
-#define REG_PORTF_INEN_CLR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
-#define REG_PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
-#define REG_PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
-#define REG_PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Polarity Invert Register */
-#define REG_PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Polarity Invert Set Register */
-#define REG_PORTF_POL_CLR               0xFFC032C0         /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
-#define REG_PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
-
-/* =========================
-        PORTG
-   ========================= */
-#define REG_PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
-#define REG_PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
-#define REG_PORTG_FER_CLR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
-#define REG_PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
-#define REG_PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
-#define REG_PORTG_DATA_CLR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
-#define REG_PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
-#define REG_PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
-#define REG_PORTG_DIR_CLR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
-#define REG_PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
-#define REG_PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
-#define REG_PORTG_INEN_CLR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
-#define REG_PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
-#define REG_PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
-#define REG_PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Polarity Invert Register */
-#define REG_PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Polarity Invert Set Register */
-#define REG_PORTG_POL_CLR               0xFFC03340         /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
-#define REG_PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
-
-/* =========================
-        PORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_PX15                   15                               /* Port x Bit 15 Mode */
-#define BITP_PORT_FER_PX14                   14                               /* Port x Bit 14 Mode */
-#define BITP_PORT_FER_PX13                   13                               /* Port x Bit 13 Mode */
-#define BITP_PORT_FER_PX12                   12                               /* Port x Bit 12 Mode */
-#define BITP_PORT_FER_PX11                   11                               /* Port x Bit 11 Mode */
-#define BITP_PORT_FER_PX10                   10                               /* Port x Bit 10 Mode */
-#define BITP_PORT_FER_PX9                     9                               /* Port x Bit 9 Mode */
-#define BITP_PORT_FER_PX8                     8                               /* Port x Bit 8 Mode */
-#define BITP_PORT_FER_PX7                     7                               /* Port x Bit 7 Mode */
-#define BITP_PORT_FER_PX6                     6                               /* Port x Bit 6 Mode */
-#define BITP_PORT_FER_PX5                     5                               /* Port x Bit 5 Mode */
-#define BITP_PORT_FER_PX4                     4                               /* Port x Bit 4 Mode */
-#define BITP_PORT_FER_PX3                     3                               /* Port x Bit 3 Mode */
-#define BITP_PORT_FER_PX2                     2                               /* Port x Bit 2 Mode */
-#define BITP_PORT_FER_PX1                     1                               /* Port x Bit 1 Mode */
-#define BITP_PORT_FER_PX0                     0                               /* Port x Bit 0 Mode */
-#define BITM_PORT_FER_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode */
-#define BITM_PORT_FER_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode */
-#define BITM_PORT_FER_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode */
-#define BITM_PORT_FER_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode */
-#define BITM_PORT_FER_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode */
-#define BITM_PORT_FER_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode */
-#define BITM_PORT_FER_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode */
-#define BITM_PORT_FER_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode */
-#define BITM_PORT_FER_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode */
-#define BITM_PORT_FER_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode */
-#define BITM_PORT_FER_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode */
-#define BITM_PORT_FER_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode */
-#define BITM_PORT_FER_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode */
-#define BITM_PORT_FER_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode */
-#define BITM_PORT_FER_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode */
-#define BITM_PORT_FER_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_SET_PX15               15                               /* Port x Bit 15 Mode Set */
-#define BITP_PORT_FER_SET_PX14               14                               /* Port x Bit 14 Mode Set */
-#define BITP_PORT_FER_SET_PX13               13                               /* Port x Bit 13 Mode Set */
-#define BITP_PORT_FER_SET_PX12               12                               /* Port x Bit 12 Mode Set */
-#define BITP_PORT_FER_SET_PX11               11                               /* Port x Bit 11 Mode Set */
-#define BITP_PORT_FER_SET_PX10               10                               /* Port x Bit 10 Mode Set */
-#define BITP_PORT_FER_SET_PX9                 9                               /* Port x Bit 9 Mode Set */
-#define BITP_PORT_FER_SET_PX8                 8                               /* Port x Bit 8 Mode Set */
-#define BITP_PORT_FER_SET_PX7                 7                               /* Port x Bit 7 Mode Set */
-#define BITP_PORT_FER_SET_PX6                 6                               /* Port x Bit 6 Mode Set */
-#define BITP_PORT_FER_SET_PX5                 5                               /* Port x Bit 5 Mode Set */
-#define BITP_PORT_FER_SET_PX4                 4                               /* Port x Bit 4 Mode Set */
-#define BITP_PORT_FER_SET_PX3                 3                               /* Port x Bit 3 Mode Set */
-#define BITP_PORT_FER_SET_PX2                 2                               /* Port x Bit 2 Mode Set */
-#define BITP_PORT_FER_SET_PX1                 1                               /* Port x Bit 1 Mode Set */
-#define BITP_PORT_FER_SET_PX0                 0                               /* Port x Bit 0 Mode Set */
-#define BITM_PORT_FER_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Set */
-#define BITM_PORT_FER_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Set */
-#define BITM_PORT_FER_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Set */
-#define BITM_PORT_FER_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Set */
-#define BITM_PORT_FER_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Set */
-#define BITM_PORT_FER_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Set */
-#define BITM_PORT_FER_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Set */
-#define BITM_PORT_FER_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Set */
-#define BITM_PORT_FER_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Set */
-#define BITM_PORT_FER_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Set */
-#define BITM_PORT_FER_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Set */
-#define BITM_PORT_FER_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Set */
-#define BITM_PORT_FER_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Set */
-#define BITM_PORT_FER_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Set */
-#define BITM_PORT_FER_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Set */
-#define BITM_PORT_FER_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_CLR_PX15               15                               /* Port x Bit 15 Mode Clear */
-#define BITP_PORT_FER_CLR_PX14               14                               /* Port x Bit 14 Mode Clear */
-#define BITP_PORT_FER_CLR_PX13               13                               /* Port x Bit 13 Mode Clear */
-#define BITP_PORT_FER_CLR_PX12               12                               /* Port x Bit 12 Mode Clear */
-#define BITP_PORT_FER_CLR_PX11               11                               /* Port x Bit 11 Mode Clear */
-#define BITP_PORT_FER_CLR_PX10               10                               /* Port x Bit 10 Mode Clear */
-#define BITP_PORT_FER_CLR_PX9                 9                               /* Port x Bit 9 Mode Clear */
-#define BITP_PORT_FER_CLR_PX8                 8                               /* Port x Bit 8 Mode Clear */
-#define BITP_PORT_FER_CLR_PX7                 7                               /* Port x Bit 7 Mode Clear */
-#define BITP_PORT_FER_CLR_PX6                 6                               /* Port x Bit 6 Mode Clear */
-#define BITP_PORT_FER_CLR_PX5                 5                               /* Port x Bit 5 Mode Clear */
-#define BITP_PORT_FER_CLR_PX4                 4                               /* Port x Bit 4 Mode Clear */
-#define BITP_PORT_FER_CLR_PX3                 3                               /* Port x Bit 3 Mode Clear */
-#define BITP_PORT_FER_CLR_PX2                 2                               /* Port x Bit 2 Mode Clear */
-#define BITP_PORT_FER_CLR_PX1                 1                               /* Port x Bit 1 Mode Clear */
-#define BITP_PORT_FER_CLR_PX0                 0                               /* Port x Bit 0 Mode Clear */
-#define BITM_PORT_FER_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Clear */
-#define BITM_PORT_FER_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Clear */
-#define BITM_PORT_FER_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Clear */
-#define BITM_PORT_FER_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Clear */
-#define BITM_PORT_FER_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Clear */
-#define BITM_PORT_FER_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Clear */
-#define BITM_PORT_FER_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Clear */
-#define BITM_PORT_FER_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Clear */
-#define BITM_PORT_FER_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Clear */
-#define BITM_PORT_FER_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Clear */
-#define BITM_PORT_FER_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Clear */
-#define BITM_PORT_FER_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Clear */
-#define BITM_PORT_FER_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Clear */
-#define BITM_PORT_FER_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Clear */
-#define BITM_PORT_FER_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Clear */
-#define BITM_PORT_FER_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_PX15                  15                               /* Port x Bit 15 Data */
-#define BITP_PORT_DATA_PX14                  14                               /* Port x Bit 14 Data */
-#define BITP_PORT_DATA_PX13                  13                               /* Port x Bit 13 Data */
-#define BITP_PORT_DATA_PX12                  12                               /* Port x Bit 12 Data */
-#define BITP_PORT_DATA_PX11                  11                               /* Port x Bit 11 Data */
-#define BITP_PORT_DATA_PX10                  10                               /* Port x Bit 10 Data */
-#define BITP_PORT_DATA_PX9                    9                               /* Port x Bit 9 Data */
-#define BITP_PORT_DATA_PX8                    8                               /* Port x Bit 8 Data */
-#define BITP_PORT_DATA_PX7                    7                               /* Port x Bit 7 Data */
-#define BITP_PORT_DATA_PX6                    6                               /* Port x Bit 6 Data */
-#define BITP_PORT_DATA_PX5                    5                               /* Port x Bit 5 Data */
-#define BITP_PORT_DATA_PX4                    4                               /* Port x Bit 4 Data */
-#define BITP_PORT_DATA_PX3                    3                               /* Port x Bit 3 Data */
-#define BITP_PORT_DATA_PX2                    2                               /* Port x Bit 2 Data */
-#define BITP_PORT_DATA_PX1                    1                               /* Port x Bit 1 Data */
-#define BITP_PORT_DATA_PX0                    0                               /* Port x Bit 0 Data */
-#define BITM_PORT_DATA_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data */
-#define BITM_PORT_DATA_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data */
-#define BITM_PORT_DATA_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data */
-#define BITM_PORT_DATA_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data */
-#define BITM_PORT_DATA_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data */
-#define BITM_PORT_DATA_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data */
-#define BITM_PORT_DATA_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data */
-#define BITM_PORT_DATA_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data */
-#define BITM_PORT_DATA_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data */
-#define BITM_PORT_DATA_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data */
-#define BITM_PORT_DATA_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data */
-#define BITM_PORT_DATA_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data */
-#define BITM_PORT_DATA_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data */
-#define BITM_PORT_DATA_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data */
-#define BITM_PORT_DATA_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data */
-#define BITM_PORT_DATA_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_SET_PX15              15                               /* Port x Bit 15 Data Set */
-#define BITP_PORT_DATA_SET_PX14              14                               /* Port x Bit 14 Data Set */
-#define BITP_PORT_DATA_SET_PX13              13                               /* Port x Bit 13 Data Set */
-#define BITP_PORT_DATA_SET_PX12              12                               /* Port x Bit 12 Data Set */
-#define BITP_PORT_DATA_SET_PX11              11                               /* Port x Bit 11 Data Set */
-#define BITP_PORT_DATA_SET_PX10              10                               /* Port x Bit 10 Data Set */
-#define BITP_PORT_DATA_SET_PX9                9                               /* Port x Bit 9 Data Set */
-#define BITP_PORT_DATA_SET_PX8                8                               /* Port x Bit 8 Data Set */
-#define BITP_PORT_DATA_SET_PX7                7                               /* Port x Bit 7 Data Set */
-#define BITP_PORT_DATA_SET_PX6                6                               /* Port x Bit 6 Data Set */
-#define BITP_PORT_DATA_SET_PX5                5                               /* Port x Bit 5 Data Set */
-#define BITP_PORT_DATA_SET_PX4                4                               /* Port x Bit 4 Data Set */
-#define BITP_PORT_DATA_SET_PX3                3                               /* Port x Bit 3 Data Set */
-#define BITP_PORT_DATA_SET_PX2                2                               /* Port x Bit 2 Data Set */
-#define BITP_PORT_DATA_SET_PX1                1                               /* Port x Bit 1 Data Set */
-#define BITP_PORT_DATA_SET_PX0                0                               /* Port x Bit 0 Data Set */
-#define BITM_PORT_DATA_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Set */
-#define BITM_PORT_DATA_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Set */
-#define BITM_PORT_DATA_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Set */
-#define BITM_PORT_DATA_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Set */
-#define BITM_PORT_DATA_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Set */
-#define BITM_PORT_DATA_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Set */
-#define BITM_PORT_DATA_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Set */
-#define BITM_PORT_DATA_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Set */
-#define BITM_PORT_DATA_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Set */
-#define BITM_PORT_DATA_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Set */
-#define BITM_PORT_DATA_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Set */
-#define BITM_PORT_DATA_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Set */
-#define BITM_PORT_DATA_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Set */
-#define BITM_PORT_DATA_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Set */
-#define BITM_PORT_DATA_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Set */
-#define BITM_PORT_DATA_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_CLR_PX15              15                               /* Port x Bit 15 Data Clear */
-#define BITP_PORT_DATA_CLR_PX14              14                               /* Port x Bit 14 Data Clear */
-#define BITP_PORT_DATA_CLR_PX13              13                               /* Port x Bit 13 Data Clear */
-#define BITP_PORT_DATA_CLR_PX12              12                               /* Port x Bit 12 Data Clear */
-#define BITP_PORT_DATA_CLR_PX11              11                               /* Port x Bit 11 Data Clear */
-#define BITP_PORT_DATA_CLR_PX10              10                               /* Port x Bit 10 Data Clear */
-#define BITP_PORT_DATA_CLR_PX9                9                               /* Port x Bit 9 Data Clear */
-#define BITP_PORT_DATA_CLR_PX8                8                               /* Port x Bit 8 Data Clear */
-#define BITP_PORT_DATA_CLR_PX7                7                               /* Port x Bit 7 Data Clear */
-#define BITP_PORT_DATA_CLR_PX6                6                               /* Port x Bit 6 Data Clear */
-#define BITP_PORT_DATA_CLR_PX5                5                               /* Port x Bit 5 Data Clear */
-#define BITP_PORT_DATA_CLR_PX4                4                               /* Port x Bit 4 Data Clear */
-#define BITP_PORT_DATA_CLR_PX3                3                               /* Port x Bit 3 Data Clear */
-#define BITP_PORT_DATA_CLR_PX2                2                               /* Port x Bit 2 Data Clear */
-#define BITP_PORT_DATA_CLR_PX1                1                               /* Port x Bit 1 Data Clear */
-#define BITP_PORT_DATA_CLR_PX0                0                               /* Port x Bit 0 Data Clear */
-#define BITM_PORT_DATA_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Clear */
-#define BITM_PORT_DATA_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Clear */
-#define BITM_PORT_DATA_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Clear */
-#define BITM_PORT_DATA_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Clear */
-#define BITM_PORT_DATA_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Clear */
-#define BITM_PORT_DATA_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Clear */
-#define BITM_PORT_DATA_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Clear */
-#define BITM_PORT_DATA_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Clear */
-#define BITM_PORT_DATA_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Clear */
-#define BITM_PORT_DATA_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Clear */
-#define BITM_PORT_DATA_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Clear */
-#define BITM_PORT_DATA_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Clear */
-#define BITM_PORT_DATA_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Clear */
-#define BITM_PORT_DATA_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Clear */
-#define BITM_PORT_DATA_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Clear */
-#define BITM_PORT_DATA_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_PX15                   15                               /* Port x Bit 15 Direction */
-#define BITP_PORT_DIR_PX14                   14                               /* Port x Bit 14 Direction */
-#define BITP_PORT_DIR_PX13                   13                               /* Port x Bit 13 Direction */
-#define BITP_PORT_DIR_PX12                   12                               /* Port x Bit 12 Direction */
-#define BITP_PORT_DIR_PX11                   11                               /* Port x Bit 11 Direction */
-#define BITP_PORT_DIR_PX10                   10                               /* Port x Bit 10 Direction */
-#define BITP_PORT_DIR_PX9                     9                               /* Port x Bit 9 Direction */
-#define BITP_PORT_DIR_PX8                     8                               /* Port x Bit 8 Direction */
-#define BITP_PORT_DIR_PX7                     7                               /* Port x Bit 7 Direction */
-#define BITP_PORT_DIR_PX6                     6                               /* Port x Bit 6 Direction */
-#define BITP_PORT_DIR_PX5                     5                               /* Port x Bit 5 Direction */
-#define BITP_PORT_DIR_PX4                     4                               /* Port x Bit 4 Direction */
-#define BITP_PORT_DIR_PX3                     3                               /* Port x Bit 3 Direction */
-#define BITP_PORT_DIR_PX2                     2                               /* Port x Bit 2 Direction */
-#define BITP_PORT_DIR_PX1                     1                               /* Port x Bit 1 Direction */
-#define BITP_PORT_DIR_PX0                     0                               /* Port x Bit 0 Direction */
-#define BITM_PORT_DIR_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction */
-#define BITM_PORT_DIR_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction */
-#define BITM_PORT_DIR_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction */
-#define BITM_PORT_DIR_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction */
-#define BITM_PORT_DIR_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction */
-#define BITM_PORT_DIR_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction */
-#define BITM_PORT_DIR_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction */
-#define BITM_PORT_DIR_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction */
-#define BITM_PORT_DIR_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction */
-#define BITM_PORT_DIR_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction */
-#define BITM_PORT_DIR_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction */
-#define BITM_PORT_DIR_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction */
-#define BITM_PORT_DIR_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction */
-#define BITM_PORT_DIR_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction */
-#define BITM_PORT_DIR_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction */
-#define BITM_PORT_DIR_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_SET_PX15               15                               /* Port x Bit 15 Direction Set */
-#define BITP_PORT_DIR_SET_PX14               14                               /* Port x Bit 14 Direction Set */
-#define BITP_PORT_DIR_SET_PX13               13                               /* Port x Bit 13 Direction Set */
-#define BITP_PORT_DIR_SET_PX12               12                               /* Port x Bit 12 Direction Set */
-#define BITP_PORT_DIR_SET_PX11               11                               /* Port x Bit 11 Direction Set */
-#define BITP_PORT_DIR_SET_PX10               10                               /* Port x Bit 10 Direction Set */
-#define BITP_PORT_DIR_SET_PX9                 9                               /* Port x Bit 9 Direction Set */
-#define BITP_PORT_DIR_SET_PX8                 8                               /* Port x Bit 8 Direction Set */
-#define BITP_PORT_DIR_SET_PX7                 7                               /* Port x Bit 7 Direction Set */
-#define BITP_PORT_DIR_SET_PX6                 6                               /* Port x Bit 6 Direction Set */
-#define BITP_PORT_DIR_SET_PX5                 5                               /* Port x Bit 5 Direction Set */
-#define BITP_PORT_DIR_SET_PX4                 4                               /* Port x Bit 4 Direction Set */
-#define BITP_PORT_DIR_SET_PX3                 3                               /* Port x Bit 3 Direction Set */
-#define BITP_PORT_DIR_SET_PX2                 2                               /* Port x Bit 2 Direction Set */
-#define BITP_PORT_DIR_SET_PX1                 1                               /* Port x Bit 1 Direction Set */
-#define BITP_PORT_DIR_SET_PX0                 0                               /* Port x Bit 0 Direction Set */
-#define BITM_PORT_DIR_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Set */
-#define BITM_PORT_DIR_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Set */
-#define BITM_PORT_DIR_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Set */
-#define BITM_PORT_DIR_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Set */
-#define BITM_PORT_DIR_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Set */
-#define BITM_PORT_DIR_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Set */
-#define BITM_PORT_DIR_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Set */
-#define BITM_PORT_DIR_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Set */
-#define BITM_PORT_DIR_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Set */
-#define BITM_PORT_DIR_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Set */
-#define BITM_PORT_DIR_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Set */
-#define BITM_PORT_DIR_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Set */
-#define BITM_PORT_DIR_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Set */
-#define BITM_PORT_DIR_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Set */
-#define BITM_PORT_DIR_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Set */
-#define BITM_PORT_DIR_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_CLR_PX15               15                               /* Port x Bit 15 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX14               14                               /* Port x Bit 14 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX13               13                               /* Port x Bit 13 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX12               12                               /* Port x Bit 12 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX11               11                               /* Port x Bit 11 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX10               10                               /* Port x Bit 10 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX9                 9                               /* Port x Bit 9 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX8                 8                               /* Port x Bit 8 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX7                 7                               /* Port x Bit 7 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX6                 6                               /* Port x Bit 6 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX5                 5                               /* Port x Bit 5 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX4                 4                               /* Port x Bit 4 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX3                 3                               /* Port x Bit 3 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX2                 2                               /* Port x Bit 2 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX1                 1                               /* Port x Bit 1 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX0                 0                               /* Port x Bit 0 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_PX15                  15                               /* Port x Bit 15 Input Enable */
-#define BITP_PORT_INEN_PX14                  14                               /* Port x Bit 14 Input Enable */
-#define BITP_PORT_INEN_PX13                  13                               /* Port x Bit 13 Input Enable */
-#define BITP_PORT_INEN_PX12                  12                               /* Port x Bit 12 Input Enable */
-#define BITP_PORT_INEN_PX11                  11                               /* Port x Bit 11 Input Enable */
-#define BITP_PORT_INEN_PX10                  10                               /* Port x Bit 10 Input Enable */
-#define BITP_PORT_INEN_PX9                    9                               /* Port x Bit 9 Input Enable */
-#define BITP_PORT_INEN_PX8                    8                               /* Port x Bit 8 Input Enable */
-#define BITP_PORT_INEN_PX7                    7                               /* Port x Bit 7 Input Enable */
-#define BITP_PORT_INEN_PX6                    6                               /* Port x Bit 6 Input Enable */
-#define BITP_PORT_INEN_PX5                    5                               /* Port x Bit 5 Input Enable */
-#define BITP_PORT_INEN_PX4                    4                               /* Port x Bit 4 Input Enable */
-#define BITP_PORT_INEN_PX3                    3                               /* Port x Bit 3 Input Enable */
-#define BITP_PORT_INEN_PX2                    2                               /* Port x Bit 2 Input Enable */
-#define BITP_PORT_INEN_PX1                    1                               /* Port x Bit 1 Input Enable */
-#define BITP_PORT_INEN_PX0                    0                               /* Port x Bit 0 Input Enable */
-#define BITM_PORT_INEN_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable */
-#define BITM_PORT_INEN_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable */
-#define BITM_PORT_INEN_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable */
-#define BITM_PORT_INEN_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable */
-#define BITM_PORT_INEN_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable */
-#define BITM_PORT_INEN_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable */
-#define BITM_PORT_INEN_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable */
-#define BITM_PORT_INEN_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable */
-#define BITM_PORT_INEN_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable */
-#define BITM_PORT_INEN_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable */
-#define BITM_PORT_INEN_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable */
-#define BITM_PORT_INEN_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable */
-#define BITM_PORT_INEN_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable */
-#define BITM_PORT_INEN_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable */
-#define BITM_PORT_INEN_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable */
-#define BITM_PORT_INEN_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_SET_PX15              15                               /* Port x Bit 15 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX14              14                               /* Port x Bit 14 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX13              13                               /* Port x Bit 13 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX12              12                               /* Port x Bit 12 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX11              11                               /* Port x Bit 11 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX10              10                               /* Port x Bit 10 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX9                9                               /* Port x Bit 9 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX8                8                               /* Port x Bit 8 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX7                7                               /* Port x Bit 7 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX6                6                               /* Port x Bit 6 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX5                5                               /* Port x Bit 5 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX4                4                               /* Port x Bit 4 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX3                3                               /* Port x Bit 3 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX2                2                               /* Port x Bit 2 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX1                1                               /* Port x Bit 1 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX0                0                               /* Port x Bit 0 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_CLR_PX15              15                               /* Port x Bit 15 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX14              14                               /* Port x Bit 14 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX13              13                               /* Port x Bit 13 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX12              12                               /* Port x Bit 12 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX11              11                               /* Port x Bit 11 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX10              10                               /* Port x Bit 10 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX9                9                               /* Port x Bit 9 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX8                8                               /* Port x Bit 8 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX7                7                               /* Port x Bit 7 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX6                6                               /* Port x Bit 6 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX5                5                               /* Port x Bit 5 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX4                4                               /* Port x Bit 4 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX3                3                               /* Port x Bit 3 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX2                2                               /* Port x Bit 2 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX1                1                               /* Port x Bit 1 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX0                0                               /* Port x Bit 0 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_MUX                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_MUX_MUX15                  30                               /* Mux for Port x Bit 15 */
-#define BITP_PORT_MUX_MUX14                  28                               /* Mux for Port x Bit 14 */
-#define BITP_PORT_MUX_MUX13                  26                               /* Mux for Port x Bit 13 */
-#define BITP_PORT_MUX_MUX12                  24                               /* Mux for Port x Bit 12 */
-#define BITP_PORT_MUX_MUX11                  22                               /* Mux for Port x Bit 11 */
-#define BITP_PORT_MUX_MUX10                  20                               /* Mux for Port x Bit 10 */
-#define BITP_PORT_MUX_MUX9                   18                               /* Mux for Port x Bit 9 */
-#define BITP_PORT_MUX_MUX8                   16                               /* Mux for Port x Bit 8 */
-#define BITP_PORT_MUX_MUX7                   14                               /* Mux for Port x Bit 7 */
-#define BITP_PORT_MUX_MUX6                   12                               /* Mux for Port x Bit 6 */
-#define BITP_PORT_MUX_MUX5                   10                               /* Mux for Port x Bit 5 */
-#define BITP_PORT_MUX_MUX4                    8                               /* Mux for Port x Bit 4 */
-#define BITP_PORT_MUX_MUX3                    6                               /* Mux for Port x Bit 3 */
-#define BITP_PORT_MUX_MUX2                    4                               /* Mux for Port x Bit 2 */
-#define BITP_PORT_MUX_MUX1                    2                               /* Mux for Port x Bit 1 */
-#define BITP_PORT_MUX_MUX0                    0                               /* Mux for Port x Bit 0 */
-#define BITM_PORT_MUX_MUX15                  (_ADI_MSK(0xC0000000,uint32_t))  /* Mux for Port x Bit 15 */
-#define BITM_PORT_MUX_MUX14                  (_ADI_MSK(0x30000000,uint32_t))  /* Mux for Port x Bit 14 */
-#define BITM_PORT_MUX_MUX13                  (_ADI_MSK(0x0C000000,uint32_t))  /* Mux for Port x Bit 13 */
-#define BITM_PORT_MUX_MUX12                  (_ADI_MSK(0x03000000,uint32_t))  /* Mux for Port x Bit 12 */
-#define BITM_PORT_MUX_MUX11                  (_ADI_MSK(0x00C00000,uint32_t))  /* Mux for Port x Bit 11 */
-#define BITM_PORT_MUX_MUX10                  (_ADI_MSK(0x00300000,uint32_t))  /* Mux for Port x Bit 10 */
-#define BITM_PORT_MUX_MUX9                   (_ADI_MSK(0x000C0000,uint32_t))  /* Mux for Port x Bit 9 */
-#define BITM_PORT_MUX_MUX8                   (_ADI_MSK(0x00030000,uint32_t))  /* Mux for Port x Bit 8 */
-#define BITM_PORT_MUX_MUX7                   (_ADI_MSK(0x0000C000,uint32_t))  /* Mux for Port x Bit 7 */
-#define BITM_PORT_MUX_MUX6                   (_ADI_MSK(0x00003000,uint32_t))  /* Mux for Port x Bit 6 */
-#define BITM_PORT_MUX_MUX5                   (_ADI_MSK(0x00000C00,uint32_t))  /* Mux for Port x Bit 5 */
-#define BITM_PORT_MUX_MUX4                   (_ADI_MSK(0x00000300,uint32_t))  /* Mux for Port x Bit 4 */
-#define BITM_PORT_MUX_MUX3                   (_ADI_MSK(0x000000C0,uint32_t))  /* Mux for Port x Bit 3 */
-#define BITM_PORT_MUX_MUX2                   (_ADI_MSK(0x00000030,uint32_t))  /* Mux for Port x Bit 2 */
-#define BITM_PORT_MUX_MUX1                   (_ADI_MSK(0x0000000C,uint32_t))  /* Mux for Port x Bit 1 */
-#define BITM_PORT_MUX_MUX0                   (_ADI_MSK(0x00000003,uint32_t))  /* Mux for Port x Bit 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_TGL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_TGL_PX15              15                               /* Port x Bit 15 Toggle */
-#define BITP_PORT_DATA_TGL_PX14              14                               /* Port x Bit 14 Toggle */
-#define BITP_PORT_DATA_TGL_PX13              13                               /* Port x Bit 13 Toggle */
-#define BITP_PORT_DATA_TGL_PX12              12                               /* Port x Bit 12 Toggle */
-#define BITP_PORT_DATA_TGL_PX11              11                               /* Port x Bit 11 Toggle */
-#define BITP_PORT_DATA_TGL_PX10              10                               /* Port x Bit 10 Toggle */
-#define BITP_PORT_DATA_TGL_PX9                9                               /* Port x Bit 9 Toggle */
-#define BITP_PORT_DATA_TGL_PX8                8                               /* Port x Bit 8 Toggle */
-#define BITP_PORT_DATA_TGL_PX7                7                               /* Port x Bit 7 Toggle */
-#define BITP_PORT_DATA_TGL_PX6                6                               /* Port x Bit 6 Toggle */
-#define BITP_PORT_DATA_TGL_PX5                5                               /* Port x Bit 5 Toggle */
-#define BITP_PORT_DATA_TGL_PX4                4                               /* Port x Bit 4 Toggle */
-#define BITP_PORT_DATA_TGL_PX3                3                               /* Port x Bit 3 Toggle */
-#define BITP_PORT_DATA_TGL_PX2                2                               /* Port x Bit 2 Toggle */
-#define BITP_PORT_DATA_TGL_PX1                1                               /* Port x Bit 1 Toggle */
-#define BITP_PORT_DATA_TGL_PX0                0                               /* Port x Bit 0 Toggle */
-#define BITM_PORT_DATA_TGL_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Toggle */
-#define BITM_PORT_DATA_TGL_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Toggle */
-#define BITM_PORT_DATA_TGL_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Toggle */
-#define BITM_PORT_DATA_TGL_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Toggle */
-#define BITM_PORT_DATA_TGL_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Toggle */
-#define BITM_PORT_DATA_TGL_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Toggle */
-#define BITM_PORT_DATA_TGL_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Toggle */
-#define BITM_PORT_DATA_TGL_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Toggle */
-#define BITM_PORT_DATA_TGL_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Toggle */
-#define BITM_PORT_DATA_TGL_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Toggle */
-#define BITM_PORT_DATA_TGL_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Toggle */
-#define BITM_PORT_DATA_TGL_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Toggle */
-#define BITM_PORT_DATA_TGL_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Toggle */
-#define BITM_PORT_DATA_TGL_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Toggle */
-#define BITM_PORT_DATA_TGL_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Toggle */
-#define BITM_PORT_DATA_TGL_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Toggle */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_PX15                   15                               /* Port x Bit 15 Polarity Invert */
-#define BITP_PORT_POL_PX14                   14                               /* Port x Bit 14 Polarity Invert */
-#define BITP_PORT_POL_PX13                   13                               /* Port x Bit 13 Polarity Invert */
-#define BITP_PORT_POL_PX12                   12                               /* Port x Bit 12 Polarity Invert */
-#define BITP_PORT_POL_PX11                   11                               /* Port x Bit 11 Polarity Invert */
-#define BITP_PORT_POL_PX10                   10                               /* Port x Bit 10 Polarity Invert */
-#define BITP_PORT_POL_PX9                     9                               /* Port x Bit 9 Polarity Invert */
-#define BITP_PORT_POL_PX8                     8                               /* Port x Bit 8 Polarity Invert */
-#define BITP_PORT_POL_PX7                     7                               /* Port x Bit 7 Polarity Invert */
-#define BITP_PORT_POL_PX6                     6                               /* Port x Bit 6 Polarity Invert */
-#define BITP_PORT_POL_PX5                     5                               /* Port x Bit 5 Polarity Invert */
-#define BITP_PORT_POL_PX4                     4                               /* Port x Bit 4 Polarity Invert */
-#define BITP_PORT_POL_PX3                     3                               /* Port x Bit 3 Polarity Invert */
-#define BITP_PORT_POL_PX2                     2                               /* Port x Bit 2 Polarity Invert */
-#define BITP_PORT_POL_PX1                     1                               /* Port x Bit 1 Polarity Invert */
-#define BITP_PORT_POL_PX0                     0                               /* Port x Bit 0 Polarity Invert */
-#define BITM_PORT_POL_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert */
-#define BITM_PORT_POL_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert */
-#define BITM_PORT_POL_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert */
-#define BITM_PORT_POL_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert */
-#define BITM_PORT_POL_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert */
-#define BITM_PORT_POL_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert */
-#define BITM_PORT_POL_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert */
-#define BITM_PORT_POL_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert */
-#define BITM_PORT_POL_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert */
-#define BITM_PORT_POL_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert */
-#define BITM_PORT_POL_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert */
-#define BITM_PORT_POL_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert */
-#define BITM_PORT_POL_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert */
-#define BITM_PORT_POL_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert */
-#define BITM_PORT_POL_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert */
-#define BITM_PORT_POL_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_SET_PX15               15                               /* Port x Bit 15 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX14               14                               /* Port x Bit 14 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX13               13                               /* Port x Bit 13 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX12               12                               /* Port x Bit 12 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX11               11                               /* Port x Bit 11 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX10               10                               /* Port x Bit 10 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX9                 9                               /* Port x Bit 9 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX8                 8                               /* Port x Bit 8 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX7                 7                               /* Port x Bit 7 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX6                 6                               /* Port x Bit 6 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX5                 5                               /* Port x Bit 5 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX4                 4                               /* Port x Bit 4 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX3                 3                               /* Port x Bit 3 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX2                 2                               /* Port x Bit 2 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX1                 1                               /* Port x Bit 1 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX0                 0                               /* Port x Bit 0 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_CLR_PX15               15                               /* Port x Bit 15 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX14               14                               /* Port x Bit 14 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX13               13                               /* Port x Bit 13 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX12               12                               /* Port x Bit 12 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX11               11                               /* Port x Bit 11 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX10               10                               /* Port x Bit 10 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX9                 9                               /* Port x Bit 9 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX8                 8                               /* Port x Bit 8 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX7                 7                               /* Port x Bit 7 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX6                 6                               /* Port x Bit 6 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX5                 5                               /* Port x Bit 5 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX4                 4                               /* Port x Bit 4 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX3                 3                               /* Port x Bit 3 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX2                 2                               /* Port x Bit 2 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX1                 1                               /* Port x Bit 1 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX0                 0                               /* Port x Bit 0 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_LOCK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_LOCK_LOCK                  31                               /* Lock */
-#define BITP_PORT_LOCK_POLAR                  5                               /* Polarity Lock */
-#define BITP_PORT_LOCK_INEN                   4                               /* Input Enable Lock */
-#define BITP_PORT_LOCK_DIR                    3                               /* Direction Lock */
-#define BITP_PORT_LOCK_DATA                   2                               /* Data Lock */
-#define BITP_PORT_LOCK_MUX                    1                               /* Function Multiplexer Lock */
-#define BITP_PORT_LOCK_FER                    0                               /* Function Enable Lock */
-#define BITM_PORT_LOCK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_PORT_LOCK_POLAR                 (_ADI_MSK(0x00000020,uint32_t))  /* Polarity Lock */
-#define BITM_PORT_LOCK_INEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Input Enable Lock */
-#define BITM_PORT_LOCK_DIR                   (_ADI_MSK(0x00000008,uint32_t))  /* Direction Lock */
-#define BITM_PORT_LOCK_DATA                  (_ADI_MSK(0x00000004,uint32_t))  /* Data Lock */
-#define BITM_PORT_LOCK_MUX                   (_ADI_MSK(0x00000002,uint32_t))  /* Function Multiplexer Lock */
-#define BITM_PORT_LOCK_FER                   (_ADI_MSK(0x00000001,uint32_t))  /* Function Enable Lock */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_REVID_MAJOR                 4                               /* Major ID */
-#define BITP_PORT_REVID_REV                   0                               /* Revision ID */
-#define BITM_PORT_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PORT_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID */
-
-/* ==================================================
-        Pads Controller Registers
-   ================================================== */
-
-/* =========================
-        PADS0
-   ========================= */
-#define REG_PADS0_EMAC_PTP_CLKSEL       0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
-#define REG_PADS0_TWI_VSEL              0xFFC03408         /* PADS0 TWI Voltage Selection */
-#define REG_PADS0_PORTS_HYST            0xFFC03440         /* PADS0 Hysteresis Enable Register */
-
-/* =========================
-        PADS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_EMAC_PTP_CLKSEL                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC1       2                               /* Select Clock Source for PTP Block in EMAC1 */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC0       0                               /* PTP Clock Source 0 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC1      (_ADI_MSK(0x0000000C,uint32_t))  /* Select Clock Source for PTP Block in EMAC1 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC0      (_ADI_MSK(0x00000003,uint32_t))  /* PTP Clock Source 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_TWI_VSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_TWI_VSEL_TWI1               4                               /* TWI Voltage Select 1 */
-#define BITP_PADS_TWI_VSEL_TWI0               0                               /* TWI Voltage Select 0 */
-#define BITM_PADS_TWI_VSEL_TWI1              (_ADI_MSK(0x00000070,uint32_t))  /* TWI Voltage Select 1 */
-#define BITM_PADS_TWI_VSEL_TWI0              (_ADI_MSK(0x00000007,uint32_t))  /* TWI Voltage Select 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_PORTS_HYST                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_PORTS_HYST_G                6                               /* Port G Hysteresis */
-#define BITP_PADS_PORTS_HYST_F                5                               /* Port F Hysteresis */
-#define BITP_PADS_PORTS_HYST_E                4                               /* Port E Hysteresis */
-#define BITP_PADS_PORTS_HYST_D                3                               /* Port D Hysteresis */
-#define BITP_PADS_PORTS_HYST_C                2                               /* Port C Hysteresis */
-#define BITP_PADS_PORTS_HYST_B                1                               /* Port B Hysteresis */
-#define BITP_PADS_PORTS_HYST_A                0                               /* Port A Hysteresis */
-#define BITM_PADS_PORTS_HYST_G               (_ADI_MSK(0x00000040,uint32_t))  /* Port G Hysteresis */
-#define BITM_PADS_PORTS_HYST_F               (_ADI_MSK(0x00000020,uint32_t))  /* Port F Hysteresis */
-#define BITM_PADS_PORTS_HYST_E               (_ADI_MSK(0x00000010,uint32_t))  /* Port E Hysteresis */
-#define BITM_PADS_PORTS_HYST_D               (_ADI_MSK(0x00000008,uint32_t))  /* Port D Hysteresis */
-#define BITM_PADS_PORTS_HYST_C               (_ADI_MSK(0x00000004,uint32_t))  /* Port C Hysteresis */
-#define BITM_PADS_PORTS_HYST_B               (_ADI_MSK(0x00000002,uint32_t))  /* Port B Hysteresis */
-#define BITM_PADS_PORTS_HYST_A               (_ADI_MSK(0x00000001,uint32_t))  /* Port A Hysteresis */
-
-/* ==================================================
-        PINT Registers
-   ================================================== */
-
-/* =========================
-        PINT0
-   ========================= */
-#define REG_PINT0_MSK_SET               0xFFC04000         /* PINT0 Pint Mask Set Register */
-#define REG_PINT0_MSK_CLR               0xFFC04004         /* PINT0 Pint Mask Clear Register */
-#define REG_PINT0_REQ                   0xFFC04008         /* PINT0 Pint Request Register */
-#define REG_PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
-#define REG_PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
-#define REG_PINT0_EDGE_CLR              0xFFC04014         /* PINT0 Pint Edge Clear Register */
-#define REG_PINT0_INV_SET               0xFFC04018         /* PINT0 Pint Invert Set Register */
-#define REG_PINT0_INV_CLR               0xFFC0401C         /* PINT0 Pint Invert Clear Register */
-#define REG_PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
-#define REG_PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
-
-/* =========================
-        PINT1
-   ========================= */
-#define REG_PINT1_MSK_SET               0xFFC04100         /* PINT1 Pint Mask Set Register */
-#define REG_PINT1_MSK_CLR               0xFFC04104         /* PINT1 Pint Mask Clear Register */
-#define REG_PINT1_REQ                   0xFFC04108         /* PINT1 Pint Request Register */
-#define REG_PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
-#define REG_PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
-#define REG_PINT1_EDGE_CLR              0xFFC04114         /* PINT1 Pint Edge Clear Register */
-#define REG_PINT1_INV_SET               0xFFC04118         /* PINT1 Pint Invert Set Register */
-#define REG_PINT1_INV_CLR               0xFFC0411C         /* PINT1 Pint Invert Clear Register */
-#define REG_PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
-#define REG_PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
-
-/* =========================
-        PINT2
-   ========================= */
-#define REG_PINT2_MSK_SET               0xFFC04200         /* PINT2 Pint Mask Set Register */
-#define REG_PINT2_MSK_CLR               0xFFC04204         /* PINT2 Pint Mask Clear Register */
-#define REG_PINT2_REQ                   0xFFC04208         /* PINT2 Pint Request Register */
-#define REG_PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
-#define REG_PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
-#define REG_PINT2_EDGE_CLR              0xFFC04214         /* PINT2 Pint Edge Clear Register */
-#define REG_PINT2_INV_SET               0xFFC04218         /* PINT2 Pint Invert Set Register */
-#define REG_PINT2_INV_CLR               0xFFC0421C         /* PINT2 Pint Invert Clear Register */
-#define REG_PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
-#define REG_PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
-
-/* =========================
-        PINT3
-   ========================= */
-#define REG_PINT3_MSK_SET               0xFFC04300         /* PINT3 Pint Mask Set Register */
-#define REG_PINT3_MSK_CLR               0xFFC04304         /* PINT3 Pint Mask Clear Register */
-#define REG_PINT3_REQ                   0xFFC04308         /* PINT3 Pint Request Register */
-#define REG_PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
-#define REG_PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
-#define REG_PINT3_EDGE_CLR              0xFFC04314         /* PINT3 Pint Edge Clear Register */
-#define REG_PINT3_INV_SET               0xFFC04318         /* PINT3 Pint Invert Set Register */
-#define REG_PINT3_INV_CLR               0xFFC0431C         /* PINT3 Pint Invert Clear Register */
-#define REG_PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
-#define REG_PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
-
-/* =========================
-        PINT4
-   ========================= */
-#define REG_PINT4_MSK_SET               0xFFC04400         /* PINT4 Pint Mask Set Register */
-#define REG_PINT4_MSK_CLR               0xFFC04404         /* PINT4 Pint Mask Clear Register */
-#define REG_PINT4_REQ                   0xFFC04408         /* PINT4 Pint Request Register */
-#define REG_PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
-#define REG_PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
-#define REG_PINT4_EDGE_CLR              0xFFC04414         /* PINT4 Pint Edge Clear Register */
-#define REG_PINT4_INV_SET               0xFFC04418         /* PINT4 Pint Invert Set Register */
-#define REG_PINT4_INV_CLR               0xFFC0441C         /* PINT4 Pint Invert Clear Register */
-#define REG_PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
-#define REG_PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
-
-/* =========================
-        PINT5
-   ========================= */
-#define REG_PINT5_MSK_SET               0xFFC04500         /* PINT5 Pint Mask Set Register */
-#define REG_PINT5_MSK_CLR               0xFFC04504         /* PINT5 Pint Mask Clear Register */
-#define REG_PINT5_REQ                   0xFFC04508         /* PINT5 Pint Request Register */
-#define REG_PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
-#define REG_PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
-#define REG_PINT5_EDGE_CLR              0xFFC04514         /* PINT5 Pint Edge Clear Register */
-#define REG_PINT5_INV_SET               0xFFC04518         /* PINT5 Pint Invert Set Register */
-#define REG_PINT5_INV_CLR               0xFFC0451C         /* PINT5 Pint Invert Clear Register */
-#define REG_PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
-#define REG_PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
-
-/* =========================
-        PINT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_SET_PIQ31              31                               /* Pin Interrupt 31 Unmask */
-#define BITP_PINT_MSK_SET_PIQ30              30                               /* Pin Interrupt 30 Unmask */
-#define BITP_PINT_MSK_SET_PIQ29              29                               /* Pin Interrupt 29 Unmask */
-#define BITP_PINT_MSK_SET_PIQ28              28                               /* Pin Interrupt 28 Unmask */
-#define BITP_PINT_MSK_SET_PIQ27              27                               /* Pin Interrupt 27 Unmask */
-#define BITP_PINT_MSK_SET_PIQ26              26                               /* Pin Interrupt 26 Unmask */
-#define BITP_PINT_MSK_SET_PIQ25              25                               /* Pin Interrupt 25 Unmask */
-#define BITP_PINT_MSK_SET_PIQ24              24                               /* Pin Interrupt 24 Unmask */
-#define BITP_PINT_MSK_SET_PIQ23              23                               /* Pin Interrupt 23 Unmask */
-#define BITP_PINT_MSK_SET_PIQ22              22                               /* Pin Interrupt 22 Unmask */
-#define BITP_PINT_MSK_SET_PIQ21              21                               /* Pin Interrupt 21 Unmask */
-#define BITP_PINT_MSK_SET_PIQ20              20                               /* Pin Interrupt 20 Unmask */
-#define BITP_PINT_MSK_SET_PIQ19              19                               /* Pin Interrupt 19 Unmask */
-#define BITP_PINT_MSK_SET_PIQ18              18                               /* Pin Interrupt 18 Unmask */
-#define BITP_PINT_MSK_SET_PIQ17              17                               /* Pin Interrupt 17 Unmask */
-#define BITP_PINT_MSK_SET_PIQ16              16                               /* Pin Interrupt 16 Unmask */
-#define BITP_PINT_MSK_SET_PIQ15              15                               /* Pin Interrupt 15 Unmask */
-#define BITP_PINT_MSK_SET_PIQ14              14                               /* Pin Interrupt 14 Unmask */
-#define BITP_PINT_MSK_SET_PIQ13              13                               /* Pin Interrupt 13 Unmask */
-#define BITP_PINT_MSK_SET_PIQ12              12                               /* Pin Interrupt 12 Unmask */
-#define BITP_PINT_MSK_SET_PIQ11              11                               /* Pin Interrupt 11 Unmask */
-#define BITP_PINT_MSK_SET_PIQ10              10                               /* Pin Interrupt 10 Unmask */
-#define BITP_PINT_MSK_SET_PIQ9                9                               /* Pin Interrupt 9 Unmask */
-#define BITP_PINT_MSK_SET_PIQ8                8                               /* Pin Interrupt 8 Unmask */
-#define BITP_PINT_MSK_SET_PIQ7                7                               /* Pin Interrupt 7 Unmask */
-#define BITP_PINT_MSK_SET_PIQ6                6                               /* Pin Interrupt 6 Unmask */
-#define BITP_PINT_MSK_SET_PIQ5                5                               /* Pin Interrupt 5 Unmask */
-#define BITP_PINT_MSK_SET_PIQ4                4                               /* Pin Interrupt 4 Unmask */
-#define BITP_PINT_MSK_SET_PIQ3                3                               /* Pin Interrupt 3 Unmask */
-#define BITP_PINT_MSK_SET_PIQ2                2                               /* Pin Interrupt 2 Unmask */
-#define BITP_PINT_MSK_SET_PIQ1                1                               /* Pin Interrupt 1 Unmask */
-#define BITP_PINT_MSK_SET_PIQ0                0                               /* Pin Interrupt 0 Unmask */
-#define BITM_PINT_MSK_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Unmask */
-#define BITM_PINT_MSK_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Unmask */
-#define BITM_PINT_MSK_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Unmask */
-#define BITM_PINT_MSK_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Unmask */
-#define BITM_PINT_MSK_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Unmask */
-#define BITM_PINT_MSK_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Unmask */
-#define BITM_PINT_MSK_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Unmask */
-#define BITM_PINT_MSK_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Unmask */
-#define BITM_PINT_MSK_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Unmask */
-#define BITM_PINT_MSK_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Unmask */
-#define BITM_PINT_MSK_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Unmask */
-#define BITM_PINT_MSK_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Unmask */
-#define BITM_PINT_MSK_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Unmask */
-#define BITM_PINT_MSK_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Unmask */
-#define BITM_PINT_MSK_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Unmask */
-#define BITM_PINT_MSK_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Unmask */
-#define BITM_PINT_MSK_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Unmask */
-#define BITM_PINT_MSK_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Unmask */
-#define BITM_PINT_MSK_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Unmask */
-#define BITM_PINT_MSK_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Unmask */
-#define BITM_PINT_MSK_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Unmask */
-#define BITM_PINT_MSK_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Unmask */
-#define BITM_PINT_MSK_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Unmask */
-#define BITM_PINT_MSK_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Unmask */
-#define BITM_PINT_MSK_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Unmask */
-#define BITM_PINT_MSK_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Unmask */
-#define BITM_PINT_MSK_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Unmask */
-#define BITM_PINT_MSK_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Unmask */
-#define BITM_PINT_MSK_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Unmask */
-#define BITM_PINT_MSK_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Unmask */
-#define BITM_PINT_MSK_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Unmask */
-#define BITM_PINT_MSK_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_CLR_PIQ31              31                               /* Pin Interrupt 31 Mask */
-#define BITP_PINT_MSK_CLR_PIQ30              30                               /* Pin Interrupt 30 Mask */
-#define BITP_PINT_MSK_CLR_PIQ29              29                               /* Pin Interrupt 29 Mask */
-#define BITP_PINT_MSK_CLR_PIQ28              28                               /* Pin Interrupt 28 Mask */
-#define BITP_PINT_MSK_CLR_PIQ27              27                               /* Pin Interrupt 27 Mask */
-#define BITP_PINT_MSK_CLR_PIQ26              26                               /* Pin Interrupt 26 Mask */
-#define BITP_PINT_MSK_CLR_PIQ25              25                               /* Pin Interrupt 25 Mask */
-#define BITP_PINT_MSK_CLR_PIQ24              24                               /* Pin Interrupt 24 Mask */
-#define BITP_PINT_MSK_CLR_PIQ23              23                               /* Pin Interrupt 23 Mask */
-#define BITP_PINT_MSK_CLR_PIQ22              22                               /* Pin Interrupt 22 Mask */
-#define BITP_PINT_MSK_CLR_PIQ21              21                               /* Pin Interrupt 21 Mask */
-#define BITP_PINT_MSK_CLR_PIQ20              20                               /* Pin Interrupt 20 Mask */
-#define BITP_PINT_MSK_CLR_PIQ19              19                               /* Pin Interrupt 19 Mask */
-#define BITP_PINT_MSK_CLR_PIQ18              18                               /* Pin Interrupt 18 Mask */
-#define BITP_PINT_MSK_CLR_PIQ17              17                               /* Pin Interrupt 17 Mask */
-#define BITP_PINT_MSK_CLR_PIQ16              16                               /* Pin Interrupt 16 Mask */
-#define BITP_PINT_MSK_CLR_PIQ15              15                               /* Pin Interrupt 15 Mask */
-#define BITP_PINT_MSK_CLR_PIQ14              14                               /* Pin Interrupt 14 Mask */
-#define BITP_PINT_MSK_CLR_PIQ13              13                               /* Pin Interrupt 13 Mask */
-#define BITP_PINT_MSK_CLR_PIQ12              12                               /* Pin Interrupt 12 Mask */
-#define BITP_PINT_MSK_CLR_PIQ11              11                               /* Pin Interrupt 11 Mask */
-#define BITP_PINT_MSK_CLR_PIQ10              10                               /* Pin Interrupt 10 Mask */
-#define BITP_PINT_MSK_CLR_PIQ9                9                               /* Pin Interrupt 9 Mask */
-#define BITP_PINT_MSK_CLR_PIQ8                8                               /* Pin Interrupt 8 Mask */
-#define BITP_PINT_MSK_CLR_PIQ7                7                               /* Pin Interrupt 7 Mask */
-#define BITP_PINT_MSK_CLR_PIQ6                6                               /* Pin Interrupt 6 Mask */
-#define BITP_PINT_MSK_CLR_PIQ5                5                               /* Pin Interrupt 5 Mask */
-#define BITP_PINT_MSK_CLR_PIQ4                4                               /* Pin Interrupt 4 Mask */
-#define BITP_PINT_MSK_CLR_PIQ3                3                               /* Pin Interrupt 3 Mask */
-#define BITP_PINT_MSK_CLR_PIQ2                2                               /* Pin Interrupt 2 Mask */
-#define BITP_PINT_MSK_CLR_PIQ1                1                               /* Pin Interrupt 1 Mask */
-#define BITP_PINT_MSK_CLR_PIQ0                0                               /* Pin Interrupt 0 Mask */
-#define BITM_PINT_MSK_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Mask */
-#define BITM_PINT_MSK_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Mask */
-#define BITM_PINT_MSK_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Mask */
-#define BITM_PINT_MSK_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Mask */
-#define BITM_PINT_MSK_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Mask */
-#define BITM_PINT_MSK_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Mask */
-#define BITM_PINT_MSK_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Mask */
-#define BITM_PINT_MSK_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Mask */
-#define BITM_PINT_MSK_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Mask */
-#define BITM_PINT_MSK_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Mask */
-#define BITM_PINT_MSK_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Mask */
-#define BITM_PINT_MSK_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Mask */
-#define BITM_PINT_MSK_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Mask */
-#define BITM_PINT_MSK_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Mask */
-#define BITM_PINT_MSK_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Mask */
-#define BITM_PINT_MSK_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Mask */
-#define BITM_PINT_MSK_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Mask */
-#define BITM_PINT_MSK_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Mask */
-#define BITM_PINT_MSK_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Mask */
-#define BITM_PINT_MSK_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Mask */
-#define BITM_PINT_MSK_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Mask */
-#define BITM_PINT_MSK_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Mask */
-#define BITM_PINT_MSK_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Mask */
-#define BITM_PINT_MSK_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Mask */
-#define BITM_PINT_MSK_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Mask */
-#define BITM_PINT_MSK_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Mask */
-#define BITM_PINT_MSK_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Mask */
-#define BITM_PINT_MSK_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Mask */
-#define BITM_PINT_MSK_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Mask */
-#define BITM_PINT_MSK_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Mask */
-#define BITM_PINT_MSK_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Mask */
-#define BITM_PINT_MSK_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_REQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_REQ_PIQ31                  31                               /* Pin Interrupt 31 Request */
-#define BITP_PINT_REQ_PIQ30                  30                               /* Pin Interrupt 30 Request */
-#define BITP_PINT_REQ_PIQ29                  29                               /* Pin Interrupt 29 Request */
-#define BITP_PINT_REQ_PIQ28                  28                               /* Pin Interrupt 28 Request */
-#define BITP_PINT_REQ_PIQ27                  27                               /* Pin Interrupt 27 Request */
-#define BITP_PINT_REQ_PIQ26                  26                               /* Pin Interrupt 26 Request */
-#define BITP_PINT_REQ_PIQ25                  25                               /* Pin Interrupt 25 Request */
-#define BITP_PINT_REQ_PIQ24                  24                               /* Pin Interrupt 24 Request */
-#define BITP_PINT_REQ_PIQ23                  23                               /* Pin Interrupt 23 Request */
-#define BITP_PINT_REQ_PIQ22                  22                               /* Pin Interrupt 22 Request */
-#define BITP_PINT_REQ_PIQ21                  21                               /* Pin Interrupt 21 Request */
-#define BITP_PINT_REQ_PIQ20                  20                               /* Pin Interrupt 20 Request */
-#define BITP_PINT_REQ_PIQ19                  19                               /* Pin Interrupt 19 Request */
-#define BITP_PINT_REQ_PIQ18                  18                               /* Pin Interrupt 18 Request */
-#define BITP_PINT_REQ_PIQ17                  17                               /* Pin Interrupt 17 Request */
-#define BITP_PINT_REQ_PIQ16                  16                               /* Pin Interrupt 16 Request */
-#define BITP_PINT_REQ_PIQ15                  15                               /* Pin Interrupt 15 Request */
-#define BITP_PINT_REQ_PIQ14                  14                               /* Pin Interrupt 14 Request */
-#define BITP_PINT_REQ_PIQ13                  13                               /* Pin Interrupt 13 Request */
-#define BITP_PINT_REQ_PIQ12                  12                               /* Pin Interrupt 12 Request */
-#define BITP_PINT_REQ_PIQ11                  11                               /* Pin Interrupt 11 Request */
-#define BITP_PINT_REQ_PIQ10                  10                               /* Pin Interrupt 10 Request */
-#define BITP_PINT_REQ_PIQ9                    9                               /* Pin Interrupt 9 Request */
-#define BITP_PINT_REQ_PIQ8                    8                               /* Pin Interrupt 8 Request */
-#define BITP_PINT_REQ_PIQ7                    7                               /* Pin Interrupt 7 Request */
-#define BITP_PINT_REQ_PIQ6                    6                               /* Pin Interrupt 6 Request */
-#define BITP_PINT_REQ_PIQ5                    5                               /* Pin Interrupt 5 Request */
-#define BITP_PINT_REQ_PIQ4                    4                               /* Pin Interrupt 4 Request */
-#define BITP_PINT_REQ_PIQ3                    3                               /* Pin Interrupt 3 Request */
-#define BITP_PINT_REQ_PIQ2                    2                               /* Pin Interrupt 2 Request */
-#define BITP_PINT_REQ_PIQ1                    1                               /* Pin Interrupt 1 Request */
-#define BITP_PINT_REQ_PIQ0                    0                               /* Pin Interrupt 0 Request */
-#define BITM_PINT_REQ_PIQ31                  (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Request */
-#define BITM_PINT_REQ_PIQ30                  (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Request */
-#define BITM_PINT_REQ_PIQ29                  (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Request */
-#define BITM_PINT_REQ_PIQ28                  (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Request */
-#define BITM_PINT_REQ_PIQ27                  (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Request */
-#define BITM_PINT_REQ_PIQ26                  (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Request */
-#define BITM_PINT_REQ_PIQ25                  (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Request */
-#define BITM_PINT_REQ_PIQ24                  (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Request */
-#define BITM_PINT_REQ_PIQ23                  (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Request */
-#define BITM_PINT_REQ_PIQ22                  (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Request */
-#define BITM_PINT_REQ_PIQ21                  (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Request */
-#define BITM_PINT_REQ_PIQ20                  (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Request */
-#define BITM_PINT_REQ_PIQ19                  (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Request */
-#define BITM_PINT_REQ_PIQ18                  (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Request */
-#define BITM_PINT_REQ_PIQ17                  (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Request */
-#define BITM_PINT_REQ_PIQ16                  (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Request */
-#define BITM_PINT_REQ_PIQ15                  (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Request */
-#define BITM_PINT_REQ_PIQ14                  (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Request */
-#define BITM_PINT_REQ_PIQ13                  (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Request */
-#define BITM_PINT_REQ_PIQ12                  (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Request */
-#define BITM_PINT_REQ_PIQ11                  (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Request */
-#define BITM_PINT_REQ_PIQ10                  (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Request */
-#define BITM_PINT_REQ_PIQ9                   (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Request */
-#define BITM_PINT_REQ_PIQ8                   (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Request */
-#define BITM_PINT_REQ_PIQ7                   (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Request */
-#define BITM_PINT_REQ_PIQ6                   (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Request */
-#define BITM_PINT_REQ_PIQ5                   (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Request */
-#define BITM_PINT_REQ_PIQ4                   (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Request */
-#define BITM_PINT_REQ_PIQ3                   (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Request */
-#define BITM_PINT_REQ_PIQ2                   (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Request */
-#define BITM_PINT_REQ_PIQ1                   (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Request */
-#define BITM_PINT_REQ_PIQ0                   (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_ASSIGN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_ASSIGN_B3MAP               24                               /* Byte 3 Mapping */
-#define BITP_PINT_ASSIGN_B2MAP               16                               /* Byte 2 Mapping */
-#define BITP_PINT_ASSIGN_B1MAP                8                               /* Byte 1 Mapping */
-#define BITP_PINT_ASSIGN_B0MAP                0                               /* Byte 0 Mapping */
-#define BITM_PINT_ASSIGN_B3MAP               (_ADI_MSK(0xFF000000,uint32_t))  /* Byte 3 Mapping */
-#define BITM_PINT_ASSIGN_B2MAP               (_ADI_MSK(0x00FF0000,uint32_t))  /* Byte 2 Mapping */
-#define BITM_PINT_ASSIGN_B1MAP               (_ADI_MSK(0x0000FF00,uint32_t))  /* Byte 1 Mapping */
-#define BITM_PINT_ASSIGN_B0MAP               (_ADI_MSK(0x000000FF,uint32_t))  /* Byte 0 Mapping */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_SET_PIQ31             31                               /* Pin Interrupt 31 Edge */
-#define BITP_PINT_EDGE_SET_PIQ30             30                               /* Pin Interrupt 30 Edge */
-#define BITP_PINT_EDGE_SET_PIQ29             29                               /* Pin Interrupt 29 Edge */
-#define BITP_PINT_EDGE_SET_PIQ28             28                               /* Pin Interrupt 28 Edge */
-#define BITP_PINT_EDGE_SET_PIQ27             27                               /* Pin Interrupt 27 Edge */
-#define BITP_PINT_EDGE_SET_PIQ26             26                               /* Pin Interrupt 26 Edge */
-#define BITP_PINT_EDGE_SET_PIQ25             25                               /* Pin Interrupt 25 Edge */
-#define BITP_PINT_EDGE_SET_PIQ24             24                               /* Pin Interrupt 24 Edge */
-#define BITP_PINT_EDGE_SET_PIQ23             23                               /* Pin Interrupt 23 Edge */
-#define BITP_PINT_EDGE_SET_PIQ22             22                               /* Pin Interrupt 22 Edge */
-#define BITP_PINT_EDGE_SET_PIQ21             21                               /* Pin Interrupt 21 Edge */
-#define BITP_PINT_EDGE_SET_PIQ20             20                               /* Pin Interrupt 20 Edge */
-#define BITP_PINT_EDGE_SET_PIQ19             19                               /* Pin Interrupt 19 Edge */
-#define BITP_PINT_EDGE_SET_PIQ18             18                               /* Pin Interrupt 18 Edge */
-#define BITP_PINT_EDGE_SET_PIQ17             17                               /* Pin Interrupt 17 Edge */
-#define BITP_PINT_EDGE_SET_PIQ16             16                               /* Pin Interrupt 16 Edge */
-#define BITP_PINT_EDGE_SET_PIQ15             15                               /* Pin Interrupt 15 Edge */
-#define BITP_PINT_EDGE_SET_PIQ14             14                               /* Pin Interrupt 14 Edge */
-#define BITP_PINT_EDGE_SET_PIQ13             13                               /* Pin Interrupt 13 Edge */
-#define BITP_PINT_EDGE_SET_PIQ12             12                               /* Pin Interrupt 12 Edge */
-#define BITP_PINT_EDGE_SET_PIQ11             11                               /* Pin Interrupt 11 Edge */
-#define BITP_PINT_EDGE_SET_PIQ10             10                               /* Pin Interrupt 10 Edge */
-#define BITP_PINT_EDGE_SET_PIQ9               9                               /* Pin Interrupt 9 Edge */
-#define BITP_PINT_EDGE_SET_PIQ8               8                               /* Pin Interrupt 8 Edge */
-#define BITP_PINT_EDGE_SET_PIQ7               7                               /* Pin Interrupt 7 Edge */
-#define BITP_PINT_EDGE_SET_PIQ6               6                               /* Pin Interrupt 6 Edge */
-#define BITP_PINT_EDGE_SET_PIQ5               5                               /* Pin Interrupt 5 Edge */
-#define BITP_PINT_EDGE_SET_PIQ4               4                               /* Pin Interrupt 4 Edge */
-#define BITP_PINT_EDGE_SET_PIQ3               3                               /* Pin Interrupt 3 Edge */
-#define BITP_PINT_EDGE_SET_PIQ2               2                               /* Pin Interrupt 2 Edge */
-#define BITP_PINT_EDGE_SET_PIQ1               1                               /* Pin Interrupt 1 Edge */
-#define BITP_PINT_EDGE_SET_PIQ0               0                               /* Pin Interrupt 0 Edge */
-#define BITM_PINT_EDGE_SET_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Edge */
-#define BITM_PINT_EDGE_SET_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Edge */
-#define BITM_PINT_EDGE_SET_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Edge */
-#define BITM_PINT_EDGE_SET_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Edge */
-#define BITM_PINT_EDGE_SET_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Edge */
-#define BITM_PINT_EDGE_SET_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Edge */
-#define BITM_PINT_EDGE_SET_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Edge */
-#define BITM_PINT_EDGE_SET_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Edge */
-#define BITM_PINT_EDGE_SET_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Edge */
-#define BITM_PINT_EDGE_SET_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Edge */
-#define BITM_PINT_EDGE_SET_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Edge */
-#define BITM_PINT_EDGE_SET_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Edge */
-#define BITM_PINT_EDGE_SET_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Edge */
-#define BITM_PINT_EDGE_SET_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Edge */
-#define BITM_PINT_EDGE_SET_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Edge */
-#define BITM_PINT_EDGE_SET_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Edge */
-#define BITM_PINT_EDGE_SET_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Edge */
-#define BITM_PINT_EDGE_SET_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Edge */
-#define BITM_PINT_EDGE_SET_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Edge */
-#define BITM_PINT_EDGE_SET_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Edge */
-#define BITM_PINT_EDGE_SET_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Edge */
-#define BITM_PINT_EDGE_SET_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Edge */
-#define BITM_PINT_EDGE_SET_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Edge */
-#define BITM_PINT_EDGE_SET_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Edge */
-#define BITM_PINT_EDGE_SET_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Edge */
-#define BITM_PINT_EDGE_SET_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Edge */
-#define BITM_PINT_EDGE_SET_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Edge */
-#define BITM_PINT_EDGE_SET_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Edge */
-#define BITM_PINT_EDGE_SET_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Edge */
-#define BITM_PINT_EDGE_SET_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Edge */
-#define BITM_PINT_EDGE_SET_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Edge */
-#define BITM_PINT_EDGE_SET_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Edge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_CLR_PIQ31             31                               /* Pin Interrupt 31 Level */
-#define BITP_PINT_EDGE_CLR_PIQ30             30                               /* Pin Interrupt 30 Level */
-#define BITP_PINT_EDGE_CLR_PIQ29             29                               /* Pin Interrupt 29 Level */
-#define BITP_PINT_EDGE_CLR_PIQ28             28                               /* Pin Interrupt 28 Level */
-#define BITP_PINT_EDGE_CLR_PIQ27             27                               /* Pin Interrupt 27 Level */
-#define BITP_PINT_EDGE_CLR_PIQ26             26                               /* Pin Interrupt 26 Level */
-#define BITP_PINT_EDGE_CLR_PIQ25             25                               /* Pin Interrupt 25 Level */
-#define BITP_PINT_EDGE_CLR_PIQ24             24                               /* Pin Interrupt 24 Level */
-#define BITP_PINT_EDGE_CLR_PIQ23             23                               /* Pin Interrupt 23 Level */
-#define BITP_PINT_EDGE_CLR_PIQ22             22                               /* Pin Interrupt 22 Level */
-#define BITP_PINT_EDGE_CLR_PIQ21             21                               /* Pin Interrupt 21 Level */
-#define BITP_PINT_EDGE_CLR_PIQ20             20                               /* Pin Interrupt 20 Level */
-#define BITP_PINT_EDGE_CLR_PIQ19             19                               /* Pin Interrupt 19 Level */
-#define BITP_PINT_EDGE_CLR_PIQ18             18                               /* Pin Interrupt 18 Level */
-#define BITP_PINT_EDGE_CLR_PIQ17             17                               /* Pin Interrupt 17 Level */
-#define BITP_PINT_EDGE_CLR_PIQ16             16                               /* Pin Interrupt 16 Level */
-#define BITP_PINT_EDGE_CLR_PIQ15             15                               /* Pin Interrupt 15 Level */
-#define BITP_PINT_EDGE_CLR_PIQ14             14                               /* Pin Interrupt 14 Level */
-#define BITP_PINT_EDGE_CLR_PIQ13             13                               /* Pin Interrupt 13 Level */
-#define BITP_PINT_EDGE_CLR_PIQ12             12                               /* Pin Interrupt 12 Level */
-#define BITP_PINT_EDGE_CLR_PIQ11             11                               /* Pin Interrupt 11 Level */
-#define BITP_PINT_EDGE_CLR_PIQ10             10                               /* Pin Interrupt 10 Level */
-#define BITP_PINT_EDGE_CLR_PIQ9               9                               /* Pin Interrupt 9 Level */
-#define BITP_PINT_EDGE_CLR_PIQ8               8                               /* Pin Interrupt 8 Level */
-#define BITP_PINT_EDGE_CLR_PIQ7               7                               /* Pin Interrupt 7 Level */
-#define BITP_PINT_EDGE_CLR_PIQ6               6                               /* Pin Interrupt 6 Level */
-#define BITP_PINT_EDGE_CLR_PIQ5               5                               /* Pin Interrupt 5 Level */
-#define BITP_PINT_EDGE_CLR_PIQ4               4                               /* Pin Interrupt 4 Level */
-#define BITP_PINT_EDGE_CLR_PIQ3               3                               /* Pin Interrupt 3 Level */
-#define BITP_PINT_EDGE_CLR_PIQ2               2                               /* Pin Interrupt 2 Level */
-#define BITP_PINT_EDGE_CLR_PIQ1               1                               /* Pin Interrupt 1 Level */
-#define BITP_PINT_EDGE_CLR_PIQ0               0                               /* Pin Interrupt 0 Level */
-#define BITM_PINT_EDGE_CLR_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Level */
-#define BITM_PINT_EDGE_CLR_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Level */
-#define BITM_PINT_EDGE_CLR_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Level */
-#define BITM_PINT_EDGE_CLR_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Level */
-#define BITM_PINT_EDGE_CLR_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Level */
-#define BITM_PINT_EDGE_CLR_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Level */
-#define BITM_PINT_EDGE_CLR_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Level */
-#define BITM_PINT_EDGE_CLR_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Level */
-#define BITM_PINT_EDGE_CLR_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Level */
-#define BITM_PINT_EDGE_CLR_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Level */
-#define BITM_PINT_EDGE_CLR_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Level */
-#define BITM_PINT_EDGE_CLR_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Level */
-#define BITM_PINT_EDGE_CLR_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Level */
-#define BITM_PINT_EDGE_CLR_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Level */
-#define BITM_PINT_EDGE_CLR_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Level */
-#define BITM_PINT_EDGE_CLR_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Level */
-#define BITM_PINT_EDGE_CLR_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Level */
-#define BITM_PINT_EDGE_CLR_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Level */
-#define BITM_PINT_EDGE_CLR_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Level */
-#define BITM_PINT_EDGE_CLR_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Level */
-#define BITM_PINT_EDGE_CLR_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Level */
-#define BITM_PINT_EDGE_CLR_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Level */
-#define BITM_PINT_EDGE_CLR_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Level */
-#define BITM_PINT_EDGE_CLR_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Level */
-#define BITM_PINT_EDGE_CLR_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Level */
-#define BITM_PINT_EDGE_CLR_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Level */
-#define BITM_PINT_EDGE_CLR_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Level */
-#define BITM_PINT_EDGE_CLR_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Level */
-#define BITM_PINT_EDGE_CLR_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Level */
-#define BITM_PINT_EDGE_CLR_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Level */
-#define BITM_PINT_EDGE_CLR_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Level */
-#define BITM_PINT_EDGE_CLR_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Level */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_SET_PIQ31              31                               /* Pin Interrupt 31 Invert */
-#define BITP_PINT_INV_SET_PIQ30              30                               /* Pin Interrupt 30 Invert */
-#define BITP_PINT_INV_SET_PIQ29              29                               /* Pin Interrupt 29 Invert */
-#define BITP_PINT_INV_SET_PIQ28              28                               /* Pin Interrupt 28 Invert */
-#define BITP_PINT_INV_SET_PIQ27              27                               /* Pin Interrupt 27 Invert */
-#define BITP_PINT_INV_SET_PIQ26              26                               /* Pin Interrupt 26 Invert */
-#define BITP_PINT_INV_SET_PIQ25              25                               /* Pin Interrupt 25 Invert */
-#define BITP_PINT_INV_SET_PIQ24              24                               /* Pin Interrupt 24 Invert */
-#define BITP_PINT_INV_SET_PIQ23              23                               /* Pin Interrupt 23 Invert */
-#define BITP_PINT_INV_SET_PIQ22              22                               /* Pin Interrupt 22 Invert */
-#define BITP_PINT_INV_SET_PIQ21              21                               /* Pin Interrupt 21 Invert */
-#define BITP_PINT_INV_SET_PIQ20              20                               /* Pin Interrupt 20 Invert */
-#define BITP_PINT_INV_SET_PIQ19              19                               /* Pin Interrupt 19 Invert */
-#define BITP_PINT_INV_SET_PIQ18              18                               /* Pin Interrupt 18 Invert */
-#define BITP_PINT_INV_SET_PIQ17              17                               /* Pin Interrupt 17 Invert */
-#define BITP_PINT_INV_SET_PIQ16              16                               /* Pin Interrupt 16 Invert */
-#define BITP_PINT_INV_SET_PIQ15              15                               /* Pin Interrupt 15 Invert */
-#define BITP_PINT_INV_SET_PIQ14              14                               /* Pin Interrupt 14 Invert */
-#define BITP_PINT_INV_SET_PIQ13              13                               /* Pin Interrupt 13 Invert */
-#define BITP_PINT_INV_SET_PIQ12              12                               /* Pin Interrupt 12 Invert */
-#define BITP_PINT_INV_SET_PIQ11              11                               /* Pin Interrupt 11 Invert */
-#define BITP_PINT_INV_SET_PIQ10              10                               /* Pin Interrupt 10 Invert */
-#define BITP_PINT_INV_SET_PIQ9                9                               /* Pin Interrupt 9 Invert */
-#define BITP_PINT_INV_SET_PIQ8                8                               /* Pin Interrupt 8 Invert */
-#define BITP_PINT_INV_SET_PIQ7                7                               /* Pin Interrupt 7 Invert */
-#define BITP_PINT_INV_SET_PIQ6                6                               /* Pin Interrupt 6 Invert */
-#define BITP_PINT_INV_SET_PIQ5                5                               /* Pin Interrupt 5 Invert */
-#define BITP_PINT_INV_SET_PIQ4                4                               /* Pin Interrupt 4 Invert */
-#define BITP_PINT_INV_SET_PIQ3                3                               /* Pin Interrupt 3 Invert */
-#define BITP_PINT_INV_SET_PIQ2                2                               /* Pin Interrupt 2 Invert */
-#define BITP_PINT_INV_SET_PIQ1                1                               /* Pin Interrupt 1 Invert */
-#define BITP_PINT_INV_SET_PIQ0                0                               /* Pin Interrupt 0 Invert */
-#define BITM_PINT_INV_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Invert */
-#define BITM_PINT_INV_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Invert */
-#define BITM_PINT_INV_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Invert */
-#define BITM_PINT_INV_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Invert */
-#define BITM_PINT_INV_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Invert */
-#define BITM_PINT_INV_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Invert */
-#define BITM_PINT_INV_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Invert */
-#define BITM_PINT_INV_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Invert */
-#define BITM_PINT_INV_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Invert */
-#define BITM_PINT_INV_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Invert */
-#define BITM_PINT_INV_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Invert */
-#define BITM_PINT_INV_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Invert */
-#define BITM_PINT_INV_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Invert */
-#define BITM_PINT_INV_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Invert */
-#define BITM_PINT_INV_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Invert */
-#define BITM_PINT_INV_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Invert */
-#define BITM_PINT_INV_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Invert */
-#define BITM_PINT_INV_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Invert */
-#define BITM_PINT_INV_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Invert */
-#define BITM_PINT_INV_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Invert */
-#define BITM_PINT_INV_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Invert */
-#define BITM_PINT_INV_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Invert */
-#define BITM_PINT_INV_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Invert */
-#define BITM_PINT_INV_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Invert */
-#define BITM_PINT_INV_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Invert */
-#define BITM_PINT_INV_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Invert */
-#define BITM_PINT_INV_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Invert */
-#define BITM_PINT_INV_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Invert */
-#define BITM_PINT_INV_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Invert */
-#define BITM_PINT_INV_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Invert */
-#define BITM_PINT_INV_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Invert */
-#define BITM_PINT_INV_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_CLR_PIQ31              31                               /* Pin Interrupt 31 No Invert */
-#define BITP_PINT_INV_CLR_PIQ30              30                               /* Pin Interrupt 30 No Invert */
-#define BITP_PINT_INV_CLR_PIQ29              29                               /* Pin Interrupt 29 No Invert */
-#define BITP_PINT_INV_CLR_PIQ28              28                               /* Pin Interrupt 28 No Invert */
-#define BITP_PINT_INV_CLR_PIQ27              27                               /* Pin Interrupt 27 No Invert */
-#define BITP_PINT_INV_CLR_PIQ26              26                               /* Pin Interrupt 26 No Invert */
-#define BITP_PINT_INV_CLR_PIQ25              25                               /* Pin Interrupt 25 No Invert */
-#define BITP_PINT_INV_CLR_PIQ24              24                               /* Pin Interrupt 24 No Invert */
-#define BITP_PINT_INV_CLR_PIQ23              23                               /* Pin Interrupt 23 No Invert */
-#define BITP_PINT_INV_CLR_PIQ22              22                               /* Pin Interrupt 22 No Invert */
-#define BITP_PINT_INV_CLR_PIQ21              21                               /* Pin Interrupt 21 No Invert */
-#define BITP_PINT_INV_CLR_PIQ20              20                               /* Pin Interrupt 20 No Invert */
-#define BITP_PINT_INV_CLR_PIQ19              19                               /* Pin Interrupt 19 No Invert */
-#define BITP_PINT_INV_CLR_PIQ18              18                               /* Pin Interrupt 18 No Invert */
-#define BITP_PINT_INV_CLR_PIQ17              17                               /* Pin Interrupt 17 No Invert */
-#define BITP_PINT_INV_CLR_PIQ16              16                               /* Pin Interrupt 16 No Invert */
-#define BITP_PINT_INV_CLR_PIQ15              15                               /* Pin Interrupt 15 No Invert */
-#define BITP_PINT_INV_CLR_PIQ14              14                               /* Pin Interrupt 14 No Invert */
-#define BITP_PINT_INV_CLR_PIQ13              13                               /* Pin Interrupt 13 No Invert */
-#define BITP_PINT_INV_CLR_PIQ12              12                               /* Pin Interrupt 12 No Invert */
-#define BITP_PINT_INV_CLR_PIQ11              11                               /* Pin Interrupt 11 No Invert */
-#define BITP_PINT_INV_CLR_PIQ10              10                               /* Pin Interrupt 10 No Invert */
-#define BITP_PINT_INV_CLR_PIQ9                9                               /* Pin Interrupt 9 No Invert */
-#define BITP_PINT_INV_CLR_PIQ8                8                               /* Pin Interrupt 8 No Invert */
-#define BITP_PINT_INV_CLR_PIQ7                7                               /* Pin Interrupt 7 No Invert */
-#define BITP_PINT_INV_CLR_PIQ6                6                               /* Pin Interrupt 6 No Invert */
-#define BITP_PINT_INV_CLR_PIQ5                5                               /* Pin Interrupt 5 No Invert */
-#define BITP_PINT_INV_CLR_PIQ4                4                               /* Pin Interrupt 4 No Invert */
-#define BITP_PINT_INV_CLR_PIQ3                3                               /* Pin Interrupt 3 No Invert */
-#define BITP_PINT_INV_CLR_PIQ2                2                               /* Pin Interrupt 2 No Invert */
-#define BITP_PINT_INV_CLR_PIQ1                1                               /* Pin Interrupt 1 No Invert */
-#define BITP_PINT_INV_CLR_PIQ0                0                               /* Pin Interrupt 0 No Invert */
-#define BITM_PINT_INV_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 No Invert */
-#define BITM_PINT_INV_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 No Invert */
-#define BITM_PINT_INV_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 No Invert */
-#define BITM_PINT_INV_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 No Invert */
-#define BITM_PINT_INV_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 No Invert */
-#define BITM_PINT_INV_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 No Invert */
-#define BITM_PINT_INV_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 No Invert */
-#define BITM_PINT_INV_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 No Invert */
-#define BITM_PINT_INV_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 No Invert */
-#define BITM_PINT_INV_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 No Invert */
-#define BITM_PINT_INV_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 No Invert */
-#define BITM_PINT_INV_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 No Invert */
-#define BITM_PINT_INV_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 No Invert */
-#define BITM_PINT_INV_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 No Invert */
-#define BITM_PINT_INV_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 No Invert */
-#define BITM_PINT_INV_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 No Invert */
-#define BITM_PINT_INV_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 No Invert */
-#define BITM_PINT_INV_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 No Invert */
-#define BITM_PINT_INV_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 No Invert */
-#define BITM_PINT_INV_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 No Invert */
-#define BITM_PINT_INV_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 No Invert */
-#define BITM_PINT_INV_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 No Invert */
-#define BITM_PINT_INV_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 No Invert */
-#define BITM_PINT_INV_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 No Invert */
-#define BITM_PINT_INV_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 No Invert */
-#define BITM_PINT_INV_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 No Invert */
-#define BITM_PINT_INV_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 No Invert */
-#define BITM_PINT_INV_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 No Invert */
-#define BITM_PINT_INV_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 No Invert */
-#define BITM_PINT_INV_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 No Invert */
-#define BITM_PINT_INV_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 No Invert */
-#define BITM_PINT_INV_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 No Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_PINSTATE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_PINSTATE_PIQ31             31                               /* Pin Interrupt 31 State */
-#define BITP_PINT_PINSTATE_PIQ30             30                               /* Pin Interrupt 30 State */
-#define BITP_PINT_PINSTATE_PIQ29             29                               /* Pin Interrupt 29 State */
-#define BITP_PINT_PINSTATE_PIQ28             28                               /* Pin Interrupt 28 State */
-#define BITP_PINT_PINSTATE_PIQ27             27                               /* Pin Interrupt 27 State */
-#define BITP_PINT_PINSTATE_PIQ26             26                               /* Pin Interrupt 26 State */
-#define BITP_PINT_PINSTATE_PIQ25             25                               /* Pin Interrupt 25 State */
-#define BITP_PINT_PINSTATE_PIQ24             24                               /* Pin Interrupt 24 State */
-#define BITP_PINT_PINSTATE_PIQ23             23                               /* Pin Interrupt 23 State */
-#define BITP_PINT_PINSTATE_PIQ22             22                               /* Pin Interrupt 22 State */
-#define BITP_PINT_PINSTATE_PIQ21             21                               /* Pin Interrupt 21 State */
-#define BITP_PINT_PINSTATE_PIQ20             20                               /* Pin Interrupt 20 State */
-#define BITP_PINT_PINSTATE_PIQ19             19                               /* Pin Interrupt 19 State */
-#define BITP_PINT_PINSTATE_PIQ18             18                               /* Pin Interrupt 18 State */
-#define BITP_PINT_PINSTATE_PIQ17             17                               /* Pin Interrupt 17 State */
-#define BITP_PINT_PINSTATE_PIQ16             16                               /* Pin Interrupt 16 State */
-#define BITP_PINT_PINSTATE_PIQ15             15                               /* Pin Interrupt 15 State */
-#define BITP_PINT_PINSTATE_PIQ14             14                               /* Pin Interrupt 14 State */
-#define BITP_PINT_PINSTATE_PIQ13             13                               /* Pin Interrupt 13 State */
-#define BITP_PINT_PINSTATE_PIQ12             12                               /* Pin Interrupt 12 State */
-#define BITP_PINT_PINSTATE_PIQ11             11                               /* Pin Interrupt 11 State */
-#define BITP_PINT_PINSTATE_PIQ10             10                               /* Pin Interrupt 10 State */
-#define BITP_PINT_PINSTATE_PIQ9               9                               /* Pin Interrupt 9 State */
-#define BITP_PINT_PINSTATE_PIQ8               8                               /* Pin Interrupt 8 State */
-#define BITP_PINT_PINSTATE_PIQ7               7                               /* Pin Interrupt 7 State */
-#define BITP_PINT_PINSTATE_PIQ6               6                               /* Pin Interrupt 6 State */
-#define BITP_PINT_PINSTATE_PIQ5               5                               /* Pin Interrupt 5 State */
-#define BITP_PINT_PINSTATE_PIQ4               4                               /* Pin Interrupt 4 State */
-#define BITP_PINT_PINSTATE_PIQ3               3                               /* Pin Interrupt 3 State */
-#define BITP_PINT_PINSTATE_PIQ2               2                               /* Pin Interrupt 2 State */
-#define BITP_PINT_PINSTATE_PIQ1               1                               /* Pin Interrupt 1 State */
-#define BITP_PINT_PINSTATE_PIQ0               0                               /* Pin Interrupt 0 State */
-#define BITM_PINT_PINSTATE_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 State */
-#define BITM_PINT_PINSTATE_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 State */
-#define BITM_PINT_PINSTATE_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 State */
-#define BITM_PINT_PINSTATE_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 State */
-#define BITM_PINT_PINSTATE_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 State */
-#define BITM_PINT_PINSTATE_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 State */
-#define BITM_PINT_PINSTATE_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 State */
-#define BITM_PINT_PINSTATE_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 State */
-#define BITM_PINT_PINSTATE_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 State */
-#define BITM_PINT_PINSTATE_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 State */
-#define BITM_PINT_PINSTATE_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 State */
-#define BITM_PINT_PINSTATE_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 State */
-#define BITM_PINT_PINSTATE_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 State */
-#define BITM_PINT_PINSTATE_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 State */
-#define BITM_PINT_PINSTATE_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 State */
-#define BITM_PINT_PINSTATE_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 State */
-#define BITM_PINT_PINSTATE_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 State */
-#define BITM_PINT_PINSTATE_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 State */
-#define BITM_PINT_PINSTATE_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 State */
-#define BITM_PINT_PINSTATE_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 State */
-#define BITM_PINT_PINSTATE_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 State */
-#define BITM_PINT_PINSTATE_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 State */
-#define BITM_PINT_PINSTATE_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 State */
-#define BITM_PINT_PINSTATE_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 State */
-#define BITM_PINT_PINSTATE_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 State */
-#define BITM_PINT_PINSTATE_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 State */
-#define BITM_PINT_PINSTATE_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 State */
-#define BITM_PINT_PINSTATE_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 State */
-#define BITM_PINT_PINSTATE_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 State */
-#define BITM_PINT_PINSTATE_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 State */
-#define BITM_PINT_PINSTATE_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 State */
-#define BITM_PINT_PINSTATE_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_LATCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_LATCH_PIQ31                31                               /* Pin Interrupt 31 Latch */
-#define BITP_PINT_LATCH_PIQ30                30                               /* Pin Interrupt 30 Latch */
-#define BITP_PINT_LATCH_PIQ29                29                               /* Pin Interrupt 29 Latch */
-#define BITP_PINT_LATCH_PIQ28                28                               /* Pin Interrupt 28 Latch */
-#define BITP_PINT_LATCH_PIQ27                27                               /* Pin Interrupt 27 Latch */
-#define BITP_PINT_LATCH_PIQ26                26                               /* Pin Interrupt 26 Latch */
-#define BITP_PINT_LATCH_PIQ25                25                               /* Pin Interrupt 25 Latch */
-#define BITP_PINT_LATCH_PIQ24                24                               /* Pin Interrupt 24 Latch */
-#define BITP_PINT_LATCH_PIQ23                23                               /* Pin Interrupt 23 Latch */
-#define BITP_PINT_LATCH_PIQ22                22                               /* Pin Interrupt 22 Latch */
-#define BITP_PINT_LATCH_PIQ21                21                               /* Pin Interrupt 21 Latch */
-#define BITP_PINT_LATCH_PIQ20                20                               /* Pin Interrupt 20 Latch */
-#define BITP_PINT_LATCH_PIQ19                19                               /* Pin Interrupt 19 Latch */
-#define BITP_PINT_LATCH_PIQ18                18                               /* Pin Interrupt 18 Latch */
-#define BITP_PINT_LATCH_PIQ17                17                               /* Pin Interrupt 17 Latch */
-#define BITP_PINT_LATCH_PIQ16                16                               /* Pin Interrupt 16 Latch */
-#define BITP_PINT_LATCH_PIQ15                15                               /* Pin Interrupt 15 Latch */
-#define BITP_PINT_LATCH_PIQ14                14                               /* Pin Interrupt 14 Latch */
-#define BITP_PINT_LATCH_PIQ13                13                               /* Pin Interrupt 13 Latch */
-#define BITP_PINT_LATCH_PIQ12                12                               /* Pin Interrupt 12 Latch */
-#define BITP_PINT_LATCH_PIQ11                11                               /* Pin Interrupt 11 Latch */
-#define BITP_PINT_LATCH_PIQ10                10                               /* Pin Interrupt 10 Latch */
-#define BITP_PINT_LATCH_PIQ9                  9                               /* Pin Interrupt 9 Latch */
-#define BITP_PINT_LATCH_PIQ8                  8                               /* Pin Interrupt 8 Latch */
-#define BITP_PINT_LATCH_PIQ7                  7                               /* Pin Interrupt 7 Latch */
-#define BITP_PINT_LATCH_PIQ6                  6                               /* Pin Interrupt 6 Latch */
-#define BITP_PINT_LATCH_PIQ5                  5                               /* Pin Interrupt 5 Latch */
-#define BITP_PINT_LATCH_PIQ4                  4                               /* Pin Interrupt 4 Latch */
-#define BITP_PINT_LATCH_PIQ3                  3                               /* Pin Interrupt 3 Latch */
-#define BITP_PINT_LATCH_PIQ2                  2                               /* Pin Interrupt 2 Latch */
-#define BITP_PINT_LATCH_PIQ1                  1                               /* Pin Interrupt 1 Latch */
-#define BITP_PINT_LATCH_PIQ0                  0                               /* Pin Interrupt 0 Latch */
-#define BITM_PINT_LATCH_PIQ31                (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Latch */
-#define BITM_PINT_LATCH_PIQ30                (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Latch */
-#define BITM_PINT_LATCH_PIQ29                (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Latch */
-#define BITM_PINT_LATCH_PIQ28                (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Latch */
-#define BITM_PINT_LATCH_PIQ27                (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Latch */
-#define BITM_PINT_LATCH_PIQ26                (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Latch */
-#define BITM_PINT_LATCH_PIQ25                (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Latch */
-#define BITM_PINT_LATCH_PIQ24                (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Latch */
-#define BITM_PINT_LATCH_PIQ23                (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Latch */
-#define BITM_PINT_LATCH_PIQ22                (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Latch */
-#define BITM_PINT_LATCH_PIQ21                (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Latch */
-#define BITM_PINT_LATCH_PIQ20                (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Latch */
-#define BITM_PINT_LATCH_PIQ19                (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Latch */
-#define BITM_PINT_LATCH_PIQ18                (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Latch */
-#define BITM_PINT_LATCH_PIQ17                (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Latch */
-#define BITM_PINT_LATCH_PIQ16                (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Latch */
-#define BITM_PINT_LATCH_PIQ15                (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Latch */
-#define BITM_PINT_LATCH_PIQ14                (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Latch */
-#define BITM_PINT_LATCH_PIQ13                (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Latch */
-#define BITM_PINT_LATCH_PIQ12                (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Latch */
-#define BITM_PINT_LATCH_PIQ11                (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Latch */
-#define BITM_PINT_LATCH_PIQ10                (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Latch */
-#define BITM_PINT_LATCH_PIQ9                 (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Latch */
-#define BITM_PINT_LATCH_PIQ8                 (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Latch */
-#define BITM_PINT_LATCH_PIQ7                 (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Latch */
-#define BITM_PINT_LATCH_PIQ6                 (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Latch */
-#define BITM_PINT_LATCH_PIQ5                 (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Latch */
-#define BITM_PINT_LATCH_PIQ4                 (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Latch */
-#define BITM_PINT_LATCH_PIQ3                 (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Latch */
-#define BITM_PINT_LATCH_PIQ2                 (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Latch */
-#define BITM_PINT_LATCH_PIQ1                 (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Latch */
-#define BITM_PINT_LATCH_PIQ0                 (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Latch */
-
-/* ==================================================
-        Static Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        SMC0
-   ========================= */
-#define REG_SMC0_GCTL                   0xFFC16004         /* SMC0 Grant Control Register */
-#define REG_SMC0_GSTAT                  0xFFC16008         /* SMC0 Grant Status Register */
-#define REG_SMC0_B0CTL                  0xFFC1600C         /* SMC0 Bank 0 Control Register */
-#define REG_SMC0_B0TIM                  0xFFC16010         /* SMC0 Bank 0 Timing Register */
-#define REG_SMC0_B0ETIM                 0xFFC16014         /* SMC0 Bank 0 Extended Timing Register */
-#define REG_SMC0_B1CTL                  0xFFC1601C         /* SMC0 Bank 1 Control Register */
-#define REG_SMC0_B1TIM                  0xFFC16020         /* SMC0 Bank 1 Timing Register */
-#define REG_SMC0_B1ETIM                 0xFFC16024         /* SMC0 Bank 1 Extended Timing Register */
-#define REG_SMC0_B2CTL                  0xFFC1602C         /* SMC0 Bank 2 Control Register */
-#define REG_SMC0_B2TIM                  0xFFC16030         /* SMC0 Bank 2 Timing Register */
-#define REG_SMC0_B2ETIM                 0xFFC16034         /* SMC0 Bank 2 Extended Timing Register */
-#define REG_SMC0_B3CTL                  0xFFC1603C         /* SMC0 Bank 3 Control Register */
-#define REG_SMC0_B3TIM                  0xFFC16040         /* SMC0 Bank 3 Timing Register */
-#define REG_SMC0_B3ETIM                 0xFFC16044         /* SMC0 Bank 3 Extended Timing Register */
-
-/* =========================
-        SMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GCTL_BGDIS                   4                               /* Bus Grant Disable */
-#define BITM_SMC_GCTL_BGDIS                  (_ADI_MSK(0x00000010,uint32_t))  /* Bus Grant Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GSTAT_BGHSTAT                2                               /* Bus Grant Hold Status */
-#define BITP_SMC_GSTAT_BRQSTAT                1                               /* Bus Request Status */
-#define BITP_SMC_GSTAT_BGSTAT                 0                               /* Bus Grant Status */
-#define BITM_SMC_GSTAT_BGHSTAT               (_ADI_MSK(0x00000004,uint32_t))  /* Bus Grant Hold Status */
-#define BITM_SMC_GSTAT_BRQSTAT               (_ADI_MSK(0x00000002,uint32_t))  /* Bus Request Status */
-#define BITM_SMC_GSTAT_BGSTAT                (_ADI_MSK(0x00000001,uint32_t))  /* Bus Grant Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B0CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B0CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B0CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B0CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B0CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B0CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B0CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B0CTL_EN                     0                               /* Bank 0 Enable */
-#define BITM_SMC_B0CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B0CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B0CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B0CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B0CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B0CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B0CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B0CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B0CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B0TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B0TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B0TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B0TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B0TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B0TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B0TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B0TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B0TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B0TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B0TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B0ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B0ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B0ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B0ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B0ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B0ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B0ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B0ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B0ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B1CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B1CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B1CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B1CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B1CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B1CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B1CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B1CTL_EN                     0                               /* Bank 1 Enable */
-#define BITM_SMC_B1CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B1CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B1CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B1CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B1CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B1CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B1CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B1CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B1CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 1 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B1TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B1TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B1TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B1TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B1TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B1TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B1TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B1TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B1TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B1TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B1TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B1ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B1ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B1ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B1ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B1ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B1ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B1ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B1ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B1ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B2CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B2CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B2CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B2CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B2CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B2CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B2CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B2CTL_EN                     0                               /* Bank 2 Enable */
-#define BITM_SMC_B2CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B2CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B2CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B2CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B2CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B2CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B2CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B2CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B2CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 2 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B2TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B2TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B2TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B2TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B2TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B2TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B2TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B2TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B2TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B2TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B2TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B2ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B2ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B2ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B2ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B2ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B2ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B2ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B2ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B2ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B3CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B3CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B3CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B3CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B3CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B3CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B3CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B3CTL_EN                     0                               /* Bank 3 Enable */
-#define BITM_SMC_B3CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B3CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B3CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B3CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B3CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B3CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B3CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B3CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B3CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 3 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B3TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B3TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B3TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B3TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B3TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B3TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B3TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B3TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B3TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B3TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B3TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B3ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B3ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B3ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B3ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B3ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B3ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B3ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B3ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B3ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ==================================================
-        Watch Dog Timer Unit Registers
-   ================================================== */
-
-/* =========================
-        WDOG0
-   ========================= */
-#define REG_WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
-#define REG_WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
-#define REG_WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG1
-   ========================= */
-#define REG_WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
-#define REG_WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
-#define REG_WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WDOG_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WDOG_CTL_WDRO                   15                               /* Watch Dog Rollover */
-#define BITP_WDOG_CTL_WDEN                    4                               /* Watch Dog Enable */
-
-#define BITM_WDOG_CTL_WDRO                   (_ADI_MSK(0x00008000,uint32_t))  /* Watch Dog Rollover */
-#define ENUM_WDOG_CTL_WDTEXP                 (_ADI_MSK(0x00008000,uint32_t))  /* WDRO: WDT has expired */
-#define BITM_WDOG_CTL_WDEN                   (_ADI_MSK(0x00000FF0,uint32_t))  /* Watch Dog Enable */
-
-/* ==================================================
-        EPPI Registers
-   ================================================== */
-
-/* =========================
-        EPPI0
-   ========================= */
-#define REG_EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
-#define REG_EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
-#define REG_EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
-#define REG_EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
-#define REG_EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
-#define REG_EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
-#define REG_EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
-#define REG_EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
-#define REG_EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
-#define REG_EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
-#define REG_EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
-#define REG_EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
-#define REG_EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
-
-/* =========================
-        EPPI1
-   ========================= */
-#define REG_EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
-#define REG_EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
-#define REG_EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
-#define REG_EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
-#define REG_EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
-#define REG_EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
-#define REG_EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
-#define REG_EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
-#define REG_EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
-#define REG_EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
-#define REG_EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
-#define REG_EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
-#define REG_EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
-
-/* =========================
-        EPPI2
-   ========================= */
-#define REG_EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
-#define REG_EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
-#define REG_EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
-#define REG_EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
-#define REG_EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
-#define REG_EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
-#define REG_EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
-#define REG_EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
-#define REG_EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
-#define REG_EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
-#define REG_EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
-#define REG_EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
-#define REG_EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
-
-/* =========================
-        EPPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_STAT_FLD                   15                               /* Current Field Received by EPPI */
-#define BITP_EPPI_STAT_ERRDET                14                               /* Preamble Error Detected */
-#define BITP_EPPI_STAT_PXPERR                 7                               /* PxP Ready Error */
-#define BITP_EPPI_STAT_ERRNCOR                6                               /* Preamble Error Not Corrected */
-#define BITP_EPPI_STAT_FTERRUNDR              5                               /* Frame Track Underflow */
-#define BITP_EPPI_STAT_FTERROVR               4                               /* Frame Track Overflow */
-#define BITP_EPPI_STAT_LTERRUNDR              3                               /* Line Track Underflow */
-#define BITP_EPPI_STAT_LTERROVR               2                               /* Line Track Overflow */
-#define BITP_EPPI_STAT_YFIFOERR               1                               /* Luma FIFO Error */
-#define BITP_EPPI_STAT_CFIFOERR               0                               /* Chroma FIFO Error */
-
-#define BITM_EPPI_STAT_FLD                   (_ADI_MSK(0x00008000,uint32_t))  /* Current Field Received by EPPI */
-#define ENUM_EPPI_STAT_FIELD1                (_ADI_MSK(0x00000000,uint32_t))  /* FLD: Field 1 */
-#define ENUM_EPPI_STAT_FIELD2                (_ADI_MSK(0x00008000,uint32_t))  /* FLD: Field 2 */
-
-#define BITM_EPPI_STAT_ERRDET                (_ADI_MSK(0x00004000,uint32_t))  /* Preamble Error Detected */
-#define ENUM_EPPI_STAT_NO_PRERR              (_ADI_MSK(0x00000000,uint32_t))  /* ERRDET: No preamble error detected */
-#define ENUM_EPPI_STAT_PRERR                 (_ADI_MSK(0x00004000,uint32_t))  /* ERRDET: Preamble error detected */
-#define BITM_EPPI_STAT_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error */
-
-#define BITM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* Preamble Error Not Corrected */
-#define ENUM_EPPI_STAT_NO_ERRNCOR            (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: No uncorrected preamble error has occurred */
-#define ENUM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Preamble error detected but not corrected */
-
-#define BITM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow */
-#define ENUM_EPPI_STAT_NO_FTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow */
-#define ENUM_EPPI_STAT_NO_FTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow */
-#define ENUM_EPPI_STAT_NO_LTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow */
-#define ENUM_EPPI_STAT_NO_LTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* Luma FIFO Error */
-#define ENUM_EPPI_STAT_NO_YFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Error Occurred */
-
-#define BITM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* Chroma FIFO Error */
-#define ENUM_EPPI_STAT_NO_CFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HCNT_VALUE                  0                               /* Horizontal Transfer Count */
-#define BITM_EPPI_HCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HDLY_VALUE                  0                               /* Horizontal Delay Count */
-#define BITM_EPPI_HDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VCNT_VALUE                  0                               /* Vertical Transfer Count */
-#define BITM_EPPI_VCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VDLY_VALUE                  0                               /* Vertical Delay Count */
-#define BITM_EPPI_VDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FRAME                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FRAME_VALUE                 0                               /* Lines Per Frame */
-#define BITM_EPPI_FRAME_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lines Per Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_LINE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_LINE_VALUE                  0                               /* Samples Per Line */
-#define BITM_EPPI_LINE_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Samples Per Line */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CLKDIV                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CLKDIV_VALUE                0                               /* Internal Clock Divider */
-#define BITM_EPPI_CLKDIV_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* Internal Clock Divider */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL_CLKGATEN               31                               /* Clock Gating Enable */
-#define BITP_EPPI_CTL_MUXSEL                 30                               /* MUX Select */
-#define BITP_EPPI_CTL_DMAFINEN               29                               /* DMA Finish Enable */
-#define BITP_EPPI_CTL_DMACFG                 28                               /* One or Two DMA Channels Mode */
-#define BITP_EPPI_CTL_RGBFMTEN               27                               /* RGB Formatting Enable */
-#define BITP_EPPI_CTL_SPLTWRD                26                               /* Split Word */
-#define BITP_EPPI_CTL_SUBSPLTODD             25                               /* Sub-Split Odd Samples */
-#define BITP_EPPI_CTL_SPLTEO                 24                               /* Split Even and Odd Data Samples */
-#define BITP_EPPI_CTL_SWAPEN                 23                               /* Swap Enable */
-#define BITP_EPPI_CTL_PACKEN                 22                               /* Pack/Unpack Enable */
-#define BITP_EPPI_CTL_SKIPEO                 21                               /* Skip Even or Odd */
-#define BITP_EPPI_CTL_SKIPEN                 20                               /* Skip Enable */
-#define BITP_EPPI_CTL_DMIRR                  19                               /* Data Mirroring */
-#define BITP_EPPI_CTL_DLEN                   16                               /* Data Length */
-#define BITP_EPPI_CTL_POLS                   14                               /* Frame Sync Polarity */
-#define BITP_EPPI_CTL_POLC                   12                               /* Clock Polarity */
-#define BITP_EPPI_CTL_SIGNEXT                11                               /* Sign Extension */
-#define BITP_EPPI_CTL_IFSGEN                 10                               /* Internal Frame Sync Generation */
-#define BITP_EPPI_CTL_ICLKGEN                 9                               /* Internal Clock Generation */
-#define BITP_EPPI_CTL_BLANKGEN                8                               /* king Generation (ITU Output Mode) */
-#define BITP_EPPI_CTL_ITUTYPE                 7                               /* ITU Interlace or Progressive */
-#define BITP_EPPI_CTL_FLDSEL                  6                               /* Field Select/Trigger */
-#define BITP_EPPI_CTL_FSCFG                   4                               /* Frame Sync Configuration */
-#define BITP_EPPI_CTL_XFRTYPE                 2                               /* Transfer Type ( Operating Mode) */
-#define BITP_EPPI_CTL_DIR                     1                               /* PPI Direction */
-#define BITP_EPPI_CTL_EN                      0                               /* PPI Enable */
-
-#define BITM_EPPI_CTL_CLKGATEN               (_ADI_MSK(0x80000000,uint32_t))  /* Clock Gating Enable */
-#define ENUM_EPPI_CTL_CLKGATE_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* CLKGATEN: Disable */
-#define ENUM_EPPI_CTL_CLKGATE_EN             (_ADI_MSK(0x80000000,uint32_t))  /* CLKGATEN: Enable */
-
-#define BITM_EPPI_CTL_MUXSEL                 (_ADI_MSK(0x40000000,uint32_t))  /* MUX Select */
-#define ENUM_EPPI_CTL_MUXSEL0                (_ADI_MSK(0x00000000,uint32_t))  /* MUXSEL: Normal Operation */
-#define ENUM_EPPI_CTL_MUXSEL1                (_ADI_MSK(0x40000000,uint32_t))  /* MUXSEL: Multiplexed Operation */
-
-#define BITM_EPPI_CTL_DMAFINEN               (_ADI_MSK(0x20000000,uint32_t))  /* DMA Finish Enable */
-#define ENUM_EPPI_CTL_FINISH_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* DMAFINEN: No Finish Command */
-#define ENUM_EPPI_CTL_FINISH_EN              (_ADI_MSK(0x20000000,uint32_t))  /* DMAFINEN: Enable Send Finish Command */
-
-#define BITM_EPPI_CTL_DMACFG                 (_ADI_MSK(0x10000000,uint32_t))  /* One or Two DMA Channels Mode */
-#define ENUM_EPPI_CTL_DMA1CHAN               (_ADI_MSK(0x00000000,uint32_t))  /* DMACFG: PPI uses one DMA Channel */
-#define ENUM_EPPI_CTL_DMA2CHAN               (_ADI_MSK(0x10000000,uint32_t))  /* DMACFG: PPI uses two DMA Channels */
-
-#define BITM_EPPI_CTL_RGBFMTEN               (_ADI_MSK(0x08000000,uint32_t))  /* RGB Formatting Enable */
-#define ENUM_EPPI_CTL_RGBFMT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RGBFMTEN: Disable RGB Formatted Output */
-#define ENUM_EPPI_CTL_RGBFMT_EN              (_ADI_MSK(0x08000000,uint32_t))  /* RGBFMTEN: Enable RGB Formatted Output */
-
-#define BITM_EPPI_CTL_SPLTWRD                (_ADI_MSK(0x04000000,uint32_t))  /* Split Word */
-#define ENUM_EPPI_CTL_NO_WORDSPLIT           (_ADI_MSK(0x00000000,uint32_t))  /* SPLTWRD: PPI_DATA has (DLEN-1) bits of Y or Cr or Cb */
-#define ENUM_EPPI_CTL_WORDSPLIT              (_ADI_MSK(0x04000000,uint32_t))  /* SPLTWRD: PPI_DATA contains 2 elements per word */
-
-#define BITM_EPPI_CTL_SUBSPLTODD             (_ADI_MSK(0x02000000,uint32_t))  /* Sub-Split Odd Samples */
-#define ENUM_EPPI_CTL_NO_SUBSPLIT            (_ADI_MSK(0x00000000,uint32_t))  /* SUBSPLTODD: Disable */
-#define ENUM_EPPI_CTL_SUBSPLIT_ODD           (_ADI_MSK(0x02000000,uint32_t))  /* SUBSPLTODD: Enable */
-
-#define BITM_EPPI_CTL_SPLTEO                 (_ADI_MSK(0x01000000,uint32_t))  /* Split Even and Odd Data Samples */
-#define ENUM_EPPI_CTL_SPLTEO_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SPLTEO: Do Not Split Samples */
-#define ENUM_EPPI_CTL_SPLTEO_EN              (_ADI_MSK(0x01000000,uint32_t))  /* SPLTEO: Split Even/Odd Samples */
-
-#define BITM_EPPI_CTL_SWAPEN                 (_ADI_MSK(0x00800000,uint32_t))  /* Swap Enable */
-#define ENUM_EPPI_CTL_SWAP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* SWAPEN: Disable */
-#define ENUM_EPPI_CTL_SWAP_EN                (_ADI_MSK(0x00800000,uint32_t))  /* SWAPEN: Enable */
-
-#define BITM_EPPI_CTL_PACKEN                 (_ADI_MSK(0x00400000,uint32_t))  /* Pack/Unpack Enable */
-#define ENUM_EPPI_CTL_PACK_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* PACKEN: Disable */
-#define ENUM_EPPI_CTL_PACK_EN                (_ADI_MSK(0x00400000,uint32_t))  /* PACKEN: Enable */
-
-#define BITM_EPPI_CTL_SKIPEO                 (_ADI_MSK(0x00200000,uint32_t))  /* Skip Even or Odd */
-#define ENUM_EPPI_CTL_SKIPODD                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEO: Skip Odd Samples */
-#define ENUM_EPPI_CTL_SKIPEVEN               (_ADI_MSK(0x00200000,uint32_t))  /* SKIPEO: Skip Even Samples */
-
-#define BITM_EPPI_CTL_SKIPEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Skip Enable */
-#define ENUM_EPPI_CTL_NO_SKIP                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEN: No Samples Skipping */
-#define ENUM_EPPI_CTL_SKIP                   (_ADI_MSK(0x00100000,uint32_t))  /* SKIPEN: Skip Alternate Samples */
-
-#define BITM_EPPI_CTL_DMIRR                  (_ADI_MSK(0x00080000,uint32_t))  /* Data Mirroring */
-#define ENUM_EPPI_CTL_NO_MIRROR              (_ADI_MSK(0x00000000,uint32_t))  /* DMIRR: No Data Mirroring */
-#define ENUM_EPPI_CTL_MIRROR                 (_ADI_MSK(0x00080000,uint32_t))  /* DMIRR: Data Mirroring */
-
-#define BITM_EPPI_CTL_DLEN                   (_ADI_MSK(0x00070000,uint32_t))  /* Data Length */
-#define ENUM_EPPI_CTL_DLEN08                 (_ADI_MSK(0x00000000,uint32_t))  /* DLEN: 8 bits */
-#define ENUM_EPPI_CTL_DLEN10                 (_ADI_MSK(0x00010000,uint32_t))  /* DLEN: 10 bits */
-#define ENUM_EPPI_CTL_DLEN12                 (_ADI_MSK(0x00020000,uint32_t))  /* DLEN: 12 bits */
-#define ENUM_EPPI_CTL_DLEN14                 (_ADI_MSK(0x00030000,uint32_t))  /* DLEN: 14 bits */
-#define ENUM_EPPI_CTL_DLEN16                 (_ADI_MSK(0x00040000,uint32_t))  /* DLEN: 16 bits */
-#define ENUM_EPPI_CTL_DLEN18                 (_ADI_MSK(0x00050000,uint32_t))  /* DLEN: 18 bits */
-#define ENUM_EPPI_CTL_DLEN20                 (_ADI_MSK(0x00060000,uint32_t))  /* DLEN: 20 bits */
-#define ENUM_EPPI_CTL_DLEN24                 (_ADI_MSK(0x00070000,uint32_t))  /* DLEN: 24 bits */
-
-#define BITM_EPPI_CTL_POLS                   (_ADI_MSK(0x0000C000,uint32_t))  /* Frame Sync Polarity */
-#define ENUM_EPPI_CTL_FS1HI_FS2HI            (_ADI_MSK(0x00000000,uint32_t))  /* POLS: FS1 and FS2 are active high */
-#define ENUM_EPPI_CTL_FS1LO_FS2HI            (_ADI_MSK(0x00004000,uint32_t))  /* POLS: FS1 is active low. FS2 is active high */
-#define ENUM_EPPI_CTL_FS1HI_FS2LO            (_ADI_MSK(0x00008000,uint32_t))  /* POLS: FS1 is active high. FS2 is active low */
-#define ENUM_EPPI_CTL_FS1LO_FS2LO            (_ADI_MSK(0x0000C000,uint32_t))  /* POLS: FS1 and FS2 are active low */
-
-#define BITM_EPPI_CTL_POLC                   (_ADI_MSK(0x00003000,uint32_t))  /* Clock Polarity */
-#define ENUM_EPPI_CTL_POLC00                 (_ADI_MSK(0x00000000,uint32_t))  /* POLC: Clock/Sync polarity mode 0 */
-#define ENUM_EPPI_CTL_POLC01                 (_ADI_MSK(0x00001000,uint32_t))  /* POLC: Clock/Sync polarity mode 1 */
-#define ENUM_EPPI_CTL_POLC10                 (_ADI_MSK(0x00002000,uint32_t))  /* POLC: Clock/Sync polarity mode 2 */
-#define ENUM_EPPI_CTL_POLC11                 (_ADI_MSK(0x00003000,uint32_t))  /* POLC: Clock/Sync polarity mode 3 */
-
-#define BITM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* Sign Extension */
-#define ENUM_EPPI_CTL_ZEROFILL               (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Filled */
-#define ENUM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* SIGNEXT: Sign Extended */
-
-#define BITM_EPPI_CTL_IFSGEN                 (_ADI_MSK(0x00000400,uint32_t))  /* Internal Frame Sync Generation */
-#define ENUM_EPPI_CTL_EXTFS                  (_ADI_MSK(0x00000000,uint32_t))  /* IFSGEN: External Frame Sync */
-#define ENUM_EPPI_CTL_INTFS                  (_ADI_MSK(0x00000400,uint32_t))  /* IFSGEN: Internal Frame Sync */
-
-#define BITM_EPPI_CTL_ICLKGEN                (_ADI_MSK(0x00000200,uint32_t))  /* Internal Clock Generation */
-#define ENUM_EPPI_CTL_EXTCLK                 (_ADI_MSK(0x00000000,uint32_t))  /* ICLKGEN: External Clock */
-#define ENUM_EPPI_CTL_INTCLK                 (_ADI_MSK(0x00000200,uint32_t))  /* ICLKGEN: Internal Clock */
-
-#define BITM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* king Generation (ITU Output Mode) */
-#define ENUM_EPPI_CTL_NO_BLANKGEN            (_ADI_MSK(0x00000000,uint32_t))  /* BLANKGEN: Disable */
-#define ENUM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* BLANKGEN: Enable */
-
-#define BITM_EPPI_CTL_ITUTYPE                (_ADI_MSK(0x00000080,uint32_t))  /* ITU Interlace or Progressive */
-#define ENUM_EPPI_CTL_INTERLACED             (_ADI_MSK(0x00000000,uint32_t))  /* ITUTYPE: Interlaced */
-#define ENUM_EPPI_CTL_PROGRESSIVE            (_ADI_MSK(0x00000080,uint32_t))  /* ITUTYPE: Progressive */
-
-#define BITM_EPPI_CTL_FLDSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* Field Select/Trigger */
-#define ENUM_EPPI_CTL_FLDSEL_LO              (_ADI_MSK(0x00000000,uint32_t))  /* FLDSEL: Field Mode 0 */
-#define ENUM_EPPI_CTL_FLDSEL_HI              (_ADI_MSK(0x00000040,uint32_t))  /* FLDSEL: Field Mode 1 */
-
-#define BITM_EPPI_CTL_FSCFG                  (_ADI_MSK(0x00000030,uint32_t))  /* Frame Sync Configuration */
-#define ENUM_EPPI_CTL_SYNC0                  (_ADI_MSK(0x00000000,uint32_t))  /* FSCFG: Sync Mode 0 */
-#define ENUM_EPPI_CTL_SYNC1                  (_ADI_MSK(0x00000010,uint32_t))  /* FSCFG: Sync Mode 1 */
-#define ENUM_EPPI_CTL_SYNC2                  (_ADI_MSK(0x00000020,uint32_t))  /* FSCFG: Sync Mode 2 */
-#define ENUM_EPPI_CTL_SYNC3                  (_ADI_MSK(0x00000030,uint32_t))  /* FSCFG: Sync Mode 3 */
-
-#define BITM_EPPI_CTL_XFRTYPE                (_ADI_MSK(0x0000000C,uint32_t))  /* Transfer Type ( Operating Mode) */
-#define ENUM_EPPI_CTL_ACTIVE656              (_ADI_MSK(0x00000000,uint32_t))  /* XFRTYPE: ITU656 Active Video Only Mode */
-#define ENUM_EPPI_CTL_ENTIRE656              (_ADI_MSK(0x00000004,uint32_t))  /* XFRTYPE: ITU656 Entire Field Mode */
-#define ENUM_EPPI_CTL_VERT656                (_ADI_MSK(0x00000008,uint32_t))  /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define ENUM_EPPI_CTL_NON656                 (_ADI_MSK(0x0000000C,uint32_t))  /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-
-#define BITM_EPPI_CTL_DIR                    (_ADI_MSK(0x00000002,uint32_t))  /* PPI Direction */
-#define ENUM_EPPI_CTL_RXMODE                 (_ADI_MSK(0x00000000,uint32_t))  /* DIR: Receive Mode */
-#define ENUM_EPPI_CTL_TXMODE                 (_ADI_MSK(0x00000002,uint32_t))  /* DIR: Transmit Mode */
-
-#define BITM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* PPI Enable */
-#define ENUM_EPPI_CTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_WLVB                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_WLVB_F2VBAD            24                               /* Field 2 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F2VBBD            16                               /* Field 2 Vertical Blanking Before Data */
-#define BITP_EPPI_FS2_WLVB_F1VBAD             8                               /* Field 1 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F1VBBD             0                               /* Field 1 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F2VBAD            (_ADI_MSK(0xFF000000,uint32_t))  /* Field 2 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F2VBBD            (_ADI_MSK(0x00FF0000,uint32_t))  /* Field 2 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F1VBAD            (_ADI_MSK(0x0000FF00,uint32_t))  /* Field 1 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F1VBBD            (_ADI_MSK(0x000000FF,uint32_t))  /* Field 1 Vertical Blanking Before Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_PALPF                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_PALPF_F2ACT            16                               /* Field 2 Active */
-#define BITP_EPPI_FS2_PALPF_F1ACT             0                               /* Field 1 Active */
-#define BITM_EPPI_FS2_PALPF_F2ACT            (_ADI_MSK(0xFFFF0000,uint32_t))  /* Field 2 Active */
-#define BITM_EPPI_FS2_PALPF_F1ACT            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Field 1 Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_IMSK_PXPERR                 7                               /* PxP Ready Error Interrupt Mask */
-#define BITP_EPPI_IMSK_ERRNCOR                6                               /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERRUNDR              5                               /* Frame Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERROVR               4                               /* Frame Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERRUNDR              3                               /* Line Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERROVR               2                               /* Line Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_YFIFOERR               1                               /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_CFIFOERR               0                               /* CFIFO Underflow or Overflow Error Interrupt Mask */
-
-#define BITM_EPPI_IMSK_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_PXPERR_UMSK           (_ADI_MSK(0x00000000,uint32_t))  /* PXPERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_PXPERR_MSK            (_ADI_MSK(0x00000080,uint32_t))  /* PXPERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define ENUM_EPPI_IMSK_ERRNCOR_UMSK          (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_ERRNCOR_MSK           (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERRUNDR_MSK         (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERROVR_MSK          (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERRUNDR_MSK         (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERROVR_MSK          (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_YFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_YFIFOERR_MSK          (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_CFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_CFIFOERR_MSK          (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Mask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_ODDCLIP                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_ODDCLIP_HIGHODD            16                               /* High Odd Clipping Threshold (Chroma Data) */
-#define BITP_EPPI_ODDCLIP_LOWODD              0                               /* Low Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_HIGHODD            (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_LOWODD             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Odd Clipping Threshold (Chroma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_EVENCLIP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_EVENCLIP_HIGHEVEN          16                               /* High Even Clipping Threshold (Luma Data) */
-#define BITP_EPPI_EVENCLIP_LOWEVEN            0                               /* Low Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_HIGHEVEN          (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_LOWEVEN           (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Even Clipping Threshold (Luma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL2_FS1FINEN               1                               /* HSYNC Finish Enable */
-
-#define BITM_EPPI_CTL2_FS1FINEN              (_ADI_MSK(0x00000002,uint32_t))  /* HSYNC Finish Enable */
-#define ENUM_EPPI_CTL2_FS2FIN_EN             (_ADI_MSK(0x00000000,uint32_t))  /* FS1FINEN: Finish sent after frame RX done */
-#define ENUM_EPPI_CTL2_FS1FIN_EN             (_ADI_MSK(0x00000002,uint32_t))  /* FS1FINEN: Finish sent after frame/line RX done */
-
-/* ==================================================
-        Pulse-Width Modulator Registers
-   ================================================== */
-
-/* =========================
-        PWM0
-   ========================= */
-#define REG_PWM0_CTL                    0xFFC1B000         /* PWM0 Control Register */
-#define REG_PWM0_CHANCFG                0xFFC1B004         /* PWM0 Channel Config Register */
-#define REG_PWM0_TRIPCFG                0xFFC1B008         /* PWM0 Trip Config Register */
-#define REG_PWM0_STAT                   0xFFC1B00C         /* PWM0 Status Register */
-#define REG_PWM0_IMSK                   0xFFC1B010         /* PWM0 Interrupt Mask Register */
-#define REG_PWM0_ILAT                   0xFFC1B014         /* PWM0 Interrupt Latch Register */
-#define REG_PWM0_CHOPCFG                0xFFC1B018         /* PWM0 Chop Configuration Register */
-#define REG_PWM0_DT                     0xFFC1B01C         /* PWM0 Dead Time Register */
-#define REG_PWM0_SYNC_WID               0xFFC1B020         /* PWM0 Sync Pulse Width Register */
-#define REG_PWM0_TM0                    0xFFC1B024         /* PWM0 Timer 0 Period Register */
-#define REG_PWM0_TM1                    0xFFC1B028         /* PWM0 Timer 1 Period Register */
-#define REG_PWM0_TM2                    0xFFC1B02C         /* PWM0 Timer 2 Period Register */
-#define REG_PWM0_TM3                    0xFFC1B030         /* PWM0 Timer 3 Period Register */
-#define REG_PWM0_TM4                    0xFFC1B034         /* PWM0 Timer 4 Period Register */
-#define REG_PWM0_DLYA                   0xFFC1B038         /* PWM0 Channel A Delay Register */
-#define REG_PWM0_DLYB                   0xFFC1B03C         /* PWM0 Channel B Delay Register */
-#define REG_PWM0_DLYC                   0xFFC1B040         /* PWM0 Channel C Delay Register */
-#define REG_PWM0_DLYD                   0xFFC1B044         /* PWM0 Channel D Delay Register */
-#define REG_PWM0_ACTL                   0xFFC1B048         /* PWM0 Channel A Control Register */
-#define REG_PWM0_AH0                    0xFFC1B04C         /* PWM0 Channel A-High Duty-0 Register */
-#define REG_PWM0_AH1                    0xFFC1B050         /* PWM0 Channel A-High Duty-1 Register */
-#define REG_PWM0_AL0                    0xFFC1B05C         /* PWM0 Channel A-Low Duty-0 Register */
-#define REG_PWM0_AL1                    0xFFC1B060         /* PWM0 Channel A-Low Duty-1 Register */
-#define REG_PWM0_BCTL                   0xFFC1B064         /* PWM0 Channel B Control Register */
-#define REG_PWM0_BH0                    0xFFC1B068         /* PWM0 Channel B-High Duty-0 Register */
-#define REG_PWM0_BH1                    0xFFC1B06C         /* PWM0 Channel B-High Duty-1 Register */
-#define REG_PWM0_BL0                    0xFFC1B078         /* PWM0 Channel B-Low Duty-0 Register */
-#define REG_PWM0_BL1                    0xFFC1B07C         /* PWM0 Channel B-Low Duty-1 Register */
-#define REG_PWM0_CCTL                   0xFFC1B080         /* PWM0 Channel C Control Register */
-#define REG_PWM0_CH0                    0xFFC1B084         /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM0_CH1                    0xFFC1B088         /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM0_CL0                    0xFFC1B094         /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM0_CL1                    0xFFC1B098         /* PWM0 Channel C-Low Duty-1 Register */
-#define REG_PWM0_DCTL                   0xFFC1B09C         /* PWM0 Channel D Control Register */
-#define REG_PWM0_DH0                    0xFFC1B0A0         /* PWM0 Channel D-High Duty-0 Register */
-#define REG_PWM0_DH1                    0xFFC1B0A4         /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM0_DL0                    0xFFC1B0B0         /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM0_DL1                    0xFFC1B0B4         /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM1
-   ========================= */
-#define REG_PWM1_CTL                    0xFFC1B400         /* PWM1 Control Register */
-#define REG_PWM1_CHANCFG                0xFFC1B404         /* PWM1 Channel Config Register */
-#define REG_PWM1_TRIPCFG                0xFFC1B408         /* PWM1 Trip Config Register */
-#define REG_PWM1_STAT                   0xFFC1B40C         /* PWM1 Status Register */
-#define REG_PWM1_IMSK                   0xFFC1B410         /* PWM1 Interrupt Mask Register */
-#define REG_PWM1_ILAT                   0xFFC1B414         /* PWM1 Interrupt Latch Register */
-#define REG_PWM1_CHOPCFG                0xFFC1B418         /* PWM1 Chop Configuration Register */
-#define REG_PWM1_DT                     0xFFC1B41C         /* PWM1 Dead Time Register */
-#define REG_PWM1_SYNC_WID               0xFFC1B420         /* PWM1 Sync Pulse Width Register */
-#define REG_PWM1_TM0                    0xFFC1B424         /* PWM1 Timer 0 Period Register */
-#define REG_PWM1_TM1                    0xFFC1B428         /* PWM1 Timer 1 Period Register */
-#define REG_PWM1_TM2                    0xFFC1B42C         /* PWM1 Timer 2 Period Register */
-#define REG_PWM1_TM3                    0xFFC1B430         /* PWM1 Timer 3 Period Register */
-#define REG_PWM1_TM4                    0xFFC1B434         /* PWM1 Timer 4 Period Register */
-#define REG_PWM1_DLYA                   0xFFC1B438         /* PWM1 Channel A Delay Register */
-#define REG_PWM1_DLYB                   0xFFC1B43C         /* PWM1 Channel B Delay Register */
-#define REG_PWM1_DLYC                   0xFFC1B440         /* PWM1 Channel C Delay Register */
-#define REG_PWM1_DLYD                   0xFFC1B444         /* PWM1 Channel D Delay Register */
-#define REG_PWM1_ACTL                   0xFFC1B448         /* PWM1 Channel A Control Register */
-#define REG_PWM1_AH0                    0xFFC1B44C         /* PWM1 Channel A-High Duty-0 Register */
-#define REG_PWM1_AH1                    0xFFC1B450         /* PWM1 Channel A-High Duty-1 Register */
-#define REG_PWM1_AL0                    0xFFC1B45C         /* PWM1 Channel A-Low Duty-0 Register */
-#define REG_PWM1_AL1                    0xFFC1B460         /* PWM1 Channel A-Low Duty-1 Register */
-#define REG_PWM1_BCTL                   0xFFC1B464         /* PWM1 Channel B Control Register */
-#define REG_PWM1_BH0                    0xFFC1B468         /* PWM1 Channel B-High Duty-0 Register */
-#define REG_PWM1_BH1                    0xFFC1B46C         /* PWM1 Channel B-High Duty-1 Register */
-#define REG_PWM1_BL0                    0xFFC1B478         /* PWM1 Channel B-Low Duty-0 Register */
-#define REG_PWM1_BL1                    0xFFC1B47C         /* PWM1 Channel B-Low Duty-1 Register */
-#define REG_PWM1_CCTL                   0xFFC1B480         /* PWM1 Channel C Control Register */
-#define REG_PWM1_CH0                    0xFFC1B484         /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM1_CH1                    0xFFC1B488         /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM1_CL0                    0xFFC1B494         /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM1_CL1                    0xFFC1B498         /* PWM1 Channel C-Low Duty-1 Register */
-#define REG_PWM1_DCTL                   0xFFC1B49C         /* PWM1 Channel D Control Register */
-#define REG_PWM1_DH0                    0xFFC1B4A0         /* PWM1 Channel D-High Duty-0 Register */
-#define REG_PWM1_DH1                    0xFFC1B4A4         /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM1_DL0                    0xFFC1B4B0         /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM1_DL1                    0xFFC1B4B4         /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CTL_INTSYNCREF              18                               /* Timer reference for Internal Sync */
-#define BITP_PWM_CTL_EXTSYNCSEL              17                               /* External Sync Select */
-#define BITP_PWM_CTL_EXTSYNC                 16                               /* External Sync */
-#define BITP_PWM_CTL_DLYDEN                   7                               /* Enable Delay Counter for Channel D */
-#define BITP_PWM_CTL_DLYCEN                   6                               /* Enable Delay Counter for Channel C */
-#define BITP_PWM_CTL_DLYBEN                   5                               /* Enable Delay Counter for Channel B */
-#define BITP_PWM_CTL_DLYAEN                   4                               /* Enable Delay Counter for Channel A */
-#define BITP_PWM_CTL_SWTRIP                   2                               /* Software Trip */
-#define BITP_PWM_CTL_EMURUN                   1                               /* Output Behavior During Emulation Mode */
-#define BITP_PWM_CTL_GLOBEN                   0                               /* Module Enable */
-
-#define BITM_PWM_CTL_INTSYNCREF              (_ADI_MSK(0x001C0000,uint32_t))  /* Timer reference for Internal Sync */
-#define ENUM_PWM_CTL_INTSYNC_0               (_ADI_MSK(0x00000000,uint32_t))  /* INTSYNCREF: PWMTMR0 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_1               (_ADI_MSK(0x00040000,uint32_t))  /* INTSYNCREF: PWMTMR1 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_2               (_ADI_MSK(0x00080000,uint32_t))  /* INTSYNCREF: PWMTMR2 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_3               (_ADI_MSK(0x000C0000,uint32_t))  /* INTSYNCREF: PWMTMR3 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_4               (_ADI_MSK(0x00100000,uint32_t))  /* INTSYNCREF: PWMTMR4 provides sync reference */
-
-#define BITM_PWM_CTL_EXTSYNCSEL              (_ADI_MSK(0x00020000,uint32_t))  /* External Sync Select */
-#define ENUM_PWM_CTL_EXTSYNC_ASYNC           (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNCSEL: Asynchronous External Sync */
-#define ENUM_PWM_CTL_EXTSYNC_SYNC            (_ADI_MSK(0x00020000,uint32_t))  /* EXTSYNCSEL: Synchronous External Sync */
-
-#define BITM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* External Sync */
-#define ENUM_PWM_CTL_INTSYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNC: Internal sync used */
-#define ENUM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* EXTSYNC: External sync used */
-
-#define BITM_PWM_CTL_DLYDEN                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Delay Counter for Channel D */
-#define ENUM_PWM_CTL_DLYD_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYDEN: Disable */
-#define ENUM_PWM_CTL_DLYD_EN                 (_ADI_MSK(0x00000080,uint32_t))  /* DLYDEN: Enable */
-
-#define BITM_PWM_CTL_DLYCEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Delay Counter for Channel C */
-#define ENUM_PWM_CTL_DLYC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYCEN: Disable */
-#define ENUM_PWM_CTL_DLYC_EN                 (_ADI_MSK(0x00000040,uint32_t))  /* DLYCEN: Enable */
-
-#define BITM_PWM_CTL_DLYBEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Delay Counter for Channel B */
-#define ENUM_PWM_CTL_DLYB_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYBEN: Disable */
-#define ENUM_PWM_CTL_DLYB_EN                 (_ADI_MSK(0x00000020,uint32_t))  /* DLYBEN: Enable */
-
-#define BITM_PWM_CTL_DLYAEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable Delay Counter for Channel A */
-#define ENUM_PWM_CTL_DLYA_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYAEN: Disable */
-#define ENUM_PWM_CTL_DLYA_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* DLYAEN: Enable */
-
-#define BITM_PWM_CTL_SWTRIP                  (_ADI_MSK(0x00000004,uint32_t))  /* Software Trip */
-#define ENUM_PWM_CTL_FORCE_TRIP              (_ADI_MSK(0x00000004,uint32_t))  /* SWTRIP: Force a Fault Trip Condition */
-
-#define BITM_PWM_CTL_EMURUN                  (_ADI_MSK(0x00000002,uint32_t))  /* Output Behavior During Emulation Mode */
-#define ENUM_PWM_CTL_EMURUN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* EMURUN: Disable Outputs */
-#define ENUM_PWM_CTL_EMURUN_EN               (_ADI_MSK(0x00000002,uint32_t))  /* EMURUN: Enable Outputs */
-
-#define BITM_PWM_CTL_GLOBEN                  (_ADI_MSK(0x00000001,uint32_t))  /* Module Enable */
-#define ENUM_PWM_CTL_PWM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* GLOBEN: Disable */
-#define ENUM_PWM_CTL_PWM_EN                  (_ADI_MSK(0x00000001,uint32_t))  /* GLOBEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHANCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHANCFG_ENCHOPDL            30                               /* Channel D Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLDL               29                               /* Channel D low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPDH            27                               /* Channel D Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLDH               26                               /* Channel D High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSD             25                               /* Channel D Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRD             24                               /* Channel D Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPCL            22                               /* Channel C Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLCL               21                               /* Channel C low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPCH            19                               /* Channel C Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLCH               18                               /* Channel C High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSC             17                               /* Channel C Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRC             16                               /* Channel C Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPBL            14                               /* Channel B Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLBL               13                               /* Channel B low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPBH            11                               /* Channel B Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLBH               10                               /* Channel B High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSB              9                               /* Channel B Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRB              8                               /* Channel B Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPAL             6                               /* Channel A Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLAL                5                               /* Channel A low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPAH             3                               /* Channel A Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLAH                2                               /* Channel A High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSA              1                               /* Channel A Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRA              0                               /* Channel A Timer Reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPDL            (_ADI_MSK(0x40000000,uint32_t))  /* Channel D Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDL: Disable Chopping Channel D Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_EN           (_ADI_MSK(0x40000000,uint32_t))  /* ENCHOPDL: Enable Chopping Channel D Low Side */
-
-#define BITM_PWM_CHANCFG_POLDL               (_ADI_MSK(0x20000000,uint32_t))  /* Channel D low side Polarity */
-#define ENUM_PWM_CHANCFG_DL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDL: Active Low */
-#define ENUM_PWM_CHANCFG_DL_ACTHI            (_ADI_MSK(0x20000000,uint32_t))  /* POLDL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPDH            (_ADI_MSK(0x08000000,uint32_t))  /* Channel D Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDH: Disable Chopping Channel D High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_EN           (_ADI_MSK(0x08000000,uint32_t))  /* ENCHOPDH: Enable Chopping Channel D High Side */
-
-#define BITM_PWM_CHANCFG_POLDH               (_ADI_MSK(0x04000000,uint32_t))  /* Channel D High side Polarity */
-#define ENUM_PWM_CHANCFG_DH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDH: Active Low */
-#define ENUM_PWM_CHANCFG_DH_ACTHI            (_ADI_MSK(0x04000000,uint32_t))  /* POLDH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSD             (_ADI_MSK(0x02000000,uint32_t))  /* Channel D Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOD_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSD: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOD_IND             (_ADI_MSK(0x02000000,uint32_t))  /* MODELSD: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRD             (_ADI_MSK(0x01000000,uint32_t))  /* Channel D Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRD: PWMTMR0 is Channel D reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_1           (_ADI_MSK(0x01000000,uint32_t))  /* REFTMRD: PWMTMR1 is Channel D reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPCL            (_ADI_MSK(0x00400000,uint32_t))  /* Channel C Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCL: Disable Chopping Channel C Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_EN           (_ADI_MSK(0x00400000,uint32_t))  /* ENCHOPCL: Enable Chopping Channel C Low Side */
-
-#define BITM_PWM_CHANCFG_POLCL               (_ADI_MSK(0x00200000,uint32_t))  /* Channel C low side Polarity */
-#define ENUM_PWM_CHANCFG_CL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCL: Active Low */
-#define ENUM_PWM_CHANCFG_CL_ACTHI            (_ADI_MSK(0x00200000,uint32_t))  /* POLCL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPCH            (_ADI_MSK(0x00080000,uint32_t))  /* Channel C Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCH: Disable Chopping Channel C High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_EN           (_ADI_MSK(0x00080000,uint32_t))  /* ENCHOPCH: Enable Chopping Channel C High Side */
-
-#define BITM_PWM_CHANCFG_POLCH               (_ADI_MSK(0x00040000,uint32_t))  /* Channel C High side Polarity */
-#define ENUM_PWM_CHANCFG_CH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCH: Active Low */
-#define ENUM_PWM_CHANCFG_CH_ACTHI            (_ADI_MSK(0x00040000,uint32_t))  /* POLCH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSC             (_ADI_MSK(0x00020000,uint32_t))  /* Channel C Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOC_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSC: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOC_IND             (_ADI_MSK(0x00020000,uint32_t))  /* MODELSC: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRC             (_ADI_MSK(0x00010000,uint32_t))  /* Channel C Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRC: PWMTMR0 is Channel C reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_1           (_ADI_MSK(0x00010000,uint32_t))  /* REFTMRC: PWMTMR1 is Channel C reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPBL            (_ADI_MSK(0x00004000,uint32_t))  /* Channel B Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBL: Disable Chopping Channel B Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_EN           (_ADI_MSK(0x00004000,uint32_t))  /* ENCHOPBL: Enable Chopping Channel B Low Side */
-
-#define BITM_PWM_CHANCFG_POLBL               (_ADI_MSK(0x00002000,uint32_t))  /* Channel B low side Polarity */
-#define ENUM_PWM_CHANCFG_BL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBL: Active Low */
-#define ENUM_PWM_CHANCFG_BL_ACTHI            (_ADI_MSK(0x00002000,uint32_t))  /* POLBL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPBH            (_ADI_MSK(0x00000800,uint32_t))  /* Channel B Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBH: Disable Chopping Channel B High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_EN           (_ADI_MSK(0x00000800,uint32_t))  /* ENCHOPBH: Enable Chopping Channel B High Side */
-
-#define BITM_PWM_CHANCFG_POLBH               (_ADI_MSK(0x00000400,uint32_t))  /* Channel B High side Polarity */
-#define ENUM_PWM_CHANCFG_BH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBH: Active Low */
-#define ENUM_PWM_CHANCFG_BH_ACTHI            (_ADI_MSK(0x00000400,uint32_t))  /* POLBH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSB             (_ADI_MSK(0x00000200,uint32_t))  /* Channel B Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOB_INV             (_ADI_MSK(0x00000000,uint32_t))  /* MODELSB: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOB_IND             (_ADI_MSK(0x00000200,uint32_t))  /* MODELSB: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRB             (_ADI_MSK(0x00000100,uint32_t))  /* Channel B Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRB: PWMTMR0 is Channel  B reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_1           (_ADI_MSK(0x00000100,uint32_t))  /* REFTMRB: PWMTMR1 is Channel B reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPAL            (_ADI_MSK(0x00000040,uint32_t))  /* Channel A Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAL: Disable Chopping Channel A Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_EN           (_ADI_MSK(0x00000040,uint32_t))  /* ENCHOPAL: Enable Chopping Channel A Low Side */
-
-#define BITM_PWM_CHANCFG_POLAL               (_ADI_MSK(0x00000020,uint32_t))  /* Channel A low side Polarity */
-#define ENUM_PWM_CHANCFG_AL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAL: Active Low */
-#define ENUM_PWM_CHANCFG_AL_ACTHI            (_ADI_MSK(0x00000020,uint32_t))  /* POLAL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPAH            (_ADI_MSK(0x00000008,uint32_t))  /* Channel A Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAH: Disable Chopping Channel A High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_EN           (_ADI_MSK(0x00000008,uint32_t))  /* ENCHOPAH: Enable Chopping Channel A High Side */
-
-#define BITM_PWM_CHANCFG_POLAH               (_ADI_MSK(0x00000004,uint32_t))  /* Channel A High side Polarity */
-#define ENUM_PWM_CHANCFG_AH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAH: Active Low */
-#define ENUM_PWM_CHANCFG_AH_ACTHI            (_ADI_MSK(0x00000004,uint32_t))  /* POLAH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSA             (_ADI_MSK(0x00000002,uint32_t))  /* Channel A Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOA_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSA: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOA_IND             (_ADI_MSK(0x00000002,uint32_t))  /* MODELSA: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRA             (_ADI_MSK(0x00000001,uint32_t))  /* Channel A Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRA: PWMTMR0 is Channel A reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_1           (_ADI_MSK(0x00000001,uint32_t))  /* REFTMRA: PWMTMR1 is Channel A reference */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TRIPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TRIPCFG_MODE1D              27                               /* Mode of TRIP1 for Channel D */
-#define BITP_PWM_TRIPCFG_EN1D                26                               /* Enable TRIP1 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE0D              25                               /* Mode of TRIP0 for Channel D */
-#define BITP_PWM_TRIPCFG_EN0D                24                               /* Enable TRIP0 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE1C              19                               /* Mode of TRIP1 for Channel C */
-#define BITP_PWM_TRIPCFG_EN1C                18                               /* Enable TRIP1 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE0C              17                               /* Mode of TRIP0 for Channel C */
-#define BITP_PWM_TRIPCFG_EN0C                16                               /* Enable TRIP0 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE1B              11                               /* Mode of TRIP1 for Channel B */
-#define BITP_PWM_TRIPCFG_EN1B                10                               /* Enable TRIP1 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE0B               9                               /* Mode of TRIP0 for Channel B */
-#define BITP_PWM_TRIPCFG_EN0B                 8                               /* Enable TRIP0 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE1A               3                               /* Mode of TRIP1 for Channel A */
-#define BITP_PWM_TRIPCFG_EN1A                 2                               /* Enable TRIP1 as a trip source for Channel A */
-#define BITP_PWM_TRIPCFG_MODE0A               1                               /* Mode of TRIP0 for Channel A */
-#define BITP_PWM_TRIPCFG_EN0A                 0                               /* Enable TRIP0 as a trip source for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE1D              (_ADI_MSK(0x08000000,uint32_t))  /* Mode of TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1D: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1D_RSTRT        (_ADI_MSK(0x08000000,uint32_t))  /* MODE1D: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1D                (_ADI_MSK(0x04000000,uint32_t))  /* Enable TRIP1 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1D: Disable TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_EN           (_ADI_MSK(0x04000000,uint32_t))  /* EN1D: Enable TRIP1 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE0D              (_ADI_MSK(0x02000000,uint32_t))  /* Mode of TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0D: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0D_RSTRT        (_ADI_MSK(0x02000000,uint32_t))  /* MODE0D: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0D                (_ADI_MSK(0x01000000,uint32_t))  /* Enable TRIP0 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0D: Disable TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_EN           (_ADI_MSK(0x01000000,uint32_t))  /* EN0D: Enable TRIP0 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE1C              (_ADI_MSK(0x00080000,uint32_t))  /* Mode of TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1C: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1C_RSTRT        (_ADI_MSK(0x00080000,uint32_t))  /* MODE1C: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1C                (_ADI_MSK(0x00040000,uint32_t))  /* Enable TRIP1 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1C: Disable TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_EN           (_ADI_MSK(0x00040000,uint32_t))  /* EN1C: Enable TRIP1 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE0C              (_ADI_MSK(0x00020000,uint32_t))  /* Mode of TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0C: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0C_RSTRT        (_ADI_MSK(0x00020000,uint32_t))  /* MODE0C: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0C                (_ADI_MSK(0x00010000,uint32_t))  /* Enable TRIP0 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0C: Disable TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_EN           (_ADI_MSK(0x00010000,uint32_t))  /* EN0C: Enable TRIP0 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE1B              (_ADI_MSK(0x00000800,uint32_t))  /* Mode of TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1B: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1B_RSTRT        (_ADI_MSK(0x00000800,uint32_t))  /* MODE1B: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1B                (_ADI_MSK(0x00000400,uint32_t))  /* Enable TRIP1 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1B: Disable TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_EN           (_ADI_MSK(0x00000400,uint32_t))  /* EN1B: Enable TRIP1 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE0B              (_ADI_MSK(0x00000200,uint32_t))  /* Mode of TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0B: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0B_RSTRT        (_ADI_MSK(0x00000200,uint32_t))  /* MODE0B: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0B                (_ADI_MSK(0x00000100,uint32_t))  /* Enable TRIP0 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0B: Disable TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_EN           (_ADI_MSK(0x00000100,uint32_t))  /* EN0B: Enable TRIP0 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE1A              (_ADI_MSK(0x00000008,uint32_t))  /* Mode of TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1A: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1A_RSTRT        (_ADI_MSK(0x00000008,uint32_t))  /* MODE1A: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1A                (_ADI_MSK(0x00000004,uint32_t))  /* Enable TRIP1 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1A: Disable TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_EN           (_ADI_MSK(0x00000004,uint32_t))  /* EN1A: Enable TRIP1 for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE0A              (_ADI_MSK(0x00000002,uint32_t))  /* Mode of TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0A: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0A_RSTRT        (_ADI_MSK(0x00000002,uint32_t))  /* MODE0A: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0A                (_ADI_MSK(0x00000001,uint32_t))  /* Enable TRIP0 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0A: Disable TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_EN           (_ADI_MSK(0x00000001,uint32_t))  /* EN0A: Enable TRIP0 for Channel A */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_STAT_TMR4PHASE              28                               /* PWMTMR4 Phase Status */
-#define BITP_PWM_STAT_TMR3PHASE              27                               /* PWMTMR3 Phase Status */
-#define BITP_PWM_STAT_TMR2PHASE              26                               /* PWMTMR2 Phase Status */
-#define BITP_PWM_STAT_TMR1PHASE              25                               /* PWMTMR1 Phase Status */
-#define BITP_PWM_STAT_TMR0PHASE              24                               /* PWMTMR0 Phase Status */
-#define BITP_PWM_STAT_TMR4PER                20                               /* PWMTMR4 Period Boundary Status */
-#define BITP_PWM_STAT_TMR3PER                19                               /* PWMTMR3 Period Boundary Status */
-#define BITP_PWM_STAT_TMR2PER                18                               /* PWMTMR2 Period Boundary Status */
-#define BITP_PWM_STAT_TMR1PER                17                               /* PWMTMR1 Period Boundary Status */
-#define BITP_PWM_STAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Status */
-#define BITP_PWM_STAT_SRTRIPD                11                               /* Self-Restart Trip Status for Channel D */
-#define BITP_PWM_STAT_FLTTRIPD               10                               /* Fault Trip Status for Channel D */
-#define BITP_PWM_STAT_SRTRIPC                 9                               /* Self-Restart Trip Status for Channel C */
-#define BITP_PWM_STAT_FLTTRIPC                8                               /* Fault Trip Status for Channel C */
-#define BITP_PWM_STAT_SRTRIPB                 7                               /* Self-Restart Trip Status for Channel B */
-#define BITP_PWM_STAT_FLTTRIPB                6                               /* Fault Trip Status for Channel B */
-#define BITP_PWM_STAT_SRTRIPA                 5                               /* Self-Restart Trip Status for Channel A */
-#define BITP_PWM_STAT_FLTTRIPA                4                               /* Fault Trip Status for Channel A */
-#define BITP_PWM_STAT_RAWTRIP1                3                               /* Raw Trip 1 Status */
-#define BITP_PWM_STAT_RAWTRIP0                2                               /* Raw Trip 0 Status */
-#define BITP_PWM_STAT_TRIP1                   1                               /* Status bit set when TRIP1 is active low */
-#define BITP_PWM_STAT_TRIP0                   0                               /* Status bit set when TRIP0 is active low */
-
-#define BITM_PWM_STAT_TMR4PHASE              (_ADI_MSK(0x10000000,uint32_t))  /* PWMTMR4 Phase Status */
-#define ENUM_PWM_STAT_TMR4PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR4PH2                (_ADI_MSK(0x10000000,uint32_t))  /* TMR4PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR3PHASE              (_ADI_MSK(0x08000000,uint32_t))  /* PWMTMR3 Phase Status */
-#define ENUM_PWM_STAT_TMR3PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR3PH2                (_ADI_MSK(0x08000000,uint32_t))  /* TMR3PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR2PHASE              (_ADI_MSK(0x04000000,uint32_t))  /* PWMTMR2 Phase Status */
-#define ENUM_PWM_STAT_TMR2PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR2PH2                (_ADI_MSK(0x04000000,uint32_t))  /* TMR2PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR1PHASE              (_ADI_MSK(0x02000000,uint32_t))  /* PWMTMR1 Phase Status */
-#define ENUM_PWM_STAT_TMR1PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR1PH2                (_ADI_MSK(0x02000000,uint32_t))  /* TMR1PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR0PHASE              (_ADI_MSK(0x01000000,uint32_t))  /* PWMTMR0 Phase Status */
-#define ENUM_PWM_STAT_TMR0PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR0PH2                (_ADI_MSK(0x01000000,uint32_t))  /* TMR0PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER4               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary not reached */
-#define ENUM_PWM_STAT_PER4                   (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary reached */
-
-#define BITM_PWM_STAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER3               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary not reached */
-#define ENUM_PWM_STAT_PER3                   (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary reached */
-
-#define BITM_PWM_STAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER2               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary not reached */
-#define ENUM_PWM_STAT_PER2                   (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary reached */
-
-#define BITM_PWM_STAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER1               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary not reached */
-#define ENUM_PWM_STAT_PER1                   (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary reached */
-
-#define BITM_PWM_STAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER0               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary not reached */
-#define ENUM_PWM_STAT_PER0                   (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary reached */
-
-#define BITM_PWM_STAT_SRTRIPD                (_ADI_MSK(0x00000800,uint32_t))  /* Self-Restart Trip Status for Channel D */
-#define ENUM_PWM_STAT_SRD_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRD_TRIP               (_ADI_MSK(0x00000800,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPD               (_ADI_MSK(0x00000400,uint32_t))  /* Fault Trip Status for Channel D */
-#define ENUM_PWM_STAT_FLTD_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTD_TRIP              (_ADI_MSK(0x00000400,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPC                (_ADI_MSK(0x00000200,uint32_t))  /* Self-Restart Trip Status for Channel C */
-#define ENUM_PWM_STAT_SRC_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRC_TRIP               (_ADI_MSK(0x00000200,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPC               (_ADI_MSK(0x00000100,uint32_t))  /* Fault Trip Status for Channel C */
-#define ENUM_PWM_STAT_FLTC_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTC_TRIP              (_ADI_MSK(0x00000100,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPB                (_ADI_MSK(0x00000080,uint32_t))  /* Self-Restart Trip Status for Channel B */
-#define ENUM_PWM_STAT_SRB_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRB_TRIP               (_ADI_MSK(0x00000080,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPB               (_ADI_MSK(0x00000040,uint32_t))  /* Fault Trip Status for Channel B */
-#define ENUM_PWM_STAT_FLTB_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPB: Channel B Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTB_TRIP              (_ADI_MSK(0x00000040,uint32_t))  /* FLTTRIPB: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPA                (_ADI_MSK(0x00000020,uint32_t))  /* Self-Restart Trip Status for Channel A */
-#define ENUM_PWM_STAT_SRA_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRA_TRIP               (_ADI_MSK(0x00000020,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPA               (_ADI_MSK(0x00000010,uint32_t))  /* Fault Trip Status for Channel A */
-#define ENUM_PWM_STAT_FLTA_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTA_TRIP              (_ADI_MSK(0x00000010,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_RAWTRIP1               (_ADI_MSK(0x00000008,uint32_t))  /* Raw Trip 1 Status */
-#define ENUM_PWM_STAT_TRIP1LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP1: TRIP1 Level is Low */
-#define ENUM_PWM_STAT_TRIP1LVL_HI            (_ADI_MSK(0x00000008,uint32_t))  /* RAWTRIP1: TRIP1 Level is High */
-
-#define BITM_PWM_STAT_RAWTRIP0               (_ADI_MSK(0x00000004,uint32_t))  /* Raw Trip 0 Status */
-#define ENUM_PWM_STAT_TRIP0LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP0: TRIP0 Level is Low */
-#define ENUM_PWM_STAT_TRIP0LVL_HI            (_ADI_MSK(0x00000004,uint32_t))  /* RAWTRIP0: TRIP0 Level is High */
-
-#define BITM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* Status bit set when TRIP1 is active low */
-#define ENUM_PWM_STAT_NO_TRIP1               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: TRIP1 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: TRIP1 status is "tripped" (active low) */
-
-#define BITM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* Status bit set when TRIP0 is active low */
-#define ENUM_PWM_STAT_NO_TRIP0               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: TRIP0 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: TRIP0 status is "tripped" (active low) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_IMSK_TMR4PER                20                               /* PWMTMR4 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR3PER                19                               /* PWMTMR3 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR2PER                18                               /* PWMTMR2 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR1PER                17                               /* PWMTMR1 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP1                   1                               /* TRIP1 Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP0                   0                               /* TRIP0 Interrupt Enable */
-
-#define BITM_PWM_IMSK_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER4_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: Mask PWMTMR4 Period Interrupt */
-#define ENUM_PWM_IMSK_PER4_UMSK              (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Unmask PWMTMR4 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER3_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: Mask PWMTMR3 Period Interrupt */
-#define ENUM_PWM_IMSK_PER3_UMSK              (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Unmask PWMTMR3 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER2_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: Mask PWMTMR2 Period Interrupt */
-#define ENUM_PWM_IMSK_PER2_UMSK              (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Unmask PWMTMR2 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER1_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: Mask PWMTMR1 Period Interrupt */
-#define ENUM_PWM_IMSK_PER1_UMSK              (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Unmask PWMTMR1 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER0_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: Mask PWMTMR0 Period Interrupt */
-#define ENUM_PWM_IMSK_PER0_UMSK              (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Unmask PWMTMR0 Period Interrupt */
-
-#define BITM_PWM_IMSK_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP1_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: Mask TRIP1 Interrupt */
-#define ENUM_PWM_IMSK_TRIP1_UMSK             (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Unmask TRIP1 Interrupt */
-
-#define BITM_PWM_IMSK_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP0_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: Mask TRIP0 Interrupt */
-#define ENUM_PWM_IMSK_TRIP0_UMSK             (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Unmask TRIP0 Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ILAT_TMR4PER                20                               /* PWMTMR4 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR3PER                19                               /* PWMTMR3 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR2PER                18                               /* PWMTMR2 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR1PER                17                               /* PWMTMR1 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP1                   1                               /* TRIP1 Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP0                   0                               /* TRIP0 Interrupt Latched Status */
-
-#define BITM_PWM_ILAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER4_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER4_INTHI             (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER3_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER3_INTHI             (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER2_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER2_INTHI             (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER1_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER1_INTHI             (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define ENUM_PWM_ILAT_PER0_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER0_INTHI             (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP1_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP1_INTHI            (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP0_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP0_INTHI            (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Interrupt Latched */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHOPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHOPCFG_VALUE                0                               /* Gate Chopping Divisor */
-#define BITM_PWM_CHOPCFG_VALUE               (_ADI_MSK(0x000000FF,uint32_t))  /* Gate Chopping Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DT_VALUE                     0                               /* Dead Time */
-#define BITM_PWM_DT_VALUE                    (_ADI_MSK(0x000003FF,uint32_t))  /* Dead Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_SYNC_WID                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_SYNC_WID_VALUE               0                               /* Sync Pulse Width */
-#define BITM_PWM_SYNC_WID_VALUE              (_ADI_MSK(0x000003FF,uint32_t))  /* Sync Pulse Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM0_VALUE                    0                               /* Timer PWMTMR0 Period Value */
-#define BITM_PWM_TM0_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR0 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM1_VALUE                    0                               /* Timer PWMTMR1 Period Value */
-#define BITM_PWM_TM1_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR1 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM2_VALUE                    0                               /* Timer PWMTMR2 Period Value */
-#define BITM_PWM_TM2_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR2 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM3                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM3_VALUE                    0                               /* Timer PWMTMR3 Period Value */
-#define BITM_PWM_TM3_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR3 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM4                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM4_VALUE                    0                               /* Timer PWMTMR4 Period Value */
-#define BITM_PWM_TM4_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR4 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYA                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYA_VALUE                   0                               /* Channel A Delay Value */
-#define BITM_PWM_DLYA_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel A Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYB                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYB_VALUE                   0                               /* Channel B Delay Value */
-#define BITM_PWM_DLYB_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel B Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYC                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYC_VALUE                   0                               /* Channel C Delay Value */
-#define BITM_PWM_DLYC_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel C Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYD_VALUE                   0                               /* Channel D Delay Value */
-#define BITM_PWM_DLYD_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel D Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ACTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ACTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_ACTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_ACTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_ACTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_ACTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-#define BITM_PWM_ACTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define ENUM_PWM_SYM_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODELO: Symmetrical */
-#define ENUM_PWM_ASYM_LO                     (_ADI_MSK(0x00000400,uint32_t))  /* PULSEMODELO: Asymmetrical */
-#define ENUM_PWM_LEFT_LO                     (_ADI_MSK(0x00000800,uint32_t))  /* PULSEMODELO: Left Half */
-#define ENUM_PWM_RIGHT_LO                    (_ADI_MSK(0x00000C00,uint32_t))  /* PULSEMODELO: Right Half */
-
-#define BITM_PWM_ACTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define ENUM_PWM_SYM_HI                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODEHI: Symmetrical */
-#define ENUM_PWM_ASYM_HI                     (_ADI_MSK(0x00000100,uint32_t))  /* PULSEMODEHI: Asymmetrical */
-#define ENUM_PWM_LEFT_HI                     (_ADI_MSK(0x00000200,uint32_t))  /* PULSEMODEHI: Left Half */
-#define ENUM_PWM_RIGHT_HI                    (_ADI_MSK(0x00000300,uint32_t))  /* PULSEMODEHI: Right Half */
-
-#define BITM_PWM_ACTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define ENUM_PWM_XOVR_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* XOVR: Disable Crossover */
-#define ENUM_PWM_XOVR_EN                     (_ADI_MSK(0x00000004,uint32_t))  /* XOVR: Enable Crossover */
-
-#define BITM_PWM_ACTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define ENUM_PWM_LO_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISLO: Disable Low Side Output */
-#define ENUM_PWM_LO_EN                       (_ADI_MSK(0x00000002,uint32_t))  /* DISLO: Enable Low Side Output */
-
-#define BITM_PWM_ACTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-#define ENUM_PWM_HI_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISHI: Disable High Side Output */
-#define ENUM_PWM_HI_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* DISHI: Enable High Side Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_BCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_BCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_BCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_BCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_BCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_BCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_BCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_BCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_BCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_BCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_CCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_CCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_CCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_CCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_CCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_CCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_CCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_CCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_CCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_CCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_DCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_DCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_DCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_DCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_DCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_DCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_DCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_DCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_DCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_DCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ==================================================
-        Video Subsystem Registers Registers
-   ================================================== */
-
-/* =========================
-        VID0
-   ========================= */
-#define REG_VID0_CONN                   0xFFC1D000         /* VID0 Video Subsystem Connect Register */
-
-/* =========================
-        VID
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        VID_CONN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_VID_CONN_PPI2BCAST              23                               /* PPI_2 Broadcast Mode */
-#define BITP_VID_CONN_PPI1BCAST              22                               /* PPI_1 Broadcast Mode */
-#define BITP_VID_CONN_PPI0BCAST              21                               /* PPI_0 Broadcast Mode */
-#define BITP_VID_CONN_PPI2TX                 16                               /* PPI_2_TX Connectivity */
-#define BITP_VID_CONN_PPI1TX                 12                               /* PPI_1_TX Connectivity */
-#define BITP_VID_CONN_PPI0TX                  8                               /* PPI_0_TX Connectivity */
-#define BITM_VID_CONN_PPI2BCAST              (_ADI_MSK(0x00800000,uint32_t))  /* PPI_2 Broadcast Mode */
-#define BITM_VID_CONN_PPI1BCAST              (_ADI_MSK(0x00400000,uint32_t))  /* PPI_1 Broadcast Mode */
-#define BITM_VID_CONN_PPI0BCAST              (_ADI_MSK(0x00200000,uint32_t))  /* PPI_0 Broadcast Mode */
-#define BITM_VID_CONN_PPI2TX                 (_ADI_MSK(0x000F0000,uint32_t))  /* PPI_2_TX Connectivity */
-#define BITM_VID_CONN_PPI1TX                 (_ADI_MSK(0x0000F000,uint32_t))  /* PPI_1_TX Connectivity */
-#define BITM_VID_CONN_PPI0TX                 (_ADI_MSK(0x00000F00,uint32_t))  /* PPI_0_TX Connectivity */
-
-/* ==================================================
-        System Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        SWU0
-   ========================= */
-#define REG_SWU0_GCTL                   0xFFC1E000         /* SWU0 Global Control Register */
-#define REG_SWU0_GSTAT                  0xFFC1E004         /* SWU0 Global Status Register */
-#define REG_SWU0_CTL0                   0xFFC1E010         /* SWU0 Control Register n */
-#define REG_SWU0_CTL1                   0xFFC1E030         /* SWU0 Control Register n */
-#define REG_SWU0_CTL2                   0xFFC1E050         /* SWU0 Control Register n */
-#define REG_SWU0_CTL3                   0xFFC1E070         /* SWU0 Control Register n */
-#define REG_SWU0_LA0                    0xFFC1E014         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA1                    0xFFC1E034         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA2                    0xFFC1E054         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA3                    0xFFC1E074         /* SWU0 Lower Address Register n */
-#define REG_SWU0_UA0                    0xFFC1E018         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA1                    0xFFC1E038         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA2                    0xFFC1E058         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA3                    0xFFC1E078         /* SWU0 Upper Address Register n */
-#define REG_SWU0_ID0                    0xFFC1E01C         /* SWU0 ID Register n */
-#define REG_SWU0_ID1                    0xFFC1E03C         /* SWU0 ID Register n */
-#define REG_SWU0_ID2                    0xFFC1E05C         /* SWU0 ID Register n */
-#define REG_SWU0_ID3                    0xFFC1E07C         /* SWU0 ID Register n */
-#define REG_SWU0_CNT0                   0xFFC1E020         /* SWU0 Count Register n */
-#define REG_SWU0_CNT1                   0xFFC1E040         /* SWU0 Count Register n */
-#define REG_SWU0_CNT2                   0xFFC1E060         /* SWU0 Count Register n */
-#define REG_SWU0_CNT3                   0xFFC1E080         /* SWU0 Count Register n */
-#define REG_SWU0_TARG0                  0xFFC1E024         /* SWU0 Target Register n */
-#define REG_SWU0_TARG1                  0xFFC1E044         /* SWU0 Target Register n */
-#define REG_SWU0_TARG2                  0xFFC1E064         /* SWU0 Target Register n */
-#define REG_SWU0_TARG3                  0xFFC1E084         /* SWU0 Target Register n */
-#define REG_SWU0_HIST0                  0xFFC1E028         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST1                  0xFFC1E048         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST2                  0xFFC1E068         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST3                  0xFFC1E088         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_CUR0                   0xFFC1E02C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR1                   0xFFC1E04C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR2                   0xFFC1E06C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR3                   0xFFC1E08C         /* SWU0 Current Register n */
-
-/* =========================
-        SWU1
-   ========================= */
-#define REG_SWU1_GCTL                   0xFFCAB000         /* SWU1 Global Control Register */
-#define REG_SWU1_GSTAT                  0xFFCAB004         /* SWU1 Global Status Register */
-#define REG_SWU1_CTL0                   0xFFCAB010         /* SWU1 Control Register n */
-#define REG_SWU1_CTL1                   0xFFCAB030         /* SWU1 Control Register n */
-#define REG_SWU1_CTL2                   0xFFCAB050         /* SWU1 Control Register n */
-#define REG_SWU1_CTL3                   0xFFCAB070         /* SWU1 Control Register n */
-#define REG_SWU1_LA0                    0xFFCAB014         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA1                    0xFFCAB034         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA2                    0xFFCAB054         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA3                    0xFFCAB074         /* SWU1 Lower Address Register n */
-#define REG_SWU1_UA0                    0xFFCAB018         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA1                    0xFFCAB038         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA2                    0xFFCAB058         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA3                    0xFFCAB078         /* SWU1 Upper Address Register n */
-#define REG_SWU1_ID0                    0xFFCAB01C         /* SWU1 ID Register n */
-#define REG_SWU1_ID1                    0xFFCAB03C         /* SWU1 ID Register n */
-#define REG_SWU1_ID2                    0xFFCAB05C         /* SWU1 ID Register n */
-#define REG_SWU1_ID3                    0xFFCAB07C         /* SWU1 ID Register n */
-#define REG_SWU1_CNT0                   0xFFCAB020         /* SWU1 Count Register n */
-#define REG_SWU1_CNT1                   0xFFCAB040         /* SWU1 Count Register n */
-#define REG_SWU1_CNT2                   0xFFCAB060         /* SWU1 Count Register n */
-#define REG_SWU1_CNT3                   0xFFCAB080         /* SWU1 Count Register n */
-#define REG_SWU1_TARG0                  0xFFCAB024         /* SWU1 Target Register n */
-#define REG_SWU1_TARG1                  0xFFCAB044         /* SWU1 Target Register n */
-#define REG_SWU1_TARG2                  0xFFCAB064         /* SWU1 Target Register n */
-#define REG_SWU1_TARG3                  0xFFCAB084         /* SWU1 Target Register n */
-#define REG_SWU1_HIST0                  0xFFCAB028         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST1                  0xFFCAB048         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST2                  0xFFCAB068         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST3                  0xFFCAB088         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_CUR0                   0xFFCAB02C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR1                   0xFFCAB04C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR2                   0xFFCAB06C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR3                   0xFFCAB08C         /* SWU1 Current Register n */
-
-/* =========================
-        SWU2
-   ========================= */
-#define REG_SWU2_GCTL                   0xFFCAC000         /* SWU2 Global Control Register */
-#define REG_SWU2_GSTAT                  0xFFCAC004         /* SWU2 Global Status Register */
-#define REG_SWU2_CTL0                   0xFFCAC010         /* SWU2 Control Register n */
-#define REG_SWU2_CTL1                   0xFFCAC030         /* SWU2 Control Register n */
-#define REG_SWU2_CTL2                   0xFFCAC050         /* SWU2 Control Register n */
-#define REG_SWU2_CTL3                   0xFFCAC070         /* SWU2 Control Register n */
-#define REG_SWU2_LA0                    0xFFCAC014         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA1                    0xFFCAC034         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA2                    0xFFCAC054         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA3                    0xFFCAC074         /* SWU2 Lower Address Register n */
-#define REG_SWU2_UA0                    0xFFCAC018         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA1                    0xFFCAC038         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA2                    0xFFCAC058         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA3                    0xFFCAC078         /* SWU2 Upper Address Register n */
-#define REG_SWU2_ID0                    0xFFCAC01C         /* SWU2 ID Register n */
-#define REG_SWU2_ID1                    0xFFCAC03C         /* SWU2 ID Register n */
-#define REG_SWU2_ID2                    0xFFCAC05C         /* SWU2 ID Register n */
-#define REG_SWU2_ID3                    0xFFCAC07C         /* SWU2 ID Register n */
-#define REG_SWU2_CNT0                   0xFFCAC020         /* SWU2 Count Register n */
-#define REG_SWU2_CNT1                   0xFFCAC040         /* SWU2 Count Register n */
-#define REG_SWU2_CNT2                   0xFFCAC060         /* SWU2 Count Register n */
-#define REG_SWU2_CNT3                   0xFFCAC080         /* SWU2 Count Register n */
-#define REG_SWU2_TARG0                  0xFFCAC024         /* SWU2 Target Register n */
-#define REG_SWU2_TARG1                  0xFFCAC044         /* SWU2 Target Register n */
-#define REG_SWU2_TARG2                  0xFFCAC064         /* SWU2 Target Register n */
-#define REG_SWU2_TARG3                  0xFFCAC084         /* SWU2 Target Register n */
-#define REG_SWU2_HIST0                  0xFFCAC028         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST1                  0xFFCAC048         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST2                  0xFFCAC068         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST3                  0xFFCAC088         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_CUR0                   0xFFCAC02C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR1                   0xFFCAC04C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR2                   0xFFCAC06C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR3                   0xFFCAC08C         /* SWU2 Current Register n */
-
-/* =========================
-        SWU3
-   ========================= */
-#define REG_SWU3_GCTL                   0xFFCAD000         /* SWU3 Global Control Register */
-#define REG_SWU3_GSTAT                  0xFFCAD004         /* SWU3 Global Status Register */
-#define REG_SWU3_CTL0                   0xFFCAD010         /* SWU3 Control Register n */
-#define REG_SWU3_CTL1                   0xFFCAD030         /* SWU3 Control Register n */
-#define REG_SWU3_CTL2                   0xFFCAD050         /* SWU3 Control Register n */
-#define REG_SWU3_CTL3                   0xFFCAD070         /* SWU3 Control Register n */
-#define REG_SWU3_LA0                    0xFFCAD014         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA1                    0xFFCAD034         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA2                    0xFFCAD054         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA3                    0xFFCAD074         /* SWU3 Lower Address Register n */
-#define REG_SWU3_UA0                    0xFFCAD018         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA1                    0xFFCAD038         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA2                    0xFFCAD058         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA3                    0xFFCAD078         /* SWU3 Upper Address Register n */
-#define REG_SWU3_ID0                    0xFFCAD01C         /* SWU3 ID Register n */
-#define REG_SWU3_ID1                    0xFFCAD03C         /* SWU3 ID Register n */
-#define REG_SWU3_ID2                    0xFFCAD05C         /* SWU3 ID Register n */
-#define REG_SWU3_ID3                    0xFFCAD07C         /* SWU3 ID Register n */
-#define REG_SWU3_CNT0                   0xFFCAD020         /* SWU3 Count Register n */
-#define REG_SWU3_CNT1                   0xFFCAD040         /* SWU3 Count Register n */
-#define REG_SWU3_CNT2                   0xFFCAD060         /* SWU3 Count Register n */
-#define REG_SWU3_CNT3                   0xFFCAD080         /* SWU3 Count Register n */
-#define REG_SWU3_TARG0                  0xFFCAD024         /* SWU3 Target Register n */
-#define REG_SWU3_TARG1                  0xFFCAD044         /* SWU3 Target Register n */
-#define REG_SWU3_TARG2                  0xFFCAD064         /* SWU3 Target Register n */
-#define REG_SWU3_TARG3                  0xFFCAD084         /* SWU3 Target Register n */
-#define REG_SWU3_HIST0                  0xFFCAD028         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST1                  0xFFCAD048         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST2                  0xFFCAD068         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST3                  0xFFCAD088         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_CUR0                   0xFFCAD02C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR1                   0xFFCAD04C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR2                   0xFFCAD06C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR3                   0xFFCAD08C         /* SWU3 Current Register n */
-
-/* =========================
-        SWU4
-   ========================= */
-#define REG_SWU4_GCTL                   0xFFCAE000         /* SWU4 Global Control Register */
-#define REG_SWU4_GSTAT                  0xFFCAE004         /* SWU4 Global Status Register */
-#define REG_SWU4_CTL0                   0xFFCAE010         /* SWU4 Control Register n */
-#define REG_SWU4_CTL1                   0xFFCAE030         /* SWU4 Control Register n */
-#define REG_SWU4_CTL2                   0xFFCAE050         /* SWU4 Control Register n */
-#define REG_SWU4_CTL3                   0xFFCAE070         /* SWU4 Control Register n */
-#define REG_SWU4_LA0                    0xFFCAE014         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA1                    0xFFCAE034         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA2                    0xFFCAE054         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA3                    0xFFCAE074         /* SWU4 Lower Address Register n */
-#define REG_SWU4_UA0                    0xFFCAE018         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA1                    0xFFCAE038         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA2                    0xFFCAE058         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA3                    0xFFCAE078         /* SWU4 Upper Address Register n */
-#define REG_SWU4_ID0                    0xFFCAE01C         /* SWU4 ID Register n */
-#define REG_SWU4_ID1                    0xFFCAE03C         /* SWU4 ID Register n */
-#define REG_SWU4_ID2                    0xFFCAE05C         /* SWU4 ID Register n */
-#define REG_SWU4_ID3                    0xFFCAE07C         /* SWU4 ID Register n */
-#define REG_SWU4_CNT0                   0xFFCAE020         /* SWU4 Count Register n */
-#define REG_SWU4_CNT1                   0xFFCAE040         /* SWU4 Count Register n */
-#define REG_SWU4_CNT2                   0xFFCAE060         /* SWU4 Count Register n */
-#define REG_SWU4_CNT3                   0xFFCAE080         /* SWU4 Count Register n */
-#define REG_SWU4_TARG0                  0xFFCAE024         /* SWU4 Target Register n */
-#define REG_SWU4_TARG1                  0xFFCAE044         /* SWU4 Target Register n */
-#define REG_SWU4_TARG2                  0xFFCAE064         /* SWU4 Target Register n */
-#define REG_SWU4_TARG3                  0xFFCAE084         /* SWU4 Target Register n */
-#define REG_SWU4_HIST0                  0xFFCAE028         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST1                  0xFFCAE048         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST2                  0xFFCAE068         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST3                  0xFFCAE088         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_CUR0                   0xFFCAE02C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR1                   0xFFCAE04C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR2                   0xFFCAE06C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR3                   0xFFCAE08C         /* SWU4 Current Register n */
-
-/* =========================
-        SWU5
-   ========================= */
-#define REG_SWU5_GCTL                   0xFFCAF000         /* SWU5 Global Control Register */
-#define REG_SWU5_GSTAT                  0xFFCAF004         /* SWU5 Global Status Register */
-#define REG_SWU5_CTL0                   0xFFCAF010         /* SWU5 Control Register n */
-#define REG_SWU5_CTL1                   0xFFCAF030         /* SWU5 Control Register n */
-#define REG_SWU5_CTL2                   0xFFCAF050         /* SWU5 Control Register n */
-#define REG_SWU5_CTL3                   0xFFCAF070         /* SWU5 Control Register n */
-#define REG_SWU5_LA0                    0xFFCAF014         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA1                    0xFFCAF034         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA2                    0xFFCAF054         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA3                    0xFFCAF074         /* SWU5 Lower Address Register n */
-#define REG_SWU5_UA0                    0xFFCAF018         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA1                    0xFFCAF038         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA2                    0xFFCAF058         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA3                    0xFFCAF078         /* SWU5 Upper Address Register n */
-#define REG_SWU5_ID0                    0xFFCAF01C         /* SWU5 ID Register n */
-#define REG_SWU5_ID1                    0xFFCAF03C         /* SWU5 ID Register n */
-#define REG_SWU5_ID2                    0xFFCAF05C         /* SWU5 ID Register n */
-#define REG_SWU5_ID3                    0xFFCAF07C         /* SWU5 ID Register n */
-#define REG_SWU5_CNT0                   0xFFCAF020         /* SWU5 Count Register n */
-#define REG_SWU5_CNT1                   0xFFCAF040         /* SWU5 Count Register n */
-#define REG_SWU5_CNT2                   0xFFCAF060         /* SWU5 Count Register n */
-#define REG_SWU5_CNT3                   0xFFCAF080         /* SWU5 Count Register n */
-#define REG_SWU5_TARG0                  0xFFCAF024         /* SWU5 Target Register n */
-#define REG_SWU5_TARG1                  0xFFCAF044         /* SWU5 Target Register n */
-#define REG_SWU5_TARG2                  0xFFCAF064         /* SWU5 Target Register n */
-#define REG_SWU5_TARG3                  0xFFCAF084         /* SWU5 Target Register n */
-#define REG_SWU5_HIST0                  0xFFCAF028         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST1                  0xFFCAF048         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST2                  0xFFCAF068         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST3                  0xFFCAF088         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_CUR0                   0xFFCAF02C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR1                   0xFFCAF04C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR2                   0xFFCAF06C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR3                   0xFFCAF08C         /* SWU5 Current Register n */
-
-/* =========================
-        SWU6
-   ========================= */
-#define REG_SWU6_GCTL                   0xFFC82000         /* SWU6 Global Control Register */
-#define REG_SWU6_GSTAT                  0xFFC82004         /* SWU6 Global Status Register */
-#define REG_SWU6_CTL0                   0xFFC82010         /* SWU6 Control Register n */
-#define REG_SWU6_CTL1                   0xFFC82030         /* SWU6 Control Register n */
-#define REG_SWU6_CTL2                   0xFFC82050         /* SWU6 Control Register n */
-#define REG_SWU6_CTL3                   0xFFC82070         /* SWU6 Control Register n */
-#define REG_SWU6_LA0                    0xFFC82014         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA1                    0xFFC82034         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA2                    0xFFC82054         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA3                    0xFFC82074         /* SWU6 Lower Address Register n */
-#define REG_SWU6_UA0                    0xFFC82018         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA1                    0xFFC82038         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA2                    0xFFC82058         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA3                    0xFFC82078         /* SWU6 Upper Address Register n */
-#define REG_SWU6_ID0                    0xFFC8201C         /* SWU6 ID Register n */
-#define REG_SWU6_ID1                    0xFFC8203C         /* SWU6 ID Register n */
-#define REG_SWU6_ID2                    0xFFC8205C         /* SWU6 ID Register n */
-#define REG_SWU6_ID3                    0xFFC8207C         /* SWU6 ID Register n */
-#define REG_SWU6_CNT0                   0xFFC82020         /* SWU6 Count Register n */
-#define REG_SWU6_CNT1                   0xFFC82040         /* SWU6 Count Register n */
-#define REG_SWU6_CNT2                   0xFFC82060         /* SWU6 Count Register n */
-#define REG_SWU6_CNT3                   0xFFC82080         /* SWU6 Count Register n */
-#define REG_SWU6_TARG0                  0xFFC82024         /* SWU6 Target Register n */
-#define REG_SWU6_TARG1                  0xFFC82044         /* SWU6 Target Register n */
-#define REG_SWU6_TARG2                  0xFFC82064         /* SWU6 Target Register n */
-#define REG_SWU6_TARG3                  0xFFC82084         /* SWU6 Target Register n */
-#define REG_SWU6_HIST0                  0xFFC82028         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST1                  0xFFC82048         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST2                  0xFFC82068         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST3                  0xFFC82088         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_CUR0                   0xFFC8202C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR1                   0xFFC8204C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR2                   0xFFC8206C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR3                   0xFFC8208C         /* SWU6 Current Register n */
-
-/* =========================
-        SWU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GCTL_RST                     1                               /* Global Reset */
-#define BITP_SWU_GCTL_EN                      0                               /* Global Enable */
-#define BITM_SWU_GCTL_RST                    (_ADI_MSK(0x00000002,uint32_t))  /* Global Reset */
-#define BITM_SWU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Global Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GSTAT_ADDRERR               30                               /* Address Error Status */
-#define BITP_SWU_GSTAT_OVRBW3                15                               /* Group 3 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW3               14                               /* Group 3 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW2                13                               /* Group 2 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW2               12                               /* Group 2 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW1                11                               /* Group 1 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW1               10                               /* Group 1 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW0                 9                               /* Group 0 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW0                8                               /* Group 0 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_INT3                   7                               /* Group 3 Interrupt Status */
-#define BITP_SWU_GSTAT_INT2                   6                               /* Group 2 Interrupt Status */
-#define BITP_SWU_GSTAT_INT1                   5                               /* Group 1 Interrupt Status */
-#define BITP_SWU_GSTAT_INT0                   4                               /* Group 0 Interrupt Status */
-#define BITP_SWU_GSTAT_MTCH3                  3                               /* Group 3 Match */
-#define BITP_SWU_GSTAT_MTCH2                  2                               /* Group 2 Match */
-#define BITP_SWU_GSTAT_MTCH1                  1                               /* Group 1 Match */
-#define BITP_SWU_GSTAT_MTCH0                  0                               /* Group 0 Match */
-#define BITM_SWU_GSTAT_ADDRERR               (_ADI_MSK(0x40000000,uint32_t))  /* Address Error Status */
-#define BITM_SWU_GSTAT_OVRBW3                (_ADI_MSK(0x00008000,uint32_t))  /* Group 3 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW3               (_ADI_MSK(0x00004000,uint32_t))  /* Group 3 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW2                (_ADI_MSK(0x00002000,uint32_t))  /* Group 2 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW2               (_ADI_MSK(0x00001000,uint32_t))  /* Group 2 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW1                (_ADI_MSK(0x00000800,uint32_t))  /* Group 1 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW1               (_ADI_MSK(0x00000400,uint32_t))  /* Group 1 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW0                (_ADI_MSK(0x00000200,uint32_t))  /* Group 0 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW0               (_ADI_MSK(0x00000100,uint32_t))  /* Group 0 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_INT3                  (_ADI_MSK(0x00000080,uint32_t))  /* Group 3 Interrupt Status */
-#define BITM_SWU_GSTAT_INT2                  (_ADI_MSK(0x00000040,uint32_t))  /* Group 2 Interrupt Status */
-#define BITM_SWU_GSTAT_INT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Group 1 Interrupt Status */
-#define BITM_SWU_GSTAT_INT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Group 0 Interrupt Status */
-#define BITM_SWU_GSTAT_MTCH3                 (_ADI_MSK(0x00000008,uint32_t))  /* Group 3 Match */
-#define BITM_SWU_GSTAT_MTCH2                 (_ADI_MSK(0x00000004,uint32_t))  /* Group 2 Match */
-#define BITM_SWU_GSTAT_MTCH1                 (_ADI_MSK(0x00000002,uint32_t))  /* Group 1 Match */
-#define BITM_SWU_GSTAT_MTCH0                 (_ADI_MSK(0x00000001,uint32_t))  /* Group 0 Match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CTL_MAXACT                  19                               /* Action for Bandwidth Above Maximum */
-#define BITP_SWU_CTL_MINACT                  18                               /* Action for Bandwidth Below Minimum */
-#define BITP_SWU_CTL_BLENINC                 17                               /* Increment Bandwidth Count by Burst Length */
-#define BITP_SWU_CTL_BWEN                    16                               /* Bandwidth Mode Enable */
-#define BITP_SWU_CTL_TMEN                    15                               /* Trace Message Enable */
-#define BITP_SWU_CTL_TRGEN                   14                               /* Trigger Enable */
-#define BITP_SWU_CTL_INTEN                   13                               /* Interrupt Enable */
-#define BITP_SWU_CTL_DBGEN                   12                               /* Debug Event Enable */
-#define BITP_SWU_CTL_CNTRPTEN                 9                               /* Count Repeat Enable */
-#define BITP_SWU_CTL_CNTEN                    8                               /* Count Enable */
-#define BITP_SWU_CTL_LCMPEN                   6                               /* Locked Comparison Enable */
-#define BITP_SWU_CTL_SCMPEN                   5                               /* Secure Comparison Enable */
-#define BITP_SWU_CTL_IDCMPEN                  4                               /* ID Comparison Enable */
-#define BITP_SWU_CTL_ACMPM                    2                               /* Address Comparison Mode */
-#define BITP_SWU_CTL_DIR                      1                               /* Transaction Direction for Match */
-#define BITP_SWU_CTL_EN                       0                               /* Enable Watchpoint */
-#define BITM_SWU_CTL_MAXACT                  (_ADI_MSK(0x00080000,uint32_t))  /* Action for Bandwidth Above Maximum */
-#define BITM_SWU_CTL_MINACT                  (_ADI_MSK(0x00040000,uint32_t))  /* Action for Bandwidth Below Minimum */
-#define BITM_SWU_CTL_BLENINC                 (_ADI_MSK(0x00020000,uint32_t))  /* Increment Bandwidth Count by Burst Length */
-#define BITM_SWU_CTL_BWEN                    (_ADI_MSK(0x00010000,uint32_t))  /* Bandwidth Mode Enable */
-#define BITM_SWU_CTL_TMEN                    (_ADI_MSK(0x00008000,uint32_t))  /* Trace Message Enable */
-#define BITM_SWU_CTL_TRGEN                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Enable */
-#define BITM_SWU_CTL_INTEN                   (_ADI_MSK(0x00002000,uint32_t))  /* Interrupt Enable */
-#define BITM_SWU_CTL_DBGEN                   (_ADI_MSK(0x00001000,uint32_t))  /* Debug Event Enable */
-#define BITM_SWU_CTL_CNTRPTEN                (_ADI_MSK(0x00000200,uint32_t))  /* Count Repeat Enable */
-#define BITM_SWU_CTL_CNTEN                   (_ADI_MSK(0x00000100,uint32_t))  /* Count Enable */
-#define BITM_SWU_CTL_LCMPEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Locked Comparison Enable */
-#define BITM_SWU_CTL_SCMPEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Secure Comparison Enable */
-#define BITM_SWU_CTL_IDCMPEN                 (_ADI_MSK(0x00000010,uint32_t))  /* ID Comparison Enable */
-#define BITM_SWU_CTL_ACMPM                   (_ADI_MSK(0x0000000C,uint32_t))  /* Address Comparison Mode */
-#define BITM_SWU_CTL_DIR                     (_ADI_MSK(0x00000002,uint32_t))  /* Transaction Direction for Match */
-#define BITM_SWU_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable Watchpoint */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_ID                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_ID_IDMASK                   16                               /* Identity Mask (for Or with ID) */
-#define BITP_SWU_ID_ID                        0                               /* Identity */
-#define BITM_SWU_ID_IDMASK                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Identity Mask (for Or with ID) */
-#define BITM_SWU_ID_ID                       (_ADI_MSK(0x0000FFFF,uint32_t))  /* Identity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CNT_COUNT                    0                               /* Count */
-#define BITM_SWU_CNT_COUNT                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_TARG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_TARG_BWMAX                  16                               /* Maximum Bandwidth Target */
-#define BITP_SWU_TARG_BWMIN                   0                               /* Minimum Bandwidth Target */
-#define BITM_SWU_TARG_BWMAX                  (_ADI_MSK(0xFFFF0000,uint32_t))  /* Maximum Bandwidth Target */
-#define BITM_SWU_TARG_BWMIN                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Minimum Bandwidth Target */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_HIST                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_HIST_BWHIST1                16                               /* Bandwidth from Window Before Last */
-#define BITP_SWU_HIST_BWHIST0                 0                               /* Bandwidth from Last Window */
-#define BITM_SWU_HIST_BWHIST1                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Bandwidth from Window Before Last */
-#define BITM_SWU_HIST_BWHIST0                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth from Last Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CUR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CUR_CURBW                   16                               /* Current Bandwidth */
-#define BITP_SWU_CUR_CURCNT                   0                               /* Current Count */
-#define BITM_SWU_CUR_CURBW                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Current Bandwidth */
-#define BITM_SWU_CUR_CURCNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Current Count */
-
-/* ==================================================
-        System Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        SDU0
-   ========================= */
-#define REG_SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
-#define REG_SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
-#define REG_SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
-#define REG_SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
-#define REG_SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
-#define REG_SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
-#define REG_SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
-#define REG_SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
-#define REG_SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
-#define REG_SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
-#define REG_SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
-#define REG_SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
-
-/* =========================
-        SDU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_IDCODE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_IDCODE_REVID                28                               /* Revision ID */
-#define BITP_SDU_IDCODE_PRID                 12                               /* Product ID */
-#define BITP_SDU_IDCODE_MFID                  1                               /* Manufacturer ID */
-#define BITM_SDU_IDCODE_REVID                (_ADI_MSK(0xF0000000,uint32_t))  /* Revision ID */
-#define BITM_SDU_IDCODE_PRID                 (_ADI_MSK(0x0FFFF000,uint32_t))  /* Product ID */
-#define BITM_SDU_IDCODE_MFID                 (_ADI_MSK(0x00000FFE,uint32_t))  /* Manufacturer ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_CTL_EHLT                     8                               /* Emulator Halt Select */
-#define BITP_SDU_CTL_EMEEN                    4                               /* Emulation Event Enable */
-#define BITP_SDU_CTL_DMAEN                    2                               /* DMA Enable */
-#define BITP_SDU_CTL_CSPEN                    1                               /* Core Scan Path Enable */
-#define BITP_SDU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_SDU_CTL_EHLT                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Emulator Halt Select */
-#define BITM_SDU_CTL_EMEEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Emulation Event Enable */
-#define BITM_SDU_CTL_DMAEN                   (_ADI_MSK(0x00000004,uint32_t))  /* DMA Enable */
-#define BITM_SDU_CTL_CSPEN                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Scan Path Enable */
-#define BITM_SDU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_STAT_CRST                   22                               /* Core Reset */
-#define BITP_SDU_STAT_CHLT                   21                               /* Core Halt */
-#define BITP_SDU_STAT_EME                    20                               /* Emulation Event */
-#define BITP_SDU_STAT_GHLTC                  17                               /* Group Halt Cause */
-#define BITP_SDU_STAT_GHLT                   16                               /* Group Halt */
-#define BITP_SDU_STAT_DMAFIFO                12                               /* DMA FIFO */
-#define BITP_SDU_STAT_ADDRERR                11                               /* Address Error */
-#define BITP_SDU_STAT_DMAWDRDY               10                               /* DMAWD Ready */
-#define BITP_SDU_STAT_DMARDRDY                9                               /* DMARD Ready */
-#define BITP_SDU_STAT_MACRDY                  8                               /* MAC Ready */
-#define BITP_SDU_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_SDU_STAT_SECURE                  3                               /* Secure Mode */
-#define BITP_SDU_STAT_DEEPSLEEP               2                               /* Deep Sleep Mode */
-#define BITP_SDU_STAT_ERR                     1                               /* Error */
-#define BITP_SDU_STAT_SYSRST                  0                               /* System Reset */
-#define BITM_SDU_STAT_CRST                   (_ADI_MSK(0x00400000,uint32_t))  /* Core Reset */
-#define BITM_SDU_STAT_CHLT                   (_ADI_MSK(0x00200000,uint32_t))  /* Core Halt */
-#define BITM_SDU_STAT_EME                    (_ADI_MSK(0x00100000,uint32_t))  /* Emulation Event */
-#define BITM_SDU_STAT_GHLTC                  (_ADI_MSK(0x000E0000,uint32_t))  /* Group Halt Cause */
-#define BITM_SDU_STAT_GHLT                   (_ADI_MSK(0x00010000,uint32_t))  /* Group Halt */
-#define BITM_SDU_STAT_DMAFIFO                (_ADI_MSK(0x00007000,uint32_t))  /* DMA FIFO */
-#define BITM_SDU_STAT_ADDRERR                (_ADI_MSK(0x00000800,uint32_t))  /* Address Error */
-#define BITM_SDU_STAT_DMAWDRDY               (_ADI_MSK(0x00000400,uint32_t))  /* DMAWD Ready */
-#define BITM_SDU_STAT_DMARDRDY               (_ADI_MSK(0x00000200,uint32_t))  /* DMARD Ready */
-#define BITM_SDU_STAT_MACRDY                 (_ADI_MSK(0x00000100,uint32_t))  /* MAC Ready */
-#define BITM_SDU_STAT_ERRC                   (_ADI_MSK(0x000000F0,uint32_t))  /* Error Cause */
-#define BITM_SDU_STAT_SECURE                 (_ADI_MSK(0x00000008,uint32_t))  /* Secure Mode */
-#define BITM_SDU_STAT_DEEPSLEEP              (_ADI_MSK(0x00000004,uint32_t))  /* Deep Sleep Mode */
-#define BITM_SDU_STAT_ERR                    (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define BITM_SDU_STAT_SYSRST                 (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MACCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MACCTL_AUTOINC               4                               /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITP_SDU_MACCTL_RNW                   3                               /* Read Not Write */
-#define BITP_SDU_MACCTL_SIZE                  0                               /* Transfer Data Size */
-#define BITM_SDU_MACCTL_AUTOINC              (_ADI_MSK(0x00000010,uint32_t))  /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITM_SDU_MACCTL_RNW                  (_ADI_MSK(0x00000008,uint32_t))  /* Read Not Write */
-#define BITM_SDU_MACCTL_SIZE                 (_ADI_MSK(0x00000007,uint32_t))  /* Transfer Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MSG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MSG_CALLERR                 31                               /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITP_SDU_MSG_CALLBACK                30                               /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITP_SDU_MSG_CALLINIT                29                               /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITP_SDU_MSG_CALLAPP                 28                               /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITP_SDU_MSG_HALTONERR               27                               /* Generate an Emulation Exception Prior to an Error Call */
-#define BITP_SDU_MSG_HALTONCALL              26                               /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITP_SDU_MSG_HALTONINIT              25                               /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITP_SDU_MSG_HALTONAPP               24                               /* Generate an Emulation Exception Prior to an Application Call */
-#define BITP_SDU_MSG_L3INIT                  23                               /* Indicates that the L3 Resource is Initialized */
-#define BITP_SDU_MSG_L2INIT                  22                               /* Indicates that the L2 Resource is Initialized */
-#define BITP_SDU_MSG_C1L1INIT                17                               /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITP_SDU_MSG_C0L1INIT                16                               /* Indicates that the Core 0 L1 Resource is Initialized */
-#define BITM_SDU_MSG_CALLERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITM_SDU_MSG_CALLBACK                (_ADI_MSK(0x40000000,uint32_t))  /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITM_SDU_MSG_CALLINIT                (_ADI_MSK(0x20000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITM_SDU_MSG_CALLAPP                 (_ADI_MSK(0x10000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITM_SDU_MSG_HALTONERR               (_ADI_MSK(0x08000000,uint32_t))  /* Generate an Emulation Exception Prior to an Error Call */
-#define BITM_SDU_MSG_HALTONCALL              (_ADI_MSK(0x04000000,uint32_t))  /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITM_SDU_MSG_HALTONINIT              (_ADI_MSK(0x02000000,uint32_t))  /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITM_SDU_MSG_HALTONAPP               (_ADI_MSK(0x01000000,uint32_t))  /* Generate an Emulation Exception Prior to an Application Call */
-#define BITM_SDU_MSG_L3INIT                  (_ADI_MSK(0x00800000,uint32_t))  /* Indicates that the L3 Resource is Initialized */
-#define BITM_SDU_MSG_L2INIT                  (_ADI_MSK(0x00400000,uint32_t))  /* Indicates that the L2 Resource is Initialized */
-#define BITM_SDU_MSG_C1L1INIT                (_ADI_MSK(0x00020000,uint32_t))  /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITM_SDU_MSG_C0L1INIT                (_ADI_MSK(0x00010000,uint32_t))  /* Indicates that the Core 0 L1 Resource is Initialized */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_GHLT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_GHLT_SS2                    18                               /* Slave Select 2 */
-#define BITP_SDU_GHLT_SS1                    17                               /* Slave Select 1 */
-#define BITP_SDU_GHLT_SS0                    16                               /* Slave Select 0 */
-#define BITP_SDU_GHLT_MS2                     2                               /* Master Select 2 */
-#define BITP_SDU_GHLT_MS1                     1                               /* Master Select 1 */
-#define BITP_SDU_GHLT_MS0                     0                               /* Master Select 0 */
-#define BITM_SDU_GHLT_SS2                    (_ADI_MSK(0x00040000,uint32_t))  /* Slave Select 2 */
-#define BITM_SDU_GHLT_SS1                    (_ADI_MSK(0x00020000,uint32_t))  /* Slave Select 1 */
-#define BITM_SDU_GHLT_SS0                    (_ADI_MSK(0x00010000,uint32_t))  /* Slave Select 0 */
-#define BITM_SDU_GHLT_MS2                    (_ADI_MSK(0x00000004,uint32_t))  /* Master Select 2 */
-#define BITM_SDU_GHLT_MS1                    (_ADI_MSK(0x00000002,uint32_t))  /* Master Select 1 */
-#define BITM_SDU_GHLT_MS0                    (_ADI_MSK(0x00000001,uint32_t))  /* Master Select 0 */
-
-/* ==================================================
-        Ethernet MAC Registers
-   ================================================== */
-
-/* =========================
-        EMAC0
-   ========================= */
-#define REG_EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
-#define REG_EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 MAC Rx Frame Filter Register */
-#define REG_EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Hash Table High Register */
-#define REG_EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Hash Table Low Register */
-#define REG_EMAC0_SMI_ADDR              0xFFC20010         /* EMAC0 SMI Address Register */
-#define REG_EMAC0_SMI_DATA              0xFFC20014         /* EMAC0 SMI Data Register */
-#define REG_EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 FLow Control Register */
-#define REG_EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
-#define REG_EMAC0_DBG                   0xFFC20024         /* EMAC0 Debug Register */
-#define REG_EMAC0_ISTAT                 0xFFC20038         /* EMAC0 Interrupt Status Register */
-#define REG_EMAC0_IMSK                  0xFFC2003C         /* EMAC0 Interrupt Mask Register */
-#define REG_EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 MAC Address 0 High Register */
-#define REG_EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 MAC Address 0 Low Register */
-#define REG_EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
-#define REG_EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC Rx Interrupt Register */
-#define REG_EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC Tx Interrupt Register */
-#define REG_EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC Rx Interrupt Mask Register */
-#define REG_EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
-#define REG_EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Tx Multicast Frames (Good) Register */
-#define REG_EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Tx Underflow Error Register */
-#define REG_EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Tx Single Collision (Good) Register */
-#define REG_EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Tx Multiple Collision (Good) Register */
-#define REG_EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Tx Deferred Register */
-#define REG_EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Tx Late Collision Register */
-#define REG_EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Tx Excess Collision Register */
-#define REG_EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Tx Carrier Error Register */
-#define REG_EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Tx Octet Count (Good) Register */
-#define REG_EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Tx Frame Count (Good) Register */
-#define REG_EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Tx Excess Deferral Register */
-#define REG_EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Tx Pause Frame Register */
-#define REG_EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Tx VLAN Frames (Good) Register */
-#define REG_EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Rx Octet Count (Good) Register */
-#define REG_EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Rx Multicast Frames (Good) Register */
-#define REG_EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Rx CRC Error Register */
-#define REG_EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Rx alignment Error Register */
-#define REG_EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Rx Runt Error Register */
-#define REG_EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Rx Jab Error Register */
-#define REG_EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Rx Undersize (Good) Register */
-#define REG_EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Rx Oversize (Good) Register */
-#define REG_EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Rx Unicast Frames (Good) Register */
-#define REG_EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Rx Length Error Register */
-#define REG_EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Rx Out Of Range Type Register */
-#define REG_EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Rx Pause Frames Register */
-#define REG_EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Rx FIFO Overflow Register */
-#define REG_EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Rx Watch Dog Error Register */
-#define REG_EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC Rx Interrupt Register */
-#define REG_EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Rx UDP Good Frames Register */
-#define REG_EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Rx UDP Error Frames Register */
-#define REG_EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Rx TCP Good Frames Register */
-#define REG_EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Rx TCP Error Frames Register */
-#define REG_EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Rx ICMP Good Frames Register */
-#define REG_EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Rx ICMP Error Frames Register */
-#define REG_EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Rx IPv6 Good Octets Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Rx IPv6 Header Errors Register */
-#define REG_EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Rx UDP Good Octets Register */
-#define REG_EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Rx UDP Error Octets Register */
-#define REG_EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Rx TCP Good Octets Register */
-#define REG_EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Rx TCP Error Octets Register */
-#define REG_EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Rx ICMP Good Octets Register */
-#define REG_EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Rx ICMP Error Octets Register */
-#define REG_EMAC0_TM_CTL                0xFFC20700         /* EMAC0 Time Stamp Control Register */
-#define REG_EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 Time Stamp Sub Second Increment Register */
-#define REG_EMAC0_TM_SEC                0xFFC20708         /* EMAC0 Time Stamp Low Seconds Register */
-#define REG_EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 Time Stamp Nano Seconds Register */
-#define REG_EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 Time Stamp Seconds Update Register */
-#define REG_EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 Time Stamp Addend Register */
-#define REG_EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 Time Stamp Target Time Seconds Register */
-#define REG_EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 Time Stamp High Second Register */
-#define REG_EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 Time Stamp Status Register */
-#define REG_EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 PPS Control Register */
-#define REG_EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC0_TM_PPSINTVL           0xFFC20760         /* EMAC0 Time Stamp PPS Interval Register */
-#define REG_EMAC0_TM_PPSWIDTH           0xFFC20764         /* EMAC0 PPS Width Register */
-#define REG_EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 DMA Bus Mode Register */
-#define REG_EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 DMA Tx Poll Demand Register */
-#define REG_EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 DMA Rx Poll Demand register */
-#define REG_EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define REG_EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define REG_EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
-#define REG_EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
-#define REG_EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
-#define REG_EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA Missed Frame Register */
-#define REG_EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 DMA SCB Bus Mode Register */
-#define REG_EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 DMA SCB Status Register */
-#define REG_EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 DMA Tx Descriptor Current Register */
-#define REG_EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 DMA Rx Descriptor Current Register */
-#define REG_EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 DMA Tx Buffer Current Register */
-#define REG_EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC1
-   ========================= */
-#define REG_EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
-#define REG_EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 MAC Rx Frame Filter Register */
-#define REG_EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Hash Table High Register */
-#define REG_EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Hash Table Low Register */
-#define REG_EMAC1_SMI_ADDR              0xFFC22010         /* EMAC1 SMI Address Register */
-#define REG_EMAC1_SMI_DATA              0xFFC22014         /* EMAC1 SMI Data Register */
-#define REG_EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 FLow Control Register */
-#define REG_EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
-#define REG_EMAC1_DBG                   0xFFC22024         /* EMAC1 Debug Register */
-#define REG_EMAC1_ISTAT                 0xFFC22038         /* EMAC1 Interrupt Status Register */
-#define REG_EMAC1_IMSK                  0xFFC2203C         /* EMAC1 Interrupt Mask Register */
-#define REG_EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 MAC Address 0 High Register */
-#define REG_EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 MAC Address 0 Low Register */
-#define REG_EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
-#define REG_EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC Rx Interrupt Register */
-#define REG_EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC Tx Interrupt Register */
-#define REG_EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC Rx Interrupt Mask Register */
-#define REG_EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
-#define REG_EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Tx Multicast Frames (Good) Register */
-#define REG_EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Tx Underflow Error Register */
-#define REG_EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Tx Single Collision (Good) Register */
-#define REG_EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Tx Multiple Collision (Good) Register */
-#define REG_EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Tx Deferred Register */
-#define REG_EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Tx Late Collision Register */
-#define REG_EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Tx Excess Collision Register */
-#define REG_EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Tx Carrier Error Register */
-#define REG_EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Tx Octet Count (Good) Register */
-#define REG_EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Tx Frame Count (Good) Register */
-#define REG_EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Tx Excess Deferral Register */
-#define REG_EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Tx Pause Frame Register */
-#define REG_EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Tx VLAN Frames (Good) Register */
-#define REG_EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Rx Octet Count (Good) Register */
-#define REG_EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Rx Multicast Frames (Good) Register */
-#define REG_EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Rx CRC Error Register */
-#define REG_EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Rx alignment Error Register */
-#define REG_EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Rx Runt Error Register */
-#define REG_EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Rx Jab Error Register */
-#define REG_EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Rx Undersize (Good) Register */
-#define REG_EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Rx Oversize (Good) Register */
-#define REG_EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Rx Unicast Frames (Good) Register */
-#define REG_EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Rx Length Error Register */
-#define REG_EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Rx Out Of Range Type Register */
-#define REG_EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Rx Pause Frames Register */
-#define REG_EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Rx FIFO Overflow Register */
-#define REG_EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Rx Watch Dog Error Register */
-#define REG_EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC Rx Interrupt Register */
-#define REG_EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Rx UDP Good Frames Register */
-#define REG_EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Rx UDP Error Frames Register */
-#define REG_EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Rx TCP Good Frames Register */
-#define REG_EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Rx TCP Error Frames Register */
-#define REG_EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Rx ICMP Good Frames Register */
-#define REG_EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Rx ICMP Error Frames Register */
-#define REG_EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Rx IPv6 Good Octets Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Rx IPv6 Header Errors Register */
-#define REG_EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Rx UDP Good Octets Register */
-#define REG_EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Rx UDP Error Octets Register */
-#define REG_EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Rx TCP Good Octets Register */
-#define REG_EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Rx TCP Error Octets Register */
-#define REG_EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Rx ICMP Good Octets Register */
-#define REG_EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Rx ICMP Error Octets Register */
-#define REG_EMAC1_TM_CTL                0xFFC22700         /* EMAC1 Time Stamp Control Register */
-#define REG_EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 Time Stamp Sub Second Increment Register */
-#define REG_EMAC1_TM_SEC                0xFFC22708         /* EMAC1 Time Stamp Low Seconds Register */
-#define REG_EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 Time Stamp Nano Seconds Register */
-#define REG_EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 Time Stamp Seconds Update Register */
-#define REG_EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 Time Stamp Addend Register */
-#define REG_EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 Time Stamp Target Time Seconds Register */
-#define REG_EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 Time Stamp High Second Register */
-#define REG_EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 Time Stamp Status Register */
-#define REG_EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 PPS Control Register */
-#define REG_EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC1_TM_PPSINTVL           0xFFC22760         /* EMAC1 Time Stamp PPS Interval Register */
-#define REG_EMAC1_TM_PPSWIDTH           0xFFC22764         /* EMAC1 PPS Width Register */
-#define REG_EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 DMA Bus Mode Register */
-#define REG_EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 DMA Tx Poll Demand Register */
-#define REG_EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 DMA Rx Poll Demand register */
-#define REG_EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define REG_EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define REG_EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
-#define REG_EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
-#define REG_EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
-#define REG_EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA Missed Frame Register */
-#define REG_EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 DMA SCB Bus Mode Register */
-#define REG_EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 DMA SCB Status Register */
-#define REG_EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 DMA Tx Descriptor Current Register */
-#define REG_EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 DMA Rx Descriptor Current Register */
-#define REG_EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 DMA Tx Buffer Current Register */
-#define REG_EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACCFG_CST                 25                               /* CRC Stripping */
-#define BITP_EMAC_MACCFG_WD                  23                               /* Watch Dog Disable */
-#define BITP_EMAC_MACCFG_JB                  22                               /* Jabber Disable */
-#define BITP_EMAC_MACCFG_JE                  20                               /* Jumbo Frame Enable */
-#define BITP_EMAC_MACCFG_IFG                 17                               /* Inter Frame Gap */
-#define BITP_EMAC_MACCFG_DCRS                16                               /* Disable Carrier Sense */
-#define BITP_EMAC_MACCFG_FES                 14                               /* Speed of Operation */
-#define BITP_EMAC_MACCFG_DO                  13                               /* Disable Receive Own */
-#define BITP_EMAC_MACCFG_LM                  12                               /* Loopback Mode */
-#define BITP_EMAC_MACCFG_DM                  11                               /* Duplex Mode */
-#define BITP_EMAC_MACCFG_IPC                 10                               /* IP Checksum */
-#define BITP_EMAC_MACCFG_DR                   9                               /* Disable Retry */
-#define BITP_EMAC_MACCFG_ACS                  7                               /* Automatic Pad/CRC Stripping */
-#define BITP_EMAC_MACCFG_BL                   5                               /* Back Off Limit */
-#define BITP_EMAC_MACCFG_DC                   4                               /* Deferral Check */
-#define BITP_EMAC_MACCFG_TE                   3                               /* Transmitter Enable */
-#define BITP_EMAC_MACCFG_RE                   2                               /* Receiver Enable */
-#define BITM_EMAC_MACCFG_CST                 (_ADI_MSK(0x02000000,uint32_t))  /* CRC Stripping */
-#define BITM_EMAC_MACCFG_WD                  (_ADI_MSK(0x00800000,uint32_t))  /* Watch Dog Disable */
-#define BITM_EMAC_MACCFG_JB                  (_ADI_MSK(0x00400000,uint32_t))  /* Jabber Disable */
-#define BITM_EMAC_MACCFG_JE                  (_ADI_MSK(0x00100000,uint32_t))  /* Jumbo Frame Enable */
-
-#define BITM_EMAC_MACCFG_IFG                 (_ADI_MSK(0x000E0000,uint32_t))  /* Inter Frame Gap */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_96        (_ADI_MSK(0x00000000,uint32_t))  /* IFG: 96 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_88        (_ADI_MSK(0x00020000,uint32_t))  /* IFG: 88 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_80        (_ADI_MSK(0x00040000,uint32_t))  /* IFG: 80 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_72        (_ADI_MSK(0x00060000,uint32_t))  /* IFG: 72 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_64        (_ADI_MSK(0x00080000,uint32_t))  /* IFG: 64 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_56        (_ADI_MSK(0x000A0000,uint32_t))  /* IFG: 56 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_48        (_ADI_MSK(0x000C0000,uint32_t))  /* IFG: 48 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_40        (_ADI_MSK(0x000E0000,uint32_t))  /* IFG: 40 bit times */
-#define BITM_EMAC_MACCFG_DCRS                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Carrier Sense */
-#define BITM_EMAC_MACCFG_FES                 (_ADI_MSK(0x00004000,uint32_t))  /* Speed of Operation */
-#define BITM_EMAC_MACCFG_DO                  (_ADI_MSK(0x00002000,uint32_t))  /* Disable Receive Own */
-#define BITM_EMAC_MACCFG_LM                  (_ADI_MSK(0x00001000,uint32_t))  /* Loopback Mode */
-#define BITM_EMAC_MACCFG_DM                  (_ADI_MSK(0x00000800,uint32_t))  /* Duplex Mode */
-#define BITM_EMAC_MACCFG_IPC                 (_ADI_MSK(0x00000400,uint32_t))  /* IP Checksum */
-
-#define BITM_EMAC_MACCFG_DR                  (_ADI_MSK(0x00000200,uint32_t))  /* Disable Retry */
-#define ENUM_EMAC_MACCFG_RETRY_ENABLED       (_ADI_MSK(0x00000000,uint32_t))  /* DR: Retry enabled */
-#define ENUM_EMAC_MACCFG_RETRY_DISABLED      (_ADI_MSK(0x00000200,uint32_t))  /* DR: Retry disabled */
-#define BITM_EMAC_MACCFG_ACS                 (_ADI_MSK(0x00000080,uint32_t))  /* Automatic Pad/CRC Stripping */
-
-#define BITM_EMAC_MACCFG_BL                  (_ADI_MSK(0x00000060,uint32_t))  /* Back Off Limit */
-#define ENUM_EMAC_MACCFG_BL_10               (_ADI_MSK(0x00000000,uint32_t))  /* BL: k = min (n, 10) */
-#define ENUM_EMAC_MACCFG_BL_8                (_ADI_MSK(0x00000020,uint32_t))  /* BL: k = min (n, 8) */
-#define ENUM_EMAC_MACCFG_BL_4                (_ADI_MSK(0x00000040,uint32_t))  /* BL: k = min (n, 4) */
-#define ENUM_EMAC_MACCFG_BL_1                (_ADI_MSK(0x00000060,uint32_t))  /* BL: k = min (n, 1) */
-#define BITM_EMAC_MACCFG_DC                  (_ADI_MSK(0x00000010,uint32_t))  /* Deferral Check */
-#define BITM_EMAC_MACCFG_TE                  (_ADI_MSK(0x00000008,uint32_t))  /* Transmitter Enable */
-#define BITM_EMAC_MACCFG_RE                  (_ADI_MSK(0x00000004,uint32_t))  /* Receiver Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACFRMFILT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACFRMFILT_RA              31                               /* Receive All Frames */
-#define BITP_EMAC_MACFRMFILT_HPF             10                               /* Hash or Perfect Filter */
-#define BITP_EMAC_MACFRMFILT_PCF              6                               /* Pass Control Frames */
-#define BITP_EMAC_MACFRMFILT_DBF              5                               /* Disable Broadcast Frames */
-#define BITP_EMAC_MACFRMFILT_PM               4                               /* Pass All Multicast Frames */
-#define BITP_EMAC_MACFRMFILT_DAIF             3                               /* Destination Address Inverse Filtering */
-#define BITP_EMAC_MACFRMFILT_HMC              2                               /* Hash Multicast */
-#define BITP_EMAC_MACFRMFILT_HUC              1                               /* Hash Unicast */
-#define BITP_EMAC_MACFRMFILT_PR               0                               /* Promiscuous Mode */
-#define BITM_EMAC_MACFRMFILT_RA              (_ADI_MSK(0x80000000,uint32_t))  /* Receive All Frames */
-#define BITM_EMAC_MACFRMFILT_HPF             (_ADI_MSK(0x00000400,uint32_t))  /* Hash or Perfect Filter */
-
-#define BITM_EMAC_MACFRMFILT_PCF             (_ADI_MSK(0x000000C0,uint32_t))  /* Pass Control Frames */
-#define ENUM_EMAC_MACFRMFILT_FILT_ALL        (_ADI_MSK(0x00000000,uint32_t))  /* PCF: Pass no control frames */
-#define ENUM_EMAC_MACFRMFILT_NO_PAUSE        (_ADI_MSK(0x00000040,uint32_t))  /* PCF: Pass no PAUSE frames */
-#define ENUM_EMAC_MACFRMFILT_FWD_ALL         (_ADI_MSK(0x00000080,uint32_t))  /* PCF: Pass all control frames */
-#define ENUM_EMAC_MACFRMFILT_PADR_FILT       (_ADI_MSK(0x000000C0,uint32_t))  /* PCF: Pass address filtered control frames */
-
-#define BITM_EMAC_MACFRMFILT_DBF             (_ADI_MSK(0x00000020,uint32_t))  /* Disable Broadcast Frames */
-#define ENUM_EMAC_MACFRMFILT_DIS_BCAST       (_ADI_MSK(0x00000000,uint32_t))  /* DBF: AFM module passes all received broadcast frames */
-#define ENUM_EMAC_MACFRMFILT_EN_BCAST        (_ADI_MSK(0x00000020,uint32_t))  /* DBF: AFM module filters all incoming broadcast frames */
-#define BITM_EMAC_MACFRMFILT_PM              (_ADI_MSK(0x00000010,uint32_t))  /* Pass All Multicast Frames */
-#define BITM_EMAC_MACFRMFILT_DAIF            (_ADI_MSK(0x00000008,uint32_t))  /* Destination Address Inverse Filtering */
-#define BITM_EMAC_MACFRMFILT_HMC             (_ADI_MSK(0x00000004,uint32_t))  /* Hash Multicast */
-#define BITM_EMAC_MACFRMFILT_HUC             (_ADI_MSK(0x00000002,uint32_t))  /* Hash Unicast */
-#define BITM_EMAC_MACFRMFILT_PR              (_ADI_MSK(0x00000001,uint32_t))  /* Promiscuous Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_ADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_ADDR_PA                11                               /* Physical Layer Address */
-#define BITP_EMAC_SMI_ADDR_SMIR               6                               /* SMI Register Address */
-#define BITP_EMAC_SMI_ADDR_CR                 2                               /* Clock Range */
-#define BITP_EMAC_SMI_ADDR_SMIW               1                               /* SMI Write */
-#define BITP_EMAC_SMI_ADDR_SMIB               0                               /* SMI Busy */
-#define BITM_EMAC_SMI_ADDR_PA                (_ADI_MSK(0x0000F800,uint32_t))  /* Physical Layer Address */
-#define BITM_EMAC_SMI_ADDR_SMIR              (_ADI_MSK(0x000007C0,uint32_t))  /* SMI Register Address */
-#define BITM_EMAC_SMI_ADDR_CR                (_ADI_MSK(0x0000003C,uint32_t))  /* Clock Range */
-#define BITM_EMAC_SMI_ADDR_SMIW              (_ADI_MSK(0x00000002,uint32_t))  /* SMI Write */
-#define BITM_EMAC_SMI_ADDR_SMIB              (_ADI_MSK(0x00000001,uint32_t))  /* SMI Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_DATA                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_DATA_SMID               0                               /* SMI Data */
-#define BITM_EMAC_SMI_DATA_SMID              (_ADI_MSK(0x0000FFFF,uint32_t))  /* SMI Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_FLOWCTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_FLOWCTL_PT                 16                               /* Pause Time */
-#define BITP_EMAC_FLOWCTL_UP                  3                               /* Unicast Pause Frame Detect */
-#define BITP_EMAC_FLOWCTL_RFE                 2                               /* Receive Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_TFE                 1                               /* Transmit Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_FCBBPA              0                               /* Initiate Pause Control Frame */
-#define BITM_EMAC_FLOWCTL_PT                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Pause Time */
-#define BITM_EMAC_FLOWCTL_UP                 (_ADI_MSK(0x00000008,uint32_t))  /* Unicast Pause Frame Detect */
-#define BITM_EMAC_FLOWCTL_RFE                (_ADI_MSK(0x00000004,uint32_t))  /* Receive Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_TFE                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_FCBBPA             (_ADI_MSK(0x00000001,uint32_t))  /* Initiate Pause Control Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_VLANTAG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_VLANTAG_ETV                16                               /* Enable Tag VLAN Comparison */
-#define BITP_EMAC_VLANTAG_VL                  0                               /* VLAN Tag Id Receive Frames */
-#define BITM_EMAC_VLANTAG_ETV                (_ADI_MSK(0x00010000,uint32_t))  /* Enable Tag VLAN Comparison */
-#define BITM_EMAC_VLANTAG_VL                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* VLAN Tag Id Receive Frames */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DBG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DBG_TXFIFOFULL             25                               /* Tx FIFO Full */
-#define BITP_EMAC_DBG_TXFIFONE               24                               /* Tx FIFO Not Empty */
-#define BITP_EMAC_DBG_TXFIFOACT              22                               /* Tx FIFO Active */
-#define BITP_EMAC_DBG_TXFIFOCTLST            20                               /* Tx FIFO Controller State */
-#define BITP_EMAC_DBG_TXPAUSE                19                               /* Tx Paused */
-#define BITP_EMAC_DBG_TXFRCTL                17                               /* Tx Frame Controller State */
-#define BITP_EMAC_DBG_MMTEA                  16                               /* MM Tx Engine Active */
-#define BITP_EMAC_DBG_RXFIFOST                8                               /* Rx FIFO State */
-#define BITP_EMAC_DBG_RXFIFOCTLST             5                               /* Rx FIFO Controller State */
-#define BITP_EMAC_DBG_RXFIFOACT               4                               /* Rx FIFO Active */
-#define BITP_EMAC_DBG_SFIFOST                 1                               /* Small FIFO State */
-#define BITP_EMAC_DBG_MMREA                   0                               /* MM Rx Engine Active */
-#define BITM_EMAC_DBG_TXFIFOFULL             (_ADI_MSK(0x02000000,uint32_t))  /* Tx FIFO Full */
-#define BITM_EMAC_DBG_TXFIFONE               (_ADI_MSK(0x01000000,uint32_t))  /* Tx FIFO Not Empty */
-#define BITM_EMAC_DBG_TXFIFOACT              (_ADI_MSK(0x00400000,uint32_t))  /* Tx FIFO Active */
-#define BITM_EMAC_DBG_TXFIFOCTLST            (_ADI_MSK(0x00300000,uint32_t))  /* Tx FIFO Controller State */
-#define BITM_EMAC_DBG_TXPAUSE                (_ADI_MSK(0x00080000,uint32_t))  /* Tx Paused */
-
-#define BITM_EMAC_DBG_TXFRCTL                (_ADI_MSK(0x00060000,uint32_t))  /* Tx Frame Controller State */
-#define ENUM_EMAC_DBG_TXFRCTL_IDLE           (_ADI_MSK(0x00000000,uint32_t))  /* TXFRCTL: Idle */
-#define ENUM_EMAC_DBG_TXFRCTL_WT_STATUS      (_ADI_MSK(0x00020000,uint32_t))  /* TXFRCTL: Wait */
-#define ENUM_EMAC_DBG_TXFRCTL_PAUSE          (_ADI_MSK(0x00040000,uint32_t))  /* TXFRCTL: Pause */
-#define ENUM_EMAC_DBG_TXFRCTL_TXFRAME        (_ADI_MSK(0x00060000,uint32_t))  /* TXFRCTL: Transmit */
-#define BITM_EMAC_DBG_MMTEA                  (_ADI_MSK(0x00010000,uint32_t))  /* MM Tx Engine Active */
-
-#define BITM_EMAC_DBG_RXFIFOST               (_ADI_MSK(0x00000300,uint32_t))  /* Rx FIFO State */
-#define ENUM_EMAC_DBG_FIFO_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOST: Rx FIFO Empty */
-#define ENUM_EMAC_DBG_FIFO_BEL_THERSHLD      (_ADI_MSK(0x00000100,uint32_t))  /* RXFIFOST: Rx FIFO Below De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_ABV_THERSHLD      (_ADI_MSK(0x00000200,uint32_t))  /* RXFIFOST: Rx FIFO Above De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_FULL              (_ADI_MSK(0x00000300,uint32_t))  /* RXFIFOST: Rx FIFO Full */
-
-#define BITM_EMAC_DBG_RXFIFOCTLST            (_ADI_MSK(0x00000060,uint32_t))  /* Rx FIFO Controller State */
-#define ENUM_EMAC_DBG_IDLE_FIFO              (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOCTLST: Idle */
-#define ENUM_EMAC_DBG_RD_DATA_FIFO           (_ADI_MSK(0x00000020,uint32_t))  /* RXFIFOCTLST: Read Data */
-#define ENUM_EMAC_DBG_RD_STS_FIFO            (_ADI_MSK(0x00000040,uint32_t))  /* RXFIFOCTLST: Read Status */
-#define ENUM_EMAC_DBG_FLUSH_FIFO             (_ADI_MSK(0x00000060,uint32_t))  /* RXFIFOCTLST: Flush */
-#define BITM_EMAC_DBG_RXFIFOACT              (_ADI_MSK(0x00000010,uint32_t))  /* Rx FIFO Active */
-#define BITM_EMAC_DBG_SFIFOST                (_ADI_MSK(0x00000006,uint32_t))  /* Small FIFO State */
-#define BITM_EMAC_DBG_MMREA                  (_ADI_MSK(0x00000001,uint32_t))  /* MM Rx Engine Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ISTAT_TS                    9                               /* Time Stamp Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRC                 7                               /* MMC Receive Checksum Offload Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCTX                 6                               /* MMC Transmit Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRX                 5                               /* MMC Receive Interrupt Status */
-#define BITP_EMAC_ISTAT_MMC                   4                               /* MMC Interrupt Status */
-#define BITM_EMAC_ISTAT_TS                   (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRC                (_ADI_MSK(0x00000080,uint32_t))  /* MMC Receive Checksum Offload Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCTX                (_ADI_MSK(0x00000040,uint32_t))  /* MMC Transmit Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRX                (_ADI_MSK(0x00000020,uint32_t))  /* MMC Receive Interrupt Status */
-#define BITM_EMAC_ISTAT_MMC                  (_ADI_MSK(0x00000010,uint32_t))  /* MMC Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IMSK_TS                     9                               /* Time Stamp Interrupt Mask */
-#define BITM_EMAC_IMSK_TS                    (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ADDR0_HI                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ADDR0_HI_ADDR               0                               /* Address */
-#define BITM_EMAC_ADDR0_HI_ADDR              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_CTL_FULLPSET            5                               /* Full Preset */
-#define BITP_EMAC_MMC_CTL_CNTRPSET            4                               /* Counter Reset/Preset */
-#define BITP_EMAC_MMC_CTL_CNTRFRZ             3                               /* Counter Freeze */
-#define BITP_EMAC_MMC_CTL_RDRST               2                               /* Read Reset */
-#define BITP_EMAC_MMC_CTL_NOROLL              1                               /* No Rollover */
-#define BITP_EMAC_MMC_CTL_RST                 0                               /* Reset */
-#define BITM_EMAC_MMC_CTL_FULLPSET           (_ADI_MSK(0x00000020,uint32_t))  /* Full Preset */
-#define BITM_EMAC_MMC_CTL_CNTRPSET           (_ADI_MSK(0x00000010,uint32_t))  /* Counter Reset/Preset */
-#define BITM_EMAC_MMC_CTL_CNTRFRZ            (_ADI_MSK(0x00000008,uint32_t))  /* Counter Freeze */
-#define BITM_EMAC_MMC_CTL_RDRST              (_ADI_MSK(0x00000004,uint32_t))  /* Read Reset */
-#define BITM_EMAC_MMC_CTL_NOROLL             (_ADI_MSK(0x00000002,uint32_t))  /* No Rollover */
-#define BITM_EMAC_MMC_CTL_RST                (_ADI_MSK(0x00000001,uint32_t))  /* Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXINT_WDOGERR          23                               /* Rx Watch Dog Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_VLANFRGB         22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_FIFOOVF          21                               /* Rx FIFO Overflow Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_PAUSEFR          20                               /* Rx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OUTRANGE         19                               /* Rx Out Of Range Type Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_LENERR           18                               /* Rx Length Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_UCASTG           17                               /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R1024TOMAX       16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R512TO1023       15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R256TO511        14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R128TO255        13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R65TO127         12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R64              11                               /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OSIZEG           10                               /* Rx Oversize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_USIZEG            9                               /* Rx Undersize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_JABERR            8                               /* Rx Jabber Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_RUNTERR           7                               /* Rx Runt Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_ALIGNERR          6                               /* Rx Alignment Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_CRCERR            5                               /* Rx CRC Error Counter Half/Full */
-#define BITP_EMAC_MMC_RXINT_MCASTG            4                               /* Rx Multicast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_BCASTG            3                               /* Rx Broadcast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTG           2                               /* Octet Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTGB          1                               /* Octet Count (Good/Bad) Half/Full */
-#define BITP_EMAC_MMC_RXINT_FRCNTGB           0                               /* Frame Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_WDOGERR          (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_VLANFRGB         (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_FIFOOVF          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_PAUSEFR          (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OUTRANGE         (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_LENERR           (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_UCASTG           (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R1024TOMAX       (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R512TO1023       (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R256TO511        (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R128TO255        (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R65TO127         (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R64              (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OSIZEG           (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_USIZEG           (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_JABERR           (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_RUNTERR          (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_ALIGNERR         (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_CRCERR           (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Counter Half/Full */
-#define BITM_EMAC_MMC_RXINT_MCASTG           (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_BCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTG          (_ADI_MSK(0x00000004,uint32_t))  /* Octet Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Octet Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_FRCNTGB          (_ADI_MSK(0x00000001,uint32_t))  /* Frame Count (Good/Bad) Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXINT_VLANFRGB         24                               /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_PAUSEFRM         23                               /* Tx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSDEF        22                               /* Tx Excess Deferred Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTG           21                               /* Tx Frame Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTG          20                               /* Tx Octet Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_CARRERR          19                               /* Tx Carrier Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSCOL        18                               /* Tx Exess Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_LATECOL          17                               /* Tx Late Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_DEFERRED         16                               /* Tx Deffered Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MULTCOLG         15                               /* Tx Multiple collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_SNGCOLG          14                               /* Tx Single Collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UNDERR           13                               /* Tx Underflow Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTGB          12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTGB          11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UCASTGB          10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T1024TOMAX        9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T512TO1023        8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T256TO511         7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T128TO255         6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T65TO127          5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T64               4                               /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTG            3                               /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTG            2                               /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTGB           1                               /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTGB          0                               /* Tx Octet Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_VLANFRGB         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_PAUSEFRM         (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSDEF        (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTG           (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTG          (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_CARRERR          (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSCOL        (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_LATECOL          (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_DEFERRED         (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deffered Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MULTCOLG         (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_SNGCOLG          (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UNDERR           (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTGB          (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTGB          (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UCASTGB          (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T1024TOMAX       (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T512TO1023       (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T256TO511        (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T128TO255        (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T65TO127         (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T64              (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTG           (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTGB          (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXIMSK_WATCHERR        23                               /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_VLANFRGB        22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FIFOOV          21                               /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_PAUSEFRM        20                               /* Rx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OUTRANGE        19                               /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_LENERR          18                               /* Rx Length Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_UCASTG          17                               /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R1024TOMAX      16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R512TO1023      15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R256TO511       14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R128TO255       13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R65TO127        12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R64             11                               /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OSIZEG          10                               /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_USIZEG           9                               /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_JABERR           8                               /* Rx Jabber Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_RUNTERR          7                               /* Rx Runt Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_ALIGNERR         6                               /* Rx Alignment Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_CRCERR           5                               /* Rx CRC Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_MCASTG           4                               /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_BCASTG           3                               /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTG          2                               /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTGB         1                               /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FRCNTGB          0                               /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_WATCHERR        (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_VLANFRGB        (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FIFOOV          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_PAUSEFRM        (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OUTRANGE        (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_LENERR          (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_UCASTG          (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R1024TOMAX      (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R512TO1023      (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R256TO511       (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R128TO255       (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R65TO127        (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R64             (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OSIZEG          (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_USIZEG          (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_JABERR          (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_RUNTERR         (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_ALIGNERR        (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_CRCERR          (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_MCASTG          (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_BCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTG         (_ADI_MSK(0x00000004,uint32_t))  /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTGB        (_ADI_MSK(0x00000002,uint32_t))  /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FRCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXIMSK_VLANFRG         24                               /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_PAUSEFRM        23                               /* Tx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSDEF       22                               /* Tx Excess Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTG          21                               /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTG         20                               /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_CARRERR         19                               /* Tx Carrier Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSCOL       18                               /* Tx Exess collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_LATECOL         17                               /* Tx Late Collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_DEFERRED        16                               /* Tx Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MULTCOLG        15                               /* Tx Multiple Collisions (Good) Count Mask */
-#define BITP_EMAC_MMC_TXIMSK_SNGCOLG         14                               /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UNDERR          13                               /* Tx Underflow Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTGB         12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTGB         11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UCASTGB         10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T1024TOMAX       9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T512TO1023       8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T256TO511        7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T128TO255        6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T65TO127         5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T64              4                               /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTG           3                               /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTG           2                               /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTGB          1                               /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTGB         0                               /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_VLANFRG         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_PAUSEFRM        (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSDEF       (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTG          (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTG         (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_CARRERR         (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSCOL       (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_LATECOL         (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_DEFERRED        (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MULTCOLG        (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple Collisions (Good) Count Mask */
-#define BITM_EMAC_MMC_TXIMSK_SNGCOLG         (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UNDERR          (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTGB         (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTGB         (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UCASTGB         (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T1024TOMAX      (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T512TO1023      (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T256TO511       (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T128TO255       (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T65TO127        (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T64             (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTG          (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTGB        (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERROCT      29                               /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGOCT        28                               /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERROCT       27                               /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGOCT         26                               /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERROCT       25                               /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGOCT         24                               /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYOCT      23                               /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERROCT      22                               /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GOCT          21                               /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLOCT      20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGOCT       19                               /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYOCT      18                               /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERROCT      17                               /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GOCT          16                               /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERRFRM      13                               /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGFRM        12                               /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERRFRM       11                               /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGFRM         10                               /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERRFRM        9                               /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGFRM          8                               /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYFRM       7                               /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERRFRM       6                               /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GFRM           5                               /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLFRM       4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGFRM        3                               /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYFRM       2                               /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERRFRM       1                               /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GFRM           0                               /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERROCT      (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGOCT        (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERROCT       (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGOCT         (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERROCT       (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGOCT         (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYOCT      (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERROCT      (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GOCT          (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLOCT      (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGOCT       (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYOCT      (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERROCT      (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GOCT          (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERRFRM      (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGFRM        (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERRFRM       (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGFRM         (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERRFRM       (_ADI_MSK(0x00000200,uint32_t))  /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGFRM         (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYFRM      (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERRFRM      (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GFRM          (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLFRM      (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGFRM       (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYFRM      (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERRFRM      (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GFRM          (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXINT_ICMPERROCT       29                               /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGOCT         28                               /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERROCT        27                               /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGOCT          26                               /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERROCT        25                               /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGOCT          24                               /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYOCT       23                               /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERROCT       22                               /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GOCT           21                               /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLOCT       20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGOCT        19                               /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYOCT       18                               /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERROCT       17                               /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GOCT           16                               /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPERRFRM       13                               /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGFRM         12                               /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERRFRM        11                               /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGFRM          10                               /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERRFRM         9                               /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGFRM           8                               /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYFRM        7                               /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERRFRM        6                               /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GFRM            5                               /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLFRM        4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGFRM         3                               /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYFRM        2                               /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERRFRM        1                               /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GFRM            0                               /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERROCT       (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGOCT         (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERROCT        (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGOCT          (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERROCT        (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGOCT          (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYOCT       (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERROCT       (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GOCT           (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLOCT       (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGOCT        (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYOCT       (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERROCT       (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GOCT           (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERRFRM       (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGFRM         (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERRFRM        (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGFRM          (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERRFRM        (_ADI_MSK(0x00000200,uint32_t))  /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGFRM          (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYFRM       (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERRFRM       (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GFRM           (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLFRM       (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGFRM        (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYFRM       (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERRFRM       (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GFRM           (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_CTL_ATSFC               24                               /* Auxilary Time Stamp FIFO Clear */
-#define BITP_EMAC_TM_CTL_TSENMACADDR         18                               /* Time Stamp Enable MAC Address */
-#define BITP_EMAC_TM_CTL_SNAPTYPSEL          16                               /* Snapshot Type Select */
-#define BITP_EMAC_TM_CTL_TSMSTRENA           15                               /* Time Stamp Master (Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSEVNTENA           14                               /* Time Stamp Event (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV4ENA           13                               /* Time Stamp IPV4 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV6ENA           12                               /* Time Stamp IPV6 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPENA             11                               /* Time Stamp IP Enable */
-#define BITP_EMAC_TM_CTL_TSVER2ENA           10                               /* Time Stamp VER2 (Snooping) Enable */
-#define BITP_EMAC_TM_CTL_TSCTRLSSR            9                               /* Time Stamp Control Nanosecond Rollover */
-#define BITP_EMAC_TM_CTL_TSENALL              8                               /* Time Stamp Enable All (Frames) */
-#define BITP_EMAC_TM_CTL_TSADDREG             5                               /* Time Stamp Addend Register Update */
-#define BITP_EMAC_TM_CTL_TSTRIG               4                               /* Time Stamp (Target Time) Trigger Enable */
-#define BITP_EMAC_TM_CTL_TSUPDT               3                               /* Time Stamp (System Time) Update */
-#define BITP_EMAC_TM_CTL_TSINIT               2                               /* Time Stamp (System Time) Initialize */
-#define BITP_EMAC_TM_CTL_TSCFUPDT             1                               /* Time Stamp (System Time) Fine/Coarse Update */
-#define BITP_EMAC_TM_CTL_TSENA                0                               /* Time Stamp (PTP) Enable */
-#define BITM_EMAC_TM_CTL_ATSFC               (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp FIFO Clear */
-
-#define BITM_EMAC_TM_CTL_TSENMACADDR         (_ADI_MSK(0x00040000,uint32_t))  /* Time Stamp Enable MAC Address */
-#define ENUM_EMAC_TM_CTL_D_PTP_ADDRFILT      (_ADI_MSK(0x00000000,uint32_t))  /* TSENMACADDR: Disable PTP MAC address filter */
-#define ENUM_EMAC_TM_CTL_E_PTP_ADDRFILT      (_ADI_MSK(0x00040000,uint32_t))  /* TSENMACADDR: Enable PTP MAC address filter */
-#define BITM_EMAC_TM_CTL_SNAPTYPSEL          (_ADI_MSK(0x00030000,uint32_t))  /* Snapshot Type Select */
-
-#define BITM_EMAC_TM_CTL_TSMSTRENA           (_ADI_MSK(0x00008000,uint32_t))  /* Time Stamp Master (Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_SLVSNPT_MSGS      (_ADI_MSK(0x00000000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Slave Messages */
-#define ENUM_EMAC_TM_CTL_E_MSSNPST_MSGS      (_ADI_MSK(0x00008000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Master Messages */
-
-#define BITM_EMAC_TM_CTL_TSEVNTENA           (_ADI_MSK(0x00004000,uint32_t))  /* Time Stamp Event (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_ATSTMP_MSGS       (_ADI_MSK(0x00000000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for All Messages */
-#define ENUM_EMAC_TM_CTL_E_ETSTMP_MSGS       (_ADI_MSK(0x00004000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for Event Messages Only */
-
-#define BITM_EMAC_TM_CTL_TSIPV4ENA           (_ADI_MSK(0x00002000,uint32_t))  /* Time Stamp IPV4 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV4        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV4ENA: Disable Time Stamp for PTP Over IPv4 Frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV4        (_ADI_MSK(0x00002000,uint32_t))  /* TSIPV4ENA: Enable Time Stamp for PTP Over IPv4 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPV6ENA           (_ADI_MSK(0x00001000,uint32_t))  /* Time Stamp IPV6 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV6        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV6ENA: Disable Time Stamp for PTP Over IPv6 frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV6        (_ADI_MSK(0x00001000,uint32_t))  /* TSIPV6ENA: Enable Time Stamp for PTP Over IPv6 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPENA             (_ADI_MSK(0x00000800,uint32_t))  /* Time Stamp IP Enable */
-#define ENUM_EMAC_TM_CTL_D_PTP_OV_ETHER      (_ADI_MSK(0x00000000,uint32_t))  /* TSIPENA: Disable PTP Over Ethernet Frames */
-#define ENUM_EMAC_TM_CTL_E_PTP_OV_ETHER      (_ADI_MSK(0x00000800,uint32_t))  /* TSIPENA: Enable PTP Over Ethernet Frames */
-
-#define BITM_EMAC_TM_CTL_TSVER2ENA           (_ADI_MSK(0x00000400,uint32_t))  /* Time Stamp VER2 (Snooping) Enable */
-#define ENUM_EMAC_TM_CTL_D_PKT_SNOOP_V2      (_ADI_MSK(0x00000000,uint32_t))  /* TSVER2ENA: Disable packet snooping for V2 frames */
-#define ENUM_EMAC_TM_CTL_E_PKT_SNOOP_V2      (_ADI_MSK(0x00000400,uint32_t))  /* TSVER2ENA: Enable packet snooping for V2 frames */
-
-#define BITM_EMAC_TM_CTL_TSCTRLSSR           (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Control Nanosecond Rollover */
-#define ENUM_EMAC_TM_CTL_RO_SUBSEC_RES       (_ADI_MSK(0x00000000,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x7FFFFFFF */
-#define ENUM_EMAC_TM_CTL_RO_NANO_RES         (_ADI_MSK(0x00000200,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x3B9AC9FF */
-
-#define BITM_EMAC_TM_CTL_TSENALL             (_ADI_MSK(0x00000100,uint32_t))  /* Time Stamp Enable All (Frames) */
-#define ENUM_EMAC_TM_CTL_D_TSALL_FRAMES      (_ADI_MSK(0x00000000,uint32_t))  /* TSENALL: Disable timestamp for all frames */
-#define ENUM_EMAC_TM_CTL_E_TSALL_FRAMES      (_ADI_MSK(0x00000100,uint32_t))  /* TSENALL: Enable timestamp for all frames */
-#define BITM_EMAC_TM_CTL_TSADDREG            (_ADI_MSK(0x00000020,uint32_t))  /* Time Stamp Addend Register Update */
-
-#define BITM_EMAC_TM_CTL_TSTRIG              (_ADI_MSK(0x00000010,uint32_t))  /* Time Stamp (Target Time) Trigger Enable */
-#define ENUM_EMAC_TM_CTL_EN_TRIGGER          (_ADI_MSK(0x00000010,uint32_t))  /* TSTRIG: Interrupt (TS) if system time is greater than target time register */
-
-#define BITM_EMAC_TM_CTL_TSUPDT              (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp (System Time) Update */
-#define ENUM_EMAC_TM_CTL_EN_UPDATE           (_ADI_MSK(0x00000008,uint32_t))  /* TSUPDT: System time updated with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSINIT              (_ADI_MSK(0x00000004,uint32_t))  /* Time Stamp (System Time) Initialize */
-#define ENUM_EMAC_TM_CTL_EN_TS_INIT          (_ADI_MSK(0x00000004,uint32_t))  /* TSINIT: System time initialized with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSCFUPDT            (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp (System Time) Fine/Coarse Update */
-#define ENUM_EMAC_TM_CTL_EN_COARSE_UPDT      (_ADI_MSK(0x00000000,uint32_t))  /* TSCFUPDT: Use Coarse Correction Method for System Time Update */
-#define ENUM_EMAC_TM_CTL_EN_FINE_UPDT        (_ADI_MSK(0x00000002,uint32_t))  /* TSCFUPDT: Use Fine Correction Method for System Time Update */
-
-#define BITM_EMAC_TM_CTL_TSENA               (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp (PTP) Enable */
-#define ENUM_EMAC_TM_CTL_DTS                 (_ADI_MSK(0x00000000,uint32_t))  /* TSENA: Disable PTP Module */
-#define ENUM_EMAC_TM_CTL_TS                  (_ADI_MSK(0x00000001,uint32_t))  /* TSENA: Enable PTP Module */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_SUBSEC                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_SUBSEC_SSINC             0                               /* Sub-Second Increment Value */
-#define BITM_EMAC_TM_SUBSEC_SSINC            (_ADI_MSK(0x000000FF,uint32_t))  /* Sub-Second Increment Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSEC                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSEC_TSSS                0                               /* Time Stamp Nanoseconds */
-#define BITM_EMAC_TM_NSEC_TSSS               (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Nanoseconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSECUPDT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSECUPDT_ADDSUB         31                               /* Add or Subtract the Time */
-#define BITP_EMAC_TM_NSECUPDT_TSSS            0                               /* Time Stamp Sub Second Initialize/Increment */
-#define BITM_EMAC_TM_NSECUPDT_ADDSUB         (_ADI_MSK(0x80000000,uint32_t))  /* Add or Subtract the Time */
-#define BITM_EMAC_TM_NSECUPDT_TSSS           (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Sub Second Initialize/Increment */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NTGTM                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NTGTM_TSTRBUSY          31                               /* Target Time Register Busy */
-#define BITP_EMAC_TM_NTGTM_TSTR               0                               /* Target Time Nano Seconds */
-#define BITM_EMAC_TM_NTGTM_TSTRBUSY          (_ADI_MSK(0x80000000,uint32_t))  /* Target Time Register Busy */
-#define BITM_EMAC_TM_NTGTM_TSTR              (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Target Time Nano Seconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_HISEC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_HISEC_TSHWR              0                               /* Time Stamp Higher Word Seconds Register */
-#define BITM_EMAC_TM_HISEC_TSHWR             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Time Stamp Higher Word Seconds Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_STMPSTAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_STMPSTAT_ATSNS          25                               /* Auxilary Time Stamp Number of Snapshots */
-#define BITP_EMAC_TM_STMPSTAT_ATSSTM         24                               /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITP_EMAC_TM_STMPSTAT_TSTRGTERR       3                               /* Time Stamp Target Time Programming Error */
-#define BITP_EMAC_TM_STMPSTAT_ATSTS           2                               /* Auxilary Time Stamp Trigger Snapshot */
-#define BITP_EMAC_TM_STMPSTAT_TSTARGT         1                               /* Time Stamp Target Time Reached */
-#define BITP_EMAC_TM_STMPSTAT_TSSOVF          0                               /* Time Stamp Seconds Overflow */
-#define BITM_EMAC_TM_STMPSTAT_ATSNS          (_ADI_MSK(0x0E000000,uint32_t))  /* Auxilary Time Stamp Number of Snapshots */
-#define BITM_EMAC_TM_STMPSTAT_ATSSTM         (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITM_EMAC_TM_STMPSTAT_TSTRGTERR      (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp Target Time Programming Error */
-#define BITM_EMAC_TM_STMPSTAT_ATSTS          (_ADI_MSK(0x00000004,uint32_t))  /* Auxilary Time Stamp Trigger Snapshot */
-#define BITM_EMAC_TM_STMPSTAT_TSTARGT        (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp Target Time Reached */
-#define BITM_EMAC_TM_STMPSTAT_TSSOVF         (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp Seconds Overflow */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_PPSCTL                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_PPSCTL_TRGTMODSEL        5                               /* Target Time Register Mode */
-#define BITP_EMAC_TM_PPSCTL_PPSEN             4                               /* Enable the flexible PPS output mode */
-#define BITP_EMAC_TM_PPSCTL_PPSCTL            0                               /* PPS Frequency Control */
-#define BITM_EMAC_TM_PPSCTL_TRGTMODSEL       (_ADI_MSK(0x00000060,uint32_t))  /* Target Time Register Mode */
-#define BITM_EMAC_TM_PPSCTL_PPSEN            (_ADI_MSK(0x00000010,uint32_t))  /* Enable the flexible PPS output mode */
-#define BITM_EMAC_TM_PPSCTL_PPSCTL           (_ADI_MSK(0x0000000F,uint32_t))  /* PPS Frequency Control */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BUSMODE                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BUSMODE_AAL            25                               /* Address Aligned Bursts */
-#define BITP_EMAC_DMA_BUSMODE_PBL8           24                               /* PBL * 8 */
-#define BITP_EMAC_DMA_BUSMODE_USP            23                               /* Use Separate PBL */
-#define BITP_EMAC_DMA_BUSMODE_RPBL           17                               /* Receive Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_FB             16                               /* Fixed Burst */
-#define BITP_EMAC_DMA_BUSMODE_PBL             8                               /* Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_ATDS            7                               /* Alternate Descriptor Size */
-#define BITP_EMAC_DMA_BUSMODE_DSL             2                               /* Descriptor Skip Length */
-#define BITP_EMAC_DMA_BUSMODE_SWR             0                               /* Software Reset */
-#define BITM_EMAC_DMA_BUSMODE_AAL            (_ADI_MSK(0x02000000,uint32_t))  /* Address Aligned Bursts */
-#define BITM_EMAC_DMA_BUSMODE_PBL8           (_ADI_MSK(0x01000000,uint32_t))  /* PBL * 8 */
-#define BITM_EMAC_DMA_BUSMODE_USP            (_ADI_MSK(0x00800000,uint32_t))  /* Use Separate PBL */
-#define BITM_EMAC_DMA_BUSMODE_RPBL           (_ADI_MSK(0x007E0000,uint32_t))  /* Receive Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_FB             (_ADI_MSK(0x00010000,uint32_t))  /* Fixed Burst */
-#define BITM_EMAC_DMA_BUSMODE_PBL            (_ADI_MSK(0x00003F00,uint32_t))  /* Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_ATDS           (_ADI_MSK(0x00000080,uint32_t))  /* Alternate Descriptor Size */
-#define BITM_EMAC_DMA_BUSMODE_DSL            (_ADI_MSK(0x0000007C,uint32_t))  /* Descriptor Skip Length */
-#define BITM_EMAC_DMA_BUSMODE_SWR            (_ADI_MSK(0x00000001,uint32_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_STAT_TTI               29                               /* Time Stamp Trigger Interrupt */
-#define BITP_EMAC_DMA_STAT_MCI               27                               /* MAC MMC Interrupt */
-#define BITP_EMAC_DMA_STAT_EB                23                               /* Error Bits */
-#define BITP_EMAC_DMA_STAT_TS                20                               /* Transmit Process State */
-#define BITP_EMAC_DMA_STAT_RS                17                               /* Receive Process State */
-#define BITP_EMAC_DMA_STAT_NIS               16                               /* Normal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_AIS               15                               /* Abnormal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_ERI               14                               /* Early Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_FBI               13                               /* Fatal Bus Error Interrupt */
-#define BITP_EMAC_DMA_STAT_ETI               10                               /* Early Transmit Interrupt */
-#define BITP_EMAC_DMA_STAT_RWT                9                               /* Receive WatchDog Timeout */
-#define BITP_EMAC_DMA_STAT_RPS                8                               /* Receive Process Stopped */
-#define BITP_EMAC_DMA_STAT_RU                 7                               /* Receive Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_RI                 6                               /* Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_UNF                5                               /* Transmit Buffer Underflow */
-#define BITP_EMAC_DMA_STAT_OVF                4                               /* Receive Buffer Overflow */
-#define BITP_EMAC_DMA_STAT_TJT                3                               /* Transmit Jabber Timeout */
-#define BITP_EMAC_DMA_STAT_TU                 2                               /* Transmit Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_TPS                1                               /* Transmit Process Stopped */
-#define BITP_EMAC_DMA_STAT_TI                 0                               /* Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_TTI               (_ADI_MSK(0x20000000,uint32_t))  /* Time Stamp Trigger Interrupt */
-#define BITM_EMAC_DMA_STAT_MCI               (_ADI_MSK(0x08000000,uint32_t))  /* MAC MMC Interrupt */
-#define BITM_EMAC_DMA_STAT_EB                (_ADI_MSK(0x03800000,uint32_t))  /* Error Bits */
-
-#define BITM_EMAC_DMA_STAT_TS                (_ADI_MSK(0x00700000,uint32_t))  /* Transmit Process State */
-#define ENUM_EMAC_DMA_STAT_TS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* TS: Stopped; Reset or Stop Transmit Command issued */
-#define ENUM_EMAC_DMA_STAT_TS_R_FTD          (_ADI_MSK(0x00100000,uint32_t))  /* TS: Running; Fetching Transmit Transfer Descriptor */
-#define ENUM_EMAC_DMA_STAT_TS_R_WSTAT        (_ADI_MSK(0x00200000,uint32_t))  /* TS: Running; Waiting for status */
-#define ENUM_EMAC_DMA_STAT_TS_R_TXHMBUF      (_ADI_MSK(0x00300000,uint32_t))  /* TS: Reading Data from host memory buffer and queuing it to TX buffer */
-#define ENUM_EMAC_DMA_STAT_TS_WR_TSTMP       (_ADI_MSK(0x00400000,uint32_t))  /* TS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_TS_SUSPENDED      (_ADI_MSK(0x00600000,uint32_t))  /* TS: Suspended; Transmit Descriptor Unavailable or TX Buffer Underflow */
-#define ENUM_EMAC_DMA_STAT_TS_R_CLSTD        (_ADI_MSK(0x00700000,uint32_t))  /* TS: Closing Transmit Descriptor */
-
-#define BITM_EMAC_DMA_STAT_RS                (_ADI_MSK(0x000E0000,uint32_t))  /* Receive Process State */
-#define ENUM_EMAC_DMA_STAT_RS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* RS: Stopped: Reset or Stop Receive Command issued. */
-#define ENUM_EMAC_DMA_STAT_RS_R_FRD          (_ADI_MSK(0x00020000,uint32_t))  /* RS: Running: Fetching Receive Transfer Descriptor. */
-#define ENUM_EMAC_DMA_STAT_RS_R_WTRX         (_ADI_MSK(0x00060000,uint32_t))  /* RS: Running: Waiting for receive packet */
-#define ENUM_EMAC_DMA_STAT_RS_SUSPENDED      (_ADI_MSK(0x00080000,uint32_t))  /* RS: Suspended: Receive Descriptor Unavailable */
-#define ENUM_EMAC_DMA_STAT_RS_R_CLSRD        (_ADI_MSK(0x000A0000,uint32_t))  /* RS: Running: Closing Receive Descriptor */
-#define ENUM_EMAC_DMA_STAT_RS_WR_TSTMP       (_ADI_MSK(0x000C0000,uint32_t))  /* RS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_RS_R_RXWRHM       (_ADI_MSK(0x000E0000,uint32_t))  /* RS: Running: Transferring RX packet data from RX buffer to host memory */
-#define BITM_EMAC_DMA_STAT_NIS               (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_AIS               (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_ERI               (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_FBI               (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Interrupt */
-#define BITM_EMAC_DMA_STAT_ETI               (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_RWT               (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchDog Timeout */
-#define BITM_EMAC_DMA_STAT_RPS               (_ADI_MSK(0x00000100,uint32_t))  /* Receive Process Stopped */
-#define BITM_EMAC_DMA_STAT_RU                (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_RI                (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_UNF               (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Buffer Underflow */
-#define BITM_EMAC_DMA_STAT_OVF               (_ADI_MSK(0x00000010,uint32_t))  /* Receive Buffer Overflow */
-#define BITM_EMAC_DMA_STAT_TJT               (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout */
-#define BITM_EMAC_DMA_STAT_TU                (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_TPS               (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Process Stopped */
-#define BITM_EMAC_DMA_STAT_TI                (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_OPMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_OPMODE_DT              26                               /* Disable Dropping TCP/IP Errors */
-#define BITP_EMAC_DMA_OPMODE_RSF             25                               /* Receive Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_DFF             24                               /* Disable Flushing of received Frames */
-#define BITP_EMAC_DMA_OPMODE_TSF             21                               /* Transmit Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_FTF             20                               /* Flush Transmit FIFO */
-#define BITP_EMAC_DMA_OPMODE_TTC             14                               /* Transmit Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_ST              13                               /* Start/Stop Transmission */
-#define BITP_EMAC_DMA_OPMODE_FEF              7                               /* Forward Error Frames */
-#define BITP_EMAC_DMA_OPMODE_FUF              6                               /* Forward Undersized good Frames */
-#define BITP_EMAC_DMA_OPMODE_RTC              3                               /* Receive Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_OSF              2                               /* Operate on Second Frame */
-#define BITP_EMAC_DMA_OPMODE_SR               1                               /* Start/Stop Receive */
-#define BITM_EMAC_DMA_OPMODE_DT              (_ADI_MSK(0x04000000,uint32_t))  /* Disable Dropping TCP/IP Errors */
-#define BITM_EMAC_DMA_OPMODE_RSF             (_ADI_MSK(0x02000000,uint32_t))  /* Receive Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_DFF             (_ADI_MSK(0x01000000,uint32_t))  /* Disable Flushing of received Frames */
-#define BITM_EMAC_DMA_OPMODE_TSF             (_ADI_MSK(0x00200000,uint32_t))  /* Transmit Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_FTF             (_ADI_MSK(0x00100000,uint32_t))  /* Flush Transmit FIFO */
-
-#define BITM_EMAC_DMA_OPMODE_TTC             (_ADI_MSK(0x0001C000,uint32_t))  /* Transmit Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_TTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* TTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_128         (_ADI_MSK(0x00004000,uint32_t))  /* TTC: 128 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_192         (_ADI_MSK(0x00008000,uint32_t))  /* TTC: 192 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_256         (_ADI_MSK(0x0000C000,uint32_t))  /* TTC: 256 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_40          (_ADI_MSK(0x00010000,uint32_t))  /* TTC: 40 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_32          (_ADI_MSK(0x00014000,uint32_t))  /* TTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_24          (_ADI_MSK(0x00018000,uint32_t))  /* TTC: 24 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_16          (_ADI_MSK(0x0001C000,uint32_t))  /* TTC: 16 */
-#define BITM_EMAC_DMA_OPMODE_ST              (_ADI_MSK(0x00002000,uint32_t))  /* Start/Stop Transmission */
-#define BITM_EMAC_DMA_OPMODE_FEF             (_ADI_MSK(0x00000080,uint32_t))  /* Forward Error Frames */
-#define BITM_EMAC_DMA_OPMODE_FUF             (_ADI_MSK(0x00000040,uint32_t))  /* Forward Undersized good Frames */
-
-#define BITM_EMAC_DMA_OPMODE_RTC             (_ADI_MSK(0x00000018,uint32_t))  /* Receive Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_RTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* RTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_32          (_ADI_MSK(0x00000008,uint32_t))  /* RTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_96          (_ADI_MSK(0x00000010,uint32_t))  /* RTC: 96 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_128         (_ADI_MSK(0x00000018,uint32_t))  /* RTC: 128 */
-#define BITM_EMAC_DMA_OPMODE_OSF             (_ADI_MSK(0x00000004,uint32_t))  /* Operate on Second Frame */
-#define BITM_EMAC_DMA_OPMODE_SR              (_ADI_MSK(0x00000002,uint32_t))  /* Start/Stop Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_IEN                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_IEN_NIS                16                               /* Normal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_AIS                15                               /* Abnormal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_ERI                14                               /* Early Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_FBI                13                               /* Fatal Bus Error Enable */
-#define BITP_EMAC_DMA_IEN_ETI                10                               /* Early Transmit Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_RWT                 9                               /* Receive WatchdogTimeout Enable */
-#define BITP_EMAC_DMA_IEN_RPS                 8                               /* Receive Stopped Enable */
-#define BITP_EMAC_DMA_IEN_RU                  7                               /* Receive Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_RI                  6                               /* Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_UNF                 5                               /* Underflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_OVF                 4                               /* Overflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_TJT                 3                               /* Transmit Jabber Timeout Enable */
-#define BITP_EMAC_DMA_IEN_TU                  2                               /* Transmit Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_TPS                 1                               /* Transmit Stopped Enable */
-#define BITP_EMAC_DMA_IEN_TI                  0                               /* Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_NIS                (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_AIS                (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_ERI                (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_FBI                (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Enable */
-#define BITM_EMAC_DMA_IEN_ETI                (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_RWT                (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchdogTimeout Enable */
-#define BITM_EMAC_DMA_IEN_RPS                (_ADI_MSK(0x00000100,uint32_t))  /* Receive Stopped Enable */
-#define BITM_EMAC_DMA_IEN_RU                 (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_RI                 (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_UNF                (_ADI_MSK(0x00000020,uint32_t))  /* Underflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_OVF                (_ADI_MSK(0x00000010,uint32_t))  /* Overflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_TJT                (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout Enable */
-#define BITM_EMAC_DMA_IEN_TU                 (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_TPS                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Stopped Enable */
-#define BITM_EMAC_DMA_IEN_TI                 (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_MISS_FRM                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_MISS_FRM_OVFFIFO       28                               /* Overflow bit for FIFO Overflow Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFROV      17                               /* Missed Frames Buffer Overflow */
-#define BITP_EMAC_DMA_MISS_FRM_OVFMISS       16                               /* Overflow bit for Missed Frame Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFRUN       0                               /* Missed Frames Unavailable Buffer */
-#define BITM_EMAC_DMA_MISS_FRM_OVFFIFO       (_ADI_MSK(0x10000000,uint32_t))  /* Overflow bit for FIFO Overflow Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFROV      (_ADI_MSK(0x0FFE0000,uint32_t))  /* Missed Frames Buffer Overflow */
-#define BITM_EMAC_DMA_MISS_FRM_OVFMISS       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow bit for Missed Frame Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFRUN      (_ADI_MSK(0x0000FFFF,uint32_t))  /* Missed Frames Unavailable Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_RXIWDOG                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_RXIWDOG_RIWT            0                               /* RI WatchDog Timer Count */
-#define BITM_EMAC_DMA_RXIWDOG_RIWT           (_ADI_MSK(0x000000FF,uint32_t))  /* RI WatchDog Timer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMMODE_WROSRLMT        20                               /* SCB Maximum Write Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_RDOSRLMT        16                               /* SCB Maximum Read Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_AAL             12                               /* Address Aligned Beats */
-#define BITP_EMAC_DMA_BMMODE_BLEN16           3                               /* SCB Burst Length 16 */
-#define BITP_EMAC_DMA_BMMODE_BLEN8            2                               /* SCB Burst Length 8 */
-#define BITP_EMAC_DMA_BMMODE_BLEN4            1                               /* SCB Burst Length 4 */
-#define BITP_EMAC_DMA_BMMODE_UNDEF            0                               /* SCB Undefined Burst Length */
-#define BITM_EMAC_DMA_BMMODE_WROSRLMT        (_ADI_MSK(0x00700000,uint32_t))  /* SCB Maximum Write Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_RDOSRLMT        (_ADI_MSK(0x00070000,uint32_t))  /* SCB Maximum Read Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_AAL             (_ADI_MSK(0x00001000,uint32_t))  /* Address Aligned Beats */
-#define BITM_EMAC_DMA_BMMODE_BLEN16          (_ADI_MSK(0x00000008,uint32_t))  /* SCB Burst Length 16 */
-#define BITM_EMAC_DMA_BMMODE_BLEN8           (_ADI_MSK(0x00000004,uint32_t))  /* SCB Burst Length 8 */
-#define BITM_EMAC_DMA_BMMODE_BLEN4           (_ADI_MSK(0x00000002,uint32_t))  /* SCB Burst Length 4 */
-#define BITM_EMAC_DMA_BMMODE_UNDEF           (_ADI_MSK(0x00000001,uint32_t))  /* SCB Undefined Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMSTAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMSTAT_BUSRD            1                               /* Bus (SCB master) Read Active */
-#define BITP_EMAC_DMA_BMSTAT_BUSWR            0                               /* Bus (SCB master) Write Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSRD           (_ADI_MSK(0x00000002,uint32_t))  /* Bus (SCB master) Read Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSWR           (_ADI_MSK(0x00000001,uint32_t))  /* Bus (SCB master) Write Active */
-
-/* ==================================================
-        Serial Port Registers
-   ================================================== */
-
-/* =========================
-        SPORT0
-   ========================= */
-#define REG_SPORT0_CTL_A                0xFFC40000         /* SPORT0 Half SPORT 'A' Control Register */
-#define REG_SPORT0_DIV_A                0xFFC40004         /* SPORT0 Half SPORT 'A' Divisor Register */
-#define REG_SPORT0_MCTL_A               0xFFC40008         /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT0_CS0_A                0xFFC4000C         /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_A                0xFFC40010         /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_A                0xFFC40014         /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT0_CS3_A                0xFFC40018         /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT0_ERR_A                0xFFC40020         /* SPORT0 Half SPORT 'A' Error Register */
-#define REG_SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_A               0xFFC40028         /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT0_CTL_B                0xFFC40080         /* SPORT0 Half SPORT 'B' Control Register */
-#define REG_SPORT0_DIV_B                0xFFC40084         /* SPORT0 Half SPORT 'B' Divisor Register */
-#define REG_SPORT0_MCTL_B               0xFFC40088         /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT0_CS0_B                0xFFC4008C         /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_B                0xFFC40090         /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_B                0xFFC40094         /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT0_CS3_B                0xFFC40098         /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT0_ERR_B                0xFFC400A0         /* SPORT0 Half SPORT 'B' Error Register */
-#define REG_SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT1
-   ========================= */
-#define REG_SPORT1_CTL_A                0xFFC40100         /* SPORT1 Half SPORT 'A' Control Register */
-#define REG_SPORT1_DIV_A                0xFFC40104         /* SPORT1 Half SPORT 'A' Divisor Register */
-#define REG_SPORT1_MCTL_A               0xFFC40108         /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT1_CS0_A                0xFFC4010C         /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_A                0xFFC40110         /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_A                0xFFC40114         /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT1_CS3_A                0xFFC40118         /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT1_ERR_A                0xFFC40120         /* SPORT1 Half SPORT 'A' Error Register */
-#define REG_SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_A               0xFFC40128         /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT1_CTL_B                0xFFC40180         /* SPORT1 Half SPORT 'B' Control Register */
-#define REG_SPORT1_DIV_B                0xFFC40184         /* SPORT1 Half SPORT 'B' Divisor Register */
-#define REG_SPORT1_MCTL_B               0xFFC40188         /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT1_CS0_B                0xFFC4018C         /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_B                0xFFC40190         /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_B                0xFFC40194         /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT1_CS3_B                0xFFC40198         /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT1_ERR_B                0xFFC401A0         /* SPORT1 Half SPORT 'B' Error Register */
-#define REG_SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT2
-   ========================= */
-#define REG_SPORT2_CTL_A                0xFFC40200         /* SPORT2 Half SPORT 'A' Control Register */
-#define REG_SPORT2_DIV_A                0xFFC40204         /* SPORT2 Half SPORT 'A' Divisor Register */
-#define REG_SPORT2_MCTL_A               0xFFC40208         /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT2_CS0_A                0xFFC4020C         /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_A                0xFFC40210         /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_A                0xFFC40214         /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT2_CS3_A                0xFFC40218         /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT2_ERR_A                0xFFC40220         /* SPORT2 Half SPORT 'A' Error Register */
-#define REG_SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_A               0xFFC40228         /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT2_CTL_B                0xFFC40280         /* SPORT2 Half SPORT 'B' Control Register */
-#define REG_SPORT2_DIV_B                0xFFC40284         /* SPORT2 Half SPORT 'B' Divisor Register */
-#define REG_SPORT2_MCTL_B               0xFFC40288         /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT2_CS0_B                0xFFC4028C         /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_B                0xFFC40290         /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_B                0xFFC40294         /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT2_CS3_B                0xFFC40298         /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT2_ERR_B                0xFFC402A0         /* SPORT2 Half SPORT 'B' Error Register */
-#define REG_SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_A_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_DXSPRI                30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_A_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_DERRPRI               29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_A_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_DXSSEC                27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_A_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_DERRSEC               26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_A_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_SPTRAN                25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_A_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_SPENSEC               24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_A_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_GCLKEN                21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_A_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_TFIEN                 20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_A_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_FSED                  19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_A_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_RJUST                 18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_A_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_LAFS                  17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_A_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_LFS                   16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_A_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_DIFS                  15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_A_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_IFS                   14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_A_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_FSR                   13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_A_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_CKRE                  12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_A_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_OPMODE                11                               /* Operation mode */
-#define BITP_SPORT_CTL_A_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_ICLK                  10                               /* Internal Clock */
-#define BITP_SPORT_CTL_A_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_PACK                   9                               /* Packing Enable */
-#define BITP_SPORT_CTL_A_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_SLEN                   4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_A_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_LSBF                   3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_A_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_DTYPE                  1                               /* Data Type */
-#define BITP_SPORT_CTL_A_SPENPRI              0                               /* Serial Port Enable (Primary) */
-#define BITP_SPORT_CTL_SPENPRI                0                               /* Serial Port Enable (Primary) */
-
-#define BITM_SPORT_CTL_A_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_DXSPRI                (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSPRI: Empty */
-#define ENUM_SPORT_CTL_PRM_PART_FULL         (_ADI_MSK(0x80000000,uint32_t))  /* DXSPRI: Partially full */
-#define ENUM_SPORT_CTL_PRM_FULL              (_ADI_MSK(0xC0000000,uint32_t))  /* DXSPRI: Full */
-
-#define BITM_SPORT_CTL_A_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_DERRPRI               (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRPRI: No error */
-#define ENUM_SPORT_CTL_PRM_ERR               (_ADI_MSK(0x20000000,uint32_t))  /* DERRPRI: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_DXSSEC                (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSSEC: Empty */
-#define ENUM_SPORT_CTL_SEC_PART_FULL         (_ADI_MSK(0x10000000,uint32_t))  /* DXSSEC: Partially full */
-#define ENUM_SPORT_CTL_SEC_FULL              (_ADI_MSK(0x18000000,uint32_t))  /* DXSSEC: Full */
-
-#define BITM_SPORT_CTL_A_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_DERRSEC               (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRSEC: No error */
-#define ENUM_SPORT_CTL_SEC_ERR               (_ADI_MSK(0x04000000,uint32_t))  /* DERRSEC: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_SPTRAN                (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define ENUM_SPORT_CTL_RX                    (_ADI_MSK(0x00000000,uint32_t))  /* SPTRAN: Receive */
-#define ENUM_SPORT_CTL_TX                    (_ADI_MSK(0x02000000,uint32_t))  /* SPTRAN: Transmit */
-
-#define BITM_SPORT_CTL_A_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_SPENSEC               (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define ENUM_SPORT_CTL_SECONDARY_DIS         (_ADI_MSK(0x00000000,uint32_t))  /* SPENSEC: Disable */
-#define ENUM_SPORT_CTL_SECONDARY_EN          (_ADI_MSK(0x01000000,uint32_t))  /* SPENSEC: Enable */
-
-#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_GCLKEN                (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define ENUM_SPORT_CTL_GCLK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* GCLKEN: Disable */
-#define ENUM_SPORT_CTL_GCLK_EN               (_ADI_MSK(0x00200000,uint32_t))  /* GCLKEN: Enable */
-
-#define BITM_SPORT_CTL_A_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_TFIEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define ENUM_SPORT_CTL_TXFIN_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TFIEN: Last word sent (DMA count done) interrupt */
-#define ENUM_SPORT_CTL_TXFIN_EN              (_ADI_MSK(0x00100000,uint32_t))  /* TFIEN: Last bit sent (Tx buffer done) interrupt */
-
-#define BITM_SPORT_CTL_A_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_FSED                  (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define ENUM_SPORT_CTL_LEVEL_FS              (_ADI_MSK(0x00000000,uint32_t))  /* FSED: Level detect frame sync */
-#define ENUM_SPORT_CTL_EDGE_FS               (_ADI_MSK(0x00080000,uint32_t))  /* FSED: Edge detect frame sync */
-
-#define BITM_SPORT_CTL_A_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_RJUST                 (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define ENUM_SPORT_CTL_RJUST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RJUST: Disable */
-#define ENUM_SPORT_CTL_RJUST_EN              (_ADI_MSK(0x00040000,uint32_t))  /* RJUST: Enable */
-
-#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_LAFS                  (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define ENUM_SPORT_CTL_EARLY_FS              (_ADI_MSK(0x00000000,uint32_t))  /* LAFS: Early frame sync */
-#define ENUM_SPORT_CTL_LATE_FS               (_ADI_MSK(0x00020000,uint32_t))  /* LAFS: Late frame sync */
-
-#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_LFS                   (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define ENUM_SPORT_CTL_FS_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* LFS: Active high frame sync (DSP standard mode) */
-#define ENUM_SPORT_CTL_FS_HI                 (_ADI_MSK(0x00010000,uint32_t))  /* LFS: Active low frame sync (DSP standard mode) */
-
-#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_DIFS                  (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define ENUM_SPORT_CTL_DATA_DEP_FS           (_ADI_MSK(0x00000000,uint32_t))  /* DIFS: Data-dependent frame sync */
-#define ENUM_SPORT_CTL_DATA_INDP_FS          (_ADI_MSK(0x00008000,uint32_t))  /* DIFS: Data-independent frame sync */
-
-#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_IFS                   (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define ENUM_SPORT_CTL_EXTERNAL_FS           (_ADI_MSK(0x00000000,uint32_t))  /* IFS: External frame sync */
-#define ENUM_SPORT_CTL_INTERNAL_FS           (_ADI_MSK(0x00004000,uint32_t))  /* IFS: Internal frame sync */
-
-#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_FSR                   (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define ENUM_SPORT_CTL_FS_NOT_REQ            (_ADI_MSK(0x00000000,uint32_t))  /* FSR: No frame sync required */
-#define ENUM_SPORT_CTL_FS_REQ                (_ADI_MSK(0x00002000,uint32_t))  /* FSR: Frame sync required */
-
-#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_CKRE                  (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define ENUM_SPORT_CTL_CLK_FALL_EDGE         (_ADI_MSK(0x00000000,uint32_t))  /* CKRE: Clock falling edge */
-#define ENUM_SPORT_CTL_CLK_RISE_EDGE         (_ADI_MSK(0x00001000,uint32_t))  /* CKRE: Clock rising edge */
-
-#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_OPMODE                (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define ENUM_SPORT_CTL_SERIAL_MC_MODE        (_ADI_MSK(0x00000000,uint32_t))  /* OPMODE: DSP standard/multi-channel mode */
-#define ENUM_SPORT_CTL_I2S_MODE              (_ADI_MSK(0x00000800,uint32_t))  /* OPMODE: I2S/packed/left-justified mode */
-
-#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_ICLK                  (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define ENUM_SPORT_CTL_EXTERNAL_CLK          (_ADI_MSK(0x00000000,uint32_t))  /* ICLK: External clock */
-#define ENUM_SPORT_CTL_INTERNAL_CLK          (_ADI_MSK(0x00000400,uint32_t))  /* ICLK: Internal clock */
-
-#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_PACK                  (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define ENUM_SPORT_CTL_PACK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* PACK: Disable */
-#define ENUM_SPORT_CTL_PACK_EN               (_ADI_MSK(0x00000200,uint32_t))  /* PACK: Enable */
-#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_SLEN                  (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-
-#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_LSBF                  (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define ENUM_SPORT_CTL_MSB_FIRST             (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB first sent/received (big endian) */
-#define ENUM_SPORT_CTL_LSB_FIRST             (_ADI_MSK(0x00000008,uint32_t))  /* LSBF: LSB first sent/received (little endian) */
-
-#define BITM_SPORT_CTL_A_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_DTYPE                 (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define ENUM_SPORT_CTL_RJUSTIFY_ZFILL        (_ADI_MSK(0x00000000,uint32_t))  /* DTYPE: Right-justify data, zero-fill unused MSBs */
-#define ENUM_SPORT_CTL_RJUSTIFY_SFILL        (_ADI_MSK(0x00000002,uint32_t))  /* DTYPE: Right-justify data, sign-extend unused MSBs */
-#define ENUM_SPORT_CTL_USE_U_LAW             (_ADI_MSK(0x00000004,uint32_t))  /* DTYPE: m-law compand data */
-#define ENUM_SPORT_CTL_USE_A_LAW             (_ADI_MSK(0x00000006,uint32_t))  /* DTYPE: A-law compand data */
-
-#define BITM_SPORT_CTL_A_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define BITM_SPORT_CTL_SPENPRI               (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define ENUM_SPORT_CTL_DIS                   (_ADI_MSK(0x00000000,uint32_t))  /* SPENPRI: Disable */
-#define ENUM_SPORT_CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* SPENPRI: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_A_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_FSDIV                 16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_A_CLKDIV               0                               /* Clock Divisor */
-#define BITP_SPORT_DIV_CLKDIV                 0                               /* Clock Divisor */
-#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_FSDIV                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-#define BITM_SPORT_DIV_CLKDIV                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_A_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_WOFFSET              16                               /* Window Offset */
-#define BITP_SPORT_MCTL_A_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_WSIZE                 8                               /* Window Size */
-#define BITP_SPORT_MCTL_A_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_MFD                   4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_A_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_MCPDE                 2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_A_MCE                 0                               /* Multichannel enable */
-#define BITP_SPORT_MCTL_MCE                   0                               /* Multichannel enable */
-#define BITM_SPORT_MCTL_A_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_WOFFSET              (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_A_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_WSIZE                (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_A_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_MFD                  (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-
-#define BITM_SPORT_MCTL_A_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_MCPDE                (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define ENUM_SPORT_MCTL_MCPD_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* MCPDE: Disable */
-#define ENUM_SPORT_MCTL_MCPD_EN              (_ADI_MSK(0x00000004,uint32_t))  /* MCPDE: Enable */
-
-#define BITM_SPORT_MCTL_A_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define BITM_SPORT_MCTL_MCE                  (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define ENUM_SPORT_MCTL_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* MCE: Disable */
-#define ENUM_SPORT_MCTL_EN                   (_ADI_MSK(0x00000001,uint32_t))  /* MCE: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_A_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_FSERRSTAT              6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_A_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_DERRSSTAT              5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_A_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_DERRPSTAT              4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_A_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_FSERRMSK               2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRSMSK               1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRPMSK               0                               /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_FSERRSTAT             (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_A_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_DERRSSTAT             (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_A_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_DERRPSTAT             (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_A_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_FSERRMSK              (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRSMSK              (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRPMSK              (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_A_CURCHAN            0                               /* Current Channel */
-#define BITP_SPORT_MSTAT_CURCHAN              0                               /* Current Channel */
-#define BITM_SPORT_MSTAT_A_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-#define BITM_SPORT_MSTAT_CURCHAN             (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_A_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_CKMUXSEL              1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_A_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-#define BITP_SPORT_CTL2_FSMUXSEL              0                               /* Frame Sync Multiplexer Select */
-
-#define BITM_SPORT_CTL2_A_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_CKMUXSEL             (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define ENUM_SPORT_CTL2_CLK_MUX_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* CKMUXSEL: Disable serial clock multiplexing */
-#define ENUM_SPORT_CTL2_CLK_MUX_EN           (_ADI_MSK(0x00000002,uint32_t))  /* CKMUXSEL: Enable serial clock multiplexing */
-
-#define BITM_SPORT_CTL2_A_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define BITM_SPORT_CTL2_FSMUXSEL             (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define ENUM_SPORT_CTL2_FS_MUX_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* FSMUXSEL: Disable frame sync multiplexing */
-#define ENUM_SPORT_CTL2_FS_MUX_EN            (_ADI_MSK(0x00000001,uint32_t))  /* FSMUXSEL: Enable frame sync multiplexing */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_B_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_B_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_B_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_B_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_B_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_B_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_B_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_B_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_B_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_B_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_B_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_B_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_B_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_B_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_B_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_B_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_B_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_B_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_B_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_B_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_B_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_B_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_B_SPENPRI              0                               /* Serial Port Enable (Primary) */
-
-/* The fields and enumerations for SPORT_CTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL_A */
-
-#define BITM_SPORT_CTL_B_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_B_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_B_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_B_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_B_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_B_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_B_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_B_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_B_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_B_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_B_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_B_CLKDIV               0                               /* Clock Divisor */
-
-/* The fields and enumerations for SPORT_DIV_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_DIV_A */
-
-#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_B_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_B_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_B_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_B_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_B_MCE                 0                               /* Multi-Channel Enable */
-
-/* The fields and enumerations for SPORT_MCTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MCTL_A */
-
-#define BITM_SPORT_MCTL_B_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_B_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_B_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_B_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_B_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multi-Channel Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_B_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_B_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_B_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_B_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-
-/* The fields and enumerations for SPORT_ERR_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_ERR_A */
-
-#define BITM_SPORT_ERR_B_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_B_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_B_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_B_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_B_CURCHAN            0                               /* Current Channel */
-
-/* The fields and enumerations for SPORT_MSTAT_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MSTAT_A */
-
-#define BITM_SPORT_MSTAT_B_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_B_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_B_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-
-/* The fields and enumerations for SPORT_CTL2_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL2_A */
-
-#define BITM_SPORT_CTL2_B_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_B_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-
-/* ==================================================
-        Serial Peripheral Interface Registers
-   ================================================== */
-
-/* =========================
-        SPI0
-   ========================= */
-#define REG_SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
-#define REG_SPI0_RXCTL                  0xFFC40408         /* SPI0 Receive Control Register */
-#define REG_SPI0_TXCTL                  0xFFC4040C         /* SPI0 Transmit Control Register */
-#define REG_SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
-#define REG_SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
-#define REG_SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
-#define REG_SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word Count Register */
-#define REG_SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word Count Reload Register */
-#define REG_SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word Count Register */
-#define REG_SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word Count Reload Register */
-#define REG_SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
-#define REG_SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
-#define REG_SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
-#define REG_SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
-#define REG_SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
-#define REG_SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
-#define REG_SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
-#define REG_SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
-        SPI1
-   ========================= */
-#define REG_SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
-#define REG_SPI1_RXCTL                  0xFFC40508         /* SPI1 Receive Control Register */
-#define REG_SPI1_TXCTL                  0xFFC4050C         /* SPI1 Transmit Control Register */
-#define REG_SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
-#define REG_SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
-#define REG_SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
-#define REG_SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word Count Register */
-#define REG_SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word Count Reload Register */
-#define REG_SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word Count Register */
-#define REG_SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word Count Reload Register */
-#define REG_SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
-#define REG_SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
-#define REG_SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
-#define REG_SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
-#define REG_SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
-#define REG_SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
-#define REG_SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
-#define REG_SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
-        SPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CTL_SOSI                    22                               /* Start on MOSI */
-#define BITP_SPI_CTL_MIOM                    20                               /* Multiple I/O Mode */
-#define BITP_SPI_CTL_FMODE                   18                               /* Fast-Mode Enable */
-#define BITP_SPI_CTL_FCWM                    16                               /* Flow Control Watermark */
-#define BITP_SPI_CTL_FCPL                    15                               /* Flow Control Polarity */
-#define BITP_SPI_CTL_FCCH                    14                               /* Flow Control Channel Selection */
-#define BITP_SPI_CTL_FCEN                    13                               /* Flow Control Enable */
-#define BITP_SPI_CTL_LSBF                    12                               /* Least Significant Bit First */
-#define BITP_SPI_CTL_SIZE                     9                               /* Word Transfer Size */
-#define BITP_SPI_CTL_EMISO                    8                               /* Enable MISO */
-#define BITP_SPI_CTL_SELST                    7                               /* Slave Select Polarity Between Transfers */
-#define BITP_SPI_CTL_ASSEL                    6                               /* Slave Select Pin Control */
-#define BITP_SPI_CTL_CPOL                     5                               /* Clock Polarity */
-#define BITP_SPI_CTL_CPHA                     4                               /* Clock Phase */
-#define BITP_SPI_CTL_ODM                      3                               /* Open Drain Mode */
-#define BITP_SPI_CTL_PSSE                     2                               /* Protected Slave Select Enable */
-#define BITP_SPI_CTL_MSTR                     1                               /* Master / Slave */
-#define BITP_SPI_CTL_EN                       0                               /* Enable */
-
-#define BITM_SPI_CTL_SOSI                    (_ADI_MSK(0x00400000,uint32_t))  /* Start on MOSI */
-#define ENUM_SPI_CTL_STMISO                  (_ADI_MSK(0x00000000,uint32_t))  /* SOSI: Bit 1 on MISO (DIOM) or on D3 (QIOM) */
-#define ENUM_SPI_CTL_STMOSI                  (_ADI_MSK(0x00400000,uint32_t))  /* SOSI: Bit 1 on MOSI (DIOM and QIOM) */
-
-#define BITM_SPI_CTL_MIOM                    (_ADI_MSK(0x00300000,uint32_t))  /* Multiple I/O Mode */
-#define ENUM_SPI_CTL_MIO_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* MIOM: No MIOM (disabled) */
-#define ENUM_SPI_CTL_MIO_DUAL                (_ADI_MSK(0x00100000,uint32_t))  /* MIOM: DIOM operation */
-#define ENUM_SPI_CTL_MIO_QUAD                (_ADI_MSK(0x00200000,uint32_t))  /* MIOM: QIOM operation */
-
-#define BITM_SPI_CTL_FMODE                   (_ADI_MSK(0x00040000,uint32_t))  /* Fast-Mode Enable */
-#define ENUM_SPI_CTL_FAST_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FMODE: Disable */
-#define ENUM_SPI_CTL_FAST_EN                 (_ADI_MSK(0x00040000,uint32_t))  /* FMODE: Enable */
-
-#define BITM_SPI_CTL_FCWM                    (_ADI_MSK(0x00030000,uint32_t))  /* Flow Control Watermark */
-#define ENUM_SPI_CTL_FIFO0                   (_ADI_MSK(0x00000000,uint32_t))  /* FCWM: TFIFO empty or RFIFO full */
-#define ENUM_SPI_CTL_FIFO1                   (_ADI_MSK(0x00010000,uint32_t))  /* FCWM: TFIFO 75% or more empty, or RFIFO full */
-#define ENUM_SPI_CTL_FIFO2                   (_ADI_MSK(0x00020000,uint32_t))  /* FCWM: TFIFO 50% or more empty, or RFIFO full */
-
-#define BITM_SPI_CTL_FCPL                    (_ADI_MSK(0x00008000,uint32_t))  /* Flow Control Polarity */
-#define ENUM_SPI_CTL_FLOW_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* FCPL: Active-low RDY */
-#define ENUM_SPI_CTL_FLOW_HI                 (_ADI_MSK(0x00008000,uint32_t))  /* FCPL: Active-high RDY */
-
-#define BITM_SPI_CTL_FCCH                    (_ADI_MSK(0x00004000,uint32_t))  /* Flow Control Channel Selection */
-#define ENUM_SPI_CTL_FLOW_RX                 (_ADI_MSK(0x00000000,uint32_t))  /* FCCH: Flow control on RX buffer */
-#define ENUM_SPI_CTL_FLOW_TX                 (_ADI_MSK(0x00004000,uint32_t))  /* FCCH: Flow control on TX buffer */
-
-#define BITM_SPI_CTL_FCEN                    (_ADI_MSK(0x00002000,uint32_t))  /* Flow Control Enable */
-#define ENUM_SPI_CTL_FLOW_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FCEN: Disable */
-#define ENUM_SPI_CTL_FLOW_EN                 (_ADI_MSK(0x00002000,uint32_t))  /* FCEN: Enable */
-
-#define BITM_SPI_CTL_LSBF                    (_ADI_MSK(0x00001000,uint32_t))  /* Least Significant Bit First */
-#define ENUM_SPI_CTL_MSB_FIRST               (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB sent/received first (big endian) */
-#define ENUM_SPI_CTL_LSB_FIRST               (_ADI_MSK(0x00001000,uint32_t))  /* LSBF: LSB sent/received first (little endian) */
-
-#define BITM_SPI_CTL_SIZE                    (_ADI_MSK(0x00000600,uint32_t))  /* Word Transfer Size */
-#define ENUM_SPI_CTL_SIZE08                  (_ADI_MSK(0x00000000,uint32_t))  /* SIZE: 8-bit word */
-#define ENUM_SPI_CTL_SIZE16                  (_ADI_MSK(0x00000200,uint32_t))  /* SIZE: 16-bit word */
-#define ENUM_SPI_CTL_SIZE32                  (_ADI_MSK(0x00000400,uint32_t))  /* SIZE: 32-bit word */
-
-#define BITM_SPI_CTL_EMISO                   (_ADI_MSK(0x00000100,uint32_t))  /* Enable MISO */
-#define ENUM_SPI_CTL_MISO_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EMISO: Disable */
-#define ENUM_SPI_CTL_MISO_EN                 (_ADI_MSK(0x00000100,uint32_t))  /* EMISO: Enable */
-
-#define BITM_SPI_CTL_SELST                   (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select Polarity Between Transfers */
-#define ENUM_SPI_CTL_DEASSRT_SSEL            (_ADI_MSK(0x00000000,uint32_t))  /* SELST: De-assert slave select (high) */
-#define ENUM_SPI_CTL_ASSRT_SSEL              (_ADI_MSK(0x00000080,uint32_t))  /* SELST: Assert slave select (low) */
-
-#define BITM_SPI_CTL_ASSEL                   (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select Pin Control */
-#define ENUM_SPI_CTL_SW_SSEL                 (_ADI_MSK(0x00000000,uint32_t))  /* ASSEL: Software Slave Select Control */
-#define ENUM_SPI_CTL_HW_SSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* ASSEL: Hardware Slave Select Control */
-
-#define BITM_SPI_CTL_CPOL                    (_ADI_MSK(0x00000020,uint32_t))  /* Clock Polarity */
-#define ENUM_SPI_CTL_SCKHI                   (_ADI_MSK(0x00000000,uint32_t))  /* CPOL: Active-high SPI CLK */
-#define ENUM_SPI_CTL_SCKLO                   (_ADI_MSK(0x00000020,uint32_t))  /* CPOL: Active-low SPI CLK */
-
-#define BITM_SPI_CTL_CPHA                    (_ADI_MSK(0x00000010,uint32_t))  /* Clock Phase */
-#define ENUM_SPI_CTL_SCKMID                  (_ADI_MSK(0x00000000,uint32_t))  /* CPHA: SPI CLK toggles from middle */
-#define ENUM_SPI_CTL_SCKBEG                  (_ADI_MSK(0x00000010,uint32_t))  /* CPHA: SPI CLK toggles from start */
-
-#define BITM_SPI_CTL_ODM                     (_ADI_MSK(0x00000008,uint32_t))  /* Open Drain Mode */
-#define ENUM_SPI_CTL_ODM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* ODM: Disable */
-#define ENUM_SPI_CTL_ODM_EN                  (_ADI_MSK(0x00000008,uint32_t))  /* ODM: Enable */
-
-#define BITM_SPI_CTL_PSSE                    (_ADI_MSK(0x00000004,uint32_t))  /* Protected Slave Select Enable */
-#define ENUM_SPI_CTL_PSSE_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* PSSE: Disable */
-#define ENUM_SPI_CTL_PSSE_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* PSSE: Enable */
-
-#define BITM_SPI_CTL_MSTR                    (_ADI_MSK(0x00000002,uint32_t))  /* Master / Slave */
-#define ENUM_SPI_CTL_SLAVE                   (_ADI_MSK(0x00000000,uint32_t))  /* MSTR: Slave */
-#define ENUM_SPI_CTL_MASTER                  (_ADI_MSK(0x00000002,uint32_t))  /* MSTR: Master */
-
-#define BITM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SPI_CTL_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable SPI module */
-#define ENUM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RXCTL_RUWM                  16                               /* Receive FIFO Urgent Watermark */
-#define BITP_SPI_RXCTL_RRWM                  12                               /* Receive FIFO Regular Watermark */
-#define BITP_SPI_RXCTL_RDO                    8                               /* Receive Data Overrun */
-#define BITP_SPI_RXCTL_RDR                    4                               /* Receive Data Request */
-#define BITP_SPI_RXCTL_RWCEN                  3                               /* Receive Word Counter Enable */
-#define BITP_SPI_RXCTL_RTI                    2                               /* Receive Transfer Initiate */
-#define BITP_SPI_RXCTL_REN                    0                               /* Receive Enable */
-
-#define BITM_SPI_RXCTL_RUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* Receive FIFO Urgent Watermark */
-#define ENUM_SPI_RXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disabled */
-#define ENUM_SPI_RXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* RUWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* RUWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* RUWM: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_FULL              (_ADI_MSK(0x00040000,uint32_t))  /* RUWM: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* Receive FIFO Regular Watermark */
-#define ENUM_SPI_RXCTL_RWM_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RRWM: Empty RFIFO */
-#define ENUM_SPI_RXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* RRWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* RRWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* RRWM: 75% full RFIFO */
-
-#define BITM_SPI_RXCTL_RDO                   (_ADI_MSK(0x00000100,uint32_t))  /* Receive Data Overrun */
-#define ENUM_SPI_RXCTL_DISCARD               (_ADI_MSK(0x00000000,uint32_t))  /* RDO: KeDiscard incoming data if SPI_RFIFO is full */
-#define ENUM_SPI_RXCTL_OVERWRITE             (_ADI_MSK(0x00000100,uint32_t))  /* RDO: Overwrite old data if SPI_RFIFO is full */
-
-#define BITM_SPI_RXCTL_RDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Receive Data Request */
-#define ENUM_SPI_RXCTL_RDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RDR: Disabled */
-#define ENUM_SPI_RXCTL_RDR_NE                (_ADI_MSK(0x00000010,uint32_t))  /* RDR: Not empty RFIFO */
-#define ENUM_SPI_RXCTL_RDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* RDR: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* RDR: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* RDR: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_FULL              (_ADI_MSK(0x00000050,uint32_t))  /* RDR: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Receive Word Counter Enable */
-#define ENUM_SPI_RXCTL_RWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RWCEN: Disable */
-#define ENUM_SPI_RXCTL_RWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* RWCEN: Enable */
-
-#define BITM_SPI_RXCTL_RTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Receive Transfer Initiate */
-#define ENUM_SPI_RXCTL_RTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RTI: Disable */
-#define ENUM_SPI_RXCTL_RTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* RTI: Enable */
-
-#define BITM_SPI_RXCTL_REN                   (_ADI_MSK(0x00000001,uint32_t))  /* Receive Enable */
-#define ENUM_SPI_RXCTL_RX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* REN: Disable */
-#define ENUM_SPI_RXCTL_RX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* REN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TXCTL_TUWM                  16                               /* FIFO Urgent Watermark */
-#define BITP_SPI_TXCTL_TRWM                  12                               /* FIFO Regular Watermark */
-#define BITP_SPI_TXCTL_TDU                    8                               /* Transmit Data Under-run */
-#define BITP_SPI_TXCTL_TDR                    4                               /* Transmit Data Request */
-#define BITP_SPI_TXCTL_TWCEN                  3                               /* Transmit Word Counter Enable */
-#define BITP_SPI_TXCTL_TTI                    2                               /* Transmit Transfer Initiate */
-#define BITP_SPI_TXCTL_TEN                    0                               /* Transmit Enable */
-
-#define BITM_SPI_TXCTL_TUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Urgent Watermark */
-#define ENUM_SPI_TXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disabled */
-#define ENUM_SPI_TXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* TUWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* TUWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* TUWM: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_EMPTY             (_ADI_MSK(0x00040000,uint32_t))  /* TUWM: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* FIFO Regular Watermark */
-#define ENUM_SPI_TXCTL_RWM_FULL              (_ADI_MSK(0x00000000,uint32_t))  /* TRWM: Full TFIFO */
-#define ENUM_SPI_TXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* TRWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* TRWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* TRWM: 75% empty TFIFO */
-
-#define BITM_SPI_TXCTL_TDU                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Data Under-run */
-#define ENUM_SPI_TXCTL_LASTWD                (_ADI_MSK(0x00000000,uint32_t))  /* TDU: Send last word when SPI_TFIFO is empty */
-#define ENUM_SPI_TXCTL_ZERO                  (_ADI_MSK(0x00000100,uint32_t))  /* TDU: Send zeros when SPI_TFIFO is empty */
-
-#define BITM_SPI_TXCTL_TDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Transmit Data Request */
-#define ENUM_SPI_TXCTL_TDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TDR: Disabled */
-#define ENUM_SPI_TXCTL_TDR_NF                (_ADI_MSK(0x00000010,uint32_t))  /* TDR: Not full TFIFO */
-#define ENUM_SPI_TXCTL_TDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* TDR: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* TDR: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* TDR: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_EMPTY             (_ADI_MSK(0x00000050,uint32_t))  /* TDR: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Word Counter Enable */
-#define ENUM_SPI_TXCTL_TWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TWCEN: Disable */
-#define ENUM_SPI_TXCTL_TWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* TWCEN: Enable */
-
-#define BITM_SPI_TXCTL_TTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Transfer Initiate */
-#define ENUM_SPI_TXCTL_TTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TTI: Disable */
-#define ENUM_SPI_TXCTL_TTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* TTI: Enable */
-
-#define BITM_SPI_TXCTL_TEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Enable */
-#define ENUM_SPI_TXCTL_TX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* TEN: Disable */
-#define ENUM_SPI_TXCTL_TX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* TEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CLK_BAUD                     0                               /* Baud Rate */
-#define BITM_SPI_CLK_BAUD                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Baud Rate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_DLY                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_DLY_LAGX                     9                               /* Extended SPI Clock Lag Control */
-#define BITP_SPI_DLY_LEADX                    8                               /* Extended SPI Clock Lead Control */
-#define BITP_SPI_DLY_STOP                     0                               /* Transfer delay time in multiples of SPI clock period */
-#define BITM_SPI_DLY_LAGX                    (_ADI_MSK(0x00000200,uint32_t))  /* Extended SPI Clock Lag Control */
-#define BITM_SPI_DLY_LEADX                   (_ADI_MSK(0x00000100,uint32_t))  /* Extended SPI Clock Lead Control */
-#define BITM_SPI_DLY_STOP                    (_ADI_MSK(0x000000FF,uint32_t))  /* Transfer delay time in multiples of SPI clock period */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_SLVSEL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_SLVSEL_SSEL7                15                               /* Slave Select 7 Input */
-#define BITP_SPI_SLVSEL_SSEL6                14                               /* Slave Select 6 Input */
-#define BITP_SPI_SLVSEL_SSEL5                13                               /* Slave Select 5 Input */
-#define BITP_SPI_SLVSEL_SSEL4                12                               /* Slave Select 4 Input */
-#define BITP_SPI_SLVSEL_SSEL3                11                               /* Slave Select 3 Input */
-#define BITP_SPI_SLVSEL_SSEL2                10                               /* Slave Select 2 Input */
-#define BITP_SPI_SLVSEL_SSEL1                 9                               /* Slave Select 1 Input */
-#define BITP_SPI_SLVSEL_SSE7                  7                               /* Slave Select 7 Enable */
-#define BITP_SPI_SLVSEL_SSE6                  6                               /* Slave Select 6 Enable */
-#define BITP_SPI_SLVSEL_SSE5                  5                               /* Slave Select 5 Enable */
-#define BITP_SPI_SLVSEL_SSE4                  4                               /* Slave Select 4 Enable */
-#define BITP_SPI_SLVSEL_SSE3                  3                               /* Slave Select 3 Enable */
-#define BITP_SPI_SLVSEL_SSE2                  2                               /* Slave Select 2 Enable */
-#define BITP_SPI_SLVSEL_SSE1                  1                               /* Slave Select 1 Enable */
-
-#define BITM_SPI_SLVSEL_SSEL7                (_ADI_MSK(0x00008000,uint32_t))  /* Slave Select 7 Input */
-#define ENUM_SPI_SLVSEL_SSEL7_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL7: Low */
-#define ENUM_SPI_SLVSEL_SSEL7_HI             (_ADI_MSK(0x00008000,uint32_t))  /* SSEL7: High */
-
-#define BITM_SPI_SLVSEL_SSEL6                (_ADI_MSK(0x00004000,uint32_t))  /* Slave Select 6 Input */
-#define ENUM_SPI_SLVSEL_SSEL6_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL6: Low */
-#define ENUM_SPI_SLVSEL_SSEL6_HI             (_ADI_MSK(0x00004000,uint32_t))  /* SSEL6: High */
-
-#define BITM_SPI_SLVSEL_SSEL5                (_ADI_MSK(0x00002000,uint32_t))  /* Slave Select 5 Input */
-#define ENUM_SPI_SLVSEL_SSEL5_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL5: Low */
-#define ENUM_SPI_SLVSEL_SSEL5_HI             (_ADI_MSK(0x00002000,uint32_t))  /* SSEL5: High */
-
-#define BITM_SPI_SLVSEL_SSEL4                (_ADI_MSK(0x00001000,uint32_t))  /* Slave Select 4 Input */
-#define ENUM_SPI_SLVSEL_SSEL4_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL4: Low */
-#define ENUM_SPI_SLVSEL_SSEL4_HI             (_ADI_MSK(0x00001000,uint32_t))  /* SSEL4: High */
-
-#define BITM_SPI_SLVSEL_SSEL3                (_ADI_MSK(0x00000800,uint32_t))  /* Slave Select 3 Input */
-#define ENUM_SPI_SLVSEL_SSEL3_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL3: Low */
-#define ENUM_SPI_SLVSEL_SSEL3_HI             (_ADI_MSK(0x00000800,uint32_t))  /* SSEL3: High */
-
-#define BITM_SPI_SLVSEL_SSEL2                (_ADI_MSK(0x00000400,uint32_t))  /* Slave Select 2 Input */
-#define ENUM_SPI_SLVSEL_SSEL2_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL2: Low */
-#define ENUM_SPI_SLVSEL_SSEL2_HI             (_ADI_MSK(0x00000400,uint32_t))  /* SSEL2: High */
-
-#define BITM_SPI_SLVSEL_SSEL1                (_ADI_MSK(0x00000200,uint32_t))  /* Slave Select 1 Input */
-#define ENUM_SPI_SLVSEL_SSEL1_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL1: Low */
-#define ENUM_SPI_SLVSEL_SSEL1_HI             (_ADI_MSK(0x00000200,uint32_t))  /* SSEL1: High */
-
-#define BITM_SPI_SLVSEL_SSE7                 (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select 7 Enable */
-#define ENUM_SPI_SLVSEL_SSEL7_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE7: Disable */
-#define ENUM_SPI_SLVSEL_SSEL7_EN             (_ADI_MSK(0x00000080,uint32_t))  /* SSE7: Enable */
-
-#define BITM_SPI_SLVSEL_SSE6                 (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select 6 Enable */
-#define ENUM_SPI_SLVSEL_SSEL6_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE6: Disable */
-#define ENUM_SPI_SLVSEL_SSEL6_EN             (_ADI_MSK(0x00000040,uint32_t))  /* SSE6: Enable */
-
-#define BITM_SPI_SLVSEL_SSE5                 (_ADI_MSK(0x00000020,uint32_t))  /* Slave Select 5 Enable */
-#define ENUM_SPI_SLVSEL_SSEL5_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE5: Disable */
-#define ENUM_SPI_SLVSEL_SSEL5_EN             (_ADI_MSK(0x00000020,uint32_t))  /* SSE5: Enable */
-
-#define BITM_SPI_SLVSEL_SSE4                 (_ADI_MSK(0x00000010,uint32_t))  /* Slave Select 4 Enable */
-#define ENUM_SPI_SLVSEL_SSEL4_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE4: Disable */
-#define ENUM_SPI_SLVSEL_SSEL4_EN             (_ADI_MSK(0x00000010,uint32_t))  /* SSE4: Enable */
-
-#define BITM_SPI_SLVSEL_SSE3                 (_ADI_MSK(0x00000008,uint32_t))  /* Slave Select 3 Enable */
-#define ENUM_SPI_SLVSEL_SSEL3_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE3: Disable */
-#define ENUM_SPI_SLVSEL_SSEL3_EN             (_ADI_MSK(0x00000008,uint32_t))  /* SSE3: Enable */
-
-#define BITM_SPI_SLVSEL_SSE2                 (_ADI_MSK(0x00000004,uint32_t))  /* Slave Select 2 Enable */
-#define ENUM_SPI_SLVSEL_SSEL2_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE2: Disable */
-#define ENUM_SPI_SLVSEL_SSEL2_EN             (_ADI_MSK(0x00000004,uint32_t))  /* SSE2: Enable */
-
-#define BITM_SPI_SLVSEL_SSE1                 (_ADI_MSK(0x00000002,uint32_t))  /* Slave Select 1 Enable */
-#define ENUM_SPI_SLVSEL_SSEL1_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE1: Disable */
-#define ENUM_SPI_SLVSEL_SSEL1_EN             (_ADI_MSK(0x00000002,uint32_t))  /* SSE1: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWC_VALUE                    0                               /* Received Word Count */
-#define BITM_SPI_RWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWCR_VALUE                   0                               /* Received Word Count Reload */
-#define BITM_SPI_RWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWC_VALUE                    0                               /* Transmitted Word Count */
-#define BITM_SPI_TWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWCR_VALUE                   0                               /* Transmitted Word Count Reload */
-#define BITM_SPI_TWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_TF                     11                               /* Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_RF                     10                               /* Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_TS                      9                               /* Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_RS                      8                               /* Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_MF                      7                               /* Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_TC                      6                               /* Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_TUR                     5                               /* Transmit Underrun Interrupt Mask */
-#define BITP_SPI_IMSK_ROR                     4                               /* Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_RUWM                    1                               /* Receive Urgent Watermark Interrupt Mask */
-
-#define BITM_SPI_IMSK_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Mask */
-#define ENUM_SPI_TF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TF: Disable (mask) interrupt */
-#define ENUM_SPI_TF_HI                       (_ADI_MSK(0x00000800,uint32_t))  /* TF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Mask */
-#define ENUM_SPI_RF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RF: Disable (mask) interrupt */
-#define ENUM_SPI_RF_HI                       (_ADI_MSK(0x00000400,uint32_t))  /* RF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Mask */
-#define ENUM_SPI_TS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TS: Disable (mask) interrupt */
-#define ENUM_SPI_TS_HI                       (_ADI_MSK(0x00000200,uint32_t))  /* TS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Mask */
-#define ENUM_SPI_RS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RS: Disable (mask) interrupt */
-#define ENUM_SPI_RS_HI                       (_ADI_MSK(0x00000100,uint32_t))  /* RS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Mask */
-#define ENUM_SPI_MF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* MF: Disable (mask) interrupt */
-#define ENUM_SPI_MF_HI                       (_ADI_MSK(0x00000080,uint32_t))  /* MF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Mask */
-#define ENUM_SPI_TC_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TC: Disable (mask) interrupt */
-#define ENUM_SPI_TC_HI                       (_ADI_MSK(0x00000040,uint32_t))  /* TC: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Interrupt Mask */
-#define ENUM_SPI_TUR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* TUR: Disable (mask) interrupt */
-#define ENUM_SPI_TUR_HI                      (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Mask */
-#define ENUM_SPI_ROR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* ROR: Disable (mask) interrupt */
-#define ENUM_SPI_ROR_HI                      (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_TUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disable (mask) interrupt */
-#define ENUM_SPI_TUWM_HI                     (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_RUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disable (mask) interrupt */
-#define ENUM_SPI_RUWM_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RF                 10                               /* Clear Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TS                  9                               /* Clear Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RS                  8                               /* Clear Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_MF                  7                               /* Clear Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_SET_TF                 11                               /* Set Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RF                 10                               /* Set Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TS                  9                               /* Set Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RS                  8                               /* Set Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_MF                  7                               /* Set Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TC                  6                               /* Set Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUR                 5                               /* Set Transmit Under-run  Interrupt Mask */
-#define BITP_SPI_IMSK_SET_ROR                 4                               /* Set Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUWM                2                               /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RUWM                1                               /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_SET are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_SET_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Set Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Set Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Set Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Set Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Set Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Set Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Set Transmit Under-run  Interrupt Mask */
-#define BITM_SPI_IMSK_SET_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Set Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_STAT_TFF                    23                               /* SPI_TFIFO Full */
-#define BITP_SPI_STAT_RFE                    22                               /* SPI_RFIFO Empty */
-#define BITP_SPI_STAT_FCS                    20                               /* Flow Control Stall Indication */
-#define BITP_SPI_STAT_TFS                    16                               /* SPI_TFIFO Status */
-#define BITP_SPI_STAT_RFS                    12                               /* SPI_RFIFO Status */
-#define BITP_SPI_STAT_TF                     11                               /* Transmit Finish Indication */
-#define BITP_SPI_STAT_RF                     10                               /* Receive Finish Indication */
-#define BITP_SPI_STAT_TS                      9                               /* Transmit Start */
-#define BITP_SPI_STAT_RS                      8                               /* Receive Start */
-#define BITP_SPI_STAT_MF                      7                               /* Mode Fault Indication */
-#define BITP_SPI_STAT_TC                      6                               /* Transmit Collision Indication */
-#define BITP_SPI_STAT_TUR                     5                               /* Transmit Underrun Indication */
-#define BITP_SPI_STAT_ROR                     4                               /* Receive Overrun Indication */
-#define BITP_SPI_STAT_TUWM                    2                               /* Transmit Urgent Watermark Breached */
-#define BITP_SPI_STAT_RUWM                    1                               /* Receive Urgent Watermark Breached */
-#define BITP_SPI_STAT_SPIF                    0                               /* SPI Finished */
-
-#define BITM_SPI_STAT_TFF                    (_ADI_MSK(0x00800000,uint32_t))  /* SPI_TFIFO Full */
-#define ENUM_SPI_STAT_TFIFO_NF               (_ADI_MSK(0x00000000,uint32_t))  /* TFF: Not full Tx FIFO */
-#define ENUM_SPI_STAT_TFIFO_F                (_ADI_MSK(0x00800000,uint32_t))  /* TFF: Full Tx FIFO */
-
-#define BITM_SPI_STAT_RFE                    (_ADI_MSK(0x00400000,uint32_t))  /* SPI_RFIFO Empty */
-#define ENUM_SPI_STAT_RFIFO_E                (_ADI_MSK(0x00000000,uint32_t))  /* RFE: Empty Rx FIFO */
-#define ENUM_SPI_STAT_RFIFO_NE               (_ADI_MSK(0x00400000,uint32_t))  /* RFE: Not empty Rx FIFO */
-
-#define BITM_SPI_STAT_FCS                    (_ADI_MSK(0x00100000,uint32_t))  /* Flow Control Stall Indication */
-#define ENUM_SPI_STAT_STALL                  (_ADI_MSK(0x00000000,uint32_t))  /* FCS: Stall (RDY pin asserted) */
-#define ENUM_SPI_STAT_NOSTALL                (_ADI_MSK(0x00100000,uint32_t))  /* FCS: No stall (RDY pin de-asserted) */
-
-#define BITM_SPI_STAT_TFS                    (_ADI_MSK(0x00070000,uint32_t))  /* SPI_TFIFO Status */
-#define ENUM_SPI_STAT_TFIFO_FULL             (_ADI_MSK(0x00000000,uint32_t))  /* TFS: Full TFIFO */
-#define ENUM_SPI_STAT_TFIFO_25               (_ADI_MSK(0x00010000,uint32_t))  /* TFS: 25% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_50               (_ADI_MSK(0x00020000,uint32_t))  /* TFS: 50% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_75               (_ADI_MSK(0x00030000,uint32_t))  /* TFS: 75% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_EMPTY            (_ADI_MSK(0x00040000,uint32_t))  /* TFS: Empty TFIFO */
-
-#define BITM_SPI_STAT_RFS                    (_ADI_MSK(0x00007000,uint32_t))  /* SPI_RFIFO Status */
-#define ENUM_SPI_STAT_RFIFO_EMPTY            (_ADI_MSK(0x00000000,uint32_t))  /* RFS: Empty RFIFO */
-#define ENUM_SPI_STAT_RFIFO_25               (_ADI_MSK(0x00001000,uint32_t))  /* RFS: 25% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_50               (_ADI_MSK(0x00002000,uint32_t))  /* RFS: 50% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_75               (_ADI_MSK(0x00003000,uint32_t))  /* RFS: 75% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_FULL             (_ADI_MSK(0x00004000,uint32_t))  /* RFS: Full RFIFO */
-
-#define BITM_SPI_STAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Indication */
-#define ENUM_SPI_STAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No status */
-#define ENUM_SPI_STAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Transmit finish detected */
-
-#define BITM_SPI_STAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Indication */
-#define ENUM_SPI_STAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No status */
-#define ENUM_SPI_STAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Receive finish detected */
-
-#define BITM_SPI_STAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start */
-#define ENUM_SPI_STAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No status */
-#define ENUM_SPI_STAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Transmit start detected */
-
-#define BITM_SPI_STAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start */
-#define ENUM_SPI_STAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No status */
-#define ENUM_SPI_STAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Receive start detected */
-
-#define BITM_SPI_STAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Indication */
-#define ENUM_SPI_STAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No status */
-#define ENUM_SPI_STAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Mode fault occurred */
-
-#define BITM_SPI_STAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Indication */
-#define ENUM_SPI_STAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No status */
-#define ENUM_SPI_STAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Transmit collision occurred */
-
-#define BITM_SPI_STAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Indication */
-#define ENUM_SPI_STAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No status */
-#define ENUM_SPI_STAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Transmit underrun occurred */
-
-#define BITM_SPI_STAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Indication */
-#define ENUM_SPI_STAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No status */
-#define ENUM_SPI_STAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Receive overrun occurred */
-
-#define BITM_SPI_STAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Breached */
-#define ENUM_SPI_STAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: TX Regular Watermark reached */
-#define ENUM_SPI_STAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: TX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Breached */
-#define ENUM_SPI_STAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: RX Regular Watermark reached */
-#define ENUM_SPI_STAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: RX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_SPIF                   (_ADI_MSK(0x00000001,uint32_t))  /* SPI Finished */
-#define ENUM_SPI_STAT_SPIF_LO                (_ADI_MSK(0x00000000,uint32_t))  /* SPIF: No status */
-#define ENUM_SPI_STAT_SPIF_HI                (_ADI_MSK(0x00000001,uint32_t))  /* SPIF: Completed single-word transfer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_TF                     11                               /* Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_RF                     10                               /* Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_TS                      9                               /* Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_RS                      8                               /* Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_MF                      7                               /* Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_TC                      6                               /* Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_TUR                     5                               /* Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_ROR                     4                               /* Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_RUWM                    1                               /* Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-
-#define BITM_SPI_ILAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No interrupt */
-#define ENUM_SPI_ILAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Latched interrupt */
-
-#define BITM_SPI_ILAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No interrupt */
-#define ENUM_SPI_ILAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Latch */
-#define ENUM_SPI_ILAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No interrupt */
-#define ENUM_SPI_ILAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Latched interrupt */
-
-#define BITM_SPI_ILAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Latch */
-#define ENUM_SPI_ILAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No interrupt */
-#define ENUM_SPI_ILAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Latched interrupt */
-
-#define BITM_SPI_ILAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Latch */
-#define ENUM_SPI_ILAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No interrupt */
-#define ENUM_SPI_ILAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Latch */
-#define ENUM_SPI_ILAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No interrupt */
-#define ENUM_SPI_ILAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Under-run Interrupt Latch */
-#define ENUM_SPI_ILAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No interrupt */
-#define ENUM_SPI_ILAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Latched interrupt */
-
-#define BITM_SPI_ILAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Latch */
-#define ENUM_SPI_ILAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No interrupt */
-#define ENUM_SPI_ILAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: No interrupt */
-#define ENUM_SPI_ILAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Latched interrupt */
-
-#define BITM_SPI_ILAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: No interrupt */
-#define ENUM_SPI_ILAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Latched interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RF                 10                               /* Clear Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TS                  9                               /* Clear Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RS                  8                               /* Clear Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_MF                  7                               /* Clear Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_ILAT_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* ==================================================
-        DMA Channel Registers
-   ================================================== */
-
-/* =========================
-        DMA0
-   ========================= */
-#define REG_DMA0_DSCPTR_NXT             0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
-#define REG_DMA0_ADDRSTART              0xFFC41004         /* DMA0 Start Address of Current Buffer */
-#define REG_DMA0_CFG                    0xFFC41008         /* DMA0 Configuration Register */
-#define REG_DMA0_XCNT                   0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
-#define REG_DMA0_XMOD                   0xFFC41010         /* DMA0 Inner Loop Address Increment */
-#define REG_DMA0_YCNT                   0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
-#define REG_DMA0_YMOD                   0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
-#define REG_DMA0_DSCPTR_CUR             0xFFC41024         /* DMA0 Current Descriptor Pointer */
-#define REG_DMA0_DSCPTR_PRV             0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
-#define REG_DMA0_ADDR_CUR               0xFFC4102C         /* DMA0 Current Address */
-#define REG_DMA0_STAT                   0xFFC41030         /* DMA0 Status Register */
-#define REG_DMA0_XCNT_CUR               0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA0_YCNT_CUR               0xFFC41038         /* DMA0 Current Row Count (2D only) */
-#define REG_DMA0_BWLCNT                 0xFFC41040         /* DMA0 Bandwidth Limit Count */
-#define REG_DMA0_BWLCNT_CUR             0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
-#define REG_DMA0_BWMCNT                 0xFFC41048         /* DMA0 Bandwidth Monitor Count */
-#define REG_DMA0_BWMCNT_CUR             0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA1
-   ========================= */
-#define REG_DMA1_DSCPTR_NXT             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
-#define REG_DMA1_ADDRSTART              0xFFC41084         /* DMA1 Start Address of Current Buffer */
-#define REG_DMA1_CFG                    0xFFC41088         /* DMA1 Configuration Register */
-#define REG_DMA1_XCNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
-#define REG_DMA1_XMOD                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
-#define REG_DMA1_YCNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
-#define REG_DMA1_YMOD                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
-#define REG_DMA1_DSCPTR_CUR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
-#define REG_DMA1_DSCPTR_PRV             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
-#define REG_DMA1_ADDR_CUR               0xFFC410AC         /* DMA1 Current Address */
-#define REG_DMA1_STAT                   0xFFC410B0         /* DMA1 Status Register */
-#define REG_DMA1_XCNT_CUR               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA1_YCNT_CUR               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
-#define REG_DMA1_BWLCNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
-#define REG_DMA1_BWLCNT_CUR             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
-#define REG_DMA1_BWMCNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
-#define REG_DMA1_BWMCNT_CUR             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA2
-   ========================= */
-#define REG_DMA2_DSCPTR_NXT             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
-#define REG_DMA2_ADDRSTART              0xFFC41104         /* DMA2 Start Address of Current Buffer */
-#define REG_DMA2_CFG                    0xFFC41108         /* DMA2 Configuration Register */
-#define REG_DMA2_XCNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
-#define REG_DMA2_XMOD                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
-#define REG_DMA2_YCNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
-#define REG_DMA2_YMOD                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
-#define REG_DMA2_DSCPTR_CUR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
-#define REG_DMA2_DSCPTR_PRV             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
-#define REG_DMA2_ADDR_CUR               0xFFC4112C         /* DMA2 Current Address */
-#define REG_DMA2_STAT                   0xFFC41130         /* DMA2 Status Register */
-#define REG_DMA2_XCNT_CUR               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA2_YCNT_CUR               0xFFC41138         /* DMA2 Current Row Count (2D only) */
-#define REG_DMA2_BWLCNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
-#define REG_DMA2_BWLCNT_CUR             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
-#define REG_DMA2_BWMCNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
-#define REG_DMA2_BWMCNT_CUR             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA3
-   ========================= */
-#define REG_DMA3_DSCPTR_NXT             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
-#define REG_DMA3_ADDRSTART              0xFFC41184         /* DMA3 Start Address of Current Buffer */
-#define REG_DMA3_CFG                    0xFFC41188         /* DMA3 Configuration Register */
-#define REG_DMA3_XCNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
-#define REG_DMA3_XMOD                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
-#define REG_DMA3_YCNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
-#define REG_DMA3_YMOD                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
-#define REG_DMA3_DSCPTR_CUR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
-#define REG_DMA3_DSCPTR_PRV             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
-#define REG_DMA3_ADDR_CUR               0xFFC411AC         /* DMA3 Current Address */
-#define REG_DMA3_STAT                   0xFFC411B0         /* DMA3 Status Register */
-#define REG_DMA3_XCNT_CUR               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA3_YCNT_CUR               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
-#define REG_DMA3_BWLCNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
-#define REG_DMA3_BWLCNT_CUR             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
-#define REG_DMA3_BWMCNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
-#define REG_DMA3_BWMCNT_CUR             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA4
-   ========================= */
-#define REG_DMA4_DSCPTR_NXT             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
-#define REG_DMA4_ADDRSTART              0xFFC41204         /* DMA4 Start Address of Current Buffer */
-#define REG_DMA4_CFG                    0xFFC41208         /* DMA4 Configuration Register */
-#define REG_DMA4_XCNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
-#define REG_DMA4_XMOD                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
-#define REG_DMA4_YCNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
-#define REG_DMA4_YMOD                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
-#define REG_DMA4_DSCPTR_CUR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
-#define REG_DMA4_DSCPTR_PRV             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
-#define REG_DMA4_ADDR_CUR               0xFFC4122C         /* DMA4 Current Address */
-#define REG_DMA4_STAT                   0xFFC41230         /* DMA4 Status Register */
-#define REG_DMA4_XCNT_CUR               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA4_YCNT_CUR               0xFFC41238         /* DMA4 Current Row Count (2D only) */
-#define REG_DMA4_BWLCNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
-#define REG_DMA4_BWLCNT_CUR             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
-#define REG_DMA4_BWMCNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
-#define REG_DMA4_BWMCNT_CUR             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA5
-   ========================= */
-#define REG_DMA5_DSCPTR_NXT             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
-#define REG_DMA5_ADDRSTART              0xFFC41284         /* DMA5 Start Address of Current Buffer */
-#define REG_DMA5_CFG                    0xFFC41288         /* DMA5 Configuration Register */
-#define REG_DMA5_XCNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
-#define REG_DMA5_XMOD                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
-#define REG_DMA5_YCNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
-#define REG_DMA5_YMOD                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
-#define REG_DMA5_DSCPTR_CUR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
-#define REG_DMA5_DSCPTR_PRV             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
-#define REG_DMA5_ADDR_CUR               0xFFC412AC         /* DMA5 Current Address */
-#define REG_DMA5_STAT                   0xFFC412B0         /* DMA5 Status Register */
-#define REG_DMA5_XCNT_CUR               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA5_YCNT_CUR               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
-#define REG_DMA5_BWLCNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
-#define REG_DMA5_BWLCNT_CUR             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
-#define REG_DMA5_BWMCNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
-#define REG_DMA5_BWMCNT_CUR             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA6
-   ========================= */
-#define REG_DMA6_DSCPTR_NXT             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
-#define REG_DMA6_ADDRSTART              0xFFC41304         /* DMA6 Start Address of Current Buffer */
-#define REG_DMA6_CFG                    0xFFC41308         /* DMA6 Configuration Register */
-#define REG_DMA6_XCNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
-#define REG_DMA6_XMOD                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
-#define REG_DMA6_YCNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
-#define REG_DMA6_YMOD                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
-#define REG_DMA6_DSCPTR_CUR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
-#define REG_DMA6_DSCPTR_PRV             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
-#define REG_DMA6_ADDR_CUR               0xFFC4132C         /* DMA6 Current Address */
-#define REG_DMA6_STAT                   0xFFC41330         /* DMA6 Status Register */
-#define REG_DMA6_XCNT_CUR               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA6_YCNT_CUR               0xFFC41338         /* DMA6 Current Row Count (2D only) */
-#define REG_DMA6_BWLCNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
-#define REG_DMA6_BWLCNT_CUR             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
-#define REG_DMA6_BWMCNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
-#define REG_DMA6_BWMCNT_CUR             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA7
-   ========================= */
-#define REG_DMA7_DSCPTR_NXT             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
-#define REG_DMA7_ADDRSTART              0xFFC41384         /* DMA7 Start Address of Current Buffer */
-#define REG_DMA7_CFG                    0xFFC41388         /* DMA7 Configuration Register */
-#define REG_DMA7_XCNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
-#define REG_DMA7_XMOD                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
-#define REG_DMA7_YCNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
-#define REG_DMA7_YMOD                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
-#define REG_DMA7_DSCPTR_CUR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
-#define REG_DMA7_DSCPTR_PRV             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
-#define REG_DMA7_ADDR_CUR               0xFFC413AC         /* DMA7 Current Address */
-#define REG_DMA7_STAT                   0xFFC413B0         /* DMA7 Status Register */
-#define REG_DMA7_XCNT_CUR               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA7_YCNT_CUR               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
-#define REG_DMA7_BWLCNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
-#define REG_DMA7_BWLCNT_CUR             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
-#define REG_DMA7_BWMCNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
-#define REG_DMA7_BWMCNT_CUR             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA8
-   ========================= */
-#define REG_DMA8_DSCPTR_NXT             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
-#define REG_DMA8_ADDRSTART              0xFFC41404         /* DMA8 Start Address of Current Buffer */
-#define REG_DMA8_CFG                    0xFFC41408         /* DMA8 Configuration Register */
-#define REG_DMA8_XCNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
-#define REG_DMA8_XMOD                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
-#define REG_DMA8_YCNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
-#define REG_DMA8_YMOD                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
-#define REG_DMA8_DSCPTR_CUR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
-#define REG_DMA8_DSCPTR_PRV             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
-#define REG_DMA8_ADDR_CUR               0xFFC4142C         /* DMA8 Current Address */
-#define REG_DMA8_STAT                   0xFFC41430         /* DMA8 Status Register */
-#define REG_DMA8_XCNT_CUR               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA8_YCNT_CUR               0xFFC41438         /* DMA8 Current Row Count (2D only) */
-#define REG_DMA8_BWLCNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
-#define REG_DMA8_BWLCNT_CUR             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
-#define REG_DMA8_BWMCNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
-#define REG_DMA8_BWMCNT_CUR             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA9
-   ========================= */
-#define REG_DMA9_DSCPTR_NXT             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
-#define REG_DMA9_ADDRSTART              0xFFC41484         /* DMA9 Start Address of Current Buffer */
-#define REG_DMA9_CFG                    0xFFC41488         /* DMA9 Configuration Register */
-#define REG_DMA9_XCNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
-#define REG_DMA9_XMOD                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
-#define REG_DMA9_YCNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
-#define REG_DMA9_YMOD                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
-#define REG_DMA9_DSCPTR_CUR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
-#define REG_DMA9_DSCPTR_PRV             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
-#define REG_DMA9_ADDR_CUR               0xFFC414AC         /* DMA9 Current Address */
-#define REG_DMA9_STAT                   0xFFC414B0         /* DMA9 Status Register */
-#define REG_DMA9_XCNT_CUR               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA9_YCNT_CUR               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
-#define REG_DMA9_BWLCNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
-#define REG_DMA9_BWLCNT_CUR             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
-#define REG_DMA9_BWMCNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
-#define REG_DMA9_BWMCNT_CUR             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA10
-   ========================= */
-#define REG_DMA10_DSCPTR_NXT            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
-#define REG_DMA10_ADDRSTART             0xFFC05004         /* DMA10 Start Address of Current Buffer */
-#define REG_DMA10_CFG                   0xFFC05008         /* DMA10 Configuration Register */
-#define REG_DMA10_XCNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
-#define REG_DMA10_XMOD                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
-#define REG_DMA10_YCNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
-#define REG_DMA10_YMOD                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
-#define REG_DMA10_DSCPTR_CUR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
-#define REG_DMA10_DSCPTR_PRV            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
-#define REG_DMA10_ADDR_CUR              0xFFC0502C         /* DMA10 Current Address */
-#define REG_DMA10_STAT                  0xFFC05030         /* DMA10 Status Register */
-#define REG_DMA10_XCNT_CUR              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA10_YCNT_CUR              0xFFC05038         /* DMA10 Current Row Count (2D only) */
-#define REG_DMA10_BWLCNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
-#define REG_DMA10_BWLCNT_CUR            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
-#define REG_DMA10_BWMCNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
-#define REG_DMA10_BWMCNT_CUR            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA11
-   ========================= */
-#define REG_DMA11_DSCPTR_NXT            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
-#define REG_DMA11_ADDRSTART             0xFFC05084         /* DMA11 Start Address of Current Buffer */
-#define REG_DMA11_CFG                   0xFFC05088         /* DMA11 Configuration Register */
-#define REG_DMA11_XCNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
-#define REG_DMA11_XMOD                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
-#define REG_DMA11_YCNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
-#define REG_DMA11_YMOD                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
-#define REG_DMA11_DSCPTR_CUR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
-#define REG_DMA11_DSCPTR_PRV            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
-#define REG_DMA11_ADDR_CUR              0xFFC050AC         /* DMA11 Current Address */
-#define REG_DMA11_STAT                  0xFFC050B0         /* DMA11 Status Register */
-#define REG_DMA11_XCNT_CUR              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA11_YCNT_CUR              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
-#define REG_DMA11_BWLCNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
-#define REG_DMA11_BWLCNT_CUR            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
-#define REG_DMA11_BWMCNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
-#define REG_DMA11_BWMCNT_CUR            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA12
-   ========================= */
-#define REG_DMA12_DSCPTR_NXT            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
-#define REG_DMA12_ADDRSTART             0xFFC05104         /* DMA12 Start Address of Current Buffer */
-#define REG_DMA12_CFG                   0xFFC05108         /* DMA12 Configuration Register */
-#define REG_DMA12_XCNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
-#define REG_DMA12_XMOD                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
-#define REG_DMA12_YCNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
-#define REG_DMA12_YMOD                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
-#define REG_DMA12_DSCPTR_CUR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
-#define REG_DMA12_DSCPTR_PRV            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
-#define REG_DMA12_ADDR_CUR              0xFFC0512C         /* DMA12 Current Address */
-#define REG_DMA12_STAT                  0xFFC05130         /* DMA12 Status Register */
-#define REG_DMA12_XCNT_CUR              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA12_YCNT_CUR              0xFFC05138         /* DMA12 Current Row Count (2D only) */
-#define REG_DMA12_BWLCNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
-#define REG_DMA12_BWLCNT_CUR            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
-#define REG_DMA12_BWMCNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
-#define REG_DMA12_BWMCNT_CUR            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA13
-   ========================= */
-#define REG_DMA13_DSCPTR_NXT            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
-#define REG_DMA13_ADDRSTART             0xFFC07004         /* DMA13 Start Address of Current Buffer */
-#define REG_DMA13_CFG                   0xFFC07008         /* DMA13 Configuration Register */
-#define REG_DMA13_XCNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
-#define REG_DMA13_XMOD                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
-#define REG_DMA13_YCNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
-#define REG_DMA13_YMOD                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
-#define REG_DMA13_DSCPTR_CUR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
-#define REG_DMA13_DSCPTR_PRV            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
-#define REG_DMA13_ADDR_CUR              0xFFC0702C         /* DMA13 Current Address */
-#define REG_DMA13_STAT                  0xFFC07030         /* DMA13 Status Register */
-#define REG_DMA13_XCNT_CUR              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA13_YCNT_CUR              0xFFC07038         /* DMA13 Current Row Count (2D only) */
-#define REG_DMA13_BWLCNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
-#define REG_DMA13_BWLCNT_CUR            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
-#define REG_DMA13_BWMCNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
-#define REG_DMA13_BWMCNT_CUR            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA14
-   ========================= */
-#define REG_DMA14_DSCPTR_NXT            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
-#define REG_DMA14_ADDRSTART             0xFFC07084         /* DMA14 Start Address of Current Buffer */
-#define REG_DMA14_CFG                   0xFFC07088         /* DMA14 Configuration Register */
-#define REG_DMA14_XCNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
-#define REG_DMA14_XMOD                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
-#define REG_DMA14_YCNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
-#define REG_DMA14_YMOD                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
-#define REG_DMA14_DSCPTR_CUR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
-#define REG_DMA14_DSCPTR_PRV            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
-#define REG_DMA14_ADDR_CUR              0xFFC070AC         /* DMA14 Current Address */
-#define REG_DMA14_STAT                  0xFFC070B0         /* DMA14 Status Register */
-#define REG_DMA14_XCNT_CUR              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA14_YCNT_CUR              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
-#define REG_DMA14_BWLCNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
-#define REG_DMA14_BWLCNT_CUR            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
-#define REG_DMA14_BWMCNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
-#define REG_DMA14_BWMCNT_CUR            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA15
-   ========================= */
-#define REG_DMA15_DSCPTR_NXT            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
-#define REG_DMA15_ADDRSTART             0xFFC07104         /* DMA15 Start Address of Current Buffer */
-#define REG_DMA15_CFG                   0xFFC07108         /* DMA15 Configuration Register */
-#define REG_DMA15_XCNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
-#define REG_DMA15_XMOD                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
-#define REG_DMA15_YCNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
-#define REG_DMA15_YMOD                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
-#define REG_DMA15_DSCPTR_CUR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
-#define REG_DMA15_DSCPTR_PRV            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
-#define REG_DMA15_ADDR_CUR              0xFFC0712C         /* DMA15 Current Address */
-#define REG_DMA15_STAT                  0xFFC07130         /* DMA15 Status Register */
-#define REG_DMA15_XCNT_CUR              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA15_YCNT_CUR              0xFFC07138         /* DMA15 Current Row Count (2D only) */
-#define REG_DMA15_BWLCNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
-#define REG_DMA15_BWLCNT_CUR            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
-#define REG_DMA15_BWMCNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
-#define REG_DMA15_BWMCNT_CUR            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA16
-   ========================= */
-#define REG_DMA16_DSCPTR_NXT            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
-#define REG_DMA16_ADDRSTART             0xFFC07184         /* DMA16 Start Address of Current Buffer */
-#define REG_DMA16_CFG                   0xFFC07188         /* DMA16 Configuration Register */
-#define REG_DMA16_XCNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
-#define REG_DMA16_XMOD                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
-#define REG_DMA16_YCNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
-#define REG_DMA16_YMOD                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
-#define REG_DMA16_DSCPTR_CUR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
-#define REG_DMA16_DSCPTR_PRV            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
-#define REG_DMA16_ADDR_CUR              0xFFC071AC         /* DMA16 Current Address */
-#define REG_DMA16_STAT                  0xFFC071B0         /* DMA16 Status Register */
-#define REG_DMA16_XCNT_CUR              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA16_YCNT_CUR              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
-#define REG_DMA16_BWLCNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
-#define REG_DMA16_BWLCNT_CUR            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
-#define REG_DMA16_BWMCNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
-#define REG_DMA16_BWMCNT_CUR            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA17
-   ========================= */
-#define REG_DMA17_DSCPTR_NXT            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
-#define REG_DMA17_ADDRSTART             0xFFC07204         /* DMA17 Start Address of Current Buffer */
-#define REG_DMA17_CFG                   0xFFC07208         /* DMA17 Configuration Register */
-#define REG_DMA17_XCNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
-#define REG_DMA17_XMOD                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
-#define REG_DMA17_YCNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
-#define REG_DMA17_YMOD                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
-#define REG_DMA17_DSCPTR_CUR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
-#define REG_DMA17_DSCPTR_PRV            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
-#define REG_DMA17_ADDR_CUR              0xFFC0722C         /* DMA17 Current Address */
-#define REG_DMA17_STAT                  0xFFC07230         /* DMA17 Status Register */
-#define REG_DMA17_XCNT_CUR              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA17_YCNT_CUR              0xFFC07238         /* DMA17 Current Row Count (2D only) */
-#define REG_DMA17_BWLCNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
-#define REG_DMA17_BWLCNT_CUR            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
-#define REG_DMA17_BWMCNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
-#define REG_DMA17_BWMCNT_CUR            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA18
-   ========================= */
-#define REG_DMA18_DSCPTR_NXT            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
-#define REG_DMA18_ADDRSTART             0xFFC07284         /* DMA18 Start Address of Current Buffer */
-#define REG_DMA18_CFG                   0xFFC07288         /* DMA18 Configuration Register */
-#define REG_DMA18_XCNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
-#define REG_DMA18_XMOD                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
-#define REG_DMA18_YCNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
-#define REG_DMA18_YMOD                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
-#define REG_DMA18_DSCPTR_CUR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
-#define REG_DMA18_DSCPTR_PRV            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
-#define REG_DMA18_ADDR_CUR              0xFFC072AC         /* DMA18 Current Address */
-#define REG_DMA18_STAT                  0xFFC072B0         /* DMA18 Status Register */
-#define REG_DMA18_XCNT_CUR              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA18_YCNT_CUR              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
-#define REG_DMA18_BWLCNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
-#define REG_DMA18_BWLCNT_CUR            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
-#define REG_DMA18_BWMCNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
-#define REG_DMA18_BWMCNT_CUR            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA19
-   ========================= */
-#define REG_DMA19_DSCPTR_NXT            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
-#define REG_DMA19_ADDRSTART             0xFFC07304         /* DMA19 Start Address of Current Buffer */
-#define REG_DMA19_CFG                   0xFFC07308         /* DMA19 Configuration Register */
-#define REG_DMA19_XCNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
-#define REG_DMA19_XMOD                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
-#define REG_DMA19_YCNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
-#define REG_DMA19_YMOD                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
-#define REG_DMA19_DSCPTR_CUR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
-#define REG_DMA19_DSCPTR_PRV            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
-#define REG_DMA19_ADDR_CUR              0xFFC0732C         /* DMA19 Current Address */
-#define REG_DMA19_STAT                  0xFFC07330         /* DMA19 Status Register */
-#define REG_DMA19_XCNT_CUR              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA19_YCNT_CUR              0xFFC07338         /* DMA19 Current Row Count (2D only) */
-#define REG_DMA19_BWLCNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
-#define REG_DMA19_BWLCNT_CUR            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
-#define REG_DMA19_BWMCNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
-#define REG_DMA19_BWMCNT_CUR            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA20
-   ========================= */
-#define REG_DMA20_DSCPTR_NXT            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
-#define REG_DMA20_ADDRSTART             0xFFC07384         /* DMA20 Start Address of Current Buffer */
-#define REG_DMA20_CFG                   0xFFC07388         /* DMA20 Configuration Register */
-#define REG_DMA20_XCNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
-#define REG_DMA20_XMOD                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
-#define REG_DMA20_YCNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
-#define REG_DMA20_YMOD                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
-#define REG_DMA20_DSCPTR_CUR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
-#define REG_DMA20_DSCPTR_PRV            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
-#define REG_DMA20_ADDR_CUR              0xFFC073AC         /* DMA20 Current Address */
-#define REG_DMA20_STAT                  0xFFC073B0         /* DMA20 Status Register */
-#define REG_DMA20_XCNT_CUR              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA20_YCNT_CUR              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
-#define REG_DMA20_BWLCNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
-#define REG_DMA20_BWLCNT_CUR            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
-#define REG_DMA20_BWMCNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
-#define REG_DMA20_BWMCNT_CUR            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA21
-   ========================= */
-#define REG_DMA21_DSCPTR_NXT            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
-#define REG_DMA21_ADDRSTART             0xFFC09004         /* DMA21 Start Address of Current Buffer */
-#define REG_DMA21_CFG                   0xFFC09008         /* DMA21 Configuration Register */
-#define REG_DMA21_XCNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
-#define REG_DMA21_XMOD                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
-#define REG_DMA21_YCNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
-#define REG_DMA21_YMOD                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
-#define REG_DMA21_DSCPTR_CUR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
-#define REG_DMA21_DSCPTR_PRV            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
-#define REG_DMA21_ADDR_CUR              0xFFC0902C         /* DMA21 Current Address */
-#define REG_DMA21_STAT                  0xFFC09030         /* DMA21 Status Register */
-#define REG_DMA21_XCNT_CUR              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA21_YCNT_CUR              0xFFC09038         /* DMA21 Current Row Count (2D only) */
-#define REG_DMA21_BWLCNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
-#define REG_DMA21_BWLCNT_CUR            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
-#define REG_DMA21_BWMCNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
-#define REG_DMA21_BWMCNT_CUR            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA22
-   ========================= */
-#define REG_DMA22_DSCPTR_NXT            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
-#define REG_DMA22_ADDRSTART             0xFFC09084         /* DMA22 Start Address of Current Buffer */
-#define REG_DMA22_CFG                   0xFFC09088         /* DMA22 Configuration Register */
-#define REG_DMA22_XCNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
-#define REG_DMA22_XMOD                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
-#define REG_DMA22_YCNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
-#define REG_DMA22_YMOD                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
-#define REG_DMA22_DSCPTR_CUR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
-#define REG_DMA22_DSCPTR_PRV            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
-#define REG_DMA22_ADDR_CUR              0xFFC090AC         /* DMA22 Current Address */
-#define REG_DMA22_STAT                  0xFFC090B0         /* DMA22 Status Register */
-#define REG_DMA22_XCNT_CUR              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA22_YCNT_CUR              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
-#define REG_DMA22_BWLCNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
-#define REG_DMA22_BWLCNT_CUR            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
-#define REG_DMA22_BWMCNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
-#define REG_DMA22_BWMCNT_CUR            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA23
-   ========================= */
-#define REG_DMA23_DSCPTR_NXT            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
-#define REG_DMA23_ADDRSTART             0xFFC09104         /* DMA23 Start Address of Current Buffer */
-#define REG_DMA23_CFG                   0xFFC09108         /* DMA23 Configuration Register */
-#define REG_DMA23_XCNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
-#define REG_DMA23_XMOD                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
-#define REG_DMA23_YCNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
-#define REG_DMA23_YMOD                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
-#define REG_DMA23_DSCPTR_CUR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
-#define REG_DMA23_DSCPTR_PRV            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
-#define REG_DMA23_ADDR_CUR              0xFFC0912C         /* DMA23 Current Address */
-#define REG_DMA23_STAT                  0xFFC09130         /* DMA23 Status Register */
-#define REG_DMA23_XCNT_CUR              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA23_YCNT_CUR              0xFFC09138         /* DMA23 Current Row Count (2D only) */
-#define REG_DMA23_BWLCNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
-#define REG_DMA23_BWLCNT_CUR            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
-#define REG_DMA23_BWMCNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
-#define REG_DMA23_BWMCNT_CUR            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA24
-   ========================= */
-#define REG_DMA24_DSCPTR_NXT            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
-#define REG_DMA24_ADDRSTART             0xFFC09184         /* DMA24 Start Address of Current Buffer */
-#define REG_DMA24_CFG                   0xFFC09188         /* DMA24 Configuration Register */
-#define REG_DMA24_XCNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
-#define REG_DMA24_XMOD                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
-#define REG_DMA24_YCNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
-#define REG_DMA24_YMOD                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
-#define REG_DMA24_DSCPTR_CUR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
-#define REG_DMA24_DSCPTR_PRV            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
-#define REG_DMA24_ADDR_CUR              0xFFC091AC         /* DMA24 Current Address */
-#define REG_DMA24_STAT                  0xFFC091B0         /* DMA24 Status Register */
-#define REG_DMA24_XCNT_CUR              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA24_YCNT_CUR              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
-#define REG_DMA24_BWLCNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
-#define REG_DMA24_BWLCNT_CUR            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
-#define REG_DMA24_BWMCNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
-#define REG_DMA24_BWMCNT_CUR            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA25
-   ========================= */
-#define REG_DMA25_DSCPTR_NXT            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
-#define REG_DMA25_ADDRSTART             0xFFC09204         /* DMA25 Start Address of Current Buffer */
-#define REG_DMA25_CFG                   0xFFC09208         /* DMA25 Configuration Register */
-#define REG_DMA25_XCNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
-#define REG_DMA25_XMOD                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
-#define REG_DMA25_YCNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
-#define REG_DMA25_YMOD                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
-#define REG_DMA25_DSCPTR_CUR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
-#define REG_DMA25_DSCPTR_PRV            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
-#define REG_DMA25_ADDR_CUR              0xFFC0922C         /* DMA25 Current Address */
-#define REG_DMA25_STAT                  0xFFC09230         /* DMA25 Status Register */
-#define REG_DMA25_XCNT_CUR              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA25_YCNT_CUR              0xFFC09238         /* DMA25 Current Row Count (2D only) */
-#define REG_DMA25_BWLCNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
-#define REG_DMA25_BWLCNT_CUR            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
-#define REG_DMA25_BWMCNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
-#define REG_DMA25_BWMCNT_CUR            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA26
-   ========================= */
-#define REG_DMA26_DSCPTR_NXT            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
-#define REG_DMA26_ADDRSTART             0xFFC09284         /* DMA26 Start Address of Current Buffer */
-#define REG_DMA26_CFG                   0xFFC09288         /* DMA26 Configuration Register */
-#define REG_DMA26_XCNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
-#define REG_DMA26_XMOD                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
-#define REG_DMA26_YCNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
-#define REG_DMA26_YMOD                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
-#define REG_DMA26_DSCPTR_CUR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
-#define REG_DMA26_DSCPTR_PRV            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
-#define REG_DMA26_ADDR_CUR              0xFFC092AC         /* DMA26 Current Address */
-#define REG_DMA26_STAT                  0xFFC092B0         /* DMA26 Status Register */
-#define REG_DMA26_XCNT_CUR              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA26_YCNT_CUR              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
-#define REG_DMA26_BWLCNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
-#define REG_DMA26_BWLCNT_CUR            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
-#define REG_DMA26_BWMCNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
-#define REG_DMA26_BWMCNT_CUR            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA27
-   ========================= */
-#define REG_DMA27_DSCPTR_NXT            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
-#define REG_DMA27_ADDRSTART             0xFFC09304         /* DMA27 Start Address of Current Buffer */
-#define REG_DMA27_CFG                   0xFFC09308         /* DMA27 Configuration Register */
-#define REG_DMA27_XCNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
-#define REG_DMA27_XMOD                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
-#define REG_DMA27_YCNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
-#define REG_DMA27_YMOD                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
-#define REG_DMA27_DSCPTR_CUR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
-#define REG_DMA27_DSCPTR_PRV            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
-#define REG_DMA27_ADDR_CUR              0xFFC0932C         /* DMA27 Current Address */
-#define REG_DMA27_STAT                  0xFFC09330         /* DMA27 Status Register */
-#define REG_DMA27_XCNT_CUR              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA27_YCNT_CUR              0xFFC09338         /* DMA27 Current Row Count (2D only) */
-#define REG_DMA27_BWLCNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
-#define REG_DMA27_BWLCNT_CUR            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
-#define REG_DMA27_BWMCNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
-#define REG_DMA27_BWMCNT_CUR            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA28
-   ========================= */
-#define REG_DMA28_DSCPTR_NXT            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
-#define REG_DMA28_ADDRSTART             0xFFC09384         /* DMA28 Start Address of Current Buffer */
-#define REG_DMA28_CFG                   0xFFC09388         /* DMA28 Configuration Register */
-#define REG_DMA28_XCNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
-#define REG_DMA28_XMOD                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
-#define REG_DMA28_YCNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
-#define REG_DMA28_YMOD                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
-#define REG_DMA28_DSCPTR_CUR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
-#define REG_DMA28_DSCPTR_PRV            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
-#define REG_DMA28_ADDR_CUR              0xFFC093AC         /* DMA28 Current Address */
-#define REG_DMA28_STAT                  0xFFC093B0         /* DMA28 Status Register */
-#define REG_DMA28_XCNT_CUR              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA28_YCNT_CUR              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
-#define REG_DMA28_BWLCNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
-#define REG_DMA28_BWLCNT_CUR            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
-#define REG_DMA28_BWMCNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
-#define REG_DMA28_BWMCNT_CUR            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA29
-   ========================= */
-#define REG_DMA29_DSCPTR_NXT            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
-#define REG_DMA29_ADDRSTART             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
-#define REG_DMA29_CFG                   0xFFC0B008         /* DMA29 Configuration Register */
-#define REG_DMA29_XCNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
-#define REG_DMA29_XMOD                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
-#define REG_DMA29_YCNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
-#define REG_DMA29_YMOD                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
-#define REG_DMA29_DSCPTR_CUR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
-#define REG_DMA29_DSCPTR_PRV            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
-#define REG_DMA29_ADDR_CUR              0xFFC0B02C         /* DMA29 Current Address */
-#define REG_DMA29_STAT                  0xFFC0B030         /* DMA29 Status Register */
-#define REG_DMA29_XCNT_CUR              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA29_YCNT_CUR              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
-#define REG_DMA29_BWLCNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
-#define REG_DMA29_BWLCNT_CUR            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
-#define REG_DMA29_BWMCNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
-#define REG_DMA29_BWMCNT_CUR            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA30
-   ========================= */
-#define REG_DMA30_DSCPTR_NXT            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
-#define REG_DMA30_ADDRSTART             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
-#define REG_DMA30_CFG                   0xFFC0B088         /* DMA30 Configuration Register */
-#define REG_DMA30_XCNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
-#define REG_DMA30_XMOD                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
-#define REG_DMA30_YCNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
-#define REG_DMA30_YMOD                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
-#define REG_DMA30_DSCPTR_CUR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
-#define REG_DMA30_DSCPTR_PRV            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
-#define REG_DMA30_ADDR_CUR              0xFFC0B0AC         /* DMA30 Current Address */
-#define REG_DMA30_STAT                  0xFFC0B0B0         /* DMA30 Status Register */
-#define REG_DMA30_XCNT_CUR              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA30_YCNT_CUR              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
-#define REG_DMA30_BWLCNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
-#define REG_DMA30_BWLCNT_CUR            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
-#define REG_DMA30_BWMCNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
-#define REG_DMA30_BWMCNT_CUR            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA31
-   ========================= */
-#define REG_DMA31_DSCPTR_NXT            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
-#define REG_DMA31_ADDRSTART             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
-#define REG_DMA31_CFG                   0xFFC0B108         /* DMA31 Configuration Register */
-#define REG_DMA31_XCNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
-#define REG_DMA31_XMOD                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
-#define REG_DMA31_YCNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
-#define REG_DMA31_YMOD                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
-#define REG_DMA31_DSCPTR_CUR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
-#define REG_DMA31_DSCPTR_PRV            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
-#define REG_DMA31_ADDR_CUR              0xFFC0B12C         /* DMA31 Current Address */
-#define REG_DMA31_STAT                  0xFFC0B130         /* DMA31 Status Register */
-#define REG_DMA31_XCNT_CUR              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA31_YCNT_CUR              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
-#define REG_DMA31_BWLCNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
-#define REG_DMA31_BWLCNT_CUR            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
-#define REG_DMA31_BWMCNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
-#define REG_DMA31_BWMCNT_CUR            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA32
-   ========================= */
-#define REG_DMA32_DSCPTR_NXT            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
-#define REG_DMA32_ADDRSTART             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
-#define REG_DMA32_CFG                   0xFFC0B188         /* DMA32 Configuration Register */
-#define REG_DMA32_XCNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
-#define REG_DMA32_XMOD                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
-#define REG_DMA32_YCNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
-#define REG_DMA32_YMOD                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
-#define REG_DMA32_DSCPTR_CUR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
-#define REG_DMA32_DSCPTR_PRV            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
-#define REG_DMA32_ADDR_CUR              0xFFC0B1AC         /* DMA32 Current Address */
-#define REG_DMA32_STAT                  0xFFC0B1B0         /* DMA32 Status Register */
-#define REG_DMA32_XCNT_CUR              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA32_YCNT_CUR              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
-#define REG_DMA32_BWLCNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
-#define REG_DMA32_BWLCNT_CUR            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
-#define REG_DMA32_BWMCNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
-#define REG_DMA32_BWMCNT_CUR            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA33
-   ========================= */
-#define REG_DMA33_DSCPTR_NXT            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
-#define REG_DMA33_ADDRSTART             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
-#define REG_DMA33_CFG                   0xFFC0D008         /* DMA33 Configuration Register */
-#define REG_DMA33_XCNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
-#define REG_DMA33_XMOD                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
-#define REG_DMA33_YCNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
-#define REG_DMA33_YMOD                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
-#define REG_DMA33_DSCPTR_CUR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
-#define REG_DMA33_DSCPTR_PRV            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
-#define REG_DMA33_ADDR_CUR              0xFFC0D02C         /* DMA33 Current Address */
-#define REG_DMA33_STAT                  0xFFC0D030         /* DMA33 Status Register */
-#define REG_DMA33_XCNT_CUR              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA33_YCNT_CUR              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
-#define REG_DMA33_BWLCNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
-#define REG_DMA33_BWLCNT_CUR            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
-#define REG_DMA33_BWMCNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
-#define REG_DMA33_BWMCNT_CUR            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA34
-   ========================= */
-#define REG_DMA34_DSCPTR_NXT            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
-#define REG_DMA34_ADDRSTART             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
-#define REG_DMA34_CFG                   0xFFC0D088         /* DMA34 Configuration Register */
-#define REG_DMA34_XCNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
-#define REG_DMA34_XMOD                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
-#define REG_DMA34_YCNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
-#define REG_DMA34_YMOD                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
-#define REG_DMA34_DSCPTR_CUR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
-#define REG_DMA34_DSCPTR_PRV            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
-#define REG_DMA34_ADDR_CUR              0xFFC0D0AC         /* DMA34 Current Address */
-#define REG_DMA34_STAT                  0xFFC0D0B0         /* DMA34 Status Register */
-#define REG_DMA34_XCNT_CUR              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA34_YCNT_CUR              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
-#define REG_DMA34_BWLCNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
-#define REG_DMA34_BWLCNT_CUR            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
-#define REG_DMA34_BWMCNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
-#define REG_DMA34_BWMCNT_CUR            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA35
-   ========================= */
-#define REG_DMA35_DSCPTR_NXT            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
-#define REG_DMA35_ADDRSTART             0xFFC10004         /* DMA35 Start Address of Current Buffer */
-#define REG_DMA35_CFG                   0xFFC10008         /* DMA35 Configuration Register */
-#define REG_DMA35_XCNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
-#define REG_DMA35_XMOD                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
-#define REG_DMA35_YCNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
-#define REG_DMA35_YMOD                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
-#define REG_DMA35_DSCPTR_CUR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
-#define REG_DMA35_DSCPTR_PRV            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
-#define REG_DMA35_ADDR_CUR              0xFFC1002C         /* DMA35 Current Address */
-#define REG_DMA35_STAT                  0xFFC10030         /* DMA35 Status Register */
-#define REG_DMA35_XCNT_CUR              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA35_YCNT_CUR              0xFFC10038         /* DMA35 Current Row Count (2D only) */
-#define REG_DMA35_BWLCNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
-#define REG_DMA35_BWLCNT_CUR            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
-#define REG_DMA35_BWMCNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
-#define REG_DMA35_BWMCNT_CUR            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA36
-   ========================= */
-#define REG_DMA36_DSCPTR_NXT            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
-#define REG_DMA36_ADDRSTART             0xFFC10084         /* DMA36 Start Address of Current Buffer */
-#define REG_DMA36_CFG                   0xFFC10088         /* DMA36 Configuration Register */
-#define REG_DMA36_XCNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
-#define REG_DMA36_XMOD                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
-#define REG_DMA36_YCNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
-#define REG_DMA36_YMOD                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
-#define REG_DMA36_DSCPTR_CUR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
-#define REG_DMA36_DSCPTR_PRV            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
-#define REG_DMA36_ADDR_CUR              0xFFC100AC         /* DMA36 Current Address */
-#define REG_DMA36_STAT                  0xFFC100B0         /* DMA36 Status Register */
-#define REG_DMA36_XCNT_CUR              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA36_YCNT_CUR              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
-#define REG_DMA36_BWLCNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
-#define REG_DMA36_BWLCNT_CUR            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
-#define REG_DMA36_BWMCNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
-#define REG_DMA36_BWMCNT_CUR            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA37
-   ========================= */
-#define REG_DMA37_DSCPTR_NXT            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
-#define REG_DMA37_ADDRSTART             0xFFC10104         /* DMA37 Start Address of Current Buffer */
-#define REG_DMA37_CFG                   0xFFC10108         /* DMA37 Configuration Register */
-#define REG_DMA37_XCNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
-#define REG_DMA37_XMOD                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
-#define REG_DMA37_YCNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
-#define REG_DMA37_YMOD                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
-#define REG_DMA37_DSCPTR_CUR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
-#define REG_DMA37_DSCPTR_PRV            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
-#define REG_DMA37_ADDR_CUR              0xFFC1012C         /* DMA37 Current Address */
-#define REG_DMA37_STAT                  0xFFC10130         /* DMA37 Status Register */
-#define REG_DMA37_XCNT_CUR              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA37_YCNT_CUR              0xFFC10138         /* DMA37 Current Row Count (2D only) */
-#define REG_DMA37_BWLCNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
-#define REG_DMA37_BWLCNT_CUR            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
-#define REG_DMA37_BWMCNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
-#define REG_DMA37_BWMCNT_CUR            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA38
-   ========================= */
-#define REG_DMA38_DSCPTR_NXT            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
-#define REG_DMA38_ADDRSTART             0xFFC12004         /* DMA38 Start Address of Current Buffer */
-#define REG_DMA38_CFG                   0xFFC12008         /* DMA38 Configuration Register */
-#define REG_DMA38_XCNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
-#define REG_DMA38_XMOD                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
-#define REG_DMA38_YCNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
-#define REG_DMA38_YMOD                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
-#define REG_DMA38_DSCPTR_CUR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
-#define REG_DMA38_DSCPTR_PRV            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
-#define REG_DMA38_ADDR_CUR              0xFFC1202C         /* DMA38 Current Address */
-#define REG_DMA38_STAT                  0xFFC12030         /* DMA38 Status Register */
-#define REG_DMA38_XCNT_CUR              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA38_YCNT_CUR              0xFFC12038         /* DMA38 Current Row Count (2D only) */
-#define REG_DMA38_BWLCNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
-#define REG_DMA38_BWLCNT_CUR            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
-#define REG_DMA38_BWMCNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
-#define REG_DMA38_BWMCNT_CUR            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA39
-   ========================= */
-#define REG_DMA39_DSCPTR_NXT            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
-#define REG_DMA39_ADDRSTART             0xFFC12084         /* DMA39 Start Address of Current Buffer */
-#define REG_DMA39_CFG                   0xFFC12088         /* DMA39 Configuration Register */
-#define REG_DMA39_XCNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
-#define REG_DMA39_XMOD                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
-#define REG_DMA39_YCNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
-#define REG_DMA39_YMOD                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
-#define REG_DMA39_DSCPTR_CUR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
-#define REG_DMA39_DSCPTR_PRV            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
-#define REG_DMA39_ADDR_CUR              0xFFC120AC         /* DMA39 Current Address */
-#define REG_DMA39_STAT                  0xFFC120B0         /* DMA39 Status Register */
-#define REG_DMA39_XCNT_CUR              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA39_YCNT_CUR              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
-#define REG_DMA39_BWLCNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
-#define REG_DMA39_BWLCNT_CUR            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
-#define REG_DMA39_BWMCNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
-#define REG_DMA39_BWMCNT_CUR            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA40
-   ========================= */
-#define REG_DMA40_DSCPTR_NXT            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
-#define REG_DMA40_ADDRSTART             0xFFC12104         /* DMA40 Start Address of Current Buffer */
-#define REG_DMA40_CFG                   0xFFC12108         /* DMA40 Configuration Register */
-#define REG_DMA40_XCNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
-#define REG_DMA40_XMOD                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
-#define REG_DMA40_YCNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
-#define REG_DMA40_YMOD                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
-#define REG_DMA40_DSCPTR_CUR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
-#define REG_DMA40_DSCPTR_PRV            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
-#define REG_DMA40_ADDR_CUR              0xFFC1212C         /* DMA40 Current Address */
-#define REG_DMA40_STAT                  0xFFC12130         /* DMA40 Status Register */
-#define REG_DMA40_XCNT_CUR              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA40_YCNT_CUR              0xFFC12138         /* DMA40 Current Row Count (2D only) */
-#define REG_DMA40_BWLCNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
-#define REG_DMA40_BWLCNT_CUR            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
-#define REG_DMA40_BWMCNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
-#define REG_DMA40_BWMCNT_CUR            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA41
-   ========================= */
-#define REG_DMA41_DSCPTR_NXT            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
-#define REG_DMA41_ADDRSTART             0xFFC12184         /* DMA41 Start Address of Current Buffer */
-#define REG_DMA41_CFG                   0xFFC12188         /* DMA41 Configuration Register */
-#define REG_DMA41_XCNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
-#define REG_DMA41_XMOD                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
-#define REG_DMA41_YCNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
-#define REG_DMA41_YMOD                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
-#define REG_DMA41_DSCPTR_CUR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
-#define REG_DMA41_DSCPTR_PRV            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
-#define REG_DMA41_ADDR_CUR              0xFFC121AC         /* DMA41 Current Address */
-#define REG_DMA41_STAT                  0xFFC121B0         /* DMA41 Status Register */
-#define REG_DMA41_XCNT_CUR              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA41_YCNT_CUR              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
-#define REG_DMA41_BWLCNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
-#define REG_DMA41_BWLCNT_CUR            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
-#define REG_DMA41_BWMCNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
-#define REG_DMA41_BWMCNT_CUR            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA42
-   ========================= */
-#define REG_DMA42_DSCPTR_NXT            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
-#define REG_DMA42_ADDRSTART             0xFFC14004         /* DMA42 Start Address of Current Buffer */
-#define REG_DMA42_CFG                   0xFFC14008         /* DMA42 Configuration Register */
-#define REG_DMA42_XCNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
-#define REG_DMA42_XMOD                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
-#define REG_DMA42_YCNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
-#define REG_DMA42_YMOD                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
-#define REG_DMA42_DSCPTR_CUR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
-#define REG_DMA42_DSCPTR_PRV            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
-#define REG_DMA42_ADDR_CUR              0xFFC1402C         /* DMA42 Current Address */
-#define REG_DMA42_STAT                  0xFFC14030         /* DMA42 Status Register */
-#define REG_DMA42_XCNT_CUR              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA42_YCNT_CUR              0xFFC14038         /* DMA42 Current Row Count (2D only) */
-#define REG_DMA42_BWLCNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
-#define REG_DMA42_BWLCNT_CUR            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
-#define REG_DMA42_BWMCNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
-#define REG_DMA42_BWMCNT_CUR            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA43
-   ========================= */
-#define REG_DMA43_DSCPTR_NXT            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
-#define REG_DMA43_ADDRSTART             0xFFC14084         /* DMA43 Start Address of Current Buffer */
-#define REG_DMA43_CFG                   0xFFC14088         /* DMA43 Configuration Register */
-#define REG_DMA43_XCNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
-#define REG_DMA43_XMOD                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
-#define REG_DMA43_YCNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
-#define REG_DMA43_YMOD                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
-#define REG_DMA43_DSCPTR_CUR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
-#define REG_DMA43_DSCPTR_PRV            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
-#define REG_DMA43_ADDR_CUR              0xFFC140AC         /* DMA43 Current Address */
-#define REG_DMA43_STAT                  0xFFC140B0         /* DMA43 Status Register */
-#define REG_DMA43_XCNT_CUR              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA43_YCNT_CUR              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
-#define REG_DMA43_BWLCNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
-#define REG_DMA43_BWLCNT_CUR            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
-#define REG_DMA43_BWMCNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
-#define REG_DMA43_BWMCNT_CUR            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA44
-   ========================= */
-#define REG_DMA44_DSCPTR_NXT            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
-#define REG_DMA44_ADDRSTART             0xFFC14104         /* DMA44 Start Address of Current Buffer */
-#define REG_DMA44_CFG                   0xFFC14108         /* DMA44 Configuration Register */
-#define REG_DMA44_XCNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
-#define REG_DMA44_XMOD                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
-#define REG_DMA44_YCNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
-#define REG_DMA44_YMOD                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
-#define REG_DMA44_DSCPTR_CUR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
-#define REG_DMA44_DSCPTR_PRV            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
-#define REG_DMA44_ADDR_CUR              0xFFC1412C         /* DMA44 Current Address */
-#define REG_DMA44_STAT                  0xFFC14130         /* DMA44 Status Register */
-#define REG_DMA44_XCNT_CUR              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA44_YCNT_CUR              0xFFC14138         /* DMA44 Current Row Count (2D only) */
-#define REG_DMA44_BWLCNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
-#define REG_DMA44_BWLCNT_CUR            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
-#define REG_DMA44_BWMCNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
-#define REG_DMA44_BWMCNT_CUR            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA45
-   ========================= */
-#define REG_DMA45_DSCPTR_NXT            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
-#define REG_DMA45_ADDRSTART             0xFFC14184         /* DMA45 Start Address of Current Buffer */
-#define REG_DMA45_CFG                   0xFFC14188         /* DMA45 Configuration Register */
-#define REG_DMA45_XCNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
-#define REG_DMA45_XMOD                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
-#define REG_DMA45_YCNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
-#define REG_DMA45_YMOD                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
-#define REG_DMA45_DSCPTR_CUR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
-#define REG_DMA45_DSCPTR_PRV            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
-#define REG_DMA45_ADDR_CUR              0xFFC141AC         /* DMA45 Current Address */
-#define REG_DMA45_STAT                  0xFFC141B0         /* DMA45 Status Register */
-#define REG_DMA45_XCNT_CUR              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA45_YCNT_CUR              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
-#define REG_DMA45_BWLCNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
-#define REG_DMA45_BWLCNT_CUR            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
-#define REG_DMA45_BWMCNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
-#define REG_DMA45_BWMCNT_CUR            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA46
-   ========================= */
-#define REG_DMA46_DSCPTR_NXT            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
-#define REG_DMA46_ADDRSTART             0xFFC14204         /* DMA46 Start Address of Current Buffer */
-#define REG_DMA46_CFG                   0xFFC14208         /* DMA46 Configuration Register */
-#define REG_DMA46_XCNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
-#define REG_DMA46_XMOD                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
-#define REG_DMA46_YCNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
-#define REG_DMA46_YMOD                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
-#define REG_DMA46_DSCPTR_CUR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
-#define REG_DMA46_DSCPTR_PRV            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
-#define REG_DMA46_ADDR_CUR              0xFFC1422C         /* DMA46 Current Address */
-#define REG_DMA46_STAT                  0xFFC14230         /* DMA46 Status Register */
-#define REG_DMA46_XCNT_CUR              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA46_YCNT_CUR              0xFFC14238         /* DMA46 Current Row Count (2D only) */
-#define REG_DMA46_BWLCNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
-#define REG_DMA46_BWLCNT_CUR            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
-#define REG_DMA46_BWMCNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
-#define REG_DMA46_BWMCNT_CUR            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_CFG_PDRF                    28                               /* Peripheral Data Request Forward */
-#define BITP_DMA_CFG_TWOD                    26                               /* Two Dimension Addressing Enable */
-#define BITP_DMA_CFG_DESCIDCPY               25                               /* Descriptor ID Copy Control */
-#define BITP_DMA_CFG_TOVEN                   24                               /* Trigger Overrun Error Enable */
-#define BITP_DMA_CFG_TRIG                    22                               /* Generate Outgoing Trigger */
-#define BITP_DMA_CFG_INT                     20                               /* Generate Interrupt */
-#define BITP_DMA_CFG_NDSIZE                  16                               /* Next Descriptor Set Size */
-#define BITP_DMA_CFG_TWAIT                   15                               /* Wait for Trigger */
-#define BITP_DMA_CFG_FLOW                    12                               /* Next Operation */
-#define BITP_DMA_CFG_MSIZE                    8                               /* Memory Transfer Word Size */
-#define BITP_DMA_CFG_PSIZE                    4                               /* Peripheral Transfer Word Size */
-#define BITP_DMA_CFG_CADDR                    3                               /* Use Current Address */
-#define BITP_DMA_CFG_SYNC                     2                               /* Synchronize Work Unit Transitions */
-#define BITP_DMA_CFG_WNR                      1                               /* Write/Read Channel Direction */
-#define BITP_DMA_CFG_EN                       0                               /* DMA Channel Enable */
-
-#define BITM_DMA_CFG_PDRF                    (_ADI_MSK(0x10000000,uint32_t))  /* Peripheral Data Request Forward */
-#define ENUM_DMA_CFG_PDAT_NOTFWD             (_ADI_MSK(0x00000000,uint32_t))  /* PDRF: Peripheral Data Request Not Forwarded */
-#define ENUM_DMA_CFG_PDAT_FWD                (_ADI_MSK(0x10000000,uint32_t))  /* PDRF: Peripheral Data Request Forwarded */
-
-#define BITM_DMA_CFG_TWOD                    (_ADI_MSK(0x04000000,uint32_t))  /* Two Dimension Addressing Enable */
-#define ENUM_DMA_CFG_ADDR1D                  (_ADI_MSK(0x00000000,uint32_t))  /* TWOD: One-Dimensional Addressing */
-#define ENUM_DMA_CFG_ADDR2D                  (_ADI_MSK(0x04000000,uint32_t))  /* TWOD: Two-Dimensional Addressing */
-
-#define BITM_DMA_CFG_DESCIDCPY               (_ADI_MSK(0x02000000,uint32_t))  /* Descriptor ID Copy Control */
-#define ENUM_DMA_CFG_NO_COPY                 (_ADI_MSK(0x00000000,uint32_t))  /* DESCIDCPY: Never Copy */
-#define ENUM_DMA_CFG_COPY                    (_ADI_MSK(0x02000000,uint32_t))  /* DESCIDCPY: Copy on Work Unit Complete */
-
-#define BITM_DMA_CFG_TOVEN                   (_ADI_MSK(0x01000000,uint32_t))  /* Trigger Overrun Error Enable */
-#define ENUM_DMA_CFG_TOV_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* TOVEN: Ignore Trigger Overrun */
-#define ENUM_DMA_CFG_TOV_EN                  (_ADI_MSK(0x01000000,uint32_t))  /* TOVEN: Error on Trigger Overrun */
-
-#define BITM_DMA_CFG_TRIG                    (_ADI_MSK(0x00C00000,uint32_t))  /* Generate Outgoing Trigger */
-#define ENUM_DMA_CFG_NO_TRIG                 (_ADI_MSK(0x00000000,uint32_t))  /* TRIG: Never assert Trigger */
-#define ENUM_DMA_CFG_XCNT_TRIG               (_ADI_MSK(0x00400000,uint32_t))  /* TRIG: Trigger when XCNTCUR reaches 0 */
-#define ENUM_DMA_CFG_YCNT_TRIG               (_ADI_MSK(0x00800000,uint32_t))  /* TRIG: Trigger when YCNTCUR reaches 0 */
-
-#define BITM_DMA_CFG_INT                     (_ADI_MSK(0x00300000,uint32_t))  /* Generate Interrupt */
-#define ENUM_DMA_CFG_NO_INT                  (_ADI_MSK(0x00000000,uint32_t))  /* INT: Never assert Interrupt */
-#define ENUM_DMA_CFG_XCNT_INT                (_ADI_MSK(0x00100000,uint32_t))  /* INT: Interrupt when X Count Expires */
-#define ENUM_DMA_CFG_YCNT_INT                (_ADI_MSK(0x00200000,uint32_t))  /* INT: Interrupt when Y Count Expires */
-#define ENUM_DMA_CFG_PERIPH_INT              (_ADI_MSK(0x00300000,uint32_t))  /* INT: Peripheral Interrupt */
-
-#define BITM_DMA_CFG_NDSIZE                  (_ADI_MSK(0x00070000,uint32_t))  /* Next Descriptor Set Size */
-#define ENUM_DMA_CFG_FETCH01                 (_ADI_MSK(0x00000000,uint32_t))  /* NDSIZE: Fetch one Descriptor Element */
-#define ENUM_DMA_CFG_FETCH02                 (_ADI_MSK(0x00010000,uint32_t))  /* NDSIZE: Fetch two Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH03                 (_ADI_MSK(0x00020000,uint32_t))  /* NDSIZE: Fetch three Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH04                 (_ADI_MSK(0x00030000,uint32_t))  /* NDSIZE: Fetch four Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH05                 (_ADI_MSK(0x00040000,uint32_t))  /* NDSIZE: Fetch five Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH06                 (_ADI_MSK(0x00050000,uint32_t))  /* NDSIZE: Fetch six Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH07                 (_ADI_MSK(0x00060000,uint32_t))  /* NDSIZE: Fetch seven Descriptor Elements */
-
-#define BITM_DMA_CFG_TWAIT                   (_ADI_MSK(0x00008000,uint32_t))  /* Wait for Trigger */
-#define ENUM_DMA_CFG_NO_TRGWAIT              (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: Begin Work Unit Automatically (No Wait) */
-#define ENUM_DMA_CFG_TRGWAIT                 (_ADI_MSK(0x00008000,uint32_t))  /* TWAIT: Wait for Trigger (Halt before Work Unit) */
-
-#define BITM_DMA_CFG_FLOW                    (_ADI_MSK(0x00007000,uint32_t))  /* Next Operation */
-#define ENUM_DMA_CFG_STOP                    (_ADI_MSK(0x00000000,uint32_t))  /* FLOW: STOP - Stop */
-#define ENUM_DMA_CFG_AUTO                    (_ADI_MSK(0x00001000,uint32_t))  /* FLOW: AUTO - Autobuffer */
-#define ENUM_DMA_CFG_DSCLIST                 (_ADI_MSK(0x00004000,uint32_t))  /* FLOW: DSCL - Descriptor List */
-#define ENUM_DMA_CFG_DSCARRAY                (_ADI_MSK(0x00005000,uint32_t))  /* FLOW: DSCA - Descriptor Array */
-#define ENUM_DMA_CFG_DODLIST                 (_ADI_MSK(0x00006000,uint32_t))  /* FLOW: Descriptor On Demand List */
-#define ENUM_DMA_CFG_DODARRAY                (_ADI_MSK(0x00007000,uint32_t))  /* FLOW: Descriptor On Demand Array */
-
-#define BITM_DMA_CFG_MSIZE                   (_ADI_MSK(0x00000700,uint32_t))  /* Memory Transfer Word Size */
-#define ENUM_DMA_CFG_MSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* MSIZE: 1 Byte */
-#define ENUM_DMA_CFG_MSIZE02                 (_ADI_MSK(0x00000100,uint32_t))  /* MSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_MSIZE04                 (_ADI_MSK(0x00000200,uint32_t))  /* MSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_MSIZE08                 (_ADI_MSK(0x00000300,uint32_t))  /* MSIZE: 8 Bytes */
-#define ENUM_DMA_CFG_MSIZE16                 (_ADI_MSK(0x00000400,uint32_t))  /* MSIZE: 16 Bytes */
-#define ENUM_DMA_CFG_MSIZE32                 (_ADI_MSK(0x00000500,uint32_t))  /* MSIZE: 32 Bytes */
-
-#define BITM_DMA_CFG_PSIZE                   (_ADI_MSK(0x00000070,uint32_t))  /* Peripheral Transfer Word Size */
-#define ENUM_DMA_CFG_PSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 Byte */
-#define ENUM_DMA_CFG_PSIZE02                 (_ADI_MSK(0x00000010,uint32_t))  /* PSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_PSIZE04                 (_ADI_MSK(0x00000020,uint32_t))  /* PSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_PSIZE08                 (_ADI_MSK(0x00000030,uint32_t))  /* PSIZE: 8 Bytes */
-
-#define BITM_DMA_CFG_CADDR                   (_ADI_MSK(0x00000008,uint32_t))  /* Use Current Address */
-#define ENUM_DMA_CFG_LD_STARTADDR            (_ADI_MSK(0x00000000,uint32_t))  /* CADDR: Load Starting Address */
-#define ENUM_DMA_CFG_LD_CURADDR              (_ADI_MSK(0x00000008,uint32_t))  /* CADDR: Use Current Address */
-
-#define BITM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* Synchronize Work Unit Transitions */
-#define ENUM_DMA_CFG_NO_SYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* SYNC: No Synchronization */
-#define ENUM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* SYNC: Synchronize  Channel */
-
-#define BITM_DMA_CFG_WNR                     (_ADI_MSK(0x00000002,uint32_t))  /* Write/Read Channel Direction */
-#define ENUM_DMA_CFG_READ                    (_ADI_MSK(0x00000000,uint32_t))  /* WNR: Transmit (Read from memory) */
-#define ENUM_DMA_CFG_WRITE                   (_ADI_MSK(0x00000002,uint32_t))  /* WNR: Receive (Write to memory) */
-
-#define BITM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* DMA Channel Enable */
-#define ENUM_DMA_CFG_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_DSCPTR_PRV                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_DSCPTR_PRV_DESCPPREV         2                               /* Pointer for Previous Descriptor Element */
-#define BITP_DMA_DSCPTR_PRV_PDPO              0                               /* Previous Descriptor Pointer Overrun */
-#define BITM_DMA_DSCPTR_PRV_DESCPPREV        (_ADI_MSK(0xFFFFFFFC,uint32_t))  /* Pointer for Previous Descriptor Element */
-#define BITM_DMA_DSCPTR_PRV_PDPO             (_ADI_MSK(0x00000001,uint32_t))  /* Previous Descriptor Pointer Overrun */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_STAT_TWAIT                  20                               /* Trigger Wait Status */
-#define BITP_DMA_STAT_FIFOFILL               16                               /* FIFO Fill Status */
-#define BITP_DMA_STAT_MBWID                  14                               /* Memory Bus Width */
-#define BITP_DMA_STAT_PBWID                  12                               /* Peripheral Bus Width */
-#define BITP_DMA_STAT_RUN                     8                               /* Run Status */
-#define BITP_DMA_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_DMA_STAT_PIRQ                    2                               /* Peripheral Interrupt Request */
-#define BITP_DMA_STAT_IRQERR                  1                               /* Error Interrupt */
-#define BITP_DMA_STAT_IRQDONE                 0                               /* Work Unit/Row Done Interrupt */
-
-#define BITM_DMA_STAT_TWAIT                  (_ADI_MSK(0x00100000,uint32_t))  /* Trigger Wait Status */
-#define ENUM_DMA_STAT_NOTRIGRX               (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: No trigger received */
-#define ENUM_DMA_STAT_TRIGRX                 (_ADI_MSK(0x00100000,uint32_t))  /* TWAIT: Trigger received */
-
-#define BITM_DMA_STAT_FIFOFILL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Fill Status */
-#define ENUM_DMA_STAT_FIFOEMPTY              (_ADI_MSK(0x00000000,uint32_t))  /* FIFOFILL: Empty */
-#define ENUM_DMA_STAT_FIFO25                 (_ADI_MSK(0x00010000,uint32_t))  /* FIFOFILL: Empty < FIFO = 1/4 Full */
-#define ENUM_DMA_STAT_FIFO50                 (_ADI_MSK(0x00020000,uint32_t))  /* FIFOFILL: 1/4 Full < FIFO = 1/2 Full */
-#define ENUM_DMA_STAT_FIFO75                 (_ADI_MSK(0x00030000,uint32_t))  /* FIFOFILL: 1/2 Full < FIFO = 3/4 Full */
-#define ENUM_DMA_STAT_FIFONEARFULL           (_ADI_MSK(0x00040000,uint32_t))  /* FIFOFILL: 3/4 Full < FIFO = Full */
-#define ENUM_DMA_STAT_FIFOFULL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFOFILL: Full */
-
-#define BITM_DMA_STAT_MBWID                  (_ADI_MSK(0x0000C000,uint32_t))  /* Memory Bus Width */
-#define ENUM_DMA_STAT_MBUS02                 (_ADI_MSK(0x00000000,uint32_t))  /* MBWID: 2 Bytes */
-#define ENUM_DMA_STAT_MBUS04                 (_ADI_MSK(0x00004000,uint32_t))  /* MBWID: 4 Bytes */
-#define ENUM_DMA_STAT_MBUS08                 (_ADI_MSK(0x00008000,uint32_t))  /* MBWID: 8 Bytes */
-#define ENUM_DMA_STAT_MBUS16                 (_ADI_MSK(0x0000C000,uint32_t))  /* MBWID: 16 Bytes */
-
-#define BITM_DMA_STAT_PBWID                  (_ADI_MSK(0x00003000,uint32_t))  /* Peripheral Bus Width */
-#define ENUM_DMA_STAT_PBUS01                 (_ADI_MSK(0x00000000,uint32_t))  /* PBWID: 1 Byte */
-#define ENUM_DMA_STAT_PBUS02                 (_ADI_MSK(0x00001000,uint32_t))  /* PBWID: 2 Bytes */
-#define ENUM_DMA_STAT_PBUS04                 (_ADI_MSK(0x00002000,uint32_t))  /* PBWID: 4 Bytes */
-#define ENUM_DMA_STAT_PBUS08                 (_ADI_MSK(0x00003000,uint32_t))  /* PBWID: 8 Bytes */
-
-#define BITM_DMA_STAT_RUN                    (_ADI_MSK(0x00000700,uint32_t))  /* Run Status */
-#define ENUM_DMA_STAT_STOPPED                (_ADI_MSK(0x00000000,uint32_t))  /* RUN: Idle/Stop State */
-#define ENUM_DMA_STAT_DSCFETCH               (_ADI_MSK(0x00000100,uint32_t))  /* RUN: Descriptor Fetch */
-#define ENUM_DMA_STAT_DATAXFER               (_ADI_MSK(0x00000200,uint32_t))  /* RUN: Data Transfer */
-#define ENUM_DMA_STAT_TRGWAIT                (_ADI_MSK(0x00000300,uint32_t))  /* RUN: Waiting for Trigger */
-#define ENUM_DMA_STAT_ACKWAIT                (_ADI_MSK(0x00000400,uint32_t))  /* RUN: Waiting for Write ACK/FIFO Drain to Peripheral */
-
-#define BITM_DMA_STAT_ERRC                   (_ADI_MSK(0x00000070,uint32_t))  /* Error Cause */
-#define ENUM_DMA_STAT_CFGERR                 (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Configuration Error */
-#define ENUM_DMA_STAT_ILLWRERR               (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Illegal Write Occurred While Channel Running */
-#define ENUM_DMA_STAT_ALGNERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: Address Alignment Error */
-#define ENUM_DMA_STAT_MEMERR                 (_ADI_MSK(0x00000030,uint32_t))  /* ERRC: Memory Access/Fabric Error */
-#define ENUM_DMA_STAT_TRGOVERR               (_ADI_MSK(0x00000050,uint32_t))  /* ERRC: Trigger Overrun */
-#define ENUM_DMA_STAT_BWMONERR               (_ADI_MSK(0x00000060,uint32_t))  /* ERRC: Bandwidth Monitor Error */
-
-#define BITM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* Peripheral Interrupt Request */
-#define ENUM_DMA_STAT_NO_PIRQ                (_ADI_MSK(0x00000000,uint32_t))  /* PIRQ: No Interrupt */
-#define ENUM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* PIRQ: Interrupt Signaled by Peripheral */
-
-#define BITM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Interrupt */
-#define ENUM_DMA_STAT_NO_IRQERR              (_ADI_MSK(0x00000000,uint32_t))  /* IRQERR: No Error */
-#define ENUM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* IRQERR: Error Occurred */
-
-#define BITM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* Work Unit/Row Done Interrupt */
-#define ENUM_DMA_STAT_NO_IRQ                 (_ADI_MSK(0x00000000,uint32_t))  /* IRQDONE: Inactive */
-#define ENUM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* IRQDONE: Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_VALUE                 0                               /* Bandwidth Limit Count */
-#define BITM_DMA_BWLCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT_CUR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_CUR_VALUE             0                               /* Bandwidth Limit Count Current */
-#define BITM_DMA_BWLCNT_CUR_VALUE            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count Current */
-
-/* ==================================================
-        ACM Registers
-   ================================================== */
-
-/* =========================
-        ACM0
-   ========================= */
-#define REG_ACM0_CTL                    0xFFC45000         /* ACM0 ACM Control Register */
-#define REG_ACM0_TC0                    0xFFC45004         /* ACM0 ACM Timing Configuration 0 Register */
-#define REG_ACM0_TC1                    0xFFC45008         /* ACM0 ACM Timing Configuration 1 Register */
-#define REG_ACM0_STAT                   0xFFC4500C         /* ACM0 ACM Status Register */
-#define REG_ACM0_EVSTAT                 0xFFC45010         /* ACM0 ACM Event Status Register */
-#define REG_ACM0_EVMSK                  0xFFC45014         /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define REG_ACM0_MEVSTAT                0xFFC45018         /* ACM0 ACM Missed Event Status Register */
-#define REG_ACM0_MEVMSK                 0xFFC4501C         /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define REG_ACM0_EVCTL0                 0xFFC45020         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL1                 0xFFC45024         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL2                 0xFFC45028         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL3                 0xFFC4502C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL4                 0xFFC45030         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL5                 0xFFC45034         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL6                 0xFFC45038         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL7                 0xFFC4503C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL8                 0xFFC45040         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL9                 0xFFC45044         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL10                0xFFC45048         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL11                0xFFC4504C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL12                0xFFC45050         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL13                0xFFC45054         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL14                0xFFC45058         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL15                0xFFC4505C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVTIME0                0xFFC45060         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME1                0xFFC45064         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME2                0xFFC45068         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME3                0xFFC4506C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME4                0xFFC45070         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME5                0xFFC45074         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME6                0xFFC45078         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME7                0xFFC4507C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME8                0xFFC45080         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME9                0xFFC45084         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME10               0xFFC45088         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME11               0xFFC4508C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME12               0xFFC45090         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME13               0xFFC45094         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME14               0xFFC45098         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME15               0xFFC4509C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVORD0                 0xFFC450A0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD1                 0xFFC450A4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD2                 0xFFC450A8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD3                 0xFFC450AC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD4                 0xFFC450B0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD5                 0xFFC450B4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD6                 0xFFC450B8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD7                 0xFFC450BC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD8                 0xFFC450C0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD9                 0xFFC450C4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD10                0xFFC450C8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD11                0xFFC450CC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD12                0xFFC450D0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD13                0xFFC450D4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD14                0xFFC450D8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD15                0xFFC450DC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_TMR0                   0xFFC450E8         /* ACM0 ACM Timer 0 Register */
-#define REG_ACM0_TMR1                   0xFFC450EC         /* ACM0 ACM Timer 1 Register */
-
-/* =========================
-        ACM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_CTL_EPS                     15                               /* External Peripheral Select */
-#define BITP_ACM_CTL_OTSEL                   14                               /* Trigger Select for Order Register Reset */
-#define BITP_ACM_CTL_AOREN                   13                               /* Automatic Order Reset Enable */
-#define BITP_ACM_CTL_ORST                    12                               /* Order Register Reset Bit */
-#define BITP_ACM_CTL_CLKMOD                  11                               /* ADC Clock Mode */
-#define BITP_ACM_CTL_CLKPOL                  10                               /* ADC_CLK Polarity */
-#define BITP_ACM_CTL_CSPOL                    9                               /* CS Polarity */
-#define BITP_ACM_CTL_TRGPOL1                  8                               /* Trigger Polarity for Timer1 Triggers */
-#define BITP_ACM_CTL_TRGPOL0                  7                               /* Trigger Polarity for Timer0 Triggers */
-#define BITP_ACM_CTL_TRGSEL1                  5                               /* Trigger Select 1 */
-#define BITP_ACM_CTL_TRGSEL0                  3                               /* Trigger Select 0 */
-#define BITP_ACM_CTL_TMR1EN                   2                               /* Enable ACM Timer1 */
-#define BITP_ACM_CTL_TMR0EN                   1                               /* Enable ACM Timer0 */
-#define BITP_ACM_CTL_EN                       0                               /* ACM Enable */
-#define BITM_ACM_CTL_EPS                     (_ADI_MSK(0x00008000,uint32_t))  /* External Peripheral Select */
-#define BITM_ACM_CTL_OTSEL                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Select for Order Register Reset */
-#define BITM_ACM_CTL_AOREN                   (_ADI_MSK(0x00002000,uint32_t))  /* Automatic Order Reset Enable */
-#define BITM_ACM_CTL_ORST                    (_ADI_MSK(0x00001000,uint32_t))  /* Order Register Reset Bit */
-#define BITM_ACM_CTL_CLKMOD                  (_ADI_MSK(0x00000800,uint32_t))  /* ADC Clock Mode */
-#define BITM_ACM_CTL_CLKPOL                  (_ADI_MSK(0x00000400,uint32_t))  /* ADC_CLK Polarity */
-#define BITM_ACM_CTL_CSPOL                   (_ADI_MSK(0x00000200,uint32_t))  /* CS Polarity */
-#define BITM_ACM_CTL_TRGPOL1                 (_ADI_MSK(0x00000100,uint32_t))  /* Trigger Polarity for Timer1 Triggers */
-#define BITM_ACM_CTL_TRGPOL0                 (_ADI_MSK(0x00000080,uint32_t))  /* Trigger Polarity for Timer0 Triggers */
-#define BITM_ACM_CTL_TRGSEL1                 (_ADI_MSK(0x00000060,uint32_t))  /* Trigger Select 1 */
-#define BITM_ACM_CTL_TRGSEL0                 (_ADI_MSK(0x00000018,uint32_t))  /* Trigger Select 0 */
-#define BITM_ACM_CTL_TMR1EN                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable ACM Timer1 */
-#define BITM_ACM_CTL_TMR0EN                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable ACM Timer0 */
-#define BITM_ACM_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* ACM Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC0_SC                      16                               /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITP_ACM_TC0_CKDIV                    0                               /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-#define BITM_ACM_TC0_SC                      (_ADI_MSK(0x0FFF0000,uint32_t))  /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITM_ACM_TC0_CKDIV                   (_ADI_MSK(0x000000FF,uint32_t))  /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC1_ZC                      12                               /* Zero Cycle - ADC Control zero duration */
-#define BITP_ACM_TC1_HC                       8                               /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITP_ACM_TC1_CSW                      0                               /* CS Width. Active duration of CS in ACLK cycles */
-#define BITM_ACM_TC1_ZC                      (_ADI_MSK(0x0000F000,uint32_t))  /* Zero Cycle - ADC Control zero duration */
-#define BITM_ACM_TC1_HC                      (_ADI_MSK(0x00000F00,uint32_t))  /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITM_ACM_TC1_CSW                     (_ADI_MSK(0x000000FF,uint32_t))  /* CS Width. Active duration of CS in ACLK cycles */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_STAT_CEVNT                   4                               /* Current Event. */
-#define BITP_ACM_STAT_ECOM1                   3                               /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_ECOM0                   2                               /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_EMISS                   1                               /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITP_ACM_STAT_BSY                     0                               /* ACM Busy */
-#define BITM_ACM_STAT_CEVNT                  (_ADI_MSK(0x000000F0,uint32_t))  /* Current Event. */
-#define BITM_ACM_STAT_ECOM1                  (_ADI_MSK(0x00000008,uint32_t))  /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_ECOM0                  (_ADI_MSK(0x00000004,uint32_t))  /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_EMISS                  (_ADI_MSK(0x00000002,uint32_t))  /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITM_ACM_STAT_BSY                    (_ADI_MSK(0x00000001,uint32_t))  /* ACM Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVSTAT_ECOM1S               17                               /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_ECOM0S               16                               /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_EV15                 15                               /* Event15 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV14                 14                               /* Event14 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV13                 13                               /* Event13 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV12                 12                               /* Event12 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV11                 11                               /* Event11 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV10                 10                               /* Event10 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV9                   9                               /* Event9 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV8                   8                               /* Event8 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV7                   7                               /* Event7 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV6                   6                               /* Event6 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV5                   5                               /* Event5 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV4                   4                               /* Event4 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV3                   3                               /* Event3 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV2                   2                               /* Event2 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV1                   1                               /* Event1 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV0                   0                               /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-#define BITM_ACM_EVSTAT_ECOM1S               (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_ECOM0S               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVMSK_IECOM1                17                               /* Timer1 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_IECOM0                16                               /* Timer0 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV15                  15                               /* Event15 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV14                  14                               /* Event14 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV13                  13                               /* Event13 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV12                  12                               /* Event12 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV11                  11                               /* Event11 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV10                  10                               /* Event10 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV9                    9                               /* Event9 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV8                    8                               /* Event8 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV7                    7                               /* Event7 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV6                    6                               /* Event6 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV5                    5                               /* Event5 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV4                    4                               /* Event4 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV3                    3                               /* Event3 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV2                    2                               /* Event2 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV1                    1                               /* Event1 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV0                    0                               /* Event0 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM1                (_ADI_MSK(0x00020000,uint32_t))  /* Timer1 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM0                (_ADI_MSK(0x00010000,uint32_t))  /* Timer0 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV15                  (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV14                  (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV13                  (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV12                  (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV11                  (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV10                  (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV9                   (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV8                   (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV7                   (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV6                   (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV5                   (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV4                   (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV3                   (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV2                   (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV1                   (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV0                   (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVSTAT_EV15                15                               /* Event15 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV14                14                               /* Event14 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV13                13                               /* Event13 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV12                12                               /* Event12 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV11                11                               /* Event11 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV10                10                               /* Event10 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV9                  9                               /* Event9 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV8                  8                               /* Event8 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV7                  7                               /* Event7 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV6                  6                               /* Event6 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV5                  5                               /* Event5 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV4                  4                               /* Event4 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV3                  3                               /* Event3 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV2                  2                               /* Event2 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV1                  1                               /* Event1 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV0                  0                               /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-#define BITM_ACM_MEVSTAT_EV15                (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV14                (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV13                (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV12                (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV11                (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV10                (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV9                 (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV8                 (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV7                 (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV6                 (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV5                 (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV4                 (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV3                 (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV2                 (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV1                 (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV0                 (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVMSK                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVMSK_EV15                 15                               /* Event15 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV14                 14                               /* Event14 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV13                 13                               /* Event13 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV12                 12                               /* Event12 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV11                 11                               /* Event11 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV10                 10                               /* Event10 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV9                   9                               /* Event9 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV8                   8                               /* Event8 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV7                   7                               /* Event7 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV6                   6                               /* Event6 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV5                   5                               /* Event5 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV4                   4                               /* Event4 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV3                   3                               /* Event3 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV2                   2                               /* Event2 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV1                   1                               /* Event1 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV0                   0                               /* Event0 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVCTL_EPF                    1                               /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITP_ACM_EVCTL_ENAEV                  0                               /* Enable Event */
-#define BITM_ACM_EVCTL_EPF                   (_ADI_MSK(0x0000003E,uint32_t))  /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITM_ACM_EVCTL_ENAEV                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Event */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVORD                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVORD_EVSTAT                17                               /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITP_ACM_EVORD_MEVSTAT               16                               /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITP_ACM_EVORD_ORD                    0                               /* Order of Event Completion */
-#define BITM_ACM_EVORD_EVSTAT                (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITM_ACM_EVORD_MEVSTAT               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITM_ACM_EVORD_ORD                   (_ADI_MSK(0x000000FF,uint32_t))  /* Order of Event Completion */
-
-/* ==================================================
-        DDR Registers
-   ================================================== */
-
-/* =========================
-        DMC0
-   ========================= */
-#define REG_DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
-#define REG_DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
-#define REG_DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Control Register */
-#define REG_DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
-#define REG_DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask Register */
-#define REG_DMC0_CFG                    0xFFC80040         /* DMC0 Configuration Register */
-#define REG_DMC0_TR0                    0xFFC80044         /* DMC0 Timing 0 Register */
-#define REG_DMC0_TR1                    0xFFC80048         /* DMC0 Timing 1 Register */
-#define REG_DMC0_TR2                    0xFFC8004C         /* DMC0 Timing 2 Register */
-#define REG_DMC0_MSK                    0xFFC8005C         /* DMC0 Mask (Mode Register Shadow) Register */
-#define REG_DMC0_MR                     0xFFC80060         /* DMC0 Shadow MR Register */
-#define REG_DMC0_EMR1                   0xFFC80064         /* DMC0 Shadow EMR1 Register */
-#define REG_DMC0_EMR2                   0xFFC80068         /* DMC0 Shadow EMR2 Register */
-#define REG_DMC0_EMR3                   0xFFC8006C         /* DMC0 Shadow EMR3 Register */
-#define REG_DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
-#define REG_DMC0_PHY_CTL0               0xFFC80090         /* DMC0 PHY Control 0 Register */
-#define REG_DMC0_PHY_CTL1               0xFFC80094         /* DMC0 PHY Control 1 Register */
-#define REG_DMC0_PHY_CTL2               0xFFC80098         /* DMC0 PHY Control 2 Register */
-#define REG_DMC0_PHY_CTL3               0xFFC8009C         /* DMC0 PHY Control 3 Register */
-#define REG_DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register */
-
-/* =========================
-        DMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CTL_DLLCAL                  13                               /* DLL Calibration Start */
-#define BITP_DMC_CTL_PPREF                   12                               /* Postpone Refresh */
-#define BITP_DMC_CTL_RDTOWR                   9                               /* Read-to-Write Cycle */
-#define BITP_DMC_CTL_ADDRMODE                 8                               /* Addressing (Page/Bank) Mode */
-#define BITP_DMC_CTL_PREC                     6                               /* Precharge */
-#define BITP_DMC_CTL_DPDREQ                   5                               /* Deep Power Down Request */
-#define BITP_DMC_CTL_PDREQ                    4                               /* Power Down Request */
-#define BITP_DMC_CTL_SRREQ                    3                               /* Self Refresh Request */
-#define BITP_DMC_CTL_INIT                     2                               /* Initialize DRAM Start */
-#define BITP_DMC_CTL_LPDDR                    1                               /* Low Power DDR Mode */
-#define BITM_DMC_CTL_DLLCAL                  (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Start */
-#define BITM_DMC_CTL_PPREF                   (_ADI_MSK(0x00001000,uint32_t))  /* Postpone Refresh */
-
-#define BITM_DMC_CTL_RDTOWR                  (_ADI_MSK(0x00000E00,uint32_t))  /* Read-to-Write Cycle */
-#define ENUM_DMC_CTL_RDTOWR0                 (_ADI_MSK(0x00000000,uint32_t))  /* RDTOWR: 0 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR1                 (_ADI_MSK(0x00000200,uint32_t))  /* RDTOWR: 1 Cycle Added */
-#define ENUM_DMC_CTL_RDTOWR2                 (_ADI_MSK(0x00000400,uint32_t))  /* RDTOWR: 2 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR3                 (_ADI_MSK(0x00000600,uint32_t))  /* RDTOWR: 3 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR4                 (_ADI_MSK(0x00000800,uint32_t))  /* RDTOWR: 4 Cycles Added */
-#define BITM_DMC_CTL_ADDRMODE                (_ADI_MSK(0x00000100,uint32_t))  /* Addressing (Page/Bank) Mode */
-#define BITM_DMC_CTL_PREC                    (_ADI_MSK(0x00000040,uint32_t))  /* Precharge */
-#define BITM_DMC_CTL_DPDREQ                  (_ADI_MSK(0x00000020,uint32_t))  /* Deep Power Down Request */
-#define BITM_DMC_CTL_PDREQ                   (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Request */
-#define BITM_DMC_CTL_SRREQ                   (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Request */
-#define BITM_DMC_CTL_INIT                    (_ADI_MSK(0x00000004,uint32_t))  /* Initialize DRAM Start */
-#define BITM_DMC_CTL_LPDDR                   (_ADI_MSK(0x00000002,uint32_t))  /* Low Power DDR Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_STAT_PHYRDPHASE             20                               /* PHY Read Phase */
-#define BITP_DMC_STAT_PENDREF                16                               /* Pending Refresh */
-#define BITP_DMC_STAT_DLLCALDONE             13                               /* DLL Calibration Done */
-#define BITP_DMC_STAT_DPDACK                  5                               /* Deep Powerdown Acknowledge */
-#define BITP_DMC_STAT_PDACK                   4                               /* Power Down Acknowledge */
-#define BITP_DMC_STAT_SRACK                   3                               /* Self Refresh Acknowledge */
-#define BITP_DMC_STAT_MEMINITDONE             1                               /* Memory Initialization Done */
-#define BITP_DMC_STAT_IDLE                    0                               /* Idle State */
-#define BITM_DMC_STAT_PHYRDPHASE             (_ADI_MSK(0x00F00000,uint32_t))  /* PHY Read Phase */
-#define BITM_DMC_STAT_PENDREF                (_ADI_MSK(0x000F0000,uint32_t))  /* Pending Refresh */
-#define BITM_DMC_STAT_DLLCALDONE             (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Done */
-#define BITM_DMC_STAT_DPDACK                 (_ADI_MSK(0x00000020,uint32_t))  /* Deep Powerdown Acknowledge */
-#define BITM_DMC_STAT_PDACK                  (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Acknowledge */
-#define BITM_DMC_STAT_SRACK                  (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Acknowledge */
-#define BITM_DMC_STAT_MEMINITDONE            (_ADI_MSK(0x00000002,uint32_t))  /* Memory Initialization Done */
-#define BITM_DMC_STAT_IDLE                   (_ADI_MSK(0x00000001,uint32_t))  /* Idle State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EFFCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EFFCTL_IDLECYC              20                               /* Idle Cycle */
-#define BITP_DMC_EFFCTL_NUMREF               16                               /* Number of Refresh Commands */
-#define BITP_DMC_EFFCTL_PRECBANK7            15                               /* Precharge Bank 7 */
-#define BITP_DMC_EFFCTL_PRECBANK6            14                               /* Precharge Bank 6 */
-#define BITP_DMC_EFFCTL_PRECBANK5            13                               /* Precharge Bank 5 */
-#define BITP_DMC_EFFCTL_PRECBANK4            12                               /* Precharge Bank 4 */
-#define BITP_DMC_EFFCTL_PRECBANK3            11                               /* Precharge Bank 3 */
-#define BITP_DMC_EFFCTL_PRECBANK2            10                               /* Precharge Bank 2 */
-#define BITP_DMC_EFFCTL_PRECBANK1             9                               /* Precharge Bank 1 */
-#define BITP_DMC_EFFCTL_PRECBANK0             8                               /* Precharge Bank 0 */
-#define BITP_DMC_EFFCTL_WAITWRDATA            7                               /* Wait in Write Data Snapshot */
-#define BITP_DMC_EFFCTL_FULLWRDATA            6                               /* Wait for Full Write Data */
-#define BITM_DMC_EFFCTL_IDLECYC              (_ADI_MSK(0x00F00000,uint32_t))  /* Idle Cycle */
-#define BITM_DMC_EFFCTL_NUMREF               (_ADI_MSK(0x000F0000,uint32_t))  /* Number of Refresh Commands */
-#define BITM_DMC_EFFCTL_PRECBANK7            (_ADI_MSK(0x00008000,uint32_t))  /* Precharge Bank 7 */
-#define BITM_DMC_EFFCTL_PRECBANK6            (_ADI_MSK(0x00004000,uint32_t))  /* Precharge Bank 6 */
-#define BITM_DMC_EFFCTL_PRECBANK5            (_ADI_MSK(0x00002000,uint32_t))  /* Precharge Bank 5 */
-#define BITM_DMC_EFFCTL_PRECBANK4            (_ADI_MSK(0x00001000,uint32_t))  /* Precharge Bank 4 */
-#define BITM_DMC_EFFCTL_PRECBANK3            (_ADI_MSK(0x00000800,uint32_t))  /* Precharge Bank 3 */
-#define BITM_DMC_EFFCTL_PRECBANK2            (_ADI_MSK(0x00000400,uint32_t))  /* Precharge Bank 2 */
-#define BITM_DMC_EFFCTL_PRECBANK1            (_ADI_MSK(0x00000200,uint32_t))  /* Precharge Bank 1 */
-#define BITM_DMC_EFFCTL_PRECBANK0            (_ADI_MSK(0x00000100,uint32_t))  /* Precharge Bank 0 */
-#define BITM_DMC_EFFCTL_WAITWRDATA           (_ADI_MSK(0x00000080,uint32_t))  /* Wait in Write Data Snapshot */
-#define BITM_DMC_EFFCTL_FULLWRDATA           (_ADI_MSK(0x00000040,uint32_t))  /* Wait for Full Write Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIO                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIO_ID2                    16                               /* ID2 Requiring Elevated Priority */
-#define BITP_DMC_PRIO_ID1                     0                               /* ID1 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID2                    (_ADI_MSK(0xFFFF0000,uint32_t))  /* ID2 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID1                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* ID1 Requiring Elevated Priority */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIOMSK                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIOMSK_ID2MSK              16                               /* Mask for ID2 */
-#define BITP_DMC_PRIOMSK_ID1MSK               0                               /* Mask for ID1 */
-#define BITM_DMC_PRIOMSK_ID2MSK              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Mask for ID2 */
-#define BITM_DMC_PRIOMSK_ID1MSK              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Mask for ID1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CFG_EXTBANK                 12                               /* External Banks */
-#define BITP_DMC_CFG_SDRSIZE                  8                               /* SDRAM Size */
-#define BITP_DMC_CFG_SDRWID                   4                               /* SDRAM Width */
-#define BITP_DMC_CFG_IFWID                    0                               /* Interface Width */
-
-#define BITM_DMC_CFG_EXTBANK                 (_ADI_MSK(0x0000F000,uint32_t))  /* External Banks */
-#define ENUM_DMC_CFG_EXTBANK1                (_ADI_MSK(0x00000000,uint32_t))  /* EXTBANK: 1 External Bank */
-
-#define BITM_DMC_CFG_SDRSIZE                 (_ADI_MSK(0x00000F00,uint32_t))  /* SDRAM Size */
-#define ENUM_DMC_CFG_SDRSIZE64               (_ADI_MSK(0x00000000,uint32_t))  /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE128              (_ADI_MSK(0x00000100,uint32_t))  /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE256              (_ADI_MSK(0x00000200,uint32_t))  /* SDRSIZE: 256M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE512              (_ADI_MSK(0x00000300,uint32_t))  /* SDRSIZE: 512M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE1G               (_ADI_MSK(0x00000400,uint32_t))  /* SDRSIZE: 1G Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE2G               (_ADI_MSK(0x00000500,uint32_t))  /* SDRSIZE: 2G Bit SDRAM */
-
-#define BITM_DMC_CFG_SDRWID                  (_ADI_MSK(0x000000F0,uint32_t))  /* SDRAM Width */
-#define ENUM_DMC_CFG_SDRWID16                (_ADI_MSK(0x00000020,uint32_t))  /* SDRWID: 16-Bit Wide SDRAM */
-
-#define BITM_DMC_CFG_IFWID                   (_ADI_MSK(0x0000000F,uint32_t))  /* Interface Width */
-#define ENUM_DMC_CFG_IFWID16                 (_ADI_MSK(0x00000002,uint32_t))  /* IFWID: 16-Bit Wide Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR0_TMRD                    28                               /* Timing Mode Register Delay */
-#define BITP_DMC_TR0_TRC                     20                               /* Timing Row Cycle */
-#define BITP_DMC_TR0_TRAS                    12                               /* Timing Row Active Time */
-#define BITP_DMC_TR0_TRP                      8                               /* Timing RAS Precharge. */
-#define BITP_DMC_TR0_TWTR                     4                               /* Timing Write to Read */
-#define BITP_DMC_TR0_TRCD                     0                               /* Timing RAS to CAS Delay */
-#define BITM_DMC_TR0_TMRD                    (_ADI_MSK(0xF0000000,uint32_t))  /* Timing Mode Register Delay */
-#define BITM_DMC_TR0_TRC                     (_ADI_MSK(0x03F00000,uint32_t))  /* Timing Row Cycle */
-#define BITM_DMC_TR0_TRAS                    (_ADI_MSK(0x0001F000,uint32_t))  /* Timing Row Active Time */
-#define BITM_DMC_TR0_TRP                     (_ADI_MSK(0x00000F00,uint32_t))  /* Timing RAS Precharge. */
-#define BITM_DMC_TR0_TWTR                    (_ADI_MSK(0x000000F0,uint32_t))  /* Timing Write to Read */
-#define BITM_DMC_TR0_TRCD                    (_ADI_MSK(0x0000000F,uint32_t))  /* Timing RAS to CAS Delay */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR1_TRRD                    28                               /* Timing Read-Read Delay */
-#define BITP_DMC_TR1_TRFC                    16                               /* Timing Refresh-to-Command */
-#define BITP_DMC_TR1_TREF                     0                               /* Timing Refresh Interval */
-#define BITM_DMC_TR1_TRRD                    (_ADI_MSK(0x70000000,uint32_t))  /* Timing Read-Read Delay */
-#define BITM_DMC_TR1_TRFC                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Timing Refresh-to-Command */
-#define BITM_DMC_TR1_TREF                    (_ADI_MSK(0x00003FFF,uint32_t))  /* Timing Refresh Interval */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR2_TCKE                    20                               /* Timing Clock Enable */
-#define BITP_DMC_TR2_TXP                     16                               /* Timing Exit Powerdown */
-#define BITP_DMC_TR2_TWR                     12                               /* Timing Write Recovery */
-#define BITP_DMC_TR2_TRTP                     8                               /* Timing Read-to-Precharge */
-#define BITP_DMC_TR2_TFAW                     0                               /* Timing Four-Activated-Window */
-#define BITM_DMC_TR2_TCKE                    (_ADI_MSK(0x00F00000,uint32_t))  /* Timing Clock Enable */
-#define BITM_DMC_TR2_TXP                     (_ADI_MSK(0x000F0000,uint32_t))  /* Timing Exit Powerdown */
-#define BITM_DMC_TR2_TWR                     (_ADI_MSK(0x0000F000,uint32_t))  /* Timing Write Recovery */
-#define BITM_DMC_TR2_TRTP                    (_ADI_MSK(0x00000F00,uint32_t))  /* Timing Read-to-Precharge */
-#define BITM_DMC_TR2_TFAW                    (_ADI_MSK(0x0000001F,uint32_t))  /* Timing Four-Activated-Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MSK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MSK_EMR3                    11                               /* Shadow EMR3 Unmask */
-#define BITP_DMC_MSK_EMR2                    10                               /* Shadow EMR2 Unmask */
-#define BITP_DMC_MSK_EMR1                     9                               /* Shadow EMR1 Unmask */
-#define BITP_DMC_MSK_MR                       8                               /* Shadow MR Unmask */
-#define BITM_DMC_MSK_EMR3                    (_ADI_MSK(0x00000800,uint32_t))  /* Shadow EMR3 Unmask */
-#define BITM_DMC_MSK_EMR2                    (_ADI_MSK(0x00000400,uint32_t))  /* Shadow EMR2 Unmask */
-#define BITM_DMC_MSK_EMR1                    (_ADI_MSK(0x00000200,uint32_t))  /* Shadow EMR1 Unmask */
-#define BITM_DMC_MSK_MR                      (_ADI_MSK(0x00000100,uint32_t))  /* Shadow MR Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MR                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MR_PD                       12                               /* Active Powerdown Mode */
-#define BITP_DMC_MR_WRRECOV                   9                               /* Write Recovery */
-#define BITP_DMC_MR_DLLRST                    8                               /* DLL Reset */
-#define BITP_DMC_MR_CL                        4                               /* CAS Latency */
-#define BITP_DMC_MR_BLEN                      0                               /* Burst Length */
-#define BITM_DMC_MR_PD                       (_ADI_MSK(0x00001000,uint32_t))  /* Active Powerdown Mode */
-#define BITM_DMC_MR_WRRECOV                  (_ADI_MSK(0x00000E00,uint32_t))  /* Write Recovery */
-#define BITM_DMC_MR_DLLRST                   (_ADI_MSK(0x00000100,uint32_t))  /* DLL Reset */
-
-#define BITM_DMC_MR_CL                       (_ADI_MSK(0x00000070,uint32_t))  /* CAS Latency */
-#define ENUM_DMC_MR_CL2                      (_ADI_MSK(0x00000020,uint32_t))  /* CL: 2 clock cycle latency */
-#define ENUM_DMC_MR_CL3                      (_ADI_MSK(0x00000030,uint32_t))  /* CL: 3 clock cycle latency */
-#define ENUM_DMC_MR_CL4                      (_ADI_MSK(0x00000040,uint32_t))  /* CL: 4 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL5                      (_ADI_MSK(0x00000050,uint32_t))  /* CL: 5 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL6                      (_ADI_MSK(0x00000060,uint32_t))  /* CL: 6 clock cycle latency (DDR2) */
-
-#define BITM_DMC_MR_BLEN                     (_ADI_MSK(0x00000007,uint32_t))  /* Burst Length */
-#define ENUM_DMC_MR_BLEN4                    (_ADI_MSK(0x00000002,uint32_t))  /* BLEN: 4-Bit Burst Length */
-#define ENUM_DMC_MR_BLEN8                    (_ADI_MSK(0x00000003,uint32_t))  /* BLEN: 8-Bit Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR1_QOFF                   12                               /* Output Buffer Enable */
-#define BITP_DMC_EMR1_DQS                    10                               /* DQS Enable */
-#define BITP_DMC_EMR1_RTT1                    6                               /* Termination Resistance 1 */
-#define BITP_DMC_EMR1_AL                      3                               /* Additive Latency */
-#define BITP_DMC_EMR1_RTT0                    2                               /* Termination Resistance 0. */
-#define BITP_DMC_EMR1_DIC                     1                               /* Output Driver Impedance Control */
-#define BITP_DMC_EMR1_DLLEN                   0                               /* DLL Enable */
-#define BITM_DMC_EMR1_QOFF                   (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Enable */
-#define BITM_DMC_EMR1_DQS                    (_ADI_MSK(0x00000400,uint32_t))  /* DQS Enable */
-
-#define BITM_DMC_EMR1_RTT1                   (_ADI_MSK(0x00000040,uint32_t))  /* Termination Resistance 1 */
-#define ENUM_DMC_EMR1_RTT1_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT1: Disable RTT1 */
-#define ENUM_DMC_EMR1_RTT1_1                 (_ADI_MSK(0x00000040,uint32_t))  /* RTT1: Enable RTT1 */
-#define BITM_DMC_EMR1_AL                     (_ADI_MSK(0x00000038,uint32_t))  /* Additive Latency */
-
-#define BITM_DMC_EMR1_RTT0                   (_ADI_MSK(0x00000004,uint32_t))  /* Termination Resistance 0. */
-#define ENUM_DMC_EMR1_RTT0_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT0: Disable RTT0 */
-#define ENUM_DMC_EMR1_RTT0_1                 (_ADI_MSK(0x00000004,uint32_t))  /* RTT0: Enable RTT0 */
-#define BITM_DMC_EMR1_DIC                    (_ADI_MSK(0x00000002,uint32_t))  /* Output Driver Impedance Control */
-#define BITM_DMC_EMR1_DLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* DLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR2_SRF                     7                               /* High Temp. Self Refresh */
-#define BITP_DMC_EMR2_DS                      5                               /* Drive Strength */
-#define BITP_DMC_EMR2_TCSR                    3                               /* Temp. Comp. Self Refresh */
-#define BITP_DMC_EMR2_PASR                    0                               /* Partial Array Self Refresh */
-#define BITM_DMC_EMR2_SRF                    (_ADI_MSK(0x00000080,uint32_t))  /* High Temp. Self Refresh */
-#define BITM_DMC_EMR2_DS                     (_ADI_MSK(0x00000060,uint32_t))  /* Drive Strength */
-#define BITM_DMC_EMR2_TCSR                   (_ADI_MSK(0x00000018,uint32_t))  /* Temp. Comp. Self Refresh */
-#define BITM_DMC_EMR2_PASR                   (_ADI_MSK(0x00000007,uint32_t))  /* Partial Array Self Refresh */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_DLLCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_DLLCTL_DATACYC               8                               /* Data Cycles */
-#define BITP_DMC_DLLCTL_DLLCALRDCNT           0                               /* DLL Calibration RD Count */
-
-#define BITM_DMC_DLLCTL_DATACYC              (_ADI_MSK(0x00000F00,uint32_t))  /* Data Cycles */
-#define ENUM_DMC_DLLCTL_DATACYC2             (_ADI_MSK(0x00000200,uint32_t))  /* DATACYC: 2 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC3             (_ADI_MSK(0x00000300,uint32_t))  /* DATACYC: 3 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC4             (_ADI_MSK(0x00000400,uint32_t))  /* DATACYC: 4 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC5             (_ADI_MSK(0x00000500,uint32_t))  /* DATACYC: 5 Clock Cycles Latency */
-#define BITM_DMC_DLLCTL_DLLCALRDCNT          (_ADI_MSK(0x000000FF,uint32_t))  /* DLL Calibration RD Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL1                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL1_CONTODTVAL         19                               /* Select ODT value on controller */
-
-#define BITM_DMC_PHY_CTL1_CONTODTVAL         (_ADI_MSK(0x00080000,uint32_t))  /* Select ODT value on controller */
-#define ENUM_DMC_PHY_CTL1_ODT_75             (_ADI_MSK(0x00000000,uint32_t))  /* CONTODTVAL: 75 Ohms Termination */
-#define ENUM_DMC_PHY_CTL1_ODT_150            (_ADI_MSK(0x00080000,uint32_t))  /* CONTODTVAL: 150 Ohms Termination */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL3                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL3_OFST1              26                               /* Offset Parameter 1 */
-#define BITP_DMC_PHY_CTL3_OFST0              24                               /* Offset Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQS           10                               /* Enables controller ODT on read of DQS */
-#define BITP_DMC_PHY_CTL3_TMG1                7                               /* Timing Parameter 1 */
-#define BITP_DMC_PHY_CTL3_TMG0                6                               /* Timing Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQ             2                               /* Enables controller ODT on read of DQ */
-#define BITM_DMC_PHY_CTL3_OFST1              (_ADI_MSK(0x04000000,uint32_t))  /* Offset Parameter 1 */
-#define BITM_DMC_PHY_CTL3_OFST0              (_ADI_MSK(0x01000000,uint32_t))  /* Offset Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQS           (_ADI_MSK(0x00000400,uint32_t))  /* Enables controller ODT on read of DQS */
-#define BITM_DMC_PHY_CTL3_TMG1               (_ADI_MSK(0x00000080,uint32_t))  /* Timing Parameter 1 */
-#define BITM_DMC_PHY_CTL3_TMG0               (_ADI_MSK(0x00000040,uint32_t))  /* Timing Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQ            (_ADI_MSK(0x00000004,uint32_t))  /* Enables controller ODT on read of DQ */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PADCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PADCTL_CKEOE                19                               /* CKE Output Enable */
-#define BITP_DMC_PADCTL_CKEPWD               18                               /* CKE pad receiver power down. */
-#define BITP_DMC_PADCTL_CKEODS               16                               /* CKE Output Drive Strength */
-#define BITP_DMC_PADCTL_CMDOE                15                               /* CMD Output Enable */
-#define BITP_DMC_PADCTL_CMDPWD               14                               /* CMD Powerdown */
-#define BITP_DMC_PADCTL_CMDODS               12                               /* CMD Output Drive Strength */
-#define BITP_DMC_PADCTL_CLKOE                11                               /* CLK Output Enable */
-#define BITP_DMC_PADCTL_CLKPWD               10                               /* CLK Powerdown */
-#define BITP_DMC_PADCTL_CLKODS                8                               /* Clock Output Drive Strength */
-#define BITP_DMC_PADCTL_DQSPWD                6                               /* DQ/DQS Powerdown */
-#define BITP_DMC_PADCTL_DQSODS                4                               /* DQS Output Drive Strength */
-#define BITP_DMC_PADCTL_DQPWD                 2                               /* DQ Powerdown. */
-#define BITP_DMC_PADCTL_DQODS                 0                               /* DQ Output Drive Strength */
-#define BITM_DMC_PADCTL_CKEOE                (_ADI_MSK(0x00080000,uint32_t))  /* CKE Output Enable */
-#define BITM_DMC_PADCTL_CKEPWD               (_ADI_MSK(0x00040000,uint32_t))  /* CKE pad receiver power down. */
-#define BITM_DMC_PADCTL_CKEODS               (_ADI_MSK(0x00030000,uint32_t))  /* CKE Output Drive Strength */
-#define BITM_DMC_PADCTL_CMDOE                (_ADI_MSK(0x00008000,uint32_t))  /* CMD Output Enable */
-#define BITM_DMC_PADCTL_CMDPWD               (_ADI_MSK(0x00004000,uint32_t))  /* CMD Powerdown */
-#define BITM_DMC_PADCTL_CMDODS               (_ADI_MSK(0x00003000,uint32_t))  /* CMD Output Drive Strength */
-#define BITM_DMC_PADCTL_CLKOE                (_ADI_MSK(0x00000800,uint32_t))  /* CLK Output Enable */
-#define BITM_DMC_PADCTL_CLKPWD               (_ADI_MSK(0x00000400,uint32_t))  /* CLK Powerdown */
-#define BITM_DMC_PADCTL_CLKODS               (_ADI_MSK(0x00000300,uint32_t))  /* Clock Output Drive Strength */
-#define BITM_DMC_PADCTL_DQSPWD               (_ADI_MSK(0x00000040,uint32_t))  /* DQ/DQS Powerdown */
-#define BITM_DMC_PADCTL_DQSODS               (_ADI_MSK(0x00000030,uint32_t))  /* DQS Output Drive Strength */
-#define BITM_DMC_PADCTL_DQPWD                (_ADI_MSK(0x00000004,uint32_t))  /* DQ Powerdown. */
-#define BITM_DMC_PADCTL_DQODS                (_ADI_MSK(0x00000003,uint32_t))  /* DQ Output Drive Strength */
-
-/* ==================================================
-        System Cross Bar Registers
-   ================================================== */
-
-/* =========================
-        SCB0
-   ========================= */
-#define REG_SCB0_ARBR0                  0xFFCA2408         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR1                  0xFFCA2428         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR2                  0xFFCA2448         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR3                  0xFFCA2468         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR4                  0xFFCA2488         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR5                  0xFFCA24A8         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBW0                  0xFFCA240C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW1                  0xFFCA242C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW2                  0xFFCA244C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW3                  0xFFCA246C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW4                  0xFFCA248C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW5                  0xFFCA24AC         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_SLAVES                 0xFFCA2FC0         /* SCB0 Slave Interfaces Number Register */
-#define REG_SCB0_MASTERS                0xFFCA2FC4         /* SCB0 Master Interfaces Number Register */
-
-/* =========================
-        SCB1
-   ========================= */
-#define REG_SCB1_ARBR0                  0xFFC42408         /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB1_ARBW0                  0xFFC4240C         /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB1_SLAVES                 0xFFC42FC0         /* SCB1 Slave Interfaces Number Register */
-#define REG_SCB1_MASTERS                0xFFC42FC4         /* SCB1 Master Interfaces Number Register */
-
-/* =========================
-        SCB2
-   ========================= */
-#define REG_SCB2_ARBR0                  0xFFC06408         /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB2_ARBW0                  0xFFC0640C         /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB2_SLAVES                 0xFFC06FC0         /* SCB2 Slave Interfaces Number Register */
-#define REG_SCB2_MASTERS                0xFFC06FC4         /* SCB2 Master Interfaces Number Register */
-
-/* =========================
-        SCB3
-   ========================= */
-#define REG_SCB3_ARBR0                  0xFFC08408         /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB3_ARBW0                  0xFFC0840C         /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB3_SLAVES                 0xFFC08FC0         /* SCB3 Slave Interfaces Number Register */
-#define REG_SCB3_MASTERS                0xFFC08FC4         /* SCB3 Master Interfaces Number Register */
-
-/* =========================
-        SCB4
-   ========================= */
-#define REG_SCB4_ARBR0                  0xFFC0A408         /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB4_ARBW0                  0xFFC0A40C         /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB4_SLAVES                 0xFFC0AFC0         /* SCB4 Slave Interfaces Number Register */
-#define REG_SCB4_MASTERS                0xFFC0AFC4         /* SCB4 Master Interfaces Number Register */
-
-/* =========================
-        SCB5
-   ========================= */
-#define REG_SCB5_ARBR0                  0xFFC0C408         /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB5_ARBW0                  0xFFC0C40C         /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB5_SLAVES                 0xFFC0CFC0         /* SCB5 Slave Interfaces Number Register */
-#define REG_SCB5_MASTERS                0xFFC0CFC4         /* SCB5 Master Interfaces Number Register */
-
-/* =========================
-        SCB6
-   ========================= */
-#define REG_SCB6_ARBR0                  0xFFC0E408         /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB6_ARBW0                  0xFFC0E40C         /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB6_SLAVES                 0xFFC0EFC0         /* SCB6 Slave Interfaces Number Register */
-#define REG_SCB6_MASTERS                0xFFC0EFC4         /* SCB6 Master Interfaces Number Register */
-
-/* =========================
-        SCB7
-   ========================= */
-#define REG_SCB7_ARBR0                  0xFFC11408         /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB7_ARBW0                  0xFFC1140C         /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB7_SLAVES                 0xFFC11FC0         /* SCB7 Slave Interfaces Number Register */
-#define REG_SCB7_MASTERS                0xFFC11FC4         /* SCB7 Master Interfaces Number Register */
-
-/* =========================
-        SCB8
-   ========================= */
-#define REG_SCB8_ARBR0                  0xFFC13408         /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB8_ARBW0                  0xFFC1340C         /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB8_SLAVES                 0xFFC13FC0         /* SCB8 Slave Interfaces Number Register */
-#define REG_SCB8_MASTERS                0xFFC13FC4         /* SCB8 Master Interfaces Number Register */
-
-/* =========================
-        SCB9
-   ========================= */
-#define REG_SCB9_ARBR0                  0xFFC15408         /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB9_ARBW0                  0xFFC1540C         /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB9_SLAVES                 0xFFC15FC0         /* SCB9 Slave Interfaces Number Register */
-#define REG_SCB9_MASTERS                0xFFC15FC4         /* SCB9 Master Interfaces Number Register */
-
-/* =========================
-        SCB10
-   ========================= */
-#define REG_SCB10_ARBR0                 0xFFCA1408         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR1                 0xFFCA1428         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR2                 0xFFCA1448         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBW0                 0xFFCA140C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW1                 0xFFCA142C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW2                 0xFFCA144C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_SLAVES                0xFFCA1FC0         /* SCB10 Slave Interfaces Number Register */
-#define REG_SCB10_MASTERS               0xFFCA1FC4         /* SCB10 Master Interfaces Number Register */
-
-/* =========================
-        SCB11
-   ========================= */
-#define REG_SCB11_ARBR0                 0xFFCA0408         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR1                 0xFFCA0428         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR2                 0xFFCA0448         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR3                 0xFFCA0468         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR4                 0xFFCA0488         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR5                 0xFFCA04A8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR6                 0xFFCA04C8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBW0                 0xFFCA040C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW1                 0xFFCA042C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW2                 0xFFCA044C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW3                 0xFFCA046C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW4                 0xFFCA048C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW5                 0xFFCA04AC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW6                 0xFFCA04CC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_SLAVES                0xFFCA0FC0         /* SCB11 Slave Interfaces Number Register */
-#define REG_SCB11_MASTERS               0xFFCA0FC4         /* SCB11 Master Interfaces Number Register */
-
-/* =========================
-        SCB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBR_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBR_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBR_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBR_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBW                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBW_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBW_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBW_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBW_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_SLAVES                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_SLAVES_SI                    0                               /* Slave Interface Value */
-#define BITM_SCB_SLAVES_SI                   (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_MASTERS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_MASTERS_MI                   0                               /* Master Interface Value */
-#define BITM_SCB_MASTERS_MI                  (_ADI_MSK(0x000000FF,uint32_t))  /* Master Interface Value */
-
-/* ==================================================
-        L2 Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        L2CTL0
-   ========================= */
-#define REG_L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 Control Register */
-#define REG_L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 Access Control Core 0 Register */
-#define REG_L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 Access Control Core 1 Register */
-#define REG_L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 Access Control System Register */
-#define REG_L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 Status Register */
-#define REG_L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 Read Priority Count Register */
-#define REG_L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 Write Priority Count Register */
-#define REG_L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 Refresh Address Register */
-#define REG_L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 ECC Error Address 0 Register */
-#define REG_L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 ECC Error Address 1 Register */
-#define REG_L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 ECC Error Address 2 Register */
-#define REG_L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 ECC Error Address 3 Register */
-#define REG_L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 ECC Error Address 4 Register */
-#define REG_L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 ECC Error Address 5 Register */
-#define REG_L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 ECC Error Address 6 Register */
-#define REG_L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 ECC Error Address 7 Register */
-#define REG_L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 Error Type 0 Register */
-#define REG_L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 Error Type 0 Address Register */
-#define REG_L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 Error Type 1 Register */
-#define REG_L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 Error Type 1 Address Register */
-
-/* =========================
-        L2CTL
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_CTL_LOCK                  31                               /* Lock */
-#define BITP_L2CTL_CTL_DISURP                16                               /* Disable Urgent Request Priority */
-#define BITP_L2CTL_CTL_ECCMAP7               15                               /* ECC Map Bank 7 */
-#define BITP_L2CTL_CTL_ECCMAP6               14                               /* ECC Map Bank 6 */
-#define BITP_L2CTL_CTL_ECCMAP5               13                               /* ECC Map Bank 5 */
-#define BITP_L2CTL_CTL_ECCMAP4               12                               /* ECC Map Bank 4 */
-#define BITP_L2CTL_CTL_ECCMAP3               11                               /* ECC Map Bank 3 */
-#define BITP_L2CTL_CTL_ECCMAP2               10                               /* ECC Map Bank 2 */
-#define BITP_L2CTL_CTL_ECCMAP1                9                               /* ECC Map Bank 1 */
-#define BITP_L2CTL_CTL_ECCMAP0                8                               /* ECC Map Bank 0 */
-#define BITP_L2CTL_CTL_BK7EDIS                7                               /* Bank 7 ECC Disable */
-#define BITP_L2CTL_CTL_BK6EDIS                6                               /* Bank 6 ECC Disable */
-#define BITP_L2CTL_CTL_BK5EDIS                5                               /* Bank 5 ECC Disable */
-#define BITP_L2CTL_CTL_BK4EDIS                4                               /* Bank 4 ECC Disable */
-#define BITP_L2CTL_CTL_BK3EDIS                3                               /* Bank 3 ECC Disable */
-#define BITP_L2CTL_CTL_BK2EDIS                2                               /* Bank 2 ECC Disable */
-#define BITP_L2CTL_CTL_BK1EDIS                1                               /* Bank 1 ECC Disable */
-#define BITP_L2CTL_CTL_BK0EDIS                0                               /* Bank 0 ECC Disable */
-#define BITM_L2CTL_CTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_CTL_DISURP                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Urgent Request Priority */
-#define BITM_L2CTL_CTL_ECCMAP7               (_ADI_MSK(0x00008000,uint32_t))  /* ECC Map Bank 7 */
-#define BITM_L2CTL_CTL_ECCMAP6               (_ADI_MSK(0x00004000,uint32_t))  /* ECC Map Bank 6 */
-#define BITM_L2CTL_CTL_ECCMAP5               (_ADI_MSK(0x00002000,uint32_t))  /* ECC Map Bank 5 */
-#define BITM_L2CTL_CTL_ECCMAP4               (_ADI_MSK(0x00001000,uint32_t))  /* ECC Map Bank 4 */
-#define BITM_L2CTL_CTL_ECCMAP3               (_ADI_MSK(0x00000800,uint32_t))  /* ECC Map Bank 3 */
-#define BITM_L2CTL_CTL_ECCMAP2               (_ADI_MSK(0x00000400,uint32_t))  /* ECC Map Bank 2 */
-#define BITM_L2CTL_CTL_ECCMAP1               (_ADI_MSK(0x00000200,uint32_t))  /* ECC Map Bank 1 */
-#define BITM_L2CTL_CTL_ECCMAP0               (_ADI_MSK(0x00000100,uint32_t))  /* ECC Map Bank 0 */
-#define BITM_L2CTL_CTL_BK7EDIS               (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 ECC Disable */
-#define BITM_L2CTL_CTL_BK6EDIS               (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 ECC Disable */
-#define BITM_L2CTL_CTL_BK5EDIS               (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 ECC Disable */
-#define BITM_L2CTL_CTL_BK4EDIS               (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 ECC Disable */
-#define BITM_L2CTL_CTL_BK3EDIS               (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 ECC Disable */
-#define BITM_L2CTL_CTL_BK2EDIS               (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 ECC Disable */
-#define BITM_L2CTL_CTL_BK1EDIS               (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 ECC Disable */
-#define BITM_L2CTL_CTL_BK0EDIS               (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 ECC Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C0_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C0_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C0_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C0_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C1_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C1_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C1_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C1_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_SYS                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_SYS_LOCK             31                               /* Lock */
-#define BITP_L2CTL_ACTL_SYS_BK7WDIS           7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK6WDIS           6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK5WDIS           5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK4WDIS           4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK3WDIS           3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK2WDIS           2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK1WDIS           1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK0WDIS           0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_LOCK             (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_SYS_BK7WDIS          (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK6WDIS          (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK5WDIS          (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK4WDIS          (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK3WDIS          (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK2WDIS          (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK1WDIS          (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK0WDIS          (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_STAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_STAT_ECCERR7              15                               /* ECC Error Bank 7 */
-#define BITP_L2CTL_STAT_ECCERR6              14                               /* ECC Error Bank 6 */
-#define BITP_L2CTL_STAT_ECCERR5              13                               /* ECC Error Bank 5 */
-#define BITP_L2CTL_STAT_ECCERR4              12                               /* ECC Error Bank 4 */
-#define BITP_L2CTL_STAT_ECCERR3              11                               /* ECC Error Bank 3 */
-#define BITP_L2CTL_STAT_ECCERR2              10                               /* ECC Error Bank 2 */
-#define BITP_L2CTL_STAT_ECCERR1               9                               /* ECC Error Bank 1 */
-#define BITP_L2CTL_STAT_ECCERR0               8                               /* ECC Error Bank 0 */
-#define BITP_L2CTL_STAT_RFRS                  4                               /* Refresh Register Status */
-#define BITP_L2CTL_STAT_ERR1                  1                               /* Error Port 1 */
-#define BITP_L2CTL_STAT_ERR0                  0                               /* Error Port 0 */
-#define BITM_L2CTL_STAT_ECCERR7              (_ADI_MSK(0x00008000,uint32_t))  /* ECC Error Bank 7 */
-#define BITM_L2CTL_STAT_ECCERR6              (_ADI_MSK(0x00004000,uint32_t))  /* ECC Error Bank 6 */
-#define BITM_L2CTL_STAT_ECCERR5              (_ADI_MSK(0x00002000,uint32_t))  /* ECC Error Bank 5 */
-#define BITM_L2CTL_STAT_ECCERR4              (_ADI_MSK(0x00001000,uint32_t))  /* ECC Error Bank 4 */
-#define BITM_L2CTL_STAT_ECCERR3              (_ADI_MSK(0x00000800,uint32_t))  /* ECC Error Bank 3 */
-#define BITM_L2CTL_STAT_ECCERR2              (_ADI_MSK(0x00000400,uint32_t))  /* ECC Error Bank 2 */
-#define BITM_L2CTL_STAT_ECCERR1              (_ADI_MSK(0x00000200,uint32_t))  /* ECC Error Bank 1 */
-#define BITM_L2CTL_STAT_ECCERR0              (_ADI_MSK(0x00000100,uint32_t))  /* ECC Error Bank 0 */
-#define BITM_L2CTL_STAT_RFRS                 (_ADI_MSK(0x00000010,uint32_t))  /* Refresh Register Status */
-#define BITM_L2CTL_STAT_ERR1                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Port 1 */
-#define BITM_L2CTL_STAT_ERR0                 (_ADI_MSK(0x00000001,uint32_t))  /* Error Port 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RPCR_RPC1                  8                               /* Read Priority Count 1 */
-#define BITP_L2CTL_RPCR_RPC0                  0                               /* Read Priority Count 0 */
-#define BITM_L2CTL_RPCR_RPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Read Priority Count 1 */
-#define BITM_L2CTL_RPCR_RPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Read Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_WPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_WPCR_WPC1                  8                               /* Write Priority Count 1 */
-#define BITP_L2CTL_WPCR_WPC0                  0                               /* Write Priority Count 0 */
-#define BITM_L2CTL_WPCR_WPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Write Priority Count 1 */
-#define BITM_L2CTL_WPCR_WPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Write Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RFA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RFA_ADDRHI                16                               /* Address High */
-#define BITP_L2CTL_RFA_ADDRLO                 0                               /* Address Low */
-#define BITM_L2CTL_RFA_ADDRHI                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Address High */
-#define BITM_L2CTL_RFA_ADDRLO                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address Low */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET0_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET0_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET0_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET0_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET0_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET0_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET0_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET0_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET0_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET0_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET0_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET0_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET1_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET1_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET1_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET1_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET1_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET1_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET1_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET1_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET1_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET1_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET1_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET1_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ==================================================
-        System Event Controller Registers
-   ================================================== */
-
-/* =========================
-        SEC0
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Core Interface (SCI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_CCTL0                  0xFFCA4400         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CCTL1                  0xFFCA4440         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CSTAT0                 0xFFCA4404         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CSTAT1                 0xFFCA4444         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CPND0                  0xFFCA4408         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CPND1                  0xFFCA4448         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CACT0                  0xFFCA440C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CACT1                  0xFFCA444C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CPMSK0                 0xFFCA4410         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CPMSK1                 0xFFCA4450         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CGMSK0                 0xFFCA4414         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CGMSK1                 0xFFCA4454         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CPLVL0                 0xFFCA4418         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CPLVL1                 0xFFCA4458         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CSID0                  0xFFCA441C         /* SEC0 SCI Source ID Register n */
-#define REG_SEC0_CSID1                  0xFFCA445C         /* SEC0 SCI Source ID Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Fault Management Interface (SFI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_FCTL                   0xFFCA4010         /* SEC0 Fault Control Register */
-#define REG_SEC0_FSTAT                  0xFFCA4014         /* SEC0 Fault Status Register */
-#define REG_SEC0_FSID                   0xFFCA4018         /* SEC0 Fault Source ID Register */
-#define REG_SEC0_FEND                   0xFFCA401C         /* SEC0 Fault End Register */
-#define REG_SEC0_FDLY                   0xFFCA4020         /* SEC0 Fault Delay Register */
-#define REG_SEC0_FDLY_CUR               0xFFCA4024         /* SEC0 Fault Delay Current Register */
-#define REG_SEC0_FSRDLY                 0xFFCA4028         /* SEC0 Fault System Reset Delay Register */
-#define REG_SEC0_FSRDLY_CUR             0xFFCA402C         /* SEC0 Fault System Reset Delay Current Register */
-#define REG_SEC0_FCOPP                  0xFFCA4030         /* SEC0 Fault COP Period Register */
-#define REG_SEC0_FCOPP_CUR              0xFFCA4034         /* SEC0 Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Global Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_GCTL                   0xFFCA4000         /* SEC0 Global Control Register */
-#define REG_SEC0_GSTAT                  0xFFCA4004         /* SEC0 Global Status Register */
-#define REG_SEC0_RAISE                  0xFFCA4008         /* SEC0 Global Raise Register */
-#define REG_SEC0_END                    0xFFCA400C         /* SEC0 Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Source Interface (SSI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_SCTL0                  0xFFCA4800         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL1                  0xFFCA4808         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL2                  0xFFCA4810         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL3                  0xFFCA4818         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL4                  0xFFCA4820         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL5                  0xFFCA4828         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL6                  0xFFCA4830         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL7                  0xFFCA4838         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL8                  0xFFCA4840         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL9                  0xFFCA4848         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL10                 0xFFCA4850         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL11                 0xFFCA4858         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL12                 0xFFCA4860         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL13                 0xFFCA4868         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL14                 0xFFCA4870         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL15                 0xFFCA4878         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL16                 0xFFCA4880         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL17                 0xFFCA4888         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL18                 0xFFCA4890         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL19                 0xFFCA4898         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL20                 0xFFCA48A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL21                 0xFFCA48A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL22                 0xFFCA48B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL23                 0xFFCA48B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL24                 0xFFCA48C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL25                 0xFFCA48C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL26                 0xFFCA48D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL27                 0xFFCA48D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL28                 0xFFCA48E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL29                 0xFFCA48E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL30                 0xFFCA48F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL31                 0xFFCA48F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL32                 0xFFCA4900         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL33                 0xFFCA4908         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL34                 0xFFCA4910         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL35                 0xFFCA4918         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL36                 0xFFCA4920         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL37                 0xFFCA4928         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL38                 0xFFCA4930         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL39                 0xFFCA4938         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL40                 0xFFCA4940         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL41                 0xFFCA4948         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL42                 0xFFCA4950         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL43                 0xFFCA4958         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL44                 0xFFCA4960         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL45                 0xFFCA4968         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL46                 0xFFCA4970         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL47                 0xFFCA4978         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL48                 0xFFCA4980         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL49                 0xFFCA4988         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL50                 0xFFCA4990         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL51                 0xFFCA4998         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL52                 0xFFCA49A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL53                 0xFFCA49A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL54                 0xFFCA49B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL55                 0xFFCA49B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL56                 0xFFCA49C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL57                 0xFFCA49C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL58                 0xFFCA49D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL59                 0xFFCA49D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL60                 0xFFCA49E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL61                 0xFFCA49E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL62                 0xFFCA49F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL63                 0xFFCA49F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL64                 0xFFCA4A00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL65                 0xFFCA4A08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL66                 0xFFCA4A10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL67                 0xFFCA4A18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL68                 0xFFCA4A20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL69                 0xFFCA4A28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL70                 0xFFCA4A30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL71                 0xFFCA4A38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL72                 0xFFCA4A40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL73                 0xFFCA4A48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL74                 0xFFCA4A50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL75                 0xFFCA4A58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL76                 0xFFCA4A60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL77                 0xFFCA4A68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL78                 0xFFCA4A70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL79                 0xFFCA4A78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL80                 0xFFCA4A80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL81                 0xFFCA4A88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL82                 0xFFCA4A90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL83                 0xFFCA4A98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL84                 0xFFCA4AA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL85                 0xFFCA4AA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL86                 0xFFCA4AB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL87                 0xFFCA4AB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL88                 0xFFCA4AC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL89                 0xFFCA4AC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL90                 0xFFCA4AD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL91                 0xFFCA4AD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL92                 0xFFCA4AE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL93                 0xFFCA4AE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL94                 0xFFCA4AF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL95                 0xFFCA4AF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL96                 0xFFCA4B00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL97                 0xFFCA4B08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL98                 0xFFCA4B10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL99                 0xFFCA4B18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL100                0xFFCA4B20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL101                0xFFCA4B28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL102                0xFFCA4B30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL103                0xFFCA4B38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL104                0xFFCA4B40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL105                0xFFCA4B48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL106                0xFFCA4B50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL107                0xFFCA4B58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL108                0xFFCA4B60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL109                0xFFCA4B68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL110                0xFFCA4B70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL111                0xFFCA4B78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL112                0xFFCA4B80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL113                0xFFCA4B88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL114                0xFFCA4B90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL115                0xFFCA4B98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL116                0xFFCA4BA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL117                0xFFCA4BA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL118                0xFFCA4BB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL119                0xFFCA4BB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL120                0xFFCA4BC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL121                0xFFCA4BC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL122                0xFFCA4BD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL123                0xFFCA4BD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL124                0xFFCA4BE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL125                0xFFCA4BE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL126                0xFFCA4BF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL127                0xFFCA4BF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL128                0xFFCA4C00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL129                0xFFCA4C08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL130                0xFFCA4C10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL131                0xFFCA4C18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL132                0xFFCA4C20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL133                0xFFCA4C28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL134                0xFFCA4C30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL135                0xFFCA4C38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL136                0xFFCA4C40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL137                0xFFCA4C48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL138                0xFFCA4C50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL139                0xFFCA4C58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SSTAT0                 0xFFCA4804         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT1                 0xFFCA480C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT2                 0xFFCA4814         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT3                 0xFFCA481C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT4                 0xFFCA4824         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT5                 0xFFCA482C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT6                 0xFFCA4834         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT7                 0xFFCA483C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT8                 0xFFCA4844         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT9                 0xFFCA484C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT10                0xFFCA4854         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT11                0xFFCA485C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT12                0xFFCA4864         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT13                0xFFCA486C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT14                0xFFCA4874         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT15                0xFFCA487C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT16                0xFFCA4884         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT17                0xFFCA488C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT18                0xFFCA4894         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT19                0xFFCA489C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT20                0xFFCA48A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT21                0xFFCA48AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT22                0xFFCA48B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT23                0xFFCA48BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT24                0xFFCA48C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT25                0xFFCA48CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT26                0xFFCA48D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT27                0xFFCA48DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT28                0xFFCA48E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT29                0xFFCA48EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT30                0xFFCA48F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT31                0xFFCA48FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT32                0xFFCA4904         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT33                0xFFCA490C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT34                0xFFCA4914         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT35                0xFFCA491C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT36                0xFFCA4924         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT37                0xFFCA492C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT38                0xFFCA4934         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT39                0xFFCA493C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT40                0xFFCA4944         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT41                0xFFCA494C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT42                0xFFCA4954         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT43                0xFFCA495C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT44                0xFFCA4964         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT45                0xFFCA496C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT46                0xFFCA4974         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT47                0xFFCA497C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT48                0xFFCA4984         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT49                0xFFCA498C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT50                0xFFCA4994         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT51                0xFFCA499C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT52                0xFFCA49A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT53                0xFFCA49AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT54                0xFFCA49B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT55                0xFFCA49BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT56                0xFFCA49C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT57                0xFFCA49CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT58                0xFFCA49D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT59                0xFFCA49DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT60                0xFFCA49E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT61                0xFFCA49EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT62                0xFFCA49F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT63                0xFFCA49FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT64                0xFFCA4A04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT65                0xFFCA4A0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT66                0xFFCA4A14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT67                0xFFCA4A1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT68                0xFFCA4A24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT69                0xFFCA4A2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT70                0xFFCA4A34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT71                0xFFCA4A3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT72                0xFFCA4A44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT73                0xFFCA4A4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT74                0xFFCA4A54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT75                0xFFCA4A5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT76                0xFFCA4A64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT77                0xFFCA4A6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT78                0xFFCA4A74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT79                0xFFCA4A7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT80                0xFFCA4A84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT81                0xFFCA4A8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT82                0xFFCA4A94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT83                0xFFCA4A9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT84                0xFFCA4AA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT85                0xFFCA4AAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT86                0xFFCA4AB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT87                0xFFCA4ABC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT88                0xFFCA4AC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT89                0xFFCA4ACC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT90                0xFFCA4AD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT91                0xFFCA4ADC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT92                0xFFCA4AE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT93                0xFFCA4AEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT94                0xFFCA4AF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT95                0xFFCA4AFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT96                0xFFCA4B04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT97                0xFFCA4B0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT98                0xFFCA4B14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT99                0xFFCA4B1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT100               0xFFCA4B24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT101               0xFFCA4B2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT102               0xFFCA4B34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT103               0xFFCA4B3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT104               0xFFCA4B44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT105               0xFFCA4B4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT106               0xFFCA4B54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT107               0xFFCA4B5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT108               0xFFCA4B64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT109               0xFFCA4B6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT110               0xFFCA4B74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT111               0xFFCA4B7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT112               0xFFCA4B84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT113               0xFFCA4B8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT114               0xFFCA4B94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT115               0xFFCA4B9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT116               0xFFCA4BA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT117               0xFFCA4BAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT118               0xFFCA4BB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT119               0xFFCA4BBC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT120               0xFFCA4BC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT121               0xFFCA4BCC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT122               0xFFCA4BD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT123               0xFFCA4BDC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT124               0xFFCA4BE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT125               0xFFCA4BEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT126               0xFFCA4BF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT127               0xFFCA4BFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT128               0xFFCA4C04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT129               0xFFCA4C0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT130               0xFFCA4C14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT131               0xFFCA4C1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT132               0xFFCA4C24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT133               0xFFCA4C2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT134               0xFFCA4C34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT135               0xFFCA4C3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT136               0xFFCA4C44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT137               0xFFCA4C4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT138               0xFFCA4C54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT139               0xFFCA4C5C         /* SEC0 Source Status Register n */
-
-/* =========================
-        SEC
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_CCTL_NMIEN                  16                               /* NMI Enable */
-#define BITP_SEC_CCTL_WFI                    12                               /* Wait For Idle */
-#define BITP_SEC_CCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_CCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CCTL_NMIEN                  (_ADI_MSK(0x00010000,uint32_t))  /* NMI Enable */
-#define ENUM_SEC_CCTL_NMI_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* NMIEN: Disable */
-#define ENUM_SEC_CCTL_NMI_EN                 (_ADI_MSK(0x00010000,uint32_t))  /* NMIEN: Enable */
-
-#define BITM_SEC_CCTL_WFI                    (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CCTL_NO_WAITIDLE            (_ADI_MSK(0x00000000,uint32_t))  /* WFI: No Action */
-#define ENUM_SEC_CCTL_WAITIDLE               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Wait for Idle */
-
-#define BITM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_CCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_CCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSTAT_NMI                   16                               /* NMI */
-#define BITP_SEC_CSTAT_WFI                   12                               /* Wait For Idle */
-#define BITP_SEC_CSTAT_SIDV                  10                               /* SID Valid */
-#define BITP_SEC_CSTAT_ACTV                   9                               /* ACT Valid */
-#define BITP_SEC_CSTAT_PNDV                   8                               /* PND Valid */
-#define BITP_SEC_CSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_CSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI */
-#define ENUM_SEC_CSTAT_NO_NMI                (_ADI_MSK(0x00000000,uint32_t))  /* NMI: No NMI Occured */
-#define ENUM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI: NMI Occurred */
-
-#define BITM_SEC_CSTAT_WFI                   (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CSTAT_NOT_WAITING           (_ADI_MSK(0x00000000,uint32_t))  /* WFI: Not Waiting */
-#define ENUM_SEC_CSTAT_WAITING               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Waiting */
-
-#define BITM_SEC_CSTAT_SIDV                  (_ADI_MSK(0x00000400,uint32_t))  /* SID Valid */
-#define ENUM_SEC_CSTAT_INVALID_SID           (_ADI_MSK(0x00000000,uint32_t))  /* SIDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_SID             (_ADI_MSK(0x00000400,uint32_t))  /* SIDV: Valid */
-
-#define BITM_SEC_CSTAT_ACTV                  (_ADI_MSK(0x00000200,uint32_t))  /* ACT Valid */
-#define ENUM_SEC_CSTAT_INVALID_ACT           (_ADI_MSK(0x00000000,uint32_t))  /* ACTV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_ACT             (_ADI_MSK(0x00000200,uint32_t))  /* ACTV: Valid */
-
-#define BITM_SEC_CSTAT_PNDV                  (_ADI_MSK(0x00000100,uint32_t))  /* PND Valid */
-#define ENUM_SEC_CSTAT_INVALID_PND           (_ADI_MSK(0x00000000,uint32_t))  /* PNDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_PND             (_ADI_MSK(0x00000100,uint32_t))  /* PNDV: Valid */
-
-#define BITM_SEC_CSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_CSTAT_ACKERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Acknowledge Error */
-
-#define BITM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_CSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPND_PRIO                    8                               /* Highest Pending IRQ Priority */
-#define BITP_SEC_CPND_SID                     0                               /* Highest Pending IRQ Source ID */
-#define BITM_SEC_CPND_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Pending IRQ Priority */
-#define BITM_SEC_CPND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CACT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CACT_PRIO                    8                               /* Highest Active IRQ Priority */
-#define BITP_SEC_CACT_SID                     0                               /* Highest Active IRQ Source ID */
-#define BITM_SEC_CACT_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Active IRQ Priority */
-#define BITM_SEC_CACT_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPMSK_PRIO                   0                               /* IRQ Priority Mask */
-
-#define BITM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPMSK_PRIO                  (_ADI_MSK(0x000000FF,uint32_t))  /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CGMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CGMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CGMSK_UGRP                   8                               /* Ungrouped Mask */
-#define BITP_SEC_CGMSK_GRP                    0                               /* Grouped Mask */
-
-#define BITM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CGMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CGMSK_UGRP                  (_ADI_MSK(0x00000100,uint32_t))  /* Ungrouped Mask */
-#define ENUM_SEC_CGMSK_UNMASK                (_ADI_MSK(0x00000000,uint32_t))  /* UGRP: Unmask Ungrouped Sources */
-#define ENUM_SEC_CGMSK_MASK                  (_ADI_MSK(0x00000100,uint32_t))  /* UGRP: Mask Ungrouped Sources */
-#define BITM_SEC_CGMSK_GRP                   (_ADI_MSK(0x0000000F,uint32_t))  /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPLVL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPLVL_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPLVL_PLVL                   0                               /* Priority Levels */
-
-#define BITM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPLVL_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPLVL_PLVL                  (_ADI_MSK(0x00000007,uint32_t))  /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSID_SID                     0                               /* Source ID */
-#define BITM_SEC_CSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_FCTL_TES                    13                               /* Trigger Event Select */
-#define BITP_SEC_FCTL_CMS                    12                               /* COP Mode Select */
-#define BITP_SEC_FCTL_FIEN                    7                               /* Fault Input Enable */
-#define BITP_SEC_FCTL_SREN                    6                               /* System Reset Enable */
-#define BITP_SEC_FCTL_TOEN                    5                               /* Trigger Output Enable */
-#define BITP_SEC_FCTL_FOEN                    4                               /* Fault Output Enable */
-#define BITP_SEC_FCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_FCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_FCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: UnLock */
-#define ENUM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_FCTL_TES                    (_ADI_MSK(0x00002000,uint32_t))  /* Trigger Event Select */
-#define ENUM_SEC_FCTL_FLTACT_MODE            (_ADI_MSK(0x00000000,uint32_t))  /* TES: Fault Active Mode */
-#define ENUM_SEC_FCTL_FLTPND_MODE            (_ADI_MSK(0x00002000,uint32_t))  /* TES: Fault Pending Mode */
-
-#define BITM_SEC_FCTL_CMS                    (_ADI_MSK(0x00001000,uint32_t))  /* COP Mode Select */
-#define ENUM_SEC_FCTL_FLT_MODE               (_ADI_MSK(0x00000000,uint32_t))  /* CMS: Fault Mode */
-#define ENUM_SEC_FCTL_COP_MODE               (_ADI_MSK(0x00001000,uint32_t))  /* CMS: COP Mode */
-
-#define BITM_SEC_FCTL_FIEN                   (_ADI_MSK(0x00000080,uint32_t))  /* Fault Input Enable */
-#define ENUM_SEC_FCTL_FLTIN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FIEN: Disable */
-#define ENUM_SEC_FCTL_FLTIN_EN               (_ADI_MSK(0x00000080,uint32_t))  /* FIEN: Enable */
-
-#define BITM_SEC_FCTL_SREN                   (_ADI_MSK(0x00000040,uint32_t))  /* System Reset Enable */
-#define ENUM_SEC_FCTL_SYSRST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SREN: Disable */
-#define ENUM_SEC_FCTL_SYSRST_EN              (_ADI_MSK(0x00000040,uint32_t))  /* SREN: Enable */
-
-#define BITM_SEC_FCTL_TOEN                   (_ADI_MSK(0x00000020,uint32_t))  /* Trigger Output Enable */
-#define ENUM_SEC_FCTL_TRGOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TOEN: Disable */
-#define ENUM_SEC_FCTL_TRGOUT_EN              (_ADI_MSK(0x00000020,uint32_t))  /* TOEN: Enable */
-
-#define BITM_SEC_FCTL_FOEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Fault Output Enable */
-#define ENUM_SEC_FCTL_FLTOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* FOEN: Disable */
-#define ENUM_SEC_FCTL_FLTOUT_EN              (_ADI_MSK(0x00000010,uint32_t))  /* FOEN: Enable */
-
-#define BITM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_FCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_FCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSTAT_NPND                  10                               /* Next Pending Fault */
-#define BITP_SEC_FSTAT_ACT                    9                               /* Fault Active */
-#define BITP_SEC_FSTAT_PND                    8                               /* Pending Fault */
-#define BITP_SEC_FSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_FSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_FSTAT_NPND                  (_ADI_MSK(0x00000400,uint32_t))  /* Next Pending Fault */
-#define ENUM_SEC_FSTAT_NO_NXTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* NPND: Not Pending */
-#define ENUM_SEC_FSTAT_NXTFLT                (_ADI_MSK(0x00000400,uint32_t))  /* NPND: Pending */
-
-#define BITM_SEC_FSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Fault Active */
-#define ENUM_SEC_FSTAT_NO_FLTACT             (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Fault */
-#define ENUM_SEC_FSTAT_FLTACT                (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Fault */
-
-#define BITM_SEC_FSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Fault */
-#define ENUM_SEC_FSTAT_NO_FLTPND             (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_FSTAT_FLTPND                (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_FSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_FSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_FSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSID_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FSID_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FSID_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FSID_SRC_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FSID_SRC_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FEND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FEND_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FEND_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FEND_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FEND_END_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FEND_END_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FEND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_GCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_GCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_GCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_GCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_GCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GSTAT_LWERR                 31                               /* Lock Write Error */
-#define BITP_SEC_GSTAT_ADRERR                30                               /* Address Error */
-#define BITP_SEC_GSTAT_SID                   16                               /* Source ID for SSI Error */
-#define BITP_SEC_GSTAT_SCI                    8                               /* SCI ID for SCI Error */
-#define BITP_SEC_GSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_GSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define ENUM_SEC_GSTAT_NO_LWERR              (_ADI_MSK(0x00000000,uint32_t))  /* LWERR: No Error */
-#define ENUM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* LWERR: Error Occurred */
-
-#define BITM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define ENUM_SEC_GSTAT_NO_ADRERR             (_ADI_MSK(0x00000000,uint32_t))  /* ADRERR: No Error */
-#define ENUM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* ADRERR: Error Occurred */
-#define BITM_SEC_GSTAT_SID                   (_ADI_MSK(0x00FF0000,uint32_t))  /* Source ID for SSI Error */
-#define BITM_SEC_GSTAT_SCI                   (_ADI_MSK(0x00000F00,uint32_t))  /* SCI ID for SCI Error */
-
-#define BITM_SEC_GSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_GSTAT_SFIERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: SFI Error */
-#define ENUM_SEC_GSTAT_SCIERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: SCI Error */
-#define ENUM_SEC_GSTAT_SSIERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: SSI Error */
-
-#define BITM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_GSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_RAISE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_RAISE_SID                    0                               /* Source ID IRQ Set to Pending */
-#define BITM_SEC_RAISE_SID                   (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_END                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_END_SID                      0                               /* Source ID IRQ to End */
-#define BITM_SEC_END_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_SCTL_CTG                    24                               /* Core Target Select */
-#define BITP_SEC_SCTL_GRP                    16                               /* Group Select */
-#define BITP_SEC_SCTL_PRIO                    8                               /* Priority Level Select */
-#define BITP_SEC_SCTL_ERREN                   4                               /* Error Enable */
-#define BITP_SEC_SCTL_ES                      3                               /* Edge Select */
-#define BITP_SEC_SCTL_SEN                     2                               /* Source (signal) Enable */
-#define BITP_SEC_SCTL_FEN                     1                               /* Fault Enable */
-#define BITP_SEC_SCTL_IEN                     0                               /* Interrupt Enable */
-
-#define BITM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_SCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_SCTL_CTG                    (_ADI_MSK(0x0F000000,uint32_t))  /* Core Target Select */
-#define BITM_SEC_SCTL_GRP                    (_ADI_MSK(0x000F0000,uint32_t))  /* Group Select */
-#define BITM_SEC_SCTL_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Priority Level Select */
-
-#define BITM_SEC_SCTL_ERREN                  (_ADI_MSK(0x00000010,uint32_t))  /* Error Enable */
-#define ENUM_SEC_SCTL_ERR_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* ERREN: Disable */
-#define ENUM_SEC_SCTL_ERR_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* ERREN: Enable */
-
-#define BITM_SEC_SCTL_ES                     (_ADI_MSK(0x00000008,uint32_t))  /* Edge Select */
-#define ENUM_SEC_SCTL_LEVEL                  (_ADI_MSK(0x00000000,uint32_t))  /* ES: Level Sensitive */
-#define ENUM_SEC_SCTL_EDGE                   (_ADI_MSK(0x00000008,uint32_t))  /* ES: Edge Sensitive */
-
-#define BITM_SEC_SCTL_SEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Source (signal) Enable */
-#define ENUM_SEC_SCTL_SRC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* SEN: Disable */
-#define ENUM_SEC_SCTL_SRC_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* SEN: Enable */
-
-#define BITM_SEC_SCTL_FEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Fault Enable */
-#define ENUM_SEC_SCTL_FAULT_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FEN: Disable */
-#define ENUM_SEC_SCTL_FAULT_EN               (_ADI_MSK(0x00000002,uint32_t))  /* FEN: Enable */
-
-#define BITM_SEC_SCTL_IEN                    (_ADI_MSK(0x00000001,uint32_t))  /* Interrupt Enable */
-#define ENUM_SEC_SCTL_INT_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* IEN: Disable */
-#define ENUM_SEC_SCTL_INT_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SSTAT_CHID                  16                               /* Channel ID */
-#define BITP_SEC_SSTAT_ACT                    9                               /* Active Source */
-#define BITP_SEC_SSTAT_PND                    8                               /* Pending Source */
-#define BITP_SEC_SSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_SSTAT_ERR                    1                               /* Error */
-#define BITM_SEC_SSTAT_CHID                  (_ADI_MSK(0x00FF0000,uint32_t))  /* Channel ID */
-
-#define BITM_SEC_SSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Active Source */
-#define ENUM_SEC_SSTAT_NO_SRC                (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Source */
-#define ENUM_SEC_SSTAT_ACTIVE_SRC            (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Source */
-
-#define BITM_SEC_SSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Source */
-#define ENUM_SEC_SSTAT_NOTPENDING            (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_SSTAT_PENDING               (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_SSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_SSTAT_SOVFERR               (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Source Overflow Error */
-#define ENUM_SEC_SSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_SSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ==================================================
-        Trigger Routing Unit Registers
-   ================================================== */
-
-/* =========================
-        TRU0
-   ========================= */
-#define REG_TRU0_SSR0                   0xFFCA5000         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR1                   0xFFCA5004         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR2                   0xFFCA5008         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR3                   0xFFCA500C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR4                   0xFFCA5010         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR5                   0xFFCA5014         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR6                   0xFFCA5018         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR7                   0xFFCA501C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR8                   0xFFCA5020         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR9                   0xFFCA5024         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR10                  0xFFCA5028         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR11                  0xFFCA502C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR12                  0xFFCA5030         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR13                  0xFFCA5034         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR14                  0xFFCA5038         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR15                  0xFFCA503C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR16                  0xFFCA5040         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR17                  0xFFCA5044         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR18                  0xFFCA5048         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR19                  0xFFCA504C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR20                  0xFFCA5050         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR21                  0xFFCA5054         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR22                  0xFFCA5058         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR23                  0xFFCA505C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR24                  0xFFCA5060         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR25                  0xFFCA5064         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR26                  0xFFCA5068         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR27                  0xFFCA506C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR28                  0xFFCA5070         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR29                  0xFFCA5074         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR30                  0xFFCA5078         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR31                  0xFFCA507C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR32                  0xFFCA5080         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR33                  0xFFCA5084         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR34                  0xFFCA5088         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR35                  0xFFCA508C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR36                  0xFFCA5090         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR37                  0xFFCA5094         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR38                  0xFFCA5098         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR39                  0xFFCA509C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR40                  0xFFCA50A0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR41                  0xFFCA50A4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR42                  0xFFCA50A8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR43                  0xFFCA50AC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR44                  0xFFCA50B0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR45                  0xFFCA50B4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR46                  0xFFCA50B8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR47                  0xFFCA50BC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR48                  0xFFCA50C0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR49                  0xFFCA50C4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR50                  0xFFCA50C8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR51                  0xFFCA50CC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR52                  0xFFCA50D0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR53                  0xFFCA50D4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR54                  0xFFCA50D8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR55                  0xFFCA50DC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR56                  0xFFCA50E0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR57                  0xFFCA50E4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR58                  0xFFCA50E8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR59                  0xFFCA50EC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR60                  0xFFCA50F0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR61                  0xFFCA50F4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR62                  0xFFCA50F8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR63                  0xFFCA50FC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR64                  0xFFCA5100         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR65                  0xFFCA5104         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR66                  0xFFCA5108         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR67                  0xFFCA510C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR68                  0xFFCA5110         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR69                  0xFFCA5114         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR70                  0xFFCA5118         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR71                  0xFFCA511C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR72                  0xFFCA5120         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR73                  0xFFCA5124         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR74                  0xFFCA5128         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR75                  0xFFCA512C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR76                  0xFFCA5130         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR77                  0xFFCA5134         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR78                  0xFFCA5138         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR79                  0xFFCA513C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR80                  0xFFCA5140         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR81                  0xFFCA5144         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR82                  0xFFCA5148         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR83                  0xFFCA514C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR84                  0xFFCA5150         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR85                  0xFFCA5154         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR86                  0xFFCA5158         /* TRU0 Slave Select Register */
-#define REG_TRU0_MTR                    0xFFCA57E0         /* TRU0 Master Trigger Register */
-#define REG_TRU0_ERRADDR                0xFFCA57E8         /* TRU0 Error Address Register */
-#define REG_TRU0_STAT                   0xFFCA57EC         /* TRU0 Status Information Register */
-#define REG_TRU0_REVID                  0xFFCA57F0         /* TRU0 Revision ID Register */
-#define REG_TRU0_GCTL                   0xFFCA57F4         /* TRU0 Global Control Register */
-
-/* =========================
-        TRU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_SSR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_SSR_LOCK                    31                               /* SSRn Lock */
-#define BITP_TRU_SSR_SSR                      0                               /* SSRn Slave Select */
-#define BITM_TRU_SSR_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* SSRn Lock */
-#define BITM_TRU_SSR_SSR                     (_ADI_MSK(0x000000FF,uint32_t))  /* SSRn Slave Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_MTR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_MTR_MTR3                    24                               /* Master Trigger Register 3 */
-#define BITP_TRU_MTR_MTR2                    16                               /* Master Trigger Register 2 */
-#define BITP_TRU_MTR_MTR1                     8                               /* Master Trigger Register 1 */
-#define BITP_TRU_MTR_MTR0                     0                               /* Master Trigger Register 0 */
-#define BITM_TRU_MTR_MTR3                    (_ADI_MSK(0xFF000000,uint32_t))  /* Master Trigger Register 3 */
-#define BITM_TRU_MTR_MTR2                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Master Trigger Register 2 */
-#define BITM_TRU_MTR_MTR1                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Master Trigger Register 1 */
-#define BITM_TRU_MTR_MTR0                    (_ADI_MSK(0x000000FF,uint32_t))  /* Master Trigger Register 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_ERRADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_ERRADDR_ADDR                 0                               /* Error Address */
-#define BITM_TRU_ERRADDR_ADDR                (_ADI_MSK(0x00000FFF,uint32_t))  /* Error Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_STAT_ADDRERR                 1                               /* Address Error Status */
-#define BITP_TRU_STAT_LWERR                   0                               /* Lock Write Error Status */
-#define BITM_TRU_STAT_ADDRERR                (_ADI_MSK(0x00000002,uint32_t))  /* Address Error Status */
-#define BITM_TRU_STAT_LWERR                  (_ADI_MSK(0x00000001,uint32_t))  /* Lock Write Error Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_REVID_MAJOR                  4                               /* Major Version ID */
-#define BITP_TRU_REVID_REV                    0                               /* Incremental Version ID */
-#define BITM_TRU_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_TRU_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_GCTL_LOCK                   31                               /* GCTL Lock Bit */
-#define BITP_TRU_GCTL_MTRL                    2                               /* MTR Lock Bit */
-#define BITP_TRU_GCTL_RESET                   1                               /* Soft Reset */
-#define BITP_TRU_GCTL_EN                      0                               /* Non-MMR Enable */
-#define BITM_TRU_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* GCTL Lock Bit */
-#define BITM_TRU_GCTL_MTRL                   (_ADI_MSK(0x00000004,uint32_t))  /* MTR Lock Bit */
-#define BITM_TRU_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Soft Reset */
-#define BITM_TRU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Non-MMR Enable */
-
-/* ==================================================
-        Reset Control Unit Registers
-   ================================================== */
-
-/* =========================
-        RCU0
-   ========================= */
-#define REG_RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
-#define REG_RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
-#define REG_RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
-#define REG_RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
-#define REG_RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
-#define REG_RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
-#define REG_RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
-#define REG_RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
-#define REG_RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
-#define REG_RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
-
-/* =========================
-        RCU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CTL_LOCK                    31                               /* Lock */
-#define BITP_RCU_CTL_RSTOUTDSRT               2                               /* Reset Out Deassert */
-#define BITP_RCU_CTL_RSTOUTASRT               1                               /* Reset Out Assert */
-#define BITP_RCU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_RCU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CTL_RSTOUTDSRT              (_ADI_MSK(0x00000004,uint32_t))  /* Reset Out Deassert */
-#define BITM_RCU_CTL_RSTOUTASRT              (_ADI_MSK(0x00000002,uint32_t))  /* Reset Out Assert */
-#define BITM_RCU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_STAT_RSTOUTERR              18                               /* Reset Out Error */
-#define BITP_RCU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_RCU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_RCU_STAT_BMODE                   8                               /* Boot Mode */
-#define BITP_RCU_STAT_RSTOUT                  5                               /* Reset Out Status */
-#define BITP_RCU_STAT_SWRST                   3                               /* Software Reset */
-#define BITP_RCU_STAT_SSRST                   2                               /* System Source Reset */
-#define BITP_RCU_STAT_HBRST                   1                               /* Hibernate Reset */
-#define BITP_RCU_STAT_HWRST                   0                               /* Hardware Reset */
-#define BITM_RCU_STAT_RSTOUTERR              (_ADI_MSK(0x00040000,uint32_t))  /* Reset Out Error */
-#define BITM_RCU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_RCU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_RCU_STAT_BMODE                  (_ADI_MSK(0x00000F00,uint32_t))  /* Boot Mode */
-#define BITM_RCU_STAT_RSTOUT                 (_ADI_MSK(0x00000020,uint32_t))  /* Reset Out Status */
-#define BITM_RCU_STAT_SWRST                  (_ADI_MSK(0x00000008,uint32_t))  /* Software Reset */
-#define BITM_RCU_STAT_SSRST                  (_ADI_MSK(0x00000004,uint32_t))  /* System Source Reset */
-#define BITM_RCU_STAT_HBRST                  (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Reset */
-#define BITM_RCU_STAT_HWRST                  (_ADI_MSK(0x00000001,uint32_t))  /* Hardware Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRCTL_LOCK                  31                               /* Lock */
-#define BITP_RCU_CRCTL_CR0                    0                               /* Core Reset n */
-#define BITP_RCU_CRCTL_CR1                    1                               /* Core Reset n */
-#define BITM_RCU_CRCTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CRCTL_CR0                   (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRCTL_CR1                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRSTAT_CR0                   0                               /* Core Reset n */
-#define BITP_RCU_CRSTAT_CR1                   1                               /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR0                  (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR1                  (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SIDIS                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SIDIS_LOCK                  31                               /* Lock */
-#define BITP_RCU_SIDIS_SI0                    0                               /* System Interface n */
-#define BITP_RCU_SIDIS_SI1                    1                               /* System Interface n */
-#define BITM_RCU_SIDIS_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SIDIS_SI0                   (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SIDIS_SI1                   (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SISTAT_SI0                   0                               /* System Interface n */
-#define BITP_RCU_SISTAT_SI1                   1                               /* System Interface n */
-#define BITM_RCU_SISTAT_SI0                  (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SISTAT_SI1                  (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SVECT_LCK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SVECT_LCK_LOCK              31                               /* Lock */
-#define BITP_RCU_SVECT_LCK_SVECT0             0                               /* Software Vector Register n */
-#define BITP_RCU_SVECT_LCK_SVECT1             1                               /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SVECT_LCK_SVECT0            (_ADI_MSK(0x00000001,uint32_t))  /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_SVECT1            (_ADI_MSK(0x00000002,uint32_t))  /* Software Vector Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_BCODE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_BCODE_LOCK                  31                               /* Lock */
-#define BITP_RCU_BCODE_BCODE                  0                               /* Boot Code */
-#define BITM_RCU_BCODE_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_BCODE_BCODE                 (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Boot Code */
-
-/* ==================================================
-        System Protection Unit Registers
-   ================================================== */
-
-/* =========================
-        SPU0
-   ========================= */
-#define REG_SPU0_CTL                    0xFFCA7000         /* SPU0 Control Register */
-#define REG_SPU0_STAT                   0xFFCA7004         /* SPU0 Status Register */
-#define REG_SPU0_WP0                    0xFFCA7400         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP1                    0xFFCA7404         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP2                    0xFFCA7408         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP3                    0xFFCA740C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP4                    0xFFCA7410         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP5                    0xFFCA7414         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP6                    0xFFCA7418         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP7                    0xFFCA741C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP8                    0xFFCA7420         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP9                    0xFFCA7424         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP10                   0xFFCA7428         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP11                   0xFFCA742C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP12                   0xFFCA7430         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP13                   0xFFCA7434         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP14                   0xFFCA7438         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP15                   0xFFCA743C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP16                   0xFFCA7440         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP17                   0xFFCA7444         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP18                   0xFFCA7448         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP19                   0xFFCA744C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP20                   0xFFCA7450         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP21                   0xFFCA7454         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP22                   0xFFCA7458         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP23                   0xFFCA745C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP24                   0xFFCA7460         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP25                   0xFFCA7464         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP26                   0xFFCA7468         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP27                   0xFFCA746C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP28                   0xFFCA7470         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP29                   0xFFCA7474         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP30                   0xFFCA7478         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP31                   0xFFCA747C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP32                   0xFFCA7480         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP33                   0xFFCA7484         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP34                   0xFFCA7488         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP35                   0xFFCA748C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP36                   0xFFCA7490         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP37                   0xFFCA7494         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP38                   0xFFCA7498         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP39                   0xFFCA749C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP40                   0xFFCA74A0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP41                   0xFFCA74A4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP42                   0xFFCA74A8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP43                   0xFFCA74AC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP44                   0xFFCA74B0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP45                   0xFFCA74B4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP46                   0xFFCA74B8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP47                   0xFFCA74BC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP48                   0xFFCA74C0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP49                   0xFFCA74C4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP50                   0xFFCA74C8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP51                   0xFFCA74CC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP52                   0xFFCA74D0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP53                   0xFFCA74D4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP54                   0xFFCA74D8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP55                   0xFFCA74DC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP56                   0xFFCA74E0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP57                   0xFFCA74E4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP58                   0xFFCA74E8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP59                   0xFFCA74EC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP60                   0xFFCA74F0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP61                   0xFFCA74F4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP62                   0xFFCA74F8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP63                   0xFFCA74FC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP64                   0xFFCA7500         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP65                   0xFFCA7504         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP66                   0xFFCA7508         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP67                   0xFFCA750C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP68                   0xFFCA7510         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP69                   0xFFCA7514         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP70                   0xFFCA7518         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP71                   0xFFCA751C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP72                   0xFFCA7520         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP73                   0xFFCA7524         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP74                   0xFFCA7528         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP75                   0xFFCA752C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP76                   0xFFCA7530         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP77                   0xFFCA7534         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP78                   0xFFCA7538         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP79                   0xFFCA753C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP80                   0xFFCA7540         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP81                   0xFFCA7544         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP82                   0xFFCA7548         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP83                   0xFFCA754C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP84                   0xFFCA7550         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP85                   0xFFCA7554         /* SPU0 Write Protect Register n */
-
-/* =========================
-        SPU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_CTL_WPLCK                   16                               /* Write Protect Register Lock */
-#define BITP_SPU_CTL_GLCK                     0                               /* Global Lock Disable */
-#define BITM_SPU_CTL_WPLCK                   (_ADI_MSK(0x00010000,uint32_t))  /* Write Protect Register Lock */
-#define BITM_SPU_CTL_GLCK                    (_ADI_MSK(0x000000FF,uint32_t))  /* Global Lock Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_STAT_LWERR                  31                               /* Lock Write Error */
-#define BITP_SPU_STAT_ADDRERR                30                               /* Address Error */
-#define BITP_SPU_STAT_GLCK                    0                               /* Global Lock Status */
-#define BITM_SPU_STAT_LWERR                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define BITM_SPU_STAT_ADDRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define BITM_SPU_STAT_GLCK                   (_ADI_MSK(0x00000001,uint32_t))  /* Global Lock Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_WP                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_WP_SM0                      16                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_SM1                      17                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_CM0                       0                               /* Core Master x Write Protect Enable */
-#define BITP_SPU_WP_CM1                       1                               /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_SM0                      (_ADI_MSK(0x00010000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_SM1                      (_ADI_MSK(0x00020000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_CM0                      (_ADI_MSK(0x00000001,uint32_t))  /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_CM1                      (_ADI_MSK(0x00000002,uint32_t))  /* Core Master x Write Protect Enable */
-
-/* ==================================================
-        Clock Generation Unit Registers
-   ================================================== */
-
-/* =========================
-        CGU0
-   ========================= */
-#define REG_CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
-#define REG_CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
-#define REG_CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
-#define REG_CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
-
-/* =========================
-        CGU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CTL_LOCK                    31                               /* Lock */
-#define BITP_CGU_CTL_WFI                     30                               /* Wait For Idle */
-#define BITP_CGU_CTL_MSEL                     8                               /* Multiplier Select */
-#define BITP_CGU_CTL_DF                       0                               /* Divide Frequency */
-#define BITM_CGU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_CTL_WFI                     (_ADI_MSK(0x40000000,uint32_t))  /* Wait For Idle */
-
-#define BITM_CGU_CTL_MSEL                    (_ADI_MSK(0x00007F00,uint32_t))  /* Multiplier Select */
-#define ENUM_CGU_CTL_MSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* MSEL: MSEL = 1 to 127 */
-#define BITM_CGU_CTL_DF                      (_ADI_MSK(0x00000001,uint32_t))  /* Divide Frequency */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_STAT_PLOCKERR               21                               /* PLL Lock Error */
-#define BITP_CGU_STAT_WDIVERR                20                               /* Write to DIV Error */
-#define BITP_CGU_STAT_WDFMSERR               19                               /* Write to DF or MSEL Error */
-#define BITP_CGU_STAT_DIVERR                 18                               /* DIV Error */
-#define BITP_CGU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_CGU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_CGU_STAT_OCBF                    9                               /* OUTCLK Buffer Status */
-#define BITP_CGU_STAT_DCBF                    8                               /* DCLK Buffer Status */
-#define BITP_CGU_STAT_SCBF1                   7                               /* SCLK1 Buffer Status */
-#define BITP_CGU_STAT_SCBF0                   6                               /* SCLK0 Buffer Status */
-#define BITP_CGU_STAT_CCBF1                   5                               /* CCLK1 Buffer Status */
-#define BITP_CGU_STAT_CCBF0                   4                               /* CCLK0 Buffer Status */
-#define BITP_CGU_STAT_CLKSALGN                3                               /* Clock Alignment */
-#define BITP_CGU_STAT_PLOCK                   2                               /* PLL Lock */
-#define BITP_CGU_STAT_PLLBP                   1                               /* PLL Bypass */
-#define BITP_CGU_STAT_PLLEN                   0                               /* PLL Enable */
-#define BITM_CGU_STAT_PLOCKERR               (_ADI_MSK(0x00200000,uint32_t))  /* PLL Lock Error */
-#define BITM_CGU_STAT_WDIVERR                (_ADI_MSK(0x00100000,uint32_t))  /* Write to DIV Error */
-#define BITM_CGU_STAT_WDFMSERR               (_ADI_MSK(0x00080000,uint32_t))  /* Write to DF or MSEL Error */
-#define BITM_CGU_STAT_DIVERR                 (_ADI_MSK(0x00040000,uint32_t))  /* DIV Error */
-#define BITM_CGU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_CGU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_CGU_STAT_OCBF                   (_ADI_MSK(0x00000200,uint32_t))  /* OUTCLK Buffer Status */
-#define BITM_CGU_STAT_DCBF                   (_ADI_MSK(0x00000100,uint32_t))  /* DCLK Buffer Status */
-#define BITM_CGU_STAT_SCBF1                  (_ADI_MSK(0x00000080,uint32_t))  /* SCLK1 Buffer Status */
-#define BITM_CGU_STAT_SCBF0                  (_ADI_MSK(0x00000040,uint32_t))  /* SCLK0 Buffer Status */
-#define BITM_CGU_STAT_CCBF1                  (_ADI_MSK(0x00000020,uint32_t))  /* CCLK1 Buffer Status */
-#define BITM_CGU_STAT_CCBF0                  (_ADI_MSK(0x00000010,uint32_t))  /* CCLK0 Buffer Status */
-#define BITM_CGU_STAT_CLKSALGN               (_ADI_MSK(0x00000008,uint32_t))  /* Clock Alignment */
-#define BITM_CGU_STAT_PLOCK                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Lock */
-#define BITM_CGU_STAT_PLLBP                  (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass */
-#define BITM_CGU_STAT_PLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* PLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_DIV                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_DIV_LOCK                    31                               /* Lock */
-#define BITP_CGU_DIV_UPDT                    30                               /* Update Clock Divisors */
-#define BITP_CGU_DIV_ALGN                    29                               /* Align */
-#define BITP_CGU_DIV_OSEL                    22                               /* OUTCLK Divisor */
-#define BITP_CGU_DIV_DSEL                    16                               /* DCLK Divisor */
-#define BITP_CGU_DIV_S1SEL                   13                               /* SCLK 1 Divisor */
-#define BITP_CGU_DIV_SYSSEL                   8                               /* SYSCLK Divisor */
-#define BITP_CGU_DIV_S0SEL                    5                               /* SCLK 0 Divisor */
-#define BITP_CGU_DIV_CSEL                     0                               /* CCLK Divisor */
-#define BITM_CGU_DIV_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_DIV_UPDT                    (_ADI_MSK(0x40000000,uint32_t))  /* Update Clock Divisors */
-#define BITM_CGU_DIV_ALGN                    (_ADI_MSK(0x20000000,uint32_t))  /* Align */
-
-#define BITM_CGU_DIV_OSEL                    (_ADI_MSK(0x1FC00000,uint32_t))  /* OUTCLK Divisor */
-#define ENUM_CGU_DIV_OSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* OSEL: OSEL = 1 to 127 */
-
-#define BITM_CGU_DIV_DSEL                    (_ADI_MSK(0x001F0000,uint32_t))  /* DCLK Divisor */
-#define ENUM_CGU_DIV_DSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* DSEL: DSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S1SEL                   (_ADI_MSK(0x0000E000,uint32_t))  /* SCLK 1 Divisor */
-#define ENUM_CGU_DIV_S1SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S1SEL: S1SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_SYSSEL                  (_ADI_MSK(0x00001F00,uint32_t))  /* SYSCLK Divisor */
-#define ENUM_CGU_DIV_SYSSEL1TO31             (_ADI_MSK(0x00000000,uint32_t))  /* SYSSEL: SYSSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S0SEL                   (_ADI_MSK(0x000000E0,uint32_t))  /* SCLK 0 Divisor */
-#define ENUM_CGU_DIV_S0SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S0SEL: S0SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_CSEL                    (_ADI_MSK(0x0000001F,uint32_t))  /* CCLK Divisor */
-#define ENUM_CGU_DIV_CSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* CSEL: CSEL= 1 to 31 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CLKOUTSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CLKOUTSEL_LOCK              31                               /* Lock */
-#define BITP_CGU_CLKOUTSEL_CLKOUTSEL          0                               /* CLKOUT Select */
-
-#define BITM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_CGU_CLKOUTSEL_UNLOCK            (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_CGU_CLKOUTSEL_CLKOUTSEL         (_ADI_MSK(0x0000000F,uint32_t))  /* CLKOUT Select */
-#define ENUM_CGU_CLKOUTSEL_CLKIN             (_ADI_MSK(0x00000000,uint32_t))  /* CLKOUTSEL: CLKIN */
-#define ENUM_CGU_CLKOUTSEL_CCLKDIV4          (_ADI_MSK(0x00000001,uint32_t))  /* CLKOUTSEL: CCLKn/4 */
-#define ENUM_CGU_CLKOUTSEL_GNDDIS            (_ADI_MSK(0x0000000B,uint32_t))  /* CLKOUTSEL: GND (Disable OUTCLK) */
-#define ENUM_CGU_CLKOUTSEL_SYSCLKDIV2        (_ADI_MSK(0x00000002,uint32_t))  /* CLKOUTSEL: SYSCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_SCLK0             (_ADI_MSK(0x00000003,uint32_t))  /* CLKOUTSEL: SCLK0 */
-#define ENUM_CGU_CLKOUTSEL_SCLK1             (_ADI_MSK(0x00000004,uint32_t))  /* CLKOUTSEL: SCLK1 */
-#define ENUM_CGU_CLKOUTSEL_DCLKDIV2          (_ADI_MSK(0x00000005,uint32_t))  /* CLKOUTSEL: DCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_OUTCLK            (_ADI_MSK(0x00000007,uint32_t))  /* CLKOUTSEL: OUTCLK */
-
-/* ==================================================
-        Dynamic Power Management Registers
-   ================================================== */
-
-/* =========================
-        DPM0
-   ========================= */
-#define REG_DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
-#define REG_DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
-#define REG_DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
-#define REG_DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
-#define REG_DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
-#define REG_DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
-#define REG_DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
-#define REG_DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
-#define REG_DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
-#define REG_DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
-#define REG_DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
-#define REG_DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
-#define REG_DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore n Register */
-
-/* =========================
-        DPM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CTL_LOCK                    31                               /* Lock */
-#define BITP_DPM_CTL_HIBERNATE                4                               /* Hibernate */
-#define BITP_DPM_CTL_DEEPSLEEP                3                               /* Deep Sleep */
-#define BITP_DPM_CTL_PLLDIS                   2                               /* PLL Disable */
-#define BITP_DPM_CTL_PLLBPCL                  1                               /* PLL Bypass Clear */
-#define BITP_DPM_CTL_PLLBPST                  0                               /* PLL Bypass Set */
-#define BITM_DPM_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CTL_HIBERNATE               (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate */
-#define BITM_DPM_CTL_DEEPSLEEP               (_ADI_MSK(0x00000008,uint32_t))  /* Deep Sleep */
-#define BITM_DPM_CTL_PLLDIS                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Disable */
-#define BITM_DPM_CTL_PLLBPCL                 (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass Clear */
-#define BITM_DPM_CTL_PLLBPST                 (_ADI_MSK(0x00000001,uint32_t))  /* PLL Bypass Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_STAT_PLLCFGERR              19                               /* PLL Configuration Error */
-#define BITP_DPM_STAT_HVBSYERR               18                               /* HV Busy Error */
-#define BITP_DPM_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_DPM_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_DPM_STAT_HVBSY                   9                               /* HV Busy */
-#define BITP_DPM_STAT_CCLKDIS                 8                               /* Core Clock(s) Disabled */
-#define BITP_DPM_STAT_PRVMODE                 4                               /* Previous Mode */
-#define BITP_DPM_STAT_CURMODE                 0                               /* Current Mode */
-#define BITM_DPM_STAT_PLLCFGERR              (_ADI_MSK(0x00080000,uint32_t))  /* PLL Configuration Error */
-#define BITM_DPM_STAT_HVBSYERR               (_ADI_MSK(0x00040000,uint32_t))  /* HV Busy Error */
-#define BITM_DPM_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_DPM_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_DPM_STAT_HVBSY                  (_ADI_MSK(0x00000200,uint32_t))  /* HV Busy */
-#define BITM_DPM_STAT_CCLKDIS                (_ADI_MSK(0x00000100,uint32_t))  /* Core Clock(s) Disabled */
-#define BITM_DPM_STAT_PRVMODE                (_ADI_MSK(0x000000F0,uint32_t))  /* Previous Mode */
-#define BITM_DPM_STAT_CURMODE                (_ADI_MSK(0x0000000F,uint32_t))  /* Current Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_CCBF_DIS_CCBF0               0                               /* Core Clock Buffer n Disable */
-#define BITP_DPM_CCBF_DIS_CCBF1               1                               /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_DIS_CCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_CCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_CCBF_EN_CCBF0                0                               /* Core Clock Buffer n Enable */
-#define BITP_DPM_CCBF_EN_CCBF1                1                               /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_EN_CCBF0               (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_CCBF1               (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_CCBF0              0                               /* Core Clock Buffer n Status */
-#define BITP_DPM_CCBF_STAT_CCBF1              1                               /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF0             (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF1             (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT_STKY                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF0         0                               /* Core Clock Buffer n Status - Sticky */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF1         1                               /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF0        (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF1        (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_SCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_SCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_SCBF_DIS_SCBF0               0                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF1               1                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF2               2                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF3               3                               /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_SCBF_DIS_SCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF2              (_ADI_MSK(0x00000004,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF3              (_ADI_MSK(0x00000008,uint32_t))  /* System Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_WAKE_EN_WS0                  0                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS1                  1                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS2                  2                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS3                  3                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS4                  4                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS5                  5                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS6                  6                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS7                  7                               /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_EN_WS0                 (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS1                 (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS2                 (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS3                 (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS4                 (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS5                 (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS6                 (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS7                 (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_POL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_POL_LOCK               31                               /* Lock */
-#define BITP_DPM_WAKE_POL_WS0                 0                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS1                 1                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS2                 2                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS3                 3                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS4                 4                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS5                 5                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS6                 6                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS7                 7                               /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_POL_WS0                (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS1                (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS2                (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS3                (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS4                (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS5                (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS6                (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS7                (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Polarity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_STAT_WS0                0                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS1                1                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS2                2                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS3                3                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS4                4                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS5                5                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS6                6                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS7                7                               /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS0               (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS1               (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS2               (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS3               (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS4               (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS5               (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS6               (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS7               (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_HIB_DIS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_HIB_DIS_LOCK                31                               /* Lock */
-#define BITP_DPM_HIB_DIS_HD0                  0                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD1                  1                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD2                  2                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD3                  3                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD4                  4                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD5                  5                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD6                  6                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD7                  7                               /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_HIB_DIS_HD0                 (_ADI_MSK(0x00000001,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD1                 (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD2                 (_ADI_MSK(0x00000004,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD3                 (_ADI_MSK(0x00000008,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD4                 (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD5                 (_ADI_MSK(0x00000020,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD6                 (_ADI_MSK(0x00000040,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD7                 (_ADI_MSK(0x00000080,uint32_t))  /* Hibernate Disable n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_PGCNTR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_PGCNTR_LOCK                 31                               /* Lock */
-#define BITP_DPM_PGCNTR_CNT                   0                               /* Power Good Count */
-#define BITM_DPM_PGCNTR_LOCK                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_PGCNTR_CNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Power Good Count */
-
-/* ==================================================
-        eFUSE Controller Registers
-   ================================================== */
-
-/* =========================
-        EFS0
-   ========================= */
-#define REG_EFS0_CTL                    0xFFCC0000         /* EFS0 Control Register */
-#define REG_EFS0_DAT0                   0xFFCC0008         /* EFS0 Data Register 0 */
-#define REG_EFS0_DAT1                   0xFFCC000C         /* EFS0 Data Register 1 */
-#define REG_EFS0_DAT2                   0xFFCC0010         /* EFS0 Data Register 2 */
-#define REG_EFS0_DAT3                   0xFFCC0014         /* EFS0 Data Register 3 */
-#define REG_EFS0_DAT4                   0xFFCC0018         /* EFS0 Data Register 4 */
-#define REG_EFS0_DAT5                   0xFFCC001C         /* EFS0 Data Register 5 */
-#define REG_EFS0_DAT6                   0xFFCC0020         /* EFS0 Data Register 6 */
-#define REG_EFS0_DAT7                   0xFFCC0024         /* EFS0 Data Register 7 */
-
-/* =========================
-        EFS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EFS_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EFS_CTL_READ                     0                               /* Read */
-#define BITM_EFS_CTL_READ                    (_ADI_MSK(0x00000001,uint32_t))  /* Read */
-
-/* ==================================================
-        Universal Serial Bus Controller Registers
-   ================================================== */
-
-/* =========================
-        USB0
-   ========================= */
-#define REG_USB0_FADDR                  0xFFCC1000         /* USB0 Function Address Register */
-#define REG_USB0_POWER                  0xFFCC1001         /* USB0 Power and Device Control Register */
-#define REG_USB0_INTRTX                 0xFFCC1002         /* USB0 Transmit Interrupt Register */
-#define REG_USB0_INTRRX                 0xFFCC1004         /* USB0 Receive Interrupt Register */
-#define REG_USB0_INTRTXE                0xFFCC1006         /* USB0 Transmit Interrupt Enable Register */
-#define REG_USB0_INTRRXE                0xFFCC1008         /* USB0 Receive Interrupt Enable Register */
-#define REG_USB0_IRQ                    0xFFCC100A         /* USB0 Common Interrupts Register */
-#define REG_USB0_IEN                    0xFFCC100B         /* USB0 Common Interrupts Enable Register */
-#define REG_USB0_FRAME                  0xFFCC100C         /* USB0 Frame Number Register */
-#define REG_USB0_INDEX                  0xFFCC100E         /* USB0 Index Register */
-#define REG_USB0_TESTMODE               0xFFCC100F         /* USB0 Testmode Register */
-#define REG_USB0_EPI_TXMAXP0            0xFFCC1010         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EPI_TXCSR_P0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EPI_TXCSR_H0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0I_CSR0_P            0xFFCC1012         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CSR0_H            0xFFCC1012         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXMAXP0            0xFFCC1014         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EPI_RXCSR_H0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXCSR_P0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CNT0              0xFFCC1018         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EPI_RXCNT0             0xFFCC1018         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EPI_TXTYPE0            0xFFCC101A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0I_TYPE0             0xFFCC101A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EPI_TXINTERVAL0        0xFFCC101B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0I_NAKLIMIT0         0xFFCC101B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EPI_RXTYPE0            0xFFCC101C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EPI_RXINTERVAL0        0xFFCC101D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0I_CFGDATA0          0xFFCC101F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_FIFOB0                 0xFFCC1020         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB1                 0xFFCC1024         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB2                 0xFFCC1028         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB3                 0xFFCC102C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB4                 0xFFCC1030         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB5                 0xFFCC1034         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB6                 0xFFCC1038         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB7                 0xFFCC103C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB8                 0xFFCC1040         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB9                 0xFFCC1044         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB10                0xFFCC1048         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB11                0xFFCC104C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOH0                 0xFFCC1020         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH1                 0xFFCC1024         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH2                 0xFFCC1028         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH3                 0xFFCC102C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH4                 0xFFCC1030         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH5                 0xFFCC1034         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH6                 0xFFCC1038         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH7                 0xFFCC103C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH8                 0xFFCC1040         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH9                 0xFFCC1044         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH10                0xFFCC1048         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH11                0xFFCC104C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFO0                  0xFFCC1020         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO1                  0xFFCC1024         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO2                  0xFFCC1028         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO3                  0xFFCC102C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO4                  0xFFCC1030         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO5                  0xFFCC1034         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO6                  0xFFCC1038         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO7                  0xFFCC103C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO8                  0xFFCC1040         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO9                  0xFFCC1044         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO10                 0xFFCC1048         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO11                 0xFFCC104C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_DEV_CTL                0xFFCC1060         /* USB0 Device Control Register */
-#define REG_USB0_TXFIFOSZ               0xFFCC1062         /* USB0 Transmit FIFO Size Register */
-#define REG_USB0_RXFIFOSZ               0xFFCC1063         /* USB0 Receive FIFO Size Register */
-#define REG_USB0_TXFIFOADDR             0xFFCC1064         /* USB0 Transmit FIFO Address Register */
-#define REG_USB0_RXFIFOADDR             0xFFCC1066         /* USB0 Receive FIFO Address Register */
-#define REG_USB0_EPINFO                 0xFFCC1078         /* USB0 Endpoint Information Register */
-#define REG_USB0_RAMINFO                0xFFCC1079         /* USB0 RAM Information Register */
-#define REG_USB0_LINKINFO               0xFFCC107A         /* USB0 Link Information Register */
-#define REG_USB0_VPLEN                  0xFFCC107B         /* USB0 VBUS Pulse Length Register */
-#define REG_USB0_HS_EOF1                0xFFCC107C         /* USB0 High-Speed EOF 1 Register */
-#define REG_USB0_FS_EOF1                0xFFCC107D         /* USB0 Full-Speed EOF 1 Register */
-#define REG_USB0_LS_EOF1                0xFFCC107E         /* USB0 Low-Speed EOF 1 Register */
-#define REG_USB0_SOFT_RST               0xFFCC107F         /* USB0 Software Reset Register */
-#define REG_USB0_MP0_TXFUNCADDR         0xFFCC1080         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP1_TXFUNCADDR         0xFFCC1088         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP2_TXFUNCADDR         0xFFCC1090         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP3_TXFUNCADDR         0xFFCC1098         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP4_TXFUNCADDR         0xFFCC10A0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP5_TXFUNCADDR         0xFFCC10A8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP6_TXFUNCADDR         0xFFCC10B0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP7_TXFUNCADDR         0xFFCC10B8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP8_TXFUNCADDR         0xFFCC10C0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP9_TXFUNCADDR         0xFFCC10C8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP10_TXFUNCADDR        0xFFCC10D0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP11_TXFUNCADDR        0xFFCC10D8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP0_TXHUBADDR          0xFFCC1082         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP1_TXHUBADDR          0xFFCC108A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP2_TXHUBADDR          0xFFCC1092         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP3_TXHUBADDR          0xFFCC109A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP4_TXHUBADDR          0xFFCC10A2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP5_TXHUBADDR          0xFFCC10AA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP6_TXHUBADDR          0xFFCC10B2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP7_TXHUBADDR          0xFFCC10BA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP8_TXHUBADDR          0xFFCC10C2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP9_TXHUBADDR          0xFFCC10CA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP10_TXHUBADDR         0xFFCC10D2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP11_TXHUBADDR         0xFFCC10DA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP0_TXHUBPORT          0xFFCC1083         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP1_TXHUBPORT          0xFFCC108B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP2_TXHUBPORT          0xFFCC1093         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP3_TXHUBPORT          0xFFCC109B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP4_TXHUBPORT          0xFFCC10A3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP5_TXHUBPORT          0xFFCC10AB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP6_TXHUBPORT          0xFFCC10B3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP7_TXHUBPORT          0xFFCC10BB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP8_TXHUBPORT          0xFFCC10C3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP9_TXHUBPORT          0xFFCC10CB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP10_TXHUBPORT         0xFFCC10D3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP11_TXHUBPORT         0xFFCC10DB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP0_RXFUNCADDR         0xFFCC1084         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP1_RXFUNCADDR         0xFFCC108C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP2_RXFUNCADDR         0xFFCC1094         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP3_RXFUNCADDR         0xFFCC109C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP4_RXFUNCADDR         0xFFCC10A4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP5_RXFUNCADDR         0xFFCC10AC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP6_RXFUNCADDR         0xFFCC10B4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP7_RXFUNCADDR         0xFFCC10BC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP8_RXFUNCADDR         0xFFCC10C4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP9_RXFUNCADDR         0xFFCC10CC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP10_RXFUNCADDR        0xFFCC10D4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP11_RXFUNCADDR        0xFFCC10DC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP0_RXHUBADDR          0xFFCC1086         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP1_RXHUBADDR          0xFFCC108E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP2_RXHUBADDR          0xFFCC1096         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP3_RXHUBADDR          0xFFCC109E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP4_RXHUBADDR          0xFFCC10A6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP5_RXHUBADDR          0xFFCC10AE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP6_RXHUBADDR          0xFFCC10B6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP7_RXHUBADDR          0xFFCC10BE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP8_RXHUBADDR          0xFFCC10C6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP9_RXHUBADDR          0xFFCC10CE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP10_RXHUBADDR         0xFFCC10D6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP11_RXHUBADDR         0xFFCC10DE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP0_RXHUBPORT          0xFFCC1087         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP1_RXHUBPORT          0xFFCC108F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP2_RXHUBPORT          0xFFCC1097         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP3_RXHUBPORT          0xFFCC109F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP4_RXHUBPORT          0xFFCC10A7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP5_RXHUBPORT          0xFFCC10AF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP6_RXHUBPORT          0xFFCC10B7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP7_RXHUBPORT          0xFFCC10BF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP8_RXHUBPORT          0xFFCC10C7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP9_RXHUBPORT          0xFFCC10CF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP10_RXHUBPORT         0xFFCC10D7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP11_RXHUBPORT         0xFFCC10DF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_EP0_TXMAXP             0xFFCC1100         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP1_TXMAXP             0xFFCC1110         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP2_TXMAXP             0xFFCC1120         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP3_TXMAXP             0xFFCC1130         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP4_TXMAXP             0xFFCC1140         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP5_TXMAXP             0xFFCC1150         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP6_TXMAXP             0xFFCC1160         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP7_TXMAXP             0xFFCC1170         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP8_TXMAXP             0xFFCC1180         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP9_TXMAXP             0xFFCC1190         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP10_TXMAXP            0xFFCC11A0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP11_TXMAXP            0xFFCC11B0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP0_CSR0_H             0xFFCC1102         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EP0_TXCSR_H            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP1_TXCSR_H            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP2_TXCSR_H            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP3_TXCSR_H            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP4_TXCSR_H            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP5_TXCSR_H            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP6_TXCSR_H            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP7_TXCSR_H            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP8_TXCSR_H            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP9_TXCSR_H            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP10_TXCSR_H           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP11_TXCSR_H           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0_CSR0_P             0xFFCC1102         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_TXCSR_P            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_TXCSR_P            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_TXCSR_P            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_TXCSR_P            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_TXCSR_P            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_TXCSR_P            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_TXCSR_P            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_TXCSR_P            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_TXCSR_P            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_TXCSR_P            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_TXCSR_P           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_TXCSR_P           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_RXMAXP             0xFFCC1104         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP1_RXMAXP             0xFFCC1114         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP2_RXMAXP             0xFFCC1124         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP3_RXMAXP             0xFFCC1134         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP4_RXMAXP             0xFFCC1144         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP5_RXMAXP             0xFFCC1154         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP6_RXMAXP             0xFFCC1164         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP7_RXMAXP             0xFFCC1174         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP8_RXMAXP             0xFFCC1184         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP9_RXMAXP             0xFFCC1194         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP10_RXMAXP            0xFFCC11A4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP11_RXMAXP            0xFFCC11B4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP0_RXCSR_H            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP1_RXCSR_H            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP2_RXCSR_H            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP3_RXCSR_H            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP4_RXCSR_H            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP5_RXCSR_H            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP6_RXCSR_H            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP7_RXCSR_H            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP8_RXCSR_H            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP9_RXCSR_H            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP10_RXCSR_H           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP11_RXCSR_H           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP0_RXCSR_P            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_RXCSR_P            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_RXCSR_P            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_RXCSR_P            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_RXCSR_P            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_RXCSR_P            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_RXCSR_P            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_RXCSR_P            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_RXCSR_P            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_RXCSR_P            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_RXCSR_P           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_RXCSR_P           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_CNT0               0xFFCC1108         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EP0_RXCNT              0xFFCC1108         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP1_RXCNT              0xFFCC1118         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP2_RXCNT              0xFFCC1128         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP3_RXCNT              0xFFCC1138         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP4_RXCNT              0xFFCC1148         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP5_RXCNT              0xFFCC1158         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP6_RXCNT              0xFFCC1168         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP7_RXCNT              0xFFCC1178         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP8_RXCNT              0xFFCC1188         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP9_RXCNT              0xFFCC1198         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP10_RXCNT             0xFFCC11A8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP11_RXCNT             0xFFCC11B8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP0_TYPE0              0xFFCC110A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EP0_TXTYPE             0xFFCC110A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP1_TXTYPE             0xFFCC111A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP2_TXTYPE             0xFFCC112A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP3_TXTYPE             0xFFCC113A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP4_TXTYPE             0xFFCC114A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP5_TXTYPE             0xFFCC115A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP6_TXTYPE             0xFFCC116A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP7_TXTYPE             0xFFCC117A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP8_TXTYPE             0xFFCC118A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP9_TXTYPE             0xFFCC119A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP10_TXTYPE            0xFFCC11AA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP11_TXTYPE            0xFFCC11BA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0_NAKLIMIT0          0xFFCC110B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EP0_TXINTERVAL         0xFFCC110B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP1_TXINTERVAL         0xFFCC111B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP2_TXINTERVAL         0xFFCC112B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP3_TXINTERVAL         0xFFCC113B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP4_TXINTERVAL         0xFFCC114B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP5_TXINTERVAL         0xFFCC115B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP6_TXINTERVAL         0xFFCC116B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP7_TXINTERVAL         0xFFCC117B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP8_TXINTERVAL         0xFFCC118B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP9_TXINTERVAL         0xFFCC119B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP10_TXINTERVAL        0xFFCC11AB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP11_TXINTERVAL        0xFFCC11BB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0_RXTYPE             0xFFCC110C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP1_RXTYPE             0xFFCC111C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP2_RXTYPE             0xFFCC112C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP3_RXTYPE             0xFFCC113C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP4_RXTYPE             0xFFCC114C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP5_RXTYPE             0xFFCC115C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP6_RXTYPE             0xFFCC116C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP7_RXTYPE             0xFFCC117C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP8_RXTYPE             0xFFCC118C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP9_RXTYPE             0xFFCC119C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP10_RXTYPE            0xFFCC11AC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP11_RXTYPE            0xFFCC11BC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP0_RXINTERVAL         0xFFCC110D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP1_RXINTERVAL         0xFFCC111D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP2_RXINTERVAL         0xFFCC112D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP3_RXINTERVAL         0xFFCC113D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP4_RXINTERVAL         0xFFCC114D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP5_RXINTERVAL         0xFFCC115D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP6_RXINTERVAL         0xFFCC116D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP7_RXINTERVAL         0xFFCC117D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP8_RXINTERVAL         0xFFCC118D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP9_RXINTERVAL         0xFFCC119D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP10_RXINTERVAL        0xFFCC11AD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP11_RXINTERVAL        0xFFCC11BD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0_CFGDATA0           0xFFCC110F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_DMA_IRQ                0xFFCC1200         /* USB0 DMA Interrupt Register */
-#define REG_USB0_DMA0_CTL               0xFFCC1204         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA1_CTL               0xFFCC1214         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA2_CTL               0xFFCC1224         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA3_CTL               0xFFCC1234         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA4_CTL               0xFFCC1244         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA5_CTL               0xFFCC1254         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA6_CTL               0xFFCC1264         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA7_CTL               0xFFCC1274         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA0_ADDR              0xFFCC1208         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA1_ADDR              0xFFCC1218         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA2_ADDR              0xFFCC1228         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA3_ADDR              0xFFCC1238         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA4_ADDR              0xFFCC1248         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA5_ADDR              0xFFCC1258         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA6_ADDR              0xFFCC1268         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA7_ADDR              0xFFCC1278         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA0_CNT               0xFFCC120C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA1_CNT               0xFFCC121C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA2_CNT               0xFFCC122C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA3_CNT               0xFFCC123C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA4_CNT               0xFFCC124C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA5_CNT               0xFFCC125C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA6_CNT               0xFFCC126C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA7_CNT               0xFFCC127C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_RQPKTCNT0              0xFFCC1300         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT1              0xFFCC1304         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT2              0xFFCC1308         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT3              0xFFCC130C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT4              0xFFCC1310         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT5              0xFFCC1314         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT6              0xFFCC1318         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT7              0xFFCC131C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT8              0xFFCC1320         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT9              0xFFCC1324         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT10             0xFFCC1328         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_CT_UCH                 0xFFCC1344         /* USB0 Chirp Timeout Register */
-#define REG_USB0_CT_HHSRTN              0xFFCC1346         /* USB0 Host High Speed Return to Normal Register */
-#define REG_USB0_CT_HSBT                0xFFCC1348         /* USB0 High Speed Timeout Register */
-#define REG_USB0_LPM_ATTR               0xFFCC1360         /* USB0 LPM Attribute Register */
-#define REG_USB0_LPM_CTL                0xFFCC1362         /* USB0 LPM Control Register */
-#define REG_USB0_LPM_IEN                0xFFCC1363         /* USB0 LPM Interrupt Enable Register */
-#define REG_USB0_LPM_IRQ                0xFFCC1364         /* USB0 LPM Interrupt Status Register */
-#define REG_USB0_LPM_FADDR              0xFFCC1365         /* USB0 LPM Function Address Register */
-#define REG_USB0_VBUS_CTL               0xFFCC1380         /* USB0 VBUS Control Register */
-#define REG_USB0_BAT_CHG                0xFFCC1381         /* USB0 Battery Charging Control Register */
-#define REG_USB0_PHY_CTL                0xFFCC1394         /* USB0 PHY Control Register */
-#define REG_USB0_PLL_OSC                0xFFCC1398         /* USB0 PLL and Oscillator Control Register */
-
-/* =========================
-        USB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FADDR                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FADDR_VALUE                  0                               /* Function Address Value */
-#define BITM_USB_FADDR_VALUE                 (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_POWER                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_POWER_ISOUPDT                7                               /* ISO Update Enable */
-#define BITP_USB_POWER_SOFTCONN               6                               /* Soft Connect/Disconnect Enable */
-#define BITP_USB_POWER_HSEN                   5                               /* High Speed Mode Enable */
-#define BITP_USB_POWER_HSMODE                 4                               /* High Speed Mode */
-#define BITP_USB_POWER_RESET                  3                               /* Reset USB */
-#define BITP_USB_POWER_RESUME                 2                               /* Resume Mode */
-#define BITP_USB_POWER_SUSPEND                1                               /* Suspend Mode */
-#define BITP_USB_POWER_SUSEN                  0                               /* SUSPENDM Output Enable */
-
-#define BITM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISO Update Enable */
-#define ENUM_USB_POWER_NO_ISOUPDT            (_ADI_MSK(0x00000000,uint8_t))   /* ISOUPDT: Disable ISO Update */
-#define ENUM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISOUPDT: Enable ISO Update */
-
-#define BITM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* Soft Connect/Disconnect Enable */
-#define ENUM_USB_POWER_NO_SOFTCONN           (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCONN: Disable Soft Connect/Disconnect */
-#define ENUM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* SOFTCONN: Enable Soft Connect/Disconnect */
-
-#define BITM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* High Speed Mode Enable */
-#define ENUM_USB_POWER_HSDIS                 (_ADI_MSK(0x00000000,uint8_t))   /* HSEN: Disable Negotiation for HS Mode */
-#define ENUM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* HSEN: Enable Negotiation for HS Mode */
-
-#define BITM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* High Speed Mode */
-#define ENUM_USB_POWER_NO_HSMODE             (_ADI_MSK(0x00000000,uint8_t))   /* HSMODE: Full Speed Mode (HS fail during reset) */
-#define ENUM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* HSMODE: High Speed Mode (HS success during reset) */
-
-#define BITM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* Reset USB */
-#define ENUM_USB_POWER_NO_RESET              (_ADI_MSK(0x00000000,uint8_t))   /* RESET: No Reset */
-#define ENUM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* RESET: Reset USB */
-
-#define BITM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* Resume Mode */
-#define ENUM_USB_POWER_NO_RESUME             (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Resume Signaling */
-#define ENUM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* RESUME: Enable Resume Signaling */
-
-#define BITM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* Suspend Mode */
-#define ENUM_USB_POWER_NO_SUSPEND            (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Suspend Mode (Host) */
-#define ENUM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* SUSPEND: Enable Suspend Mode (Host) */
-
-#define BITM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPENDM Output Enable */
-#define ENUM_USB_POWER_SUSDIS                (_ADI_MSK(0x00000000,uint8_t))   /* SUSEN: Disable SUSPENDM Output */
-#define ENUM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSEN: Enable SUSPENDM Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTX_EP11                 11                               /* End Point 11 Tx Interrupt */
-#define BITP_USB_INTRTX_EP10                 10                               /* End Point 10 Tx Interrupt */
-#define BITP_USB_INTRTX_EP9                   9                               /* End Point 9 Tx Interrupt */
-#define BITP_USB_INTRTX_EP8                   8                               /* End Point 8 Tx Interrupt */
-#define BITP_USB_INTRTX_EP7                   7                               /* End Point 7 Tx Interrupt */
-#define BITP_USB_INTRTX_EP6                   6                               /* End Point 6 Tx Interrupt */
-#define BITP_USB_INTRTX_EP5                   5                               /* End Point 5 Tx Interrupt */
-#define BITP_USB_INTRTX_EP4                   4                               /* End Point 4 Tx Interrupt */
-#define BITP_USB_INTRTX_EP3                   3                               /* End Point 3 Tx Interrupt */
-#define BITP_USB_INTRTX_EP2                   2                               /* End Point 2 Tx Interrupt */
-#define BITP_USB_INTRTX_EP1                   1                               /* End Point 1 Tx Interrupt */
-#define BITP_USB_INTRTX_EP0                   0                               /* End Point 0 Tx Interrupt */
-#define BITM_USB_INTRTX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt */
-#define BITM_USB_INTRTX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt */
-#define BITM_USB_INTRTX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt */
-#define BITM_USB_INTRTX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt */
-#define BITM_USB_INTRTX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt */
-#define BITM_USB_INTRTX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt */
-#define BITM_USB_INTRTX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt */
-#define BITM_USB_INTRTX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt */
-#define BITM_USB_INTRTX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt */
-#define BITM_USB_INTRTX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt */
-#define BITM_USB_INTRTX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt */
-#define BITM_USB_INTRTX_EP0                  (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRX_EP11                 11                               /* End Point 11 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP10                 10                               /* End Point 10 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP9                   9                               /* End Point 9 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP8                   8                               /* End Point 8 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP7                   7                               /* End Point 7 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP6                   6                               /* End Point 6 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP5                   5                               /* End Point 5 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP4                   4                               /* End Point 4 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP3                   3                               /* End Point 3 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP2                   2                               /* End Point 2 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP1                   1                               /* End Point 1 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTXE_EP11                11                               /* End Point 11 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP10                10                               /* End Point 10 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP9                  9                               /* End Point 9 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP8                  8                               /* End Point 8 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP7                  7                               /* End Point 7 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP6                  6                               /* End Point 6 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP5                  5                               /* End Point 5 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP4                  4                               /* End Point 4 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP3                  3                               /* End Point 3 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP2                  2                               /* End Point 2 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP1                  1                               /* End Point 1 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP0                  0                               /* End Point 0 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP0                 (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRXE_EP11                11                               /* End Point 11 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP10                10                               /* End Point 10 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP9                  9                               /* End Point 9 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP8                  8                               /* End Point 8 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP7                  7                               /* End Point 7 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP6                  6                               /* End Point 6 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP5                  5                               /* End Point 5 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP4                  4                               /* End Point 4 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP3                  3                               /* End Point 3 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP2                  2                               /* End Point 2 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP1                  1                               /* End Point 1 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IRQ                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IRQ_VBUSERR                  7                               /* VBUS Threshold Indicator */
-#define BITP_USB_IRQ_SESSREQ                  6                               /* Session Request Indicator */
-#define BITP_USB_IRQ_DISCON                   5                               /* Disconnect Indicator */
-#define BITP_USB_IRQ_CON                      4                               /* Connection Indicator */
-#define BITP_USB_IRQ_SOF                      3                               /* Start-of-frame Indicator */
-#define BITP_USB_IRQ_RSTBABBLE                2                               /* Reset/Babble Indicator */
-#define BITP_USB_IRQ_RESUME                   1                               /* Resume Indicator */
-#define BITP_USB_IRQ_SUSPEND                  0                               /* Suspend Indicator */
-
-#define BITM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator */
-#define ENUM_USB_IRQ_NO_VBUSERR              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: No Interrupt */
-#define ENUM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Interrupt Pending */
-
-#define BITM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator */
-#define ENUM_USB_IRQ_NO_SESSREQ              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: No Interrupt */
-#define ENUM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Interrupt Pending */
-
-#define BITM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator */
-#define ENUM_USB_IRQ_NO_DISCON               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: No Interrupt */
-#define ENUM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Interrupt Pending */
-
-#define BITM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator */
-#define ENUM_USB_IRQ_NO_CON                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: No Interrupt */
-#define ENUM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* CON: Interrupt Pending */
-
-#define BITM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator */
-#define ENUM_USB_IRQ_NO_SOF                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: No Interrupt */
-#define ENUM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Interrupt Pending */
-
-#define BITM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator */
-#define ENUM_USB_IRQ_NO_RSTBABBLE            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: No Interrupt */
-#define ENUM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Interrupt Pending */
-
-#define BITM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator */
-#define ENUM_USB_IRQ_NO_RESUME               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: No Interrupt */
-#define ENUM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Interrupt Pending */
-
-#define BITM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator */
-#define ENUM_USB_IRQ_NO_SUSPEND              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: No Interrupt */
-#define ENUM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IEN                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IEN_VBUSERR                  7                               /* VBUS Threshold Indicator Interrupt Enable */
-#define BITP_USB_IEN_SESSREQ                  6                               /* Session Request Indicator Interrupt Enable */
-#define BITP_USB_IEN_DISCON                   5                               /* Disconnect Indicator Interrupt Enable */
-#define BITP_USB_IEN_CON                      4                               /* Connection Indicator Interrupt Enable */
-#define BITP_USB_IEN_SOF                      3                               /* Start-of-frame Indicator Interrupt Enable */
-#define BITP_USB_IEN_RSTBABBLE                2                               /* Reset/Babble Indicator Interrupt Enable */
-#define BITP_USB_IEN_RESUME                   1                               /* Resume Indicator Interrupt Enable */
-#define BITP_USB_IEN_SUSPEND                  0                               /* Suspend Indicator Interrupt Enable */
-
-#define BITM_USB_IEN_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator Interrupt Enable */
-#define ENUM_USB_IEN_VBUSERRDIS              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: Disable Interrupt */
-#define ENUM_USB_IEN_VBUSERREN               (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Enable Interrupt */
-
-#define BITM_USB_IEN_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SESSREQDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: Disable Interrupt */
-#define ENUM_USB_IEN_SESSREQEN               (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Enable Interrupt */
-
-#define BITM_USB_IEN_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator Interrupt Enable */
-#define ENUM_USB_IEN_DISCONDIS               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: Disable Interrupt */
-#define ENUM_USB_IEN_DISCONEN                (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Enable Interrupt */
-
-#define BITM_USB_IEN_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator Interrupt Enable */
-#define ENUM_USB_IEN_CONDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: Disable Interrupt */
-#define ENUM_USB_IEN_CONEN                   (_ADI_MSK(0x00000010,uint8_t))   /* CON: Enable Interrupt */
-
-#define BITM_USB_IEN_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SOFDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: Disable Interrupt */
-#define ENUM_USB_IEN_SOFEN                   (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Enable Interrupt */
-
-#define BITM_USB_IEN_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RSTBABBLEDIS            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: Disable Interrupt */
-#define ENUM_USB_IEN_RSTBABBLEEN             (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Enable Interrupt */
-
-#define BITM_USB_IEN_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RESUMEDIS               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Interrupt */
-#define ENUM_USB_IEN_RESUMEEN                (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Enable Interrupt */
-
-#define BITM_USB_IEN_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SUSPENDDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Interrupt */
-#define ENUM_USB_IEN_SUSPENDEN               (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Enable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FRAME                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FRAME_VALUE                  0                               /* Frame Number Value */
-#define BITM_USB_FRAME_VALUE                 (_ADI_MSK(0x000007FF,uint16_t))  /* Frame Number Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INDEX                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INDEX_EP                     0                               /* Endpoint Index */
-#define BITM_USB_INDEX_EP                    (_ADI_MSK(0x0000000F,uint8_t))   /* Endpoint Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TESTMODE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TESTMODE_FIFOACCESS          6                               /* FIFO Access */
-#define BITP_USB_TESTMODE_TESTPACKET          3                               /* Test_Packet Mode */
-#define BITP_USB_TESTMODE_TESTK               2                               /* Test_K Mode */
-#define BITP_USB_TESTMODE_TESTJ               1                               /* Test_J Mode */
-#define BITP_USB_TESTMODE_TESTSE0NAK          0                               /* Test SE0 NAK */
-#define BITM_USB_TESTMODE_FIFOACCESS         (_ADI_MSK(0x00000040,uint8_t))   /* FIFO Access */
-#define BITM_USB_TESTMODE_TESTPACKET         (_ADI_MSK(0x00000008,uint8_t))   /* Test_Packet Mode */
-#define BITM_USB_TESTMODE_TESTK              (_ADI_MSK(0x00000004,uint8_t))   /* Test_K Mode */
-#define BITM_USB_TESTMODE_TESTJ              (_ADI_MSK(0x00000002,uint8_t))   /* Test_J Mode */
-#define BITM_USB_TESTMODE_TESTSE0NAK         (_ADI_MSK(0x00000001,uint8_t))   /* Test SE0 NAK */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_TXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_TXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_TXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_P_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_P_ISO             14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EPI_TXCSR_P_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_P_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_P_INCOMPTX         7                               /* Incomplete Tx */
-#define BITP_USB_EPI_TXCSR_P_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_SENTSTALL        5                               /* Sent STALL */
-#define BITP_USB_EPI_TXCSR_P_SENDSTALL        4                               /* Send STALL */
-#define BITP_USB_EPI_TXCSR_P_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_P_URUNERR          2                               /* Underrun Error */
-#define BITP_USB_EPI_TXCSR_P_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_P_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_P_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EPI_TXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EPI_TXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_P_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_P_INCOMPTX        (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EPI_TXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EPI_TXCSR_P_INCOMP          (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EPI_TXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_P_SENTSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_P_STALSNT         (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_TXCSR_P_SENDSTALL       (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EPI_TXCSR_P_STALL           (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EPI_TXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_P_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EPI_TXCSR_P_NO_URUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EPI_TXCSR_P_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FIFONE       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_P_FIFONE          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_P_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_H_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_H_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_H_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_H_DATGLEN          9                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_TXCSR_H_DATGL            8                               /* Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_NAKTOINCMP       7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EPI_TXCSR_H_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_RXSTALL          5                               /* Rx STALL */
-#define BITP_USB_EPI_TXCSR_H_SETUPPKT         4                               /* Setup Packet */
-#define BITP_USB_EPI_TXCSR_H_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXTOERR          2                               /* Tx Timeout Error */
-#define BITP_USB_EPI_TXCSR_H_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_H_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGLEN      (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EPI_TXCSR_H_NAKTOINCMP      (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EPI_TXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EPI_TXCSR_H_NAKTO           (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EPI_TXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_TXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EPI_TXCSR_H_NO_SETUPPK      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EPI_TXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_H_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EPI_TXCSR_H_NO_TXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_NEFIFO       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_H_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_P_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_P_SSETUPEND         7                               /* Service Setup End */
-#define BITP_USB_EP0I_CSR_P_SPKTRDY           6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_SENDSTALL         5                               /* Send Stall */
-#define BITP_USB_EP0I_CSR_P_SETUPEND          4                               /* Setup End */
-#define BITP_USB_EP0I_CSR_P_DATAEND           3                               /* Data End */
-#define BITP_USB_EP0I_CSR_P_SENTSTALL         2                               /* Sent Stall */
-#define BITP_USB_EP0I_CSR_P_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_P_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_P_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0I_CSR_P_NOSSETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_SPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0I_CSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0I_CSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0I_CSR_P_NO_SETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0I_CSR_P_NO_DATAEND       (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0I_CSR_P_SENTSTALL        (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_P_STALSNT          (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0I_CSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_H_DISPING          11                               /* Disable Ping */
-#define BITP_USB_EP0I_CSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0I_CSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP0I_CSR_H_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_H_NAKTO             7                               /* NAK Timeout */
-#define BITP_USB_EP0I_CSR_H_STATUSPKT         6                               /* Status Packet */
-#define BITP_USB_EP0I_CSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP0I_CSR_H_TOERR             4                               /* Timeout Error */
-#define BITP_USB_EP0I_CSR_H_SETUPPKT          3                               /* Setup Packet */
-#define BITP_USB_EP0I_CSR_H_RXSTALL           2                               /* Rx Stall */
-#define BITP_USB_EP0I_CSR_H_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0I_CSR_H_NO_DISPING       (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0I_CSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0I_CSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0I_CSR_H_NO_DATATGL       (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0I_CSR_H_DATATGL          (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0I_CSR_H_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_H_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0I_CSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0I_CSR_H_STATUSPKT        (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_STATPKT       (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_STATPKT          (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0I_CSR_H_NO_TOERR         (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_SETUPPKT      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0I_CSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_RXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_RXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_RXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_RXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_H_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_AUTOREQ         14                               /* Auto Request Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_H_PIDERR          12                               /* Packet ID Error */
-#define BITP_USB_EPI_RXCSR_H_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_H_DATGLEN         10                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_RXCSR_H_DATGL            9                               /* Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_H_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_RXSTALL          6                               /* Rx STALL */
-#define BITP_USB_EPI_RXCSR_H_REQPKT           5                               /* Request Packet */
-#define BITP_USB_EPI_RXCSR_H_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_H_NAKTODERR        3                               /* NAK Timeout Data Error */
-#define BITP_USB_EPI_RXCSR_H_RXTOERR          2                               /* Rx Timeout Error */
-#define BITP_USB_EPI_RXCSR_H_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_H_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOREQ      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_PIDERR       (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_RXCSR_H_DATGLDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EPI_RXCSR_H_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_H_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_H_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_H_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EPI_RXCSR_H_NO_REQPKT       (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EPI_RXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_H_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_H_NAKTODERR       (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_NAKTO           (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EPI_RXCSR_H_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_H_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_H_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_P_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_P_ISO             14                               /* Isochronous Transfers */
-#define BITP_USB_EPI_RXCSR_P_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_P_DNYETPERR       12                               /* Disable NYET Handshake */
-#define BITP_USB_EPI_RXCSR_P_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_P_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_P_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_P_SENTSTALL        6                               /* Sent STALL */
-#define BITP_USB_EPI_RXCSR_P_SENDSTALL        5                               /* Send STALL */
-#define BITP_USB_EPI_RXCSR_P_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_P_DATAERR          3                               /* Data Error */
-#define BITP_USB_EPI_RXCSR_P_ORUNERR          2                               /* OUT Run Error */
-#define BITP_USB_EPI_RXCSR_P_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_P_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_P_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EPI_RXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EPI_RXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_P_DNYETPERR       (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERREN       (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERRDIS      (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_P_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_P_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_P_SENTSTALL       (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_STALSNT         (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_RXCSR_P_SENDSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_STALL           (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_P_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_DATAERR      (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_ORUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EPI_RXCSR_P_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_P_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_P_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CNT_RXCNT               0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0I_CNT_RXCNT              (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCNT_EPRXCNT            0                               /* EP Rx Count */
-#define BITM_USB_EPI_RXCNT_EPRXCNT           (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_TXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_TXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_TXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_TXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_TXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_TXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_TXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_TXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_TXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_TXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_TXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_TXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_TXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_TXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_TYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_TYPE_SPEED              0                               /* Speed of Operation Value */
-#define BITM_USB_EP0I_TYPE_SPEED             (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_NAKLIMIT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_NAKLIMIT_VALUE          0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0I_NAKLIMIT_VALUE         (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_RXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_RXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_RXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_RXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_RXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_RXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_RXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_RXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_RXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_RXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_RXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_RXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_RXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_RXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CFGDATA                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CFGDATA_MPRX            7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_MPTX            6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_BIGEND          5                               /* Big Endian Data */
-#define BITP_USB_EP0I_CFGDATA_HBRX            4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_HBTX            3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_DYNFIFO         2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0I_CFGDATA_SOFTCON         1                               /* Soft Connect Enable */
-#define BITP_USB_EP0I_CFGDATA_UTMIWID         0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0I_CFGDATA_MPRX           (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPRXEN         (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_MPTX           (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPTXEN         (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_BIGEND         (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDDIS      (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDEN       (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0I_CFGDATA_HBRX           (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0I_CFGDATA_HBRXEN         (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0I_CFGDATA_HBTX           (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0I_CFGDATA_HBTXEN         (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0I_CFGDATA_DYNFIFO        (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZDIS       (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZEN        (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0I_CFGDATA_SOFTCON        (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONDIS      (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONEN       (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0I_CFGDATA_UTMIWID        (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID8       (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID16      (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DEV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DEV_CTL_BDEVICE              7                               /* A or B Devices Indicator */
-#define BITP_USB_DEV_CTL_FSDEV                6                               /* Full or High-Speed Indicator */
-#define BITP_USB_DEV_CTL_LSDEV                5                               /* Low-Speed Indicator */
-#define BITP_USB_DEV_CTL_VBUS                 3                               /* VBUS Level Indicator */
-#define BITP_USB_DEV_CTL_HOSTMODE             2                               /* Host Mode Indicator */
-#define BITP_USB_DEV_CTL_HOSTREQ              1                               /* Host Negotiation Request */
-#define BITP_USB_DEV_CTL_SESSION              0                               /* Session Indicator */
-
-#define BITM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* A or B Devices Indicator */
-#define ENUM_USB_DEV_CTL_ADEVICE             (_ADI_MSK(0x00000000,uint8_t))   /* BDEVICE: A Device Detected */
-#define ENUM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* BDEVICE: B Device Detected */
-
-#define BITM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* Full or High-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_FSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* FSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* FSDEV: Full or High Speed Detected */
-
-#define BITM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* Low-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_LSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* LSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* LSDEV: Low Speed Detected */
-
-#define BITM_USB_DEV_CTL_VBUS                (_ADI_MSK(0x00000018,uint8_t))   /* VBUS Level Indicator */
-#define ENUM_USB_DEV_CTL_VBUS_BS             (_ADI_MSK(0x00000000,uint8_t))   /* VBUS: Below SessionEnd */
-#define ENUM_USB_DEV_CTL_VBUS_ASBA           (_ADI_MSK(0x00000008,uint8_t))   /* VBUS: Above SessionEnd, below AValid */
-#define ENUM_USB_DEV_CTL_VBUS_AABV           (_ADI_MSK(0x00000010,uint8_t))   /* VBUS: Above AValid, below VBUSValid */
-#define ENUM_USB_DEV_CTL_VBUS_AV             (_ADI_MSK(0x00000018,uint8_t))   /* VBUS: Above VBUSValid */
-
-#define BITM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* Host Mode Indicator */
-#define ENUM_USB_DEV_CTL_NO_HOSTMODE         (_ADI_MSK(0x00000000,uint8_t))   /* HOSTMODE: Peripheral Mode */
-#define ENUM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* HOSTMODE: Host Mode */
-
-#define BITM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* Host Negotiation Request */
-#define ENUM_USB_DEV_CTL_NO_HOSTREQ          (_ADI_MSK(0x00000000,uint8_t))   /* HOSTREQ: No Request */
-#define ENUM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* HOSTREQ: Place Request */
-
-#define BITM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* Session Indicator */
-#define ENUM_USB_DEV_CTL_NO_SESSION          (_ADI_MSK(0x00000000,uint8_t))   /* SESSION: Not Detected */
-#define ENUM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* SESSION: Detected Session */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_TXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_TXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_TXFIFOSZ_DPNDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_TXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_TXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_TXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_TXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_TXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_TXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_TXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_TXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_TXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_TXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_TXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_TXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_RXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_RXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_RXFIFOSZ_DPBDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_RXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_RXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_RXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_RXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_RXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_RXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_RXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_RXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_RXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_RXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_RXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_RXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOADDR_VALUE             0                               /* Tx FIFO Start Address */
-#define BITM_USB_TXFIFOADDR_VALUE            (_ADI_MSK(0x00001FFF,uint16_t))  /* Tx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOADDR_VALUE             0                               /* Rx FIFO Start Address */
-#define BITM_USB_RXFIFOADDR_VALUE            (_ADI_MSK(0x00000FFF,uint16_t))  /* Rx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPINFO                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPINFO_RXEP                  4                               /* Rx Endpoints */
-#define BITP_USB_EPINFO_TXEP                  0                               /* Tx Endpoints */
-#define BITM_USB_EPINFO_RXEP                 (_ADI_MSK(0x000000F0,uint8_t))   /* Rx Endpoints */
-#define BITM_USB_EPINFO_TXEP                 (_ADI_MSK(0x0000000F,uint8_t))   /* Tx Endpoints */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RAMINFO                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RAMINFO_DMACHANS             4                               /* DMA Channels */
-#define BITP_USB_RAMINFO_RAMBITS              0                               /* RAM Address Bits */
-#define BITM_USB_RAMINFO_DMACHANS            (_ADI_MSK(0x000000F0,uint8_t))   /* DMA Channels */
-#define BITM_USB_RAMINFO_RAMBITS             (_ADI_MSK(0x0000000F,uint8_t))   /* RAM Address Bits */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LINKINFO                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LINKINFO_WTCON               4                               /* Wait for Connect/Disconnect */
-#define BITP_USB_LINKINFO_WTID                0                               /* Wait from ID Pull-up */
-#define BITM_USB_LINKINFO_WTCON              (_ADI_MSK(0x000000F0,uint8_t))   /* Wait for Connect/Disconnect */
-#define BITM_USB_LINKINFO_WTID               (_ADI_MSK(0x0000000F,uint8_t))   /* Wait from ID Pull-up */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_SOFT_RST                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_SOFT_RST_RSTX                1                               /* Reset USB XCLK Domain */
-#define BITP_USB_SOFT_RST_RST                 0                               /* Reset USB CLK Domain */
-
-#define BITM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* Reset USB XCLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RSTX            (_ADI_MSK(0x00000000,uint8_t))   /* RSTX: No Reset */
-#define ENUM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* RSTX: Reset USB XCLK Domain */
-
-#define BITM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* Reset USB CLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RST             (_ADI_MSK(0x00000000,uint8_t))   /* RST: No Reset */
-#define ENUM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* RST: Reset USB CLK Domain */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXFUNCADDR_VALUE          0                               /* Tx Function Address Value */
-#define BITM_USB_MP_TXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Tx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_TXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_TXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_TXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_TXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXFUNCADDR_VALUE          0                               /* Rx Function Address Value */
-#define BITM_USB_MP_RXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Rx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_RXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_RXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_RXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_RXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_TXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_TXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_TXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_H                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_H_DISPING           11                               /* Disable Ping */
-#define BITP_USB_EP0_CSR_H_DATGLEN           10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0_CSR_H_DATGL              9                               /* Data Toggle */
-#define BITP_USB_EP0_CSR_H_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_H_NAKTO              7                               /* NAK Timeout */
-#define BITP_USB_EP0_CSR_H_STATUSPKT          6                               /* Status Packet */
-#define BITP_USB_EP0_CSR_H_REQPKT             5                               /* Request Packet */
-#define BITP_USB_EP0_CSR_H_TOERR              4                               /* Timeout Error */
-#define BITP_USB_EP0_CSR_H_SETUPPKT           3                               /* Setup Packet */
-#define BITP_USB_EP0_CSR_H_RXSTALL            2                               /* Rx Stall */
-#define BITP_USB_EP0_CSR_H_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_H_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0_CSR_H_NO_DISPING        (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0_CSR_H_NO_DATGLEN        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0_CSR_H_DATGL             (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0_CSR_H_NO_DATATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0_CSR_H_DATATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0_CSR_H_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_H_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_H_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0_CSR_H_NO_NAKTO          (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0_CSR_H_STATUSPKT         (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0_CSR_H_NO_STATPKT        (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_STATPKT           (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0_CSR_H_NO_REQPKT         (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0_CSR_H_NO_TOERR          (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0_CSR_H_NO_SETUPPKT       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0_CSR_H_NO_RXSTALL        (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_RXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_H_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_H_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_H_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_H_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_H_DATGLEN           9                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_TXCSR_H_DATGL             8                               /* Data Toggle */
-#define BITP_USB_EP_TXCSR_H_NAKTOINCMP        7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EP_TXCSR_H_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_H_RXSTALL           5                               /* Rx STALL */
-#define BITP_USB_EP_TXCSR_H_SETUPPKT          4                               /* Setup Packet */
-#define BITP_USB_EP_TXCSR_H_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_H_TXTOERR           2                               /* Tx Timeout Error */
-#define BITP_USB_EP_TXCSR_H_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_H_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_H_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EP_TXCSR_H_NAKTOINCMP       (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EP_TXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EP_TXCSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EP_TXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_TXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP_TXCSR_H_NO_SETUPPK       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EP_TXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_H_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EP_TXCSR_H_NO_TXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_NEFIFO        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_H_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_P                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_P_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_P_SSETUPEND          7                               /* Service Setup End */
-#define BITP_USB_EP0_CSR_P_SPKTRDY            6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0_CSR_P_SENDSTALL          5                               /* Send Stall */
-#define BITP_USB_EP0_CSR_P_SETUPEND           4                               /* Setup End */
-#define BITP_USB_EP0_CSR_P_DATAEND            3                               /* Data End */
-#define BITP_USB_EP0_CSR_P_SENTSTALL          2                               /* Sent Stall */
-#define BITP_USB_EP0_CSR_P_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_P_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_P_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_P_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_P_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0_CSR_P_NOSSETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_SPKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0_CSR_P_SENDSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALL          (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0_CSR_P_STALL             (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0_CSR_P_NO_SETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0_CSR_P_NO_DATAEND        (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0_CSR_P_SENTSTALL         (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALSNT        (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0_CSR_P_STALSNT           (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0_CSR_P_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_PKTRDY         (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_P_PKTRDY            (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_P_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_P_ISO              14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EP_TXCSR_P_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_P_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_P_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_P_INCOMPTX          7                               /* Incomplete Tx */
-#define BITP_USB_EP_TXCSR_P_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_P_SENTSTALL         5                               /* Sent STALL */
-#define BITP_USB_EP_TXCSR_P_SENDSTALL         4                               /* Send STALL */
-#define BITP_USB_EP_TXCSR_P_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_P_URUNERR           2                               /* Underrun Error */
-#define BITP_USB_EP_TXCSR_P_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_P_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_P_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EP_TXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EP_TXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_P_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_P_INCOMPTX         (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EP_TXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EP_TXCSR_P_INCOMP           (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EP_TXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_P_SENTSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_P_STALSNT          (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_TXCSR_P_SENDSTALL        (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EP_TXCSR_P_STALL            (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EP_TXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_P_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EP_TXCSR_P_NO_URUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EP_TXCSR_P_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FIFONE        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_P_FIFONE           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_P_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_RXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_RXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_RXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_H_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_H_AUTOREQ          14                               /* Auto Request Clear Enable */
-#define BITP_USB_EP_RXCSR_H_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_H_PIDERR           12                               /* Packet ID Error */
-#define BITP_USB_EP_RXCSR_H_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_RXCSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP_RXCSR_H_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_H_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_H_RXSTALL           6                               /* Rx STALL */
-#define BITP_USB_EP_RXCSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP_RXCSR_H_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_H_NAKTODERR         3                               /* NAK Timeout Data Error */
-#define BITP_USB_EP_RXCSR_H_RXTOERR           2                               /* Rx Timeout Error */
-#define BITP_USB_EP_RXCSR_H_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOREQ       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EP_RXCSR_H_NO_PIDERR        (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_RXCSR_H_DATGLDIS         (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP_RXCSR_H_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_H_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_H_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_H_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_RXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP_RXCSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP_RXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_H_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_H_NAKTODERR        (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EP_RXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_NAKTO            (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EP_RXCSR_H_NO_RXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EP_RXCSR_H_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_H_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_H_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_P_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_P_ISO              14                               /* Isochronous Transfers */
-#define BITP_USB_EP_RXCSR_P_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_P_DNYETPERR        12                               /* Disable NYET Handshake */
-#define BITP_USB_EP_RXCSR_P_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_P_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_P_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_P_SENTSTALL         6                               /* Sent STALL */
-#define BITP_USB_EP_RXCSR_P_SENDSTALL         5                               /* Send STALL */
-#define BITP_USB_EP_RXCSR_P_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_P_DATAERR           3                               /* Data Error */
-#define BITP_USB_EP_RXCSR_P_ORUNERR           2                               /* OUT Run Error */
-#define BITP_USB_EP_RXCSR_P_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_P_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EP_RXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EP_RXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_P_DNYETPERR        (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERREN        (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERRDIS       (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_P_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_P_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_P_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_P_SENTSTALL        (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_P_STALSNT          (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_RXCSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP_RXCSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EP_RXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_P_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EP_RXCSR_P_NO_DATAERR       (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EP_RXCSR_P_NO_ORUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EP_RXCSR_P_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_P_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_P_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CNT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CNT_RXCNT                0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0_CNT_RXCNT               (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCNT_EPRXCNT             0                               /* EP Rx Count */
-#define BITM_USB_EP_RXCNT_EPRXCNT            (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_TYPE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_TYPE_SPEED               0                               /* Speed of Operation Value */
-#define BITM_USB_EP0_TYPE_SPEED              (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_TXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_TXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_TXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_TXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_TXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_TXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_TXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_TXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_TXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_TXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_TXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_TXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_TXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_TXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_TXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_TXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_TXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_TXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_TXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_TXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_TXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_TXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_TXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_TXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_TXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_TXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_TXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_TXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_TXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_NAKLIMIT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_NAKLIMIT_VALUE           0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0_NAKLIMIT_VALUE          (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_RXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_RXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_RXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_RXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_RXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_RXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_RXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_RXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_RXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_RXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_RXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_RXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_RXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_RXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_RXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_RXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_RXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_RXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_RXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_RXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_RXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_RXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_RXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_RXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_RXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_RXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_RXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_RXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_RXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CFGDATA                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CFGDATA_MPRX             7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0_CFGDATA_MPTX             6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0_CFGDATA_BIGEND           5                               /* Big Endian Data */
-#define BITP_USB_EP0_CFGDATA_HBRX             4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0_CFGDATA_HBTX             3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0_CFGDATA_DYNFIFO          2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0_CFGDATA_SOFTCON          1                               /* Soft Connect Enable */
-#define BITP_USB_EP0_CFGDATA_UTMIWID          0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0_CFGDATA_MPRX            (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPRXEN          (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_MPTX            (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPTXEN          (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_BIGEND          (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0_CFGDATA_BIGENDDIS       (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0_CFGDATA_BIGENDEN        (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0_CFGDATA_HBRX            (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0_CFGDATA_HBRXEN          (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0_CFGDATA_HBTX            (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0_CFGDATA_HBTXEN          (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0_CFGDATA_DYNFIFO         (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0_CFGDATA_DYNSZDIS        (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0_CFGDATA_DYNSZEN         (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0_CFGDATA_SOFTCON         (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0_CFGDATA_SFTCONDIS       (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0_CFGDATA_SFTCONEN        (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0_CFGDATA_UTMIWID         (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID8        (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID16       (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_IRQ_D7                   7                               /* DMA 7 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D6                   6                               /* DMA 6 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D5                   5                               /* DMA 5 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D4                   4                               /* DMA 4 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D3                   3                               /* DMA 3 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D2                   2                               /* DMA 2 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D1                   1                               /* DMA 1 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D0                   0                               /* DMA 0 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D7                  (_ADI_MSK(0x00000080,uint8_t))   /* DMA 7 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D6                  (_ADI_MSK(0x00000040,uint8_t))   /* DMA 6 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D5                  (_ADI_MSK(0x00000020,uint8_t))   /* DMA 5 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D4                  (_ADI_MSK(0x00000010,uint8_t))   /* DMA 4 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D3                  (_ADI_MSK(0x00000008,uint8_t))   /* DMA 3 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D2                  (_ADI_MSK(0x00000004,uint8_t))   /* DMA 2 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D1                  (_ADI_MSK(0x00000002,uint8_t))   /* DMA 1 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D0                  (_ADI_MSK(0x00000001,uint8_t))   /* DMA 0 Interrupt Pending Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_CTL_BRSTM                9                               /* Burst Mode */
-#define BITP_USB_DMA_CTL_ERR                  8                               /* Bus Error */
-#define BITP_USB_DMA_CTL_EP                   4                               /* DMA Channel Endpoint Assignment */
-#define BITP_USB_DMA_CTL_IE                   3                               /* DMA Interrupt Enable */
-#define BITP_USB_DMA_CTL_MODE                 2                               /* DMA Mode */
-#define BITP_USB_DMA_CTL_DIR                  1                               /* DMA Transfer Direction */
-#define BITP_USB_DMA_CTL_EN                   0                               /* DMA Enable */
-
-#define BITM_USB_DMA_CTL_BRSTM               (_ADI_MSK(0x00000600,uint16_t))  /* Burst Mode */
-#define ENUM_USB_DMA_CTL_BRSTM00             (_ADI_MSK(0x00000000,uint16_t))  /* BRSTM: Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM01             (_ADI_MSK(0x00000200,uint16_t))  /* BRSTM: INCR4 or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM10             (_ADI_MSK(0x00000400,uint16_t))  /* BRSTM: INCR8, INCR4, or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM11             (_ADI_MSK(0x00000600,uint16_t))  /* BRSTM: INCR16, INCR8, INCR4, or Unspecified Length */
-
-#define BITM_USB_DMA_CTL_ERR                 (_ADI_MSK(0x00000100,uint16_t))  /* Bus Error */
-#define ENUM_USB_DMA_CTL_NO_DMAERR           (_ADI_MSK(0x00000000,uint16_t))  /* ERR: No Status */
-#define ENUM_USB_DMA_CTL_DMAERR              (_ADI_MSK(0x00000100,uint16_t))  /* ERR: Bus Error */
-
-#define BITM_USB_DMA_CTL_EP                  (_ADI_MSK(0x000000F0,uint16_t))  /* DMA Channel Endpoint Assignment */
-#define ENUM_USB_DMA_CTL_DMAEP0              (_ADI_MSK(0x00000000,uint16_t))  /* EP: Endpoint 0 */
-#define ENUM_USB_DMA_CTL_DMAEP1              (_ADI_MSK(0x00000010,uint16_t))  /* EP: Endpoint 1 */
-#define ENUM_USB_DMA_CTL_DMAEP10             (_ADI_MSK(0x000000A0,uint16_t))  /* EP: Endpoint 10 */
-#define ENUM_USB_DMA_CTL_DMAEP11             (_ADI_MSK(0x000000B0,uint16_t))  /* EP: Endpoint 11 */
-#define ENUM_USB_DMA_CTL_DMAEP12             (_ADI_MSK(0x000000C0,uint16_t))  /* EP: Endpoint 12 */
-#define ENUM_USB_DMA_CTL_DMAEP13             (_ADI_MSK(0x000000D0,uint16_t))  /* EP: Endpoint 13 */
-#define ENUM_USB_DMA_CTL_DMAEP14             (_ADI_MSK(0x000000E0,uint16_t))  /* EP: Endpoint 14 */
-#define ENUM_USB_DMA_CTL_DMAEP15             (_ADI_MSK(0x000000F0,uint16_t))  /* EP: Endpoint 15 */
-#define ENUM_USB_DMA_CTL_DMAEP2              (_ADI_MSK(0x00000020,uint16_t))  /* EP: Endpoint 2 */
-#define ENUM_USB_DMA_CTL_DMAEP3              (_ADI_MSK(0x00000030,uint16_t))  /* EP: Endpoint 3 */
-#define ENUM_USB_DMA_CTL_DMAEP4              (_ADI_MSK(0x00000040,uint16_t))  /* EP: Endpoint 4 */
-#define ENUM_USB_DMA_CTL_DMAEP5              (_ADI_MSK(0x00000050,uint16_t))  /* EP: Endpoint 5 */
-#define ENUM_USB_DMA_CTL_DMAEP6              (_ADI_MSK(0x00000060,uint16_t))  /* EP: Endpoint 6 */
-#define ENUM_USB_DMA_CTL_DMAEP7              (_ADI_MSK(0x00000070,uint16_t))  /* EP: Endpoint 7 */
-#define ENUM_USB_DMA_CTL_DMAEP8              (_ADI_MSK(0x00000080,uint16_t))  /* EP: Endpoint 8 */
-#define ENUM_USB_DMA_CTL_DMAEP9              (_ADI_MSK(0x00000090,uint16_t))  /* EP: Endpoint 9 */
-
-#define BITM_USB_DMA_CTL_IE                  (_ADI_MSK(0x00000008,uint16_t))  /* DMA Interrupt Enable */
-#define ENUM_USB_DMA_CTL_DMAINTDIS           (_ADI_MSK(0x00000000,uint16_t))  /* IE: Disable Interrupt */
-#define ENUM_USB_DMA_CTL_DMAINTEN            (_ADI_MSK(0x00000008,uint16_t))  /* IE: Enable Interrupt */
-
-#define BITM_USB_DMA_CTL_MODE                (_ADI_MSK(0x00000004,uint16_t))  /* DMA Mode */
-#define ENUM_USB_DMA_CTL_DMAMODE0            (_ADI_MSK(0x00000000,uint16_t))  /* MODE: DMA Mode 0 */
-#define ENUM_USB_DMA_CTL_DMAMODE1            (_ADI_MSK(0x00000004,uint16_t))  /* MODE: DMA Mode 1 */
-
-#define BITM_USB_DMA_CTL_DIR                 (_ADI_MSK(0x00000002,uint16_t))  /* DMA Transfer Direction */
-#define ENUM_USB_DMA_CTL_DMADIR_RX           (_ADI_MSK(0x00000000,uint16_t))  /* DIR: DMA Write (for Rx Endpoint) */
-#define ENUM_USB_DMA_CTL_DMADIR_TX           (_ADI_MSK(0x00000002,uint16_t))  /* DIR: DMA Read (for Tx Endpoint) */
-
-#define BITM_USB_DMA_CTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* DMA Enable */
-#define ENUM_USB_DMA_CTL_DMADIS              (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable DMA */
-#define ENUM_USB_DMA_CTL_DMAEN               (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable DMA (Start Transfer) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_UCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_UCH_VALUE                 0                               /* Chirp Timeout Value */
-#define BITM_USB_CT_UCH_VALUE                (_ADI_MSK(0x00007FFF,uint16_t))  /* Chirp Timeout Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HHSRTN                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HHSRTN_VALUE              0                               /* Host High Speed Return to Normal Value */
-#define BITM_USB_CT_HHSRTN_VALUE             (_ADI_MSK(0x00007FFF,uint16_t))  /* Host High Speed Return to Normal Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HSBT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HSBT_VALUE                0                               /* HS Timeout Adder */
-#define BITM_USB_CT_HSBT_VALUE               (_ADI_MSK(0x0000000F,uint16_t))  /* HS Timeout Adder */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_ATTR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_ATTR_EP                 12                               /* Endpoint */
-#define BITP_USB_LPM_ATTR_RMTWAK              8                               /* Remote Wakeup Enable */
-#define BITP_USB_LPM_ATTR_HIRD                4                               /* Host Initiated Resume Duration */
-#define BITP_USB_LPM_ATTR_LINKSTATE           0                               /* Link State */
-#define BITM_USB_LPM_ATTR_EP                 (_ADI_MSK(0x0000F000,uint16_t))  /* Endpoint */
-
-#define BITM_USB_LPM_ATTR_RMTWAK             (_ADI_MSK(0x00000100,uint16_t))  /* Remote Wakeup Enable */
-#define ENUM_USB_LPM_ATTR_RMTWAKDIS          (_ADI_MSK(0x00000000,uint16_t))  /* RMTWAK: Disable Remote Wakeup */
-#define ENUM_USB_LPM_ATTR_RMTWAKEN           (_ADI_MSK(0x00000100,uint16_t))  /* RMTWAK: Enable Remote Wakeup */
-#define BITM_USB_LPM_ATTR_HIRD               (_ADI_MSK(0x000000F0,uint16_t))  /* Host Initiated Resume Duration */
-
-#define BITM_USB_LPM_ATTR_LINKSTATE          (_ADI_MSK(0x0000000F,uint16_t))  /* Link State */
-#define ENUM_USB_LPM_ATTR_LNKSTATE_SSL1      (_ADI_MSK(0x00000001,uint16_t))  /* LINKSTATE: Sleep State (L1) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_CTL_NAK                  4                               /* LPM NAK Enable */
-#define BITP_USB_LPM_CTL_EN                   2                               /* LPM Enable */
-#define BITP_USB_LPM_CTL_RESUME               1                               /* LPM Resume (Remote Wakeup) */
-#define BITP_USB_LPM_CTL_TX                   0                               /* LPM Transmit */
-#define BITM_USB_LPM_CTL_NAK                 (_ADI_MSK(0x00000010,uint8_t))   /* LPM NAK Enable */
-#define BITM_USB_LPM_CTL_EN                  (_ADI_MSK(0x0000000C,uint8_t))   /* LPM Enable */
-#define BITM_USB_LPM_CTL_RESUME              (_ADI_MSK(0x00000002,uint8_t))   /* LPM Resume (Remote Wakeup) */
-#define BITM_USB_LPM_CTL_TX                  (_ADI_MSK(0x00000001,uint8_t))   /* LPM Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IEN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IEN_LPMERR               5                               /* LPM Error Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMRES               4                               /* LPM Resume Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNC                3                               /* LPM NYET Control Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMACK               2                               /* LPM ACK Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNY                1                               /* LPM NYET Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMST                0                               /* LPM STALL Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMST               (_ADI_MSK(0x00000001,uint8_t))   /* LPM STALL Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IRQ_LPMERR               5                               /* LPM Error Interrupt */
-#define BITP_USB_LPM_IRQ_LPMRES               4                               /* LPM Resume Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNC                3                               /* LPM NYET Control Interrupt */
-#define BITP_USB_LPM_IRQ_LPMACK               2                               /* LPM ACK Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNY                1                               /* LPM NYET Interrupt */
-#define BITP_USB_LPM_IRQ_LPMST                0
-#define BITM_USB_LPM_IRQ_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt */
-#define BITM_USB_LPM_IRQ_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt */
-#define BITM_USB_LPM_IRQ_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt */
-#define BITM_USB_LPM_IRQ_LPMST               (_ADI_MSK(0x00000001,uint8_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_FADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_FADDR_VALUE              0                               /* Function Address Value */
-#define BITM_USB_LPM_FADDR_VALUE             (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_VBUS_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_VBUS_CTL_DRV                 4                               /* VBUS Drive */
-#define BITP_USB_VBUS_CTL_DRVINT              3                               /* VBUS Drive Interrupt */
-#define BITP_USB_VBUS_CTL_DRVIEN              2                               /* VBUS Drive Interrupt Enable */
-#define BITP_USB_VBUS_CTL_DRVOD               1                               /* VBUS Drive Open Drain */
-#define BITP_USB_VBUS_CTL_INVDRV              0                               /* VBUS Invert Drive */
-#define BITM_USB_VBUS_CTL_DRV                (_ADI_MSK(0x00000010,uint8_t))   /* VBUS Drive */
-#define BITM_USB_VBUS_CTL_DRVINT             (_ADI_MSK(0x00000008,uint8_t))   /* VBUS Drive Interrupt */
-#define BITM_USB_VBUS_CTL_DRVIEN             (_ADI_MSK(0x00000004,uint8_t))   /* VBUS Drive Interrupt Enable */
-#define BITM_USB_VBUS_CTL_DRVOD              (_ADI_MSK(0x00000002,uint8_t))   /* VBUS Drive Open Drain */
-#define BITM_USB_VBUS_CTL_INVDRV             (_ADI_MSK(0x00000001,uint8_t))   /* VBUS Invert Drive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_BAT_CHG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_BAT_CHG_DEDCHG               4                               /* Dedicated Charging Port */
-#define BITP_USB_BAT_CHG_CHGDET               3                               /* Charging Port Detected */
-#define BITP_USB_BAT_CHG_SNSCHGDET            2                               /* Sense Charger Detection */
-#define BITP_USB_BAT_CHG_CONDET               1                               /* Connected Detected */
-#define BITP_USB_BAT_CHG_SNSCONDET            0                               /* Sense Connection Detection */
-#define BITM_USB_BAT_CHG_DEDCHG              (_ADI_MSK(0x00000010,uint8_t))   /* Dedicated Charging Port */
-#define BITM_USB_BAT_CHG_CHGDET              (_ADI_MSK(0x00000008,uint8_t))   /* Charging Port Detected */
-#define BITM_USB_BAT_CHG_SNSCHGDET           (_ADI_MSK(0x00000004,uint8_t))   /* Sense Charger Detection */
-#define BITM_USB_BAT_CHG_CONDET              (_ADI_MSK(0x00000002,uint8_t))   /* Connected Detected */
-#define BITM_USB_BAT_CHG_SNSCONDET           (_ADI_MSK(0x00000001,uint8_t))   /* Sense Connection Detection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PHY_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PHY_CTL_EN                   7                               /* PHY Enable */
-#define BITP_USB_PHY_CTL_RESTORE              1                               /* Restore from Hibernate */
-#define BITP_USB_PHY_CTL_HIBER                0                               /* Hibernate */
-#define BITM_USB_PHY_CTL_EN                  (_ADI_MSK(0x00000080,uint8_t))   /* PHY Enable */
-#define BITM_USB_PHY_CTL_RESTORE             (_ADI_MSK(0x00000002,uint8_t))   /* Restore from Hibernate */
-#define BITM_USB_PHY_CTL_HIBER               (_ADI_MSK(0x00000001,uint8_t))   /* Hibernate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PLL_OSC                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PLL_OSC_PLLMSEL              7                               /* PLL Multiplier Select */
-#define BITP_USB_PLL_OSC_PLLM                 1                               /* PLL Multiplier Value */
-#define BITP_USB_PLL_OSC_DIVCLKIN             0                               /* Divide CLKIN */
-#define BITM_USB_PLL_OSC_PLLMSEL             (_ADI_MSK(0x00000080,uint16_t))  /* PLL Multiplier Select */
-#define BITM_USB_PLL_OSC_PLLM                (_ADI_MSK(0x0000007E,uint16_t))  /* PLL Multiplier Value */
-#define BITM_USB_PLL_OSC_DIVCLKIN            (_ADI_MSK(0x00000001,uint16_t))  /* Divide CLKIN */
-
-/* ==================================================
-        Data Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1DM0
-   ========================= */
-#define SRAM_BASE_ADDRESS               0xFFE00000         /* SRAM Base Address */
-#define DMEM_CONTROL                    0xFFE00004         /* Data memory control */
-#define DCPLB_STATUS                    0xFFE00008         /* Data Cacheability Protection Lookaside Buffer Status */
-#define DCPLB_FAULT_STATUS              0xFFE00008         /*     Older definition or alias of above */
-#define DCPLB_FAULT_ADDR                0xFFE0000C         /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define DCPLB_ADDR0                     0xFFE00100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR1                     0xFFE00104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR2                     0xFFE00108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR3                     0xFFE0010C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR4                     0xFFE00110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR5                     0xFFE00114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR6                     0xFFE00118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR7                     0xFFE0011C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR8                     0xFFE00120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR9                     0xFFE00124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR10                    0xFFE00128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR11                    0xFFE0012C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR12                    0xFFE00130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR13                    0xFFE00134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR14                    0xFFE00138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR15                    0xFFE0013C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_DATA0                     0xFFE00200         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA1                     0xFFE00204         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA2                     0xFFE00208         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA3                     0xFFE0020C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA4                     0xFFE00210         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA5                     0xFFE00214         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA6                     0xFFE00218         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA7                     0xFFE0021C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA8                     0xFFE00220         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA9                     0xFFE00224         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA10                    0xFFE00228         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA11                    0xFFE0022C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA12                    0xFFE00230         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA13                    0xFFE00234         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA14                    0xFFE00238         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA15                    0xFFE0023C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DTEST_COMMAND                   0xFFE00300         /* Data Test Command Register */
-#define DTEST_DATA0                     0xFFE00400         /* Data Test Data Register */
-#define DTEST_DATA1                     0xFFE00404         /* Data Test Data Register */
-#define L1DBNKA_PELOC                   0xFFE00408         /* Data Bank A Parity Error Location */
-#define L1DBNKB_PELOC                   0xFFE0040C         /* Data Bank B Parity Error Location */
-
-/* =========================
-        L1DM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SRAM_BASE_ADDRESS                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SRAM_BASE_ADDRESS_ADDR          22                               /* SRAM Base Address */
-#define BITM_SRAM_BASE_ADDRESS_ADDR          (_ADI_MSK(0xFFC00000,uint32_t))  /* SRAM Base Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMEM_CONTROL_PARCTL             15                               /* L1 Scratch Parity Control */
-#define BITP_DMEM_CONTROL_PARSEL             14                               /* L1 Scratch Parity Select */
-#define BITP_DMEM_CONTROL_PPREF1             13                               /* DAG1 Port Preference */
-#define BITP_DMEM_CONTROL_PPREF0             12                               /* DAG0 Port Preference */
-#define BITP_DMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_DMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_DMEM_CONTROL_DCBS                4                               /* L1 Data Cache Bank Select */
-#define BITP_DMEM_CONTROL_CFG                 2                               /* Data Memory Configuration */
-#define BITP_DMEM_CONTROL_ENCPLB              1                               /* Enable DCPLB */
-
-#define BITM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* L1 Scratch Parity Control */
-#define ENUM_DMEM_CONTROL_NO_PARCTL          (_ADI_MSK(0x00000000,uint32_t))  /* PARCTL: No Parity Control  (Normal Behavior for L1 RD / L1 WT) */
-#define ENUM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* PARCTL: Parity Control Enabled */
-#define BITM_DMEM_CONTROL_PARSEL             (_ADI_MSK(0x00004000,uint32_t))  /* L1 Scratch Parity Select */
-
-#define BITM_DMEM_CONTROL_PPREF1             (_ADI_MSK(0x00002000,uint32_t))  /* DAG1 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF1A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF1B            (_ADI_MSK(0x00002000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_PPREF0             (_ADI_MSK(0x00001000,uint32_t))  /* DAG0 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF0A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF0B            (_ADI_MSK(0x00001000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_DMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_DMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_DMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_DMEM_CONTROL_DCBS               (_ADI_MSK(0x00000010,uint32_t))  /* L1 Data Cache Bank Select */
-#define ENUM_DMEM_CONTROL_DCBS14             (_ADI_MSK(0x00000000,uint32_t))  /* DCBS: Address bit 14 used to select Bank A or B for cache access */
-#define ENUM_DMEM_CONTROL_DCBS23             (_ADI_MSK(0x00000010,uint32_t))  /* DCBS: Address bit 23 used to select Bank A or B for cache access */
-
-#define BITM_DMEM_CONTROL_CFG                (_ADI_MSK(0x0000000C,uint32_t))  /* Data Memory Configuration */
-#define ENUM_DMEM_CONTROL_ASRAM_BSRAM        (_ADI_MSK(0x00000000,uint32_t))  /* CFG: A SRAM, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BSRAM       (_ADI_MSK(0x00000008,uint32_t))  /* CFG: A Cache, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BCACHE      (_ADI_MSK(0x0000000C,uint32_t))  /* CFG: A Cache, B Cache */
-
-#define BITM_DMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable DCPLB */
-#define ENUM_DMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs Disabled */
-#define ENUM_DMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs Enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_DCPLB_STATUS_DAG                18                               /* Access DAG */
-#define BITP_DCPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_DCPLB_STATUS_RW                 16                               /* Access Read/Write */
-#define BITP_DCPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_DCPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_DCPLB_STATUS_DAG                (_ADI_MSK(0x00040000,uint32_t))  /* Access DAG */
-#define BITM_DCPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_DCPLB_STATUS_RW                 (_ADI_MSK(0x00010000,uint32_t))  /* Access Read/Write */
-#define BITM_DCPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_DCPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_DCPLB_DATA_WT                   14                               /* CPLB Write Through */
-#define BITP_DCPLB_DATA_L2_CHBL              13                               /* CPLB L2 Cacheable */
-#define BITP_DCPLB_DATA_L1_CHBL              12                               /* CPLB L1 Cacheable */
-#define BITP_DCPLB_DATA_DIRTY                 7                               /* CPLB DIRTY */
-#define BITP_DCPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_DCPLB_DATA_SWRITE                4                               /* CPLB Supervisor Write */
-#define BITP_DCPLB_DATA_UWRITE                3                               /* CPLB User Write */
-#define BITP_DCPLB_DATA_UREAD                 2                               /* CPLB User Read */
-#define BITP_DCPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_DCPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_DCPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_DCPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_DCPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_DCPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_DCPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_DCPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_DCPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_DCPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_DCPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* CPLB Write Through */
-#define ENUM_DCPLB_DATA_WB                   (_ADI_MSK(0x00000000,uint32_t))  /* WT: Write-back */
-#define ENUM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* WT: Write-through */
-
-#define BITM_DCPLB_DATA_L2_CHBL              (_ADI_MSK(0x00002000,uint32_t))  /* CPLB L2 Cacheable */
-#define ENUM_DCPLB_DATA_L2CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L2CHBL: Non-cacheable in L2 */
-#define ENUM_DCPLB_DATA_L2CHBL_EN            (_ADI_MSK(0x00002000,uint32_t))  /* L2CHBL: Cacheable in L2 */
-
-#define BITM_DCPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* CPLB L1 Cacheable */
-#define ENUM_DCPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_DCPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* CPLB DIRTY */
-#define ENUM_DCPLB_DATA_CLEAN                (_ADI_MSK(0x00000000,uint32_t))  /* DIRTY: Clean */
-#define ENUM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* DIRTY: Dirty */
-#define BITM_DCPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* CPLB Supervisor Write */
-#define ENUM_DCPLB_DATA_NO_SWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* SWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* SWRITE: Write Access Allowed (Supervisor Mode) */
-
-#define BITM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* CPLB User Write */
-#define ENUM_DCPLB_DATA_NO_UWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* UWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* UWRITE: Write Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* CPLB User Read */
-#define ENUM_DCPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_DCPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_DCPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_DCPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid Entry */
-#define ENUM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DTEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DTEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_DTEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_DTEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bit 11 */
-#define BITP_DTEST_COMMAND_IDSEL             24                               /* Instruction/Data Access */
-#define BITP_DTEST_COMMAND_BNKSEL            23                               /* Data Bank Access */
-#define BITP_DTEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_DTEST_COMMAND_SEL16K            14                               /* Address bit 14 */
-#define BITP_DTEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_DTEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_DTEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_DTEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_DTEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_DTEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_DTEST_COMMAND_WAYSEL            (_ADI_MSK(0x04000000,uint32_t))  /* Access Way/Instruction Address Bit 11 */
-#define BITM_DTEST_COMMAND_IDSEL             (_ADI_MSK(0x01000000,uint32_t))  /* Instruction/Data Access */
-#define BITM_DTEST_COMMAND_BNKSEL            (_ADI_MSK(0x00800000,uint32_t))  /* Data Bank Access */
-#define BITM_DTEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_DTEST_COMMAND_SEL16K            (_ADI_MSK(0x00004000,uint32_t))  /* Address bit 14 */
-#define BITM_DTEST_COMMAND_SET               (_ADI_MSK(0x000007E0,uint32_t))  /* Set Index */
-#define BITM_DTEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_DTEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_DTEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKA_PELOC_SCRATCH_MEM       12                               /* Scratch Memory Parity Status */
-#define BITP_L1DBNKA_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_SCRATCH_MEM       (_ADI_MSK(0x00001000,uint32_t))  /* Scratch Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKB_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKB_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Instruction Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1IM0
-   ========================= */
-#define IMEM_CONTROL                    0xFFE01004         /* Instruction memory control */
-#define ICPLB_STATUS                    0xFFE01008         /* Cacheability Protection Lookaside Buffer Status */
-#define CODE_FAULT_STATUS               0xFFE01008         /*     Older definition or alias of above */
-#define ICPLB_FAULT_ADDR                0xFFE0100C         /* Cacheability Protection Lookaside Buffer Fault Address */
-#define CODE_FAULT_ADDR                 0xFFE0100C         /*     Older definition or alias of above */
-#define ICPLB_ADDR0                     0xFFE01100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR1                     0xFFE01104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR2                     0xFFE01108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR3                     0xFFE0110C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR4                     0xFFE01110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR5                     0xFFE01114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR6                     0xFFE01118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR7                     0xFFE0111C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR8                     0xFFE01120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR9                     0xFFE01124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR10                    0xFFE01128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR11                    0xFFE0112C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR12                    0xFFE01130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR13                    0xFFE01134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR14                    0xFFE01138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR15                    0xFFE0113C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_DATA0                     0xFFE01200         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA1                     0xFFE01204         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA2                     0xFFE01208         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA3                     0xFFE0120C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA4                     0xFFE01210         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA5                     0xFFE01214         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA6                     0xFFE01218         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA7                     0xFFE0121C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA8                     0xFFE01220         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA9                     0xFFE01224         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA10                    0xFFE01228         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA11                    0xFFE0122C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA12                    0xFFE01230         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA13                    0xFFE01234         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA14                    0xFFE01238         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA15                    0xFFE0123C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ITEST_COMMAND                   0xFFE01300         /* Instruction Test Command Register */
-#define ITEST_DATA0                     0xFFE01400         /* Instruction Test Data Register */
-#define ITEST_DATA1                     0xFFE01404         /* Instruction Test Data Register */
-#define L1IBNKA_PELOC                   0xFFE01408         /* Instruction Bank A Parity Error Location */
-#define L1IBNKB_PELOC                   0xFFE0140C         /* Instruction Bank B Parity Error Location */
-#define L1IBNKC_PELOC                   0xFFE01410         /* Instruction Bank C Parity Error Location */
-
-/* =========================
-        L1IM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMEM_CONTROL_LRUPRIORST         13                               /* LRU Priority Reset */
-#define BITP_IMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_IMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_IMEM_CONTROL_LOC                 3                               /* Cache Way Lock */
-#define BITP_IMEM_CONTROL_CFG                 2                               /* Configure L1 code memory as cache */
-#define BITP_IMEM_CONTROL_ENCPLB              1                               /* Enable ICPLB */
-
-#define BITM_IMEM_CONTROL_LRUPRIORST         (_ADI_MSK(0x00002000,uint32_t))  /* LRU Priority Reset */
-#define ENUM_IMEM_CONTROL_LRUPRIO_EN         (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIORST: LRU Priority functionality is enabled */
-#define ENUM_IMEM_CONTROL_LRUPRIO_CLR        (_ADI_MSK(0x00002000,uint32_t))  /* LRUPRIORST: All cached LRU priority bits are cleared */
-
-#define BITM_IMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_IMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_IMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_IMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_IMEM_CONTROL_LOC                (_ADI_MSK(0x00000078,uint32_t))  /* Cache Way Lock */
-#define ENUM_IMEM_CONTROL_WAYLOCK_NONE       (_ADI_MSK(0x00000000,uint32_t))  /* LOC: All Ways Not Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_0          (_ADI_MSK(0x00000008,uint32_t))  /* LOC: Way3, Way2, Way1 Not Locked, Way0 Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_ALL        (_ADI_MSK(0x00000078,uint32_t))  /* LOC: All Ways Locked */
-
-#define BITM_IMEM_CONTROL_CFG                (_ADI_MSK(0x00000004,uint32_t))  /* Configure L1 code memory as cache */
-#define ENUM_IMEM_CONTROL_CFG_SRAM           (_ADI_MSK(0x00000000,uint32_t))  /* CFG: L1 Instruction Memory Configured as SRAM */
-#define ENUM_IMEM_CONTROL_CFG_CACHE          (_ADI_MSK(0x00000004,uint32_t))  /* CFG: L1 Instruction Memory Configures as Cache */
-
-#define BITM_IMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable ICPLB */
-#define ENUM_IMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs disabled */
-#define ENUM_IMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_ICPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_ICPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_ICPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_ICPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_ICPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_ICPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_ICPLB_DATA_L1_CHBL              12                               /* L1 Cacheable */
-#define BITP_ICPLB_DATA_LRUPRIO               8                               /* Least Recently Used Priority */
-#define BITP_ICPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_ICPLB_DATA_UREAD                 2                               /* Allow User Read */
-#define BITP_ICPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_ICPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_ICPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_ICPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_ICPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_ICPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_ICPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_ICPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_ICPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_ICPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_ICPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_ICPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* L1 Cacheable */
-#define ENUM_ICPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_ICPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_ICPLB_DATA_LRUPRIO              (_ADI_MSK(0x00000100,uint32_t))  /* Least Recently Used Priority */
-#define ENUM_ICPLB_DATA_LRUPRIO_LO           (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIO: Low Importance */
-#define ENUM_ICPLB_DATA_LRUPRIO_HI           (_ADI_MSK(0x00000100,uint32_t))  /* LRUPRIO: High Importance */
-#define BITM_ICPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* Allow User Read */
-#define ENUM_ICPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_ICPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_ICPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_ICPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_ICPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid (disabled) CPLB Entry */
-#define ENUM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid (enabled) CPLB Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ITEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ITEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_ITEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_ITEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bits 11:10 */
-#define BITP_ITEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_ITEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_ITEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_ITEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_ITEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_ITEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_ITEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_ITEST_COMMAND_WAYSEL            (_ADI_MSK(0x0C000000,uint32_t))  /* Access Way/Instruction Address Bits 11:10 */
-#define BITM_ITEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_ITEST_COMMAND_SET               (_ADI_MSK(0x000003E0,uint32_t))  /* Set Index */
-#define BITM_ITEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_ITEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_ITEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKC_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKC_PELOC_TAGPAIR            4                               /* Tag Parity Status */
-#define BITP_L1IBNKC_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKC_PELOC_TAGPAIR           (_ADI_MSK(0x00000030,uint32_t))  /* Tag Parity Status */
-#define BITM_L1IBNKC_PELOC_MEMBLK            (_ADI_MSK(0x0000000F,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Interrupt Controller Registers
-   ================================================== */
-
-/* =========================
-        ICU0
-   ========================= */
-#define EVT0                            0xFFE02000         /* Event Vector */
-#define EVT1                            0xFFE02004         /* Event Vector */
-#define EVT2                            0xFFE02008         /* Event Vector */
-#define EVT3                            0xFFE0200C         /* Event Vector */
-#define EVT4                            0xFFE02010         /* Event Vector */
-#define EVT5                            0xFFE02014         /* Event Vector */
-#define EVT6                            0xFFE02018         /* Event Vector */
-#define EVT7                            0xFFE0201C         /* Event Vector */
-#define EVT8                            0xFFE02020         /* Event Vector */
-#define EVT9                            0xFFE02024         /* Event Vector */
-#define EVT10                           0xFFE02028         /* Event Vector */
-#define EVT11                           0xFFE0202C         /* Event Vector */
-#define EVT12                           0xFFE02030         /* Event Vector */
-#define EVT13                           0xFFE02034         /* Event Vector */
-#define EVT14                           0xFFE02038         /* Event Vector */
-#define EVT15                           0xFFE0203C         /* Event Vector */
-#define IMASK                           0xFFE02104         /* Interrupt Mask Register */
-#define IPEND                           0xFFE02108         /* Interrupts Pending Register */
-#define ILAT                            0xFFE0210C         /* Interrupt Latch Register */
-#define IPRIO                           0xFFE02110         /* Interrupt Priority Register */
-#define CEC_SID                         0xFFE02118         /* Core System Interrupt ID */
-
-/* =========================
-        ICU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMASK                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMASK_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IMASK_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IMASK_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IMASK_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IMASK_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IMASK_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IMASK_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IMASK_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IMASK_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IMASK_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IMASK_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IMASK_UNMASKABLE                 0                               /* Unmaskable interrupts */
-#define BITM_IMASK_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IMASK_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IMASK_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IMASK_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IMASK_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IMASK_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IMASK_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IMASK_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IMASK_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IMASK_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IMASK_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IMASK_UNMASKABLE                (_ADI_MSK(0x0000001F,uint32_t))  /* Unmaskable interrupts */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPEND                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPEND_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IPEND_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IPEND_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IPEND_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IPEND_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IPEND_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IPEND_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IPEND_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IPEND_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IPEND_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IPEND_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IPEND_IRPTEN                     4                               /* Global interrupt enable bit position */
-#define BITP_IPEND_EVX                        3                               /* Exception bit position */
-#define BITP_IPEND_NMI                        2                               /* Non Maskable interrupt bit position */
-#define BITP_IPEND_RST                        1                               /* Reset interrupt bit position */
-#define BITP_IPEND_EMU                        0                               /* Emulator interrupt bit position */
-#define BITM_IPEND_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IPEND_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IPEND_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IPEND_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IPEND_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IPEND_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IPEND_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IPEND_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IPEND_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IPEND_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IPEND_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IPEND_IRPTEN                    (_ADI_MSK(0x00000010,uint32_t))  /* Global interrupt enable bit position */
-#define BITM_IPEND_EVX                       (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_IPEND_NMI                       (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_IPEND_RST                       (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_IPEND_EMU                       (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ILAT                                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ILAT_IVG15                      15                               /* IVG15 interrupt bit position */
-#define BITP_ILAT_IVG14                      14                               /* IVG14 interrupt bit position */
-#define BITP_ILAT_IVG13                      13                               /* IVG13 interrupt bit position */
-#define BITP_ILAT_IVG12                      12                               /* IVG12 interrupt bit position */
-#define BITP_ILAT_IVG11                      11                               /* IVG11 interrupt bit position */
-#define BITP_ILAT_IVG10                      10                               /* IVG10 interrupt bit position */
-#define BITP_ILAT_IVG9                        9                               /* IVG9 interrupt bit position */
-#define BITP_ILAT_IVG8                        8                               /* IVG8 interrupt bit position */
-#define BITP_ILAT_IVG7                        7                               /* IVG7 interrupt bit position */
-#define BITP_ILAT_IVTMR                       6                               /* Timer interrupt bit position */
-#define BITP_ILAT_IVHW                        5                               /* Hardware Error interrupt bit position */
-#define BITP_ILAT_EVX                         3                               /* Exception bit position */
-#define BITP_ILAT_NMI                         2                               /* Non Maskable interrupt bit position */
-#define BITP_ILAT_RST                         1                               /* Reset interrupt bit position */
-#define BITP_ILAT_EMU                         0                               /* Emulator interrupt bit position */
-#define BITM_ILAT_IVG15                      (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_ILAT_IVG14                      (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_ILAT_IVG13                      (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_ILAT_IVG12                      (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_ILAT_IVG11                      (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_ILAT_IVG10                      (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_ILAT_IVG9                       (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_ILAT_IVG8                       (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_ILAT_IVG7                       (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_ILAT_IVTMR                      (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_ILAT_IVHW                       (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_ILAT_EVX                        (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_ILAT_NMI                        (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_ILAT_RST                        (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_ILAT_EMU                        (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPRIO                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPRIO_IPRIO_MARK                 0                               /* Priority Watermark */
-#define BITM_IPRIO_IPRIO_MARK                (_ADI_MSK(0x0000000F,uint32_t))  /* Priority Watermark */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CEC_SID                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CEC_SID_SID                      0                               /* System Interrupt ID */
-#define BITM_CEC_SID_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* System Interrupt ID */
-
-/* ==================================================
-        Core Timer Registers
-   ================================================== */
-
-/* =========================
-        TMR0
-   ========================= */
-#define TCNTL                           0xFFE03000         /* Timer Control Register */
-#define TPERIOD                         0xFFE03004         /* Timer Period Register */
-#define TSCALE                          0xFFE03008         /* Timer Scale Register */
-#define TCOUNT                          0xFFE0300C         /* Timer Count Register */
-
-/* =========================
-        TMR
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TCNTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TCNTL_INT                        3                               /* Interrupt Status (sticky) */
-#define BITP_TCNTL_AUTORLD                    2                               /* Auto Reload Enable */
-#define BITP_TCNTL_EN                         1                               /* Timer Enable */
-#define BITP_TCNTL_PWR                        0                               /* Low Power Mode Select */
-#define BITM_TCNTL_INT                       (_ADI_MSK(0x00000008,uint32_t))  /* Interrupt Status (sticky) */
-#define BITM_TCNTL_AUTORLD                   (_ADI_MSK(0x00000004,uint32_t))  /* Auto Reload Enable */
-#define BITM_TCNTL_EN                        (_ADI_MSK(0x00000002,uint32_t))  /* Timer Enable */
-#define BITM_TCNTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Low Power Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TSCALE                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TSCALE_SCALE                     0                               /* Timer Scaling Value */
-#define BITM_TSCALE_SCALE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Timer Scaling Value */
-
-/* ==================================================
-        Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        DBG0
-   ========================= */
-#define DSPID                           0xFFE05000         /* DSP Identification Register */
-
-/* =========================
-        DBG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DSPID                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DSPID_COMPANY                   24                               /* Analog Devices, Inc. */
-#define BITP_DSPID_MAJOR                     16                               /* Major Architectural Change */
-#define BITP_DSPID_COREID                     0                               /* Core ID */
-#define BITM_DSPID_COMPANY                   (_ADI_MSK(0xFF000000,uint32_t))  /* Analog Devices, Inc. */
-
-#define BITM_DSPID_MAJOR                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Major Architectural Change */
-#define ENUM_DSPID_BF533                     (_ADI_MSK(0x00040000,uint32_t))  /* MAJOR: ADSP-BF533 Core Compatible */
-#define BITM_DSPID_COREID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Core ID */
-
-/* ==================================================
-        Trace Unit Registers
-   ================================================== */
-
-/* =========================
-        TB0
-   ========================= */
-#define TBUFCTL                         0xFFE06000         /* Trace Buffer Control Register */
-#define TBUFSTAT                        0xFFE06004         /* Trace Buffer Status Register */
-#define TBUF                            0xFFE06100         /* Trace Buffer */
-
-/* =========================
-        TB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFCTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFCTL_COMPRESS                 3                               /* Trace Buffer Compression */
-#define BITP_TBUFCTL_OVF                      2                               /* Trace Buffer Overflow */
-#define BITP_TBUFCTL_EN                       1                               /* Trace Buffer Enable */
-#define BITP_TBUFCTL_PWR                      0                               /* Trace Buffer Power */
-#define BITM_TBUFCTL_COMPRESS                (_ADI_MSK(0x00000018,uint32_t))  /* Trace Buffer Compression */
-#define BITM_TBUFCTL_OVF                     (_ADI_MSK(0x00000004,uint32_t))  /* Trace Buffer Overflow */
-#define BITM_TBUFCTL_EN                      (_ADI_MSK(0x00000002,uint32_t))  /* Trace Buffer Enable */
-#define BITM_TBUFCTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Trace Buffer Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFSTAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFSTAT_CNT                     0                               /* Trace Buffer Count */
-#define BITM_TBUFSTAT_CNT                    (_ADI_MSK(0x0000001F,uint32_t))  /* Trace Buffer Count */
-
-/* ==================================================
-        Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        WP0
-   ========================= */
-#define WPIACTL                         0xFFE07000         /* Watchpoint Instruction Address Control Register 01 */
-#define WPIA0                           0xFFE07040         /* Watchpoint Instruction Address Register */
-#define WPIA1                           0xFFE07044         /* Watchpoint Instruction Address Register */
-#define WPIA2                           0xFFE07048         /* Watchpoint Instruction Address Register */
-#define WPIA3                           0xFFE0704C         /* Watchpoint Instruction Address Register */
-#define WPIA4                           0xFFE07050         /* Watchpoint Instruction Address Register */
-#define WPIA5                           0xFFE07054         /* Watchpoint Instruction Address Register */
-#define WPIACNT0                        0xFFE07080         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT1                        0xFFE07084         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT2                        0xFFE07088         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT3                        0xFFE0708C         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT4                        0xFFE07090         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT5                        0xFFE07094         /* Watchpoint Instruction Address Count Register */
-#define WPDACTL                         0xFFE07100         /* Watchpoint Data Address Control Register */
-#define WPDA0                           0xFFE07140         /* Watchpoint Data Address Register */
-#define WPDA1                           0xFFE07144         /* Watchpoint Data Address Register */
-#define WPDACNT0                        0xFFE07180         /* Watchpoint Data Address Count Value Register */
-#define WPDACNT1                        0xFFE07184         /* Watchpoint Data Address Count Value Register */
-#define WPSTAT                          0xFFE07200         /* Watchpoint Status Register */
-
-/* =========================
-        WP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACTL_WPAND                   25                               /* And Triggers */
-#define BITP_WPIACTL_ACT5                    24                               /* Action field for WPIA5 */
-#define BITP_WPIACTL_ACT4                    23                               /* Action field for WPIA4 */
-#define BITP_WPIACTL_ENCNT5                  22                               /* Enable Counter for WPIA5 */
-#define BITP_WPIACTL_ENCNT4                  21                               /* Enable Counter for WPIA4 */
-#define BITP_WPIACTL_ENIA5                   20                               /* Enable WPIA5 */
-#define BITP_WPIACTL_ENIA4                   19                               /* Enable WPIA4 */
-#define BITP_WPIACTL_INVIR45                 18                               /* Invert Instruction Range 45 */
-#define BITP_WPIACTL_ENIR45                  17                               /* Enable Instruction Range 45 */
-#define BITP_WPIACTL_ACT3                    16                               /* Action field for WPIA3 */
-#define BITP_WPIACTL_ACT2                    15                               /* Action field for WPIA2 */
-#define BITP_WPIACTL_ENCNT3                  14                               /* Enable Counter for WPIA3 */
-#define BITP_WPIACTL_ENCNT2                  13                               /* Enable Counter for WPIA2 */
-#define BITP_WPIACTL_ENIA3                   12                               /* Enable WPIA3 */
-#define BITP_WPIACTL_ENIA2                   11                               /* Enable WPIA2 */
-#define BITP_WPIACTL_INVIR23                 10                               /* Invert Instruction Range 23 */
-#define BITP_WPIACTL_ENIR23                   9                               /* Enable Instruction Range 23 */
-#define BITP_WPIACTL_ACT1                     8                               /* Action field for WPIA1 */
-#define BITP_WPIACTL_ACT0                     7                               /* Action field for WPIA0 */
-#define BITP_WPIACTL_ENCNT1                   6                               /* Enable Counter for WPIA1 */
-#define BITP_WPIACTL_ENCNT0                   5                               /* Enable Counter for WPIA0 */
-#define BITP_WPIACTL_ENIA1                    4                               /* Enable WPIA1 */
-#define BITP_WPIACTL_ENIA0                    3                               /* Enable WPIA0 */
-#define BITP_WPIACTL_INVIR01                  2                               /* Invert Instruction Range 01 */
-#define BITP_WPIACTL_ENIR01                   1                               /* Enable Instruction Range 01 */
-#define BITP_WPIACTL_PWR                      0                               /* Power */
-#define BITM_WPIACTL_WPAND                   (_ADI_MSK(0x02000000,uint32_t))  /* And Triggers */
-#define BITM_WPIACTL_ACT5                    (_ADI_MSK(0x01000000,uint32_t))  /* Action field for WPIA5 */
-#define BITM_WPIACTL_ACT4                    (_ADI_MSK(0x00800000,uint32_t))  /* Action field for WPIA4 */
-#define BITM_WPIACTL_ENCNT5                  (_ADI_MSK(0x00400000,uint32_t))  /* Enable Counter for WPIA5 */
-#define BITM_WPIACTL_ENCNT4                  (_ADI_MSK(0x00200000,uint32_t))  /* Enable Counter for WPIA4 */
-#define BITM_WPIACTL_ENIA5                   (_ADI_MSK(0x00100000,uint32_t))  /* Enable WPIA5 */
-#define BITM_WPIACTL_ENIA4                   (_ADI_MSK(0x00080000,uint32_t))  /* Enable WPIA4 */
-#define BITM_WPIACTL_INVIR45                 (_ADI_MSK(0x00040000,uint32_t))  /* Invert Instruction Range 45 */
-#define BITM_WPIACTL_ENIR45                  (_ADI_MSK(0x00020000,uint32_t))  /* Enable Instruction Range 45 */
-#define BITM_WPIACTL_ACT3                    (_ADI_MSK(0x00010000,uint32_t))  /* Action field for WPIA3 */
-#define BITM_WPIACTL_ACT2                    (_ADI_MSK(0x00008000,uint32_t))  /* Action field for WPIA2 */
-#define BITM_WPIACTL_ENCNT3                  (_ADI_MSK(0x00004000,uint32_t))  /* Enable Counter for WPIA3 */
-#define BITM_WPIACTL_ENCNT2                  (_ADI_MSK(0x00002000,uint32_t))  /* Enable Counter for WPIA2 */
-#define BITM_WPIACTL_ENIA3                   (_ADI_MSK(0x00001000,uint32_t))  /* Enable WPIA3 */
-#define BITM_WPIACTL_ENIA2                   (_ADI_MSK(0x00000800,uint32_t))  /* Enable WPIA2 */
-#define BITM_WPIACTL_INVIR23                 (_ADI_MSK(0x00000400,uint32_t))  /* Invert Instruction Range 23 */
-#define BITM_WPIACTL_ENIR23                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable Instruction Range 23 */
-#define BITM_WPIACTL_ACT1                    (_ADI_MSK(0x00000100,uint32_t))  /* Action field for WPIA1 */
-#define BITM_WPIACTL_ACT0                    (_ADI_MSK(0x00000080,uint32_t))  /* Action field for WPIA0 */
-#define BITM_WPIACTL_ENCNT1                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Counter for WPIA1 */
-#define BITM_WPIACTL_ENCNT0                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Counter for WPIA0 */
-#define BITM_WPIACTL_ENIA1                   (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPIA1 */
-#define BITM_WPIACTL_ENIA0                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPIA0 */
-#define BITM_WPIACTL_INVIR01                 (_ADI_MSK(0x00000004,uint32_t))  /* Invert Instruction Range 01 */
-#define BITM_WPIACTL_ENIR01                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable Instruction Range 01 */
-#define BITM_WPIACTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACNT_CNT                      0                               /* Count Value */
-#define BITM_WPIACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACTL_ACC1                    12                               /* Access type for WPDA1 */
-#define BITP_WPDACTL_SRC1                    10                               /* DAG Source for WPDA1 */
-#define BITP_WPDACTL_ACC0                     8                               /* Access type for WPDA0 */
-#define BITP_WPDACTL_SRC0                     6                               /* DAG Source for WPDA0 */
-#define BITP_WPDACTL_ENCNT1                   5                               /* Enable WPDA1 Counter */
-#define BITP_WPDACTL_ENCNT0                   4                               /* Enable WPDA0 Counter */
-#define BITP_WPDACTL_ENDA1                    3                               /* Enable WPDA1 */
-#define BITP_WPDACTL_ENDA0                    2                               /* Enable WPDA0 */
-#define BITP_WPDACTL_INVR                     1                               /* Invert Range Comparision */
-#define BITP_WPDACTL_ENR                      0                               /* Enable Range Comparison */
-#define BITM_WPDACTL_ACC1                    (_ADI_MSK(0x00003000,uint32_t))  /* Access type for WPDA1 */
-#define BITM_WPDACTL_SRC1                    (_ADI_MSK(0x00000C00,uint32_t))  /* DAG Source for WPDA1 */
-#define BITM_WPDACTL_ACC0                    (_ADI_MSK(0x00000300,uint32_t))  /* Access type for WPDA0 */
-#define BITM_WPDACTL_SRC0                    (_ADI_MSK(0x000000C0,uint32_t))  /* DAG Source for WPDA0 */
-#define BITM_WPDACTL_ENCNT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable WPDA1 Counter */
-#define BITM_WPDACTL_ENCNT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPDA0 Counter */
-#define BITM_WPDACTL_ENDA1                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPDA1 */
-#define BITM_WPDACTL_ENDA0                   (_ADI_MSK(0x00000004,uint32_t))  /* Enable WPDA0 */
-#define BITM_WPDACTL_INVR                    (_ADI_MSK(0x00000002,uint32_t))  /* Invert Range Comparision */
-#define BITM_WPDACTL_ENR                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable Range Comparison */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACNT_CNT                      0                               /* Count Value */
-#define BITM_WPDACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPSTAT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPSTAT_DA1                       7                               /* WPDA1 match */
-#define BITP_WPSTAT_DA0                       6                               /* WPDA0 or WPDA0:1 range match */
-#define BITP_WPSTAT_IA5                       5                               /* WPIA5 match */
-#define BITP_WPSTAT_IA4                       4                               /* WPIA4 or WPIA4:5 range match */
-#define BITP_WPSTAT_IA3                       3                               /* WPIA3 match */
-#define BITP_WPSTAT_IA2                       2                               /* WPIA2 or WPIA2:3 range match */
-#define BITP_WPSTAT_IA1                       1                               /* WPIA1 match */
-#define BITP_WPSTAT_IA0                       0                               /* WPIA0 or WPIA0:1 range match */
-#define BITM_WPSTAT_DA1                      (_ADI_MSK(0x00000080,uint32_t))  /* WPDA1 match */
-#define BITM_WPSTAT_DA0                      (_ADI_MSK(0x00000040,uint32_t))  /* WPDA0 or WPDA0:1 range match */
-#define BITM_WPSTAT_IA5                      (_ADI_MSK(0x00000020,uint32_t))  /* WPIA5 match */
-#define BITM_WPSTAT_IA4                      (_ADI_MSK(0x00000010,uint32_t))  /* WPIA4 or WPIA4:5 range match */
-#define BITM_WPSTAT_IA3                      (_ADI_MSK(0x00000008,uint32_t))  /* WPIA3 match */
-#define BITM_WPSTAT_IA2                      (_ADI_MSK(0x00000004,uint32_t))  /* WPIA2 or WPIA2:3 range match */
-#define BITM_WPSTAT_IA1                      (_ADI_MSK(0x00000002,uint32_t))  /* WPIA1 match */
-#define BITM_WPSTAT_IA0                      (_ADI_MSK(0x00000001,uint32_t))  /* WPIA0 or WPIA0:1 range match */
-
-/* ==================================================
-        Performance Monitor Registers
-   ================================================== */
-
-/* =========================
-        PF0
-   ========================= */
-#define PFCTL                           0xFFE08000         /* Performance Monitor Control Register */
-#define PFCNTR0                         0xFFE08100         /* Performance Monitor Counter 0 */
-#define PFCNTR1                         0xFFE08104         /* Performance Monitor Counter 1 */
-
-/* =========================
-        PF
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PFCTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PFCTL_CNT1                      25                               /* Count Cycles or Edges 1 */
-#define BITP_PFCTL_CNT0                      24                               /* Count Cycles or Edges 0 */
-#define BITP_PFCTL_MON1                      16                               /* Monitor 1 Events */
-#define BITP_PFCTL_ENA1                      14                               /* Enable Monitor 1 */
-#define BITP_PFCTL_EVENT1                    13                               /* Emulator or Exception Event 1 */
-#define BITP_PFCTL_MON0                       5                               /* Monitor 0 Events */
-#define BITP_PFCTL_ENA0                       3                               /* Enable Monitor 0 */
-#define BITP_PFCTL_EVENT0                     2                               /* Emulator or Exception Event 0 */
-#define BITP_PFCTL_PWR                        0                               /* Power */
-#define BITM_PFCTL_CNT1                      (_ADI_MSK(0x02000000,uint32_t))  /* Count Cycles or Edges 1 */
-#define BITM_PFCTL_CNT0                      (_ADI_MSK(0x01000000,uint32_t))  /* Count Cycles or Edges 0 */
-#define BITM_PFCTL_MON1                      (_ADI_MSK(0x00FF0000,uint32_t))  /* Monitor 1 Events */
-#define BITM_PFCTL_ENA1                      (_ADI_MSK(0x0000C000,uint32_t))  /* Enable Monitor 1 */
-#define BITM_PFCTL_EVENT1                    (_ADI_MSK(0x00002000,uint32_t))  /* Emulator or Exception Event 1 */
-#define BITM_PFCTL_MON0                      (_ADI_MSK(0x00001FE0,uint32_t))  /* Monitor 0 Events */
-#define BITM_PFCTL_ENA0                      (_ADI_MSK(0x00000018,uint32_t))  /* Enable Monitor 0 */
-#define BITM_PFCTL_EVENT0                    (_ADI_MSK(0x00000004,uint32_t))  /* Emulator or Exception Event 0 */
-#define BITM_PFCTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ==================================
-       DMA Alias Definitions
-   ================================== */
-#define SPORT0_A_DMA_DSCPTR_NXT              (REG_DMA0_DSCPTR_NXT)
-#define SPORT0_A_DMA_ADDRSTART               (REG_DMA0_ADDRSTART)
-#define SPORT0_A_DMA_CFG                     (REG_DMA0_CFG)
-#define SPORT0_A_DMA_XCNT                    (REG_DMA0_XCNT)
-#define SPORT0_A_DMA_XMOD                    (REG_DMA0_XMOD)
-#define SPORT0_A_DMA_YCNT                    (REG_DMA0_YCNT)
-#define SPORT0_A_DMA_YMOD                    (REG_DMA0_YMOD)
-#define SPORT0_A_DMA_DSCPTR_CUR              (REG_DMA0_DSCPTR_CUR)
-#define SPORT0_A_DMA_DSCPTR_PRV              (REG_DMA0_DSCPTR_PRV)
-#define SPORT0_A_DMA_ADDR_CUR                (REG_DMA0_ADDR_CUR)
-#define SPORT0_A_DMA_STAT                    (REG_DMA0_STAT)
-#define SPORT0_A_DMA_XCNT_CUR                (REG_DMA0_XCNT_CUR)
-#define SPORT0_A_DMA_YCNT_CUR                (REG_DMA0_YCNT_CUR)
-#define SPORT0_A_DMA_BWLCNT                  (REG_DMA0_BWLCNT)
-#define SPORT0_A_DMA_BWLCNT_CUR              (REG_DMA0_BWLCNT_CUR)
-#define SPORT0_A_DMA_BWMCNT                  (REG_DMA0_BWMCNT)
-#define SPORT0_A_DMA_BWMCNT_CUR              (REG_DMA0_BWMCNT_CUR)
-#define SPORT0_B_DMA_DSCPTR_NXT              (REG_DMA1_DSCPTR_NXT)
-#define SPORT0_B_DMA_ADDRSTART               (REG_DMA1_ADDRSTART)
-#define SPORT0_B_DMA_CFG                     (REG_DMA1_CFG)
-#define SPORT0_B_DMA_XCNT                    (REG_DMA1_XCNT)
-#define SPORT0_B_DMA_XMOD                    (REG_DMA1_XMOD)
-#define SPORT0_B_DMA_YCNT                    (REG_DMA1_YCNT)
-#define SPORT0_B_DMA_YMOD                    (REG_DMA1_YMOD)
-#define SPORT0_B_DMA_DSCPTR_CUR              (REG_DMA1_DSCPTR_CUR)
-#define SPORT0_B_DMA_DSCPTR_PRV              (REG_DMA1_DSCPTR_PRV)
-#define SPORT0_B_DMA_ADDR_CUR                (REG_DMA1_ADDR_CUR)
-#define SPORT0_B_DMA_STAT                    (REG_DMA1_STAT)
-#define SPORT0_B_DMA_XCNT_CUR                (REG_DMA1_XCNT_CUR)
-#define SPORT0_B_DMA_YCNT_CUR                (REG_DMA1_YCNT_CUR)
-#define SPORT0_B_DMA_BWLCNT                  (REG_DMA1_BWLCNT)
-#define SPORT0_B_DMA_BWLCNT_CUR              (REG_DMA1_BWLCNT_CUR)
-#define SPORT0_B_DMA_BWMCNT                  (REG_DMA1_BWMCNT)
-#define SPORT0_B_DMA_BWMCNT_CUR              (REG_DMA1_BWMCNT_CUR)
-#define SPORT1_A_DMA_DSCPTR_NXT              (REG_DMA2_DSCPTR_NXT)
-#define SPORT1_A_DMA_ADDRSTART               (REG_DMA2_ADDRSTART)
-#define SPORT1_A_DMA_CFG                     (REG_DMA2_CFG)
-#define SPORT1_A_DMA_XCNT                    (REG_DMA2_XCNT)
-#define SPORT1_A_DMA_XMOD                    (REG_DMA2_XMOD)
-#define SPORT1_A_DMA_YCNT                    (REG_DMA2_YCNT)
-#define SPORT1_A_DMA_YMOD                    (REG_DMA2_YMOD)
-#define SPORT1_A_DMA_DSCPTR_CUR              (REG_DMA2_DSCPTR_CUR)
-#define SPORT1_A_DMA_DSCPTR_PRV              (REG_DMA2_DSCPTR_PRV)
-#define SPORT1_A_DMA_ADDR_CUR                (REG_DMA2_ADDR_CUR)
-#define SPORT1_A_DMA_STAT                    (REG_DMA2_STAT)
-#define SPORT1_A_DMA_XCNT_CUR                (REG_DMA2_XCNT_CUR)
-#define SPORT1_A_DMA_YCNT_CUR                (REG_DMA2_YCNT_CUR)
-#define SPORT1_A_DMA_BWLCNT                  (REG_DMA2_BWLCNT)
-#define SPORT1_A_DMA_BWLCNT_CUR              (REG_DMA2_BWLCNT_CUR)
-#define SPORT1_A_DMA_BWMCNT                  (REG_DMA2_BWMCNT)
-#define SPORT1_A_DMA_BWMCNT_CUR              (REG_DMA2_BWMCNT_CUR)
-#define SPORT1_B_DMA_DSCPTR_NXT              (REG_DMA3_DSCPTR_NXT)
-#define SPORT1_B_DMA_ADDRSTART               (REG_DMA3_ADDRSTART)
-#define SPORT1_B_DMA_CFG                     (REG_DMA3_CFG)
-#define SPORT1_B_DMA_XCNT                    (REG_DMA3_XCNT)
-#define SPORT1_B_DMA_XMOD                    (REG_DMA3_XMOD)
-#define SPORT1_B_DMA_YCNT                    (REG_DMA3_YCNT)
-#define SPORT1_B_DMA_YMOD                    (REG_DMA3_YMOD)
-#define SPORT1_B_DMA_DSCPTR_CUR              (REG_DMA3_DSCPTR_CUR)
-#define SPORT1_B_DMA_DSCPTR_PRV              (REG_DMA3_DSCPTR_PRV)
-#define SPORT1_B_DMA_ADDR_CUR                (REG_DMA3_ADDR_CUR)
-#define SPORT1_B_DMA_STAT                    (REG_DMA3_STAT)
-#define SPORT1_B_DMA_XCNT_CUR                (REG_DMA3_XCNT_CUR)
-#define SPORT1_B_DMA_YCNT_CUR                (REG_DMA3_YCNT_CUR)
-#define SPORT1_B_DMA_BWLCNT                  (REG_DMA3_BWLCNT)
-#define SPORT1_B_DMA_BWLCNT_CUR              (REG_DMA3_BWLCNT_CUR)
-#define SPORT1_B_DMA_BWMCNT                  (REG_DMA3_BWMCNT)
-#define SPORT1_B_DMA_BWMCNT_CUR              (REG_DMA3_BWMCNT_CUR)
-#define SPORT2_A_DMA_DSCPTR_NXT              (REG_DMA4_DSCPTR_NXT)
-#define SPORT2_A_DMA_ADDRSTART               (REG_DMA4_ADDRSTART)
-#define SPORT2_A_DMA_CFG                     (REG_DMA4_CFG)
-#define SPORT2_A_DMA_XCNT                    (REG_DMA4_XCNT)
-#define SPORT2_A_DMA_XMOD                    (REG_DMA4_XMOD)
-#define SPORT2_A_DMA_YCNT                    (REG_DMA4_YCNT)
-#define SPORT2_A_DMA_YMOD                    (REG_DMA4_YMOD)
-#define SPORT2_A_DMA_DSCPTR_CUR              (REG_DMA4_DSCPTR_CUR)
-#define SPORT2_A_DMA_DSCPTR_PRV              (REG_DMA4_DSCPTR_PRV)
-#define SPORT2_A_DMA_ADDR_CUR                (REG_DMA4_ADDR_CUR)
-#define SPORT2_A_DMA_STAT                    (REG_DMA4_STAT)
-#define SPORT2_A_DMA_XCNT_CUR                (REG_DMA4_XCNT_CUR)
-#define SPORT2_A_DMA_YCNT_CUR                (REG_DMA4_YCNT_CUR)
-#define SPORT2_A_DMA_BWLCNT                  (REG_DMA4_BWLCNT)
-#define SPORT2_A_DMA_BWLCNT_CUR              (REG_DMA4_BWLCNT_CUR)
-#define SPORT2_A_DMA_BWMCNT                  (REG_DMA4_BWMCNT)
-#define SPORT2_A_DMA_BWMCNT_CUR              (REG_DMA4_BWMCNT_CUR)
-#define SPORT2_B_DMA_DSCPTR_NXT              (REG_DMA5_DSCPTR_NXT)
-#define SPORT2_B_DMA_ADDRSTART               (REG_DMA5_ADDRSTART)
-#define SPORT2_B_DMA_CFG                     (REG_DMA5_CFG)
-#define SPORT2_B_DMA_XCNT                    (REG_DMA5_XCNT)
-#define SPORT2_B_DMA_XMOD                    (REG_DMA5_XMOD)
-#define SPORT2_B_DMA_YCNT                    (REG_DMA5_YCNT)
-#define SPORT2_B_DMA_YMOD                    (REG_DMA5_YMOD)
-#define SPORT2_B_DMA_DSCPTR_CUR              (REG_DMA5_DSCPTR_CUR)
-#define SPORT2_B_DMA_DSCPTR_PRV              (REG_DMA5_DSCPTR_PRV)
-#define SPORT2_B_DMA_ADDR_CUR                (REG_DMA5_ADDR_CUR)
-#define SPORT2_B_DMA_STAT                    (REG_DMA5_STAT)
-#define SPORT2_B_DMA_XCNT_CUR                (REG_DMA5_XCNT_CUR)
-#define SPORT2_B_DMA_YCNT_CUR                (REG_DMA5_YCNT_CUR)
-#define SPORT2_B_DMA_BWLCNT                  (REG_DMA5_BWLCNT)
-#define SPORT2_B_DMA_BWLCNT_CUR              (REG_DMA5_BWLCNT_CUR)
-#define SPORT2_B_DMA_BWMCNT                  (REG_DMA5_BWMCNT)
-#define SPORT2_B_DMA_BWMCNT_CUR              (REG_DMA5_BWMCNT_CUR)
-#define SPI0_TXDMA_DSCPTR_NXT                (REG_DMA6_DSCPTR_NXT)
-#define SPI0_TXDMA_ADDRSTART                 (REG_DMA6_ADDRSTART)
-#define SPI0_TXDMA_CFG                       (REG_DMA6_CFG)
-#define SPI0_TXDMA_XCNT                      (REG_DMA6_XCNT)
-#define SPI0_TXDMA_XMOD                      (REG_DMA6_XMOD)
-#define SPI0_TXDMA_YCNT                      (REG_DMA6_YCNT)
-#define SPI0_TXDMA_YMOD                      (REG_DMA6_YMOD)
-#define SPI0_TXDMA_DSCPTR_CUR                (REG_DMA6_DSCPTR_CUR)
-#define SPI0_TXDMA_DSCPTR_PRV                (REG_DMA6_DSCPTR_PRV)
-#define SPI0_TXDMA_ADDR_CUR                  (REG_DMA6_ADDR_CUR)
-#define SPI0_TXDMA_STAT                      (REG_DMA6_STAT)
-#define SPI0_TXDMA_XCNT_CUR                  (REG_DMA6_XCNT_CUR)
-#define SPI0_TXDMA_YCNT_CUR                  (REG_DMA6_YCNT_CUR)
-#define SPI0_TXDMA_BWLCNT                    (REG_DMA6_BWLCNT)
-#define SPI0_TXDMA_BWLCNT_CUR                (REG_DMA6_BWLCNT_CUR)
-#define SPI0_TXDMA_BWMCNT                    (REG_DMA6_BWMCNT)
-#define SPI0_TXDMA_BWMCNT_CUR                (REG_DMA6_BWMCNT_CUR)
-#define SPI0_RXDMA_DSCPTR_NXT                (REG_DMA7_DSCPTR_NXT)
-#define SPI0_RXDMA_ADDRSTART                 (REG_DMA7_ADDRSTART)
-#define SPI0_RXDMA_CFG                       (REG_DMA7_CFG)
-#define SPI0_RXDMA_XCNT                      (REG_DMA7_XCNT)
-#define SPI0_RXDMA_XMOD                      (REG_DMA7_XMOD)
-#define SPI0_RXDMA_YCNT                      (REG_DMA7_YCNT)
-#define SPI0_RXDMA_YMOD                      (REG_DMA7_YMOD)
-#define SPI0_RXDMA_DSCPTR_CUR                (REG_DMA7_DSCPTR_CUR)
-#define SPI0_RXDMA_DSCPTR_PRV                (REG_DMA7_DSCPTR_PRV)
-#define SPI0_RXDMA_ADDR_CUR                  (REG_DMA7_ADDR_CUR)
-#define SPI0_RXDMA_STAT                      (REG_DMA7_STAT)
-#define SPI0_RXDMA_XCNT_CUR                  (REG_DMA7_XCNT_CUR)
-#define SPI0_RXDMA_YCNT_CUR                  (REG_DMA7_YCNT_CUR)
-#define SPI0_RXDMA_BWLCNT                    (REG_DMA7_BWLCNT)
-#define SPI0_RXDMA_BWLCNT_CUR                (REG_DMA7_BWLCNT_CUR)
-#define SPI0_RXDMA_BWMCNT                    (REG_DMA7_BWMCNT)
-#define SPI0_RXDMA_BWMCNT_CUR                (REG_DMA7_BWMCNT_CUR)
-#define SPI1_TXDMA_DSCPTR_NXT                (REG_DMA8_DSCPTR_NXT)
-#define SPI1_TXDMA_ADDRSTART                 (REG_DMA8_ADDRSTART)
-#define SPI1_TXDMA_CFG                       (REG_DMA8_CFG)
-#define SPI1_TXDMA_XCNT                      (REG_DMA8_XCNT)
-#define SPI1_TXDMA_XMOD                      (REG_DMA8_XMOD)
-#define SPI1_TXDMA_YCNT                      (REG_DMA8_YCNT)
-#define SPI1_TXDMA_YMOD                      (REG_DMA8_YMOD)
-#define SPI1_TXDMA_DSCPTR_CUR                (REG_DMA8_DSCPTR_CUR)
-#define SPI1_TXDMA_DSCPTR_PRV                (REG_DMA8_DSCPTR_PRV)
-#define SPI1_TXDMA_ADDR_CUR                  (REG_DMA8_ADDR_CUR)
-#define SPI1_TXDMA_STAT                      (REG_DMA8_STAT)
-#define SPI1_TXDMA_XCNT_CUR                  (REG_DMA8_XCNT_CUR)
-#define SPI1_TXDMA_YCNT_CUR                  (REG_DMA8_YCNT_CUR)
-#define SPI1_TXDMA_BWLCNT                    (REG_DMA8_BWLCNT)
-#define SPI1_TXDMA_BWLCNT_CUR                (REG_DMA8_BWLCNT_CUR)
-#define SPI1_TXDMA_BWMCNT                    (REG_DMA8_BWMCNT)
-#define SPI1_TXDMA_BWMCNT_CUR                (REG_DMA8_BWMCNT_CUR)
-#define SPI1_RXDMA_DSCPTR_NXT                (REG_DMA9_DSCPTR_NXT)
-#define SPI1_RXDMA_ADDRSTART                 (REG_DMA9_ADDRSTART)
-#define SPI1_RXDMA_CFG                       (REG_DMA9_CFG)
-#define SPI1_RXDMA_XCNT                      (REG_DMA9_XCNT)
-#define SPI1_RXDMA_XMOD                      (REG_DMA9_XMOD)
-#define SPI1_RXDMA_YCNT                      (REG_DMA9_YCNT)
-#define SPI1_RXDMA_YMOD                      (REG_DMA9_YMOD)
-#define SPI1_RXDMA_DSCPTR_CUR                (REG_DMA9_DSCPTR_CUR)
-#define SPI1_RXDMA_DSCPTR_PRV                (REG_DMA9_DSCPTR_PRV)
-#define SPI1_RXDMA_ADDR_CUR                  (REG_DMA9_ADDR_CUR)
-#define SPI1_RXDMA_STAT                      (REG_DMA9_STAT)
-#define SPI1_RXDMA_XCNT_CUR                  (REG_DMA9_XCNT_CUR)
-#define SPI1_RXDMA_YCNT_CUR                  (REG_DMA9_YCNT_CUR)
-#define SPI1_RXDMA_BWLCNT                    (REG_DMA9_BWLCNT)
-#define SPI1_RXDMA_BWLCNT_CUR                (REG_DMA9_BWLCNT_CUR)
-#define SPI1_RXDMA_BWMCNT                    (REG_DMA9_BWMCNT)
-#define SPI1_RXDMA_BWMCNT_CUR                (REG_DMA9_BWMCNT_CUR)
-#define RSI0_DMA_DSCPTR_NXT                  (REG_DMA10_DSCPTR_NXT)
-#define RSI0_DMA_ADDRSTART                   (REG_DMA10_ADDRSTART)
-#define RSI0_DMA_CFG                         (REG_DMA10_CFG)
-#define RSI0_DMA_XCNT                        (REG_DMA10_XCNT)
-#define RSI0_DMA_XMOD                        (REG_DMA10_XMOD)
-#define RSI0_DMA_YCNT                        (REG_DMA10_YCNT)
-#define RSI0_DMA_YMOD                        (REG_DMA10_YMOD)
-#define RSI0_DMA_DSCPTR_CUR                  (REG_DMA10_DSCPTR_CUR)
-#define RSI0_DMA_DSCPTR_PRV                  (REG_DMA10_DSCPTR_PRV)
-#define RSI0_DMA_ADDR_CUR                    (REG_DMA10_ADDR_CUR)
-#define RSI0_DMA_STAT                        (REG_DMA10_STAT)
-#define RSI0_DMA_XCNT_CUR                    (REG_DMA10_XCNT_CUR)
-#define RSI0_DMA_YCNT_CUR                    (REG_DMA10_YCNT_CUR)
-#define RSI0_DMA_BWLCNT                      (REG_DMA10_BWLCNT)
-#define RSI0_DMA_BWLCNT_CUR                  (REG_DMA10_BWLCNT_CUR)
-#define RSI0_DMA_BWMCNT                      (REG_DMA10_BWMCNT)
-#define RSI0_DMA_BWMCNT_CUR                  (REG_DMA10_BWMCNT_CUR)
-#define SDU0_DMA_DSCPTR_NXT                  (REG_DMA11_DSCPTR_NXT)
-#define SDU0_DMA_ADDRSTART                   (REG_DMA11_ADDRSTART)
-#define SDU0_DMA_CFG                         (REG_DMA11_CFG)
-#define SDU0_DMA_XCNT                        (REG_DMA11_XCNT)
-#define SDU0_DMA_XMOD                        (REG_DMA11_XMOD)
-#define SDU0_DMA_YCNT                        (REG_DMA11_YCNT)
-#define SDU0_DMA_YMOD                        (REG_DMA11_YMOD)
-#define SDU0_DMA_DSCPTR_CUR                  (REG_DMA11_DSCPTR_CUR)
-#define SDU0_DMA_DSCPTR_PRV                  (REG_DMA11_DSCPTR_PRV)
-#define SDU0_DMA_ADDR_CUR                    (REG_DMA11_ADDR_CUR)
-#define SDU0_DMA_STAT                        (REG_DMA11_STAT)
-#define SDU0_DMA_XCNT_CUR                    (REG_DMA11_XCNT_CUR)
-#define SDU0_DMA_YCNT_CUR                    (REG_DMA11_YCNT_CUR)
-#define SDU0_DMA_BWLCNT                      (REG_DMA11_BWLCNT)
-#define SDU0_DMA_BWLCNT_CUR                  (REG_DMA11_BWLCNT_CUR)
-#define SDU0_DMA_BWMCNT                      (REG_DMA11_BWMCNT)
-#define SDU0_DMA_BWMCNT_CUR                  (REG_DMA11_BWMCNT_CUR)
-#define LP0_DMA_DSCPTR_NXT                   (REG_DMA13_DSCPTR_NXT)
-#define LP0_DMA_ADDRSTART                    (REG_DMA13_ADDRSTART)
-#define LP0_DMA_CFG                          (REG_DMA13_CFG)
-#define LP0_DMA_XCNT                         (REG_DMA13_XCNT)
-#define LP0_DMA_XMOD                         (REG_DMA13_XMOD)
-#define LP0_DMA_YCNT                         (REG_DMA13_YCNT)
-#define LP0_DMA_YMOD                         (REG_DMA13_YMOD)
-#define LP0_DMA_DSCPTR_CUR                   (REG_DMA13_DSCPTR_CUR)
-#define LP0_DMA_DSCPTR_PRV                   (REG_DMA13_DSCPTR_PRV)
-#define LP0_DMA_ADDR_CUR                     (REG_DMA13_ADDR_CUR)
-#define LP0_DMA_STAT                         (REG_DMA13_STAT)
-#define LP0_DMA_XCNT_CUR                     (REG_DMA13_XCNT_CUR)
-#define LP0_DMA_YCNT_CUR                     (REG_DMA13_YCNT_CUR)
-#define LP0_DMA_BWLCNT                       (REG_DMA13_BWLCNT)
-#define LP0_DMA_BWLCNT_CUR                   (REG_DMA13_BWLCNT_CUR)
-#define LP0_DMA_BWMCNT                       (REG_DMA13_BWMCNT)
-#define LP0_DMA_BWMCNT_CUR                   (REG_DMA13_BWMCNT_CUR)
-#define LP1_DMA_DSCPTR_NXT                   (REG_DMA14_DSCPTR_NXT)
-#define LP1_DMA_ADDRSTART                    (REG_DMA14_ADDRSTART)
-#define LP1_DMA_CFG                          (REG_DMA14_CFG)
-#define LP1_DMA_XCNT                         (REG_DMA14_XCNT)
-#define LP1_DMA_XMOD                         (REG_DMA14_XMOD)
-#define LP1_DMA_YCNT                         (REG_DMA14_YCNT)
-#define LP1_DMA_YMOD                         (REG_DMA14_YMOD)
-#define LP1_DMA_DSCPTR_CUR                   (REG_DMA14_DSCPTR_CUR)
-#define LP1_DMA_DSCPTR_PRV                   (REG_DMA14_DSCPTR_PRV)
-#define LP1_DMA_ADDR_CUR                     (REG_DMA14_ADDR_CUR)
-#define LP1_DMA_STAT                         (REG_DMA14_STAT)
-#define LP1_DMA_XCNT_CUR                     (REG_DMA14_XCNT_CUR)
-#define LP1_DMA_YCNT_CUR                     (REG_DMA14_YCNT_CUR)
-#define LP1_DMA_BWLCNT                       (REG_DMA14_BWLCNT)
-#define LP1_DMA_BWLCNT_CUR                   (REG_DMA14_BWLCNT_CUR)
-#define LP1_DMA_BWMCNT                       (REG_DMA14_BWMCNT)
-#define LP1_DMA_BWMCNT_CUR                   (REG_DMA14_BWMCNT_CUR)
-#define LP2_DMA_DSCPTR_NXT                   (REG_DMA15_DSCPTR_NXT)
-#define LP2_DMA_ADDRSTART                    (REG_DMA15_ADDRSTART)
-#define LP2_DMA_CFG                          (REG_DMA15_CFG)
-#define LP2_DMA_XCNT                         (REG_DMA15_XCNT)
-#define LP2_DMA_XMOD                         (REG_DMA15_XMOD)
-#define LP2_DMA_YCNT                         (REG_DMA15_YCNT)
-#define LP2_DMA_YMOD                         (REG_DMA15_YMOD)
-#define LP2_DMA_DSCPTR_CUR                   (REG_DMA15_DSCPTR_CUR)
-#define LP2_DMA_DSCPTR_PRV                   (REG_DMA15_DSCPTR_PRV)
-#define LP2_DMA_ADDR_CUR                     (REG_DMA15_ADDR_CUR)
-#define LP2_DMA_STAT                         (REG_DMA15_STAT)
-#define LP2_DMA_XCNT_CUR                     (REG_DMA15_XCNT_CUR)
-#define LP2_DMA_YCNT_CUR                     (REG_DMA15_YCNT_CUR)
-#define LP2_DMA_BWLCNT                       (REG_DMA15_BWLCNT)
-#define LP2_DMA_BWLCNT_CUR                   (REG_DMA15_BWLCNT_CUR)
-#define LP2_DMA_BWMCNT                       (REG_DMA15_BWMCNT)
-#define LP2_DMA_BWMCNT_CUR                   (REG_DMA15_BWMCNT_CUR)
-#define LP3_DMA_DSCPTR_NXT                   (REG_DMA16_DSCPTR_NXT)
-#define LP3_DMA_ADDRSTART                    (REG_DMA16_ADDRSTART)
-#define LP3_DMA_CFG                          (REG_DMA16_CFG)
-#define LP3_DMA_XCNT                         (REG_DMA16_XCNT)
-#define LP3_DMA_XMOD                         (REG_DMA16_XMOD)
-#define LP3_DMA_YCNT                         (REG_DMA16_YCNT)
-#define LP3_DMA_YMOD                         (REG_DMA16_YMOD)
-#define LP3_DMA_DSCPTR_CUR                   (REG_DMA16_DSCPTR_CUR)
-#define LP3_DMA_DSCPTR_PRV                   (REG_DMA16_DSCPTR_PRV)
-#define LP3_DMA_ADDR_CUR                     (REG_DMA16_ADDR_CUR)
-#define LP3_DMA_STAT                         (REG_DMA16_STAT)
-#define LP3_DMA_XCNT_CUR                     (REG_DMA16_XCNT_CUR)
-#define LP3_DMA_YCNT_CUR                     (REG_DMA16_YCNT_CUR)
-#define LP3_DMA_BWLCNT                       (REG_DMA16_BWLCNT)
-#define LP3_DMA_BWLCNT_CUR                   (REG_DMA16_BWLCNT_CUR)
-#define LP3_DMA_BWMCNT                       (REG_DMA16_BWMCNT)
-#define LP3_DMA_BWMCNT_CUR                   (REG_DMA16_BWMCNT_CUR)
-#define UART0_TXDMA_DSCPTR_NXT               (REG_DMA17_DSCPTR_NXT)
-#define UART0_TXDMA_ADDRSTART                (REG_DMA17_ADDRSTART)
-#define UART0_TXDMA_CFG                      (REG_DMA17_CFG)
-#define UART0_TXDMA_XCNT                     (REG_DMA17_XCNT)
-#define UART0_TXDMA_XMOD                     (REG_DMA17_XMOD)
-#define UART0_TXDMA_YCNT                     (REG_DMA17_YCNT)
-#define UART0_TXDMA_YMOD                     (REG_DMA17_YMOD)
-#define UART0_TXDMA_DSCPTR_CUR               (REG_DMA17_DSCPTR_CUR)
-#define UART0_TXDMA_DSCPTR_PRV               (REG_DMA17_DSCPTR_PRV)
-#define UART0_TXDMA_ADDR_CUR                 (REG_DMA17_ADDR_CUR)
-#define UART0_TXDMA_STAT                     (REG_DMA17_STAT)
-#define UART0_TXDMA_XCNT_CUR                 (REG_DMA17_XCNT_CUR)
-#define UART0_TXDMA_YCNT_CUR                 (REG_DMA17_YCNT_CUR)
-#define UART0_TXDMA_BWLCNT                   (REG_DMA17_BWLCNT)
-#define UART0_TXDMA_BWLCNT_CUR               (REG_DMA17_BWLCNT_CUR)
-#define UART0_TXDMA_BWMCNT                   (REG_DMA17_BWMCNT)
-#define UART0_TXDMA_BWMCNT_CUR               (REG_DMA17_BWMCNT_CUR)
-#define UART0_RXDMA_DSCPTR_NXT               (REG_DMA18_DSCPTR_NXT)
-#define UART0_RXDMA_ADDRSTART                (REG_DMA18_ADDRSTART)
-#define UART0_RXDMA_CFG                      (REG_DMA18_CFG)
-#define UART0_RXDMA_XCNT                     (REG_DMA18_XCNT)
-#define UART0_RXDMA_XMOD                     (REG_DMA18_XMOD)
-#define UART0_RXDMA_YCNT                     (REG_DMA18_YCNT)
-#define UART0_RXDMA_YMOD                     (REG_DMA18_YMOD)
-#define UART0_RXDMA_DSCPTR_CUR               (REG_DMA18_DSCPTR_CUR)
-#define UART0_RXDMA_DSCPTR_PRV               (REG_DMA18_DSCPTR_PRV)
-#define UART0_RXDMA_ADDR_CUR                 (REG_DMA18_ADDR_CUR)
-#define UART0_RXDMA_STAT                     (REG_DMA18_STAT)
-#define UART0_RXDMA_XCNT_CUR                 (REG_DMA18_XCNT_CUR)
-#define UART0_RXDMA_YCNT_CUR                 (REG_DMA18_YCNT_CUR)
-#define UART0_RXDMA_BWLCNT                   (REG_DMA18_BWLCNT)
-#define UART0_RXDMA_BWLCNT_CUR               (REG_DMA18_BWLCNT_CUR)
-#define UART0_RXDMA_BWMCNT                   (REG_DMA18_BWMCNT)
-#define UART0_RXDMA_BWMCNT_CUR               (REG_DMA18_BWMCNT_CUR)
-#define UART1_TXDMA_DSCPTR_NXT               (REG_DMA19_DSCPTR_NXT)
-#define UART1_TXDMA_ADDRSTART                (REG_DMA19_ADDRSTART)
-#define UART1_TXDMA_CFG                      (REG_DMA19_CFG)
-#define UART1_TXDMA_XCNT                     (REG_DMA19_XCNT)
-#define UART1_TXDMA_XMOD                     (REG_DMA19_XMOD)
-#define UART1_TXDMA_YCNT                     (REG_DMA19_YCNT)
-#define UART1_TXDMA_YMOD                     (REG_DMA19_YMOD)
-#define UART1_TXDMA_DSCPTR_CUR               (REG_DMA19_DSCPTR_CUR)
-#define UART1_TXDMA_DSCPTR_PRV               (REG_DMA19_DSCPTR_PRV)
-#define UART1_TXDMA_ADDR_CUR                 (REG_DMA19_ADDR_CUR)
-#define UART1_TXDMA_STAT                     (REG_DMA19_STAT)
-#define UART1_TXDMA_XCNT_CUR                 (REG_DMA19_XCNT_CUR)
-#define UART1_TXDMA_YCNT_CUR                 (REG_DMA19_YCNT_CUR)
-#define UART1_TXDMA_BWLCNT                   (REG_DMA19_BWLCNT)
-#define UART1_TXDMA_BWLCNT_CUR               (REG_DMA19_BWLCNT_CUR)
-#define UART1_TXDMA_BWMCNT                   (REG_DMA19_BWMCNT)
-#define UART1_TXDMA_BWMCNT_CUR               (REG_DMA19_BWMCNT_CUR)
-#define UART1_RXDMA_DSCPTR_NXT               (REG_DMA20_DSCPTR_NXT)
-#define UART1_RXDMA_ADDRSTART                (REG_DMA20_ADDRSTART)
-#define UART1_RXDMA_CFG                      (REG_DMA20_CFG)
-#define UART1_RXDMA_XCNT                     (REG_DMA20_XCNT)
-#define UART1_RXDMA_XMOD                     (REG_DMA20_XMOD)
-#define UART1_RXDMA_YCNT                     (REG_DMA20_YCNT)
-#define UART1_RXDMA_YMOD                     (REG_DMA20_YMOD)
-#define UART1_RXDMA_DSCPTR_CUR               (REG_DMA20_DSCPTR_CUR)
-#define UART1_RXDMA_DSCPTR_PRV               (REG_DMA20_DSCPTR_PRV)
-#define UART1_RXDMA_ADDR_CUR                 (REG_DMA20_ADDR_CUR)
-#define UART1_RXDMA_STAT                     (REG_DMA20_STAT)
-#define UART1_RXDMA_XCNT_CUR                 (REG_DMA20_XCNT_CUR)
-#define UART1_RXDMA_YCNT_CUR                 (REG_DMA20_YCNT_CUR)
-#define UART1_RXDMA_BWLCNT                   (REG_DMA20_BWLCNT)
-#define UART1_RXDMA_BWLCNT_CUR               (REG_DMA20_BWLCNT_CUR)
-#define UART1_RXDMA_BWMCNT                   (REG_DMA20_BWMCNT)
-#define UART1_RXDMA_BWMCNT_CUR               (REG_DMA20_BWMCNT_CUR)
-#define MDMA0_SRC_DSCPTR_NXT                 (REG_DMA21_DSCPTR_NXT)
-#define MDMA0_SRC_ADDRSTART                  (REG_DMA21_ADDRSTART)
-#define MDMA0_SRC_CFG                        (REG_DMA21_CFG)
-#define MDMA0_SRC_XCNT                       (REG_DMA21_XCNT)
-#define MDMA0_SRC_XMOD                       (REG_DMA21_XMOD)
-#define MDMA0_SRC_YCNT                       (REG_DMA21_YCNT)
-#define MDMA0_SRC_YMOD                       (REG_DMA21_YMOD)
-#define MDMA0_SRC_DSCPTR_CUR                 (REG_DMA21_DSCPTR_CUR)
-#define MDMA0_SRC_DSCPTR_PRV                 (REG_DMA21_DSCPTR_PRV)
-#define MDMA0_SRC_ADDR_CUR                   (REG_DMA21_ADDR_CUR)
-#define MDMA0_SRC_STAT                       (REG_DMA21_STAT)
-#define MDMA0_SRC_XCNT_CUR                   (REG_DMA21_XCNT_CUR)
-#define MDMA0_SRC_YCNT_CUR                   (REG_DMA21_YCNT_CUR)
-#define MDMA0_SRC_BWLCNT                     (REG_DMA21_BWLCNT)
-#define MDMA0_SRC_BWLCNT_CUR                 (REG_DMA21_BWLCNT_CUR)
-#define MDMA0_SRC_BWMCNT                     (REG_DMA21_BWMCNT)
-#define MDMA0_SRC_BWMCNT_CUR                 (REG_DMA21_BWMCNT_CUR)
-#define MDMA0_DST_DSCPTR_NXT                 (REG_DMA22_DSCPTR_NXT)
-#define MDMA0_DST_ADDRSTART                  (REG_DMA22_ADDRSTART)
-#define MDMA0_DST_CFG                        (REG_DMA22_CFG)
-#define MDMA0_DST_XCNT                       (REG_DMA22_XCNT)
-#define MDMA0_DST_XMOD                       (REG_DMA22_XMOD)
-#define MDMA0_DST_YCNT                       (REG_DMA22_YCNT)
-#define MDMA0_DST_YMOD                       (REG_DMA22_YMOD)
-#define MDMA0_DST_DSCPTR_CUR                 (REG_DMA22_DSCPTR_CUR)
-#define MDMA0_DST_DSCPTR_PRV                 (REG_DMA22_DSCPTR_PRV)
-#define MDMA0_DST_ADDR_CUR                   (REG_DMA22_ADDR_CUR)
-#define MDMA0_DST_STAT                       (REG_DMA22_STAT)
-#define MDMA0_DST_XCNT_CUR                   (REG_DMA22_XCNT_CUR)
-#define MDMA0_DST_YCNT_CUR                   (REG_DMA22_YCNT_CUR)
-#define MDMA0_DST_BWLCNT                     (REG_DMA22_BWLCNT)
-#define MDMA0_DST_BWLCNT_CUR                 (REG_DMA22_BWLCNT_CUR)
-#define MDMA0_DST_BWMCNT                     (REG_DMA22_BWMCNT)
-#define MDMA0_DST_BWMCNT_CUR                 (REG_DMA22_BWMCNT_CUR)
-#define MDMA1_SRC_DSCPTR_NXT                 (REG_DMA23_DSCPTR_NXT)
-#define MDMA1_SRC_ADDRSTART                  (REG_DMA23_ADDRSTART)
-#define MDMA1_SRC_CFG                        (REG_DMA23_CFG)
-#define MDMA1_SRC_XCNT                       (REG_DMA23_XCNT)
-#define MDMA1_SRC_XMOD                       (REG_DMA23_XMOD)
-#define MDMA1_SRC_YCNT                       (REG_DMA23_YCNT)
-#define MDMA1_SRC_YMOD                       (REG_DMA23_YMOD)
-#define MDMA1_SRC_DSCPTR_CUR                 (REG_DMA23_DSCPTR_CUR)
-#define MDMA1_SRC_DSCPTR_PRV                 (REG_DMA23_DSCPTR_PRV)
-#define MDMA1_SRC_ADDR_CUR                   (REG_DMA23_ADDR_CUR)
-#define MDMA1_SRC_STAT                       (REG_DMA23_STAT)
-#define MDMA1_SRC_XCNT_CUR                   (REG_DMA23_XCNT_CUR)
-#define MDMA1_SRC_YCNT_CUR                   (REG_DMA23_YCNT_CUR)
-#define MDMA1_SRC_BWLCNT                     (REG_DMA23_BWLCNT)
-#define MDMA1_SRC_BWLCNT_CUR                 (REG_DMA23_BWLCNT_CUR)
-#define MDMA1_SRC_BWMCNT                     (REG_DMA23_BWMCNT)
-#define MDMA1_SRC_BWMCNT_CUR                 (REG_DMA23_BWMCNT_CUR)
-#define MDMA1_DST_DSCPTR_NXT                 (REG_DMA24_DSCPTR_NXT)
-#define MDMA1_DST_ADDRSTART                  (REG_DMA24_ADDRSTART)
-#define MDMA1_DST_CFG                        (REG_DMA24_CFG)
-#define MDMA1_DST_XCNT                       (REG_DMA24_XCNT)
-#define MDMA1_DST_XMOD                       (REG_DMA24_XMOD)
-#define MDMA1_DST_YCNT                       (REG_DMA24_YCNT)
-#define MDMA1_DST_YMOD                       (REG_DMA24_YMOD)
-#define MDMA1_DST_DSCPTR_CUR                 (REG_DMA24_DSCPTR_CUR)
-#define MDMA1_DST_DSCPTR_PRV                 (REG_DMA24_DSCPTR_PRV)
-#define MDMA1_DST_ADDR_CUR                   (REG_DMA24_ADDR_CUR)
-#define MDMA1_DST_STAT                       (REG_DMA24_STAT)
-#define MDMA1_DST_XCNT_CUR                   (REG_DMA24_XCNT_CUR)
-#define MDMA1_DST_YCNT_CUR                   (REG_DMA24_YCNT_CUR)
-#define MDMA1_DST_BWLCNT                     (REG_DMA24_BWLCNT)
-#define MDMA1_DST_BWLCNT_CUR                 (REG_DMA24_BWLCNT_CUR)
-#define MDMA1_DST_BWMCNT                     (REG_DMA24_BWMCNT)
-#define MDMA1_DST_BWMCNT_CUR                 (REG_DMA24_BWMCNT_CUR)
-#define MDMA2_SRC_DSCPTR_NXT                 (REG_DMA25_DSCPTR_NXT)
-#define MDMA2_SRC_ADDRSTART                  (REG_DMA25_ADDRSTART)
-#define MDMA2_SRC_CFG                        (REG_DMA25_CFG)
-#define MDMA2_SRC_XCNT                       (REG_DMA25_XCNT)
-#define MDMA2_SRC_XMOD                       (REG_DMA25_XMOD)
-#define MDMA2_SRC_YCNT                       (REG_DMA25_YCNT)
-#define MDMA2_SRC_YMOD                       (REG_DMA25_YMOD)
-#define MDMA2_SRC_DSCPTR_CUR                 (REG_DMA25_DSCPTR_CUR)
-#define MDMA2_SRC_DSCPTR_PRV                 (REG_DMA25_DSCPTR_PRV)
-#define MDMA2_SRC_ADDR_CUR                   (REG_DMA25_ADDR_CUR)
-#define MDMA2_SRC_STAT                       (REG_DMA25_STAT)
-#define MDMA2_SRC_XCNT_CUR                   (REG_DMA25_XCNT_CUR)
-#define MDMA2_SRC_YCNT_CUR                   (REG_DMA25_YCNT_CUR)
-#define MDMA2_SRC_BWLCNT                     (REG_DMA25_BWLCNT)
-#define MDMA2_SRC_BWLCNT_CUR                 (REG_DMA25_BWLCNT_CUR)
-#define MDMA2_SRC_BWMCNT                     (REG_DMA25_BWMCNT)
-#define MDMA2_SRC_BWMCNT_CUR                 (REG_DMA25_BWMCNT_CUR)
-#define MDMA2_DST_DSCPTR_NXT                 (REG_DMA26_DSCPTR_NXT)
-#define MDMA2_DST_ADDRSTART                  (REG_DMA26_ADDRSTART)
-#define MDMA2_DST_CFG                        (REG_DMA26_CFG)
-#define MDMA2_DST_XCNT                       (REG_DMA26_XCNT)
-#define MDMA2_DST_XMOD                       (REG_DMA26_XMOD)
-#define MDMA2_DST_YCNT                       (REG_DMA26_YCNT)
-#define MDMA2_DST_YMOD                       (REG_DMA26_YMOD)
-#define MDMA2_DST_DSCPTR_CUR                 (REG_DMA26_DSCPTR_CUR)
-#define MDMA2_DST_DSCPTR_PRV                 (REG_DMA26_DSCPTR_PRV)
-#define MDMA2_DST_ADDR_CUR                   (REG_DMA26_ADDR_CUR)
-#define MDMA2_DST_STAT                       (REG_DMA26_STAT)
-#define MDMA2_DST_XCNT_CUR                   (REG_DMA26_XCNT_CUR)
-#define MDMA2_DST_YCNT_CUR                   (REG_DMA26_YCNT_CUR)
-#define MDMA2_DST_BWLCNT                     (REG_DMA26_BWLCNT)
-#define MDMA2_DST_BWLCNT_CUR                 (REG_DMA26_BWLCNT_CUR)
-#define MDMA2_DST_BWMCNT                     (REG_DMA26_BWMCNT)
-#define MDMA2_DST_BWMCNT_CUR                 (REG_DMA26_BWMCNT_CUR)
-#define MDMA3_SRC_DSCPTR_NXT                 (REG_DMA27_DSCPTR_NXT)
-#define MDMA3_SRC_ADDRSTART                  (REG_DMA27_ADDRSTART)
-#define MDMA3_SRC_CFG                        (REG_DMA27_CFG)
-#define MDMA3_SRC_XCNT                       (REG_DMA27_XCNT)
-#define MDMA3_SRC_XMOD                       (REG_DMA27_XMOD)
-#define MDMA3_SRC_YCNT                       (REG_DMA27_YCNT)
-#define MDMA3_SRC_YMOD                       (REG_DMA27_YMOD)
-#define MDMA3_SRC_DSCPTR_CUR                 (REG_DMA27_DSCPTR_CUR)
-#define MDMA3_SRC_DSCPTR_PRV                 (REG_DMA27_DSCPTR_PRV)
-#define MDMA3_SRC_ADDR_CUR                   (REG_DMA27_ADDR_CUR)
-#define MDMA3_SRC_STAT                       (REG_DMA27_STAT)
-#define MDMA3_SRC_XCNT_CUR                   (REG_DMA27_XCNT_CUR)
-#define MDMA3_SRC_YCNT_CUR                   (REG_DMA27_YCNT_CUR)
-#define MDMA3_SRC_BWLCNT                     (REG_DMA27_BWLCNT)
-#define MDMA3_SRC_BWLCNT_CUR                 (REG_DMA27_BWLCNT_CUR)
-#define MDMA3_SRC_BWMCNT                     (REG_DMA27_BWMCNT)
-#define MDMA3_SRC_BWMCNT_CUR                 (REG_DMA27_BWMCNT_CUR)
-#define MDMA3_DST_DSCPTR_NXT                 (REG_DMA28_DSCPTR_NXT)
-#define MDMA3_DST_ADDRSTART                  (REG_DMA28_ADDRSTART)
-#define MDMA3_DST_CFG                        (REG_DMA28_CFG)
-#define MDMA3_DST_XCNT                       (REG_DMA28_XCNT)
-#define MDMA3_DST_XMOD                       (REG_DMA28_XMOD)
-#define MDMA3_DST_YCNT                       (REG_DMA28_YCNT)
-#define MDMA3_DST_YMOD                       (REG_DMA28_YMOD)
-#define MDMA3_DST_DSCPTR_CUR                 (REG_DMA28_DSCPTR_CUR)
-#define MDMA3_DST_DSCPTR_PRV                 (REG_DMA28_DSCPTR_PRV)
-#define MDMA3_DST_ADDR_CUR                   (REG_DMA28_ADDR_CUR)
-#define MDMA3_DST_STAT                       (REG_DMA28_STAT)
-#define MDMA3_DST_XCNT_CUR                   (REG_DMA28_XCNT_CUR)
-#define MDMA3_DST_YCNT_CUR                   (REG_DMA28_YCNT_CUR)
-#define MDMA3_DST_BWLCNT                     (REG_DMA28_BWLCNT)
-#define MDMA3_DST_BWLCNT_CUR                 (REG_DMA28_BWLCNT_CUR)
-#define MDMA3_DST_BWMCNT                     (REG_DMA28_BWMCNT)
-#define MDMA3_DST_BWMCNT_CUR                 (REG_DMA28_BWMCNT_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_NXT             (REG_DMA29_DSCPTR_NXT)
-#define EPPI0_CH0_DMA_ADDRSTART              (REG_DMA29_ADDRSTART)
-#define EPPI0_CH0_DMA_CFG                    (REG_DMA29_CFG)
-#define EPPI0_CH0_DMA_XCNT                   (REG_DMA29_XCNT)
-#define EPPI0_CH0_DMA_XMOD                   (REG_DMA29_XMOD)
-#define EPPI0_CH0_DMA_YCNT                   (REG_DMA29_YCNT)
-#define EPPI0_CH0_DMA_YMOD                   (REG_DMA29_YMOD)
-#define EPPI0_CH0_DMA_DSCPTR_CUR             (REG_DMA29_DSCPTR_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_PRV             (REG_DMA29_DSCPTR_PRV)
-#define EPPI0_CH0_DMA_ADDR_CUR               (REG_DMA29_ADDR_CUR)
-#define EPPI0_CH0_DMA_STAT                   (REG_DMA29_STAT)
-#define EPPI0_CH0_DMA_XCNT_CUR               (REG_DMA29_XCNT_CUR)
-#define EPPI0_CH0_DMA_YCNT_CUR               (REG_DMA29_YCNT_CUR)
-#define EPPI0_CH0_DMA_BWLCNT                 (REG_DMA29_BWLCNT)
-#define EPPI0_CH0_DMA_BWLCNT_CUR             (REG_DMA29_BWLCNT_CUR)
-#define EPPI0_CH0_DMA_BWMCNT                 (REG_DMA29_BWMCNT)
-#define EPPI0_CH0_DMA_BWMCNT_CUR             (REG_DMA29_BWMCNT_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_NXT             (REG_DMA30_DSCPTR_NXT)
-#define EPPI0_CH1_DMA_ADDRSTART              (REG_DMA30_ADDRSTART)
-#define EPPI0_CH1_DMA_CFG                    (REG_DMA30_CFG)
-#define EPPI0_CH1_DMA_XCNT                   (REG_DMA30_XCNT)
-#define EPPI0_CH1_DMA_XMOD                   (REG_DMA30_XMOD)
-#define EPPI0_CH1_DMA_YCNT                   (REG_DMA30_YCNT)
-#define EPPI0_CH1_DMA_YMOD                   (REG_DMA30_YMOD)
-#define EPPI0_CH1_DMA_DSCPTR_CUR             (REG_DMA30_DSCPTR_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_PRV             (REG_DMA30_DSCPTR_PRV)
-#define EPPI0_CH1_DMA_ADDR_CUR               (REG_DMA30_ADDR_CUR)
-#define EPPI0_CH1_DMA_STAT                   (REG_DMA30_STAT)
-#define EPPI0_CH1_DMA_XCNT_CUR               (REG_DMA30_XCNT_CUR)
-#define EPPI0_CH1_DMA_YCNT_CUR               (REG_DMA30_YCNT_CUR)
-#define EPPI0_CH1_DMA_BWLCNT                 (REG_DMA30_BWLCNT)
-#define EPPI0_CH1_DMA_BWLCNT_CUR             (REG_DMA30_BWLCNT_CUR)
-#define EPPI0_CH1_DMA_BWMCNT                 (REG_DMA30_BWMCNT)
-#define EPPI0_CH1_DMA_BWMCNT_CUR             (REG_DMA30_BWMCNT_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_NXT             (REG_DMA31_DSCPTR_NXT)
-#define EPPI2_CH0_DMA_ADDRSTART              (REG_DMA31_ADDRSTART)
-#define EPPI2_CH0_DMA_CFG                    (REG_DMA31_CFG)
-#define EPPI2_CH0_DMA_XCNT                   (REG_DMA31_XCNT)
-#define EPPI2_CH0_DMA_XMOD                   (REG_DMA31_XMOD)
-#define EPPI2_CH0_DMA_YCNT                   (REG_DMA31_YCNT)
-#define EPPI2_CH0_DMA_YMOD                   (REG_DMA31_YMOD)
-#define EPPI2_CH0_DMA_DSCPTR_CUR             (REG_DMA31_DSCPTR_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_PRV             (REG_DMA31_DSCPTR_PRV)
-#define EPPI2_CH0_DMA_ADDR_CUR               (REG_DMA31_ADDR_CUR)
-#define EPPI2_CH0_DMA_STAT                   (REG_DMA31_STAT)
-#define EPPI2_CH0_DMA_XCNT_CUR               (REG_DMA31_XCNT_CUR)
-#define EPPI2_CH0_DMA_YCNT_CUR               (REG_DMA31_YCNT_CUR)
-#define EPPI2_CH0_DMA_BWLCNT                 (REG_DMA31_BWLCNT)
-#define EPPI2_CH0_DMA_BWLCNT_CUR             (REG_DMA31_BWLCNT_CUR)
-#define EPPI2_CH0_DMA_BWMCNT                 (REG_DMA31_BWMCNT)
-#define EPPI2_CH0_DMA_BWMCNT_CUR             (REG_DMA31_BWMCNT_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_NXT             (REG_DMA32_DSCPTR_NXT)
-#define EPPI2_CH1_DMA_ADDRSTART              (REG_DMA32_ADDRSTART)
-#define EPPI2_CH1_DMA_CFG                    (REG_DMA32_CFG)
-#define EPPI2_CH1_DMA_XCNT                   (REG_DMA32_XCNT)
-#define EPPI2_CH1_DMA_XMOD                   (REG_DMA32_XMOD)
-#define EPPI2_CH1_DMA_YCNT                   (REG_DMA32_YCNT)
-#define EPPI2_CH1_DMA_YMOD                   (REG_DMA32_YMOD)
-#define EPPI2_CH1_DMA_DSCPTR_CUR             (REG_DMA32_DSCPTR_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_PRV             (REG_DMA32_DSCPTR_PRV)
-#define EPPI2_CH1_DMA_ADDR_CUR               (REG_DMA32_ADDR_CUR)
-#define EPPI2_CH1_DMA_STAT                   (REG_DMA32_STAT)
-#define EPPI2_CH1_DMA_XCNT_CUR               (REG_DMA32_XCNT_CUR)
-#define EPPI2_CH1_DMA_YCNT_CUR               (REG_DMA32_YCNT_CUR)
-#define EPPI2_CH1_DMA_BWLCNT                 (REG_DMA32_BWLCNT)
-#define EPPI2_CH1_DMA_BWLCNT_CUR             (REG_DMA32_BWLCNT_CUR)
-#define EPPI2_CH1_DMA_BWMCNT                 (REG_DMA32_BWMCNT)
-#define EPPI2_CH1_DMA_BWMCNT_CUR             (REG_DMA32_BWMCNT_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_NXT             (REG_DMA33_DSCPTR_NXT)
-#define EPPI1_CH0_DMA_ADDRSTART              (REG_DMA33_ADDRSTART)
-#define EPPI1_CH0_DMA_CFG                    (REG_DMA33_CFG)
-#define EPPI1_CH0_DMA_XCNT                   (REG_DMA33_XCNT)
-#define EPPI1_CH0_DMA_XMOD                   (REG_DMA33_XMOD)
-#define EPPI1_CH0_DMA_YCNT                   (REG_DMA33_YCNT)
-#define EPPI1_CH0_DMA_YMOD                   (REG_DMA33_YMOD)
-#define EPPI1_CH0_DMA_DSCPTR_CUR             (REG_DMA33_DSCPTR_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_PRV             (REG_DMA33_DSCPTR_PRV)
-#define EPPI1_CH0_DMA_ADDR_CUR               (REG_DMA33_ADDR_CUR)
-#define EPPI1_CH0_DMA_STAT                   (REG_DMA33_STAT)
-#define EPPI1_CH0_DMA_XCNT_CUR               (REG_DMA33_XCNT_CUR)
-#define EPPI1_CH0_DMA_YCNT_CUR               (REG_DMA33_YCNT_CUR)
-#define EPPI1_CH0_DMA_BWLCNT                 (REG_DMA33_BWLCNT)
-#define EPPI1_CH0_DMA_BWLCNT_CUR             (REG_DMA33_BWLCNT_CUR)
-#define EPPI1_CH0_DMA_BWMCNT                 (REG_DMA33_BWMCNT)
-#define EPPI1_CH0_DMA_BWMCNT_CUR             (REG_DMA33_BWMCNT_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_NXT             (REG_DMA34_DSCPTR_NXT)
-#define EPPI1_CH1_DMA_ADDRSTART              (REG_DMA34_ADDRSTART)
-#define EPPI1_CH1_DMA_CFG                    (REG_DMA34_CFG)
-#define EPPI1_CH1_DMA_XCNT                   (REG_DMA34_XCNT)
-#define EPPI1_CH1_DMA_XMOD                   (REG_DMA34_XMOD)
-#define EPPI1_CH1_DMA_YCNT                   (REG_DMA34_YCNT)
-#define EPPI1_CH1_DMA_YMOD                   (REG_DMA34_YMOD)
-#define EPPI1_CH1_DMA_DSCPTR_CUR             (REG_DMA34_DSCPTR_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_PRV             (REG_DMA34_DSCPTR_PRV)
-#define EPPI1_CH1_DMA_ADDR_CUR               (REG_DMA34_ADDR_CUR)
-#define EPPI1_CH1_DMA_STAT                   (REG_DMA34_STAT)
-#define EPPI1_CH1_DMA_XCNT_CUR               (REG_DMA34_XCNT_CUR)
-#define EPPI1_CH1_DMA_YCNT_CUR               (REG_DMA34_YCNT_CUR)
-#define EPPI1_CH1_DMA_BWLCNT                 (REG_DMA34_BWLCNT)
-#define EPPI1_CH1_DMA_BWLCNT_CUR             (REG_DMA34_BWLCNT_CUR)
-#define EPPI1_CH1_DMA_BWMCNT                 (REG_DMA34_BWMCNT)
-#define EPPI1_CH1_DMA_BWMCNT_CUR             (REG_DMA34_BWMCNT_CUR)
-
-/* ==================================
-       DMA Error CHID Definitions
-   ================================== */
-#define CHID_SPORT0_A_DMA                      0           /* Channel A DMA */
-#define CHID_SPORT0_B_DMA                      1           /* Channel B DMA */
-#define CHID_SPORT1_A_DMA                      2           /* Channel A DMA */
-#define CHID_SPORT1_B_DMA                      3           /* Channel B DMA */
-#define CHID_SPORT2_A_DMA                      4           /* Channel A DMA */
-#define CHID_SPORT2_B_DMA                      5           /* Channel B DMA */
-#define CHID_SPI0_TXDMA                        6           /* TX DMA Channel */
-#define CHID_SPI0_RXDMA                        7           /* RX DMA Channel */
-#define CHID_SPI1_TXDMA                        8           /* TX DMA Channel */
-#define CHID_SPI1_RXDMA                        9           /* RX DMA Channel */
-#define CHID_RSI0_DMA                         10           /* DMA Channel */
-#define CHID_SDU0_DMA                         11           /* DMA */
-/*      -- RESERVED --                        12  */
-#define CHID_LP0_DMA                          13           /* DMA Channel */
-#define CHID_LP1_DMA                          14           /* DMA Channel */
-#define CHID_LP2_DMA                          15           /* DMA Channel */
-#define CHID_LP3_DMA                          16           /* DMA Channel */
-#define CHID_UART0_TXDMA                      17           /* Transmit DMA */
-#define CHID_UART0_RXDMA                      18           /* Receive DMA */
-#define CHID_UART1_TXDMA                      19           /* Transmit DMA */
-#define CHID_UART1_RXDMA                      20           /* Receive DMA */
-#define CHID_MDMA0_SRC                        21           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define CHID_MDMA0_DST                        22           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define CHID_MDMA1_SRC                        23           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define CHID_MDMA1_DST                        24           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define CHID_MDMA2_SRC                        25           /* Memory DMA Stream 2 Source Channel */
-#define CHID_MDMA2_DST                        26           /* Memory DMA Stream 2 Destination Channel */
-#define CHID_MDMA3_SRC                        27           /* Memory DMA Stream 3 Source Channel */
-#define CHID_MDMA3_DST                        28           /* Memory DMA Stream 3 Destination Channel */
-#define CHID_EPPI0_CH0_DMA                    29           /* Channel 0 DMA */
-#define CHID_EPPI0_CH1_DMA                    30           /* Channel 1 DMA */
-#define CHID_EPPI2_CH0_DMA                    31           /* Channel 0 DMA */
-#define CHID_EPPI2_CH1_DMA                    32           /* Channel 1 DMA */
-#define CHID_EPPI1_CH0_DMA                    33           /* Channel 0 DMA */
-#define CHID_EPPI1_CH1_DMA                    34           /* Channel 1 DMA */
-
-/* ==============================
-       Interrupt Definitions
-   ============================== */
-#define INTR_SEC0_ERR                          0           /* Error */
-#define INTR_CGU0_EVT                          1           /* Event */
-#define INTR_WDOG0_EXP                         2           /* Expiration */
-#define INTR_WDOG1_EXP                         3           /* Expiration */
-#define INTR_L2CTL0_ECC_ERR                    4           /* ECC Error */
-#define INTR_L2CTL0_ECC_WARNING                5           /* ECC Warning */
-#define INTR_C0_DBL_FAULT                      6           /* Core 0 Double Fault */
-#define INTR_C1_DBL_FAULT                      7           /* Core 1 Double Fault */
-#define INTR_C0_HW_ERR                         8           /* Core 0 Hardware Error */
-#define INTR_C1_HW_ERR                         9           /* Core 1 Hardware Error */
-#define INTR_C0_NMI_L1_PARITY_ERR             10           /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_C1_NMI_L1_PARITY_ERR             11           /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_TIMER0_TMR0                      12           /* Timer 0 */
-#define INTR_TIMER0_TMR1                      13           /* Timer 1 */
-#define INTR_TIMER0_TMR2                      14           /* Timer 2 */
-#define INTR_TIMER0_TMR3                      15           /* Timer 3 */
-#define INTR_TIMER0_TMR4                      16           /* Timer 4 */
-#define INTR_TIMER0_TMR5                      17           /* Timer 5 */
-#define INTR_TIMER0_TMR6                      18           /* Timer 6 */
-#define INTR_TIMER0_TMR7                      19           /* Timer 7 */
-#define INTR_TIMER0_STAT                      20           /* Status */
-#define INTR_PINT0_BLOCK                      21           /* Pin Interrupt Block */
-#define INTR_PINT1_BLOCK                      22           /* Pin Interrupt Block */
-#define INTR_PINT2_BLOCK                      23           /* Pin Interrupt Block */
-#define INTR_PINT3_BLOCK                      24           /* Pin Interrupt Block */
-#define INTR_PINT4_BLOCK                      25           /* Pin Interrupt Block */
-#define INTR_PINT5_BLOCK                      26           /* Pin Interrupt Block */
-#define INTR_CNT0_STAT                        27           /* Status */
-#define INTR_PWM0_SYNC                        28           /* Sync */
-#define INTR_PWM0_TRIP                        29           /* Trip */
-#define INTR_PWM1_SYNC                        30           /* Sync */
-#define INTR_PWM1_TRIP                        31           /* Trip */
-#define INTR_TWI0_DATA                        32           /* Data Interrupt */
-#define INTR_TWI1_DATA                        33           /* Data Interrupt */
-#define INTR_SOFT0                            34           /* Software-driven Interrupt 0 */
-#define INTR_SOFT1                            35           /* Software-driven Interrupt 1 */
-#define INTR_SOFT2                            36           /* Software-driven Interrupt 2 */
-#define INTR_SOFT3                            37           /* Software-driven Interrupt 3 */
-#define INTR_ACM0_EVT_MISS                    38           /* Event Miss */
-#define INTR_ACM0_EVT_COMPLETE                39           /* Event Complete */
-#define INTR_CAN0_RX                          40           /* Receive */
-#define INTR_CAN0_TX                          41           /* Transmit */
-#define INTR_CAN0_STAT                        42           /* Status */
-#define INTR_SPORT0_A_DMA                     43           /* Channel A DMA */
-#define INTR_SPORT0_A_STAT                    44           /* Channel A Status */
-#define INTR_SPORT0_B_DMA                     45           /* Channel B DMA */
-#define INTR_SPORT0_B_STAT                    46           /* Channel B Status */
-#define INTR_SPORT1_A_DMA                     47           /* Channel A DMA */
-#define INTR_SPORT1_A_STAT                    48           /* Channel A Status */
-#define INTR_SPORT1_B_DMA                     49           /* Channel B DMA */
-#define INTR_SPORT1_B_STAT                    50           /* Channel B Status */
-#define INTR_SPORT2_A_DMA                     51           /* Channel A DMA */
-#define INTR_SPORT2_A_STAT                    52           /* Channel A Status */
-#define INTR_SPORT2_B_DMA                     53           /* Channel B DMA */
-#define INTR_SPORT2_B_STAT                    54           /* Channel B Status */
-#define INTR_SPI0_TXDMA                       55           /* TX DMA Channel */
-#define INTR_SPI0_RXDMA                       56           /* RX DMA Channel */
-#define INTR_SPI0_STAT                        57           /* Status */
-#define INTR_SPI1_TXDMA                       58           /* TX DMA Channel */
-#define INTR_SPI1_RXDMA                       59           /* RX DMA Channel */
-#define INTR_SPI1_STAT                        60           /* Status */
-#define INTR_RSI0_DMA                         61           /* DMA Channel */
-#define INTR_RSI0_INT0                        62           /* Interrupt 0 */
-#define INTR_RSI0_INT1                        63           /* Interrupt 1 */
-#define INTR_SDU0_DMA                         64           /* DMA */
-/*      -- RESERVED --                        65  */
-/*      -- RESERVED --                        66  */
-/*      -- RESERVED --                        67  */
-#define INTR_EMAC0_STAT                       68           /* Status */
-/*      -- RESERVED --                        69  */
-#define INTR_EMAC1_STAT                       70           /* Status */
-/*      -- RESERVED --                        71  */
-#define INTR_LP0_DMA                          72           /* DMA Channel */
-#define INTR_LP0_STAT                         73           /* Status */
-#define INTR_LP1_DMA                          74           /* DMA Channel */
-#define INTR_LP1_STAT                         75           /* Status */
-#define INTR_LP2_DMA                          76           /* DMA Channel */
-#define INTR_LP2_STAT                         77           /* Status */
-#define INTR_LP3_DMA                          78           /* DMA Channel */
-#define INTR_LP3_STAT                         79           /* Status */
-#define INTR_UART0_TXDMA                      80           /* Transmit DMA */
-#define INTR_UART0_RXDMA                      81           /* Receive DMA */
-#define INTR_UART0_STAT                       82           /* Status */
-#define INTR_UART1_TXDMA                      83           /* Transmit DMA */
-#define INTR_UART1_RXDMA                      84           /* Receive DMA */
-#define INTR_UART1_STAT                       85           /* Status */
-#define INTR_MDMA0_SRC                        86           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define INTR_MDMA0_DST                        87           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define INTR_CRC0_DCNTEXP                     88           /* Datacount expiration */
-#define INTR_CRC0_ERR                         89           /* Error */
-#define INTR_MDMA1_SRC                        90           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define INTR_MDMA1_DST                        91           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define INTR_CRC1_DCNTEXP                     92           /* Datacount expiration */
-#define INTR_CRC1_ERR                         93           /* Error */
-#define INTR_MDMA2_SRC                        94           /* Memory DMA Stream 2 Source Channel */
-#define INTR_MDMA2_DST                        95           /* Memory DMA Stream 2 Destination Channel */
-#define INTR_MDMA3_SRC                        96           /* Memory DMA Stream 3 Source Channel */
-#define INTR_MDMA3_DST                        97           /* Memory DMA Stream 3 Destination Channel */
-#define INTR_EPPI0_CH0_DMA                    98           /* Channel 0 DMA */
-#define INTR_EPPI0_CH1_DMA                    99           /* Channel 1 DMA */
-#define INTR_EPPI0_STAT                      100           /* Status */
-#define INTR_EPPI2_CH0_DMA                   101           /* Channel 0 DMA */
-#define INTR_EPPI2_CH1_DMA                   102           /* Channel 1 DMA */
-#define INTR_EPPI2_STAT                      103           /* Status */
-#define INTR_EPPI1_CH0_DMA                   104           /* Channel 0 DMA */
-#define INTR_EPPI1_CH1_DMA                   105           /* Channel 1 DMA */
-#define INTR_EPPI1_STAT                      106           /* Status */
-#define INTR_USB0_STAT                       122           /* Status/FIFO Data Ready */
-#define INTR_USB0_DATA                       123           /* DMA Status/Transfer Complete */
-#define INTR_TRU0_INT0                       124           /* Interrupt 0 */
-#define INTR_TRU0_INT1                       125           /* Interrupt 1 */
-#define INTR_TRU0_INT2                       126           /* Interrupt 2 */
-#define INTR_TRU0_INT3                       127           /* Interrupt 3 */
-#define INTR_DMAC_ERR                        128           /* DMA Controller Error */
-#define INTR_CGU0_ERR                        129           /* Error */
-/*      -- RESERVED --                       130  */
-#define INTR_DPM0_EVT                        131           /* Event */
-/*      -- RESERVED --                       132  */
-#define INTR_SWU0_EVT                        133           /* Event */
-#define INTR_SWU1_EVT                        134           /* Event */
-#define INTR_SWU2_EVT                        135           /* Event */
-#define INTR_SWU3_EVT                        136           /* Event */
-#define INTR_SWU4_EVT                        137           /* Event */
-#define INTR_SWU5_EVT                        138           /* Event */
-#define INTR_SWU6_EVT                        139           /* Event */
-
-/* ==============================
-       Parameters
-   ============================== */
-
-
-/* Generic System Module Parameters */
-
-#define PARAM_SYS0_NUM_BMODE                          3
-#define PARAM_SYS0_NUM_CORES                          2
-#define PARAM_SYS0_NUM_MDMA_STREAMS                   4
-#define PARAM_SYS0_NUM_RSVD_INT                       7
-#define PARAM_SYS0_NUM_RSVD_TRIG                      6
-#define PARAM_SYS0_NUM_SW_INT                         4
-#define PARAM_SYS0_NUM_SW_TRIG                        6
-
-
-
-
-/* RSI Parameters */
-
-#define PARAM_RSI0_NUM_DATA                           8
-#define PARAM_RSI0_NUM_INT                            2
-
-
-
-/* Link Port Parameters */
-
-#define PARAM_LP0_NUM_DATA                            8
-#define PARAM_LP1_NUM_DATA                            8
-#define PARAM_LP2_NUM_DATA                            8
-#define PARAM_LP3_NUM_DATA                            8
-
-
-/* General Purpose Timer Block Parameters */
-
-#define PARAM_TIMER0_NUMTIMERS                        8
-
-
-
-
-
-/* General Purpose Input/Output Parameters */
-
-#define PARAM_PORTA_PORT_WIDTH                       16
-#define PARAM_PORTB_PORT_WIDTH                       16
-#define PARAM_PORTC_PORT_WIDTH                       16
-#define PARAM_PORTD_PORT_WIDTH                       16
-#define PARAM_PORTE_PORT_WIDTH                       16
-#define PARAM_PORTF_PORT_WIDTH                       16
-#define PARAM_PORTG_PORT_WIDTH                       16
-
-
-
-
-/* Static Memory Controller Parameters */
-
-#define PARAM_SMC0_NUM_ABE                            2
-#define PARAM_SMC0_NUM_ADDR                          26
-#define PARAM_SMC0_NUM_AMS                            4
-#define PARAM_SMC0_NUM_DATA                          16
-
-
-
-/* EPPI Parameters */
-
-#define PARAM_EPPI0_MAXWIDTH                         24
-#define PARAM_EPPI0_NUM_DATA                         24
-#define PARAM_EPPI1_MAXWIDTH                         24
-#define PARAM_EPPI1_NUM_DATA                         18
-#define PARAM_EPPI2_MAXWIDTH                         24
-#define PARAM_EPPI2_NUM_DATA                         18
-
-
-/* Pulse-Width Modulator Parameters */
-
-#define PARAM_PWM0_ASYM_DEADTIME                      0
-#define PARAM_PWM0_COMPRESS                           1
-#define PARAM_PWM0_DOUBLE_UPDATE                      0
-#define PARAM_PWM0_FULL_DUTY_REGS                     0
-#define PARAM_PWM0_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM0_LO_HP_REGS                         0
-#define PARAM_PWM0_NUM_TRIP                           2
-#define PARAM_PWM0_NUM_TRIP_PINS                      2
-#define PARAM_PWM0_NUM_TRIP_TRIG                      0
-#define PARAM_PWM0_REVID_MAJOR                        0
-#define PARAM_PWM0_REVID_REV                          0
-#define PARAM_PWM1_ASYM_DEADTIME                      0
-#define PARAM_PWM1_COMPRESS                           1
-#define PARAM_PWM1_DOUBLE_UPDATE                      0
-#define PARAM_PWM1_FULL_DUTY_REGS                     0
-#define PARAM_PWM1_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM1_LO_HP_REGS                         0
-#define PARAM_PWM1_NUM_TRIP                           2
-#define PARAM_PWM1_NUM_TRIP_PINS                      2
-#define PARAM_PWM1_NUM_TRIP_TRIG                      0
-#define PARAM_PWM1_REVID_MAJOR                        0
-#define PARAM_PWM1_REVID_REV                          0
-
-
-/* Video Subsystem Registers Parameters */
-
-#define PARAM_VID0_PIXC_ABSENT                        1
-#define PARAM_VID0_PVP_ABSENT                         1
-
-
-
-/* System Debug Unit Parameters */
-
-#define PARAM_SDU0_IDCODE_PRID                        0
-#define PARAM_SDU0_IDCODE_REVID                       0
-
-
-/* Ethernet MAC Parameters */
-
-#define PARAM_EMAC0_NUM_RX                            2
-#define PARAM_EMAC0_NUM_TX                            2
-#define PARAM_EMAC1_NUM_RX                            2
-#define PARAM_EMAC1_NUM_TX                            2
-
-
-
-/* Serial Peripheral Interface Parameters */
-
-#define PARAM_SPI0_MEM_MAPPED                         0
-#define PARAM_SPI0_NUM_SEL                            7
-#define PARAM_SPI0_PTM_EXISTS                         1
-#define PARAM_SPI0_REVID_MAJOR                        3
-#define PARAM_SPI0_REVID_REV                          0
-#define PARAM_SPI1_MEM_MAPPED                         0
-#define PARAM_SPI1_NUM_SEL                            7
-#define PARAM_SPI1_PTM_EXISTS                         1
-#define PARAM_SPI1_REVID_MAJOR                        3
-#define PARAM_SPI1_REVID_REV                          0
-
-
-
-/* ACM Parameters */
-
-#define PARAM_ACM0_NUM_ADDR                           5
-#define PARAM_ACM0_NUM_TRIG                           2
-
-
-/* DDR Parameters */
-
-#define PARAM_DMC0_NUM_ADDR                          14
-#define PARAM_DMC0_NUM_BA                             3
-#define PARAM_DMC0_NUM_CS                             1
-#define PARAM_DMC0_NUM_DATA                          16
-
-
-/* System Cross Bar Parameters */
-
-#define PARAM_SCB0_NUM_MASTERS                        6
-#define PARAM_SCB0_NUM_SLOTS                         32
-#define PARAM_SCB1_NUM_MASTERS                        1
-#define PARAM_SCB1_NUM_SLOTS                         32
-#define PARAM_SCB2_NUM_MASTERS                        1
-#define PARAM_SCB2_NUM_SLOTS                         32
-#define PARAM_SCB3_NUM_MASTERS                        1
-#define PARAM_SCB3_NUM_SLOTS                         32
-#define PARAM_SCB4_NUM_MASTERS                        1
-#define PARAM_SCB4_NUM_SLOTS                         32
-#define PARAM_SCB5_NUM_MASTERS                        1
-#define PARAM_SCB5_NUM_SLOTS                         32
-#define PARAM_SCB6_NUM_MASTERS                        1
-#define PARAM_SCB6_NUM_SLOTS                         32
-#define PARAM_SCB7_NUM_MASTERS                        1
-#define PARAM_SCB7_NUM_SLOTS                         32
-#define PARAM_SCB8_NUM_MASTERS                        1
-#define PARAM_SCB8_NUM_SLOTS                         32
-#define PARAM_SCB9_NUM_MASTERS                        1
-#define PARAM_SCB9_NUM_SLOTS                         32
-#define PARAM_SCB10_NUM_MASTERS                       3
-#define PARAM_SCB10_NUM_SLOTS                        32
-#define PARAM_SCB11_NUM_MASTERS                       7
-#define PARAM_SCB11_NUM_SLOTS                        32
-
-
-
-/* System Event Controller Parameters */
-
-#define PARAM_SEC0_CCOUNT                             2
-#define PARAM_SEC0_SCOUNT                           140
-
-
-/* Trigger Routing Unit Parameters */
-
-#define PARAM_TRU0_NUM_INTS                           4
-#define PARAM_TRU0_NUM_TRIGS                          4
-#define PARAM_TRU0_SSRCOUNT                          87
-
-
-/* Reset Control Unit Parameters */
-
-#define PARAM_RCU0_CCOUNT                             2
-#define PARAM_RCU0_CRCTL_CR_INIT                      2
-#define PARAM_RCU0_CRSTAT_CR_INIT                     3
-#define PARAM_RCU0_SICOUNT                            2
-#define PARAM_RCU0_SVECT_INIT                     65440
-
-
-/* System Protection Unit Parameters */
-
-#define PARAM_SPU0_CM_COUNT                           2
-#define PARAM_SPU0_END_POINT_COUNT                   86
-#define PARAM_SPU0_SM_COUNT                           2
-
-
-/* Clock Generation Unit Parameters */
-
-#define PARAM_CGU0_CSEL_DEFAULT                       4
-#define PARAM_CGU0_DSEL_DEFAULT                       8
-#define PARAM_CGU0_MSEL_DEFAULT                      16
-#define PARAM_CGU0_OSEL_DEFAULT                      16
-#define PARAM_CGU0_PLLBP_DEFAULT                      0
-#define PARAM_CGU0_S0SEL_DEFAULT                      2
-#define PARAM_CGU0_S1SEL_DEFAULT                      2
-#define PARAM_CGU0_SYSSEL_DEFAULT                     8
-
-
-/* Dynamic Power Management Parameters */
-
-#define PARAM_DPM0_NUM_CCLK                           2
-#define PARAM_DPM0_NUM_HV                             8
-#define PARAM_DPM0_NUM_SCLK                           4
-#define PARAM_DPM0_NUM_WAKE                           8
-
-
-
-/* Universal Serial Bus Controller Parameters */
-
-#define PARAM_USB0_DMA_CHAN                           8
-#define PARAM_USB0_DYN_FIFO_SIZE                      1
-#define PARAM_USB0_FS_PHY                             0
-#define PARAM_USB0_HS_PHY                             1
-#define PARAM_USB0_LOOPBACK                           1
-#define PARAM_USB0_NUM_ENDPTS                        12
-#define PARAM_USB0_NUM_ENDPTS_MINUS_1                11
-
-
-/* Data Memory Unit Parameters */
-
-#define PARAM_L1DM0_L1_BASE_ADDRESS          1111111110
-
-
-
-
-
-
-
-
-/* ===================================
-       Trigger Master Definitions
-   =================================== */
-/*      -- RESERVED --                         0  */
-#define TRGM_CGU0_EVT                          1           /* Event */
-#define TRGM_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGM_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGM_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGM_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGM_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGM_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGM_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGM_TIMER0_TMR7                       9           /* Timer 7 */
-#define TRGM_PINT0_BLOCK                      10           /* Pin Interrupt Block */
-#define TRGM_PINT1_BLOCK                      11           /* Pin Interrupt Block */
-#define TRGM_PINT2_BLOCK                      12           /* Pin Interrupt Block */
-#define TRGM_PINT3_BLOCK                      13           /* Pin Interrupt Block */
-#define TRGM_PINT4_BLOCK                      14           /* Pin Interrupt Block */
-#define TRGM_PINT5_BLOCK                      15           /* Pin Interrupt Block */
-#define TRGM_CNT0_STAT                        16           /* Status */
-#define TRGM_PWM0_SYNC                        17           /* Sync */
-#define TRGM_PWM1_SYNC                        18           /* Sync */
-#define TRGM_ACM0_EVT_COMPLETE                19           /* Event Complete */
-#define TRGM_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGM_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGM_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGM_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGM_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGM_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGM_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGM_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGM_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGM_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGM_RSI0_DMA                         30           /* DMA Channel */
-#define TRGM_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGM_EMAC0_STAT                       33           /* Status */
-#define TRGM_EMAC1_STAT                       34           /* Status */
-#define TRGM_LP0_DMA                          35           /* DMA Channel */
-#define TRGM_LP1_DMA                          36           /* DMA Channel */
-#define TRGM_LP2_DMA                          37           /* DMA Channel */
-#define TRGM_LP3_DMA                          38           /* DMA Channel */
-#define TRGM_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGM_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGM_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGM_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGM_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGM_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGM_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGM_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGM_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGM_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGM_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGM_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGM_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGM_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGM_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGM_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGM_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGM_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGM_USB0_DATA                        69           /* DMA Status/Transfer Complete */
-/*      -- RESERVED --                        70  */
-#define TRGM_SEC0_FAULT                       71           /* Fault */
-#define TRGM_SOFT0                            72           /* Software-driven Trigger 0 */
-#define TRGM_SOFT1                            73           /* Software-driven Trigger 1 */
-#define TRGM_SOFT2                            74           /* Software-driven Trigger 2 */
-#define TRGM_SOFT3                            75           /* Software-driven Trigger 3 */
-#define TRGM_SOFT4                            76           /* Software-driven Trigger 4 */
-#define TRGM_SOFT5                            77           /* Software-driven Trigger 5 */
-#define TRGM_SWU0_EVT                         80           /* Event */
-#define TRGM_SWU1_EVT                         81           /* Event */
-#define TRGM_SWU2_EVT                         82           /* Event */
-#define TRGM_SWU3_EVT                         83           /* Event */
-#define TRGM_SWU4_EVT                         84           /* Event */
-#define TRGM_SWU5_EVT                         85           /* Event */
-#define TRGM_SWU6_EVT                         86           /* Event */
-
-/* ===================================
-       Trigger Slave Definitions
-   =================================== */
-#define TRGS_RCU0_SYSRST0                      0           /* System Reset 0 */
-#define TRGS_RCU0_SYSRST1                      1           /* System Reset 1 */
-#define TRGS_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGS_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGS_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGS_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGS_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGS_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGS_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGS_TIMER0_TMR7                       9           /* Timer 7 */
-/*      -- RESERVED --                        10  */
-/*      -- RESERVED --                        11  */
-#define TRGS_C0_NMI_S0                        12           /* NMI (Core 0) Slave 0 */
-#define TRGS_C0_NMI_S1                        13           /* NMI (Core 0) Slave 1 */
-#define TRGS_C1_NMI_S0                        14           /* NMI (Core 1) Slave 0 */
-#define TRGS_C1_NMI_S1                        15           /* NMI (Core 1) Slave 1 */
-#define TRGS_TRU0_IRQ0                        16           /* Interrupt Request 0 */
-#define TRGS_TRU0_IRQ1                        17           /* Interrupt Request 1 */
-#define TRGS_TRU0_IRQ2                        18           /* Interrupt Request 2 */
-#define TRGS_TRU0_IRQ3                        19           /* Interrupt Request 3 */
-#define TRGS_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGS_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGS_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGS_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGS_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGS_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGS_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGS_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGS_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGS_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGS_RSI0_DMA                         30           /* DMA Channel */
-#define TRGS_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGS_ACM0_TRIG2                       33           /* Trigger Input 2 */
-#define TRGS_ACM0_TRIG3                       34           /* Trigger Input 3 */
-#define TRGS_LP0_DMA                          35           /* DMA Channel */
-#define TRGS_LP1_DMA                          36           /* DMA Channel */
-#define TRGS_LP2_DMA                          37           /* DMA Channel */
-#define TRGS_LP3_DMA                          38           /* DMA Channel */
-#define TRGS_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGS_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGS_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGS_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGS_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGS_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGS_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGS_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGS_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGS_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGS_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGS_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGS_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGS_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGS_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGS_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGS_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGS_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGS_SDU0_SLAVE                       69           /* Slave Trigger */
-/*      -- RESERVED --                        70  */
-#define TRGS_C0_WAKE0                         71           /* Core 0 Wakeup Input 0 */
-#define TRGS_C0_WAKE1                         72           /* Core 0 Wakeup Input 1 */
-#define TRGS_C0_WAKE2                         73           /* Core 0 Wakeup Input 2 */
-#define TRGS_C0_WAKE3                         74           /* Core 0 Wakeup Input 3 */
-#define TRGS_C1_WAKE0                         75           /* Core 1 Wakeup Input 0 */
-#define TRGS_C1_WAKE1                         76           /* Core 1 Wakeup Input 1 */
-#define TRGS_C1_WAKE2                         77           /* Core 1 Wakeup Input 2 */
-#define TRGS_C1_WAKE3                         78           /* Core 1 Wakeup Input 3 */
-/*      -- RESERVED --                        79  */
-#define TRGS_SWU0_EVT                         80           /* Event */
-#define TRGS_SWU1_EVT                         81           /* Event */
-#define TRGS_SWU2_EVT                         82           /* Event */
-#define TRGS_SWU3_EVT                         83           /* Event */
-#define TRGS_SWU4_EVT                         84           /* Event */
-#define TRGS_SWU5_EVT                         85           /* Event */
-#define TRGS_SWU6_EVT                         86           /* Event */
-
-
-/* ============================================================================
-       Memory Map Macros
-   ============================================================================ */
-
-/* ADSP-BF606 is a multi-core processor */
-
-#define MEM_NUM_CORES                   2
-
-/* Internal memory range */
-
-#define MEM_BASE_INTERNAL               0xC0000000
-#define MEM_END_INTERNAL                0xFFFFFFFF
-#define MEM_SIZE_INTERNAL               0x40000000
-
-/* External memory range */
-
-#define MEM_BASE_EXTERNAL               0x00000000
-#define MEM_END_EXTERNAL                0xBFFFFFFF
-#define MEM_SIZE_EXTERNAL               0xC0000000
-
-/* Shared DDR2 or LPDDR Memory (256 MB) */
-
-#define MEM_BASE_DDR                    0x00000000
-#define MEM_END_DDR                     0x0FFFFFFF
-#define MEM_SIZE_DDR                    0x10000000
-
-/* Shared Async Memory (256 MB) */
-
-#define MEM_BASE_ASYNC                  0xB0000000
-#define MEM_END_ASYNC                   0xBFFFFFFF
-#define MEM_SIZE_ASYNC                  0x10000000
-
-/* Shared Async Memory Bank 0 (64 MB) */
-
-#define MEM_BASE_ASYNC_0                0xB0000000
-#define MEM_END_ASYNC_0                 0xB3FFFFFF
-#define MEM_SIZE_ASYNC_0                0x4000000
-
-/* Shared Async Memory Bank 1 (64 MB) */
-
-#define MEM_BASE_ASYNC_1                0xB4000000
-#define MEM_END_ASYNC_1                 0xB7FFFFFF
-#define MEM_SIZE_ASYNC_1                0x4000000
-
-/* Shared Async Memory Bank 2 (64 MB) */
-
-#define MEM_BASE_ASYNC_2                0xB8000000
-#define MEM_END_ASYNC_2                 0xBBFFFFFF
-#define MEM_SIZE_ASYNC_2                0x4000000
-
-/* Shared Async Memory Bank 3 (64 MB) */
-
-#define MEM_BASE_ASYNC_3                0xBC000000
-#define MEM_END_ASYNC_3                 0xBFFFFFFF
-#define MEM_SIZE_ASYNC_3                0x4000000
-
-/* Shared L2 ROM (32 KB) */
-
-#define MEM_BASE_L2_ROM                 0xC8000000
-#define MEM_END_L2_ROM                  0xC8007FFF
-#define MEM_SIZE_L2_ROM                 0x8000
-
-/* Shared L2 SRAM (128 KB) */
-
-#define MEM_BASE_L2_SRAM                0xC8080000
-#define MEM_END_L2_SRAM                 0xC809FFFF
-#define MEM_SIZE_L2_SRAM                0x20000
-
-/* Core 1 L1 Data Bank A (32 KB) */
-
-#define MEM_C1_BASE_L1DM_A              0xFF400000
-#define MEM_C1_END_L1DM_A               0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A              0x8000
-
-/* Core 1 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM         0xFF400000
-#define MEM_C1_END_L1DM_A_SRAM          0xFF403FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 1 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM_CACHE   0xFF404000
-#define MEM_C1_END_L1DM_A_SRAM_CACHE    0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Data Bank B (32 KB) */
-
-#define MEM_C1_BASE_L1DM_B              0xFF500000
-#define MEM_C1_END_L1DM_B               0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B              0x8000
-
-/* Core 1 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM         0xFF500000
-#define MEM_C1_END_L1DM_B_SRAM          0xFF503FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 1 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM_CACHE   0xFF504000
-#define MEM_C1_END_L1DM_B_SRAM_CACHE    0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Instruction (80 KB) */
-
-#define MEM_C1_BASE_L1IM                0xFF600000
-#define MEM_C1_END_L1IM                 0xFF613FFF
-#define MEM_C1_SIZE_L1IM                0x14000
-
-/* Core 1 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM           0xFF600000
-#define MEM_C1_END_L1IM_SRAM            0xFF60FFFF
-#define MEM_C1_SIZE_L1IM_SRAM           0x10000
-
-/* Core 1 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM_CACHE     0xFF610000
-#define MEM_C1_END_L1IM_SRAM_CACHE      0xFF613FFF
-#define MEM_C1_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 1 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C1_BASE_L1_XPAD_SRAM        0xFF700000
-#define MEM_C1_END_L1_XPAD_SRAM         0xFF700FFF
-#define MEM_C1_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Core 0 L1 Data Bank A (32 KB) */
-
-#define MEM_C0_BASE_L1DM_A              0xFF800000
-#define MEM_C0_END_L1DM_A               0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A              0x8000
-
-/* Core 0 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM         0xFF800000
-#define MEM_C0_END_L1DM_A_SRAM          0xFF803FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 0 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM_CACHE   0xFF804000
-#define MEM_C0_END_L1DM_A_SRAM_CACHE    0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Data Bank B (32 KB) */
-
-#define MEM_C0_BASE_L1DM_B              0xFF900000
-#define MEM_C0_END_L1DM_B               0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B              0x8000
-
-/* Core 0 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM         0xFF900000
-#define MEM_C0_END_L1DM_B_SRAM          0xFF903FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 0 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM_CACHE   0xFF904000
-#define MEM_C0_END_L1DM_B_SRAM_CACHE    0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Instruction (80 KB) */
-
-#define MEM_C0_BASE_L1IM                0xFFA00000
-#define MEM_C0_END_L1IM                 0xFFA13FFF
-#define MEM_C0_SIZE_L1IM                0x14000
-
-/* Core 0 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM           0xFFA00000
-#define MEM_C0_END_L1IM_SRAM            0xFFA0FFFF
-#define MEM_C0_SIZE_L1IM_SRAM           0x10000
-
-/* Core 0 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM_CACHE     0xFFA10000
-#define MEM_C0_END_L1IM_SRAM_CACHE      0xFFA13FFF
-#define MEM_C0_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 0 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C0_BASE_L1_XPAD_SRAM        0xFFB00000
-#define MEM_C0_END_L1_XPAD_SRAM         0xFFB00FFF
-#define MEM_C0_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Shared System MMR Registers (2 MB) */
-
-#define MEM_BASE_MMR_SYSTEM             0xFFC00000
-#define MEM_END_MMR_SYSTEM              0xFFDFFFFF
-#define MEM_SIZE_MMR_SYSTEM             0x200000
-
-/* Core 0 Core MMR Registers (2 MB) */
-
-#define MEM_C0_BASE_MMR_CORE            0xFFE00000
-#define MEM_C0_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C0_SIZE_MMR_CORE            0x200000
-
-/* Core 1 Core MMR Registers (2 MB) */
-
-#define MEM_C1_BASE_MMR_CORE            0xFFE00000
-#define MEM_C1_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C1_SIZE_MMR_CORE            0x200000
-
-
-#endif	/* end ifndef _DEF_BF606_H */
diff --git a/libgloss/bfin/include/defBF607.h b/libgloss/bfin/include/defBF607.h
deleted file mode 100644
index dd4f49d9e..000000000
--- a/libgloss/bfin/include/defBF607.h
+++ /dev/null
@@ -1,17724 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* ================================================================================
-
-     Project      :   ADSP-BF607
-     File         :   defBF607.h
-     Description  :   Register Definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ================================================================================ */
-
-#ifndef _DEF_BF607_H
-#define _DEF_BF607_H
-
-#if defined (_MISRA_RULES)
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
-#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
-#endif /* _MISRA_RULES */
-
-/* do not add casts to literal constants in assembly code */
-#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
-#define _ADI_MSK( mask, type ) (mask) /* Make a bitmask */
-#else
-#define _ADI_MSK( mask, type ) ((type)(mask)) /* Make a bitmask */
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#ifndef __ADI_GENERATED_DEF_HEADERS__
-#define __ADI_GENERATED_DEF_HEADERS__    1
-#endif
-
-/* MMR modules defined for the ADSP-BF607 */
-
-#define __ADI_HAS_SYS__           1
-#define __ADI_HAS_SIMENV__        1
-#define __ADI_HAS_CNT__           1
-#define __ADI_HAS_RSI__           1
-#define __ADI_HAS_CAN__           1
-#define __ADI_HAS_LP__            1
-#define __ADI_HAS_TIMER__         1
-#define __ADI_HAS_CRC__           1
-#define __ADI_HAS_TWI__           1
-#define __ADI_HAS_UART__          1
-#define __ADI_HAS_PORT__          1
-#define __ADI_HAS_PADS__          1
-#define __ADI_HAS_PINT__          1
-#define __ADI_HAS_SMC__           1
-#define __ADI_HAS_WDOG__          1
-#define __ADI_HAS_EPPI__          1
-#define __ADI_HAS_PWM__           1
-#define __ADI_HAS_VID__           1
-#define __ADI_HAS_SWU__           1
-#define __ADI_HAS_SDU__           1
-#define __ADI_HAS_EMAC__          1
-#define __ADI_HAS_SPORT__         1
-#define __ADI_HAS_SPI__           1
-#define __ADI_HAS_DMA__           1
-#define __ADI_HAS_ACM__           1
-#define __ADI_HAS_DMC__           1
-#define __ADI_HAS_SCB__           1
-#define __ADI_HAS_L2CTL__         1
-#define __ADI_HAS_SEC__           1
-#define __ADI_HAS_TRU__           1
-#define __ADI_HAS_RCU__           1
-#define __ADI_HAS_SPU__           1
-#define __ADI_HAS_CGU__           1
-#define __ADI_HAS_DPM__           1
-#define __ADI_HAS_EFS__           1
-#define __ADI_HAS_USB__           1
-#define __ADI_HAS_L1DM__          1
-#define __ADI_HAS_L1IM__          1
-#define __ADI_HAS_ICU__           1
-#define __ADI_HAS_TMR__           1
-#define __ADI_HAS_DBG__           1
-#define __ADI_HAS_TB__            1
-#define __ADI_HAS_WP__            1
-#define __ADI_HAS_PF__            1
-
-/* =========================
-        REGFILE
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ASTAT                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ASTAT_VS                        25                               /* Sticky version of ASTAT_V */
-#define BITP_ASTAT_V                         24                               /* Overflow Flag */
-#define BITP_ASTAT_AV1S                      19                               /* Sticky Overflow Flag 1 */
-#define BITP_ASTAT_AV1                       18                               /* Overflow Flag 1 */
-#define BITP_ASTAT_AV0S                      17                               /* Sticky Overflow Flag 0 */
-#define BITP_ASTAT_AV0                       16                               /* Overflow Flag 0 */
-#define BITP_ASTAT_AC1                       13                               /* Carry Flag 1 */
-#define BITP_ASTAT_AC0                       12                               /* Carry Flag 0 */
-#define BITP_ASTAT_RND_MOD                    8                               /* Rounding Mode */
-#define BITP_ASTAT_AQ                         6                               /* Quotient Bit */
-#define BITP_ASTAT_CC                         5                               /* Condition Code */
-#define BITP_ASTAT_V_COPY                     3                               /* Overflow Flag */
-#define BITP_ASTAT_AC0_COPY                   2                               /* Carry Flag 0 */
-#define BITP_ASTAT_AN                         1                               /* Negative Flag */
-#define BITP_ASTAT_AZ                         0                               /* Zero Flag */
-#define BITM_ASTAT_VS                        (_ADI_MSK(0x02000000,uint32_t))  /* Sticky version of ASTAT_V */
-#define BITM_ASTAT_V                         (_ADI_MSK(0x01000000,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AV1S                      (_ADI_MSK(0x00080000,uint32_t))  /* Sticky Overflow Flag 1 */
-#define BITM_ASTAT_AV1                       (_ADI_MSK(0x00040000,uint32_t))  /* Overflow Flag 1 */
-#define BITM_ASTAT_AV0S                      (_ADI_MSK(0x00020000,uint32_t))  /* Sticky Overflow Flag 0 */
-#define BITM_ASTAT_AV0                       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow Flag 0 */
-#define BITM_ASTAT_AC1                       (_ADI_MSK(0x00002000,uint32_t))  /* Carry Flag 1 */
-#define BITM_ASTAT_AC0                       (_ADI_MSK(0x00001000,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_RND_MOD                   (_ADI_MSK(0x00000100,uint32_t))  /* Rounding Mode */
-#define BITM_ASTAT_AQ                        (_ADI_MSK(0x00000040,uint32_t))  /* Quotient Bit */
-#define BITM_ASTAT_CC                        (_ADI_MSK(0x00000020,uint32_t))  /* Condition Code */
-#define BITM_ASTAT_V_COPY                    (_ADI_MSK(0x00000008,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AC0_COPY                  (_ADI_MSK(0x00000004,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_AN                        (_ADI_MSK(0x00000002,uint32_t))  /* Negative Flag */
-#define BITM_ASTAT_AZ                        (_ADI_MSK(0x00000001,uint32_t))  /* Zero Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LT                                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LT_ADDR                          1                               /* Loop Top Address */
-#define BITP_LT_LSB                           0
-#define BITM_LT_ADDR                         (_ADI_MSK(0xFFFFFFFE,uint32_t))  /* Loop Top Address */
-#define BITM_LT_LSB                          (_ADI_MSK(0x00000001,uint32_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEQSTAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEQSTAT_NSPECABT                19                               /* Nonspeculative access was aborted */
-#define BITP_SEQSTAT_HWERRCAUSE              14                               /* Holds cause of last hardware error generated by the core */
-#define BITP_SEQSTAT_SFTRESET                13                               /* Indicates whether the last reset was a software reset */
-#define BITP_SEQSTAT_ITESTABT                12                               /* ITEST_COMMAND was aborted */
-#define BITP_SEQSTAT_DTESTABT                11                               /* DTEST_COMMAND was aborted */
-#define BITP_SEQSTAT_SYSNMI                  10                               /* System NMI Input Active */
-#define BITP_SEQSTAT_PEIC                     9                               /* Parity Error on Instruction L1 Read for Core */
-#define BITP_SEQSTAT_PEDC                     8                               /* Parity Error on Data L1 Read for Core */
-#define BITP_SEQSTAT_PEIX                     7                               /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_PEDX                     6                               /* Parity Error on Data L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_EXCAUSE                  0                               /* Holds cause of last-executed exception */
-#define BITM_SEQSTAT_NSPECABT                (_ADI_MSK(0x00080000,uint32_t))  /* Nonspeculative access was aborted */
-#define BITM_SEQSTAT_HWERRCAUSE              (_ADI_MSK(0x0007C000,uint32_t))  /* Holds cause of last hardware error generated by the core */
-#define BITM_SEQSTAT_SFTRESET                (_ADI_MSK(0x00002000,uint32_t))  /* Indicates whether the last reset was a software reset */
-#define BITM_SEQSTAT_ITESTABT                (_ADI_MSK(0x00001000,uint32_t))  /* ITEST_COMMAND was aborted */
-#define BITM_SEQSTAT_DTESTABT                (_ADI_MSK(0x00000800,uint32_t))  /* DTEST_COMMAND was aborted */
-#define BITM_SEQSTAT_SYSNMI                  (_ADI_MSK(0x00000400,uint32_t))  /* System NMI Input Active */
-#define BITM_SEQSTAT_PEIC                    (_ADI_MSK(0x00000200,uint32_t))  /* Parity Error on Instruction L1 Read for Core */
-#define BITM_SEQSTAT_PEDC                    (_ADI_MSK(0x00000100,uint32_t))  /* Parity Error on Data L1 Read for Core */
-#define BITM_SEQSTAT_PEIX                    (_ADI_MSK(0x00000080,uint32_t))  /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITM_SEQSTAT_PEDX                    (_ADI_MSK(0x00000040,uint32_t))  /* Parity Error on Data L1 Read for L2 Transfer */
-
-#define BITM_SEQSTAT_EXCAUSE                 (_ADI_MSK(0x0000003F,uint32_t))  /* Holds cause of last-executed exception */
-#define ENUM_SEQSTAT_EXINST                  (_ADI_MSK(0x00000000,uint32_t))  /* EXCAUSE: EXCPT Instruction */
-#define ENUM_SEQSTAT_SSTEP                   (_ADI_MSK(0x00000010,uint32_t))  /* EXCAUSE: Single Step */
-#define ENUM_SEQSTAT_EMUTROV                 (_ADI_MSK(0x00000011,uint32_t))  /* EXCAUSE: Trace Buffer */
-#define ENUM_SEQSTAT_UNDEFINST               (_ADI_MSK(0x00000021,uint32_t))  /* EXCAUSE: Undefined Instruction */
-#define ENUM_SEQSTAT_ILLCOMB                 (_ADI_MSK(0x00000022,uint32_t))  /* EXCAUSE: Illegal Combination */
-#define ENUM_SEQSTAT_DAGPROTVIOL             (_ADI_MSK(0x00000023,uint32_t))  /* EXCAUSE: DAG Protection Violation */
-#define ENUM_SEQSTAT_DAGALGN                 (_ADI_MSK(0x00000024,uint32_t))  /* EXCAUSE: DAG Misaligned Access */
-#define ENUM_SEQSTAT_UNRECOVER               (_ADI_MSK(0x00000025,uint32_t))  /* EXCAUSE: Unrecoverable Event */
-#define ENUM_SEQSTAT_DAGCPLBMISS             (_ADI_MSK(0x00000026,uint32_t))  /* EXCAUSE: DAG CPLB Miss */
-#define ENUM_SEQSTAT_DAGMCPLBH               (_ADI_MSK(0x00000027,uint32_t))  /* EXCAUSE: DAG Multiple CPLB Hits */
-#define ENUM_SEQSTAT_EMUWPMATCH              (_ADI_MSK(0x00000028,uint32_t))  /* EXCAUSE: Watchpoint Match */
-#define ENUM_SEQSTAT_IFALGN                  (_ADI_MSK(0x0000002A,uint32_t))  /* EXCAUSE: I-Fetch Misaligned Access */
-#define ENUM_SEQSTAT_IFPROTVIOL              (_ADI_MSK(0x0000002B,uint32_t))  /* EXCAUSE: I-Fetch Protection Violation */
-#define ENUM_SEQSTAT_IFCPLBMISS              (_ADI_MSK(0x0000002C,uint32_t))  /* EXCAUSE: I-Fetch CPLB Miss */
-#define ENUM_SEQSTAT_IFMCPLBH                (_ADI_MSK(0x0000002D,uint32_t))  /* EXCAUSE: I-Fetch Multiple CPLB Hits */
-#define ENUM_SEQSTAT_PROTVIOL                (_ADI_MSK(0x0000002E,uint32_t))  /* EXCAUSE: Illegal use superv. res */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SYSCFG                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SYSCFG_SNEN                      2                               /* Self-Nesting Interrupt Enable */
-#define BITP_SYSCFG_CCEN                      1                               /* Enable cycle counter */
-#define BITP_SYSCFG_SSSTEP                    0                               /* Supervisor single step */
-#define BITM_SYSCFG_SNEN                     (_ADI_MSK(0x00000004,uint32_t))  /* Self-Nesting Interrupt Enable */
-#define BITM_SYSCFG_CCEN                     (_ADI_MSK(0x00000002,uint32_t))  /* Enable cycle counter */
-#define BITM_SYSCFG_SSSTEP                   (_ADI_MSK(0x00000001,uint32_t))  /* Supervisor single step */
-
-/* ==================================================
-        CNT Registers
-   ================================================== */
-
-/* =========================
-        CNT0
-   ========================= */
-#define REG_CNT0_CFG                    0xFFC00400         /* CNT0 Configuration Register */
-#define REG_CNT0_IMSK                   0xFFC00404         /* CNT0 Interrupt Mask Register */
-#define REG_CNT0_STAT                   0xFFC00408         /* CNT0 Status Register */
-#define REG_CNT0_CMD                    0xFFC0040C         /* CNT0 Command Register */
-#define REG_CNT0_DEBNCE                 0xFFC00410         /* CNT0 Debounce Register */
-#define REG_CNT0_CNTR                   0xFFC00414         /* CNT0 Counter Register */
-#define REG_CNT0_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
-#define REG_CNT0_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
-
-/* =========================
-        CNT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CFG_INPDIS                  15                               /* CUD and CDG Pin Input Disable */
-#define BITP_CNT_CFG_BNDMODE                 12                               /* Boundary Register Mode */
-#define BITP_CNT_CFG_ZMZC                    11                               /* CZM Zeroes Counter Enable */
-#define BITP_CNT_CFG_CNTMODE                  8                               /* Counter Operating Mode */
-#define BITP_CNT_CFG_CZMINV                   6                               /* CZM Pin Polarity Invert */
-#define BITP_CNT_CFG_CUDINV                   5                               /* CUD Pin Polarity Invert */
-#define BITP_CNT_CFG_CDGINV                   4                               /* CDG Pin Polarity Invert */
-#define BITP_CNT_CFG_DEBEN                    1                               /* Debounce Enable */
-#define BITP_CNT_CFG_EN                       0                               /* Counter Enable */
-
-#define BITM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* CUD and CDG Pin Input Disable */
-#define ENUM_CNT_CFG_NO_INPDIS               (_ADI_MSK(0x00000000,uint16_t))  /* INPDIS: Enable */
-#define ENUM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* INPDIS: Pin Input Disable */
-
-#define BITM_CNT_CFG_BNDMODE                 (_ADI_MSK(0x00003000,uint16_t))  /* Boundary Register Mode */
-#define ENUM_CNT_CFG_BNDMODE_BNDCOMP         (_ADI_MSK(0x00000000,uint16_t))  /* BNDMODE: BND_COMP */
-#define ENUM_CNT_CFG_BNDMODE_BINENC          (_ADI_MSK(0x00001000,uint16_t))  /* BNDMODE: BIN_ENC */
-#define ENUM_CNT_CFG_BNDMODE_BNDCAPT         (_ADI_MSK(0x00002000,uint16_t))  /* BNDMODE: BND_CAPT */
-#define ENUM_CNT_CFG_BNDMODE_BNDAEXT         (_ADI_MSK(0x00003000,uint16_t))  /* BNDMODE: BND_AEXT */
-
-#define BITM_CNT_CFG_ZMZC                    (_ADI_MSK(0x00000800,uint16_t))  /* CZM Zeroes Counter Enable */
-#define ENUM_CNT_CFG_ZMZC_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* ZMZC: Disable */
-#define ENUM_CNT_CFG_ZMZC_EN                 (_ADI_MSK(0x00000800,uint16_t))  /* ZMZC: Enable */
-
-#define BITM_CNT_CFG_CNTMODE                 (_ADI_MSK(0x00000700,uint16_t))  /* Counter Operating Mode */
-#define ENUM_CNT_CFG_CNTMODE_QUADENC         (_ADI_MSK(0x00000000,uint16_t))  /* CNTMODE: QUAD_ENC */
-#define ENUM_CNT_CFG_CNTMODE_BINENC          (_ADI_MSK(0x00000100,uint16_t))  /* CNTMODE: BIN_ENC */
-#define ENUM_CNT_CFG_CNTMODE_UDCNT           (_ADI_MSK(0x00000200,uint16_t))  /* CNTMODE: UD_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRCNT          (_ADI_MSK(0x00000400,uint16_t))  /* CNTMODE: DIR_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRTMR          (_ADI_MSK(0x00000500,uint16_t))  /* CNTMODE: DIR_TMR */
-
-#define BITM_CNT_CFG_CZMINV                  (_ADI_MSK(0x00000040,uint16_t))  /* CZM Pin Polarity Invert */
-#define ENUM_CNT_CFG_CZMINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CZMINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CZMINV_ALO              (_ADI_MSK(0x00000040,uint16_t))  /* CZMINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CUDINV                  (_ADI_MSK(0x00000020,uint16_t))  /* CUD Pin Polarity Invert */
-#define ENUM_CNT_CFG_CUDINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CUDINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CUDINV_ALO              (_ADI_MSK(0x00000020,uint16_t))  /* CUDINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CDGINV                  (_ADI_MSK(0x00000010,uint16_t))  /* CDG Pin Polarity Invert */
-#define ENUM_CNT_CFG_CDGINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CDGINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CDGINV_ALO              (_ADI_MSK(0x00000010,uint16_t))  /* CDGINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* Debounce Enable */
-#define ENUM_CNT_CFG_DEBDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* DEBEN: Disable */
-#define ENUM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* DEBEN: Enable */
-
-#define BITM_CNT_CFG_EN                      (_ADI_MSK(0x00000001,uint16_t))  /* Counter Enable */
-#define ENUM_CNT_CFG_CNTDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Counter Disable */
-#define ENUM_CNT_CFG_CNTEN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Counter Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_IMSK_CZMZ                   10                               /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define BITP_CNT_IMSK_CZME                    9                               /* Zero Marker Error Interrupt Enable */
-#define BITP_CNT_IMSK_CZM                     8                               /* CZM Pin / Pushbutton Interrupt Enable */
-#define BITP_CNT_IMSK_CZERO                   7                               /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define BITP_CNT_IMSK_COV15                   6                               /* Bit 15 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_COV31                   5                               /* Bit 31 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_MAXC                    4                               /* Max Count Interrupt Enable */
-#define BITP_CNT_IMSK_MINC                    3                               /* Min Count Interrupt Enable */
-#define BITP_CNT_IMSK_DC                      2                               /* Downcount Interrupt enable */
-#define BITP_CNT_IMSK_UC                      1                               /* Upcount Interrupt Enable */
-#define BITP_CNT_IMSK_IC                      0                               /* Illegal Gray/Binary Code Interrupt Enable */
-
-#define BITM_CNT_IMSK_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define ENUM_CNT_IMSK_CZMZ_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZMZ: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZMZ_UMSK              (_ADI_MSK(0x00000400,uint16_t))  /* CZMZ: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error Interrupt Enable */
-#define ENUM_CNT_IMSK_CZME_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZME: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZME_UMSK              (_ADI_MSK(0x00000200,uint16_t))  /* CZME: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin / Pushbutton Interrupt Enable */
-#define ENUM_CNT_IMSK_CZM_MSK                (_ADI_MSK(0x00000000,uint16_t))  /* CZM: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZM_UMSK               (_ADI_MSK(0x00000100,uint16_t))  /* CZM: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define ENUM_CNT_IMSK_CZERO_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* CZERO: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZERO_UMSK             (_ADI_MSK(0x00000080,uint16_t))  /* CZERO: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV15_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV15: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV15_UMSK             (_ADI_MSK(0x00000040,uint16_t))  /* COV15: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV31_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV31: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV31_UMSK             (_ADI_MSK(0x00000020,uint16_t))  /* COV31: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MAXC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MAXC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MAXC_UMSK              (_ADI_MSK(0x00000010,uint16_t))  /* MAXC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MINC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MINC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MINC_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* MINC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount Interrupt enable */
-#define ENUM_CNT_IMSK_DC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* DC: Mask Interrupt */
-#define ENUM_CNT_IMSK_DC_UMSK                (_ADI_MSK(0x00000004,uint16_t))  /* DC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount Interrupt Enable */
-#define ENUM_CNT_IMSK_UC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* UC: Mask Interrupt */
-#define ENUM_CNT_IMSK_UC_UMSK                (_ADI_MSK(0x00000002,uint16_t))  /* UC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal Gray/Binary Code Interrupt Enable */
-#define ENUM_CNT_IMSK_IC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* IC: Mask Interrupt */
-#define ENUM_CNT_IMSK_IC_UMSK                (_ADI_MSK(0x00000001,uint16_t))  /* IC: Unmask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_STAT_CZMZ                   10                               /* Counter Zeroed By Zero Marker interrupt */
-#define BITP_CNT_STAT_CZME                    9                               /* Zero Marker Error interrupt */
-#define BITP_CNT_STAT_CZM                     8                               /* CZM Pin/Pushbutton interrupt */
-#define BITP_CNT_STAT_CZERO                   7                               /* CNT_CNTR Counts To Zero interrupt */
-#define BITP_CNT_STAT_COV15                   6                               /* Bit 15 overflow interrupt */
-#define BITP_CNT_STAT_COV31                   5                               /* Bit 31 overflow interrupt */
-#define BITP_CNT_STAT_MAXC                    4                               /* Max interrupt */
-#define BITP_CNT_STAT_MINC                    3                               /* Min interrupt */
-#define BITP_CNT_STAT_DC                      2                               /* Downcount interrupt */
-#define BITP_CNT_STAT_UC                      1                               /* Upcount interrupt */
-#define BITP_CNT_STAT_IC                      0                               /* Illegal gray/binary code interrupt */
-#define BITM_CNT_STAT_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed By Zero Marker interrupt */
-#define BITM_CNT_STAT_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error interrupt */
-#define BITM_CNT_STAT_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin/Pushbutton interrupt */
-#define BITM_CNT_STAT_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero interrupt */
-#define BITM_CNT_STAT_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 overflow interrupt */
-#define BITM_CNT_STAT_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 overflow interrupt */
-#define BITM_CNT_STAT_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max interrupt */
-#define BITM_CNT_STAT_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min interrupt */
-#define BITM_CNT_STAT_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount interrupt */
-#define BITM_CNT_STAT_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount interrupt */
-#define BITM_CNT_STAT_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal gray/binary code interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CMD_W1ZMONCE                12                               /* Write 1 Zero Marker Clear Once Enable */
-#define BITP_CNT_CMD_W1LMAXMIN               10                               /* Write 1 MAX copy from MIN */
-#define BITP_CNT_CMD_W1LMAXCNT                9                               /* Write 1 MAX capture from CNTR */
-#define BITP_CNT_CMD_W1LMAXZERO               8                               /* Write 1 MAX to zero */
-#define BITP_CNT_CMD_W1LMINMAX                7                               /* Write 1 MIN copy from MAX */
-#define BITP_CNT_CMD_W1LMINCNT                5                               /* Write 1 MIN capture from CNTR */
-#define BITP_CNT_CMD_W1LMINZERO               4                               /* Write 1 MIN to zero */
-#define BITP_CNT_CMD_W1LCNTMAX                3                               /* Write 1 CNTR load from MAX */
-#define BITP_CNT_CMD_W1LCNTMIN                2                               /* Write 1 CNTR load from MIN */
-#define BITP_CNT_CMD_W1LCNTZERO               0                               /* Write 1 CNTR to zero */
-#define BITM_CNT_CMD_W1ZMONCE                (_ADI_MSK(0x00001000,uint16_t))  /* Write 1 Zero Marker Clear Once Enable */
-#define BITM_CNT_CMD_W1LMAXMIN               (_ADI_MSK(0x00000400,uint16_t))  /* Write 1 MAX copy from MIN */
-#define BITM_CNT_CMD_W1LMAXCNT               (_ADI_MSK(0x00000200,uint16_t))  /* Write 1 MAX capture from CNTR */
-#define BITM_CNT_CMD_W1LMAXZERO              (_ADI_MSK(0x00000100,uint16_t))  /* Write 1 MAX to zero */
-#define BITM_CNT_CMD_W1LMINMAX               (_ADI_MSK(0x00000080,uint16_t))  /* Write 1 MIN copy from MAX */
-#define BITM_CNT_CMD_W1LMINCNT               (_ADI_MSK(0x00000020,uint16_t))  /* Write 1 MIN capture from CNTR */
-#define BITM_CNT_CMD_W1LMINZERO              (_ADI_MSK(0x00000010,uint16_t))  /* Write 1 MIN to zero */
-#define BITM_CNT_CMD_W1LCNTMAX               (_ADI_MSK(0x00000008,uint16_t))  /* Write 1 CNTR load from MAX */
-#define BITM_CNT_CMD_W1LCNTMIN               (_ADI_MSK(0x00000004,uint16_t))  /* Write 1 CNTR load from MIN */
-#define BITM_CNT_CMD_W1LCNTZERO              (_ADI_MSK(0x00000001,uint16_t))  /* Write 1 CNTR to zero */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_DEBNCE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_DEBNCE_DPRESCALE             0                               /* Debounce Prescale */
-#define BITM_CNT_DEBNCE_DPRESCALE            (_ADI_MSK(0x0000001F,uint16_t))  /* Debounce Prescale */
-
-/* ==================================================
-        RSI Registers
-   ================================================== */
-
-/* =========================
-        RSI0
-   ========================= */
-#define REG_RSI0_CTL                    0xFFC00604         /* RSI0 Control Register */
-#define REG_RSI0_ARG                    0xFFC00608         /* RSI0 Argument Register */
-#define REG_RSI0_CMD                    0xFFC0060C         /* RSI0 Command Register */
-#define REG_RSI0_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
-#define REG_RSI0_RESP0                  0xFFC00614         /* RSI0 Response 0 Register */
-#define REG_RSI0_RESP1                  0xFFC00618         /* RSI0 Response 1 Register */
-#define REG_RSI0_RESP2                  0xFFC0061C         /* RSI0 Response 2 Register */
-#define REG_RSI0_RESP3                  0xFFC00620         /* RSI0 Response 3 Register */
-#define REG_RSI0_DATA_TMR               0xFFC00624         /* RSI0 Data Timer Register */
-#define REG_RSI0_DATA_LEN               0xFFC00628         /* RSI0 Data Length Register */
-#define REG_RSI0_DATA_CTL               0xFFC0062C         /* RSI0 Data Control Register */
-#define REG_RSI0_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
-#define REG_RSI0_XFRSTAT                0xFFC00634         /* RSI0 Status Register */
-#define REG_RSI0_XFRSTAT_CLR            0xFFC00638         /* RSI0 Status Clear Register */
-#define REG_RSI0_XFR_IMSK0              0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
-#define REG_RSI0_XFR_IMSK1              0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
-#define REG_RSI0_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
-#define REG_RSI0_CEATA                  0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
-#define REG_RSI0_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
-#define REG_RSI0_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
-#define REG_RSI0_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
-#define REG_RSI0_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
-#define REG_RSI0_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
-#define REG_RSI0_STAT0                  0xFFC006C0         /* RSI0 Exception Status Register */
-#define REG_RSI0_IMSK0                  0xFFC006C4         /* RSI0 Exception Mask Register */
-#define REG_RSI0_CFG                    0xFFC006C8         /* RSI0 Configuration Register */
-#define REG_RSI0_RD_WAIT                0xFFC006CC         /* RSI0 Read Wait Enable Register */
-#define REG_RSI0_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
-
-/* =========================
-        RSI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CTL_CARDTYPE                13                               /* Type of Card */
-#define BITP_RSI_CTL_BUSWID                  11                               /* Wide Bus Mode Enable */
-#define BITP_RSI_CTL_BYPASS                  10                               /* Bypass clock divisor */
-#define BITP_RSI_CTL_PWRSAVE                  9                               /* Power Save Enable */
-#define BITP_RSI_CTL_CLKEN                    8                               /* RSI_CLK Bus Clock Enable */
-#define BITP_RSI_CTL_CLKDIV                   0                               /* RSI_CLK Divisor */
-#define BITM_RSI_CTL_CARDTYPE                (_ADI_MSK(0x0000E000,uint16_t))  /* Type of Card */
-#define BITM_RSI_CTL_BUSWID                  (_ADI_MSK(0x00001800,uint16_t))  /* Wide Bus Mode Enable */
-#define BITM_RSI_CTL_BYPASS                  (_ADI_MSK(0x00000400,uint16_t))  /* Bypass clock divisor */
-#define BITM_RSI_CTL_PWRSAVE                 (_ADI_MSK(0x00000200,uint16_t))  /* Power Save Enable */
-#define BITM_RSI_CTL_CLKEN                   (_ADI_MSK(0x00000100,uint16_t))  /* RSI_CLK Bus Clock Enable */
-#define BITM_RSI_CTL_CLKDIV                  (_ADI_MSK(0x000000FF,uint16_t))  /* RSI_CLK Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CMD_CHKBUSY                 12                               /* Check Busy Condition */
-#define BITP_RSI_CMD_CRCDIS                  11                               /* Disable CRC Check */
-#define BITP_RSI_CMD_EN                      10                               /* Command Enable */
-#define BITP_RSI_CMD_PNDEN                    9                               /* Command Pending enabled */
-#define BITP_RSI_CMD_IEN                      8                               /* Command Interrupt Enabled */
-#define BITP_RSI_CMD_LRSP                     7                               /* Long Response */
-#define BITP_RSI_CMD_RSP                      6                               /* Response */
-#define BITP_RSI_CMD_IDX                      0                               /* Command Index */
-#define BITM_RSI_CMD_CHKBUSY                 (_ADI_MSK(0x00001000,uint16_t))  /* Check Busy Condition */
-#define BITM_RSI_CMD_CRCDIS                  (_ADI_MSK(0x00000800,uint16_t))  /* Disable CRC Check */
-#define BITM_RSI_CMD_EN                      (_ADI_MSK(0x00000400,uint16_t))  /* Command Enable */
-#define BITM_RSI_CMD_PNDEN                   (_ADI_MSK(0x00000200,uint16_t))  /* Command Pending enabled */
-#define BITM_RSI_CMD_IEN                     (_ADI_MSK(0x00000100,uint16_t))  /* Command Interrupt Enabled */
-#define BITM_RSI_CMD_LRSP                    (_ADI_MSK(0x00000080,uint16_t))  /* Long Response */
-#define BITM_RSI_CMD_RSP                     (_ADI_MSK(0x00000040,uint16_t))  /* Response */
-#define BITM_RSI_CMD_IDX                     (_ADI_MSK(0x0000003F,uint16_t))  /* Command Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RESP_CMD                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RESP_CMD_VALUE               0                               /* Response Command */
-#define BITM_RSI_RESP_CMD_VALUE              (_ADI_MSK(0x0000003F,uint16_t))  /* Response Command */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_DATA_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_DATA_CTL_CEATAIEN            9                               /* Ceata Command Completion Interrupt Enable */
-#define BITP_RSI_DATA_CTL_CEATAMODE           8                               /* Ceata Mode enable */
-#define BITP_RSI_DATA_CTL_DMAEN               3                               /* Data Transfer DMA Enable */
-#define BITP_RSI_DATA_CTL_DATMODE             2                               /* Data Transfer Mode */
-#define BITP_RSI_DATA_CTL_DATDIR              1                               /* Data Transfer Direction */
-#define BITP_RSI_DATA_CTL_DATEN               0                               /* Data Transfer Enable */
-#define BITM_RSI_DATA_CTL_CEATAIEN           (_ADI_MSK(0x00000200,uint16_t))  /* Ceata Command Completion Interrupt Enable */
-#define BITM_RSI_DATA_CTL_CEATAMODE          (_ADI_MSK(0x00000100,uint16_t))  /* Ceata Mode enable */
-#define BITM_RSI_DATA_CTL_DMAEN              (_ADI_MSK(0x00000008,uint16_t))  /* Data Transfer DMA Enable */
-#define BITM_RSI_DATA_CTL_DATMODE            (_ADI_MSK(0x00000004,uint16_t))  /* Data Transfer Mode */
-#define BITM_RSI_DATA_CTL_DATDIR             (_ADI_MSK(0x00000002,uint16_t))  /* Data Transfer Direction */
-#define BITM_RSI_DATA_CTL_DATEN              (_ADI_MSK(0x00000001,uint16_t))  /* Data Transfer Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_RXFIFORDY           21                               /* Receive FIFO Available */
-#define BITP_RSI_XFRSTAT_TXFIFORDY           20                               /* Transmit FIFO Available */
-#define BITP_RSI_XFRSTAT_RXFIFOZERO          19                               /* Receive FIFO Empty */
-#define BITP_RSI_XFRSTAT_TXFIFOZERO          18                               /* Transmit FIFO Empty */
-#define BITP_RSI_XFRSTAT_RXFIFOFULL          17                               /* Receive FIFO Full */
-#define BITP_RSI_XFRSTAT_TXFIFOFULL          16                               /* Transmit FIFO Full */
-#define BITP_RSI_XFRSTAT_RXFIFOSTAT          15                               /* Receive FIFO Status */
-#define BITP_RSI_XFRSTAT_TXFIFOSTAT          14                               /* Transmit FIFO Status */
-#define BITP_RSI_XFRSTAT_RXACT               13                               /* Receive Active */
-#define BITP_RSI_XFRSTAT_TXACT               12                               /* Transmit Active */
-#define BITP_RSI_XFRSTAT_CMDACT              11                               /* Command Active */
-#define BITP_RSI_XFRSTAT_DATBLKEND           10                               /* Data Block End */
-#define BITP_RSI_XFRSTAT_SBITERR              9                               /* Start Bit Error */
-#define BITP_RSI_XFRSTAT_DATEND               8                               /* Data End */
-#define BITP_RSI_XFRSTAT_CMDSENT              7                               /* Command Sent */
-#define BITP_RSI_XFRSTAT_RESPEND              6                               /* Command Response End */
-#define BITP_RSI_XFRSTAT_RXOVER               5                               /* Receive Over run */
-#define BITP_RSI_XFRSTAT_TXUNDR               4                               /* Transmit Under run */
-#define BITP_RSI_XFRSTAT_DATTO                3                               /* Data Timeout */
-#define BITP_RSI_XFRSTAT_CMDTO                2                               /* CMD Timeout */
-#define BITP_RSI_XFRSTAT_DATCRCFAIL           1                               /* Data CRC Fail */
-#define BITP_RSI_XFRSTAT_CMDCRCFAIL           0                               /* CMD CRC Fail */
-#define BITM_RSI_XFRSTAT_RXFIFORDY           (_ADI_MSK(0x00200000,uint32_t))  /* Receive FIFO Available */
-#define BITM_RSI_XFRSTAT_TXFIFORDY           (_ADI_MSK(0x00100000,uint32_t))  /* Transmit FIFO Available */
-#define BITM_RSI_XFRSTAT_RXFIFOZERO          (_ADI_MSK(0x00080000,uint32_t))  /* Receive FIFO Empty */
-#define BITM_RSI_XFRSTAT_TXFIFOZERO          (_ADI_MSK(0x00040000,uint32_t))  /* Transmit FIFO Empty */
-#define BITM_RSI_XFRSTAT_RXFIFOFULL          (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Full */
-#define BITM_RSI_XFRSTAT_TXFIFOFULL          (_ADI_MSK(0x00010000,uint32_t))  /* Transmit FIFO Full */
-#define BITM_RSI_XFRSTAT_RXFIFOSTAT          (_ADI_MSK(0x00008000,uint32_t))  /* Receive FIFO Status */
-#define BITM_RSI_XFRSTAT_TXFIFOSTAT          (_ADI_MSK(0x00004000,uint32_t))  /* Transmit FIFO Status */
-#define BITM_RSI_XFRSTAT_RXACT               (_ADI_MSK(0x00002000,uint32_t))  /* Receive Active */
-#define BITM_RSI_XFRSTAT_TXACT               (_ADI_MSK(0x00001000,uint32_t))  /* Transmit Active */
-#define BITM_RSI_XFRSTAT_CMDACT              (_ADI_MSK(0x00000800,uint32_t))  /* Command Active */
-#define BITM_RSI_XFRSTAT_DATBLKEND           (_ADI_MSK(0x00000400,uint32_t))  /* Data Block End */
-#define BITM_RSI_XFRSTAT_SBITERR             (_ADI_MSK(0x00000200,uint32_t))  /* Start Bit Error */
-#define BITM_RSI_XFRSTAT_DATEND              (_ADI_MSK(0x00000100,uint32_t))  /* Data End */
-#define BITM_RSI_XFRSTAT_CMDSENT             (_ADI_MSK(0x00000080,uint32_t))  /* Command Sent */
-#define BITM_RSI_XFRSTAT_RESPEND             (_ADI_MSK(0x00000040,uint32_t))  /* Command Response End */
-#define BITM_RSI_XFRSTAT_RXOVER              (_ADI_MSK(0x00000020,uint32_t))  /* Receive Over run */
-#define BITM_RSI_XFRSTAT_TXUNDR              (_ADI_MSK(0x00000010,uint32_t))  /* Transmit Under run */
-#define BITM_RSI_XFRSTAT_DATTO               (_ADI_MSK(0x00000008,uint32_t))  /* Data Timeout */
-#define BITM_RSI_XFRSTAT_CMDTO               (_ADI_MSK(0x00000004,uint32_t))  /* CMD Timeout */
-#define BITM_RSI_XFRSTAT_DATCRCFAIL          (_ADI_MSK(0x00000002,uint32_t))  /* Data CRC Fail */
-#define BITM_RSI_XFRSTAT_CMDCRCFAIL          (_ADI_MSK(0x00000001,uint32_t))  /* CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT_CLR                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_CLR_DATBLKEND       10                               /* Data Block End Status */
-#define BITP_RSI_XFRSTAT_CLR_STRTBITERR       9                               /* Start Bit Error Status */
-#define BITP_RSI_XFRSTAT_CLR_DATEND           8                               /* Data End Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDSENT          7                               /* Command Sent Status */
-#define BITP_RSI_XFRSTAT_CLR_RESPEND          6                               /* Command Response End Status */
-#define BITP_RSI_XFRSTAT_CLR_RXOVER           5                               /* Receive Over run Status */
-#define BITP_RSI_XFRSTAT_CLR_TXUNDR           4                               /* Transmit Under run Status */
-#define BITP_RSI_XFRSTAT_CLR_DATTO            3                               /* Data Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDTO            2                               /* CMD Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_DATCRCFAIL       1                               /* Data CRC Fail Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDCRCFAIL       0                               /* CMD CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_DATBLKEND       (_ADI_MSK(0x00000400,uint16_t))  /* Data Block End Status */
-#define BITM_RSI_XFRSTAT_CLR_STRTBITERR      (_ADI_MSK(0x00000200,uint16_t))  /* Start Bit Error Status */
-#define BITM_RSI_XFRSTAT_CLR_DATEND          (_ADI_MSK(0x00000100,uint16_t))  /* Data End Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDSENT         (_ADI_MSK(0x00000080,uint16_t))  /* Command Sent Status */
-#define BITM_RSI_XFRSTAT_CLR_RESPEND         (_ADI_MSK(0x00000040,uint16_t))  /* Command Response End Status */
-#define BITM_RSI_XFRSTAT_CLR_RXOVER          (_ADI_MSK(0x00000020,uint16_t))  /* Receive Over run Status */
-#define BITM_RSI_XFRSTAT_CLR_TXUNDR          (_ADI_MSK(0x00000010,uint16_t))  /* Transmit Under run Status */
-#define BITM_RSI_XFRSTAT_CLR_DATTO           (_ADI_MSK(0x00000008,uint16_t))  /* Data Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDTO           (_ADI_MSK(0x00000004,uint16_t))  /* CMD Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_DATCRCFAIL      (_ADI_MSK(0x00000002,uint16_t))  /* Data CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDCRCFAIL      (_ADI_MSK(0x00000001,uint16_t))  /* CMD CRC Fail Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK0_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK0_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK0_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK0_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK0_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK0_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK0_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK0_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK0_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK0_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK0_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK0_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK0_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK0_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK0_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK0_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK0_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK0_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK0_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK0_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK0_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK0_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK0_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK0_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK0_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK0_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK0_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK0_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK0_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK0_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK0_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK0_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK0_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK0_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK0_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK0_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK0_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK0_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK0_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK0_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK1_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK1_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK1_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK1_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK1_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK1_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK1_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK1_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK1_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK1_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK1_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK1_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK1_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK1_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK1_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK1_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK1_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK1_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK1_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK1_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK1_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK1_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK1_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK1_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK1_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK1_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK1_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK1_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK1_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK1_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK1_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK1_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK1_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK1_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK1_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK1_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK1_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK1_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK1_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK1_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_FIFO_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_FIFO_CNT_VALUE               0                               /* FIFO Count */
-#define BITM_RSI_FIFO_CNT_VALUE              (_ADI_MSK(0x00007FFF,uint16_t))  /* FIFO Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CEATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CEATA_INT_DIS                0                               /* CEATA Disable Interrupt */
-#define BITM_RSI_CEATA_INT_DIS               (_ADI_MSK(0x00000001,uint32_t))  /* CEATA Disable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BOOT_TCNTR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BOOT_TCNTR_HOLD              8                               /* Boot Hold Time */
-#define BITP_RSI_BOOT_TCNTR_SETUP             0                               /* Boot Setup Time */
-#define BITM_RSI_BOOT_TCNTR_HOLD             (_ADI_MSK(0x0000FF00,uint16_t))  /* Boot Hold Time */
-#define BITM_RSI_BOOT_TCNTR_SETUP            (_ADI_MSK(0x000000FF,uint16_t))  /* Boot Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BLKSZ                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BLKSZ_VALUE                  0                               /* Size of Each Block of Data */
-#define BITM_RSI_BLKSZ_VALUE                 (_ADI_MSK(0x00001FFF,uint16_t))  /* Size of Each Block of Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_STAT0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_STAT0_BUSYMODE              31                               /* Card is in Busy mode */
-#define BITP_RSI_STAT0_SLPMODE               30                               /* Card in Sleep Mode */
-#define BITP_RSI_STAT0_CARDRDY               17                               /* Card Ready */
-#define BITP_RSI_STAT0_SLPWKPTOUT            16                               /* Sleep Wakeup Timer Expired */
-#define BITP_RSI_STAT0_WKPDONE               15                               /* Card Entered Standby state */
-#define BITP_RSI_STAT0_SLPDONE               14                               /* Card Entered Sleep State */
-#define BITP_RSI_STAT0_BACKDONE              13                               /* Correct Boot Ack is received */
-#define BITP_RSI_STAT0_BACKBAD               12                               /* Boot Ack received is corrupted */
-#define BITP_RSI_STAT0_BACKTO                11                               /* Boot Acknowledge Timeout */
-#define BITP_RSI_STAT0_BDATTO                10                               /* Boot Data Timeout */
-#define BITP_RSI_STAT0_BHOLDEXP               9                               /* Boot Hold Time Expiry */
-#define BITP_RSI_STAT0_BSETUPEXP              8                               /* Boot Setup Time Expiry */
-#define BITP_RSI_STAT0_CEATAINT               5                               /* CEATA Interrupt */
-#define BITP_RSI_STAT0_SDCARD                 4                               /* SD Card Detected */
-#define BITP_RSI_STAT0_SDIOINT                1                               /* SDIO Interrupt */
-#define BITM_RSI_STAT0_BUSYMODE              (_ADI_MSK(0x80000000,uint32_t))  /* Card is in Busy mode */
-#define BITM_RSI_STAT0_SLPMODE               (_ADI_MSK(0x40000000,uint32_t))  /* Card in Sleep Mode */
-#define BITM_RSI_STAT0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Card Ready */
-#define BITM_RSI_STAT0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Sleep Wakeup Timer Expired */
-#define BITM_RSI_STAT0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Card Entered Standby state */
-#define BITM_RSI_STAT0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Card Entered Sleep State */
-#define BITM_RSI_STAT0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Correct Boot Ack is received */
-#define BITM_RSI_STAT0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Boot Ack received is corrupted */
-#define BITM_RSI_STAT0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Boot Acknowledge Timeout */
-#define BITM_RSI_STAT0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Boot Data Timeout */
-#define BITM_RSI_STAT0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Boot Hold Time Expiry */
-#define BITM_RSI_STAT0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Boot Setup Time Expiry */
-#define BITM_RSI_STAT0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* CEATA Interrupt */
-#define BITM_RSI_STAT0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* SD Card Detected */
-#define BITM_RSI_STAT0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_IMSK0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_IMSK0_CARDRDY               17                               /* Mask Interrupt for Card Ready */
-#define BITP_RSI_IMSK0_SLPWKPTOUT            16                               /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITP_RSI_IMSK0_WKPDONE               15                               /* Mask Interrupt for Card Entered Standby state */
-#define BITP_RSI_IMSK0_SLPDONE               14                               /* Mask Interrupt for Card Entered Sleep State */
-#define BITP_RSI_IMSK0_BACKDONE              13                               /* Mask Interrupt for Correct Boot Ack is received */
-#define BITP_RSI_IMSK0_BACKBAD               12                               /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITP_RSI_IMSK0_BACKTO                11                               /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITP_RSI_IMSK0_BDATTO                10                               /* Mask Interrupt for Boot Data Timeout */
-#define BITP_RSI_IMSK0_BHOLDEXP               9                               /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITP_RSI_IMSK0_BSETUPEXP              8                               /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITP_RSI_IMSK0_CEATAINT               5                               /* Mask CEATA Interrupt */
-#define BITP_RSI_IMSK0_SDCARD                 4                               /* Mask Interrupt for SD Card Detected */
-#define BITP_RSI_IMSK0_SDIOINT                1                               /* Mask SDIO Interrupt */
-#define BITM_RSI_IMSK0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Mask Interrupt for Card Ready */
-#define BITM_RSI_IMSK0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITM_RSI_IMSK0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Mask Interrupt for Card Entered Standby state */
-#define BITM_RSI_IMSK0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Mask Interrupt for Card Entered Sleep State */
-#define BITM_RSI_IMSK0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Mask Interrupt for Correct Boot Ack is received */
-#define BITM_RSI_IMSK0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITM_RSI_IMSK0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITM_RSI_IMSK0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Mask Interrupt for Boot Data Timeout */
-#define BITM_RSI_IMSK0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITM_RSI_IMSK0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITM_RSI_IMSK0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* Mask CEATA Interrupt */
-#define BITM_RSI_IMSK0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* Mask Interrupt for SD Card Detected */
-#define BITM_RSI_IMSK0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* Mask SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CFG_BACKEN                  14                               /* Boot Acknowledge enabled */
-#define BITP_RSI_CFG_MMCBMODE                13                               /* MMC Boot Mode select */
-#define BITP_RSI_CFG_MMCBEN                  12                               /* MMC Boot Enabled */
-#define BITP_RSI_CFG_OPENDRAIN               11                               /* MC_CMD Output Control */
-#define BITP_RSI_CFG_PWRON                    9                               /* 11 - RSI Enabled */
-#define BITP_RSI_CFG_IEBYPDIS                 8                               /* Disabled IE Bypass */
-#define BITP_RSI_CFG_DAT3PUP                  6                               /* Pull-Up SD_DAT3 */
-#define BITP_RSI_CFG_DATPUP                   5                               /* Pull-Up SD_DAT */
-#define BITP_RSI_CFG_RST                      4                               /* SDMMC Reset */
-#define BITP_RSI_CFG_MWINEN                   3                               /* Moving Window Enable */
-#define BITP_RSI_CFG_SD4EN                    2                               /* SDIO 4-Bit Enable */
-#define BITP_RSI_CFG_CLKSEN                   0                               /* Clocks Enable */
-#define BITM_RSI_CFG_BACKEN                  (_ADI_MSK(0x00004000,uint16_t))  /* Boot Acknowledge enabled */
-#define BITM_RSI_CFG_MMCBMODE                (_ADI_MSK(0x00002000,uint16_t))  /* MMC Boot Mode select */
-#define BITM_RSI_CFG_MMCBEN                  (_ADI_MSK(0x00001000,uint16_t))  /* MMC Boot Enabled */
-#define BITM_RSI_CFG_OPENDRAIN               (_ADI_MSK(0x00000800,uint16_t))  /* MC_CMD Output Control */
-#define BITM_RSI_CFG_PWRON                   (_ADI_MSK(0x00000600,uint16_t))  /* 11 - RSI Enabled */
-#define BITM_RSI_CFG_IEBYPDIS                (_ADI_MSK(0x00000100,uint16_t))  /* Disabled IE Bypass */
-#define BITM_RSI_CFG_DAT3PUP                 (_ADI_MSK(0x00000040,uint16_t))  /* Pull-Up SD_DAT3 */
-#define BITM_RSI_CFG_DATPUP                  (_ADI_MSK(0x00000020,uint16_t))  /* Pull-Up SD_DAT */
-#define BITM_RSI_CFG_RST                     (_ADI_MSK(0x00000010,uint16_t))  /* SDMMC Reset */
-#define BITM_RSI_CFG_MWINEN                  (_ADI_MSK(0x00000008,uint16_t))  /* Moving Window Enable */
-#define BITM_RSI_CFG_SD4EN                   (_ADI_MSK(0x00000004,uint16_t))  /* SDIO 4-Bit Enable */
-#define BITM_RSI_CFG_CLKSEN                  (_ADI_MSK(0x00000001,uint16_t))  /* Clocks Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RD_WAIT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RD_WAIT_REQUEST              0                               /* Read Wait Request */
-#define BITM_RSI_RD_WAIT_REQUEST             (_ADI_MSK(0x00000001,uint16_t))  /* Read Wait Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID0                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID0_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID0_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID1_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID1_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID2_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID2_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID3                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID3_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID3_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ==================================================
-        Controller Area Network Registers
-   ================================================== */
-
-/* =========================
-        CAN0
-   ========================= */
-#define REG_CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration 1 Register */
-#define REG_CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction 1 Register */
-#define REG_CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set 1 Register */
-#define REG_CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset 1 Register */
-#define REG_CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge 1 Register */
-#define REG_CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge 1 Register */
-#define REG_CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending 1 Register */
-#define REG_CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost 1 Register */
-#define REG_CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define REG_CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define REG_CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define REG_CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling 1 Register */
-#define REG_CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define REG_CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration 2 Register */
-#define REG_CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction 2 Register */
-#define REG_CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set 2 Register */
-#define REG_CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset 2 Register */
-#define REG_CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge 2 Register */
-#define REG_CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge 2 Register */
-#define REG_CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending 2 Register */
-#define REG_CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost 2 Register */
-#define REG_CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define REG_CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define REG_CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define REG_CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling 2 Register */
-#define REG_CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define REG_CAN0_CLK                    0xFFC00A80         /* CAN0 Clock Register */
-#define REG_CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
-#define REG_CAN0_DBG                    0xFFC00A88         /* CAN0 Debug Register */
-#define REG_CAN0_STAT                   0xFFC00A8C         /* CAN0 Status Register */
-#define REG_CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
-#define REG_CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status Register */
-#define REG_CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask Register */
-#define REG_CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag Register */
-#define REG_CAN0_CTL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
-#define REG_CAN0_INT                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
-#define REG_CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
-#define REG_CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
-#define REG_CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
-#define REG_CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
-#define REG_CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
-#define REG_CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
-#define REG_CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox ID 1 Register */
-
-/* =========================
-        CAN
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC1_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD1_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS1_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR1_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA1_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA1_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP1_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML1_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF1_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF1_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM1_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH1_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS1_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC2_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD2_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS2_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR2_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA2_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA2_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP2_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML2_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF2_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF2_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM2_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH2_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS2_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CLK_BRP                      0                               /* Bit Rate Prescaler */
-#define BITM_CAN_CLK_BRP                     (_ADI_MSK(0x000003FF,uint16_t))  /* Bit Rate Prescaler */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TIMING                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TIMING_SJW                   8                               /* Synchronization Jump Width */
-#define BITP_CAN_TIMING_SAM                   7                               /* Sampling */
-#define BITP_CAN_TIMING_TSEG2                 4                               /* Time Segment 2 */
-#define BITP_CAN_TIMING_TSEG1                 0                               /* Time Segment 1 */
-#define BITM_CAN_TIMING_SJW                  (_ADI_MSK(0x00000300,uint16_t))  /* Synchronization Jump Width */
-#define BITM_CAN_TIMING_SAM                  (_ADI_MSK(0x00000080,uint16_t))  /* Sampling */
-#define BITM_CAN_TIMING_TSEG2                (_ADI_MSK(0x00000070,uint16_t))  /* Time Segment 2 */
-#define BITM_CAN_TIMING_TSEG1                (_ADI_MSK(0x0000000F,uint16_t))  /* Time Segment 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_DBG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_DBG_CDE                     15                               /* CAN Debug Mode Enable */
-#define BITP_CAN_DBG_MRB                      5                               /* Mode Read Back */
-#define BITP_CAN_DBG_MAA                      4                               /* Mode Auto Acknowledge */
-#define BITP_CAN_DBG_DIL                      3                               /* Disable Internal Loop */
-#define BITP_CAN_DBG_DTO                      2                               /* Disable Tx Output Pin */
-#define BITP_CAN_DBG_DRI                      1                               /* Disable Receive Input Pin */
-#define BITP_CAN_DBG_DEC                      0                               /* Disable Transmit and Receive Error Counters */
-#define BITM_CAN_DBG_CDE                     (_ADI_MSK(0x00008000,uint16_t))  /* CAN Debug Mode Enable */
-#define BITM_CAN_DBG_MRB                     (_ADI_MSK(0x00000020,uint16_t))  /* Mode Read Back */
-#define BITM_CAN_DBG_MAA                     (_ADI_MSK(0x00000010,uint16_t))  /* Mode Auto Acknowledge */
-#define BITM_CAN_DBG_DIL                     (_ADI_MSK(0x00000008,uint16_t))  /* Disable Internal Loop */
-#define BITM_CAN_DBG_DTO                     (_ADI_MSK(0x00000004,uint16_t))  /* Disable Tx Output Pin */
-#define BITM_CAN_DBG_DRI                     (_ADI_MSK(0x00000002,uint16_t))  /* Disable Receive Input Pin */
-#define BITM_CAN_DBG_DEC                     (_ADI_MSK(0x00000001,uint16_t))  /* Disable Transmit and Receive Error Counters */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_STAT_REC                    15                               /* Receive Mode */
-#define BITP_CAN_STAT_TRM                    14                               /* Transmit Mode */
-#define BITP_CAN_STAT_MBPTR                   8                               /* Mailbox Pointer */
-#define BITP_CAN_STAT_CCA                     7                               /* CAN Configuration Mode Acknowledge */
-#define BITP_CAN_STAT_CSA                     6                               /* CAN Suspend Mode Acknowledge */
-#define BITP_CAN_STAT_EBO                     3                               /* CAN Error Bus Off Mode */
-#define BITP_CAN_STAT_EP                      2                               /* CAN Error Passive Mode */
-#define BITP_CAN_STAT_WR                      1                               /* CAN Receive Warning Flag */
-#define BITP_CAN_STAT_WT                      0                               /* CAN Transmit Warning Flag */
-#define BITM_CAN_STAT_REC                    (_ADI_MSK(0x00008000,uint16_t))  /* Receive Mode */
-#define BITM_CAN_STAT_TRM                    (_ADI_MSK(0x00004000,uint16_t))  /* Transmit Mode */
-#define BITM_CAN_STAT_MBPTR                  (_ADI_MSK(0x00001F00,uint16_t))  /* Mailbox Pointer */
-#define BITM_CAN_STAT_CCA                    (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Acknowledge */
-#define BITM_CAN_STAT_CSA                    (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Acknowledge */
-#define BITM_CAN_STAT_EBO                    (_ADI_MSK(0x00000008,uint16_t))  /* CAN Error Bus Off Mode */
-#define BITM_CAN_STAT_EP                     (_ADI_MSK(0x00000004,uint16_t))  /* CAN Error Passive Mode */
-#define BITM_CAN_STAT_WR                     (_ADI_MSK(0x00000002,uint16_t))  /* CAN Receive Warning Flag */
-#define BITM_CAN_STAT_WT                     (_ADI_MSK(0x00000001,uint16_t))  /* CAN Transmit Warning Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CEC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CEC_TXECNT                   8                               /* Transmit Error Counter */
-#define BITP_CAN_CEC_RXECNT                   0                               /* Receive Error Counter */
-#define BITM_CAN_CEC_TXECNT                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Counter */
-#define BITM_CAN_CEC_RXECNT                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Counter */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIS                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIS_ADIS                    10                               /* Access Denied Interrupt Status */
-#define BITP_CAN_GIS_UCEIS                    8                               /* Universal Counter Exceeded Interrupt Status */
-#define BITP_CAN_GIS_RMLIS                    7                               /* Receive Message Lost Interrupt Status */
-#define BITP_CAN_GIS_AAIS                     6                               /* Abort Acknowledge Interrupt Status */
-#define BITP_CAN_GIS_UIAIS                    5                               /* Unimplemented Address Interrupt Status */
-#define BITP_CAN_GIS_WUIS                     4                               /* Wake Up Interrupt Status */
-#define BITP_CAN_GIS_BOIS                     3                               /* Bus Off Interrupt Status */
-#define BITP_CAN_GIS_EPIS                     2                               /* Error Passive Interrupt Status */
-#define BITP_CAN_GIS_EWRIS                    1                               /* Error Warning Receive  Interrupt Status */
-#define BITP_CAN_GIS_EWTIS                    0                               /* Error Warning Transmit Interrupt Status */
-#define BITM_CAN_GIS_ADIS                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Status */
-#define BITM_CAN_GIS_UCEIS                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Status */
-#define BITM_CAN_GIS_RMLIS                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Status */
-#define BITM_CAN_GIS_AAIS                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Status */
-#define BITM_CAN_GIS_UIAIS                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Status */
-#define BITM_CAN_GIS_WUIS                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Status */
-#define BITM_CAN_GIS_BOIS                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Status */
-#define BITM_CAN_GIS_EPIS                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Status */
-#define BITM_CAN_GIS_EWRIS                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive  Interrupt Status */
-#define BITM_CAN_GIS_EWTIS                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIM                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIM_ADIM                    10                               /* Access Denied Interrupt Mask */
-#define BITP_CAN_GIM_UCEIM                    8                               /* Universal Counter Exceeded Interrupt Mask */
-#define BITP_CAN_GIM_RMLIM                    7                               /* Receive Message Lost Interrupt Mask */
-#define BITP_CAN_GIM_AAIM                     6                               /* Abort Acknowledge Interrupt Mask */
-#define BITP_CAN_GIM_UIAIM                    5                               /* Unimplemented Address Interrupt Mask */
-#define BITP_CAN_GIM_WUIM                     4                               /* Wake Up Interrupt Mask */
-#define BITP_CAN_GIM_BOIM                     3                               /* Bus Off Interrupt Mask */
-#define BITP_CAN_GIM_EPIM                     2                               /* Error Passive Interrupt Mask */
-#define BITP_CAN_GIM_EWRIM                    1                               /* Error Warning Receive Interrupt Mask */
-#define BITP_CAN_GIM_EWTIM                    0                               /* Error Warning Transmit Interrupt Mask */
-#define BITM_CAN_GIM_ADIM                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Mask */
-#define BITM_CAN_GIM_UCEIM                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Mask */
-#define BITM_CAN_GIM_RMLIM                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Mask */
-#define BITM_CAN_GIM_AAIM                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Mask */
-#define BITM_CAN_GIM_UIAIM                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Mask */
-#define BITM_CAN_GIM_WUIM                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Mask */
-#define BITM_CAN_GIM_BOIM                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Mask */
-#define BITM_CAN_GIM_EPIM                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Mask */
-#define BITM_CAN_GIM_EWRIM                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Mask */
-#define BITM_CAN_GIM_EWTIM                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIF                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIF_ADIF                    10                               /* Access Denied Interrupt Flag */
-#define BITP_CAN_GIF_UCEIF                    8                               /* Universal Counter Exceeded Interrupt Flag */
-#define BITP_CAN_GIF_RMLIF                    7                               /* Receive Message Lost Interrupt Flag */
-#define BITP_CAN_GIF_AAIF                     6                               /* Abort Acknowledge Interrupt Flag */
-#define BITP_CAN_GIF_UIAIF                    5                               /* Unimplemented Address Interrupt Flag */
-#define BITP_CAN_GIF_WUIF                     4                               /* Wake Up Interrupt Flag */
-#define BITP_CAN_GIF_BOIF                     3                               /* Bus Off Interrupt Flag */
-#define BITP_CAN_GIF_EPIF                     2                               /* Error Passive Interrupt Flag */
-#define BITP_CAN_GIF_EWRIF                    1                               /* Error Warning Receive Interrupt Flag */
-#define BITP_CAN_GIF_EWTIF                    0                               /* Error Warning Transmit Interrupt Flag */
-#define BITM_CAN_GIF_ADIF                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Flag */
-#define BITM_CAN_GIF_UCEIF                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Flag */
-#define BITM_CAN_GIF_RMLIF                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Flag */
-#define BITM_CAN_GIF_AAIF                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Flag */
-#define BITM_CAN_GIF_UIAIF                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Flag */
-#define BITM_CAN_GIF_WUIF                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Flag */
-#define BITM_CAN_GIF_BOIF                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Flag */
-#define BITM_CAN_GIF_EPIF                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Flag */
-#define BITM_CAN_GIF_EWRIF                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Flag */
-#define BITM_CAN_GIF_EWTIF                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CTL_CCR                      7                               /* CAN Configuration Mode Request */
-#define BITP_CAN_CTL_CSR                      6                               /* CAN Suspend Mode Request */
-#define BITP_CAN_CTL_SMR                      5                               /* Sleep Mode Request */
-#define BITP_CAN_CTL_WBA                      4                               /* Wake Up on CAN Bus Activity */
-#define BITP_CAN_CTL_ABO                      2                               /* Auto Bus On */
-#define BITP_CAN_CTL_DNM                      1                               /* Device Net Mode */
-#define BITP_CAN_CTL_SRS                      0                               /* Software Reset */
-#define BITM_CAN_CTL_CCR                     (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Request */
-#define BITM_CAN_CTL_CSR                     (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Request */
-#define BITM_CAN_CTL_SMR                     (_ADI_MSK(0x00000020,uint16_t))  /* Sleep Mode Request */
-#define BITM_CAN_CTL_WBA                     (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up on CAN Bus Activity */
-#define BITM_CAN_CTL_ABO                     (_ADI_MSK(0x00000004,uint16_t))  /* Auto Bus On */
-#define BITM_CAN_CTL_DNM                     (_ADI_MSK(0x00000002,uint16_t))  /* Device Net Mode */
-#define BITM_CAN_CTL_SRS                     (_ADI_MSK(0x00000001,uint16_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_INT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_INT_CANRX                    7                               /* Serial Input From Transceiver */
-#define BITP_CAN_INT_CANTX                    6                               /* Serial Input To Transceiver */
-#define BITP_CAN_INT_SMACK                    3                               /* Sleep Mode Acknowledge */
-#define BITP_CAN_INT_GIRQ                     2                               /* Global CAN Interrupt Output */
-#define BITP_CAN_INT_MBTIRQ                   1                               /* Mailbox Transmit Interrupt Output */
-#define BITP_CAN_INT_MBRIRQ                   0                               /* Mailbox Receive Interrupt Output */
-#define BITM_CAN_INT_CANRX                   (_ADI_MSK(0x00000080,uint16_t))  /* Serial Input From Transceiver */
-#define BITM_CAN_INT_CANTX                   (_ADI_MSK(0x00000040,uint16_t))  /* Serial Input To Transceiver */
-#define BITM_CAN_INT_SMACK                   (_ADI_MSK(0x00000008,uint16_t))  /* Sleep Mode Acknowledge */
-#define BITM_CAN_INT_GIRQ                    (_ADI_MSK(0x00000004,uint16_t))  /* Global CAN Interrupt Output */
-#define BITM_CAN_INT_MBTIRQ                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox Transmit Interrupt Output */
-#define BITM_CAN_INT_MBRIRQ                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox Receive Interrupt Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTD_TDR                     7                               /* Temporary Disable Request */
-#define BITP_CAN_MBTD_TDA                     6                               /* Temporary Disable Acknowledge */
-#define BITP_CAN_MBTD_TDPTR                   0                               /* Temporary Disable Pointer */
-#define BITM_CAN_MBTD_TDR                    (_ADI_MSK(0x00000080,uint16_t))  /* Temporary Disable Request */
-#define BITM_CAN_MBTD_TDA                    (_ADI_MSK(0x00000040,uint16_t))  /* Temporary Disable Acknowledge */
-#define BITM_CAN_MBTD_TDPTR                  (_ADI_MSK(0x0000001F,uint16_t))  /* Temporary Disable Pointer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_EWR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_EWR_EWLTEC                   8                               /* Transmit Error Warning Limit */
-#define BITP_CAN_EWR_EWLREC                   0                               /* Receive Error Warning Limit */
-#define BITM_CAN_EWR_EWLTEC                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Warning Limit */
-#define BITM_CAN_EWR_EWLREC                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Warning Limit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_ESR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_ESR_FER                      7                               /* Form Error */
-#define BITP_CAN_ESR_BEF                      6                               /* Bit Error Flag */
-#define BITP_CAN_ESR_SAO                      5                               /* Stuck at Dominant */
-#define BITP_CAN_ESR_CRCE                     4                               /* CRC Error */
-#define BITP_CAN_ESR_SER                      3                               /* Stuff Bit Error */
-#define BITP_CAN_ESR_ACKE                     2                               /* Acknowledge Error */
-#define BITM_CAN_ESR_FER                     (_ADI_MSK(0x00000080,uint16_t))  /* Form Error */
-#define BITM_CAN_ESR_BEF                     (_ADI_MSK(0x00000040,uint16_t))  /* Bit Error Flag */
-#define BITM_CAN_ESR_SAO                     (_ADI_MSK(0x00000020,uint16_t))  /* Stuck at Dominant */
-#define BITM_CAN_ESR_CRCE                    (_ADI_MSK(0x00000010,uint16_t))  /* CRC Error */
-#define BITM_CAN_ESR_SER                     (_ADI_MSK(0x00000008,uint16_t))  /* Stuff Bit Error */
-#define BITM_CAN_ESR_ACKE                    (_ADI_MSK(0x00000004,uint16_t))  /* Acknowledge Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_UCCNF                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_UCCNF_UCE                    7                               /* Universal Counter Enable */
-#define BITP_CAN_UCCNF_UCCT                   6                               /* Universal Counter CAN Trigger */
-#define BITP_CAN_UCCNF_UCRC                   5                               /* Universal Counter Reload/Clear */
-#define BITP_CAN_UCCNF_UCCNF                  0                               /* Universal Counter Configuration */
-#define BITM_CAN_UCCNF_UCE                   (_ADI_MSK(0x00000080,uint16_t))  /* Universal Counter Enable */
-#define BITM_CAN_UCCNF_UCCT                  (_ADI_MSK(0x00000040,uint16_t))  /* Universal Counter CAN Trigger */
-#define BITM_CAN_UCCNF_UCRC                  (_ADI_MSK(0x00000020,uint16_t))  /* Universal Counter Reload/Clear */
-#define BITM_CAN_UCCNF_UCCNF                 (_ADI_MSK(0x0000000F,uint16_t))  /* Universal Counter Configuration */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AMnH                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AMH_FDF                     15                               /* Filter on Delay Field */
-#define BITP_CAN_AMH_FMD                     14                               /* Full Mask Data */
-#define BITP_CAN_AMH_AMIDE                   13                               /* Acceptance Mask Identifier Extension */
-#define BITP_CAN_AMH_BASEID                   2                               /* Base Identifier */
-#define BITP_CAN_AMH_EXTID                    0                               /* Extended Identifier */
-#define BITM_CAN_AMH_FDF                     (_ADI_MSK(0x00008000,uint16_t))  /* Filter on Delay Field */
-#define BITM_CAN_AMH_FMD                     (_ADI_MSK(0x00004000,uint16_t))  /* Full Mask Data */
-#define BITM_CAN_AMH_AMIDE                   (_ADI_MSK(0x00002000,uint16_t))  /* Acceptance Mask Identifier Extension */
-#define BITM_CAN_AMH_BASEID                  (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_AMH_EXTID                   (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA0_DFB6                8                               /* Data Field Byte 6 */
-#define BITP_CAN_MB_DATA0_DFB7                0                               /* Data Field Byte 7 */
-#define BITM_CAN_MB_DATA0_DFB6               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 6 */
-#define BITM_CAN_MB_DATA0_DFB7               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 7 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA1_DFB4                8                               /* Data Field Byte 4 */
-#define BITP_CAN_MB_DATA1_DFB5                0                               /* Data Field Byte 5 */
-#define BITM_CAN_MB_DATA1_DFB4               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 4 */
-#define BITM_CAN_MB_DATA1_DFB5               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 5 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA2                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA2_DFB2                8                               /* Data Field Byte 2 */
-#define BITP_CAN_MB_DATA2_DFB3                0                               /* Data Field Byte 3 */
-#define BITM_CAN_MB_DATA2_DFB2               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 2 */
-#define BITM_CAN_MB_DATA2_DFB3               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 3 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA3                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA3_DFB0                8                               /* Data Field Byte 0 */
-#define BITP_CAN_MB_DATA3_DFB1                0                               /* Data Field Byte 1 */
-#define BITM_CAN_MB_DATA3_DFB0               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 0 */
-#define BITM_CAN_MB_DATA3_DFB1               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_LENGTH                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_LENGTH_DLC                0                               /* Data Length Code */
-#define BITM_CAN_MB_LENGTH_DLC               (_ADI_MSK(0x0000000F,uint16_t))  /* Data Length Code */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_ID1                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_ID1_AME                  15                               /* Acceptance Mask Enable */
-#define BITP_CAN_MB_ID1_RTR                  14                               /* Remote Transmission Request */
-#define BITP_CAN_MB_ID1_IDE                  13                               /* Identifier Extension */
-#define BITP_CAN_MB_ID1_BASEID                2                               /* Base Identifier */
-#define BITP_CAN_MB_ID1_EXTID                 0                               /* Extended Identifier */
-#define BITM_CAN_MB_ID1_AME                  (_ADI_MSK(0x00008000,uint16_t))  /* Acceptance Mask Enable */
-#define BITM_CAN_MB_ID1_RTR                  (_ADI_MSK(0x00004000,uint16_t))  /* Remote Transmission Request */
-#define BITM_CAN_MB_ID1_IDE                  (_ADI_MSK(0x00002000,uint16_t))  /* Identifier Extension */
-#define BITM_CAN_MB_ID1_BASEID               (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_MB_ID1_EXTID                (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ==================================================
-        Link Port Registers
-   ================================================== */
-
-/* =========================
-        LP0
-   ========================= */
-#define REG_LP0_CTL                     0xFFC01000         /* LP0 Control Register */
-#define REG_LP0_STAT                    0xFFC01004         /* LP0 Status Register */
-#define REG_LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
-#define REG_LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
-#define REG_LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
-#define REG_LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
-#define REG_LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP1
-   ========================= */
-#define REG_LP1_CTL                     0xFFC01100         /* LP1 Control Register */
-#define REG_LP1_STAT                    0xFFC01104         /* LP1 Status Register */
-#define REG_LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
-#define REG_LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
-#define REG_LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
-#define REG_LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
-#define REG_LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP2
-   ========================= */
-#define REG_LP2_CTL                     0xFFC01200         /* LP2 Control Register */
-#define REG_LP2_STAT                    0xFFC01204         /* LP2 Status Register */
-#define REG_LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
-#define REG_LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
-#define REG_LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
-#define REG_LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
-#define REG_LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP3
-   ========================= */
-#define REG_LP3_CTL                     0xFFC01300         /* LP3 Control Register */
-#define REG_LP3_STAT                    0xFFC01304         /* LP3 Status Register */
-#define REG_LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
-#define REG_LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
-#define REG_LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
-#define REG_LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
-#define REG_LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_CTL                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_CTL_ITMSK                    11                               /* Receive FIFO Overflow Interrupt Mask */
-#define BITP_LP_CTL_RRQMSK                    9                               /* Receive Request Interrupt Mask */
-#define BITP_LP_CTL_TRQMSK                    8                               /* Transmit Request Interrupt Mask */
-#define BITP_LP_CTL_TRAN                      3                               /* Transfer Direction */
-#define BITP_LP_CTL_EN                        0                               /* Enable */
-
-#define BITM_LP_CTL_ITMSK                    (_ADI_MSK(0x00000800,uint32_t))  /* Receive FIFO Overflow Interrupt Mask */
-#define ENUM_LP_CTL_RX_OVF_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* ITMSK: Mask */
-#define ENUM_LP_CTL_RX_OVF_EN                (_ADI_MSK(0x00000800,uint32_t))  /* ITMSK: Unmask */
-
-#define BITM_LP_CTL_RRQMSK                   (_ADI_MSK(0x00000200,uint32_t))  /* Receive Request Interrupt Mask */
-#define ENUM_LP_CTL_RRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* RRQMSK: Mask */
-#define ENUM_LP_CTL_RRQ_EN                   (_ADI_MSK(0x00000200,uint32_t))  /* RRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRQMSK                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Request Interrupt Mask */
-#define ENUM_LP_CTL_TRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* TRQMSK: Mask */
-#define ENUM_LP_CTL_TRQ_EN                   (_ADI_MSK(0x00000100,uint32_t))  /* TRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRAN                     (_ADI_MSK(0x00000008,uint32_t))  /* Transfer Direction */
-#define ENUM_LP_CTL_RX                       (_ADI_MSK(0x00000000,uint32_t))  /* TRAN: Receive */
-#define ENUM_LP_CTL_TX                       (_ADI_MSK(0x00000008,uint32_t))  /* TRAN: Transmit */
-
-#define BITM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_LP_CTL_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable   linkport */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_STAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_STAT_LPBS                     8                               /* Bus Status */
-#define BITP_LP_STAT_LERR                     7                               /* Buffer Pack Error Status */
-#define BITP_LP_STAT_FFST                     4                               /* FIFO Status */
-#define BITP_LP_STAT_LPIT                     3                               /* Receive FIFO Overflow Interrupt */
-#define BITP_LP_STAT_LRRQ                     1                               /* Receive Request */
-#define BITP_LP_STAT_LTRQ                     0                               /* Transmit Request */
-
-#define BITM_LP_STAT_LPBS                    (_ADI_MSK(0x00000100,uint32_t))  /* Bus Status */
-#define ENUM_LP_STAT_IDLE                    (_ADI_MSK(0x00000000,uint32_t))  /* LPBS: Bus is Idle */
-#define ENUM_LP_STAT_BUSY                    (_ADI_MSK(0x00000100,uint32_t))  /* LPBS: Bus Busy */
-
-#define BITM_LP_STAT_LERR                    (_ADI_MSK(0x00000080,uint32_t))  /* Buffer Pack Error Status */
-#define ENUM_LP_STAT_PACK_DONE               (_ADI_MSK(0x00000000,uint32_t))  /* LERR: Packing Complete */
-#define ENUM_LP_STAT_PACK_PROG               (_ADI_MSK(0x00000080,uint32_t))  /* LERR: Packing Incomplete */
-
-#define BITM_LP_STAT_FFST                    (_ADI_MSK(0x00000070,uint32_t))  /* FIFO Status */
-#define ENUM_LP_STAT_RX0_TX0                 (_ADI_MSK(0x00000000,uint32_t))  /* FFST: TX - Empty; RX -Empty */
-#define ENUM_LP_STAT_RX1_TXR                 (_ADI_MSK(0x00000010,uint32_t))  /* FFST: TX - reserved ; RX - One Word */
-#define ENUM_LP_STAT_RX2_TXR                 (_ADI_MSK(0x00000020,uint32_t))  /* FFST: TX - reserved; RX - Two Word */
-#define ENUM_LP_STAT_RX3_TXR                 (_ADI_MSK(0x00000030,uint32_t))  /* FFST: TX - reserved; RX - Three Word */
-#define ENUM_LP_STAT_RX4_TX1                 (_ADI_MSK(0x00000040,uint32_t))  /* FFST: TX - One Word; RX - Four word */
-#define ENUM_LP_STAT_RXR1_TXR1               (_ADI_MSK(0x00000050,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define ENUM_LP_STAT_RXR2_TXR2               (_ADI_MSK(0x00000060,uint32_t))  /* FFST: TX - FIFO Full; RX - Reserved */
-#define ENUM_LP_STAT_RXR3_TXR3               (_ADI_MSK(0x00000070,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define BITM_LP_STAT_LPIT                    (_ADI_MSK(0x00000008,uint32_t))  /* Receive FIFO Overflow Interrupt */
-#define BITM_LP_STAT_LRRQ                    (_ADI_MSK(0x00000002,uint32_t))  /* Receive Request */
-#define BITM_LP_STAT_LTRQ                    (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_DIV                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_DIV_VALUE                     0                               /* Divisor Value */
-#define BITM_LP_DIV_VALUE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Divisor Value */
-
-/* ==================================================
-        General Purpose Timer Block Registers
-   ================================================== */
-
-/* =========================
-        TIMER0
-   ========================= */
-#define REG_TIMER0_REVID                0xFFC01400         /* TIMER0 Revision ID Register */
-#define REG_TIMER0_RUN                  0xFFC01404         /* TIMER0 Run Register */
-#define REG_TIMER0_RUN_SET              0xFFC01408         /* TIMER0 Run Set Register */
-#define REG_TIMER0_RUN_CLR              0xFFC0140C         /* TIMER0 Run Clear Register */
-#define REG_TIMER0_STOP_CFG             0xFFC01410         /* TIMER0 Stop Configuration Register */
-#define REG_TIMER0_STOP_CFG_SET         0xFFC01414         /* TIMER0 Stop Configuration Set Register */
-#define REG_TIMER0_STOP_CFG_CLR         0xFFC01418         /* TIMER0 Stop Configuration Clear Register */
-#define REG_TIMER0_DATA_IMSK            0xFFC0141C         /* TIMER0 Data Interrupt Mask Register */
-#define REG_TIMER0_STAT_IMSK            0xFFC01420         /* TIMER0 Status Interrupt Mask Register */
-#define REG_TIMER0_TRG_MSK              0xFFC01424         /* TIMER0 Trigger Master Mask Register */
-#define REG_TIMER0_TRG_IE               0xFFC01428         /* TIMER0 Trigger Slave Enable Register */
-#define REG_TIMER0_DATA_ILAT            0xFFC0142C         /* TIMER0 Data Interrupt Latch Register */
-#define REG_TIMER0_STAT_ILAT            0xFFC01430         /* TIMER0 Status Interrupt Latch Register */
-#define REG_TIMER0_ERR_TYPE             0xFFC01434         /* TIMER0 Error Type Status Register */
-#define REG_TIMER0_BCAST_PER            0xFFC01438         /* TIMER0 Broadcast Period Register */
-#define REG_TIMER0_BCAST_WID            0xFFC0143C         /* TIMER0 Broadcast Width Register */
-#define REG_TIMER0_BCAST_DLY            0xFFC01440         /* TIMER0 Broadcast Delay Register */
-#define REG_TIMER0_TMR0_CFG             0xFFC01460         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR1_CFG             0xFFC01480         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR2_CFG             0xFFC014A0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR3_CFG             0xFFC014C0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR4_CFG             0xFFC014E0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR5_CFG             0xFFC01500         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR6_CFG             0xFFC01520         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR7_CFG             0xFFC01540         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR0_CNT             0xFFC01464         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR1_CNT             0xFFC01484         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR2_CNT             0xFFC014A4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR3_CNT             0xFFC014C4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR4_CNT             0xFFC014E4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR5_CNT             0xFFC01504         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR6_CNT             0xFFC01524         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR7_CNT             0xFFC01544         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR0_PER             0xFFC01468         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR1_PER             0xFFC01488         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR2_PER             0xFFC014A8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR3_PER             0xFFC014C8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR4_PER             0xFFC014E8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR5_PER             0xFFC01508         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR6_PER             0xFFC01528         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR7_PER             0xFFC01548         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR0_WID             0xFFC0146C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR1_WID             0xFFC0148C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR2_WID             0xFFC014AC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR3_WID             0xFFC014CC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR4_WID             0xFFC014EC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR5_WID             0xFFC0150C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR6_WID             0xFFC0152C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR7_WID             0xFFC0154C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR0_DLY             0xFFC01470         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR1_DLY             0xFFC01490         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR2_DLY             0xFFC014B0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR3_DLY             0xFFC014D0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR4_DLY             0xFFC014F0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR5_DLY             0xFFC01510         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR6_DLY             0xFFC01530         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR7_DLY             0xFFC01550         /* TIMER0 Timer n Delay Register */
-
-/* =========================
-        TIMER
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_REVID                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_REVID_MAJOR                4                               /* Major Revision ID */
-#define BITP_TIMER_REVID_REV                  0                               /* Incremental Revision ID */
-#define BITM_TIMER_REVID_MAJOR               (_ADI_MSK(0x000000F0,uint16_t))  /* Major Revision ID */
-#define BITM_TIMER_REVID_REV                 (_ADI_MSK(0x0000000F,uint16_t))  /* Incremental Revision ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_TMR00                  0                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR01                  1                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR02                  2                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR03                  3                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR04                  4                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR05                  5                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR06                  6                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR07                  7                               /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR00                 (_ADI_MSK(0x00000001,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR01                 (_ADI_MSK(0x00000002,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR02                 (_ADI_MSK(0x00000004,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR03                 (_ADI_MSK(0x00000008,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR04                 (_ADI_MSK(0x00000010,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR05                 (_ADI_MSK(0x00000020,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR06                 (_ADI_MSK(0x00000040,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR07                 (_ADI_MSK(0x00000080,uint16_t))  /* Start/Stop Timer n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_SET_TMR00              0                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR01              1                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR02              2                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR03              3                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR04              4                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR05              5                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR06              6                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR07              7                               /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_CLR_TMR00              0                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR01              1                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR02              2                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR03              3                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR04              4                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR05              5                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR06              6                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR07              7                               /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_TMR00             0                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR01             1                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR02             2                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR03             3                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR04             4                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR05             5                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR06             6                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR07             7                               /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR00            (_ADI_MSK(0x00000001,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR01            (_ADI_MSK(0x00000002,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR02            (_ADI_MSK(0x00000004,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR03            (_ADI_MSK(0x00000008,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR04            (_ADI_MSK(0x00000010,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR05            (_ADI_MSK(0x00000020,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR06            (_ADI_MSK(0x00000040,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR07            (_ADI_MSK(0x00000080,uint16_t))  /* Stop Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_SET                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_SET_TMR00         0                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR01         1                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR02         2                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR03         3                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR04         4                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR05         5                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR06         6                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR07         7                               /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_CLR                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_CLR_TMR00         0                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR01         1                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR02         2                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR03         3                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR04         4                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR05         5                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR06         6                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR07         7                               /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_IMSK_TMR00            0                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR01            1                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR02            2                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR03            3                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR04            4                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR05            5                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR06            6                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR07            7                               /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_IMSK_TMR00            0                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR01            1                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR02            2                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR03            3                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR04            4                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR05            5                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR06            6                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR07            7                               /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_MSK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_MSK_TMR00              0                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR01              1                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR02              2                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR03              3                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR04              4                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR05              5                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR06              6                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR07              7                               /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Output Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_IE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_IE_TMR00               0                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR01               1                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR02               2                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR03               3                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR04               4                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR05               5                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR06               6                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR07               7                               /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR00              (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR01              (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR02              (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR03              (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR04              (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR05              (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR06              (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR07              (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_ILAT_TMR00            0                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR01            1                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR02            2                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR03            3                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR04            4                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR05            5                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR06            6                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR07            7                               /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_ILAT_TMR00            0                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR01            1                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR02            2                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR03            3                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR04            4                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR05            5                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR06            6                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR07            7                               /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_ERR_TYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_ERR_TYPE_TERR7            14                               /* Error type for Timer 7 */
-#define BITP_TIMER_ERR_TYPE_TERR6            12                               /* Error type for Timer 6 */
-#define BITP_TIMER_ERR_TYPE_TERR5            10                               /* Error type for Timer 5 */
-#define BITP_TIMER_ERR_TYPE_TERR4             8                               /* Error type for Timer 4 */
-#define BITP_TIMER_ERR_TYPE_TERR3             6                               /* Error type for Timer 3 */
-#define BITP_TIMER_ERR_TYPE_TERR2             4                               /* Error type for Timer 2 */
-#define BITP_TIMER_ERR_TYPE_TERR1             2                               /* Error type for Timer 1 */
-#define BITP_TIMER_ERR_TYPE_TERR0             0                               /* Error type for Timer 0 */
-
-#define BITM_TIMER_ERR_TYPE_TERR7            (_ADI_MSK(0x0000C000,uint32_t))  /* Error type for Timer 7 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR7          (_ADI_MSK(0x00000000,uint32_t))  /* TERR7: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF7          (_ADI_MSK(0x00004000,uint32_t))  /* TERR7: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG7          (_ADI_MSK(0x00008000,uint32_t))  /* TERR7: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG7        (_ADI_MSK(0x0000C000,uint32_t))  /* TERR7: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR6            (_ADI_MSK(0x00003000,uint32_t))  /* Error type for Timer 6 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR6          (_ADI_MSK(0x00000000,uint32_t))  /* TERR6: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF6          (_ADI_MSK(0x00001000,uint32_t))  /* TERR6: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG6          (_ADI_MSK(0x00002000,uint32_t))  /* TERR6: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG6        (_ADI_MSK(0x00003000,uint32_t))  /* TERR6: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR5            (_ADI_MSK(0x00000C00,uint32_t))  /* Error type for Timer 5 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR5          (_ADI_MSK(0x00000000,uint32_t))  /* TERR5: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF5          (_ADI_MSK(0x00000400,uint32_t))  /* TERR5: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG5          (_ADI_MSK(0x00000800,uint32_t))  /* TERR5: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG5        (_ADI_MSK(0x00000C00,uint32_t))  /* TERR5: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR4            (_ADI_MSK(0x00000300,uint32_t))  /* Error type for Timer 4 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR4          (_ADI_MSK(0x00000000,uint32_t))  /* TERR4: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF4          (_ADI_MSK(0x00000100,uint32_t))  /* TERR4: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG4          (_ADI_MSK(0x00000200,uint32_t))  /* TERR4: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG4        (_ADI_MSK(0x00000300,uint32_t))  /* TERR4: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR3            (_ADI_MSK(0x000000C0,uint32_t))  /* Error type for Timer 3 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR3          (_ADI_MSK(0x00000000,uint32_t))  /* TERR3: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF3          (_ADI_MSK(0x00000040,uint32_t))  /* TERR3: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG3          (_ADI_MSK(0x00000080,uint32_t))  /* TERR3: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG3        (_ADI_MSK(0x000000C0,uint32_t))  /* TERR3: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR2            (_ADI_MSK(0x00000030,uint32_t))  /* Error type for Timer 2 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR2          (_ADI_MSK(0x00000000,uint32_t))  /* TERR2: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF2          (_ADI_MSK(0x00000010,uint32_t))  /* TERR2: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG2          (_ADI_MSK(0x00000020,uint32_t))  /* TERR2: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG2        (_ADI_MSK(0x00000030,uint32_t))  /* TERR2: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR1            (_ADI_MSK(0x0000000C,uint32_t))  /* Error type for Timer 1 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR1          (_ADI_MSK(0x00000000,uint32_t))  /* TERR1: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF1          (_ADI_MSK(0x00000004,uint32_t))  /* TERR1: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG1          (_ADI_MSK(0x00000008,uint32_t))  /* TERR1: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG1        (_ADI_MSK(0x0000000C,uint32_t))  /* TERR1: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR0            (_ADI_MSK(0x00000003,uint32_t))  /* Error type for Timer 0 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR0          (_ADI_MSK(0x00000000,uint32_t))  /* TERR0: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF0          (_ADI_MSK(0x00000001,uint32_t))  /* TERR0: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG0          (_ADI_MSK(0x00000002,uint32_t))  /* TERR0: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG0        (_ADI_MSK(0x00000003,uint32_t))  /* TERR0: WID or DLY Register Programming Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TMR_CFG                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TMR_CFG_EMURUN            15                               /* Run Timer (Counter) During Emulation */
-#define BITP_TIMER_TMR_CFG_BPEREN            14                               /* Broadcast Period Enable */
-#define BITP_TIMER_TMR_CFG_BWIDEN            13                               /* Broadcast Width Enable */
-#define BITP_TIMER_TMR_CFG_BDLYEN            12                               /* Broadcast Delay Enable */
-#define BITP_TIMER_TMR_CFG_OUTDIS            11                               /* Output Disable */
-#define BITP_TIMER_TMR_CFG_TINSEL            10                               /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define BITP_TIMER_TMR_CFG_CLKSEL             8                               /* Clock Select */
-#define BITP_TIMER_TMR_CFG_PULSEHI            7                               /* Polarity Response Select */
-#define BITP_TIMER_TMR_CFG_SLAVETRIG          6                               /* Slave Trigger Response */
-#define BITP_TIMER_TMR_CFG_IRQMODE            4                               /* Interrupt Modes */
-#define BITP_TIMER_TMR_CFG_TMODE              0                               /* Timer Mode Select */
-
-#define BITM_TIMER_TMR_CFG_EMURUN            (_ADI_MSK(0x00008000,uint16_t))  /* Run Timer (Counter) During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_NOCNT         (_ADI_MSK(0x00000000,uint16_t))  /* EMURUN: Stop Timer During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_CNT           (_ADI_MSK(0x00008000,uint16_t))  /* EMURUN: Run Timer During Emulation */
-
-#define BITM_TIMER_TMR_CFG_BPEREN            (_ADI_MSK(0x00004000,uint16_t))  /* Broadcast Period Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BPEREN: Disable Broadcast to PER Register */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_EN       (_ADI_MSK(0x00004000,uint16_t))  /* BPEREN: Enable Broadcast to PER Register */
-
-#define BITM_TIMER_TMR_CFG_BWIDEN            (_ADI_MSK(0x00002000,uint16_t))  /* Broadcast Width Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BWIDEN: Disable Broadcast to WID Register */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_EN       (_ADI_MSK(0x00002000,uint16_t))  /* BWIDEN: Enable Broadcast to WID Register */
-
-#define BITM_TIMER_TMR_CFG_BDLYEN            (_ADI_MSK(0x00001000,uint16_t))  /* Broadcast Delay Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BDLYEN: Disable Broadcast to DLY Register */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_EN       (_ADI_MSK(0x00001000,uint16_t))  /* BDLYEN: Enable Broadcast to DLY Register */
-
-#define BITM_TIMER_TMR_CFG_OUTDIS            (_ADI_MSK(0x00000800,uint16_t))  /* Output Disable */
-#define ENUM_TIMER_TMR_CFG_PADOUT_EN         (_ADI_MSK(0x00000000,uint16_t))  /* OUTDIS: Enable TMR pin output buffer */
-#define ENUM_TIMER_TMR_CFG_PADOUT_DIS        (_ADI_MSK(0x00000800,uint16_t))  /* OUTDIS: Disable TMR pin output buffer */
-
-#define BITM_TIMER_TMR_CFG_TINSEL            (_ADI_MSK(0x00000400,uint16_t))  /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define ENUM_TIMER_TMR_CFG_TINSEL_TMR        (_ADI_MSK(0x00000000,uint16_t))  /* TINSEL: Use TMR pin input */
-#define ENUM_TIMER_TMR_CFG_TINSEL_AUX        (_ADI_MSK(0x00000400,uint16_t))  /* TINSEL: Use TMR Alternate Capture Input */
-
-#define BITM_TIMER_TMR_CFG_CLKSEL            (_ADI_MSK(0x00000300,uint16_t))  /* Clock Select */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_SCLK       (_ADI_MSK(0x00000000,uint16_t))  /* CLKSEL: Use SCLK */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT0       (_ADI_MSK(0x00000100,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK0 as the TMR clock */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT1       (_ADI_MSK(0x00000300,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK1 as the TMR clock */
-
-#define BITM_TIMER_TMR_CFG_PULSEHI           (_ADI_MSK(0x00000080,uint16_t))  /* Polarity Response Select */
-#define ENUM_TIMER_TMR_CFG_NEG_EDGE          (_ADI_MSK(0x00000000,uint16_t))  /* PULSEHI: Negative Response/Pulse */
-#define ENUM_TIMER_TMR_CFG_POS_EDGE          (_ADI_MSK(0x00000080,uint16_t))  /* PULSEHI: Positive  Response/Pulse */
-
-#define BITM_TIMER_TMR_CFG_SLAVETRIG         (_ADI_MSK(0x00000040,uint16_t))  /* Slave Trigger Response */
-#define ENUM_TIMER_TMR_CFG_TRIGSTOP          (_ADI_MSK(0x00000000,uint16_t))  /* SLAVETRIG: Pulse stops timer if it is running */
-#define ENUM_TIMER_TMR_CFG_TRIGSTART         (_ADI_MSK(0x00000040,uint16_t))  /* SLAVETRIG: Pulse starts timer if it is stopped */
-
-#define BITM_TIMER_TMR_CFG_IRQMODE           (_ADI_MSK(0x00000030,uint16_t))  /* Interrupt Modes */
-#define ENUM_TIMER_TMR_CFG_IRQMODE0          (_ADI_MSK(0x00000000,uint16_t))  /* IRQMODE: Active Edge Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE1          (_ADI_MSK(0x00000010,uint16_t))  /* IRQMODE: Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE2          (_ADI_MSK(0x00000020,uint16_t))  /* IRQMODE: Width Plus Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE3          (_ADI_MSK(0x00000030,uint16_t))  /* IRQMODE: Period Expired Mode */
-
-#define BITM_TIMER_TMR_CFG_TMODE             (_ADI_MSK(0x0000000F,uint16_t))  /* Timer Mode Select */
-#define ENUM_TIMER_TMR_CFG_IDLE_MODE         (_ADI_MSK(0x00000000,uint16_t))  /* TMODE: Idle Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP0_MODE      (_ADI_MSK(0x0000000A,uint16_t))  /* TMODE: Width Capture Asserted Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP1_MODE      (_ADI_MSK(0x0000000B,uint16_t))  /* TMODE: Width Capture Deasserted Mode */
-#define ENUM_TIMER_TMR_CFG_PWMCONT_MODE      (_ADI_MSK(0x0000000C,uint16_t))  /* TMODE: Continuous PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_PWMSING_MODE      (_ADI_MSK(0x0000000D,uint16_t))  /* TMODE: Single pulse PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_EXTCLK_MODE       (_ADI_MSK(0x0000000E,uint16_t))  /* TMODE: EXTCLK mode */
-#define ENUM_TIMER_TMR_CFG_PININT_MODE       (_ADI_MSK(0x0000000F,uint16_t))  /* TMODE: PININT (pin interrupt) mode */
-#define ENUM_TIMER_TMR_CFG_WDPER_MODE        (_ADI_MSK(0x00000008,uint16_t))  /* TMODE: Period Watchdog Mode */
-#define ENUM_TIMER_TMR_CFG_WDWID_MODE        (_ADI_MSK(0x00000009,uint16_t))  /* TMODE: Width Watchdog Mode */
-
-/* ==================================================
-        Cyclic Redundancy Check Unit Registers
-   ================================================== */
-
-/* =========================
-        CRC0
-   ========================= */
-#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
-#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 Data Compare Register */
-#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 Data FIFO Register */
-#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 Data Count Capture Register */
-#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 CRC Final Result Register */
-#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 CRC Current Result Register */
-#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
-
-/* =========================
-        CRC1
-   ========================= */
-#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
-#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 Data Compare Register */
-#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 Data FIFO Register */
-#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 Data Count Capture Register */
-#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 CRC Final Result Register */
-#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 CRC Current Result Register */
-#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
-
-/* =========================
-        CRC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_CTL_CMPMIRR                 22                               /* COMPARE Register Mirroring */
-#define BITP_CRC_CTL_POLYMIRR                21                               /* Polynomial Register Mirroring */
-#define BITP_CRC_CTL_RSLTMIRR                20                               /* Result Register Mirroring */
-#define BITP_CRC_CTL_FDSEL                   19                               /* FIFO Data Select */
-#define BITP_CRC_CTL_W16SWP                  18                               /* Word16 Swapping */
-#define BITP_CRC_CTL_BYTMIRR                 17                               /* Byte Mirroring */
-#define BITP_CRC_CTL_BITMIRR                 16                               /* Bit Mirroring */
-#define BITP_CRC_CTL_IRRSTALL                13                               /* Intermediate Result Ready Stall */
-#define BITP_CRC_CTL_OBRSTALL                12                               /* Output Buffer Ready Stall */
-#define BITP_CRC_CTL_AUTOCLRF                 9                               /* Auto Clear to One */
-#define BITP_CRC_CTL_AUTOCLRZ                 8                               /* Auto Clear to Zero */
-#define BITP_CRC_CTL_OPMODE                   4                               /* Operation Mode */
-#define BITP_CRC_CTL_BLKEN                    0                               /* Block Enable */
-#define BITM_CRC_CTL_CMPMIRR                 (_ADI_MSK(0x00400000,uint32_t))  /* COMPARE Register Mirroring */
-#define BITM_CRC_CTL_POLYMIRR                (_ADI_MSK(0x00200000,uint32_t))  /* Polynomial Register Mirroring */
-#define BITM_CRC_CTL_RSLTMIRR                (_ADI_MSK(0x00100000,uint32_t))  /* Result Register Mirroring */
-#define BITM_CRC_CTL_FDSEL                   (_ADI_MSK(0x00080000,uint32_t))  /* FIFO Data Select */
-#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK(0x00040000,uint32_t))  /* Word16 Swapping */
-#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK(0x00020000,uint32_t))  /* Byte Mirroring */
-#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK(0x00010000,uint32_t))  /* Bit Mirroring */
-#define BITM_CRC_CTL_IRRSTALL                (_ADI_MSK(0x00002000,uint32_t))  /* Intermediate Result Ready Stall */
-#define BITM_CRC_CTL_OBRSTALL                (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Ready Stall */
-#define BITM_CRC_CTL_AUTOCLRF                (_ADI_MSK(0x00000200,uint32_t))  /* Auto Clear to One */
-#define BITM_CRC_CTL_AUTOCLRZ                (_ADI_MSK(0x00000100,uint32_t))  /* Auto Clear to Zero */
-#define BITM_CRC_CTL_OPMODE                  (_ADI_MSK(0x000000F0,uint32_t))  /* Operation Mode */
-#define BITM_CRC_CTL_BLKEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Block Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_DCNTEXP                 4                               /* Data Count Expired (Status) Interrupt Enable */
-#define BITP_CRC_INEN_CMPERR                  1                               /* Compare Error Interrupt Enable */
-
-#define BITM_CRC_INEN_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable */
-#define ENUM_CRC_INEN_DCNTEXP_MSK            (_ADI_MSK(0x00000000,uint32_t))  /* DCNTEXP: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_DCNTEXP_UMSK           (_ADI_MSK(0x00000010,uint32_t))  /* DCNTEXP: Enable (unmask) interrupt */
-
-#define BITM_CRC_INEN_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable */
-#define ENUM_CRC_INEN_CMPERR_MSK             (_ADI_MSK(0x00000000,uint32_t))  /* CMPERR: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_CMPERR_UMSK            (_ADI_MSK(0x00000002,uint32_t))  /* CMPERR: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_SET_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITP_CRC_INEN_SET_CMPERR              1                               /* Compare Error Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_CLR_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITP_CRC_INEN_CLR_CMPERR              1                               /* Compare Error Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_STAT_FSTAT                  20                               /* FIFO Status */
-#define BITP_CRC_STAT_LUTDONE                19                               /* Look Up Table Done */
-#define BITP_CRC_STAT_IRR                    18                               /* Intermediate Result Ready */
-#define BITP_CRC_STAT_OBR                    17                               /* Output Buffer Ready */
-#define BITP_CRC_STAT_IBR                    16                               /* Input Buffer Ready */
-#define BITP_CRC_STAT_DCNTEXP                 4                               /* Data Count Expired */
-#define BITP_CRC_STAT_CMPERR                  1                               /* Compare Error */
-#define BITM_CRC_STAT_FSTAT                  (_ADI_MSK(0x00700000,uint32_t))  /* FIFO Status */
-#define BITM_CRC_STAT_LUTDONE                (_ADI_MSK(0x00080000,uint32_t))  /* Look Up Table Done */
-#define BITM_CRC_STAT_IRR                    (_ADI_MSK(0x00040000,uint32_t))  /* Intermediate Result Ready */
-#define BITM_CRC_STAT_OBR                    (_ADI_MSK(0x00020000,uint32_t))  /* Output Buffer Ready */
-#define BITM_CRC_STAT_IBR                    (_ADI_MSK(0x00010000,uint32_t))  /* Input Buffer Ready */
-#define BITM_CRC_STAT_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired */
-#define BITM_CRC_STAT_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_REVID_MAJOR                  4                               /* Major Revision ID */
-#define BITP_CRC_REVID_REV                    0                               /* Incremental Revision ID */
-#define BITM_CRC_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Revision ID */
-#define BITM_CRC_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Revision ID */
-
-/* ==================================================
-        2-Wire Interface Registers
-   ================================================== */
-
-/* =========================
-        TWI0
-   ========================= */
-#define REG_TWI0_CLKDIV                 0xFFC01E00         /* TWI0 SCL Clock Divider Register */
-#define REG_TWI0_CTL                    0xFFC01E04         /* TWI0 Control Register */
-#define REG_TWI0_SLVCTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
-#define REG_TWI0_SLVSTAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
-#define REG_TWI0_SLVADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
-#define REG_TWI0_MSTRCTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
-#define REG_TWI0_MSTRSTAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
-#define REG_TWI0_MSTRADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
-#define REG_TWI0_ISTAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
-#define REG_TWI0_IMSK                   0xFFC01E24         /* TWI0 Interrupt Mask Register */
-#define REG_TWI0_FIFOCTL                0xFFC01E28         /* TWI0 FIFO Control Register */
-#define REG_TWI0_FIFOSTAT               0xFFC01E2C         /* TWI0 FIFO Status Register */
-#define REG_TWI0_TXDATA8                0xFFC01E80         /* TWI0 Tx Data Single-Byte Register */
-#define REG_TWI0_TXDATA16               0xFFC01E84         /* TWI0 Tx Data Double-Byte Register */
-#define REG_TWI0_RXDATA8                0xFFC01E88         /* TWI0 Rx Data Single-Byte Register */
-#define REG_TWI0_RXDATA16               0xFFC01E8C         /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI1
-   ========================= */
-#define REG_TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider Register */
-#define REG_TWI1_CTL                    0xFFC01F04         /* TWI1 Control Register */
-#define REG_TWI1_SLVCTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
-#define REG_TWI1_SLVSTAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
-#define REG_TWI1_SLVADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
-#define REG_TWI1_MSTRCTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
-#define REG_TWI1_MSTRSTAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
-#define REG_TWI1_MSTRADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
-#define REG_TWI1_ISTAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
-#define REG_TWI1_IMSK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
-#define REG_TWI1_FIFOCTL                0xFFC01F28         /* TWI1 FIFO Control Register */
-#define REG_TWI1_FIFOSTAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
-#define REG_TWI1_TXDATA8                0xFFC01F80         /* TWI1 Tx Data Single-Byte Register */
-#define REG_TWI1_TXDATA16               0xFFC01F84         /* TWI1 Tx Data Double-Byte Register */
-#define REG_TWI1_RXDATA8                0xFFC01F88         /* TWI1 Rx Data Single-Byte Register */
-#define REG_TWI1_RXDATA16               0xFFC01F8C         /* TWI1 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CLKDIV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CLKDIV_CLKHI                 8                               /* SCL Clock High Periods */
-#define BITP_TWI_CLKDIV_CLKLO                 0                               /* SCL Clock Low Periods */
-#define BITM_TWI_CLKDIV_CLKHI                (_ADI_MSK(0x0000FF00,uint16_t))  /* SCL Clock High Periods */
-#define BITM_TWI_CLKDIV_CLKLO                (_ADI_MSK(0x000000FF,uint16_t))  /* SCL Clock Low Periods */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CTL_SCCB                     9                               /* SCCB Compatibility */
-#define BITP_TWI_CTL_EN                       7                               /* Enable Module */
-#define BITP_TWI_CTL_PRESCALE                 0                               /* SCLK Prescale Value */
-
-#define BITM_TWI_CTL_SCCB                    (_ADI_MSK(0x00000200,uint16_t))  /* SCCB Compatibility */
-#define ENUM_TWI_CTL_SCCB_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* SCCB: Disable SCCB compatibility */
-#define ENUM_TWI_CTL_SCCB_EN                 (_ADI_MSK(0x00000200,uint16_t))  /* SCCB: Enable SCCB compatibility */
-
-#define BITM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* Enable Module */
-#define ENUM_TWI_CTL_DIS                     (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* EN: Enable */
-#define BITM_TWI_CTL_PRESCALE                (_ADI_MSK(0x0000007F,uint16_t))  /* SCLK Prescale Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVCTL_GEN                   4                               /* General Call Enable */
-#define BITP_TWI_SLVCTL_NAK                   3                               /* Not Acknowledge */
-#define BITP_TWI_SLVCTL_TDVAL                 2                               /* Transmit Data Valid for Slave */
-#define BITP_TWI_SLVCTL_EN                    0                               /* Enable Slave Mode */
-
-#define BITM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* General Call Enable */
-#define ENUM_TWI_SLVCTL_GDIS                 (_ADI_MSK(0x00000000,uint16_t))  /* GEN: Disable General Call Matching */
-#define ENUM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* GEN: Enable General Call Matching */
-
-#define BITM_TWI_SLVCTL_NAK                  (_ADI_MSK(0x00000008,uint16_t))  /* Not Acknowledge */
-#define ENUM_TWI_SLVCTL_ACKGEN               (_ADI_MSK(0x00000000,uint16_t))  /* NAK: Generate ACK */
-#define ENUM_TWI_SLVCTL_NAKGEN               (_ADI_MSK(0x00000008,uint16_t))  /* NAK: Generate NAK */
-
-#define BITM_TWI_SLVCTL_TDVAL                (_ADI_MSK(0x00000004,uint16_t))  /* Transmit Data Valid for Slave */
-#define ENUM_TWI_SLVCTL_INVALID              (_ADI_MSK(0x00000000,uint16_t))  /* TDVAL: Data Invalid for Slave Tx */
-#define ENUM_TWI_SLVCTL_VALID                (_ADI_MSK(0x00000004,uint16_t))  /* TDVAL: Data Valid for Slave Tx */
-
-#define BITM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* Enable Slave Mode */
-#define ENUM_TWI_SLVCTL_DIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVSTAT_GCALL                1                               /* General Call */
-#define BITP_TWI_SLVSTAT_DIR                  0                               /* Transfer Direction for Slave */
-
-#define BITM_TWI_SLVSTAT_GCALL               (_ADI_MSK(0x00000002,uint16_t))  /* General Call */
-#define ENUM_TWI_SLVSTAT_NO                  (_ADI_MSK(0x00000000,uint16_t))  /* GCALL: Not a General Call Address */
-#define ENUM_TWI_SLVSTAT_YES                 (_ADI_MSK(0x00000002,uint16_t))  /* GCALL: General Call Address */
-
-#define BITM_TWI_SLVSTAT_DIR                 (_ADI_MSK(0x00000001,uint16_t))  /* Transfer Direction for Slave */
-#define ENUM_TWI_SLVSTAT_RX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Slave Receive */
-#define ENUM_TWI_SLVSTAT_TX                  (_ADI_MSK(0x00000001,uint16_t))  /* DIR: Slave Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVADDR_ADDR                 0                               /* Slave Mode Address */
-#define BITM_TWI_SLVADDR_ADDR                (_ADI_MSK(0x0000007F,uint16_t))  /* Slave Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRCTL_SCLOVR              15                               /* Serial Clock Override */
-#define BITP_TWI_MSTRCTL_SDAOVR              14                               /* Serial Data Override */
-#define BITP_TWI_MSTRCTL_DCNT                 6                               /* Data Transfer Count */
-#define BITP_TWI_MSTRCTL_RSTART               5                               /* Repeat Start */
-#define BITP_TWI_MSTRCTL_STOP                 4                               /* Issue Stop Condition */
-#define BITP_TWI_MSTRCTL_FAST                 3                               /* Fast Mode */
-#define BITP_TWI_MSTRCTL_DIR                  2                               /* Transfer Direction for Master */
-#define BITP_TWI_MSTRCTL_EN                   0                               /* Enable Master Mode */
-
-#define BITM_TWI_MSTRCTL_SCLOVR              (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Override */
-#define ENUM_TWI_MSTRCTL_SCLNORM             (_ADI_MSK(0x00000000,uint16_t))  /* SCLOVR: Permit Normal SCL Operation */
-#define ENUM_TWI_MSTRCTL_SCLOVER             (_ADI_MSK(0x00008000,uint16_t))  /* SCLOVR: Override Normal SCL Operation */
-
-#define BITM_TWI_MSTRCTL_SDAOVR              (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Override */
-#define ENUM_TWI_MSTRCTL_SDANORM             (_ADI_MSK(0x00000000,uint16_t))  /* SDAOVR: Permit Normal SDA Operation */
-#define ENUM_TWI_MSTRCTL_SDAOVER             (_ADI_MSK(0x00004000,uint16_t))  /* SDAOVR: Override Normal SDA Operation */
-#define BITM_TWI_MSTRCTL_DCNT                (_ADI_MSK(0x00003FC0,uint16_t))  /* Data Transfer Count */
-
-#define BITM_TWI_MSTRCTL_RSTART              (_ADI_MSK(0x00000020,uint16_t))  /* Repeat Start */
-#define ENUM_TWI_MSTRCTL_END                 (_ADI_MSK(0x00000000,uint16_t))  /* RSTART: Disable Repeat Start */
-#define ENUM_TWI_MSTRCTL_RPT                 (_ADI_MSK(0x00000020,uint16_t))  /* RSTART: Enable Repeat Start */
-
-#define BITM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* Issue Stop Condition */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* STOP: Permit Normal Operation */
-#define ENUM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* STOP: Issue Stop */
-
-#define BITM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* Fast Mode */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* FAST: Select Standard Mode */
-#define ENUM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* FAST: Select Fast Mode */
-
-#define BITM_TWI_MSTRCTL_DIR                 (_ADI_MSK(0x00000004,uint16_t))  /* Transfer Direction for Master */
-#define ENUM_TWI_MSTRCTL_TX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Master Transmit */
-#define ENUM_TWI_MSTRCTL_RX                  (_ADI_MSK(0x00000004,uint16_t))  /* DIR: Master Receive */
-
-#define BITM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* Enable Master Mode */
-#define ENUM_TWI_MSTRCTL_DIS                 (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRSTAT_BUSBUSY             8                               /* Bus Busy */
-#define BITP_TWI_MSTRSTAT_SCLSEN              7                               /* Serial Clock Sense */
-#define BITP_TWI_MSTRSTAT_SDASEN              6                               /* Serial Data Sense */
-#define BITP_TWI_MSTRSTAT_BUFWRERR            5                               /* Buffer Write Error */
-#define BITP_TWI_MSTRSTAT_BUFRDERR            4                               /* Buffer Read Error */
-#define BITP_TWI_MSTRSTAT_DNAK                3                               /* Data Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_ANAK                2                               /* Address Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_LOSTARB             1                               /* Lost Arbitration */
-#define BITP_TWI_MSTRSTAT_MPROG               0                               /* Master Transfer in Progress */
-
-#define BITM_TWI_MSTRSTAT_BUSBUSY            (_ADI_MSK(0x00000100,uint16_t))  /* Bus Busy */
-#define ENUM_TWI_MSTRSTAT_FREE               (_ADI_MSK(0x00000000,uint16_t))  /* BUSBUSY: Bus Free */
-#define ENUM_TWI_MSTRSTAT_BUSY               (_ADI_MSK(0x00000100,uint16_t))  /* BUSBUSY: Bus Busy */
-
-#define BITM_TWI_MSTRSTAT_SCLSEN             (_ADI_MSK(0x00000080,uint16_t))  /* Serial Clock Sense */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SCLSEN: SCL Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_YES         (_ADI_MSK(0x00000080,uint16_t))  /* SCLSEN: SCL Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_SDASEN             (_ADI_MSK(0x00000040,uint16_t))  /* Serial Data Sense */
-#define ENUM_TWI_MSTRSTAT_SDASEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SDASEN: SDA Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SDASEN_YES         (_ADI_MSK(0x00000040,uint16_t))  /* SDASEN: SDA Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_BUFWRERR           (_ADI_MSK(0x00000020,uint16_t))  /* Buffer Write Error */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFWRERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_YES       (_ADI_MSK(0x00000020,uint16_t))  /* BUFWRERR: Buffer Write Error */
-
-#define BITM_TWI_MSTRSTAT_BUFRDERR           (_ADI_MSK(0x00000010,uint16_t))  /* Buffer Read Error */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFRDERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_YES       (_ADI_MSK(0x00000010,uint16_t))  /* BUFRDERR: Buffer Read Error */
-
-#define BITM_TWI_MSTRSTAT_DNAK               (_ADI_MSK(0x00000008,uint16_t))  /* Data Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_DNAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* DNAK: No Status */
-#define ENUM_TWI_MSTRSTAT_DNAK_YES           (_ADI_MSK(0x00000008,uint16_t))  /* DNAK: Data NAK */
-
-#define BITM_TWI_MSTRSTAT_ANAK               (_ADI_MSK(0x00000004,uint16_t))  /* Address Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_ANAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* ANAK: No Status */
-#define ENUM_TWI_MSTRSTAT_ANAK_YES           (_ADI_MSK(0x00000004,uint16_t))  /* ANAK: Address NAK */
-
-#define BITM_TWI_MSTRSTAT_LOSTARB            (_ADI_MSK(0x00000002,uint16_t))  /* Lost Arbitration */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_NO         (_ADI_MSK(0x00000000,uint16_t))  /* LOSTARB: No Status */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_YES        (_ADI_MSK(0x00000002,uint16_t))  /* LOSTARB: Lost Arbitration */
-
-#define BITM_TWI_MSTRSTAT_MPROG              (_ADI_MSK(0x00000001,uint16_t))  /* Master Transfer in Progress */
-#define ENUM_TWI_MSTRSTAT_MPROG_NO           (_ADI_MSK(0x00000000,uint16_t))  /* MPROG: No Status */
-#define ENUM_TWI_MSTRSTAT_MPROG_YES          (_ADI_MSK(0x00000001,uint16_t))  /* MPROG: Master Transfer in Progress */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRADDR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRADDR_ADDR                0                               /* Master Mode Address */
-#define BITM_TWI_MSTRADDR_ADDR               (_ADI_MSK(0x0000007F,uint16_t))  /* Master Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_ISTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_ISTAT_SCLI                  15                               /* Serial Clock Interrupt */
-#define BITP_TWI_ISTAT_SDAI                  14                               /* Serial Data Interrupt */
-#define BITP_TWI_ISTAT_RXSERV                 7                               /* Rx FIFO Service */
-#define BITP_TWI_ISTAT_TXSERV                 6                               /* Tx FIFO Service */
-#define BITP_TWI_ISTAT_MERR                   5                               /* Master Transfer Error */
-#define BITP_TWI_ISTAT_MCOMP                  4                               /* Master Transfer Complete */
-#define BITP_TWI_ISTAT_SOVF                   3                               /* Slave Overflow */
-#define BITP_TWI_ISTAT_SERR                   2                               /* Slave Transfer Error */
-#define BITP_TWI_ISTAT_SCOMP                  1                               /* Slave Transfer Complete */
-#define BITP_TWI_ISTAT_SINIT                  0                               /* Slave Transfer Initiated */
-
-#define BITM_TWI_ISTAT_SCLI                  (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: No Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_YES              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SDAI                  (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: No Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_YES              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_RXSERV                (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service */
-#define ENUM_TWI_ISTAT_RXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_RXSERV_YES            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_TXSERV                (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service */
-#define ENUM_TWI_ISTAT_TXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_TXSERV_YES            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MERR                  (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error */
-#define ENUM_TWI_ISTAT_MERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: No Interrupt */
-#define ENUM_TWI_ISTAT_MERR_YES              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MCOMP                 (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete */
-#define ENUM_TWI_ISTAT_MCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_MCOMP_YES             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SOVF                  (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow */
-#define ENUM_TWI_ISTAT_SOVF_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: No Interrupt */
-#define ENUM_TWI_ISTAT_SOVF_YES              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SERR                  (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error */
-#define ENUM_TWI_ISTAT_SERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: No Interrupt */
-#define ENUM_TWI_ISTAT_SERR_YES              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SCOMP                 (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete */
-#define ENUM_TWI_ISTAT_SCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_SCOMP_YES             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SINIT                 (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated */
-#define ENUM_TWI_ISTAT_SINIT_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: No Interrupt */
-#define ENUM_TWI_ISTAT_SINIT_YES             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Interrupt Detected */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_IMSK_SCLI                   15                               /* Serial Clock Interrupt Mask */
-#define BITP_TWI_IMSK_SDAI                   14                               /* Serial Data Interrupt Mask */
-#define BITP_TWI_IMSK_RXSERV                  7                               /* Rx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_TXSERV                  6                               /* Tx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_MERR                    5                               /* Master Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_MCOMP                   4                               /* Master Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SOVF                    3                               /* Slave Overflow Interrupt Mask */
-#define BITP_TWI_IMSK_SERR                    2                               /* Slave Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_SCOMP                   1                               /* Slave Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SINIT                   0                               /* Slave Transfer Initiated Interrupt Mask */
-
-#define BITM_TWI_IMSK_SCLI                   (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt Mask */
-#define ENUM_TWI_IMSK_SCLI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCLI_UMSK              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SDAI                   (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt Mask */
-#define ENUM_TWI_IMSK_SDAI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SDAI_UMSK              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_RXSERV                 (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_RXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_RXSERV_UMSK            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_TXSERV                 (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_TXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_TXSERV_UMSK            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MERR                   (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_MERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MERR_UMSK              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MCOMP                  (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_MCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MCOMP_UMSK             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SOVF                   (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow Interrupt Mask */
-#define ENUM_TWI_IMSK_SOVF_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SOVF_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SERR                   (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_SERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SERR_UMSK              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SCOMP                  (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_SCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCOMP_UMSK             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SINIT                  (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated Interrupt Mask */
-#define ENUM_TWI_IMSK_SINIT_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SINIT_UMSK             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Unmask (Enable) Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOCTL_RXILEN               3                               /* Rx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_TXILEN               2                               /* Tx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_RXFLUSH              1                               /* Rx Buffer Flush */
-#define BITP_TWI_FIFOCTL_TXFLUSH              0                               /* Tx Buffer Flush */
-
-#define BITM_TWI_FIFOCTL_RXILEN              (_ADI_MSK(0x00000008,uint16_t))  /* Rx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_RXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* RXILEN: RXSERVI on 1 or 2 Bytes in FIFO */
-#define ENUM_TWI_FIFOCTL_RXTWOBYTE           (_ADI_MSK(0x00000008,uint16_t))  /* RXILEN: RXSERVI on 2 Bytes in FIFO */
-
-#define BITM_TWI_FIFOCTL_TXILEN              (_ADI_MSK(0x00000004,uint16_t))  /* Tx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_TXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* TXILEN: TXSERVI on 1 Byte of FIFO Empty */
-#define ENUM_TWI_FIFOCTL_TXTWOBYTE           (_ADI_MSK(0x00000004,uint16_t))  /* TXILEN: TXSERVI on 2 Bytes of FIFO Empty */
-
-#define BITM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* Rx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_RXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* RXFLUSH: Normal Operation of Rx Buffer */
-#define ENUM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* RXFLUSH: Flush Rx Buffer */
-
-#define BITM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* Tx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_TXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* TXFLUSH: Normal Operation of Tx Buffer */
-#define ENUM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* TXFLUSH: Flush Tx Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOSTAT_RXSTAT              2                               /* Rx FIFO Status */
-#define BITP_TWI_FIFOSTAT_TXSTAT              0                               /* Tx FIFO Status */
-#define BITM_TWI_FIFOSTAT_RXSTAT             (_ADI_MSK(0x0000000C,uint16_t))  /* Rx FIFO Status */
-#define BITM_TWI_FIFOSTAT_TXSTAT             (_ADI_MSK(0x00000003,uint16_t))  /* Tx FIFO Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_TXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_TXDATA8_VALUE                0                               /* Tx Data 8-Bit Value */
-#define BITM_TWI_TXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Tx Data 8-Bit Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_RXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_RXDATA8_VALUE                0                               /* Rx Data 8-Bit Value */
-#define BITM_TWI_RXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Rx Data 8-Bit Value */
-
-/* ==================================================
-        UART Registers
-   ================================================== */
-
-/* =========================
-        UART0
-   ========================= */
-#define REG_UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
-#define REG_UART0_CTL                   0xFFC02004         /* UART0 Control Register */
-#define REG_UART0_STAT                  0xFFC02008         /* UART0 Status Register */
-#define REG_UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
-#define REG_UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
-#define REG_UART0_IMSK                  0xFFC02014         /* UART0 Interrupt Mask Register */
-#define REG_UART0_IMSK_SET              0xFFC02018         /* UART0 Interrupt Mask Set Register */
-#define REG_UART0_IMSK_CLR              0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
-#define REG_UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
-#define REG_UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
-#define REG_UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
-#define REG_UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
-#define REG_UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
-#define REG_UART0_TXCNT                 0xFFC02034         /* UART0 Transmit Counter Register */
-#define REG_UART0_RXCNT                 0xFFC02038         /* UART0 Receive Counter Register */
-
-/* =========================
-        UART1
-   ========================= */
-#define REG_UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
-#define REG_UART1_CTL                   0xFFC02404         /* UART1 Control Register */
-#define REG_UART1_STAT                  0xFFC02408         /* UART1 Status Register */
-#define REG_UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
-#define REG_UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
-#define REG_UART1_IMSK                  0xFFC02414         /* UART1 Interrupt Mask Register */
-#define REG_UART1_IMSK_SET              0xFFC02418         /* UART1 Interrupt Mask Set Register */
-#define REG_UART1_IMSK_CLR              0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
-#define REG_UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
-#define REG_UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
-#define REG_UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
-#define REG_UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
-#define REG_UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
-#define REG_UART1_TXCNT                 0xFFC02434         /* UART1 Transmit Counter Register */
-#define REG_UART1_RXCNT                 0xFFC02438         /* UART1 Receive Counter Register */
-
-/* =========================
-        UART
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_REVID_MAJOR                 4                               /* Major Version */
-#define BITP_UART_REVID_REV                   0                               /* Incremental Version */
-#define BITM_UART_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version */
-#define BITM_UART_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CTL_RFRT                   30                               /* Receive FIFO RTS Threshold */
-#define BITP_UART_CTL_RFIT                   29                               /* Receive FIFO IRQ Threshold */
-#define BITP_UART_CTL_ACTS                   28                               /* Automatic CTS */
-#define BITP_UART_CTL_ARTS                   27                               /* Automatic RTS */
-#define BITP_UART_CTL_XOFF                   26                               /* Transmitter off */
-#define BITP_UART_CTL_MRTS                   25                               /* Manual Request to Send */
-#define BITP_UART_CTL_TPOLC                  24                               /* IrDA TX Polarity Change */
-#define BITP_UART_CTL_RPOLC                  23                               /* IrDA RX Polarity Change */
-#define BITP_UART_CTL_FCPOL                  22                               /* Flow Control Pin Polarity */
-#define BITP_UART_CTL_SB                     19                               /* Set Break */
-#define BITP_UART_CTL_FFE                    18                               /* Force Framing Error on Transmit */
-#define BITP_UART_CTL_FPE                    17                               /* Force Parity Error on Transmit */
-#define BITP_UART_CTL_STP                    16                               /* Sticky Parity */
-#define BITP_UART_CTL_EPS                    15                               /* Even Parity Select */
-#define BITP_UART_CTL_PEN                    14                               /* Parity Enable */
-#define BITP_UART_CTL_STBH                   13                               /* Stop Bits (Half Bit Time) */
-#define BITP_UART_CTL_STB                    12                               /* Stop Bits */
-#define BITP_UART_CTL_WLS                     8                               /* Word Length Select */
-#define BITP_UART_CTL_MOD                     4                               /* Mode of Operation */
-#define BITP_UART_CTL_LOOP_EN                 1                               /* Loopback Enable */
-#define BITP_UART_CTL_EN                      0                               /* Enable UART */
-
-#define BITM_UART_CTL_RFRT                   (_ADI_MSK(0x40000000,uint32_t))  /* Receive FIFO RTS Threshold */
-#define ENUM_UART_CTL_RX_RTS_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 4; assert if <= 4 */
-#define ENUM_UART_CTL_RX_RTS_TH7             (_ADI_MSK(0x40000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 7; assert if <= 7 */
-
-#define BITM_UART_CTL_RFIT                   (_ADI_MSK(0x20000000,uint32_t))  /* Receive FIFO IRQ Threshold */
-#define ENUM_UART_CTL_RX_IRQ_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 4 */
-#define ENUM_UART_CTL_RX_IRQ_TH7             (_ADI_MSK(0x20000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 7 */
-
-#define BITM_UART_CTL_ACTS                   (_ADI_MSK(0x10000000,uint32_t))  /* Automatic CTS */
-#define ENUM_UART_CTL_CTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ACTS: Disable TX handshaking protocol */
-#define ENUM_UART_CTL_CTS_AUTO               (_ADI_MSK(0x10000000,uint32_t))  /* ACTS: Enable TX handshaking protocol */
-
-#define BITM_UART_CTL_ARTS                   (_ADI_MSK(0x08000000,uint32_t))  /* Automatic RTS */
-#define ENUM_UART_CTL_RTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ARTS: Disable RX handshaking protocol. */
-#define ENUM_UART_CTL_RTS_AUTO               (_ADI_MSK(0x08000000,uint32_t))  /* ARTS: Enable RX handshaking protocol. */
-
-#define BITM_UART_CTL_XOFF                   (_ADI_MSK(0x04000000,uint32_t))  /* Transmitter off */
-#define ENUM_UART_CTL_TX_ON                  (_ADI_MSK(0x00000000,uint32_t))  /* XOFF: Transmission ON, if ACTS=0 */
-#define ENUM_UART_CTL_TX_OFF                 (_ADI_MSK(0x04000000,uint32_t))  /* XOFF: Transmission OFF, if ACTS=0 */
-
-#define BITM_UART_CTL_MRTS                   (_ADI_MSK(0x02000000,uint32_t))  /* Manual Request to Send */
-#define ENUM_UART_CTL_RTS_DEASSERT           (_ADI_MSK(0x00000000,uint32_t))  /* MRTS: De-assert RTS pin when ARTS=0 */
-#define ENUM_UART_CTL_RTS_ASSERT             (_ADI_MSK(0x02000000,uint32_t))  /* MRTS: Assert RTS pin  when ARTS=0 */
-
-#define BITM_UART_CTL_TPOLC                  (_ADI_MSK(0x01000000,uint32_t))  /* IrDA TX Polarity Change */
-#define ENUM_UART_CTL_TPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* TPOLC: Active-low TX polarity setting */
-#define ENUM_UART_CTL_TPOLC_HI               (_ADI_MSK(0x01000000,uint32_t))  /* TPOLC: Active-high TX polarity setting */
-
-#define BITM_UART_CTL_RPOLC                  (_ADI_MSK(0x00800000,uint32_t))  /* IrDA RX Polarity Change */
-#define ENUM_UART_CTL_RPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RPOLC: Active-low RX polarity setting */
-#define ENUM_UART_CTL_RPOLC_HI               (_ADI_MSK(0x00800000,uint32_t))  /* RPOLC: Active-high RX polarity setting */
-
-#define BITM_UART_CTL_FCPOL                  (_ADI_MSK(0x00400000,uint32_t))  /* Flow Control Pin Polarity */
-#define ENUM_UART_CTL_FCPOL_LO               (_ADI_MSK(0x00000000,uint32_t))  /* FCPOL: Active low CTS/RTS */
-#define ENUM_UART_CTL_FCPOL_HI               (_ADI_MSK(0x00400000,uint32_t))  /* FCPOL: Active high CTS/RTS */
-
-#define BITM_UART_CTL_SB                     (_ADI_MSK(0x00080000,uint32_t))  /* Set Break */
-#define ENUM_UART_CTL_NORM_BREAK             (_ADI_MSK(0x00000000,uint32_t))  /* SB: No force */
-#define ENUM_UART_CTL_FORCE_BREAK            (_ADI_MSK(0x00080000,uint32_t))  /* SB: Force TX pin to 0 */
-
-#define BITM_UART_CTL_FFE                    (_ADI_MSK(0x00040000,uint32_t))  /* Force Framing Error on Transmit */
-#define ENUM_UART_CTL_NORM_FRM_ERR           (_ADI_MSK(0x00000000,uint32_t))  /* FFE: Normal operation */
-#define ENUM_UART_CTL_FORCE_FRM_ERR          (_ADI_MSK(0x00040000,uint32_t))  /* FFE: Force error */
-
-#define BITM_UART_CTL_FPE                    (_ADI_MSK(0x00020000,uint32_t))  /* Force Parity Error on Transmit */
-#define ENUM_UART_CTL_NORM_PARITY_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FPE: Normal operation */
-#define ENUM_UART_CTL_FORCE_PARITY_ERR       (_ADI_MSK(0x00020000,uint32_t))  /* FPE: Force parity error */
-
-#define BITM_UART_CTL_STP                    (_ADI_MSK(0x00010000,uint32_t))  /* Sticky Parity */
-#define ENUM_UART_CTL_NORM_PARITY            (_ADI_MSK(0x00000000,uint32_t))  /* STP: No Forced Parity */
-#define ENUM_UART_CTL_STICKY_PARITY          (_ADI_MSK(0x00010000,uint32_t))  /* STP: Force (Stick) Parity to Defined Value (if PEN=1) */
-
-#define BITM_UART_CTL_EPS                    (_ADI_MSK(0x00008000,uint32_t))  /* Even Parity Select */
-#define ENUM_UART_CTL_ODD_PARITY             (_ADI_MSK(0x00000000,uint32_t))  /* EPS: Odd parity */
-#define ENUM_UART_CTL_EVEN_PARITY            (_ADI_MSK(0x00008000,uint32_t))  /* EPS: Even parity */
-
-#define BITM_UART_CTL_PEN                    (_ADI_MSK(0x00004000,uint32_t))  /* Parity Enable */
-#define ENUM_UART_CTL_PARITY_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* PEN: Disable */
-#define ENUM_UART_CTL_PARITY_EN              (_ADI_MSK(0x00004000,uint32_t))  /* PEN: Enable parity transmit and check */
-
-#define BITM_UART_CTL_STBH                   (_ADI_MSK(0x00002000,uint32_t))  /* Stop Bits (Half Bit Time) */
-#define ENUM_UART_CTL_NO_EXTRA_STBH          (_ADI_MSK(0x00000000,uint32_t))  /* STBH: 0 half-bit-time stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STBH           (_ADI_MSK(0x00002000,uint32_t))  /* STBH: 1 half-bit-time stop bit */
-
-#define BITM_UART_CTL_STB                    (_ADI_MSK(0x00001000,uint32_t))  /* Stop Bits */
-#define ENUM_UART_CTL_NO_EXTRA_STB           (_ADI_MSK(0x00000000,uint32_t))  /* STB: 1 stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STB            (_ADI_MSK(0x00001000,uint32_t))  /* STB: 2 stop bits */
-
-#define BITM_UART_CTL_WLS                    (_ADI_MSK(0x00000300,uint32_t))  /* Word Length Select */
-#define ENUM_UART_CTL_WL5BITS                (_ADI_MSK(0x00000000,uint32_t))  /* WLS: 5-bit Word */
-#define ENUM_UART_CTL_WL6BITS                (_ADI_MSK(0x00000100,uint32_t))  /* WLS: 6-bit Word */
-#define ENUM_UART_CTL_WL7BITS                (_ADI_MSK(0x00000200,uint32_t))  /* WLS: 7-bit Word */
-#define ENUM_UART_CTL_WL8BITS                (_ADI_MSK(0x00000300,uint32_t))  /* WLS: 8-bit Word */
-
-#define BITM_UART_CTL_MOD                    (_ADI_MSK(0x00000030,uint32_t))  /* Mode of Operation */
-#define ENUM_UART_CTL_UART_MODE              (_ADI_MSK(0x00000000,uint32_t))  /* MOD: UART Mode */
-#define ENUM_UART_CTL_MDB_MODE               (_ADI_MSK(0x00000010,uint32_t))  /* MOD: MDB Mode */
-#define ENUM_UART_CTL_IRDA_MODE              (_ADI_MSK(0x00000020,uint32_t))  /* MOD: IrDA SIR Mode */
-
-#define BITM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* Loopback Enable */
-#define ENUM_UART_CTL_LOOP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* LOOP_EN: Disable */
-#define ENUM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* LOOP_EN: Enable */
-
-#define BITM_UART_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable UART */
-#define ENUM_UART_CTL_CLK_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_UART_CTL_CLK_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_STAT_RFCS                  17                               /* Receive FIFO Count Status */
-#define BITP_UART_STAT_CTS                   16                               /* Clear to Send */
-#define BITP_UART_STAT_SCTS                  12                               /* Sticky CTS */
-#define BITP_UART_STAT_RO                    11                               /* Reception On-going */
-#define BITP_UART_STAT_ADDR                  10                               /* Address Bit Status */
-#define BITP_UART_STAT_ASTKY                  9                               /* Address Sticky */
-#define BITP_UART_STAT_TFI                    8                               /* Transmission Finished Indicator */
-#define BITP_UART_STAT_TEMT                   7                               /* TSR and THR Empty */
-#define BITP_UART_STAT_THRE                   5                               /* Transmit Hold Register Empty */
-#define BITP_UART_STAT_BI                     4                               /* Break Indicator */
-#define BITP_UART_STAT_FE                     3                               /* Framing Error */
-#define BITP_UART_STAT_PE                     2                               /* Parity Error */
-#define BITP_UART_STAT_OE                     1                               /* Overrun Error */
-#define BITP_UART_STAT_DR                     0                               /* Data Ready */
-
-#define BITM_UART_STAT_RFCS                  (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Count Status */
-#define ENUM_UART_STAT_RFCS_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RFCS: RX FIFO has less than 4 (7) entries when RFIT=0 (1) */
-#define ENUM_UART_STAT_RFCS_HI               (_ADI_MSK(0x00020000,uint32_t))  /* RFCS: RX FIFO has at least 4 (7) entries when RFIT=0 (1) */
-
-#define BITM_UART_STAT_CTS                   (_ADI_MSK(0x00010000,uint32_t))  /* Clear to Send */
-#define ENUM_UART_STAT_CTS_LO                (_ADI_MSK(0x00000000,uint32_t))  /* CTS: Not clear to send (External device not ready to receive) */
-#define ENUM_UART_STAT_CTS_HI                (_ADI_MSK(0x00010000,uint32_t))  /* CTS: Clear to send (External device ready to receive) */
-
-#define BITM_UART_STAT_SCTS                  (_ADI_MSK(0x00001000,uint32_t))  /* Sticky CTS */
-#define ENUM_UART_STAT_CTS_LO_STKY           (_ADI_MSK(0x00000000,uint32_t))  /* SCTS: CTS has not transitioned from low to high */
-#define ENUM_UART_STAT_CTS_HI_STKY           (_ADI_MSK(0x00001000,uint32_t))  /* SCTS: CTS has transitioned from low to high */
-
-#define BITM_UART_STAT_RO                    (_ADI_MSK(0x00000800,uint32_t))  /* Reception On-going */
-#define ENUM_UART_STAT_NO_RX_PROGRESS        (_ADI_MSK(0x00000000,uint32_t))  /* RO: No data reception in progress */
-#define ENUM_UART_STAT_RX_PROGRESS           (_ADI_MSK(0x00000800,uint32_t))  /* RO: Data reception in progress */
-
-#define BITM_UART_STAT_ADDR                  (_ADI_MSK(0x00000400,uint32_t))  /* Address Bit Status */
-#define ENUM_UART_STAT_ADDR_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ADDR: Address bit is low */
-#define ENUM_UART_STAT_ADDR_HI               (_ADI_MSK(0x00000400,uint32_t))  /* ADDR: Address bit is high */
-
-#define BITM_UART_STAT_ASTKY                 (_ADI_MSK(0x00000200,uint32_t))  /* Address Sticky */
-#define ENUM_UART_STAT_ADDR_LO_STKY          (_ADI_MSK(0x00000000,uint32_t))  /* ASTKY: ADDR bit has not been set */
-#define ENUM_UART_STAT_ADDR_HI_STKY          (_ADI_MSK(0x00000200,uint32_t))  /* ASTKY: ADDR bit has been set */
-
-#define BITM_UART_STAT_TFI                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmission Finished Indicator */
-#define ENUM_UART_STAT_TX_NOT_DONE           (_ADI_MSK(0x00000000,uint32_t))  /* TFI: TEMT did not transition from 0 to 1 */
-#define ENUM_UART_STAT_TX_DONE               (_ADI_MSK(0x00000100,uint32_t))  /* TFI: TEMT transition from 0 to 1 */
-
-#define BITM_UART_STAT_TEMT                  (_ADI_MSK(0x00000080,uint32_t))  /* TSR and THR Empty */
-#define ENUM_UART_STAT_TX_NOT_EMPTY          (_ADI_MSK(0x00000000,uint32_t))  /* TEMT: Not empty TSR/THR */
-#define ENUM_UART_STAT_TX_EMPTY              (_ADI_MSK(0x00000080,uint32_t))  /* TEMT: TSR/THR Empty */
-
-#define BITM_UART_STAT_THRE                  (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Hold Register Empty */
-#define ENUM_UART_STAT_THR_NOT_EMPTY         (_ADI_MSK(0x00000000,uint32_t))  /* THRE: Not empty THR/TAIP */
-#define ENUM_UART_STAT_THR_EMPTY             (_ADI_MSK(0x00000020,uint32_t))  /* THRE: Empty THR/TAIP */
-
-#define BITM_UART_STAT_BI                    (_ADI_MSK(0x00000010,uint32_t))  /* Break Indicator */
-#define ENUM_UART_STAT_NO_BREAK_INT          (_ADI_MSK(0x00000000,uint32_t))  /* BI: No break interrupt */
-#define ENUM_UART_STAT_BREAK_INT             (_ADI_MSK(0x00000010,uint32_t))  /* BI: Break interrupt */
-
-#define BITM_UART_STAT_FE                    (_ADI_MSK(0x00000008,uint32_t))  /* Framing Error */
-#define ENUM_UART_STAT_NO_FRAMING_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FE: No error */
-#define ENUM_UART_STAT_FRAMING_ERR           (_ADI_MSK(0x00000008,uint32_t))  /* FE: Invalid stop bit error */
-
-#define BITM_UART_STAT_PE                    (_ADI_MSK(0x00000004,uint32_t))  /* Parity Error */
-#define ENUM_UART_STAT_NO_PARITY_ERR         (_ADI_MSK(0x00000000,uint32_t))  /* PE: No parity error */
-#define ENUM_UART_STAT_PARITY_ERR            (_ADI_MSK(0x00000004,uint32_t))  /* PE: Parity error */
-
-#define BITM_UART_STAT_OE                    (_ADI_MSK(0x00000002,uint32_t))  /* Overrun Error */
-#define ENUM_UART_STAT_NO_OVR_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* OE: No overrun */
-#define ENUM_UART_STAT_OVR_ERR               (_ADI_MSK(0x00000002,uint32_t))  /* OE: Overrun error */
-
-#define BITM_UART_STAT_DR                    (_ADI_MSK(0x00000001,uint32_t))  /* Data Ready */
-#define ENUM_UART_STAT_NO_DATA               (_ADI_MSK(0x00000000,uint32_t))  /* DR: No new data */
-#define ENUM_UART_STAT_NEW_DATA              (_ADI_MSK(0x00000001,uint32_t))  /* DR: New data in RBR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_SCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_SCR_VALUE                   0                               /* Stored 8-bit Data */
-#define BITM_UART_SCR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Stored 8-bit Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CLK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CLK_EDBO                   31                               /* Enable Divide By One */
-#define BITP_UART_CLK_DIV                     0                               /* Divisor */
-
-#define BITM_UART_CLK_EDBO                   (_ADI_MSK(0x80000000,uint32_t))  /* Enable Divide By One */
-#define ENUM_UART_CLK_DIS_DIV_BY_ONE         (_ADI_MSK(0x00000000,uint32_t))  /* EDBO: Bit clock prescaler = 16 */
-#define ENUM_UART_CLK_EN_DIV_BY_ONE          (_ADI_MSK(0x80000000,uint32_t))  /* EDBO: Bit clock prescaler = 1 */
-#define BITM_UART_CLK_DIV                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_ETXS                   9                               /* Enable TX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ERXS                   8                               /* Enable RX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_EAWI                   7                               /* Enable Address Word Interrupt Mask Status */
-#define BITP_UART_IMSK_ERFCI                  6                               /* Enable Receive FIFO Count Interrupt Mask Status */
-#define BITP_UART_IMSK_ETFI                   5                               /* Enable Transmission Finished Interrupt Mask Status */
-#define BITP_UART_IMSK_EDTPTI                 4                               /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define BITP_UART_IMSK_EDSSI                  3                               /* Enable Modem Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ELSI                   2                               /* Enable Line Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ETBEI                  1                               /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define BITP_UART_IMSK_ERBFI                  0                               /* Enable Receive Buffer Full Interrupt Mask Status */
-
-#define BITM_UART_IMSK_ETXS                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Status */
-#define ENUM_UART_ETXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETXS: Interrupt is masked */
-#define ENUM_UART_ETXS_HI                    (_ADI_MSK(0x00000200,uint32_t))  /* ETXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERXS                  (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Status */
-#define ENUM_UART_ERXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ERXS: Interrupt is masked */
-#define ENUM_UART_ERXS_HI                    (_ADI_MSK(0x00000100,uint32_t))  /* ERXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EAWI                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Status */
-#define ENUM_UART_EAWI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* EAWI: Interrupt is masked */
-#define ENUM_UART_EAWI_HI                    (_ADI_MSK(0x00000080,uint32_t))  /* EAWI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERFCI                 (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Status */
-#define ENUM_UART_ERFCI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERFCI: Interrupt is masked */
-#define ENUM_UART_ERFCI_HI                   (_ADI_MSK(0x00000040,uint32_t))  /* ERFCI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETFI                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Status */
-#define ENUM_UART_ETFI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETFI: Interrupt is masked */
-#define ENUM_UART_ETFI_HI                    (_ADI_MSK(0x00000020,uint32_t))  /* ETFI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDTPTI                (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define ENUM_UART_EDTPTI_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* EDTPTI: Interrupt is masked */
-#define ENUM_UART_EDTPTI_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* EDTPTI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDSSI                 (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Status */
-#define ENUM_UART_EDSSI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* EDSSI: Interrupt is masked */
-#define ENUM_UART_EDSSI_HI                   (_ADI_MSK(0x00000008,uint32_t))  /* EDSSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ELSI                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Status */
-#define ENUM_UART_ELSI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ELSI: Interrupt is masked */
-#define ENUM_UART_ELSI_HI                    (_ADI_MSK(0x00000004,uint32_t))  /* ELSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETBEI                 (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define ENUM_UART_ETBEI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ETBEI: Interrupt is masked */
-#define ENUM_UART_ETBEI_HI                   (_ADI_MSK(0x00000002,uint32_t))  /* ETBEI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERBFI                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Status */
-#define ENUM_UART_ERBFI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERBFI: Interrupt is masked */
-#define ENUM_UART_ERBFI_HI                   (_ADI_MSK(0x00000001,uint32_t))  /* ERBFI: Interrupt is unmasked */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_SET_ETXS               9                               /* Enable TX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERXS               8                               /* Enable RX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EAWI               7                               /* Enable Address Word Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDSSI              3                               /* Enable Modem Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ELSI               2                               /* Enable Line Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* The fields and enumerations for UART_IMSK_SET are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_SET_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_CLR_ETXS               9                               /* Enable TX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERXS               8                               /* Enable RX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EAWI               7                               /* Enable Address Word Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDSSI              3                               /* Enable Modem Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ELSI               2                               /* Enable Line Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* The fields and enumerations for UART_IMSK_CLR are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_CLR_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RBR_VALUE                   0                               /* 8-bit data */
-#define BITM_UART_RBR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_THR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_THR_VALUE                   0                               /* 8 bit data */
-#define BITM_UART_THR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8 bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TAIP                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TAIP_VALUE                  0                               /* 8-bit data */
-#define BITM_UART_TAIP_VALUE                 (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TSR_VALUE                   0                               /* Contents of TSR */
-#define BITM_UART_TSR_VALUE                  (_ADI_MSK(0x000007FF,uint32_t))  /* Contents of TSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RSR_VALUE                   0                               /* Contents of RSR */
-#define BITM_UART_RSR_VALUE                  (_ADI_MSK(0x000003FF,uint32_t))  /* Contents of RSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_TXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_RXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ==================================================
-        General Purpose Input/Output Registers
-   ================================================== */
-
-/* =========================
-        PORTA
-   ========================= */
-#define REG_PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
-#define REG_PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
-#define REG_PORTA_FER_CLR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
-#define REG_PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
-#define REG_PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
-#define REG_PORTA_DATA_CLR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
-#define REG_PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
-#define REG_PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
-#define REG_PORTA_DIR_CLR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
-#define REG_PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
-#define REG_PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
-#define REG_PORTA_INEN_CLR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
-#define REG_PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
-#define REG_PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
-#define REG_PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Polarity Invert Register */
-#define REG_PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Polarity Invert Set Register */
-#define REG_PORTA_POL_CLR               0xFFC03040         /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
-#define REG_PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
-
-/* =========================
-        PORTB
-   ========================= */
-#define REG_PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
-#define REG_PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
-#define REG_PORTB_FER_CLR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
-#define REG_PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
-#define REG_PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
-#define REG_PORTB_DATA_CLR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
-#define REG_PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
-#define REG_PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
-#define REG_PORTB_DIR_CLR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
-#define REG_PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
-#define REG_PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
-#define REG_PORTB_INEN_CLR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
-#define REG_PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
-#define REG_PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
-#define REG_PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Polarity Invert Register */
-#define REG_PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Polarity Invert Set Register */
-#define REG_PORTB_POL_CLR               0xFFC030C0         /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
-#define REG_PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
-
-/* =========================
-        PORTC
-   ========================= */
-#define REG_PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
-#define REG_PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
-#define REG_PORTC_FER_CLR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
-#define REG_PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
-#define REG_PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
-#define REG_PORTC_DATA_CLR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
-#define REG_PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
-#define REG_PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
-#define REG_PORTC_DIR_CLR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
-#define REG_PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
-#define REG_PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
-#define REG_PORTC_INEN_CLR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
-#define REG_PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
-#define REG_PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
-#define REG_PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Polarity Invert Register */
-#define REG_PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Polarity Invert Set Register */
-#define REG_PORTC_POL_CLR               0xFFC03140         /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
-#define REG_PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
-
-/* =========================
-        PORTD
-   ========================= */
-#define REG_PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
-#define REG_PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
-#define REG_PORTD_FER_CLR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
-#define REG_PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
-#define REG_PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
-#define REG_PORTD_DATA_CLR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
-#define REG_PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
-#define REG_PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
-#define REG_PORTD_DIR_CLR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
-#define REG_PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
-#define REG_PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
-#define REG_PORTD_INEN_CLR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
-#define REG_PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
-#define REG_PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
-#define REG_PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Polarity Invert Register */
-#define REG_PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Polarity Invert Set Register */
-#define REG_PORTD_POL_CLR               0xFFC031C0         /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
-#define REG_PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
-
-/* =========================
-        PORTE
-   ========================= */
-#define REG_PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
-#define REG_PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
-#define REG_PORTE_FER_CLR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
-#define REG_PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
-#define REG_PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
-#define REG_PORTE_DATA_CLR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
-#define REG_PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
-#define REG_PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
-#define REG_PORTE_DIR_CLR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
-#define REG_PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
-#define REG_PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
-#define REG_PORTE_INEN_CLR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
-#define REG_PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
-#define REG_PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
-#define REG_PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Polarity Invert Register */
-#define REG_PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Polarity Invert Set Register */
-#define REG_PORTE_POL_CLR               0xFFC03240         /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
-#define REG_PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
-
-/* =========================
-        PORTF
-   ========================= */
-#define REG_PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
-#define REG_PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
-#define REG_PORTF_FER_CLR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
-#define REG_PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
-#define REG_PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
-#define REG_PORTF_DATA_CLR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
-#define REG_PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
-#define REG_PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
-#define REG_PORTF_DIR_CLR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
-#define REG_PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
-#define REG_PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
-#define REG_PORTF_INEN_CLR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
-#define REG_PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
-#define REG_PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
-#define REG_PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Polarity Invert Register */
-#define REG_PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Polarity Invert Set Register */
-#define REG_PORTF_POL_CLR               0xFFC032C0         /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
-#define REG_PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
-
-/* =========================
-        PORTG
-   ========================= */
-#define REG_PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
-#define REG_PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
-#define REG_PORTG_FER_CLR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
-#define REG_PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
-#define REG_PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
-#define REG_PORTG_DATA_CLR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
-#define REG_PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
-#define REG_PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
-#define REG_PORTG_DIR_CLR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
-#define REG_PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
-#define REG_PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
-#define REG_PORTG_INEN_CLR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
-#define REG_PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
-#define REG_PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
-#define REG_PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Polarity Invert Register */
-#define REG_PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Polarity Invert Set Register */
-#define REG_PORTG_POL_CLR               0xFFC03340         /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
-#define REG_PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
-
-/* =========================
-        PORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_PX15                   15                               /* Port x Bit 15 Mode */
-#define BITP_PORT_FER_PX14                   14                               /* Port x Bit 14 Mode */
-#define BITP_PORT_FER_PX13                   13                               /* Port x Bit 13 Mode */
-#define BITP_PORT_FER_PX12                   12                               /* Port x Bit 12 Mode */
-#define BITP_PORT_FER_PX11                   11                               /* Port x Bit 11 Mode */
-#define BITP_PORT_FER_PX10                   10                               /* Port x Bit 10 Mode */
-#define BITP_PORT_FER_PX9                     9                               /* Port x Bit 9 Mode */
-#define BITP_PORT_FER_PX8                     8                               /* Port x Bit 8 Mode */
-#define BITP_PORT_FER_PX7                     7                               /* Port x Bit 7 Mode */
-#define BITP_PORT_FER_PX6                     6                               /* Port x Bit 6 Mode */
-#define BITP_PORT_FER_PX5                     5                               /* Port x Bit 5 Mode */
-#define BITP_PORT_FER_PX4                     4                               /* Port x Bit 4 Mode */
-#define BITP_PORT_FER_PX3                     3                               /* Port x Bit 3 Mode */
-#define BITP_PORT_FER_PX2                     2                               /* Port x Bit 2 Mode */
-#define BITP_PORT_FER_PX1                     1                               /* Port x Bit 1 Mode */
-#define BITP_PORT_FER_PX0                     0                               /* Port x Bit 0 Mode */
-#define BITM_PORT_FER_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode */
-#define BITM_PORT_FER_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode */
-#define BITM_PORT_FER_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode */
-#define BITM_PORT_FER_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode */
-#define BITM_PORT_FER_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode */
-#define BITM_PORT_FER_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode */
-#define BITM_PORT_FER_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode */
-#define BITM_PORT_FER_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode */
-#define BITM_PORT_FER_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode */
-#define BITM_PORT_FER_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode */
-#define BITM_PORT_FER_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode */
-#define BITM_PORT_FER_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode */
-#define BITM_PORT_FER_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode */
-#define BITM_PORT_FER_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode */
-#define BITM_PORT_FER_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode */
-#define BITM_PORT_FER_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_SET_PX15               15                               /* Port x Bit 15 Mode Set */
-#define BITP_PORT_FER_SET_PX14               14                               /* Port x Bit 14 Mode Set */
-#define BITP_PORT_FER_SET_PX13               13                               /* Port x Bit 13 Mode Set */
-#define BITP_PORT_FER_SET_PX12               12                               /* Port x Bit 12 Mode Set */
-#define BITP_PORT_FER_SET_PX11               11                               /* Port x Bit 11 Mode Set */
-#define BITP_PORT_FER_SET_PX10               10                               /* Port x Bit 10 Mode Set */
-#define BITP_PORT_FER_SET_PX9                 9                               /* Port x Bit 9 Mode Set */
-#define BITP_PORT_FER_SET_PX8                 8                               /* Port x Bit 8 Mode Set */
-#define BITP_PORT_FER_SET_PX7                 7                               /* Port x Bit 7 Mode Set */
-#define BITP_PORT_FER_SET_PX6                 6                               /* Port x Bit 6 Mode Set */
-#define BITP_PORT_FER_SET_PX5                 5                               /* Port x Bit 5 Mode Set */
-#define BITP_PORT_FER_SET_PX4                 4                               /* Port x Bit 4 Mode Set */
-#define BITP_PORT_FER_SET_PX3                 3                               /* Port x Bit 3 Mode Set */
-#define BITP_PORT_FER_SET_PX2                 2                               /* Port x Bit 2 Mode Set */
-#define BITP_PORT_FER_SET_PX1                 1                               /* Port x Bit 1 Mode Set */
-#define BITP_PORT_FER_SET_PX0                 0                               /* Port x Bit 0 Mode Set */
-#define BITM_PORT_FER_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Set */
-#define BITM_PORT_FER_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Set */
-#define BITM_PORT_FER_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Set */
-#define BITM_PORT_FER_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Set */
-#define BITM_PORT_FER_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Set */
-#define BITM_PORT_FER_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Set */
-#define BITM_PORT_FER_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Set */
-#define BITM_PORT_FER_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Set */
-#define BITM_PORT_FER_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Set */
-#define BITM_PORT_FER_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Set */
-#define BITM_PORT_FER_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Set */
-#define BITM_PORT_FER_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Set */
-#define BITM_PORT_FER_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Set */
-#define BITM_PORT_FER_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Set */
-#define BITM_PORT_FER_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Set */
-#define BITM_PORT_FER_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_CLR_PX15               15                               /* Port x Bit 15 Mode Clear */
-#define BITP_PORT_FER_CLR_PX14               14                               /* Port x Bit 14 Mode Clear */
-#define BITP_PORT_FER_CLR_PX13               13                               /* Port x Bit 13 Mode Clear */
-#define BITP_PORT_FER_CLR_PX12               12                               /* Port x Bit 12 Mode Clear */
-#define BITP_PORT_FER_CLR_PX11               11                               /* Port x Bit 11 Mode Clear */
-#define BITP_PORT_FER_CLR_PX10               10                               /* Port x Bit 10 Mode Clear */
-#define BITP_PORT_FER_CLR_PX9                 9                               /* Port x Bit 9 Mode Clear */
-#define BITP_PORT_FER_CLR_PX8                 8                               /* Port x Bit 8 Mode Clear */
-#define BITP_PORT_FER_CLR_PX7                 7                               /* Port x Bit 7 Mode Clear */
-#define BITP_PORT_FER_CLR_PX6                 6                               /* Port x Bit 6 Mode Clear */
-#define BITP_PORT_FER_CLR_PX5                 5                               /* Port x Bit 5 Mode Clear */
-#define BITP_PORT_FER_CLR_PX4                 4                               /* Port x Bit 4 Mode Clear */
-#define BITP_PORT_FER_CLR_PX3                 3                               /* Port x Bit 3 Mode Clear */
-#define BITP_PORT_FER_CLR_PX2                 2                               /* Port x Bit 2 Mode Clear */
-#define BITP_PORT_FER_CLR_PX1                 1                               /* Port x Bit 1 Mode Clear */
-#define BITP_PORT_FER_CLR_PX0                 0                               /* Port x Bit 0 Mode Clear */
-#define BITM_PORT_FER_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Clear */
-#define BITM_PORT_FER_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Clear */
-#define BITM_PORT_FER_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Clear */
-#define BITM_PORT_FER_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Clear */
-#define BITM_PORT_FER_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Clear */
-#define BITM_PORT_FER_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Clear */
-#define BITM_PORT_FER_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Clear */
-#define BITM_PORT_FER_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Clear */
-#define BITM_PORT_FER_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Clear */
-#define BITM_PORT_FER_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Clear */
-#define BITM_PORT_FER_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Clear */
-#define BITM_PORT_FER_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Clear */
-#define BITM_PORT_FER_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Clear */
-#define BITM_PORT_FER_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Clear */
-#define BITM_PORT_FER_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Clear */
-#define BITM_PORT_FER_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_PX15                  15                               /* Port x Bit 15 Data */
-#define BITP_PORT_DATA_PX14                  14                               /* Port x Bit 14 Data */
-#define BITP_PORT_DATA_PX13                  13                               /* Port x Bit 13 Data */
-#define BITP_PORT_DATA_PX12                  12                               /* Port x Bit 12 Data */
-#define BITP_PORT_DATA_PX11                  11                               /* Port x Bit 11 Data */
-#define BITP_PORT_DATA_PX10                  10                               /* Port x Bit 10 Data */
-#define BITP_PORT_DATA_PX9                    9                               /* Port x Bit 9 Data */
-#define BITP_PORT_DATA_PX8                    8                               /* Port x Bit 8 Data */
-#define BITP_PORT_DATA_PX7                    7                               /* Port x Bit 7 Data */
-#define BITP_PORT_DATA_PX6                    6                               /* Port x Bit 6 Data */
-#define BITP_PORT_DATA_PX5                    5                               /* Port x Bit 5 Data */
-#define BITP_PORT_DATA_PX4                    4                               /* Port x Bit 4 Data */
-#define BITP_PORT_DATA_PX3                    3                               /* Port x Bit 3 Data */
-#define BITP_PORT_DATA_PX2                    2                               /* Port x Bit 2 Data */
-#define BITP_PORT_DATA_PX1                    1                               /* Port x Bit 1 Data */
-#define BITP_PORT_DATA_PX0                    0                               /* Port x Bit 0 Data */
-#define BITM_PORT_DATA_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data */
-#define BITM_PORT_DATA_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data */
-#define BITM_PORT_DATA_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data */
-#define BITM_PORT_DATA_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data */
-#define BITM_PORT_DATA_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data */
-#define BITM_PORT_DATA_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data */
-#define BITM_PORT_DATA_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data */
-#define BITM_PORT_DATA_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data */
-#define BITM_PORT_DATA_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data */
-#define BITM_PORT_DATA_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data */
-#define BITM_PORT_DATA_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data */
-#define BITM_PORT_DATA_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data */
-#define BITM_PORT_DATA_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data */
-#define BITM_PORT_DATA_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data */
-#define BITM_PORT_DATA_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data */
-#define BITM_PORT_DATA_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_SET_PX15              15                               /* Port x Bit 15 Data Set */
-#define BITP_PORT_DATA_SET_PX14              14                               /* Port x Bit 14 Data Set */
-#define BITP_PORT_DATA_SET_PX13              13                               /* Port x Bit 13 Data Set */
-#define BITP_PORT_DATA_SET_PX12              12                               /* Port x Bit 12 Data Set */
-#define BITP_PORT_DATA_SET_PX11              11                               /* Port x Bit 11 Data Set */
-#define BITP_PORT_DATA_SET_PX10              10                               /* Port x Bit 10 Data Set */
-#define BITP_PORT_DATA_SET_PX9                9                               /* Port x Bit 9 Data Set */
-#define BITP_PORT_DATA_SET_PX8                8                               /* Port x Bit 8 Data Set */
-#define BITP_PORT_DATA_SET_PX7                7                               /* Port x Bit 7 Data Set */
-#define BITP_PORT_DATA_SET_PX6                6                               /* Port x Bit 6 Data Set */
-#define BITP_PORT_DATA_SET_PX5                5                               /* Port x Bit 5 Data Set */
-#define BITP_PORT_DATA_SET_PX4                4                               /* Port x Bit 4 Data Set */
-#define BITP_PORT_DATA_SET_PX3                3                               /* Port x Bit 3 Data Set */
-#define BITP_PORT_DATA_SET_PX2                2                               /* Port x Bit 2 Data Set */
-#define BITP_PORT_DATA_SET_PX1                1                               /* Port x Bit 1 Data Set */
-#define BITP_PORT_DATA_SET_PX0                0                               /* Port x Bit 0 Data Set */
-#define BITM_PORT_DATA_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Set */
-#define BITM_PORT_DATA_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Set */
-#define BITM_PORT_DATA_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Set */
-#define BITM_PORT_DATA_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Set */
-#define BITM_PORT_DATA_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Set */
-#define BITM_PORT_DATA_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Set */
-#define BITM_PORT_DATA_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Set */
-#define BITM_PORT_DATA_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Set */
-#define BITM_PORT_DATA_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Set */
-#define BITM_PORT_DATA_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Set */
-#define BITM_PORT_DATA_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Set */
-#define BITM_PORT_DATA_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Set */
-#define BITM_PORT_DATA_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Set */
-#define BITM_PORT_DATA_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Set */
-#define BITM_PORT_DATA_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Set */
-#define BITM_PORT_DATA_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_CLR_PX15              15                               /* Port x Bit 15 Data Clear */
-#define BITP_PORT_DATA_CLR_PX14              14                               /* Port x Bit 14 Data Clear */
-#define BITP_PORT_DATA_CLR_PX13              13                               /* Port x Bit 13 Data Clear */
-#define BITP_PORT_DATA_CLR_PX12              12                               /* Port x Bit 12 Data Clear */
-#define BITP_PORT_DATA_CLR_PX11              11                               /* Port x Bit 11 Data Clear */
-#define BITP_PORT_DATA_CLR_PX10              10                               /* Port x Bit 10 Data Clear */
-#define BITP_PORT_DATA_CLR_PX9                9                               /* Port x Bit 9 Data Clear */
-#define BITP_PORT_DATA_CLR_PX8                8                               /* Port x Bit 8 Data Clear */
-#define BITP_PORT_DATA_CLR_PX7                7                               /* Port x Bit 7 Data Clear */
-#define BITP_PORT_DATA_CLR_PX6                6                               /* Port x Bit 6 Data Clear */
-#define BITP_PORT_DATA_CLR_PX5                5                               /* Port x Bit 5 Data Clear */
-#define BITP_PORT_DATA_CLR_PX4                4                               /* Port x Bit 4 Data Clear */
-#define BITP_PORT_DATA_CLR_PX3                3                               /* Port x Bit 3 Data Clear */
-#define BITP_PORT_DATA_CLR_PX2                2                               /* Port x Bit 2 Data Clear */
-#define BITP_PORT_DATA_CLR_PX1                1                               /* Port x Bit 1 Data Clear */
-#define BITP_PORT_DATA_CLR_PX0                0                               /* Port x Bit 0 Data Clear */
-#define BITM_PORT_DATA_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Clear */
-#define BITM_PORT_DATA_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Clear */
-#define BITM_PORT_DATA_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Clear */
-#define BITM_PORT_DATA_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Clear */
-#define BITM_PORT_DATA_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Clear */
-#define BITM_PORT_DATA_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Clear */
-#define BITM_PORT_DATA_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Clear */
-#define BITM_PORT_DATA_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Clear */
-#define BITM_PORT_DATA_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Clear */
-#define BITM_PORT_DATA_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Clear */
-#define BITM_PORT_DATA_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Clear */
-#define BITM_PORT_DATA_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Clear */
-#define BITM_PORT_DATA_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Clear */
-#define BITM_PORT_DATA_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Clear */
-#define BITM_PORT_DATA_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Clear */
-#define BITM_PORT_DATA_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_PX15                   15                               /* Port x Bit 15 Direction */
-#define BITP_PORT_DIR_PX14                   14                               /* Port x Bit 14 Direction */
-#define BITP_PORT_DIR_PX13                   13                               /* Port x Bit 13 Direction */
-#define BITP_PORT_DIR_PX12                   12                               /* Port x Bit 12 Direction */
-#define BITP_PORT_DIR_PX11                   11                               /* Port x Bit 11 Direction */
-#define BITP_PORT_DIR_PX10                   10                               /* Port x Bit 10 Direction */
-#define BITP_PORT_DIR_PX9                     9                               /* Port x Bit 9 Direction */
-#define BITP_PORT_DIR_PX8                     8                               /* Port x Bit 8 Direction */
-#define BITP_PORT_DIR_PX7                     7                               /* Port x Bit 7 Direction */
-#define BITP_PORT_DIR_PX6                     6                               /* Port x Bit 6 Direction */
-#define BITP_PORT_DIR_PX5                     5                               /* Port x Bit 5 Direction */
-#define BITP_PORT_DIR_PX4                     4                               /* Port x Bit 4 Direction */
-#define BITP_PORT_DIR_PX3                     3                               /* Port x Bit 3 Direction */
-#define BITP_PORT_DIR_PX2                     2                               /* Port x Bit 2 Direction */
-#define BITP_PORT_DIR_PX1                     1                               /* Port x Bit 1 Direction */
-#define BITP_PORT_DIR_PX0                     0                               /* Port x Bit 0 Direction */
-#define BITM_PORT_DIR_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction */
-#define BITM_PORT_DIR_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction */
-#define BITM_PORT_DIR_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction */
-#define BITM_PORT_DIR_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction */
-#define BITM_PORT_DIR_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction */
-#define BITM_PORT_DIR_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction */
-#define BITM_PORT_DIR_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction */
-#define BITM_PORT_DIR_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction */
-#define BITM_PORT_DIR_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction */
-#define BITM_PORT_DIR_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction */
-#define BITM_PORT_DIR_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction */
-#define BITM_PORT_DIR_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction */
-#define BITM_PORT_DIR_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction */
-#define BITM_PORT_DIR_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction */
-#define BITM_PORT_DIR_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction */
-#define BITM_PORT_DIR_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_SET_PX15               15                               /* Port x Bit 15 Direction Set */
-#define BITP_PORT_DIR_SET_PX14               14                               /* Port x Bit 14 Direction Set */
-#define BITP_PORT_DIR_SET_PX13               13                               /* Port x Bit 13 Direction Set */
-#define BITP_PORT_DIR_SET_PX12               12                               /* Port x Bit 12 Direction Set */
-#define BITP_PORT_DIR_SET_PX11               11                               /* Port x Bit 11 Direction Set */
-#define BITP_PORT_DIR_SET_PX10               10                               /* Port x Bit 10 Direction Set */
-#define BITP_PORT_DIR_SET_PX9                 9                               /* Port x Bit 9 Direction Set */
-#define BITP_PORT_DIR_SET_PX8                 8                               /* Port x Bit 8 Direction Set */
-#define BITP_PORT_DIR_SET_PX7                 7                               /* Port x Bit 7 Direction Set */
-#define BITP_PORT_DIR_SET_PX6                 6                               /* Port x Bit 6 Direction Set */
-#define BITP_PORT_DIR_SET_PX5                 5                               /* Port x Bit 5 Direction Set */
-#define BITP_PORT_DIR_SET_PX4                 4                               /* Port x Bit 4 Direction Set */
-#define BITP_PORT_DIR_SET_PX3                 3                               /* Port x Bit 3 Direction Set */
-#define BITP_PORT_DIR_SET_PX2                 2                               /* Port x Bit 2 Direction Set */
-#define BITP_PORT_DIR_SET_PX1                 1                               /* Port x Bit 1 Direction Set */
-#define BITP_PORT_DIR_SET_PX0                 0                               /* Port x Bit 0 Direction Set */
-#define BITM_PORT_DIR_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Set */
-#define BITM_PORT_DIR_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Set */
-#define BITM_PORT_DIR_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Set */
-#define BITM_PORT_DIR_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Set */
-#define BITM_PORT_DIR_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Set */
-#define BITM_PORT_DIR_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Set */
-#define BITM_PORT_DIR_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Set */
-#define BITM_PORT_DIR_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Set */
-#define BITM_PORT_DIR_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Set */
-#define BITM_PORT_DIR_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Set */
-#define BITM_PORT_DIR_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Set */
-#define BITM_PORT_DIR_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Set */
-#define BITM_PORT_DIR_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Set */
-#define BITM_PORT_DIR_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Set */
-#define BITM_PORT_DIR_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Set */
-#define BITM_PORT_DIR_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_CLR_PX15               15                               /* Port x Bit 15 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX14               14                               /* Port x Bit 14 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX13               13                               /* Port x Bit 13 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX12               12                               /* Port x Bit 12 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX11               11                               /* Port x Bit 11 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX10               10                               /* Port x Bit 10 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX9                 9                               /* Port x Bit 9 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX8                 8                               /* Port x Bit 8 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX7                 7                               /* Port x Bit 7 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX6                 6                               /* Port x Bit 6 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX5                 5                               /* Port x Bit 5 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX4                 4                               /* Port x Bit 4 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX3                 3                               /* Port x Bit 3 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX2                 2                               /* Port x Bit 2 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX1                 1                               /* Port x Bit 1 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX0                 0                               /* Port x Bit 0 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_PX15                  15                               /* Port x Bit 15 Input Enable */
-#define BITP_PORT_INEN_PX14                  14                               /* Port x Bit 14 Input Enable */
-#define BITP_PORT_INEN_PX13                  13                               /* Port x Bit 13 Input Enable */
-#define BITP_PORT_INEN_PX12                  12                               /* Port x Bit 12 Input Enable */
-#define BITP_PORT_INEN_PX11                  11                               /* Port x Bit 11 Input Enable */
-#define BITP_PORT_INEN_PX10                  10                               /* Port x Bit 10 Input Enable */
-#define BITP_PORT_INEN_PX9                    9                               /* Port x Bit 9 Input Enable */
-#define BITP_PORT_INEN_PX8                    8                               /* Port x Bit 8 Input Enable */
-#define BITP_PORT_INEN_PX7                    7                               /* Port x Bit 7 Input Enable */
-#define BITP_PORT_INEN_PX6                    6                               /* Port x Bit 6 Input Enable */
-#define BITP_PORT_INEN_PX5                    5                               /* Port x Bit 5 Input Enable */
-#define BITP_PORT_INEN_PX4                    4                               /* Port x Bit 4 Input Enable */
-#define BITP_PORT_INEN_PX3                    3                               /* Port x Bit 3 Input Enable */
-#define BITP_PORT_INEN_PX2                    2                               /* Port x Bit 2 Input Enable */
-#define BITP_PORT_INEN_PX1                    1                               /* Port x Bit 1 Input Enable */
-#define BITP_PORT_INEN_PX0                    0                               /* Port x Bit 0 Input Enable */
-#define BITM_PORT_INEN_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable */
-#define BITM_PORT_INEN_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable */
-#define BITM_PORT_INEN_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable */
-#define BITM_PORT_INEN_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable */
-#define BITM_PORT_INEN_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable */
-#define BITM_PORT_INEN_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable */
-#define BITM_PORT_INEN_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable */
-#define BITM_PORT_INEN_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable */
-#define BITM_PORT_INEN_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable */
-#define BITM_PORT_INEN_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable */
-#define BITM_PORT_INEN_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable */
-#define BITM_PORT_INEN_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable */
-#define BITM_PORT_INEN_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable */
-#define BITM_PORT_INEN_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable */
-#define BITM_PORT_INEN_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable */
-#define BITM_PORT_INEN_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_SET_PX15              15                               /* Port x Bit 15 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX14              14                               /* Port x Bit 14 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX13              13                               /* Port x Bit 13 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX12              12                               /* Port x Bit 12 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX11              11                               /* Port x Bit 11 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX10              10                               /* Port x Bit 10 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX9                9                               /* Port x Bit 9 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX8                8                               /* Port x Bit 8 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX7                7                               /* Port x Bit 7 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX6                6                               /* Port x Bit 6 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX5                5                               /* Port x Bit 5 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX4                4                               /* Port x Bit 4 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX3                3                               /* Port x Bit 3 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX2                2                               /* Port x Bit 2 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX1                1                               /* Port x Bit 1 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX0                0                               /* Port x Bit 0 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_CLR_PX15              15                               /* Port x Bit 15 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX14              14                               /* Port x Bit 14 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX13              13                               /* Port x Bit 13 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX12              12                               /* Port x Bit 12 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX11              11                               /* Port x Bit 11 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX10              10                               /* Port x Bit 10 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX9                9                               /* Port x Bit 9 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX8                8                               /* Port x Bit 8 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX7                7                               /* Port x Bit 7 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX6                6                               /* Port x Bit 6 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX5                5                               /* Port x Bit 5 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX4                4                               /* Port x Bit 4 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX3                3                               /* Port x Bit 3 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX2                2                               /* Port x Bit 2 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX1                1                               /* Port x Bit 1 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX0                0                               /* Port x Bit 0 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_MUX                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_MUX_MUX15                  30                               /* Mux for Port x Bit 15 */
-#define BITP_PORT_MUX_MUX14                  28                               /* Mux for Port x Bit 14 */
-#define BITP_PORT_MUX_MUX13                  26                               /* Mux for Port x Bit 13 */
-#define BITP_PORT_MUX_MUX12                  24                               /* Mux for Port x Bit 12 */
-#define BITP_PORT_MUX_MUX11                  22                               /* Mux for Port x Bit 11 */
-#define BITP_PORT_MUX_MUX10                  20                               /* Mux for Port x Bit 10 */
-#define BITP_PORT_MUX_MUX9                   18                               /* Mux for Port x Bit 9 */
-#define BITP_PORT_MUX_MUX8                   16                               /* Mux for Port x Bit 8 */
-#define BITP_PORT_MUX_MUX7                   14                               /* Mux for Port x Bit 7 */
-#define BITP_PORT_MUX_MUX6                   12                               /* Mux for Port x Bit 6 */
-#define BITP_PORT_MUX_MUX5                   10                               /* Mux for Port x Bit 5 */
-#define BITP_PORT_MUX_MUX4                    8                               /* Mux for Port x Bit 4 */
-#define BITP_PORT_MUX_MUX3                    6                               /* Mux for Port x Bit 3 */
-#define BITP_PORT_MUX_MUX2                    4                               /* Mux for Port x Bit 2 */
-#define BITP_PORT_MUX_MUX1                    2                               /* Mux for Port x Bit 1 */
-#define BITP_PORT_MUX_MUX0                    0                               /* Mux for Port x Bit 0 */
-#define BITM_PORT_MUX_MUX15                  (_ADI_MSK(0xC0000000,uint32_t))  /* Mux for Port x Bit 15 */
-#define BITM_PORT_MUX_MUX14                  (_ADI_MSK(0x30000000,uint32_t))  /* Mux for Port x Bit 14 */
-#define BITM_PORT_MUX_MUX13                  (_ADI_MSK(0x0C000000,uint32_t))  /* Mux for Port x Bit 13 */
-#define BITM_PORT_MUX_MUX12                  (_ADI_MSK(0x03000000,uint32_t))  /* Mux for Port x Bit 12 */
-#define BITM_PORT_MUX_MUX11                  (_ADI_MSK(0x00C00000,uint32_t))  /* Mux for Port x Bit 11 */
-#define BITM_PORT_MUX_MUX10                  (_ADI_MSK(0x00300000,uint32_t))  /* Mux for Port x Bit 10 */
-#define BITM_PORT_MUX_MUX9                   (_ADI_MSK(0x000C0000,uint32_t))  /* Mux for Port x Bit 9 */
-#define BITM_PORT_MUX_MUX8                   (_ADI_MSK(0x00030000,uint32_t))  /* Mux for Port x Bit 8 */
-#define BITM_PORT_MUX_MUX7                   (_ADI_MSK(0x0000C000,uint32_t))  /* Mux for Port x Bit 7 */
-#define BITM_PORT_MUX_MUX6                   (_ADI_MSK(0x00003000,uint32_t))  /* Mux for Port x Bit 6 */
-#define BITM_PORT_MUX_MUX5                   (_ADI_MSK(0x00000C00,uint32_t))  /* Mux for Port x Bit 5 */
-#define BITM_PORT_MUX_MUX4                   (_ADI_MSK(0x00000300,uint32_t))  /* Mux for Port x Bit 4 */
-#define BITM_PORT_MUX_MUX3                   (_ADI_MSK(0x000000C0,uint32_t))  /* Mux for Port x Bit 3 */
-#define BITM_PORT_MUX_MUX2                   (_ADI_MSK(0x00000030,uint32_t))  /* Mux for Port x Bit 2 */
-#define BITM_PORT_MUX_MUX1                   (_ADI_MSK(0x0000000C,uint32_t))  /* Mux for Port x Bit 1 */
-#define BITM_PORT_MUX_MUX0                   (_ADI_MSK(0x00000003,uint32_t))  /* Mux for Port x Bit 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_TGL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_TGL_PX15              15                               /* Port x Bit 15 Toggle */
-#define BITP_PORT_DATA_TGL_PX14              14                               /* Port x Bit 14 Toggle */
-#define BITP_PORT_DATA_TGL_PX13              13                               /* Port x Bit 13 Toggle */
-#define BITP_PORT_DATA_TGL_PX12              12                               /* Port x Bit 12 Toggle */
-#define BITP_PORT_DATA_TGL_PX11              11                               /* Port x Bit 11 Toggle */
-#define BITP_PORT_DATA_TGL_PX10              10                               /* Port x Bit 10 Toggle */
-#define BITP_PORT_DATA_TGL_PX9                9                               /* Port x Bit 9 Toggle */
-#define BITP_PORT_DATA_TGL_PX8                8                               /* Port x Bit 8 Toggle */
-#define BITP_PORT_DATA_TGL_PX7                7                               /* Port x Bit 7 Toggle */
-#define BITP_PORT_DATA_TGL_PX6                6                               /* Port x Bit 6 Toggle */
-#define BITP_PORT_DATA_TGL_PX5                5                               /* Port x Bit 5 Toggle */
-#define BITP_PORT_DATA_TGL_PX4                4                               /* Port x Bit 4 Toggle */
-#define BITP_PORT_DATA_TGL_PX3                3                               /* Port x Bit 3 Toggle */
-#define BITP_PORT_DATA_TGL_PX2                2                               /* Port x Bit 2 Toggle */
-#define BITP_PORT_DATA_TGL_PX1                1                               /* Port x Bit 1 Toggle */
-#define BITP_PORT_DATA_TGL_PX0                0                               /* Port x Bit 0 Toggle */
-#define BITM_PORT_DATA_TGL_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Toggle */
-#define BITM_PORT_DATA_TGL_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Toggle */
-#define BITM_PORT_DATA_TGL_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Toggle */
-#define BITM_PORT_DATA_TGL_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Toggle */
-#define BITM_PORT_DATA_TGL_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Toggle */
-#define BITM_PORT_DATA_TGL_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Toggle */
-#define BITM_PORT_DATA_TGL_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Toggle */
-#define BITM_PORT_DATA_TGL_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Toggle */
-#define BITM_PORT_DATA_TGL_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Toggle */
-#define BITM_PORT_DATA_TGL_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Toggle */
-#define BITM_PORT_DATA_TGL_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Toggle */
-#define BITM_PORT_DATA_TGL_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Toggle */
-#define BITM_PORT_DATA_TGL_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Toggle */
-#define BITM_PORT_DATA_TGL_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Toggle */
-#define BITM_PORT_DATA_TGL_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Toggle */
-#define BITM_PORT_DATA_TGL_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Toggle */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_PX15                   15                               /* Port x Bit 15 Polarity Invert */
-#define BITP_PORT_POL_PX14                   14                               /* Port x Bit 14 Polarity Invert */
-#define BITP_PORT_POL_PX13                   13                               /* Port x Bit 13 Polarity Invert */
-#define BITP_PORT_POL_PX12                   12                               /* Port x Bit 12 Polarity Invert */
-#define BITP_PORT_POL_PX11                   11                               /* Port x Bit 11 Polarity Invert */
-#define BITP_PORT_POL_PX10                   10                               /* Port x Bit 10 Polarity Invert */
-#define BITP_PORT_POL_PX9                     9                               /* Port x Bit 9 Polarity Invert */
-#define BITP_PORT_POL_PX8                     8                               /* Port x Bit 8 Polarity Invert */
-#define BITP_PORT_POL_PX7                     7                               /* Port x Bit 7 Polarity Invert */
-#define BITP_PORT_POL_PX6                     6                               /* Port x Bit 6 Polarity Invert */
-#define BITP_PORT_POL_PX5                     5                               /* Port x Bit 5 Polarity Invert */
-#define BITP_PORT_POL_PX4                     4                               /* Port x Bit 4 Polarity Invert */
-#define BITP_PORT_POL_PX3                     3                               /* Port x Bit 3 Polarity Invert */
-#define BITP_PORT_POL_PX2                     2                               /* Port x Bit 2 Polarity Invert */
-#define BITP_PORT_POL_PX1                     1                               /* Port x Bit 1 Polarity Invert */
-#define BITP_PORT_POL_PX0                     0                               /* Port x Bit 0 Polarity Invert */
-#define BITM_PORT_POL_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert */
-#define BITM_PORT_POL_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert */
-#define BITM_PORT_POL_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert */
-#define BITM_PORT_POL_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert */
-#define BITM_PORT_POL_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert */
-#define BITM_PORT_POL_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert */
-#define BITM_PORT_POL_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert */
-#define BITM_PORT_POL_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert */
-#define BITM_PORT_POL_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert */
-#define BITM_PORT_POL_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert */
-#define BITM_PORT_POL_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert */
-#define BITM_PORT_POL_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert */
-#define BITM_PORT_POL_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert */
-#define BITM_PORT_POL_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert */
-#define BITM_PORT_POL_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert */
-#define BITM_PORT_POL_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_SET_PX15               15                               /* Port x Bit 15 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX14               14                               /* Port x Bit 14 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX13               13                               /* Port x Bit 13 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX12               12                               /* Port x Bit 12 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX11               11                               /* Port x Bit 11 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX10               10                               /* Port x Bit 10 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX9                 9                               /* Port x Bit 9 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX8                 8                               /* Port x Bit 8 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX7                 7                               /* Port x Bit 7 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX6                 6                               /* Port x Bit 6 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX5                 5                               /* Port x Bit 5 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX4                 4                               /* Port x Bit 4 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX3                 3                               /* Port x Bit 3 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX2                 2                               /* Port x Bit 2 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX1                 1                               /* Port x Bit 1 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX0                 0                               /* Port x Bit 0 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_CLR_PX15               15                               /* Port x Bit 15 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX14               14                               /* Port x Bit 14 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX13               13                               /* Port x Bit 13 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX12               12                               /* Port x Bit 12 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX11               11                               /* Port x Bit 11 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX10               10                               /* Port x Bit 10 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX9                 9                               /* Port x Bit 9 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX8                 8                               /* Port x Bit 8 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX7                 7                               /* Port x Bit 7 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX6                 6                               /* Port x Bit 6 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX5                 5                               /* Port x Bit 5 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX4                 4                               /* Port x Bit 4 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX3                 3                               /* Port x Bit 3 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX2                 2                               /* Port x Bit 2 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX1                 1                               /* Port x Bit 1 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX0                 0                               /* Port x Bit 0 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_LOCK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_LOCK_LOCK                  31                               /* Lock */
-#define BITP_PORT_LOCK_POLAR                  5                               /* Polarity Lock */
-#define BITP_PORT_LOCK_INEN                   4                               /* Input Enable Lock */
-#define BITP_PORT_LOCK_DIR                    3                               /* Direction Lock */
-#define BITP_PORT_LOCK_DATA                   2                               /* Data Lock */
-#define BITP_PORT_LOCK_MUX                    1                               /* Function Multiplexer Lock */
-#define BITP_PORT_LOCK_FER                    0                               /* Function Enable Lock */
-#define BITM_PORT_LOCK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_PORT_LOCK_POLAR                 (_ADI_MSK(0x00000020,uint32_t))  /* Polarity Lock */
-#define BITM_PORT_LOCK_INEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Input Enable Lock */
-#define BITM_PORT_LOCK_DIR                   (_ADI_MSK(0x00000008,uint32_t))  /* Direction Lock */
-#define BITM_PORT_LOCK_DATA                  (_ADI_MSK(0x00000004,uint32_t))  /* Data Lock */
-#define BITM_PORT_LOCK_MUX                   (_ADI_MSK(0x00000002,uint32_t))  /* Function Multiplexer Lock */
-#define BITM_PORT_LOCK_FER                   (_ADI_MSK(0x00000001,uint32_t))  /* Function Enable Lock */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_REVID_MAJOR                 4                               /* Major ID */
-#define BITP_PORT_REVID_REV                   0                               /* Revision ID */
-#define BITM_PORT_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PORT_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID */
-
-/* ==================================================
-        Pads Controller Registers
-   ================================================== */
-
-/* =========================
-        PADS0
-   ========================= */
-#define REG_PADS0_EMAC_PTP_CLKSEL       0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
-#define REG_PADS0_TWI_VSEL              0xFFC03408         /* PADS0 TWI Voltage Selection */
-#define REG_PADS0_PORTS_HYST            0xFFC03440         /* PADS0 Hysteresis Enable Register */
-
-/* =========================
-        PADS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_EMAC_PTP_CLKSEL                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC1       2                               /* Select Clock Source for PTP Block in EMAC1 */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC0       0                               /* PTP Clock Source 0 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC1      (_ADI_MSK(0x0000000C,uint32_t))  /* Select Clock Source for PTP Block in EMAC1 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC0      (_ADI_MSK(0x00000003,uint32_t))  /* PTP Clock Source 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_TWI_VSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_TWI_VSEL_TWI1               4                               /* TWI Voltage Select 1 */
-#define BITP_PADS_TWI_VSEL_TWI0               0                               /* TWI Voltage Select 0 */
-#define BITM_PADS_TWI_VSEL_TWI1              (_ADI_MSK(0x00000070,uint32_t))  /* TWI Voltage Select 1 */
-#define BITM_PADS_TWI_VSEL_TWI0              (_ADI_MSK(0x00000007,uint32_t))  /* TWI Voltage Select 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_PORTS_HYST                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_PORTS_HYST_G                6                               /* Port G Hysteresis */
-#define BITP_PADS_PORTS_HYST_F                5                               /* Port F Hysteresis */
-#define BITP_PADS_PORTS_HYST_E                4                               /* Port E Hysteresis */
-#define BITP_PADS_PORTS_HYST_D                3                               /* Port D Hysteresis */
-#define BITP_PADS_PORTS_HYST_C                2                               /* Port C Hysteresis */
-#define BITP_PADS_PORTS_HYST_B                1                               /* Port B Hysteresis */
-#define BITP_PADS_PORTS_HYST_A                0                               /* Port A Hysteresis */
-#define BITM_PADS_PORTS_HYST_G               (_ADI_MSK(0x00000040,uint32_t))  /* Port G Hysteresis */
-#define BITM_PADS_PORTS_HYST_F               (_ADI_MSK(0x00000020,uint32_t))  /* Port F Hysteresis */
-#define BITM_PADS_PORTS_HYST_E               (_ADI_MSK(0x00000010,uint32_t))  /* Port E Hysteresis */
-#define BITM_PADS_PORTS_HYST_D               (_ADI_MSK(0x00000008,uint32_t))  /* Port D Hysteresis */
-#define BITM_PADS_PORTS_HYST_C               (_ADI_MSK(0x00000004,uint32_t))  /* Port C Hysteresis */
-#define BITM_PADS_PORTS_HYST_B               (_ADI_MSK(0x00000002,uint32_t))  /* Port B Hysteresis */
-#define BITM_PADS_PORTS_HYST_A               (_ADI_MSK(0x00000001,uint32_t))  /* Port A Hysteresis */
-
-/* ==================================================
-        PINT Registers
-   ================================================== */
-
-/* =========================
-        PINT0
-   ========================= */
-#define REG_PINT0_MSK_SET               0xFFC04000         /* PINT0 Pint Mask Set Register */
-#define REG_PINT0_MSK_CLR               0xFFC04004         /* PINT0 Pint Mask Clear Register */
-#define REG_PINT0_REQ                   0xFFC04008         /* PINT0 Pint Request Register */
-#define REG_PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
-#define REG_PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
-#define REG_PINT0_EDGE_CLR              0xFFC04014         /* PINT0 Pint Edge Clear Register */
-#define REG_PINT0_INV_SET               0xFFC04018         /* PINT0 Pint Invert Set Register */
-#define REG_PINT0_INV_CLR               0xFFC0401C         /* PINT0 Pint Invert Clear Register */
-#define REG_PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
-#define REG_PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
-
-/* =========================
-        PINT1
-   ========================= */
-#define REG_PINT1_MSK_SET               0xFFC04100         /* PINT1 Pint Mask Set Register */
-#define REG_PINT1_MSK_CLR               0xFFC04104         /* PINT1 Pint Mask Clear Register */
-#define REG_PINT1_REQ                   0xFFC04108         /* PINT1 Pint Request Register */
-#define REG_PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
-#define REG_PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
-#define REG_PINT1_EDGE_CLR              0xFFC04114         /* PINT1 Pint Edge Clear Register */
-#define REG_PINT1_INV_SET               0xFFC04118         /* PINT1 Pint Invert Set Register */
-#define REG_PINT1_INV_CLR               0xFFC0411C         /* PINT1 Pint Invert Clear Register */
-#define REG_PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
-#define REG_PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
-
-/* =========================
-        PINT2
-   ========================= */
-#define REG_PINT2_MSK_SET               0xFFC04200         /* PINT2 Pint Mask Set Register */
-#define REG_PINT2_MSK_CLR               0xFFC04204         /* PINT2 Pint Mask Clear Register */
-#define REG_PINT2_REQ                   0xFFC04208         /* PINT2 Pint Request Register */
-#define REG_PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
-#define REG_PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
-#define REG_PINT2_EDGE_CLR              0xFFC04214         /* PINT2 Pint Edge Clear Register */
-#define REG_PINT2_INV_SET               0xFFC04218         /* PINT2 Pint Invert Set Register */
-#define REG_PINT2_INV_CLR               0xFFC0421C         /* PINT2 Pint Invert Clear Register */
-#define REG_PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
-#define REG_PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
-
-/* =========================
-        PINT3
-   ========================= */
-#define REG_PINT3_MSK_SET               0xFFC04300         /* PINT3 Pint Mask Set Register */
-#define REG_PINT3_MSK_CLR               0xFFC04304         /* PINT3 Pint Mask Clear Register */
-#define REG_PINT3_REQ                   0xFFC04308         /* PINT3 Pint Request Register */
-#define REG_PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
-#define REG_PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
-#define REG_PINT3_EDGE_CLR              0xFFC04314         /* PINT3 Pint Edge Clear Register */
-#define REG_PINT3_INV_SET               0xFFC04318         /* PINT3 Pint Invert Set Register */
-#define REG_PINT3_INV_CLR               0xFFC0431C         /* PINT3 Pint Invert Clear Register */
-#define REG_PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
-#define REG_PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
-
-/* =========================
-        PINT4
-   ========================= */
-#define REG_PINT4_MSK_SET               0xFFC04400         /* PINT4 Pint Mask Set Register */
-#define REG_PINT4_MSK_CLR               0xFFC04404         /* PINT4 Pint Mask Clear Register */
-#define REG_PINT4_REQ                   0xFFC04408         /* PINT4 Pint Request Register */
-#define REG_PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
-#define REG_PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
-#define REG_PINT4_EDGE_CLR              0xFFC04414         /* PINT4 Pint Edge Clear Register */
-#define REG_PINT4_INV_SET               0xFFC04418         /* PINT4 Pint Invert Set Register */
-#define REG_PINT4_INV_CLR               0xFFC0441C         /* PINT4 Pint Invert Clear Register */
-#define REG_PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
-#define REG_PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
-
-/* =========================
-        PINT5
-   ========================= */
-#define REG_PINT5_MSK_SET               0xFFC04500         /* PINT5 Pint Mask Set Register */
-#define REG_PINT5_MSK_CLR               0xFFC04504         /* PINT5 Pint Mask Clear Register */
-#define REG_PINT5_REQ                   0xFFC04508         /* PINT5 Pint Request Register */
-#define REG_PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
-#define REG_PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
-#define REG_PINT5_EDGE_CLR              0xFFC04514         /* PINT5 Pint Edge Clear Register */
-#define REG_PINT5_INV_SET               0xFFC04518         /* PINT5 Pint Invert Set Register */
-#define REG_PINT5_INV_CLR               0xFFC0451C         /* PINT5 Pint Invert Clear Register */
-#define REG_PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
-#define REG_PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
-
-/* =========================
-        PINT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_SET_PIQ31              31                               /* Pin Interrupt 31 Unmask */
-#define BITP_PINT_MSK_SET_PIQ30              30                               /* Pin Interrupt 30 Unmask */
-#define BITP_PINT_MSK_SET_PIQ29              29                               /* Pin Interrupt 29 Unmask */
-#define BITP_PINT_MSK_SET_PIQ28              28                               /* Pin Interrupt 28 Unmask */
-#define BITP_PINT_MSK_SET_PIQ27              27                               /* Pin Interrupt 27 Unmask */
-#define BITP_PINT_MSK_SET_PIQ26              26                               /* Pin Interrupt 26 Unmask */
-#define BITP_PINT_MSK_SET_PIQ25              25                               /* Pin Interrupt 25 Unmask */
-#define BITP_PINT_MSK_SET_PIQ24              24                               /* Pin Interrupt 24 Unmask */
-#define BITP_PINT_MSK_SET_PIQ23              23                               /* Pin Interrupt 23 Unmask */
-#define BITP_PINT_MSK_SET_PIQ22              22                               /* Pin Interrupt 22 Unmask */
-#define BITP_PINT_MSK_SET_PIQ21              21                               /* Pin Interrupt 21 Unmask */
-#define BITP_PINT_MSK_SET_PIQ20              20                               /* Pin Interrupt 20 Unmask */
-#define BITP_PINT_MSK_SET_PIQ19              19                               /* Pin Interrupt 19 Unmask */
-#define BITP_PINT_MSK_SET_PIQ18              18                               /* Pin Interrupt 18 Unmask */
-#define BITP_PINT_MSK_SET_PIQ17              17                               /* Pin Interrupt 17 Unmask */
-#define BITP_PINT_MSK_SET_PIQ16              16                               /* Pin Interrupt 16 Unmask */
-#define BITP_PINT_MSK_SET_PIQ15              15                               /* Pin Interrupt 15 Unmask */
-#define BITP_PINT_MSK_SET_PIQ14              14                               /* Pin Interrupt 14 Unmask */
-#define BITP_PINT_MSK_SET_PIQ13              13                               /* Pin Interrupt 13 Unmask */
-#define BITP_PINT_MSK_SET_PIQ12              12                               /* Pin Interrupt 12 Unmask */
-#define BITP_PINT_MSK_SET_PIQ11              11                               /* Pin Interrupt 11 Unmask */
-#define BITP_PINT_MSK_SET_PIQ10              10                               /* Pin Interrupt 10 Unmask */
-#define BITP_PINT_MSK_SET_PIQ9                9                               /* Pin Interrupt 9 Unmask */
-#define BITP_PINT_MSK_SET_PIQ8                8                               /* Pin Interrupt 8 Unmask */
-#define BITP_PINT_MSK_SET_PIQ7                7                               /* Pin Interrupt 7 Unmask */
-#define BITP_PINT_MSK_SET_PIQ6                6                               /* Pin Interrupt 6 Unmask */
-#define BITP_PINT_MSK_SET_PIQ5                5                               /* Pin Interrupt 5 Unmask */
-#define BITP_PINT_MSK_SET_PIQ4                4                               /* Pin Interrupt 4 Unmask */
-#define BITP_PINT_MSK_SET_PIQ3                3                               /* Pin Interrupt 3 Unmask */
-#define BITP_PINT_MSK_SET_PIQ2                2                               /* Pin Interrupt 2 Unmask */
-#define BITP_PINT_MSK_SET_PIQ1                1                               /* Pin Interrupt 1 Unmask */
-#define BITP_PINT_MSK_SET_PIQ0                0                               /* Pin Interrupt 0 Unmask */
-#define BITM_PINT_MSK_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Unmask */
-#define BITM_PINT_MSK_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Unmask */
-#define BITM_PINT_MSK_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Unmask */
-#define BITM_PINT_MSK_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Unmask */
-#define BITM_PINT_MSK_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Unmask */
-#define BITM_PINT_MSK_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Unmask */
-#define BITM_PINT_MSK_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Unmask */
-#define BITM_PINT_MSK_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Unmask */
-#define BITM_PINT_MSK_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Unmask */
-#define BITM_PINT_MSK_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Unmask */
-#define BITM_PINT_MSK_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Unmask */
-#define BITM_PINT_MSK_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Unmask */
-#define BITM_PINT_MSK_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Unmask */
-#define BITM_PINT_MSK_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Unmask */
-#define BITM_PINT_MSK_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Unmask */
-#define BITM_PINT_MSK_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Unmask */
-#define BITM_PINT_MSK_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Unmask */
-#define BITM_PINT_MSK_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Unmask */
-#define BITM_PINT_MSK_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Unmask */
-#define BITM_PINT_MSK_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Unmask */
-#define BITM_PINT_MSK_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Unmask */
-#define BITM_PINT_MSK_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Unmask */
-#define BITM_PINT_MSK_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Unmask */
-#define BITM_PINT_MSK_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Unmask */
-#define BITM_PINT_MSK_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Unmask */
-#define BITM_PINT_MSK_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Unmask */
-#define BITM_PINT_MSK_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Unmask */
-#define BITM_PINT_MSK_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Unmask */
-#define BITM_PINT_MSK_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Unmask */
-#define BITM_PINT_MSK_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Unmask */
-#define BITM_PINT_MSK_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Unmask */
-#define BITM_PINT_MSK_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_CLR_PIQ31              31                               /* Pin Interrupt 31 Mask */
-#define BITP_PINT_MSK_CLR_PIQ30              30                               /* Pin Interrupt 30 Mask */
-#define BITP_PINT_MSK_CLR_PIQ29              29                               /* Pin Interrupt 29 Mask */
-#define BITP_PINT_MSK_CLR_PIQ28              28                               /* Pin Interrupt 28 Mask */
-#define BITP_PINT_MSK_CLR_PIQ27              27                               /* Pin Interrupt 27 Mask */
-#define BITP_PINT_MSK_CLR_PIQ26              26                               /* Pin Interrupt 26 Mask */
-#define BITP_PINT_MSK_CLR_PIQ25              25                               /* Pin Interrupt 25 Mask */
-#define BITP_PINT_MSK_CLR_PIQ24              24                               /* Pin Interrupt 24 Mask */
-#define BITP_PINT_MSK_CLR_PIQ23              23                               /* Pin Interrupt 23 Mask */
-#define BITP_PINT_MSK_CLR_PIQ22              22                               /* Pin Interrupt 22 Mask */
-#define BITP_PINT_MSK_CLR_PIQ21              21                               /* Pin Interrupt 21 Mask */
-#define BITP_PINT_MSK_CLR_PIQ20              20                               /* Pin Interrupt 20 Mask */
-#define BITP_PINT_MSK_CLR_PIQ19              19                               /* Pin Interrupt 19 Mask */
-#define BITP_PINT_MSK_CLR_PIQ18              18                               /* Pin Interrupt 18 Mask */
-#define BITP_PINT_MSK_CLR_PIQ17              17                               /* Pin Interrupt 17 Mask */
-#define BITP_PINT_MSK_CLR_PIQ16              16                               /* Pin Interrupt 16 Mask */
-#define BITP_PINT_MSK_CLR_PIQ15              15                               /* Pin Interrupt 15 Mask */
-#define BITP_PINT_MSK_CLR_PIQ14              14                               /* Pin Interrupt 14 Mask */
-#define BITP_PINT_MSK_CLR_PIQ13              13                               /* Pin Interrupt 13 Mask */
-#define BITP_PINT_MSK_CLR_PIQ12              12                               /* Pin Interrupt 12 Mask */
-#define BITP_PINT_MSK_CLR_PIQ11              11                               /* Pin Interrupt 11 Mask */
-#define BITP_PINT_MSK_CLR_PIQ10              10                               /* Pin Interrupt 10 Mask */
-#define BITP_PINT_MSK_CLR_PIQ9                9                               /* Pin Interrupt 9 Mask */
-#define BITP_PINT_MSK_CLR_PIQ8                8                               /* Pin Interrupt 8 Mask */
-#define BITP_PINT_MSK_CLR_PIQ7                7                               /* Pin Interrupt 7 Mask */
-#define BITP_PINT_MSK_CLR_PIQ6                6                               /* Pin Interrupt 6 Mask */
-#define BITP_PINT_MSK_CLR_PIQ5                5                               /* Pin Interrupt 5 Mask */
-#define BITP_PINT_MSK_CLR_PIQ4                4                               /* Pin Interrupt 4 Mask */
-#define BITP_PINT_MSK_CLR_PIQ3                3                               /* Pin Interrupt 3 Mask */
-#define BITP_PINT_MSK_CLR_PIQ2                2                               /* Pin Interrupt 2 Mask */
-#define BITP_PINT_MSK_CLR_PIQ1                1                               /* Pin Interrupt 1 Mask */
-#define BITP_PINT_MSK_CLR_PIQ0                0                               /* Pin Interrupt 0 Mask */
-#define BITM_PINT_MSK_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Mask */
-#define BITM_PINT_MSK_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Mask */
-#define BITM_PINT_MSK_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Mask */
-#define BITM_PINT_MSK_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Mask */
-#define BITM_PINT_MSK_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Mask */
-#define BITM_PINT_MSK_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Mask */
-#define BITM_PINT_MSK_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Mask */
-#define BITM_PINT_MSK_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Mask */
-#define BITM_PINT_MSK_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Mask */
-#define BITM_PINT_MSK_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Mask */
-#define BITM_PINT_MSK_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Mask */
-#define BITM_PINT_MSK_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Mask */
-#define BITM_PINT_MSK_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Mask */
-#define BITM_PINT_MSK_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Mask */
-#define BITM_PINT_MSK_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Mask */
-#define BITM_PINT_MSK_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Mask */
-#define BITM_PINT_MSK_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Mask */
-#define BITM_PINT_MSK_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Mask */
-#define BITM_PINT_MSK_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Mask */
-#define BITM_PINT_MSK_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Mask */
-#define BITM_PINT_MSK_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Mask */
-#define BITM_PINT_MSK_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Mask */
-#define BITM_PINT_MSK_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Mask */
-#define BITM_PINT_MSK_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Mask */
-#define BITM_PINT_MSK_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Mask */
-#define BITM_PINT_MSK_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Mask */
-#define BITM_PINT_MSK_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Mask */
-#define BITM_PINT_MSK_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Mask */
-#define BITM_PINT_MSK_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Mask */
-#define BITM_PINT_MSK_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Mask */
-#define BITM_PINT_MSK_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Mask */
-#define BITM_PINT_MSK_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_REQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_REQ_PIQ31                  31                               /* Pin Interrupt 31 Request */
-#define BITP_PINT_REQ_PIQ30                  30                               /* Pin Interrupt 30 Request */
-#define BITP_PINT_REQ_PIQ29                  29                               /* Pin Interrupt 29 Request */
-#define BITP_PINT_REQ_PIQ28                  28                               /* Pin Interrupt 28 Request */
-#define BITP_PINT_REQ_PIQ27                  27                               /* Pin Interrupt 27 Request */
-#define BITP_PINT_REQ_PIQ26                  26                               /* Pin Interrupt 26 Request */
-#define BITP_PINT_REQ_PIQ25                  25                               /* Pin Interrupt 25 Request */
-#define BITP_PINT_REQ_PIQ24                  24                               /* Pin Interrupt 24 Request */
-#define BITP_PINT_REQ_PIQ23                  23                               /* Pin Interrupt 23 Request */
-#define BITP_PINT_REQ_PIQ22                  22                               /* Pin Interrupt 22 Request */
-#define BITP_PINT_REQ_PIQ21                  21                               /* Pin Interrupt 21 Request */
-#define BITP_PINT_REQ_PIQ20                  20                               /* Pin Interrupt 20 Request */
-#define BITP_PINT_REQ_PIQ19                  19                               /* Pin Interrupt 19 Request */
-#define BITP_PINT_REQ_PIQ18                  18                               /* Pin Interrupt 18 Request */
-#define BITP_PINT_REQ_PIQ17                  17                               /* Pin Interrupt 17 Request */
-#define BITP_PINT_REQ_PIQ16                  16                               /* Pin Interrupt 16 Request */
-#define BITP_PINT_REQ_PIQ15                  15                               /* Pin Interrupt 15 Request */
-#define BITP_PINT_REQ_PIQ14                  14                               /* Pin Interrupt 14 Request */
-#define BITP_PINT_REQ_PIQ13                  13                               /* Pin Interrupt 13 Request */
-#define BITP_PINT_REQ_PIQ12                  12                               /* Pin Interrupt 12 Request */
-#define BITP_PINT_REQ_PIQ11                  11                               /* Pin Interrupt 11 Request */
-#define BITP_PINT_REQ_PIQ10                  10                               /* Pin Interrupt 10 Request */
-#define BITP_PINT_REQ_PIQ9                    9                               /* Pin Interrupt 9 Request */
-#define BITP_PINT_REQ_PIQ8                    8                               /* Pin Interrupt 8 Request */
-#define BITP_PINT_REQ_PIQ7                    7                               /* Pin Interrupt 7 Request */
-#define BITP_PINT_REQ_PIQ6                    6                               /* Pin Interrupt 6 Request */
-#define BITP_PINT_REQ_PIQ5                    5                               /* Pin Interrupt 5 Request */
-#define BITP_PINT_REQ_PIQ4                    4                               /* Pin Interrupt 4 Request */
-#define BITP_PINT_REQ_PIQ3                    3                               /* Pin Interrupt 3 Request */
-#define BITP_PINT_REQ_PIQ2                    2                               /* Pin Interrupt 2 Request */
-#define BITP_PINT_REQ_PIQ1                    1                               /* Pin Interrupt 1 Request */
-#define BITP_PINT_REQ_PIQ0                    0                               /* Pin Interrupt 0 Request */
-#define BITM_PINT_REQ_PIQ31                  (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Request */
-#define BITM_PINT_REQ_PIQ30                  (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Request */
-#define BITM_PINT_REQ_PIQ29                  (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Request */
-#define BITM_PINT_REQ_PIQ28                  (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Request */
-#define BITM_PINT_REQ_PIQ27                  (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Request */
-#define BITM_PINT_REQ_PIQ26                  (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Request */
-#define BITM_PINT_REQ_PIQ25                  (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Request */
-#define BITM_PINT_REQ_PIQ24                  (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Request */
-#define BITM_PINT_REQ_PIQ23                  (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Request */
-#define BITM_PINT_REQ_PIQ22                  (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Request */
-#define BITM_PINT_REQ_PIQ21                  (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Request */
-#define BITM_PINT_REQ_PIQ20                  (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Request */
-#define BITM_PINT_REQ_PIQ19                  (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Request */
-#define BITM_PINT_REQ_PIQ18                  (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Request */
-#define BITM_PINT_REQ_PIQ17                  (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Request */
-#define BITM_PINT_REQ_PIQ16                  (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Request */
-#define BITM_PINT_REQ_PIQ15                  (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Request */
-#define BITM_PINT_REQ_PIQ14                  (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Request */
-#define BITM_PINT_REQ_PIQ13                  (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Request */
-#define BITM_PINT_REQ_PIQ12                  (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Request */
-#define BITM_PINT_REQ_PIQ11                  (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Request */
-#define BITM_PINT_REQ_PIQ10                  (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Request */
-#define BITM_PINT_REQ_PIQ9                   (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Request */
-#define BITM_PINT_REQ_PIQ8                   (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Request */
-#define BITM_PINT_REQ_PIQ7                   (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Request */
-#define BITM_PINT_REQ_PIQ6                   (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Request */
-#define BITM_PINT_REQ_PIQ5                   (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Request */
-#define BITM_PINT_REQ_PIQ4                   (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Request */
-#define BITM_PINT_REQ_PIQ3                   (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Request */
-#define BITM_PINT_REQ_PIQ2                   (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Request */
-#define BITM_PINT_REQ_PIQ1                   (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Request */
-#define BITM_PINT_REQ_PIQ0                   (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_ASSIGN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_ASSIGN_B3MAP               24                               /* Byte 3 Mapping */
-#define BITP_PINT_ASSIGN_B2MAP               16                               /* Byte 2 Mapping */
-#define BITP_PINT_ASSIGN_B1MAP                8                               /* Byte 1 Mapping */
-#define BITP_PINT_ASSIGN_B0MAP                0                               /* Byte 0 Mapping */
-#define BITM_PINT_ASSIGN_B3MAP               (_ADI_MSK(0xFF000000,uint32_t))  /* Byte 3 Mapping */
-#define BITM_PINT_ASSIGN_B2MAP               (_ADI_MSK(0x00FF0000,uint32_t))  /* Byte 2 Mapping */
-#define BITM_PINT_ASSIGN_B1MAP               (_ADI_MSK(0x0000FF00,uint32_t))  /* Byte 1 Mapping */
-#define BITM_PINT_ASSIGN_B0MAP               (_ADI_MSK(0x000000FF,uint32_t))  /* Byte 0 Mapping */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_SET_PIQ31             31                               /* Pin Interrupt 31 Edge */
-#define BITP_PINT_EDGE_SET_PIQ30             30                               /* Pin Interrupt 30 Edge */
-#define BITP_PINT_EDGE_SET_PIQ29             29                               /* Pin Interrupt 29 Edge */
-#define BITP_PINT_EDGE_SET_PIQ28             28                               /* Pin Interrupt 28 Edge */
-#define BITP_PINT_EDGE_SET_PIQ27             27                               /* Pin Interrupt 27 Edge */
-#define BITP_PINT_EDGE_SET_PIQ26             26                               /* Pin Interrupt 26 Edge */
-#define BITP_PINT_EDGE_SET_PIQ25             25                               /* Pin Interrupt 25 Edge */
-#define BITP_PINT_EDGE_SET_PIQ24             24                               /* Pin Interrupt 24 Edge */
-#define BITP_PINT_EDGE_SET_PIQ23             23                               /* Pin Interrupt 23 Edge */
-#define BITP_PINT_EDGE_SET_PIQ22             22                               /* Pin Interrupt 22 Edge */
-#define BITP_PINT_EDGE_SET_PIQ21             21                               /* Pin Interrupt 21 Edge */
-#define BITP_PINT_EDGE_SET_PIQ20             20                               /* Pin Interrupt 20 Edge */
-#define BITP_PINT_EDGE_SET_PIQ19             19                               /* Pin Interrupt 19 Edge */
-#define BITP_PINT_EDGE_SET_PIQ18             18                               /* Pin Interrupt 18 Edge */
-#define BITP_PINT_EDGE_SET_PIQ17             17                               /* Pin Interrupt 17 Edge */
-#define BITP_PINT_EDGE_SET_PIQ16             16                               /* Pin Interrupt 16 Edge */
-#define BITP_PINT_EDGE_SET_PIQ15             15                               /* Pin Interrupt 15 Edge */
-#define BITP_PINT_EDGE_SET_PIQ14             14                               /* Pin Interrupt 14 Edge */
-#define BITP_PINT_EDGE_SET_PIQ13             13                               /* Pin Interrupt 13 Edge */
-#define BITP_PINT_EDGE_SET_PIQ12             12                               /* Pin Interrupt 12 Edge */
-#define BITP_PINT_EDGE_SET_PIQ11             11                               /* Pin Interrupt 11 Edge */
-#define BITP_PINT_EDGE_SET_PIQ10             10                               /* Pin Interrupt 10 Edge */
-#define BITP_PINT_EDGE_SET_PIQ9               9                               /* Pin Interrupt 9 Edge */
-#define BITP_PINT_EDGE_SET_PIQ8               8                               /* Pin Interrupt 8 Edge */
-#define BITP_PINT_EDGE_SET_PIQ7               7                               /* Pin Interrupt 7 Edge */
-#define BITP_PINT_EDGE_SET_PIQ6               6                               /* Pin Interrupt 6 Edge */
-#define BITP_PINT_EDGE_SET_PIQ5               5                               /* Pin Interrupt 5 Edge */
-#define BITP_PINT_EDGE_SET_PIQ4               4                               /* Pin Interrupt 4 Edge */
-#define BITP_PINT_EDGE_SET_PIQ3               3                               /* Pin Interrupt 3 Edge */
-#define BITP_PINT_EDGE_SET_PIQ2               2                               /* Pin Interrupt 2 Edge */
-#define BITP_PINT_EDGE_SET_PIQ1               1                               /* Pin Interrupt 1 Edge */
-#define BITP_PINT_EDGE_SET_PIQ0               0                               /* Pin Interrupt 0 Edge */
-#define BITM_PINT_EDGE_SET_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Edge */
-#define BITM_PINT_EDGE_SET_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Edge */
-#define BITM_PINT_EDGE_SET_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Edge */
-#define BITM_PINT_EDGE_SET_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Edge */
-#define BITM_PINT_EDGE_SET_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Edge */
-#define BITM_PINT_EDGE_SET_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Edge */
-#define BITM_PINT_EDGE_SET_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Edge */
-#define BITM_PINT_EDGE_SET_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Edge */
-#define BITM_PINT_EDGE_SET_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Edge */
-#define BITM_PINT_EDGE_SET_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Edge */
-#define BITM_PINT_EDGE_SET_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Edge */
-#define BITM_PINT_EDGE_SET_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Edge */
-#define BITM_PINT_EDGE_SET_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Edge */
-#define BITM_PINT_EDGE_SET_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Edge */
-#define BITM_PINT_EDGE_SET_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Edge */
-#define BITM_PINT_EDGE_SET_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Edge */
-#define BITM_PINT_EDGE_SET_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Edge */
-#define BITM_PINT_EDGE_SET_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Edge */
-#define BITM_PINT_EDGE_SET_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Edge */
-#define BITM_PINT_EDGE_SET_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Edge */
-#define BITM_PINT_EDGE_SET_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Edge */
-#define BITM_PINT_EDGE_SET_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Edge */
-#define BITM_PINT_EDGE_SET_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Edge */
-#define BITM_PINT_EDGE_SET_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Edge */
-#define BITM_PINT_EDGE_SET_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Edge */
-#define BITM_PINT_EDGE_SET_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Edge */
-#define BITM_PINT_EDGE_SET_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Edge */
-#define BITM_PINT_EDGE_SET_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Edge */
-#define BITM_PINT_EDGE_SET_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Edge */
-#define BITM_PINT_EDGE_SET_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Edge */
-#define BITM_PINT_EDGE_SET_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Edge */
-#define BITM_PINT_EDGE_SET_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Edge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_CLR_PIQ31             31                               /* Pin Interrupt 31 Level */
-#define BITP_PINT_EDGE_CLR_PIQ30             30                               /* Pin Interrupt 30 Level */
-#define BITP_PINT_EDGE_CLR_PIQ29             29                               /* Pin Interrupt 29 Level */
-#define BITP_PINT_EDGE_CLR_PIQ28             28                               /* Pin Interrupt 28 Level */
-#define BITP_PINT_EDGE_CLR_PIQ27             27                               /* Pin Interrupt 27 Level */
-#define BITP_PINT_EDGE_CLR_PIQ26             26                               /* Pin Interrupt 26 Level */
-#define BITP_PINT_EDGE_CLR_PIQ25             25                               /* Pin Interrupt 25 Level */
-#define BITP_PINT_EDGE_CLR_PIQ24             24                               /* Pin Interrupt 24 Level */
-#define BITP_PINT_EDGE_CLR_PIQ23             23                               /* Pin Interrupt 23 Level */
-#define BITP_PINT_EDGE_CLR_PIQ22             22                               /* Pin Interrupt 22 Level */
-#define BITP_PINT_EDGE_CLR_PIQ21             21                               /* Pin Interrupt 21 Level */
-#define BITP_PINT_EDGE_CLR_PIQ20             20                               /* Pin Interrupt 20 Level */
-#define BITP_PINT_EDGE_CLR_PIQ19             19                               /* Pin Interrupt 19 Level */
-#define BITP_PINT_EDGE_CLR_PIQ18             18                               /* Pin Interrupt 18 Level */
-#define BITP_PINT_EDGE_CLR_PIQ17             17                               /* Pin Interrupt 17 Level */
-#define BITP_PINT_EDGE_CLR_PIQ16             16                               /* Pin Interrupt 16 Level */
-#define BITP_PINT_EDGE_CLR_PIQ15             15                               /* Pin Interrupt 15 Level */
-#define BITP_PINT_EDGE_CLR_PIQ14             14                               /* Pin Interrupt 14 Level */
-#define BITP_PINT_EDGE_CLR_PIQ13             13                               /* Pin Interrupt 13 Level */
-#define BITP_PINT_EDGE_CLR_PIQ12             12                               /* Pin Interrupt 12 Level */
-#define BITP_PINT_EDGE_CLR_PIQ11             11                               /* Pin Interrupt 11 Level */
-#define BITP_PINT_EDGE_CLR_PIQ10             10                               /* Pin Interrupt 10 Level */
-#define BITP_PINT_EDGE_CLR_PIQ9               9                               /* Pin Interrupt 9 Level */
-#define BITP_PINT_EDGE_CLR_PIQ8               8                               /* Pin Interrupt 8 Level */
-#define BITP_PINT_EDGE_CLR_PIQ7               7                               /* Pin Interrupt 7 Level */
-#define BITP_PINT_EDGE_CLR_PIQ6               6                               /* Pin Interrupt 6 Level */
-#define BITP_PINT_EDGE_CLR_PIQ5               5                               /* Pin Interrupt 5 Level */
-#define BITP_PINT_EDGE_CLR_PIQ4               4                               /* Pin Interrupt 4 Level */
-#define BITP_PINT_EDGE_CLR_PIQ3               3                               /* Pin Interrupt 3 Level */
-#define BITP_PINT_EDGE_CLR_PIQ2               2                               /* Pin Interrupt 2 Level */
-#define BITP_PINT_EDGE_CLR_PIQ1               1                               /* Pin Interrupt 1 Level */
-#define BITP_PINT_EDGE_CLR_PIQ0               0                               /* Pin Interrupt 0 Level */
-#define BITM_PINT_EDGE_CLR_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Level */
-#define BITM_PINT_EDGE_CLR_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Level */
-#define BITM_PINT_EDGE_CLR_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Level */
-#define BITM_PINT_EDGE_CLR_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Level */
-#define BITM_PINT_EDGE_CLR_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Level */
-#define BITM_PINT_EDGE_CLR_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Level */
-#define BITM_PINT_EDGE_CLR_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Level */
-#define BITM_PINT_EDGE_CLR_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Level */
-#define BITM_PINT_EDGE_CLR_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Level */
-#define BITM_PINT_EDGE_CLR_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Level */
-#define BITM_PINT_EDGE_CLR_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Level */
-#define BITM_PINT_EDGE_CLR_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Level */
-#define BITM_PINT_EDGE_CLR_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Level */
-#define BITM_PINT_EDGE_CLR_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Level */
-#define BITM_PINT_EDGE_CLR_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Level */
-#define BITM_PINT_EDGE_CLR_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Level */
-#define BITM_PINT_EDGE_CLR_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Level */
-#define BITM_PINT_EDGE_CLR_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Level */
-#define BITM_PINT_EDGE_CLR_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Level */
-#define BITM_PINT_EDGE_CLR_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Level */
-#define BITM_PINT_EDGE_CLR_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Level */
-#define BITM_PINT_EDGE_CLR_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Level */
-#define BITM_PINT_EDGE_CLR_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Level */
-#define BITM_PINT_EDGE_CLR_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Level */
-#define BITM_PINT_EDGE_CLR_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Level */
-#define BITM_PINT_EDGE_CLR_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Level */
-#define BITM_PINT_EDGE_CLR_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Level */
-#define BITM_PINT_EDGE_CLR_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Level */
-#define BITM_PINT_EDGE_CLR_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Level */
-#define BITM_PINT_EDGE_CLR_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Level */
-#define BITM_PINT_EDGE_CLR_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Level */
-#define BITM_PINT_EDGE_CLR_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Level */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_SET_PIQ31              31                               /* Pin Interrupt 31 Invert */
-#define BITP_PINT_INV_SET_PIQ30              30                               /* Pin Interrupt 30 Invert */
-#define BITP_PINT_INV_SET_PIQ29              29                               /* Pin Interrupt 29 Invert */
-#define BITP_PINT_INV_SET_PIQ28              28                               /* Pin Interrupt 28 Invert */
-#define BITP_PINT_INV_SET_PIQ27              27                               /* Pin Interrupt 27 Invert */
-#define BITP_PINT_INV_SET_PIQ26              26                               /* Pin Interrupt 26 Invert */
-#define BITP_PINT_INV_SET_PIQ25              25                               /* Pin Interrupt 25 Invert */
-#define BITP_PINT_INV_SET_PIQ24              24                               /* Pin Interrupt 24 Invert */
-#define BITP_PINT_INV_SET_PIQ23              23                               /* Pin Interrupt 23 Invert */
-#define BITP_PINT_INV_SET_PIQ22              22                               /* Pin Interrupt 22 Invert */
-#define BITP_PINT_INV_SET_PIQ21              21                               /* Pin Interrupt 21 Invert */
-#define BITP_PINT_INV_SET_PIQ20              20                               /* Pin Interrupt 20 Invert */
-#define BITP_PINT_INV_SET_PIQ19              19                               /* Pin Interrupt 19 Invert */
-#define BITP_PINT_INV_SET_PIQ18              18                               /* Pin Interrupt 18 Invert */
-#define BITP_PINT_INV_SET_PIQ17              17                               /* Pin Interrupt 17 Invert */
-#define BITP_PINT_INV_SET_PIQ16              16                               /* Pin Interrupt 16 Invert */
-#define BITP_PINT_INV_SET_PIQ15              15                               /* Pin Interrupt 15 Invert */
-#define BITP_PINT_INV_SET_PIQ14              14                               /* Pin Interrupt 14 Invert */
-#define BITP_PINT_INV_SET_PIQ13              13                               /* Pin Interrupt 13 Invert */
-#define BITP_PINT_INV_SET_PIQ12              12                               /* Pin Interrupt 12 Invert */
-#define BITP_PINT_INV_SET_PIQ11              11                               /* Pin Interrupt 11 Invert */
-#define BITP_PINT_INV_SET_PIQ10              10                               /* Pin Interrupt 10 Invert */
-#define BITP_PINT_INV_SET_PIQ9                9                               /* Pin Interrupt 9 Invert */
-#define BITP_PINT_INV_SET_PIQ8                8                               /* Pin Interrupt 8 Invert */
-#define BITP_PINT_INV_SET_PIQ7                7                               /* Pin Interrupt 7 Invert */
-#define BITP_PINT_INV_SET_PIQ6                6                               /* Pin Interrupt 6 Invert */
-#define BITP_PINT_INV_SET_PIQ5                5                               /* Pin Interrupt 5 Invert */
-#define BITP_PINT_INV_SET_PIQ4                4                               /* Pin Interrupt 4 Invert */
-#define BITP_PINT_INV_SET_PIQ3                3                               /* Pin Interrupt 3 Invert */
-#define BITP_PINT_INV_SET_PIQ2                2                               /* Pin Interrupt 2 Invert */
-#define BITP_PINT_INV_SET_PIQ1                1                               /* Pin Interrupt 1 Invert */
-#define BITP_PINT_INV_SET_PIQ0                0                               /* Pin Interrupt 0 Invert */
-#define BITM_PINT_INV_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Invert */
-#define BITM_PINT_INV_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Invert */
-#define BITM_PINT_INV_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Invert */
-#define BITM_PINT_INV_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Invert */
-#define BITM_PINT_INV_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Invert */
-#define BITM_PINT_INV_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Invert */
-#define BITM_PINT_INV_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Invert */
-#define BITM_PINT_INV_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Invert */
-#define BITM_PINT_INV_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Invert */
-#define BITM_PINT_INV_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Invert */
-#define BITM_PINT_INV_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Invert */
-#define BITM_PINT_INV_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Invert */
-#define BITM_PINT_INV_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Invert */
-#define BITM_PINT_INV_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Invert */
-#define BITM_PINT_INV_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Invert */
-#define BITM_PINT_INV_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Invert */
-#define BITM_PINT_INV_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Invert */
-#define BITM_PINT_INV_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Invert */
-#define BITM_PINT_INV_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Invert */
-#define BITM_PINT_INV_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Invert */
-#define BITM_PINT_INV_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Invert */
-#define BITM_PINT_INV_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Invert */
-#define BITM_PINT_INV_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Invert */
-#define BITM_PINT_INV_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Invert */
-#define BITM_PINT_INV_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Invert */
-#define BITM_PINT_INV_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Invert */
-#define BITM_PINT_INV_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Invert */
-#define BITM_PINT_INV_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Invert */
-#define BITM_PINT_INV_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Invert */
-#define BITM_PINT_INV_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Invert */
-#define BITM_PINT_INV_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Invert */
-#define BITM_PINT_INV_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_CLR_PIQ31              31                               /* Pin Interrupt 31 No Invert */
-#define BITP_PINT_INV_CLR_PIQ30              30                               /* Pin Interrupt 30 No Invert */
-#define BITP_PINT_INV_CLR_PIQ29              29                               /* Pin Interrupt 29 No Invert */
-#define BITP_PINT_INV_CLR_PIQ28              28                               /* Pin Interrupt 28 No Invert */
-#define BITP_PINT_INV_CLR_PIQ27              27                               /* Pin Interrupt 27 No Invert */
-#define BITP_PINT_INV_CLR_PIQ26              26                               /* Pin Interrupt 26 No Invert */
-#define BITP_PINT_INV_CLR_PIQ25              25                               /* Pin Interrupt 25 No Invert */
-#define BITP_PINT_INV_CLR_PIQ24              24                               /* Pin Interrupt 24 No Invert */
-#define BITP_PINT_INV_CLR_PIQ23              23                               /* Pin Interrupt 23 No Invert */
-#define BITP_PINT_INV_CLR_PIQ22              22                               /* Pin Interrupt 22 No Invert */
-#define BITP_PINT_INV_CLR_PIQ21              21                               /* Pin Interrupt 21 No Invert */
-#define BITP_PINT_INV_CLR_PIQ20              20                               /* Pin Interrupt 20 No Invert */
-#define BITP_PINT_INV_CLR_PIQ19              19                               /* Pin Interrupt 19 No Invert */
-#define BITP_PINT_INV_CLR_PIQ18              18                               /* Pin Interrupt 18 No Invert */
-#define BITP_PINT_INV_CLR_PIQ17              17                               /* Pin Interrupt 17 No Invert */
-#define BITP_PINT_INV_CLR_PIQ16              16                               /* Pin Interrupt 16 No Invert */
-#define BITP_PINT_INV_CLR_PIQ15              15                               /* Pin Interrupt 15 No Invert */
-#define BITP_PINT_INV_CLR_PIQ14              14                               /* Pin Interrupt 14 No Invert */
-#define BITP_PINT_INV_CLR_PIQ13              13                               /* Pin Interrupt 13 No Invert */
-#define BITP_PINT_INV_CLR_PIQ12              12                               /* Pin Interrupt 12 No Invert */
-#define BITP_PINT_INV_CLR_PIQ11              11                               /* Pin Interrupt 11 No Invert */
-#define BITP_PINT_INV_CLR_PIQ10              10                               /* Pin Interrupt 10 No Invert */
-#define BITP_PINT_INV_CLR_PIQ9                9                               /* Pin Interrupt 9 No Invert */
-#define BITP_PINT_INV_CLR_PIQ8                8                               /* Pin Interrupt 8 No Invert */
-#define BITP_PINT_INV_CLR_PIQ7                7                               /* Pin Interrupt 7 No Invert */
-#define BITP_PINT_INV_CLR_PIQ6                6                               /* Pin Interrupt 6 No Invert */
-#define BITP_PINT_INV_CLR_PIQ5                5                               /* Pin Interrupt 5 No Invert */
-#define BITP_PINT_INV_CLR_PIQ4                4                               /* Pin Interrupt 4 No Invert */
-#define BITP_PINT_INV_CLR_PIQ3                3                               /* Pin Interrupt 3 No Invert */
-#define BITP_PINT_INV_CLR_PIQ2                2                               /* Pin Interrupt 2 No Invert */
-#define BITP_PINT_INV_CLR_PIQ1                1                               /* Pin Interrupt 1 No Invert */
-#define BITP_PINT_INV_CLR_PIQ0                0                               /* Pin Interrupt 0 No Invert */
-#define BITM_PINT_INV_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 No Invert */
-#define BITM_PINT_INV_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 No Invert */
-#define BITM_PINT_INV_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 No Invert */
-#define BITM_PINT_INV_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 No Invert */
-#define BITM_PINT_INV_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 No Invert */
-#define BITM_PINT_INV_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 No Invert */
-#define BITM_PINT_INV_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 No Invert */
-#define BITM_PINT_INV_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 No Invert */
-#define BITM_PINT_INV_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 No Invert */
-#define BITM_PINT_INV_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 No Invert */
-#define BITM_PINT_INV_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 No Invert */
-#define BITM_PINT_INV_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 No Invert */
-#define BITM_PINT_INV_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 No Invert */
-#define BITM_PINT_INV_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 No Invert */
-#define BITM_PINT_INV_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 No Invert */
-#define BITM_PINT_INV_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 No Invert */
-#define BITM_PINT_INV_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 No Invert */
-#define BITM_PINT_INV_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 No Invert */
-#define BITM_PINT_INV_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 No Invert */
-#define BITM_PINT_INV_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 No Invert */
-#define BITM_PINT_INV_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 No Invert */
-#define BITM_PINT_INV_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 No Invert */
-#define BITM_PINT_INV_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 No Invert */
-#define BITM_PINT_INV_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 No Invert */
-#define BITM_PINT_INV_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 No Invert */
-#define BITM_PINT_INV_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 No Invert */
-#define BITM_PINT_INV_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 No Invert */
-#define BITM_PINT_INV_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 No Invert */
-#define BITM_PINT_INV_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 No Invert */
-#define BITM_PINT_INV_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 No Invert */
-#define BITM_PINT_INV_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 No Invert */
-#define BITM_PINT_INV_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 No Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_PINSTATE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_PINSTATE_PIQ31             31                               /* Pin Interrupt 31 State */
-#define BITP_PINT_PINSTATE_PIQ30             30                               /* Pin Interrupt 30 State */
-#define BITP_PINT_PINSTATE_PIQ29             29                               /* Pin Interrupt 29 State */
-#define BITP_PINT_PINSTATE_PIQ28             28                               /* Pin Interrupt 28 State */
-#define BITP_PINT_PINSTATE_PIQ27             27                               /* Pin Interrupt 27 State */
-#define BITP_PINT_PINSTATE_PIQ26             26                               /* Pin Interrupt 26 State */
-#define BITP_PINT_PINSTATE_PIQ25             25                               /* Pin Interrupt 25 State */
-#define BITP_PINT_PINSTATE_PIQ24             24                               /* Pin Interrupt 24 State */
-#define BITP_PINT_PINSTATE_PIQ23             23                               /* Pin Interrupt 23 State */
-#define BITP_PINT_PINSTATE_PIQ22             22                               /* Pin Interrupt 22 State */
-#define BITP_PINT_PINSTATE_PIQ21             21                               /* Pin Interrupt 21 State */
-#define BITP_PINT_PINSTATE_PIQ20             20                               /* Pin Interrupt 20 State */
-#define BITP_PINT_PINSTATE_PIQ19             19                               /* Pin Interrupt 19 State */
-#define BITP_PINT_PINSTATE_PIQ18             18                               /* Pin Interrupt 18 State */
-#define BITP_PINT_PINSTATE_PIQ17             17                               /* Pin Interrupt 17 State */
-#define BITP_PINT_PINSTATE_PIQ16             16                               /* Pin Interrupt 16 State */
-#define BITP_PINT_PINSTATE_PIQ15             15                               /* Pin Interrupt 15 State */
-#define BITP_PINT_PINSTATE_PIQ14             14                               /* Pin Interrupt 14 State */
-#define BITP_PINT_PINSTATE_PIQ13             13                               /* Pin Interrupt 13 State */
-#define BITP_PINT_PINSTATE_PIQ12             12                               /* Pin Interrupt 12 State */
-#define BITP_PINT_PINSTATE_PIQ11             11                               /* Pin Interrupt 11 State */
-#define BITP_PINT_PINSTATE_PIQ10             10                               /* Pin Interrupt 10 State */
-#define BITP_PINT_PINSTATE_PIQ9               9                               /* Pin Interrupt 9 State */
-#define BITP_PINT_PINSTATE_PIQ8               8                               /* Pin Interrupt 8 State */
-#define BITP_PINT_PINSTATE_PIQ7               7                               /* Pin Interrupt 7 State */
-#define BITP_PINT_PINSTATE_PIQ6               6                               /* Pin Interrupt 6 State */
-#define BITP_PINT_PINSTATE_PIQ5               5                               /* Pin Interrupt 5 State */
-#define BITP_PINT_PINSTATE_PIQ4               4                               /* Pin Interrupt 4 State */
-#define BITP_PINT_PINSTATE_PIQ3               3                               /* Pin Interrupt 3 State */
-#define BITP_PINT_PINSTATE_PIQ2               2                               /* Pin Interrupt 2 State */
-#define BITP_PINT_PINSTATE_PIQ1               1                               /* Pin Interrupt 1 State */
-#define BITP_PINT_PINSTATE_PIQ0               0                               /* Pin Interrupt 0 State */
-#define BITM_PINT_PINSTATE_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 State */
-#define BITM_PINT_PINSTATE_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 State */
-#define BITM_PINT_PINSTATE_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 State */
-#define BITM_PINT_PINSTATE_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 State */
-#define BITM_PINT_PINSTATE_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 State */
-#define BITM_PINT_PINSTATE_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 State */
-#define BITM_PINT_PINSTATE_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 State */
-#define BITM_PINT_PINSTATE_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 State */
-#define BITM_PINT_PINSTATE_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 State */
-#define BITM_PINT_PINSTATE_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 State */
-#define BITM_PINT_PINSTATE_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 State */
-#define BITM_PINT_PINSTATE_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 State */
-#define BITM_PINT_PINSTATE_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 State */
-#define BITM_PINT_PINSTATE_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 State */
-#define BITM_PINT_PINSTATE_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 State */
-#define BITM_PINT_PINSTATE_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 State */
-#define BITM_PINT_PINSTATE_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 State */
-#define BITM_PINT_PINSTATE_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 State */
-#define BITM_PINT_PINSTATE_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 State */
-#define BITM_PINT_PINSTATE_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 State */
-#define BITM_PINT_PINSTATE_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 State */
-#define BITM_PINT_PINSTATE_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 State */
-#define BITM_PINT_PINSTATE_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 State */
-#define BITM_PINT_PINSTATE_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 State */
-#define BITM_PINT_PINSTATE_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 State */
-#define BITM_PINT_PINSTATE_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 State */
-#define BITM_PINT_PINSTATE_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 State */
-#define BITM_PINT_PINSTATE_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 State */
-#define BITM_PINT_PINSTATE_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 State */
-#define BITM_PINT_PINSTATE_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 State */
-#define BITM_PINT_PINSTATE_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 State */
-#define BITM_PINT_PINSTATE_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_LATCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_LATCH_PIQ31                31                               /* Pin Interrupt 31 Latch */
-#define BITP_PINT_LATCH_PIQ30                30                               /* Pin Interrupt 30 Latch */
-#define BITP_PINT_LATCH_PIQ29                29                               /* Pin Interrupt 29 Latch */
-#define BITP_PINT_LATCH_PIQ28                28                               /* Pin Interrupt 28 Latch */
-#define BITP_PINT_LATCH_PIQ27                27                               /* Pin Interrupt 27 Latch */
-#define BITP_PINT_LATCH_PIQ26                26                               /* Pin Interrupt 26 Latch */
-#define BITP_PINT_LATCH_PIQ25                25                               /* Pin Interrupt 25 Latch */
-#define BITP_PINT_LATCH_PIQ24                24                               /* Pin Interrupt 24 Latch */
-#define BITP_PINT_LATCH_PIQ23                23                               /* Pin Interrupt 23 Latch */
-#define BITP_PINT_LATCH_PIQ22                22                               /* Pin Interrupt 22 Latch */
-#define BITP_PINT_LATCH_PIQ21                21                               /* Pin Interrupt 21 Latch */
-#define BITP_PINT_LATCH_PIQ20                20                               /* Pin Interrupt 20 Latch */
-#define BITP_PINT_LATCH_PIQ19                19                               /* Pin Interrupt 19 Latch */
-#define BITP_PINT_LATCH_PIQ18                18                               /* Pin Interrupt 18 Latch */
-#define BITP_PINT_LATCH_PIQ17                17                               /* Pin Interrupt 17 Latch */
-#define BITP_PINT_LATCH_PIQ16                16                               /* Pin Interrupt 16 Latch */
-#define BITP_PINT_LATCH_PIQ15                15                               /* Pin Interrupt 15 Latch */
-#define BITP_PINT_LATCH_PIQ14                14                               /* Pin Interrupt 14 Latch */
-#define BITP_PINT_LATCH_PIQ13                13                               /* Pin Interrupt 13 Latch */
-#define BITP_PINT_LATCH_PIQ12                12                               /* Pin Interrupt 12 Latch */
-#define BITP_PINT_LATCH_PIQ11                11                               /* Pin Interrupt 11 Latch */
-#define BITP_PINT_LATCH_PIQ10                10                               /* Pin Interrupt 10 Latch */
-#define BITP_PINT_LATCH_PIQ9                  9                               /* Pin Interrupt 9 Latch */
-#define BITP_PINT_LATCH_PIQ8                  8                               /* Pin Interrupt 8 Latch */
-#define BITP_PINT_LATCH_PIQ7                  7                               /* Pin Interrupt 7 Latch */
-#define BITP_PINT_LATCH_PIQ6                  6                               /* Pin Interrupt 6 Latch */
-#define BITP_PINT_LATCH_PIQ5                  5                               /* Pin Interrupt 5 Latch */
-#define BITP_PINT_LATCH_PIQ4                  4                               /* Pin Interrupt 4 Latch */
-#define BITP_PINT_LATCH_PIQ3                  3                               /* Pin Interrupt 3 Latch */
-#define BITP_PINT_LATCH_PIQ2                  2                               /* Pin Interrupt 2 Latch */
-#define BITP_PINT_LATCH_PIQ1                  1                               /* Pin Interrupt 1 Latch */
-#define BITP_PINT_LATCH_PIQ0                  0                               /* Pin Interrupt 0 Latch */
-#define BITM_PINT_LATCH_PIQ31                (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Latch */
-#define BITM_PINT_LATCH_PIQ30                (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Latch */
-#define BITM_PINT_LATCH_PIQ29                (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Latch */
-#define BITM_PINT_LATCH_PIQ28                (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Latch */
-#define BITM_PINT_LATCH_PIQ27                (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Latch */
-#define BITM_PINT_LATCH_PIQ26                (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Latch */
-#define BITM_PINT_LATCH_PIQ25                (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Latch */
-#define BITM_PINT_LATCH_PIQ24                (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Latch */
-#define BITM_PINT_LATCH_PIQ23                (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Latch */
-#define BITM_PINT_LATCH_PIQ22                (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Latch */
-#define BITM_PINT_LATCH_PIQ21                (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Latch */
-#define BITM_PINT_LATCH_PIQ20                (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Latch */
-#define BITM_PINT_LATCH_PIQ19                (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Latch */
-#define BITM_PINT_LATCH_PIQ18                (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Latch */
-#define BITM_PINT_LATCH_PIQ17                (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Latch */
-#define BITM_PINT_LATCH_PIQ16                (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Latch */
-#define BITM_PINT_LATCH_PIQ15                (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Latch */
-#define BITM_PINT_LATCH_PIQ14                (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Latch */
-#define BITM_PINT_LATCH_PIQ13                (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Latch */
-#define BITM_PINT_LATCH_PIQ12                (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Latch */
-#define BITM_PINT_LATCH_PIQ11                (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Latch */
-#define BITM_PINT_LATCH_PIQ10                (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Latch */
-#define BITM_PINT_LATCH_PIQ9                 (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Latch */
-#define BITM_PINT_LATCH_PIQ8                 (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Latch */
-#define BITM_PINT_LATCH_PIQ7                 (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Latch */
-#define BITM_PINT_LATCH_PIQ6                 (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Latch */
-#define BITM_PINT_LATCH_PIQ5                 (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Latch */
-#define BITM_PINT_LATCH_PIQ4                 (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Latch */
-#define BITM_PINT_LATCH_PIQ3                 (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Latch */
-#define BITM_PINT_LATCH_PIQ2                 (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Latch */
-#define BITM_PINT_LATCH_PIQ1                 (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Latch */
-#define BITM_PINT_LATCH_PIQ0                 (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Latch */
-
-/* ==================================================
-        Static Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        SMC0
-   ========================= */
-#define REG_SMC0_GCTL                   0xFFC16004         /* SMC0 Grant Control Register */
-#define REG_SMC0_GSTAT                  0xFFC16008         /* SMC0 Grant Status Register */
-#define REG_SMC0_B0CTL                  0xFFC1600C         /* SMC0 Bank 0 Control Register */
-#define REG_SMC0_B0TIM                  0xFFC16010         /* SMC0 Bank 0 Timing Register */
-#define REG_SMC0_B0ETIM                 0xFFC16014         /* SMC0 Bank 0 Extended Timing Register */
-#define REG_SMC0_B1CTL                  0xFFC1601C         /* SMC0 Bank 1 Control Register */
-#define REG_SMC0_B1TIM                  0xFFC16020         /* SMC0 Bank 1 Timing Register */
-#define REG_SMC0_B1ETIM                 0xFFC16024         /* SMC0 Bank 1 Extended Timing Register */
-#define REG_SMC0_B2CTL                  0xFFC1602C         /* SMC0 Bank 2 Control Register */
-#define REG_SMC0_B2TIM                  0xFFC16030         /* SMC0 Bank 2 Timing Register */
-#define REG_SMC0_B2ETIM                 0xFFC16034         /* SMC0 Bank 2 Extended Timing Register */
-#define REG_SMC0_B3CTL                  0xFFC1603C         /* SMC0 Bank 3 Control Register */
-#define REG_SMC0_B3TIM                  0xFFC16040         /* SMC0 Bank 3 Timing Register */
-#define REG_SMC0_B3ETIM                 0xFFC16044         /* SMC0 Bank 3 Extended Timing Register */
-
-/* =========================
-        SMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GCTL_BGDIS                   4                               /* Bus Grant Disable */
-#define BITM_SMC_GCTL_BGDIS                  (_ADI_MSK(0x00000010,uint32_t))  /* Bus Grant Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GSTAT_BGHSTAT                2                               /* Bus Grant Hold Status */
-#define BITP_SMC_GSTAT_BRQSTAT                1                               /* Bus Request Status */
-#define BITP_SMC_GSTAT_BGSTAT                 0                               /* Bus Grant Status */
-#define BITM_SMC_GSTAT_BGHSTAT               (_ADI_MSK(0x00000004,uint32_t))  /* Bus Grant Hold Status */
-#define BITM_SMC_GSTAT_BRQSTAT               (_ADI_MSK(0x00000002,uint32_t))  /* Bus Request Status */
-#define BITM_SMC_GSTAT_BGSTAT                (_ADI_MSK(0x00000001,uint32_t))  /* Bus Grant Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B0CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B0CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B0CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B0CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B0CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B0CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B0CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B0CTL_EN                     0                               /* Bank 0 Enable */
-#define BITM_SMC_B0CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B0CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B0CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B0CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B0CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B0CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B0CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B0CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B0CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B0TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B0TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B0TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B0TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B0TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B0TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B0TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B0TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B0TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B0TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B0TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B0ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B0ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B0ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B0ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B0ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B0ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B0ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B0ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B0ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B1CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B1CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B1CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B1CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B1CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B1CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B1CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B1CTL_EN                     0                               /* Bank 1 Enable */
-#define BITM_SMC_B1CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B1CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B1CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B1CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B1CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B1CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B1CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B1CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B1CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 1 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B1TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B1TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B1TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B1TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B1TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B1TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B1TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B1TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B1TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B1TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B1TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B1ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B1ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B1ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B1ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B1ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B1ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B1ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B1ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B1ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B2CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B2CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B2CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B2CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B2CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B2CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B2CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B2CTL_EN                     0                               /* Bank 2 Enable */
-#define BITM_SMC_B2CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B2CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B2CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B2CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B2CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B2CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B2CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B2CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B2CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 2 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B2TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B2TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B2TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B2TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B2TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B2TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B2TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B2TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B2TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B2TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B2TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B2ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B2ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B2ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B2ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B2ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B2ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B2ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B2ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B2ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B3CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B3CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B3CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B3CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B3CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B3CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B3CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B3CTL_EN                     0                               /* Bank 3 Enable */
-#define BITM_SMC_B3CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B3CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B3CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B3CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B3CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B3CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B3CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B3CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B3CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 3 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B3TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B3TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B3TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B3TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B3TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B3TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B3TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B3TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B3TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B3TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B3TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B3ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B3ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B3ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B3ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B3ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B3ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B3ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B3ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B3ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ==================================================
-        Watch Dog Timer Unit Registers
-   ================================================== */
-
-/* =========================
-        WDOG0
-   ========================= */
-#define REG_WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
-#define REG_WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
-#define REG_WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG1
-   ========================= */
-#define REG_WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
-#define REG_WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
-#define REG_WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WDOG_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WDOG_CTL_WDRO                   15                               /* Watch Dog Rollover */
-#define BITP_WDOG_CTL_WDEN                    4                               /* Watch Dog Enable */
-
-#define BITM_WDOG_CTL_WDRO                   (_ADI_MSK(0x00008000,uint32_t))  /* Watch Dog Rollover */
-#define ENUM_WDOG_CTL_WDTEXP                 (_ADI_MSK(0x00008000,uint32_t))  /* WDRO: WDT has expired */
-#define BITM_WDOG_CTL_WDEN                   (_ADI_MSK(0x00000FF0,uint32_t))  /* Watch Dog Enable */
-
-/* ==================================================
-        EPPI Registers
-   ================================================== */
-
-/* =========================
-        EPPI0
-   ========================= */
-#define REG_EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
-#define REG_EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
-#define REG_EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
-#define REG_EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
-#define REG_EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
-#define REG_EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
-#define REG_EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
-#define REG_EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
-#define REG_EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
-#define REG_EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
-#define REG_EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
-#define REG_EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
-#define REG_EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
-
-/* =========================
-        EPPI1
-   ========================= */
-#define REG_EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
-#define REG_EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
-#define REG_EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
-#define REG_EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
-#define REG_EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
-#define REG_EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
-#define REG_EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
-#define REG_EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
-#define REG_EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
-#define REG_EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
-#define REG_EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
-#define REG_EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
-#define REG_EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
-
-/* =========================
-        EPPI2
-   ========================= */
-#define REG_EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
-#define REG_EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
-#define REG_EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
-#define REG_EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
-#define REG_EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
-#define REG_EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
-#define REG_EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
-#define REG_EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
-#define REG_EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
-#define REG_EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
-#define REG_EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
-#define REG_EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
-#define REG_EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
-
-/* =========================
-        EPPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_STAT_FLD                   15                               /* Current Field Received by EPPI */
-#define BITP_EPPI_STAT_ERRDET                14                               /* Preamble Error Detected */
-#define BITP_EPPI_STAT_PXPERR                 7                               /* PxP Ready Error */
-#define BITP_EPPI_STAT_ERRNCOR                6                               /* Preamble Error Not Corrected */
-#define BITP_EPPI_STAT_FTERRUNDR              5                               /* Frame Track Underflow */
-#define BITP_EPPI_STAT_FTERROVR               4                               /* Frame Track Overflow */
-#define BITP_EPPI_STAT_LTERRUNDR              3                               /* Line Track Underflow */
-#define BITP_EPPI_STAT_LTERROVR               2                               /* Line Track Overflow */
-#define BITP_EPPI_STAT_YFIFOERR               1                               /* Luma FIFO Error */
-#define BITP_EPPI_STAT_CFIFOERR               0                               /* Chroma FIFO Error */
-
-#define BITM_EPPI_STAT_FLD                   (_ADI_MSK(0x00008000,uint32_t))  /* Current Field Received by EPPI */
-#define ENUM_EPPI_STAT_FIELD1                (_ADI_MSK(0x00000000,uint32_t))  /* FLD: Field 1 */
-#define ENUM_EPPI_STAT_FIELD2                (_ADI_MSK(0x00008000,uint32_t))  /* FLD: Field 2 */
-
-#define BITM_EPPI_STAT_ERRDET                (_ADI_MSK(0x00004000,uint32_t))  /* Preamble Error Detected */
-#define ENUM_EPPI_STAT_NO_PRERR              (_ADI_MSK(0x00000000,uint32_t))  /* ERRDET: No preamble error detected */
-#define ENUM_EPPI_STAT_PRERR                 (_ADI_MSK(0x00004000,uint32_t))  /* ERRDET: Preamble error detected */
-#define BITM_EPPI_STAT_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error */
-
-#define BITM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* Preamble Error Not Corrected */
-#define ENUM_EPPI_STAT_NO_ERRNCOR            (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: No uncorrected preamble error has occurred */
-#define ENUM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Preamble error detected but not corrected */
-
-#define BITM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow */
-#define ENUM_EPPI_STAT_NO_FTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow */
-#define ENUM_EPPI_STAT_NO_FTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow */
-#define ENUM_EPPI_STAT_NO_LTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow */
-#define ENUM_EPPI_STAT_NO_LTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* Luma FIFO Error */
-#define ENUM_EPPI_STAT_NO_YFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Error Occurred */
-
-#define BITM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* Chroma FIFO Error */
-#define ENUM_EPPI_STAT_NO_CFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HCNT_VALUE                  0                               /* Horizontal Transfer Count */
-#define BITM_EPPI_HCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HDLY_VALUE                  0                               /* Horizontal Delay Count */
-#define BITM_EPPI_HDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VCNT_VALUE                  0                               /* Vertical Transfer Count */
-#define BITM_EPPI_VCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VDLY_VALUE                  0                               /* Vertical Delay Count */
-#define BITM_EPPI_VDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FRAME                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FRAME_VALUE                 0                               /* Lines Per Frame */
-#define BITM_EPPI_FRAME_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lines Per Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_LINE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_LINE_VALUE                  0                               /* Samples Per Line */
-#define BITM_EPPI_LINE_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Samples Per Line */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CLKDIV                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CLKDIV_VALUE                0                               /* Internal Clock Divider */
-#define BITM_EPPI_CLKDIV_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* Internal Clock Divider */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL_CLKGATEN               31                               /* Clock Gating Enable */
-#define BITP_EPPI_CTL_MUXSEL                 30                               /* MUX Select */
-#define BITP_EPPI_CTL_DMAFINEN               29                               /* DMA Finish Enable */
-#define BITP_EPPI_CTL_DMACFG                 28                               /* One or Two DMA Channels Mode */
-#define BITP_EPPI_CTL_RGBFMTEN               27                               /* RGB Formatting Enable */
-#define BITP_EPPI_CTL_SPLTWRD                26                               /* Split Word */
-#define BITP_EPPI_CTL_SUBSPLTODD             25                               /* Sub-Split Odd Samples */
-#define BITP_EPPI_CTL_SPLTEO                 24                               /* Split Even and Odd Data Samples */
-#define BITP_EPPI_CTL_SWAPEN                 23                               /* Swap Enable */
-#define BITP_EPPI_CTL_PACKEN                 22                               /* Pack/Unpack Enable */
-#define BITP_EPPI_CTL_SKIPEO                 21                               /* Skip Even or Odd */
-#define BITP_EPPI_CTL_SKIPEN                 20                               /* Skip Enable */
-#define BITP_EPPI_CTL_DMIRR                  19                               /* Data Mirroring */
-#define BITP_EPPI_CTL_DLEN                   16                               /* Data Length */
-#define BITP_EPPI_CTL_POLS                   14                               /* Frame Sync Polarity */
-#define BITP_EPPI_CTL_POLC                   12                               /* Clock Polarity */
-#define BITP_EPPI_CTL_SIGNEXT                11                               /* Sign Extension */
-#define BITP_EPPI_CTL_IFSGEN                 10                               /* Internal Frame Sync Generation */
-#define BITP_EPPI_CTL_ICLKGEN                 9                               /* Internal Clock Generation */
-#define BITP_EPPI_CTL_BLANKGEN                8                               /* king Generation (ITU Output Mode) */
-#define BITP_EPPI_CTL_ITUTYPE                 7                               /* ITU Interlace or Progressive */
-#define BITP_EPPI_CTL_FLDSEL                  6                               /* Field Select/Trigger */
-#define BITP_EPPI_CTL_FSCFG                   4                               /* Frame Sync Configuration */
-#define BITP_EPPI_CTL_XFRTYPE                 2                               /* Transfer Type ( Operating Mode) */
-#define BITP_EPPI_CTL_DIR                     1                               /* PPI Direction */
-#define BITP_EPPI_CTL_EN                      0                               /* PPI Enable */
-
-#define BITM_EPPI_CTL_CLKGATEN               (_ADI_MSK(0x80000000,uint32_t))  /* Clock Gating Enable */
-#define ENUM_EPPI_CTL_CLKGATE_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* CLKGATEN: Disable */
-#define ENUM_EPPI_CTL_CLKGATE_EN             (_ADI_MSK(0x80000000,uint32_t))  /* CLKGATEN: Enable */
-
-#define BITM_EPPI_CTL_MUXSEL                 (_ADI_MSK(0x40000000,uint32_t))  /* MUX Select */
-#define ENUM_EPPI_CTL_MUXSEL0                (_ADI_MSK(0x00000000,uint32_t))  /* MUXSEL: Normal Operation */
-#define ENUM_EPPI_CTL_MUXSEL1                (_ADI_MSK(0x40000000,uint32_t))  /* MUXSEL: Multiplexed Operation */
-
-#define BITM_EPPI_CTL_DMAFINEN               (_ADI_MSK(0x20000000,uint32_t))  /* DMA Finish Enable */
-#define ENUM_EPPI_CTL_FINISH_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* DMAFINEN: No Finish Command */
-#define ENUM_EPPI_CTL_FINISH_EN              (_ADI_MSK(0x20000000,uint32_t))  /* DMAFINEN: Enable Send Finish Command */
-
-#define BITM_EPPI_CTL_DMACFG                 (_ADI_MSK(0x10000000,uint32_t))  /* One or Two DMA Channels Mode */
-#define ENUM_EPPI_CTL_DMA1CHAN               (_ADI_MSK(0x00000000,uint32_t))  /* DMACFG: PPI uses one DMA Channel */
-#define ENUM_EPPI_CTL_DMA2CHAN               (_ADI_MSK(0x10000000,uint32_t))  /* DMACFG: PPI uses two DMA Channels */
-
-#define BITM_EPPI_CTL_RGBFMTEN               (_ADI_MSK(0x08000000,uint32_t))  /* RGB Formatting Enable */
-#define ENUM_EPPI_CTL_RGBFMT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RGBFMTEN: Disable RGB Formatted Output */
-#define ENUM_EPPI_CTL_RGBFMT_EN              (_ADI_MSK(0x08000000,uint32_t))  /* RGBFMTEN: Enable RGB Formatted Output */
-
-#define BITM_EPPI_CTL_SPLTWRD                (_ADI_MSK(0x04000000,uint32_t))  /* Split Word */
-#define ENUM_EPPI_CTL_NO_WORDSPLIT           (_ADI_MSK(0x00000000,uint32_t))  /* SPLTWRD: PPI_DATA has (DLEN-1) bits of Y or Cr or Cb */
-#define ENUM_EPPI_CTL_WORDSPLIT              (_ADI_MSK(0x04000000,uint32_t))  /* SPLTWRD: PPI_DATA contains 2 elements per word */
-
-#define BITM_EPPI_CTL_SUBSPLTODD             (_ADI_MSK(0x02000000,uint32_t))  /* Sub-Split Odd Samples */
-#define ENUM_EPPI_CTL_NO_SUBSPLIT            (_ADI_MSK(0x00000000,uint32_t))  /* SUBSPLTODD: Disable */
-#define ENUM_EPPI_CTL_SUBSPLIT_ODD           (_ADI_MSK(0x02000000,uint32_t))  /* SUBSPLTODD: Enable */
-
-#define BITM_EPPI_CTL_SPLTEO                 (_ADI_MSK(0x01000000,uint32_t))  /* Split Even and Odd Data Samples */
-#define ENUM_EPPI_CTL_SPLTEO_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SPLTEO: Do Not Split Samples */
-#define ENUM_EPPI_CTL_SPLTEO_EN              (_ADI_MSK(0x01000000,uint32_t))  /* SPLTEO: Split Even/Odd Samples */
-
-#define BITM_EPPI_CTL_SWAPEN                 (_ADI_MSK(0x00800000,uint32_t))  /* Swap Enable */
-#define ENUM_EPPI_CTL_SWAP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* SWAPEN: Disable */
-#define ENUM_EPPI_CTL_SWAP_EN                (_ADI_MSK(0x00800000,uint32_t))  /* SWAPEN: Enable */
-
-#define BITM_EPPI_CTL_PACKEN                 (_ADI_MSK(0x00400000,uint32_t))  /* Pack/Unpack Enable */
-#define ENUM_EPPI_CTL_PACK_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* PACKEN: Disable */
-#define ENUM_EPPI_CTL_PACK_EN                (_ADI_MSK(0x00400000,uint32_t))  /* PACKEN: Enable */
-
-#define BITM_EPPI_CTL_SKIPEO                 (_ADI_MSK(0x00200000,uint32_t))  /* Skip Even or Odd */
-#define ENUM_EPPI_CTL_SKIPODD                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEO: Skip Odd Samples */
-#define ENUM_EPPI_CTL_SKIPEVEN               (_ADI_MSK(0x00200000,uint32_t))  /* SKIPEO: Skip Even Samples */
-
-#define BITM_EPPI_CTL_SKIPEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Skip Enable */
-#define ENUM_EPPI_CTL_NO_SKIP                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEN: No Samples Skipping */
-#define ENUM_EPPI_CTL_SKIP                   (_ADI_MSK(0x00100000,uint32_t))  /* SKIPEN: Skip Alternate Samples */
-
-#define BITM_EPPI_CTL_DMIRR                  (_ADI_MSK(0x00080000,uint32_t))  /* Data Mirroring */
-#define ENUM_EPPI_CTL_NO_MIRROR              (_ADI_MSK(0x00000000,uint32_t))  /* DMIRR: No Data Mirroring */
-#define ENUM_EPPI_CTL_MIRROR                 (_ADI_MSK(0x00080000,uint32_t))  /* DMIRR: Data Mirroring */
-
-#define BITM_EPPI_CTL_DLEN                   (_ADI_MSK(0x00070000,uint32_t))  /* Data Length */
-#define ENUM_EPPI_CTL_DLEN08                 (_ADI_MSK(0x00000000,uint32_t))  /* DLEN: 8 bits */
-#define ENUM_EPPI_CTL_DLEN10                 (_ADI_MSK(0x00010000,uint32_t))  /* DLEN: 10 bits */
-#define ENUM_EPPI_CTL_DLEN12                 (_ADI_MSK(0x00020000,uint32_t))  /* DLEN: 12 bits */
-#define ENUM_EPPI_CTL_DLEN14                 (_ADI_MSK(0x00030000,uint32_t))  /* DLEN: 14 bits */
-#define ENUM_EPPI_CTL_DLEN16                 (_ADI_MSK(0x00040000,uint32_t))  /* DLEN: 16 bits */
-#define ENUM_EPPI_CTL_DLEN18                 (_ADI_MSK(0x00050000,uint32_t))  /* DLEN: 18 bits */
-#define ENUM_EPPI_CTL_DLEN20                 (_ADI_MSK(0x00060000,uint32_t))  /* DLEN: 20 bits */
-#define ENUM_EPPI_CTL_DLEN24                 (_ADI_MSK(0x00070000,uint32_t))  /* DLEN: 24 bits */
-
-#define BITM_EPPI_CTL_POLS                   (_ADI_MSK(0x0000C000,uint32_t))  /* Frame Sync Polarity */
-#define ENUM_EPPI_CTL_FS1HI_FS2HI            (_ADI_MSK(0x00000000,uint32_t))  /* POLS: FS1 and FS2 are active high */
-#define ENUM_EPPI_CTL_FS1LO_FS2HI            (_ADI_MSK(0x00004000,uint32_t))  /* POLS: FS1 is active low. FS2 is active high */
-#define ENUM_EPPI_CTL_FS1HI_FS2LO            (_ADI_MSK(0x00008000,uint32_t))  /* POLS: FS1 is active high. FS2 is active low */
-#define ENUM_EPPI_CTL_FS1LO_FS2LO            (_ADI_MSK(0x0000C000,uint32_t))  /* POLS: FS1 and FS2 are active low */
-
-#define BITM_EPPI_CTL_POLC                   (_ADI_MSK(0x00003000,uint32_t))  /* Clock Polarity */
-#define ENUM_EPPI_CTL_POLC00                 (_ADI_MSK(0x00000000,uint32_t))  /* POLC: Clock/Sync polarity mode 0 */
-#define ENUM_EPPI_CTL_POLC01                 (_ADI_MSK(0x00001000,uint32_t))  /* POLC: Clock/Sync polarity mode 1 */
-#define ENUM_EPPI_CTL_POLC10                 (_ADI_MSK(0x00002000,uint32_t))  /* POLC: Clock/Sync polarity mode 2 */
-#define ENUM_EPPI_CTL_POLC11                 (_ADI_MSK(0x00003000,uint32_t))  /* POLC: Clock/Sync polarity mode 3 */
-
-#define BITM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* Sign Extension */
-#define ENUM_EPPI_CTL_ZEROFILL               (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Filled */
-#define ENUM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* SIGNEXT: Sign Extended */
-
-#define BITM_EPPI_CTL_IFSGEN                 (_ADI_MSK(0x00000400,uint32_t))  /* Internal Frame Sync Generation */
-#define ENUM_EPPI_CTL_EXTFS                  (_ADI_MSK(0x00000000,uint32_t))  /* IFSGEN: External Frame Sync */
-#define ENUM_EPPI_CTL_INTFS                  (_ADI_MSK(0x00000400,uint32_t))  /* IFSGEN: Internal Frame Sync */
-
-#define BITM_EPPI_CTL_ICLKGEN                (_ADI_MSK(0x00000200,uint32_t))  /* Internal Clock Generation */
-#define ENUM_EPPI_CTL_EXTCLK                 (_ADI_MSK(0x00000000,uint32_t))  /* ICLKGEN: External Clock */
-#define ENUM_EPPI_CTL_INTCLK                 (_ADI_MSK(0x00000200,uint32_t))  /* ICLKGEN: Internal Clock */
-
-#define BITM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* king Generation (ITU Output Mode) */
-#define ENUM_EPPI_CTL_NO_BLANKGEN            (_ADI_MSK(0x00000000,uint32_t))  /* BLANKGEN: Disable */
-#define ENUM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* BLANKGEN: Enable */
-
-#define BITM_EPPI_CTL_ITUTYPE                (_ADI_MSK(0x00000080,uint32_t))  /* ITU Interlace or Progressive */
-#define ENUM_EPPI_CTL_INTERLACED             (_ADI_MSK(0x00000000,uint32_t))  /* ITUTYPE: Interlaced */
-#define ENUM_EPPI_CTL_PROGRESSIVE            (_ADI_MSK(0x00000080,uint32_t))  /* ITUTYPE: Progressive */
-
-#define BITM_EPPI_CTL_FLDSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* Field Select/Trigger */
-#define ENUM_EPPI_CTL_FLDSEL_LO              (_ADI_MSK(0x00000000,uint32_t))  /* FLDSEL: Field Mode 0 */
-#define ENUM_EPPI_CTL_FLDSEL_HI              (_ADI_MSK(0x00000040,uint32_t))  /* FLDSEL: Field Mode 1 */
-
-#define BITM_EPPI_CTL_FSCFG                  (_ADI_MSK(0x00000030,uint32_t))  /* Frame Sync Configuration */
-#define ENUM_EPPI_CTL_SYNC0                  (_ADI_MSK(0x00000000,uint32_t))  /* FSCFG: Sync Mode 0 */
-#define ENUM_EPPI_CTL_SYNC1                  (_ADI_MSK(0x00000010,uint32_t))  /* FSCFG: Sync Mode 1 */
-#define ENUM_EPPI_CTL_SYNC2                  (_ADI_MSK(0x00000020,uint32_t))  /* FSCFG: Sync Mode 2 */
-#define ENUM_EPPI_CTL_SYNC3                  (_ADI_MSK(0x00000030,uint32_t))  /* FSCFG: Sync Mode 3 */
-
-#define BITM_EPPI_CTL_XFRTYPE                (_ADI_MSK(0x0000000C,uint32_t))  /* Transfer Type ( Operating Mode) */
-#define ENUM_EPPI_CTL_ACTIVE656              (_ADI_MSK(0x00000000,uint32_t))  /* XFRTYPE: ITU656 Active Video Only Mode */
-#define ENUM_EPPI_CTL_ENTIRE656              (_ADI_MSK(0x00000004,uint32_t))  /* XFRTYPE: ITU656 Entire Field Mode */
-#define ENUM_EPPI_CTL_VERT656                (_ADI_MSK(0x00000008,uint32_t))  /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define ENUM_EPPI_CTL_NON656                 (_ADI_MSK(0x0000000C,uint32_t))  /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-
-#define BITM_EPPI_CTL_DIR                    (_ADI_MSK(0x00000002,uint32_t))  /* PPI Direction */
-#define ENUM_EPPI_CTL_RXMODE                 (_ADI_MSK(0x00000000,uint32_t))  /* DIR: Receive Mode */
-#define ENUM_EPPI_CTL_TXMODE                 (_ADI_MSK(0x00000002,uint32_t))  /* DIR: Transmit Mode */
-
-#define BITM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* PPI Enable */
-#define ENUM_EPPI_CTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_WLVB                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_WLVB_F2VBAD            24                               /* Field 2 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F2VBBD            16                               /* Field 2 Vertical Blanking Before Data */
-#define BITP_EPPI_FS2_WLVB_F1VBAD             8                               /* Field 1 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F1VBBD             0                               /* Field 1 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F2VBAD            (_ADI_MSK(0xFF000000,uint32_t))  /* Field 2 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F2VBBD            (_ADI_MSK(0x00FF0000,uint32_t))  /* Field 2 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F1VBAD            (_ADI_MSK(0x0000FF00,uint32_t))  /* Field 1 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F1VBBD            (_ADI_MSK(0x000000FF,uint32_t))  /* Field 1 Vertical Blanking Before Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_PALPF                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_PALPF_F2ACT            16                               /* Field 2 Active */
-#define BITP_EPPI_FS2_PALPF_F1ACT             0                               /* Field 1 Active */
-#define BITM_EPPI_FS2_PALPF_F2ACT            (_ADI_MSK(0xFFFF0000,uint32_t))  /* Field 2 Active */
-#define BITM_EPPI_FS2_PALPF_F1ACT            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Field 1 Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_IMSK_PXPERR                 7                               /* PxP Ready Error Interrupt Mask */
-#define BITP_EPPI_IMSK_ERRNCOR                6                               /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERRUNDR              5                               /* Frame Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERROVR               4                               /* Frame Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERRUNDR              3                               /* Line Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERROVR               2                               /* Line Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_YFIFOERR               1                               /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_CFIFOERR               0                               /* CFIFO Underflow or Overflow Error Interrupt Mask */
-
-#define BITM_EPPI_IMSK_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_PXPERR_UMSK           (_ADI_MSK(0x00000000,uint32_t))  /* PXPERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_PXPERR_MSK            (_ADI_MSK(0x00000080,uint32_t))  /* PXPERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define ENUM_EPPI_IMSK_ERRNCOR_UMSK          (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_ERRNCOR_MSK           (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERRUNDR_MSK         (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERROVR_MSK          (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERRUNDR_MSK         (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERROVR_MSK          (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_YFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_YFIFOERR_MSK          (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_CFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_CFIFOERR_MSK          (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Mask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_ODDCLIP                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_ODDCLIP_HIGHODD            16                               /* High Odd Clipping Threshold (Chroma Data) */
-#define BITP_EPPI_ODDCLIP_LOWODD              0                               /* Low Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_HIGHODD            (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_LOWODD             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Odd Clipping Threshold (Chroma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_EVENCLIP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_EVENCLIP_HIGHEVEN          16                               /* High Even Clipping Threshold (Luma Data) */
-#define BITP_EPPI_EVENCLIP_LOWEVEN            0                               /* Low Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_HIGHEVEN          (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_LOWEVEN           (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Even Clipping Threshold (Luma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL2_FS1FINEN               1                               /* HSYNC Finish Enable */
-
-#define BITM_EPPI_CTL2_FS1FINEN              (_ADI_MSK(0x00000002,uint32_t))  /* HSYNC Finish Enable */
-#define ENUM_EPPI_CTL2_FS2FIN_EN             (_ADI_MSK(0x00000000,uint32_t))  /* FS1FINEN: Finish sent after frame RX done */
-#define ENUM_EPPI_CTL2_FS1FIN_EN             (_ADI_MSK(0x00000002,uint32_t))  /* FS1FINEN: Finish sent after frame/line RX done */
-
-/* ==================================================
-        Pulse-Width Modulator Registers
-   ================================================== */
-
-/* =========================
-        PWM0
-   ========================= */
-#define REG_PWM0_CTL                    0xFFC1B000         /* PWM0 Control Register */
-#define REG_PWM0_CHANCFG                0xFFC1B004         /* PWM0 Channel Config Register */
-#define REG_PWM0_TRIPCFG                0xFFC1B008         /* PWM0 Trip Config Register */
-#define REG_PWM0_STAT                   0xFFC1B00C         /* PWM0 Status Register */
-#define REG_PWM0_IMSK                   0xFFC1B010         /* PWM0 Interrupt Mask Register */
-#define REG_PWM0_ILAT                   0xFFC1B014         /* PWM0 Interrupt Latch Register */
-#define REG_PWM0_CHOPCFG                0xFFC1B018         /* PWM0 Chop Configuration Register */
-#define REG_PWM0_DT                     0xFFC1B01C         /* PWM0 Dead Time Register */
-#define REG_PWM0_SYNC_WID               0xFFC1B020         /* PWM0 Sync Pulse Width Register */
-#define REG_PWM0_TM0                    0xFFC1B024         /* PWM0 Timer 0 Period Register */
-#define REG_PWM0_TM1                    0xFFC1B028         /* PWM0 Timer 1 Period Register */
-#define REG_PWM0_TM2                    0xFFC1B02C         /* PWM0 Timer 2 Period Register */
-#define REG_PWM0_TM3                    0xFFC1B030         /* PWM0 Timer 3 Period Register */
-#define REG_PWM0_TM4                    0xFFC1B034         /* PWM0 Timer 4 Period Register */
-#define REG_PWM0_DLYA                   0xFFC1B038         /* PWM0 Channel A Delay Register */
-#define REG_PWM0_DLYB                   0xFFC1B03C         /* PWM0 Channel B Delay Register */
-#define REG_PWM0_DLYC                   0xFFC1B040         /* PWM0 Channel C Delay Register */
-#define REG_PWM0_DLYD                   0xFFC1B044         /* PWM0 Channel D Delay Register */
-#define REG_PWM0_ACTL                   0xFFC1B048         /* PWM0 Channel A Control Register */
-#define REG_PWM0_AH0                    0xFFC1B04C         /* PWM0 Channel A-High Duty-0 Register */
-#define REG_PWM0_AH1                    0xFFC1B050         /* PWM0 Channel A-High Duty-1 Register */
-#define REG_PWM0_AL0                    0xFFC1B05C         /* PWM0 Channel A-Low Duty-0 Register */
-#define REG_PWM0_AL1                    0xFFC1B060         /* PWM0 Channel A-Low Duty-1 Register */
-#define REG_PWM0_BCTL                   0xFFC1B064         /* PWM0 Channel B Control Register */
-#define REG_PWM0_BH0                    0xFFC1B068         /* PWM0 Channel B-High Duty-0 Register */
-#define REG_PWM0_BH1                    0xFFC1B06C         /* PWM0 Channel B-High Duty-1 Register */
-#define REG_PWM0_BL0                    0xFFC1B078         /* PWM0 Channel B-Low Duty-0 Register */
-#define REG_PWM0_BL1                    0xFFC1B07C         /* PWM0 Channel B-Low Duty-1 Register */
-#define REG_PWM0_CCTL                   0xFFC1B080         /* PWM0 Channel C Control Register */
-#define REG_PWM0_CH0                    0xFFC1B084         /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM0_CH1                    0xFFC1B088         /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM0_CL0                    0xFFC1B094         /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM0_CL1                    0xFFC1B098         /* PWM0 Channel C-Low Duty-1 Register */
-#define REG_PWM0_DCTL                   0xFFC1B09C         /* PWM0 Channel D Control Register */
-#define REG_PWM0_DH0                    0xFFC1B0A0         /* PWM0 Channel D-High Duty-0 Register */
-#define REG_PWM0_DH1                    0xFFC1B0A4         /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM0_DL0                    0xFFC1B0B0         /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM0_DL1                    0xFFC1B0B4         /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM1
-   ========================= */
-#define REG_PWM1_CTL                    0xFFC1B400         /* PWM1 Control Register */
-#define REG_PWM1_CHANCFG                0xFFC1B404         /* PWM1 Channel Config Register */
-#define REG_PWM1_TRIPCFG                0xFFC1B408         /* PWM1 Trip Config Register */
-#define REG_PWM1_STAT                   0xFFC1B40C         /* PWM1 Status Register */
-#define REG_PWM1_IMSK                   0xFFC1B410         /* PWM1 Interrupt Mask Register */
-#define REG_PWM1_ILAT                   0xFFC1B414         /* PWM1 Interrupt Latch Register */
-#define REG_PWM1_CHOPCFG                0xFFC1B418         /* PWM1 Chop Configuration Register */
-#define REG_PWM1_DT                     0xFFC1B41C         /* PWM1 Dead Time Register */
-#define REG_PWM1_SYNC_WID               0xFFC1B420         /* PWM1 Sync Pulse Width Register */
-#define REG_PWM1_TM0                    0xFFC1B424         /* PWM1 Timer 0 Period Register */
-#define REG_PWM1_TM1                    0xFFC1B428         /* PWM1 Timer 1 Period Register */
-#define REG_PWM1_TM2                    0xFFC1B42C         /* PWM1 Timer 2 Period Register */
-#define REG_PWM1_TM3                    0xFFC1B430         /* PWM1 Timer 3 Period Register */
-#define REG_PWM1_TM4                    0xFFC1B434         /* PWM1 Timer 4 Period Register */
-#define REG_PWM1_DLYA                   0xFFC1B438         /* PWM1 Channel A Delay Register */
-#define REG_PWM1_DLYB                   0xFFC1B43C         /* PWM1 Channel B Delay Register */
-#define REG_PWM1_DLYC                   0xFFC1B440         /* PWM1 Channel C Delay Register */
-#define REG_PWM1_DLYD                   0xFFC1B444         /* PWM1 Channel D Delay Register */
-#define REG_PWM1_ACTL                   0xFFC1B448         /* PWM1 Channel A Control Register */
-#define REG_PWM1_AH0                    0xFFC1B44C         /* PWM1 Channel A-High Duty-0 Register */
-#define REG_PWM1_AH1                    0xFFC1B450         /* PWM1 Channel A-High Duty-1 Register */
-#define REG_PWM1_AL0                    0xFFC1B45C         /* PWM1 Channel A-Low Duty-0 Register */
-#define REG_PWM1_AL1                    0xFFC1B460         /* PWM1 Channel A-Low Duty-1 Register */
-#define REG_PWM1_BCTL                   0xFFC1B464         /* PWM1 Channel B Control Register */
-#define REG_PWM1_BH0                    0xFFC1B468         /* PWM1 Channel B-High Duty-0 Register */
-#define REG_PWM1_BH1                    0xFFC1B46C         /* PWM1 Channel B-High Duty-1 Register */
-#define REG_PWM1_BL0                    0xFFC1B478         /* PWM1 Channel B-Low Duty-0 Register */
-#define REG_PWM1_BL1                    0xFFC1B47C         /* PWM1 Channel B-Low Duty-1 Register */
-#define REG_PWM1_CCTL                   0xFFC1B480         /* PWM1 Channel C Control Register */
-#define REG_PWM1_CH0                    0xFFC1B484         /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM1_CH1                    0xFFC1B488         /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM1_CL0                    0xFFC1B494         /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM1_CL1                    0xFFC1B498         /* PWM1 Channel C-Low Duty-1 Register */
-#define REG_PWM1_DCTL                   0xFFC1B49C         /* PWM1 Channel D Control Register */
-#define REG_PWM1_DH0                    0xFFC1B4A0         /* PWM1 Channel D-High Duty-0 Register */
-#define REG_PWM1_DH1                    0xFFC1B4A4         /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM1_DL0                    0xFFC1B4B0         /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM1_DL1                    0xFFC1B4B4         /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CTL_INTSYNCREF              18                               /* Timer reference for Internal Sync */
-#define BITP_PWM_CTL_EXTSYNCSEL              17                               /* External Sync Select */
-#define BITP_PWM_CTL_EXTSYNC                 16                               /* External Sync */
-#define BITP_PWM_CTL_DLYDEN                   7                               /* Enable Delay Counter for Channel D */
-#define BITP_PWM_CTL_DLYCEN                   6                               /* Enable Delay Counter for Channel C */
-#define BITP_PWM_CTL_DLYBEN                   5                               /* Enable Delay Counter for Channel B */
-#define BITP_PWM_CTL_DLYAEN                   4                               /* Enable Delay Counter for Channel A */
-#define BITP_PWM_CTL_SWTRIP                   2                               /* Software Trip */
-#define BITP_PWM_CTL_EMURUN                   1                               /* Output Behavior During Emulation Mode */
-#define BITP_PWM_CTL_GLOBEN                   0                               /* Module Enable */
-
-#define BITM_PWM_CTL_INTSYNCREF              (_ADI_MSK(0x001C0000,uint32_t))  /* Timer reference for Internal Sync */
-#define ENUM_PWM_CTL_INTSYNC_0               (_ADI_MSK(0x00000000,uint32_t))  /* INTSYNCREF: PWMTMR0 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_1               (_ADI_MSK(0x00040000,uint32_t))  /* INTSYNCREF: PWMTMR1 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_2               (_ADI_MSK(0x00080000,uint32_t))  /* INTSYNCREF: PWMTMR2 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_3               (_ADI_MSK(0x000C0000,uint32_t))  /* INTSYNCREF: PWMTMR3 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_4               (_ADI_MSK(0x00100000,uint32_t))  /* INTSYNCREF: PWMTMR4 provides sync reference */
-
-#define BITM_PWM_CTL_EXTSYNCSEL              (_ADI_MSK(0x00020000,uint32_t))  /* External Sync Select */
-#define ENUM_PWM_CTL_EXTSYNC_ASYNC           (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNCSEL: Asynchronous External Sync */
-#define ENUM_PWM_CTL_EXTSYNC_SYNC            (_ADI_MSK(0x00020000,uint32_t))  /* EXTSYNCSEL: Synchronous External Sync */
-
-#define BITM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* External Sync */
-#define ENUM_PWM_CTL_INTSYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNC: Internal sync used */
-#define ENUM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* EXTSYNC: External sync used */
-
-#define BITM_PWM_CTL_DLYDEN                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Delay Counter for Channel D */
-#define ENUM_PWM_CTL_DLYD_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYDEN: Disable */
-#define ENUM_PWM_CTL_DLYD_EN                 (_ADI_MSK(0x00000080,uint32_t))  /* DLYDEN: Enable */
-
-#define BITM_PWM_CTL_DLYCEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Delay Counter for Channel C */
-#define ENUM_PWM_CTL_DLYC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYCEN: Disable */
-#define ENUM_PWM_CTL_DLYC_EN                 (_ADI_MSK(0x00000040,uint32_t))  /* DLYCEN: Enable */
-
-#define BITM_PWM_CTL_DLYBEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Delay Counter for Channel B */
-#define ENUM_PWM_CTL_DLYB_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYBEN: Disable */
-#define ENUM_PWM_CTL_DLYB_EN                 (_ADI_MSK(0x00000020,uint32_t))  /* DLYBEN: Enable */
-
-#define BITM_PWM_CTL_DLYAEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable Delay Counter for Channel A */
-#define ENUM_PWM_CTL_DLYA_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYAEN: Disable */
-#define ENUM_PWM_CTL_DLYA_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* DLYAEN: Enable */
-
-#define BITM_PWM_CTL_SWTRIP                  (_ADI_MSK(0x00000004,uint32_t))  /* Software Trip */
-#define ENUM_PWM_CTL_FORCE_TRIP              (_ADI_MSK(0x00000004,uint32_t))  /* SWTRIP: Force a Fault Trip Condition */
-
-#define BITM_PWM_CTL_EMURUN                  (_ADI_MSK(0x00000002,uint32_t))  /* Output Behavior During Emulation Mode */
-#define ENUM_PWM_CTL_EMURUN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* EMURUN: Disable Outputs */
-#define ENUM_PWM_CTL_EMURUN_EN               (_ADI_MSK(0x00000002,uint32_t))  /* EMURUN: Enable Outputs */
-
-#define BITM_PWM_CTL_GLOBEN                  (_ADI_MSK(0x00000001,uint32_t))  /* Module Enable */
-#define ENUM_PWM_CTL_PWM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* GLOBEN: Disable */
-#define ENUM_PWM_CTL_PWM_EN                  (_ADI_MSK(0x00000001,uint32_t))  /* GLOBEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHANCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHANCFG_ENCHOPDL            30                               /* Channel D Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLDL               29                               /* Channel D low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPDH            27                               /* Channel D Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLDH               26                               /* Channel D High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSD             25                               /* Channel D Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRD             24                               /* Channel D Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPCL            22                               /* Channel C Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLCL               21                               /* Channel C low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPCH            19                               /* Channel C Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLCH               18                               /* Channel C High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSC             17                               /* Channel C Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRC             16                               /* Channel C Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPBL            14                               /* Channel B Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLBL               13                               /* Channel B low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPBH            11                               /* Channel B Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLBH               10                               /* Channel B High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSB              9                               /* Channel B Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRB              8                               /* Channel B Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPAL             6                               /* Channel A Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLAL                5                               /* Channel A low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPAH             3                               /* Channel A Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLAH                2                               /* Channel A High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSA              1                               /* Channel A Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRA              0                               /* Channel A Timer Reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPDL            (_ADI_MSK(0x40000000,uint32_t))  /* Channel D Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDL: Disable Chopping Channel D Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_EN           (_ADI_MSK(0x40000000,uint32_t))  /* ENCHOPDL: Enable Chopping Channel D Low Side */
-
-#define BITM_PWM_CHANCFG_POLDL               (_ADI_MSK(0x20000000,uint32_t))  /* Channel D low side Polarity */
-#define ENUM_PWM_CHANCFG_DL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDL: Active Low */
-#define ENUM_PWM_CHANCFG_DL_ACTHI            (_ADI_MSK(0x20000000,uint32_t))  /* POLDL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPDH            (_ADI_MSK(0x08000000,uint32_t))  /* Channel D Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDH: Disable Chopping Channel D High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_EN           (_ADI_MSK(0x08000000,uint32_t))  /* ENCHOPDH: Enable Chopping Channel D High Side */
-
-#define BITM_PWM_CHANCFG_POLDH               (_ADI_MSK(0x04000000,uint32_t))  /* Channel D High side Polarity */
-#define ENUM_PWM_CHANCFG_DH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDH: Active Low */
-#define ENUM_PWM_CHANCFG_DH_ACTHI            (_ADI_MSK(0x04000000,uint32_t))  /* POLDH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSD             (_ADI_MSK(0x02000000,uint32_t))  /* Channel D Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOD_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSD: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOD_IND             (_ADI_MSK(0x02000000,uint32_t))  /* MODELSD: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRD             (_ADI_MSK(0x01000000,uint32_t))  /* Channel D Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRD: PWMTMR0 is Channel D reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_1           (_ADI_MSK(0x01000000,uint32_t))  /* REFTMRD: PWMTMR1 is Channel D reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPCL            (_ADI_MSK(0x00400000,uint32_t))  /* Channel C Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCL: Disable Chopping Channel C Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_EN           (_ADI_MSK(0x00400000,uint32_t))  /* ENCHOPCL: Enable Chopping Channel C Low Side */
-
-#define BITM_PWM_CHANCFG_POLCL               (_ADI_MSK(0x00200000,uint32_t))  /* Channel C low side Polarity */
-#define ENUM_PWM_CHANCFG_CL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCL: Active Low */
-#define ENUM_PWM_CHANCFG_CL_ACTHI            (_ADI_MSK(0x00200000,uint32_t))  /* POLCL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPCH            (_ADI_MSK(0x00080000,uint32_t))  /* Channel C Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCH: Disable Chopping Channel C High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_EN           (_ADI_MSK(0x00080000,uint32_t))  /* ENCHOPCH: Enable Chopping Channel C High Side */
-
-#define BITM_PWM_CHANCFG_POLCH               (_ADI_MSK(0x00040000,uint32_t))  /* Channel C High side Polarity */
-#define ENUM_PWM_CHANCFG_CH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCH: Active Low */
-#define ENUM_PWM_CHANCFG_CH_ACTHI            (_ADI_MSK(0x00040000,uint32_t))  /* POLCH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSC             (_ADI_MSK(0x00020000,uint32_t))  /* Channel C Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOC_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSC: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOC_IND             (_ADI_MSK(0x00020000,uint32_t))  /* MODELSC: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRC             (_ADI_MSK(0x00010000,uint32_t))  /* Channel C Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRC: PWMTMR0 is Channel C reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_1           (_ADI_MSK(0x00010000,uint32_t))  /* REFTMRC: PWMTMR1 is Channel C reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPBL            (_ADI_MSK(0x00004000,uint32_t))  /* Channel B Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBL: Disable Chopping Channel B Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_EN           (_ADI_MSK(0x00004000,uint32_t))  /* ENCHOPBL: Enable Chopping Channel B Low Side */
-
-#define BITM_PWM_CHANCFG_POLBL               (_ADI_MSK(0x00002000,uint32_t))  /* Channel B low side Polarity */
-#define ENUM_PWM_CHANCFG_BL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBL: Active Low */
-#define ENUM_PWM_CHANCFG_BL_ACTHI            (_ADI_MSK(0x00002000,uint32_t))  /* POLBL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPBH            (_ADI_MSK(0x00000800,uint32_t))  /* Channel B Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBH: Disable Chopping Channel B High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_EN           (_ADI_MSK(0x00000800,uint32_t))  /* ENCHOPBH: Enable Chopping Channel B High Side */
-
-#define BITM_PWM_CHANCFG_POLBH               (_ADI_MSK(0x00000400,uint32_t))  /* Channel B High side Polarity */
-#define ENUM_PWM_CHANCFG_BH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBH: Active Low */
-#define ENUM_PWM_CHANCFG_BH_ACTHI            (_ADI_MSK(0x00000400,uint32_t))  /* POLBH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSB             (_ADI_MSK(0x00000200,uint32_t))  /* Channel B Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOB_INV             (_ADI_MSK(0x00000000,uint32_t))  /* MODELSB: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOB_IND             (_ADI_MSK(0x00000200,uint32_t))  /* MODELSB: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRB             (_ADI_MSK(0x00000100,uint32_t))  /* Channel B Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRB: PWMTMR0 is Channel  B reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_1           (_ADI_MSK(0x00000100,uint32_t))  /* REFTMRB: PWMTMR1 is Channel B reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPAL            (_ADI_MSK(0x00000040,uint32_t))  /* Channel A Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAL: Disable Chopping Channel A Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_EN           (_ADI_MSK(0x00000040,uint32_t))  /* ENCHOPAL: Enable Chopping Channel A Low Side */
-
-#define BITM_PWM_CHANCFG_POLAL               (_ADI_MSK(0x00000020,uint32_t))  /* Channel A low side Polarity */
-#define ENUM_PWM_CHANCFG_AL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAL: Active Low */
-#define ENUM_PWM_CHANCFG_AL_ACTHI            (_ADI_MSK(0x00000020,uint32_t))  /* POLAL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPAH            (_ADI_MSK(0x00000008,uint32_t))  /* Channel A Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAH: Disable Chopping Channel A High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_EN           (_ADI_MSK(0x00000008,uint32_t))  /* ENCHOPAH: Enable Chopping Channel A High Side */
-
-#define BITM_PWM_CHANCFG_POLAH               (_ADI_MSK(0x00000004,uint32_t))  /* Channel A High side Polarity */
-#define ENUM_PWM_CHANCFG_AH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAH: Active Low */
-#define ENUM_PWM_CHANCFG_AH_ACTHI            (_ADI_MSK(0x00000004,uint32_t))  /* POLAH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSA             (_ADI_MSK(0x00000002,uint32_t))  /* Channel A Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOA_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSA: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOA_IND             (_ADI_MSK(0x00000002,uint32_t))  /* MODELSA: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRA             (_ADI_MSK(0x00000001,uint32_t))  /* Channel A Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRA: PWMTMR0 is Channel A reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_1           (_ADI_MSK(0x00000001,uint32_t))  /* REFTMRA: PWMTMR1 is Channel A reference */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TRIPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TRIPCFG_MODE1D              27                               /* Mode of TRIP1 for Channel D */
-#define BITP_PWM_TRIPCFG_EN1D                26                               /* Enable TRIP1 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE0D              25                               /* Mode of TRIP0 for Channel D */
-#define BITP_PWM_TRIPCFG_EN0D                24                               /* Enable TRIP0 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE1C              19                               /* Mode of TRIP1 for Channel C */
-#define BITP_PWM_TRIPCFG_EN1C                18                               /* Enable TRIP1 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE0C              17                               /* Mode of TRIP0 for Channel C */
-#define BITP_PWM_TRIPCFG_EN0C                16                               /* Enable TRIP0 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE1B              11                               /* Mode of TRIP1 for Channel B */
-#define BITP_PWM_TRIPCFG_EN1B                10                               /* Enable TRIP1 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE0B               9                               /* Mode of TRIP0 for Channel B */
-#define BITP_PWM_TRIPCFG_EN0B                 8                               /* Enable TRIP0 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE1A               3                               /* Mode of TRIP1 for Channel A */
-#define BITP_PWM_TRIPCFG_EN1A                 2                               /* Enable TRIP1 as a trip source for Channel A */
-#define BITP_PWM_TRIPCFG_MODE0A               1                               /* Mode of TRIP0 for Channel A */
-#define BITP_PWM_TRIPCFG_EN0A                 0                               /* Enable TRIP0 as a trip source for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE1D              (_ADI_MSK(0x08000000,uint32_t))  /* Mode of TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1D: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1D_RSTRT        (_ADI_MSK(0x08000000,uint32_t))  /* MODE1D: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1D                (_ADI_MSK(0x04000000,uint32_t))  /* Enable TRIP1 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1D: Disable TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_EN           (_ADI_MSK(0x04000000,uint32_t))  /* EN1D: Enable TRIP1 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE0D              (_ADI_MSK(0x02000000,uint32_t))  /* Mode of TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0D: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0D_RSTRT        (_ADI_MSK(0x02000000,uint32_t))  /* MODE0D: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0D                (_ADI_MSK(0x01000000,uint32_t))  /* Enable TRIP0 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0D: Disable TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_EN           (_ADI_MSK(0x01000000,uint32_t))  /* EN0D: Enable TRIP0 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE1C              (_ADI_MSK(0x00080000,uint32_t))  /* Mode of TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1C: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1C_RSTRT        (_ADI_MSK(0x00080000,uint32_t))  /* MODE1C: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1C                (_ADI_MSK(0x00040000,uint32_t))  /* Enable TRIP1 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1C: Disable TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_EN           (_ADI_MSK(0x00040000,uint32_t))  /* EN1C: Enable TRIP1 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE0C              (_ADI_MSK(0x00020000,uint32_t))  /* Mode of TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0C: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0C_RSTRT        (_ADI_MSK(0x00020000,uint32_t))  /* MODE0C: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0C                (_ADI_MSK(0x00010000,uint32_t))  /* Enable TRIP0 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0C: Disable TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_EN           (_ADI_MSK(0x00010000,uint32_t))  /* EN0C: Enable TRIP0 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE1B              (_ADI_MSK(0x00000800,uint32_t))  /* Mode of TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1B: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1B_RSTRT        (_ADI_MSK(0x00000800,uint32_t))  /* MODE1B: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1B                (_ADI_MSK(0x00000400,uint32_t))  /* Enable TRIP1 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1B: Disable TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_EN           (_ADI_MSK(0x00000400,uint32_t))  /* EN1B: Enable TRIP1 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE0B              (_ADI_MSK(0x00000200,uint32_t))  /* Mode of TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0B: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0B_RSTRT        (_ADI_MSK(0x00000200,uint32_t))  /* MODE0B: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0B                (_ADI_MSK(0x00000100,uint32_t))  /* Enable TRIP0 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0B: Disable TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_EN           (_ADI_MSK(0x00000100,uint32_t))  /* EN0B: Enable TRIP0 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE1A              (_ADI_MSK(0x00000008,uint32_t))  /* Mode of TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1A: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1A_RSTRT        (_ADI_MSK(0x00000008,uint32_t))  /* MODE1A: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1A                (_ADI_MSK(0x00000004,uint32_t))  /* Enable TRIP1 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1A: Disable TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_EN           (_ADI_MSK(0x00000004,uint32_t))  /* EN1A: Enable TRIP1 for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE0A              (_ADI_MSK(0x00000002,uint32_t))  /* Mode of TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0A: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0A_RSTRT        (_ADI_MSK(0x00000002,uint32_t))  /* MODE0A: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0A                (_ADI_MSK(0x00000001,uint32_t))  /* Enable TRIP0 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0A: Disable TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_EN           (_ADI_MSK(0x00000001,uint32_t))  /* EN0A: Enable TRIP0 for Channel A */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_STAT_TMR4PHASE              28                               /* PWMTMR4 Phase Status */
-#define BITP_PWM_STAT_TMR3PHASE              27                               /* PWMTMR3 Phase Status */
-#define BITP_PWM_STAT_TMR2PHASE              26                               /* PWMTMR2 Phase Status */
-#define BITP_PWM_STAT_TMR1PHASE              25                               /* PWMTMR1 Phase Status */
-#define BITP_PWM_STAT_TMR0PHASE              24                               /* PWMTMR0 Phase Status */
-#define BITP_PWM_STAT_TMR4PER                20                               /* PWMTMR4 Period Boundary Status */
-#define BITP_PWM_STAT_TMR3PER                19                               /* PWMTMR3 Period Boundary Status */
-#define BITP_PWM_STAT_TMR2PER                18                               /* PWMTMR2 Period Boundary Status */
-#define BITP_PWM_STAT_TMR1PER                17                               /* PWMTMR1 Period Boundary Status */
-#define BITP_PWM_STAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Status */
-#define BITP_PWM_STAT_SRTRIPD                11                               /* Self-Restart Trip Status for Channel D */
-#define BITP_PWM_STAT_FLTTRIPD               10                               /* Fault Trip Status for Channel D */
-#define BITP_PWM_STAT_SRTRIPC                 9                               /* Self-Restart Trip Status for Channel C */
-#define BITP_PWM_STAT_FLTTRIPC                8                               /* Fault Trip Status for Channel C */
-#define BITP_PWM_STAT_SRTRIPB                 7                               /* Self-Restart Trip Status for Channel B */
-#define BITP_PWM_STAT_FLTTRIPB                6                               /* Fault Trip Status for Channel B */
-#define BITP_PWM_STAT_SRTRIPA                 5                               /* Self-Restart Trip Status for Channel A */
-#define BITP_PWM_STAT_FLTTRIPA                4                               /* Fault Trip Status for Channel A */
-#define BITP_PWM_STAT_RAWTRIP1                3                               /* Raw Trip 1 Status */
-#define BITP_PWM_STAT_RAWTRIP0                2                               /* Raw Trip 0 Status */
-#define BITP_PWM_STAT_TRIP1                   1                               /* Status bit set when TRIP1 is active low */
-#define BITP_PWM_STAT_TRIP0                   0                               /* Status bit set when TRIP0 is active low */
-
-#define BITM_PWM_STAT_TMR4PHASE              (_ADI_MSK(0x10000000,uint32_t))  /* PWMTMR4 Phase Status */
-#define ENUM_PWM_STAT_TMR4PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR4PH2                (_ADI_MSK(0x10000000,uint32_t))  /* TMR4PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR3PHASE              (_ADI_MSK(0x08000000,uint32_t))  /* PWMTMR3 Phase Status */
-#define ENUM_PWM_STAT_TMR3PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR3PH2                (_ADI_MSK(0x08000000,uint32_t))  /* TMR3PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR2PHASE              (_ADI_MSK(0x04000000,uint32_t))  /* PWMTMR2 Phase Status */
-#define ENUM_PWM_STAT_TMR2PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR2PH2                (_ADI_MSK(0x04000000,uint32_t))  /* TMR2PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR1PHASE              (_ADI_MSK(0x02000000,uint32_t))  /* PWMTMR1 Phase Status */
-#define ENUM_PWM_STAT_TMR1PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR1PH2                (_ADI_MSK(0x02000000,uint32_t))  /* TMR1PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR0PHASE              (_ADI_MSK(0x01000000,uint32_t))  /* PWMTMR0 Phase Status */
-#define ENUM_PWM_STAT_TMR0PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR0PH2                (_ADI_MSK(0x01000000,uint32_t))  /* TMR0PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER4               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary not reached */
-#define ENUM_PWM_STAT_PER4                   (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary reached */
-
-#define BITM_PWM_STAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER3               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary not reached */
-#define ENUM_PWM_STAT_PER3                   (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary reached */
-
-#define BITM_PWM_STAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER2               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary not reached */
-#define ENUM_PWM_STAT_PER2                   (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary reached */
-
-#define BITM_PWM_STAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER1               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary not reached */
-#define ENUM_PWM_STAT_PER1                   (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary reached */
-
-#define BITM_PWM_STAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER0               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary not reached */
-#define ENUM_PWM_STAT_PER0                   (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary reached */
-
-#define BITM_PWM_STAT_SRTRIPD                (_ADI_MSK(0x00000800,uint32_t))  /* Self-Restart Trip Status for Channel D */
-#define ENUM_PWM_STAT_SRD_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRD_TRIP               (_ADI_MSK(0x00000800,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPD               (_ADI_MSK(0x00000400,uint32_t))  /* Fault Trip Status for Channel D */
-#define ENUM_PWM_STAT_FLTD_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTD_TRIP              (_ADI_MSK(0x00000400,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPC                (_ADI_MSK(0x00000200,uint32_t))  /* Self-Restart Trip Status for Channel C */
-#define ENUM_PWM_STAT_SRC_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRC_TRIP               (_ADI_MSK(0x00000200,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPC               (_ADI_MSK(0x00000100,uint32_t))  /* Fault Trip Status for Channel C */
-#define ENUM_PWM_STAT_FLTC_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTC_TRIP              (_ADI_MSK(0x00000100,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPB                (_ADI_MSK(0x00000080,uint32_t))  /* Self-Restart Trip Status for Channel B */
-#define ENUM_PWM_STAT_SRB_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRB_TRIP               (_ADI_MSK(0x00000080,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPB               (_ADI_MSK(0x00000040,uint32_t))  /* Fault Trip Status for Channel B */
-#define ENUM_PWM_STAT_FLTB_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPB: Channel B Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTB_TRIP              (_ADI_MSK(0x00000040,uint32_t))  /* FLTTRIPB: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPA                (_ADI_MSK(0x00000020,uint32_t))  /* Self-Restart Trip Status for Channel A */
-#define ENUM_PWM_STAT_SRA_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRA_TRIP               (_ADI_MSK(0x00000020,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPA               (_ADI_MSK(0x00000010,uint32_t))  /* Fault Trip Status for Channel A */
-#define ENUM_PWM_STAT_FLTA_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTA_TRIP              (_ADI_MSK(0x00000010,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_RAWTRIP1               (_ADI_MSK(0x00000008,uint32_t))  /* Raw Trip 1 Status */
-#define ENUM_PWM_STAT_TRIP1LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP1: TRIP1 Level is Low */
-#define ENUM_PWM_STAT_TRIP1LVL_HI            (_ADI_MSK(0x00000008,uint32_t))  /* RAWTRIP1: TRIP1 Level is High */
-
-#define BITM_PWM_STAT_RAWTRIP0               (_ADI_MSK(0x00000004,uint32_t))  /* Raw Trip 0 Status */
-#define ENUM_PWM_STAT_TRIP0LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP0: TRIP0 Level is Low */
-#define ENUM_PWM_STAT_TRIP0LVL_HI            (_ADI_MSK(0x00000004,uint32_t))  /* RAWTRIP0: TRIP0 Level is High */
-
-#define BITM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* Status bit set when TRIP1 is active low */
-#define ENUM_PWM_STAT_NO_TRIP1               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: TRIP1 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: TRIP1 status is "tripped" (active low) */
-
-#define BITM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* Status bit set when TRIP0 is active low */
-#define ENUM_PWM_STAT_NO_TRIP0               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: TRIP0 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: TRIP0 status is "tripped" (active low) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_IMSK_TMR4PER                20                               /* PWMTMR4 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR3PER                19                               /* PWMTMR3 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR2PER                18                               /* PWMTMR2 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR1PER                17                               /* PWMTMR1 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP1                   1                               /* TRIP1 Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP0                   0                               /* TRIP0 Interrupt Enable */
-
-#define BITM_PWM_IMSK_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER4_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: Mask PWMTMR4 Period Interrupt */
-#define ENUM_PWM_IMSK_PER4_UMSK              (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Unmask PWMTMR4 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER3_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: Mask PWMTMR3 Period Interrupt */
-#define ENUM_PWM_IMSK_PER3_UMSK              (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Unmask PWMTMR3 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER2_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: Mask PWMTMR2 Period Interrupt */
-#define ENUM_PWM_IMSK_PER2_UMSK              (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Unmask PWMTMR2 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER1_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: Mask PWMTMR1 Period Interrupt */
-#define ENUM_PWM_IMSK_PER1_UMSK              (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Unmask PWMTMR1 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER0_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: Mask PWMTMR0 Period Interrupt */
-#define ENUM_PWM_IMSK_PER0_UMSK              (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Unmask PWMTMR0 Period Interrupt */
-
-#define BITM_PWM_IMSK_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP1_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: Mask TRIP1 Interrupt */
-#define ENUM_PWM_IMSK_TRIP1_UMSK             (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Unmask TRIP1 Interrupt */
-
-#define BITM_PWM_IMSK_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP0_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: Mask TRIP0 Interrupt */
-#define ENUM_PWM_IMSK_TRIP0_UMSK             (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Unmask TRIP0 Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ILAT_TMR4PER                20                               /* PWMTMR4 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR3PER                19                               /* PWMTMR3 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR2PER                18                               /* PWMTMR2 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR1PER                17                               /* PWMTMR1 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP1                   1                               /* TRIP1 Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP0                   0                               /* TRIP0 Interrupt Latched Status */
-
-#define BITM_PWM_ILAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER4_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER4_INTHI             (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER3_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER3_INTHI             (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER2_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER2_INTHI             (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER1_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER1_INTHI             (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define ENUM_PWM_ILAT_PER0_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER0_INTHI             (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP1_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP1_INTHI            (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP0_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP0_INTHI            (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Interrupt Latched */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHOPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHOPCFG_VALUE                0                               /* Gate Chopping Divisor */
-#define BITM_PWM_CHOPCFG_VALUE               (_ADI_MSK(0x000000FF,uint32_t))  /* Gate Chopping Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DT_VALUE                     0                               /* Dead Time */
-#define BITM_PWM_DT_VALUE                    (_ADI_MSK(0x000003FF,uint32_t))  /* Dead Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_SYNC_WID                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_SYNC_WID_VALUE               0                               /* Sync Pulse Width */
-#define BITM_PWM_SYNC_WID_VALUE              (_ADI_MSK(0x000003FF,uint32_t))  /* Sync Pulse Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM0_VALUE                    0                               /* Timer PWMTMR0 Period Value */
-#define BITM_PWM_TM0_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR0 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM1_VALUE                    0                               /* Timer PWMTMR1 Period Value */
-#define BITM_PWM_TM1_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR1 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM2_VALUE                    0                               /* Timer PWMTMR2 Period Value */
-#define BITM_PWM_TM2_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR2 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM3                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM3_VALUE                    0                               /* Timer PWMTMR3 Period Value */
-#define BITM_PWM_TM3_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR3 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM4                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM4_VALUE                    0                               /* Timer PWMTMR4 Period Value */
-#define BITM_PWM_TM4_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR4 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYA                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYA_VALUE                   0                               /* Channel A Delay Value */
-#define BITM_PWM_DLYA_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel A Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYB                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYB_VALUE                   0                               /* Channel B Delay Value */
-#define BITM_PWM_DLYB_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel B Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYC                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYC_VALUE                   0                               /* Channel C Delay Value */
-#define BITM_PWM_DLYC_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel C Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYD_VALUE                   0                               /* Channel D Delay Value */
-#define BITM_PWM_DLYD_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel D Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ACTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ACTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_ACTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_ACTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_ACTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_ACTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-#define BITM_PWM_ACTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define ENUM_PWM_SYM_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODELO: Symmetrical */
-#define ENUM_PWM_ASYM_LO                     (_ADI_MSK(0x00000400,uint32_t))  /* PULSEMODELO: Asymmetrical */
-#define ENUM_PWM_LEFT_LO                     (_ADI_MSK(0x00000800,uint32_t))  /* PULSEMODELO: Left Half */
-#define ENUM_PWM_RIGHT_LO                    (_ADI_MSK(0x00000C00,uint32_t))  /* PULSEMODELO: Right Half */
-
-#define BITM_PWM_ACTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define ENUM_PWM_SYM_HI                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODEHI: Symmetrical */
-#define ENUM_PWM_ASYM_HI                     (_ADI_MSK(0x00000100,uint32_t))  /* PULSEMODEHI: Asymmetrical */
-#define ENUM_PWM_LEFT_HI                     (_ADI_MSK(0x00000200,uint32_t))  /* PULSEMODEHI: Left Half */
-#define ENUM_PWM_RIGHT_HI                    (_ADI_MSK(0x00000300,uint32_t))  /* PULSEMODEHI: Right Half */
-
-#define BITM_PWM_ACTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define ENUM_PWM_XOVR_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* XOVR: Disable Crossover */
-#define ENUM_PWM_XOVR_EN                     (_ADI_MSK(0x00000004,uint32_t))  /* XOVR: Enable Crossover */
-
-#define BITM_PWM_ACTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define ENUM_PWM_LO_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISLO: Disable Low Side Output */
-#define ENUM_PWM_LO_EN                       (_ADI_MSK(0x00000002,uint32_t))  /* DISLO: Enable Low Side Output */
-
-#define BITM_PWM_ACTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-#define ENUM_PWM_HI_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISHI: Disable High Side Output */
-#define ENUM_PWM_HI_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* DISHI: Enable High Side Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_BCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_BCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_BCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_BCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_BCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_BCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_BCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_BCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_BCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_BCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_CCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_CCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_CCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_CCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_CCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_CCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_CCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_CCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_CCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_CCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_DCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_DCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_DCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_DCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_DCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_DCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_DCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_DCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_DCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_DCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ==================================================
-        Video Subsystem Registers Registers
-   ================================================== */
-
-/* =========================
-        VID0
-   ========================= */
-#define REG_VID0_CONN                   0xFFC1D000         /* VID0 Video Subsystem Connect Register */
-
-/* =========================
-        VID
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        VID_CONN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_VID_CONN_PPI2BCAST              23                               /* PPI_2 Broadcast Mode */
-#define BITP_VID_CONN_PPI1BCAST              22                               /* PPI_1 Broadcast Mode */
-#define BITP_VID_CONN_PPI0BCAST              21                               /* PPI_0 Broadcast Mode */
-#define BITP_VID_CONN_PPI2TX                 16                               /* PPI_2_TX Connectivity */
-#define BITP_VID_CONN_PPI1TX                 12                               /* PPI_1_TX Connectivity */
-#define BITP_VID_CONN_PPI0TX                  8                               /* PPI_0_TX Connectivity */
-#define BITM_VID_CONN_PPI2BCAST              (_ADI_MSK(0x00800000,uint32_t))  /* PPI_2 Broadcast Mode */
-#define BITM_VID_CONN_PPI1BCAST              (_ADI_MSK(0x00400000,uint32_t))  /* PPI_1 Broadcast Mode */
-#define BITM_VID_CONN_PPI0BCAST              (_ADI_MSK(0x00200000,uint32_t))  /* PPI_0 Broadcast Mode */
-#define BITM_VID_CONN_PPI2TX                 (_ADI_MSK(0x000F0000,uint32_t))  /* PPI_2_TX Connectivity */
-#define BITM_VID_CONN_PPI1TX                 (_ADI_MSK(0x0000F000,uint32_t))  /* PPI_1_TX Connectivity */
-#define BITM_VID_CONN_PPI0TX                 (_ADI_MSK(0x00000F00,uint32_t))  /* PPI_0_TX Connectivity */
-
-/* ==================================================
-        System Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        SWU0
-   ========================= */
-#define REG_SWU0_GCTL                   0xFFC1E000         /* SWU0 Global Control Register */
-#define REG_SWU0_GSTAT                  0xFFC1E004         /* SWU0 Global Status Register */
-#define REG_SWU0_CTL0                   0xFFC1E010         /* SWU0 Control Register n */
-#define REG_SWU0_CTL1                   0xFFC1E030         /* SWU0 Control Register n */
-#define REG_SWU0_CTL2                   0xFFC1E050         /* SWU0 Control Register n */
-#define REG_SWU0_CTL3                   0xFFC1E070         /* SWU0 Control Register n */
-#define REG_SWU0_LA0                    0xFFC1E014         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA1                    0xFFC1E034         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA2                    0xFFC1E054         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA3                    0xFFC1E074         /* SWU0 Lower Address Register n */
-#define REG_SWU0_UA0                    0xFFC1E018         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA1                    0xFFC1E038         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA2                    0xFFC1E058         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA3                    0xFFC1E078         /* SWU0 Upper Address Register n */
-#define REG_SWU0_ID0                    0xFFC1E01C         /* SWU0 ID Register n */
-#define REG_SWU0_ID1                    0xFFC1E03C         /* SWU0 ID Register n */
-#define REG_SWU0_ID2                    0xFFC1E05C         /* SWU0 ID Register n */
-#define REG_SWU0_ID3                    0xFFC1E07C         /* SWU0 ID Register n */
-#define REG_SWU0_CNT0                   0xFFC1E020         /* SWU0 Count Register n */
-#define REG_SWU0_CNT1                   0xFFC1E040         /* SWU0 Count Register n */
-#define REG_SWU0_CNT2                   0xFFC1E060         /* SWU0 Count Register n */
-#define REG_SWU0_CNT3                   0xFFC1E080         /* SWU0 Count Register n */
-#define REG_SWU0_TARG0                  0xFFC1E024         /* SWU0 Target Register n */
-#define REG_SWU0_TARG1                  0xFFC1E044         /* SWU0 Target Register n */
-#define REG_SWU0_TARG2                  0xFFC1E064         /* SWU0 Target Register n */
-#define REG_SWU0_TARG3                  0xFFC1E084         /* SWU0 Target Register n */
-#define REG_SWU0_HIST0                  0xFFC1E028         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST1                  0xFFC1E048         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST2                  0xFFC1E068         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST3                  0xFFC1E088         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_CUR0                   0xFFC1E02C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR1                   0xFFC1E04C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR2                   0xFFC1E06C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR3                   0xFFC1E08C         /* SWU0 Current Register n */
-
-/* =========================
-        SWU1
-   ========================= */
-#define REG_SWU1_GCTL                   0xFFCAB000         /* SWU1 Global Control Register */
-#define REG_SWU1_GSTAT                  0xFFCAB004         /* SWU1 Global Status Register */
-#define REG_SWU1_CTL0                   0xFFCAB010         /* SWU1 Control Register n */
-#define REG_SWU1_CTL1                   0xFFCAB030         /* SWU1 Control Register n */
-#define REG_SWU1_CTL2                   0xFFCAB050         /* SWU1 Control Register n */
-#define REG_SWU1_CTL3                   0xFFCAB070         /* SWU1 Control Register n */
-#define REG_SWU1_LA0                    0xFFCAB014         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA1                    0xFFCAB034         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA2                    0xFFCAB054         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA3                    0xFFCAB074         /* SWU1 Lower Address Register n */
-#define REG_SWU1_UA0                    0xFFCAB018         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA1                    0xFFCAB038         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA2                    0xFFCAB058         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA3                    0xFFCAB078         /* SWU1 Upper Address Register n */
-#define REG_SWU1_ID0                    0xFFCAB01C         /* SWU1 ID Register n */
-#define REG_SWU1_ID1                    0xFFCAB03C         /* SWU1 ID Register n */
-#define REG_SWU1_ID2                    0xFFCAB05C         /* SWU1 ID Register n */
-#define REG_SWU1_ID3                    0xFFCAB07C         /* SWU1 ID Register n */
-#define REG_SWU1_CNT0                   0xFFCAB020         /* SWU1 Count Register n */
-#define REG_SWU1_CNT1                   0xFFCAB040         /* SWU1 Count Register n */
-#define REG_SWU1_CNT2                   0xFFCAB060         /* SWU1 Count Register n */
-#define REG_SWU1_CNT3                   0xFFCAB080         /* SWU1 Count Register n */
-#define REG_SWU1_TARG0                  0xFFCAB024         /* SWU1 Target Register n */
-#define REG_SWU1_TARG1                  0xFFCAB044         /* SWU1 Target Register n */
-#define REG_SWU1_TARG2                  0xFFCAB064         /* SWU1 Target Register n */
-#define REG_SWU1_TARG3                  0xFFCAB084         /* SWU1 Target Register n */
-#define REG_SWU1_HIST0                  0xFFCAB028         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST1                  0xFFCAB048         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST2                  0xFFCAB068         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST3                  0xFFCAB088         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_CUR0                   0xFFCAB02C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR1                   0xFFCAB04C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR2                   0xFFCAB06C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR3                   0xFFCAB08C         /* SWU1 Current Register n */
-
-/* =========================
-        SWU2
-   ========================= */
-#define REG_SWU2_GCTL                   0xFFCAC000         /* SWU2 Global Control Register */
-#define REG_SWU2_GSTAT                  0xFFCAC004         /* SWU2 Global Status Register */
-#define REG_SWU2_CTL0                   0xFFCAC010         /* SWU2 Control Register n */
-#define REG_SWU2_CTL1                   0xFFCAC030         /* SWU2 Control Register n */
-#define REG_SWU2_CTL2                   0xFFCAC050         /* SWU2 Control Register n */
-#define REG_SWU2_CTL3                   0xFFCAC070         /* SWU2 Control Register n */
-#define REG_SWU2_LA0                    0xFFCAC014         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA1                    0xFFCAC034         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA2                    0xFFCAC054         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA3                    0xFFCAC074         /* SWU2 Lower Address Register n */
-#define REG_SWU2_UA0                    0xFFCAC018         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA1                    0xFFCAC038         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA2                    0xFFCAC058         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA3                    0xFFCAC078         /* SWU2 Upper Address Register n */
-#define REG_SWU2_ID0                    0xFFCAC01C         /* SWU2 ID Register n */
-#define REG_SWU2_ID1                    0xFFCAC03C         /* SWU2 ID Register n */
-#define REG_SWU2_ID2                    0xFFCAC05C         /* SWU2 ID Register n */
-#define REG_SWU2_ID3                    0xFFCAC07C         /* SWU2 ID Register n */
-#define REG_SWU2_CNT0                   0xFFCAC020         /* SWU2 Count Register n */
-#define REG_SWU2_CNT1                   0xFFCAC040         /* SWU2 Count Register n */
-#define REG_SWU2_CNT2                   0xFFCAC060         /* SWU2 Count Register n */
-#define REG_SWU2_CNT3                   0xFFCAC080         /* SWU2 Count Register n */
-#define REG_SWU2_TARG0                  0xFFCAC024         /* SWU2 Target Register n */
-#define REG_SWU2_TARG1                  0xFFCAC044         /* SWU2 Target Register n */
-#define REG_SWU2_TARG2                  0xFFCAC064         /* SWU2 Target Register n */
-#define REG_SWU2_TARG3                  0xFFCAC084         /* SWU2 Target Register n */
-#define REG_SWU2_HIST0                  0xFFCAC028         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST1                  0xFFCAC048         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST2                  0xFFCAC068         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST3                  0xFFCAC088         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_CUR0                   0xFFCAC02C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR1                   0xFFCAC04C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR2                   0xFFCAC06C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR3                   0xFFCAC08C         /* SWU2 Current Register n */
-
-/* =========================
-        SWU3
-   ========================= */
-#define REG_SWU3_GCTL                   0xFFCAD000         /* SWU3 Global Control Register */
-#define REG_SWU3_GSTAT                  0xFFCAD004         /* SWU3 Global Status Register */
-#define REG_SWU3_CTL0                   0xFFCAD010         /* SWU3 Control Register n */
-#define REG_SWU3_CTL1                   0xFFCAD030         /* SWU3 Control Register n */
-#define REG_SWU3_CTL2                   0xFFCAD050         /* SWU3 Control Register n */
-#define REG_SWU3_CTL3                   0xFFCAD070         /* SWU3 Control Register n */
-#define REG_SWU3_LA0                    0xFFCAD014         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA1                    0xFFCAD034         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA2                    0xFFCAD054         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA3                    0xFFCAD074         /* SWU3 Lower Address Register n */
-#define REG_SWU3_UA0                    0xFFCAD018         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA1                    0xFFCAD038         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA2                    0xFFCAD058         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA3                    0xFFCAD078         /* SWU3 Upper Address Register n */
-#define REG_SWU3_ID0                    0xFFCAD01C         /* SWU3 ID Register n */
-#define REG_SWU3_ID1                    0xFFCAD03C         /* SWU3 ID Register n */
-#define REG_SWU3_ID2                    0xFFCAD05C         /* SWU3 ID Register n */
-#define REG_SWU3_ID3                    0xFFCAD07C         /* SWU3 ID Register n */
-#define REG_SWU3_CNT0                   0xFFCAD020         /* SWU3 Count Register n */
-#define REG_SWU3_CNT1                   0xFFCAD040         /* SWU3 Count Register n */
-#define REG_SWU3_CNT2                   0xFFCAD060         /* SWU3 Count Register n */
-#define REG_SWU3_CNT3                   0xFFCAD080         /* SWU3 Count Register n */
-#define REG_SWU3_TARG0                  0xFFCAD024         /* SWU3 Target Register n */
-#define REG_SWU3_TARG1                  0xFFCAD044         /* SWU3 Target Register n */
-#define REG_SWU3_TARG2                  0xFFCAD064         /* SWU3 Target Register n */
-#define REG_SWU3_TARG3                  0xFFCAD084         /* SWU3 Target Register n */
-#define REG_SWU3_HIST0                  0xFFCAD028         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST1                  0xFFCAD048         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST2                  0xFFCAD068         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST3                  0xFFCAD088         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_CUR0                   0xFFCAD02C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR1                   0xFFCAD04C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR2                   0xFFCAD06C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR3                   0xFFCAD08C         /* SWU3 Current Register n */
-
-/* =========================
-        SWU4
-   ========================= */
-#define REG_SWU4_GCTL                   0xFFCAE000         /* SWU4 Global Control Register */
-#define REG_SWU4_GSTAT                  0xFFCAE004         /* SWU4 Global Status Register */
-#define REG_SWU4_CTL0                   0xFFCAE010         /* SWU4 Control Register n */
-#define REG_SWU4_CTL1                   0xFFCAE030         /* SWU4 Control Register n */
-#define REG_SWU4_CTL2                   0xFFCAE050         /* SWU4 Control Register n */
-#define REG_SWU4_CTL3                   0xFFCAE070         /* SWU4 Control Register n */
-#define REG_SWU4_LA0                    0xFFCAE014         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA1                    0xFFCAE034         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA2                    0xFFCAE054         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA3                    0xFFCAE074         /* SWU4 Lower Address Register n */
-#define REG_SWU4_UA0                    0xFFCAE018         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA1                    0xFFCAE038         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA2                    0xFFCAE058         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA3                    0xFFCAE078         /* SWU4 Upper Address Register n */
-#define REG_SWU4_ID0                    0xFFCAE01C         /* SWU4 ID Register n */
-#define REG_SWU4_ID1                    0xFFCAE03C         /* SWU4 ID Register n */
-#define REG_SWU4_ID2                    0xFFCAE05C         /* SWU4 ID Register n */
-#define REG_SWU4_ID3                    0xFFCAE07C         /* SWU4 ID Register n */
-#define REG_SWU4_CNT0                   0xFFCAE020         /* SWU4 Count Register n */
-#define REG_SWU4_CNT1                   0xFFCAE040         /* SWU4 Count Register n */
-#define REG_SWU4_CNT2                   0xFFCAE060         /* SWU4 Count Register n */
-#define REG_SWU4_CNT3                   0xFFCAE080         /* SWU4 Count Register n */
-#define REG_SWU4_TARG0                  0xFFCAE024         /* SWU4 Target Register n */
-#define REG_SWU4_TARG1                  0xFFCAE044         /* SWU4 Target Register n */
-#define REG_SWU4_TARG2                  0xFFCAE064         /* SWU4 Target Register n */
-#define REG_SWU4_TARG3                  0xFFCAE084         /* SWU4 Target Register n */
-#define REG_SWU4_HIST0                  0xFFCAE028         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST1                  0xFFCAE048         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST2                  0xFFCAE068         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST3                  0xFFCAE088         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_CUR0                   0xFFCAE02C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR1                   0xFFCAE04C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR2                   0xFFCAE06C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR3                   0xFFCAE08C         /* SWU4 Current Register n */
-
-/* =========================
-        SWU5
-   ========================= */
-#define REG_SWU5_GCTL                   0xFFCAF000         /* SWU5 Global Control Register */
-#define REG_SWU5_GSTAT                  0xFFCAF004         /* SWU5 Global Status Register */
-#define REG_SWU5_CTL0                   0xFFCAF010         /* SWU5 Control Register n */
-#define REG_SWU5_CTL1                   0xFFCAF030         /* SWU5 Control Register n */
-#define REG_SWU5_CTL2                   0xFFCAF050         /* SWU5 Control Register n */
-#define REG_SWU5_CTL3                   0xFFCAF070         /* SWU5 Control Register n */
-#define REG_SWU5_LA0                    0xFFCAF014         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA1                    0xFFCAF034         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA2                    0xFFCAF054         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA3                    0xFFCAF074         /* SWU5 Lower Address Register n */
-#define REG_SWU5_UA0                    0xFFCAF018         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA1                    0xFFCAF038         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA2                    0xFFCAF058         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA3                    0xFFCAF078         /* SWU5 Upper Address Register n */
-#define REG_SWU5_ID0                    0xFFCAF01C         /* SWU5 ID Register n */
-#define REG_SWU5_ID1                    0xFFCAF03C         /* SWU5 ID Register n */
-#define REG_SWU5_ID2                    0xFFCAF05C         /* SWU5 ID Register n */
-#define REG_SWU5_ID3                    0xFFCAF07C         /* SWU5 ID Register n */
-#define REG_SWU5_CNT0                   0xFFCAF020         /* SWU5 Count Register n */
-#define REG_SWU5_CNT1                   0xFFCAF040         /* SWU5 Count Register n */
-#define REG_SWU5_CNT2                   0xFFCAF060         /* SWU5 Count Register n */
-#define REG_SWU5_CNT3                   0xFFCAF080         /* SWU5 Count Register n */
-#define REG_SWU5_TARG0                  0xFFCAF024         /* SWU5 Target Register n */
-#define REG_SWU5_TARG1                  0xFFCAF044         /* SWU5 Target Register n */
-#define REG_SWU5_TARG2                  0xFFCAF064         /* SWU5 Target Register n */
-#define REG_SWU5_TARG3                  0xFFCAF084         /* SWU5 Target Register n */
-#define REG_SWU5_HIST0                  0xFFCAF028         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST1                  0xFFCAF048         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST2                  0xFFCAF068         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST3                  0xFFCAF088         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_CUR0                   0xFFCAF02C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR1                   0xFFCAF04C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR2                   0xFFCAF06C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR3                   0xFFCAF08C         /* SWU5 Current Register n */
-
-/* =========================
-        SWU6
-   ========================= */
-#define REG_SWU6_GCTL                   0xFFC82000         /* SWU6 Global Control Register */
-#define REG_SWU6_GSTAT                  0xFFC82004         /* SWU6 Global Status Register */
-#define REG_SWU6_CTL0                   0xFFC82010         /* SWU6 Control Register n */
-#define REG_SWU6_CTL1                   0xFFC82030         /* SWU6 Control Register n */
-#define REG_SWU6_CTL2                   0xFFC82050         /* SWU6 Control Register n */
-#define REG_SWU6_CTL3                   0xFFC82070         /* SWU6 Control Register n */
-#define REG_SWU6_LA0                    0xFFC82014         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA1                    0xFFC82034         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA2                    0xFFC82054         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA3                    0xFFC82074         /* SWU6 Lower Address Register n */
-#define REG_SWU6_UA0                    0xFFC82018         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA1                    0xFFC82038         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA2                    0xFFC82058         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA3                    0xFFC82078         /* SWU6 Upper Address Register n */
-#define REG_SWU6_ID0                    0xFFC8201C         /* SWU6 ID Register n */
-#define REG_SWU6_ID1                    0xFFC8203C         /* SWU6 ID Register n */
-#define REG_SWU6_ID2                    0xFFC8205C         /* SWU6 ID Register n */
-#define REG_SWU6_ID3                    0xFFC8207C         /* SWU6 ID Register n */
-#define REG_SWU6_CNT0                   0xFFC82020         /* SWU6 Count Register n */
-#define REG_SWU6_CNT1                   0xFFC82040         /* SWU6 Count Register n */
-#define REG_SWU6_CNT2                   0xFFC82060         /* SWU6 Count Register n */
-#define REG_SWU6_CNT3                   0xFFC82080         /* SWU6 Count Register n */
-#define REG_SWU6_TARG0                  0xFFC82024         /* SWU6 Target Register n */
-#define REG_SWU6_TARG1                  0xFFC82044         /* SWU6 Target Register n */
-#define REG_SWU6_TARG2                  0xFFC82064         /* SWU6 Target Register n */
-#define REG_SWU6_TARG3                  0xFFC82084         /* SWU6 Target Register n */
-#define REG_SWU6_HIST0                  0xFFC82028         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST1                  0xFFC82048         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST2                  0xFFC82068         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST3                  0xFFC82088         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_CUR0                   0xFFC8202C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR1                   0xFFC8204C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR2                   0xFFC8206C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR3                   0xFFC8208C         /* SWU6 Current Register n */
-
-/* =========================
-        SWU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GCTL_RST                     1                               /* Global Reset */
-#define BITP_SWU_GCTL_EN                      0                               /* Global Enable */
-#define BITM_SWU_GCTL_RST                    (_ADI_MSK(0x00000002,uint32_t))  /* Global Reset */
-#define BITM_SWU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Global Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GSTAT_ADDRERR               30                               /* Address Error Status */
-#define BITP_SWU_GSTAT_OVRBW3                15                               /* Group 3 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW3               14                               /* Group 3 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW2                13                               /* Group 2 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW2               12                               /* Group 2 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW1                11                               /* Group 1 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW1               10                               /* Group 1 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW0                 9                               /* Group 0 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW0                8                               /* Group 0 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_INT3                   7                               /* Group 3 Interrupt Status */
-#define BITP_SWU_GSTAT_INT2                   6                               /* Group 2 Interrupt Status */
-#define BITP_SWU_GSTAT_INT1                   5                               /* Group 1 Interrupt Status */
-#define BITP_SWU_GSTAT_INT0                   4                               /* Group 0 Interrupt Status */
-#define BITP_SWU_GSTAT_MTCH3                  3                               /* Group 3 Match */
-#define BITP_SWU_GSTAT_MTCH2                  2                               /* Group 2 Match */
-#define BITP_SWU_GSTAT_MTCH1                  1                               /* Group 1 Match */
-#define BITP_SWU_GSTAT_MTCH0                  0                               /* Group 0 Match */
-#define BITM_SWU_GSTAT_ADDRERR               (_ADI_MSK(0x40000000,uint32_t))  /* Address Error Status */
-#define BITM_SWU_GSTAT_OVRBW3                (_ADI_MSK(0x00008000,uint32_t))  /* Group 3 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW3               (_ADI_MSK(0x00004000,uint32_t))  /* Group 3 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW2                (_ADI_MSK(0x00002000,uint32_t))  /* Group 2 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW2               (_ADI_MSK(0x00001000,uint32_t))  /* Group 2 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW1                (_ADI_MSK(0x00000800,uint32_t))  /* Group 1 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW1               (_ADI_MSK(0x00000400,uint32_t))  /* Group 1 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW0                (_ADI_MSK(0x00000200,uint32_t))  /* Group 0 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW0               (_ADI_MSK(0x00000100,uint32_t))  /* Group 0 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_INT3                  (_ADI_MSK(0x00000080,uint32_t))  /* Group 3 Interrupt Status */
-#define BITM_SWU_GSTAT_INT2                  (_ADI_MSK(0x00000040,uint32_t))  /* Group 2 Interrupt Status */
-#define BITM_SWU_GSTAT_INT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Group 1 Interrupt Status */
-#define BITM_SWU_GSTAT_INT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Group 0 Interrupt Status */
-#define BITM_SWU_GSTAT_MTCH3                 (_ADI_MSK(0x00000008,uint32_t))  /* Group 3 Match */
-#define BITM_SWU_GSTAT_MTCH2                 (_ADI_MSK(0x00000004,uint32_t))  /* Group 2 Match */
-#define BITM_SWU_GSTAT_MTCH1                 (_ADI_MSK(0x00000002,uint32_t))  /* Group 1 Match */
-#define BITM_SWU_GSTAT_MTCH0                 (_ADI_MSK(0x00000001,uint32_t))  /* Group 0 Match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CTL_MAXACT                  19                               /* Action for Bandwidth Above Maximum */
-#define BITP_SWU_CTL_MINACT                  18                               /* Action for Bandwidth Below Minimum */
-#define BITP_SWU_CTL_BLENINC                 17                               /* Increment Bandwidth Count by Burst Length */
-#define BITP_SWU_CTL_BWEN                    16                               /* Bandwidth Mode Enable */
-#define BITP_SWU_CTL_TMEN                    15                               /* Trace Message Enable */
-#define BITP_SWU_CTL_TRGEN                   14                               /* Trigger Enable */
-#define BITP_SWU_CTL_INTEN                   13                               /* Interrupt Enable */
-#define BITP_SWU_CTL_DBGEN                   12                               /* Debug Event Enable */
-#define BITP_SWU_CTL_CNTRPTEN                 9                               /* Count Repeat Enable */
-#define BITP_SWU_CTL_CNTEN                    8                               /* Count Enable */
-#define BITP_SWU_CTL_LCMPEN                   6                               /* Locked Comparison Enable */
-#define BITP_SWU_CTL_SCMPEN                   5                               /* Secure Comparison Enable */
-#define BITP_SWU_CTL_IDCMPEN                  4                               /* ID Comparison Enable */
-#define BITP_SWU_CTL_ACMPM                    2                               /* Address Comparison Mode */
-#define BITP_SWU_CTL_DIR                      1                               /* Transaction Direction for Match */
-#define BITP_SWU_CTL_EN                       0                               /* Enable Watchpoint */
-#define BITM_SWU_CTL_MAXACT                  (_ADI_MSK(0x00080000,uint32_t))  /* Action for Bandwidth Above Maximum */
-#define BITM_SWU_CTL_MINACT                  (_ADI_MSK(0x00040000,uint32_t))  /* Action for Bandwidth Below Minimum */
-#define BITM_SWU_CTL_BLENINC                 (_ADI_MSK(0x00020000,uint32_t))  /* Increment Bandwidth Count by Burst Length */
-#define BITM_SWU_CTL_BWEN                    (_ADI_MSK(0x00010000,uint32_t))  /* Bandwidth Mode Enable */
-#define BITM_SWU_CTL_TMEN                    (_ADI_MSK(0x00008000,uint32_t))  /* Trace Message Enable */
-#define BITM_SWU_CTL_TRGEN                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Enable */
-#define BITM_SWU_CTL_INTEN                   (_ADI_MSK(0x00002000,uint32_t))  /* Interrupt Enable */
-#define BITM_SWU_CTL_DBGEN                   (_ADI_MSK(0x00001000,uint32_t))  /* Debug Event Enable */
-#define BITM_SWU_CTL_CNTRPTEN                (_ADI_MSK(0x00000200,uint32_t))  /* Count Repeat Enable */
-#define BITM_SWU_CTL_CNTEN                   (_ADI_MSK(0x00000100,uint32_t))  /* Count Enable */
-#define BITM_SWU_CTL_LCMPEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Locked Comparison Enable */
-#define BITM_SWU_CTL_SCMPEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Secure Comparison Enable */
-#define BITM_SWU_CTL_IDCMPEN                 (_ADI_MSK(0x00000010,uint32_t))  /* ID Comparison Enable */
-#define BITM_SWU_CTL_ACMPM                   (_ADI_MSK(0x0000000C,uint32_t))  /* Address Comparison Mode */
-#define BITM_SWU_CTL_DIR                     (_ADI_MSK(0x00000002,uint32_t))  /* Transaction Direction for Match */
-#define BITM_SWU_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable Watchpoint */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_ID                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_ID_IDMASK                   16                               /* Identity Mask (for Or with ID) */
-#define BITP_SWU_ID_ID                        0                               /* Identity */
-#define BITM_SWU_ID_IDMASK                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Identity Mask (for Or with ID) */
-#define BITM_SWU_ID_ID                       (_ADI_MSK(0x0000FFFF,uint32_t))  /* Identity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CNT_COUNT                    0                               /* Count */
-#define BITM_SWU_CNT_COUNT                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_TARG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_TARG_BWMAX                  16                               /* Maximum Bandwidth Target */
-#define BITP_SWU_TARG_BWMIN                   0                               /* Minimum Bandwidth Target */
-#define BITM_SWU_TARG_BWMAX                  (_ADI_MSK(0xFFFF0000,uint32_t))  /* Maximum Bandwidth Target */
-#define BITM_SWU_TARG_BWMIN                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Minimum Bandwidth Target */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_HIST                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_HIST_BWHIST1                16                               /* Bandwidth from Window Before Last */
-#define BITP_SWU_HIST_BWHIST0                 0                               /* Bandwidth from Last Window */
-#define BITM_SWU_HIST_BWHIST1                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Bandwidth from Window Before Last */
-#define BITM_SWU_HIST_BWHIST0                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth from Last Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CUR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CUR_CURBW                   16                               /* Current Bandwidth */
-#define BITP_SWU_CUR_CURCNT                   0                               /* Current Count */
-#define BITM_SWU_CUR_CURBW                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Current Bandwidth */
-#define BITM_SWU_CUR_CURCNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Current Count */
-
-/* ==================================================
-        System Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        SDU0
-   ========================= */
-#define REG_SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
-#define REG_SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
-#define REG_SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
-#define REG_SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
-#define REG_SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
-#define REG_SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
-#define REG_SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
-#define REG_SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
-#define REG_SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
-#define REG_SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
-#define REG_SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
-#define REG_SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
-
-/* =========================
-        SDU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_IDCODE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_IDCODE_REVID                28                               /* Revision ID */
-#define BITP_SDU_IDCODE_PRID                 12                               /* Product ID */
-#define BITP_SDU_IDCODE_MFID                  1                               /* Manufacturer ID */
-#define BITM_SDU_IDCODE_REVID                (_ADI_MSK(0xF0000000,uint32_t))  /* Revision ID */
-#define BITM_SDU_IDCODE_PRID                 (_ADI_MSK(0x0FFFF000,uint32_t))  /* Product ID */
-#define BITM_SDU_IDCODE_MFID                 (_ADI_MSK(0x00000FFE,uint32_t))  /* Manufacturer ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_CTL_EHLT                     8                               /* Emulator Halt Select */
-#define BITP_SDU_CTL_EMEEN                    4                               /* Emulation Event Enable */
-#define BITP_SDU_CTL_DMAEN                    2                               /* DMA Enable */
-#define BITP_SDU_CTL_CSPEN                    1                               /* Core Scan Path Enable */
-#define BITP_SDU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_SDU_CTL_EHLT                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Emulator Halt Select */
-#define BITM_SDU_CTL_EMEEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Emulation Event Enable */
-#define BITM_SDU_CTL_DMAEN                   (_ADI_MSK(0x00000004,uint32_t))  /* DMA Enable */
-#define BITM_SDU_CTL_CSPEN                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Scan Path Enable */
-#define BITM_SDU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_STAT_CRST                   22                               /* Core Reset */
-#define BITP_SDU_STAT_CHLT                   21                               /* Core Halt */
-#define BITP_SDU_STAT_EME                    20                               /* Emulation Event */
-#define BITP_SDU_STAT_GHLTC                  17                               /* Group Halt Cause */
-#define BITP_SDU_STAT_GHLT                   16                               /* Group Halt */
-#define BITP_SDU_STAT_DMAFIFO                12                               /* DMA FIFO */
-#define BITP_SDU_STAT_ADDRERR                11                               /* Address Error */
-#define BITP_SDU_STAT_DMAWDRDY               10                               /* DMAWD Ready */
-#define BITP_SDU_STAT_DMARDRDY                9                               /* DMARD Ready */
-#define BITP_SDU_STAT_MACRDY                  8                               /* MAC Ready */
-#define BITP_SDU_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_SDU_STAT_SECURE                  3                               /* Secure Mode */
-#define BITP_SDU_STAT_DEEPSLEEP               2                               /* Deep Sleep Mode */
-#define BITP_SDU_STAT_ERR                     1                               /* Error */
-#define BITP_SDU_STAT_SYSRST                  0                               /* System Reset */
-#define BITM_SDU_STAT_CRST                   (_ADI_MSK(0x00400000,uint32_t))  /* Core Reset */
-#define BITM_SDU_STAT_CHLT                   (_ADI_MSK(0x00200000,uint32_t))  /* Core Halt */
-#define BITM_SDU_STAT_EME                    (_ADI_MSK(0x00100000,uint32_t))  /* Emulation Event */
-#define BITM_SDU_STAT_GHLTC                  (_ADI_MSK(0x000E0000,uint32_t))  /* Group Halt Cause */
-#define BITM_SDU_STAT_GHLT                   (_ADI_MSK(0x00010000,uint32_t))  /* Group Halt */
-#define BITM_SDU_STAT_DMAFIFO                (_ADI_MSK(0x00007000,uint32_t))  /* DMA FIFO */
-#define BITM_SDU_STAT_ADDRERR                (_ADI_MSK(0x00000800,uint32_t))  /* Address Error */
-#define BITM_SDU_STAT_DMAWDRDY               (_ADI_MSK(0x00000400,uint32_t))  /* DMAWD Ready */
-#define BITM_SDU_STAT_DMARDRDY               (_ADI_MSK(0x00000200,uint32_t))  /* DMARD Ready */
-#define BITM_SDU_STAT_MACRDY                 (_ADI_MSK(0x00000100,uint32_t))  /* MAC Ready */
-#define BITM_SDU_STAT_ERRC                   (_ADI_MSK(0x000000F0,uint32_t))  /* Error Cause */
-#define BITM_SDU_STAT_SECURE                 (_ADI_MSK(0x00000008,uint32_t))  /* Secure Mode */
-#define BITM_SDU_STAT_DEEPSLEEP              (_ADI_MSK(0x00000004,uint32_t))  /* Deep Sleep Mode */
-#define BITM_SDU_STAT_ERR                    (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define BITM_SDU_STAT_SYSRST                 (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MACCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MACCTL_AUTOINC               4                               /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITP_SDU_MACCTL_RNW                   3                               /* Read Not Write */
-#define BITP_SDU_MACCTL_SIZE                  0                               /* Transfer Data Size */
-#define BITM_SDU_MACCTL_AUTOINC              (_ADI_MSK(0x00000010,uint32_t))  /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITM_SDU_MACCTL_RNW                  (_ADI_MSK(0x00000008,uint32_t))  /* Read Not Write */
-#define BITM_SDU_MACCTL_SIZE                 (_ADI_MSK(0x00000007,uint32_t))  /* Transfer Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MSG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MSG_CALLERR                 31                               /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITP_SDU_MSG_CALLBACK                30                               /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITP_SDU_MSG_CALLINIT                29                               /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITP_SDU_MSG_CALLAPP                 28                               /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITP_SDU_MSG_HALTONERR               27                               /* Generate an Emulation Exception Prior to an Error Call */
-#define BITP_SDU_MSG_HALTONCALL              26                               /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITP_SDU_MSG_HALTONINIT              25                               /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITP_SDU_MSG_HALTONAPP               24                               /* Generate an Emulation Exception Prior to an Application Call */
-#define BITP_SDU_MSG_L3INIT                  23                               /* Indicates that the L3 Resource is Initialized */
-#define BITP_SDU_MSG_L2INIT                  22                               /* Indicates that the L2 Resource is Initialized */
-#define BITP_SDU_MSG_C1L1INIT                17                               /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITP_SDU_MSG_C0L1INIT                16                               /* Indicates that the Core 0 L1 Resource is Initialized */
-#define BITM_SDU_MSG_CALLERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITM_SDU_MSG_CALLBACK                (_ADI_MSK(0x40000000,uint32_t))  /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITM_SDU_MSG_CALLINIT                (_ADI_MSK(0x20000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITM_SDU_MSG_CALLAPP                 (_ADI_MSK(0x10000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITM_SDU_MSG_HALTONERR               (_ADI_MSK(0x08000000,uint32_t))  /* Generate an Emulation Exception Prior to an Error Call */
-#define BITM_SDU_MSG_HALTONCALL              (_ADI_MSK(0x04000000,uint32_t))  /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITM_SDU_MSG_HALTONINIT              (_ADI_MSK(0x02000000,uint32_t))  /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITM_SDU_MSG_HALTONAPP               (_ADI_MSK(0x01000000,uint32_t))  /* Generate an Emulation Exception Prior to an Application Call */
-#define BITM_SDU_MSG_L3INIT                  (_ADI_MSK(0x00800000,uint32_t))  /* Indicates that the L3 Resource is Initialized */
-#define BITM_SDU_MSG_L2INIT                  (_ADI_MSK(0x00400000,uint32_t))  /* Indicates that the L2 Resource is Initialized */
-#define BITM_SDU_MSG_C1L1INIT                (_ADI_MSK(0x00020000,uint32_t))  /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITM_SDU_MSG_C0L1INIT                (_ADI_MSK(0x00010000,uint32_t))  /* Indicates that the Core 0 L1 Resource is Initialized */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_GHLT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_GHLT_SS2                    18                               /* Slave Select 2 */
-#define BITP_SDU_GHLT_SS1                    17                               /* Slave Select 1 */
-#define BITP_SDU_GHLT_SS0                    16                               /* Slave Select 0 */
-#define BITP_SDU_GHLT_MS2                     2                               /* Master Select 2 */
-#define BITP_SDU_GHLT_MS1                     1                               /* Master Select 1 */
-#define BITP_SDU_GHLT_MS0                     0                               /* Master Select 0 */
-#define BITM_SDU_GHLT_SS2                    (_ADI_MSK(0x00040000,uint32_t))  /* Slave Select 2 */
-#define BITM_SDU_GHLT_SS1                    (_ADI_MSK(0x00020000,uint32_t))  /* Slave Select 1 */
-#define BITM_SDU_GHLT_SS0                    (_ADI_MSK(0x00010000,uint32_t))  /* Slave Select 0 */
-#define BITM_SDU_GHLT_MS2                    (_ADI_MSK(0x00000004,uint32_t))  /* Master Select 2 */
-#define BITM_SDU_GHLT_MS1                    (_ADI_MSK(0x00000002,uint32_t))  /* Master Select 1 */
-#define BITM_SDU_GHLT_MS0                    (_ADI_MSK(0x00000001,uint32_t))  /* Master Select 0 */
-
-/* ==================================================
-        Ethernet MAC Registers
-   ================================================== */
-
-/* =========================
-        EMAC0
-   ========================= */
-#define REG_EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
-#define REG_EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 MAC Rx Frame Filter Register */
-#define REG_EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Hash Table High Register */
-#define REG_EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Hash Table Low Register */
-#define REG_EMAC0_SMI_ADDR              0xFFC20010         /* EMAC0 SMI Address Register */
-#define REG_EMAC0_SMI_DATA              0xFFC20014         /* EMAC0 SMI Data Register */
-#define REG_EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 FLow Control Register */
-#define REG_EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
-#define REG_EMAC0_DBG                   0xFFC20024         /* EMAC0 Debug Register */
-#define REG_EMAC0_ISTAT                 0xFFC20038         /* EMAC0 Interrupt Status Register */
-#define REG_EMAC0_IMSK                  0xFFC2003C         /* EMAC0 Interrupt Mask Register */
-#define REG_EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 MAC Address 0 High Register */
-#define REG_EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 MAC Address 0 Low Register */
-#define REG_EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
-#define REG_EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC Rx Interrupt Register */
-#define REG_EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC Tx Interrupt Register */
-#define REG_EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC Rx Interrupt Mask Register */
-#define REG_EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
-#define REG_EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Tx Multicast Frames (Good) Register */
-#define REG_EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Tx Underflow Error Register */
-#define REG_EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Tx Single Collision (Good) Register */
-#define REG_EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Tx Multiple Collision (Good) Register */
-#define REG_EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Tx Deferred Register */
-#define REG_EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Tx Late Collision Register */
-#define REG_EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Tx Excess Collision Register */
-#define REG_EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Tx Carrier Error Register */
-#define REG_EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Tx Octet Count (Good) Register */
-#define REG_EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Tx Frame Count (Good) Register */
-#define REG_EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Tx Excess Deferral Register */
-#define REG_EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Tx Pause Frame Register */
-#define REG_EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Tx VLAN Frames (Good) Register */
-#define REG_EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Rx Octet Count (Good) Register */
-#define REG_EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Rx Multicast Frames (Good) Register */
-#define REG_EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Rx CRC Error Register */
-#define REG_EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Rx alignment Error Register */
-#define REG_EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Rx Runt Error Register */
-#define REG_EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Rx Jab Error Register */
-#define REG_EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Rx Undersize (Good) Register */
-#define REG_EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Rx Oversize (Good) Register */
-#define REG_EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Rx Unicast Frames (Good) Register */
-#define REG_EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Rx Length Error Register */
-#define REG_EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Rx Out Of Range Type Register */
-#define REG_EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Rx Pause Frames Register */
-#define REG_EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Rx FIFO Overflow Register */
-#define REG_EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Rx Watch Dog Error Register */
-#define REG_EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC Rx Interrupt Register */
-#define REG_EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Rx UDP Good Frames Register */
-#define REG_EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Rx UDP Error Frames Register */
-#define REG_EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Rx TCP Good Frames Register */
-#define REG_EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Rx TCP Error Frames Register */
-#define REG_EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Rx ICMP Good Frames Register */
-#define REG_EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Rx ICMP Error Frames Register */
-#define REG_EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Rx IPv6 Good Octets Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Rx IPv6 Header Errors Register */
-#define REG_EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Rx UDP Good Octets Register */
-#define REG_EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Rx UDP Error Octets Register */
-#define REG_EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Rx TCP Good Octets Register */
-#define REG_EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Rx TCP Error Octets Register */
-#define REG_EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Rx ICMP Good Octets Register */
-#define REG_EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Rx ICMP Error Octets Register */
-#define REG_EMAC0_TM_CTL                0xFFC20700         /* EMAC0 Time Stamp Control Register */
-#define REG_EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 Time Stamp Sub Second Increment Register */
-#define REG_EMAC0_TM_SEC                0xFFC20708         /* EMAC0 Time Stamp Low Seconds Register */
-#define REG_EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 Time Stamp Nano Seconds Register */
-#define REG_EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 Time Stamp Seconds Update Register */
-#define REG_EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 Time Stamp Addend Register */
-#define REG_EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 Time Stamp Target Time Seconds Register */
-#define REG_EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 Time Stamp High Second Register */
-#define REG_EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 Time Stamp Status Register */
-#define REG_EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 PPS Control Register */
-#define REG_EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC0_TM_PPSINTVL           0xFFC20760         /* EMAC0 Time Stamp PPS Interval Register */
-#define REG_EMAC0_TM_PPSWIDTH           0xFFC20764         /* EMAC0 PPS Width Register */
-#define REG_EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 DMA Bus Mode Register */
-#define REG_EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 DMA Tx Poll Demand Register */
-#define REG_EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 DMA Rx Poll Demand register */
-#define REG_EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define REG_EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define REG_EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
-#define REG_EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
-#define REG_EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
-#define REG_EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA Missed Frame Register */
-#define REG_EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 DMA SCB Bus Mode Register */
-#define REG_EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 DMA SCB Status Register */
-#define REG_EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 DMA Tx Descriptor Current Register */
-#define REG_EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 DMA Rx Descriptor Current Register */
-#define REG_EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 DMA Tx Buffer Current Register */
-#define REG_EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC1
-   ========================= */
-#define REG_EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
-#define REG_EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 MAC Rx Frame Filter Register */
-#define REG_EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Hash Table High Register */
-#define REG_EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Hash Table Low Register */
-#define REG_EMAC1_SMI_ADDR              0xFFC22010         /* EMAC1 SMI Address Register */
-#define REG_EMAC1_SMI_DATA              0xFFC22014         /* EMAC1 SMI Data Register */
-#define REG_EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 FLow Control Register */
-#define REG_EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
-#define REG_EMAC1_DBG                   0xFFC22024         /* EMAC1 Debug Register */
-#define REG_EMAC1_ISTAT                 0xFFC22038         /* EMAC1 Interrupt Status Register */
-#define REG_EMAC1_IMSK                  0xFFC2203C         /* EMAC1 Interrupt Mask Register */
-#define REG_EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 MAC Address 0 High Register */
-#define REG_EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 MAC Address 0 Low Register */
-#define REG_EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
-#define REG_EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC Rx Interrupt Register */
-#define REG_EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC Tx Interrupt Register */
-#define REG_EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC Rx Interrupt Mask Register */
-#define REG_EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
-#define REG_EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Tx Multicast Frames (Good) Register */
-#define REG_EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Tx Underflow Error Register */
-#define REG_EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Tx Single Collision (Good) Register */
-#define REG_EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Tx Multiple Collision (Good) Register */
-#define REG_EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Tx Deferred Register */
-#define REG_EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Tx Late Collision Register */
-#define REG_EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Tx Excess Collision Register */
-#define REG_EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Tx Carrier Error Register */
-#define REG_EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Tx Octet Count (Good) Register */
-#define REG_EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Tx Frame Count (Good) Register */
-#define REG_EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Tx Excess Deferral Register */
-#define REG_EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Tx Pause Frame Register */
-#define REG_EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Tx VLAN Frames (Good) Register */
-#define REG_EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Rx Octet Count (Good) Register */
-#define REG_EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Rx Multicast Frames (Good) Register */
-#define REG_EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Rx CRC Error Register */
-#define REG_EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Rx alignment Error Register */
-#define REG_EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Rx Runt Error Register */
-#define REG_EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Rx Jab Error Register */
-#define REG_EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Rx Undersize (Good) Register */
-#define REG_EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Rx Oversize (Good) Register */
-#define REG_EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Rx Unicast Frames (Good) Register */
-#define REG_EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Rx Length Error Register */
-#define REG_EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Rx Out Of Range Type Register */
-#define REG_EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Rx Pause Frames Register */
-#define REG_EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Rx FIFO Overflow Register */
-#define REG_EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Rx Watch Dog Error Register */
-#define REG_EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC Rx Interrupt Register */
-#define REG_EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Rx UDP Good Frames Register */
-#define REG_EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Rx UDP Error Frames Register */
-#define REG_EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Rx TCP Good Frames Register */
-#define REG_EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Rx TCP Error Frames Register */
-#define REG_EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Rx ICMP Good Frames Register */
-#define REG_EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Rx ICMP Error Frames Register */
-#define REG_EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Rx IPv6 Good Octets Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Rx IPv6 Header Errors Register */
-#define REG_EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Rx UDP Good Octets Register */
-#define REG_EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Rx UDP Error Octets Register */
-#define REG_EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Rx TCP Good Octets Register */
-#define REG_EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Rx TCP Error Octets Register */
-#define REG_EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Rx ICMP Good Octets Register */
-#define REG_EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Rx ICMP Error Octets Register */
-#define REG_EMAC1_TM_CTL                0xFFC22700         /* EMAC1 Time Stamp Control Register */
-#define REG_EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 Time Stamp Sub Second Increment Register */
-#define REG_EMAC1_TM_SEC                0xFFC22708         /* EMAC1 Time Stamp Low Seconds Register */
-#define REG_EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 Time Stamp Nano Seconds Register */
-#define REG_EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 Time Stamp Seconds Update Register */
-#define REG_EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 Time Stamp Addend Register */
-#define REG_EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 Time Stamp Target Time Seconds Register */
-#define REG_EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 Time Stamp High Second Register */
-#define REG_EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 Time Stamp Status Register */
-#define REG_EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 PPS Control Register */
-#define REG_EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC1_TM_PPSINTVL           0xFFC22760         /* EMAC1 Time Stamp PPS Interval Register */
-#define REG_EMAC1_TM_PPSWIDTH           0xFFC22764         /* EMAC1 PPS Width Register */
-#define REG_EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 DMA Bus Mode Register */
-#define REG_EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 DMA Tx Poll Demand Register */
-#define REG_EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 DMA Rx Poll Demand register */
-#define REG_EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define REG_EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define REG_EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
-#define REG_EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
-#define REG_EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
-#define REG_EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA Missed Frame Register */
-#define REG_EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 DMA SCB Bus Mode Register */
-#define REG_EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 DMA SCB Status Register */
-#define REG_EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 DMA Tx Descriptor Current Register */
-#define REG_EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 DMA Rx Descriptor Current Register */
-#define REG_EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 DMA Tx Buffer Current Register */
-#define REG_EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACCFG_CST                 25                               /* CRC Stripping */
-#define BITP_EMAC_MACCFG_WD                  23                               /* Watch Dog Disable */
-#define BITP_EMAC_MACCFG_JB                  22                               /* Jabber Disable */
-#define BITP_EMAC_MACCFG_JE                  20                               /* Jumbo Frame Enable */
-#define BITP_EMAC_MACCFG_IFG                 17                               /* Inter Frame Gap */
-#define BITP_EMAC_MACCFG_DCRS                16                               /* Disable Carrier Sense */
-#define BITP_EMAC_MACCFG_FES                 14                               /* Speed of Operation */
-#define BITP_EMAC_MACCFG_DO                  13                               /* Disable Receive Own */
-#define BITP_EMAC_MACCFG_LM                  12                               /* Loopback Mode */
-#define BITP_EMAC_MACCFG_DM                  11                               /* Duplex Mode */
-#define BITP_EMAC_MACCFG_IPC                 10                               /* IP Checksum */
-#define BITP_EMAC_MACCFG_DR                   9                               /* Disable Retry */
-#define BITP_EMAC_MACCFG_ACS                  7                               /* Automatic Pad/CRC Stripping */
-#define BITP_EMAC_MACCFG_BL                   5                               /* Back Off Limit */
-#define BITP_EMAC_MACCFG_DC                   4                               /* Deferral Check */
-#define BITP_EMAC_MACCFG_TE                   3                               /* Transmitter Enable */
-#define BITP_EMAC_MACCFG_RE                   2                               /* Receiver Enable */
-#define BITM_EMAC_MACCFG_CST                 (_ADI_MSK(0x02000000,uint32_t))  /* CRC Stripping */
-#define BITM_EMAC_MACCFG_WD                  (_ADI_MSK(0x00800000,uint32_t))  /* Watch Dog Disable */
-#define BITM_EMAC_MACCFG_JB                  (_ADI_MSK(0x00400000,uint32_t))  /* Jabber Disable */
-#define BITM_EMAC_MACCFG_JE                  (_ADI_MSK(0x00100000,uint32_t))  /* Jumbo Frame Enable */
-
-#define BITM_EMAC_MACCFG_IFG                 (_ADI_MSK(0x000E0000,uint32_t))  /* Inter Frame Gap */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_96        (_ADI_MSK(0x00000000,uint32_t))  /* IFG: 96 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_88        (_ADI_MSK(0x00020000,uint32_t))  /* IFG: 88 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_80        (_ADI_MSK(0x00040000,uint32_t))  /* IFG: 80 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_72        (_ADI_MSK(0x00060000,uint32_t))  /* IFG: 72 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_64        (_ADI_MSK(0x00080000,uint32_t))  /* IFG: 64 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_56        (_ADI_MSK(0x000A0000,uint32_t))  /* IFG: 56 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_48        (_ADI_MSK(0x000C0000,uint32_t))  /* IFG: 48 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_40        (_ADI_MSK(0x000E0000,uint32_t))  /* IFG: 40 bit times */
-#define BITM_EMAC_MACCFG_DCRS                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Carrier Sense */
-#define BITM_EMAC_MACCFG_FES                 (_ADI_MSK(0x00004000,uint32_t))  /* Speed of Operation */
-#define BITM_EMAC_MACCFG_DO                  (_ADI_MSK(0x00002000,uint32_t))  /* Disable Receive Own */
-#define BITM_EMAC_MACCFG_LM                  (_ADI_MSK(0x00001000,uint32_t))  /* Loopback Mode */
-#define BITM_EMAC_MACCFG_DM                  (_ADI_MSK(0x00000800,uint32_t))  /* Duplex Mode */
-#define BITM_EMAC_MACCFG_IPC                 (_ADI_MSK(0x00000400,uint32_t))  /* IP Checksum */
-
-#define BITM_EMAC_MACCFG_DR                  (_ADI_MSK(0x00000200,uint32_t))  /* Disable Retry */
-#define ENUM_EMAC_MACCFG_RETRY_ENABLED       (_ADI_MSK(0x00000000,uint32_t))  /* DR: Retry enabled */
-#define ENUM_EMAC_MACCFG_RETRY_DISABLED      (_ADI_MSK(0x00000200,uint32_t))  /* DR: Retry disabled */
-#define BITM_EMAC_MACCFG_ACS                 (_ADI_MSK(0x00000080,uint32_t))  /* Automatic Pad/CRC Stripping */
-
-#define BITM_EMAC_MACCFG_BL                  (_ADI_MSK(0x00000060,uint32_t))  /* Back Off Limit */
-#define ENUM_EMAC_MACCFG_BL_10               (_ADI_MSK(0x00000000,uint32_t))  /* BL: k = min (n, 10) */
-#define ENUM_EMAC_MACCFG_BL_8                (_ADI_MSK(0x00000020,uint32_t))  /* BL: k = min (n, 8) */
-#define ENUM_EMAC_MACCFG_BL_4                (_ADI_MSK(0x00000040,uint32_t))  /* BL: k = min (n, 4) */
-#define ENUM_EMAC_MACCFG_BL_1                (_ADI_MSK(0x00000060,uint32_t))  /* BL: k = min (n, 1) */
-#define BITM_EMAC_MACCFG_DC                  (_ADI_MSK(0x00000010,uint32_t))  /* Deferral Check */
-#define BITM_EMAC_MACCFG_TE                  (_ADI_MSK(0x00000008,uint32_t))  /* Transmitter Enable */
-#define BITM_EMAC_MACCFG_RE                  (_ADI_MSK(0x00000004,uint32_t))  /* Receiver Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACFRMFILT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACFRMFILT_RA              31                               /* Receive All Frames */
-#define BITP_EMAC_MACFRMFILT_HPF             10                               /* Hash or Perfect Filter */
-#define BITP_EMAC_MACFRMFILT_PCF              6                               /* Pass Control Frames */
-#define BITP_EMAC_MACFRMFILT_DBF              5                               /* Disable Broadcast Frames */
-#define BITP_EMAC_MACFRMFILT_PM               4                               /* Pass All Multicast Frames */
-#define BITP_EMAC_MACFRMFILT_DAIF             3                               /* Destination Address Inverse Filtering */
-#define BITP_EMAC_MACFRMFILT_HMC              2                               /* Hash Multicast */
-#define BITP_EMAC_MACFRMFILT_HUC              1                               /* Hash Unicast */
-#define BITP_EMAC_MACFRMFILT_PR               0                               /* Promiscuous Mode */
-#define BITM_EMAC_MACFRMFILT_RA              (_ADI_MSK(0x80000000,uint32_t))  /* Receive All Frames */
-#define BITM_EMAC_MACFRMFILT_HPF             (_ADI_MSK(0x00000400,uint32_t))  /* Hash or Perfect Filter */
-
-#define BITM_EMAC_MACFRMFILT_PCF             (_ADI_MSK(0x000000C0,uint32_t))  /* Pass Control Frames */
-#define ENUM_EMAC_MACFRMFILT_FILT_ALL        (_ADI_MSK(0x00000000,uint32_t))  /* PCF: Pass no control frames */
-#define ENUM_EMAC_MACFRMFILT_NO_PAUSE        (_ADI_MSK(0x00000040,uint32_t))  /* PCF: Pass no PAUSE frames */
-#define ENUM_EMAC_MACFRMFILT_FWD_ALL         (_ADI_MSK(0x00000080,uint32_t))  /* PCF: Pass all control frames */
-#define ENUM_EMAC_MACFRMFILT_PADR_FILT       (_ADI_MSK(0x000000C0,uint32_t))  /* PCF: Pass address filtered control frames */
-
-#define BITM_EMAC_MACFRMFILT_DBF             (_ADI_MSK(0x00000020,uint32_t))  /* Disable Broadcast Frames */
-#define ENUM_EMAC_MACFRMFILT_DIS_BCAST       (_ADI_MSK(0x00000000,uint32_t))  /* DBF: AFM module passes all received broadcast frames */
-#define ENUM_EMAC_MACFRMFILT_EN_BCAST        (_ADI_MSK(0x00000020,uint32_t))  /* DBF: AFM module filters all incoming broadcast frames */
-#define BITM_EMAC_MACFRMFILT_PM              (_ADI_MSK(0x00000010,uint32_t))  /* Pass All Multicast Frames */
-#define BITM_EMAC_MACFRMFILT_DAIF            (_ADI_MSK(0x00000008,uint32_t))  /* Destination Address Inverse Filtering */
-#define BITM_EMAC_MACFRMFILT_HMC             (_ADI_MSK(0x00000004,uint32_t))  /* Hash Multicast */
-#define BITM_EMAC_MACFRMFILT_HUC             (_ADI_MSK(0x00000002,uint32_t))  /* Hash Unicast */
-#define BITM_EMAC_MACFRMFILT_PR              (_ADI_MSK(0x00000001,uint32_t))  /* Promiscuous Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_ADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_ADDR_PA                11                               /* Physical Layer Address */
-#define BITP_EMAC_SMI_ADDR_SMIR               6                               /* SMI Register Address */
-#define BITP_EMAC_SMI_ADDR_CR                 2                               /* Clock Range */
-#define BITP_EMAC_SMI_ADDR_SMIW               1                               /* SMI Write */
-#define BITP_EMAC_SMI_ADDR_SMIB               0                               /* SMI Busy */
-#define BITM_EMAC_SMI_ADDR_PA                (_ADI_MSK(0x0000F800,uint32_t))  /* Physical Layer Address */
-#define BITM_EMAC_SMI_ADDR_SMIR              (_ADI_MSK(0x000007C0,uint32_t))  /* SMI Register Address */
-#define BITM_EMAC_SMI_ADDR_CR                (_ADI_MSK(0x0000003C,uint32_t))  /* Clock Range */
-#define BITM_EMAC_SMI_ADDR_SMIW              (_ADI_MSK(0x00000002,uint32_t))  /* SMI Write */
-#define BITM_EMAC_SMI_ADDR_SMIB              (_ADI_MSK(0x00000001,uint32_t))  /* SMI Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_DATA                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_DATA_SMID               0                               /* SMI Data */
-#define BITM_EMAC_SMI_DATA_SMID              (_ADI_MSK(0x0000FFFF,uint32_t))  /* SMI Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_FLOWCTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_FLOWCTL_PT                 16                               /* Pause Time */
-#define BITP_EMAC_FLOWCTL_UP                  3                               /* Unicast Pause Frame Detect */
-#define BITP_EMAC_FLOWCTL_RFE                 2                               /* Receive Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_TFE                 1                               /* Transmit Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_FCBBPA              0                               /* Initiate Pause Control Frame */
-#define BITM_EMAC_FLOWCTL_PT                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Pause Time */
-#define BITM_EMAC_FLOWCTL_UP                 (_ADI_MSK(0x00000008,uint32_t))  /* Unicast Pause Frame Detect */
-#define BITM_EMAC_FLOWCTL_RFE                (_ADI_MSK(0x00000004,uint32_t))  /* Receive Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_TFE                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_FCBBPA             (_ADI_MSK(0x00000001,uint32_t))  /* Initiate Pause Control Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_VLANTAG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_VLANTAG_ETV                16                               /* Enable Tag VLAN Comparison */
-#define BITP_EMAC_VLANTAG_VL                  0                               /* VLAN Tag Id Receive Frames */
-#define BITM_EMAC_VLANTAG_ETV                (_ADI_MSK(0x00010000,uint32_t))  /* Enable Tag VLAN Comparison */
-#define BITM_EMAC_VLANTAG_VL                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* VLAN Tag Id Receive Frames */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DBG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DBG_TXFIFOFULL             25                               /* Tx FIFO Full */
-#define BITP_EMAC_DBG_TXFIFONE               24                               /* Tx FIFO Not Empty */
-#define BITP_EMAC_DBG_TXFIFOACT              22                               /* Tx FIFO Active */
-#define BITP_EMAC_DBG_TXFIFOCTLST            20                               /* Tx FIFO Controller State */
-#define BITP_EMAC_DBG_TXPAUSE                19                               /* Tx Paused */
-#define BITP_EMAC_DBG_TXFRCTL                17                               /* Tx Frame Controller State */
-#define BITP_EMAC_DBG_MMTEA                  16                               /* MM Tx Engine Active */
-#define BITP_EMAC_DBG_RXFIFOST                8                               /* Rx FIFO State */
-#define BITP_EMAC_DBG_RXFIFOCTLST             5                               /* Rx FIFO Controller State */
-#define BITP_EMAC_DBG_RXFIFOACT               4                               /* Rx FIFO Active */
-#define BITP_EMAC_DBG_SFIFOST                 1                               /* Small FIFO State */
-#define BITP_EMAC_DBG_MMREA                   0                               /* MM Rx Engine Active */
-#define BITM_EMAC_DBG_TXFIFOFULL             (_ADI_MSK(0x02000000,uint32_t))  /* Tx FIFO Full */
-#define BITM_EMAC_DBG_TXFIFONE               (_ADI_MSK(0x01000000,uint32_t))  /* Tx FIFO Not Empty */
-#define BITM_EMAC_DBG_TXFIFOACT              (_ADI_MSK(0x00400000,uint32_t))  /* Tx FIFO Active */
-#define BITM_EMAC_DBG_TXFIFOCTLST            (_ADI_MSK(0x00300000,uint32_t))  /* Tx FIFO Controller State */
-#define BITM_EMAC_DBG_TXPAUSE                (_ADI_MSK(0x00080000,uint32_t))  /* Tx Paused */
-
-#define BITM_EMAC_DBG_TXFRCTL                (_ADI_MSK(0x00060000,uint32_t))  /* Tx Frame Controller State */
-#define ENUM_EMAC_DBG_TXFRCTL_IDLE           (_ADI_MSK(0x00000000,uint32_t))  /* TXFRCTL: Idle */
-#define ENUM_EMAC_DBG_TXFRCTL_WT_STATUS      (_ADI_MSK(0x00020000,uint32_t))  /* TXFRCTL: Wait */
-#define ENUM_EMAC_DBG_TXFRCTL_PAUSE          (_ADI_MSK(0x00040000,uint32_t))  /* TXFRCTL: Pause */
-#define ENUM_EMAC_DBG_TXFRCTL_TXFRAME        (_ADI_MSK(0x00060000,uint32_t))  /* TXFRCTL: Transmit */
-#define BITM_EMAC_DBG_MMTEA                  (_ADI_MSK(0x00010000,uint32_t))  /* MM Tx Engine Active */
-
-#define BITM_EMAC_DBG_RXFIFOST               (_ADI_MSK(0x00000300,uint32_t))  /* Rx FIFO State */
-#define ENUM_EMAC_DBG_FIFO_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOST: Rx FIFO Empty */
-#define ENUM_EMAC_DBG_FIFO_BEL_THERSHLD      (_ADI_MSK(0x00000100,uint32_t))  /* RXFIFOST: Rx FIFO Below De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_ABV_THERSHLD      (_ADI_MSK(0x00000200,uint32_t))  /* RXFIFOST: Rx FIFO Above De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_FULL              (_ADI_MSK(0x00000300,uint32_t))  /* RXFIFOST: Rx FIFO Full */
-
-#define BITM_EMAC_DBG_RXFIFOCTLST            (_ADI_MSK(0x00000060,uint32_t))  /* Rx FIFO Controller State */
-#define ENUM_EMAC_DBG_IDLE_FIFO              (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOCTLST: Idle */
-#define ENUM_EMAC_DBG_RD_DATA_FIFO           (_ADI_MSK(0x00000020,uint32_t))  /* RXFIFOCTLST: Read Data */
-#define ENUM_EMAC_DBG_RD_STS_FIFO            (_ADI_MSK(0x00000040,uint32_t))  /* RXFIFOCTLST: Read Status */
-#define ENUM_EMAC_DBG_FLUSH_FIFO             (_ADI_MSK(0x00000060,uint32_t))  /* RXFIFOCTLST: Flush */
-#define BITM_EMAC_DBG_RXFIFOACT              (_ADI_MSK(0x00000010,uint32_t))  /* Rx FIFO Active */
-#define BITM_EMAC_DBG_SFIFOST                (_ADI_MSK(0x00000006,uint32_t))  /* Small FIFO State */
-#define BITM_EMAC_DBG_MMREA                  (_ADI_MSK(0x00000001,uint32_t))  /* MM Rx Engine Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ISTAT_TS                    9                               /* Time Stamp Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRC                 7                               /* MMC Receive Checksum Offload Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCTX                 6                               /* MMC Transmit Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRX                 5                               /* MMC Receive Interrupt Status */
-#define BITP_EMAC_ISTAT_MMC                   4                               /* MMC Interrupt Status */
-#define BITM_EMAC_ISTAT_TS                   (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRC                (_ADI_MSK(0x00000080,uint32_t))  /* MMC Receive Checksum Offload Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCTX                (_ADI_MSK(0x00000040,uint32_t))  /* MMC Transmit Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRX                (_ADI_MSK(0x00000020,uint32_t))  /* MMC Receive Interrupt Status */
-#define BITM_EMAC_ISTAT_MMC                  (_ADI_MSK(0x00000010,uint32_t))  /* MMC Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IMSK_TS                     9                               /* Time Stamp Interrupt Mask */
-#define BITM_EMAC_IMSK_TS                    (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ADDR0_HI                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ADDR0_HI_ADDR               0                               /* Address */
-#define BITM_EMAC_ADDR0_HI_ADDR              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_CTL_FULLPSET            5                               /* Full Preset */
-#define BITP_EMAC_MMC_CTL_CNTRPSET            4                               /* Counter Reset/Preset */
-#define BITP_EMAC_MMC_CTL_CNTRFRZ             3                               /* Counter Freeze */
-#define BITP_EMAC_MMC_CTL_RDRST               2                               /* Read Reset */
-#define BITP_EMAC_MMC_CTL_NOROLL              1                               /* No Rollover */
-#define BITP_EMAC_MMC_CTL_RST                 0                               /* Reset */
-#define BITM_EMAC_MMC_CTL_FULLPSET           (_ADI_MSK(0x00000020,uint32_t))  /* Full Preset */
-#define BITM_EMAC_MMC_CTL_CNTRPSET           (_ADI_MSK(0x00000010,uint32_t))  /* Counter Reset/Preset */
-#define BITM_EMAC_MMC_CTL_CNTRFRZ            (_ADI_MSK(0x00000008,uint32_t))  /* Counter Freeze */
-#define BITM_EMAC_MMC_CTL_RDRST              (_ADI_MSK(0x00000004,uint32_t))  /* Read Reset */
-#define BITM_EMAC_MMC_CTL_NOROLL             (_ADI_MSK(0x00000002,uint32_t))  /* No Rollover */
-#define BITM_EMAC_MMC_CTL_RST                (_ADI_MSK(0x00000001,uint32_t))  /* Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXINT_WDOGERR          23                               /* Rx Watch Dog Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_VLANFRGB         22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_FIFOOVF          21                               /* Rx FIFO Overflow Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_PAUSEFR          20                               /* Rx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OUTRANGE         19                               /* Rx Out Of Range Type Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_LENERR           18                               /* Rx Length Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_UCASTG           17                               /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R1024TOMAX       16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R512TO1023       15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R256TO511        14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R128TO255        13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R65TO127         12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R64              11                               /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OSIZEG           10                               /* Rx Oversize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_USIZEG            9                               /* Rx Undersize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_JABERR            8                               /* Rx Jabber Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_RUNTERR           7                               /* Rx Runt Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_ALIGNERR          6                               /* Rx Alignment Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_CRCERR            5                               /* Rx CRC Error Counter Half/Full */
-#define BITP_EMAC_MMC_RXINT_MCASTG            4                               /* Rx Multicast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_BCASTG            3                               /* Rx Broadcast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTG           2                               /* Octet Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTGB          1                               /* Octet Count (Good/Bad) Half/Full */
-#define BITP_EMAC_MMC_RXINT_FRCNTGB           0                               /* Frame Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_WDOGERR          (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_VLANFRGB         (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_FIFOOVF          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_PAUSEFR          (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OUTRANGE         (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_LENERR           (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_UCASTG           (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R1024TOMAX       (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R512TO1023       (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R256TO511        (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R128TO255        (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R65TO127         (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R64              (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OSIZEG           (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_USIZEG           (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_JABERR           (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_RUNTERR          (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_ALIGNERR         (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_CRCERR           (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Counter Half/Full */
-#define BITM_EMAC_MMC_RXINT_MCASTG           (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_BCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTG          (_ADI_MSK(0x00000004,uint32_t))  /* Octet Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Octet Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_FRCNTGB          (_ADI_MSK(0x00000001,uint32_t))  /* Frame Count (Good/Bad) Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXINT_VLANFRGB         24                               /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_PAUSEFRM         23                               /* Tx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSDEF        22                               /* Tx Excess Deferred Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTG           21                               /* Tx Frame Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTG          20                               /* Tx Octet Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_CARRERR          19                               /* Tx Carrier Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSCOL        18                               /* Tx Exess Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_LATECOL          17                               /* Tx Late Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_DEFERRED         16                               /* Tx Deffered Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MULTCOLG         15                               /* Tx Multiple collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_SNGCOLG          14                               /* Tx Single Collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UNDERR           13                               /* Tx Underflow Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTGB          12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTGB          11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UCASTGB          10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T1024TOMAX        9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T512TO1023        8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T256TO511         7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T128TO255         6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T65TO127          5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T64               4                               /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTG            3                               /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTG            2                               /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTGB           1                               /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTGB          0                               /* Tx Octet Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_VLANFRGB         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_PAUSEFRM         (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSDEF        (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTG           (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTG          (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_CARRERR          (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSCOL        (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_LATECOL          (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_DEFERRED         (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deffered Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MULTCOLG         (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_SNGCOLG          (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UNDERR           (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTGB          (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTGB          (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UCASTGB          (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T1024TOMAX       (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T512TO1023       (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T256TO511        (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T128TO255        (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T65TO127         (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T64              (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTG           (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTGB          (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXIMSK_WATCHERR        23                               /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_VLANFRGB        22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FIFOOV          21                               /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_PAUSEFRM        20                               /* Rx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OUTRANGE        19                               /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_LENERR          18                               /* Rx Length Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_UCASTG          17                               /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R1024TOMAX      16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R512TO1023      15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R256TO511       14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R128TO255       13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R65TO127        12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R64             11                               /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OSIZEG          10                               /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_USIZEG           9                               /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_JABERR           8                               /* Rx Jabber Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_RUNTERR          7                               /* Rx Runt Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_ALIGNERR         6                               /* Rx Alignment Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_CRCERR           5                               /* Rx CRC Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_MCASTG           4                               /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_BCASTG           3                               /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTG          2                               /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTGB         1                               /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FRCNTGB          0                               /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_WATCHERR        (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_VLANFRGB        (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FIFOOV          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_PAUSEFRM        (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OUTRANGE        (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_LENERR          (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_UCASTG          (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R1024TOMAX      (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R512TO1023      (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R256TO511       (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R128TO255       (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R65TO127        (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R64             (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OSIZEG          (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_USIZEG          (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_JABERR          (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_RUNTERR         (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_ALIGNERR        (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_CRCERR          (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_MCASTG          (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_BCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTG         (_ADI_MSK(0x00000004,uint32_t))  /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTGB        (_ADI_MSK(0x00000002,uint32_t))  /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FRCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXIMSK_VLANFRG         24                               /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_PAUSEFRM        23                               /* Tx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSDEF       22                               /* Tx Excess Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTG          21                               /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTG         20                               /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_CARRERR         19                               /* Tx Carrier Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSCOL       18                               /* Tx Exess collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_LATECOL         17                               /* Tx Late Collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_DEFERRED        16                               /* Tx Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MULTCOLG        15                               /* Tx Multiple Collisions (Good) Count Mask */
-#define BITP_EMAC_MMC_TXIMSK_SNGCOLG         14                               /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UNDERR          13                               /* Tx Underflow Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTGB         12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTGB         11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UCASTGB         10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T1024TOMAX       9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T512TO1023       8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T256TO511        7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T128TO255        6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T65TO127         5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T64              4                               /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTG           3                               /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTG           2                               /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTGB          1                               /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTGB         0                               /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_VLANFRG         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_PAUSEFRM        (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSDEF       (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTG          (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTG         (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_CARRERR         (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSCOL       (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_LATECOL         (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_DEFERRED        (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MULTCOLG        (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple Collisions (Good) Count Mask */
-#define BITM_EMAC_MMC_TXIMSK_SNGCOLG         (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UNDERR          (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTGB         (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTGB         (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UCASTGB         (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T1024TOMAX      (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T512TO1023      (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T256TO511       (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T128TO255       (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T65TO127        (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T64             (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTG          (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTGB        (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERROCT      29                               /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGOCT        28                               /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERROCT       27                               /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGOCT         26                               /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERROCT       25                               /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGOCT         24                               /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYOCT      23                               /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERROCT      22                               /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GOCT          21                               /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLOCT      20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGOCT       19                               /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYOCT      18                               /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERROCT      17                               /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GOCT          16                               /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERRFRM      13                               /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGFRM        12                               /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERRFRM       11                               /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGFRM         10                               /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERRFRM        9                               /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGFRM          8                               /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYFRM       7                               /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERRFRM       6                               /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GFRM           5                               /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLFRM       4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGFRM        3                               /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYFRM       2                               /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERRFRM       1                               /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GFRM           0                               /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERROCT      (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGOCT        (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERROCT       (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGOCT         (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERROCT       (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGOCT         (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYOCT      (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERROCT      (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GOCT          (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLOCT      (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGOCT       (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYOCT      (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERROCT      (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GOCT          (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERRFRM      (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGFRM        (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERRFRM       (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGFRM         (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERRFRM       (_ADI_MSK(0x00000200,uint32_t))  /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGFRM         (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYFRM      (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERRFRM      (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GFRM          (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLFRM      (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGFRM       (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYFRM      (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERRFRM      (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GFRM          (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXINT_ICMPERROCT       29                               /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGOCT         28                               /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERROCT        27                               /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGOCT          26                               /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERROCT        25                               /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGOCT          24                               /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYOCT       23                               /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERROCT       22                               /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GOCT           21                               /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLOCT       20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGOCT        19                               /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYOCT       18                               /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERROCT       17                               /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GOCT           16                               /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPERRFRM       13                               /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGFRM         12                               /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERRFRM        11                               /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGFRM          10                               /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERRFRM         9                               /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGFRM           8                               /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYFRM        7                               /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERRFRM        6                               /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GFRM            5                               /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLFRM        4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGFRM         3                               /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYFRM        2                               /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERRFRM        1                               /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GFRM            0                               /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERROCT       (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGOCT         (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERROCT        (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGOCT          (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERROCT        (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGOCT          (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYOCT       (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERROCT       (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GOCT           (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLOCT       (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGOCT        (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYOCT       (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERROCT       (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GOCT           (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERRFRM       (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGFRM         (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERRFRM        (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGFRM          (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERRFRM        (_ADI_MSK(0x00000200,uint32_t))  /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGFRM          (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYFRM       (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERRFRM       (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GFRM           (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLFRM       (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGFRM        (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYFRM       (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERRFRM       (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GFRM           (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_CTL_ATSFC               24                               /* Auxilary Time Stamp FIFO Clear */
-#define BITP_EMAC_TM_CTL_TSENMACADDR         18                               /* Time Stamp Enable MAC Address */
-#define BITP_EMAC_TM_CTL_SNAPTYPSEL          16                               /* Snapshot Type Select */
-#define BITP_EMAC_TM_CTL_TSMSTRENA           15                               /* Time Stamp Master (Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSEVNTENA           14                               /* Time Stamp Event (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV4ENA           13                               /* Time Stamp IPV4 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV6ENA           12                               /* Time Stamp IPV6 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPENA             11                               /* Time Stamp IP Enable */
-#define BITP_EMAC_TM_CTL_TSVER2ENA           10                               /* Time Stamp VER2 (Snooping) Enable */
-#define BITP_EMAC_TM_CTL_TSCTRLSSR            9                               /* Time Stamp Control Nanosecond Rollover */
-#define BITP_EMAC_TM_CTL_TSENALL              8                               /* Time Stamp Enable All (Frames) */
-#define BITP_EMAC_TM_CTL_TSADDREG             5                               /* Time Stamp Addend Register Update */
-#define BITP_EMAC_TM_CTL_TSTRIG               4                               /* Time Stamp (Target Time) Trigger Enable */
-#define BITP_EMAC_TM_CTL_TSUPDT               3                               /* Time Stamp (System Time) Update */
-#define BITP_EMAC_TM_CTL_TSINIT               2                               /* Time Stamp (System Time) Initialize */
-#define BITP_EMAC_TM_CTL_TSCFUPDT             1                               /* Time Stamp (System Time) Fine/Coarse Update */
-#define BITP_EMAC_TM_CTL_TSENA                0                               /* Time Stamp (PTP) Enable */
-#define BITM_EMAC_TM_CTL_ATSFC               (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp FIFO Clear */
-
-#define BITM_EMAC_TM_CTL_TSENMACADDR         (_ADI_MSK(0x00040000,uint32_t))  /* Time Stamp Enable MAC Address */
-#define ENUM_EMAC_TM_CTL_D_PTP_ADDRFILT      (_ADI_MSK(0x00000000,uint32_t))  /* TSENMACADDR: Disable PTP MAC address filter */
-#define ENUM_EMAC_TM_CTL_E_PTP_ADDRFILT      (_ADI_MSK(0x00040000,uint32_t))  /* TSENMACADDR: Enable PTP MAC address filter */
-#define BITM_EMAC_TM_CTL_SNAPTYPSEL          (_ADI_MSK(0x00030000,uint32_t))  /* Snapshot Type Select */
-
-#define BITM_EMAC_TM_CTL_TSMSTRENA           (_ADI_MSK(0x00008000,uint32_t))  /* Time Stamp Master (Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_SLVSNPT_MSGS      (_ADI_MSK(0x00000000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Slave Messages */
-#define ENUM_EMAC_TM_CTL_E_MSSNPST_MSGS      (_ADI_MSK(0x00008000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Master Messages */
-
-#define BITM_EMAC_TM_CTL_TSEVNTENA           (_ADI_MSK(0x00004000,uint32_t))  /* Time Stamp Event (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_ATSTMP_MSGS       (_ADI_MSK(0x00000000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for All Messages */
-#define ENUM_EMAC_TM_CTL_E_ETSTMP_MSGS       (_ADI_MSK(0x00004000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for Event Messages Only */
-
-#define BITM_EMAC_TM_CTL_TSIPV4ENA           (_ADI_MSK(0x00002000,uint32_t))  /* Time Stamp IPV4 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV4        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV4ENA: Disable Time Stamp for PTP Over IPv4 Frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV4        (_ADI_MSK(0x00002000,uint32_t))  /* TSIPV4ENA: Enable Time Stamp for PTP Over IPv4 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPV6ENA           (_ADI_MSK(0x00001000,uint32_t))  /* Time Stamp IPV6 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV6        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV6ENA: Disable Time Stamp for PTP Over IPv6 frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV6        (_ADI_MSK(0x00001000,uint32_t))  /* TSIPV6ENA: Enable Time Stamp for PTP Over IPv6 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPENA             (_ADI_MSK(0x00000800,uint32_t))  /* Time Stamp IP Enable */
-#define ENUM_EMAC_TM_CTL_D_PTP_OV_ETHER      (_ADI_MSK(0x00000000,uint32_t))  /* TSIPENA: Disable PTP Over Ethernet Frames */
-#define ENUM_EMAC_TM_CTL_E_PTP_OV_ETHER      (_ADI_MSK(0x00000800,uint32_t))  /* TSIPENA: Enable PTP Over Ethernet Frames */
-
-#define BITM_EMAC_TM_CTL_TSVER2ENA           (_ADI_MSK(0x00000400,uint32_t))  /* Time Stamp VER2 (Snooping) Enable */
-#define ENUM_EMAC_TM_CTL_D_PKT_SNOOP_V2      (_ADI_MSK(0x00000000,uint32_t))  /* TSVER2ENA: Disable packet snooping for V2 frames */
-#define ENUM_EMAC_TM_CTL_E_PKT_SNOOP_V2      (_ADI_MSK(0x00000400,uint32_t))  /* TSVER2ENA: Enable packet snooping for V2 frames */
-
-#define BITM_EMAC_TM_CTL_TSCTRLSSR           (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Control Nanosecond Rollover */
-#define ENUM_EMAC_TM_CTL_RO_SUBSEC_RES       (_ADI_MSK(0x00000000,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x7FFFFFFF */
-#define ENUM_EMAC_TM_CTL_RO_NANO_RES         (_ADI_MSK(0x00000200,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x3B9AC9FF */
-
-#define BITM_EMAC_TM_CTL_TSENALL             (_ADI_MSK(0x00000100,uint32_t))  /* Time Stamp Enable All (Frames) */
-#define ENUM_EMAC_TM_CTL_D_TSALL_FRAMES      (_ADI_MSK(0x00000000,uint32_t))  /* TSENALL: Disable timestamp for all frames */
-#define ENUM_EMAC_TM_CTL_E_TSALL_FRAMES      (_ADI_MSK(0x00000100,uint32_t))  /* TSENALL: Enable timestamp for all frames */
-#define BITM_EMAC_TM_CTL_TSADDREG            (_ADI_MSK(0x00000020,uint32_t))  /* Time Stamp Addend Register Update */
-
-#define BITM_EMAC_TM_CTL_TSTRIG              (_ADI_MSK(0x00000010,uint32_t))  /* Time Stamp (Target Time) Trigger Enable */
-#define ENUM_EMAC_TM_CTL_EN_TRIGGER          (_ADI_MSK(0x00000010,uint32_t))  /* TSTRIG: Interrupt (TS) if system time is greater than target time register */
-
-#define BITM_EMAC_TM_CTL_TSUPDT              (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp (System Time) Update */
-#define ENUM_EMAC_TM_CTL_EN_UPDATE           (_ADI_MSK(0x00000008,uint32_t))  /* TSUPDT: System time updated with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSINIT              (_ADI_MSK(0x00000004,uint32_t))  /* Time Stamp (System Time) Initialize */
-#define ENUM_EMAC_TM_CTL_EN_TS_INIT          (_ADI_MSK(0x00000004,uint32_t))  /* TSINIT: System time initialized with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSCFUPDT            (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp (System Time) Fine/Coarse Update */
-#define ENUM_EMAC_TM_CTL_EN_COARSE_UPDT      (_ADI_MSK(0x00000000,uint32_t))  /* TSCFUPDT: Use Coarse Correction Method for System Time Update */
-#define ENUM_EMAC_TM_CTL_EN_FINE_UPDT        (_ADI_MSK(0x00000002,uint32_t))  /* TSCFUPDT: Use Fine Correction Method for System Time Update */
-
-#define BITM_EMAC_TM_CTL_TSENA               (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp (PTP) Enable */
-#define ENUM_EMAC_TM_CTL_DTS                 (_ADI_MSK(0x00000000,uint32_t))  /* TSENA: Disable PTP Module */
-#define ENUM_EMAC_TM_CTL_TS                  (_ADI_MSK(0x00000001,uint32_t))  /* TSENA: Enable PTP Module */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_SUBSEC                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_SUBSEC_SSINC             0                               /* Sub-Second Increment Value */
-#define BITM_EMAC_TM_SUBSEC_SSINC            (_ADI_MSK(0x000000FF,uint32_t))  /* Sub-Second Increment Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSEC                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSEC_TSSS                0                               /* Time Stamp Nanoseconds */
-#define BITM_EMAC_TM_NSEC_TSSS               (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Nanoseconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSECUPDT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSECUPDT_ADDSUB         31                               /* Add or Subtract the Time */
-#define BITP_EMAC_TM_NSECUPDT_TSSS            0                               /* Time Stamp Sub Second Initialize/Increment */
-#define BITM_EMAC_TM_NSECUPDT_ADDSUB         (_ADI_MSK(0x80000000,uint32_t))  /* Add or Subtract the Time */
-#define BITM_EMAC_TM_NSECUPDT_TSSS           (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Sub Second Initialize/Increment */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NTGTM                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NTGTM_TSTRBUSY          31                               /* Target Time Register Busy */
-#define BITP_EMAC_TM_NTGTM_TSTR               0                               /* Target Time Nano Seconds */
-#define BITM_EMAC_TM_NTGTM_TSTRBUSY          (_ADI_MSK(0x80000000,uint32_t))  /* Target Time Register Busy */
-#define BITM_EMAC_TM_NTGTM_TSTR              (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Target Time Nano Seconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_HISEC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_HISEC_TSHWR              0                               /* Time Stamp Higher Word Seconds Register */
-#define BITM_EMAC_TM_HISEC_TSHWR             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Time Stamp Higher Word Seconds Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_STMPSTAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_STMPSTAT_ATSNS          25                               /* Auxilary Time Stamp Number of Snapshots */
-#define BITP_EMAC_TM_STMPSTAT_ATSSTM         24                               /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITP_EMAC_TM_STMPSTAT_TSTRGTERR       3                               /* Time Stamp Target Time Programming Error */
-#define BITP_EMAC_TM_STMPSTAT_ATSTS           2                               /* Auxilary Time Stamp Trigger Snapshot */
-#define BITP_EMAC_TM_STMPSTAT_TSTARGT         1                               /* Time Stamp Target Time Reached */
-#define BITP_EMAC_TM_STMPSTAT_TSSOVF          0                               /* Time Stamp Seconds Overflow */
-#define BITM_EMAC_TM_STMPSTAT_ATSNS          (_ADI_MSK(0x0E000000,uint32_t))  /* Auxilary Time Stamp Number of Snapshots */
-#define BITM_EMAC_TM_STMPSTAT_ATSSTM         (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITM_EMAC_TM_STMPSTAT_TSTRGTERR      (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp Target Time Programming Error */
-#define BITM_EMAC_TM_STMPSTAT_ATSTS          (_ADI_MSK(0x00000004,uint32_t))  /* Auxilary Time Stamp Trigger Snapshot */
-#define BITM_EMAC_TM_STMPSTAT_TSTARGT        (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp Target Time Reached */
-#define BITM_EMAC_TM_STMPSTAT_TSSOVF         (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp Seconds Overflow */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_PPSCTL                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_PPSCTL_TRGTMODSEL        5                               /* Target Time Register Mode */
-#define BITP_EMAC_TM_PPSCTL_PPSEN             4                               /* Enable the flexible PPS output mode */
-#define BITP_EMAC_TM_PPSCTL_PPSCTL            0                               /* PPS Frequency Control */
-#define BITM_EMAC_TM_PPSCTL_TRGTMODSEL       (_ADI_MSK(0x00000060,uint32_t))  /* Target Time Register Mode */
-#define BITM_EMAC_TM_PPSCTL_PPSEN            (_ADI_MSK(0x00000010,uint32_t))  /* Enable the flexible PPS output mode */
-#define BITM_EMAC_TM_PPSCTL_PPSCTL           (_ADI_MSK(0x0000000F,uint32_t))  /* PPS Frequency Control */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BUSMODE                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BUSMODE_AAL            25                               /* Address Aligned Bursts */
-#define BITP_EMAC_DMA_BUSMODE_PBL8           24                               /* PBL * 8 */
-#define BITP_EMAC_DMA_BUSMODE_USP            23                               /* Use Separate PBL */
-#define BITP_EMAC_DMA_BUSMODE_RPBL           17                               /* Receive Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_FB             16                               /* Fixed Burst */
-#define BITP_EMAC_DMA_BUSMODE_PBL             8                               /* Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_ATDS            7                               /* Alternate Descriptor Size */
-#define BITP_EMAC_DMA_BUSMODE_DSL             2                               /* Descriptor Skip Length */
-#define BITP_EMAC_DMA_BUSMODE_SWR             0                               /* Software Reset */
-#define BITM_EMAC_DMA_BUSMODE_AAL            (_ADI_MSK(0x02000000,uint32_t))  /* Address Aligned Bursts */
-#define BITM_EMAC_DMA_BUSMODE_PBL8           (_ADI_MSK(0x01000000,uint32_t))  /* PBL * 8 */
-#define BITM_EMAC_DMA_BUSMODE_USP            (_ADI_MSK(0x00800000,uint32_t))  /* Use Separate PBL */
-#define BITM_EMAC_DMA_BUSMODE_RPBL           (_ADI_MSK(0x007E0000,uint32_t))  /* Receive Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_FB             (_ADI_MSK(0x00010000,uint32_t))  /* Fixed Burst */
-#define BITM_EMAC_DMA_BUSMODE_PBL            (_ADI_MSK(0x00003F00,uint32_t))  /* Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_ATDS           (_ADI_MSK(0x00000080,uint32_t))  /* Alternate Descriptor Size */
-#define BITM_EMAC_DMA_BUSMODE_DSL            (_ADI_MSK(0x0000007C,uint32_t))  /* Descriptor Skip Length */
-#define BITM_EMAC_DMA_BUSMODE_SWR            (_ADI_MSK(0x00000001,uint32_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_STAT_TTI               29                               /* Time Stamp Trigger Interrupt */
-#define BITP_EMAC_DMA_STAT_MCI               27                               /* MAC MMC Interrupt */
-#define BITP_EMAC_DMA_STAT_EB                23                               /* Error Bits */
-#define BITP_EMAC_DMA_STAT_TS                20                               /* Transmit Process State */
-#define BITP_EMAC_DMA_STAT_RS                17                               /* Receive Process State */
-#define BITP_EMAC_DMA_STAT_NIS               16                               /* Normal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_AIS               15                               /* Abnormal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_ERI               14                               /* Early Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_FBI               13                               /* Fatal Bus Error Interrupt */
-#define BITP_EMAC_DMA_STAT_ETI               10                               /* Early Transmit Interrupt */
-#define BITP_EMAC_DMA_STAT_RWT                9                               /* Receive WatchDog Timeout */
-#define BITP_EMAC_DMA_STAT_RPS                8                               /* Receive Process Stopped */
-#define BITP_EMAC_DMA_STAT_RU                 7                               /* Receive Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_RI                 6                               /* Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_UNF                5                               /* Transmit Buffer Underflow */
-#define BITP_EMAC_DMA_STAT_OVF                4                               /* Receive Buffer Overflow */
-#define BITP_EMAC_DMA_STAT_TJT                3                               /* Transmit Jabber Timeout */
-#define BITP_EMAC_DMA_STAT_TU                 2                               /* Transmit Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_TPS                1                               /* Transmit Process Stopped */
-#define BITP_EMAC_DMA_STAT_TI                 0                               /* Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_TTI               (_ADI_MSK(0x20000000,uint32_t))  /* Time Stamp Trigger Interrupt */
-#define BITM_EMAC_DMA_STAT_MCI               (_ADI_MSK(0x08000000,uint32_t))  /* MAC MMC Interrupt */
-#define BITM_EMAC_DMA_STAT_EB                (_ADI_MSK(0x03800000,uint32_t))  /* Error Bits */
-
-#define BITM_EMAC_DMA_STAT_TS                (_ADI_MSK(0x00700000,uint32_t))  /* Transmit Process State */
-#define ENUM_EMAC_DMA_STAT_TS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* TS: Stopped; Reset or Stop Transmit Command issued */
-#define ENUM_EMAC_DMA_STAT_TS_R_FTD          (_ADI_MSK(0x00100000,uint32_t))  /* TS: Running; Fetching Transmit Transfer Descriptor */
-#define ENUM_EMAC_DMA_STAT_TS_R_WSTAT        (_ADI_MSK(0x00200000,uint32_t))  /* TS: Running; Waiting for status */
-#define ENUM_EMAC_DMA_STAT_TS_R_TXHMBUF      (_ADI_MSK(0x00300000,uint32_t))  /* TS: Reading Data from host memory buffer and queuing it to TX buffer */
-#define ENUM_EMAC_DMA_STAT_TS_WR_TSTMP       (_ADI_MSK(0x00400000,uint32_t))  /* TS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_TS_SUSPENDED      (_ADI_MSK(0x00600000,uint32_t))  /* TS: Suspended; Transmit Descriptor Unavailable or TX Buffer Underflow */
-#define ENUM_EMAC_DMA_STAT_TS_R_CLSTD        (_ADI_MSK(0x00700000,uint32_t))  /* TS: Closing Transmit Descriptor */
-
-#define BITM_EMAC_DMA_STAT_RS                (_ADI_MSK(0x000E0000,uint32_t))  /* Receive Process State */
-#define ENUM_EMAC_DMA_STAT_RS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* RS: Stopped: Reset or Stop Receive Command issued. */
-#define ENUM_EMAC_DMA_STAT_RS_R_FRD          (_ADI_MSK(0x00020000,uint32_t))  /* RS: Running: Fetching Receive Transfer Descriptor. */
-#define ENUM_EMAC_DMA_STAT_RS_R_WTRX         (_ADI_MSK(0x00060000,uint32_t))  /* RS: Running: Waiting for receive packet */
-#define ENUM_EMAC_DMA_STAT_RS_SUSPENDED      (_ADI_MSK(0x00080000,uint32_t))  /* RS: Suspended: Receive Descriptor Unavailable */
-#define ENUM_EMAC_DMA_STAT_RS_R_CLSRD        (_ADI_MSK(0x000A0000,uint32_t))  /* RS: Running: Closing Receive Descriptor */
-#define ENUM_EMAC_DMA_STAT_RS_WR_TSTMP       (_ADI_MSK(0x000C0000,uint32_t))  /* RS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_RS_R_RXWRHM       (_ADI_MSK(0x000E0000,uint32_t))  /* RS: Running: Transferring RX packet data from RX buffer to host memory */
-#define BITM_EMAC_DMA_STAT_NIS               (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_AIS               (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_ERI               (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_FBI               (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Interrupt */
-#define BITM_EMAC_DMA_STAT_ETI               (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_RWT               (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchDog Timeout */
-#define BITM_EMAC_DMA_STAT_RPS               (_ADI_MSK(0x00000100,uint32_t))  /* Receive Process Stopped */
-#define BITM_EMAC_DMA_STAT_RU                (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_RI                (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_UNF               (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Buffer Underflow */
-#define BITM_EMAC_DMA_STAT_OVF               (_ADI_MSK(0x00000010,uint32_t))  /* Receive Buffer Overflow */
-#define BITM_EMAC_DMA_STAT_TJT               (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout */
-#define BITM_EMAC_DMA_STAT_TU                (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_TPS               (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Process Stopped */
-#define BITM_EMAC_DMA_STAT_TI                (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_OPMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_OPMODE_DT              26                               /* Disable Dropping TCP/IP Errors */
-#define BITP_EMAC_DMA_OPMODE_RSF             25                               /* Receive Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_DFF             24                               /* Disable Flushing of received Frames */
-#define BITP_EMAC_DMA_OPMODE_TSF             21                               /* Transmit Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_FTF             20                               /* Flush Transmit FIFO */
-#define BITP_EMAC_DMA_OPMODE_TTC             14                               /* Transmit Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_ST              13                               /* Start/Stop Transmission */
-#define BITP_EMAC_DMA_OPMODE_FEF              7                               /* Forward Error Frames */
-#define BITP_EMAC_DMA_OPMODE_FUF              6                               /* Forward Undersized good Frames */
-#define BITP_EMAC_DMA_OPMODE_RTC              3                               /* Receive Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_OSF              2                               /* Operate on Second Frame */
-#define BITP_EMAC_DMA_OPMODE_SR               1                               /* Start/Stop Receive */
-#define BITM_EMAC_DMA_OPMODE_DT              (_ADI_MSK(0x04000000,uint32_t))  /* Disable Dropping TCP/IP Errors */
-#define BITM_EMAC_DMA_OPMODE_RSF             (_ADI_MSK(0x02000000,uint32_t))  /* Receive Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_DFF             (_ADI_MSK(0x01000000,uint32_t))  /* Disable Flushing of received Frames */
-#define BITM_EMAC_DMA_OPMODE_TSF             (_ADI_MSK(0x00200000,uint32_t))  /* Transmit Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_FTF             (_ADI_MSK(0x00100000,uint32_t))  /* Flush Transmit FIFO */
-
-#define BITM_EMAC_DMA_OPMODE_TTC             (_ADI_MSK(0x0001C000,uint32_t))  /* Transmit Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_TTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* TTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_128         (_ADI_MSK(0x00004000,uint32_t))  /* TTC: 128 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_192         (_ADI_MSK(0x00008000,uint32_t))  /* TTC: 192 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_256         (_ADI_MSK(0x0000C000,uint32_t))  /* TTC: 256 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_40          (_ADI_MSK(0x00010000,uint32_t))  /* TTC: 40 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_32          (_ADI_MSK(0x00014000,uint32_t))  /* TTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_24          (_ADI_MSK(0x00018000,uint32_t))  /* TTC: 24 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_16          (_ADI_MSK(0x0001C000,uint32_t))  /* TTC: 16 */
-#define BITM_EMAC_DMA_OPMODE_ST              (_ADI_MSK(0x00002000,uint32_t))  /* Start/Stop Transmission */
-#define BITM_EMAC_DMA_OPMODE_FEF             (_ADI_MSK(0x00000080,uint32_t))  /* Forward Error Frames */
-#define BITM_EMAC_DMA_OPMODE_FUF             (_ADI_MSK(0x00000040,uint32_t))  /* Forward Undersized good Frames */
-
-#define BITM_EMAC_DMA_OPMODE_RTC             (_ADI_MSK(0x00000018,uint32_t))  /* Receive Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_RTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* RTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_32          (_ADI_MSK(0x00000008,uint32_t))  /* RTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_96          (_ADI_MSK(0x00000010,uint32_t))  /* RTC: 96 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_128         (_ADI_MSK(0x00000018,uint32_t))  /* RTC: 128 */
-#define BITM_EMAC_DMA_OPMODE_OSF             (_ADI_MSK(0x00000004,uint32_t))  /* Operate on Second Frame */
-#define BITM_EMAC_DMA_OPMODE_SR              (_ADI_MSK(0x00000002,uint32_t))  /* Start/Stop Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_IEN                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_IEN_NIS                16                               /* Normal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_AIS                15                               /* Abnormal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_ERI                14                               /* Early Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_FBI                13                               /* Fatal Bus Error Enable */
-#define BITP_EMAC_DMA_IEN_ETI                10                               /* Early Transmit Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_RWT                 9                               /* Receive WatchdogTimeout Enable */
-#define BITP_EMAC_DMA_IEN_RPS                 8                               /* Receive Stopped Enable */
-#define BITP_EMAC_DMA_IEN_RU                  7                               /* Receive Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_RI                  6                               /* Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_UNF                 5                               /* Underflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_OVF                 4                               /* Overflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_TJT                 3                               /* Transmit Jabber Timeout Enable */
-#define BITP_EMAC_DMA_IEN_TU                  2                               /* Transmit Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_TPS                 1                               /* Transmit Stopped Enable */
-#define BITP_EMAC_DMA_IEN_TI                  0                               /* Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_NIS                (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_AIS                (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_ERI                (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_FBI                (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Enable */
-#define BITM_EMAC_DMA_IEN_ETI                (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_RWT                (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchdogTimeout Enable */
-#define BITM_EMAC_DMA_IEN_RPS                (_ADI_MSK(0x00000100,uint32_t))  /* Receive Stopped Enable */
-#define BITM_EMAC_DMA_IEN_RU                 (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_RI                 (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_UNF                (_ADI_MSK(0x00000020,uint32_t))  /* Underflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_OVF                (_ADI_MSK(0x00000010,uint32_t))  /* Overflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_TJT                (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout Enable */
-#define BITM_EMAC_DMA_IEN_TU                 (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_TPS                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Stopped Enable */
-#define BITM_EMAC_DMA_IEN_TI                 (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_MISS_FRM                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_MISS_FRM_OVFFIFO       28                               /* Overflow bit for FIFO Overflow Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFROV      17                               /* Missed Frames Buffer Overflow */
-#define BITP_EMAC_DMA_MISS_FRM_OVFMISS       16                               /* Overflow bit for Missed Frame Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFRUN       0                               /* Missed Frames Unavailable Buffer */
-#define BITM_EMAC_DMA_MISS_FRM_OVFFIFO       (_ADI_MSK(0x10000000,uint32_t))  /* Overflow bit for FIFO Overflow Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFROV      (_ADI_MSK(0x0FFE0000,uint32_t))  /* Missed Frames Buffer Overflow */
-#define BITM_EMAC_DMA_MISS_FRM_OVFMISS       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow bit for Missed Frame Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFRUN      (_ADI_MSK(0x0000FFFF,uint32_t))  /* Missed Frames Unavailable Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_RXIWDOG                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_RXIWDOG_RIWT            0                               /* RI WatchDog Timer Count */
-#define BITM_EMAC_DMA_RXIWDOG_RIWT           (_ADI_MSK(0x000000FF,uint32_t))  /* RI WatchDog Timer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMMODE_WROSRLMT        20                               /* SCB Maximum Write Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_RDOSRLMT        16                               /* SCB Maximum Read Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_AAL             12                               /* Address Aligned Beats */
-#define BITP_EMAC_DMA_BMMODE_BLEN16           3                               /* SCB Burst Length 16 */
-#define BITP_EMAC_DMA_BMMODE_BLEN8            2                               /* SCB Burst Length 8 */
-#define BITP_EMAC_DMA_BMMODE_BLEN4            1                               /* SCB Burst Length 4 */
-#define BITP_EMAC_DMA_BMMODE_UNDEF            0                               /* SCB Undefined Burst Length */
-#define BITM_EMAC_DMA_BMMODE_WROSRLMT        (_ADI_MSK(0x00700000,uint32_t))  /* SCB Maximum Write Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_RDOSRLMT        (_ADI_MSK(0x00070000,uint32_t))  /* SCB Maximum Read Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_AAL             (_ADI_MSK(0x00001000,uint32_t))  /* Address Aligned Beats */
-#define BITM_EMAC_DMA_BMMODE_BLEN16          (_ADI_MSK(0x00000008,uint32_t))  /* SCB Burst Length 16 */
-#define BITM_EMAC_DMA_BMMODE_BLEN8           (_ADI_MSK(0x00000004,uint32_t))  /* SCB Burst Length 8 */
-#define BITM_EMAC_DMA_BMMODE_BLEN4           (_ADI_MSK(0x00000002,uint32_t))  /* SCB Burst Length 4 */
-#define BITM_EMAC_DMA_BMMODE_UNDEF           (_ADI_MSK(0x00000001,uint32_t))  /* SCB Undefined Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMSTAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMSTAT_BUSRD            1                               /* Bus (SCB master) Read Active */
-#define BITP_EMAC_DMA_BMSTAT_BUSWR            0                               /* Bus (SCB master) Write Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSRD           (_ADI_MSK(0x00000002,uint32_t))  /* Bus (SCB master) Read Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSWR           (_ADI_MSK(0x00000001,uint32_t))  /* Bus (SCB master) Write Active */
-
-/* ==================================================
-        Serial Port Registers
-   ================================================== */
-
-/* =========================
-        SPORT0
-   ========================= */
-#define REG_SPORT0_CTL_A                0xFFC40000         /* SPORT0 Half SPORT 'A' Control Register */
-#define REG_SPORT0_DIV_A                0xFFC40004         /* SPORT0 Half SPORT 'A' Divisor Register */
-#define REG_SPORT0_MCTL_A               0xFFC40008         /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT0_CS0_A                0xFFC4000C         /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_A                0xFFC40010         /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_A                0xFFC40014         /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT0_CS3_A                0xFFC40018         /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT0_ERR_A                0xFFC40020         /* SPORT0 Half SPORT 'A' Error Register */
-#define REG_SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_A               0xFFC40028         /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT0_CTL_B                0xFFC40080         /* SPORT0 Half SPORT 'B' Control Register */
-#define REG_SPORT0_DIV_B                0xFFC40084         /* SPORT0 Half SPORT 'B' Divisor Register */
-#define REG_SPORT0_MCTL_B               0xFFC40088         /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT0_CS0_B                0xFFC4008C         /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_B                0xFFC40090         /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_B                0xFFC40094         /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT0_CS3_B                0xFFC40098         /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT0_ERR_B                0xFFC400A0         /* SPORT0 Half SPORT 'B' Error Register */
-#define REG_SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT1
-   ========================= */
-#define REG_SPORT1_CTL_A                0xFFC40100         /* SPORT1 Half SPORT 'A' Control Register */
-#define REG_SPORT1_DIV_A                0xFFC40104         /* SPORT1 Half SPORT 'A' Divisor Register */
-#define REG_SPORT1_MCTL_A               0xFFC40108         /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT1_CS0_A                0xFFC4010C         /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_A                0xFFC40110         /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_A                0xFFC40114         /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT1_CS3_A                0xFFC40118         /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT1_ERR_A                0xFFC40120         /* SPORT1 Half SPORT 'A' Error Register */
-#define REG_SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_A               0xFFC40128         /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT1_CTL_B                0xFFC40180         /* SPORT1 Half SPORT 'B' Control Register */
-#define REG_SPORT1_DIV_B                0xFFC40184         /* SPORT1 Half SPORT 'B' Divisor Register */
-#define REG_SPORT1_MCTL_B               0xFFC40188         /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT1_CS0_B                0xFFC4018C         /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_B                0xFFC40190         /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_B                0xFFC40194         /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT1_CS3_B                0xFFC40198         /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT1_ERR_B                0xFFC401A0         /* SPORT1 Half SPORT 'B' Error Register */
-#define REG_SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT2
-   ========================= */
-#define REG_SPORT2_CTL_A                0xFFC40200         /* SPORT2 Half SPORT 'A' Control Register */
-#define REG_SPORT2_DIV_A                0xFFC40204         /* SPORT2 Half SPORT 'A' Divisor Register */
-#define REG_SPORT2_MCTL_A               0xFFC40208         /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT2_CS0_A                0xFFC4020C         /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_A                0xFFC40210         /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_A                0xFFC40214         /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT2_CS3_A                0xFFC40218         /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT2_ERR_A                0xFFC40220         /* SPORT2 Half SPORT 'A' Error Register */
-#define REG_SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_A               0xFFC40228         /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT2_CTL_B                0xFFC40280         /* SPORT2 Half SPORT 'B' Control Register */
-#define REG_SPORT2_DIV_B                0xFFC40284         /* SPORT2 Half SPORT 'B' Divisor Register */
-#define REG_SPORT2_MCTL_B               0xFFC40288         /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT2_CS0_B                0xFFC4028C         /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_B                0xFFC40290         /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_B                0xFFC40294         /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT2_CS3_B                0xFFC40298         /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT2_ERR_B                0xFFC402A0         /* SPORT2 Half SPORT 'B' Error Register */
-#define REG_SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_A_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_DXSPRI                30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_A_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_DERRPRI               29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_A_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_DXSSEC                27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_A_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_DERRSEC               26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_A_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_SPTRAN                25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_A_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_SPENSEC               24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_A_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_GCLKEN                21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_A_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_TFIEN                 20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_A_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_FSED                  19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_A_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_RJUST                 18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_A_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_LAFS                  17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_A_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_LFS                   16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_A_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_DIFS                  15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_A_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_IFS                   14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_A_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_FSR                   13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_A_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_CKRE                  12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_A_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_OPMODE                11                               /* Operation mode */
-#define BITP_SPORT_CTL_A_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_ICLK                  10                               /* Internal Clock */
-#define BITP_SPORT_CTL_A_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_PACK                   9                               /* Packing Enable */
-#define BITP_SPORT_CTL_A_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_SLEN                   4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_A_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_LSBF                   3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_A_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_DTYPE                  1                               /* Data Type */
-#define BITP_SPORT_CTL_A_SPENPRI              0                               /* Serial Port Enable (Primary) */
-#define BITP_SPORT_CTL_SPENPRI                0                               /* Serial Port Enable (Primary) */
-
-#define BITM_SPORT_CTL_A_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_DXSPRI                (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSPRI: Empty */
-#define ENUM_SPORT_CTL_PRM_PART_FULL         (_ADI_MSK(0x80000000,uint32_t))  /* DXSPRI: Partially full */
-#define ENUM_SPORT_CTL_PRM_FULL              (_ADI_MSK(0xC0000000,uint32_t))  /* DXSPRI: Full */
-
-#define BITM_SPORT_CTL_A_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_DERRPRI               (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRPRI: No error */
-#define ENUM_SPORT_CTL_PRM_ERR               (_ADI_MSK(0x20000000,uint32_t))  /* DERRPRI: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_DXSSEC                (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSSEC: Empty */
-#define ENUM_SPORT_CTL_SEC_PART_FULL         (_ADI_MSK(0x10000000,uint32_t))  /* DXSSEC: Partially full */
-#define ENUM_SPORT_CTL_SEC_FULL              (_ADI_MSK(0x18000000,uint32_t))  /* DXSSEC: Full */
-
-#define BITM_SPORT_CTL_A_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_DERRSEC               (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRSEC: No error */
-#define ENUM_SPORT_CTL_SEC_ERR               (_ADI_MSK(0x04000000,uint32_t))  /* DERRSEC: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_SPTRAN                (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define ENUM_SPORT_CTL_RX                    (_ADI_MSK(0x00000000,uint32_t))  /* SPTRAN: Receive */
-#define ENUM_SPORT_CTL_TX                    (_ADI_MSK(0x02000000,uint32_t))  /* SPTRAN: Transmit */
-
-#define BITM_SPORT_CTL_A_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_SPENSEC               (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define ENUM_SPORT_CTL_SECONDARY_DIS         (_ADI_MSK(0x00000000,uint32_t))  /* SPENSEC: Disable */
-#define ENUM_SPORT_CTL_SECONDARY_EN          (_ADI_MSK(0x01000000,uint32_t))  /* SPENSEC: Enable */
-
-#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_GCLKEN                (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define ENUM_SPORT_CTL_GCLK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* GCLKEN: Disable */
-#define ENUM_SPORT_CTL_GCLK_EN               (_ADI_MSK(0x00200000,uint32_t))  /* GCLKEN: Enable */
-
-#define BITM_SPORT_CTL_A_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_TFIEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define ENUM_SPORT_CTL_TXFIN_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TFIEN: Last word sent (DMA count done) interrupt */
-#define ENUM_SPORT_CTL_TXFIN_EN              (_ADI_MSK(0x00100000,uint32_t))  /* TFIEN: Last bit sent (Tx buffer done) interrupt */
-
-#define BITM_SPORT_CTL_A_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_FSED                  (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define ENUM_SPORT_CTL_LEVEL_FS              (_ADI_MSK(0x00000000,uint32_t))  /* FSED: Level detect frame sync */
-#define ENUM_SPORT_CTL_EDGE_FS               (_ADI_MSK(0x00080000,uint32_t))  /* FSED: Edge detect frame sync */
-
-#define BITM_SPORT_CTL_A_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_RJUST                 (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define ENUM_SPORT_CTL_RJUST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RJUST: Disable */
-#define ENUM_SPORT_CTL_RJUST_EN              (_ADI_MSK(0x00040000,uint32_t))  /* RJUST: Enable */
-
-#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_LAFS                  (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define ENUM_SPORT_CTL_EARLY_FS              (_ADI_MSK(0x00000000,uint32_t))  /* LAFS: Early frame sync */
-#define ENUM_SPORT_CTL_LATE_FS               (_ADI_MSK(0x00020000,uint32_t))  /* LAFS: Late frame sync */
-
-#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_LFS                   (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define ENUM_SPORT_CTL_FS_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* LFS: Active high frame sync (DSP standard mode) */
-#define ENUM_SPORT_CTL_FS_HI                 (_ADI_MSK(0x00010000,uint32_t))  /* LFS: Active low frame sync (DSP standard mode) */
-
-#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_DIFS                  (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define ENUM_SPORT_CTL_DATA_DEP_FS           (_ADI_MSK(0x00000000,uint32_t))  /* DIFS: Data-dependent frame sync */
-#define ENUM_SPORT_CTL_DATA_INDP_FS          (_ADI_MSK(0x00008000,uint32_t))  /* DIFS: Data-independent frame sync */
-
-#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_IFS                   (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define ENUM_SPORT_CTL_EXTERNAL_FS           (_ADI_MSK(0x00000000,uint32_t))  /* IFS: External frame sync */
-#define ENUM_SPORT_CTL_INTERNAL_FS           (_ADI_MSK(0x00004000,uint32_t))  /* IFS: Internal frame sync */
-
-#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_FSR                   (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define ENUM_SPORT_CTL_FS_NOT_REQ            (_ADI_MSK(0x00000000,uint32_t))  /* FSR: No frame sync required */
-#define ENUM_SPORT_CTL_FS_REQ                (_ADI_MSK(0x00002000,uint32_t))  /* FSR: Frame sync required */
-
-#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_CKRE                  (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define ENUM_SPORT_CTL_CLK_FALL_EDGE         (_ADI_MSK(0x00000000,uint32_t))  /* CKRE: Clock falling edge */
-#define ENUM_SPORT_CTL_CLK_RISE_EDGE         (_ADI_MSK(0x00001000,uint32_t))  /* CKRE: Clock rising edge */
-
-#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_OPMODE                (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define ENUM_SPORT_CTL_SERIAL_MC_MODE        (_ADI_MSK(0x00000000,uint32_t))  /* OPMODE: DSP standard/multi-channel mode */
-#define ENUM_SPORT_CTL_I2S_MODE              (_ADI_MSK(0x00000800,uint32_t))  /* OPMODE: I2S/packed/left-justified mode */
-
-#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_ICLK                  (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define ENUM_SPORT_CTL_EXTERNAL_CLK          (_ADI_MSK(0x00000000,uint32_t))  /* ICLK: External clock */
-#define ENUM_SPORT_CTL_INTERNAL_CLK          (_ADI_MSK(0x00000400,uint32_t))  /* ICLK: Internal clock */
-
-#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_PACK                  (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define ENUM_SPORT_CTL_PACK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* PACK: Disable */
-#define ENUM_SPORT_CTL_PACK_EN               (_ADI_MSK(0x00000200,uint32_t))  /* PACK: Enable */
-#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_SLEN                  (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-
-#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_LSBF                  (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define ENUM_SPORT_CTL_MSB_FIRST             (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB first sent/received (big endian) */
-#define ENUM_SPORT_CTL_LSB_FIRST             (_ADI_MSK(0x00000008,uint32_t))  /* LSBF: LSB first sent/received (little endian) */
-
-#define BITM_SPORT_CTL_A_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_DTYPE                 (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define ENUM_SPORT_CTL_RJUSTIFY_ZFILL        (_ADI_MSK(0x00000000,uint32_t))  /* DTYPE: Right-justify data, zero-fill unused MSBs */
-#define ENUM_SPORT_CTL_RJUSTIFY_SFILL        (_ADI_MSK(0x00000002,uint32_t))  /* DTYPE: Right-justify data, sign-extend unused MSBs */
-#define ENUM_SPORT_CTL_USE_U_LAW             (_ADI_MSK(0x00000004,uint32_t))  /* DTYPE: m-law compand data */
-#define ENUM_SPORT_CTL_USE_A_LAW             (_ADI_MSK(0x00000006,uint32_t))  /* DTYPE: A-law compand data */
-
-#define BITM_SPORT_CTL_A_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define BITM_SPORT_CTL_SPENPRI               (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define ENUM_SPORT_CTL_DIS                   (_ADI_MSK(0x00000000,uint32_t))  /* SPENPRI: Disable */
-#define ENUM_SPORT_CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* SPENPRI: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_A_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_FSDIV                 16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_A_CLKDIV               0                               /* Clock Divisor */
-#define BITP_SPORT_DIV_CLKDIV                 0                               /* Clock Divisor */
-#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_FSDIV                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-#define BITM_SPORT_DIV_CLKDIV                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_A_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_WOFFSET              16                               /* Window Offset */
-#define BITP_SPORT_MCTL_A_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_WSIZE                 8                               /* Window Size */
-#define BITP_SPORT_MCTL_A_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_MFD                   4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_A_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_MCPDE                 2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_A_MCE                 0                               /* Multichannel enable */
-#define BITP_SPORT_MCTL_MCE                   0                               /* Multichannel enable */
-#define BITM_SPORT_MCTL_A_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_WOFFSET              (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_A_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_WSIZE                (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_A_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_MFD                  (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-
-#define BITM_SPORT_MCTL_A_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_MCPDE                (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define ENUM_SPORT_MCTL_MCPD_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* MCPDE: Disable */
-#define ENUM_SPORT_MCTL_MCPD_EN              (_ADI_MSK(0x00000004,uint32_t))  /* MCPDE: Enable */
-
-#define BITM_SPORT_MCTL_A_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define BITM_SPORT_MCTL_MCE                  (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define ENUM_SPORT_MCTL_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* MCE: Disable */
-#define ENUM_SPORT_MCTL_EN                   (_ADI_MSK(0x00000001,uint32_t))  /* MCE: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_A_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_FSERRSTAT              6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_A_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_DERRSSTAT              5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_A_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_DERRPSTAT              4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_A_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_FSERRMSK               2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRSMSK               1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRPMSK               0                               /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_FSERRSTAT             (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_A_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_DERRSSTAT             (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_A_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_DERRPSTAT             (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_A_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_FSERRMSK              (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRSMSK              (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRPMSK              (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_A_CURCHAN            0                               /* Current Channel */
-#define BITP_SPORT_MSTAT_CURCHAN              0                               /* Current Channel */
-#define BITM_SPORT_MSTAT_A_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-#define BITM_SPORT_MSTAT_CURCHAN             (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_A_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_CKMUXSEL              1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_A_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-#define BITP_SPORT_CTL2_FSMUXSEL              0                               /* Frame Sync Multiplexer Select */
-
-#define BITM_SPORT_CTL2_A_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_CKMUXSEL             (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define ENUM_SPORT_CTL2_CLK_MUX_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* CKMUXSEL: Disable serial clock multiplexing */
-#define ENUM_SPORT_CTL2_CLK_MUX_EN           (_ADI_MSK(0x00000002,uint32_t))  /* CKMUXSEL: Enable serial clock multiplexing */
-
-#define BITM_SPORT_CTL2_A_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define BITM_SPORT_CTL2_FSMUXSEL             (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define ENUM_SPORT_CTL2_FS_MUX_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* FSMUXSEL: Disable frame sync multiplexing */
-#define ENUM_SPORT_CTL2_FS_MUX_EN            (_ADI_MSK(0x00000001,uint32_t))  /* FSMUXSEL: Enable frame sync multiplexing */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_B_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_B_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_B_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_B_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_B_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_B_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_B_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_B_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_B_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_B_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_B_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_B_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_B_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_B_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_B_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_B_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_B_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_B_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_B_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_B_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_B_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_B_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_B_SPENPRI              0                               /* Serial Port Enable (Primary) */
-
-/* The fields and enumerations for SPORT_CTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL_A */
-
-#define BITM_SPORT_CTL_B_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_B_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_B_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_B_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_B_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_B_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_B_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_B_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_B_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_B_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_B_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_B_CLKDIV               0                               /* Clock Divisor */
-
-/* The fields and enumerations for SPORT_DIV_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_DIV_A */
-
-#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_B_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_B_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_B_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_B_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_B_MCE                 0                               /* Multi-Channel Enable */
-
-/* The fields and enumerations for SPORT_MCTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MCTL_A */
-
-#define BITM_SPORT_MCTL_B_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_B_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_B_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_B_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_B_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multi-Channel Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_B_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_B_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_B_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_B_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-
-/* The fields and enumerations for SPORT_ERR_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_ERR_A */
-
-#define BITM_SPORT_ERR_B_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_B_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_B_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_B_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_B_CURCHAN            0                               /* Current Channel */
-
-/* The fields and enumerations for SPORT_MSTAT_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MSTAT_A */
-
-#define BITM_SPORT_MSTAT_B_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_B_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_B_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-
-/* The fields and enumerations for SPORT_CTL2_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL2_A */
-
-#define BITM_SPORT_CTL2_B_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_B_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-
-/* ==================================================
-        Serial Peripheral Interface Registers
-   ================================================== */
-
-/* =========================
-        SPI0
-   ========================= */
-#define REG_SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
-#define REG_SPI0_RXCTL                  0xFFC40408         /* SPI0 Receive Control Register */
-#define REG_SPI0_TXCTL                  0xFFC4040C         /* SPI0 Transmit Control Register */
-#define REG_SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
-#define REG_SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
-#define REG_SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
-#define REG_SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word Count Register */
-#define REG_SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word Count Reload Register */
-#define REG_SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word Count Register */
-#define REG_SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word Count Reload Register */
-#define REG_SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
-#define REG_SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
-#define REG_SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
-#define REG_SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
-#define REG_SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
-#define REG_SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
-#define REG_SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
-#define REG_SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
-        SPI1
-   ========================= */
-#define REG_SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
-#define REG_SPI1_RXCTL                  0xFFC40508         /* SPI1 Receive Control Register */
-#define REG_SPI1_TXCTL                  0xFFC4050C         /* SPI1 Transmit Control Register */
-#define REG_SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
-#define REG_SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
-#define REG_SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
-#define REG_SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word Count Register */
-#define REG_SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word Count Reload Register */
-#define REG_SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word Count Register */
-#define REG_SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word Count Reload Register */
-#define REG_SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
-#define REG_SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
-#define REG_SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
-#define REG_SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
-#define REG_SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
-#define REG_SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
-#define REG_SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
-#define REG_SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
-        SPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CTL_SOSI                    22                               /* Start on MOSI */
-#define BITP_SPI_CTL_MIOM                    20                               /* Multiple I/O Mode */
-#define BITP_SPI_CTL_FMODE                   18                               /* Fast-Mode Enable */
-#define BITP_SPI_CTL_FCWM                    16                               /* Flow Control Watermark */
-#define BITP_SPI_CTL_FCPL                    15                               /* Flow Control Polarity */
-#define BITP_SPI_CTL_FCCH                    14                               /* Flow Control Channel Selection */
-#define BITP_SPI_CTL_FCEN                    13                               /* Flow Control Enable */
-#define BITP_SPI_CTL_LSBF                    12                               /* Least Significant Bit First */
-#define BITP_SPI_CTL_SIZE                     9                               /* Word Transfer Size */
-#define BITP_SPI_CTL_EMISO                    8                               /* Enable MISO */
-#define BITP_SPI_CTL_SELST                    7                               /* Slave Select Polarity Between Transfers */
-#define BITP_SPI_CTL_ASSEL                    6                               /* Slave Select Pin Control */
-#define BITP_SPI_CTL_CPOL                     5                               /* Clock Polarity */
-#define BITP_SPI_CTL_CPHA                     4                               /* Clock Phase */
-#define BITP_SPI_CTL_ODM                      3                               /* Open Drain Mode */
-#define BITP_SPI_CTL_PSSE                     2                               /* Protected Slave Select Enable */
-#define BITP_SPI_CTL_MSTR                     1                               /* Master / Slave */
-#define BITP_SPI_CTL_EN                       0                               /* Enable */
-
-#define BITM_SPI_CTL_SOSI                    (_ADI_MSK(0x00400000,uint32_t))  /* Start on MOSI */
-#define ENUM_SPI_CTL_STMISO                  (_ADI_MSK(0x00000000,uint32_t))  /* SOSI: Bit 1 on MISO (DIOM) or on D3 (QIOM) */
-#define ENUM_SPI_CTL_STMOSI                  (_ADI_MSK(0x00400000,uint32_t))  /* SOSI: Bit 1 on MOSI (DIOM and QIOM) */
-
-#define BITM_SPI_CTL_MIOM                    (_ADI_MSK(0x00300000,uint32_t))  /* Multiple I/O Mode */
-#define ENUM_SPI_CTL_MIO_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* MIOM: No MIOM (disabled) */
-#define ENUM_SPI_CTL_MIO_DUAL                (_ADI_MSK(0x00100000,uint32_t))  /* MIOM: DIOM operation */
-#define ENUM_SPI_CTL_MIO_QUAD                (_ADI_MSK(0x00200000,uint32_t))  /* MIOM: QIOM operation */
-
-#define BITM_SPI_CTL_FMODE                   (_ADI_MSK(0x00040000,uint32_t))  /* Fast-Mode Enable */
-#define ENUM_SPI_CTL_FAST_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FMODE: Disable */
-#define ENUM_SPI_CTL_FAST_EN                 (_ADI_MSK(0x00040000,uint32_t))  /* FMODE: Enable */
-
-#define BITM_SPI_CTL_FCWM                    (_ADI_MSK(0x00030000,uint32_t))  /* Flow Control Watermark */
-#define ENUM_SPI_CTL_FIFO0                   (_ADI_MSK(0x00000000,uint32_t))  /* FCWM: TFIFO empty or RFIFO full */
-#define ENUM_SPI_CTL_FIFO1                   (_ADI_MSK(0x00010000,uint32_t))  /* FCWM: TFIFO 75% or more empty, or RFIFO full */
-#define ENUM_SPI_CTL_FIFO2                   (_ADI_MSK(0x00020000,uint32_t))  /* FCWM: TFIFO 50% or more empty, or RFIFO full */
-
-#define BITM_SPI_CTL_FCPL                    (_ADI_MSK(0x00008000,uint32_t))  /* Flow Control Polarity */
-#define ENUM_SPI_CTL_FLOW_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* FCPL: Active-low RDY */
-#define ENUM_SPI_CTL_FLOW_HI                 (_ADI_MSK(0x00008000,uint32_t))  /* FCPL: Active-high RDY */
-
-#define BITM_SPI_CTL_FCCH                    (_ADI_MSK(0x00004000,uint32_t))  /* Flow Control Channel Selection */
-#define ENUM_SPI_CTL_FLOW_RX                 (_ADI_MSK(0x00000000,uint32_t))  /* FCCH: Flow control on RX buffer */
-#define ENUM_SPI_CTL_FLOW_TX                 (_ADI_MSK(0x00004000,uint32_t))  /* FCCH: Flow control on TX buffer */
-
-#define BITM_SPI_CTL_FCEN                    (_ADI_MSK(0x00002000,uint32_t))  /* Flow Control Enable */
-#define ENUM_SPI_CTL_FLOW_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FCEN: Disable */
-#define ENUM_SPI_CTL_FLOW_EN                 (_ADI_MSK(0x00002000,uint32_t))  /* FCEN: Enable */
-
-#define BITM_SPI_CTL_LSBF                    (_ADI_MSK(0x00001000,uint32_t))  /* Least Significant Bit First */
-#define ENUM_SPI_CTL_MSB_FIRST               (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB sent/received first (big endian) */
-#define ENUM_SPI_CTL_LSB_FIRST               (_ADI_MSK(0x00001000,uint32_t))  /* LSBF: LSB sent/received first (little endian) */
-
-#define BITM_SPI_CTL_SIZE                    (_ADI_MSK(0x00000600,uint32_t))  /* Word Transfer Size */
-#define ENUM_SPI_CTL_SIZE08                  (_ADI_MSK(0x00000000,uint32_t))  /* SIZE: 8-bit word */
-#define ENUM_SPI_CTL_SIZE16                  (_ADI_MSK(0x00000200,uint32_t))  /* SIZE: 16-bit word */
-#define ENUM_SPI_CTL_SIZE32                  (_ADI_MSK(0x00000400,uint32_t))  /* SIZE: 32-bit word */
-
-#define BITM_SPI_CTL_EMISO                   (_ADI_MSK(0x00000100,uint32_t))  /* Enable MISO */
-#define ENUM_SPI_CTL_MISO_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EMISO: Disable */
-#define ENUM_SPI_CTL_MISO_EN                 (_ADI_MSK(0x00000100,uint32_t))  /* EMISO: Enable */
-
-#define BITM_SPI_CTL_SELST                   (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select Polarity Between Transfers */
-#define ENUM_SPI_CTL_DEASSRT_SSEL            (_ADI_MSK(0x00000000,uint32_t))  /* SELST: De-assert slave select (high) */
-#define ENUM_SPI_CTL_ASSRT_SSEL              (_ADI_MSK(0x00000080,uint32_t))  /* SELST: Assert slave select (low) */
-
-#define BITM_SPI_CTL_ASSEL                   (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select Pin Control */
-#define ENUM_SPI_CTL_SW_SSEL                 (_ADI_MSK(0x00000000,uint32_t))  /* ASSEL: Software Slave Select Control */
-#define ENUM_SPI_CTL_HW_SSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* ASSEL: Hardware Slave Select Control */
-
-#define BITM_SPI_CTL_CPOL                    (_ADI_MSK(0x00000020,uint32_t))  /* Clock Polarity */
-#define ENUM_SPI_CTL_SCKHI                   (_ADI_MSK(0x00000000,uint32_t))  /* CPOL: Active-high SPI CLK */
-#define ENUM_SPI_CTL_SCKLO                   (_ADI_MSK(0x00000020,uint32_t))  /* CPOL: Active-low SPI CLK */
-
-#define BITM_SPI_CTL_CPHA                    (_ADI_MSK(0x00000010,uint32_t))  /* Clock Phase */
-#define ENUM_SPI_CTL_SCKMID                  (_ADI_MSK(0x00000000,uint32_t))  /* CPHA: SPI CLK toggles from middle */
-#define ENUM_SPI_CTL_SCKBEG                  (_ADI_MSK(0x00000010,uint32_t))  /* CPHA: SPI CLK toggles from start */
-
-#define BITM_SPI_CTL_ODM                     (_ADI_MSK(0x00000008,uint32_t))  /* Open Drain Mode */
-#define ENUM_SPI_CTL_ODM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* ODM: Disable */
-#define ENUM_SPI_CTL_ODM_EN                  (_ADI_MSK(0x00000008,uint32_t))  /* ODM: Enable */
-
-#define BITM_SPI_CTL_PSSE                    (_ADI_MSK(0x00000004,uint32_t))  /* Protected Slave Select Enable */
-#define ENUM_SPI_CTL_PSSE_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* PSSE: Disable */
-#define ENUM_SPI_CTL_PSSE_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* PSSE: Enable */
-
-#define BITM_SPI_CTL_MSTR                    (_ADI_MSK(0x00000002,uint32_t))  /* Master / Slave */
-#define ENUM_SPI_CTL_SLAVE                   (_ADI_MSK(0x00000000,uint32_t))  /* MSTR: Slave */
-#define ENUM_SPI_CTL_MASTER                  (_ADI_MSK(0x00000002,uint32_t))  /* MSTR: Master */
-
-#define BITM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SPI_CTL_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable SPI module */
-#define ENUM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RXCTL_RUWM                  16                               /* Receive FIFO Urgent Watermark */
-#define BITP_SPI_RXCTL_RRWM                  12                               /* Receive FIFO Regular Watermark */
-#define BITP_SPI_RXCTL_RDO                    8                               /* Receive Data Overrun */
-#define BITP_SPI_RXCTL_RDR                    4                               /* Receive Data Request */
-#define BITP_SPI_RXCTL_RWCEN                  3                               /* Receive Word Counter Enable */
-#define BITP_SPI_RXCTL_RTI                    2                               /* Receive Transfer Initiate */
-#define BITP_SPI_RXCTL_REN                    0                               /* Receive Enable */
-
-#define BITM_SPI_RXCTL_RUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* Receive FIFO Urgent Watermark */
-#define ENUM_SPI_RXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disabled */
-#define ENUM_SPI_RXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* RUWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* RUWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* RUWM: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_FULL              (_ADI_MSK(0x00040000,uint32_t))  /* RUWM: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* Receive FIFO Regular Watermark */
-#define ENUM_SPI_RXCTL_RWM_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RRWM: Empty RFIFO */
-#define ENUM_SPI_RXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* RRWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* RRWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* RRWM: 75% full RFIFO */
-
-#define BITM_SPI_RXCTL_RDO                   (_ADI_MSK(0x00000100,uint32_t))  /* Receive Data Overrun */
-#define ENUM_SPI_RXCTL_DISCARD               (_ADI_MSK(0x00000000,uint32_t))  /* RDO: KeDiscard incoming data if SPI_RFIFO is full */
-#define ENUM_SPI_RXCTL_OVERWRITE             (_ADI_MSK(0x00000100,uint32_t))  /* RDO: Overwrite old data if SPI_RFIFO is full */
-
-#define BITM_SPI_RXCTL_RDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Receive Data Request */
-#define ENUM_SPI_RXCTL_RDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RDR: Disabled */
-#define ENUM_SPI_RXCTL_RDR_NE                (_ADI_MSK(0x00000010,uint32_t))  /* RDR: Not empty RFIFO */
-#define ENUM_SPI_RXCTL_RDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* RDR: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* RDR: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* RDR: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_FULL              (_ADI_MSK(0x00000050,uint32_t))  /* RDR: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Receive Word Counter Enable */
-#define ENUM_SPI_RXCTL_RWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RWCEN: Disable */
-#define ENUM_SPI_RXCTL_RWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* RWCEN: Enable */
-
-#define BITM_SPI_RXCTL_RTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Receive Transfer Initiate */
-#define ENUM_SPI_RXCTL_RTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RTI: Disable */
-#define ENUM_SPI_RXCTL_RTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* RTI: Enable */
-
-#define BITM_SPI_RXCTL_REN                   (_ADI_MSK(0x00000001,uint32_t))  /* Receive Enable */
-#define ENUM_SPI_RXCTL_RX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* REN: Disable */
-#define ENUM_SPI_RXCTL_RX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* REN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TXCTL_TUWM                  16                               /* FIFO Urgent Watermark */
-#define BITP_SPI_TXCTL_TRWM                  12                               /* FIFO Regular Watermark */
-#define BITP_SPI_TXCTL_TDU                    8                               /* Transmit Data Under-run */
-#define BITP_SPI_TXCTL_TDR                    4                               /* Transmit Data Request */
-#define BITP_SPI_TXCTL_TWCEN                  3                               /* Transmit Word Counter Enable */
-#define BITP_SPI_TXCTL_TTI                    2                               /* Transmit Transfer Initiate */
-#define BITP_SPI_TXCTL_TEN                    0                               /* Transmit Enable */
-
-#define BITM_SPI_TXCTL_TUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Urgent Watermark */
-#define ENUM_SPI_TXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disabled */
-#define ENUM_SPI_TXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* TUWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* TUWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* TUWM: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_EMPTY             (_ADI_MSK(0x00040000,uint32_t))  /* TUWM: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* FIFO Regular Watermark */
-#define ENUM_SPI_TXCTL_RWM_FULL              (_ADI_MSK(0x00000000,uint32_t))  /* TRWM: Full TFIFO */
-#define ENUM_SPI_TXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* TRWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* TRWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* TRWM: 75% empty TFIFO */
-
-#define BITM_SPI_TXCTL_TDU                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Data Under-run */
-#define ENUM_SPI_TXCTL_LASTWD                (_ADI_MSK(0x00000000,uint32_t))  /* TDU: Send last word when SPI_TFIFO is empty */
-#define ENUM_SPI_TXCTL_ZERO                  (_ADI_MSK(0x00000100,uint32_t))  /* TDU: Send zeros when SPI_TFIFO is empty */
-
-#define BITM_SPI_TXCTL_TDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Transmit Data Request */
-#define ENUM_SPI_TXCTL_TDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TDR: Disabled */
-#define ENUM_SPI_TXCTL_TDR_NF                (_ADI_MSK(0x00000010,uint32_t))  /* TDR: Not full TFIFO */
-#define ENUM_SPI_TXCTL_TDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* TDR: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* TDR: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* TDR: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_EMPTY             (_ADI_MSK(0x00000050,uint32_t))  /* TDR: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Word Counter Enable */
-#define ENUM_SPI_TXCTL_TWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TWCEN: Disable */
-#define ENUM_SPI_TXCTL_TWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* TWCEN: Enable */
-
-#define BITM_SPI_TXCTL_TTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Transfer Initiate */
-#define ENUM_SPI_TXCTL_TTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TTI: Disable */
-#define ENUM_SPI_TXCTL_TTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* TTI: Enable */
-
-#define BITM_SPI_TXCTL_TEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Enable */
-#define ENUM_SPI_TXCTL_TX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* TEN: Disable */
-#define ENUM_SPI_TXCTL_TX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* TEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CLK_BAUD                     0                               /* Baud Rate */
-#define BITM_SPI_CLK_BAUD                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Baud Rate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_DLY                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_DLY_LAGX                     9                               /* Extended SPI Clock Lag Control */
-#define BITP_SPI_DLY_LEADX                    8                               /* Extended SPI Clock Lead Control */
-#define BITP_SPI_DLY_STOP                     0                               /* Transfer delay time in multiples of SPI clock period */
-#define BITM_SPI_DLY_LAGX                    (_ADI_MSK(0x00000200,uint32_t))  /* Extended SPI Clock Lag Control */
-#define BITM_SPI_DLY_LEADX                   (_ADI_MSK(0x00000100,uint32_t))  /* Extended SPI Clock Lead Control */
-#define BITM_SPI_DLY_STOP                    (_ADI_MSK(0x000000FF,uint32_t))  /* Transfer delay time in multiples of SPI clock period */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_SLVSEL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_SLVSEL_SSEL7                15                               /* Slave Select 7 Input */
-#define BITP_SPI_SLVSEL_SSEL6                14                               /* Slave Select 6 Input */
-#define BITP_SPI_SLVSEL_SSEL5                13                               /* Slave Select 5 Input */
-#define BITP_SPI_SLVSEL_SSEL4                12                               /* Slave Select 4 Input */
-#define BITP_SPI_SLVSEL_SSEL3                11                               /* Slave Select 3 Input */
-#define BITP_SPI_SLVSEL_SSEL2                10                               /* Slave Select 2 Input */
-#define BITP_SPI_SLVSEL_SSEL1                 9                               /* Slave Select 1 Input */
-#define BITP_SPI_SLVSEL_SSE7                  7                               /* Slave Select 7 Enable */
-#define BITP_SPI_SLVSEL_SSE6                  6                               /* Slave Select 6 Enable */
-#define BITP_SPI_SLVSEL_SSE5                  5                               /* Slave Select 5 Enable */
-#define BITP_SPI_SLVSEL_SSE4                  4                               /* Slave Select 4 Enable */
-#define BITP_SPI_SLVSEL_SSE3                  3                               /* Slave Select 3 Enable */
-#define BITP_SPI_SLVSEL_SSE2                  2                               /* Slave Select 2 Enable */
-#define BITP_SPI_SLVSEL_SSE1                  1                               /* Slave Select 1 Enable */
-
-#define BITM_SPI_SLVSEL_SSEL7                (_ADI_MSK(0x00008000,uint32_t))  /* Slave Select 7 Input */
-#define ENUM_SPI_SLVSEL_SSEL7_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL7: Low */
-#define ENUM_SPI_SLVSEL_SSEL7_HI             (_ADI_MSK(0x00008000,uint32_t))  /* SSEL7: High */
-
-#define BITM_SPI_SLVSEL_SSEL6                (_ADI_MSK(0x00004000,uint32_t))  /* Slave Select 6 Input */
-#define ENUM_SPI_SLVSEL_SSEL6_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL6: Low */
-#define ENUM_SPI_SLVSEL_SSEL6_HI             (_ADI_MSK(0x00004000,uint32_t))  /* SSEL6: High */
-
-#define BITM_SPI_SLVSEL_SSEL5                (_ADI_MSK(0x00002000,uint32_t))  /* Slave Select 5 Input */
-#define ENUM_SPI_SLVSEL_SSEL5_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL5: Low */
-#define ENUM_SPI_SLVSEL_SSEL5_HI             (_ADI_MSK(0x00002000,uint32_t))  /* SSEL5: High */
-
-#define BITM_SPI_SLVSEL_SSEL4                (_ADI_MSK(0x00001000,uint32_t))  /* Slave Select 4 Input */
-#define ENUM_SPI_SLVSEL_SSEL4_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL4: Low */
-#define ENUM_SPI_SLVSEL_SSEL4_HI             (_ADI_MSK(0x00001000,uint32_t))  /* SSEL4: High */
-
-#define BITM_SPI_SLVSEL_SSEL3                (_ADI_MSK(0x00000800,uint32_t))  /* Slave Select 3 Input */
-#define ENUM_SPI_SLVSEL_SSEL3_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL3: Low */
-#define ENUM_SPI_SLVSEL_SSEL3_HI             (_ADI_MSK(0x00000800,uint32_t))  /* SSEL3: High */
-
-#define BITM_SPI_SLVSEL_SSEL2                (_ADI_MSK(0x00000400,uint32_t))  /* Slave Select 2 Input */
-#define ENUM_SPI_SLVSEL_SSEL2_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL2: Low */
-#define ENUM_SPI_SLVSEL_SSEL2_HI             (_ADI_MSK(0x00000400,uint32_t))  /* SSEL2: High */
-
-#define BITM_SPI_SLVSEL_SSEL1                (_ADI_MSK(0x00000200,uint32_t))  /* Slave Select 1 Input */
-#define ENUM_SPI_SLVSEL_SSEL1_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL1: Low */
-#define ENUM_SPI_SLVSEL_SSEL1_HI             (_ADI_MSK(0x00000200,uint32_t))  /* SSEL1: High */
-
-#define BITM_SPI_SLVSEL_SSE7                 (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select 7 Enable */
-#define ENUM_SPI_SLVSEL_SSEL7_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE7: Disable */
-#define ENUM_SPI_SLVSEL_SSEL7_EN             (_ADI_MSK(0x00000080,uint32_t))  /* SSE7: Enable */
-
-#define BITM_SPI_SLVSEL_SSE6                 (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select 6 Enable */
-#define ENUM_SPI_SLVSEL_SSEL6_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE6: Disable */
-#define ENUM_SPI_SLVSEL_SSEL6_EN             (_ADI_MSK(0x00000040,uint32_t))  /* SSE6: Enable */
-
-#define BITM_SPI_SLVSEL_SSE5                 (_ADI_MSK(0x00000020,uint32_t))  /* Slave Select 5 Enable */
-#define ENUM_SPI_SLVSEL_SSEL5_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE5: Disable */
-#define ENUM_SPI_SLVSEL_SSEL5_EN             (_ADI_MSK(0x00000020,uint32_t))  /* SSE5: Enable */
-
-#define BITM_SPI_SLVSEL_SSE4                 (_ADI_MSK(0x00000010,uint32_t))  /* Slave Select 4 Enable */
-#define ENUM_SPI_SLVSEL_SSEL4_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE4: Disable */
-#define ENUM_SPI_SLVSEL_SSEL4_EN             (_ADI_MSK(0x00000010,uint32_t))  /* SSE4: Enable */
-
-#define BITM_SPI_SLVSEL_SSE3                 (_ADI_MSK(0x00000008,uint32_t))  /* Slave Select 3 Enable */
-#define ENUM_SPI_SLVSEL_SSEL3_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE3: Disable */
-#define ENUM_SPI_SLVSEL_SSEL3_EN             (_ADI_MSK(0x00000008,uint32_t))  /* SSE3: Enable */
-
-#define BITM_SPI_SLVSEL_SSE2                 (_ADI_MSK(0x00000004,uint32_t))  /* Slave Select 2 Enable */
-#define ENUM_SPI_SLVSEL_SSEL2_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE2: Disable */
-#define ENUM_SPI_SLVSEL_SSEL2_EN             (_ADI_MSK(0x00000004,uint32_t))  /* SSE2: Enable */
-
-#define BITM_SPI_SLVSEL_SSE1                 (_ADI_MSK(0x00000002,uint32_t))  /* Slave Select 1 Enable */
-#define ENUM_SPI_SLVSEL_SSEL1_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE1: Disable */
-#define ENUM_SPI_SLVSEL_SSEL1_EN             (_ADI_MSK(0x00000002,uint32_t))  /* SSE1: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWC_VALUE                    0                               /* Received Word Count */
-#define BITM_SPI_RWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWCR_VALUE                   0                               /* Received Word Count Reload */
-#define BITM_SPI_RWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWC_VALUE                    0                               /* Transmitted Word Count */
-#define BITM_SPI_TWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWCR_VALUE                   0                               /* Transmitted Word Count Reload */
-#define BITM_SPI_TWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_TF                     11                               /* Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_RF                     10                               /* Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_TS                      9                               /* Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_RS                      8                               /* Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_MF                      7                               /* Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_TC                      6                               /* Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_TUR                     5                               /* Transmit Underrun Interrupt Mask */
-#define BITP_SPI_IMSK_ROR                     4                               /* Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_RUWM                    1                               /* Receive Urgent Watermark Interrupt Mask */
-
-#define BITM_SPI_IMSK_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Mask */
-#define ENUM_SPI_TF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TF: Disable (mask) interrupt */
-#define ENUM_SPI_TF_HI                       (_ADI_MSK(0x00000800,uint32_t))  /* TF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Mask */
-#define ENUM_SPI_RF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RF: Disable (mask) interrupt */
-#define ENUM_SPI_RF_HI                       (_ADI_MSK(0x00000400,uint32_t))  /* RF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Mask */
-#define ENUM_SPI_TS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TS: Disable (mask) interrupt */
-#define ENUM_SPI_TS_HI                       (_ADI_MSK(0x00000200,uint32_t))  /* TS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Mask */
-#define ENUM_SPI_RS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RS: Disable (mask) interrupt */
-#define ENUM_SPI_RS_HI                       (_ADI_MSK(0x00000100,uint32_t))  /* RS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Mask */
-#define ENUM_SPI_MF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* MF: Disable (mask) interrupt */
-#define ENUM_SPI_MF_HI                       (_ADI_MSK(0x00000080,uint32_t))  /* MF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Mask */
-#define ENUM_SPI_TC_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TC: Disable (mask) interrupt */
-#define ENUM_SPI_TC_HI                       (_ADI_MSK(0x00000040,uint32_t))  /* TC: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Interrupt Mask */
-#define ENUM_SPI_TUR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* TUR: Disable (mask) interrupt */
-#define ENUM_SPI_TUR_HI                      (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Mask */
-#define ENUM_SPI_ROR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* ROR: Disable (mask) interrupt */
-#define ENUM_SPI_ROR_HI                      (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_TUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disable (mask) interrupt */
-#define ENUM_SPI_TUWM_HI                     (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_RUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disable (mask) interrupt */
-#define ENUM_SPI_RUWM_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RF                 10                               /* Clear Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TS                  9                               /* Clear Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RS                  8                               /* Clear Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_MF                  7                               /* Clear Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_SET_TF                 11                               /* Set Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RF                 10                               /* Set Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TS                  9                               /* Set Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RS                  8                               /* Set Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_MF                  7                               /* Set Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TC                  6                               /* Set Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUR                 5                               /* Set Transmit Under-run  Interrupt Mask */
-#define BITP_SPI_IMSK_SET_ROR                 4                               /* Set Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUWM                2                               /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RUWM                1                               /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_SET are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_SET_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Set Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Set Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Set Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Set Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Set Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Set Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Set Transmit Under-run  Interrupt Mask */
-#define BITM_SPI_IMSK_SET_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Set Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_STAT_TFF                    23                               /* SPI_TFIFO Full */
-#define BITP_SPI_STAT_RFE                    22                               /* SPI_RFIFO Empty */
-#define BITP_SPI_STAT_FCS                    20                               /* Flow Control Stall Indication */
-#define BITP_SPI_STAT_TFS                    16                               /* SPI_TFIFO Status */
-#define BITP_SPI_STAT_RFS                    12                               /* SPI_RFIFO Status */
-#define BITP_SPI_STAT_TF                     11                               /* Transmit Finish Indication */
-#define BITP_SPI_STAT_RF                     10                               /* Receive Finish Indication */
-#define BITP_SPI_STAT_TS                      9                               /* Transmit Start */
-#define BITP_SPI_STAT_RS                      8                               /* Receive Start */
-#define BITP_SPI_STAT_MF                      7                               /* Mode Fault Indication */
-#define BITP_SPI_STAT_TC                      6                               /* Transmit Collision Indication */
-#define BITP_SPI_STAT_TUR                     5                               /* Transmit Underrun Indication */
-#define BITP_SPI_STAT_ROR                     4                               /* Receive Overrun Indication */
-#define BITP_SPI_STAT_TUWM                    2                               /* Transmit Urgent Watermark Breached */
-#define BITP_SPI_STAT_RUWM                    1                               /* Receive Urgent Watermark Breached */
-#define BITP_SPI_STAT_SPIF                    0                               /* SPI Finished */
-
-#define BITM_SPI_STAT_TFF                    (_ADI_MSK(0x00800000,uint32_t))  /* SPI_TFIFO Full */
-#define ENUM_SPI_STAT_TFIFO_NF               (_ADI_MSK(0x00000000,uint32_t))  /* TFF: Not full Tx FIFO */
-#define ENUM_SPI_STAT_TFIFO_F                (_ADI_MSK(0x00800000,uint32_t))  /* TFF: Full Tx FIFO */
-
-#define BITM_SPI_STAT_RFE                    (_ADI_MSK(0x00400000,uint32_t))  /* SPI_RFIFO Empty */
-#define ENUM_SPI_STAT_RFIFO_E                (_ADI_MSK(0x00000000,uint32_t))  /* RFE: Empty Rx FIFO */
-#define ENUM_SPI_STAT_RFIFO_NE               (_ADI_MSK(0x00400000,uint32_t))  /* RFE: Not empty Rx FIFO */
-
-#define BITM_SPI_STAT_FCS                    (_ADI_MSK(0x00100000,uint32_t))  /* Flow Control Stall Indication */
-#define ENUM_SPI_STAT_STALL                  (_ADI_MSK(0x00000000,uint32_t))  /* FCS: Stall (RDY pin asserted) */
-#define ENUM_SPI_STAT_NOSTALL                (_ADI_MSK(0x00100000,uint32_t))  /* FCS: No stall (RDY pin de-asserted) */
-
-#define BITM_SPI_STAT_TFS                    (_ADI_MSK(0x00070000,uint32_t))  /* SPI_TFIFO Status */
-#define ENUM_SPI_STAT_TFIFO_FULL             (_ADI_MSK(0x00000000,uint32_t))  /* TFS: Full TFIFO */
-#define ENUM_SPI_STAT_TFIFO_25               (_ADI_MSK(0x00010000,uint32_t))  /* TFS: 25% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_50               (_ADI_MSK(0x00020000,uint32_t))  /* TFS: 50% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_75               (_ADI_MSK(0x00030000,uint32_t))  /* TFS: 75% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_EMPTY            (_ADI_MSK(0x00040000,uint32_t))  /* TFS: Empty TFIFO */
-
-#define BITM_SPI_STAT_RFS                    (_ADI_MSK(0x00007000,uint32_t))  /* SPI_RFIFO Status */
-#define ENUM_SPI_STAT_RFIFO_EMPTY            (_ADI_MSK(0x00000000,uint32_t))  /* RFS: Empty RFIFO */
-#define ENUM_SPI_STAT_RFIFO_25               (_ADI_MSK(0x00001000,uint32_t))  /* RFS: 25% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_50               (_ADI_MSK(0x00002000,uint32_t))  /* RFS: 50% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_75               (_ADI_MSK(0x00003000,uint32_t))  /* RFS: 75% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_FULL             (_ADI_MSK(0x00004000,uint32_t))  /* RFS: Full RFIFO */
-
-#define BITM_SPI_STAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Indication */
-#define ENUM_SPI_STAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No status */
-#define ENUM_SPI_STAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Transmit finish detected */
-
-#define BITM_SPI_STAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Indication */
-#define ENUM_SPI_STAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No status */
-#define ENUM_SPI_STAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Receive finish detected */
-
-#define BITM_SPI_STAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start */
-#define ENUM_SPI_STAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No status */
-#define ENUM_SPI_STAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Transmit start detected */
-
-#define BITM_SPI_STAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start */
-#define ENUM_SPI_STAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No status */
-#define ENUM_SPI_STAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Receive start detected */
-
-#define BITM_SPI_STAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Indication */
-#define ENUM_SPI_STAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No status */
-#define ENUM_SPI_STAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Mode fault occurred */
-
-#define BITM_SPI_STAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Indication */
-#define ENUM_SPI_STAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No status */
-#define ENUM_SPI_STAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Transmit collision occurred */
-
-#define BITM_SPI_STAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Indication */
-#define ENUM_SPI_STAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No status */
-#define ENUM_SPI_STAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Transmit underrun occurred */
-
-#define BITM_SPI_STAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Indication */
-#define ENUM_SPI_STAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No status */
-#define ENUM_SPI_STAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Receive overrun occurred */
-
-#define BITM_SPI_STAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Breached */
-#define ENUM_SPI_STAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: TX Regular Watermark reached */
-#define ENUM_SPI_STAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: TX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Breached */
-#define ENUM_SPI_STAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: RX Regular Watermark reached */
-#define ENUM_SPI_STAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: RX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_SPIF                   (_ADI_MSK(0x00000001,uint32_t))  /* SPI Finished */
-#define ENUM_SPI_STAT_SPIF_LO                (_ADI_MSK(0x00000000,uint32_t))  /* SPIF: No status */
-#define ENUM_SPI_STAT_SPIF_HI                (_ADI_MSK(0x00000001,uint32_t))  /* SPIF: Completed single-word transfer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_TF                     11                               /* Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_RF                     10                               /* Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_TS                      9                               /* Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_RS                      8                               /* Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_MF                      7                               /* Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_TC                      6                               /* Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_TUR                     5                               /* Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_ROR                     4                               /* Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_RUWM                    1                               /* Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-
-#define BITM_SPI_ILAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No interrupt */
-#define ENUM_SPI_ILAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Latched interrupt */
-
-#define BITM_SPI_ILAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No interrupt */
-#define ENUM_SPI_ILAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Latch */
-#define ENUM_SPI_ILAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No interrupt */
-#define ENUM_SPI_ILAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Latched interrupt */
-
-#define BITM_SPI_ILAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Latch */
-#define ENUM_SPI_ILAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No interrupt */
-#define ENUM_SPI_ILAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Latched interrupt */
-
-#define BITM_SPI_ILAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Latch */
-#define ENUM_SPI_ILAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No interrupt */
-#define ENUM_SPI_ILAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Latch */
-#define ENUM_SPI_ILAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No interrupt */
-#define ENUM_SPI_ILAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Under-run Interrupt Latch */
-#define ENUM_SPI_ILAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No interrupt */
-#define ENUM_SPI_ILAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Latched interrupt */
-
-#define BITM_SPI_ILAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Latch */
-#define ENUM_SPI_ILAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No interrupt */
-#define ENUM_SPI_ILAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: No interrupt */
-#define ENUM_SPI_ILAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Latched interrupt */
-
-#define BITM_SPI_ILAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: No interrupt */
-#define ENUM_SPI_ILAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Latched interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RF                 10                               /* Clear Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TS                  9                               /* Clear Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RS                  8                               /* Clear Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_MF                  7                               /* Clear Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_ILAT_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* ==================================================
-        DMA Channel Registers
-   ================================================== */
-
-/* =========================
-        DMA0
-   ========================= */
-#define REG_DMA0_DSCPTR_NXT             0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
-#define REG_DMA0_ADDRSTART              0xFFC41004         /* DMA0 Start Address of Current Buffer */
-#define REG_DMA0_CFG                    0xFFC41008         /* DMA0 Configuration Register */
-#define REG_DMA0_XCNT                   0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
-#define REG_DMA0_XMOD                   0xFFC41010         /* DMA0 Inner Loop Address Increment */
-#define REG_DMA0_YCNT                   0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
-#define REG_DMA0_YMOD                   0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
-#define REG_DMA0_DSCPTR_CUR             0xFFC41024         /* DMA0 Current Descriptor Pointer */
-#define REG_DMA0_DSCPTR_PRV             0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
-#define REG_DMA0_ADDR_CUR               0xFFC4102C         /* DMA0 Current Address */
-#define REG_DMA0_STAT                   0xFFC41030         /* DMA0 Status Register */
-#define REG_DMA0_XCNT_CUR               0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA0_YCNT_CUR               0xFFC41038         /* DMA0 Current Row Count (2D only) */
-#define REG_DMA0_BWLCNT                 0xFFC41040         /* DMA0 Bandwidth Limit Count */
-#define REG_DMA0_BWLCNT_CUR             0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
-#define REG_DMA0_BWMCNT                 0xFFC41048         /* DMA0 Bandwidth Monitor Count */
-#define REG_DMA0_BWMCNT_CUR             0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA1
-   ========================= */
-#define REG_DMA1_DSCPTR_NXT             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
-#define REG_DMA1_ADDRSTART              0xFFC41084         /* DMA1 Start Address of Current Buffer */
-#define REG_DMA1_CFG                    0xFFC41088         /* DMA1 Configuration Register */
-#define REG_DMA1_XCNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
-#define REG_DMA1_XMOD                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
-#define REG_DMA1_YCNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
-#define REG_DMA1_YMOD                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
-#define REG_DMA1_DSCPTR_CUR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
-#define REG_DMA1_DSCPTR_PRV             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
-#define REG_DMA1_ADDR_CUR               0xFFC410AC         /* DMA1 Current Address */
-#define REG_DMA1_STAT                   0xFFC410B0         /* DMA1 Status Register */
-#define REG_DMA1_XCNT_CUR               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA1_YCNT_CUR               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
-#define REG_DMA1_BWLCNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
-#define REG_DMA1_BWLCNT_CUR             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
-#define REG_DMA1_BWMCNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
-#define REG_DMA1_BWMCNT_CUR             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA2
-   ========================= */
-#define REG_DMA2_DSCPTR_NXT             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
-#define REG_DMA2_ADDRSTART              0xFFC41104         /* DMA2 Start Address of Current Buffer */
-#define REG_DMA2_CFG                    0xFFC41108         /* DMA2 Configuration Register */
-#define REG_DMA2_XCNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
-#define REG_DMA2_XMOD                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
-#define REG_DMA2_YCNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
-#define REG_DMA2_YMOD                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
-#define REG_DMA2_DSCPTR_CUR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
-#define REG_DMA2_DSCPTR_PRV             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
-#define REG_DMA2_ADDR_CUR               0xFFC4112C         /* DMA2 Current Address */
-#define REG_DMA2_STAT                   0xFFC41130         /* DMA2 Status Register */
-#define REG_DMA2_XCNT_CUR               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA2_YCNT_CUR               0xFFC41138         /* DMA2 Current Row Count (2D only) */
-#define REG_DMA2_BWLCNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
-#define REG_DMA2_BWLCNT_CUR             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
-#define REG_DMA2_BWMCNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
-#define REG_DMA2_BWMCNT_CUR             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA3
-   ========================= */
-#define REG_DMA3_DSCPTR_NXT             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
-#define REG_DMA3_ADDRSTART              0xFFC41184         /* DMA3 Start Address of Current Buffer */
-#define REG_DMA3_CFG                    0xFFC41188         /* DMA3 Configuration Register */
-#define REG_DMA3_XCNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
-#define REG_DMA3_XMOD                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
-#define REG_DMA3_YCNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
-#define REG_DMA3_YMOD                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
-#define REG_DMA3_DSCPTR_CUR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
-#define REG_DMA3_DSCPTR_PRV             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
-#define REG_DMA3_ADDR_CUR               0xFFC411AC         /* DMA3 Current Address */
-#define REG_DMA3_STAT                   0xFFC411B0         /* DMA3 Status Register */
-#define REG_DMA3_XCNT_CUR               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA3_YCNT_CUR               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
-#define REG_DMA3_BWLCNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
-#define REG_DMA3_BWLCNT_CUR             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
-#define REG_DMA3_BWMCNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
-#define REG_DMA3_BWMCNT_CUR             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA4
-   ========================= */
-#define REG_DMA4_DSCPTR_NXT             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
-#define REG_DMA4_ADDRSTART              0xFFC41204         /* DMA4 Start Address of Current Buffer */
-#define REG_DMA4_CFG                    0xFFC41208         /* DMA4 Configuration Register */
-#define REG_DMA4_XCNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
-#define REG_DMA4_XMOD                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
-#define REG_DMA4_YCNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
-#define REG_DMA4_YMOD                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
-#define REG_DMA4_DSCPTR_CUR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
-#define REG_DMA4_DSCPTR_PRV             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
-#define REG_DMA4_ADDR_CUR               0xFFC4122C         /* DMA4 Current Address */
-#define REG_DMA4_STAT                   0xFFC41230         /* DMA4 Status Register */
-#define REG_DMA4_XCNT_CUR               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA4_YCNT_CUR               0xFFC41238         /* DMA4 Current Row Count (2D only) */
-#define REG_DMA4_BWLCNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
-#define REG_DMA4_BWLCNT_CUR             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
-#define REG_DMA4_BWMCNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
-#define REG_DMA4_BWMCNT_CUR             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA5
-   ========================= */
-#define REG_DMA5_DSCPTR_NXT             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
-#define REG_DMA5_ADDRSTART              0xFFC41284         /* DMA5 Start Address of Current Buffer */
-#define REG_DMA5_CFG                    0xFFC41288         /* DMA5 Configuration Register */
-#define REG_DMA5_XCNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
-#define REG_DMA5_XMOD                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
-#define REG_DMA5_YCNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
-#define REG_DMA5_YMOD                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
-#define REG_DMA5_DSCPTR_CUR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
-#define REG_DMA5_DSCPTR_PRV             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
-#define REG_DMA5_ADDR_CUR               0xFFC412AC         /* DMA5 Current Address */
-#define REG_DMA5_STAT                   0xFFC412B0         /* DMA5 Status Register */
-#define REG_DMA5_XCNT_CUR               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA5_YCNT_CUR               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
-#define REG_DMA5_BWLCNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
-#define REG_DMA5_BWLCNT_CUR             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
-#define REG_DMA5_BWMCNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
-#define REG_DMA5_BWMCNT_CUR             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA6
-   ========================= */
-#define REG_DMA6_DSCPTR_NXT             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
-#define REG_DMA6_ADDRSTART              0xFFC41304         /* DMA6 Start Address of Current Buffer */
-#define REG_DMA6_CFG                    0xFFC41308         /* DMA6 Configuration Register */
-#define REG_DMA6_XCNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
-#define REG_DMA6_XMOD                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
-#define REG_DMA6_YCNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
-#define REG_DMA6_YMOD                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
-#define REG_DMA6_DSCPTR_CUR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
-#define REG_DMA6_DSCPTR_PRV             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
-#define REG_DMA6_ADDR_CUR               0xFFC4132C         /* DMA6 Current Address */
-#define REG_DMA6_STAT                   0xFFC41330         /* DMA6 Status Register */
-#define REG_DMA6_XCNT_CUR               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA6_YCNT_CUR               0xFFC41338         /* DMA6 Current Row Count (2D only) */
-#define REG_DMA6_BWLCNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
-#define REG_DMA6_BWLCNT_CUR             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
-#define REG_DMA6_BWMCNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
-#define REG_DMA6_BWMCNT_CUR             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA7
-   ========================= */
-#define REG_DMA7_DSCPTR_NXT             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
-#define REG_DMA7_ADDRSTART              0xFFC41384         /* DMA7 Start Address of Current Buffer */
-#define REG_DMA7_CFG                    0xFFC41388         /* DMA7 Configuration Register */
-#define REG_DMA7_XCNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
-#define REG_DMA7_XMOD                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
-#define REG_DMA7_YCNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
-#define REG_DMA7_YMOD                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
-#define REG_DMA7_DSCPTR_CUR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
-#define REG_DMA7_DSCPTR_PRV             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
-#define REG_DMA7_ADDR_CUR               0xFFC413AC         /* DMA7 Current Address */
-#define REG_DMA7_STAT                   0xFFC413B0         /* DMA7 Status Register */
-#define REG_DMA7_XCNT_CUR               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA7_YCNT_CUR               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
-#define REG_DMA7_BWLCNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
-#define REG_DMA7_BWLCNT_CUR             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
-#define REG_DMA7_BWMCNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
-#define REG_DMA7_BWMCNT_CUR             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA8
-   ========================= */
-#define REG_DMA8_DSCPTR_NXT             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
-#define REG_DMA8_ADDRSTART              0xFFC41404         /* DMA8 Start Address of Current Buffer */
-#define REG_DMA8_CFG                    0xFFC41408         /* DMA8 Configuration Register */
-#define REG_DMA8_XCNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
-#define REG_DMA8_XMOD                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
-#define REG_DMA8_YCNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
-#define REG_DMA8_YMOD                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
-#define REG_DMA8_DSCPTR_CUR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
-#define REG_DMA8_DSCPTR_PRV             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
-#define REG_DMA8_ADDR_CUR               0xFFC4142C         /* DMA8 Current Address */
-#define REG_DMA8_STAT                   0xFFC41430         /* DMA8 Status Register */
-#define REG_DMA8_XCNT_CUR               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA8_YCNT_CUR               0xFFC41438         /* DMA8 Current Row Count (2D only) */
-#define REG_DMA8_BWLCNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
-#define REG_DMA8_BWLCNT_CUR             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
-#define REG_DMA8_BWMCNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
-#define REG_DMA8_BWMCNT_CUR             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA9
-   ========================= */
-#define REG_DMA9_DSCPTR_NXT             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
-#define REG_DMA9_ADDRSTART              0xFFC41484         /* DMA9 Start Address of Current Buffer */
-#define REG_DMA9_CFG                    0xFFC41488         /* DMA9 Configuration Register */
-#define REG_DMA9_XCNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
-#define REG_DMA9_XMOD                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
-#define REG_DMA9_YCNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
-#define REG_DMA9_YMOD                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
-#define REG_DMA9_DSCPTR_CUR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
-#define REG_DMA9_DSCPTR_PRV             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
-#define REG_DMA9_ADDR_CUR               0xFFC414AC         /* DMA9 Current Address */
-#define REG_DMA9_STAT                   0xFFC414B0         /* DMA9 Status Register */
-#define REG_DMA9_XCNT_CUR               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA9_YCNT_CUR               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
-#define REG_DMA9_BWLCNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
-#define REG_DMA9_BWLCNT_CUR             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
-#define REG_DMA9_BWMCNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
-#define REG_DMA9_BWMCNT_CUR             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA10
-   ========================= */
-#define REG_DMA10_DSCPTR_NXT            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
-#define REG_DMA10_ADDRSTART             0xFFC05004         /* DMA10 Start Address of Current Buffer */
-#define REG_DMA10_CFG                   0xFFC05008         /* DMA10 Configuration Register */
-#define REG_DMA10_XCNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
-#define REG_DMA10_XMOD                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
-#define REG_DMA10_YCNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
-#define REG_DMA10_YMOD                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
-#define REG_DMA10_DSCPTR_CUR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
-#define REG_DMA10_DSCPTR_PRV            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
-#define REG_DMA10_ADDR_CUR              0xFFC0502C         /* DMA10 Current Address */
-#define REG_DMA10_STAT                  0xFFC05030         /* DMA10 Status Register */
-#define REG_DMA10_XCNT_CUR              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA10_YCNT_CUR              0xFFC05038         /* DMA10 Current Row Count (2D only) */
-#define REG_DMA10_BWLCNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
-#define REG_DMA10_BWLCNT_CUR            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
-#define REG_DMA10_BWMCNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
-#define REG_DMA10_BWMCNT_CUR            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA11
-   ========================= */
-#define REG_DMA11_DSCPTR_NXT            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
-#define REG_DMA11_ADDRSTART             0xFFC05084         /* DMA11 Start Address of Current Buffer */
-#define REG_DMA11_CFG                   0xFFC05088         /* DMA11 Configuration Register */
-#define REG_DMA11_XCNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
-#define REG_DMA11_XMOD                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
-#define REG_DMA11_YCNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
-#define REG_DMA11_YMOD                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
-#define REG_DMA11_DSCPTR_CUR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
-#define REG_DMA11_DSCPTR_PRV            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
-#define REG_DMA11_ADDR_CUR              0xFFC050AC         /* DMA11 Current Address */
-#define REG_DMA11_STAT                  0xFFC050B0         /* DMA11 Status Register */
-#define REG_DMA11_XCNT_CUR              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA11_YCNT_CUR              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
-#define REG_DMA11_BWLCNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
-#define REG_DMA11_BWLCNT_CUR            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
-#define REG_DMA11_BWMCNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
-#define REG_DMA11_BWMCNT_CUR            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA12
-   ========================= */
-#define REG_DMA12_DSCPTR_NXT            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
-#define REG_DMA12_ADDRSTART             0xFFC05104         /* DMA12 Start Address of Current Buffer */
-#define REG_DMA12_CFG                   0xFFC05108         /* DMA12 Configuration Register */
-#define REG_DMA12_XCNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
-#define REG_DMA12_XMOD                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
-#define REG_DMA12_YCNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
-#define REG_DMA12_YMOD                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
-#define REG_DMA12_DSCPTR_CUR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
-#define REG_DMA12_DSCPTR_PRV            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
-#define REG_DMA12_ADDR_CUR              0xFFC0512C         /* DMA12 Current Address */
-#define REG_DMA12_STAT                  0xFFC05130         /* DMA12 Status Register */
-#define REG_DMA12_XCNT_CUR              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA12_YCNT_CUR              0xFFC05138         /* DMA12 Current Row Count (2D only) */
-#define REG_DMA12_BWLCNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
-#define REG_DMA12_BWLCNT_CUR            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
-#define REG_DMA12_BWMCNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
-#define REG_DMA12_BWMCNT_CUR            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA13
-   ========================= */
-#define REG_DMA13_DSCPTR_NXT            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
-#define REG_DMA13_ADDRSTART             0xFFC07004         /* DMA13 Start Address of Current Buffer */
-#define REG_DMA13_CFG                   0xFFC07008         /* DMA13 Configuration Register */
-#define REG_DMA13_XCNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
-#define REG_DMA13_XMOD                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
-#define REG_DMA13_YCNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
-#define REG_DMA13_YMOD                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
-#define REG_DMA13_DSCPTR_CUR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
-#define REG_DMA13_DSCPTR_PRV            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
-#define REG_DMA13_ADDR_CUR              0xFFC0702C         /* DMA13 Current Address */
-#define REG_DMA13_STAT                  0xFFC07030         /* DMA13 Status Register */
-#define REG_DMA13_XCNT_CUR              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA13_YCNT_CUR              0xFFC07038         /* DMA13 Current Row Count (2D only) */
-#define REG_DMA13_BWLCNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
-#define REG_DMA13_BWLCNT_CUR            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
-#define REG_DMA13_BWMCNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
-#define REG_DMA13_BWMCNT_CUR            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA14
-   ========================= */
-#define REG_DMA14_DSCPTR_NXT            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
-#define REG_DMA14_ADDRSTART             0xFFC07084         /* DMA14 Start Address of Current Buffer */
-#define REG_DMA14_CFG                   0xFFC07088         /* DMA14 Configuration Register */
-#define REG_DMA14_XCNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
-#define REG_DMA14_XMOD                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
-#define REG_DMA14_YCNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
-#define REG_DMA14_YMOD                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
-#define REG_DMA14_DSCPTR_CUR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
-#define REG_DMA14_DSCPTR_PRV            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
-#define REG_DMA14_ADDR_CUR              0xFFC070AC         /* DMA14 Current Address */
-#define REG_DMA14_STAT                  0xFFC070B0         /* DMA14 Status Register */
-#define REG_DMA14_XCNT_CUR              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA14_YCNT_CUR              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
-#define REG_DMA14_BWLCNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
-#define REG_DMA14_BWLCNT_CUR            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
-#define REG_DMA14_BWMCNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
-#define REG_DMA14_BWMCNT_CUR            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA15
-   ========================= */
-#define REG_DMA15_DSCPTR_NXT            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
-#define REG_DMA15_ADDRSTART             0xFFC07104         /* DMA15 Start Address of Current Buffer */
-#define REG_DMA15_CFG                   0xFFC07108         /* DMA15 Configuration Register */
-#define REG_DMA15_XCNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
-#define REG_DMA15_XMOD                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
-#define REG_DMA15_YCNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
-#define REG_DMA15_YMOD                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
-#define REG_DMA15_DSCPTR_CUR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
-#define REG_DMA15_DSCPTR_PRV            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
-#define REG_DMA15_ADDR_CUR              0xFFC0712C         /* DMA15 Current Address */
-#define REG_DMA15_STAT                  0xFFC07130         /* DMA15 Status Register */
-#define REG_DMA15_XCNT_CUR              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA15_YCNT_CUR              0xFFC07138         /* DMA15 Current Row Count (2D only) */
-#define REG_DMA15_BWLCNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
-#define REG_DMA15_BWLCNT_CUR            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
-#define REG_DMA15_BWMCNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
-#define REG_DMA15_BWMCNT_CUR            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA16
-   ========================= */
-#define REG_DMA16_DSCPTR_NXT            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
-#define REG_DMA16_ADDRSTART             0xFFC07184         /* DMA16 Start Address of Current Buffer */
-#define REG_DMA16_CFG                   0xFFC07188         /* DMA16 Configuration Register */
-#define REG_DMA16_XCNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
-#define REG_DMA16_XMOD                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
-#define REG_DMA16_YCNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
-#define REG_DMA16_YMOD                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
-#define REG_DMA16_DSCPTR_CUR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
-#define REG_DMA16_DSCPTR_PRV            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
-#define REG_DMA16_ADDR_CUR              0xFFC071AC         /* DMA16 Current Address */
-#define REG_DMA16_STAT                  0xFFC071B0         /* DMA16 Status Register */
-#define REG_DMA16_XCNT_CUR              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA16_YCNT_CUR              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
-#define REG_DMA16_BWLCNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
-#define REG_DMA16_BWLCNT_CUR            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
-#define REG_DMA16_BWMCNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
-#define REG_DMA16_BWMCNT_CUR            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA17
-   ========================= */
-#define REG_DMA17_DSCPTR_NXT            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
-#define REG_DMA17_ADDRSTART             0xFFC07204         /* DMA17 Start Address of Current Buffer */
-#define REG_DMA17_CFG                   0xFFC07208         /* DMA17 Configuration Register */
-#define REG_DMA17_XCNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
-#define REG_DMA17_XMOD                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
-#define REG_DMA17_YCNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
-#define REG_DMA17_YMOD                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
-#define REG_DMA17_DSCPTR_CUR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
-#define REG_DMA17_DSCPTR_PRV            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
-#define REG_DMA17_ADDR_CUR              0xFFC0722C         /* DMA17 Current Address */
-#define REG_DMA17_STAT                  0xFFC07230         /* DMA17 Status Register */
-#define REG_DMA17_XCNT_CUR              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA17_YCNT_CUR              0xFFC07238         /* DMA17 Current Row Count (2D only) */
-#define REG_DMA17_BWLCNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
-#define REG_DMA17_BWLCNT_CUR            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
-#define REG_DMA17_BWMCNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
-#define REG_DMA17_BWMCNT_CUR            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA18
-   ========================= */
-#define REG_DMA18_DSCPTR_NXT            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
-#define REG_DMA18_ADDRSTART             0xFFC07284         /* DMA18 Start Address of Current Buffer */
-#define REG_DMA18_CFG                   0xFFC07288         /* DMA18 Configuration Register */
-#define REG_DMA18_XCNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
-#define REG_DMA18_XMOD                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
-#define REG_DMA18_YCNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
-#define REG_DMA18_YMOD                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
-#define REG_DMA18_DSCPTR_CUR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
-#define REG_DMA18_DSCPTR_PRV            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
-#define REG_DMA18_ADDR_CUR              0xFFC072AC         /* DMA18 Current Address */
-#define REG_DMA18_STAT                  0xFFC072B0         /* DMA18 Status Register */
-#define REG_DMA18_XCNT_CUR              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA18_YCNT_CUR              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
-#define REG_DMA18_BWLCNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
-#define REG_DMA18_BWLCNT_CUR            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
-#define REG_DMA18_BWMCNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
-#define REG_DMA18_BWMCNT_CUR            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA19
-   ========================= */
-#define REG_DMA19_DSCPTR_NXT            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
-#define REG_DMA19_ADDRSTART             0xFFC07304         /* DMA19 Start Address of Current Buffer */
-#define REG_DMA19_CFG                   0xFFC07308         /* DMA19 Configuration Register */
-#define REG_DMA19_XCNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
-#define REG_DMA19_XMOD                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
-#define REG_DMA19_YCNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
-#define REG_DMA19_YMOD                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
-#define REG_DMA19_DSCPTR_CUR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
-#define REG_DMA19_DSCPTR_PRV            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
-#define REG_DMA19_ADDR_CUR              0xFFC0732C         /* DMA19 Current Address */
-#define REG_DMA19_STAT                  0xFFC07330         /* DMA19 Status Register */
-#define REG_DMA19_XCNT_CUR              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA19_YCNT_CUR              0xFFC07338         /* DMA19 Current Row Count (2D only) */
-#define REG_DMA19_BWLCNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
-#define REG_DMA19_BWLCNT_CUR            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
-#define REG_DMA19_BWMCNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
-#define REG_DMA19_BWMCNT_CUR            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA20
-   ========================= */
-#define REG_DMA20_DSCPTR_NXT            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
-#define REG_DMA20_ADDRSTART             0xFFC07384         /* DMA20 Start Address of Current Buffer */
-#define REG_DMA20_CFG                   0xFFC07388         /* DMA20 Configuration Register */
-#define REG_DMA20_XCNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
-#define REG_DMA20_XMOD                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
-#define REG_DMA20_YCNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
-#define REG_DMA20_YMOD                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
-#define REG_DMA20_DSCPTR_CUR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
-#define REG_DMA20_DSCPTR_PRV            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
-#define REG_DMA20_ADDR_CUR              0xFFC073AC         /* DMA20 Current Address */
-#define REG_DMA20_STAT                  0xFFC073B0         /* DMA20 Status Register */
-#define REG_DMA20_XCNT_CUR              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA20_YCNT_CUR              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
-#define REG_DMA20_BWLCNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
-#define REG_DMA20_BWLCNT_CUR            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
-#define REG_DMA20_BWMCNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
-#define REG_DMA20_BWMCNT_CUR            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA21
-   ========================= */
-#define REG_DMA21_DSCPTR_NXT            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
-#define REG_DMA21_ADDRSTART             0xFFC09004         /* DMA21 Start Address of Current Buffer */
-#define REG_DMA21_CFG                   0xFFC09008         /* DMA21 Configuration Register */
-#define REG_DMA21_XCNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
-#define REG_DMA21_XMOD                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
-#define REG_DMA21_YCNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
-#define REG_DMA21_YMOD                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
-#define REG_DMA21_DSCPTR_CUR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
-#define REG_DMA21_DSCPTR_PRV            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
-#define REG_DMA21_ADDR_CUR              0xFFC0902C         /* DMA21 Current Address */
-#define REG_DMA21_STAT                  0xFFC09030         /* DMA21 Status Register */
-#define REG_DMA21_XCNT_CUR              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA21_YCNT_CUR              0xFFC09038         /* DMA21 Current Row Count (2D only) */
-#define REG_DMA21_BWLCNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
-#define REG_DMA21_BWLCNT_CUR            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
-#define REG_DMA21_BWMCNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
-#define REG_DMA21_BWMCNT_CUR            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA22
-   ========================= */
-#define REG_DMA22_DSCPTR_NXT            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
-#define REG_DMA22_ADDRSTART             0xFFC09084         /* DMA22 Start Address of Current Buffer */
-#define REG_DMA22_CFG                   0xFFC09088         /* DMA22 Configuration Register */
-#define REG_DMA22_XCNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
-#define REG_DMA22_XMOD                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
-#define REG_DMA22_YCNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
-#define REG_DMA22_YMOD                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
-#define REG_DMA22_DSCPTR_CUR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
-#define REG_DMA22_DSCPTR_PRV            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
-#define REG_DMA22_ADDR_CUR              0xFFC090AC         /* DMA22 Current Address */
-#define REG_DMA22_STAT                  0xFFC090B0         /* DMA22 Status Register */
-#define REG_DMA22_XCNT_CUR              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA22_YCNT_CUR              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
-#define REG_DMA22_BWLCNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
-#define REG_DMA22_BWLCNT_CUR            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
-#define REG_DMA22_BWMCNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
-#define REG_DMA22_BWMCNT_CUR            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA23
-   ========================= */
-#define REG_DMA23_DSCPTR_NXT            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
-#define REG_DMA23_ADDRSTART             0xFFC09104         /* DMA23 Start Address of Current Buffer */
-#define REG_DMA23_CFG                   0xFFC09108         /* DMA23 Configuration Register */
-#define REG_DMA23_XCNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
-#define REG_DMA23_XMOD                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
-#define REG_DMA23_YCNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
-#define REG_DMA23_YMOD                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
-#define REG_DMA23_DSCPTR_CUR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
-#define REG_DMA23_DSCPTR_PRV            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
-#define REG_DMA23_ADDR_CUR              0xFFC0912C         /* DMA23 Current Address */
-#define REG_DMA23_STAT                  0xFFC09130         /* DMA23 Status Register */
-#define REG_DMA23_XCNT_CUR              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA23_YCNT_CUR              0xFFC09138         /* DMA23 Current Row Count (2D only) */
-#define REG_DMA23_BWLCNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
-#define REG_DMA23_BWLCNT_CUR            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
-#define REG_DMA23_BWMCNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
-#define REG_DMA23_BWMCNT_CUR            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA24
-   ========================= */
-#define REG_DMA24_DSCPTR_NXT            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
-#define REG_DMA24_ADDRSTART             0xFFC09184         /* DMA24 Start Address of Current Buffer */
-#define REG_DMA24_CFG                   0xFFC09188         /* DMA24 Configuration Register */
-#define REG_DMA24_XCNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
-#define REG_DMA24_XMOD                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
-#define REG_DMA24_YCNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
-#define REG_DMA24_YMOD                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
-#define REG_DMA24_DSCPTR_CUR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
-#define REG_DMA24_DSCPTR_PRV            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
-#define REG_DMA24_ADDR_CUR              0xFFC091AC         /* DMA24 Current Address */
-#define REG_DMA24_STAT                  0xFFC091B0         /* DMA24 Status Register */
-#define REG_DMA24_XCNT_CUR              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA24_YCNT_CUR              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
-#define REG_DMA24_BWLCNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
-#define REG_DMA24_BWLCNT_CUR            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
-#define REG_DMA24_BWMCNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
-#define REG_DMA24_BWMCNT_CUR            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA25
-   ========================= */
-#define REG_DMA25_DSCPTR_NXT            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
-#define REG_DMA25_ADDRSTART             0xFFC09204         /* DMA25 Start Address of Current Buffer */
-#define REG_DMA25_CFG                   0xFFC09208         /* DMA25 Configuration Register */
-#define REG_DMA25_XCNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
-#define REG_DMA25_XMOD                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
-#define REG_DMA25_YCNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
-#define REG_DMA25_YMOD                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
-#define REG_DMA25_DSCPTR_CUR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
-#define REG_DMA25_DSCPTR_PRV            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
-#define REG_DMA25_ADDR_CUR              0xFFC0922C         /* DMA25 Current Address */
-#define REG_DMA25_STAT                  0xFFC09230         /* DMA25 Status Register */
-#define REG_DMA25_XCNT_CUR              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA25_YCNT_CUR              0xFFC09238         /* DMA25 Current Row Count (2D only) */
-#define REG_DMA25_BWLCNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
-#define REG_DMA25_BWLCNT_CUR            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
-#define REG_DMA25_BWMCNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
-#define REG_DMA25_BWMCNT_CUR            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA26
-   ========================= */
-#define REG_DMA26_DSCPTR_NXT            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
-#define REG_DMA26_ADDRSTART             0xFFC09284         /* DMA26 Start Address of Current Buffer */
-#define REG_DMA26_CFG                   0xFFC09288         /* DMA26 Configuration Register */
-#define REG_DMA26_XCNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
-#define REG_DMA26_XMOD                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
-#define REG_DMA26_YCNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
-#define REG_DMA26_YMOD                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
-#define REG_DMA26_DSCPTR_CUR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
-#define REG_DMA26_DSCPTR_PRV            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
-#define REG_DMA26_ADDR_CUR              0xFFC092AC         /* DMA26 Current Address */
-#define REG_DMA26_STAT                  0xFFC092B0         /* DMA26 Status Register */
-#define REG_DMA26_XCNT_CUR              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA26_YCNT_CUR              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
-#define REG_DMA26_BWLCNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
-#define REG_DMA26_BWLCNT_CUR            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
-#define REG_DMA26_BWMCNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
-#define REG_DMA26_BWMCNT_CUR            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA27
-   ========================= */
-#define REG_DMA27_DSCPTR_NXT            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
-#define REG_DMA27_ADDRSTART             0xFFC09304         /* DMA27 Start Address of Current Buffer */
-#define REG_DMA27_CFG                   0xFFC09308         /* DMA27 Configuration Register */
-#define REG_DMA27_XCNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
-#define REG_DMA27_XMOD                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
-#define REG_DMA27_YCNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
-#define REG_DMA27_YMOD                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
-#define REG_DMA27_DSCPTR_CUR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
-#define REG_DMA27_DSCPTR_PRV            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
-#define REG_DMA27_ADDR_CUR              0xFFC0932C         /* DMA27 Current Address */
-#define REG_DMA27_STAT                  0xFFC09330         /* DMA27 Status Register */
-#define REG_DMA27_XCNT_CUR              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA27_YCNT_CUR              0xFFC09338         /* DMA27 Current Row Count (2D only) */
-#define REG_DMA27_BWLCNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
-#define REG_DMA27_BWLCNT_CUR            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
-#define REG_DMA27_BWMCNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
-#define REG_DMA27_BWMCNT_CUR            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA28
-   ========================= */
-#define REG_DMA28_DSCPTR_NXT            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
-#define REG_DMA28_ADDRSTART             0xFFC09384         /* DMA28 Start Address of Current Buffer */
-#define REG_DMA28_CFG                   0xFFC09388         /* DMA28 Configuration Register */
-#define REG_DMA28_XCNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
-#define REG_DMA28_XMOD                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
-#define REG_DMA28_YCNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
-#define REG_DMA28_YMOD                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
-#define REG_DMA28_DSCPTR_CUR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
-#define REG_DMA28_DSCPTR_PRV            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
-#define REG_DMA28_ADDR_CUR              0xFFC093AC         /* DMA28 Current Address */
-#define REG_DMA28_STAT                  0xFFC093B0         /* DMA28 Status Register */
-#define REG_DMA28_XCNT_CUR              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA28_YCNT_CUR              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
-#define REG_DMA28_BWLCNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
-#define REG_DMA28_BWLCNT_CUR            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
-#define REG_DMA28_BWMCNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
-#define REG_DMA28_BWMCNT_CUR            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA29
-   ========================= */
-#define REG_DMA29_DSCPTR_NXT            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
-#define REG_DMA29_ADDRSTART             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
-#define REG_DMA29_CFG                   0xFFC0B008         /* DMA29 Configuration Register */
-#define REG_DMA29_XCNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
-#define REG_DMA29_XMOD                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
-#define REG_DMA29_YCNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
-#define REG_DMA29_YMOD                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
-#define REG_DMA29_DSCPTR_CUR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
-#define REG_DMA29_DSCPTR_PRV            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
-#define REG_DMA29_ADDR_CUR              0xFFC0B02C         /* DMA29 Current Address */
-#define REG_DMA29_STAT                  0xFFC0B030         /* DMA29 Status Register */
-#define REG_DMA29_XCNT_CUR              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA29_YCNT_CUR              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
-#define REG_DMA29_BWLCNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
-#define REG_DMA29_BWLCNT_CUR            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
-#define REG_DMA29_BWMCNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
-#define REG_DMA29_BWMCNT_CUR            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA30
-   ========================= */
-#define REG_DMA30_DSCPTR_NXT            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
-#define REG_DMA30_ADDRSTART             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
-#define REG_DMA30_CFG                   0xFFC0B088         /* DMA30 Configuration Register */
-#define REG_DMA30_XCNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
-#define REG_DMA30_XMOD                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
-#define REG_DMA30_YCNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
-#define REG_DMA30_YMOD                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
-#define REG_DMA30_DSCPTR_CUR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
-#define REG_DMA30_DSCPTR_PRV            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
-#define REG_DMA30_ADDR_CUR              0xFFC0B0AC         /* DMA30 Current Address */
-#define REG_DMA30_STAT                  0xFFC0B0B0         /* DMA30 Status Register */
-#define REG_DMA30_XCNT_CUR              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA30_YCNT_CUR              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
-#define REG_DMA30_BWLCNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
-#define REG_DMA30_BWLCNT_CUR            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
-#define REG_DMA30_BWMCNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
-#define REG_DMA30_BWMCNT_CUR            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA31
-   ========================= */
-#define REG_DMA31_DSCPTR_NXT            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
-#define REG_DMA31_ADDRSTART             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
-#define REG_DMA31_CFG                   0xFFC0B108         /* DMA31 Configuration Register */
-#define REG_DMA31_XCNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
-#define REG_DMA31_XMOD                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
-#define REG_DMA31_YCNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
-#define REG_DMA31_YMOD                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
-#define REG_DMA31_DSCPTR_CUR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
-#define REG_DMA31_DSCPTR_PRV            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
-#define REG_DMA31_ADDR_CUR              0xFFC0B12C         /* DMA31 Current Address */
-#define REG_DMA31_STAT                  0xFFC0B130         /* DMA31 Status Register */
-#define REG_DMA31_XCNT_CUR              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA31_YCNT_CUR              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
-#define REG_DMA31_BWLCNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
-#define REG_DMA31_BWLCNT_CUR            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
-#define REG_DMA31_BWMCNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
-#define REG_DMA31_BWMCNT_CUR            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA32
-   ========================= */
-#define REG_DMA32_DSCPTR_NXT            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
-#define REG_DMA32_ADDRSTART             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
-#define REG_DMA32_CFG                   0xFFC0B188         /* DMA32 Configuration Register */
-#define REG_DMA32_XCNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
-#define REG_DMA32_XMOD                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
-#define REG_DMA32_YCNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
-#define REG_DMA32_YMOD                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
-#define REG_DMA32_DSCPTR_CUR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
-#define REG_DMA32_DSCPTR_PRV            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
-#define REG_DMA32_ADDR_CUR              0xFFC0B1AC         /* DMA32 Current Address */
-#define REG_DMA32_STAT                  0xFFC0B1B0         /* DMA32 Status Register */
-#define REG_DMA32_XCNT_CUR              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA32_YCNT_CUR              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
-#define REG_DMA32_BWLCNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
-#define REG_DMA32_BWLCNT_CUR            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
-#define REG_DMA32_BWMCNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
-#define REG_DMA32_BWMCNT_CUR            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA33
-   ========================= */
-#define REG_DMA33_DSCPTR_NXT            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
-#define REG_DMA33_ADDRSTART             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
-#define REG_DMA33_CFG                   0xFFC0D008         /* DMA33 Configuration Register */
-#define REG_DMA33_XCNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
-#define REG_DMA33_XMOD                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
-#define REG_DMA33_YCNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
-#define REG_DMA33_YMOD                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
-#define REG_DMA33_DSCPTR_CUR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
-#define REG_DMA33_DSCPTR_PRV            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
-#define REG_DMA33_ADDR_CUR              0xFFC0D02C         /* DMA33 Current Address */
-#define REG_DMA33_STAT                  0xFFC0D030         /* DMA33 Status Register */
-#define REG_DMA33_XCNT_CUR              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA33_YCNT_CUR              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
-#define REG_DMA33_BWLCNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
-#define REG_DMA33_BWLCNT_CUR            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
-#define REG_DMA33_BWMCNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
-#define REG_DMA33_BWMCNT_CUR            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA34
-   ========================= */
-#define REG_DMA34_DSCPTR_NXT            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
-#define REG_DMA34_ADDRSTART             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
-#define REG_DMA34_CFG                   0xFFC0D088         /* DMA34 Configuration Register */
-#define REG_DMA34_XCNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
-#define REG_DMA34_XMOD                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
-#define REG_DMA34_YCNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
-#define REG_DMA34_YMOD                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
-#define REG_DMA34_DSCPTR_CUR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
-#define REG_DMA34_DSCPTR_PRV            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
-#define REG_DMA34_ADDR_CUR              0xFFC0D0AC         /* DMA34 Current Address */
-#define REG_DMA34_STAT                  0xFFC0D0B0         /* DMA34 Status Register */
-#define REG_DMA34_XCNT_CUR              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA34_YCNT_CUR              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
-#define REG_DMA34_BWLCNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
-#define REG_DMA34_BWLCNT_CUR            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
-#define REG_DMA34_BWMCNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
-#define REG_DMA34_BWMCNT_CUR            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA35
-   ========================= */
-#define REG_DMA35_DSCPTR_NXT            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
-#define REG_DMA35_ADDRSTART             0xFFC10004         /* DMA35 Start Address of Current Buffer */
-#define REG_DMA35_CFG                   0xFFC10008         /* DMA35 Configuration Register */
-#define REG_DMA35_XCNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
-#define REG_DMA35_XMOD                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
-#define REG_DMA35_YCNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
-#define REG_DMA35_YMOD                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
-#define REG_DMA35_DSCPTR_CUR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
-#define REG_DMA35_DSCPTR_PRV            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
-#define REG_DMA35_ADDR_CUR              0xFFC1002C         /* DMA35 Current Address */
-#define REG_DMA35_STAT                  0xFFC10030         /* DMA35 Status Register */
-#define REG_DMA35_XCNT_CUR              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA35_YCNT_CUR              0xFFC10038         /* DMA35 Current Row Count (2D only) */
-#define REG_DMA35_BWLCNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
-#define REG_DMA35_BWLCNT_CUR            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
-#define REG_DMA35_BWMCNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
-#define REG_DMA35_BWMCNT_CUR            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA36
-   ========================= */
-#define REG_DMA36_DSCPTR_NXT            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
-#define REG_DMA36_ADDRSTART             0xFFC10084         /* DMA36 Start Address of Current Buffer */
-#define REG_DMA36_CFG                   0xFFC10088         /* DMA36 Configuration Register */
-#define REG_DMA36_XCNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
-#define REG_DMA36_XMOD                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
-#define REG_DMA36_YCNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
-#define REG_DMA36_YMOD                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
-#define REG_DMA36_DSCPTR_CUR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
-#define REG_DMA36_DSCPTR_PRV            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
-#define REG_DMA36_ADDR_CUR              0xFFC100AC         /* DMA36 Current Address */
-#define REG_DMA36_STAT                  0xFFC100B0         /* DMA36 Status Register */
-#define REG_DMA36_XCNT_CUR              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA36_YCNT_CUR              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
-#define REG_DMA36_BWLCNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
-#define REG_DMA36_BWLCNT_CUR            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
-#define REG_DMA36_BWMCNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
-#define REG_DMA36_BWMCNT_CUR            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA37
-   ========================= */
-#define REG_DMA37_DSCPTR_NXT            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
-#define REG_DMA37_ADDRSTART             0xFFC10104         /* DMA37 Start Address of Current Buffer */
-#define REG_DMA37_CFG                   0xFFC10108         /* DMA37 Configuration Register */
-#define REG_DMA37_XCNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
-#define REG_DMA37_XMOD                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
-#define REG_DMA37_YCNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
-#define REG_DMA37_YMOD                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
-#define REG_DMA37_DSCPTR_CUR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
-#define REG_DMA37_DSCPTR_PRV            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
-#define REG_DMA37_ADDR_CUR              0xFFC1012C         /* DMA37 Current Address */
-#define REG_DMA37_STAT                  0xFFC10130         /* DMA37 Status Register */
-#define REG_DMA37_XCNT_CUR              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA37_YCNT_CUR              0xFFC10138         /* DMA37 Current Row Count (2D only) */
-#define REG_DMA37_BWLCNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
-#define REG_DMA37_BWLCNT_CUR            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
-#define REG_DMA37_BWMCNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
-#define REG_DMA37_BWMCNT_CUR            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA38
-   ========================= */
-#define REG_DMA38_DSCPTR_NXT            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
-#define REG_DMA38_ADDRSTART             0xFFC12004         /* DMA38 Start Address of Current Buffer */
-#define REG_DMA38_CFG                   0xFFC12008         /* DMA38 Configuration Register */
-#define REG_DMA38_XCNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
-#define REG_DMA38_XMOD                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
-#define REG_DMA38_YCNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
-#define REG_DMA38_YMOD                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
-#define REG_DMA38_DSCPTR_CUR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
-#define REG_DMA38_DSCPTR_PRV            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
-#define REG_DMA38_ADDR_CUR              0xFFC1202C         /* DMA38 Current Address */
-#define REG_DMA38_STAT                  0xFFC12030         /* DMA38 Status Register */
-#define REG_DMA38_XCNT_CUR              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA38_YCNT_CUR              0xFFC12038         /* DMA38 Current Row Count (2D only) */
-#define REG_DMA38_BWLCNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
-#define REG_DMA38_BWLCNT_CUR            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
-#define REG_DMA38_BWMCNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
-#define REG_DMA38_BWMCNT_CUR            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA39
-   ========================= */
-#define REG_DMA39_DSCPTR_NXT            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
-#define REG_DMA39_ADDRSTART             0xFFC12084         /* DMA39 Start Address of Current Buffer */
-#define REG_DMA39_CFG                   0xFFC12088         /* DMA39 Configuration Register */
-#define REG_DMA39_XCNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
-#define REG_DMA39_XMOD                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
-#define REG_DMA39_YCNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
-#define REG_DMA39_YMOD                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
-#define REG_DMA39_DSCPTR_CUR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
-#define REG_DMA39_DSCPTR_PRV            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
-#define REG_DMA39_ADDR_CUR              0xFFC120AC         /* DMA39 Current Address */
-#define REG_DMA39_STAT                  0xFFC120B0         /* DMA39 Status Register */
-#define REG_DMA39_XCNT_CUR              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA39_YCNT_CUR              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
-#define REG_DMA39_BWLCNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
-#define REG_DMA39_BWLCNT_CUR            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
-#define REG_DMA39_BWMCNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
-#define REG_DMA39_BWMCNT_CUR            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA40
-   ========================= */
-#define REG_DMA40_DSCPTR_NXT            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
-#define REG_DMA40_ADDRSTART             0xFFC12104         /* DMA40 Start Address of Current Buffer */
-#define REG_DMA40_CFG                   0xFFC12108         /* DMA40 Configuration Register */
-#define REG_DMA40_XCNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
-#define REG_DMA40_XMOD                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
-#define REG_DMA40_YCNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
-#define REG_DMA40_YMOD                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
-#define REG_DMA40_DSCPTR_CUR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
-#define REG_DMA40_DSCPTR_PRV            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
-#define REG_DMA40_ADDR_CUR              0xFFC1212C         /* DMA40 Current Address */
-#define REG_DMA40_STAT                  0xFFC12130         /* DMA40 Status Register */
-#define REG_DMA40_XCNT_CUR              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA40_YCNT_CUR              0xFFC12138         /* DMA40 Current Row Count (2D only) */
-#define REG_DMA40_BWLCNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
-#define REG_DMA40_BWLCNT_CUR            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
-#define REG_DMA40_BWMCNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
-#define REG_DMA40_BWMCNT_CUR            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA41
-   ========================= */
-#define REG_DMA41_DSCPTR_NXT            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
-#define REG_DMA41_ADDRSTART             0xFFC12184         /* DMA41 Start Address of Current Buffer */
-#define REG_DMA41_CFG                   0xFFC12188         /* DMA41 Configuration Register */
-#define REG_DMA41_XCNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
-#define REG_DMA41_XMOD                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
-#define REG_DMA41_YCNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
-#define REG_DMA41_YMOD                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
-#define REG_DMA41_DSCPTR_CUR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
-#define REG_DMA41_DSCPTR_PRV            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
-#define REG_DMA41_ADDR_CUR              0xFFC121AC         /* DMA41 Current Address */
-#define REG_DMA41_STAT                  0xFFC121B0         /* DMA41 Status Register */
-#define REG_DMA41_XCNT_CUR              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA41_YCNT_CUR              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
-#define REG_DMA41_BWLCNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
-#define REG_DMA41_BWLCNT_CUR            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
-#define REG_DMA41_BWMCNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
-#define REG_DMA41_BWMCNT_CUR            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA42
-   ========================= */
-#define REG_DMA42_DSCPTR_NXT            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
-#define REG_DMA42_ADDRSTART             0xFFC14004         /* DMA42 Start Address of Current Buffer */
-#define REG_DMA42_CFG                   0xFFC14008         /* DMA42 Configuration Register */
-#define REG_DMA42_XCNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
-#define REG_DMA42_XMOD                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
-#define REG_DMA42_YCNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
-#define REG_DMA42_YMOD                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
-#define REG_DMA42_DSCPTR_CUR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
-#define REG_DMA42_DSCPTR_PRV            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
-#define REG_DMA42_ADDR_CUR              0xFFC1402C         /* DMA42 Current Address */
-#define REG_DMA42_STAT                  0xFFC14030         /* DMA42 Status Register */
-#define REG_DMA42_XCNT_CUR              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA42_YCNT_CUR              0xFFC14038         /* DMA42 Current Row Count (2D only) */
-#define REG_DMA42_BWLCNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
-#define REG_DMA42_BWLCNT_CUR            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
-#define REG_DMA42_BWMCNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
-#define REG_DMA42_BWMCNT_CUR            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA43
-   ========================= */
-#define REG_DMA43_DSCPTR_NXT            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
-#define REG_DMA43_ADDRSTART             0xFFC14084         /* DMA43 Start Address of Current Buffer */
-#define REG_DMA43_CFG                   0xFFC14088         /* DMA43 Configuration Register */
-#define REG_DMA43_XCNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
-#define REG_DMA43_XMOD                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
-#define REG_DMA43_YCNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
-#define REG_DMA43_YMOD                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
-#define REG_DMA43_DSCPTR_CUR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
-#define REG_DMA43_DSCPTR_PRV            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
-#define REG_DMA43_ADDR_CUR              0xFFC140AC         /* DMA43 Current Address */
-#define REG_DMA43_STAT                  0xFFC140B0         /* DMA43 Status Register */
-#define REG_DMA43_XCNT_CUR              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA43_YCNT_CUR              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
-#define REG_DMA43_BWLCNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
-#define REG_DMA43_BWLCNT_CUR            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
-#define REG_DMA43_BWMCNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
-#define REG_DMA43_BWMCNT_CUR            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA44
-   ========================= */
-#define REG_DMA44_DSCPTR_NXT            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
-#define REG_DMA44_ADDRSTART             0xFFC14104         /* DMA44 Start Address of Current Buffer */
-#define REG_DMA44_CFG                   0xFFC14108         /* DMA44 Configuration Register */
-#define REG_DMA44_XCNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
-#define REG_DMA44_XMOD                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
-#define REG_DMA44_YCNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
-#define REG_DMA44_YMOD                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
-#define REG_DMA44_DSCPTR_CUR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
-#define REG_DMA44_DSCPTR_PRV            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
-#define REG_DMA44_ADDR_CUR              0xFFC1412C         /* DMA44 Current Address */
-#define REG_DMA44_STAT                  0xFFC14130         /* DMA44 Status Register */
-#define REG_DMA44_XCNT_CUR              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA44_YCNT_CUR              0xFFC14138         /* DMA44 Current Row Count (2D only) */
-#define REG_DMA44_BWLCNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
-#define REG_DMA44_BWLCNT_CUR            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
-#define REG_DMA44_BWMCNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
-#define REG_DMA44_BWMCNT_CUR            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA45
-   ========================= */
-#define REG_DMA45_DSCPTR_NXT            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
-#define REG_DMA45_ADDRSTART             0xFFC14184         /* DMA45 Start Address of Current Buffer */
-#define REG_DMA45_CFG                   0xFFC14188         /* DMA45 Configuration Register */
-#define REG_DMA45_XCNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
-#define REG_DMA45_XMOD                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
-#define REG_DMA45_YCNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
-#define REG_DMA45_YMOD                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
-#define REG_DMA45_DSCPTR_CUR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
-#define REG_DMA45_DSCPTR_PRV            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
-#define REG_DMA45_ADDR_CUR              0xFFC141AC         /* DMA45 Current Address */
-#define REG_DMA45_STAT                  0xFFC141B0         /* DMA45 Status Register */
-#define REG_DMA45_XCNT_CUR              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA45_YCNT_CUR              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
-#define REG_DMA45_BWLCNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
-#define REG_DMA45_BWLCNT_CUR            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
-#define REG_DMA45_BWMCNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
-#define REG_DMA45_BWMCNT_CUR            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA46
-   ========================= */
-#define REG_DMA46_DSCPTR_NXT            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
-#define REG_DMA46_ADDRSTART             0xFFC14204         /* DMA46 Start Address of Current Buffer */
-#define REG_DMA46_CFG                   0xFFC14208         /* DMA46 Configuration Register */
-#define REG_DMA46_XCNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
-#define REG_DMA46_XMOD                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
-#define REG_DMA46_YCNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
-#define REG_DMA46_YMOD                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
-#define REG_DMA46_DSCPTR_CUR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
-#define REG_DMA46_DSCPTR_PRV            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
-#define REG_DMA46_ADDR_CUR              0xFFC1422C         /* DMA46 Current Address */
-#define REG_DMA46_STAT                  0xFFC14230         /* DMA46 Status Register */
-#define REG_DMA46_XCNT_CUR              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA46_YCNT_CUR              0xFFC14238         /* DMA46 Current Row Count (2D only) */
-#define REG_DMA46_BWLCNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
-#define REG_DMA46_BWLCNT_CUR            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
-#define REG_DMA46_BWMCNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
-#define REG_DMA46_BWMCNT_CUR            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_CFG_PDRF                    28                               /* Peripheral Data Request Forward */
-#define BITP_DMA_CFG_TWOD                    26                               /* Two Dimension Addressing Enable */
-#define BITP_DMA_CFG_DESCIDCPY               25                               /* Descriptor ID Copy Control */
-#define BITP_DMA_CFG_TOVEN                   24                               /* Trigger Overrun Error Enable */
-#define BITP_DMA_CFG_TRIG                    22                               /* Generate Outgoing Trigger */
-#define BITP_DMA_CFG_INT                     20                               /* Generate Interrupt */
-#define BITP_DMA_CFG_NDSIZE                  16                               /* Next Descriptor Set Size */
-#define BITP_DMA_CFG_TWAIT                   15                               /* Wait for Trigger */
-#define BITP_DMA_CFG_FLOW                    12                               /* Next Operation */
-#define BITP_DMA_CFG_MSIZE                    8                               /* Memory Transfer Word Size */
-#define BITP_DMA_CFG_PSIZE                    4                               /* Peripheral Transfer Word Size */
-#define BITP_DMA_CFG_CADDR                    3                               /* Use Current Address */
-#define BITP_DMA_CFG_SYNC                     2                               /* Synchronize Work Unit Transitions */
-#define BITP_DMA_CFG_WNR                      1                               /* Write/Read Channel Direction */
-#define BITP_DMA_CFG_EN                       0                               /* DMA Channel Enable */
-
-#define BITM_DMA_CFG_PDRF                    (_ADI_MSK(0x10000000,uint32_t))  /* Peripheral Data Request Forward */
-#define ENUM_DMA_CFG_PDAT_NOTFWD             (_ADI_MSK(0x00000000,uint32_t))  /* PDRF: Peripheral Data Request Not Forwarded */
-#define ENUM_DMA_CFG_PDAT_FWD                (_ADI_MSK(0x10000000,uint32_t))  /* PDRF: Peripheral Data Request Forwarded */
-
-#define BITM_DMA_CFG_TWOD                    (_ADI_MSK(0x04000000,uint32_t))  /* Two Dimension Addressing Enable */
-#define ENUM_DMA_CFG_ADDR1D                  (_ADI_MSK(0x00000000,uint32_t))  /* TWOD: One-Dimensional Addressing */
-#define ENUM_DMA_CFG_ADDR2D                  (_ADI_MSK(0x04000000,uint32_t))  /* TWOD: Two-Dimensional Addressing */
-
-#define BITM_DMA_CFG_DESCIDCPY               (_ADI_MSK(0x02000000,uint32_t))  /* Descriptor ID Copy Control */
-#define ENUM_DMA_CFG_NO_COPY                 (_ADI_MSK(0x00000000,uint32_t))  /* DESCIDCPY: Never Copy */
-#define ENUM_DMA_CFG_COPY                    (_ADI_MSK(0x02000000,uint32_t))  /* DESCIDCPY: Copy on Work Unit Complete */
-
-#define BITM_DMA_CFG_TOVEN                   (_ADI_MSK(0x01000000,uint32_t))  /* Trigger Overrun Error Enable */
-#define ENUM_DMA_CFG_TOV_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* TOVEN: Ignore Trigger Overrun */
-#define ENUM_DMA_CFG_TOV_EN                  (_ADI_MSK(0x01000000,uint32_t))  /* TOVEN: Error on Trigger Overrun */
-
-#define BITM_DMA_CFG_TRIG                    (_ADI_MSK(0x00C00000,uint32_t))  /* Generate Outgoing Trigger */
-#define ENUM_DMA_CFG_NO_TRIG                 (_ADI_MSK(0x00000000,uint32_t))  /* TRIG: Never assert Trigger */
-#define ENUM_DMA_CFG_XCNT_TRIG               (_ADI_MSK(0x00400000,uint32_t))  /* TRIG: Trigger when XCNTCUR reaches 0 */
-#define ENUM_DMA_CFG_YCNT_TRIG               (_ADI_MSK(0x00800000,uint32_t))  /* TRIG: Trigger when YCNTCUR reaches 0 */
-
-#define BITM_DMA_CFG_INT                     (_ADI_MSK(0x00300000,uint32_t))  /* Generate Interrupt */
-#define ENUM_DMA_CFG_NO_INT                  (_ADI_MSK(0x00000000,uint32_t))  /* INT: Never assert Interrupt */
-#define ENUM_DMA_CFG_XCNT_INT                (_ADI_MSK(0x00100000,uint32_t))  /* INT: Interrupt when X Count Expires */
-#define ENUM_DMA_CFG_YCNT_INT                (_ADI_MSK(0x00200000,uint32_t))  /* INT: Interrupt when Y Count Expires */
-#define ENUM_DMA_CFG_PERIPH_INT              (_ADI_MSK(0x00300000,uint32_t))  /* INT: Peripheral Interrupt */
-
-#define BITM_DMA_CFG_NDSIZE                  (_ADI_MSK(0x00070000,uint32_t))  /* Next Descriptor Set Size */
-#define ENUM_DMA_CFG_FETCH01                 (_ADI_MSK(0x00000000,uint32_t))  /* NDSIZE: Fetch one Descriptor Element */
-#define ENUM_DMA_CFG_FETCH02                 (_ADI_MSK(0x00010000,uint32_t))  /* NDSIZE: Fetch two Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH03                 (_ADI_MSK(0x00020000,uint32_t))  /* NDSIZE: Fetch three Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH04                 (_ADI_MSK(0x00030000,uint32_t))  /* NDSIZE: Fetch four Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH05                 (_ADI_MSK(0x00040000,uint32_t))  /* NDSIZE: Fetch five Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH06                 (_ADI_MSK(0x00050000,uint32_t))  /* NDSIZE: Fetch six Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH07                 (_ADI_MSK(0x00060000,uint32_t))  /* NDSIZE: Fetch seven Descriptor Elements */
-
-#define BITM_DMA_CFG_TWAIT                   (_ADI_MSK(0x00008000,uint32_t))  /* Wait for Trigger */
-#define ENUM_DMA_CFG_NO_TRGWAIT              (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: Begin Work Unit Automatically (No Wait) */
-#define ENUM_DMA_CFG_TRGWAIT                 (_ADI_MSK(0x00008000,uint32_t))  /* TWAIT: Wait for Trigger (Halt before Work Unit) */
-
-#define BITM_DMA_CFG_FLOW                    (_ADI_MSK(0x00007000,uint32_t))  /* Next Operation */
-#define ENUM_DMA_CFG_STOP                    (_ADI_MSK(0x00000000,uint32_t))  /* FLOW: STOP - Stop */
-#define ENUM_DMA_CFG_AUTO                    (_ADI_MSK(0x00001000,uint32_t))  /* FLOW: AUTO - Autobuffer */
-#define ENUM_DMA_CFG_DSCLIST                 (_ADI_MSK(0x00004000,uint32_t))  /* FLOW: DSCL - Descriptor List */
-#define ENUM_DMA_CFG_DSCARRAY                (_ADI_MSK(0x00005000,uint32_t))  /* FLOW: DSCA - Descriptor Array */
-#define ENUM_DMA_CFG_DODLIST                 (_ADI_MSK(0x00006000,uint32_t))  /* FLOW: Descriptor On Demand List */
-#define ENUM_DMA_CFG_DODARRAY                (_ADI_MSK(0x00007000,uint32_t))  /* FLOW: Descriptor On Demand Array */
-
-#define BITM_DMA_CFG_MSIZE                   (_ADI_MSK(0x00000700,uint32_t))  /* Memory Transfer Word Size */
-#define ENUM_DMA_CFG_MSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* MSIZE: 1 Byte */
-#define ENUM_DMA_CFG_MSIZE02                 (_ADI_MSK(0x00000100,uint32_t))  /* MSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_MSIZE04                 (_ADI_MSK(0x00000200,uint32_t))  /* MSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_MSIZE08                 (_ADI_MSK(0x00000300,uint32_t))  /* MSIZE: 8 Bytes */
-#define ENUM_DMA_CFG_MSIZE16                 (_ADI_MSK(0x00000400,uint32_t))  /* MSIZE: 16 Bytes */
-#define ENUM_DMA_CFG_MSIZE32                 (_ADI_MSK(0x00000500,uint32_t))  /* MSIZE: 32 Bytes */
-
-#define BITM_DMA_CFG_PSIZE                   (_ADI_MSK(0x00000070,uint32_t))  /* Peripheral Transfer Word Size */
-#define ENUM_DMA_CFG_PSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 Byte */
-#define ENUM_DMA_CFG_PSIZE02                 (_ADI_MSK(0x00000010,uint32_t))  /* PSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_PSIZE04                 (_ADI_MSK(0x00000020,uint32_t))  /* PSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_PSIZE08                 (_ADI_MSK(0x00000030,uint32_t))  /* PSIZE: 8 Bytes */
-
-#define BITM_DMA_CFG_CADDR                   (_ADI_MSK(0x00000008,uint32_t))  /* Use Current Address */
-#define ENUM_DMA_CFG_LD_STARTADDR            (_ADI_MSK(0x00000000,uint32_t))  /* CADDR: Load Starting Address */
-#define ENUM_DMA_CFG_LD_CURADDR              (_ADI_MSK(0x00000008,uint32_t))  /* CADDR: Use Current Address */
-
-#define BITM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* Synchronize Work Unit Transitions */
-#define ENUM_DMA_CFG_NO_SYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* SYNC: No Synchronization */
-#define ENUM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* SYNC: Synchronize  Channel */
-
-#define BITM_DMA_CFG_WNR                     (_ADI_MSK(0x00000002,uint32_t))  /* Write/Read Channel Direction */
-#define ENUM_DMA_CFG_READ                    (_ADI_MSK(0x00000000,uint32_t))  /* WNR: Transmit (Read from memory) */
-#define ENUM_DMA_CFG_WRITE                   (_ADI_MSK(0x00000002,uint32_t))  /* WNR: Receive (Write to memory) */
-
-#define BITM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* DMA Channel Enable */
-#define ENUM_DMA_CFG_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_DSCPTR_PRV                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_DSCPTR_PRV_DESCPPREV         2                               /* Pointer for Previous Descriptor Element */
-#define BITP_DMA_DSCPTR_PRV_PDPO              0                               /* Previous Descriptor Pointer Overrun */
-#define BITM_DMA_DSCPTR_PRV_DESCPPREV        (_ADI_MSK(0xFFFFFFFC,uint32_t))  /* Pointer for Previous Descriptor Element */
-#define BITM_DMA_DSCPTR_PRV_PDPO             (_ADI_MSK(0x00000001,uint32_t))  /* Previous Descriptor Pointer Overrun */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_STAT_TWAIT                  20                               /* Trigger Wait Status */
-#define BITP_DMA_STAT_FIFOFILL               16                               /* FIFO Fill Status */
-#define BITP_DMA_STAT_MBWID                  14                               /* Memory Bus Width */
-#define BITP_DMA_STAT_PBWID                  12                               /* Peripheral Bus Width */
-#define BITP_DMA_STAT_RUN                     8                               /* Run Status */
-#define BITP_DMA_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_DMA_STAT_PIRQ                    2                               /* Peripheral Interrupt Request */
-#define BITP_DMA_STAT_IRQERR                  1                               /* Error Interrupt */
-#define BITP_DMA_STAT_IRQDONE                 0                               /* Work Unit/Row Done Interrupt */
-
-#define BITM_DMA_STAT_TWAIT                  (_ADI_MSK(0x00100000,uint32_t))  /* Trigger Wait Status */
-#define ENUM_DMA_STAT_NOTRIGRX               (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: No trigger received */
-#define ENUM_DMA_STAT_TRIGRX                 (_ADI_MSK(0x00100000,uint32_t))  /* TWAIT: Trigger received */
-
-#define BITM_DMA_STAT_FIFOFILL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Fill Status */
-#define ENUM_DMA_STAT_FIFOEMPTY              (_ADI_MSK(0x00000000,uint32_t))  /* FIFOFILL: Empty */
-#define ENUM_DMA_STAT_FIFO25                 (_ADI_MSK(0x00010000,uint32_t))  /* FIFOFILL: Empty < FIFO = 1/4 Full */
-#define ENUM_DMA_STAT_FIFO50                 (_ADI_MSK(0x00020000,uint32_t))  /* FIFOFILL: 1/4 Full < FIFO = 1/2 Full */
-#define ENUM_DMA_STAT_FIFO75                 (_ADI_MSK(0x00030000,uint32_t))  /* FIFOFILL: 1/2 Full < FIFO = 3/4 Full */
-#define ENUM_DMA_STAT_FIFONEARFULL           (_ADI_MSK(0x00040000,uint32_t))  /* FIFOFILL: 3/4 Full < FIFO = Full */
-#define ENUM_DMA_STAT_FIFOFULL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFOFILL: Full */
-
-#define BITM_DMA_STAT_MBWID                  (_ADI_MSK(0x0000C000,uint32_t))  /* Memory Bus Width */
-#define ENUM_DMA_STAT_MBUS02                 (_ADI_MSK(0x00000000,uint32_t))  /* MBWID: 2 Bytes */
-#define ENUM_DMA_STAT_MBUS04                 (_ADI_MSK(0x00004000,uint32_t))  /* MBWID: 4 Bytes */
-#define ENUM_DMA_STAT_MBUS08                 (_ADI_MSK(0x00008000,uint32_t))  /* MBWID: 8 Bytes */
-#define ENUM_DMA_STAT_MBUS16                 (_ADI_MSK(0x0000C000,uint32_t))  /* MBWID: 16 Bytes */
-
-#define BITM_DMA_STAT_PBWID                  (_ADI_MSK(0x00003000,uint32_t))  /* Peripheral Bus Width */
-#define ENUM_DMA_STAT_PBUS01                 (_ADI_MSK(0x00000000,uint32_t))  /* PBWID: 1 Byte */
-#define ENUM_DMA_STAT_PBUS02                 (_ADI_MSK(0x00001000,uint32_t))  /* PBWID: 2 Bytes */
-#define ENUM_DMA_STAT_PBUS04                 (_ADI_MSK(0x00002000,uint32_t))  /* PBWID: 4 Bytes */
-#define ENUM_DMA_STAT_PBUS08                 (_ADI_MSK(0x00003000,uint32_t))  /* PBWID: 8 Bytes */
-
-#define BITM_DMA_STAT_RUN                    (_ADI_MSK(0x00000700,uint32_t))  /* Run Status */
-#define ENUM_DMA_STAT_STOPPED                (_ADI_MSK(0x00000000,uint32_t))  /* RUN: Idle/Stop State */
-#define ENUM_DMA_STAT_DSCFETCH               (_ADI_MSK(0x00000100,uint32_t))  /* RUN: Descriptor Fetch */
-#define ENUM_DMA_STAT_DATAXFER               (_ADI_MSK(0x00000200,uint32_t))  /* RUN: Data Transfer */
-#define ENUM_DMA_STAT_TRGWAIT                (_ADI_MSK(0x00000300,uint32_t))  /* RUN: Waiting for Trigger */
-#define ENUM_DMA_STAT_ACKWAIT                (_ADI_MSK(0x00000400,uint32_t))  /* RUN: Waiting for Write ACK/FIFO Drain to Peripheral */
-
-#define BITM_DMA_STAT_ERRC                   (_ADI_MSK(0x00000070,uint32_t))  /* Error Cause */
-#define ENUM_DMA_STAT_CFGERR                 (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Configuration Error */
-#define ENUM_DMA_STAT_ILLWRERR               (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Illegal Write Occurred While Channel Running */
-#define ENUM_DMA_STAT_ALGNERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: Address Alignment Error */
-#define ENUM_DMA_STAT_MEMERR                 (_ADI_MSK(0x00000030,uint32_t))  /* ERRC: Memory Access/Fabric Error */
-#define ENUM_DMA_STAT_TRGOVERR               (_ADI_MSK(0x00000050,uint32_t))  /* ERRC: Trigger Overrun */
-#define ENUM_DMA_STAT_BWMONERR               (_ADI_MSK(0x00000060,uint32_t))  /* ERRC: Bandwidth Monitor Error */
-
-#define BITM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* Peripheral Interrupt Request */
-#define ENUM_DMA_STAT_NO_PIRQ                (_ADI_MSK(0x00000000,uint32_t))  /* PIRQ: No Interrupt */
-#define ENUM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* PIRQ: Interrupt Signaled by Peripheral */
-
-#define BITM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Interrupt */
-#define ENUM_DMA_STAT_NO_IRQERR              (_ADI_MSK(0x00000000,uint32_t))  /* IRQERR: No Error */
-#define ENUM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* IRQERR: Error Occurred */
-
-#define BITM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* Work Unit/Row Done Interrupt */
-#define ENUM_DMA_STAT_NO_IRQ                 (_ADI_MSK(0x00000000,uint32_t))  /* IRQDONE: Inactive */
-#define ENUM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* IRQDONE: Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_VALUE                 0                               /* Bandwidth Limit Count */
-#define BITM_DMA_BWLCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT_CUR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_CUR_VALUE             0                               /* Bandwidth Limit Count Current */
-#define BITM_DMA_BWLCNT_CUR_VALUE            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count Current */
-
-/* ==================================================
-        ACM Registers
-   ================================================== */
-
-/* =========================
-        ACM0
-   ========================= */
-#define REG_ACM0_CTL                    0xFFC45000         /* ACM0 ACM Control Register */
-#define REG_ACM0_TC0                    0xFFC45004         /* ACM0 ACM Timing Configuration 0 Register */
-#define REG_ACM0_TC1                    0xFFC45008         /* ACM0 ACM Timing Configuration 1 Register */
-#define REG_ACM0_STAT                   0xFFC4500C         /* ACM0 ACM Status Register */
-#define REG_ACM0_EVSTAT                 0xFFC45010         /* ACM0 ACM Event Status Register */
-#define REG_ACM0_EVMSK                  0xFFC45014         /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define REG_ACM0_MEVSTAT                0xFFC45018         /* ACM0 ACM Missed Event Status Register */
-#define REG_ACM0_MEVMSK                 0xFFC4501C         /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define REG_ACM0_EVCTL0                 0xFFC45020         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL1                 0xFFC45024         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL2                 0xFFC45028         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL3                 0xFFC4502C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL4                 0xFFC45030         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL5                 0xFFC45034         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL6                 0xFFC45038         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL7                 0xFFC4503C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL8                 0xFFC45040         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL9                 0xFFC45044         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL10                0xFFC45048         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL11                0xFFC4504C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL12                0xFFC45050         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL13                0xFFC45054         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL14                0xFFC45058         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL15                0xFFC4505C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVTIME0                0xFFC45060         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME1                0xFFC45064         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME2                0xFFC45068         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME3                0xFFC4506C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME4                0xFFC45070         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME5                0xFFC45074         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME6                0xFFC45078         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME7                0xFFC4507C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME8                0xFFC45080         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME9                0xFFC45084         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME10               0xFFC45088         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME11               0xFFC4508C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME12               0xFFC45090         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME13               0xFFC45094         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME14               0xFFC45098         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME15               0xFFC4509C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVORD0                 0xFFC450A0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD1                 0xFFC450A4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD2                 0xFFC450A8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD3                 0xFFC450AC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD4                 0xFFC450B0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD5                 0xFFC450B4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD6                 0xFFC450B8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD7                 0xFFC450BC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD8                 0xFFC450C0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD9                 0xFFC450C4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD10                0xFFC450C8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD11                0xFFC450CC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD12                0xFFC450D0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD13                0xFFC450D4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD14                0xFFC450D8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD15                0xFFC450DC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_TMR0                   0xFFC450E8         /* ACM0 ACM Timer 0 Register */
-#define REG_ACM0_TMR1                   0xFFC450EC         /* ACM0 ACM Timer 1 Register */
-
-/* =========================
-        ACM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_CTL_EPS                     15                               /* External Peripheral Select */
-#define BITP_ACM_CTL_OTSEL                   14                               /* Trigger Select for Order Register Reset */
-#define BITP_ACM_CTL_AOREN                   13                               /* Automatic Order Reset Enable */
-#define BITP_ACM_CTL_ORST                    12                               /* Order Register Reset Bit */
-#define BITP_ACM_CTL_CLKMOD                  11                               /* ADC Clock Mode */
-#define BITP_ACM_CTL_CLKPOL                  10                               /* ADC_CLK Polarity */
-#define BITP_ACM_CTL_CSPOL                    9                               /* CS Polarity */
-#define BITP_ACM_CTL_TRGPOL1                  8                               /* Trigger Polarity for Timer1 Triggers */
-#define BITP_ACM_CTL_TRGPOL0                  7                               /* Trigger Polarity for Timer0 Triggers */
-#define BITP_ACM_CTL_TRGSEL1                  5                               /* Trigger Select 1 */
-#define BITP_ACM_CTL_TRGSEL0                  3                               /* Trigger Select 0 */
-#define BITP_ACM_CTL_TMR1EN                   2                               /* Enable ACM Timer1 */
-#define BITP_ACM_CTL_TMR0EN                   1                               /* Enable ACM Timer0 */
-#define BITP_ACM_CTL_EN                       0                               /* ACM Enable */
-#define BITM_ACM_CTL_EPS                     (_ADI_MSK(0x00008000,uint32_t))  /* External Peripheral Select */
-#define BITM_ACM_CTL_OTSEL                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Select for Order Register Reset */
-#define BITM_ACM_CTL_AOREN                   (_ADI_MSK(0x00002000,uint32_t))  /* Automatic Order Reset Enable */
-#define BITM_ACM_CTL_ORST                    (_ADI_MSK(0x00001000,uint32_t))  /* Order Register Reset Bit */
-#define BITM_ACM_CTL_CLKMOD                  (_ADI_MSK(0x00000800,uint32_t))  /* ADC Clock Mode */
-#define BITM_ACM_CTL_CLKPOL                  (_ADI_MSK(0x00000400,uint32_t))  /* ADC_CLK Polarity */
-#define BITM_ACM_CTL_CSPOL                   (_ADI_MSK(0x00000200,uint32_t))  /* CS Polarity */
-#define BITM_ACM_CTL_TRGPOL1                 (_ADI_MSK(0x00000100,uint32_t))  /* Trigger Polarity for Timer1 Triggers */
-#define BITM_ACM_CTL_TRGPOL0                 (_ADI_MSK(0x00000080,uint32_t))  /* Trigger Polarity for Timer0 Triggers */
-#define BITM_ACM_CTL_TRGSEL1                 (_ADI_MSK(0x00000060,uint32_t))  /* Trigger Select 1 */
-#define BITM_ACM_CTL_TRGSEL0                 (_ADI_MSK(0x00000018,uint32_t))  /* Trigger Select 0 */
-#define BITM_ACM_CTL_TMR1EN                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable ACM Timer1 */
-#define BITM_ACM_CTL_TMR0EN                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable ACM Timer0 */
-#define BITM_ACM_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* ACM Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC0_SC                      16                               /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITP_ACM_TC0_CKDIV                    0                               /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-#define BITM_ACM_TC0_SC                      (_ADI_MSK(0x0FFF0000,uint32_t))  /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITM_ACM_TC0_CKDIV                   (_ADI_MSK(0x000000FF,uint32_t))  /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC1_ZC                      12                               /* Zero Cycle - ADC Control zero duration */
-#define BITP_ACM_TC1_HC                       8                               /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITP_ACM_TC1_CSW                      0                               /* CS Width. Active duration of CS in ACLK cycles */
-#define BITM_ACM_TC1_ZC                      (_ADI_MSK(0x0000F000,uint32_t))  /* Zero Cycle - ADC Control zero duration */
-#define BITM_ACM_TC1_HC                      (_ADI_MSK(0x00000F00,uint32_t))  /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITM_ACM_TC1_CSW                     (_ADI_MSK(0x000000FF,uint32_t))  /* CS Width. Active duration of CS in ACLK cycles */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_STAT_CEVNT                   4                               /* Current Event. */
-#define BITP_ACM_STAT_ECOM1                   3                               /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_ECOM0                   2                               /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_EMISS                   1                               /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITP_ACM_STAT_BSY                     0                               /* ACM Busy */
-#define BITM_ACM_STAT_CEVNT                  (_ADI_MSK(0x000000F0,uint32_t))  /* Current Event. */
-#define BITM_ACM_STAT_ECOM1                  (_ADI_MSK(0x00000008,uint32_t))  /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_ECOM0                  (_ADI_MSK(0x00000004,uint32_t))  /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_EMISS                  (_ADI_MSK(0x00000002,uint32_t))  /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITM_ACM_STAT_BSY                    (_ADI_MSK(0x00000001,uint32_t))  /* ACM Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVSTAT_ECOM1S               17                               /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_ECOM0S               16                               /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_EV15                 15                               /* Event15 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV14                 14                               /* Event14 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV13                 13                               /* Event13 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV12                 12                               /* Event12 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV11                 11                               /* Event11 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV10                 10                               /* Event10 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV9                   9                               /* Event9 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV8                   8                               /* Event8 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV7                   7                               /* Event7 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV6                   6                               /* Event6 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV5                   5                               /* Event5 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV4                   4                               /* Event4 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV3                   3                               /* Event3 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV2                   2                               /* Event2 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV1                   1                               /* Event1 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV0                   0                               /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-#define BITM_ACM_EVSTAT_ECOM1S               (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_ECOM0S               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVMSK_IECOM1                17                               /* Timer1 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_IECOM0                16                               /* Timer0 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV15                  15                               /* Event15 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV14                  14                               /* Event14 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV13                  13                               /* Event13 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV12                  12                               /* Event12 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV11                  11                               /* Event11 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV10                  10                               /* Event10 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV9                    9                               /* Event9 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV8                    8                               /* Event8 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV7                    7                               /* Event7 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV6                    6                               /* Event6 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV5                    5                               /* Event5 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV4                    4                               /* Event4 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV3                    3                               /* Event3 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV2                    2                               /* Event2 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV1                    1                               /* Event1 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV0                    0                               /* Event0 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM1                (_ADI_MSK(0x00020000,uint32_t))  /* Timer1 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM0                (_ADI_MSK(0x00010000,uint32_t))  /* Timer0 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV15                  (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV14                  (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV13                  (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV12                  (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV11                  (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV10                  (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV9                   (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV8                   (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV7                   (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV6                   (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV5                   (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV4                   (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV3                   (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV2                   (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV1                   (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV0                   (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVSTAT_EV15                15                               /* Event15 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV14                14                               /* Event14 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV13                13                               /* Event13 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV12                12                               /* Event12 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV11                11                               /* Event11 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV10                10                               /* Event10 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV9                  9                               /* Event9 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV8                  8                               /* Event8 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV7                  7                               /* Event7 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV6                  6                               /* Event6 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV5                  5                               /* Event5 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV4                  4                               /* Event4 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV3                  3                               /* Event3 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV2                  2                               /* Event2 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV1                  1                               /* Event1 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV0                  0                               /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-#define BITM_ACM_MEVSTAT_EV15                (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV14                (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV13                (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV12                (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV11                (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV10                (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV9                 (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV8                 (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV7                 (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV6                 (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV5                 (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV4                 (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV3                 (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV2                 (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV1                 (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV0                 (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVMSK                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVMSK_EV15                 15                               /* Event15 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV14                 14                               /* Event14 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV13                 13                               /* Event13 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV12                 12                               /* Event12 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV11                 11                               /* Event11 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV10                 10                               /* Event10 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV9                   9                               /* Event9 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV8                   8                               /* Event8 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV7                   7                               /* Event7 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV6                   6                               /* Event6 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV5                   5                               /* Event5 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV4                   4                               /* Event4 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV3                   3                               /* Event3 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV2                   2                               /* Event2 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV1                   1                               /* Event1 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV0                   0                               /* Event0 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVCTL_EPF                    1                               /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITP_ACM_EVCTL_ENAEV                  0                               /* Enable Event */
-#define BITM_ACM_EVCTL_EPF                   (_ADI_MSK(0x0000003E,uint32_t))  /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITM_ACM_EVCTL_ENAEV                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Event */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVORD                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVORD_EVSTAT                17                               /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITP_ACM_EVORD_MEVSTAT               16                               /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITP_ACM_EVORD_ORD                    0                               /* Order of Event Completion */
-#define BITM_ACM_EVORD_EVSTAT                (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITM_ACM_EVORD_MEVSTAT               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITM_ACM_EVORD_ORD                   (_ADI_MSK(0x000000FF,uint32_t))  /* Order of Event Completion */
-
-/* ==================================================
-        DDR Registers
-   ================================================== */
-
-/* =========================
-        DMC0
-   ========================= */
-#define REG_DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
-#define REG_DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
-#define REG_DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Control Register */
-#define REG_DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
-#define REG_DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask Register */
-#define REG_DMC0_CFG                    0xFFC80040         /* DMC0 Configuration Register */
-#define REG_DMC0_TR0                    0xFFC80044         /* DMC0 Timing 0 Register */
-#define REG_DMC0_TR1                    0xFFC80048         /* DMC0 Timing 1 Register */
-#define REG_DMC0_TR2                    0xFFC8004C         /* DMC0 Timing 2 Register */
-#define REG_DMC0_MSK                    0xFFC8005C         /* DMC0 Mask (Mode Register Shadow) Register */
-#define REG_DMC0_MR                     0xFFC80060         /* DMC0 Shadow MR Register */
-#define REG_DMC0_EMR1                   0xFFC80064         /* DMC0 Shadow EMR1 Register */
-#define REG_DMC0_EMR2                   0xFFC80068         /* DMC0 Shadow EMR2 Register */
-#define REG_DMC0_EMR3                   0xFFC8006C         /* DMC0 Shadow EMR3 Register */
-#define REG_DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
-#define REG_DMC0_PHY_CTL0               0xFFC80090         /* DMC0 PHY Control 0 Register */
-#define REG_DMC0_PHY_CTL1               0xFFC80094         /* DMC0 PHY Control 1 Register */
-#define REG_DMC0_PHY_CTL2               0xFFC80098         /* DMC0 PHY Control 2 Register */
-#define REG_DMC0_PHY_CTL3               0xFFC8009C         /* DMC0 PHY Control 3 Register */
-#define REG_DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register */
-
-/* =========================
-        DMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CTL_DLLCAL                  13                               /* DLL Calibration Start */
-#define BITP_DMC_CTL_PPREF                   12                               /* Postpone Refresh */
-#define BITP_DMC_CTL_RDTOWR                   9                               /* Read-to-Write Cycle */
-#define BITP_DMC_CTL_ADDRMODE                 8                               /* Addressing (Page/Bank) Mode */
-#define BITP_DMC_CTL_PREC                     6                               /* Precharge */
-#define BITP_DMC_CTL_DPDREQ                   5                               /* Deep Power Down Request */
-#define BITP_DMC_CTL_PDREQ                    4                               /* Power Down Request */
-#define BITP_DMC_CTL_SRREQ                    3                               /* Self Refresh Request */
-#define BITP_DMC_CTL_INIT                     2                               /* Initialize DRAM Start */
-#define BITP_DMC_CTL_LPDDR                    1                               /* Low Power DDR Mode */
-#define BITM_DMC_CTL_DLLCAL                  (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Start */
-#define BITM_DMC_CTL_PPREF                   (_ADI_MSK(0x00001000,uint32_t))  /* Postpone Refresh */
-
-#define BITM_DMC_CTL_RDTOWR                  (_ADI_MSK(0x00000E00,uint32_t))  /* Read-to-Write Cycle */
-#define ENUM_DMC_CTL_RDTOWR0                 (_ADI_MSK(0x00000000,uint32_t))  /* RDTOWR: 0 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR1                 (_ADI_MSK(0x00000200,uint32_t))  /* RDTOWR: 1 Cycle Added */
-#define ENUM_DMC_CTL_RDTOWR2                 (_ADI_MSK(0x00000400,uint32_t))  /* RDTOWR: 2 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR3                 (_ADI_MSK(0x00000600,uint32_t))  /* RDTOWR: 3 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR4                 (_ADI_MSK(0x00000800,uint32_t))  /* RDTOWR: 4 Cycles Added */
-#define BITM_DMC_CTL_ADDRMODE                (_ADI_MSK(0x00000100,uint32_t))  /* Addressing (Page/Bank) Mode */
-#define BITM_DMC_CTL_PREC                    (_ADI_MSK(0x00000040,uint32_t))  /* Precharge */
-#define BITM_DMC_CTL_DPDREQ                  (_ADI_MSK(0x00000020,uint32_t))  /* Deep Power Down Request */
-#define BITM_DMC_CTL_PDREQ                   (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Request */
-#define BITM_DMC_CTL_SRREQ                   (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Request */
-#define BITM_DMC_CTL_INIT                    (_ADI_MSK(0x00000004,uint32_t))  /* Initialize DRAM Start */
-#define BITM_DMC_CTL_LPDDR                   (_ADI_MSK(0x00000002,uint32_t))  /* Low Power DDR Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_STAT_PHYRDPHASE             20                               /* PHY Read Phase */
-#define BITP_DMC_STAT_PENDREF                16                               /* Pending Refresh */
-#define BITP_DMC_STAT_DLLCALDONE             13                               /* DLL Calibration Done */
-#define BITP_DMC_STAT_DPDACK                  5                               /* Deep Powerdown Acknowledge */
-#define BITP_DMC_STAT_PDACK                   4                               /* Power Down Acknowledge */
-#define BITP_DMC_STAT_SRACK                   3                               /* Self Refresh Acknowledge */
-#define BITP_DMC_STAT_MEMINITDONE             1                               /* Memory Initialization Done */
-#define BITP_DMC_STAT_IDLE                    0                               /* Idle State */
-#define BITM_DMC_STAT_PHYRDPHASE             (_ADI_MSK(0x00F00000,uint32_t))  /* PHY Read Phase */
-#define BITM_DMC_STAT_PENDREF                (_ADI_MSK(0x000F0000,uint32_t))  /* Pending Refresh */
-#define BITM_DMC_STAT_DLLCALDONE             (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Done */
-#define BITM_DMC_STAT_DPDACK                 (_ADI_MSK(0x00000020,uint32_t))  /* Deep Powerdown Acknowledge */
-#define BITM_DMC_STAT_PDACK                  (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Acknowledge */
-#define BITM_DMC_STAT_SRACK                  (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Acknowledge */
-#define BITM_DMC_STAT_MEMINITDONE            (_ADI_MSK(0x00000002,uint32_t))  /* Memory Initialization Done */
-#define BITM_DMC_STAT_IDLE                   (_ADI_MSK(0x00000001,uint32_t))  /* Idle State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EFFCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EFFCTL_IDLECYC              20                               /* Idle Cycle */
-#define BITP_DMC_EFFCTL_NUMREF               16                               /* Number of Refresh Commands */
-#define BITP_DMC_EFFCTL_PRECBANK7            15                               /* Precharge Bank 7 */
-#define BITP_DMC_EFFCTL_PRECBANK6            14                               /* Precharge Bank 6 */
-#define BITP_DMC_EFFCTL_PRECBANK5            13                               /* Precharge Bank 5 */
-#define BITP_DMC_EFFCTL_PRECBANK4            12                               /* Precharge Bank 4 */
-#define BITP_DMC_EFFCTL_PRECBANK3            11                               /* Precharge Bank 3 */
-#define BITP_DMC_EFFCTL_PRECBANK2            10                               /* Precharge Bank 2 */
-#define BITP_DMC_EFFCTL_PRECBANK1             9                               /* Precharge Bank 1 */
-#define BITP_DMC_EFFCTL_PRECBANK0             8                               /* Precharge Bank 0 */
-#define BITP_DMC_EFFCTL_WAITWRDATA            7                               /* Wait in Write Data Snapshot */
-#define BITP_DMC_EFFCTL_FULLWRDATA            6                               /* Wait for Full Write Data */
-#define BITM_DMC_EFFCTL_IDLECYC              (_ADI_MSK(0x00F00000,uint32_t))  /* Idle Cycle */
-#define BITM_DMC_EFFCTL_NUMREF               (_ADI_MSK(0x000F0000,uint32_t))  /* Number of Refresh Commands */
-#define BITM_DMC_EFFCTL_PRECBANK7            (_ADI_MSK(0x00008000,uint32_t))  /* Precharge Bank 7 */
-#define BITM_DMC_EFFCTL_PRECBANK6            (_ADI_MSK(0x00004000,uint32_t))  /* Precharge Bank 6 */
-#define BITM_DMC_EFFCTL_PRECBANK5            (_ADI_MSK(0x00002000,uint32_t))  /* Precharge Bank 5 */
-#define BITM_DMC_EFFCTL_PRECBANK4            (_ADI_MSK(0x00001000,uint32_t))  /* Precharge Bank 4 */
-#define BITM_DMC_EFFCTL_PRECBANK3            (_ADI_MSK(0x00000800,uint32_t))  /* Precharge Bank 3 */
-#define BITM_DMC_EFFCTL_PRECBANK2            (_ADI_MSK(0x00000400,uint32_t))  /* Precharge Bank 2 */
-#define BITM_DMC_EFFCTL_PRECBANK1            (_ADI_MSK(0x00000200,uint32_t))  /* Precharge Bank 1 */
-#define BITM_DMC_EFFCTL_PRECBANK0            (_ADI_MSK(0x00000100,uint32_t))  /* Precharge Bank 0 */
-#define BITM_DMC_EFFCTL_WAITWRDATA           (_ADI_MSK(0x00000080,uint32_t))  /* Wait in Write Data Snapshot */
-#define BITM_DMC_EFFCTL_FULLWRDATA           (_ADI_MSK(0x00000040,uint32_t))  /* Wait for Full Write Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIO                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIO_ID2                    16                               /* ID2 Requiring Elevated Priority */
-#define BITP_DMC_PRIO_ID1                     0                               /* ID1 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID2                    (_ADI_MSK(0xFFFF0000,uint32_t))  /* ID2 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID1                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* ID1 Requiring Elevated Priority */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIOMSK                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIOMSK_ID2MSK              16                               /* Mask for ID2 */
-#define BITP_DMC_PRIOMSK_ID1MSK               0                               /* Mask for ID1 */
-#define BITM_DMC_PRIOMSK_ID2MSK              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Mask for ID2 */
-#define BITM_DMC_PRIOMSK_ID1MSK              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Mask for ID1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CFG_EXTBANK                 12                               /* External Banks */
-#define BITP_DMC_CFG_SDRSIZE                  8                               /* SDRAM Size */
-#define BITP_DMC_CFG_SDRWID                   4                               /* SDRAM Width */
-#define BITP_DMC_CFG_IFWID                    0                               /* Interface Width */
-
-#define BITM_DMC_CFG_EXTBANK                 (_ADI_MSK(0x0000F000,uint32_t))  /* External Banks */
-#define ENUM_DMC_CFG_EXTBANK1                (_ADI_MSK(0x00000000,uint32_t))  /* EXTBANK: 1 External Bank */
-
-#define BITM_DMC_CFG_SDRSIZE                 (_ADI_MSK(0x00000F00,uint32_t))  /* SDRAM Size */
-#define ENUM_DMC_CFG_SDRSIZE64               (_ADI_MSK(0x00000000,uint32_t))  /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE128              (_ADI_MSK(0x00000100,uint32_t))  /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE256              (_ADI_MSK(0x00000200,uint32_t))  /* SDRSIZE: 256M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE512              (_ADI_MSK(0x00000300,uint32_t))  /* SDRSIZE: 512M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE1G               (_ADI_MSK(0x00000400,uint32_t))  /* SDRSIZE: 1G Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE2G               (_ADI_MSK(0x00000500,uint32_t))  /* SDRSIZE: 2G Bit SDRAM */
-
-#define BITM_DMC_CFG_SDRWID                  (_ADI_MSK(0x000000F0,uint32_t))  /* SDRAM Width */
-#define ENUM_DMC_CFG_SDRWID16                (_ADI_MSK(0x00000020,uint32_t))  /* SDRWID: 16-Bit Wide SDRAM */
-
-#define BITM_DMC_CFG_IFWID                   (_ADI_MSK(0x0000000F,uint32_t))  /* Interface Width */
-#define ENUM_DMC_CFG_IFWID16                 (_ADI_MSK(0x00000002,uint32_t))  /* IFWID: 16-Bit Wide Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR0_TMRD                    28                               /* Timing Mode Register Delay */
-#define BITP_DMC_TR0_TRC                     20                               /* Timing Row Cycle */
-#define BITP_DMC_TR0_TRAS                    12                               /* Timing Row Active Time */
-#define BITP_DMC_TR0_TRP                      8                               /* Timing RAS Precharge. */
-#define BITP_DMC_TR0_TWTR                     4                               /* Timing Write to Read */
-#define BITP_DMC_TR0_TRCD                     0                               /* Timing RAS to CAS Delay */
-#define BITM_DMC_TR0_TMRD                    (_ADI_MSK(0xF0000000,uint32_t))  /* Timing Mode Register Delay */
-#define BITM_DMC_TR0_TRC                     (_ADI_MSK(0x03F00000,uint32_t))  /* Timing Row Cycle */
-#define BITM_DMC_TR0_TRAS                    (_ADI_MSK(0x0001F000,uint32_t))  /* Timing Row Active Time */
-#define BITM_DMC_TR0_TRP                     (_ADI_MSK(0x00000F00,uint32_t))  /* Timing RAS Precharge. */
-#define BITM_DMC_TR0_TWTR                    (_ADI_MSK(0x000000F0,uint32_t))  /* Timing Write to Read */
-#define BITM_DMC_TR0_TRCD                    (_ADI_MSK(0x0000000F,uint32_t))  /* Timing RAS to CAS Delay */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR1_TRRD                    28                               /* Timing Read-Read Delay */
-#define BITP_DMC_TR1_TRFC                    16                               /* Timing Refresh-to-Command */
-#define BITP_DMC_TR1_TREF                     0                               /* Timing Refresh Interval */
-#define BITM_DMC_TR1_TRRD                    (_ADI_MSK(0x70000000,uint32_t))  /* Timing Read-Read Delay */
-#define BITM_DMC_TR1_TRFC                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Timing Refresh-to-Command */
-#define BITM_DMC_TR1_TREF                    (_ADI_MSK(0x00003FFF,uint32_t))  /* Timing Refresh Interval */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR2_TCKE                    20                               /* Timing Clock Enable */
-#define BITP_DMC_TR2_TXP                     16                               /* Timing Exit Powerdown */
-#define BITP_DMC_TR2_TWR                     12                               /* Timing Write Recovery */
-#define BITP_DMC_TR2_TRTP                     8                               /* Timing Read-to-Precharge */
-#define BITP_DMC_TR2_TFAW                     0                               /* Timing Four-Activated-Window */
-#define BITM_DMC_TR2_TCKE                    (_ADI_MSK(0x00F00000,uint32_t))  /* Timing Clock Enable */
-#define BITM_DMC_TR2_TXP                     (_ADI_MSK(0x000F0000,uint32_t))  /* Timing Exit Powerdown */
-#define BITM_DMC_TR2_TWR                     (_ADI_MSK(0x0000F000,uint32_t))  /* Timing Write Recovery */
-#define BITM_DMC_TR2_TRTP                    (_ADI_MSK(0x00000F00,uint32_t))  /* Timing Read-to-Precharge */
-#define BITM_DMC_TR2_TFAW                    (_ADI_MSK(0x0000001F,uint32_t))  /* Timing Four-Activated-Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MSK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MSK_EMR3                    11                               /* Shadow EMR3 Unmask */
-#define BITP_DMC_MSK_EMR2                    10                               /* Shadow EMR2 Unmask */
-#define BITP_DMC_MSK_EMR1                     9                               /* Shadow EMR1 Unmask */
-#define BITP_DMC_MSK_MR                       8                               /* Shadow MR Unmask */
-#define BITM_DMC_MSK_EMR3                    (_ADI_MSK(0x00000800,uint32_t))  /* Shadow EMR3 Unmask */
-#define BITM_DMC_MSK_EMR2                    (_ADI_MSK(0x00000400,uint32_t))  /* Shadow EMR2 Unmask */
-#define BITM_DMC_MSK_EMR1                    (_ADI_MSK(0x00000200,uint32_t))  /* Shadow EMR1 Unmask */
-#define BITM_DMC_MSK_MR                      (_ADI_MSK(0x00000100,uint32_t))  /* Shadow MR Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MR                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MR_PD                       12                               /* Active Powerdown Mode */
-#define BITP_DMC_MR_WRRECOV                   9                               /* Write Recovery */
-#define BITP_DMC_MR_DLLRST                    8                               /* DLL Reset */
-#define BITP_DMC_MR_CL                        4                               /* CAS Latency */
-#define BITP_DMC_MR_BLEN                      0                               /* Burst Length */
-#define BITM_DMC_MR_PD                       (_ADI_MSK(0x00001000,uint32_t))  /* Active Powerdown Mode */
-#define BITM_DMC_MR_WRRECOV                  (_ADI_MSK(0x00000E00,uint32_t))  /* Write Recovery */
-#define BITM_DMC_MR_DLLRST                   (_ADI_MSK(0x00000100,uint32_t))  /* DLL Reset */
-
-#define BITM_DMC_MR_CL                       (_ADI_MSK(0x00000070,uint32_t))  /* CAS Latency */
-#define ENUM_DMC_MR_CL2                      (_ADI_MSK(0x00000020,uint32_t))  /* CL: 2 clock cycle latency */
-#define ENUM_DMC_MR_CL3                      (_ADI_MSK(0x00000030,uint32_t))  /* CL: 3 clock cycle latency */
-#define ENUM_DMC_MR_CL4                      (_ADI_MSK(0x00000040,uint32_t))  /* CL: 4 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL5                      (_ADI_MSK(0x00000050,uint32_t))  /* CL: 5 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL6                      (_ADI_MSK(0x00000060,uint32_t))  /* CL: 6 clock cycle latency (DDR2) */
-
-#define BITM_DMC_MR_BLEN                     (_ADI_MSK(0x00000007,uint32_t))  /* Burst Length */
-#define ENUM_DMC_MR_BLEN4                    (_ADI_MSK(0x00000002,uint32_t))  /* BLEN: 4-Bit Burst Length */
-#define ENUM_DMC_MR_BLEN8                    (_ADI_MSK(0x00000003,uint32_t))  /* BLEN: 8-Bit Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR1_QOFF                   12                               /* Output Buffer Enable */
-#define BITP_DMC_EMR1_DQS                    10                               /* DQS Enable */
-#define BITP_DMC_EMR1_RTT1                    6                               /* Termination Resistance 1 */
-#define BITP_DMC_EMR1_AL                      3                               /* Additive Latency */
-#define BITP_DMC_EMR1_RTT0                    2                               /* Termination Resistance 0. */
-#define BITP_DMC_EMR1_DIC                     1                               /* Output Driver Impedance Control */
-#define BITP_DMC_EMR1_DLLEN                   0                               /* DLL Enable */
-#define BITM_DMC_EMR1_QOFF                   (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Enable */
-#define BITM_DMC_EMR1_DQS                    (_ADI_MSK(0x00000400,uint32_t))  /* DQS Enable */
-
-#define BITM_DMC_EMR1_RTT1                   (_ADI_MSK(0x00000040,uint32_t))  /* Termination Resistance 1 */
-#define ENUM_DMC_EMR1_RTT1_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT1: Disable RTT1 */
-#define ENUM_DMC_EMR1_RTT1_1                 (_ADI_MSK(0x00000040,uint32_t))  /* RTT1: Enable RTT1 */
-#define BITM_DMC_EMR1_AL                     (_ADI_MSK(0x00000038,uint32_t))  /* Additive Latency */
-
-#define BITM_DMC_EMR1_RTT0                   (_ADI_MSK(0x00000004,uint32_t))  /* Termination Resistance 0. */
-#define ENUM_DMC_EMR1_RTT0_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT0: Disable RTT0 */
-#define ENUM_DMC_EMR1_RTT0_1                 (_ADI_MSK(0x00000004,uint32_t))  /* RTT0: Enable RTT0 */
-#define BITM_DMC_EMR1_DIC                    (_ADI_MSK(0x00000002,uint32_t))  /* Output Driver Impedance Control */
-#define BITM_DMC_EMR1_DLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* DLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR2_SRF                     7                               /* High Temp. Self Refresh */
-#define BITP_DMC_EMR2_DS                      5                               /* Drive Strength */
-#define BITP_DMC_EMR2_TCSR                    3                               /* Temp. Comp. Self Refresh */
-#define BITP_DMC_EMR2_PASR                    0                               /* Partial Array Self Refresh */
-#define BITM_DMC_EMR2_SRF                    (_ADI_MSK(0x00000080,uint32_t))  /* High Temp. Self Refresh */
-#define BITM_DMC_EMR2_DS                     (_ADI_MSK(0x00000060,uint32_t))  /* Drive Strength */
-#define BITM_DMC_EMR2_TCSR                   (_ADI_MSK(0x00000018,uint32_t))  /* Temp. Comp. Self Refresh */
-#define BITM_DMC_EMR2_PASR                   (_ADI_MSK(0x00000007,uint32_t))  /* Partial Array Self Refresh */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_DLLCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_DLLCTL_DATACYC               8                               /* Data Cycles */
-#define BITP_DMC_DLLCTL_DLLCALRDCNT           0                               /* DLL Calibration RD Count */
-
-#define BITM_DMC_DLLCTL_DATACYC              (_ADI_MSK(0x00000F00,uint32_t))  /* Data Cycles */
-#define ENUM_DMC_DLLCTL_DATACYC2             (_ADI_MSK(0x00000200,uint32_t))  /* DATACYC: 2 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC3             (_ADI_MSK(0x00000300,uint32_t))  /* DATACYC: 3 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC4             (_ADI_MSK(0x00000400,uint32_t))  /* DATACYC: 4 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC5             (_ADI_MSK(0x00000500,uint32_t))  /* DATACYC: 5 Clock Cycles Latency */
-#define BITM_DMC_DLLCTL_DLLCALRDCNT          (_ADI_MSK(0x000000FF,uint32_t))  /* DLL Calibration RD Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL1                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL1_CONTODTVAL         19                               /* Select ODT value on controller */
-
-#define BITM_DMC_PHY_CTL1_CONTODTVAL         (_ADI_MSK(0x00080000,uint32_t))  /* Select ODT value on controller */
-#define ENUM_DMC_PHY_CTL1_ODT_75             (_ADI_MSK(0x00000000,uint32_t))  /* CONTODTVAL: 75 Ohms Termination */
-#define ENUM_DMC_PHY_CTL1_ODT_150            (_ADI_MSK(0x00080000,uint32_t))  /* CONTODTVAL: 150 Ohms Termination */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL3                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL3_OFST1              26                               /* Offset Parameter 1 */
-#define BITP_DMC_PHY_CTL3_OFST0              24                               /* Offset Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQS           10                               /* Enables controller ODT on read of DQS */
-#define BITP_DMC_PHY_CTL3_TMG1                7                               /* Timing Parameter 1 */
-#define BITP_DMC_PHY_CTL3_TMG0                6                               /* Timing Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQ             2                               /* Enables controller ODT on read of DQ */
-#define BITM_DMC_PHY_CTL3_OFST1              (_ADI_MSK(0x04000000,uint32_t))  /* Offset Parameter 1 */
-#define BITM_DMC_PHY_CTL3_OFST0              (_ADI_MSK(0x01000000,uint32_t))  /* Offset Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQS           (_ADI_MSK(0x00000400,uint32_t))  /* Enables controller ODT on read of DQS */
-#define BITM_DMC_PHY_CTL3_TMG1               (_ADI_MSK(0x00000080,uint32_t))  /* Timing Parameter 1 */
-#define BITM_DMC_PHY_CTL3_TMG0               (_ADI_MSK(0x00000040,uint32_t))  /* Timing Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQ            (_ADI_MSK(0x00000004,uint32_t))  /* Enables controller ODT on read of DQ */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PADCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PADCTL_CKEOE                19                               /* CKE Output Enable */
-#define BITP_DMC_PADCTL_CKEPWD               18                               /* CKE pad receiver power down. */
-#define BITP_DMC_PADCTL_CKEODS               16                               /* CKE Output Drive Strength */
-#define BITP_DMC_PADCTL_CMDOE                15                               /* CMD Output Enable */
-#define BITP_DMC_PADCTL_CMDPWD               14                               /* CMD Powerdown */
-#define BITP_DMC_PADCTL_CMDODS               12                               /* CMD Output Drive Strength */
-#define BITP_DMC_PADCTL_CLKOE                11                               /* CLK Output Enable */
-#define BITP_DMC_PADCTL_CLKPWD               10                               /* CLK Powerdown */
-#define BITP_DMC_PADCTL_CLKODS                8                               /* Clock Output Drive Strength */
-#define BITP_DMC_PADCTL_DQSPWD                6                               /* DQ/DQS Powerdown */
-#define BITP_DMC_PADCTL_DQSODS                4                               /* DQS Output Drive Strength */
-#define BITP_DMC_PADCTL_DQPWD                 2                               /* DQ Powerdown. */
-#define BITP_DMC_PADCTL_DQODS                 0                               /* DQ Output Drive Strength */
-#define BITM_DMC_PADCTL_CKEOE                (_ADI_MSK(0x00080000,uint32_t))  /* CKE Output Enable */
-#define BITM_DMC_PADCTL_CKEPWD               (_ADI_MSK(0x00040000,uint32_t))  /* CKE pad receiver power down. */
-#define BITM_DMC_PADCTL_CKEODS               (_ADI_MSK(0x00030000,uint32_t))  /* CKE Output Drive Strength */
-#define BITM_DMC_PADCTL_CMDOE                (_ADI_MSK(0x00008000,uint32_t))  /* CMD Output Enable */
-#define BITM_DMC_PADCTL_CMDPWD               (_ADI_MSK(0x00004000,uint32_t))  /* CMD Powerdown */
-#define BITM_DMC_PADCTL_CMDODS               (_ADI_MSK(0x00003000,uint32_t))  /* CMD Output Drive Strength */
-#define BITM_DMC_PADCTL_CLKOE                (_ADI_MSK(0x00000800,uint32_t))  /* CLK Output Enable */
-#define BITM_DMC_PADCTL_CLKPWD               (_ADI_MSK(0x00000400,uint32_t))  /* CLK Powerdown */
-#define BITM_DMC_PADCTL_CLKODS               (_ADI_MSK(0x00000300,uint32_t))  /* Clock Output Drive Strength */
-#define BITM_DMC_PADCTL_DQSPWD               (_ADI_MSK(0x00000040,uint32_t))  /* DQ/DQS Powerdown */
-#define BITM_DMC_PADCTL_DQSODS               (_ADI_MSK(0x00000030,uint32_t))  /* DQS Output Drive Strength */
-#define BITM_DMC_PADCTL_DQPWD                (_ADI_MSK(0x00000004,uint32_t))  /* DQ Powerdown. */
-#define BITM_DMC_PADCTL_DQODS                (_ADI_MSK(0x00000003,uint32_t))  /* DQ Output Drive Strength */
-
-/* ==================================================
-        System Cross Bar Registers
-   ================================================== */
-
-/* =========================
-        SCB0
-   ========================= */
-#define REG_SCB0_ARBR0                  0xFFCA2408         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR1                  0xFFCA2428         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR2                  0xFFCA2448         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR3                  0xFFCA2468         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR4                  0xFFCA2488         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR5                  0xFFCA24A8         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBW0                  0xFFCA240C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW1                  0xFFCA242C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW2                  0xFFCA244C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW3                  0xFFCA246C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW4                  0xFFCA248C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW5                  0xFFCA24AC         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_SLAVES                 0xFFCA2FC0         /* SCB0 Slave Interfaces Number Register */
-#define REG_SCB0_MASTERS                0xFFCA2FC4         /* SCB0 Master Interfaces Number Register */
-
-/* =========================
-        SCB1
-   ========================= */
-#define REG_SCB1_ARBR0                  0xFFC42408         /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB1_ARBW0                  0xFFC4240C         /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB1_SLAVES                 0xFFC42FC0         /* SCB1 Slave Interfaces Number Register */
-#define REG_SCB1_MASTERS                0xFFC42FC4         /* SCB1 Master Interfaces Number Register */
-
-/* =========================
-        SCB2
-   ========================= */
-#define REG_SCB2_ARBR0                  0xFFC06408         /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB2_ARBW0                  0xFFC0640C         /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB2_SLAVES                 0xFFC06FC0         /* SCB2 Slave Interfaces Number Register */
-#define REG_SCB2_MASTERS                0xFFC06FC4         /* SCB2 Master Interfaces Number Register */
-
-/* =========================
-        SCB3
-   ========================= */
-#define REG_SCB3_ARBR0                  0xFFC08408         /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB3_ARBW0                  0xFFC0840C         /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB3_SLAVES                 0xFFC08FC0         /* SCB3 Slave Interfaces Number Register */
-#define REG_SCB3_MASTERS                0xFFC08FC4         /* SCB3 Master Interfaces Number Register */
-
-/* =========================
-        SCB4
-   ========================= */
-#define REG_SCB4_ARBR0                  0xFFC0A408         /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB4_ARBW0                  0xFFC0A40C         /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB4_SLAVES                 0xFFC0AFC0         /* SCB4 Slave Interfaces Number Register */
-#define REG_SCB4_MASTERS                0xFFC0AFC4         /* SCB4 Master Interfaces Number Register */
-
-/* =========================
-        SCB5
-   ========================= */
-#define REG_SCB5_ARBR0                  0xFFC0C408         /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB5_ARBW0                  0xFFC0C40C         /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB5_SLAVES                 0xFFC0CFC0         /* SCB5 Slave Interfaces Number Register */
-#define REG_SCB5_MASTERS                0xFFC0CFC4         /* SCB5 Master Interfaces Number Register */
-
-/* =========================
-        SCB6
-   ========================= */
-#define REG_SCB6_ARBR0                  0xFFC0E408         /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB6_ARBW0                  0xFFC0E40C         /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB6_SLAVES                 0xFFC0EFC0         /* SCB6 Slave Interfaces Number Register */
-#define REG_SCB6_MASTERS                0xFFC0EFC4         /* SCB6 Master Interfaces Number Register */
-
-/* =========================
-        SCB7
-   ========================= */
-#define REG_SCB7_ARBR0                  0xFFC11408         /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB7_ARBW0                  0xFFC1140C         /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB7_SLAVES                 0xFFC11FC0         /* SCB7 Slave Interfaces Number Register */
-#define REG_SCB7_MASTERS                0xFFC11FC4         /* SCB7 Master Interfaces Number Register */
-
-/* =========================
-        SCB8
-   ========================= */
-#define REG_SCB8_ARBR0                  0xFFC13408         /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB8_ARBW0                  0xFFC1340C         /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB8_SLAVES                 0xFFC13FC0         /* SCB8 Slave Interfaces Number Register */
-#define REG_SCB8_MASTERS                0xFFC13FC4         /* SCB8 Master Interfaces Number Register */
-
-/* =========================
-        SCB9
-   ========================= */
-#define REG_SCB9_ARBR0                  0xFFC15408         /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB9_ARBW0                  0xFFC1540C         /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB9_SLAVES                 0xFFC15FC0         /* SCB9 Slave Interfaces Number Register */
-#define REG_SCB9_MASTERS                0xFFC15FC4         /* SCB9 Master Interfaces Number Register */
-
-/* =========================
-        SCB10
-   ========================= */
-#define REG_SCB10_ARBR0                 0xFFCA1408         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR1                 0xFFCA1428         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR2                 0xFFCA1448         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBW0                 0xFFCA140C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW1                 0xFFCA142C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW2                 0xFFCA144C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_SLAVES                0xFFCA1FC0         /* SCB10 Slave Interfaces Number Register */
-#define REG_SCB10_MASTERS               0xFFCA1FC4         /* SCB10 Master Interfaces Number Register */
-
-/* =========================
-        SCB11
-   ========================= */
-#define REG_SCB11_ARBR0                 0xFFCA0408         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR1                 0xFFCA0428         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR2                 0xFFCA0448         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR3                 0xFFCA0468         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR4                 0xFFCA0488         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR5                 0xFFCA04A8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR6                 0xFFCA04C8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBW0                 0xFFCA040C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW1                 0xFFCA042C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW2                 0xFFCA044C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW3                 0xFFCA046C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW4                 0xFFCA048C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW5                 0xFFCA04AC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW6                 0xFFCA04CC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_SLAVES                0xFFCA0FC0         /* SCB11 Slave Interfaces Number Register */
-#define REG_SCB11_MASTERS               0xFFCA0FC4         /* SCB11 Master Interfaces Number Register */
-
-/* =========================
-        SCB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBR_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBR_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBR_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBR_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBW                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBW_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBW_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBW_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBW_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_SLAVES                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_SLAVES_SI                    0                               /* Slave Interface Value */
-#define BITM_SCB_SLAVES_SI                   (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_MASTERS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_MASTERS_MI                   0                               /* Master Interface Value */
-#define BITM_SCB_MASTERS_MI                  (_ADI_MSK(0x000000FF,uint32_t))  /* Master Interface Value */
-
-/* ==================================================
-        L2 Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        L2CTL0
-   ========================= */
-#define REG_L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 Control Register */
-#define REG_L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 Access Control Core 0 Register */
-#define REG_L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 Access Control Core 1 Register */
-#define REG_L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 Access Control System Register */
-#define REG_L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 Status Register */
-#define REG_L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 Read Priority Count Register */
-#define REG_L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 Write Priority Count Register */
-#define REG_L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 Refresh Address Register */
-#define REG_L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 ECC Error Address 0 Register */
-#define REG_L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 ECC Error Address 1 Register */
-#define REG_L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 ECC Error Address 2 Register */
-#define REG_L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 ECC Error Address 3 Register */
-#define REG_L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 ECC Error Address 4 Register */
-#define REG_L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 ECC Error Address 5 Register */
-#define REG_L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 ECC Error Address 6 Register */
-#define REG_L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 ECC Error Address 7 Register */
-#define REG_L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 Error Type 0 Register */
-#define REG_L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 Error Type 0 Address Register */
-#define REG_L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 Error Type 1 Register */
-#define REG_L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 Error Type 1 Address Register */
-
-/* =========================
-        L2CTL
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_CTL_LOCK                  31                               /* Lock */
-#define BITP_L2CTL_CTL_DISURP                16                               /* Disable Urgent Request Priority */
-#define BITP_L2CTL_CTL_ECCMAP7               15                               /* ECC Map Bank 7 */
-#define BITP_L2CTL_CTL_ECCMAP6               14                               /* ECC Map Bank 6 */
-#define BITP_L2CTL_CTL_ECCMAP5               13                               /* ECC Map Bank 5 */
-#define BITP_L2CTL_CTL_ECCMAP4               12                               /* ECC Map Bank 4 */
-#define BITP_L2CTL_CTL_ECCMAP3               11                               /* ECC Map Bank 3 */
-#define BITP_L2CTL_CTL_ECCMAP2               10                               /* ECC Map Bank 2 */
-#define BITP_L2CTL_CTL_ECCMAP1                9                               /* ECC Map Bank 1 */
-#define BITP_L2CTL_CTL_ECCMAP0                8                               /* ECC Map Bank 0 */
-#define BITP_L2CTL_CTL_BK7EDIS                7                               /* Bank 7 ECC Disable */
-#define BITP_L2CTL_CTL_BK6EDIS                6                               /* Bank 6 ECC Disable */
-#define BITP_L2CTL_CTL_BK5EDIS                5                               /* Bank 5 ECC Disable */
-#define BITP_L2CTL_CTL_BK4EDIS                4                               /* Bank 4 ECC Disable */
-#define BITP_L2CTL_CTL_BK3EDIS                3                               /* Bank 3 ECC Disable */
-#define BITP_L2CTL_CTL_BK2EDIS                2                               /* Bank 2 ECC Disable */
-#define BITP_L2CTL_CTL_BK1EDIS                1                               /* Bank 1 ECC Disable */
-#define BITP_L2CTL_CTL_BK0EDIS                0                               /* Bank 0 ECC Disable */
-#define BITM_L2CTL_CTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_CTL_DISURP                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Urgent Request Priority */
-#define BITM_L2CTL_CTL_ECCMAP7               (_ADI_MSK(0x00008000,uint32_t))  /* ECC Map Bank 7 */
-#define BITM_L2CTL_CTL_ECCMAP6               (_ADI_MSK(0x00004000,uint32_t))  /* ECC Map Bank 6 */
-#define BITM_L2CTL_CTL_ECCMAP5               (_ADI_MSK(0x00002000,uint32_t))  /* ECC Map Bank 5 */
-#define BITM_L2CTL_CTL_ECCMAP4               (_ADI_MSK(0x00001000,uint32_t))  /* ECC Map Bank 4 */
-#define BITM_L2CTL_CTL_ECCMAP3               (_ADI_MSK(0x00000800,uint32_t))  /* ECC Map Bank 3 */
-#define BITM_L2CTL_CTL_ECCMAP2               (_ADI_MSK(0x00000400,uint32_t))  /* ECC Map Bank 2 */
-#define BITM_L2CTL_CTL_ECCMAP1               (_ADI_MSK(0x00000200,uint32_t))  /* ECC Map Bank 1 */
-#define BITM_L2CTL_CTL_ECCMAP0               (_ADI_MSK(0x00000100,uint32_t))  /* ECC Map Bank 0 */
-#define BITM_L2CTL_CTL_BK7EDIS               (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 ECC Disable */
-#define BITM_L2CTL_CTL_BK6EDIS               (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 ECC Disable */
-#define BITM_L2CTL_CTL_BK5EDIS               (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 ECC Disable */
-#define BITM_L2CTL_CTL_BK4EDIS               (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 ECC Disable */
-#define BITM_L2CTL_CTL_BK3EDIS               (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 ECC Disable */
-#define BITM_L2CTL_CTL_BK2EDIS               (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 ECC Disable */
-#define BITM_L2CTL_CTL_BK1EDIS               (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 ECC Disable */
-#define BITM_L2CTL_CTL_BK0EDIS               (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 ECC Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C0_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C0_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C0_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C0_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C1_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C1_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C1_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C1_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_SYS                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_SYS_LOCK             31                               /* Lock */
-#define BITP_L2CTL_ACTL_SYS_BK7WDIS           7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK6WDIS           6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK5WDIS           5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK4WDIS           4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK3WDIS           3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK2WDIS           2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK1WDIS           1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK0WDIS           0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_LOCK             (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_SYS_BK7WDIS          (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK6WDIS          (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK5WDIS          (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK4WDIS          (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK3WDIS          (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK2WDIS          (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK1WDIS          (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK0WDIS          (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_STAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_STAT_ECCERR7              15                               /* ECC Error Bank 7 */
-#define BITP_L2CTL_STAT_ECCERR6              14                               /* ECC Error Bank 6 */
-#define BITP_L2CTL_STAT_ECCERR5              13                               /* ECC Error Bank 5 */
-#define BITP_L2CTL_STAT_ECCERR4              12                               /* ECC Error Bank 4 */
-#define BITP_L2CTL_STAT_ECCERR3              11                               /* ECC Error Bank 3 */
-#define BITP_L2CTL_STAT_ECCERR2              10                               /* ECC Error Bank 2 */
-#define BITP_L2CTL_STAT_ECCERR1               9                               /* ECC Error Bank 1 */
-#define BITP_L2CTL_STAT_ECCERR0               8                               /* ECC Error Bank 0 */
-#define BITP_L2CTL_STAT_RFRS                  4                               /* Refresh Register Status */
-#define BITP_L2CTL_STAT_ERR1                  1                               /* Error Port 1 */
-#define BITP_L2CTL_STAT_ERR0                  0                               /* Error Port 0 */
-#define BITM_L2CTL_STAT_ECCERR7              (_ADI_MSK(0x00008000,uint32_t))  /* ECC Error Bank 7 */
-#define BITM_L2CTL_STAT_ECCERR6              (_ADI_MSK(0x00004000,uint32_t))  /* ECC Error Bank 6 */
-#define BITM_L2CTL_STAT_ECCERR5              (_ADI_MSK(0x00002000,uint32_t))  /* ECC Error Bank 5 */
-#define BITM_L2CTL_STAT_ECCERR4              (_ADI_MSK(0x00001000,uint32_t))  /* ECC Error Bank 4 */
-#define BITM_L2CTL_STAT_ECCERR3              (_ADI_MSK(0x00000800,uint32_t))  /* ECC Error Bank 3 */
-#define BITM_L2CTL_STAT_ECCERR2              (_ADI_MSK(0x00000400,uint32_t))  /* ECC Error Bank 2 */
-#define BITM_L2CTL_STAT_ECCERR1              (_ADI_MSK(0x00000200,uint32_t))  /* ECC Error Bank 1 */
-#define BITM_L2CTL_STAT_ECCERR0              (_ADI_MSK(0x00000100,uint32_t))  /* ECC Error Bank 0 */
-#define BITM_L2CTL_STAT_RFRS                 (_ADI_MSK(0x00000010,uint32_t))  /* Refresh Register Status */
-#define BITM_L2CTL_STAT_ERR1                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Port 1 */
-#define BITM_L2CTL_STAT_ERR0                 (_ADI_MSK(0x00000001,uint32_t))  /* Error Port 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RPCR_RPC1                  8                               /* Read Priority Count 1 */
-#define BITP_L2CTL_RPCR_RPC0                  0                               /* Read Priority Count 0 */
-#define BITM_L2CTL_RPCR_RPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Read Priority Count 1 */
-#define BITM_L2CTL_RPCR_RPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Read Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_WPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_WPCR_WPC1                  8                               /* Write Priority Count 1 */
-#define BITP_L2CTL_WPCR_WPC0                  0                               /* Write Priority Count 0 */
-#define BITM_L2CTL_WPCR_WPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Write Priority Count 1 */
-#define BITM_L2CTL_WPCR_WPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Write Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RFA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RFA_ADDRHI                16                               /* Address High */
-#define BITP_L2CTL_RFA_ADDRLO                 0                               /* Address Low */
-#define BITM_L2CTL_RFA_ADDRHI                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Address High */
-#define BITM_L2CTL_RFA_ADDRLO                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address Low */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET0_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET0_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET0_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET0_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET0_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET0_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET0_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET0_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET0_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET0_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET0_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET0_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET1_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET1_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET1_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET1_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET1_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET1_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET1_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET1_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET1_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET1_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET1_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET1_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ==================================================
-        System Event Controller Registers
-   ================================================== */
-
-/* =========================
-        SEC0
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Core Interface (SCI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_CCTL0                  0xFFCA4400         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CCTL1                  0xFFCA4440         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CSTAT0                 0xFFCA4404         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CSTAT1                 0xFFCA4444         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CPND0                  0xFFCA4408         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CPND1                  0xFFCA4448         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CACT0                  0xFFCA440C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CACT1                  0xFFCA444C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CPMSK0                 0xFFCA4410         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CPMSK1                 0xFFCA4450         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CGMSK0                 0xFFCA4414         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CGMSK1                 0xFFCA4454         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CPLVL0                 0xFFCA4418         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CPLVL1                 0xFFCA4458         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CSID0                  0xFFCA441C         /* SEC0 SCI Source ID Register n */
-#define REG_SEC0_CSID1                  0xFFCA445C         /* SEC0 SCI Source ID Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Fault Management Interface (SFI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_FCTL                   0xFFCA4010         /* SEC0 Fault Control Register */
-#define REG_SEC0_FSTAT                  0xFFCA4014         /* SEC0 Fault Status Register */
-#define REG_SEC0_FSID                   0xFFCA4018         /* SEC0 Fault Source ID Register */
-#define REG_SEC0_FEND                   0xFFCA401C         /* SEC0 Fault End Register */
-#define REG_SEC0_FDLY                   0xFFCA4020         /* SEC0 Fault Delay Register */
-#define REG_SEC0_FDLY_CUR               0xFFCA4024         /* SEC0 Fault Delay Current Register */
-#define REG_SEC0_FSRDLY                 0xFFCA4028         /* SEC0 Fault System Reset Delay Register */
-#define REG_SEC0_FSRDLY_CUR             0xFFCA402C         /* SEC0 Fault System Reset Delay Current Register */
-#define REG_SEC0_FCOPP                  0xFFCA4030         /* SEC0 Fault COP Period Register */
-#define REG_SEC0_FCOPP_CUR              0xFFCA4034         /* SEC0 Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Global Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_GCTL                   0xFFCA4000         /* SEC0 Global Control Register */
-#define REG_SEC0_GSTAT                  0xFFCA4004         /* SEC0 Global Status Register */
-#define REG_SEC0_RAISE                  0xFFCA4008         /* SEC0 Global Raise Register */
-#define REG_SEC0_END                    0xFFCA400C         /* SEC0 Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Source Interface (SSI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_SCTL0                  0xFFCA4800         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL1                  0xFFCA4808         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL2                  0xFFCA4810         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL3                  0xFFCA4818         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL4                  0xFFCA4820         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL5                  0xFFCA4828         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL6                  0xFFCA4830         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL7                  0xFFCA4838         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL8                  0xFFCA4840         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL9                  0xFFCA4848         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL10                 0xFFCA4850         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL11                 0xFFCA4858         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL12                 0xFFCA4860         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL13                 0xFFCA4868         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL14                 0xFFCA4870         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL15                 0xFFCA4878         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL16                 0xFFCA4880         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL17                 0xFFCA4888         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL18                 0xFFCA4890         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL19                 0xFFCA4898         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL20                 0xFFCA48A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL21                 0xFFCA48A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL22                 0xFFCA48B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL23                 0xFFCA48B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL24                 0xFFCA48C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL25                 0xFFCA48C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL26                 0xFFCA48D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL27                 0xFFCA48D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL28                 0xFFCA48E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL29                 0xFFCA48E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL30                 0xFFCA48F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL31                 0xFFCA48F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL32                 0xFFCA4900         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL33                 0xFFCA4908         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL34                 0xFFCA4910         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL35                 0xFFCA4918         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL36                 0xFFCA4920         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL37                 0xFFCA4928         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL38                 0xFFCA4930         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL39                 0xFFCA4938         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL40                 0xFFCA4940         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL41                 0xFFCA4948         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL42                 0xFFCA4950         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL43                 0xFFCA4958         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL44                 0xFFCA4960         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL45                 0xFFCA4968         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL46                 0xFFCA4970         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL47                 0xFFCA4978         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL48                 0xFFCA4980         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL49                 0xFFCA4988         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL50                 0xFFCA4990         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL51                 0xFFCA4998         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL52                 0xFFCA49A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL53                 0xFFCA49A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL54                 0xFFCA49B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL55                 0xFFCA49B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL56                 0xFFCA49C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL57                 0xFFCA49C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL58                 0xFFCA49D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL59                 0xFFCA49D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL60                 0xFFCA49E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL61                 0xFFCA49E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL62                 0xFFCA49F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL63                 0xFFCA49F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL64                 0xFFCA4A00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL65                 0xFFCA4A08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL66                 0xFFCA4A10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL67                 0xFFCA4A18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL68                 0xFFCA4A20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL69                 0xFFCA4A28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL70                 0xFFCA4A30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL71                 0xFFCA4A38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL72                 0xFFCA4A40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL73                 0xFFCA4A48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL74                 0xFFCA4A50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL75                 0xFFCA4A58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL76                 0xFFCA4A60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL77                 0xFFCA4A68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL78                 0xFFCA4A70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL79                 0xFFCA4A78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL80                 0xFFCA4A80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL81                 0xFFCA4A88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL82                 0xFFCA4A90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL83                 0xFFCA4A98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL84                 0xFFCA4AA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL85                 0xFFCA4AA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL86                 0xFFCA4AB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL87                 0xFFCA4AB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL88                 0xFFCA4AC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL89                 0xFFCA4AC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL90                 0xFFCA4AD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL91                 0xFFCA4AD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL92                 0xFFCA4AE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL93                 0xFFCA4AE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL94                 0xFFCA4AF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL95                 0xFFCA4AF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL96                 0xFFCA4B00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL97                 0xFFCA4B08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL98                 0xFFCA4B10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL99                 0xFFCA4B18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL100                0xFFCA4B20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL101                0xFFCA4B28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL102                0xFFCA4B30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL103                0xFFCA4B38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL104                0xFFCA4B40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL105                0xFFCA4B48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL106                0xFFCA4B50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL107                0xFFCA4B58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL108                0xFFCA4B60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL109                0xFFCA4B68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL110                0xFFCA4B70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL111                0xFFCA4B78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL112                0xFFCA4B80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL113                0xFFCA4B88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL114                0xFFCA4B90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL115                0xFFCA4B98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL116                0xFFCA4BA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL117                0xFFCA4BA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL118                0xFFCA4BB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL119                0xFFCA4BB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL120                0xFFCA4BC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL121                0xFFCA4BC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL122                0xFFCA4BD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL123                0xFFCA4BD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL124                0xFFCA4BE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL125                0xFFCA4BE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL126                0xFFCA4BF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL127                0xFFCA4BF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL128                0xFFCA4C00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL129                0xFFCA4C08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL130                0xFFCA4C10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL131                0xFFCA4C18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL132                0xFFCA4C20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL133                0xFFCA4C28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL134                0xFFCA4C30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL135                0xFFCA4C38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL136                0xFFCA4C40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL137                0xFFCA4C48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL138                0xFFCA4C50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL139                0xFFCA4C58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SSTAT0                 0xFFCA4804         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT1                 0xFFCA480C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT2                 0xFFCA4814         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT3                 0xFFCA481C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT4                 0xFFCA4824         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT5                 0xFFCA482C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT6                 0xFFCA4834         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT7                 0xFFCA483C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT8                 0xFFCA4844         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT9                 0xFFCA484C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT10                0xFFCA4854         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT11                0xFFCA485C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT12                0xFFCA4864         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT13                0xFFCA486C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT14                0xFFCA4874         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT15                0xFFCA487C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT16                0xFFCA4884         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT17                0xFFCA488C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT18                0xFFCA4894         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT19                0xFFCA489C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT20                0xFFCA48A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT21                0xFFCA48AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT22                0xFFCA48B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT23                0xFFCA48BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT24                0xFFCA48C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT25                0xFFCA48CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT26                0xFFCA48D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT27                0xFFCA48DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT28                0xFFCA48E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT29                0xFFCA48EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT30                0xFFCA48F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT31                0xFFCA48FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT32                0xFFCA4904         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT33                0xFFCA490C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT34                0xFFCA4914         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT35                0xFFCA491C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT36                0xFFCA4924         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT37                0xFFCA492C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT38                0xFFCA4934         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT39                0xFFCA493C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT40                0xFFCA4944         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT41                0xFFCA494C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT42                0xFFCA4954         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT43                0xFFCA495C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT44                0xFFCA4964         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT45                0xFFCA496C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT46                0xFFCA4974         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT47                0xFFCA497C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT48                0xFFCA4984         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT49                0xFFCA498C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT50                0xFFCA4994         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT51                0xFFCA499C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT52                0xFFCA49A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT53                0xFFCA49AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT54                0xFFCA49B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT55                0xFFCA49BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT56                0xFFCA49C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT57                0xFFCA49CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT58                0xFFCA49D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT59                0xFFCA49DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT60                0xFFCA49E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT61                0xFFCA49EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT62                0xFFCA49F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT63                0xFFCA49FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT64                0xFFCA4A04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT65                0xFFCA4A0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT66                0xFFCA4A14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT67                0xFFCA4A1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT68                0xFFCA4A24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT69                0xFFCA4A2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT70                0xFFCA4A34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT71                0xFFCA4A3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT72                0xFFCA4A44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT73                0xFFCA4A4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT74                0xFFCA4A54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT75                0xFFCA4A5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT76                0xFFCA4A64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT77                0xFFCA4A6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT78                0xFFCA4A74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT79                0xFFCA4A7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT80                0xFFCA4A84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT81                0xFFCA4A8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT82                0xFFCA4A94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT83                0xFFCA4A9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT84                0xFFCA4AA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT85                0xFFCA4AAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT86                0xFFCA4AB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT87                0xFFCA4ABC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT88                0xFFCA4AC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT89                0xFFCA4ACC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT90                0xFFCA4AD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT91                0xFFCA4ADC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT92                0xFFCA4AE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT93                0xFFCA4AEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT94                0xFFCA4AF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT95                0xFFCA4AFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT96                0xFFCA4B04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT97                0xFFCA4B0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT98                0xFFCA4B14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT99                0xFFCA4B1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT100               0xFFCA4B24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT101               0xFFCA4B2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT102               0xFFCA4B34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT103               0xFFCA4B3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT104               0xFFCA4B44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT105               0xFFCA4B4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT106               0xFFCA4B54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT107               0xFFCA4B5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT108               0xFFCA4B64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT109               0xFFCA4B6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT110               0xFFCA4B74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT111               0xFFCA4B7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT112               0xFFCA4B84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT113               0xFFCA4B8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT114               0xFFCA4B94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT115               0xFFCA4B9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT116               0xFFCA4BA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT117               0xFFCA4BAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT118               0xFFCA4BB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT119               0xFFCA4BBC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT120               0xFFCA4BC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT121               0xFFCA4BCC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT122               0xFFCA4BD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT123               0xFFCA4BDC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT124               0xFFCA4BE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT125               0xFFCA4BEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT126               0xFFCA4BF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT127               0xFFCA4BFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT128               0xFFCA4C04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT129               0xFFCA4C0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT130               0xFFCA4C14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT131               0xFFCA4C1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT132               0xFFCA4C24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT133               0xFFCA4C2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT134               0xFFCA4C34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT135               0xFFCA4C3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT136               0xFFCA4C44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT137               0xFFCA4C4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT138               0xFFCA4C54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT139               0xFFCA4C5C         /* SEC0 Source Status Register n */
-
-/* =========================
-        SEC
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_CCTL_NMIEN                  16                               /* NMI Enable */
-#define BITP_SEC_CCTL_WFI                    12                               /* Wait For Idle */
-#define BITP_SEC_CCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_CCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CCTL_NMIEN                  (_ADI_MSK(0x00010000,uint32_t))  /* NMI Enable */
-#define ENUM_SEC_CCTL_NMI_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* NMIEN: Disable */
-#define ENUM_SEC_CCTL_NMI_EN                 (_ADI_MSK(0x00010000,uint32_t))  /* NMIEN: Enable */
-
-#define BITM_SEC_CCTL_WFI                    (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CCTL_NO_WAITIDLE            (_ADI_MSK(0x00000000,uint32_t))  /* WFI: No Action */
-#define ENUM_SEC_CCTL_WAITIDLE               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Wait for Idle */
-
-#define BITM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_CCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_CCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSTAT_NMI                   16                               /* NMI */
-#define BITP_SEC_CSTAT_WFI                   12                               /* Wait For Idle */
-#define BITP_SEC_CSTAT_SIDV                  10                               /* SID Valid */
-#define BITP_SEC_CSTAT_ACTV                   9                               /* ACT Valid */
-#define BITP_SEC_CSTAT_PNDV                   8                               /* PND Valid */
-#define BITP_SEC_CSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_CSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI */
-#define ENUM_SEC_CSTAT_NO_NMI                (_ADI_MSK(0x00000000,uint32_t))  /* NMI: No NMI Occured */
-#define ENUM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI: NMI Occurred */
-
-#define BITM_SEC_CSTAT_WFI                   (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CSTAT_NOT_WAITING           (_ADI_MSK(0x00000000,uint32_t))  /* WFI: Not Waiting */
-#define ENUM_SEC_CSTAT_WAITING               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Waiting */
-
-#define BITM_SEC_CSTAT_SIDV                  (_ADI_MSK(0x00000400,uint32_t))  /* SID Valid */
-#define ENUM_SEC_CSTAT_INVALID_SID           (_ADI_MSK(0x00000000,uint32_t))  /* SIDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_SID             (_ADI_MSK(0x00000400,uint32_t))  /* SIDV: Valid */
-
-#define BITM_SEC_CSTAT_ACTV                  (_ADI_MSK(0x00000200,uint32_t))  /* ACT Valid */
-#define ENUM_SEC_CSTAT_INVALID_ACT           (_ADI_MSK(0x00000000,uint32_t))  /* ACTV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_ACT             (_ADI_MSK(0x00000200,uint32_t))  /* ACTV: Valid */
-
-#define BITM_SEC_CSTAT_PNDV                  (_ADI_MSK(0x00000100,uint32_t))  /* PND Valid */
-#define ENUM_SEC_CSTAT_INVALID_PND           (_ADI_MSK(0x00000000,uint32_t))  /* PNDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_PND             (_ADI_MSK(0x00000100,uint32_t))  /* PNDV: Valid */
-
-#define BITM_SEC_CSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_CSTAT_ACKERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Acknowledge Error */
-
-#define BITM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_CSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPND_PRIO                    8                               /* Highest Pending IRQ Priority */
-#define BITP_SEC_CPND_SID                     0                               /* Highest Pending IRQ Source ID */
-#define BITM_SEC_CPND_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Pending IRQ Priority */
-#define BITM_SEC_CPND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CACT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CACT_PRIO                    8                               /* Highest Active IRQ Priority */
-#define BITP_SEC_CACT_SID                     0                               /* Highest Active IRQ Source ID */
-#define BITM_SEC_CACT_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Active IRQ Priority */
-#define BITM_SEC_CACT_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPMSK_PRIO                   0                               /* IRQ Priority Mask */
-
-#define BITM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPMSK_PRIO                  (_ADI_MSK(0x000000FF,uint32_t))  /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CGMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CGMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CGMSK_UGRP                   8                               /* Ungrouped Mask */
-#define BITP_SEC_CGMSK_GRP                    0                               /* Grouped Mask */
-
-#define BITM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CGMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CGMSK_UGRP                  (_ADI_MSK(0x00000100,uint32_t))  /* Ungrouped Mask */
-#define ENUM_SEC_CGMSK_UNMASK                (_ADI_MSK(0x00000000,uint32_t))  /* UGRP: Unmask Ungrouped Sources */
-#define ENUM_SEC_CGMSK_MASK                  (_ADI_MSK(0x00000100,uint32_t))  /* UGRP: Mask Ungrouped Sources */
-#define BITM_SEC_CGMSK_GRP                   (_ADI_MSK(0x0000000F,uint32_t))  /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPLVL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPLVL_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPLVL_PLVL                   0                               /* Priority Levels */
-
-#define BITM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPLVL_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPLVL_PLVL                  (_ADI_MSK(0x00000007,uint32_t))  /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSID_SID                     0                               /* Source ID */
-#define BITM_SEC_CSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_FCTL_TES                    13                               /* Trigger Event Select */
-#define BITP_SEC_FCTL_CMS                    12                               /* COP Mode Select */
-#define BITP_SEC_FCTL_FIEN                    7                               /* Fault Input Enable */
-#define BITP_SEC_FCTL_SREN                    6                               /* System Reset Enable */
-#define BITP_SEC_FCTL_TOEN                    5                               /* Trigger Output Enable */
-#define BITP_SEC_FCTL_FOEN                    4                               /* Fault Output Enable */
-#define BITP_SEC_FCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_FCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_FCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: UnLock */
-#define ENUM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_FCTL_TES                    (_ADI_MSK(0x00002000,uint32_t))  /* Trigger Event Select */
-#define ENUM_SEC_FCTL_FLTACT_MODE            (_ADI_MSK(0x00000000,uint32_t))  /* TES: Fault Active Mode */
-#define ENUM_SEC_FCTL_FLTPND_MODE            (_ADI_MSK(0x00002000,uint32_t))  /* TES: Fault Pending Mode */
-
-#define BITM_SEC_FCTL_CMS                    (_ADI_MSK(0x00001000,uint32_t))  /* COP Mode Select */
-#define ENUM_SEC_FCTL_FLT_MODE               (_ADI_MSK(0x00000000,uint32_t))  /* CMS: Fault Mode */
-#define ENUM_SEC_FCTL_COP_MODE               (_ADI_MSK(0x00001000,uint32_t))  /* CMS: COP Mode */
-
-#define BITM_SEC_FCTL_FIEN                   (_ADI_MSK(0x00000080,uint32_t))  /* Fault Input Enable */
-#define ENUM_SEC_FCTL_FLTIN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FIEN: Disable */
-#define ENUM_SEC_FCTL_FLTIN_EN               (_ADI_MSK(0x00000080,uint32_t))  /* FIEN: Enable */
-
-#define BITM_SEC_FCTL_SREN                   (_ADI_MSK(0x00000040,uint32_t))  /* System Reset Enable */
-#define ENUM_SEC_FCTL_SYSRST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SREN: Disable */
-#define ENUM_SEC_FCTL_SYSRST_EN              (_ADI_MSK(0x00000040,uint32_t))  /* SREN: Enable */
-
-#define BITM_SEC_FCTL_TOEN                   (_ADI_MSK(0x00000020,uint32_t))  /* Trigger Output Enable */
-#define ENUM_SEC_FCTL_TRGOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TOEN: Disable */
-#define ENUM_SEC_FCTL_TRGOUT_EN              (_ADI_MSK(0x00000020,uint32_t))  /* TOEN: Enable */
-
-#define BITM_SEC_FCTL_FOEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Fault Output Enable */
-#define ENUM_SEC_FCTL_FLTOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* FOEN: Disable */
-#define ENUM_SEC_FCTL_FLTOUT_EN              (_ADI_MSK(0x00000010,uint32_t))  /* FOEN: Enable */
-
-#define BITM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_FCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_FCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSTAT_NPND                  10                               /* Next Pending Fault */
-#define BITP_SEC_FSTAT_ACT                    9                               /* Fault Active */
-#define BITP_SEC_FSTAT_PND                    8                               /* Pending Fault */
-#define BITP_SEC_FSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_FSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_FSTAT_NPND                  (_ADI_MSK(0x00000400,uint32_t))  /* Next Pending Fault */
-#define ENUM_SEC_FSTAT_NO_NXTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* NPND: Not Pending */
-#define ENUM_SEC_FSTAT_NXTFLT                (_ADI_MSK(0x00000400,uint32_t))  /* NPND: Pending */
-
-#define BITM_SEC_FSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Fault Active */
-#define ENUM_SEC_FSTAT_NO_FLTACT             (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Fault */
-#define ENUM_SEC_FSTAT_FLTACT                (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Fault */
-
-#define BITM_SEC_FSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Fault */
-#define ENUM_SEC_FSTAT_NO_FLTPND             (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_FSTAT_FLTPND                (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_FSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_FSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_FSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSID_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FSID_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FSID_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FSID_SRC_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FSID_SRC_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FEND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FEND_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FEND_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FEND_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FEND_END_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FEND_END_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FEND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_GCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_GCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_GCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_GCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_GCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GSTAT_LWERR                 31                               /* Lock Write Error */
-#define BITP_SEC_GSTAT_ADRERR                30                               /* Address Error */
-#define BITP_SEC_GSTAT_SID                   16                               /* Source ID for SSI Error */
-#define BITP_SEC_GSTAT_SCI                    8                               /* SCI ID for SCI Error */
-#define BITP_SEC_GSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_GSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define ENUM_SEC_GSTAT_NO_LWERR              (_ADI_MSK(0x00000000,uint32_t))  /* LWERR: No Error */
-#define ENUM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* LWERR: Error Occurred */
-
-#define BITM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define ENUM_SEC_GSTAT_NO_ADRERR             (_ADI_MSK(0x00000000,uint32_t))  /* ADRERR: No Error */
-#define ENUM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* ADRERR: Error Occurred */
-#define BITM_SEC_GSTAT_SID                   (_ADI_MSK(0x00FF0000,uint32_t))  /* Source ID for SSI Error */
-#define BITM_SEC_GSTAT_SCI                   (_ADI_MSK(0x00000F00,uint32_t))  /* SCI ID for SCI Error */
-
-#define BITM_SEC_GSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_GSTAT_SFIERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: SFI Error */
-#define ENUM_SEC_GSTAT_SCIERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: SCI Error */
-#define ENUM_SEC_GSTAT_SSIERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: SSI Error */
-
-#define BITM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_GSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_RAISE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_RAISE_SID                    0                               /* Source ID IRQ Set to Pending */
-#define BITM_SEC_RAISE_SID                   (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_END                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_END_SID                      0                               /* Source ID IRQ to End */
-#define BITM_SEC_END_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_SCTL_CTG                    24                               /* Core Target Select */
-#define BITP_SEC_SCTL_GRP                    16                               /* Group Select */
-#define BITP_SEC_SCTL_PRIO                    8                               /* Priority Level Select */
-#define BITP_SEC_SCTL_ERREN                   4                               /* Error Enable */
-#define BITP_SEC_SCTL_ES                      3                               /* Edge Select */
-#define BITP_SEC_SCTL_SEN                     2                               /* Source (signal) Enable */
-#define BITP_SEC_SCTL_FEN                     1                               /* Fault Enable */
-#define BITP_SEC_SCTL_IEN                     0                               /* Interrupt Enable */
-
-#define BITM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_SCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_SCTL_CTG                    (_ADI_MSK(0x0F000000,uint32_t))  /* Core Target Select */
-#define BITM_SEC_SCTL_GRP                    (_ADI_MSK(0x000F0000,uint32_t))  /* Group Select */
-#define BITM_SEC_SCTL_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Priority Level Select */
-
-#define BITM_SEC_SCTL_ERREN                  (_ADI_MSK(0x00000010,uint32_t))  /* Error Enable */
-#define ENUM_SEC_SCTL_ERR_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* ERREN: Disable */
-#define ENUM_SEC_SCTL_ERR_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* ERREN: Enable */
-
-#define BITM_SEC_SCTL_ES                     (_ADI_MSK(0x00000008,uint32_t))  /* Edge Select */
-#define ENUM_SEC_SCTL_LEVEL                  (_ADI_MSK(0x00000000,uint32_t))  /* ES: Level Sensitive */
-#define ENUM_SEC_SCTL_EDGE                   (_ADI_MSK(0x00000008,uint32_t))  /* ES: Edge Sensitive */
-
-#define BITM_SEC_SCTL_SEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Source (signal) Enable */
-#define ENUM_SEC_SCTL_SRC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* SEN: Disable */
-#define ENUM_SEC_SCTL_SRC_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* SEN: Enable */
-
-#define BITM_SEC_SCTL_FEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Fault Enable */
-#define ENUM_SEC_SCTL_FAULT_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FEN: Disable */
-#define ENUM_SEC_SCTL_FAULT_EN               (_ADI_MSK(0x00000002,uint32_t))  /* FEN: Enable */
-
-#define BITM_SEC_SCTL_IEN                    (_ADI_MSK(0x00000001,uint32_t))  /* Interrupt Enable */
-#define ENUM_SEC_SCTL_INT_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* IEN: Disable */
-#define ENUM_SEC_SCTL_INT_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SSTAT_CHID                  16                               /* Channel ID */
-#define BITP_SEC_SSTAT_ACT                    9                               /* Active Source */
-#define BITP_SEC_SSTAT_PND                    8                               /* Pending Source */
-#define BITP_SEC_SSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_SSTAT_ERR                    1                               /* Error */
-#define BITM_SEC_SSTAT_CHID                  (_ADI_MSK(0x00FF0000,uint32_t))  /* Channel ID */
-
-#define BITM_SEC_SSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Active Source */
-#define ENUM_SEC_SSTAT_NO_SRC                (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Source */
-#define ENUM_SEC_SSTAT_ACTIVE_SRC            (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Source */
-
-#define BITM_SEC_SSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Source */
-#define ENUM_SEC_SSTAT_NOTPENDING            (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_SSTAT_PENDING               (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_SSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_SSTAT_SOVFERR               (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Source Overflow Error */
-#define ENUM_SEC_SSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_SSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ==================================================
-        Trigger Routing Unit Registers
-   ================================================== */
-
-/* =========================
-        TRU0
-   ========================= */
-#define REG_TRU0_SSR0                   0xFFCA5000         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR1                   0xFFCA5004         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR2                   0xFFCA5008         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR3                   0xFFCA500C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR4                   0xFFCA5010         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR5                   0xFFCA5014         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR6                   0xFFCA5018         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR7                   0xFFCA501C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR8                   0xFFCA5020         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR9                   0xFFCA5024         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR10                  0xFFCA5028         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR11                  0xFFCA502C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR12                  0xFFCA5030         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR13                  0xFFCA5034         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR14                  0xFFCA5038         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR15                  0xFFCA503C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR16                  0xFFCA5040         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR17                  0xFFCA5044         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR18                  0xFFCA5048         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR19                  0xFFCA504C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR20                  0xFFCA5050         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR21                  0xFFCA5054         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR22                  0xFFCA5058         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR23                  0xFFCA505C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR24                  0xFFCA5060         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR25                  0xFFCA5064         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR26                  0xFFCA5068         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR27                  0xFFCA506C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR28                  0xFFCA5070         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR29                  0xFFCA5074         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR30                  0xFFCA5078         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR31                  0xFFCA507C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR32                  0xFFCA5080         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR33                  0xFFCA5084         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR34                  0xFFCA5088         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR35                  0xFFCA508C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR36                  0xFFCA5090         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR37                  0xFFCA5094         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR38                  0xFFCA5098         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR39                  0xFFCA509C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR40                  0xFFCA50A0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR41                  0xFFCA50A4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR42                  0xFFCA50A8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR43                  0xFFCA50AC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR44                  0xFFCA50B0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR45                  0xFFCA50B4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR46                  0xFFCA50B8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR47                  0xFFCA50BC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR48                  0xFFCA50C0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR49                  0xFFCA50C4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR50                  0xFFCA50C8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR51                  0xFFCA50CC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR52                  0xFFCA50D0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR53                  0xFFCA50D4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR54                  0xFFCA50D8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR55                  0xFFCA50DC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR56                  0xFFCA50E0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR57                  0xFFCA50E4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR58                  0xFFCA50E8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR59                  0xFFCA50EC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR60                  0xFFCA50F0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR61                  0xFFCA50F4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR62                  0xFFCA50F8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR63                  0xFFCA50FC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR64                  0xFFCA5100         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR65                  0xFFCA5104         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR66                  0xFFCA5108         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR67                  0xFFCA510C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR68                  0xFFCA5110         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR69                  0xFFCA5114         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR70                  0xFFCA5118         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR71                  0xFFCA511C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR72                  0xFFCA5120         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR73                  0xFFCA5124         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR74                  0xFFCA5128         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR75                  0xFFCA512C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR76                  0xFFCA5130         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR77                  0xFFCA5134         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR78                  0xFFCA5138         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR79                  0xFFCA513C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR80                  0xFFCA5140         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR81                  0xFFCA5144         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR82                  0xFFCA5148         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR83                  0xFFCA514C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR84                  0xFFCA5150         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR85                  0xFFCA5154         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR86                  0xFFCA5158         /* TRU0 Slave Select Register */
-#define REG_TRU0_MTR                    0xFFCA57E0         /* TRU0 Master Trigger Register */
-#define REG_TRU0_ERRADDR                0xFFCA57E8         /* TRU0 Error Address Register */
-#define REG_TRU0_STAT                   0xFFCA57EC         /* TRU0 Status Information Register */
-#define REG_TRU0_REVID                  0xFFCA57F0         /* TRU0 Revision ID Register */
-#define REG_TRU0_GCTL                   0xFFCA57F4         /* TRU0 Global Control Register */
-
-/* =========================
-        TRU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_SSR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_SSR_LOCK                    31                               /* SSRn Lock */
-#define BITP_TRU_SSR_SSR                      0                               /* SSRn Slave Select */
-#define BITM_TRU_SSR_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* SSRn Lock */
-#define BITM_TRU_SSR_SSR                     (_ADI_MSK(0x000000FF,uint32_t))  /* SSRn Slave Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_MTR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_MTR_MTR3                    24                               /* Master Trigger Register 3 */
-#define BITP_TRU_MTR_MTR2                    16                               /* Master Trigger Register 2 */
-#define BITP_TRU_MTR_MTR1                     8                               /* Master Trigger Register 1 */
-#define BITP_TRU_MTR_MTR0                     0                               /* Master Trigger Register 0 */
-#define BITM_TRU_MTR_MTR3                    (_ADI_MSK(0xFF000000,uint32_t))  /* Master Trigger Register 3 */
-#define BITM_TRU_MTR_MTR2                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Master Trigger Register 2 */
-#define BITM_TRU_MTR_MTR1                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Master Trigger Register 1 */
-#define BITM_TRU_MTR_MTR0                    (_ADI_MSK(0x000000FF,uint32_t))  /* Master Trigger Register 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_ERRADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_ERRADDR_ADDR                 0                               /* Error Address */
-#define BITM_TRU_ERRADDR_ADDR                (_ADI_MSK(0x00000FFF,uint32_t))  /* Error Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_STAT_ADDRERR                 1                               /* Address Error Status */
-#define BITP_TRU_STAT_LWERR                   0                               /* Lock Write Error Status */
-#define BITM_TRU_STAT_ADDRERR                (_ADI_MSK(0x00000002,uint32_t))  /* Address Error Status */
-#define BITM_TRU_STAT_LWERR                  (_ADI_MSK(0x00000001,uint32_t))  /* Lock Write Error Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_REVID_MAJOR                  4                               /* Major Version ID */
-#define BITP_TRU_REVID_REV                    0                               /* Incremental Version ID */
-#define BITM_TRU_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_TRU_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_GCTL_LOCK                   31                               /* GCTL Lock Bit */
-#define BITP_TRU_GCTL_MTRL                    2                               /* MTR Lock Bit */
-#define BITP_TRU_GCTL_RESET                   1                               /* Soft Reset */
-#define BITP_TRU_GCTL_EN                      0                               /* Non-MMR Enable */
-#define BITM_TRU_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* GCTL Lock Bit */
-#define BITM_TRU_GCTL_MTRL                   (_ADI_MSK(0x00000004,uint32_t))  /* MTR Lock Bit */
-#define BITM_TRU_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Soft Reset */
-#define BITM_TRU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Non-MMR Enable */
-
-/* ==================================================
-        Reset Control Unit Registers
-   ================================================== */
-
-/* =========================
-        RCU0
-   ========================= */
-#define REG_RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
-#define REG_RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
-#define REG_RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
-#define REG_RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
-#define REG_RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
-#define REG_RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
-#define REG_RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
-#define REG_RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
-#define REG_RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
-#define REG_RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
-
-/* =========================
-        RCU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CTL_LOCK                    31                               /* Lock */
-#define BITP_RCU_CTL_RSTOUTDSRT               2                               /* Reset Out Deassert */
-#define BITP_RCU_CTL_RSTOUTASRT               1                               /* Reset Out Assert */
-#define BITP_RCU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_RCU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CTL_RSTOUTDSRT              (_ADI_MSK(0x00000004,uint32_t))  /* Reset Out Deassert */
-#define BITM_RCU_CTL_RSTOUTASRT              (_ADI_MSK(0x00000002,uint32_t))  /* Reset Out Assert */
-#define BITM_RCU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_STAT_RSTOUTERR              18                               /* Reset Out Error */
-#define BITP_RCU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_RCU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_RCU_STAT_BMODE                   8                               /* Boot Mode */
-#define BITP_RCU_STAT_RSTOUT                  5                               /* Reset Out Status */
-#define BITP_RCU_STAT_SWRST                   3                               /* Software Reset */
-#define BITP_RCU_STAT_SSRST                   2                               /* System Source Reset */
-#define BITP_RCU_STAT_HBRST                   1                               /* Hibernate Reset */
-#define BITP_RCU_STAT_HWRST                   0                               /* Hardware Reset */
-#define BITM_RCU_STAT_RSTOUTERR              (_ADI_MSK(0x00040000,uint32_t))  /* Reset Out Error */
-#define BITM_RCU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_RCU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_RCU_STAT_BMODE                  (_ADI_MSK(0x00000F00,uint32_t))  /* Boot Mode */
-#define BITM_RCU_STAT_RSTOUT                 (_ADI_MSK(0x00000020,uint32_t))  /* Reset Out Status */
-#define BITM_RCU_STAT_SWRST                  (_ADI_MSK(0x00000008,uint32_t))  /* Software Reset */
-#define BITM_RCU_STAT_SSRST                  (_ADI_MSK(0x00000004,uint32_t))  /* System Source Reset */
-#define BITM_RCU_STAT_HBRST                  (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Reset */
-#define BITM_RCU_STAT_HWRST                  (_ADI_MSK(0x00000001,uint32_t))  /* Hardware Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRCTL_LOCK                  31                               /* Lock */
-#define BITP_RCU_CRCTL_CR0                    0                               /* Core Reset n */
-#define BITP_RCU_CRCTL_CR1                    1                               /* Core Reset n */
-#define BITM_RCU_CRCTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CRCTL_CR0                   (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRCTL_CR1                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRSTAT_CR0                   0                               /* Core Reset n */
-#define BITP_RCU_CRSTAT_CR1                   1                               /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR0                  (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR1                  (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SIDIS                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SIDIS_LOCK                  31                               /* Lock */
-#define BITP_RCU_SIDIS_SI0                    0                               /* System Interface n */
-#define BITP_RCU_SIDIS_SI1                    1                               /* System Interface n */
-#define BITM_RCU_SIDIS_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SIDIS_SI0                   (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SIDIS_SI1                   (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SISTAT_SI0                   0                               /* System Interface n */
-#define BITP_RCU_SISTAT_SI1                   1                               /* System Interface n */
-#define BITM_RCU_SISTAT_SI0                  (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SISTAT_SI1                  (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SVECT_LCK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SVECT_LCK_LOCK              31                               /* Lock */
-#define BITP_RCU_SVECT_LCK_SVECT0             0                               /* Software Vector Register n */
-#define BITP_RCU_SVECT_LCK_SVECT1             1                               /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SVECT_LCK_SVECT0            (_ADI_MSK(0x00000001,uint32_t))  /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_SVECT1            (_ADI_MSK(0x00000002,uint32_t))  /* Software Vector Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_BCODE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_BCODE_LOCK                  31                               /* Lock */
-#define BITP_RCU_BCODE_BCODE                  0                               /* Boot Code */
-#define BITM_RCU_BCODE_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_BCODE_BCODE                 (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Boot Code */
-
-/* ==================================================
-        System Protection Unit Registers
-   ================================================== */
-
-/* =========================
-        SPU0
-   ========================= */
-#define REG_SPU0_CTL                    0xFFCA7000         /* SPU0 Control Register */
-#define REG_SPU0_STAT                   0xFFCA7004         /* SPU0 Status Register */
-#define REG_SPU0_WP0                    0xFFCA7400         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP1                    0xFFCA7404         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP2                    0xFFCA7408         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP3                    0xFFCA740C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP4                    0xFFCA7410         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP5                    0xFFCA7414         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP6                    0xFFCA7418         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP7                    0xFFCA741C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP8                    0xFFCA7420         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP9                    0xFFCA7424         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP10                   0xFFCA7428         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP11                   0xFFCA742C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP12                   0xFFCA7430         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP13                   0xFFCA7434         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP14                   0xFFCA7438         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP15                   0xFFCA743C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP16                   0xFFCA7440         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP17                   0xFFCA7444         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP18                   0xFFCA7448         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP19                   0xFFCA744C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP20                   0xFFCA7450         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP21                   0xFFCA7454         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP22                   0xFFCA7458         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP23                   0xFFCA745C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP24                   0xFFCA7460         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP25                   0xFFCA7464         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP26                   0xFFCA7468         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP27                   0xFFCA746C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP28                   0xFFCA7470         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP29                   0xFFCA7474         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP30                   0xFFCA7478         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP31                   0xFFCA747C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP32                   0xFFCA7480         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP33                   0xFFCA7484         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP34                   0xFFCA7488         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP35                   0xFFCA748C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP36                   0xFFCA7490         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP37                   0xFFCA7494         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP38                   0xFFCA7498         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP39                   0xFFCA749C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP40                   0xFFCA74A0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP41                   0xFFCA74A4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP42                   0xFFCA74A8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP43                   0xFFCA74AC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP44                   0xFFCA74B0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP45                   0xFFCA74B4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP46                   0xFFCA74B8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP47                   0xFFCA74BC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP48                   0xFFCA74C0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP49                   0xFFCA74C4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP50                   0xFFCA74C8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP51                   0xFFCA74CC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP52                   0xFFCA74D0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP53                   0xFFCA74D4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP54                   0xFFCA74D8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP55                   0xFFCA74DC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP56                   0xFFCA74E0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP57                   0xFFCA74E4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP58                   0xFFCA74E8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP59                   0xFFCA74EC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP60                   0xFFCA74F0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP61                   0xFFCA74F4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP62                   0xFFCA74F8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP63                   0xFFCA74FC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP64                   0xFFCA7500         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP65                   0xFFCA7504         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP66                   0xFFCA7508         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP67                   0xFFCA750C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP68                   0xFFCA7510         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP69                   0xFFCA7514         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP70                   0xFFCA7518         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP71                   0xFFCA751C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP72                   0xFFCA7520         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP73                   0xFFCA7524         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP74                   0xFFCA7528         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP75                   0xFFCA752C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP76                   0xFFCA7530         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP77                   0xFFCA7534         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP78                   0xFFCA7538         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP79                   0xFFCA753C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP80                   0xFFCA7540         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP81                   0xFFCA7544         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP82                   0xFFCA7548         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP83                   0xFFCA754C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP84                   0xFFCA7550         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP85                   0xFFCA7554         /* SPU0 Write Protect Register n */
-
-/* =========================
-        SPU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_CTL_WPLCK                   16                               /* Write Protect Register Lock */
-#define BITP_SPU_CTL_GLCK                     0                               /* Global Lock Disable */
-#define BITM_SPU_CTL_WPLCK                   (_ADI_MSK(0x00010000,uint32_t))  /* Write Protect Register Lock */
-#define BITM_SPU_CTL_GLCK                    (_ADI_MSK(0x000000FF,uint32_t))  /* Global Lock Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_STAT_LWERR                  31                               /* Lock Write Error */
-#define BITP_SPU_STAT_ADDRERR                30                               /* Address Error */
-#define BITP_SPU_STAT_GLCK                    0                               /* Global Lock Status */
-#define BITM_SPU_STAT_LWERR                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define BITM_SPU_STAT_ADDRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define BITM_SPU_STAT_GLCK                   (_ADI_MSK(0x00000001,uint32_t))  /* Global Lock Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_WP                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_WP_SM0                      16                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_SM1                      17                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_CM0                       0                               /* Core Master x Write Protect Enable */
-#define BITP_SPU_WP_CM1                       1                               /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_SM0                      (_ADI_MSK(0x00010000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_SM1                      (_ADI_MSK(0x00020000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_CM0                      (_ADI_MSK(0x00000001,uint32_t))  /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_CM1                      (_ADI_MSK(0x00000002,uint32_t))  /* Core Master x Write Protect Enable */
-
-/* ==================================================
-        Clock Generation Unit Registers
-   ================================================== */
-
-/* =========================
-        CGU0
-   ========================= */
-#define REG_CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
-#define REG_CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
-#define REG_CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
-#define REG_CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
-
-/* =========================
-        CGU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CTL_LOCK                    31                               /* Lock */
-#define BITP_CGU_CTL_WFI                     30                               /* Wait For Idle */
-#define BITP_CGU_CTL_MSEL                     8                               /* Multiplier Select */
-#define BITP_CGU_CTL_DF                       0                               /* Divide Frequency */
-#define BITM_CGU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_CTL_WFI                     (_ADI_MSK(0x40000000,uint32_t))  /* Wait For Idle */
-
-#define BITM_CGU_CTL_MSEL                    (_ADI_MSK(0x00007F00,uint32_t))  /* Multiplier Select */
-#define ENUM_CGU_CTL_MSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* MSEL: MSEL = 1 to 127 */
-#define BITM_CGU_CTL_DF                      (_ADI_MSK(0x00000001,uint32_t))  /* Divide Frequency */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_STAT_PLOCKERR               21                               /* PLL Lock Error */
-#define BITP_CGU_STAT_WDIVERR                20                               /* Write to DIV Error */
-#define BITP_CGU_STAT_WDFMSERR               19                               /* Write to DF or MSEL Error */
-#define BITP_CGU_STAT_DIVERR                 18                               /* DIV Error */
-#define BITP_CGU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_CGU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_CGU_STAT_OCBF                    9                               /* OUTCLK Buffer Status */
-#define BITP_CGU_STAT_DCBF                    8                               /* DCLK Buffer Status */
-#define BITP_CGU_STAT_SCBF1                   7                               /* SCLK1 Buffer Status */
-#define BITP_CGU_STAT_SCBF0                   6                               /* SCLK0 Buffer Status */
-#define BITP_CGU_STAT_CCBF1                   5                               /* CCLK1 Buffer Status */
-#define BITP_CGU_STAT_CCBF0                   4                               /* CCLK0 Buffer Status */
-#define BITP_CGU_STAT_CLKSALGN                3                               /* Clock Alignment */
-#define BITP_CGU_STAT_PLOCK                   2                               /* PLL Lock */
-#define BITP_CGU_STAT_PLLBP                   1                               /* PLL Bypass */
-#define BITP_CGU_STAT_PLLEN                   0                               /* PLL Enable */
-#define BITM_CGU_STAT_PLOCKERR               (_ADI_MSK(0x00200000,uint32_t))  /* PLL Lock Error */
-#define BITM_CGU_STAT_WDIVERR                (_ADI_MSK(0x00100000,uint32_t))  /* Write to DIV Error */
-#define BITM_CGU_STAT_WDFMSERR               (_ADI_MSK(0x00080000,uint32_t))  /* Write to DF or MSEL Error */
-#define BITM_CGU_STAT_DIVERR                 (_ADI_MSK(0x00040000,uint32_t))  /* DIV Error */
-#define BITM_CGU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_CGU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_CGU_STAT_OCBF                   (_ADI_MSK(0x00000200,uint32_t))  /* OUTCLK Buffer Status */
-#define BITM_CGU_STAT_DCBF                   (_ADI_MSK(0x00000100,uint32_t))  /* DCLK Buffer Status */
-#define BITM_CGU_STAT_SCBF1                  (_ADI_MSK(0x00000080,uint32_t))  /* SCLK1 Buffer Status */
-#define BITM_CGU_STAT_SCBF0                  (_ADI_MSK(0x00000040,uint32_t))  /* SCLK0 Buffer Status */
-#define BITM_CGU_STAT_CCBF1                  (_ADI_MSK(0x00000020,uint32_t))  /* CCLK1 Buffer Status */
-#define BITM_CGU_STAT_CCBF0                  (_ADI_MSK(0x00000010,uint32_t))  /* CCLK0 Buffer Status */
-#define BITM_CGU_STAT_CLKSALGN               (_ADI_MSK(0x00000008,uint32_t))  /* Clock Alignment */
-#define BITM_CGU_STAT_PLOCK                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Lock */
-#define BITM_CGU_STAT_PLLBP                  (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass */
-#define BITM_CGU_STAT_PLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* PLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_DIV                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_DIV_LOCK                    31                               /* Lock */
-#define BITP_CGU_DIV_UPDT                    30                               /* Update Clock Divisors */
-#define BITP_CGU_DIV_ALGN                    29                               /* Align */
-#define BITP_CGU_DIV_OSEL                    22                               /* OUTCLK Divisor */
-#define BITP_CGU_DIV_DSEL                    16                               /* DCLK Divisor */
-#define BITP_CGU_DIV_S1SEL                   13                               /* SCLK 1 Divisor */
-#define BITP_CGU_DIV_SYSSEL                   8                               /* SYSCLK Divisor */
-#define BITP_CGU_DIV_S0SEL                    5                               /* SCLK 0 Divisor */
-#define BITP_CGU_DIV_CSEL                     0                               /* CCLK Divisor */
-#define BITM_CGU_DIV_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_DIV_UPDT                    (_ADI_MSK(0x40000000,uint32_t))  /* Update Clock Divisors */
-#define BITM_CGU_DIV_ALGN                    (_ADI_MSK(0x20000000,uint32_t))  /* Align */
-
-#define BITM_CGU_DIV_OSEL                    (_ADI_MSK(0x1FC00000,uint32_t))  /* OUTCLK Divisor */
-#define ENUM_CGU_DIV_OSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* OSEL: OSEL = 1 to 127 */
-
-#define BITM_CGU_DIV_DSEL                    (_ADI_MSK(0x001F0000,uint32_t))  /* DCLK Divisor */
-#define ENUM_CGU_DIV_DSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* DSEL: DSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S1SEL                   (_ADI_MSK(0x0000E000,uint32_t))  /* SCLK 1 Divisor */
-#define ENUM_CGU_DIV_S1SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S1SEL: S1SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_SYSSEL                  (_ADI_MSK(0x00001F00,uint32_t))  /* SYSCLK Divisor */
-#define ENUM_CGU_DIV_SYSSEL1TO31             (_ADI_MSK(0x00000000,uint32_t))  /* SYSSEL: SYSSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S0SEL                   (_ADI_MSK(0x000000E0,uint32_t))  /* SCLK 0 Divisor */
-#define ENUM_CGU_DIV_S0SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S0SEL: S0SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_CSEL                    (_ADI_MSK(0x0000001F,uint32_t))  /* CCLK Divisor */
-#define ENUM_CGU_DIV_CSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* CSEL: CSEL= 1 to 31 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CLKOUTSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CLKOUTSEL_LOCK              31                               /* Lock */
-#define BITP_CGU_CLKOUTSEL_CLKOUTSEL          0                               /* CLKOUT Select */
-
-#define BITM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_CGU_CLKOUTSEL_UNLOCK            (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_CGU_CLKOUTSEL_CLKOUTSEL         (_ADI_MSK(0x0000000F,uint32_t))  /* CLKOUT Select */
-#define ENUM_CGU_CLKOUTSEL_CLKIN             (_ADI_MSK(0x00000000,uint32_t))  /* CLKOUTSEL: CLKIN */
-#define ENUM_CGU_CLKOUTSEL_CCLKDIV4          (_ADI_MSK(0x00000001,uint32_t))  /* CLKOUTSEL: CCLKn/4 */
-#define ENUM_CGU_CLKOUTSEL_GNDDIS            (_ADI_MSK(0x0000000B,uint32_t))  /* CLKOUTSEL: GND (Disable OUTCLK) */
-#define ENUM_CGU_CLKOUTSEL_SYSCLKDIV2        (_ADI_MSK(0x00000002,uint32_t))  /* CLKOUTSEL: SYSCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_SCLK0             (_ADI_MSK(0x00000003,uint32_t))  /* CLKOUTSEL: SCLK0 */
-#define ENUM_CGU_CLKOUTSEL_SCLK1             (_ADI_MSK(0x00000004,uint32_t))  /* CLKOUTSEL: SCLK1 */
-#define ENUM_CGU_CLKOUTSEL_DCLKDIV2          (_ADI_MSK(0x00000005,uint32_t))  /* CLKOUTSEL: DCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_OUTCLK            (_ADI_MSK(0x00000007,uint32_t))  /* CLKOUTSEL: OUTCLK */
-
-/* ==================================================
-        Dynamic Power Management Registers
-   ================================================== */
-
-/* =========================
-        DPM0
-   ========================= */
-#define REG_DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
-#define REG_DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
-#define REG_DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
-#define REG_DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
-#define REG_DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
-#define REG_DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
-#define REG_DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
-#define REG_DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
-#define REG_DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
-#define REG_DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
-#define REG_DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
-#define REG_DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
-#define REG_DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore n Register */
-
-/* =========================
-        DPM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CTL_LOCK                    31                               /* Lock */
-#define BITP_DPM_CTL_HIBERNATE                4                               /* Hibernate */
-#define BITP_DPM_CTL_DEEPSLEEP                3                               /* Deep Sleep */
-#define BITP_DPM_CTL_PLLDIS                   2                               /* PLL Disable */
-#define BITP_DPM_CTL_PLLBPCL                  1                               /* PLL Bypass Clear */
-#define BITP_DPM_CTL_PLLBPST                  0                               /* PLL Bypass Set */
-#define BITM_DPM_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CTL_HIBERNATE               (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate */
-#define BITM_DPM_CTL_DEEPSLEEP               (_ADI_MSK(0x00000008,uint32_t))  /* Deep Sleep */
-#define BITM_DPM_CTL_PLLDIS                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Disable */
-#define BITM_DPM_CTL_PLLBPCL                 (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass Clear */
-#define BITM_DPM_CTL_PLLBPST                 (_ADI_MSK(0x00000001,uint32_t))  /* PLL Bypass Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_STAT_PLLCFGERR              19                               /* PLL Configuration Error */
-#define BITP_DPM_STAT_HVBSYERR               18                               /* HV Busy Error */
-#define BITP_DPM_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_DPM_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_DPM_STAT_HVBSY                   9                               /* HV Busy */
-#define BITP_DPM_STAT_CCLKDIS                 8                               /* Core Clock(s) Disabled */
-#define BITP_DPM_STAT_PRVMODE                 4                               /* Previous Mode */
-#define BITP_DPM_STAT_CURMODE                 0                               /* Current Mode */
-#define BITM_DPM_STAT_PLLCFGERR              (_ADI_MSK(0x00080000,uint32_t))  /* PLL Configuration Error */
-#define BITM_DPM_STAT_HVBSYERR               (_ADI_MSK(0x00040000,uint32_t))  /* HV Busy Error */
-#define BITM_DPM_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_DPM_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_DPM_STAT_HVBSY                  (_ADI_MSK(0x00000200,uint32_t))  /* HV Busy */
-#define BITM_DPM_STAT_CCLKDIS                (_ADI_MSK(0x00000100,uint32_t))  /* Core Clock(s) Disabled */
-#define BITM_DPM_STAT_PRVMODE                (_ADI_MSK(0x000000F0,uint32_t))  /* Previous Mode */
-#define BITM_DPM_STAT_CURMODE                (_ADI_MSK(0x0000000F,uint32_t))  /* Current Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_CCBF_DIS_CCBF0               0                               /* Core Clock Buffer n Disable */
-#define BITP_DPM_CCBF_DIS_CCBF1               1                               /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_DIS_CCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_CCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_CCBF_EN_CCBF0                0                               /* Core Clock Buffer n Enable */
-#define BITP_DPM_CCBF_EN_CCBF1                1                               /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_EN_CCBF0               (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_CCBF1               (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_CCBF0              0                               /* Core Clock Buffer n Status */
-#define BITP_DPM_CCBF_STAT_CCBF1              1                               /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF0             (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF1             (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT_STKY                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF0         0                               /* Core Clock Buffer n Status - Sticky */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF1         1                               /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF0        (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF1        (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_SCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_SCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_SCBF_DIS_SCBF0               0                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF1               1                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF2               2                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF3               3                               /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_SCBF_DIS_SCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF2              (_ADI_MSK(0x00000004,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF3              (_ADI_MSK(0x00000008,uint32_t))  /* System Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_WAKE_EN_WS0                  0                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS1                  1                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS2                  2                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS3                  3                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS4                  4                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS5                  5                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS6                  6                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS7                  7                               /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_EN_WS0                 (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS1                 (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS2                 (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS3                 (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS4                 (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS5                 (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS6                 (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS7                 (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_POL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_POL_LOCK               31                               /* Lock */
-#define BITP_DPM_WAKE_POL_WS0                 0                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS1                 1                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS2                 2                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS3                 3                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS4                 4                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS5                 5                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS6                 6                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS7                 7                               /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_POL_WS0                (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS1                (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS2                (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS3                (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS4                (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS5                (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS6                (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS7                (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Polarity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_STAT_WS0                0                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS1                1                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS2                2                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS3                3                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS4                4                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS5                5                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS6                6                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS7                7                               /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS0               (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS1               (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS2               (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS3               (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS4               (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS5               (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS6               (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS7               (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_HIB_DIS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_HIB_DIS_LOCK                31                               /* Lock */
-#define BITP_DPM_HIB_DIS_HD0                  0                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD1                  1                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD2                  2                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD3                  3                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD4                  4                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD5                  5                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD6                  6                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD7                  7                               /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_HIB_DIS_HD0                 (_ADI_MSK(0x00000001,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD1                 (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD2                 (_ADI_MSK(0x00000004,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD3                 (_ADI_MSK(0x00000008,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD4                 (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD5                 (_ADI_MSK(0x00000020,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD6                 (_ADI_MSK(0x00000040,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD7                 (_ADI_MSK(0x00000080,uint32_t))  /* Hibernate Disable n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_PGCNTR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_PGCNTR_LOCK                 31                               /* Lock */
-#define BITP_DPM_PGCNTR_CNT                   0                               /* Power Good Count */
-#define BITM_DPM_PGCNTR_LOCK                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_PGCNTR_CNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Power Good Count */
-
-/* ==================================================
-        eFUSE Controller Registers
-   ================================================== */
-
-/* =========================
-        EFS0
-   ========================= */
-#define REG_EFS0_CTL                    0xFFCC0000         /* EFS0 Control Register */
-#define REG_EFS0_DAT0                   0xFFCC0008         /* EFS0 Data Register 0 */
-#define REG_EFS0_DAT1                   0xFFCC000C         /* EFS0 Data Register 1 */
-#define REG_EFS0_DAT2                   0xFFCC0010         /* EFS0 Data Register 2 */
-#define REG_EFS0_DAT3                   0xFFCC0014         /* EFS0 Data Register 3 */
-#define REG_EFS0_DAT4                   0xFFCC0018         /* EFS0 Data Register 4 */
-#define REG_EFS0_DAT5                   0xFFCC001C         /* EFS0 Data Register 5 */
-#define REG_EFS0_DAT6                   0xFFCC0020         /* EFS0 Data Register 6 */
-#define REG_EFS0_DAT7                   0xFFCC0024         /* EFS0 Data Register 7 */
-
-/* =========================
-        EFS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EFS_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EFS_CTL_READ                     0                               /* Read */
-#define BITM_EFS_CTL_READ                    (_ADI_MSK(0x00000001,uint32_t))  /* Read */
-
-/* ==================================================
-        Universal Serial Bus Controller Registers
-   ================================================== */
-
-/* =========================
-        USB0
-   ========================= */
-#define REG_USB0_FADDR                  0xFFCC1000         /* USB0 Function Address Register */
-#define REG_USB0_POWER                  0xFFCC1001         /* USB0 Power and Device Control Register */
-#define REG_USB0_INTRTX                 0xFFCC1002         /* USB0 Transmit Interrupt Register */
-#define REG_USB0_INTRRX                 0xFFCC1004         /* USB0 Receive Interrupt Register */
-#define REG_USB0_INTRTXE                0xFFCC1006         /* USB0 Transmit Interrupt Enable Register */
-#define REG_USB0_INTRRXE                0xFFCC1008         /* USB0 Receive Interrupt Enable Register */
-#define REG_USB0_IRQ                    0xFFCC100A         /* USB0 Common Interrupts Register */
-#define REG_USB0_IEN                    0xFFCC100B         /* USB0 Common Interrupts Enable Register */
-#define REG_USB0_FRAME                  0xFFCC100C         /* USB0 Frame Number Register */
-#define REG_USB0_INDEX                  0xFFCC100E         /* USB0 Index Register */
-#define REG_USB0_TESTMODE               0xFFCC100F         /* USB0 Testmode Register */
-#define REG_USB0_EPI_TXMAXP0            0xFFCC1010         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EPI_TXCSR_P0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EPI_TXCSR_H0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0I_CSR0_P            0xFFCC1012         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CSR0_H            0xFFCC1012         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXMAXP0            0xFFCC1014         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EPI_RXCSR_H0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXCSR_P0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CNT0              0xFFCC1018         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EPI_RXCNT0             0xFFCC1018         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EPI_TXTYPE0            0xFFCC101A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0I_TYPE0             0xFFCC101A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EPI_TXINTERVAL0        0xFFCC101B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0I_NAKLIMIT0         0xFFCC101B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EPI_RXTYPE0            0xFFCC101C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EPI_RXINTERVAL0        0xFFCC101D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0I_CFGDATA0          0xFFCC101F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_FIFOB0                 0xFFCC1020         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB1                 0xFFCC1024         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB2                 0xFFCC1028         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB3                 0xFFCC102C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB4                 0xFFCC1030         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB5                 0xFFCC1034         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB6                 0xFFCC1038         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB7                 0xFFCC103C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB8                 0xFFCC1040         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB9                 0xFFCC1044         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB10                0xFFCC1048         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB11                0xFFCC104C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOH0                 0xFFCC1020         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH1                 0xFFCC1024         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH2                 0xFFCC1028         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH3                 0xFFCC102C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH4                 0xFFCC1030         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH5                 0xFFCC1034         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH6                 0xFFCC1038         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH7                 0xFFCC103C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH8                 0xFFCC1040         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH9                 0xFFCC1044         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH10                0xFFCC1048         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH11                0xFFCC104C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFO0                  0xFFCC1020         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO1                  0xFFCC1024         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO2                  0xFFCC1028         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO3                  0xFFCC102C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO4                  0xFFCC1030         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO5                  0xFFCC1034         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO6                  0xFFCC1038         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO7                  0xFFCC103C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO8                  0xFFCC1040         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO9                  0xFFCC1044         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO10                 0xFFCC1048         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO11                 0xFFCC104C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_DEV_CTL                0xFFCC1060         /* USB0 Device Control Register */
-#define REG_USB0_TXFIFOSZ               0xFFCC1062         /* USB0 Transmit FIFO Size Register */
-#define REG_USB0_RXFIFOSZ               0xFFCC1063         /* USB0 Receive FIFO Size Register */
-#define REG_USB0_TXFIFOADDR             0xFFCC1064         /* USB0 Transmit FIFO Address Register */
-#define REG_USB0_RXFIFOADDR             0xFFCC1066         /* USB0 Receive FIFO Address Register */
-#define REG_USB0_EPINFO                 0xFFCC1078         /* USB0 Endpoint Information Register */
-#define REG_USB0_RAMINFO                0xFFCC1079         /* USB0 RAM Information Register */
-#define REG_USB0_LINKINFO               0xFFCC107A         /* USB0 Link Information Register */
-#define REG_USB0_VPLEN                  0xFFCC107B         /* USB0 VBUS Pulse Length Register */
-#define REG_USB0_HS_EOF1                0xFFCC107C         /* USB0 High-Speed EOF 1 Register */
-#define REG_USB0_FS_EOF1                0xFFCC107D         /* USB0 Full-Speed EOF 1 Register */
-#define REG_USB0_LS_EOF1                0xFFCC107E         /* USB0 Low-Speed EOF 1 Register */
-#define REG_USB0_SOFT_RST               0xFFCC107F         /* USB0 Software Reset Register */
-#define REG_USB0_MP0_TXFUNCADDR         0xFFCC1080         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP1_TXFUNCADDR         0xFFCC1088         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP2_TXFUNCADDR         0xFFCC1090         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP3_TXFUNCADDR         0xFFCC1098         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP4_TXFUNCADDR         0xFFCC10A0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP5_TXFUNCADDR         0xFFCC10A8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP6_TXFUNCADDR         0xFFCC10B0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP7_TXFUNCADDR         0xFFCC10B8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP8_TXFUNCADDR         0xFFCC10C0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP9_TXFUNCADDR         0xFFCC10C8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP10_TXFUNCADDR        0xFFCC10D0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP11_TXFUNCADDR        0xFFCC10D8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP0_TXHUBADDR          0xFFCC1082         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP1_TXHUBADDR          0xFFCC108A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP2_TXHUBADDR          0xFFCC1092         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP3_TXHUBADDR          0xFFCC109A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP4_TXHUBADDR          0xFFCC10A2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP5_TXHUBADDR          0xFFCC10AA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP6_TXHUBADDR          0xFFCC10B2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP7_TXHUBADDR          0xFFCC10BA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP8_TXHUBADDR          0xFFCC10C2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP9_TXHUBADDR          0xFFCC10CA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP10_TXHUBADDR         0xFFCC10D2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP11_TXHUBADDR         0xFFCC10DA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP0_TXHUBPORT          0xFFCC1083         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP1_TXHUBPORT          0xFFCC108B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP2_TXHUBPORT          0xFFCC1093         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP3_TXHUBPORT          0xFFCC109B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP4_TXHUBPORT          0xFFCC10A3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP5_TXHUBPORT          0xFFCC10AB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP6_TXHUBPORT          0xFFCC10B3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP7_TXHUBPORT          0xFFCC10BB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP8_TXHUBPORT          0xFFCC10C3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP9_TXHUBPORT          0xFFCC10CB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP10_TXHUBPORT         0xFFCC10D3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP11_TXHUBPORT         0xFFCC10DB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP0_RXFUNCADDR         0xFFCC1084         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP1_RXFUNCADDR         0xFFCC108C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP2_RXFUNCADDR         0xFFCC1094         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP3_RXFUNCADDR         0xFFCC109C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP4_RXFUNCADDR         0xFFCC10A4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP5_RXFUNCADDR         0xFFCC10AC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP6_RXFUNCADDR         0xFFCC10B4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP7_RXFUNCADDR         0xFFCC10BC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP8_RXFUNCADDR         0xFFCC10C4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP9_RXFUNCADDR         0xFFCC10CC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP10_RXFUNCADDR        0xFFCC10D4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP11_RXFUNCADDR        0xFFCC10DC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP0_RXHUBADDR          0xFFCC1086         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP1_RXHUBADDR          0xFFCC108E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP2_RXHUBADDR          0xFFCC1096         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP3_RXHUBADDR          0xFFCC109E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP4_RXHUBADDR          0xFFCC10A6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP5_RXHUBADDR          0xFFCC10AE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP6_RXHUBADDR          0xFFCC10B6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP7_RXHUBADDR          0xFFCC10BE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP8_RXHUBADDR          0xFFCC10C6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP9_RXHUBADDR          0xFFCC10CE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP10_RXHUBADDR         0xFFCC10D6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP11_RXHUBADDR         0xFFCC10DE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP0_RXHUBPORT          0xFFCC1087         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP1_RXHUBPORT          0xFFCC108F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP2_RXHUBPORT          0xFFCC1097         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP3_RXHUBPORT          0xFFCC109F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP4_RXHUBPORT          0xFFCC10A7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP5_RXHUBPORT          0xFFCC10AF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP6_RXHUBPORT          0xFFCC10B7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP7_RXHUBPORT          0xFFCC10BF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP8_RXHUBPORT          0xFFCC10C7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP9_RXHUBPORT          0xFFCC10CF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP10_RXHUBPORT         0xFFCC10D7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP11_RXHUBPORT         0xFFCC10DF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_EP0_TXMAXP             0xFFCC1100         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP1_TXMAXP             0xFFCC1110         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP2_TXMAXP             0xFFCC1120         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP3_TXMAXP             0xFFCC1130         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP4_TXMAXP             0xFFCC1140         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP5_TXMAXP             0xFFCC1150         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP6_TXMAXP             0xFFCC1160         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP7_TXMAXP             0xFFCC1170         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP8_TXMAXP             0xFFCC1180         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP9_TXMAXP             0xFFCC1190         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP10_TXMAXP            0xFFCC11A0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP11_TXMAXP            0xFFCC11B0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP0_CSR0_H             0xFFCC1102         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EP0_TXCSR_H            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP1_TXCSR_H            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP2_TXCSR_H            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP3_TXCSR_H            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP4_TXCSR_H            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP5_TXCSR_H            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP6_TXCSR_H            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP7_TXCSR_H            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP8_TXCSR_H            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP9_TXCSR_H            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP10_TXCSR_H           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP11_TXCSR_H           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0_CSR0_P             0xFFCC1102         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_TXCSR_P            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_TXCSR_P            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_TXCSR_P            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_TXCSR_P            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_TXCSR_P            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_TXCSR_P            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_TXCSR_P            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_TXCSR_P            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_TXCSR_P            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_TXCSR_P            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_TXCSR_P           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_TXCSR_P           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_RXMAXP             0xFFCC1104         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP1_RXMAXP             0xFFCC1114         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP2_RXMAXP             0xFFCC1124         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP3_RXMAXP             0xFFCC1134         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP4_RXMAXP             0xFFCC1144         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP5_RXMAXP             0xFFCC1154         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP6_RXMAXP             0xFFCC1164         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP7_RXMAXP             0xFFCC1174         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP8_RXMAXP             0xFFCC1184         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP9_RXMAXP             0xFFCC1194         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP10_RXMAXP            0xFFCC11A4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP11_RXMAXP            0xFFCC11B4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP0_RXCSR_H            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP1_RXCSR_H            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP2_RXCSR_H            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP3_RXCSR_H            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP4_RXCSR_H            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP5_RXCSR_H            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP6_RXCSR_H            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP7_RXCSR_H            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP8_RXCSR_H            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP9_RXCSR_H            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP10_RXCSR_H           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP11_RXCSR_H           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP0_RXCSR_P            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_RXCSR_P            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_RXCSR_P            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_RXCSR_P            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_RXCSR_P            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_RXCSR_P            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_RXCSR_P            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_RXCSR_P            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_RXCSR_P            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_RXCSR_P            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_RXCSR_P           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_RXCSR_P           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_CNT0               0xFFCC1108         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EP0_RXCNT              0xFFCC1108         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP1_RXCNT              0xFFCC1118         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP2_RXCNT              0xFFCC1128         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP3_RXCNT              0xFFCC1138         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP4_RXCNT              0xFFCC1148         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP5_RXCNT              0xFFCC1158         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP6_RXCNT              0xFFCC1168         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP7_RXCNT              0xFFCC1178         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP8_RXCNT              0xFFCC1188         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP9_RXCNT              0xFFCC1198         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP10_RXCNT             0xFFCC11A8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP11_RXCNT             0xFFCC11B8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP0_TYPE0              0xFFCC110A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EP0_TXTYPE             0xFFCC110A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP1_TXTYPE             0xFFCC111A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP2_TXTYPE             0xFFCC112A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP3_TXTYPE             0xFFCC113A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP4_TXTYPE             0xFFCC114A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP5_TXTYPE             0xFFCC115A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP6_TXTYPE             0xFFCC116A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP7_TXTYPE             0xFFCC117A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP8_TXTYPE             0xFFCC118A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP9_TXTYPE             0xFFCC119A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP10_TXTYPE            0xFFCC11AA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP11_TXTYPE            0xFFCC11BA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0_NAKLIMIT0          0xFFCC110B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EP0_TXINTERVAL         0xFFCC110B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP1_TXINTERVAL         0xFFCC111B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP2_TXINTERVAL         0xFFCC112B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP3_TXINTERVAL         0xFFCC113B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP4_TXINTERVAL         0xFFCC114B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP5_TXINTERVAL         0xFFCC115B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP6_TXINTERVAL         0xFFCC116B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP7_TXINTERVAL         0xFFCC117B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP8_TXINTERVAL         0xFFCC118B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP9_TXINTERVAL         0xFFCC119B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP10_TXINTERVAL        0xFFCC11AB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP11_TXINTERVAL        0xFFCC11BB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0_RXTYPE             0xFFCC110C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP1_RXTYPE             0xFFCC111C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP2_RXTYPE             0xFFCC112C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP3_RXTYPE             0xFFCC113C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP4_RXTYPE             0xFFCC114C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP5_RXTYPE             0xFFCC115C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP6_RXTYPE             0xFFCC116C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP7_RXTYPE             0xFFCC117C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP8_RXTYPE             0xFFCC118C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP9_RXTYPE             0xFFCC119C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP10_RXTYPE            0xFFCC11AC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP11_RXTYPE            0xFFCC11BC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP0_RXINTERVAL         0xFFCC110D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP1_RXINTERVAL         0xFFCC111D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP2_RXINTERVAL         0xFFCC112D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP3_RXINTERVAL         0xFFCC113D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP4_RXINTERVAL         0xFFCC114D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP5_RXINTERVAL         0xFFCC115D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP6_RXINTERVAL         0xFFCC116D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP7_RXINTERVAL         0xFFCC117D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP8_RXINTERVAL         0xFFCC118D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP9_RXINTERVAL         0xFFCC119D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP10_RXINTERVAL        0xFFCC11AD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP11_RXINTERVAL        0xFFCC11BD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0_CFGDATA0           0xFFCC110F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_DMA_IRQ                0xFFCC1200         /* USB0 DMA Interrupt Register */
-#define REG_USB0_DMA0_CTL               0xFFCC1204         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA1_CTL               0xFFCC1214         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA2_CTL               0xFFCC1224         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA3_CTL               0xFFCC1234         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA4_CTL               0xFFCC1244         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA5_CTL               0xFFCC1254         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA6_CTL               0xFFCC1264         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA7_CTL               0xFFCC1274         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA0_ADDR              0xFFCC1208         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA1_ADDR              0xFFCC1218         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA2_ADDR              0xFFCC1228         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA3_ADDR              0xFFCC1238         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA4_ADDR              0xFFCC1248         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA5_ADDR              0xFFCC1258         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA6_ADDR              0xFFCC1268         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA7_ADDR              0xFFCC1278         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA0_CNT               0xFFCC120C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA1_CNT               0xFFCC121C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA2_CNT               0xFFCC122C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA3_CNT               0xFFCC123C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA4_CNT               0xFFCC124C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA5_CNT               0xFFCC125C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA6_CNT               0xFFCC126C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA7_CNT               0xFFCC127C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_RQPKTCNT0              0xFFCC1300         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT1              0xFFCC1304         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT2              0xFFCC1308         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT3              0xFFCC130C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT4              0xFFCC1310         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT5              0xFFCC1314         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT6              0xFFCC1318         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT7              0xFFCC131C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT8              0xFFCC1320         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT9              0xFFCC1324         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT10             0xFFCC1328         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_CT_UCH                 0xFFCC1344         /* USB0 Chirp Timeout Register */
-#define REG_USB0_CT_HHSRTN              0xFFCC1346         /* USB0 Host High Speed Return to Normal Register */
-#define REG_USB0_CT_HSBT                0xFFCC1348         /* USB0 High Speed Timeout Register */
-#define REG_USB0_LPM_ATTR               0xFFCC1360         /* USB0 LPM Attribute Register */
-#define REG_USB0_LPM_CTL                0xFFCC1362         /* USB0 LPM Control Register */
-#define REG_USB0_LPM_IEN                0xFFCC1363         /* USB0 LPM Interrupt Enable Register */
-#define REG_USB0_LPM_IRQ                0xFFCC1364         /* USB0 LPM Interrupt Status Register */
-#define REG_USB0_LPM_FADDR              0xFFCC1365         /* USB0 LPM Function Address Register */
-#define REG_USB0_VBUS_CTL               0xFFCC1380         /* USB0 VBUS Control Register */
-#define REG_USB0_BAT_CHG                0xFFCC1381         /* USB0 Battery Charging Control Register */
-#define REG_USB0_PHY_CTL                0xFFCC1394         /* USB0 PHY Control Register */
-#define REG_USB0_PLL_OSC                0xFFCC1398         /* USB0 PLL and Oscillator Control Register */
-
-/* =========================
-        USB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FADDR                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FADDR_VALUE                  0                               /* Function Address Value */
-#define BITM_USB_FADDR_VALUE                 (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_POWER                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_POWER_ISOUPDT                7                               /* ISO Update Enable */
-#define BITP_USB_POWER_SOFTCONN               6                               /* Soft Connect/Disconnect Enable */
-#define BITP_USB_POWER_HSEN                   5                               /* High Speed Mode Enable */
-#define BITP_USB_POWER_HSMODE                 4                               /* High Speed Mode */
-#define BITP_USB_POWER_RESET                  3                               /* Reset USB */
-#define BITP_USB_POWER_RESUME                 2                               /* Resume Mode */
-#define BITP_USB_POWER_SUSPEND                1                               /* Suspend Mode */
-#define BITP_USB_POWER_SUSEN                  0                               /* SUSPENDM Output Enable */
-
-#define BITM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISO Update Enable */
-#define ENUM_USB_POWER_NO_ISOUPDT            (_ADI_MSK(0x00000000,uint8_t))   /* ISOUPDT: Disable ISO Update */
-#define ENUM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISOUPDT: Enable ISO Update */
-
-#define BITM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* Soft Connect/Disconnect Enable */
-#define ENUM_USB_POWER_NO_SOFTCONN           (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCONN: Disable Soft Connect/Disconnect */
-#define ENUM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* SOFTCONN: Enable Soft Connect/Disconnect */
-
-#define BITM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* High Speed Mode Enable */
-#define ENUM_USB_POWER_HSDIS                 (_ADI_MSK(0x00000000,uint8_t))   /* HSEN: Disable Negotiation for HS Mode */
-#define ENUM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* HSEN: Enable Negotiation for HS Mode */
-
-#define BITM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* High Speed Mode */
-#define ENUM_USB_POWER_NO_HSMODE             (_ADI_MSK(0x00000000,uint8_t))   /* HSMODE: Full Speed Mode (HS fail during reset) */
-#define ENUM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* HSMODE: High Speed Mode (HS success during reset) */
-
-#define BITM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* Reset USB */
-#define ENUM_USB_POWER_NO_RESET              (_ADI_MSK(0x00000000,uint8_t))   /* RESET: No Reset */
-#define ENUM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* RESET: Reset USB */
-
-#define BITM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* Resume Mode */
-#define ENUM_USB_POWER_NO_RESUME             (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Resume Signaling */
-#define ENUM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* RESUME: Enable Resume Signaling */
-
-#define BITM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* Suspend Mode */
-#define ENUM_USB_POWER_NO_SUSPEND            (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Suspend Mode (Host) */
-#define ENUM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* SUSPEND: Enable Suspend Mode (Host) */
-
-#define BITM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPENDM Output Enable */
-#define ENUM_USB_POWER_SUSDIS                (_ADI_MSK(0x00000000,uint8_t))   /* SUSEN: Disable SUSPENDM Output */
-#define ENUM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSEN: Enable SUSPENDM Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTX_EP11                 11                               /* End Point 11 Tx Interrupt */
-#define BITP_USB_INTRTX_EP10                 10                               /* End Point 10 Tx Interrupt */
-#define BITP_USB_INTRTX_EP9                   9                               /* End Point 9 Tx Interrupt */
-#define BITP_USB_INTRTX_EP8                   8                               /* End Point 8 Tx Interrupt */
-#define BITP_USB_INTRTX_EP7                   7                               /* End Point 7 Tx Interrupt */
-#define BITP_USB_INTRTX_EP6                   6                               /* End Point 6 Tx Interrupt */
-#define BITP_USB_INTRTX_EP5                   5                               /* End Point 5 Tx Interrupt */
-#define BITP_USB_INTRTX_EP4                   4                               /* End Point 4 Tx Interrupt */
-#define BITP_USB_INTRTX_EP3                   3                               /* End Point 3 Tx Interrupt */
-#define BITP_USB_INTRTX_EP2                   2                               /* End Point 2 Tx Interrupt */
-#define BITP_USB_INTRTX_EP1                   1                               /* End Point 1 Tx Interrupt */
-#define BITP_USB_INTRTX_EP0                   0                               /* End Point 0 Tx Interrupt */
-#define BITM_USB_INTRTX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt */
-#define BITM_USB_INTRTX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt */
-#define BITM_USB_INTRTX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt */
-#define BITM_USB_INTRTX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt */
-#define BITM_USB_INTRTX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt */
-#define BITM_USB_INTRTX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt */
-#define BITM_USB_INTRTX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt */
-#define BITM_USB_INTRTX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt */
-#define BITM_USB_INTRTX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt */
-#define BITM_USB_INTRTX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt */
-#define BITM_USB_INTRTX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt */
-#define BITM_USB_INTRTX_EP0                  (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRX_EP11                 11                               /* End Point 11 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP10                 10                               /* End Point 10 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP9                   9                               /* End Point 9 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP8                   8                               /* End Point 8 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP7                   7                               /* End Point 7 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP6                   6                               /* End Point 6 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP5                   5                               /* End Point 5 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP4                   4                               /* End Point 4 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP3                   3                               /* End Point 3 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP2                   2                               /* End Point 2 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP1                   1                               /* End Point 1 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTXE_EP11                11                               /* End Point 11 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP10                10                               /* End Point 10 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP9                  9                               /* End Point 9 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP8                  8                               /* End Point 8 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP7                  7                               /* End Point 7 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP6                  6                               /* End Point 6 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP5                  5                               /* End Point 5 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP4                  4                               /* End Point 4 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP3                  3                               /* End Point 3 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP2                  2                               /* End Point 2 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP1                  1                               /* End Point 1 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP0                  0                               /* End Point 0 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP0                 (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRXE_EP11                11                               /* End Point 11 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP10                10                               /* End Point 10 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP9                  9                               /* End Point 9 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP8                  8                               /* End Point 8 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP7                  7                               /* End Point 7 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP6                  6                               /* End Point 6 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP5                  5                               /* End Point 5 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP4                  4                               /* End Point 4 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP3                  3                               /* End Point 3 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP2                  2                               /* End Point 2 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP1                  1                               /* End Point 1 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IRQ                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IRQ_VBUSERR                  7                               /* VBUS Threshold Indicator */
-#define BITP_USB_IRQ_SESSREQ                  6                               /* Session Request Indicator */
-#define BITP_USB_IRQ_DISCON                   5                               /* Disconnect Indicator */
-#define BITP_USB_IRQ_CON                      4                               /* Connection Indicator */
-#define BITP_USB_IRQ_SOF                      3                               /* Start-of-frame Indicator */
-#define BITP_USB_IRQ_RSTBABBLE                2                               /* Reset/Babble Indicator */
-#define BITP_USB_IRQ_RESUME                   1                               /* Resume Indicator */
-#define BITP_USB_IRQ_SUSPEND                  0                               /* Suspend Indicator */
-
-#define BITM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator */
-#define ENUM_USB_IRQ_NO_VBUSERR              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: No Interrupt */
-#define ENUM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Interrupt Pending */
-
-#define BITM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator */
-#define ENUM_USB_IRQ_NO_SESSREQ              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: No Interrupt */
-#define ENUM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Interrupt Pending */
-
-#define BITM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator */
-#define ENUM_USB_IRQ_NO_DISCON               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: No Interrupt */
-#define ENUM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Interrupt Pending */
-
-#define BITM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator */
-#define ENUM_USB_IRQ_NO_CON                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: No Interrupt */
-#define ENUM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* CON: Interrupt Pending */
-
-#define BITM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator */
-#define ENUM_USB_IRQ_NO_SOF                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: No Interrupt */
-#define ENUM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Interrupt Pending */
-
-#define BITM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator */
-#define ENUM_USB_IRQ_NO_RSTBABBLE            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: No Interrupt */
-#define ENUM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Interrupt Pending */
-
-#define BITM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator */
-#define ENUM_USB_IRQ_NO_RESUME               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: No Interrupt */
-#define ENUM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Interrupt Pending */
-
-#define BITM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator */
-#define ENUM_USB_IRQ_NO_SUSPEND              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: No Interrupt */
-#define ENUM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IEN                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IEN_VBUSERR                  7                               /* VBUS Threshold Indicator Interrupt Enable */
-#define BITP_USB_IEN_SESSREQ                  6                               /* Session Request Indicator Interrupt Enable */
-#define BITP_USB_IEN_DISCON                   5                               /* Disconnect Indicator Interrupt Enable */
-#define BITP_USB_IEN_CON                      4                               /* Connection Indicator Interrupt Enable */
-#define BITP_USB_IEN_SOF                      3                               /* Start-of-frame Indicator Interrupt Enable */
-#define BITP_USB_IEN_RSTBABBLE                2                               /* Reset/Babble Indicator Interrupt Enable */
-#define BITP_USB_IEN_RESUME                   1                               /* Resume Indicator Interrupt Enable */
-#define BITP_USB_IEN_SUSPEND                  0                               /* Suspend Indicator Interrupt Enable */
-
-#define BITM_USB_IEN_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator Interrupt Enable */
-#define ENUM_USB_IEN_VBUSERRDIS              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: Disable Interrupt */
-#define ENUM_USB_IEN_VBUSERREN               (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Enable Interrupt */
-
-#define BITM_USB_IEN_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SESSREQDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: Disable Interrupt */
-#define ENUM_USB_IEN_SESSREQEN               (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Enable Interrupt */
-
-#define BITM_USB_IEN_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator Interrupt Enable */
-#define ENUM_USB_IEN_DISCONDIS               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: Disable Interrupt */
-#define ENUM_USB_IEN_DISCONEN                (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Enable Interrupt */
-
-#define BITM_USB_IEN_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator Interrupt Enable */
-#define ENUM_USB_IEN_CONDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: Disable Interrupt */
-#define ENUM_USB_IEN_CONEN                   (_ADI_MSK(0x00000010,uint8_t))   /* CON: Enable Interrupt */
-
-#define BITM_USB_IEN_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SOFDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: Disable Interrupt */
-#define ENUM_USB_IEN_SOFEN                   (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Enable Interrupt */
-
-#define BITM_USB_IEN_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RSTBABBLEDIS            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: Disable Interrupt */
-#define ENUM_USB_IEN_RSTBABBLEEN             (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Enable Interrupt */
-
-#define BITM_USB_IEN_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RESUMEDIS               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Interrupt */
-#define ENUM_USB_IEN_RESUMEEN                (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Enable Interrupt */
-
-#define BITM_USB_IEN_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SUSPENDDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Interrupt */
-#define ENUM_USB_IEN_SUSPENDEN               (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Enable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FRAME                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FRAME_VALUE                  0                               /* Frame Number Value */
-#define BITM_USB_FRAME_VALUE                 (_ADI_MSK(0x000007FF,uint16_t))  /* Frame Number Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INDEX                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INDEX_EP                     0                               /* Endpoint Index */
-#define BITM_USB_INDEX_EP                    (_ADI_MSK(0x0000000F,uint8_t))   /* Endpoint Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TESTMODE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TESTMODE_FIFOACCESS          6                               /* FIFO Access */
-#define BITP_USB_TESTMODE_TESTPACKET          3                               /* Test_Packet Mode */
-#define BITP_USB_TESTMODE_TESTK               2                               /* Test_K Mode */
-#define BITP_USB_TESTMODE_TESTJ               1                               /* Test_J Mode */
-#define BITP_USB_TESTMODE_TESTSE0NAK          0                               /* Test SE0 NAK */
-#define BITM_USB_TESTMODE_FIFOACCESS         (_ADI_MSK(0x00000040,uint8_t))   /* FIFO Access */
-#define BITM_USB_TESTMODE_TESTPACKET         (_ADI_MSK(0x00000008,uint8_t))   /* Test_Packet Mode */
-#define BITM_USB_TESTMODE_TESTK              (_ADI_MSK(0x00000004,uint8_t))   /* Test_K Mode */
-#define BITM_USB_TESTMODE_TESTJ              (_ADI_MSK(0x00000002,uint8_t))   /* Test_J Mode */
-#define BITM_USB_TESTMODE_TESTSE0NAK         (_ADI_MSK(0x00000001,uint8_t))   /* Test SE0 NAK */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_TXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_TXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_TXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_P_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_P_ISO             14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EPI_TXCSR_P_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_P_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_P_INCOMPTX         7                               /* Incomplete Tx */
-#define BITP_USB_EPI_TXCSR_P_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_SENTSTALL        5                               /* Sent STALL */
-#define BITP_USB_EPI_TXCSR_P_SENDSTALL        4                               /* Send STALL */
-#define BITP_USB_EPI_TXCSR_P_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_P_URUNERR          2                               /* Underrun Error */
-#define BITP_USB_EPI_TXCSR_P_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_P_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_P_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EPI_TXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EPI_TXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_P_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_P_INCOMPTX        (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EPI_TXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EPI_TXCSR_P_INCOMP          (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EPI_TXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_P_SENTSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_P_STALSNT         (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_TXCSR_P_SENDSTALL       (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EPI_TXCSR_P_STALL           (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EPI_TXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_P_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EPI_TXCSR_P_NO_URUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EPI_TXCSR_P_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FIFONE       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_P_FIFONE          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_P_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_H_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_H_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_H_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_H_DATGLEN          9                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_TXCSR_H_DATGL            8                               /* Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_NAKTOINCMP       7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EPI_TXCSR_H_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_RXSTALL          5                               /* Rx STALL */
-#define BITP_USB_EPI_TXCSR_H_SETUPPKT         4                               /* Setup Packet */
-#define BITP_USB_EPI_TXCSR_H_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXTOERR          2                               /* Tx Timeout Error */
-#define BITP_USB_EPI_TXCSR_H_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_H_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGLEN      (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EPI_TXCSR_H_NAKTOINCMP      (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EPI_TXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EPI_TXCSR_H_NAKTO           (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EPI_TXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_TXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EPI_TXCSR_H_NO_SETUPPK      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EPI_TXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_H_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EPI_TXCSR_H_NO_TXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_NEFIFO       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_H_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_P_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_P_SSETUPEND         7                               /* Service Setup End */
-#define BITP_USB_EP0I_CSR_P_SPKTRDY           6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_SENDSTALL         5                               /* Send Stall */
-#define BITP_USB_EP0I_CSR_P_SETUPEND          4                               /* Setup End */
-#define BITP_USB_EP0I_CSR_P_DATAEND           3                               /* Data End */
-#define BITP_USB_EP0I_CSR_P_SENTSTALL         2                               /* Sent Stall */
-#define BITP_USB_EP0I_CSR_P_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_P_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_P_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0I_CSR_P_NOSSETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_SPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0I_CSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0I_CSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0I_CSR_P_NO_SETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0I_CSR_P_NO_DATAEND       (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0I_CSR_P_SENTSTALL        (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_P_STALSNT          (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0I_CSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_H_DISPING          11                               /* Disable Ping */
-#define BITP_USB_EP0I_CSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0I_CSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP0I_CSR_H_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_H_NAKTO             7                               /* NAK Timeout */
-#define BITP_USB_EP0I_CSR_H_STATUSPKT         6                               /* Status Packet */
-#define BITP_USB_EP0I_CSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP0I_CSR_H_TOERR             4                               /* Timeout Error */
-#define BITP_USB_EP0I_CSR_H_SETUPPKT          3                               /* Setup Packet */
-#define BITP_USB_EP0I_CSR_H_RXSTALL           2                               /* Rx Stall */
-#define BITP_USB_EP0I_CSR_H_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0I_CSR_H_NO_DISPING       (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0I_CSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0I_CSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0I_CSR_H_NO_DATATGL       (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0I_CSR_H_DATATGL          (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0I_CSR_H_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_H_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0I_CSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0I_CSR_H_STATUSPKT        (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_STATPKT       (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_STATPKT          (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0I_CSR_H_NO_TOERR         (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_SETUPPKT      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0I_CSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_RXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_RXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_RXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_RXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_H_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_AUTOREQ         14                               /* Auto Request Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_H_PIDERR          12                               /* Packet ID Error */
-#define BITP_USB_EPI_RXCSR_H_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_H_DATGLEN         10                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_RXCSR_H_DATGL            9                               /* Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_H_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_RXSTALL          6                               /* Rx STALL */
-#define BITP_USB_EPI_RXCSR_H_REQPKT           5                               /* Request Packet */
-#define BITP_USB_EPI_RXCSR_H_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_H_NAKTODERR        3                               /* NAK Timeout Data Error */
-#define BITP_USB_EPI_RXCSR_H_RXTOERR          2                               /* Rx Timeout Error */
-#define BITP_USB_EPI_RXCSR_H_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_H_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOREQ      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_PIDERR       (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_RXCSR_H_DATGLDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EPI_RXCSR_H_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_H_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_H_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_H_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EPI_RXCSR_H_NO_REQPKT       (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EPI_RXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_H_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_H_NAKTODERR       (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_NAKTO           (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EPI_RXCSR_H_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_H_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_H_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_P_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_P_ISO             14                               /* Isochronous Transfers */
-#define BITP_USB_EPI_RXCSR_P_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_P_DNYETPERR       12                               /* Disable NYET Handshake */
-#define BITP_USB_EPI_RXCSR_P_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_P_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_P_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_P_SENTSTALL        6                               /* Sent STALL */
-#define BITP_USB_EPI_RXCSR_P_SENDSTALL        5                               /* Send STALL */
-#define BITP_USB_EPI_RXCSR_P_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_P_DATAERR          3                               /* Data Error */
-#define BITP_USB_EPI_RXCSR_P_ORUNERR          2                               /* OUT Run Error */
-#define BITP_USB_EPI_RXCSR_P_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_P_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_P_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EPI_RXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EPI_RXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_P_DNYETPERR       (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERREN       (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERRDIS      (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_P_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_P_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_P_SENTSTALL       (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_STALSNT         (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_RXCSR_P_SENDSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_STALL           (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_P_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_DATAERR      (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_ORUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EPI_RXCSR_P_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_P_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_P_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CNT_RXCNT               0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0I_CNT_RXCNT              (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCNT_EPRXCNT            0                               /* EP Rx Count */
-#define BITM_USB_EPI_RXCNT_EPRXCNT           (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_TXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_TXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_TXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_TXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_TXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_TXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_TXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_TXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_TXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_TXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_TXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_TXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_TXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_TXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_TYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_TYPE_SPEED              0                               /* Speed of Operation Value */
-#define BITM_USB_EP0I_TYPE_SPEED             (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_NAKLIMIT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_NAKLIMIT_VALUE          0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0I_NAKLIMIT_VALUE         (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_RXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_RXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_RXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_RXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_RXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_RXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_RXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_RXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_RXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_RXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_RXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_RXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_RXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_RXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CFGDATA                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CFGDATA_MPRX            7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_MPTX            6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_BIGEND          5                               /* Big Endian Data */
-#define BITP_USB_EP0I_CFGDATA_HBRX            4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_HBTX            3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_DYNFIFO         2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0I_CFGDATA_SOFTCON         1                               /* Soft Connect Enable */
-#define BITP_USB_EP0I_CFGDATA_UTMIWID         0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0I_CFGDATA_MPRX           (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPRXEN         (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_MPTX           (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPTXEN         (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_BIGEND         (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDDIS      (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDEN       (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0I_CFGDATA_HBRX           (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0I_CFGDATA_HBRXEN         (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0I_CFGDATA_HBTX           (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0I_CFGDATA_HBTXEN         (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0I_CFGDATA_DYNFIFO        (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZDIS       (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZEN        (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0I_CFGDATA_SOFTCON        (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONDIS      (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONEN       (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0I_CFGDATA_UTMIWID        (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID8       (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID16      (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DEV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DEV_CTL_BDEVICE              7                               /* A or B Devices Indicator */
-#define BITP_USB_DEV_CTL_FSDEV                6                               /* Full or High-Speed Indicator */
-#define BITP_USB_DEV_CTL_LSDEV                5                               /* Low-Speed Indicator */
-#define BITP_USB_DEV_CTL_VBUS                 3                               /* VBUS Level Indicator */
-#define BITP_USB_DEV_CTL_HOSTMODE             2                               /* Host Mode Indicator */
-#define BITP_USB_DEV_CTL_HOSTREQ              1                               /* Host Negotiation Request */
-#define BITP_USB_DEV_CTL_SESSION              0                               /* Session Indicator */
-
-#define BITM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* A or B Devices Indicator */
-#define ENUM_USB_DEV_CTL_ADEVICE             (_ADI_MSK(0x00000000,uint8_t))   /* BDEVICE: A Device Detected */
-#define ENUM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* BDEVICE: B Device Detected */
-
-#define BITM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* Full or High-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_FSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* FSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* FSDEV: Full or High Speed Detected */
-
-#define BITM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* Low-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_LSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* LSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* LSDEV: Low Speed Detected */
-
-#define BITM_USB_DEV_CTL_VBUS                (_ADI_MSK(0x00000018,uint8_t))   /* VBUS Level Indicator */
-#define ENUM_USB_DEV_CTL_VBUS_BS             (_ADI_MSK(0x00000000,uint8_t))   /* VBUS: Below SessionEnd */
-#define ENUM_USB_DEV_CTL_VBUS_ASBA           (_ADI_MSK(0x00000008,uint8_t))   /* VBUS: Above SessionEnd, below AValid */
-#define ENUM_USB_DEV_CTL_VBUS_AABV           (_ADI_MSK(0x00000010,uint8_t))   /* VBUS: Above AValid, below VBUSValid */
-#define ENUM_USB_DEV_CTL_VBUS_AV             (_ADI_MSK(0x00000018,uint8_t))   /* VBUS: Above VBUSValid */
-
-#define BITM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* Host Mode Indicator */
-#define ENUM_USB_DEV_CTL_NO_HOSTMODE         (_ADI_MSK(0x00000000,uint8_t))   /* HOSTMODE: Peripheral Mode */
-#define ENUM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* HOSTMODE: Host Mode */
-
-#define BITM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* Host Negotiation Request */
-#define ENUM_USB_DEV_CTL_NO_HOSTREQ          (_ADI_MSK(0x00000000,uint8_t))   /* HOSTREQ: No Request */
-#define ENUM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* HOSTREQ: Place Request */
-
-#define BITM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* Session Indicator */
-#define ENUM_USB_DEV_CTL_NO_SESSION          (_ADI_MSK(0x00000000,uint8_t))   /* SESSION: Not Detected */
-#define ENUM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* SESSION: Detected Session */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_TXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_TXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_TXFIFOSZ_DPNDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_TXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_TXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_TXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_TXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_TXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_TXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_TXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_TXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_TXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_TXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_TXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_TXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_RXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_RXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_RXFIFOSZ_DPBDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_RXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_RXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_RXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_RXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_RXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_RXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_RXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_RXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_RXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_RXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_RXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_RXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOADDR_VALUE             0                               /* Tx FIFO Start Address */
-#define BITM_USB_TXFIFOADDR_VALUE            (_ADI_MSK(0x00001FFF,uint16_t))  /* Tx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOADDR_VALUE             0                               /* Rx FIFO Start Address */
-#define BITM_USB_RXFIFOADDR_VALUE            (_ADI_MSK(0x00000FFF,uint16_t))  /* Rx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPINFO                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPINFO_RXEP                  4                               /* Rx Endpoints */
-#define BITP_USB_EPINFO_TXEP                  0                               /* Tx Endpoints */
-#define BITM_USB_EPINFO_RXEP                 (_ADI_MSK(0x000000F0,uint8_t))   /* Rx Endpoints */
-#define BITM_USB_EPINFO_TXEP                 (_ADI_MSK(0x0000000F,uint8_t))   /* Tx Endpoints */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RAMINFO                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RAMINFO_DMACHANS             4                               /* DMA Channels */
-#define BITP_USB_RAMINFO_RAMBITS              0                               /* RAM Address Bits */
-#define BITM_USB_RAMINFO_DMACHANS            (_ADI_MSK(0x000000F0,uint8_t))   /* DMA Channels */
-#define BITM_USB_RAMINFO_RAMBITS             (_ADI_MSK(0x0000000F,uint8_t))   /* RAM Address Bits */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LINKINFO                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LINKINFO_WTCON               4                               /* Wait for Connect/Disconnect */
-#define BITP_USB_LINKINFO_WTID                0                               /* Wait from ID Pull-up */
-#define BITM_USB_LINKINFO_WTCON              (_ADI_MSK(0x000000F0,uint8_t))   /* Wait for Connect/Disconnect */
-#define BITM_USB_LINKINFO_WTID               (_ADI_MSK(0x0000000F,uint8_t))   /* Wait from ID Pull-up */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_SOFT_RST                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_SOFT_RST_RSTX                1                               /* Reset USB XCLK Domain */
-#define BITP_USB_SOFT_RST_RST                 0                               /* Reset USB CLK Domain */
-
-#define BITM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* Reset USB XCLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RSTX            (_ADI_MSK(0x00000000,uint8_t))   /* RSTX: No Reset */
-#define ENUM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* RSTX: Reset USB XCLK Domain */
-
-#define BITM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* Reset USB CLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RST             (_ADI_MSK(0x00000000,uint8_t))   /* RST: No Reset */
-#define ENUM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* RST: Reset USB CLK Domain */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXFUNCADDR_VALUE          0                               /* Tx Function Address Value */
-#define BITM_USB_MP_TXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Tx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_TXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_TXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_TXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_TXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXFUNCADDR_VALUE          0                               /* Rx Function Address Value */
-#define BITM_USB_MP_RXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Rx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_RXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_RXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_RXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_RXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_TXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_TXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_TXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_H                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_H_DISPING           11                               /* Disable Ping */
-#define BITP_USB_EP0_CSR_H_DATGLEN           10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0_CSR_H_DATGL              9                               /* Data Toggle */
-#define BITP_USB_EP0_CSR_H_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_H_NAKTO              7                               /* NAK Timeout */
-#define BITP_USB_EP0_CSR_H_STATUSPKT          6                               /* Status Packet */
-#define BITP_USB_EP0_CSR_H_REQPKT             5                               /* Request Packet */
-#define BITP_USB_EP0_CSR_H_TOERR              4                               /* Timeout Error */
-#define BITP_USB_EP0_CSR_H_SETUPPKT           3                               /* Setup Packet */
-#define BITP_USB_EP0_CSR_H_RXSTALL            2                               /* Rx Stall */
-#define BITP_USB_EP0_CSR_H_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_H_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0_CSR_H_NO_DISPING        (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0_CSR_H_NO_DATGLEN        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0_CSR_H_DATGL             (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0_CSR_H_NO_DATATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0_CSR_H_DATATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0_CSR_H_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_H_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_H_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0_CSR_H_NO_NAKTO          (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0_CSR_H_STATUSPKT         (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0_CSR_H_NO_STATPKT        (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_STATPKT           (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0_CSR_H_NO_REQPKT         (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0_CSR_H_NO_TOERR          (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0_CSR_H_NO_SETUPPKT       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0_CSR_H_NO_RXSTALL        (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_RXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_H_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_H_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_H_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_H_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_H_DATGLEN           9                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_TXCSR_H_DATGL             8                               /* Data Toggle */
-#define BITP_USB_EP_TXCSR_H_NAKTOINCMP        7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EP_TXCSR_H_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_H_RXSTALL           5                               /* Rx STALL */
-#define BITP_USB_EP_TXCSR_H_SETUPPKT          4                               /* Setup Packet */
-#define BITP_USB_EP_TXCSR_H_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_H_TXTOERR           2                               /* Tx Timeout Error */
-#define BITP_USB_EP_TXCSR_H_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_H_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_H_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EP_TXCSR_H_NAKTOINCMP       (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EP_TXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EP_TXCSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EP_TXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_TXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP_TXCSR_H_NO_SETUPPK       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EP_TXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_H_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EP_TXCSR_H_NO_TXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_NEFIFO        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_H_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_P                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_P_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_P_SSETUPEND          7                               /* Service Setup End */
-#define BITP_USB_EP0_CSR_P_SPKTRDY            6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0_CSR_P_SENDSTALL          5                               /* Send Stall */
-#define BITP_USB_EP0_CSR_P_SETUPEND           4                               /* Setup End */
-#define BITP_USB_EP0_CSR_P_DATAEND            3                               /* Data End */
-#define BITP_USB_EP0_CSR_P_SENTSTALL          2                               /* Sent Stall */
-#define BITP_USB_EP0_CSR_P_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_P_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_P_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_P_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_P_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0_CSR_P_NOSSETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_SPKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0_CSR_P_SENDSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALL          (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0_CSR_P_STALL             (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0_CSR_P_NO_SETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0_CSR_P_NO_DATAEND        (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0_CSR_P_SENTSTALL         (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALSNT        (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0_CSR_P_STALSNT           (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0_CSR_P_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_PKTRDY         (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_P_PKTRDY            (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_P_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_P_ISO              14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EP_TXCSR_P_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_P_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_P_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_P_INCOMPTX          7                               /* Incomplete Tx */
-#define BITP_USB_EP_TXCSR_P_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_P_SENTSTALL         5                               /* Sent STALL */
-#define BITP_USB_EP_TXCSR_P_SENDSTALL         4                               /* Send STALL */
-#define BITP_USB_EP_TXCSR_P_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_P_URUNERR           2                               /* Underrun Error */
-#define BITP_USB_EP_TXCSR_P_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_P_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_P_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EP_TXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EP_TXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_P_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_P_INCOMPTX         (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EP_TXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EP_TXCSR_P_INCOMP           (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EP_TXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_P_SENTSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_P_STALSNT          (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_TXCSR_P_SENDSTALL        (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EP_TXCSR_P_STALL            (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EP_TXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_P_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EP_TXCSR_P_NO_URUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EP_TXCSR_P_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FIFONE        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_P_FIFONE           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_P_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_RXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_RXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_RXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_H_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_H_AUTOREQ          14                               /* Auto Request Clear Enable */
-#define BITP_USB_EP_RXCSR_H_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_H_PIDERR           12                               /* Packet ID Error */
-#define BITP_USB_EP_RXCSR_H_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_RXCSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP_RXCSR_H_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_H_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_H_RXSTALL           6                               /* Rx STALL */
-#define BITP_USB_EP_RXCSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP_RXCSR_H_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_H_NAKTODERR         3                               /* NAK Timeout Data Error */
-#define BITP_USB_EP_RXCSR_H_RXTOERR           2                               /* Rx Timeout Error */
-#define BITP_USB_EP_RXCSR_H_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOREQ       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EP_RXCSR_H_NO_PIDERR        (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_RXCSR_H_DATGLDIS         (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP_RXCSR_H_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_H_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_H_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_H_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_RXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP_RXCSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP_RXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_H_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_H_NAKTODERR        (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EP_RXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_NAKTO            (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EP_RXCSR_H_NO_RXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EP_RXCSR_H_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_H_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_H_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_P_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_P_ISO              14                               /* Isochronous Transfers */
-#define BITP_USB_EP_RXCSR_P_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_P_DNYETPERR        12                               /* Disable NYET Handshake */
-#define BITP_USB_EP_RXCSR_P_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_P_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_P_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_P_SENTSTALL         6                               /* Sent STALL */
-#define BITP_USB_EP_RXCSR_P_SENDSTALL         5                               /* Send STALL */
-#define BITP_USB_EP_RXCSR_P_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_P_DATAERR           3                               /* Data Error */
-#define BITP_USB_EP_RXCSR_P_ORUNERR           2                               /* OUT Run Error */
-#define BITP_USB_EP_RXCSR_P_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_P_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EP_RXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EP_RXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_P_DNYETPERR        (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERREN        (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERRDIS       (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_P_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_P_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_P_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_P_SENTSTALL        (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_P_STALSNT          (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_RXCSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP_RXCSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EP_RXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_P_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EP_RXCSR_P_NO_DATAERR       (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EP_RXCSR_P_NO_ORUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EP_RXCSR_P_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_P_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_P_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CNT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CNT_RXCNT                0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0_CNT_RXCNT               (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCNT_EPRXCNT             0                               /* EP Rx Count */
-#define BITM_USB_EP_RXCNT_EPRXCNT            (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_TYPE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_TYPE_SPEED               0                               /* Speed of Operation Value */
-#define BITM_USB_EP0_TYPE_SPEED              (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_TXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_TXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_TXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_TXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_TXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_TXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_TXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_TXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_TXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_TXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_TXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_TXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_TXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_TXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_TXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_TXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_TXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_TXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_TXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_TXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_TXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_TXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_TXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_TXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_TXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_TXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_TXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_TXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_TXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_NAKLIMIT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_NAKLIMIT_VALUE           0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0_NAKLIMIT_VALUE          (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_RXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_RXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_RXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_RXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_RXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_RXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_RXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_RXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_RXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_RXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_RXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_RXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_RXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_RXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_RXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_RXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_RXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_RXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_RXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_RXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_RXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_RXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_RXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_RXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_RXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_RXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_RXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_RXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_RXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CFGDATA                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CFGDATA_MPRX             7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0_CFGDATA_MPTX             6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0_CFGDATA_BIGEND           5                               /* Big Endian Data */
-#define BITP_USB_EP0_CFGDATA_HBRX             4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0_CFGDATA_HBTX             3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0_CFGDATA_DYNFIFO          2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0_CFGDATA_SOFTCON          1                               /* Soft Connect Enable */
-#define BITP_USB_EP0_CFGDATA_UTMIWID          0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0_CFGDATA_MPRX            (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPRXEN          (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_MPTX            (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPTXEN          (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_BIGEND          (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0_CFGDATA_BIGENDDIS       (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0_CFGDATA_BIGENDEN        (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0_CFGDATA_HBRX            (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0_CFGDATA_HBRXEN          (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0_CFGDATA_HBTX            (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0_CFGDATA_HBTXEN          (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0_CFGDATA_DYNFIFO         (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0_CFGDATA_DYNSZDIS        (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0_CFGDATA_DYNSZEN         (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0_CFGDATA_SOFTCON         (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0_CFGDATA_SFTCONDIS       (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0_CFGDATA_SFTCONEN        (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0_CFGDATA_UTMIWID         (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID8        (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID16       (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_IRQ_D7                   7                               /* DMA 7 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D6                   6                               /* DMA 6 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D5                   5                               /* DMA 5 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D4                   4                               /* DMA 4 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D3                   3                               /* DMA 3 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D2                   2                               /* DMA 2 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D1                   1                               /* DMA 1 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D0                   0                               /* DMA 0 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D7                  (_ADI_MSK(0x00000080,uint8_t))   /* DMA 7 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D6                  (_ADI_MSK(0x00000040,uint8_t))   /* DMA 6 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D5                  (_ADI_MSK(0x00000020,uint8_t))   /* DMA 5 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D4                  (_ADI_MSK(0x00000010,uint8_t))   /* DMA 4 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D3                  (_ADI_MSK(0x00000008,uint8_t))   /* DMA 3 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D2                  (_ADI_MSK(0x00000004,uint8_t))   /* DMA 2 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D1                  (_ADI_MSK(0x00000002,uint8_t))   /* DMA 1 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D0                  (_ADI_MSK(0x00000001,uint8_t))   /* DMA 0 Interrupt Pending Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_CTL_BRSTM                9                               /* Burst Mode */
-#define BITP_USB_DMA_CTL_ERR                  8                               /* Bus Error */
-#define BITP_USB_DMA_CTL_EP                   4                               /* DMA Channel Endpoint Assignment */
-#define BITP_USB_DMA_CTL_IE                   3                               /* DMA Interrupt Enable */
-#define BITP_USB_DMA_CTL_MODE                 2                               /* DMA Mode */
-#define BITP_USB_DMA_CTL_DIR                  1                               /* DMA Transfer Direction */
-#define BITP_USB_DMA_CTL_EN                   0                               /* DMA Enable */
-
-#define BITM_USB_DMA_CTL_BRSTM               (_ADI_MSK(0x00000600,uint16_t))  /* Burst Mode */
-#define ENUM_USB_DMA_CTL_BRSTM00             (_ADI_MSK(0x00000000,uint16_t))  /* BRSTM: Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM01             (_ADI_MSK(0x00000200,uint16_t))  /* BRSTM: INCR4 or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM10             (_ADI_MSK(0x00000400,uint16_t))  /* BRSTM: INCR8, INCR4, or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM11             (_ADI_MSK(0x00000600,uint16_t))  /* BRSTM: INCR16, INCR8, INCR4, or Unspecified Length */
-
-#define BITM_USB_DMA_CTL_ERR                 (_ADI_MSK(0x00000100,uint16_t))  /* Bus Error */
-#define ENUM_USB_DMA_CTL_NO_DMAERR           (_ADI_MSK(0x00000000,uint16_t))  /* ERR: No Status */
-#define ENUM_USB_DMA_CTL_DMAERR              (_ADI_MSK(0x00000100,uint16_t))  /* ERR: Bus Error */
-
-#define BITM_USB_DMA_CTL_EP                  (_ADI_MSK(0x000000F0,uint16_t))  /* DMA Channel Endpoint Assignment */
-#define ENUM_USB_DMA_CTL_DMAEP0              (_ADI_MSK(0x00000000,uint16_t))  /* EP: Endpoint 0 */
-#define ENUM_USB_DMA_CTL_DMAEP1              (_ADI_MSK(0x00000010,uint16_t))  /* EP: Endpoint 1 */
-#define ENUM_USB_DMA_CTL_DMAEP10             (_ADI_MSK(0x000000A0,uint16_t))  /* EP: Endpoint 10 */
-#define ENUM_USB_DMA_CTL_DMAEP11             (_ADI_MSK(0x000000B0,uint16_t))  /* EP: Endpoint 11 */
-#define ENUM_USB_DMA_CTL_DMAEP12             (_ADI_MSK(0x000000C0,uint16_t))  /* EP: Endpoint 12 */
-#define ENUM_USB_DMA_CTL_DMAEP13             (_ADI_MSK(0x000000D0,uint16_t))  /* EP: Endpoint 13 */
-#define ENUM_USB_DMA_CTL_DMAEP14             (_ADI_MSK(0x000000E0,uint16_t))  /* EP: Endpoint 14 */
-#define ENUM_USB_DMA_CTL_DMAEP15             (_ADI_MSK(0x000000F0,uint16_t))  /* EP: Endpoint 15 */
-#define ENUM_USB_DMA_CTL_DMAEP2              (_ADI_MSK(0x00000020,uint16_t))  /* EP: Endpoint 2 */
-#define ENUM_USB_DMA_CTL_DMAEP3              (_ADI_MSK(0x00000030,uint16_t))  /* EP: Endpoint 3 */
-#define ENUM_USB_DMA_CTL_DMAEP4              (_ADI_MSK(0x00000040,uint16_t))  /* EP: Endpoint 4 */
-#define ENUM_USB_DMA_CTL_DMAEP5              (_ADI_MSK(0x00000050,uint16_t))  /* EP: Endpoint 5 */
-#define ENUM_USB_DMA_CTL_DMAEP6              (_ADI_MSK(0x00000060,uint16_t))  /* EP: Endpoint 6 */
-#define ENUM_USB_DMA_CTL_DMAEP7              (_ADI_MSK(0x00000070,uint16_t))  /* EP: Endpoint 7 */
-#define ENUM_USB_DMA_CTL_DMAEP8              (_ADI_MSK(0x00000080,uint16_t))  /* EP: Endpoint 8 */
-#define ENUM_USB_DMA_CTL_DMAEP9              (_ADI_MSK(0x00000090,uint16_t))  /* EP: Endpoint 9 */
-
-#define BITM_USB_DMA_CTL_IE                  (_ADI_MSK(0x00000008,uint16_t))  /* DMA Interrupt Enable */
-#define ENUM_USB_DMA_CTL_DMAINTDIS           (_ADI_MSK(0x00000000,uint16_t))  /* IE: Disable Interrupt */
-#define ENUM_USB_DMA_CTL_DMAINTEN            (_ADI_MSK(0x00000008,uint16_t))  /* IE: Enable Interrupt */
-
-#define BITM_USB_DMA_CTL_MODE                (_ADI_MSK(0x00000004,uint16_t))  /* DMA Mode */
-#define ENUM_USB_DMA_CTL_DMAMODE0            (_ADI_MSK(0x00000000,uint16_t))  /* MODE: DMA Mode 0 */
-#define ENUM_USB_DMA_CTL_DMAMODE1            (_ADI_MSK(0x00000004,uint16_t))  /* MODE: DMA Mode 1 */
-
-#define BITM_USB_DMA_CTL_DIR                 (_ADI_MSK(0x00000002,uint16_t))  /* DMA Transfer Direction */
-#define ENUM_USB_DMA_CTL_DMADIR_RX           (_ADI_MSK(0x00000000,uint16_t))  /* DIR: DMA Write (for Rx Endpoint) */
-#define ENUM_USB_DMA_CTL_DMADIR_TX           (_ADI_MSK(0x00000002,uint16_t))  /* DIR: DMA Read (for Tx Endpoint) */
-
-#define BITM_USB_DMA_CTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* DMA Enable */
-#define ENUM_USB_DMA_CTL_DMADIS              (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable DMA */
-#define ENUM_USB_DMA_CTL_DMAEN               (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable DMA (Start Transfer) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_UCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_UCH_VALUE                 0                               /* Chirp Timeout Value */
-#define BITM_USB_CT_UCH_VALUE                (_ADI_MSK(0x00007FFF,uint16_t))  /* Chirp Timeout Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HHSRTN                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HHSRTN_VALUE              0                               /* Host High Speed Return to Normal Value */
-#define BITM_USB_CT_HHSRTN_VALUE             (_ADI_MSK(0x00007FFF,uint16_t))  /* Host High Speed Return to Normal Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HSBT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HSBT_VALUE                0                               /* HS Timeout Adder */
-#define BITM_USB_CT_HSBT_VALUE               (_ADI_MSK(0x0000000F,uint16_t))  /* HS Timeout Adder */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_ATTR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_ATTR_EP                 12                               /* Endpoint */
-#define BITP_USB_LPM_ATTR_RMTWAK              8                               /* Remote Wakeup Enable */
-#define BITP_USB_LPM_ATTR_HIRD                4                               /* Host Initiated Resume Duration */
-#define BITP_USB_LPM_ATTR_LINKSTATE           0                               /* Link State */
-#define BITM_USB_LPM_ATTR_EP                 (_ADI_MSK(0x0000F000,uint16_t))  /* Endpoint */
-
-#define BITM_USB_LPM_ATTR_RMTWAK             (_ADI_MSK(0x00000100,uint16_t))  /* Remote Wakeup Enable */
-#define ENUM_USB_LPM_ATTR_RMTWAKDIS          (_ADI_MSK(0x00000000,uint16_t))  /* RMTWAK: Disable Remote Wakeup */
-#define ENUM_USB_LPM_ATTR_RMTWAKEN           (_ADI_MSK(0x00000100,uint16_t))  /* RMTWAK: Enable Remote Wakeup */
-#define BITM_USB_LPM_ATTR_HIRD               (_ADI_MSK(0x000000F0,uint16_t))  /* Host Initiated Resume Duration */
-
-#define BITM_USB_LPM_ATTR_LINKSTATE          (_ADI_MSK(0x0000000F,uint16_t))  /* Link State */
-#define ENUM_USB_LPM_ATTR_LNKSTATE_SSL1      (_ADI_MSK(0x00000001,uint16_t))  /* LINKSTATE: Sleep State (L1) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_CTL_NAK                  4                               /* LPM NAK Enable */
-#define BITP_USB_LPM_CTL_EN                   2                               /* LPM Enable */
-#define BITP_USB_LPM_CTL_RESUME               1                               /* LPM Resume (Remote Wakeup) */
-#define BITP_USB_LPM_CTL_TX                   0                               /* LPM Transmit */
-#define BITM_USB_LPM_CTL_NAK                 (_ADI_MSK(0x00000010,uint8_t))   /* LPM NAK Enable */
-#define BITM_USB_LPM_CTL_EN                  (_ADI_MSK(0x0000000C,uint8_t))   /* LPM Enable */
-#define BITM_USB_LPM_CTL_RESUME              (_ADI_MSK(0x00000002,uint8_t))   /* LPM Resume (Remote Wakeup) */
-#define BITM_USB_LPM_CTL_TX                  (_ADI_MSK(0x00000001,uint8_t))   /* LPM Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IEN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IEN_LPMERR               5                               /* LPM Error Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMRES               4                               /* LPM Resume Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNC                3                               /* LPM NYET Control Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMACK               2                               /* LPM ACK Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNY                1                               /* LPM NYET Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMST                0                               /* LPM STALL Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMST               (_ADI_MSK(0x00000001,uint8_t))   /* LPM STALL Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IRQ_LPMERR               5                               /* LPM Error Interrupt */
-#define BITP_USB_LPM_IRQ_LPMRES               4                               /* LPM Resume Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNC                3                               /* LPM NYET Control Interrupt */
-#define BITP_USB_LPM_IRQ_LPMACK               2                               /* LPM ACK Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNY                1                               /* LPM NYET Interrupt */
-#define BITP_USB_LPM_IRQ_LPMST                0
-#define BITM_USB_LPM_IRQ_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt */
-#define BITM_USB_LPM_IRQ_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt */
-#define BITM_USB_LPM_IRQ_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt */
-#define BITM_USB_LPM_IRQ_LPMST               (_ADI_MSK(0x00000001,uint8_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_FADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_FADDR_VALUE              0                               /* Function Address Value */
-#define BITM_USB_LPM_FADDR_VALUE             (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_VBUS_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_VBUS_CTL_DRV                 4                               /* VBUS Drive */
-#define BITP_USB_VBUS_CTL_DRVINT              3                               /* VBUS Drive Interrupt */
-#define BITP_USB_VBUS_CTL_DRVIEN              2                               /* VBUS Drive Interrupt Enable */
-#define BITP_USB_VBUS_CTL_DRVOD               1                               /* VBUS Drive Open Drain */
-#define BITP_USB_VBUS_CTL_INVDRV              0                               /* VBUS Invert Drive */
-#define BITM_USB_VBUS_CTL_DRV                (_ADI_MSK(0x00000010,uint8_t))   /* VBUS Drive */
-#define BITM_USB_VBUS_CTL_DRVINT             (_ADI_MSK(0x00000008,uint8_t))   /* VBUS Drive Interrupt */
-#define BITM_USB_VBUS_CTL_DRVIEN             (_ADI_MSK(0x00000004,uint8_t))   /* VBUS Drive Interrupt Enable */
-#define BITM_USB_VBUS_CTL_DRVOD              (_ADI_MSK(0x00000002,uint8_t))   /* VBUS Drive Open Drain */
-#define BITM_USB_VBUS_CTL_INVDRV             (_ADI_MSK(0x00000001,uint8_t))   /* VBUS Invert Drive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_BAT_CHG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_BAT_CHG_DEDCHG               4                               /* Dedicated Charging Port */
-#define BITP_USB_BAT_CHG_CHGDET               3                               /* Charging Port Detected */
-#define BITP_USB_BAT_CHG_SNSCHGDET            2                               /* Sense Charger Detection */
-#define BITP_USB_BAT_CHG_CONDET               1                               /* Connected Detected */
-#define BITP_USB_BAT_CHG_SNSCONDET            0                               /* Sense Connection Detection */
-#define BITM_USB_BAT_CHG_DEDCHG              (_ADI_MSK(0x00000010,uint8_t))   /* Dedicated Charging Port */
-#define BITM_USB_BAT_CHG_CHGDET              (_ADI_MSK(0x00000008,uint8_t))   /* Charging Port Detected */
-#define BITM_USB_BAT_CHG_SNSCHGDET           (_ADI_MSK(0x00000004,uint8_t))   /* Sense Charger Detection */
-#define BITM_USB_BAT_CHG_CONDET              (_ADI_MSK(0x00000002,uint8_t))   /* Connected Detected */
-#define BITM_USB_BAT_CHG_SNSCONDET           (_ADI_MSK(0x00000001,uint8_t))   /* Sense Connection Detection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PHY_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PHY_CTL_EN                   7                               /* PHY Enable */
-#define BITP_USB_PHY_CTL_RESTORE              1                               /* Restore from Hibernate */
-#define BITP_USB_PHY_CTL_HIBER                0                               /* Hibernate */
-#define BITM_USB_PHY_CTL_EN                  (_ADI_MSK(0x00000080,uint8_t))   /* PHY Enable */
-#define BITM_USB_PHY_CTL_RESTORE             (_ADI_MSK(0x00000002,uint8_t))   /* Restore from Hibernate */
-#define BITM_USB_PHY_CTL_HIBER               (_ADI_MSK(0x00000001,uint8_t))   /* Hibernate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PLL_OSC                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PLL_OSC_PLLMSEL              7                               /* PLL Multiplier Select */
-#define BITP_USB_PLL_OSC_PLLM                 1                               /* PLL Multiplier Value */
-#define BITP_USB_PLL_OSC_DIVCLKIN             0                               /* Divide CLKIN */
-#define BITM_USB_PLL_OSC_PLLMSEL             (_ADI_MSK(0x00000080,uint16_t))  /* PLL Multiplier Select */
-#define BITM_USB_PLL_OSC_PLLM                (_ADI_MSK(0x0000007E,uint16_t))  /* PLL Multiplier Value */
-#define BITM_USB_PLL_OSC_DIVCLKIN            (_ADI_MSK(0x00000001,uint16_t))  /* Divide CLKIN */
-
-/* ==================================================
-        Data Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1DM0
-   ========================= */
-#define SRAM_BASE_ADDRESS               0xFFE00000         /* SRAM Base Address */
-#define DMEM_CONTROL                    0xFFE00004         /* Data memory control */
-#define DCPLB_STATUS                    0xFFE00008         /* Data Cacheability Protection Lookaside Buffer Status */
-#define DCPLB_FAULT_STATUS              0xFFE00008         /*     Older definition or alias of above */
-#define DCPLB_FAULT_ADDR                0xFFE0000C         /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define DCPLB_ADDR0                     0xFFE00100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR1                     0xFFE00104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR2                     0xFFE00108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR3                     0xFFE0010C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR4                     0xFFE00110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR5                     0xFFE00114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR6                     0xFFE00118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR7                     0xFFE0011C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR8                     0xFFE00120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR9                     0xFFE00124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR10                    0xFFE00128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR11                    0xFFE0012C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR12                    0xFFE00130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR13                    0xFFE00134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR14                    0xFFE00138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR15                    0xFFE0013C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_DATA0                     0xFFE00200         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA1                     0xFFE00204         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA2                     0xFFE00208         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA3                     0xFFE0020C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA4                     0xFFE00210         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA5                     0xFFE00214         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA6                     0xFFE00218         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA7                     0xFFE0021C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA8                     0xFFE00220         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA9                     0xFFE00224         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA10                    0xFFE00228         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA11                    0xFFE0022C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA12                    0xFFE00230         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA13                    0xFFE00234         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA14                    0xFFE00238         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA15                    0xFFE0023C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DTEST_COMMAND                   0xFFE00300         /* Data Test Command Register */
-#define DTEST_DATA0                     0xFFE00400         /* Data Test Data Register */
-#define DTEST_DATA1                     0xFFE00404         /* Data Test Data Register */
-#define L1DBNKA_PELOC                   0xFFE00408         /* Data Bank A Parity Error Location */
-#define L1DBNKB_PELOC                   0xFFE0040C         /* Data Bank B Parity Error Location */
-
-/* =========================
-        L1DM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SRAM_BASE_ADDRESS                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SRAM_BASE_ADDRESS_ADDR          22                               /* SRAM Base Address */
-#define BITM_SRAM_BASE_ADDRESS_ADDR          (_ADI_MSK(0xFFC00000,uint32_t))  /* SRAM Base Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMEM_CONTROL_PARCTL             15                               /* L1 Scratch Parity Control */
-#define BITP_DMEM_CONTROL_PARSEL             14                               /* L1 Scratch Parity Select */
-#define BITP_DMEM_CONTROL_PPREF1             13                               /* DAG1 Port Preference */
-#define BITP_DMEM_CONTROL_PPREF0             12                               /* DAG0 Port Preference */
-#define BITP_DMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_DMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_DMEM_CONTROL_DCBS                4                               /* L1 Data Cache Bank Select */
-#define BITP_DMEM_CONTROL_CFG                 2                               /* Data Memory Configuration */
-#define BITP_DMEM_CONTROL_ENCPLB              1                               /* Enable DCPLB */
-
-#define BITM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* L1 Scratch Parity Control */
-#define ENUM_DMEM_CONTROL_NO_PARCTL          (_ADI_MSK(0x00000000,uint32_t))  /* PARCTL: No Parity Control  (Normal Behavior for L1 RD / L1 WT) */
-#define ENUM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* PARCTL: Parity Control Enabled */
-#define BITM_DMEM_CONTROL_PARSEL             (_ADI_MSK(0x00004000,uint32_t))  /* L1 Scratch Parity Select */
-
-#define BITM_DMEM_CONTROL_PPREF1             (_ADI_MSK(0x00002000,uint32_t))  /* DAG1 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF1A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF1B            (_ADI_MSK(0x00002000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_PPREF0             (_ADI_MSK(0x00001000,uint32_t))  /* DAG0 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF0A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF0B            (_ADI_MSK(0x00001000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_DMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_DMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_DMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_DMEM_CONTROL_DCBS               (_ADI_MSK(0x00000010,uint32_t))  /* L1 Data Cache Bank Select */
-#define ENUM_DMEM_CONTROL_DCBS14             (_ADI_MSK(0x00000000,uint32_t))  /* DCBS: Address bit 14 used to select Bank A or B for cache access */
-#define ENUM_DMEM_CONTROL_DCBS23             (_ADI_MSK(0x00000010,uint32_t))  /* DCBS: Address bit 23 used to select Bank A or B for cache access */
-
-#define BITM_DMEM_CONTROL_CFG                (_ADI_MSK(0x0000000C,uint32_t))  /* Data Memory Configuration */
-#define ENUM_DMEM_CONTROL_ASRAM_BSRAM        (_ADI_MSK(0x00000000,uint32_t))  /* CFG: A SRAM, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BSRAM       (_ADI_MSK(0x00000008,uint32_t))  /* CFG: A Cache, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BCACHE      (_ADI_MSK(0x0000000C,uint32_t))  /* CFG: A Cache, B Cache */
-
-#define BITM_DMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable DCPLB */
-#define ENUM_DMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs Disabled */
-#define ENUM_DMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs Enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_DCPLB_STATUS_DAG                18                               /* Access DAG */
-#define BITP_DCPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_DCPLB_STATUS_RW                 16                               /* Access Read/Write */
-#define BITP_DCPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_DCPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_DCPLB_STATUS_DAG                (_ADI_MSK(0x00040000,uint32_t))  /* Access DAG */
-#define BITM_DCPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_DCPLB_STATUS_RW                 (_ADI_MSK(0x00010000,uint32_t))  /* Access Read/Write */
-#define BITM_DCPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_DCPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_DCPLB_DATA_WT                   14                               /* CPLB Write Through */
-#define BITP_DCPLB_DATA_L2_CHBL              13                               /* CPLB L2 Cacheable */
-#define BITP_DCPLB_DATA_L1_CHBL              12                               /* CPLB L1 Cacheable */
-#define BITP_DCPLB_DATA_DIRTY                 7                               /* CPLB DIRTY */
-#define BITP_DCPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_DCPLB_DATA_SWRITE                4                               /* CPLB Supervisor Write */
-#define BITP_DCPLB_DATA_UWRITE                3                               /* CPLB User Write */
-#define BITP_DCPLB_DATA_UREAD                 2                               /* CPLB User Read */
-#define BITP_DCPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_DCPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_DCPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_DCPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_DCPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_DCPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_DCPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_DCPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_DCPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_DCPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_DCPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* CPLB Write Through */
-#define ENUM_DCPLB_DATA_WB                   (_ADI_MSK(0x00000000,uint32_t))  /* WT: Write-back */
-#define ENUM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* WT: Write-through */
-
-#define BITM_DCPLB_DATA_L2_CHBL              (_ADI_MSK(0x00002000,uint32_t))  /* CPLB L2 Cacheable */
-#define ENUM_DCPLB_DATA_L2CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L2CHBL: Non-cacheable in L2 */
-#define ENUM_DCPLB_DATA_L2CHBL_EN            (_ADI_MSK(0x00002000,uint32_t))  /* L2CHBL: Cacheable in L2 */
-
-#define BITM_DCPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* CPLB L1 Cacheable */
-#define ENUM_DCPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_DCPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* CPLB DIRTY */
-#define ENUM_DCPLB_DATA_CLEAN                (_ADI_MSK(0x00000000,uint32_t))  /* DIRTY: Clean */
-#define ENUM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* DIRTY: Dirty */
-#define BITM_DCPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* CPLB Supervisor Write */
-#define ENUM_DCPLB_DATA_NO_SWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* SWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* SWRITE: Write Access Allowed (Supervisor Mode) */
-
-#define BITM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* CPLB User Write */
-#define ENUM_DCPLB_DATA_NO_UWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* UWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* UWRITE: Write Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* CPLB User Read */
-#define ENUM_DCPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_DCPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_DCPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_DCPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid Entry */
-#define ENUM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DTEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DTEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_DTEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_DTEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bit 11 */
-#define BITP_DTEST_COMMAND_IDSEL             24                               /* Instruction/Data Access */
-#define BITP_DTEST_COMMAND_BNKSEL            23                               /* Data Bank Access */
-#define BITP_DTEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_DTEST_COMMAND_SEL16K            14                               /* Address bit 14 */
-#define BITP_DTEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_DTEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_DTEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_DTEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_DTEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_DTEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_DTEST_COMMAND_WAYSEL            (_ADI_MSK(0x04000000,uint32_t))  /* Access Way/Instruction Address Bit 11 */
-#define BITM_DTEST_COMMAND_IDSEL             (_ADI_MSK(0x01000000,uint32_t))  /* Instruction/Data Access */
-#define BITM_DTEST_COMMAND_BNKSEL            (_ADI_MSK(0x00800000,uint32_t))  /* Data Bank Access */
-#define BITM_DTEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_DTEST_COMMAND_SEL16K            (_ADI_MSK(0x00004000,uint32_t))  /* Address bit 14 */
-#define BITM_DTEST_COMMAND_SET               (_ADI_MSK(0x000007E0,uint32_t))  /* Set Index */
-#define BITM_DTEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_DTEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_DTEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKA_PELOC_SCRATCH_MEM       12                               /* Scratch Memory Parity Status */
-#define BITP_L1DBNKA_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_SCRATCH_MEM       (_ADI_MSK(0x00001000,uint32_t))  /* Scratch Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKB_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKB_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Instruction Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1IM0
-   ========================= */
-#define IMEM_CONTROL                    0xFFE01004         /* Instruction memory control */
-#define ICPLB_STATUS                    0xFFE01008         /* Cacheability Protection Lookaside Buffer Status */
-#define CODE_FAULT_STATUS               0xFFE01008         /*     Older definition or alias of above */
-#define ICPLB_FAULT_ADDR                0xFFE0100C         /* Cacheability Protection Lookaside Buffer Fault Address */
-#define CODE_FAULT_ADDR                 0xFFE0100C         /*     Older definition or alias of above */
-#define ICPLB_ADDR0                     0xFFE01100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR1                     0xFFE01104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR2                     0xFFE01108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR3                     0xFFE0110C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR4                     0xFFE01110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR5                     0xFFE01114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR6                     0xFFE01118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR7                     0xFFE0111C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR8                     0xFFE01120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR9                     0xFFE01124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR10                    0xFFE01128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR11                    0xFFE0112C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR12                    0xFFE01130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR13                    0xFFE01134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR14                    0xFFE01138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR15                    0xFFE0113C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_DATA0                     0xFFE01200         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA1                     0xFFE01204         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA2                     0xFFE01208         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA3                     0xFFE0120C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA4                     0xFFE01210         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA5                     0xFFE01214         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA6                     0xFFE01218         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA7                     0xFFE0121C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA8                     0xFFE01220         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA9                     0xFFE01224         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA10                    0xFFE01228         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA11                    0xFFE0122C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA12                    0xFFE01230         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA13                    0xFFE01234         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA14                    0xFFE01238         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA15                    0xFFE0123C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ITEST_COMMAND                   0xFFE01300         /* Instruction Test Command Register */
-#define ITEST_DATA0                     0xFFE01400         /* Instruction Test Data Register */
-#define ITEST_DATA1                     0xFFE01404         /* Instruction Test Data Register */
-#define L1IBNKA_PELOC                   0xFFE01408         /* Instruction Bank A Parity Error Location */
-#define L1IBNKB_PELOC                   0xFFE0140C         /* Instruction Bank B Parity Error Location */
-#define L1IBNKC_PELOC                   0xFFE01410         /* Instruction Bank C Parity Error Location */
-
-/* =========================
-        L1IM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMEM_CONTROL_LRUPRIORST         13                               /* LRU Priority Reset */
-#define BITP_IMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_IMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_IMEM_CONTROL_LOC                 3                               /* Cache Way Lock */
-#define BITP_IMEM_CONTROL_CFG                 2                               /* Configure L1 code memory as cache */
-#define BITP_IMEM_CONTROL_ENCPLB              1                               /* Enable ICPLB */
-
-#define BITM_IMEM_CONTROL_LRUPRIORST         (_ADI_MSK(0x00002000,uint32_t))  /* LRU Priority Reset */
-#define ENUM_IMEM_CONTROL_LRUPRIO_EN         (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIORST: LRU Priority functionality is enabled */
-#define ENUM_IMEM_CONTROL_LRUPRIO_CLR        (_ADI_MSK(0x00002000,uint32_t))  /* LRUPRIORST: All cached LRU priority bits are cleared */
-
-#define BITM_IMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_IMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_IMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_IMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_IMEM_CONTROL_LOC                (_ADI_MSK(0x00000078,uint32_t))  /* Cache Way Lock */
-#define ENUM_IMEM_CONTROL_WAYLOCK_NONE       (_ADI_MSK(0x00000000,uint32_t))  /* LOC: All Ways Not Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_0          (_ADI_MSK(0x00000008,uint32_t))  /* LOC: Way3, Way2, Way1 Not Locked, Way0 Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_ALL        (_ADI_MSK(0x00000078,uint32_t))  /* LOC: All Ways Locked */
-
-#define BITM_IMEM_CONTROL_CFG                (_ADI_MSK(0x00000004,uint32_t))  /* Configure L1 code memory as cache */
-#define ENUM_IMEM_CONTROL_CFG_SRAM           (_ADI_MSK(0x00000000,uint32_t))  /* CFG: L1 Instruction Memory Configured as SRAM */
-#define ENUM_IMEM_CONTROL_CFG_CACHE          (_ADI_MSK(0x00000004,uint32_t))  /* CFG: L1 Instruction Memory Configures as Cache */
-
-#define BITM_IMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable ICPLB */
-#define ENUM_IMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs disabled */
-#define ENUM_IMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_ICPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_ICPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_ICPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_ICPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_ICPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_ICPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_ICPLB_DATA_L1_CHBL              12                               /* L1 Cacheable */
-#define BITP_ICPLB_DATA_LRUPRIO               8                               /* Least Recently Used Priority */
-#define BITP_ICPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_ICPLB_DATA_UREAD                 2                               /* Allow User Read */
-#define BITP_ICPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_ICPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_ICPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_ICPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_ICPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_ICPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_ICPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_ICPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_ICPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_ICPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_ICPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_ICPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* L1 Cacheable */
-#define ENUM_ICPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_ICPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_ICPLB_DATA_LRUPRIO              (_ADI_MSK(0x00000100,uint32_t))  /* Least Recently Used Priority */
-#define ENUM_ICPLB_DATA_LRUPRIO_LO           (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIO: Low Importance */
-#define ENUM_ICPLB_DATA_LRUPRIO_HI           (_ADI_MSK(0x00000100,uint32_t))  /* LRUPRIO: High Importance */
-#define BITM_ICPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* Allow User Read */
-#define ENUM_ICPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_ICPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_ICPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_ICPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_ICPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid (disabled) CPLB Entry */
-#define ENUM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid (enabled) CPLB Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ITEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ITEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_ITEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_ITEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bits 11:10 */
-#define BITP_ITEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_ITEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_ITEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_ITEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_ITEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_ITEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_ITEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_ITEST_COMMAND_WAYSEL            (_ADI_MSK(0x0C000000,uint32_t))  /* Access Way/Instruction Address Bits 11:10 */
-#define BITM_ITEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_ITEST_COMMAND_SET               (_ADI_MSK(0x000003E0,uint32_t))  /* Set Index */
-#define BITM_ITEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_ITEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_ITEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKC_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKC_PELOC_TAGPAIR            4                               /* Tag Parity Status */
-#define BITP_L1IBNKC_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKC_PELOC_TAGPAIR           (_ADI_MSK(0x00000030,uint32_t))  /* Tag Parity Status */
-#define BITM_L1IBNKC_PELOC_MEMBLK            (_ADI_MSK(0x0000000F,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Interrupt Controller Registers
-   ================================================== */
-
-/* =========================
-        ICU0
-   ========================= */
-#define EVT0                            0xFFE02000         /* Event Vector */
-#define EVT1                            0xFFE02004         /* Event Vector */
-#define EVT2                            0xFFE02008         /* Event Vector */
-#define EVT3                            0xFFE0200C         /* Event Vector */
-#define EVT4                            0xFFE02010         /* Event Vector */
-#define EVT5                            0xFFE02014         /* Event Vector */
-#define EVT6                            0xFFE02018         /* Event Vector */
-#define EVT7                            0xFFE0201C         /* Event Vector */
-#define EVT8                            0xFFE02020         /* Event Vector */
-#define EVT9                            0xFFE02024         /* Event Vector */
-#define EVT10                           0xFFE02028         /* Event Vector */
-#define EVT11                           0xFFE0202C         /* Event Vector */
-#define EVT12                           0xFFE02030         /* Event Vector */
-#define EVT13                           0xFFE02034         /* Event Vector */
-#define EVT14                           0xFFE02038         /* Event Vector */
-#define EVT15                           0xFFE0203C         /* Event Vector */
-#define IMASK                           0xFFE02104         /* Interrupt Mask Register */
-#define IPEND                           0xFFE02108         /* Interrupts Pending Register */
-#define ILAT                            0xFFE0210C         /* Interrupt Latch Register */
-#define IPRIO                           0xFFE02110         /* Interrupt Priority Register */
-#define CEC_SID                         0xFFE02118         /* Core System Interrupt ID */
-
-/* =========================
-        ICU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMASK                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMASK_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IMASK_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IMASK_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IMASK_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IMASK_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IMASK_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IMASK_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IMASK_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IMASK_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IMASK_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IMASK_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IMASK_UNMASKABLE                 0                               /* Unmaskable interrupts */
-#define BITM_IMASK_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IMASK_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IMASK_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IMASK_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IMASK_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IMASK_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IMASK_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IMASK_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IMASK_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IMASK_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IMASK_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IMASK_UNMASKABLE                (_ADI_MSK(0x0000001F,uint32_t))  /* Unmaskable interrupts */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPEND                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPEND_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IPEND_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IPEND_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IPEND_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IPEND_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IPEND_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IPEND_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IPEND_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IPEND_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IPEND_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IPEND_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IPEND_IRPTEN                     4                               /* Global interrupt enable bit position */
-#define BITP_IPEND_EVX                        3                               /* Exception bit position */
-#define BITP_IPEND_NMI                        2                               /* Non Maskable interrupt bit position */
-#define BITP_IPEND_RST                        1                               /* Reset interrupt bit position */
-#define BITP_IPEND_EMU                        0                               /* Emulator interrupt bit position */
-#define BITM_IPEND_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IPEND_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IPEND_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IPEND_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IPEND_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IPEND_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IPEND_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IPEND_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IPEND_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IPEND_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IPEND_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IPEND_IRPTEN                    (_ADI_MSK(0x00000010,uint32_t))  /* Global interrupt enable bit position */
-#define BITM_IPEND_EVX                       (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_IPEND_NMI                       (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_IPEND_RST                       (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_IPEND_EMU                       (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ILAT                                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ILAT_IVG15                      15                               /* IVG15 interrupt bit position */
-#define BITP_ILAT_IVG14                      14                               /* IVG14 interrupt bit position */
-#define BITP_ILAT_IVG13                      13                               /* IVG13 interrupt bit position */
-#define BITP_ILAT_IVG12                      12                               /* IVG12 interrupt bit position */
-#define BITP_ILAT_IVG11                      11                               /* IVG11 interrupt bit position */
-#define BITP_ILAT_IVG10                      10                               /* IVG10 interrupt bit position */
-#define BITP_ILAT_IVG9                        9                               /* IVG9 interrupt bit position */
-#define BITP_ILAT_IVG8                        8                               /* IVG8 interrupt bit position */
-#define BITP_ILAT_IVG7                        7                               /* IVG7 interrupt bit position */
-#define BITP_ILAT_IVTMR                       6                               /* Timer interrupt bit position */
-#define BITP_ILAT_IVHW                        5                               /* Hardware Error interrupt bit position */
-#define BITP_ILAT_EVX                         3                               /* Exception bit position */
-#define BITP_ILAT_NMI                         2                               /* Non Maskable interrupt bit position */
-#define BITP_ILAT_RST                         1                               /* Reset interrupt bit position */
-#define BITP_ILAT_EMU                         0                               /* Emulator interrupt bit position */
-#define BITM_ILAT_IVG15                      (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_ILAT_IVG14                      (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_ILAT_IVG13                      (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_ILAT_IVG12                      (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_ILAT_IVG11                      (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_ILAT_IVG10                      (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_ILAT_IVG9                       (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_ILAT_IVG8                       (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_ILAT_IVG7                       (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_ILAT_IVTMR                      (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_ILAT_IVHW                       (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_ILAT_EVX                        (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_ILAT_NMI                        (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_ILAT_RST                        (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_ILAT_EMU                        (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPRIO                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPRIO_IPRIO_MARK                 0                               /* Priority Watermark */
-#define BITM_IPRIO_IPRIO_MARK                (_ADI_MSK(0x0000000F,uint32_t))  /* Priority Watermark */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CEC_SID                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CEC_SID_SID                      0                               /* System Interrupt ID */
-#define BITM_CEC_SID_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* System Interrupt ID */
-
-/* ==================================================
-        Core Timer Registers
-   ================================================== */
-
-/* =========================
-        TMR0
-   ========================= */
-#define TCNTL                           0xFFE03000         /* Timer Control Register */
-#define TPERIOD                         0xFFE03004         /* Timer Period Register */
-#define TSCALE                          0xFFE03008         /* Timer Scale Register */
-#define TCOUNT                          0xFFE0300C         /* Timer Count Register */
-
-/* =========================
-        TMR
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TCNTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TCNTL_INT                        3                               /* Interrupt Status (sticky) */
-#define BITP_TCNTL_AUTORLD                    2                               /* Auto Reload Enable */
-#define BITP_TCNTL_EN                         1                               /* Timer Enable */
-#define BITP_TCNTL_PWR                        0                               /* Low Power Mode Select */
-#define BITM_TCNTL_INT                       (_ADI_MSK(0x00000008,uint32_t))  /* Interrupt Status (sticky) */
-#define BITM_TCNTL_AUTORLD                   (_ADI_MSK(0x00000004,uint32_t))  /* Auto Reload Enable */
-#define BITM_TCNTL_EN                        (_ADI_MSK(0x00000002,uint32_t))  /* Timer Enable */
-#define BITM_TCNTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Low Power Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TSCALE                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TSCALE_SCALE                     0                               /* Timer Scaling Value */
-#define BITM_TSCALE_SCALE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Timer Scaling Value */
-
-/* ==================================================
-        Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        DBG0
-   ========================= */
-#define DSPID                           0xFFE05000         /* DSP Identification Register */
-
-/* =========================
-        DBG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DSPID                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DSPID_COMPANY                   24                               /* Analog Devices, Inc. */
-#define BITP_DSPID_MAJOR                     16                               /* Major Architectural Change */
-#define BITP_DSPID_COREID                     0                               /* Core ID */
-#define BITM_DSPID_COMPANY                   (_ADI_MSK(0xFF000000,uint32_t))  /* Analog Devices, Inc. */
-
-#define BITM_DSPID_MAJOR                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Major Architectural Change */
-#define ENUM_DSPID_BF533                     (_ADI_MSK(0x00040000,uint32_t))  /* MAJOR: ADSP-BF533 Core Compatible */
-#define BITM_DSPID_COREID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Core ID */
-
-/* ==================================================
-        Trace Unit Registers
-   ================================================== */
-
-/* =========================
-        TB0
-   ========================= */
-#define TBUFCTL                         0xFFE06000         /* Trace Buffer Control Register */
-#define TBUFSTAT                        0xFFE06004         /* Trace Buffer Status Register */
-#define TBUF                            0xFFE06100         /* Trace Buffer */
-
-/* =========================
-        TB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFCTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFCTL_COMPRESS                 3                               /* Trace Buffer Compression */
-#define BITP_TBUFCTL_OVF                      2                               /* Trace Buffer Overflow */
-#define BITP_TBUFCTL_EN                       1                               /* Trace Buffer Enable */
-#define BITP_TBUFCTL_PWR                      0                               /* Trace Buffer Power */
-#define BITM_TBUFCTL_COMPRESS                (_ADI_MSK(0x00000018,uint32_t))  /* Trace Buffer Compression */
-#define BITM_TBUFCTL_OVF                     (_ADI_MSK(0x00000004,uint32_t))  /* Trace Buffer Overflow */
-#define BITM_TBUFCTL_EN                      (_ADI_MSK(0x00000002,uint32_t))  /* Trace Buffer Enable */
-#define BITM_TBUFCTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Trace Buffer Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFSTAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFSTAT_CNT                     0                               /* Trace Buffer Count */
-#define BITM_TBUFSTAT_CNT                    (_ADI_MSK(0x0000001F,uint32_t))  /* Trace Buffer Count */
-
-/* ==================================================
-        Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        WP0
-   ========================= */
-#define WPIACTL                         0xFFE07000         /* Watchpoint Instruction Address Control Register 01 */
-#define WPIA0                           0xFFE07040         /* Watchpoint Instruction Address Register */
-#define WPIA1                           0xFFE07044         /* Watchpoint Instruction Address Register */
-#define WPIA2                           0xFFE07048         /* Watchpoint Instruction Address Register */
-#define WPIA3                           0xFFE0704C         /* Watchpoint Instruction Address Register */
-#define WPIA4                           0xFFE07050         /* Watchpoint Instruction Address Register */
-#define WPIA5                           0xFFE07054         /* Watchpoint Instruction Address Register */
-#define WPIACNT0                        0xFFE07080         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT1                        0xFFE07084         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT2                        0xFFE07088         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT3                        0xFFE0708C         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT4                        0xFFE07090         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT5                        0xFFE07094         /* Watchpoint Instruction Address Count Register */
-#define WPDACTL                         0xFFE07100         /* Watchpoint Data Address Control Register */
-#define WPDA0                           0xFFE07140         /* Watchpoint Data Address Register */
-#define WPDA1                           0xFFE07144         /* Watchpoint Data Address Register */
-#define WPDACNT0                        0xFFE07180         /* Watchpoint Data Address Count Value Register */
-#define WPDACNT1                        0xFFE07184         /* Watchpoint Data Address Count Value Register */
-#define WPSTAT                          0xFFE07200         /* Watchpoint Status Register */
-
-/* =========================
-        WP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACTL_WPAND                   25                               /* And Triggers */
-#define BITP_WPIACTL_ACT5                    24                               /* Action field for WPIA5 */
-#define BITP_WPIACTL_ACT4                    23                               /* Action field for WPIA4 */
-#define BITP_WPIACTL_ENCNT5                  22                               /* Enable Counter for WPIA5 */
-#define BITP_WPIACTL_ENCNT4                  21                               /* Enable Counter for WPIA4 */
-#define BITP_WPIACTL_ENIA5                   20                               /* Enable WPIA5 */
-#define BITP_WPIACTL_ENIA4                   19                               /* Enable WPIA4 */
-#define BITP_WPIACTL_INVIR45                 18                               /* Invert Instruction Range 45 */
-#define BITP_WPIACTL_ENIR45                  17                               /* Enable Instruction Range 45 */
-#define BITP_WPIACTL_ACT3                    16                               /* Action field for WPIA3 */
-#define BITP_WPIACTL_ACT2                    15                               /* Action field for WPIA2 */
-#define BITP_WPIACTL_ENCNT3                  14                               /* Enable Counter for WPIA3 */
-#define BITP_WPIACTL_ENCNT2                  13                               /* Enable Counter for WPIA2 */
-#define BITP_WPIACTL_ENIA3                   12                               /* Enable WPIA3 */
-#define BITP_WPIACTL_ENIA2                   11                               /* Enable WPIA2 */
-#define BITP_WPIACTL_INVIR23                 10                               /* Invert Instruction Range 23 */
-#define BITP_WPIACTL_ENIR23                   9                               /* Enable Instruction Range 23 */
-#define BITP_WPIACTL_ACT1                     8                               /* Action field for WPIA1 */
-#define BITP_WPIACTL_ACT0                     7                               /* Action field for WPIA0 */
-#define BITP_WPIACTL_ENCNT1                   6                               /* Enable Counter for WPIA1 */
-#define BITP_WPIACTL_ENCNT0                   5                               /* Enable Counter for WPIA0 */
-#define BITP_WPIACTL_ENIA1                    4                               /* Enable WPIA1 */
-#define BITP_WPIACTL_ENIA0                    3                               /* Enable WPIA0 */
-#define BITP_WPIACTL_INVIR01                  2                               /* Invert Instruction Range 01 */
-#define BITP_WPIACTL_ENIR01                   1                               /* Enable Instruction Range 01 */
-#define BITP_WPIACTL_PWR                      0                               /* Power */
-#define BITM_WPIACTL_WPAND                   (_ADI_MSK(0x02000000,uint32_t))  /* And Triggers */
-#define BITM_WPIACTL_ACT5                    (_ADI_MSK(0x01000000,uint32_t))  /* Action field for WPIA5 */
-#define BITM_WPIACTL_ACT4                    (_ADI_MSK(0x00800000,uint32_t))  /* Action field for WPIA4 */
-#define BITM_WPIACTL_ENCNT5                  (_ADI_MSK(0x00400000,uint32_t))  /* Enable Counter for WPIA5 */
-#define BITM_WPIACTL_ENCNT4                  (_ADI_MSK(0x00200000,uint32_t))  /* Enable Counter for WPIA4 */
-#define BITM_WPIACTL_ENIA5                   (_ADI_MSK(0x00100000,uint32_t))  /* Enable WPIA5 */
-#define BITM_WPIACTL_ENIA4                   (_ADI_MSK(0x00080000,uint32_t))  /* Enable WPIA4 */
-#define BITM_WPIACTL_INVIR45                 (_ADI_MSK(0x00040000,uint32_t))  /* Invert Instruction Range 45 */
-#define BITM_WPIACTL_ENIR45                  (_ADI_MSK(0x00020000,uint32_t))  /* Enable Instruction Range 45 */
-#define BITM_WPIACTL_ACT3                    (_ADI_MSK(0x00010000,uint32_t))  /* Action field for WPIA3 */
-#define BITM_WPIACTL_ACT2                    (_ADI_MSK(0x00008000,uint32_t))  /* Action field for WPIA2 */
-#define BITM_WPIACTL_ENCNT3                  (_ADI_MSK(0x00004000,uint32_t))  /* Enable Counter for WPIA3 */
-#define BITM_WPIACTL_ENCNT2                  (_ADI_MSK(0x00002000,uint32_t))  /* Enable Counter for WPIA2 */
-#define BITM_WPIACTL_ENIA3                   (_ADI_MSK(0x00001000,uint32_t))  /* Enable WPIA3 */
-#define BITM_WPIACTL_ENIA2                   (_ADI_MSK(0x00000800,uint32_t))  /* Enable WPIA2 */
-#define BITM_WPIACTL_INVIR23                 (_ADI_MSK(0x00000400,uint32_t))  /* Invert Instruction Range 23 */
-#define BITM_WPIACTL_ENIR23                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable Instruction Range 23 */
-#define BITM_WPIACTL_ACT1                    (_ADI_MSK(0x00000100,uint32_t))  /* Action field for WPIA1 */
-#define BITM_WPIACTL_ACT0                    (_ADI_MSK(0x00000080,uint32_t))  /* Action field for WPIA0 */
-#define BITM_WPIACTL_ENCNT1                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Counter for WPIA1 */
-#define BITM_WPIACTL_ENCNT0                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Counter for WPIA0 */
-#define BITM_WPIACTL_ENIA1                   (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPIA1 */
-#define BITM_WPIACTL_ENIA0                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPIA0 */
-#define BITM_WPIACTL_INVIR01                 (_ADI_MSK(0x00000004,uint32_t))  /* Invert Instruction Range 01 */
-#define BITM_WPIACTL_ENIR01                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable Instruction Range 01 */
-#define BITM_WPIACTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACNT_CNT                      0                               /* Count Value */
-#define BITM_WPIACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACTL_ACC1                    12                               /* Access type for WPDA1 */
-#define BITP_WPDACTL_SRC1                    10                               /* DAG Source for WPDA1 */
-#define BITP_WPDACTL_ACC0                     8                               /* Access type for WPDA0 */
-#define BITP_WPDACTL_SRC0                     6                               /* DAG Source for WPDA0 */
-#define BITP_WPDACTL_ENCNT1                   5                               /* Enable WPDA1 Counter */
-#define BITP_WPDACTL_ENCNT0                   4                               /* Enable WPDA0 Counter */
-#define BITP_WPDACTL_ENDA1                    3                               /* Enable WPDA1 */
-#define BITP_WPDACTL_ENDA0                    2                               /* Enable WPDA0 */
-#define BITP_WPDACTL_INVR                     1                               /* Invert Range Comparision */
-#define BITP_WPDACTL_ENR                      0                               /* Enable Range Comparison */
-#define BITM_WPDACTL_ACC1                    (_ADI_MSK(0x00003000,uint32_t))  /* Access type for WPDA1 */
-#define BITM_WPDACTL_SRC1                    (_ADI_MSK(0x00000C00,uint32_t))  /* DAG Source for WPDA1 */
-#define BITM_WPDACTL_ACC0                    (_ADI_MSK(0x00000300,uint32_t))  /* Access type for WPDA0 */
-#define BITM_WPDACTL_SRC0                    (_ADI_MSK(0x000000C0,uint32_t))  /* DAG Source for WPDA0 */
-#define BITM_WPDACTL_ENCNT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable WPDA1 Counter */
-#define BITM_WPDACTL_ENCNT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPDA0 Counter */
-#define BITM_WPDACTL_ENDA1                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPDA1 */
-#define BITM_WPDACTL_ENDA0                   (_ADI_MSK(0x00000004,uint32_t))  /* Enable WPDA0 */
-#define BITM_WPDACTL_INVR                    (_ADI_MSK(0x00000002,uint32_t))  /* Invert Range Comparision */
-#define BITM_WPDACTL_ENR                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable Range Comparison */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACNT_CNT                      0                               /* Count Value */
-#define BITM_WPDACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPSTAT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPSTAT_DA1                       7                               /* WPDA1 match */
-#define BITP_WPSTAT_DA0                       6                               /* WPDA0 or WPDA0:1 range match */
-#define BITP_WPSTAT_IA5                       5                               /* WPIA5 match */
-#define BITP_WPSTAT_IA4                       4                               /* WPIA4 or WPIA4:5 range match */
-#define BITP_WPSTAT_IA3                       3                               /* WPIA3 match */
-#define BITP_WPSTAT_IA2                       2                               /* WPIA2 or WPIA2:3 range match */
-#define BITP_WPSTAT_IA1                       1                               /* WPIA1 match */
-#define BITP_WPSTAT_IA0                       0                               /* WPIA0 or WPIA0:1 range match */
-#define BITM_WPSTAT_DA1                      (_ADI_MSK(0x00000080,uint32_t))  /* WPDA1 match */
-#define BITM_WPSTAT_DA0                      (_ADI_MSK(0x00000040,uint32_t))  /* WPDA0 or WPDA0:1 range match */
-#define BITM_WPSTAT_IA5                      (_ADI_MSK(0x00000020,uint32_t))  /* WPIA5 match */
-#define BITM_WPSTAT_IA4                      (_ADI_MSK(0x00000010,uint32_t))  /* WPIA4 or WPIA4:5 range match */
-#define BITM_WPSTAT_IA3                      (_ADI_MSK(0x00000008,uint32_t))  /* WPIA3 match */
-#define BITM_WPSTAT_IA2                      (_ADI_MSK(0x00000004,uint32_t))  /* WPIA2 or WPIA2:3 range match */
-#define BITM_WPSTAT_IA1                      (_ADI_MSK(0x00000002,uint32_t))  /* WPIA1 match */
-#define BITM_WPSTAT_IA0                      (_ADI_MSK(0x00000001,uint32_t))  /* WPIA0 or WPIA0:1 range match */
-
-/* ==================================================
-        Performance Monitor Registers
-   ================================================== */
-
-/* =========================
-        PF0
-   ========================= */
-#define PFCTL                           0xFFE08000         /* Performance Monitor Control Register */
-#define PFCNTR0                         0xFFE08100         /* Performance Monitor Counter 0 */
-#define PFCNTR1                         0xFFE08104         /* Performance Monitor Counter 1 */
-
-/* =========================
-        PF
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PFCTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PFCTL_CNT1                      25                               /* Count Cycles or Edges 1 */
-#define BITP_PFCTL_CNT0                      24                               /* Count Cycles or Edges 0 */
-#define BITP_PFCTL_MON1                      16                               /* Monitor 1 Events */
-#define BITP_PFCTL_ENA1                      14                               /* Enable Monitor 1 */
-#define BITP_PFCTL_EVENT1                    13                               /* Emulator or Exception Event 1 */
-#define BITP_PFCTL_MON0                       5                               /* Monitor 0 Events */
-#define BITP_PFCTL_ENA0                       3                               /* Enable Monitor 0 */
-#define BITP_PFCTL_EVENT0                     2                               /* Emulator or Exception Event 0 */
-#define BITP_PFCTL_PWR                        0                               /* Power */
-#define BITM_PFCTL_CNT1                      (_ADI_MSK(0x02000000,uint32_t))  /* Count Cycles or Edges 1 */
-#define BITM_PFCTL_CNT0                      (_ADI_MSK(0x01000000,uint32_t))  /* Count Cycles or Edges 0 */
-#define BITM_PFCTL_MON1                      (_ADI_MSK(0x00FF0000,uint32_t))  /* Monitor 1 Events */
-#define BITM_PFCTL_ENA1                      (_ADI_MSK(0x0000C000,uint32_t))  /* Enable Monitor 1 */
-#define BITM_PFCTL_EVENT1                    (_ADI_MSK(0x00002000,uint32_t))  /* Emulator or Exception Event 1 */
-#define BITM_PFCTL_MON0                      (_ADI_MSK(0x00001FE0,uint32_t))  /* Monitor 0 Events */
-#define BITM_PFCTL_ENA0                      (_ADI_MSK(0x00000018,uint32_t))  /* Enable Monitor 0 */
-#define BITM_PFCTL_EVENT0                    (_ADI_MSK(0x00000004,uint32_t))  /* Emulator or Exception Event 0 */
-#define BITM_PFCTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ==================================
-       DMA Alias Definitions
-   ================================== */
-#define SPORT0_A_DMA_DSCPTR_NXT              (REG_DMA0_DSCPTR_NXT)
-#define SPORT0_A_DMA_ADDRSTART               (REG_DMA0_ADDRSTART)
-#define SPORT0_A_DMA_CFG                     (REG_DMA0_CFG)
-#define SPORT0_A_DMA_XCNT                    (REG_DMA0_XCNT)
-#define SPORT0_A_DMA_XMOD                    (REG_DMA0_XMOD)
-#define SPORT0_A_DMA_YCNT                    (REG_DMA0_YCNT)
-#define SPORT0_A_DMA_YMOD                    (REG_DMA0_YMOD)
-#define SPORT0_A_DMA_DSCPTR_CUR              (REG_DMA0_DSCPTR_CUR)
-#define SPORT0_A_DMA_DSCPTR_PRV              (REG_DMA0_DSCPTR_PRV)
-#define SPORT0_A_DMA_ADDR_CUR                (REG_DMA0_ADDR_CUR)
-#define SPORT0_A_DMA_STAT                    (REG_DMA0_STAT)
-#define SPORT0_A_DMA_XCNT_CUR                (REG_DMA0_XCNT_CUR)
-#define SPORT0_A_DMA_YCNT_CUR                (REG_DMA0_YCNT_CUR)
-#define SPORT0_A_DMA_BWLCNT                  (REG_DMA0_BWLCNT)
-#define SPORT0_A_DMA_BWLCNT_CUR              (REG_DMA0_BWLCNT_CUR)
-#define SPORT0_A_DMA_BWMCNT                  (REG_DMA0_BWMCNT)
-#define SPORT0_A_DMA_BWMCNT_CUR              (REG_DMA0_BWMCNT_CUR)
-#define SPORT0_B_DMA_DSCPTR_NXT              (REG_DMA1_DSCPTR_NXT)
-#define SPORT0_B_DMA_ADDRSTART               (REG_DMA1_ADDRSTART)
-#define SPORT0_B_DMA_CFG                     (REG_DMA1_CFG)
-#define SPORT0_B_DMA_XCNT                    (REG_DMA1_XCNT)
-#define SPORT0_B_DMA_XMOD                    (REG_DMA1_XMOD)
-#define SPORT0_B_DMA_YCNT                    (REG_DMA1_YCNT)
-#define SPORT0_B_DMA_YMOD                    (REG_DMA1_YMOD)
-#define SPORT0_B_DMA_DSCPTR_CUR              (REG_DMA1_DSCPTR_CUR)
-#define SPORT0_B_DMA_DSCPTR_PRV              (REG_DMA1_DSCPTR_PRV)
-#define SPORT0_B_DMA_ADDR_CUR                (REG_DMA1_ADDR_CUR)
-#define SPORT0_B_DMA_STAT                    (REG_DMA1_STAT)
-#define SPORT0_B_DMA_XCNT_CUR                (REG_DMA1_XCNT_CUR)
-#define SPORT0_B_DMA_YCNT_CUR                (REG_DMA1_YCNT_CUR)
-#define SPORT0_B_DMA_BWLCNT                  (REG_DMA1_BWLCNT)
-#define SPORT0_B_DMA_BWLCNT_CUR              (REG_DMA1_BWLCNT_CUR)
-#define SPORT0_B_DMA_BWMCNT                  (REG_DMA1_BWMCNT)
-#define SPORT0_B_DMA_BWMCNT_CUR              (REG_DMA1_BWMCNT_CUR)
-#define SPORT1_A_DMA_DSCPTR_NXT              (REG_DMA2_DSCPTR_NXT)
-#define SPORT1_A_DMA_ADDRSTART               (REG_DMA2_ADDRSTART)
-#define SPORT1_A_DMA_CFG                     (REG_DMA2_CFG)
-#define SPORT1_A_DMA_XCNT                    (REG_DMA2_XCNT)
-#define SPORT1_A_DMA_XMOD                    (REG_DMA2_XMOD)
-#define SPORT1_A_DMA_YCNT                    (REG_DMA2_YCNT)
-#define SPORT1_A_DMA_YMOD                    (REG_DMA2_YMOD)
-#define SPORT1_A_DMA_DSCPTR_CUR              (REG_DMA2_DSCPTR_CUR)
-#define SPORT1_A_DMA_DSCPTR_PRV              (REG_DMA2_DSCPTR_PRV)
-#define SPORT1_A_DMA_ADDR_CUR                (REG_DMA2_ADDR_CUR)
-#define SPORT1_A_DMA_STAT                    (REG_DMA2_STAT)
-#define SPORT1_A_DMA_XCNT_CUR                (REG_DMA2_XCNT_CUR)
-#define SPORT1_A_DMA_YCNT_CUR                (REG_DMA2_YCNT_CUR)
-#define SPORT1_A_DMA_BWLCNT                  (REG_DMA2_BWLCNT)
-#define SPORT1_A_DMA_BWLCNT_CUR              (REG_DMA2_BWLCNT_CUR)
-#define SPORT1_A_DMA_BWMCNT                  (REG_DMA2_BWMCNT)
-#define SPORT1_A_DMA_BWMCNT_CUR              (REG_DMA2_BWMCNT_CUR)
-#define SPORT1_B_DMA_DSCPTR_NXT              (REG_DMA3_DSCPTR_NXT)
-#define SPORT1_B_DMA_ADDRSTART               (REG_DMA3_ADDRSTART)
-#define SPORT1_B_DMA_CFG                     (REG_DMA3_CFG)
-#define SPORT1_B_DMA_XCNT                    (REG_DMA3_XCNT)
-#define SPORT1_B_DMA_XMOD                    (REG_DMA3_XMOD)
-#define SPORT1_B_DMA_YCNT                    (REG_DMA3_YCNT)
-#define SPORT1_B_DMA_YMOD                    (REG_DMA3_YMOD)
-#define SPORT1_B_DMA_DSCPTR_CUR              (REG_DMA3_DSCPTR_CUR)
-#define SPORT1_B_DMA_DSCPTR_PRV              (REG_DMA3_DSCPTR_PRV)
-#define SPORT1_B_DMA_ADDR_CUR                (REG_DMA3_ADDR_CUR)
-#define SPORT1_B_DMA_STAT                    (REG_DMA3_STAT)
-#define SPORT1_B_DMA_XCNT_CUR                (REG_DMA3_XCNT_CUR)
-#define SPORT1_B_DMA_YCNT_CUR                (REG_DMA3_YCNT_CUR)
-#define SPORT1_B_DMA_BWLCNT                  (REG_DMA3_BWLCNT)
-#define SPORT1_B_DMA_BWLCNT_CUR              (REG_DMA3_BWLCNT_CUR)
-#define SPORT1_B_DMA_BWMCNT                  (REG_DMA3_BWMCNT)
-#define SPORT1_B_DMA_BWMCNT_CUR              (REG_DMA3_BWMCNT_CUR)
-#define SPORT2_A_DMA_DSCPTR_NXT              (REG_DMA4_DSCPTR_NXT)
-#define SPORT2_A_DMA_ADDRSTART               (REG_DMA4_ADDRSTART)
-#define SPORT2_A_DMA_CFG                     (REG_DMA4_CFG)
-#define SPORT2_A_DMA_XCNT                    (REG_DMA4_XCNT)
-#define SPORT2_A_DMA_XMOD                    (REG_DMA4_XMOD)
-#define SPORT2_A_DMA_YCNT                    (REG_DMA4_YCNT)
-#define SPORT2_A_DMA_YMOD                    (REG_DMA4_YMOD)
-#define SPORT2_A_DMA_DSCPTR_CUR              (REG_DMA4_DSCPTR_CUR)
-#define SPORT2_A_DMA_DSCPTR_PRV              (REG_DMA4_DSCPTR_PRV)
-#define SPORT2_A_DMA_ADDR_CUR                (REG_DMA4_ADDR_CUR)
-#define SPORT2_A_DMA_STAT                    (REG_DMA4_STAT)
-#define SPORT2_A_DMA_XCNT_CUR                (REG_DMA4_XCNT_CUR)
-#define SPORT2_A_DMA_YCNT_CUR                (REG_DMA4_YCNT_CUR)
-#define SPORT2_A_DMA_BWLCNT                  (REG_DMA4_BWLCNT)
-#define SPORT2_A_DMA_BWLCNT_CUR              (REG_DMA4_BWLCNT_CUR)
-#define SPORT2_A_DMA_BWMCNT                  (REG_DMA4_BWMCNT)
-#define SPORT2_A_DMA_BWMCNT_CUR              (REG_DMA4_BWMCNT_CUR)
-#define SPORT2_B_DMA_DSCPTR_NXT              (REG_DMA5_DSCPTR_NXT)
-#define SPORT2_B_DMA_ADDRSTART               (REG_DMA5_ADDRSTART)
-#define SPORT2_B_DMA_CFG                     (REG_DMA5_CFG)
-#define SPORT2_B_DMA_XCNT                    (REG_DMA5_XCNT)
-#define SPORT2_B_DMA_XMOD                    (REG_DMA5_XMOD)
-#define SPORT2_B_DMA_YCNT                    (REG_DMA5_YCNT)
-#define SPORT2_B_DMA_YMOD                    (REG_DMA5_YMOD)
-#define SPORT2_B_DMA_DSCPTR_CUR              (REG_DMA5_DSCPTR_CUR)
-#define SPORT2_B_DMA_DSCPTR_PRV              (REG_DMA5_DSCPTR_PRV)
-#define SPORT2_B_DMA_ADDR_CUR                (REG_DMA5_ADDR_CUR)
-#define SPORT2_B_DMA_STAT                    (REG_DMA5_STAT)
-#define SPORT2_B_DMA_XCNT_CUR                (REG_DMA5_XCNT_CUR)
-#define SPORT2_B_DMA_YCNT_CUR                (REG_DMA5_YCNT_CUR)
-#define SPORT2_B_DMA_BWLCNT                  (REG_DMA5_BWLCNT)
-#define SPORT2_B_DMA_BWLCNT_CUR              (REG_DMA5_BWLCNT_CUR)
-#define SPORT2_B_DMA_BWMCNT                  (REG_DMA5_BWMCNT)
-#define SPORT2_B_DMA_BWMCNT_CUR              (REG_DMA5_BWMCNT_CUR)
-#define SPI0_TXDMA_DSCPTR_NXT                (REG_DMA6_DSCPTR_NXT)
-#define SPI0_TXDMA_ADDRSTART                 (REG_DMA6_ADDRSTART)
-#define SPI0_TXDMA_CFG                       (REG_DMA6_CFG)
-#define SPI0_TXDMA_XCNT                      (REG_DMA6_XCNT)
-#define SPI0_TXDMA_XMOD                      (REG_DMA6_XMOD)
-#define SPI0_TXDMA_YCNT                      (REG_DMA6_YCNT)
-#define SPI0_TXDMA_YMOD                      (REG_DMA6_YMOD)
-#define SPI0_TXDMA_DSCPTR_CUR                (REG_DMA6_DSCPTR_CUR)
-#define SPI0_TXDMA_DSCPTR_PRV                (REG_DMA6_DSCPTR_PRV)
-#define SPI0_TXDMA_ADDR_CUR                  (REG_DMA6_ADDR_CUR)
-#define SPI0_TXDMA_STAT                      (REG_DMA6_STAT)
-#define SPI0_TXDMA_XCNT_CUR                  (REG_DMA6_XCNT_CUR)
-#define SPI0_TXDMA_YCNT_CUR                  (REG_DMA6_YCNT_CUR)
-#define SPI0_TXDMA_BWLCNT                    (REG_DMA6_BWLCNT)
-#define SPI0_TXDMA_BWLCNT_CUR                (REG_DMA6_BWLCNT_CUR)
-#define SPI0_TXDMA_BWMCNT                    (REG_DMA6_BWMCNT)
-#define SPI0_TXDMA_BWMCNT_CUR                (REG_DMA6_BWMCNT_CUR)
-#define SPI0_RXDMA_DSCPTR_NXT                (REG_DMA7_DSCPTR_NXT)
-#define SPI0_RXDMA_ADDRSTART                 (REG_DMA7_ADDRSTART)
-#define SPI0_RXDMA_CFG                       (REG_DMA7_CFG)
-#define SPI0_RXDMA_XCNT                      (REG_DMA7_XCNT)
-#define SPI0_RXDMA_XMOD                      (REG_DMA7_XMOD)
-#define SPI0_RXDMA_YCNT                      (REG_DMA7_YCNT)
-#define SPI0_RXDMA_YMOD                      (REG_DMA7_YMOD)
-#define SPI0_RXDMA_DSCPTR_CUR                (REG_DMA7_DSCPTR_CUR)
-#define SPI0_RXDMA_DSCPTR_PRV                (REG_DMA7_DSCPTR_PRV)
-#define SPI0_RXDMA_ADDR_CUR                  (REG_DMA7_ADDR_CUR)
-#define SPI0_RXDMA_STAT                      (REG_DMA7_STAT)
-#define SPI0_RXDMA_XCNT_CUR                  (REG_DMA7_XCNT_CUR)
-#define SPI0_RXDMA_YCNT_CUR                  (REG_DMA7_YCNT_CUR)
-#define SPI0_RXDMA_BWLCNT                    (REG_DMA7_BWLCNT)
-#define SPI0_RXDMA_BWLCNT_CUR                (REG_DMA7_BWLCNT_CUR)
-#define SPI0_RXDMA_BWMCNT                    (REG_DMA7_BWMCNT)
-#define SPI0_RXDMA_BWMCNT_CUR                (REG_DMA7_BWMCNT_CUR)
-#define SPI1_TXDMA_DSCPTR_NXT                (REG_DMA8_DSCPTR_NXT)
-#define SPI1_TXDMA_ADDRSTART                 (REG_DMA8_ADDRSTART)
-#define SPI1_TXDMA_CFG                       (REG_DMA8_CFG)
-#define SPI1_TXDMA_XCNT                      (REG_DMA8_XCNT)
-#define SPI1_TXDMA_XMOD                      (REG_DMA8_XMOD)
-#define SPI1_TXDMA_YCNT                      (REG_DMA8_YCNT)
-#define SPI1_TXDMA_YMOD                      (REG_DMA8_YMOD)
-#define SPI1_TXDMA_DSCPTR_CUR                (REG_DMA8_DSCPTR_CUR)
-#define SPI1_TXDMA_DSCPTR_PRV                (REG_DMA8_DSCPTR_PRV)
-#define SPI1_TXDMA_ADDR_CUR                  (REG_DMA8_ADDR_CUR)
-#define SPI1_TXDMA_STAT                      (REG_DMA8_STAT)
-#define SPI1_TXDMA_XCNT_CUR                  (REG_DMA8_XCNT_CUR)
-#define SPI1_TXDMA_YCNT_CUR                  (REG_DMA8_YCNT_CUR)
-#define SPI1_TXDMA_BWLCNT                    (REG_DMA8_BWLCNT)
-#define SPI1_TXDMA_BWLCNT_CUR                (REG_DMA8_BWLCNT_CUR)
-#define SPI1_TXDMA_BWMCNT                    (REG_DMA8_BWMCNT)
-#define SPI1_TXDMA_BWMCNT_CUR                (REG_DMA8_BWMCNT_CUR)
-#define SPI1_RXDMA_DSCPTR_NXT                (REG_DMA9_DSCPTR_NXT)
-#define SPI1_RXDMA_ADDRSTART                 (REG_DMA9_ADDRSTART)
-#define SPI1_RXDMA_CFG                       (REG_DMA9_CFG)
-#define SPI1_RXDMA_XCNT                      (REG_DMA9_XCNT)
-#define SPI1_RXDMA_XMOD                      (REG_DMA9_XMOD)
-#define SPI1_RXDMA_YCNT                      (REG_DMA9_YCNT)
-#define SPI1_RXDMA_YMOD                      (REG_DMA9_YMOD)
-#define SPI1_RXDMA_DSCPTR_CUR                (REG_DMA9_DSCPTR_CUR)
-#define SPI1_RXDMA_DSCPTR_PRV                (REG_DMA9_DSCPTR_PRV)
-#define SPI1_RXDMA_ADDR_CUR                  (REG_DMA9_ADDR_CUR)
-#define SPI1_RXDMA_STAT                      (REG_DMA9_STAT)
-#define SPI1_RXDMA_XCNT_CUR                  (REG_DMA9_XCNT_CUR)
-#define SPI1_RXDMA_YCNT_CUR                  (REG_DMA9_YCNT_CUR)
-#define SPI1_RXDMA_BWLCNT                    (REG_DMA9_BWLCNT)
-#define SPI1_RXDMA_BWLCNT_CUR                (REG_DMA9_BWLCNT_CUR)
-#define SPI1_RXDMA_BWMCNT                    (REG_DMA9_BWMCNT)
-#define SPI1_RXDMA_BWMCNT_CUR                (REG_DMA9_BWMCNT_CUR)
-#define RSI0_DMA_DSCPTR_NXT                  (REG_DMA10_DSCPTR_NXT)
-#define RSI0_DMA_ADDRSTART                   (REG_DMA10_ADDRSTART)
-#define RSI0_DMA_CFG                         (REG_DMA10_CFG)
-#define RSI0_DMA_XCNT                        (REG_DMA10_XCNT)
-#define RSI0_DMA_XMOD                        (REG_DMA10_XMOD)
-#define RSI0_DMA_YCNT                        (REG_DMA10_YCNT)
-#define RSI0_DMA_YMOD                        (REG_DMA10_YMOD)
-#define RSI0_DMA_DSCPTR_CUR                  (REG_DMA10_DSCPTR_CUR)
-#define RSI0_DMA_DSCPTR_PRV                  (REG_DMA10_DSCPTR_PRV)
-#define RSI0_DMA_ADDR_CUR                    (REG_DMA10_ADDR_CUR)
-#define RSI0_DMA_STAT                        (REG_DMA10_STAT)
-#define RSI0_DMA_XCNT_CUR                    (REG_DMA10_XCNT_CUR)
-#define RSI0_DMA_YCNT_CUR                    (REG_DMA10_YCNT_CUR)
-#define RSI0_DMA_BWLCNT                      (REG_DMA10_BWLCNT)
-#define RSI0_DMA_BWLCNT_CUR                  (REG_DMA10_BWLCNT_CUR)
-#define RSI0_DMA_BWMCNT                      (REG_DMA10_BWMCNT)
-#define RSI0_DMA_BWMCNT_CUR                  (REG_DMA10_BWMCNT_CUR)
-#define SDU0_DMA_DSCPTR_NXT                  (REG_DMA11_DSCPTR_NXT)
-#define SDU0_DMA_ADDRSTART                   (REG_DMA11_ADDRSTART)
-#define SDU0_DMA_CFG                         (REG_DMA11_CFG)
-#define SDU0_DMA_XCNT                        (REG_DMA11_XCNT)
-#define SDU0_DMA_XMOD                        (REG_DMA11_XMOD)
-#define SDU0_DMA_YCNT                        (REG_DMA11_YCNT)
-#define SDU0_DMA_YMOD                        (REG_DMA11_YMOD)
-#define SDU0_DMA_DSCPTR_CUR                  (REG_DMA11_DSCPTR_CUR)
-#define SDU0_DMA_DSCPTR_PRV                  (REG_DMA11_DSCPTR_PRV)
-#define SDU0_DMA_ADDR_CUR                    (REG_DMA11_ADDR_CUR)
-#define SDU0_DMA_STAT                        (REG_DMA11_STAT)
-#define SDU0_DMA_XCNT_CUR                    (REG_DMA11_XCNT_CUR)
-#define SDU0_DMA_YCNT_CUR                    (REG_DMA11_YCNT_CUR)
-#define SDU0_DMA_BWLCNT                      (REG_DMA11_BWLCNT)
-#define SDU0_DMA_BWLCNT_CUR                  (REG_DMA11_BWLCNT_CUR)
-#define SDU0_DMA_BWMCNT                      (REG_DMA11_BWMCNT)
-#define SDU0_DMA_BWMCNT_CUR                  (REG_DMA11_BWMCNT_CUR)
-#define LP0_DMA_DSCPTR_NXT                   (REG_DMA13_DSCPTR_NXT)
-#define LP0_DMA_ADDRSTART                    (REG_DMA13_ADDRSTART)
-#define LP0_DMA_CFG                          (REG_DMA13_CFG)
-#define LP0_DMA_XCNT                         (REG_DMA13_XCNT)
-#define LP0_DMA_XMOD                         (REG_DMA13_XMOD)
-#define LP0_DMA_YCNT                         (REG_DMA13_YCNT)
-#define LP0_DMA_YMOD                         (REG_DMA13_YMOD)
-#define LP0_DMA_DSCPTR_CUR                   (REG_DMA13_DSCPTR_CUR)
-#define LP0_DMA_DSCPTR_PRV                   (REG_DMA13_DSCPTR_PRV)
-#define LP0_DMA_ADDR_CUR                     (REG_DMA13_ADDR_CUR)
-#define LP0_DMA_STAT                         (REG_DMA13_STAT)
-#define LP0_DMA_XCNT_CUR                     (REG_DMA13_XCNT_CUR)
-#define LP0_DMA_YCNT_CUR                     (REG_DMA13_YCNT_CUR)
-#define LP0_DMA_BWLCNT                       (REG_DMA13_BWLCNT)
-#define LP0_DMA_BWLCNT_CUR                   (REG_DMA13_BWLCNT_CUR)
-#define LP0_DMA_BWMCNT                       (REG_DMA13_BWMCNT)
-#define LP0_DMA_BWMCNT_CUR                   (REG_DMA13_BWMCNT_CUR)
-#define LP1_DMA_DSCPTR_NXT                   (REG_DMA14_DSCPTR_NXT)
-#define LP1_DMA_ADDRSTART                    (REG_DMA14_ADDRSTART)
-#define LP1_DMA_CFG                          (REG_DMA14_CFG)
-#define LP1_DMA_XCNT                         (REG_DMA14_XCNT)
-#define LP1_DMA_XMOD                         (REG_DMA14_XMOD)
-#define LP1_DMA_YCNT                         (REG_DMA14_YCNT)
-#define LP1_DMA_YMOD                         (REG_DMA14_YMOD)
-#define LP1_DMA_DSCPTR_CUR                   (REG_DMA14_DSCPTR_CUR)
-#define LP1_DMA_DSCPTR_PRV                   (REG_DMA14_DSCPTR_PRV)
-#define LP1_DMA_ADDR_CUR                     (REG_DMA14_ADDR_CUR)
-#define LP1_DMA_STAT                         (REG_DMA14_STAT)
-#define LP1_DMA_XCNT_CUR                     (REG_DMA14_XCNT_CUR)
-#define LP1_DMA_YCNT_CUR                     (REG_DMA14_YCNT_CUR)
-#define LP1_DMA_BWLCNT                       (REG_DMA14_BWLCNT)
-#define LP1_DMA_BWLCNT_CUR                   (REG_DMA14_BWLCNT_CUR)
-#define LP1_DMA_BWMCNT                       (REG_DMA14_BWMCNT)
-#define LP1_DMA_BWMCNT_CUR                   (REG_DMA14_BWMCNT_CUR)
-#define LP2_DMA_DSCPTR_NXT                   (REG_DMA15_DSCPTR_NXT)
-#define LP2_DMA_ADDRSTART                    (REG_DMA15_ADDRSTART)
-#define LP2_DMA_CFG                          (REG_DMA15_CFG)
-#define LP2_DMA_XCNT                         (REG_DMA15_XCNT)
-#define LP2_DMA_XMOD                         (REG_DMA15_XMOD)
-#define LP2_DMA_YCNT                         (REG_DMA15_YCNT)
-#define LP2_DMA_YMOD                         (REG_DMA15_YMOD)
-#define LP2_DMA_DSCPTR_CUR                   (REG_DMA15_DSCPTR_CUR)
-#define LP2_DMA_DSCPTR_PRV                   (REG_DMA15_DSCPTR_PRV)
-#define LP2_DMA_ADDR_CUR                     (REG_DMA15_ADDR_CUR)
-#define LP2_DMA_STAT                         (REG_DMA15_STAT)
-#define LP2_DMA_XCNT_CUR                     (REG_DMA15_XCNT_CUR)
-#define LP2_DMA_YCNT_CUR                     (REG_DMA15_YCNT_CUR)
-#define LP2_DMA_BWLCNT                       (REG_DMA15_BWLCNT)
-#define LP2_DMA_BWLCNT_CUR                   (REG_DMA15_BWLCNT_CUR)
-#define LP2_DMA_BWMCNT                       (REG_DMA15_BWMCNT)
-#define LP2_DMA_BWMCNT_CUR                   (REG_DMA15_BWMCNT_CUR)
-#define LP3_DMA_DSCPTR_NXT                   (REG_DMA16_DSCPTR_NXT)
-#define LP3_DMA_ADDRSTART                    (REG_DMA16_ADDRSTART)
-#define LP3_DMA_CFG                          (REG_DMA16_CFG)
-#define LP3_DMA_XCNT                         (REG_DMA16_XCNT)
-#define LP3_DMA_XMOD                         (REG_DMA16_XMOD)
-#define LP3_DMA_YCNT                         (REG_DMA16_YCNT)
-#define LP3_DMA_YMOD                         (REG_DMA16_YMOD)
-#define LP3_DMA_DSCPTR_CUR                   (REG_DMA16_DSCPTR_CUR)
-#define LP3_DMA_DSCPTR_PRV                   (REG_DMA16_DSCPTR_PRV)
-#define LP3_DMA_ADDR_CUR                     (REG_DMA16_ADDR_CUR)
-#define LP3_DMA_STAT                         (REG_DMA16_STAT)
-#define LP3_DMA_XCNT_CUR                     (REG_DMA16_XCNT_CUR)
-#define LP3_DMA_YCNT_CUR                     (REG_DMA16_YCNT_CUR)
-#define LP3_DMA_BWLCNT                       (REG_DMA16_BWLCNT)
-#define LP3_DMA_BWLCNT_CUR                   (REG_DMA16_BWLCNT_CUR)
-#define LP3_DMA_BWMCNT                       (REG_DMA16_BWMCNT)
-#define LP3_DMA_BWMCNT_CUR                   (REG_DMA16_BWMCNT_CUR)
-#define UART0_TXDMA_DSCPTR_NXT               (REG_DMA17_DSCPTR_NXT)
-#define UART0_TXDMA_ADDRSTART                (REG_DMA17_ADDRSTART)
-#define UART0_TXDMA_CFG                      (REG_DMA17_CFG)
-#define UART0_TXDMA_XCNT                     (REG_DMA17_XCNT)
-#define UART0_TXDMA_XMOD                     (REG_DMA17_XMOD)
-#define UART0_TXDMA_YCNT                     (REG_DMA17_YCNT)
-#define UART0_TXDMA_YMOD                     (REG_DMA17_YMOD)
-#define UART0_TXDMA_DSCPTR_CUR               (REG_DMA17_DSCPTR_CUR)
-#define UART0_TXDMA_DSCPTR_PRV               (REG_DMA17_DSCPTR_PRV)
-#define UART0_TXDMA_ADDR_CUR                 (REG_DMA17_ADDR_CUR)
-#define UART0_TXDMA_STAT                     (REG_DMA17_STAT)
-#define UART0_TXDMA_XCNT_CUR                 (REG_DMA17_XCNT_CUR)
-#define UART0_TXDMA_YCNT_CUR                 (REG_DMA17_YCNT_CUR)
-#define UART0_TXDMA_BWLCNT                   (REG_DMA17_BWLCNT)
-#define UART0_TXDMA_BWLCNT_CUR               (REG_DMA17_BWLCNT_CUR)
-#define UART0_TXDMA_BWMCNT                   (REG_DMA17_BWMCNT)
-#define UART0_TXDMA_BWMCNT_CUR               (REG_DMA17_BWMCNT_CUR)
-#define UART0_RXDMA_DSCPTR_NXT               (REG_DMA18_DSCPTR_NXT)
-#define UART0_RXDMA_ADDRSTART                (REG_DMA18_ADDRSTART)
-#define UART0_RXDMA_CFG                      (REG_DMA18_CFG)
-#define UART0_RXDMA_XCNT                     (REG_DMA18_XCNT)
-#define UART0_RXDMA_XMOD                     (REG_DMA18_XMOD)
-#define UART0_RXDMA_YCNT                     (REG_DMA18_YCNT)
-#define UART0_RXDMA_YMOD                     (REG_DMA18_YMOD)
-#define UART0_RXDMA_DSCPTR_CUR               (REG_DMA18_DSCPTR_CUR)
-#define UART0_RXDMA_DSCPTR_PRV               (REG_DMA18_DSCPTR_PRV)
-#define UART0_RXDMA_ADDR_CUR                 (REG_DMA18_ADDR_CUR)
-#define UART0_RXDMA_STAT                     (REG_DMA18_STAT)
-#define UART0_RXDMA_XCNT_CUR                 (REG_DMA18_XCNT_CUR)
-#define UART0_RXDMA_YCNT_CUR                 (REG_DMA18_YCNT_CUR)
-#define UART0_RXDMA_BWLCNT                   (REG_DMA18_BWLCNT)
-#define UART0_RXDMA_BWLCNT_CUR               (REG_DMA18_BWLCNT_CUR)
-#define UART0_RXDMA_BWMCNT                   (REG_DMA18_BWMCNT)
-#define UART0_RXDMA_BWMCNT_CUR               (REG_DMA18_BWMCNT_CUR)
-#define UART1_TXDMA_DSCPTR_NXT               (REG_DMA19_DSCPTR_NXT)
-#define UART1_TXDMA_ADDRSTART                (REG_DMA19_ADDRSTART)
-#define UART1_TXDMA_CFG                      (REG_DMA19_CFG)
-#define UART1_TXDMA_XCNT                     (REG_DMA19_XCNT)
-#define UART1_TXDMA_XMOD                     (REG_DMA19_XMOD)
-#define UART1_TXDMA_YCNT                     (REG_DMA19_YCNT)
-#define UART1_TXDMA_YMOD                     (REG_DMA19_YMOD)
-#define UART1_TXDMA_DSCPTR_CUR               (REG_DMA19_DSCPTR_CUR)
-#define UART1_TXDMA_DSCPTR_PRV               (REG_DMA19_DSCPTR_PRV)
-#define UART1_TXDMA_ADDR_CUR                 (REG_DMA19_ADDR_CUR)
-#define UART1_TXDMA_STAT                     (REG_DMA19_STAT)
-#define UART1_TXDMA_XCNT_CUR                 (REG_DMA19_XCNT_CUR)
-#define UART1_TXDMA_YCNT_CUR                 (REG_DMA19_YCNT_CUR)
-#define UART1_TXDMA_BWLCNT                   (REG_DMA19_BWLCNT)
-#define UART1_TXDMA_BWLCNT_CUR               (REG_DMA19_BWLCNT_CUR)
-#define UART1_TXDMA_BWMCNT                   (REG_DMA19_BWMCNT)
-#define UART1_TXDMA_BWMCNT_CUR               (REG_DMA19_BWMCNT_CUR)
-#define UART1_RXDMA_DSCPTR_NXT               (REG_DMA20_DSCPTR_NXT)
-#define UART1_RXDMA_ADDRSTART                (REG_DMA20_ADDRSTART)
-#define UART1_RXDMA_CFG                      (REG_DMA20_CFG)
-#define UART1_RXDMA_XCNT                     (REG_DMA20_XCNT)
-#define UART1_RXDMA_XMOD                     (REG_DMA20_XMOD)
-#define UART1_RXDMA_YCNT                     (REG_DMA20_YCNT)
-#define UART1_RXDMA_YMOD                     (REG_DMA20_YMOD)
-#define UART1_RXDMA_DSCPTR_CUR               (REG_DMA20_DSCPTR_CUR)
-#define UART1_RXDMA_DSCPTR_PRV               (REG_DMA20_DSCPTR_PRV)
-#define UART1_RXDMA_ADDR_CUR                 (REG_DMA20_ADDR_CUR)
-#define UART1_RXDMA_STAT                     (REG_DMA20_STAT)
-#define UART1_RXDMA_XCNT_CUR                 (REG_DMA20_XCNT_CUR)
-#define UART1_RXDMA_YCNT_CUR                 (REG_DMA20_YCNT_CUR)
-#define UART1_RXDMA_BWLCNT                   (REG_DMA20_BWLCNT)
-#define UART1_RXDMA_BWLCNT_CUR               (REG_DMA20_BWLCNT_CUR)
-#define UART1_RXDMA_BWMCNT                   (REG_DMA20_BWMCNT)
-#define UART1_RXDMA_BWMCNT_CUR               (REG_DMA20_BWMCNT_CUR)
-#define MDMA0_SRC_DSCPTR_NXT                 (REG_DMA21_DSCPTR_NXT)
-#define MDMA0_SRC_ADDRSTART                  (REG_DMA21_ADDRSTART)
-#define MDMA0_SRC_CFG                        (REG_DMA21_CFG)
-#define MDMA0_SRC_XCNT                       (REG_DMA21_XCNT)
-#define MDMA0_SRC_XMOD                       (REG_DMA21_XMOD)
-#define MDMA0_SRC_YCNT                       (REG_DMA21_YCNT)
-#define MDMA0_SRC_YMOD                       (REG_DMA21_YMOD)
-#define MDMA0_SRC_DSCPTR_CUR                 (REG_DMA21_DSCPTR_CUR)
-#define MDMA0_SRC_DSCPTR_PRV                 (REG_DMA21_DSCPTR_PRV)
-#define MDMA0_SRC_ADDR_CUR                   (REG_DMA21_ADDR_CUR)
-#define MDMA0_SRC_STAT                       (REG_DMA21_STAT)
-#define MDMA0_SRC_XCNT_CUR                   (REG_DMA21_XCNT_CUR)
-#define MDMA0_SRC_YCNT_CUR                   (REG_DMA21_YCNT_CUR)
-#define MDMA0_SRC_BWLCNT                     (REG_DMA21_BWLCNT)
-#define MDMA0_SRC_BWLCNT_CUR                 (REG_DMA21_BWLCNT_CUR)
-#define MDMA0_SRC_BWMCNT                     (REG_DMA21_BWMCNT)
-#define MDMA0_SRC_BWMCNT_CUR                 (REG_DMA21_BWMCNT_CUR)
-#define MDMA0_DST_DSCPTR_NXT                 (REG_DMA22_DSCPTR_NXT)
-#define MDMA0_DST_ADDRSTART                  (REG_DMA22_ADDRSTART)
-#define MDMA0_DST_CFG                        (REG_DMA22_CFG)
-#define MDMA0_DST_XCNT                       (REG_DMA22_XCNT)
-#define MDMA0_DST_XMOD                       (REG_DMA22_XMOD)
-#define MDMA0_DST_YCNT                       (REG_DMA22_YCNT)
-#define MDMA0_DST_YMOD                       (REG_DMA22_YMOD)
-#define MDMA0_DST_DSCPTR_CUR                 (REG_DMA22_DSCPTR_CUR)
-#define MDMA0_DST_DSCPTR_PRV                 (REG_DMA22_DSCPTR_PRV)
-#define MDMA0_DST_ADDR_CUR                   (REG_DMA22_ADDR_CUR)
-#define MDMA0_DST_STAT                       (REG_DMA22_STAT)
-#define MDMA0_DST_XCNT_CUR                   (REG_DMA22_XCNT_CUR)
-#define MDMA0_DST_YCNT_CUR                   (REG_DMA22_YCNT_CUR)
-#define MDMA0_DST_BWLCNT                     (REG_DMA22_BWLCNT)
-#define MDMA0_DST_BWLCNT_CUR                 (REG_DMA22_BWLCNT_CUR)
-#define MDMA0_DST_BWMCNT                     (REG_DMA22_BWMCNT)
-#define MDMA0_DST_BWMCNT_CUR                 (REG_DMA22_BWMCNT_CUR)
-#define MDMA1_SRC_DSCPTR_NXT                 (REG_DMA23_DSCPTR_NXT)
-#define MDMA1_SRC_ADDRSTART                  (REG_DMA23_ADDRSTART)
-#define MDMA1_SRC_CFG                        (REG_DMA23_CFG)
-#define MDMA1_SRC_XCNT                       (REG_DMA23_XCNT)
-#define MDMA1_SRC_XMOD                       (REG_DMA23_XMOD)
-#define MDMA1_SRC_YCNT                       (REG_DMA23_YCNT)
-#define MDMA1_SRC_YMOD                       (REG_DMA23_YMOD)
-#define MDMA1_SRC_DSCPTR_CUR                 (REG_DMA23_DSCPTR_CUR)
-#define MDMA1_SRC_DSCPTR_PRV                 (REG_DMA23_DSCPTR_PRV)
-#define MDMA1_SRC_ADDR_CUR                   (REG_DMA23_ADDR_CUR)
-#define MDMA1_SRC_STAT                       (REG_DMA23_STAT)
-#define MDMA1_SRC_XCNT_CUR                   (REG_DMA23_XCNT_CUR)
-#define MDMA1_SRC_YCNT_CUR                   (REG_DMA23_YCNT_CUR)
-#define MDMA1_SRC_BWLCNT                     (REG_DMA23_BWLCNT)
-#define MDMA1_SRC_BWLCNT_CUR                 (REG_DMA23_BWLCNT_CUR)
-#define MDMA1_SRC_BWMCNT                     (REG_DMA23_BWMCNT)
-#define MDMA1_SRC_BWMCNT_CUR                 (REG_DMA23_BWMCNT_CUR)
-#define MDMA1_DST_DSCPTR_NXT                 (REG_DMA24_DSCPTR_NXT)
-#define MDMA1_DST_ADDRSTART                  (REG_DMA24_ADDRSTART)
-#define MDMA1_DST_CFG                        (REG_DMA24_CFG)
-#define MDMA1_DST_XCNT                       (REG_DMA24_XCNT)
-#define MDMA1_DST_XMOD                       (REG_DMA24_XMOD)
-#define MDMA1_DST_YCNT                       (REG_DMA24_YCNT)
-#define MDMA1_DST_YMOD                       (REG_DMA24_YMOD)
-#define MDMA1_DST_DSCPTR_CUR                 (REG_DMA24_DSCPTR_CUR)
-#define MDMA1_DST_DSCPTR_PRV                 (REG_DMA24_DSCPTR_PRV)
-#define MDMA1_DST_ADDR_CUR                   (REG_DMA24_ADDR_CUR)
-#define MDMA1_DST_STAT                       (REG_DMA24_STAT)
-#define MDMA1_DST_XCNT_CUR                   (REG_DMA24_XCNT_CUR)
-#define MDMA1_DST_YCNT_CUR                   (REG_DMA24_YCNT_CUR)
-#define MDMA1_DST_BWLCNT                     (REG_DMA24_BWLCNT)
-#define MDMA1_DST_BWLCNT_CUR                 (REG_DMA24_BWLCNT_CUR)
-#define MDMA1_DST_BWMCNT                     (REG_DMA24_BWMCNT)
-#define MDMA1_DST_BWMCNT_CUR                 (REG_DMA24_BWMCNT_CUR)
-#define MDMA2_SRC_DSCPTR_NXT                 (REG_DMA25_DSCPTR_NXT)
-#define MDMA2_SRC_ADDRSTART                  (REG_DMA25_ADDRSTART)
-#define MDMA2_SRC_CFG                        (REG_DMA25_CFG)
-#define MDMA2_SRC_XCNT                       (REG_DMA25_XCNT)
-#define MDMA2_SRC_XMOD                       (REG_DMA25_XMOD)
-#define MDMA2_SRC_YCNT                       (REG_DMA25_YCNT)
-#define MDMA2_SRC_YMOD                       (REG_DMA25_YMOD)
-#define MDMA2_SRC_DSCPTR_CUR                 (REG_DMA25_DSCPTR_CUR)
-#define MDMA2_SRC_DSCPTR_PRV                 (REG_DMA25_DSCPTR_PRV)
-#define MDMA2_SRC_ADDR_CUR                   (REG_DMA25_ADDR_CUR)
-#define MDMA2_SRC_STAT                       (REG_DMA25_STAT)
-#define MDMA2_SRC_XCNT_CUR                   (REG_DMA25_XCNT_CUR)
-#define MDMA2_SRC_YCNT_CUR                   (REG_DMA25_YCNT_CUR)
-#define MDMA2_SRC_BWLCNT                     (REG_DMA25_BWLCNT)
-#define MDMA2_SRC_BWLCNT_CUR                 (REG_DMA25_BWLCNT_CUR)
-#define MDMA2_SRC_BWMCNT                     (REG_DMA25_BWMCNT)
-#define MDMA2_SRC_BWMCNT_CUR                 (REG_DMA25_BWMCNT_CUR)
-#define MDMA2_DST_DSCPTR_NXT                 (REG_DMA26_DSCPTR_NXT)
-#define MDMA2_DST_ADDRSTART                  (REG_DMA26_ADDRSTART)
-#define MDMA2_DST_CFG                        (REG_DMA26_CFG)
-#define MDMA2_DST_XCNT                       (REG_DMA26_XCNT)
-#define MDMA2_DST_XMOD                       (REG_DMA26_XMOD)
-#define MDMA2_DST_YCNT                       (REG_DMA26_YCNT)
-#define MDMA2_DST_YMOD                       (REG_DMA26_YMOD)
-#define MDMA2_DST_DSCPTR_CUR                 (REG_DMA26_DSCPTR_CUR)
-#define MDMA2_DST_DSCPTR_PRV                 (REG_DMA26_DSCPTR_PRV)
-#define MDMA2_DST_ADDR_CUR                   (REG_DMA26_ADDR_CUR)
-#define MDMA2_DST_STAT                       (REG_DMA26_STAT)
-#define MDMA2_DST_XCNT_CUR                   (REG_DMA26_XCNT_CUR)
-#define MDMA2_DST_YCNT_CUR                   (REG_DMA26_YCNT_CUR)
-#define MDMA2_DST_BWLCNT                     (REG_DMA26_BWLCNT)
-#define MDMA2_DST_BWLCNT_CUR                 (REG_DMA26_BWLCNT_CUR)
-#define MDMA2_DST_BWMCNT                     (REG_DMA26_BWMCNT)
-#define MDMA2_DST_BWMCNT_CUR                 (REG_DMA26_BWMCNT_CUR)
-#define MDMA3_SRC_DSCPTR_NXT                 (REG_DMA27_DSCPTR_NXT)
-#define MDMA3_SRC_ADDRSTART                  (REG_DMA27_ADDRSTART)
-#define MDMA3_SRC_CFG                        (REG_DMA27_CFG)
-#define MDMA3_SRC_XCNT                       (REG_DMA27_XCNT)
-#define MDMA3_SRC_XMOD                       (REG_DMA27_XMOD)
-#define MDMA3_SRC_YCNT                       (REG_DMA27_YCNT)
-#define MDMA3_SRC_YMOD                       (REG_DMA27_YMOD)
-#define MDMA3_SRC_DSCPTR_CUR                 (REG_DMA27_DSCPTR_CUR)
-#define MDMA3_SRC_DSCPTR_PRV                 (REG_DMA27_DSCPTR_PRV)
-#define MDMA3_SRC_ADDR_CUR                   (REG_DMA27_ADDR_CUR)
-#define MDMA3_SRC_STAT                       (REG_DMA27_STAT)
-#define MDMA3_SRC_XCNT_CUR                   (REG_DMA27_XCNT_CUR)
-#define MDMA3_SRC_YCNT_CUR                   (REG_DMA27_YCNT_CUR)
-#define MDMA3_SRC_BWLCNT                     (REG_DMA27_BWLCNT)
-#define MDMA3_SRC_BWLCNT_CUR                 (REG_DMA27_BWLCNT_CUR)
-#define MDMA3_SRC_BWMCNT                     (REG_DMA27_BWMCNT)
-#define MDMA3_SRC_BWMCNT_CUR                 (REG_DMA27_BWMCNT_CUR)
-#define MDMA3_DST_DSCPTR_NXT                 (REG_DMA28_DSCPTR_NXT)
-#define MDMA3_DST_ADDRSTART                  (REG_DMA28_ADDRSTART)
-#define MDMA3_DST_CFG                        (REG_DMA28_CFG)
-#define MDMA3_DST_XCNT                       (REG_DMA28_XCNT)
-#define MDMA3_DST_XMOD                       (REG_DMA28_XMOD)
-#define MDMA3_DST_YCNT                       (REG_DMA28_YCNT)
-#define MDMA3_DST_YMOD                       (REG_DMA28_YMOD)
-#define MDMA3_DST_DSCPTR_CUR                 (REG_DMA28_DSCPTR_CUR)
-#define MDMA3_DST_DSCPTR_PRV                 (REG_DMA28_DSCPTR_PRV)
-#define MDMA3_DST_ADDR_CUR                   (REG_DMA28_ADDR_CUR)
-#define MDMA3_DST_STAT                       (REG_DMA28_STAT)
-#define MDMA3_DST_XCNT_CUR                   (REG_DMA28_XCNT_CUR)
-#define MDMA3_DST_YCNT_CUR                   (REG_DMA28_YCNT_CUR)
-#define MDMA3_DST_BWLCNT                     (REG_DMA28_BWLCNT)
-#define MDMA3_DST_BWLCNT_CUR                 (REG_DMA28_BWLCNT_CUR)
-#define MDMA3_DST_BWMCNT                     (REG_DMA28_BWMCNT)
-#define MDMA3_DST_BWMCNT_CUR                 (REG_DMA28_BWMCNT_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_NXT             (REG_DMA29_DSCPTR_NXT)
-#define EPPI0_CH0_DMA_ADDRSTART              (REG_DMA29_ADDRSTART)
-#define EPPI0_CH0_DMA_CFG                    (REG_DMA29_CFG)
-#define EPPI0_CH0_DMA_XCNT                   (REG_DMA29_XCNT)
-#define EPPI0_CH0_DMA_XMOD                   (REG_DMA29_XMOD)
-#define EPPI0_CH0_DMA_YCNT                   (REG_DMA29_YCNT)
-#define EPPI0_CH0_DMA_YMOD                   (REG_DMA29_YMOD)
-#define EPPI0_CH0_DMA_DSCPTR_CUR             (REG_DMA29_DSCPTR_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_PRV             (REG_DMA29_DSCPTR_PRV)
-#define EPPI0_CH0_DMA_ADDR_CUR               (REG_DMA29_ADDR_CUR)
-#define EPPI0_CH0_DMA_STAT                   (REG_DMA29_STAT)
-#define EPPI0_CH0_DMA_XCNT_CUR               (REG_DMA29_XCNT_CUR)
-#define EPPI0_CH0_DMA_YCNT_CUR               (REG_DMA29_YCNT_CUR)
-#define EPPI0_CH0_DMA_BWLCNT                 (REG_DMA29_BWLCNT)
-#define EPPI0_CH0_DMA_BWLCNT_CUR             (REG_DMA29_BWLCNT_CUR)
-#define EPPI0_CH0_DMA_BWMCNT                 (REG_DMA29_BWMCNT)
-#define EPPI0_CH0_DMA_BWMCNT_CUR             (REG_DMA29_BWMCNT_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_NXT             (REG_DMA30_DSCPTR_NXT)
-#define EPPI0_CH1_DMA_ADDRSTART              (REG_DMA30_ADDRSTART)
-#define EPPI0_CH1_DMA_CFG                    (REG_DMA30_CFG)
-#define EPPI0_CH1_DMA_XCNT                   (REG_DMA30_XCNT)
-#define EPPI0_CH1_DMA_XMOD                   (REG_DMA30_XMOD)
-#define EPPI0_CH1_DMA_YCNT                   (REG_DMA30_YCNT)
-#define EPPI0_CH1_DMA_YMOD                   (REG_DMA30_YMOD)
-#define EPPI0_CH1_DMA_DSCPTR_CUR             (REG_DMA30_DSCPTR_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_PRV             (REG_DMA30_DSCPTR_PRV)
-#define EPPI0_CH1_DMA_ADDR_CUR               (REG_DMA30_ADDR_CUR)
-#define EPPI0_CH1_DMA_STAT                   (REG_DMA30_STAT)
-#define EPPI0_CH1_DMA_XCNT_CUR               (REG_DMA30_XCNT_CUR)
-#define EPPI0_CH1_DMA_YCNT_CUR               (REG_DMA30_YCNT_CUR)
-#define EPPI0_CH1_DMA_BWLCNT                 (REG_DMA30_BWLCNT)
-#define EPPI0_CH1_DMA_BWLCNT_CUR             (REG_DMA30_BWLCNT_CUR)
-#define EPPI0_CH1_DMA_BWMCNT                 (REG_DMA30_BWMCNT)
-#define EPPI0_CH1_DMA_BWMCNT_CUR             (REG_DMA30_BWMCNT_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_NXT             (REG_DMA31_DSCPTR_NXT)
-#define EPPI2_CH0_DMA_ADDRSTART              (REG_DMA31_ADDRSTART)
-#define EPPI2_CH0_DMA_CFG                    (REG_DMA31_CFG)
-#define EPPI2_CH0_DMA_XCNT                   (REG_DMA31_XCNT)
-#define EPPI2_CH0_DMA_XMOD                   (REG_DMA31_XMOD)
-#define EPPI2_CH0_DMA_YCNT                   (REG_DMA31_YCNT)
-#define EPPI2_CH0_DMA_YMOD                   (REG_DMA31_YMOD)
-#define EPPI2_CH0_DMA_DSCPTR_CUR             (REG_DMA31_DSCPTR_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_PRV             (REG_DMA31_DSCPTR_PRV)
-#define EPPI2_CH0_DMA_ADDR_CUR               (REG_DMA31_ADDR_CUR)
-#define EPPI2_CH0_DMA_STAT                   (REG_DMA31_STAT)
-#define EPPI2_CH0_DMA_XCNT_CUR               (REG_DMA31_XCNT_CUR)
-#define EPPI2_CH0_DMA_YCNT_CUR               (REG_DMA31_YCNT_CUR)
-#define EPPI2_CH0_DMA_BWLCNT                 (REG_DMA31_BWLCNT)
-#define EPPI2_CH0_DMA_BWLCNT_CUR             (REG_DMA31_BWLCNT_CUR)
-#define EPPI2_CH0_DMA_BWMCNT                 (REG_DMA31_BWMCNT)
-#define EPPI2_CH0_DMA_BWMCNT_CUR             (REG_DMA31_BWMCNT_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_NXT             (REG_DMA32_DSCPTR_NXT)
-#define EPPI2_CH1_DMA_ADDRSTART              (REG_DMA32_ADDRSTART)
-#define EPPI2_CH1_DMA_CFG                    (REG_DMA32_CFG)
-#define EPPI2_CH1_DMA_XCNT                   (REG_DMA32_XCNT)
-#define EPPI2_CH1_DMA_XMOD                   (REG_DMA32_XMOD)
-#define EPPI2_CH1_DMA_YCNT                   (REG_DMA32_YCNT)
-#define EPPI2_CH1_DMA_YMOD                   (REG_DMA32_YMOD)
-#define EPPI2_CH1_DMA_DSCPTR_CUR             (REG_DMA32_DSCPTR_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_PRV             (REG_DMA32_DSCPTR_PRV)
-#define EPPI2_CH1_DMA_ADDR_CUR               (REG_DMA32_ADDR_CUR)
-#define EPPI2_CH1_DMA_STAT                   (REG_DMA32_STAT)
-#define EPPI2_CH1_DMA_XCNT_CUR               (REG_DMA32_XCNT_CUR)
-#define EPPI2_CH1_DMA_YCNT_CUR               (REG_DMA32_YCNT_CUR)
-#define EPPI2_CH1_DMA_BWLCNT                 (REG_DMA32_BWLCNT)
-#define EPPI2_CH1_DMA_BWLCNT_CUR             (REG_DMA32_BWLCNT_CUR)
-#define EPPI2_CH1_DMA_BWMCNT                 (REG_DMA32_BWMCNT)
-#define EPPI2_CH1_DMA_BWMCNT_CUR             (REG_DMA32_BWMCNT_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_NXT             (REG_DMA33_DSCPTR_NXT)
-#define EPPI1_CH0_DMA_ADDRSTART              (REG_DMA33_ADDRSTART)
-#define EPPI1_CH0_DMA_CFG                    (REG_DMA33_CFG)
-#define EPPI1_CH0_DMA_XCNT                   (REG_DMA33_XCNT)
-#define EPPI1_CH0_DMA_XMOD                   (REG_DMA33_XMOD)
-#define EPPI1_CH0_DMA_YCNT                   (REG_DMA33_YCNT)
-#define EPPI1_CH0_DMA_YMOD                   (REG_DMA33_YMOD)
-#define EPPI1_CH0_DMA_DSCPTR_CUR             (REG_DMA33_DSCPTR_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_PRV             (REG_DMA33_DSCPTR_PRV)
-#define EPPI1_CH0_DMA_ADDR_CUR               (REG_DMA33_ADDR_CUR)
-#define EPPI1_CH0_DMA_STAT                   (REG_DMA33_STAT)
-#define EPPI1_CH0_DMA_XCNT_CUR               (REG_DMA33_XCNT_CUR)
-#define EPPI1_CH0_DMA_YCNT_CUR               (REG_DMA33_YCNT_CUR)
-#define EPPI1_CH0_DMA_BWLCNT                 (REG_DMA33_BWLCNT)
-#define EPPI1_CH0_DMA_BWLCNT_CUR             (REG_DMA33_BWLCNT_CUR)
-#define EPPI1_CH0_DMA_BWMCNT                 (REG_DMA33_BWMCNT)
-#define EPPI1_CH0_DMA_BWMCNT_CUR             (REG_DMA33_BWMCNT_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_NXT             (REG_DMA34_DSCPTR_NXT)
-#define EPPI1_CH1_DMA_ADDRSTART              (REG_DMA34_ADDRSTART)
-#define EPPI1_CH1_DMA_CFG                    (REG_DMA34_CFG)
-#define EPPI1_CH1_DMA_XCNT                   (REG_DMA34_XCNT)
-#define EPPI1_CH1_DMA_XMOD                   (REG_DMA34_XMOD)
-#define EPPI1_CH1_DMA_YCNT                   (REG_DMA34_YCNT)
-#define EPPI1_CH1_DMA_YMOD                   (REG_DMA34_YMOD)
-#define EPPI1_CH1_DMA_DSCPTR_CUR             (REG_DMA34_DSCPTR_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_PRV             (REG_DMA34_DSCPTR_PRV)
-#define EPPI1_CH1_DMA_ADDR_CUR               (REG_DMA34_ADDR_CUR)
-#define EPPI1_CH1_DMA_STAT                   (REG_DMA34_STAT)
-#define EPPI1_CH1_DMA_XCNT_CUR               (REG_DMA34_XCNT_CUR)
-#define EPPI1_CH1_DMA_YCNT_CUR               (REG_DMA34_YCNT_CUR)
-#define EPPI1_CH1_DMA_BWLCNT                 (REG_DMA34_BWLCNT)
-#define EPPI1_CH1_DMA_BWLCNT_CUR             (REG_DMA34_BWLCNT_CUR)
-#define EPPI1_CH1_DMA_BWMCNT                 (REG_DMA34_BWMCNT)
-#define EPPI1_CH1_DMA_BWMCNT_CUR             (REG_DMA34_BWMCNT_CUR)
-
-/* ==================================
-       DMA Error CHID Definitions
-   ================================== */
-#define CHID_SPORT0_A_DMA                      0           /* Channel A DMA */
-#define CHID_SPORT0_B_DMA                      1           /* Channel B DMA */
-#define CHID_SPORT1_A_DMA                      2           /* Channel A DMA */
-#define CHID_SPORT1_B_DMA                      3           /* Channel B DMA */
-#define CHID_SPORT2_A_DMA                      4           /* Channel A DMA */
-#define CHID_SPORT2_B_DMA                      5           /* Channel B DMA */
-#define CHID_SPI0_TXDMA                        6           /* TX DMA Channel */
-#define CHID_SPI0_RXDMA                        7           /* RX DMA Channel */
-#define CHID_SPI1_TXDMA                        8           /* TX DMA Channel */
-#define CHID_SPI1_RXDMA                        9           /* RX DMA Channel */
-#define CHID_RSI0_DMA                         10           /* DMA Channel */
-#define CHID_SDU0_DMA                         11           /* DMA */
-/*      -- RESERVED --                        12  */
-#define CHID_LP0_DMA                          13           /* DMA Channel */
-#define CHID_LP1_DMA                          14           /* DMA Channel */
-#define CHID_LP2_DMA                          15           /* DMA Channel */
-#define CHID_LP3_DMA                          16           /* DMA Channel */
-#define CHID_UART0_TXDMA                      17           /* Transmit DMA */
-#define CHID_UART0_RXDMA                      18           /* Receive DMA */
-#define CHID_UART1_TXDMA                      19           /* Transmit DMA */
-#define CHID_UART1_RXDMA                      20           /* Receive DMA */
-#define CHID_MDMA0_SRC                        21           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define CHID_MDMA0_DST                        22           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define CHID_MDMA1_SRC                        23           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define CHID_MDMA1_DST                        24           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define CHID_MDMA2_SRC                        25           /* Memory DMA Stream 2 Source Channel */
-#define CHID_MDMA2_DST                        26           /* Memory DMA Stream 2 Destination Channel */
-#define CHID_MDMA3_SRC                        27           /* Memory DMA Stream 3 Source Channel */
-#define CHID_MDMA3_DST                        28           /* Memory DMA Stream 3 Destination Channel */
-#define CHID_EPPI0_CH0_DMA                    29           /* Channel 0 DMA */
-#define CHID_EPPI0_CH1_DMA                    30           /* Channel 1 DMA */
-#define CHID_EPPI2_CH0_DMA                    31           /* Channel 0 DMA */
-#define CHID_EPPI2_CH1_DMA                    32           /* Channel 1 DMA */
-#define CHID_EPPI1_CH0_DMA                    33           /* Channel 0 DMA */
-#define CHID_EPPI1_CH1_DMA                    34           /* Channel 1 DMA */
-
-/* ==============================
-       Interrupt Definitions
-   ============================== */
-#define INTR_SEC0_ERR                          0           /* Error */
-#define INTR_CGU0_EVT                          1           /* Event */
-#define INTR_WDOG0_EXP                         2           /* Expiration */
-#define INTR_WDOG1_EXP                         3           /* Expiration */
-#define INTR_L2CTL0_ECC_ERR                    4           /* ECC Error */
-#define INTR_L2CTL0_ECC_WARNING                5           /* ECC Warning */
-#define INTR_C0_DBL_FAULT                      6           /* Core 0 Double Fault */
-#define INTR_C1_DBL_FAULT                      7           /* Core 1 Double Fault */
-#define INTR_C0_HW_ERR                         8           /* Core 0 Hardware Error */
-#define INTR_C1_HW_ERR                         9           /* Core 1 Hardware Error */
-#define INTR_C0_NMI_L1_PARITY_ERR             10           /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_C1_NMI_L1_PARITY_ERR             11           /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_TIMER0_TMR0                      12           /* Timer 0 */
-#define INTR_TIMER0_TMR1                      13           /* Timer 1 */
-#define INTR_TIMER0_TMR2                      14           /* Timer 2 */
-#define INTR_TIMER0_TMR3                      15           /* Timer 3 */
-#define INTR_TIMER0_TMR4                      16           /* Timer 4 */
-#define INTR_TIMER0_TMR5                      17           /* Timer 5 */
-#define INTR_TIMER0_TMR6                      18           /* Timer 6 */
-#define INTR_TIMER0_TMR7                      19           /* Timer 7 */
-#define INTR_TIMER0_STAT                      20           /* Status */
-#define INTR_PINT0_BLOCK                      21           /* Pin Interrupt Block */
-#define INTR_PINT1_BLOCK                      22           /* Pin Interrupt Block */
-#define INTR_PINT2_BLOCK                      23           /* Pin Interrupt Block */
-#define INTR_PINT3_BLOCK                      24           /* Pin Interrupt Block */
-#define INTR_PINT4_BLOCK                      25           /* Pin Interrupt Block */
-#define INTR_PINT5_BLOCK                      26           /* Pin Interrupt Block */
-#define INTR_CNT0_STAT                        27           /* Status */
-#define INTR_PWM0_SYNC                        28           /* Sync */
-#define INTR_PWM0_TRIP                        29           /* Trip */
-#define INTR_PWM1_SYNC                        30           /* Sync */
-#define INTR_PWM1_TRIP                        31           /* Trip */
-#define INTR_TWI0_DATA                        32           /* Data Interrupt */
-#define INTR_TWI1_DATA                        33           /* Data Interrupt */
-#define INTR_SOFT0                            34           /* Software-driven Interrupt 0 */
-#define INTR_SOFT1                            35           /* Software-driven Interrupt 1 */
-#define INTR_SOFT2                            36           /* Software-driven Interrupt 2 */
-#define INTR_SOFT3                            37           /* Software-driven Interrupt 3 */
-#define INTR_ACM0_EVT_MISS                    38           /* Event Miss */
-#define INTR_ACM0_EVT_COMPLETE                39           /* Event Complete */
-#define INTR_CAN0_RX                          40           /* Receive */
-#define INTR_CAN0_TX                          41           /* Transmit */
-#define INTR_CAN0_STAT                        42           /* Status */
-#define INTR_SPORT0_A_DMA                     43           /* Channel A DMA */
-#define INTR_SPORT0_A_STAT                    44           /* Channel A Status */
-#define INTR_SPORT0_B_DMA                     45           /* Channel B DMA */
-#define INTR_SPORT0_B_STAT                    46           /* Channel B Status */
-#define INTR_SPORT1_A_DMA                     47           /* Channel A DMA */
-#define INTR_SPORT1_A_STAT                    48           /* Channel A Status */
-#define INTR_SPORT1_B_DMA                     49           /* Channel B DMA */
-#define INTR_SPORT1_B_STAT                    50           /* Channel B Status */
-#define INTR_SPORT2_A_DMA                     51           /* Channel A DMA */
-#define INTR_SPORT2_A_STAT                    52           /* Channel A Status */
-#define INTR_SPORT2_B_DMA                     53           /* Channel B DMA */
-#define INTR_SPORT2_B_STAT                    54           /* Channel B Status */
-#define INTR_SPI0_TXDMA                       55           /* TX DMA Channel */
-#define INTR_SPI0_RXDMA                       56           /* RX DMA Channel */
-#define INTR_SPI0_STAT                        57           /* Status */
-#define INTR_SPI1_TXDMA                       58           /* TX DMA Channel */
-#define INTR_SPI1_RXDMA                       59           /* RX DMA Channel */
-#define INTR_SPI1_STAT                        60           /* Status */
-#define INTR_RSI0_DMA                         61           /* DMA Channel */
-#define INTR_RSI0_INT0                        62           /* Interrupt 0 */
-#define INTR_RSI0_INT1                        63           /* Interrupt 1 */
-#define INTR_SDU0_DMA                         64           /* DMA */
-/*      -- RESERVED --                        65  */
-/*      -- RESERVED --                        66  */
-/*      -- RESERVED --                        67  */
-#define INTR_EMAC0_STAT                       68           /* Status */
-/*      -- RESERVED --                        69  */
-#define INTR_EMAC1_STAT                       70           /* Status */
-/*      -- RESERVED --                        71  */
-#define INTR_LP0_DMA                          72           /* DMA Channel */
-#define INTR_LP0_STAT                         73           /* Status */
-#define INTR_LP1_DMA                          74           /* DMA Channel */
-#define INTR_LP1_STAT                         75           /* Status */
-#define INTR_LP2_DMA                          76           /* DMA Channel */
-#define INTR_LP2_STAT                         77           /* Status */
-#define INTR_LP3_DMA                          78           /* DMA Channel */
-#define INTR_LP3_STAT                         79           /* Status */
-#define INTR_UART0_TXDMA                      80           /* Transmit DMA */
-#define INTR_UART0_RXDMA                      81           /* Receive DMA */
-#define INTR_UART0_STAT                       82           /* Status */
-#define INTR_UART1_TXDMA                      83           /* Transmit DMA */
-#define INTR_UART1_RXDMA                      84           /* Receive DMA */
-#define INTR_UART1_STAT                       85           /* Status */
-#define INTR_MDMA0_SRC                        86           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define INTR_MDMA0_DST                        87           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define INTR_CRC0_DCNTEXP                     88           /* Datacount expiration */
-#define INTR_CRC0_ERR                         89           /* Error */
-#define INTR_MDMA1_SRC                        90           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define INTR_MDMA1_DST                        91           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define INTR_CRC1_DCNTEXP                     92           /* Datacount expiration */
-#define INTR_CRC1_ERR                         93           /* Error */
-#define INTR_MDMA2_SRC                        94           /* Memory DMA Stream 2 Source Channel */
-#define INTR_MDMA2_DST                        95           /* Memory DMA Stream 2 Destination Channel */
-#define INTR_MDMA3_SRC                        96           /* Memory DMA Stream 3 Source Channel */
-#define INTR_MDMA3_DST                        97           /* Memory DMA Stream 3 Destination Channel */
-#define INTR_EPPI0_CH0_DMA                    98           /* Channel 0 DMA */
-#define INTR_EPPI0_CH1_DMA                    99           /* Channel 1 DMA */
-#define INTR_EPPI0_STAT                      100           /* Status */
-#define INTR_EPPI2_CH0_DMA                   101           /* Channel 0 DMA */
-#define INTR_EPPI2_CH1_DMA                   102           /* Channel 1 DMA */
-#define INTR_EPPI2_STAT                      103           /* Status */
-#define INTR_EPPI1_CH0_DMA                   104           /* Channel 0 DMA */
-#define INTR_EPPI1_CH1_DMA                   105           /* Channel 1 DMA */
-#define INTR_EPPI1_STAT                      106           /* Status */
-#define INTR_USB0_STAT                       122           /* Status/FIFO Data Ready */
-#define INTR_USB0_DATA                       123           /* DMA Status/Transfer Complete */
-#define INTR_TRU0_INT0                       124           /* Interrupt 0 */
-#define INTR_TRU0_INT1                       125           /* Interrupt 1 */
-#define INTR_TRU0_INT2                       126           /* Interrupt 2 */
-#define INTR_TRU0_INT3                       127           /* Interrupt 3 */
-#define INTR_DMAC_ERR                        128           /* DMA Controller Error */
-#define INTR_CGU0_ERR                        129           /* Error */
-/*      -- RESERVED --                       130  */
-#define INTR_DPM0_EVT                        131           /* Event */
-/*      -- RESERVED --                       132  */
-#define INTR_SWU0_EVT                        133           /* Event */
-#define INTR_SWU1_EVT                        134           /* Event */
-#define INTR_SWU2_EVT                        135           /* Event */
-#define INTR_SWU3_EVT                        136           /* Event */
-#define INTR_SWU4_EVT                        137           /* Event */
-#define INTR_SWU5_EVT                        138           /* Event */
-#define INTR_SWU6_EVT                        139           /* Event */
-
-/* ==============================
-       Parameters
-   ============================== */
-
-
-/* Generic System Module Parameters */
-
-#define PARAM_SYS0_NUM_BMODE                          3
-#define PARAM_SYS0_NUM_CORES                          2
-#define PARAM_SYS0_NUM_MDMA_STREAMS                   4
-#define PARAM_SYS0_NUM_RSVD_INT                       7
-#define PARAM_SYS0_NUM_RSVD_TRIG                      6
-#define PARAM_SYS0_NUM_SW_INT                         4
-#define PARAM_SYS0_NUM_SW_TRIG                        6
-
-
-
-
-/* RSI Parameters */
-
-#define PARAM_RSI0_NUM_DATA                           8
-#define PARAM_RSI0_NUM_INT                            2
-
-
-
-/* Link Port Parameters */
-
-#define PARAM_LP0_NUM_DATA                            8
-#define PARAM_LP1_NUM_DATA                            8
-#define PARAM_LP2_NUM_DATA                            8
-#define PARAM_LP3_NUM_DATA                            8
-
-
-/* General Purpose Timer Block Parameters */
-
-#define PARAM_TIMER0_NUMTIMERS                        8
-
-
-
-
-
-/* General Purpose Input/Output Parameters */
-
-#define PARAM_PORTA_PORT_WIDTH                       16
-#define PARAM_PORTB_PORT_WIDTH                       16
-#define PARAM_PORTC_PORT_WIDTH                       16
-#define PARAM_PORTD_PORT_WIDTH                       16
-#define PARAM_PORTE_PORT_WIDTH                       16
-#define PARAM_PORTF_PORT_WIDTH                       16
-#define PARAM_PORTG_PORT_WIDTH                       16
-
-
-
-
-/* Static Memory Controller Parameters */
-
-#define PARAM_SMC0_NUM_ABE                            2
-#define PARAM_SMC0_NUM_ADDR                          26
-#define PARAM_SMC0_NUM_AMS                            4
-#define PARAM_SMC0_NUM_DATA                          16
-
-
-
-/* EPPI Parameters */
-
-#define PARAM_EPPI0_MAXWIDTH                         24
-#define PARAM_EPPI0_NUM_DATA                         24
-#define PARAM_EPPI1_MAXWIDTH                         24
-#define PARAM_EPPI1_NUM_DATA                         18
-#define PARAM_EPPI2_MAXWIDTH                         24
-#define PARAM_EPPI2_NUM_DATA                         18
-
-
-/* Pulse-Width Modulator Parameters */
-
-#define PARAM_PWM0_ASYM_DEADTIME                      0
-#define PARAM_PWM0_COMPRESS                           1
-#define PARAM_PWM0_DOUBLE_UPDATE                      0
-#define PARAM_PWM0_FULL_DUTY_REGS                     0
-#define PARAM_PWM0_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM0_LO_HP_REGS                         0
-#define PARAM_PWM0_NUM_TRIP                           2
-#define PARAM_PWM0_NUM_TRIP_PINS                      2
-#define PARAM_PWM0_NUM_TRIP_TRIG                      0
-#define PARAM_PWM0_REVID_MAJOR                        0
-#define PARAM_PWM0_REVID_REV                          0
-#define PARAM_PWM1_ASYM_DEADTIME                      0
-#define PARAM_PWM1_COMPRESS                           1
-#define PARAM_PWM1_DOUBLE_UPDATE                      0
-#define PARAM_PWM1_FULL_DUTY_REGS                     0
-#define PARAM_PWM1_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM1_LO_HP_REGS                         0
-#define PARAM_PWM1_NUM_TRIP                           2
-#define PARAM_PWM1_NUM_TRIP_PINS                      2
-#define PARAM_PWM1_NUM_TRIP_TRIG                      0
-#define PARAM_PWM1_REVID_MAJOR                        0
-#define PARAM_PWM1_REVID_REV                          0
-
-
-/* Video Subsystem Registers Parameters */
-
-#define PARAM_VID0_PIXC_ABSENT                        1
-#define PARAM_VID0_PVP_ABSENT                         1
-
-
-
-/* System Debug Unit Parameters */
-
-#define PARAM_SDU0_IDCODE_PRID                        0
-#define PARAM_SDU0_IDCODE_REVID                       0
-
-
-/* Ethernet MAC Parameters */
-
-#define PARAM_EMAC0_NUM_RX                            2
-#define PARAM_EMAC0_NUM_TX                            2
-#define PARAM_EMAC1_NUM_RX                            2
-#define PARAM_EMAC1_NUM_TX                            2
-
-
-
-/* Serial Peripheral Interface Parameters */
-
-#define PARAM_SPI0_MEM_MAPPED                         0
-#define PARAM_SPI0_NUM_SEL                            7
-#define PARAM_SPI0_PTM_EXISTS                         1
-#define PARAM_SPI0_REVID_MAJOR                        3
-#define PARAM_SPI0_REVID_REV                          0
-#define PARAM_SPI1_MEM_MAPPED                         0
-#define PARAM_SPI1_NUM_SEL                            7
-#define PARAM_SPI1_PTM_EXISTS                         1
-#define PARAM_SPI1_REVID_MAJOR                        3
-#define PARAM_SPI1_REVID_REV                          0
-
-
-
-/* ACM Parameters */
-
-#define PARAM_ACM0_NUM_ADDR                           5
-#define PARAM_ACM0_NUM_TRIG                           2
-
-
-/* DDR Parameters */
-
-#define PARAM_DMC0_NUM_ADDR                          14
-#define PARAM_DMC0_NUM_BA                             3
-#define PARAM_DMC0_NUM_CS                             1
-#define PARAM_DMC0_NUM_DATA                          16
-
-
-/* System Cross Bar Parameters */
-
-#define PARAM_SCB0_NUM_MASTERS                        6
-#define PARAM_SCB0_NUM_SLOTS                         32
-#define PARAM_SCB1_NUM_MASTERS                        1
-#define PARAM_SCB1_NUM_SLOTS                         32
-#define PARAM_SCB2_NUM_MASTERS                        1
-#define PARAM_SCB2_NUM_SLOTS                         32
-#define PARAM_SCB3_NUM_MASTERS                        1
-#define PARAM_SCB3_NUM_SLOTS                         32
-#define PARAM_SCB4_NUM_MASTERS                        1
-#define PARAM_SCB4_NUM_SLOTS                         32
-#define PARAM_SCB5_NUM_MASTERS                        1
-#define PARAM_SCB5_NUM_SLOTS                         32
-#define PARAM_SCB6_NUM_MASTERS                        1
-#define PARAM_SCB6_NUM_SLOTS                         32
-#define PARAM_SCB7_NUM_MASTERS                        1
-#define PARAM_SCB7_NUM_SLOTS                         32
-#define PARAM_SCB8_NUM_MASTERS                        1
-#define PARAM_SCB8_NUM_SLOTS                         32
-#define PARAM_SCB9_NUM_MASTERS                        1
-#define PARAM_SCB9_NUM_SLOTS                         32
-#define PARAM_SCB10_NUM_MASTERS                       3
-#define PARAM_SCB10_NUM_SLOTS                        32
-#define PARAM_SCB11_NUM_MASTERS                       7
-#define PARAM_SCB11_NUM_SLOTS                        32
-
-
-
-/* System Event Controller Parameters */
-
-#define PARAM_SEC0_CCOUNT                             2
-#define PARAM_SEC0_SCOUNT                           140
-
-
-/* Trigger Routing Unit Parameters */
-
-#define PARAM_TRU0_NUM_INTS                           4
-#define PARAM_TRU0_NUM_TRIGS                          4
-#define PARAM_TRU0_SSRCOUNT                          87
-
-
-/* Reset Control Unit Parameters */
-
-#define PARAM_RCU0_CCOUNT                             2
-#define PARAM_RCU0_CRCTL_CR_INIT                      2
-#define PARAM_RCU0_CRSTAT_CR_INIT                     3
-#define PARAM_RCU0_SICOUNT                            2
-#define PARAM_RCU0_SVECT_INIT                     65440
-
-
-/* System Protection Unit Parameters */
-
-#define PARAM_SPU0_CM_COUNT                           2
-#define PARAM_SPU0_END_POINT_COUNT                   86
-#define PARAM_SPU0_SM_COUNT                           2
-
-
-/* Clock Generation Unit Parameters */
-
-#define PARAM_CGU0_CSEL_DEFAULT                       4
-#define PARAM_CGU0_DSEL_DEFAULT                       8
-#define PARAM_CGU0_MSEL_DEFAULT                      16
-#define PARAM_CGU0_OSEL_DEFAULT                      16
-#define PARAM_CGU0_PLLBP_DEFAULT                      0
-#define PARAM_CGU0_S0SEL_DEFAULT                      2
-#define PARAM_CGU0_S1SEL_DEFAULT                      2
-#define PARAM_CGU0_SYSSEL_DEFAULT                     8
-
-
-/* Dynamic Power Management Parameters */
-
-#define PARAM_DPM0_NUM_CCLK                           2
-#define PARAM_DPM0_NUM_HV                             8
-#define PARAM_DPM0_NUM_SCLK                           4
-#define PARAM_DPM0_NUM_WAKE                           8
-
-
-
-/* Universal Serial Bus Controller Parameters */
-
-#define PARAM_USB0_DMA_CHAN                           8
-#define PARAM_USB0_DYN_FIFO_SIZE                      1
-#define PARAM_USB0_FS_PHY                             0
-#define PARAM_USB0_HS_PHY                             1
-#define PARAM_USB0_LOOPBACK                           1
-#define PARAM_USB0_NUM_ENDPTS                        12
-#define PARAM_USB0_NUM_ENDPTS_MINUS_1                11
-
-
-/* Data Memory Unit Parameters */
-
-#define PARAM_L1DM0_L1_BASE_ADDRESS          1111111110
-
-
-
-
-
-
-
-
-/* ===================================
-       Trigger Master Definitions
-   =================================== */
-/*      -- RESERVED --                         0  */
-#define TRGM_CGU0_EVT                          1           /* Event */
-#define TRGM_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGM_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGM_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGM_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGM_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGM_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGM_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGM_TIMER0_TMR7                       9           /* Timer 7 */
-#define TRGM_PINT0_BLOCK                      10           /* Pin Interrupt Block */
-#define TRGM_PINT1_BLOCK                      11           /* Pin Interrupt Block */
-#define TRGM_PINT2_BLOCK                      12           /* Pin Interrupt Block */
-#define TRGM_PINT3_BLOCK                      13           /* Pin Interrupt Block */
-#define TRGM_PINT4_BLOCK                      14           /* Pin Interrupt Block */
-#define TRGM_PINT5_BLOCK                      15           /* Pin Interrupt Block */
-#define TRGM_CNT0_STAT                        16           /* Status */
-#define TRGM_PWM0_SYNC                        17           /* Sync */
-#define TRGM_PWM1_SYNC                        18           /* Sync */
-#define TRGM_ACM0_EVT_COMPLETE                19           /* Event Complete */
-#define TRGM_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGM_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGM_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGM_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGM_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGM_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGM_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGM_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGM_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGM_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGM_RSI0_DMA                         30           /* DMA Channel */
-#define TRGM_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGM_EMAC0_STAT                       33           /* Status */
-#define TRGM_EMAC1_STAT                       34           /* Status */
-#define TRGM_LP0_DMA                          35           /* DMA Channel */
-#define TRGM_LP1_DMA                          36           /* DMA Channel */
-#define TRGM_LP2_DMA                          37           /* DMA Channel */
-#define TRGM_LP3_DMA                          38           /* DMA Channel */
-#define TRGM_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGM_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGM_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGM_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGM_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGM_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGM_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGM_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGM_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGM_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGM_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGM_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGM_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGM_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGM_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGM_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGM_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGM_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGM_USB0_DATA                        69           /* DMA Status/Transfer Complete */
-/*      -- RESERVED --                        70  */
-#define TRGM_SEC0_FAULT                       71           /* Fault */
-#define TRGM_SOFT0                            72           /* Software-driven Trigger 0 */
-#define TRGM_SOFT1                            73           /* Software-driven Trigger 1 */
-#define TRGM_SOFT2                            74           /* Software-driven Trigger 2 */
-#define TRGM_SOFT3                            75           /* Software-driven Trigger 3 */
-#define TRGM_SOFT4                            76           /* Software-driven Trigger 4 */
-#define TRGM_SOFT5                            77           /* Software-driven Trigger 5 */
-#define TRGM_SWU0_EVT                         80           /* Event */
-#define TRGM_SWU1_EVT                         81           /* Event */
-#define TRGM_SWU2_EVT                         82           /* Event */
-#define TRGM_SWU3_EVT                         83           /* Event */
-#define TRGM_SWU4_EVT                         84           /* Event */
-#define TRGM_SWU5_EVT                         85           /* Event */
-#define TRGM_SWU6_EVT                         86           /* Event */
-
-/* ===================================
-       Trigger Slave Definitions
-   =================================== */
-#define TRGS_RCU0_SYSRST0                      0           /* System Reset 0 */
-#define TRGS_RCU0_SYSRST1                      1           /* System Reset 1 */
-#define TRGS_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGS_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGS_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGS_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGS_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGS_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGS_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGS_TIMER0_TMR7                       9           /* Timer 7 */
-/*      -- RESERVED --                        10  */
-/*      -- RESERVED --                        11  */
-#define TRGS_C0_NMI_S0                        12           /* NMI (Core 0) Slave 0 */
-#define TRGS_C0_NMI_S1                        13           /* NMI (Core 0) Slave 1 */
-#define TRGS_C1_NMI_S0                        14           /* NMI (Core 1) Slave 0 */
-#define TRGS_C1_NMI_S1                        15           /* NMI (Core 1) Slave 1 */
-#define TRGS_TRU0_IRQ0                        16           /* Interrupt Request 0 */
-#define TRGS_TRU0_IRQ1                        17           /* Interrupt Request 1 */
-#define TRGS_TRU0_IRQ2                        18           /* Interrupt Request 2 */
-#define TRGS_TRU0_IRQ3                        19           /* Interrupt Request 3 */
-#define TRGS_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGS_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGS_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGS_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGS_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGS_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGS_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGS_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGS_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGS_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGS_RSI0_DMA                         30           /* DMA Channel */
-#define TRGS_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGS_ACM0_TRIG2                       33           /* Trigger Input 2 */
-#define TRGS_ACM0_TRIG3                       34           /* Trigger Input 3 */
-#define TRGS_LP0_DMA                          35           /* DMA Channel */
-#define TRGS_LP1_DMA                          36           /* DMA Channel */
-#define TRGS_LP2_DMA                          37           /* DMA Channel */
-#define TRGS_LP3_DMA                          38           /* DMA Channel */
-#define TRGS_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGS_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGS_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGS_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGS_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGS_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGS_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGS_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGS_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGS_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGS_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGS_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGS_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGS_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGS_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGS_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGS_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGS_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGS_SDU0_SLAVE                       69           /* Slave Trigger */
-/*      -- RESERVED --                        70  */
-#define TRGS_C0_WAKE0                         71           /* Core 0 Wakeup Input 0 */
-#define TRGS_C0_WAKE1                         72           /* Core 0 Wakeup Input 1 */
-#define TRGS_C0_WAKE2                         73           /* Core 0 Wakeup Input 2 */
-#define TRGS_C0_WAKE3                         74           /* Core 0 Wakeup Input 3 */
-#define TRGS_C1_WAKE0                         75           /* Core 1 Wakeup Input 0 */
-#define TRGS_C1_WAKE1                         76           /* Core 1 Wakeup Input 1 */
-#define TRGS_C1_WAKE2                         77           /* Core 1 Wakeup Input 2 */
-#define TRGS_C1_WAKE3                         78           /* Core 1 Wakeup Input 3 */
-/*      -- RESERVED --                        79  */
-#define TRGS_SWU0_EVT                         80           /* Event */
-#define TRGS_SWU1_EVT                         81           /* Event */
-#define TRGS_SWU2_EVT                         82           /* Event */
-#define TRGS_SWU3_EVT                         83           /* Event */
-#define TRGS_SWU4_EVT                         84           /* Event */
-#define TRGS_SWU5_EVT                         85           /* Event */
-#define TRGS_SWU6_EVT                         86           /* Event */
-
-
-/* ============================================================================
-       Memory Map Macros
-   ============================================================================ */
-
-/* ADSP-BF607 is a multi-core processor */
-
-#define MEM_NUM_CORES                   2
-
-/* Internal memory range */
-
-#define MEM_BASE_INTERNAL               0xC0000000
-#define MEM_END_INTERNAL                0xFFFFFFFF
-#define MEM_SIZE_INTERNAL               0x40000000
-
-/* External memory range */
-
-#define MEM_BASE_EXTERNAL               0x00000000
-#define MEM_END_EXTERNAL                0xBFFFFFFF
-#define MEM_SIZE_EXTERNAL               0xC0000000
-
-/* Shared DDR2 or LPDDR Memory (256 MB) */
-
-#define MEM_BASE_DDR                    0x00000000
-#define MEM_END_DDR                     0x0FFFFFFF
-#define MEM_SIZE_DDR                    0x10000000
-
-/* Shared Async Memory (256 MB) */
-
-#define MEM_BASE_ASYNC                  0xB0000000
-#define MEM_END_ASYNC                   0xBFFFFFFF
-#define MEM_SIZE_ASYNC                  0x10000000
-
-/* Shared Async Memory Bank 0 (64 MB) */
-
-#define MEM_BASE_ASYNC_0                0xB0000000
-#define MEM_END_ASYNC_0                 0xB3FFFFFF
-#define MEM_SIZE_ASYNC_0                0x4000000
-
-/* Shared Async Memory Bank 1 (64 MB) */
-
-#define MEM_BASE_ASYNC_1                0xB4000000
-#define MEM_END_ASYNC_1                 0xB7FFFFFF
-#define MEM_SIZE_ASYNC_1                0x4000000
-
-/* Shared Async Memory Bank 2 (64 MB) */
-
-#define MEM_BASE_ASYNC_2                0xB8000000
-#define MEM_END_ASYNC_2                 0xBBFFFFFF
-#define MEM_SIZE_ASYNC_2                0x4000000
-
-/* Shared Async Memory Bank 3 (64 MB) */
-
-#define MEM_BASE_ASYNC_3                0xBC000000
-#define MEM_END_ASYNC_3                 0xBFFFFFFF
-#define MEM_SIZE_ASYNC_3                0x4000000
-
-/* Shared L2 ROM (32 KB) */
-
-#define MEM_BASE_L2_ROM                 0xC8000000
-#define MEM_END_L2_ROM                  0xC8007FFF
-#define MEM_SIZE_L2_ROM                 0x8000
-
-/* Shared L2 SRAM (256 KB) */
-
-#define MEM_BASE_L2_SRAM                0xC8080000
-#define MEM_END_L2_SRAM                 0xC80BFFFF
-#define MEM_SIZE_L2_SRAM                0x40000
-
-/* Core 1 L1 Data Bank A (32 KB) */
-
-#define MEM_C1_BASE_L1DM_A              0xFF400000
-#define MEM_C1_END_L1DM_A               0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A              0x8000
-
-/* Core 1 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM         0xFF400000
-#define MEM_C1_END_L1DM_A_SRAM          0xFF403FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 1 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM_CACHE   0xFF404000
-#define MEM_C1_END_L1DM_A_SRAM_CACHE    0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Data Bank B (32 KB) */
-
-#define MEM_C1_BASE_L1DM_B              0xFF500000
-#define MEM_C1_END_L1DM_B               0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B              0x8000
-
-/* Core 1 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM         0xFF500000
-#define MEM_C1_END_L1DM_B_SRAM          0xFF503FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 1 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM_CACHE   0xFF504000
-#define MEM_C1_END_L1DM_B_SRAM_CACHE    0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Instruction (80 KB) */
-
-#define MEM_C1_BASE_L1IM                0xFF600000
-#define MEM_C1_END_L1IM                 0xFF613FFF
-#define MEM_C1_SIZE_L1IM                0x14000
-
-/* Core 1 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM           0xFF600000
-#define MEM_C1_END_L1IM_SRAM            0xFF60FFFF
-#define MEM_C1_SIZE_L1IM_SRAM           0x10000
-
-/* Core 1 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM_CACHE     0xFF610000
-#define MEM_C1_END_L1IM_SRAM_CACHE      0xFF613FFF
-#define MEM_C1_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 1 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C1_BASE_L1_XPAD_SRAM        0xFF700000
-#define MEM_C1_END_L1_XPAD_SRAM         0xFF700FFF
-#define MEM_C1_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Core 0 L1 Data Bank A (32 KB) */
-
-#define MEM_C0_BASE_L1DM_A              0xFF800000
-#define MEM_C0_END_L1DM_A               0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A              0x8000
-
-/* Core 0 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM         0xFF800000
-#define MEM_C0_END_L1DM_A_SRAM          0xFF803FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 0 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM_CACHE   0xFF804000
-#define MEM_C0_END_L1DM_A_SRAM_CACHE    0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Data Bank B (32 KB) */
-
-#define MEM_C0_BASE_L1DM_B              0xFF900000
-#define MEM_C0_END_L1DM_B               0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B              0x8000
-
-/* Core 0 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM         0xFF900000
-#define MEM_C0_END_L1DM_B_SRAM          0xFF903FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 0 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM_CACHE   0xFF904000
-#define MEM_C0_END_L1DM_B_SRAM_CACHE    0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Instruction (80 KB) */
-
-#define MEM_C0_BASE_L1IM                0xFFA00000
-#define MEM_C0_END_L1IM                 0xFFA13FFF
-#define MEM_C0_SIZE_L1IM                0x14000
-
-/* Core 0 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM           0xFFA00000
-#define MEM_C0_END_L1IM_SRAM            0xFFA0FFFF
-#define MEM_C0_SIZE_L1IM_SRAM           0x10000
-
-/* Core 0 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM_CACHE     0xFFA10000
-#define MEM_C0_END_L1IM_SRAM_CACHE      0xFFA13FFF
-#define MEM_C0_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 0 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C0_BASE_L1_XPAD_SRAM        0xFFB00000
-#define MEM_C0_END_L1_XPAD_SRAM         0xFFB00FFF
-#define MEM_C0_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Shared System MMR Registers (2 MB) */
-
-#define MEM_BASE_MMR_SYSTEM             0xFFC00000
-#define MEM_END_MMR_SYSTEM              0xFFDFFFFF
-#define MEM_SIZE_MMR_SYSTEM             0x200000
-
-/* Core 0 Core MMR Registers (2 MB) */
-
-#define MEM_C0_BASE_MMR_CORE            0xFFE00000
-#define MEM_C0_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C0_SIZE_MMR_CORE            0x200000
-
-/* Core 1 Core MMR Registers (2 MB) */
-
-#define MEM_C1_BASE_MMR_CORE            0xFFE00000
-#define MEM_C1_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C1_SIZE_MMR_CORE            0x200000
-
-
-#endif	/* end ifndef _DEF_BF607_H */
diff --git a/libgloss/bfin/include/defBF608.h b/libgloss/bfin/include/defBF608.h
deleted file mode 100644
index 147eeb478..000000000
--- a/libgloss/bfin/include/defBF608.h
+++ /dev/null
@@ -1,19426 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* ================================================================================
-
-     Project      :   ADSP-BF608
-     File         :   defBF608.h
-     Description  :   Register Definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ================================================================================ */
-
-#ifndef _DEF_BF608_H
-#define _DEF_BF608_H
-
-#if defined (_MISRA_RULES)
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
-#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
-#endif /* _MISRA_RULES */
-
-/* do not add casts to literal constants in assembly code */
-#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
-#define _ADI_MSK( mask, type ) (mask) /* Make a bitmask */
-#else
-#define _ADI_MSK( mask, type ) ((type)(mask)) /* Make a bitmask */
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#ifndef __ADI_GENERATED_DEF_HEADERS__
-#define __ADI_GENERATED_DEF_HEADERS__    1
-#endif
-
-/* MMR modules defined for the ADSP-BF608 */
-
-#define __ADI_HAS_SYS__           1
-#define __ADI_HAS_SIMENV__        1
-#define __ADI_HAS_CNT__           1
-#define __ADI_HAS_RSI__           1
-#define __ADI_HAS_CAN__           1
-#define __ADI_HAS_LP__            1
-#define __ADI_HAS_TIMER__         1
-#define __ADI_HAS_CRC__           1
-#define __ADI_HAS_TWI__           1
-#define __ADI_HAS_UART__          1
-#define __ADI_HAS_PORT__          1
-#define __ADI_HAS_PADS__          1
-#define __ADI_HAS_PINT__          1
-#define __ADI_HAS_SMC__           1
-#define __ADI_HAS_WDOG__          1
-#define __ADI_HAS_EPPI__          1
-#define __ADI_HAS_PIXC__          1
-#define __ADI_HAS_PVP__           1
-#define __ADI_HAS_PWM__           1
-#define __ADI_HAS_VID__           1
-#define __ADI_HAS_SWU__           1
-#define __ADI_HAS_SDU__           1
-#define __ADI_HAS_EMAC__          1
-#define __ADI_HAS_SPORT__         1
-#define __ADI_HAS_SPI__           1
-#define __ADI_HAS_DMA__           1
-#define __ADI_HAS_ACM__           1
-#define __ADI_HAS_DMC__           1
-#define __ADI_HAS_SCB__           1
-#define __ADI_HAS_L2CTL__         1
-#define __ADI_HAS_SEC__           1
-#define __ADI_HAS_TRU__           1
-#define __ADI_HAS_RCU__           1
-#define __ADI_HAS_SPU__           1
-#define __ADI_HAS_CGU__           1
-#define __ADI_HAS_DPM__           1
-#define __ADI_HAS_EFS__           1
-#define __ADI_HAS_USB__           1
-#define __ADI_HAS_L1DM__          1
-#define __ADI_HAS_L1IM__          1
-#define __ADI_HAS_ICU__           1
-#define __ADI_HAS_TMR__           1
-#define __ADI_HAS_DBG__           1
-#define __ADI_HAS_TB__            1
-#define __ADI_HAS_WP__            1
-#define __ADI_HAS_PF__            1
-
-/* =========================
-        REGFILE
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ASTAT                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ASTAT_VS                        25                               /* Sticky version of ASTAT_V */
-#define BITP_ASTAT_V                         24                               /* Overflow Flag */
-#define BITP_ASTAT_AV1S                      19                               /* Sticky Overflow Flag 1 */
-#define BITP_ASTAT_AV1                       18                               /* Overflow Flag 1 */
-#define BITP_ASTAT_AV0S                      17                               /* Sticky Overflow Flag 0 */
-#define BITP_ASTAT_AV0                       16                               /* Overflow Flag 0 */
-#define BITP_ASTAT_AC1                       13                               /* Carry Flag 1 */
-#define BITP_ASTAT_AC0                       12                               /* Carry Flag 0 */
-#define BITP_ASTAT_RND_MOD                    8                               /* Rounding Mode */
-#define BITP_ASTAT_AQ                         6                               /* Quotient Bit */
-#define BITP_ASTAT_CC                         5                               /* Condition Code */
-#define BITP_ASTAT_V_COPY                     3                               /* Overflow Flag */
-#define BITP_ASTAT_AC0_COPY                   2                               /* Carry Flag 0 */
-#define BITP_ASTAT_AN                         1                               /* Negative Flag */
-#define BITP_ASTAT_AZ                         0                               /* Zero Flag */
-#define BITM_ASTAT_VS                        (_ADI_MSK(0x02000000,uint32_t))  /* Sticky version of ASTAT_V */
-#define BITM_ASTAT_V                         (_ADI_MSK(0x01000000,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AV1S                      (_ADI_MSK(0x00080000,uint32_t))  /* Sticky Overflow Flag 1 */
-#define BITM_ASTAT_AV1                       (_ADI_MSK(0x00040000,uint32_t))  /* Overflow Flag 1 */
-#define BITM_ASTAT_AV0S                      (_ADI_MSK(0x00020000,uint32_t))  /* Sticky Overflow Flag 0 */
-#define BITM_ASTAT_AV0                       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow Flag 0 */
-#define BITM_ASTAT_AC1                       (_ADI_MSK(0x00002000,uint32_t))  /* Carry Flag 1 */
-#define BITM_ASTAT_AC0                       (_ADI_MSK(0x00001000,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_RND_MOD                   (_ADI_MSK(0x00000100,uint32_t))  /* Rounding Mode */
-#define BITM_ASTAT_AQ                        (_ADI_MSK(0x00000040,uint32_t))  /* Quotient Bit */
-#define BITM_ASTAT_CC                        (_ADI_MSK(0x00000020,uint32_t))  /* Condition Code */
-#define BITM_ASTAT_V_COPY                    (_ADI_MSK(0x00000008,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AC0_COPY                  (_ADI_MSK(0x00000004,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_AN                        (_ADI_MSK(0x00000002,uint32_t))  /* Negative Flag */
-#define BITM_ASTAT_AZ                        (_ADI_MSK(0x00000001,uint32_t))  /* Zero Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LT                                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LT_ADDR                          1                               /* Loop Top Address */
-#define BITP_LT_LSB                           0
-#define BITM_LT_ADDR                         (_ADI_MSK(0xFFFFFFFE,uint32_t))  /* Loop Top Address */
-#define BITM_LT_LSB                          (_ADI_MSK(0x00000001,uint32_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEQSTAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEQSTAT_NSPECABT                19                               /* Nonspeculative access was aborted */
-#define BITP_SEQSTAT_HWERRCAUSE              14                               /* Holds cause of last hardware error generated by the core */
-#define BITP_SEQSTAT_SFTRESET                13                               /* Indicates whether the last reset was a software reset */
-#define BITP_SEQSTAT_ITESTABT                12                               /* ITEST_COMMAND was aborted */
-#define BITP_SEQSTAT_DTESTABT                11                               /* DTEST_COMMAND was aborted */
-#define BITP_SEQSTAT_SYSNMI                  10                               /* System NMI Input Active */
-#define BITP_SEQSTAT_PEIC                     9                               /* Parity Error on Instruction L1 Read for Core */
-#define BITP_SEQSTAT_PEDC                     8                               /* Parity Error on Data L1 Read for Core */
-#define BITP_SEQSTAT_PEIX                     7                               /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_PEDX                     6                               /* Parity Error on Data L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_EXCAUSE                  0                               /* Holds cause of last-executed exception */
-#define BITM_SEQSTAT_NSPECABT                (_ADI_MSK(0x00080000,uint32_t))  /* Nonspeculative access was aborted */
-#define BITM_SEQSTAT_HWERRCAUSE              (_ADI_MSK(0x0007C000,uint32_t))  /* Holds cause of last hardware error generated by the core */
-#define BITM_SEQSTAT_SFTRESET                (_ADI_MSK(0x00002000,uint32_t))  /* Indicates whether the last reset was a software reset */
-#define BITM_SEQSTAT_ITESTABT                (_ADI_MSK(0x00001000,uint32_t))  /* ITEST_COMMAND was aborted */
-#define BITM_SEQSTAT_DTESTABT                (_ADI_MSK(0x00000800,uint32_t))  /* DTEST_COMMAND was aborted */
-#define BITM_SEQSTAT_SYSNMI                  (_ADI_MSK(0x00000400,uint32_t))  /* System NMI Input Active */
-#define BITM_SEQSTAT_PEIC                    (_ADI_MSK(0x00000200,uint32_t))  /* Parity Error on Instruction L1 Read for Core */
-#define BITM_SEQSTAT_PEDC                    (_ADI_MSK(0x00000100,uint32_t))  /* Parity Error on Data L1 Read for Core */
-#define BITM_SEQSTAT_PEIX                    (_ADI_MSK(0x00000080,uint32_t))  /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITM_SEQSTAT_PEDX                    (_ADI_MSK(0x00000040,uint32_t))  /* Parity Error on Data L1 Read for L2 Transfer */
-
-#define BITM_SEQSTAT_EXCAUSE                 (_ADI_MSK(0x0000003F,uint32_t))  /* Holds cause of last-executed exception */
-#define ENUM_SEQSTAT_EXINST                  (_ADI_MSK(0x00000000,uint32_t))  /* EXCAUSE: EXCPT Instruction */
-#define ENUM_SEQSTAT_SSTEP                   (_ADI_MSK(0x00000010,uint32_t))  /* EXCAUSE: Single Step */
-#define ENUM_SEQSTAT_EMUTROV                 (_ADI_MSK(0x00000011,uint32_t))  /* EXCAUSE: Trace Buffer */
-#define ENUM_SEQSTAT_UNDEFINST               (_ADI_MSK(0x00000021,uint32_t))  /* EXCAUSE: Undefined Instruction */
-#define ENUM_SEQSTAT_ILLCOMB                 (_ADI_MSK(0x00000022,uint32_t))  /* EXCAUSE: Illegal Combination */
-#define ENUM_SEQSTAT_DAGPROTVIOL             (_ADI_MSK(0x00000023,uint32_t))  /* EXCAUSE: DAG Protection Violation */
-#define ENUM_SEQSTAT_DAGALGN                 (_ADI_MSK(0x00000024,uint32_t))  /* EXCAUSE: DAG Misaligned Access */
-#define ENUM_SEQSTAT_UNRECOVER               (_ADI_MSK(0x00000025,uint32_t))  /* EXCAUSE: Unrecoverable Event */
-#define ENUM_SEQSTAT_DAGCPLBMISS             (_ADI_MSK(0x00000026,uint32_t))  /* EXCAUSE: DAG CPLB Miss */
-#define ENUM_SEQSTAT_DAGMCPLBH               (_ADI_MSK(0x00000027,uint32_t))  /* EXCAUSE: DAG Multiple CPLB Hits */
-#define ENUM_SEQSTAT_EMUWPMATCH              (_ADI_MSK(0x00000028,uint32_t))  /* EXCAUSE: Watchpoint Match */
-#define ENUM_SEQSTAT_IFALGN                  (_ADI_MSK(0x0000002A,uint32_t))  /* EXCAUSE: I-Fetch Misaligned Access */
-#define ENUM_SEQSTAT_IFPROTVIOL              (_ADI_MSK(0x0000002B,uint32_t))  /* EXCAUSE: I-Fetch Protection Violation */
-#define ENUM_SEQSTAT_IFCPLBMISS              (_ADI_MSK(0x0000002C,uint32_t))  /* EXCAUSE: I-Fetch CPLB Miss */
-#define ENUM_SEQSTAT_IFMCPLBH                (_ADI_MSK(0x0000002D,uint32_t))  /* EXCAUSE: I-Fetch Multiple CPLB Hits */
-#define ENUM_SEQSTAT_PROTVIOL                (_ADI_MSK(0x0000002E,uint32_t))  /* EXCAUSE: Illegal use superv. res */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SYSCFG                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SYSCFG_SNEN                      2                               /* Self-Nesting Interrupt Enable */
-#define BITP_SYSCFG_CCEN                      1                               /* Enable cycle counter */
-#define BITP_SYSCFG_SSSTEP                    0                               /* Supervisor single step */
-#define BITM_SYSCFG_SNEN                     (_ADI_MSK(0x00000004,uint32_t))  /* Self-Nesting Interrupt Enable */
-#define BITM_SYSCFG_CCEN                     (_ADI_MSK(0x00000002,uint32_t))  /* Enable cycle counter */
-#define BITM_SYSCFG_SSSTEP                   (_ADI_MSK(0x00000001,uint32_t))  /* Supervisor single step */
-
-/* ==================================================
-        CNT Registers
-   ================================================== */
-
-/* =========================
-        CNT0
-   ========================= */
-#define REG_CNT0_CFG                    0xFFC00400         /* CNT0 Configuration Register */
-#define REG_CNT0_IMSK                   0xFFC00404         /* CNT0 Interrupt Mask Register */
-#define REG_CNT0_STAT                   0xFFC00408         /* CNT0 Status Register */
-#define REG_CNT0_CMD                    0xFFC0040C         /* CNT0 Command Register */
-#define REG_CNT0_DEBNCE                 0xFFC00410         /* CNT0 Debounce Register */
-#define REG_CNT0_CNTR                   0xFFC00414         /* CNT0 Counter Register */
-#define REG_CNT0_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
-#define REG_CNT0_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
-
-/* =========================
-        CNT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CFG_INPDIS                  15                               /* CUD and CDG Pin Input Disable */
-#define BITP_CNT_CFG_BNDMODE                 12                               /* Boundary Register Mode */
-#define BITP_CNT_CFG_ZMZC                    11                               /* CZM Zeroes Counter Enable */
-#define BITP_CNT_CFG_CNTMODE                  8                               /* Counter Operating Mode */
-#define BITP_CNT_CFG_CZMINV                   6                               /* CZM Pin Polarity Invert */
-#define BITP_CNT_CFG_CUDINV                   5                               /* CUD Pin Polarity Invert */
-#define BITP_CNT_CFG_CDGINV                   4                               /* CDG Pin Polarity Invert */
-#define BITP_CNT_CFG_DEBEN                    1                               /* Debounce Enable */
-#define BITP_CNT_CFG_EN                       0                               /* Counter Enable */
-
-#define BITM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* CUD and CDG Pin Input Disable */
-#define ENUM_CNT_CFG_NO_INPDIS               (_ADI_MSK(0x00000000,uint16_t))  /* INPDIS: Enable */
-#define ENUM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* INPDIS: Pin Input Disable */
-
-#define BITM_CNT_CFG_BNDMODE                 (_ADI_MSK(0x00003000,uint16_t))  /* Boundary Register Mode */
-#define ENUM_CNT_CFG_BNDMODE_BNDCOMP         (_ADI_MSK(0x00000000,uint16_t))  /* BNDMODE: BND_COMP */
-#define ENUM_CNT_CFG_BNDMODE_BINENC          (_ADI_MSK(0x00001000,uint16_t))  /* BNDMODE: BIN_ENC */
-#define ENUM_CNT_CFG_BNDMODE_BNDCAPT         (_ADI_MSK(0x00002000,uint16_t))  /* BNDMODE: BND_CAPT */
-#define ENUM_CNT_CFG_BNDMODE_BNDAEXT         (_ADI_MSK(0x00003000,uint16_t))  /* BNDMODE: BND_AEXT */
-
-#define BITM_CNT_CFG_ZMZC                    (_ADI_MSK(0x00000800,uint16_t))  /* CZM Zeroes Counter Enable */
-#define ENUM_CNT_CFG_ZMZC_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* ZMZC: Disable */
-#define ENUM_CNT_CFG_ZMZC_EN                 (_ADI_MSK(0x00000800,uint16_t))  /* ZMZC: Enable */
-
-#define BITM_CNT_CFG_CNTMODE                 (_ADI_MSK(0x00000700,uint16_t))  /* Counter Operating Mode */
-#define ENUM_CNT_CFG_CNTMODE_QUADENC         (_ADI_MSK(0x00000000,uint16_t))  /* CNTMODE: QUAD_ENC */
-#define ENUM_CNT_CFG_CNTMODE_BINENC          (_ADI_MSK(0x00000100,uint16_t))  /* CNTMODE: BIN_ENC */
-#define ENUM_CNT_CFG_CNTMODE_UDCNT           (_ADI_MSK(0x00000200,uint16_t))  /* CNTMODE: UD_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRCNT          (_ADI_MSK(0x00000400,uint16_t))  /* CNTMODE: DIR_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRTMR          (_ADI_MSK(0x00000500,uint16_t))  /* CNTMODE: DIR_TMR */
-
-#define BITM_CNT_CFG_CZMINV                  (_ADI_MSK(0x00000040,uint16_t))  /* CZM Pin Polarity Invert */
-#define ENUM_CNT_CFG_CZMINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CZMINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CZMINV_ALO              (_ADI_MSK(0x00000040,uint16_t))  /* CZMINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CUDINV                  (_ADI_MSK(0x00000020,uint16_t))  /* CUD Pin Polarity Invert */
-#define ENUM_CNT_CFG_CUDINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CUDINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CUDINV_ALO              (_ADI_MSK(0x00000020,uint16_t))  /* CUDINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CDGINV                  (_ADI_MSK(0x00000010,uint16_t))  /* CDG Pin Polarity Invert */
-#define ENUM_CNT_CFG_CDGINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CDGINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CDGINV_ALO              (_ADI_MSK(0x00000010,uint16_t))  /* CDGINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* Debounce Enable */
-#define ENUM_CNT_CFG_DEBDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* DEBEN: Disable */
-#define ENUM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* DEBEN: Enable */
-
-#define BITM_CNT_CFG_EN                      (_ADI_MSK(0x00000001,uint16_t))  /* Counter Enable */
-#define ENUM_CNT_CFG_CNTDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Counter Disable */
-#define ENUM_CNT_CFG_CNTEN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Counter Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_IMSK_CZMZ                   10                               /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define BITP_CNT_IMSK_CZME                    9                               /* Zero Marker Error Interrupt Enable */
-#define BITP_CNT_IMSK_CZM                     8                               /* CZM Pin / Pushbutton Interrupt Enable */
-#define BITP_CNT_IMSK_CZERO                   7                               /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define BITP_CNT_IMSK_COV15                   6                               /* Bit 15 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_COV31                   5                               /* Bit 31 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_MAXC                    4                               /* Max Count Interrupt Enable */
-#define BITP_CNT_IMSK_MINC                    3                               /* Min Count Interrupt Enable */
-#define BITP_CNT_IMSK_DC                      2                               /* Downcount Interrupt enable */
-#define BITP_CNT_IMSK_UC                      1                               /* Upcount Interrupt Enable */
-#define BITP_CNT_IMSK_IC                      0                               /* Illegal Gray/Binary Code Interrupt Enable */
-
-#define BITM_CNT_IMSK_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define ENUM_CNT_IMSK_CZMZ_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZMZ: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZMZ_UMSK              (_ADI_MSK(0x00000400,uint16_t))  /* CZMZ: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error Interrupt Enable */
-#define ENUM_CNT_IMSK_CZME_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZME: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZME_UMSK              (_ADI_MSK(0x00000200,uint16_t))  /* CZME: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin / Pushbutton Interrupt Enable */
-#define ENUM_CNT_IMSK_CZM_MSK                (_ADI_MSK(0x00000000,uint16_t))  /* CZM: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZM_UMSK               (_ADI_MSK(0x00000100,uint16_t))  /* CZM: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define ENUM_CNT_IMSK_CZERO_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* CZERO: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZERO_UMSK             (_ADI_MSK(0x00000080,uint16_t))  /* CZERO: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV15_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV15: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV15_UMSK             (_ADI_MSK(0x00000040,uint16_t))  /* COV15: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV31_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV31: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV31_UMSK             (_ADI_MSK(0x00000020,uint16_t))  /* COV31: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MAXC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MAXC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MAXC_UMSK              (_ADI_MSK(0x00000010,uint16_t))  /* MAXC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MINC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MINC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MINC_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* MINC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount Interrupt enable */
-#define ENUM_CNT_IMSK_DC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* DC: Mask Interrupt */
-#define ENUM_CNT_IMSK_DC_UMSK                (_ADI_MSK(0x00000004,uint16_t))  /* DC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount Interrupt Enable */
-#define ENUM_CNT_IMSK_UC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* UC: Mask Interrupt */
-#define ENUM_CNT_IMSK_UC_UMSK                (_ADI_MSK(0x00000002,uint16_t))  /* UC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal Gray/Binary Code Interrupt Enable */
-#define ENUM_CNT_IMSK_IC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* IC: Mask Interrupt */
-#define ENUM_CNT_IMSK_IC_UMSK                (_ADI_MSK(0x00000001,uint16_t))  /* IC: Unmask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_STAT_CZMZ                   10                               /* Counter Zeroed By Zero Marker interrupt */
-#define BITP_CNT_STAT_CZME                    9                               /* Zero Marker Error interrupt */
-#define BITP_CNT_STAT_CZM                     8                               /* CZM Pin/Pushbutton interrupt */
-#define BITP_CNT_STAT_CZERO                   7                               /* CNT_CNTR Counts To Zero interrupt */
-#define BITP_CNT_STAT_COV15                   6                               /* Bit 15 overflow interrupt */
-#define BITP_CNT_STAT_COV31                   5                               /* Bit 31 overflow interrupt */
-#define BITP_CNT_STAT_MAXC                    4                               /* Max interrupt */
-#define BITP_CNT_STAT_MINC                    3                               /* Min interrupt */
-#define BITP_CNT_STAT_DC                      2                               /* Downcount interrupt */
-#define BITP_CNT_STAT_UC                      1                               /* Upcount interrupt */
-#define BITP_CNT_STAT_IC                      0                               /* Illegal gray/binary code interrupt */
-#define BITM_CNT_STAT_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed By Zero Marker interrupt */
-#define BITM_CNT_STAT_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error interrupt */
-#define BITM_CNT_STAT_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin/Pushbutton interrupt */
-#define BITM_CNT_STAT_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero interrupt */
-#define BITM_CNT_STAT_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 overflow interrupt */
-#define BITM_CNT_STAT_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 overflow interrupt */
-#define BITM_CNT_STAT_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max interrupt */
-#define BITM_CNT_STAT_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min interrupt */
-#define BITM_CNT_STAT_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount interrupt */
-#define BITM_CNT_STAT_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount interrupt */
-#define BITM_CNT_STAT_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal gray/binary code interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CMD_W1ZMONCE                12                               /* Write 1 Zero Marker Clear Once Enable */
-#define BITP_CNT_CMD_W1LMAXMIN               10                               /* Write 1 MAX copy from MIN */
-#define BITP_CNT_CMD_W1LMAXCNT                9                               /* Write 1 MAX capture from CNTR */
-#define BITP_CNT_CMD_W1LMAXZERO               8                               /* Write 1 MAX to zero */
-#define BITP_CNT_CMD_W1LMINMAX                7                               /* Write 1 MIN copy from MAX */
-#define BITP_CNT_CMD_W1LMINCNT                5                               /* Write 1 MIN capture from CNTR */
-#define BITP_CNT_CMD_W1LMINZERO               4                               /* Write 1 MIN to zero */
-#define BITP_CNT_CMD_W1LCNTMAX                3                               /* Write 1 CNTR load from MAX */
-#define BITP_CNT_CMD_W1LCNTMIN                2                               /* Write 1 CNTR load from MIN */
-#define BITP_CNT_CMD_W1LCNTZERO               0                               /* Write 1 CNTR to zero */
-#define BITM_CNT_CMD_W1ZMONCE                (_ADI_MSK(0x00001000,uint16_t))  /* Write 1 Zero Marker Clear Once Enable */
-#define BITM_CNT_CMD_W1LMAXMIN               (_ADI_MSK(0x00000400,uint16_t))  /* Write 1 MAX copy from MIN */
-#define BITM_CNT_CMD_W1LMAXCNT               (_ADI_MSK(0x00000200,uint16_t))  /* Write 1 MAX capture from CNTR */
-#define BITM_CNT_CMD_W1LMAXZERO              (_ADI_MSK(0x00000100,uint16_t))  /* Write 1 MAX to zero */
-#define BITM_CNT_CMD_W1LMINMAX               (_ADI_MSK(0x00000080,uint16_t))  /* Write 1 MIN copy from MAX */
-#define BITM_CNT_CMD_W1LMINCNT               (_ADI_MSK(0x00000020,uint16_t))  /* Write 1 MIN capture from CNTR */
-#define BITM_CNT_CMD_W1LMINZERO              (_ADI_MSK(0x00000010,uint16_t))  /* Write 1 MIN to zero */
-#define BITM_CNT_CMD_W1LCNTMAX               (_ADI_MSK(0x00000008,uint16_t))  /* Write 1 CNTR load from MAX */
-#define BITM_CNT_CMD_W1LCNTMIN               (_ADI_MSK(0x00000004,uint16_t))  /* Write 1 CNTR load from MIN */
-#define BITM_CNT_CMD_W1LCNTZERO              (_ADI_MSK(0x00000001,uint16_t))  /* Write 1 CNTR to zero */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_DEBNCE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_DEBNCE_DPRESCALE             0                               /* Debounce Prescale */
-#define BITM_CNT_DEBNCE_DPRESCALE            (_ADI_MSK(0x0000001F,uint16_t))  /* Debounce Prescale */
-
-/* ==================================================
-        RSI Registers
-   ================================================== */
-
-/* =========================
-        RSI0
-   ========================= */
-#define REG_RSI0_CTL                    0xFFC00604         /* RSI0 Control Register */
-#define REG_RSI0_ARG                    0xFFC00608         /* RSI0 Argument Register */
-#define REG_RSI0_CMD                    0xFFC0060C         /* RSI0 Command Register */
-#define REG_RSI0_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
-#define REG_RSI0_RESP0                  0xFFC00614         /* RSI0 Response 0 Register */
-#define REG_RSI0_RESP1                  0xFFC00618         /* RSI0 Response 1 Register */
-#define REG_RSI0_RESP2                  0xFFC0061C         /* RSI0 Response 2 Register */
-#define REG_RSI0_RESP3                  0xFFC00620         /* RSI0 Response 3 Register */
-#define REG_RSI0_DATA_TMR               0xFFC00624         /* RSI0 Data Timer Register */
-#define REG_RSI0_DATA_LEN               0xFFC00628         /* RSI0 Data Length Register */
-#define REG_RSI0_DATA_CTL               0xFFC0062C         /* RSI0 Data Control Register */
-#define REG_RSI0_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
-#define REG_RSI0_XFRSTAT                0xFFC00634         /* RSI0 Status Register */
-#define REG_RSI0_XFRSTAT_CLR            0xFFC00638         /* RSI0 Status Clear Register */
-#define REG_RSI0_XFR_IMSK0              0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
-#define REG_RSI0_XFR_IMSK1              0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
-#define REG_RSI0_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
-#define REG_RSI0_CEATA                  0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
-#define REG_RSI0_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
-#define REG_RSI0_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
-#define REG_RSI0_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
-#define REG_RSI0_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
-#define REG_RSI0_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
-#define REG_RSI0_STAT0                  0xFFC006C0         /* RSI0 Exception Status Register */
-#define REG_RSI0_IMSK0                  0xFFC006C4         /* RSI0 Exception Mask Register */
-#define REG_RSI0_CFG                    0xFFC006C8         /* RSI0 Configuration Register */
-#define REG_RSI0_RD_WAIT                0xFFC006CC         /* RSI0 Read Wait Enable Register */
-#define REG_RSI0_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
-
-/* =========================
-        RSI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CTL_CARDTYPE                13                               /* Type of Card */
-#define BITP_RSI_CTL_BUSWID                  11                               /* Wide Bus Mode Enable */
-#define BITP_RSI_CTL_BYPASS                  10                               /* Bypass clock divisor */
-#define BITP_RSI_CTL_PWRSAVE                  9                               /* Power Save Enable */
-#define BITP_RSI_CTL_CLKEN                    8                               /* RSI_CLK Bus Clock Enable */
-#define BITP_RSI_CTL_CLKDIV                   0                               /* RSI_CLK Divisor */
-#define BITM_RSI_CTL_CARDTYPE                (_ADI_MSK(0x0000E000,uint16_t))  /* Type of Card */
-#define BITM_RSI_CTL_BUSWID                  (_ADI_MSK(0x00001800,uint16_t))  /* Wide Bus Mode Enable */
-#define BITM_RSI_CTL_BYPASS                  (_ADI_MSK(0x00000400,uint16_t))  /* Bypass clock divisor */
-#define BITM_RSI_CTL_PWRSAVE                 (_ADI_MSK(0x00000200,uint16_t))  /* Power Save Enable */
-#define BITM_RSI_CTL_CLKEN                   (_ADI_MSK(0x00000100,uint16_t))  /* RSI_CLK Bus Clock Enable */
-#define BITM_RSI_CTL_CLKDIV                  (_ADI_MSK(0x000000FF,uint16_t))  /* RSI_CLK Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CMD_CHKBUSY                 12                               /* Check Busy Condition */
-#define BITP_RSI_CMD_CRCDIS                  11                               /* Disable CRC Check */
-#define BITP_RSI_CMD_EN                      10                               /* Command Enable */
-#define BITP_RSI_CMD_PNDEN                    9                               /* Command Pending enabled */
-#define BITP_RSI_CMD_IEN                      8                               /* Command Interrupt Enabled */
-#define BITP_RSI_CMD_LRSP                     7                               /* Long Response */
-#define BITP_RSI_CMD_RSP                      6                               /* Response */
-#define BITP_RSI_CMD_IDX                      0                               /* Command Index */
-#define BITM_RSI_CMD_CHKBUSY                 (_ADI_MSK(0x00001000,uint16_t))  /* Check Busy Condition */
-#define BITM_RSI_CMD_CRCDIS                  (_ADI_MSK(0x00000800,uint16_t))  /* Disable CRC Check */
-#define BITM_RSI_CMD_EN                      (_ADI_MSK(0x00000400,uint16_t))  /* Command Enable */
-#define BITM_RSI_CMD_PNDEN                   (_ADI_MSK(0x00000200,uint16_t))  /* Command Pending enabled */
-#define BITM_RSI_CMD_IEN                     (_ADI_MSK(0x00000100,uint16_t))  /* Command Interrupt Enabled */
-#define BITM_RSI_CMD_LRSP                    (_ADI_MSK(0x00000080,uint16_t))  /* Long Response */
-#define BITM_RSI_CMD_RSP                     (_ADI_MSK(0x00000040,uint16_t))  /* Response */
-#define BITM_RSI_CMD_IDX                     (_ADI_MSK(0x0000003F,uint16_t))  /* Command Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RESP_CMD                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RESP_CMD_VALUE               0                               /* Response Command */
-#define BITM_RSI_RESP_CMD_VALUE              (_ADI_MSK(0x0000003F,uint16_t))  /* Response Command */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_DATA_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_DATA_CTL_CEATAIEN            9                               /* Ceata Command Completion Interrupt Enable */
-#define BITP_RSI_DATA_CTL_CEATAMODE           8                               /* Ceata Mode enable */
-#define BITP_RSI_DATA_CTL_DMAEN               3                               /* Data Transfer DMA Enable */
-#define BITP_RSI_DATA_CTL_DATMODE             2                               /* Data Transfer Mode */
-#define BITP_RSI_DATA_CTL_DATDIR              1                               /* Data Transfer Direction */
-#define BITP_RSI_DATA_CTL_DATEN               0                               /* Data Transfer Enable */
-#define BITM_RSI_DATA_CTL_CEATAIEN           (_ADI_MSK(0x00000200,uint16_t))  /* Ceata Command Completion Interrupt Enable */
-#define BITM_RSI_DATA_CTL_CEATAMODE          (_ADI_MSK(0x00000100,uint16_t))  /* Ceata Mode enable */
-#define BITM_RSI_DATA_CTL_DMAEN              (_ADI_MSK(0x00000008,uint16_t))  /* Data Transfer DMA Enable */
-#define BITM_RSI_DATA_CTL_DATMODE            (_ADI_MSK(0x00000004,uint16_t))  /* Data Transfer Mode */
-#define BITM_RSI_DATA_CTL_DATDIR             (_ADI_MSK(0x00000002,uint16_t))  /* Data Transfer Direction */
-#define BITM_RSI_DATA_CTL_DATEN              (_ADI_MSK(0x00000001,uint16_t))  /* Data Transfer Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_RXFIFORDY           21                               /* Receive FIFO Available */
-#define BITP_RSI_XFRSTAT_TXFIFORDY           20                               /* Transmit FIFO Available */
-#define BITP_RSI_XFRSTAT_RXFIFOZERO          19                               /* Receive FIFO Empty */
-#define BITP_RSI_XFRSTAT_TXFIFOZERO          18                               /* Transmit FIFO Empty */
-#define BITP_RSI_XFRSTAT_RXFIFOFULL          17                               /* Receive FIFO Full */
-#define BITP_RSI_XFRSTAT_TXFIFOFULL          16                               /* Transmit FIFO Full */
-#define BITP_RSI_XFRSTAT_RXFIFOSTAT          15                               /* Receive FIFO Status */
-#define BITP_RSI_XFRSTAT_TXFIFOSTAT          14                               /* Transmit FIFO Status */
-#define BITP_RSI_XFRSTAT_RXACT               13                               /* Receive Active */
-#define BITP_RSI_XFRSTAT_TXACT               12                               /* Transmit Active */
-#define BITP_RSI_XFRSTAT_CMDACT              11                               /* Command Active */
-#define BITP_RSI_XFRSTAT_DATBLKEND           10                               /* Data Block End */
-#define BITP_RSI_XFRSTAT_SBITERR              9                               /* Start Bit Error */
-#define BITP_RSI_XFRSTAT_DATEND               8                               /* Data End */
-#define BITP_RSI_XFRSTAT_CMDSENT              7                               /* Command Sent */
-#define BITP_RSI_XFRSTAT_RESPEND              6                               /* Command Response End */
-#define BITP_RSI_XFRSTAT_RXOVER               5                               /* Receive Over run */
-#define BITP_RSI_XFRSTAT_TXUNDR               4                               /* Transmit Under run */
-#define BITP_RSI_XFRSTAT_DATTO                3                               /* Data Timeout */
-#define BITP_RSI_XFRSTAT_CMDTO                2                               /* CMD Timeout */
-#define BITP_RSI_XFRSTAT_DATCRCFAIL           1                               /* Data CRC Fail */
-#define BITP_RSI_XFRSTAT_CMDCRCFAIL           0                               /* CMD CRC Fail */
-#define BITM_RSI_XFRSTAT_RXFIFORDY           (_ADI_MSK(0x00200000,uint32_t))  /* Receive FIFO Available */
-#define BITM_RSI_XFRSTAT_TXFIFORDY           (_ADI_MSK(0x00100000,uint32_t))  /* Transmit FIFO Available */
-#define BITM_RSI_XFRSTAT_RXFIFOZERO          (_ADI_MSK(0x00080000,uint32_t))  /* Receive FIFO Empty */
-#define BITM_RSI_XFRSTAT_TXFIFOZERO          (_ADI_MSK(0x00040000,uint32_t))  /* Transmit FIFO Empty */
-#define BITM_RSI_XFRSTAT_RXFIFOFULL          (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Full */
-#define BITM_RSI_XFRSTAT_TXFIFOFULL          (_ADI_MSK(0x00010000,uint32_t))  /* Transmit FIFO Full */
-#define BITM_RSI_XFRSTAT_RXFIFOSTAT          (_ADI_MSK(0x00008000,uint32_t))  /* Receive FIFO Status */
-#define BITM_RSI_XFRSTAT_TXFIFOSTAT          (_ADI_MSK(0x00004000,uint32_t))  /* Transmit FIFO Status */
-#define BITM_RSI_XFRSTAT_RXACT               (_ADI_MSK(0x00002000,uint32_t))  /* Receive Active */
-#define BITM_RSI_XFRSTAT_TXACT               (_ADI_MSK(0x00001000,uint32_t))  /* Transmit Active */
-#define BITM_RSI_XFRSTAT_CMDACT              (_ADI_MSK(0x00000800,uint32_t))  /* Command Active */
-#define BITM_RSI_XFRSTAT_DATBLKEND           (_ADI_MSK(0x00000400,uint32_t))  /* Data Block End */
-#define BITM_RSI_XFRSTAT_SBITERR             (_ADI_MSK(0x00000200,uint32_t))  /* Start Bit Error */
-#define BITM_RSI_XFRSTAT_DATEND              (_ADI_MSK(0x00000100,uint32_t))  /* Data End */
-#define BITM_RSI_XFRSTAT_CMDSENT             (_ADI_MSK(0x00000080,uint32_t))  /* Command Sent */
-#define BITM_RSI_XFRSTAT_RESPEND             (_ADI_MSK(0x00000040,uint32_t))  /* Command Response End */
-#define BITM_RSI_XFRSTAT_RXOVER              (_ADI_MSK(0x00000020,uint32_t))  /* Receive Over run */
-#define BITM_RSI_XFRSTAT_TXUNDR              (_ADI_MSK(0x00000010,uint32_t))  /* Transmit Under run */
-#define BITM_RSI_XFRSTAT_DATTO               (_ADI_MSK(0x00000008,uint32_t))  /* Data Timeout */
-#define BITM_RSI_XFRSTAT_CMDTO               (_ADI_MSK(0x00000004,uint32_t))  /* CMD Timeout */
-#define BITM_RSI_XFRSTAT_DATCRCFAIL          (_ADI_MSK(0x00000002,uint32_t))  /* Data CRC Fail */
-#define BITM_RSI_XFRSTAT_CMDCRCFAIL          (_ADI_MSK(0x00000001,uint32_t))  /* CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT_CLR                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_CLR_DATBLKEND       10                               /* Data Block End Status */
-#define BITP_RSI_XFRSTAT_CLR_STRTBITERR       9                               /* Start Bit Error Status */
-#define BITP_RSI_XFRSTAT_CLR_DATEND           8                               /* Data End Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDSENT          7                               /* Command Sent Status */
-#define BITP_RSI_XFRSTAT_CLR_RESPEND          6                               /* Command Response End Status */
-#define BITP_RSI_XFRSTAT_CLR_RXOVER           5                               /* Receive Over run Status */
-#define BITP_RSI_XFRSTAT_CLR_TXUNDR           4                               /* Transmit Under run Status */
-#define BITP_RSI_XFRSTAT_CLR_DATTO            3                               /* Data Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDTO            2                               /* CMD Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_DATCRCFAIL       1                               /* Data CRC Fail Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDCRCFAIL       0                               /* CMD CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_DATBLKEND       (_ADI_MSK(0x00000400,uint16_t))  /* Data Block End Status */
-#define BITM_RSI_XFRSTAT_CLR_STRTBITERR      (_ADI_MSK(0x00000200,uint16_t))  /* Start Bit Error Status */
-#define BITM_RSI_XFRSTAT_CLR_DATEND          (_ADI_MSK(0x00000100,uint16_t))  /* Data End Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDSENT         (_ADI_MSK(0x00000080,uint16_t))  /* Command Sent Status */
-#define BITM_RSI_XFRSTAT_CLR_RESPEND         (_ADI_MSK(0x00000040,uint16_t))  /* Command Response End Status */
-#define BITM_RSI_XFRSTAT_CLR_RXOVER          (_ADI_MSK(0x00000020,uint16_t))  /* Receive Over run Status */
-#define BITM_RSI_XFRSTAT_CLR_TXUNDR          (_ADI_MSK(0x00000010,uint16_t))  /* Transmit Under run Status */
-#define BITM_RSI_XFRSTAT_CLR_DATTO           (_ADI_MSK(0x00000008,uint16_t))  /* Data Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDTO           (_ADI_MSK(0x00000004,uint16_t))  /* CMD Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_DATCRCFAIL      (_ADI_MSK(0x00000002,uint16_t))  /* Data CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDCRCFAIL      (_ADI_MSK(0x00000001,uint16_t))  /* CMD CRC Fail Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK0_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK0_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK0_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK0_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK0_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK0_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK0_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK0_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK0_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK0_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK0_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK0_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK0_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK0_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK0_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK0_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK0_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK0_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK0_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK0_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK0_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK0_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK0_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK0_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK0_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK0_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK0_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK0_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK0_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK0_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK0_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK0_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK0_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK0_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK0_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK0_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK0_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK0_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK0_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK0_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK1_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK1_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK1_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK1_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK1_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK1_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK1_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK1_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK1_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK1_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK1_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK1_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK1_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK1_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK1_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK1_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK1_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK1_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK1_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK1_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK1_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK1_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK1_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK1_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK1_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK1_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK1_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK1_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK1_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK1_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK1_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK1_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK1_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK1_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK1_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK1_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK1_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK1_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK1_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK1_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_FIFO_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_FIFO_CNT_VALUE               0                               /* FIFO Count */
-#define BITM_RSI_FIFO_CNT_VALUE              (_ADI_MSK(0x00007FFF,uint16_t))  /* FIFO Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CEATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CEATA_INT_DIS                0                               /* CEATA Disable Interrupt */
-#define BITM_RSI_CEATA_INT_DIS               (_ADI_MSK(0x00000001,uint32_t))  /* CEATA Disable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BOOT_TCNTR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BOOT_TCNTR_HOLD              8                               /* Boot Hold Time */
-#define BITP_RSI_BOOT_TCNTR_SETUP             0                               /* Boot Setup Time */
-#define BITM_RSI_BOOT_TCNTR_HOLD             (_ADI_MSK(0x0000FF00,uint16_t))  /* Boot Hold Time */
-#define BITM_RSI_BOOT_TCNTR_SETUP            (_ADI_MSK(0x000000FF,uint16_t))  /* Boot Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BLKSZ                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BLKSZ_VALUE                  0                               /* Size of Each Block of Data */
-#define BITM_RSI_BLKSZ_VALUE                 (_ADI_MSK(0x00001FFF,uint16_t))  /* Size of Each Block of Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_STAT0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_STAT0_BUSYMODE              31                               /* Card is in Busy mode */
-#define BITP_RSI_STAT0_SLPMODE               30                               /* Card in Sleep Mode */
-#define BITP_RSI_STAT0_CARDRDY               17                               /* Card Ready */
-#define BITP_RSI_STAT0_SLPWKPTOUT            16                               /* Sleep Wakeup Timer Expired */
-#define BITP_RSI_STAT0_WKPDONE               15                               /* Card Entered Standby state */
-#define BITP_RSI_STAT0_SLPDONE               14                               /* Card Entered Sleep State */
-#define BITP_RSI_STAT0_BACKDONE              13                               /* Correct Boot Ack is received */
-#define BITP_RSI_STAT0_BACKBAD               12                               /* Boot Ack received is corrupted */
-#define BITP_RSI_STAT0_BACKTO                11                               /* Boot Acknowledge Timeout */
-#define BITP_RSI_STAT0_BDATTO                10                               /* Boot Data Timeout */
-#define BITP_RSI_STAT0_BHOLDEXP               9                               /* Boot Hold Time Expiry */
-#define BITP_RSI_STAT0_BSETUPEXP              8                               /* Boot Setup Time Expiry */
-#define BITP_RSI_STAT0_CEATAINT               5                               /* CEATA Interrupt */
-#define BITP_RSI_STAT0_SDCARD                 4                               /* SD Card Detected */
-#define BITP_RSI_STAT0_SDIOINT                1                               /* SDIO Interrupt */
-#define BITM_RSI_STAT0_BUSYMODE              (_ADI_MSK(0x80000000,uint32_t))  /* Card is in Busy mode */
-#define BITM_RSI_STAT0_SLPMODE               (_ADI_MSK(0x40000000,uint32_t))  /* Card in Sleep Mode */
-#define BITM_RSI_STAT0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Card Ready */
-#define BITM_RSI_STAT0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Sleep Wakeup Timer Expired */
-#define BITM_RSI_STAT0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Card Entered Standby state */
-#define BITM_RSI_STAT0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Card Entered Sleep State */
-#define BITM_RSI_STAT0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Correct Boot Ack is received */
-#define BITM_RSI_STAT0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Boot Ack received is corrupted */
-#define BITM_RSI_STAT0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Boot Acknowledge Timeout */
-#define BITM_RSI_STAT0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Boot Data Timeout */
-#define BITM_RSI_STAT0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Boot Hold Time Expiry */
-#define BITM_RSI_STAT0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Boot Setup Time Expiry */
-#define BITM_RSI_STAT0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* CEATA Interrupt */
-#define BITM_RSI_STAT0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* SD Card Detected */
-#define BITM_RSI_STAT0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_IMSK0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_IMSK0_CARDRDY               17                               /* Mask Interrupt for Card Ready */
-#define BITP_RSI_IMSK0_SLPWKPTOUT            16                               /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITP_RSI_IMSK0_WKPDONE               15                               /* Mask Interrupt for Card Entered Standby state */
-#define BITP_RSI_IMSK0_SLPDONE               14                               /* Mask Interrupt for Card Entered Sleep State */
-#define BITP_RSI_IMSK0_BACKDONE              13                               /* Mask Interrupt for Correct Boot Ack is received */
-#define BITP_RSI_IMSK0_BACKBAD               12                               /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITP_RSI_IMSK0_BACKTO                11                               /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITP_RSI_IMSK0_BDATTO                10                               /* Mask Interrupt for Boot Data Timeout */
-#define BITP_RSI_IMSK0_BHOLDEXP               9                               /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITP_RSI_IMSK0_BSETUPEXP              8                               /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITP_RSI_IMSK0_CEATAINT               5                               /* Mask CEATA Interrupt */
-#define BITP_RSI_IMSK0_SDCARD                 4                               /* Mask Interrupt for SD Card Detected */
-#define BITP_RSI_IMSK0_SDIOINT                1                               /* Mask SDIO Interrupt */
-#define BITM_RSI_IMSK0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Mask Interrupt for Card Ready */
-#define BITM_RSI_IMSK0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITM_RSI_IMSK0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Mask Interrupt for Card Entered Standby state */
-#define BITM_RSI_IMSK0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Mask Interrupt for Card Entered Sleep State */
-#define BITM_RSI_IMSK0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Mask Interrupt for Correct Boot Ack is received */
-#define BITM_RSI_IMSK0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITM_RSI_IMSK0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITM_RSI_IMSK0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Mask Interrupt for Boot Data Timeout */
-#define BITM_RSI_IMSK0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITM_RSI_IMSK0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITM_RSI_IMSK0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* Mask CEATA Interrupt */
-#define BITM_RSI_IMSK0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* Mask Interrupt for SD Card Detected */
-#define BITM_RSI_IMSK0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* Mask SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CFG_BACKEN                  14                               /* Boot Acknowledge enabled */
-#define BITP_RSI_CFG_MMCBMODE                13                               /* MMC Boot Mode select */
-#define BITP_RSI_CFG_MMCBEN                  12                               /* MMC Boot Enabled */
-#define BITP_RSI_CFG_OPENDRAIN               11                               /* MC_CMD Output Control */
-#define BITP_RSI_CFG_PWRON                    9                               /* 11 - RSI Enabled */
-#define BITP_RSI_CFG_IEBYPDIS                 8                               /* Disabled IE Bypass */
-#define BITP_RSI_CFG_DAT3PUP                  6                               /* Pull-Up SD_DAT3 */
-#define BITP_RSI_CFG_DATPUP                   5                               /* Pull-Up SD_DAT */
-#define BITP_RSI_CFG_RST                      4                               /* SDMMC Reset */
-#define BITP_RSI_CFG_MWINEN                   3                               /* Moving Window Enable */
-#define BITP_RSI_CFG_SD4EN                    2                               /* SDIO 4-Bit Enable */
-#define BITP_RSI_CFG_CLKSEN                   0                               /* Clocks Enable */
-#define BITM_RSI_CFG_BACKEN                  (_ADI_MSK(0x00004000,uint16_t))  /* Boot Acknowledge enabled */
-#define BITM_RSI_CFG_MMCBMODE                (_ADI_MSK(0x00002000,uint16_t))  /* MMC Boot Mode select */
-#define BITM_RSI_CFG_MMCBEN                  (_ADI_MSK(0x00001000,uint16_t))  /* MMC Boot Enabled */
-#define BITM_RSI_CFG_OPENDRAIN               (_ADI_MSK(0x00000800,uint16_t))  /* MC_CMD Output Control */
-#define BITM_RSI_CFG_PWRON                   (_ADI_MSK(0x00000600,uint16_t))  /* 11 - RSI Enabled */
-#define BITM_RSI_CFG_IEBYPDIS                (_ADI_MSK(0x00000100,uint16_t))  /* Disabled IE Bypass */
-#define BITM_RSI_CFG_DAT3PUP                 (_ADI_MSK(0x00000040,uint16_t))  /* Pull-Up SD_DAT3 */
-#define BITM_RSI_CFG_DATPUP                  (_ADI_MSK(0x00000020,uint16_t))  /* Pull-Up SD_DAT */
-#define BITM_RSI_CFG_RST                     (_ADI_MSK(0x00000010,uint16_t))  /* SDMMC Reset */
-#define BITM_RSI_CFG_MWINEN                  (_ADI_MSK(0x00000008,uint16_t))  /* Moving Window Enable */
-#define BITM_RSI_CFG_SD4EN                   (_ADI_MSK(0x00000004,uint16_t))  /* SDIO 4-Bit Enable */
-#define BITM_RSI_CFG_CLKSEN                  (_ADI_MSK(0x00000001,uint16_t))  /* Clocks Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RD_WAIT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RD_WAIT_REQUEST              0                               /* Read Wait Request */
-#define BITM_RSI_RD_WAIT_REQUEST             (_ADI_MSK(0x00000001,uint16_t))  /* Read Wait Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID0                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID0_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID0_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID1_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID1_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID2_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID2_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID3                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID3_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID3_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ==================================================
-        Controller Area Network Registers
-   ================================================== */
-
-/* =========================
-        CAN0
-   ========================= */
-#define REG_CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration 1 Register */
-#define REG_CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction 1 Register */
-#define REG_CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set 1 Register */
-#define REG_CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset 1 Register */
-#define REG_CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge 1 Register */
-#define REG_CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge 1 Register */
-#define REG_CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending 1 Register */
-#define REG_CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost 1 Register */
-#define REG_CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define REG_CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define REG_CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define REG_CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling 1 Register */
-#define REG_CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define REG_CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration 2 Register */
-#define REG_CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction 2 Register */
-#define REG_CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set 2 Register */
-#define REG_CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset 2 Register */
-#define REG_CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge 2 Register */
-#define REG_CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge 2 Register */
-#define REG_CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending 2 Register */
-#define REG_CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost 2 Register */
-#define REG_CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define REG_CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define REG_CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define REG_CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling 2 Register */
-#define REG_CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define REG_CAN0_CLK                    0xFFC00A80         /* CAN0 Clock Register */
-#define REG_CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
-#define REG_CAN0_DBG                    0xFFC00A88         /* CAN0 Debug Register */
-#define REG_CAN0_STAT                   0xFFC00A8C         /* CAN0 Status Register */
-#define REG_CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
-#define REG_CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status Register */
-#define REG_CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask Register */
-#define REG_CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag Register */
-#define REG_CAN0_CTL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
-#define REG_CAN0_INT                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
-#define REG_CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
-#define REG_CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
-#define REG_CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
-#define REG_CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
-#define REG_CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
-#define REG_CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
-#define REG_CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox ID 1 Register */
-
-/* =========================
-        CAN
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC1_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD1_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS1_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR1_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA1_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA1_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP1_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML1_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF1_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF1_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM1_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH1_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS1_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC2_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD2_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS2_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR2_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA2_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA2_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP2_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML2_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF2_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF2_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM2_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH2_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS2_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CLK_BRP                      0                               /* Bit Rate Prescaler */
-#define BITM_CAN_CLK_BRP                     (_ADI_MSK(0x000003FF,uint16_t))  /* Bit Rate Prescaler */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TIMING                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TIMING_SJW                   8                               /* Synchronization Jump Width */
-#define BITP_CAN_TIMING_SAM                   7                               /* Sampling */
-#define BITP_CAN_TIMING_TSEG2                 4                               /* Time Segment 2 */
-#define BITP_CAN_TIMING_TSEG1                 0                               /* Time Segment 1 */
-#define BITM_CAN_TIMING_SJW                  (_ADI_MSK(0x00000300,uint16_t))  /* Synchronization Jump Width */
-#define BITM_CAN_TIMING_SAM                  (_ADI_MSK(0x00000080,uint16_t))  /* Sampling */
-#define BITM_CAN_TIMING_TSEG2                (_ADI_MSK(0x00000070,uint16_t))  /* Time Segment 2 */
-#define BITM_CAN_TIMING_TSEG1                (_ADI_MSK(0x0000000F,uint16_t))  /* Time Segment 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_DBG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_DBG_CDE                     15                               /* CAN Debug Mode Enable */
-#define BITP_CAN_DBG_MRB                      5                               /* Mode Read Back */
-#define BITP_CAN_DBG_MAA                      4                               /* Mode Auto Acknowledge */
-#define BITP_CAN_DBG_DIL                      3                               /* Disable Internal Loop */
-#define BITP_CAN_DBG_DTO                      2                               /* Disable Tx Output Pin */
-#define BITP_CAN_DBG_DRI                      1                               /* Disable Receive Input Pin */
-#define BITP_CAN_DBG_DEC                      0                               /* Disable Transmit and Receive Error Counters */
-#define BITM_CAN_DBG_CDE                     (_ADI_MSK(0x00008000,uint16_t))  /* CAN Debug Mode Enable */
-#define BITM_CAN_DBG_MRB                     (_ADI_MSK(0x00000020,uint16_t))  /* Mode Read Back */
-#define BITM_CAN_DBG_MAA                     (_ADI_MSK(0x00000010,uint16_t))  /* Mode Auto Acknowledge */
-#define BITM_CAN_DBG_DIL                     (_ADI_MSK(0x00000008,uint16_t))  /* Disable Internal Loop */
-#define BITM_CAN_DBG_DTO                     (_ADI_MSK(0x00000004,uint16_t))  /* Disable Tx Output Pin */
-#define BITM_CAN_DBG_DRI                     (_ADI_MSK(0x00000002,uint16_t))  /* Disable Receive Input Pin */
-#define BITM_CAN_DBG_DEC                     (_ADI_MSK(0x00000001,uint16_t))  /* Disable Transmit and Receive Error Counters */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_STAT_REC                    15                               /* Receive Mode */
-#define BITP_CAN_STAT_TRM                    14                               /* Transmit Mode */
-#define BITP_CAN_STAT_MBPTR                   8                               /* Mailbox Pointer */
-#define BITP_CAN_STAT_CCA                     7                               /* CAN Configuration Mode Acknowledge */
-#define BITP_CAN_STAT_CSA                     6                               /* CAN Suspend Mode Acknowledge */
-#define BITP_CAN_STAT_EBO                     3                               /* CAN Error Bus Off Mode */
-#define BITP_CAN_STAT_EP                      2                               /* CAN Error Passive Mode */
-#define BITP_CAN_STAT_WR                      1                               /* CAN Receive Warning Flag */
-#define BITP_CAN_STAT_WT                      0                               /* CAN Transmit Warning Flag */
-#define BITM_CAN_STAT_REC                    (_ADI_MSK(0x00008000,uint16_t))  /* Receive Mode */
-#define BITM_CAN_STAT_TRM                    (_ADI_MSK(0x00004000,uint16_t))  /* Transmit Mode */
-#define BITM_CAN_STAT_MBPTR                  (_ADI_MSK(0x00001F00,uint16_t))  /* Mailbox Pointer */
-#define BITM_CAN_STAT_CCA                    (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Acknowledge */
-#define BITM_CAN_STAT_CSA                    (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Acknowledge */
-#define BITM_CAN_STAT_EBO                    (_ADI_MSK(0x00000008,uint16_t))  /* CAN Error Bus Off Mode */
-#define BITM_CAN_STAT_EP                     (_ADI_MSK(0x00000004,uint16_t))  /* CAN Error Passive Mode */
-#define BITM_CAN_STAT_WR                     (_ADI_MSK(0x00000002,uint16_t))  /* CAN Receive Warning Flag */
-#define BITM_CAN_STAT_WT                     (_ADI_MSK(0x00000001,uint16_t))  /* CAN Transmit Warning Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CEC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CEC_TXECNT                   8                               /* Transmit Error Counter */
-#define BITP_CAN_CEC_RXECNT                   0                               /* Receive Error Counter */
-#define BITM_CAN_CEC_TXECNT                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Counter */
-#define BITM_CAN_CEC_RXECNT                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Counter */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIS                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIS_ADIS                    10                               /* Access Denied Interrupt Status */
-#define BITP_CAN_GIS_UCEIS                    8                               /* Universal Counter Exceeded Interrupt Status */
-#define BITP_CAN_GIS_RMLIS                    7                               /* Receive Message Lost Interrupt Status */
-#define BITP_CAN_GIS_AAIS                     6                               /* Abort Acknowledge Interrupt Status */
-#define BITP_CAN_GIS_UIAIS                    5                               /* Unimplemented Address Interrupt Status */
-#define BITP_CAN_GIS_WUIS                     4                               /* Wake Up Interrupt Status */
-#define BITP_CAN_GIS_BOIS                     3                               /* Bus Off Interrupt Status */
-#define BITP_CAN_GIS_EPIS                     2                               /* Error Passive Interrupt Status */
-#define BITP_CAN_GIS_EWRIS                    1                               /* Error Warning Receive  Interrupt Status */
-#define BITP_CAN_GIS_EWTIS                    0                               /* Error Warning Transmit Interrupt Status */
-#define BITM_CAN_GIS_ADIS                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Status */
-#define BITM_CAN_GIS_UCEIS                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Status */
-#define BITM_CAN_GIS_RMLIS                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Status */
-#define BITM_CAN_GIS_AAIS                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Status */
-#define BITM_CAN_GIS_UIAIS                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Status */
-#define BITM_CAN_GIS_WUIS                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Status */
-#define BITM_CAN_GIS_BOIS                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Status */
-#define BITM_CAN_GIS_EPIS                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Status */
-#define BITM_CAN_GIS_EWRIS                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive  Interrupt Status */
-#define BITM_CAN_GIS_EWTIS                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIM                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIM_ADIM                    10                               /* Access Denied Interrupt Mask */
-#define BITP_CAN_GIM_UCEIM                    8                               /* Universal Counter Exceeded Interrupt Mask */
-#define BITP_CAN_GIM_RMLIM                    7                               /* Receive Message Lost Interrupt Mask */
-#define BITP_CAN_GIM_AAIM                     6                               /* Abort Acknowledge Interrupt Mask */
-#define BITP_CAN_GIM_UIAIM                    5                               /* Unimplemented Address Interrupt Mask */
-#define BITP_CAN_GIM_WUIM                     4                               /* Wake Up Interrupt Mask */
-#define BITP_CAN_GIM_BOIM                     3                               /* Bus Off Interrupt Mask */
-#define BITP_CAN_GIM_EPIM                     2                               /* Error Passive Interrupt Mask */
-#define BITP_CAN_GIM_EWRIM                    1                               /* Error Warning Receive Interrupt Mask */
-#define BITP_CAN_GIM_EWTIM                    0                               /* Error Warning Transmit Interrupt Mask */
-#define BITM_CAN_GIM_ADIM                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Mask */
-#define BITM_CAN_GIM_UCEIM                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Mask */
-#define BITM_CAN_GIM_RMLIM                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Mask */
-#define BITM_CAN_GIM_AAIM                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Mask */
-#define BITM_CAN_GIM_UIAIM                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Mask */
-#define BITM_CAN_GIM_WUIM                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Mask */
-#define BITM_CAN_GIM_BOIM                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Mask */
-#define BITM_CAN_GIM_EPIM                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Mask */
-#define BITM_CAN_GIM_EWRIM                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Mask */
-#define BITM_CAN_GIM_EWTIM                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIF                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIF_ADIF                    10                               /* Access Denied Interrupt Flag */
-#define BITP_CAN_GIF_UCEIF                    8                               /* Universal Counter Exceeded Interrupt Flag */
-#define BITP_CAN_GIF_RMLIF                    7                               /* Receive Message Lost Interrupt Flag */
-#define BITP_CAN_GIF_AAIF                     6                               /* Abort Acknowledge Interrupt Flag */
-#define BITP_CAN_GIF_UIAIF                    5                               /* Unimplemented Address Interrupt Flag */
-#define BITP_CAN_GIF_WUIF                     4                               /* Wake Up Interrupt Flag */
-#define BITP_CAN_GIF_BOIF                     3                               /* Bus Off Interrupt Flag */
-#define BITP_CAN_GIF_EPIF                     2                               /* Error Passive Interrupt Flag */
-#define BITP_CAN_GIF_EWRIF                    1                               /* Error Warning Receive Interrupt Flag */
-#define BITP_CAN_GIF_EWTIF                    0                               /* Error Warning Transmit Interrupt Flag */
-#define BITM_CAN_GIF_ADIF                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Flag */
-#define BITM_CAN_GIF_UCEIF                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Flag */
-#define BITM_CAN_GIF_RMLIF                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Flag */
-#define BITM_CAN_GIF_AAIF                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Flag */
-#define BITM_CAN_GIF_UIAIF                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Flag */
-#define BITM_CAN_GIF_WUIF                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Flag */
-#define BITM_CAN_GIF_BOIF                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Flag */
-#define BITM_CAN_GIF_EPIF                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Flag */
-#define BITM_CAN_GIF_EWRIF                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Flag */
-#define BITM_CAN_GIF_EWTIF                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CTL_CCR                      7                               /* CAN Configuration Mode Request */
-#define BITP_CAN_CTL_CSR                      6                               /* CAN Suspend Mode Request */
-#define BITP_CAN_CTL_SMR                      5                               /* Sleep Mode Request */
-#define BITP_CAN_CTL_WBA                      4                               /* Wake Up on CAN Bus Activity */
-#define BITP_CAN_CTL_ABO                      2                               /* Auto Bus On */
-#define BITP_CAN_CTL_DNM                      1                               /* Device Net Mode */
-#define BITP_CAN_CTL_SRS                      0                               /* Software Reset */
-#define BITM_CAN_CTL_CCR                     (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Request */
-#define BITM_CAN_CTL_CSR                     (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Request */
-#define BITM_CAN_CTL_SMR                     (_ADI_MSK(0x00000020,uint16_t))  /* Sleep Mode Request */
-#define BITM_CAN_CTL_WBA                     (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up on CAN Bus Activity */
-#define BITM_CAN_CTL_ABO                     (_ADI_MSK(0x00000004,uint16_t))  /* Auto Bus On */
-#define BITM_CAN_CTL_DNM                     (_ADI_MSK(0x00000002,uint16_t))  /* Device Net Mode */
-#define BITM_CAN_CTL_SRS                     (_ADI_MSK(0x00000001,uint16_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_INT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_INT_CANRX                    7                               /* Serial Input From Transceiver */
-#define BITP_CAN_INT_CANTX                    6                               /* Serial Input To Transceiver */
-#define BITP_CAN_INT_SMACK                    3                               /* Sleep Mode Acknowledge */
-#define BITP_CAN_INT_GIRQ                     2                               /* Global CAN Interrupt Output */
-#define BITP_CAN_INT_MBTIRQ                   1                               /* Mailbox Transmit Interrupt Output */
-#define BITP_CAN_INT_MBRIRQ                   0                               /* Mailbox Receive Interrupt Output */
-#define BITM_CAN_INT_CANRX                   (_ADI_MSK(0x00000080,uint16_t))  /* Serial Input From Transceiver */
-#define BITM_CAN_INT_CANTX                   (_ADI_MSK(0x00000040,uint16_t))  /* Serial Input To Transceiver */
-#define BITM_CAN_INT_SMACK                   (_ADI_MSK(0x00000008,uint16_t))  /* Sleep Mode Acknowledge */
-#define BITM_CAN_INT_GIRQ                    (_ADI_MSK(0x00000004,uint16_t))  /* Global CAN Interrupt Output */
-#define BITM_CAN_INT_MBTIRQ                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox Transmit Interrupt Output */
-#define BITM_CAN_INT_MBRIRQ                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox Receive Interrupt Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTD_TDR                     7                               /* Temporary Disable Request */
-#define BITP_CAN_MBTD_TDA                     6                               /* Temporary Disable Acknowledge */
-#define BITP_CAN_MBTD_TDPTR                   0                               /* Temporary Disable Pointer */
-#define BITM_CAN_MBTD_TDR                    (_ADI_MSK(0x00000080,uint16_t))  /* Temporary Disable Request */
-#define BITM_CAN_MBTD_TDA                    (_ADI_MSK(0x00000040,uint16_t))  /* Temporary Disable Acknowledge */
-#define BITM_CAN_MBTD_TDPTR                  (_ADI_MSK(0x0000001F,uint16_t))  /* Temporary Disable Pointer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_EWR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_EWR_EWLTEC                   8                               /* Transmit Error Warning Limit */
-#define BITP_CAN_EWR_EWLREC                   0                               /* Receive Error Warning Limit */
-#define BITM_CAN_EWR_EWLTEC                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Warning Limit */
-#define BITM_CAN_EWR_EWLREC                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Warning Limit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_ESR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_ESR_FER                      7                               /* Form Error */
-#define BITP_CAN_ESR_BEF                      6                               /* Bit Error Flag */
-#define BITP_CAN_ESR_SAO                      5                               /* Stuck at Dominant */
-#define BITP_CAN_ESR_CRCE                     4                               /* CRC Error */
-#define BITP_CAN_ESR_SER                      3                               /* Stuff Bit Error */
-#define BITP_CAN_ESR_ACKE                     2                               /* Acknowledge Error */
-#define BITM_CAN_ESR_FER                     (_ADI_MSK(0x00000080,uint16_t))  /* Form Error */
-#define BITM_CAN_ESR_BEF                     (_ADI_MSK(0x00000040,uint16_t))  /* Bit Error Flag */
-#define BITM_CAN_ESR_SAO                     (_ADI_MSK(0x00000020,uint16_t))  /* Stuck at Dominant */
-#define BITM_CAN_ESR_CRCE                    (_ADI_MSK(0x00000010,uint16_t))  /* CRC Error */
-#define BITM_CAN_ESR_SER                     (_ADI_MSK(0x00000008,uint16_t))  /* Stuff Bit Error */
-#define BITM_CAN_ESR_ACKE                    (_ADI_MSK(0x00000004,uint16_t))  /* Acknowledge Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_UCCNF                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_UCCNF_UCE                    7                               /* Universal Counter Enable */
-#define BITP_CAN_UCCNF_UCCT                   6                               /* Universal Counter CAN Trigger */
-#define BITP_CAN_UCCNF_UCRC                   5                               /* Universal Counter Reload/Clear */
-#define BITP_CAN_UCCNF_UCCNF                  0                               /* Universal Counter Configuration */
-#define BITM_CAN_UCCNF_UCE                   (_ADI_MSK(0x00000080,uint16_t))  /* Universal Counter Enable */
-#define BITM_CAN_UCCNF_UCCT                  (_ADI_MSK(0x00000040,uint16_t))  /* Universal Counter CAN Trigger */
-#define BITM_CAN_UCCNF_UCRC                  (_ADI_MSK(0x00000020,uint16_t))  /* Universal Counter Reload/Clear */
-#define BITM_CAN_UCCNF_UCCNF                 (_ADI_MSK(0x0000000F,uint16_t))  /* Universal Counter Configuration */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AMnH                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AMH_FDF                     15                               /* Filter on Delay Field */
-#define BITP_CAN_AMH_FMD                     14                               /* Full Mask Data */
-#define BITP_CAN_AMH_AMIDE                   13                               /* Acceptance Mask Identifier Extension */
-#define BITP_CAN_AMH_BASEID                   2                               /* Base Identifier */
-#define BITP_CAN_AMH_EXTID                    0                               /* Extended Identifier */
-#define BITM_CAN_AMH_FDF                     (_ADI_MSK(0x00008000,uint16_t))  /* Filter on Delay Field */
-#define BITM_CAN_AMH_FMD                     (_ADI_MSK(0x00004000,uint16_t))  /* Full Mask Data */
-#define BITM_CAN_AMH_AMIDE                   (_ADI_MSK(0x00002000,uint16_t))  /* Acceptance Mask Identifier Extension */
-#define BITM_CAN_AMH_BASEID                  (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_AMH_EXTID                   (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA0_DFB6                8                               /* Data Field Byte 6 */
-#define BITP_CAN_MB_DATA0_DFB7                0                               /* Data Field Byte 7 */
-#define BITM_CAN_MB_DATA0_DFB6               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 6 */
-#define BITM_CAN_MB_DATA0_DFB7               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 7 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA1_DFB4                8                               /* Data Field Byte 4 */
-#define BITP_CAN_MB_DATA1_DFB5                0                               /* Data Field Byte 5 */
-#define BITM_CAN_MB_DATA1_DFB4               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 4 */
-#define BITM_CAN_MB_DATA1_DFB5               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 5 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA2                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA2_DFB2                8                               /* Data Field Byte 2 */
-#define BITP_CAN_MB_DATA2_DFB3                0                               /* Data Field Byte 3 */
-#define BITM_CAN_MB_DATA2_DFB2               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 2 */
-#define BITM_CAN_MB_DATA2_DFB3               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 3 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA3                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA3_DFB0                8                               /* Data Field Byte 0 */
-#define BITP_CAN_MB_DATA3_DFB1                0                               /* Data Field Byte 1 */
-#define BITM_CAN_MB_DATA3_DFB0               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 0 */
-#define BITM_CAN_MB_DATA3_DFB1               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_LENGTH                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_LENGTH_DLC                0                               /* Data Length Code */
-#define BITM_CAN_MB_LENGTH_DLC               (_ADI_MSK(0x0000000F,uint16_t))  /* Data Length Code */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_ID1                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_ID1_AME                  15                               /* Acceptance Mask Enable */
-#define BITP_CAN_MB_ID1_RTR                  14                               /* Remote Transmission Request */
-#define BITP_CAN_MB_ID1_IDE                  13                               /* Identifier Extension */
-#define BITP_CAN_MB_ID1_BASEID                2                               /* Base Identifier */
-#define BITP_CAN_MB_ID1_EXTID                 0                               /* Extended Identifier */
-#define BITM_CAN_MB_ID1_AME                  (_ADI_MSK(0x00008000,uint16_t))  /* Acceptance Mask Enable */
-#define BITM_CAN_MB_ID1_RTR                  (_ADI_MSK(0x00004000,uint16_t))  /* Remote Transmission Request */
-#define BITM_CAN_MB_ID1_IDE                  (_ADI_MSK(0x00002000,uint16_t))  /* Identifier Extension */
-#define BITM_CAN_MB_ID1_BASEID               (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_MB_ID1_EXTID                (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ==================================================
-        Link Port Registers
-   ================================================== */
-
-/* =========================
-        LP0
-   ========================= */
-#define REG_LP0_CTL                     0xFFC01000         /* LP0 Control Register */
-#define REG_LP0_STAT                    0xFFC01004         /* LP0 Status Register */
-#define REG_LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
-#define REG_LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
-#define REG_LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
-#define REG_LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
-#define REG_LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP1
-   ========================= */
-#define REG_LP1_CTL                     0xFFC01100         /* LP1 Control Register */
-#define REG_LP1_STAT                    0xFFC01104         /* LP1 Status Register */
-#define REG_LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
-#define REG_LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
-#define REG_LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
-#define REG_LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
-#define REG_LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP2
-   ========================= */
-#define REG_LP2_CTL                     0xFFC01200         /* LP2 Control Register */
-#define REG_LP2_STAT                    0xFFC01204         /* LP2 Status Register */
-#define REG_LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
-#define REG_LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
-#define REG_LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
-#define REG_LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
-#define REG_LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP3
-   ========================= */
-#define REG_LP3_CTL                     0xFFC01300         /* LP3 Control Register */
-#define REG_LP3_STAT                    0xFFC01304         /* LP3 Status Register */
-#define REG_LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
-#define REG_LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
-#define REG_LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
-#define REG_LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
-#define REG_LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_CTL                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_CTL_ITMSK                    11                               /* Receive FIFO Overflow Interrupt Mask */
-#define BITP_LP_CTL_RRQMSK                    9                               /* Receive Request Interrupt Mask */
-#define BITP_LP_CTL_TRQMSK                    8                               /* Transmit Request Interrupt Mask */
-#define BITP_LP_CTL_TRAN                      3                               /* Transfer Direction */
-#define BITP_LP_CTL_EN                        0                               /* Enable */
-
-#define BITM_LP_CTL_ITMSK                    (_ADI_MSK(0x00000800,uint32_t))  /* Receive FIFO Overflow Interrupt Mask */
-#define ENUM_LP_CTL_RX_OVF_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* ITMSK: Mask */
-#define ENUM_LP_CTL_RX_OVF_EN                (_ADI_MSK(0x00000800,uint32_t))  /* ITMSK: Unmask */
-
-#define BITM_LP_CTL_RRQMSK                   (_ADI_MSK(0x00000200,uint32_t))  /* Receive Request Interrupt Mask */
-#define ENUM_LP_CTL_RRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* RRQMSK: Mask */
-#define ENUM_LP_CTL_RRQ_EN                   (_ADI_MSK(0x00000200,uint32_t))  /* RRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRQMSK                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Request Interrupt Mask */
-#define ENUM_LP_CTL_TRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* TRQMSK: Mask */
-#define ENUM_LP_CTL_TRQ_EN                   (_ADI_MSK(0x00000100,uint32_t))  /* TRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRAN                     (_ADI_MSK(0x00000008,uint32_t))  /* Transfer Direction */
-#define ENUM_LP_CTL_RX                       (_ADI_MSK(0x00000000,uint32_t))  /* TRAN: Receive */
-#define ENUM_LP_CTL_TX                       (_ADI_MSK(0x00000008,uint32_t))  /* TRAN: Transmit */
-
-#define BITM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_LP_CTL_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable   linkport */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_STAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_STAT_LPBS                     8                               /* Bus Status */
-#define BITP_LP_STAT_LERR                     7                               /* Buffer Pack Error Status */
-#define BITP_LP_STAT_FFST                     4                               /* FIFO Status */
-#define BITP_LP_STAT_LPIT                     3                               /* Receive FIFO Overflow Interrupt */
-#define BITP_LP_STAT_LRRQ                     1                               /* Receive Request */
-#define BITP_LP_STAT_LTRQ                     0                               /* Transmit Request */
-
-#define BITM_LP_STAT_LPBS                    (_ADI_MSK(0x00000100,uint32_t))  /* Bus Status */
-#define ENUM_LP_STAT_IDLE                    (_ADI_MSK(0x00000000,uint32_t))  /* LPBS: Bus is Idle */
-#define ENUM_LP_STAT_BUSY                    (_ADI_MSK(0x00000100,uint32_t))  /* LPBS: Bus Busy */
-
-#define BITM_LP_STAT_LERR                    (_ADI_MSK(0x00000080,uint32_t))  /* Buffer Pack Error Status */
-#define ENUM_LP_STAT_PACK_DONE               (_ADI_MSK(0x00000000,uint32_t))  /* LERR: Packing Complete */
-#define ENUM_LP_STAT_PACK_PROG               (_ADI_MSK(0x00000080,uint32_t))  /* LERR: Packing Incomplete */
-
-#define BITM_LP_STAT_FFST                    (_ADI_MSK(0x00000070,uint32_t))  /* FIFO Status */
-#define ENUM_LP_STAT_RX0_TX0                 (_ADI_MSK(0x00000000,uint32_t))  /* FFST: TX - Empty; RX -Empty */
-#define ENUM_LP_STAT_RX1_TXR                 (_ADI_MSK(0x00000010,uint32_t))  /* FFST: TX - reserved ; RX - One Word */
-#define ENUM_LP_STAT_RX2_TXR                 (_ADI_MSK(0x00000020,uint32_t))  /* FFST: TX - reserved; RX - Two Word */
-#define ENUM_LP_STAT_RX3_TXR                 (_ADI_MSK(0x00000030,uint32_t))  /* FFST: TX - reserved; RX - Three Word */
-#define ENUM_LP_STAT_RX4_TX1                 (_ADI_MSK(0x00000040,uint32_t))  /* FFST: TX - One Word; RX - Four word */
-#define ENUM_LP_STAT_RXR1_TXR1               (_ADI_MSK(0x00000050,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define ENUM_LP_STAT_RXR2_TXR2               (_ADI_MSK(0x00000060,uint32_t))  /* FFST: TX - FIFO Full; RX - Reserved */
-#define ENUM_LP_STAT_RXR3_TXR3               (_ADI_MSK(0x00000070,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define BITM_LP_STAT_LPIT                    (_ADI_MSK(0x00000008,uint32_t))  /* Receive FIFO Overflow Interrupt */
-#define BITM_LP_STAT_LRRQ                    (_ADI_MSK(0x00000002,uint32_t))  /* Receive Request */
-#define BITM_LP_STAT_LTRQ                    (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_DIV                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_DIV_VALUE                     0                               /* Divisor Value */
-#define BITM_LP_DIV_VALUE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Divisor Value */
-
-/* ==================================================
-        General Purpose Timer Block Registers
-   ================================================== */
-
-/* =========================
-        TIMER0
-   ========================= */
-#define REG_TIMER0_REVID                0xFFC01400         /* TIMER0 Revision ID Register */
-#define REG_TIMER0_RUN                  0xFFC01404         /* TIMER0 Run Register */
-#define REG_TIMER0_RUN_SET              0xFFC01408         /* TIMER0 Run Set Register */
-#define REG_TIMER0_RUN_CLR              0xFFC0140C         /* TIMER0 Run Clear Register */
-#define REG_TIMER0_STOP_CFG             0xFFC01410         /* TIMER0 Stop Configuration Register */
-#define REG_TIMER0_STOP_CFG_SET         0xFFC01414         /* TIMER0 Stop Configuration Set Register */
-#define REG_TIMER0_STOP_CFG_CLR         0xFFC01418         /* TIMER0 Stop Configuration Clear Register */
-#define REG_TIMER0_DATA_IMSK            0xFFC0141C         /* TIMER0 Data Interrupt Mask Register */
-#define REG_TIMER0_STAT_IMSK            0xFFC01420         /* TIMER0 Status Interrupt Mask Register */
-#define REG_TIMER0_TRG_MSK              0xFFC01424         /* TIMER0 Trigger Master Mask Register */
-#define REG_TIMER0_TRG_IE               0xFFC01428         /* TIMER0 Trigger Slave Enable Register */
-#define REG_TIMER0_DATA_ILAT            0xFFC0142C         /* TIMER0 Data Interrupt Latch Register */
-#define REG_TIMER0_STAT_ILAT            0xFFC01430         /* TIMER0 Status Interrupt Latch Register */
-#define REG_TIMER0_ERR_TYPE             0xFFC01434         /* TIMER0 Error Type Status Register */
-#define REG_TIMER0_BCAST_PER            0xFFC01438         /* TIMER0 Broadcast Period Register */
-#define REG_TIMER0_BCAST_WID            0xFFC0143C         /* TIMER0 Broadcast Width Register */
-#define REG_TIMER0_BCAST_DLY            0xFFC01440         /* TIMER0 Broadcast Delay Register */
-#define REG_TIMER0_TMR0_CFG             0xFFC01460         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR1_CFG             0xFFC01480         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR2_CFG             0xFFC014A0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR3_CFG             0xFFC014C0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR4_CFG             0xFFC014E0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR5_CFG             0xFFC01500         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR6_CFG             0xFFC01520         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR7_CFG             0xFFC01540         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR0_CNT             0xFFC01464         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR1_CNT             0xFFC01484         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR2_CNT             0xFFC014A4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR3_CNT             0xFFC014C4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR4_CNT             0xFFC014E4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR5_CNT             0xFFC01504         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR6_CNT             0xFFC01524         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR7_CNT             0xFFC01544         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR0_PER             0xFFC01468         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR1_PER             0xFFC01488         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR2_PER             0xFFC014A8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR3_PER             0xFFC014C8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR4_PER             0xFFC014E8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR5_PER             0xFFC01508         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR6_PER             0xFFC01528         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR7_PER             0xFFC01548         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR0_WID             0xFFC0146C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR1_WID             0xFFC0148C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR2_WID             0xFFC014AC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR3_WID             0xFFC014CC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR4_WID             0xFFC014EC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR5_WID             0xFFC0150C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR6_WID             0xFFC0152C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR7_WID             0xFFC0154C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR0_DLY             0xFFC01470         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR1_DLY             0xFFC01490         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR2_DLY             0xFFC014B0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR3_DLY             0xFFC014D0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR4_DLY             0xFFC014F0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR5_DLY             0xFFC01510         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR6_DLY             0xFFC01530         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR7_DLY             0xFFC01550         /* TIMER0 Timer n Delay Register */
-
-/* =========================
-        TIMER
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_REVID                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_REVID_MAJOR                4                               /* Major Revision ID */
-#define BITP_TIMER_REVID_REV                  0                               /* Incremental Revision ID */
-#define BITM_TIMER_REVID_MAJOR               (_ADI_MSK(0x000000F0,uint16_t))  /* Major Revision ID */
-#define BITM_TIMER_REVID_REV                 (_ADI_MSK(0x0000000F,uint16_t))  /* Incremental Revision ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_TMR00                  0                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR01                  1                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR02                  2                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR03                  3                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR04                  4                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR05                  5                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR06                  6                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR07                  7                               /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR00                 (_ADI_MSK(0x00000001,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR01                 (_ADI_MSK(0x00000002,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR02                 (_ADI_MSK(0x00000004,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR03                 (_ADI_MSK(0x00000008,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR04                 (_ADI_MSK(0x00000010,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR05                 (_ADI_MSK(0x00000020,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR06                 (_ADI_MSK(0x00000040,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR07                 (_ADI_MSK(0x00000080,uint16_t))  /* Start/Stop Timer n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_SET_TMR00              0                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR01              1                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR02              2                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR03              3                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR04              4                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR05              5                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR06              6                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR07              7                               /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_CLR_TMR00              0                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR01              1                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR02              2                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR03              3                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR04              4                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR05              5                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR06              6                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR07              7                               /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_TMR00             0                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR01             1                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR02             2                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR03             3                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR04             4                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR05             5                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR06             6                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR07             7                               /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR00            (_ADI_MSK(0x00000001,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR01            (_ADI_MSK(0x00000002,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR02            (_ADI_MSK(0x00000004,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR03            (_ADI_MSK(0x00000008,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR04            (_ADI_MSK(0x00000010,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR05            (_ADI_MSK(0x00000020,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR06            (_ADI_MSK(0x00000040,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR07            (_ADI_MSK(0x00000080,uint16_t))  /* Stop Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_SET                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_SET_TMR00         0                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR01         1                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR02         2                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR03         3                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR04         4                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR05         5                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR06         6                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR07         7                               /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_CLR                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_CLR_TMR00         0                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR01         1                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR02         2                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR03         3                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR04         4                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR05         5                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR06         6                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR07         7                               /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_IMSK_TMR00            0                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR01            1                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR02            2                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR03            3                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR04            4                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR05            5                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR06            6                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR07            7                               /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_IMSK_TMR00            0                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR01            1                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR02            2                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR03            3                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR04            4                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR05            5                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR06            6                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR07            7                               /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_MSK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_MSK_TMR00              0                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR01              1                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR02              2                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR03              3                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR04              4                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR05              5                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR06              6                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR07              7                               /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Output Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_IE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_IE_TMR00               0                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR01               1                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR02               2                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR03               3                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR04               4                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR05               5                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR06               6                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR07               7                               /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR00              (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR01              (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR02              (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR03              (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR04              (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR05              (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR06              (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR07              (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_ILAT_TMR00            0                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR01            1                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR02            2                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR03            3                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR04            4                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR05            5                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR06            6                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR07            7                               /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_ILAT_TMR00            0                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR01            1                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR02            2                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR03            3                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR04            4                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR05            5                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR06            6                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR07            7                               /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_ERR_TYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_ERR_TYPE_TERR7            14                               /* Error type for Timer 7 */
-#define BITP_TIMER_ERR_TYPE_TERR6            12                               /* Error type for Timer 6 */
-#define BITP_TIMER_ERR_TYPE_TERR5            10                               /* Error type for Timer 5 */
-#define BITP_TIMER_ERR_TYPE_TERR4             8                               /* Error type for Timer 4 */
-#define BITP_TIMER_ERR_TYPE_TERR3             6                               /* Error type for Timer 3 */
-#define BITP_TIMER_ERR_TYPE_TERR2             4                               /* Error type for Timer 2 */
-#define BITP_TIMER_ERR_TYPE_TERR1             2                               /* Error type for Timer 1 */
-#define BITP_TIMER_ERR_TYPE_TERR0             0                               /* Error type for Timer 0 */
-
-#define BITM_TIMER_ERR_TYPE_TERR7            (_ADI_MSK(0x0000C000,uint32_t))  /* Error type for Timer 7 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR7          (_ADI_MSK(0x00000000,uint32_t))  /* TERR7: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF7          (_ADI_MSK(0x00004000,uint32_t))  /* TERR7: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG7          (_ADI_MSK(0x00008000,uint32_t))  /* TERR7: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG7        (_ADI_MSK(0x0000C000,uint32_t))  /* TERR7: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR6            (_ADI_MSK(0x00003000,uint32_t))  /* Error type for Timer 6 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR6          (_ADI_MSK(0x00000000,uint32_t))  /* TERR6: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF6          (_ADI_MSK(0x00001000,uint32_t))  /* TERR6: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG6          (_ADI_MSK(0x00002000,uint32_t))  /* TERR6: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG6        (_ADI_MSK(0x00003000,uint32_t))  /* TERR6: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR5            (_ADI_MSK(0x00000C00,uint32_t))  /* Error type for Timer 5 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR5          (_ADI_MSK(0x00000000,uint32_t))  /* TERR5: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF5          (_ADI_MSK(0x00000400,uint32_t))  /* TERR5: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG5          (_ADI_MSK(0x00000800,uint32_t))  /* TERR5: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG5        (_ADI_MSK(0x00000C00,uint32_t))  /* TERR5: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR4            (_ADI_MSK(0x00000300,uint32_t))  /* Error type for Timer 4 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR4          (_ADI_MSK(0x00000000,uint32_t))  /* TERR4: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF4          (_ADI_MSK(0x00000100,uint32_t))  /* TERR4: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG4          (_ADI_MSK(0x00000200,uint32_t))  /* TERR4: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG4        (_ADI_MSK(0x00000300,uint32_t))  /* TERR4: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR3            (_ADI_MSK(0x000000C0,uint32_t))  /* Error type for Timer 3 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR3          (_ADI_MSK(0x00000000,uint32_t))  /* TERR3: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF3          (_ADI_MSK(0x00000040,uint32_t))  /* TERR3: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG3          (_ADI_MSK(0x00000080,uint32_t))  /* TERR3: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG3        (_ADI_MSK(0x000000C0,uint32_t))  /* TERR3: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR2            (_ADI_MSK(0x00000030,uint32_t))  /* Error type for Timer 2 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR2          (_ADI_MSK(0x00000000,uint32_t))  /* TERR2: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF2          (_ADI_MSK(0x00000010,uint32_t))  /* TERR2: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG2          (_ADI_MSK(0x00000020,uint32_t))  /* TERR2: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG2        (_ADI_MSK(0x00000030,uint32_t))  /* TERR2: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR1            (_ADI_MSK(0x0000000C,uint32_t))  /* Error type for Timer 1 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR1          (_ADI_MSK(0x00000000,uint32_t))  /* TERR1: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF1          (_ADI_MSK(0x00000004,uint32_t))  /* TERR1: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG1          (_ADI_MSK(0x00000008,uint32_t))  /* TERR1: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG1        (_ADI_MSK(0x0000000C,uint32_t))  /* TERR1: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR0            (_ADI_MSK(0x00000003,uint32_t))  /* Error type for Timer 0 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR0          (_ADI_MSK(0x00000000,uint32_t))  /* TERR0: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF0          (_ADI_MSK(0x00000001,uint32_t))  /* TERR0: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG0          (_ADI_MSK(0x00000002,uint32_t))  /* TERR0: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG0        (_ADI_MSK(0x00000003,uint32_t))  /* TERR0: WID or DLY Register Programming Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TMR_CFG                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TMR_CFG_EMURUN            15                               /* Run Timer (Counter) During Emulation */
-#define BITP_TIMER_TMR_CFG_BPEREN            14                               /* Broadcast Period Enable */
-#define BITP_TIMER_TMR_CFG_BWIDEN            13                               /* Broadcast Width Enable */
-#define BITP_TIMER_TMR_CFG_BDLYEN            12                               /* Broadcast Delay Enable */
-#define BITP_TIMER_TMR_CFG_OUTDIS            11                               /* Output Disable */
-#define BITP_TIMER_TMR_CFG_TINSEL            10                               /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define BITP_TIMER_TMR_CFG_CLKSEL             8                               /* Clock Select */
-#define BITP_TIMER_TMR_CFG_PULSEHI            7                               /* Polarity Response Select */
-#define BITP_TIMER_TMR_CFG_SLAVETRIG          6                               /* Slave Trigger Response */
-#define BITP_TIMER_TMR_CFG_IRQMODE            4                               /* Interrupt Modes */
-#define BITP_TIMER_TMR_CFG_TMODE              0                               /* Timer Mode Select */
-
-#define BITM_TIMER_TMR_CFG_EMURUN            (_ADI_MSK(0x00008000,uint16_t))  /* Run Timer (Counter) During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_NOCNT         (_ADI_MSK(0x00000000,uint16_t))  /* EMURUN: Stop Timer During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_CNT           (_ADI_MSK(0x00008000,uint16_t))  /* EMURUN: Run Timer During Emulation */
-
-#define BITM_TIMER_TMR_CFG_BPEREN            (_ADI_MSK(0x00004000,uint16_t))  /* Broadcast Period Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BPEREN: Disable Broadcast to PER Register */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_EN       (_ADI_MSK(0x00004000,uint16_t))  /* BPEREN: Enable Broadcast to PER Register */
-
-#define BITM_TIMER_TMR_CFG_BWIDEN            (_ADI_MSK(0x00002000,uint16_t))  /* Broadcast Width Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BWIDEN: Disable Broadcast to WID Register */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_EN       (_ADI_MSK(0x00002000,uint16_t))  /* BWIDEN: Enable Broadcast to WID Register */
-
-#define BITM_TIMER_TMR_CFG_BDLYEN            (_ADI_MSK(0x00001000,uint16_t))  /* Broadcast Delay Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BDLYEN: Disable Broadcast to DLY Register */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_EN       (_ADI_MSK(0x00001000,uint16_t))  /* BDLYEN: Enable Broadcast to DLY Register */
-
-#define BITM_TIMER_TMR_CFG_OUTDIS            (_ADI_MSK(0x00000800,uint16_t))  /* Output Disable */
-#define ENUM_TIMER_TMR_CFG_PADOUT_EN         (_ADI_MSK(0x00000000,uint16_t))  /* OUTDIS: Enable TMR pin output buffer */
-#define ENUM_TIMER_TMR_CFG_PADOUT_DIS        (_ADI_MSK(0x00000800,uint16_t))  /* OUTDIS: Disable TMR pin output buffer */
-
-#define BITM_TIMER_TMR_CFG_TINSEL            (_ADI_MSK(0x00000400,uint16_t))  /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define ENUM_TIMER_TMR_CFG_TINSEL_TMR        (_ADI_MSK(0x00000000,uint16_t))  /* TINSEL: Use TMR pin input */
-#define ENUM_TIMER_TMR_CFG_TINSEL_AUX        (_ADI_MSK(0x00000400,uint16_t))  /* TINSEL: Use TMR Alternate Capture Input */
-
-#define BITM_TIMER_TMR_CFG_CLKSEL            (_ADI_MSK(0x00000300,uint16_t))  /* Clock Select */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_SCLK       (_ADI_MSK(0x00000000,uint16_t))  /* CLKSEL: Use SCLK */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT0       (_ADI_MSK(0x00000100,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK0 as the TMR clock */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT1       (_ADI_MSK(0x00000300,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK1 as the TMR clock */
-
-#define BITM_TIMER_TMR_CFG_PULSEHI           (_ADI_MSK(0x00000080,uint16_t))  /* Polarity Response Select */
-#define ENUM_TIMER_TMR_CFG_NEG_EDGE          (_ADI_MSK(0x00000000,uint16_t))  /* PULSEHI: Negative Response/Pulse */
-#define ENUM_TIMER_TMR_CFG_POS_EDGE          (_ADI_MSK(0x00000080,uint16_t))  /* PULSEHI: Positive  Response/Pulse */
-
-#define BITM_TIMER_TMR_CFG_SLAVETRIG         (_ADI_MSK(0x00000040,uint16_t))  /* Slave Trigger Response */
-#define ENUM_TIMER_TMR_CFG_TRIGSTOP          (_ADI_MSK(0x00000000,uint16_t))  /* SLAVETRIG: Pulse stops timer if it is running */
-#define ENUM_TIMER_TMR_CFG_TRIGSTART         (_ADI_MSK(0x00000040,uint16_t))  /* SLAVETRIG: Pulse starts timer if it is stopped */
-
-#define BITM_TIMER_TMR_CFG_IRQMODE           (_ADI_MSK(0x00000030,uint16_t))  /* Interrupt Modes */
-#define ENUM_TIMER_TMR_CFG_IRQMODE0          (_ADI_MSK(0x00000000,uint16_t))  /* IRQMODE: Active Edge Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE1          (_ADI_MSK(0x00000010,uint16_t))  /* IRQMODE: Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE2          (_ADI_MSK(0x00000020,uint16_t))  /* IRQMODE: Width Plus Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE3          (_ADI_MSK(0x00000030,uint16_t))  /* IRQMODE: Period Expired Mode */
-
-#define BITM_TIMER_TMR_CFG_TMODE             (_ADI_MSK(0x0000000F,uint16_t))  /* Timer Mode Select */
-#define ENUM_TIMER_TMR_CFG_IDLE_MODE         (_ADI_MSK(0x00000000,uint16_t))  /* TMODE: Idle Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP0_MODE      (_ADI_MSK(0x0000000A,uint16_t))  /* TMODE: Width Capture Asserted Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP1_MODE      (_ADI_MSK(0x0000000B,uint16_t))  /* TMODE: Width Capture Deasserted Mode */
-#define ENUM_TIMER_TMR_CFG_PWMCONT_MODE      (_ADI_MSK(0x0000000C,uint16_t))  /* TMODE: Continuous PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_PWMSING_MODE      (_ADI_MSK(0x0000000D,uint16_t))  /* TMODE: Single pulse PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_EXTCLK_MODE       (_ADI_MSK(0x0000000E,uint16_t))  /* TMODE: EXTCLK mode */
-#define ENUM_TIMER_TMR_CFG_PININT_MODE       (_ADI_MSK(0x0000000F,uint16_t))  /* TMODE: PININT (pin interrupt) mode */
-#define ENUM_TIMER_TMR_CFG_WDPER_MODE        (_ADI_MSK(0x00000008,uint16_t))  /* TMODE: Period Watchdog Mode */
-#define ENUM_TIMER_TMR_CFG_WDWID_MODE        (_ADI_MSK(0x00000009,uint16_t))  /* TMODE: Width Watchdog Mode */
-
-/* ==================================================
-        Cyclic Redundancy Check Unit Registers
-   ================================================== */
-
-/* =========================
-        CRC0
-   ========================= */
-#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
-#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 Data Compare Register */
-#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 Data FIFO Register */
-#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 Data Count Capture Register */
-#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 CRC Final Result Register */
-#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 CRC Current Result Register */
-#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
-
-/* =========================
-        CRC1
-   ========================= */
-#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
-#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 Data Compare Register */
-#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 Data FIFO Register */
-#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 Data Count Capture Register */
-#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 CRC Final Result Register */
-#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 CRC Current Result Register */
-#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
-
-/* =========================
-        CRC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_CTL_CMPMIRR                 22                               /* COMPARE Register Mirroring */
-#define BITP_CRC_CTL_POLYMIRR                21                               /* Polynomial Register Mirroring */
-#define BITP_CRC_CTL_RSLTMIRR                20                               /* Result Register Mirroring */
-#define BITP_CRC_CTL_FDSEL                   19                               /* FIFO Data Select */
-#define BITP_CRC_CTL_W16SWP                  18                               /* Word16 Swapping */
-#define BITP_CRC_CTL_BYTMIRR                 17                               /* Byte Mirroring */
-#define BITP_CRC_CTL_BITMIRR                 16                               /* Bit Mirroring */
-#define BITP_CRC_CTL_IRRSTALL                13                               /* Intermediate Result Ready Stall */
-#define BITP_CRC_CTL_OBRSTALL                12                               /* Output Buffer Ready Stall */
-#define BITP_CRC_CTL_AUTOCLRF                 9                               /* Auto Clear to One */
-#define BITP_CRC_CTL_AUTOCLRZ                 8                               /* Auto Clear to Zero */
-#define BITP_CRC_CTL_OPMODE                   4                               /* Operation Mode */
-#define BITP_CRC_CTL_BLKEN                    0                               /* Block Enable */
-#define BITM_CRC_CTL_CMPMIRR                 (_ADI_MSK(0x00400000,uint32_t))  /* COMPARE Register Mirroring */
-#define BITM_CRC_CTL_POLYMIRR                (_ADI_MSK(0x00200000,uint32_t))  /* Polynomial Register Mirroring */
-#define BITM_CRC_CTL_RSLTMIRR                (_ADI_MSK(0x00100000,uint32_t))  /* Result Register Mirroring */
-#define BITM_CRC_CTL_FDSEL                   (_ADI_MSK(0x00080000,uint32_t))  /* FIFO Data Select */
-#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK(0x00040000,uint32_t))  /* Word16 Swapping */
-#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK(0x00020000,uint32_t))  /* Byte Mirroring */
-#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK(0x00010000,uint32_t))  /* Bit Mirroring */
-#define BITM_CRC_CTL_IRRSTALL                (_ADI_MSK(0x00002000,uint32_t))  /* Intermediate Result Ready Stall */
-#define BITM_CRC_CTL_OBRSTALL                (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Ready Stall */
-#define BITM_CRC_CTL_AUTOCLRF                (_ADI_MSK(0x00000200,uint32_t))  /* Auto Clear to One */
-#define BITM_CRC_CTL_AUTOCLRZ                (_ADI_MSK(0x00000100,uint32_t))  /* Auto Clear to Zero */
-#define BITM_CRC_CTL_OPMODE                  (_ADI_MSK(0x000000F0,uint32_t))  /* Operation Mode */
-#define BITM_CRC_CTL_BLKEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Block Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_DCNTEXP                 4                               /* Data Count Expired (Status) Interrupt Enable */
-#define BITP_CRC_INEN_CMPERR                  1                               /* Compare Error Interrupt Enable */
-
-#define BITM_CRC_INEN_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable */
-#define ENUM_CRC_INEN_DCNTEXP_MSK            (_ADI_MSK(0x00000000,uint32_t))  /* DCNTEXP: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_DCNTEXP_UMSK           (_ADI_MSK(0x00000010,uint32_t))  /* DCNTEXP: Enable (unmask) interrupt */
-
-#define BITM_CRC_INEN_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable */
-#define ENUM_CRC_INEN_CMPERR_MSK             (_ADI_MSK(0x00000000,uint32_t))  /* CMPERR: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_CMPERR_UMSK            (_ADI_MSK(0x00000002,uint32_t))  /* CMPERR: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_SET_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITP_CRC_INEN_SET_CMPERR              1                               /* Compare Error Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_CLR_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITP_CRC_INEN_CLR_CMPERR              1                               /* Compare Error Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_STAT_FSTAT                  20                               /* FIFO Status */
-#define BITP_CRC_STAT_LUTDONE                19                               /* Look Up Table Done */
-#define BITP_CRC_STAT_IRR                    18                               /* Intermediate Result Ready */
-#define BITP_CRC_STAT_OBR                    17                               /* Output Buffer Ready */
-#define BITP_CRC_STAT_IBR                    16                               /* Input Buffer Ready */
-#define BITP_CRC_STAT_DCNTEXP                 4                               /* Data Count Expired */
-#define BITP_CRC_STAT_CMPERR                  1                               /* Compare Error */
-#define BITM_CRC_STAT_FSTAT                  (_ADI_MSK(0x00700000,uint32_t))  /* FIFO Status */
-#define BITM_CRC_STAT_LUTDONE                (_ADI_MSK(0x00080000,uint32_t))  /* Look Up Table Done */
-#define BITM_CRC_STAT_IRR                    (_ADI_MSK(0x00040000,uint32_t))  /* Intermediate Result Ready */
-#define BITM_CRC_STAT_OBR                    (_ADI_MSK(0x00020000,uint32_t))  /* Output Buffer Ready */
-#define BITM_CRC_STAT_IBR                    (_ADI_MSK(0x00010000,uint32_t))  /* Input Buffer Ready */
-#define BITM_CRC_STAT_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired */
-#define BITM_CRC_STAT_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_REVID_MAJOR                  4                               /* Major Revision ID */
-#define BITP_CRC_REVID_REV                    0                               /* Incremental Revision ID */
-#define BITM_CRC_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Revision ID */
-#define BITM_CRC_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Revision ID */
-
-/* ==================================================
-        2-Wire Interface Registers
-   ================================================== */
-
-/* =========================
-        TWI0
-   ========================= */
-#define REG_TWI0_CLKDIV                 0xFFC01E00         /* TWI0 SCL Clock Divider Register */
-#define REG_TWI0_CTL                    0xFFC01E04         /* TWI0 Control Register */
-#define REG_TWI0_SLVCTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
-#define REG_TWI0_SLVSTAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
-#define REG_TWI0_SLVADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
-#define REG_TWI0_MSTRCTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
-#define REG_TWI0_MSTRSTAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
-#define REG_TWI0_MSTRADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
-#define REG_TWI0_ISTAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
-#define REG_TWI0_IMSK                   0xFFC01E24         /* TWI0 Interrupt Mask Register */
-#define REG_TWI0_FIFOCTL                0xFFC01E28         /* TWI0 FIFO Control Register */
-#define REG_TWI0_FIFOSTAT               0xFFC01E2C         /* TWI0 FIFO Status Register */
-#define REG_TWI0_TXDATA8                0xFFC01E80         /* TWI0 Tx Data Single-Byte Register */
-#define REG_TWI0_TXDATA16               0xFFC01E84         /* TWI0 Tx Data Double-Byte Register */
-#define REG_TWI0_RXDATA8                0xFFC01E88         /* TWI0 Rx Data Single-Byte Register */
-#define REG_TWI0_RXDATA16               0xFFC01E8C         /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI1
-   ========================= */
-#define REG_TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider Register */
-#define REG_TWI1_CTL                    0xFFC01F04         /* TWI1 Control Register */
-#define REG_TWI1_SLVCTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
-#define REG_TWI1_SLVSTAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
-#define REG_TWI1_SLVADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
-#define REG_TWI1_MSTRCTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
-#define REG_TWI1_MSTRSTAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
-#define REG_TWI1_MSTRADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
-#define REG_TWI1_ISTAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
-#define REG_TWI1_IMSK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
-#define REG_TWI1_FIFOCTL                0xFFC01F28         /* TWI1 FIFO Control Register */
-#define REG_TWI1_FIFOSTAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
-#define REG_TWI1_TXDATA8                0xFFC01F80         /* TWI1 Tx Data Single-Byte Register */
-#define REG_TWI1_TXDATA16               0xFFC01F84         /* TWI1 Tx Data Double-Byte Register */
-#define REG_TWI1_RXDATA8                0xFFC01F88         /* TWI1 Rx Data Single-Byte Register */
-#define REG_TWI1_RXDATA16               0xFFC01F8C         /* TWI1 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CLKDIV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CLKDIV_CLKHI                 8                               /* SCL Clock High Periods */
-#define BITP_TWI_CLKDIV_CLKLO                 0                               /* SCL Clock Low Periods */
-#define BITM_TWI_CLKDIV_CLKHI                (_ADI_MSK(0x0000FF00,uint16_t))  /* SCL Clock High Periods */
-#define BITM_TWI_CLKDIV_CLKLO                (_ADI_MSK(0x000000FF,uint16_t))  /* SCL Clock Low Periods */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CTL_SCCB                     9                               /* SCCB Compatibility */
-#define BITP_TWI_CTL_EN                       7                               /* Enable Module */
-#define BITP_TWI_CTL_PRESCALE                 0                               /* SCLK Prescale Value */
-
-#define BITM_TWI_CTL_SCCB                    (_ADI_MSK(0x00000200,uint16_t))  /* SCCB Compatibility */
-#define ENUM_TWI_CTL_SCCB_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* SCCB: Disable SCCB compatibility */
-#define ENUM_TWI_CTL_SCCB_EN                 (_ADI_MSK(0x00000200,uint16_t))  /* SCCB: Enable SCCB compatibility */
-
-#define BITM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* Enable Module */
-#define ENUM_TWI_CTL_DIS                     (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* EN: Enable */
-#define BITM_TWI_CTL_PRESCALE                (_ADI_MSK(0x0000007F,uint16_t))  /* SCLK Prescale Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVCTL_GEN                   4                               /* General Call Enable */
-#define BITP_TWI_SLVCTL_NAK                   3                               /* Not Acknowledge */
-#define BITP_TWI_SLVCTL_TDVAL                 2                               /* Transmit Data Valid for Slave */
-#define BITP_TWI_SLVCTL_EN                    0                               /* Enable Slave Mode */
-
-#define BITM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* General Call Enable */
-#define ENUM_TWI_SLVCTL_GDIS                 (_ADI_MSK(0x00000000,uint16_t))  /* GEN: Disable General Call Matching */
-#define ENUM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* GEN: Enable General Call Matching */
-
-#define BITM_TWI_SLVCTL_NAK                  (_ADI_MSK(0x00000008,uint16_t))  /* Not Acknowledge */
-#define ENUM_TWI_SLVCTL_ACKGEN               (_ADI_MSK(0x00000000,uint16_t))  /* NAK: Generate ACK */
-#define ENUM_TWI_SLVCTL_NAKGEN               (_ADI_MSK(0x00000008,uint16_t))  /* NAK: Generate NAK */
-
-#define BITM_TWI_SLVCTL_TDVAL                (_ADI_MSK(0x00000004,uint16_t))  /* Transmit Data Valid for Slave */
-#define ENUM_TWI_SLVCTL_INVALID              (_ADI_MSK(0x00000000,uint16_t))  /* TDVAL: Data Invalid for Slave Tx */
-#define ENUM_TWI_SLVCTL_VALID                (_ADI_MSK(0x00000004,uint16_t))  /* TDVAL: Data Valid for Slave Tx */
-
-#define BITM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* Enable Slave Mode */
-#define ENUM_TWI_SLVCTL_DIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVSTAT_GCALL                1                               /* General Call */
-#define BITP_TWI_SLVSTAT_DIR                  0                               /* Transfer Direction for Slave */
-
-#define BITM_TWI_SLVSTAT_GCALL               (_ADI_MSK(0x00000002,uint16_t))  /* General Call */
-#define ENUM_TWI_SLVSTAT_NO                  (_ADI_MSK(0x00000000,uint16_t))  /* GCALL: Not a General Call Address */
-#define ENUM_TWI_SLVSTAT_YES                 (_ADI_MSK(0x00000002,uint16_t))  /* GCALL: General Call Address */
-
-#define BITM_TWI_SLVSTAT_DIR                 (_ADI_MSK(0x00000001,uint16_t))  /* Transfer Direction for Slave */
-#define ENUM_TWI_SLVSTAT_RX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Slave Receive */
-#define ENUM_TWI_SLVSTAT_TX                  (_ADI_MSK(0x00000001,uint16_t))  /* DIR: Slave Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVADDR_ADDR                 0                               /* Slave Mode Address */
-#define BITM_TWI_SLVADDR_ADDR                (_ADI_MSK(0x0000007F,uint16_t))  /* Slave Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRCTL_SCLOVR              15                               /* Serial Clock Override */
-#define BITP_TWI_MSTRCTL_SDAOVR              14                               /* Serial Data Override */
-#define BITP_TWI_MSTRCTL_DCNT                 6                               /* Data Transfer Count */
-#define BITP_TWI_MSTRCTL_RSTART               5                               /* Repeat Start */
-#define BITP_TWI_MSTRCTL_STOP                 4                               /* Issue Stop Condition */
-#define BITP_TWI_MSTRCTL_FAST                 3                               /* Fast Mode */
-#define BITP_TWI_MSTRCTL_DIR                  2                               /* Transfer Direction for Master */
-#define BITP_TWI_MSTRCTL_EN                   0                               /* Enable Master Mode */
-
-#define BITM_TWI_MSTRCTL_SCLOVR              (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Override */
-#define ENUM_TWI_MSTRCTL_SCLNORM             (_ADI_MSK(0x00000000,uint16_t))  /* SCLOVR: Permit Normal SCL Operation */
-#define ENUM_TWI_MSTRCTL_SCLOVER             (_ADI_MSK(0x00008000,uint16_t))  /* SCLOVR: Override Normal SCL Operation */
-
-#define BITM_TWI_MSTRCTL_SDAOVR              (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Override */
-#define ENUM_TWI_MSTRCTL_SDANORM             (_ADI_MSK(0x00000000,uint16_t))  /* SDAOVR: Permit Normal SDA Operation */
-#define ENUM_TWI_MSTRCTL_SDAOVER             (_ADI_MSK(0x00004000,uint16_t))  /* SDAOVR: Override Normal SDA Operation */
-#define BITM_TWI_MSTRCTL_DCNT                (_ADI_MSK(0x00003FC0,uint16_t))  /* Data Transfer Count */
-
-#define BITM_TWI_MSTRCTL_RSTART              (_ADI_MSK(0x00000020,uint16_t))  /* Repeat Start */
-#define ENUM_TWI_MSTRCTL_END                 (_ADI_MSK(0x00000000,uint16_t))  /* RSTART: Disable Repeat Start */
-#define ENUM_TWI_MSTRCTL_RPT                 (_ADI_MSK(0x00000020,uint16_t))  /* RSTART: Enable Repeat Start */
-
-#define BITM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* Issue Stop Condition */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* STOP: Permit Normal Operation */
-#define ENUM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* STOP: Issue Stop */
-
-#define BITM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* Fast Mode */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* FAST: Select Standard Mode */
-#define ENUM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* FAST: Select Fast Mode */
-
-#define BITM_TWI_MSTRCTL_DIR                 (_ADI_MSK(0x00000004,uint16_t))  /* Transfer Direction for Master */
-#define ENUM_TWI_MSTRCTL_TX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Master Transmit */
-#define ENUM_TWI_MSTRCTL_RX                  (_ADI_MSK(0x00000004,uint16_t))  /* DIR: Master Receive */
-
-#define BITM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* Enable Master Mode */
-#define ENUM_TWI_MSTRCTL_DIS                 (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRSTAT_BUSBUSY             8                               /* Bus Busy */
-#define BITP_TWI_MSTRSTAT_SCLSEN              7                               /* Serial Clock Sense */
-#define BITP_TWI_MSTRSTAT_SDASEN              6                               /* Serial Data Sense */
-#define BITP_TWI_MSTRSTAT_BUFWRERR            5                               /* Buffer Write Error */
-#define BITP_TWI_MSTRSTAT_BUFRDERR            4                               /* Buffer Read Error */
-#define BITP_TWI_MSTRSTAT_DNAK                3                               /* Data Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_ANAK                2                               /* Address Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_LOSTARB             1                               /* Lost Arbitration */
-#define BITP_TWI_MSTRSTAT_MPROG               0                               /* Master Transfer in Progress */
-
-#define BITM_TWI_MSTRSTAT_BUSBUSY            (_ADI_MSK(0x00000100,uint16_t))  /* Bus Busy */
-#define ENUM_TWI_MSTRSTAT_FREE               (_ADI_MSK(0x00000000,uint16_t))  /* BUSBUSY: Bus Free */
-#define ENUM_TWI_MSTRSTAT_BUSY               (_ADI_MSK(0x00000100,uint16_t))  /* BUSBUSY: Bus Busy */
-
-#define BITM_TWI_MSTRSTAT_SCLSEN             (_ADI_MSK(0x00000080,uint16_t))  /* Serial Clock Sense */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SCLSEN: SCL Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_YES         (_ADI_MSK(0x00000080,uint16_t))  /* SCLSEN: SCL Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_SDASEN             (_ADI_MSK(0x00000040,uint16_t))  /* Serial Data Sense */
-#define ENUM_TWI_MSTRSTAT_SDASEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SDASEN: SDA Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SDASEN_YES         (_ADI_MSK(0x00000040,uint16_t))  /* SDASEN: SDA Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_BUFWRERR           (_ADI_MSK(0x00000020,uint16_t))  /* Buffer Write Error */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFWRERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_YES       (_ADI_MSK(0x00000020,uint16_t))  /* BUFWRERR: Buffer Write Error */
-
-#define BITM_TWI_MSTRSTAT_BUFRDERR           (_ADI_MSK(0x00000010,uint16_t))  /* Buffer Read Error */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFRDERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_YES       (_ADI_MSK(0x00000010,uint16_t))  /* BUFRDERR: Buffer Read Error */
-
-#define BITM_TWI_MSTRSTAT_DNAK               (_ADI_MSK(0x00000008,uint16_t))  /* Data Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_DNAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* DNAK: No Status */
-#define ENUM_TWI_MSTRSTAT_DNAK_YES           (_ADI_MSK(0x00000008,uint16_t))  /* DNAK: Data NAK */
-
-#define BITM_TWI_MSTRSTAT_ANAK               (_ADI_MSK(0x00000004,uint16_t))  /* Address Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_ANAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* ANAK: No Status */
-#define ENUM_TWI_MSTRSTAT_ANAK_YES           (_ADI_MSK(0x00000004,uint16_t))  /* ANAK: Address NAK */
-
-#define BITM_TWI_MSTRSTAT_LOSTARB            (_ADI_MSK(0x00000002,uint16_t))  /* Lost Arbitration */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_NO         (_ADI_MSK(0x00000000,uint16_t))  /* LOSTARB: No Status */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_YES        (_ADI_MSK(0x00000002,uint16_t))  /* LOSTARB: Lost Arbitration */
-
-#define BITM_TWI_MSTRSTAT_MPROG              (_ADI_MSK(0x00000001,uint16_t))  /* Master Transfer in Progress */
-#define ENUM_TWI_MSTRSTAT_MPROG_NO           (_ADI_MSK(0x00000000,uint16_t))  /* MPROG: No Status */
-#define ENUM_TWI_MSTRSTAT_MPROG_YES          (_ADI_MSK(0x00000001,uint16_t))  /* MPROG: Master Transfer in Progress */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRADDR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRADDR_ADDR                0                               /* Master Mode Address */
-#define BITM_TWI_MSTRADDR_ADDR               (_ADI_MSK(0x0000007F,uint16_t))  /* Master Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_ISTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_ISTAT_SCLI                  15                               /* Serial Clock Interrupt */
-#define BITP_TWI_ISTAT_SDAI                  14                               /* Serial Data Interrupt */
-#define BITP_TWI_ISTAT_RXSERV                 7                               /* Rx FIFO Service */
-#define BITP_TWI_ISTAT_TXSERV                 6                               /* Tx FIFO Service */
-#define BITP_TWI_ISTAT_MERR                   5                               /* Master Transfer Error */
-#define BITP_TWI_ISTAT_MCOMP                  4                               /* Master Transfer Complete */
-#define BITP_TWI_ISTAT_SOVF                   3                               /* Slave Overflow */
-#define BITP_TWI_ISTAT_SERR                   2                               /* Slave Transfer Error */
-#define BITP_TWI_ISTAT_SCOMP                  1                               /* Slave Transfer Complete */
-#define BITP_TWI_ISTAT_SINIT                  0                               /* Slave Transfer Initiated */
-
-#define BITM_TWI_ISTAT_SCLI                  (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: No Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_YES              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SDAI                  (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: No Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_YES              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_RXSERV                (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service */
-#define ENUM_TWI_ISTAT_RXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_RXSERV_YES            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_TXSERV                (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service */
-#define ENUM_TWI_ISTAT_TXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_TXSERV_YES            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MERR                  (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error */
-#define ENUM_TWI_ISTAT_MERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: No Interrupt */
-#define ENUM_TWI_ISTAT_MERR_YES              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MCOMP                 (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete */
-#define ENUM_TWI_ISTAT_MCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_MCOMP_YES             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SOVF                  (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow */
-#define ENUM_TWI_ISTAT_SOVF_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: No Interrupt */
-#define ENUM_TWI_ISTAT_SOVF_YES              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SERR                  (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error */
-#define ENUM_TWI_ISTAT_SERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: No Interrupt */
-#define ENUM_TWI_ISTAT_SERR_YES              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SCOMP                 (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete */
-#define ENUM_TWI_ISTAT_SCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_SCOMP_YES             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SINIT                 (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated */
-#define ENUM_TWI_ISTAT_SINIT_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: No Interrupt */
-#define ENUM_TWI_ISTAT_SINIT_YES             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Interrupt Detected */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_IMSK_SCLI                   15                               /* Serial Clock Interrupt Mask */
-#define BITP_TWI_IMSK_SDAI                   14                               /* Serial Data Interrupt Mask */
-#define BITP_TWI_IMSK_RXSERV                  7                               /* Rx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_TXSERV                  6                               /* Tx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_MERR                    5                               /* Master Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_MCOMP                   4                               /* Master Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SOVF                    3                               /* Slave Overflow Interrupt Mask */
-#define BITP_TWI_IMSK_SERR                    2                               /* Slave Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_SCOMP                   1                               /* Slave Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SINIT                   0                               /* Slave Transfer Initiated Interrupt Mask */
-
-#define BITM_TWI_IMSK_SCLI                   (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt Mask */
-#define ENUM_TWI_IMSK_SCLI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCLI_UMSK              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SDAI                   (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt Mask */
-#define ENUM_TWI_IMSK_SDAI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SDAI_UMSK              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_RXSERV                 (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_RXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_RXSERV_UMSK            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_TXSERV                 (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_TXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_TXSERV_UMSK            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MERR                   (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_MERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MERR_UMSK              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MCOMP                  (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_MCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MCOMP_UMSK             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SOVF                   (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow Interrupt Mask */
-#define ENUM_TWI_IMSK_SOVF_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SOVF_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SERR                   (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_SERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SERR_UMSK              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SCOMP                  (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_SCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCOMP_UMSK             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SINIT                  (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated Interrupt Mask */
-#define ENUM_TWI_IMSK_SINIT_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SINIT_UMSK             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Unmask (Enable) Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOCTL_RXILEN               3                               /* Rx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_TXILEN               2                               /* Tx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_RXFLUSH              1                               /* Rx Buffer Flush */
-#define BITP_TWI_FIFOCTL_TXFLUSH              0                               /* Tx Buffer Flush */
-
-#define BITM_TWI_FIFOCTL_RXILEN              (_ADI_MSK(0x00000008,uint16_t))  /* Rx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_RXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* RXILEN: RXSERVI on 1 or 2 Bytes in FIFO */
-#define ENUM_TWI_FIFOCTL_RXTWOBYTE           (_ADI_MSK(0x00000008,uint16_t))  /* RXILEN: RXSERVI on 2 Bytes in FIFO */
-
-#define BITM_TWI_FIFOCTL_TXILEN              (_ADI_MSK(0x00000004,uint16_t))  /* Tx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_TXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* TXILEN: TXSERVI on 1 Byte of FIFO Empty */
-#define ENUM_TWI_FIFOCTL_TXTWOBYTE           (_ADI_MSK(0x00000004,uint16_t))  /* TXILEN: TXSERVI on 2 Bytes of FIFO Empty */
-
-#define BITM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* Rx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_RXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* RXFLUSH: Normal Operation of Rx Buffer */
-#define ENUM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* RXFLUSH: Flush Rx Buffer */
-
-#define BITM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* Tx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_TXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* TXFLUSH: Normal Operation of Tx Buffer */
-#define ENUM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* TXFLUSH: Flush Tx Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOSTAT_RXSTAT              2                               /* Rx FIFO Status */
-#define BITP_TWI_FIFOSTAT_TXSTAT              0                               /* Tx FIFO Status */
-#define BITM_TWI_FIFOSTAT_RXSTAT             (_ADI_MSK(0x0000000C,uint16_t))  /* Rx FIFO Status */
-#define BITM_TWI_FIFOSTAT_TXSTAT             (_ADI_MSK(0x00000003,uint16_t))  /* Tx FIFO Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_TXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_TXDATA8_VALUE                0                               /* Tx Data 8-Bit Value */
-#define BITM_TWI_TXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Tx Data 8-Bit Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_RXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_RXDATA8_VALUE                0                               /* Rx Data 8-Bit Value */
-#define BITM_TWI_RXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Rx Data 8-Bit Value */
-
-/* ==================================================
-        UART Registers
-   ================================================== */
-
-/* =========================
-        UART0
-   ========================= */
-#define REG_UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
-#define REG_UART0_CTL                   0xFFC02004         /* UART0 Control Register */
-#define REG_UART0_STAT                  0xFFC02008         /* UART0 Status Register */
-#define REG_UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
-#define REG_UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
-#define REG_UART0_IMSK                  0xFFC02014         /* UART0 Interrupt Mask Register */
-#define REG_UART0_IMSK_SET              0xFFC02018         /* UART0 Interrupt Mask Set Register */
-#define REG_UART0_IMSK_CLR              0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
-#define REG_UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
-#define REG_UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
-#define REG_UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
-#define REG_UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
-#define REG_UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
-#define REG_UART0_TXCNT                 0xFFC02034         /* UART0 Transmit Counter Register */
-#define REG_UART0_RXCNT                 0xFFC02038         /* UART0 Receive Counter Register */
-
-/* =========================
-        UART1
-   ========================= */
-#define REG_UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
-#define REG_UART1_CTL                   0xFFC02404         /* UART1 Control Register */
-#define REG_UART1_STAT                  0xFFC02408         /* UART1 Status Register */
-#define REG_UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
-#define REG_UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
-#define REG_UART1_IMSK                  0xFFC02414         /* UART1 Interrupt Mask Register */
-#define REG_UART1_IMSK_SET              0xFFC02418         /* UART1 Interrupt Mask Set Register */
-#define REG_UART1_IMSK_CLR              0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
-#define REG_UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
-#define REG_UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
-#define REG_UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
-#define REG_UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
-#define REG_UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
-#define REG_UART1_TXCNT                 0xFFC02434         /* UART1 Transmit Counter Register */
-#define REG_UART1_RXCNT                 0xFFC02438         /* UART1 Receive Counter Register */
-
-/* =========================
-        UART
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_REVID_MAJOR                 4                               /* Major Version */
-#define BITP_UART_REVID_REV                   0                               /* Incremental Version */
-#define BITM_UART_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version */
-#define BITM_UART_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CTL_RFRT                   30                               /* Receive FIFO RTS Threshold */
-#define BITP_UART_CTL_RFIT                   29                               /* Receive FIFO IRQ Threshold */
-#define BITP_UART_CTL_ACTS                   28                               /* Automatic CTS */
-#define BITP_UART_CTL_ARTS                   27                               /* Automatic RTS */
-#define BITP_UART_CTL_XOFF                   26                               /* Transmitter off */
-#define BITP_UART_CTL_MRTS                   25                               /* Manual Request to Send */
-#define BITP_UART_CTL_TPOLC                  24                               /* IrDA TX Polarity Change */
-#define BITP_UART_CTL_RPOLC                  23                               /* IrDA RX Polarity Change */
-#define BITP_UART_CTL_FCPOL                  22                               /* Flow Control Pin Polarity */
-#define BITP_UART_CTL_SB                     19                               /* Set Break */
-#define BITP_UART_CTL_FFE                    18                               /* Force Framing Error on Transmit */
-#define BITP_UART_CTL_FPE                    17                               /* Force Parity Error on Transmit */
-#define BITP_UART_CTL_STP                    16                               /* Sticky Parity */
-#define BITP_UART_CTL_EPS                    15                               /* Even Parity Select */
-#define BITP_UART_CTL_PEN                    14                               /* Parity Enable */
-#define BITP_UART_CTL_STBH                   13                               /* Stop Bits (Half Bit Time) */
-#define BITP_UART_CTL_STB                    12                               /* Stop Bits */
-#define BITP_UART_CTL_WLS                     8                               /* Word Length Select */
-#define BITP_UART_CTL_MOD                     4                               /* Mode of Operation */
-#define BITP_UART_CTL_LOOP_EN                 1                               /* Loopback Enable */
-#define BITP_UART_CTL_EN                      0                               /* Enable UART */
-
-#define BITM_UART_CTL_RFRT                   (_ADI_MSK(0x40000000,uint32_t))  /* Receive FIFO RTS Threshold */
-#define ENUM_UART_CTL_RX_RTS_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 4; assert if <= 4 */
-#define ENUM_UART_CTL_RX_RTS_TH7             (_ADI_MSK(0x40000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 7; assert if <= 7 */
-
-#define BITM_UART_CTL_RFIT                   (_ADI_MSK(0x20000000,uint32_t))  /* Receive FIFO IRQ Threshold */
-#define ENUM_UART_CTL_RX_IRQ_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 4 */
-#define ENUM_UART_CTL_RX_IRQ_TH7             (_ADI_MSK(0x20000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 7 */
-
-#define BITM_UART_CTL_ACTS                   (_ADI_MSK(0x10000000,uint32_t))  /* Automatic CTS */
-#define ENUM_UART_CTL_CTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ACTS: Disable TX handshaking protocol */
-#define ENUM_UART_CTL_CTS_AUTO               (_ADI_MSK(0x10000000,uint32_t))  /* ACTS: Enable TX handshaking protocol */
-
-#define BITM_UART_CTL_ARTS                   (_ADI_MSK(0x08000000,uint32_t))  /* Automatic RTS */
-#define ENUM_UART_CTL_RTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ARTS: Disable RX handshaking protocol. */
-#define ENUM_UART_CTL_RTS_AUTO               (_ADI_MSK(0x08000000,uint32_t))  /* ARTS: Enable RX handshaking protocol. */
-
-#define BITM_UART_CTL_XOFF                   (_ADI_MSK(0x04000000,uint32_t))  /* Transmitter off */
-#define ENUM_UART_CTL_TX_ON                  (_ADI_MSK(0x00000000,uint32_t))  /* XOFF: Transmission ON, if ACTS=0 */
-#define ENUM_UART_CTL_TX_OFF                 (_ADI_MSK(0x04000000,uint32_t))  /* XOFF: Transmission OFF, if ACTS=0 */
-
-#define BITM_UART_CTL_MRTS                   (_ADI_MSK(0x02000000,uint32_t))  /* Manual Request to Send */
-#define ENUM_UART_CTL_RTS_DEASSERT           (_ADI_MSK(0x00000000,uint32_t))  /* MRTS: De-assert RTS pin when ARTS=0 */
-#define ENUM_UART_CTL_RTS_ASSERT             (_ADI_MSK(0x02000000,uint32_t))  /* MRTS: Assert RTS pin  when ARTS=0 */
-
-#define BITM_UART_CTL_TPOLC                  (_ADI_MSK(0x01000000,uint32_t))  /* IrDA TX Polarity Change */
-#define ENUM_UART_CTL_TPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* TPOLC: Active-low TX polarity setting */
-#define ENUM_UART_CTL_TPOLC_HI               (_ADI_MSK(0x01000000,uint32_t))  /* TPOLC: Active-high TX polarity setting */
-
-#define BITM_UART_CTL_RPOLC                  (_ADI_MSK(0x00800000,uint32_t))  /* IrDA RX Polarity Change */
-#define ENUM_UART_CTL_RPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RPOLC: Active-low RX polarity setting */
-#define ENUM_UART_CTL_RPOLC_HI               (_ADI_MSK(0x00800000,uint32_t))  /* RPOLC: Active-high RX polarity setting */
-
-#define BITM_UART_CTL_FCPOL                  (_ADI_MSK(0x00400000,uint32_t))  /* Flow Control Pin Polarity */
-#define ENUM_UART_CTL_FCPOL_LO               (_ADI_MSK(0x00000000,uint32_t))  /* FCPOL: Active low CTS/RTS */
-#define ENUM_UART_CTL_FCPOL_HI               (_ADI_MSK(0x00400000,uint32_t))  /* FCPOL: Active high CTS/RTS */
-
-#define BITM_UART_CTL_SB                     (_ADI_MSK(0x00080000,uint32_t))  /* Set Break */
-#define ENUM_UART_CTL_NORM_BREAK             (_ADI_MSK(0x00000000,uint32_t))  /* SB: No force */
-#define ENUM_UART_CTL_FORCE_BREAK            (_ADI_MSK(0x00080000,uint32_t))  /* SB: Force TX pin to 0 */
-
-#define BITM_UART_CTL_FFE                    (_ADI_MSK(0x00040000,uint32_t))  /* Force Framing Error on Transmit */
-#define ENUM_UART_CTL_NORM_FRM_ERR           (_ADI_MSK(0x00000000,uint32_t))  /* FFE: Normal operation */
-#define ENUM_UART_CTL_FORCE_FRM_ERR          (_ADI_MSK(0x00040000,uint32_t))  /* FFE: Force error */
-
-#define BITM_UART_CTL_FPE                    (_ADI_MSK(0x00020000,uint32_t))  /* Force Parity Error on Transmit */
-#define ENUM_UART_CTL_NORM_PARITY_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FPE: Normal operation */
-#define ENUM_UART_CTL_FORCE_PARITY_ERR       (_ADI_MSK(0x00020000,uint32_t))  /* FPE: Force parity error */
-
-#define BITM_UART_CTL_STP                    (_ADI_MSK(0x00010000,uint32_t))  /* Sticky Parity */
-#define ENUM_UART_CTL_NORM_PARITY            (_ADI_MSK(0x00000000,uint32_t))  /* STP: No Forced Parity */
-#define ENUM_UART_CTL_STICKY_PARITY          (_ADI_MSK(0x00010000,uint32_t))  /* STP: Force (Stick) Parity to Defined Value (if PEN=1) */
-
-#define BITM_UART_CTL_EPS                    (_ADI_MSK(0x00008000,uint32_t))  /* Even Parity Select */
-#define ENUM_UART_CTL_ODD_PARITY             (_ADI_MSK(0x00000000,uint32_t))  /* EPS: Odd parity */
-#define ENUM_UART_CTL_EVEN_PARITY            (_ADI_MSK(0x00008000,uint32_t))  /* EPS: Even parity */
-
-#define BITM_UART_CTL_PEN                    (_ADI_MSK(0x00004000,uint32_t))  /* Parity Enable */
-#define ENUM_UART_CTL_PARITY_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* PEN: Disable */
-#define ENUM_UART_CTL_PARITY_EN              (_ADI_MSK(0x00004000,uint32_t))  /* PEN: Enable parity transmit and check */
-
-#define BITM_UART_CTL_STBH                   (_ADI_MSK(0x00002000,uint32_t))  /* Stop Bits (Half Bit Time) */
-#define ENUM_UART_CTL_NO_EXTRA_STBH          (_ADI_MSK(0x00000000,uint32_t))  /* STBH: 0 half-bit-time stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STBH           (_ADI_MSK(0x00002000,uint32_t))  /* STBH: 1 half-bit-time stop bit */
-
-#define BITM_UART_CTL_STB                    (_ADI_MSK(0x00001000,uint32_t))  /* Stop Bits */
-#define ENUM_UART_CTL_NO_EXTRA_STB           (_ADI_MSK(0x00000000,uint32_t))  /* STB: 1 stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STB            (_ADI_MSK(0x00001000,uint32_t))  /* STB: 2 stop bits */
-
-#define BITM_UART_CTL_WLS                    (_ADI_MSK(0x00000300,uint32_t))  /* Word Length Select */
-#define ENUM_UART_CTL_WL5BITS                (_ADI_MSK(0x00000000,uint32_t))  /* WLS: 5-bit Word */
-#define ENUM_UART_CTL_WL6BITS                (_ADI_MSK(0x00000100,uint32_t))  /* WLS: 6-bit Word */
-#define ENUM_UART_CTL_WL7BITS                (_ADI_MSK(0x00000200,uint32_t))  /* WLS: 7-bit Word */
-#define ENUM_UART_CTL_WL8BITS                (_ADI_MSK(0x00000300,uint32_t))  /* WLS: 8-bit Word */
-
-#define BITM_UART_CTL_MOD                    (_ADI_MSK(0x00000030,uint32_t))  /* Mode of Operation */
-#define ENUM_UART_CTL_UART_MODE              (_ADI_MSK(0x00000000,uint32_t))  /* MOD: UART Mode */
-#define ENUM_UART_CTL_MDB_MODE               (_ADI_MSK(0x00000010,uint32_t))  /* MOD: MDB Mode */
-#define ENUM_UART_CTL_IRDA_MODE              (_ADI_MSK(0x00000020,uint32_t))  /* MOD: IrDA SIR Mode */
-
-#define BITM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* Loopback Enable */
-#define ENUM_UART_CTL_LOOP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* LOOP_EN: Disable */
-#define ENUM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* LOOP_EN: Enable */
-
-#define BITM_UART_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable UART */
-#define ENUM_UART_CTL_CLK_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_UART_CTL_CLK_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_STAT_RFCS                  17                               /* Receive FIFO Count Status */
-#define BITP_UART_STAT_CTS                   16                               /* Clear to Send */
-#define BITP_UART_STAT_SCTS                  12                               /* Sticky CTS */
-#define BITP_UART_STAT_RO                    11                               /* Reception On-going */
-#define BITP_UART_STAT_ADDR                  10                               /* Address Bit Status */
-#define BITP_UART_STAT_ASTKY                  9                               /* Address Sticky */
-#define BITP_UART_STAT_TFI                    8                               /* Transmission Finished Indicator */
-#define BITP_UART_STAT_TEMT                   7                               /* TSR and THR Empty */
-#define BITP_UART_STAT_THRE                   5                               /* Transmit Hold Register Empty */
-#define BITP_UART_STAT_BI                     4                               /* Break Indicator */
-#define BITP_UART_STAT_FE                     3                               /* Framing Error */
-#define BITP_UART_STAT_PE                     2                               /* Parity Error */
-#define BITP_UART_STAT_OE                     1                               /* Overrun Error */
-#define BITP_UART_STAT_DR                     0                               /* Data Ready */
-
-#define BITM_UART_STAT_RFCS                  (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Count Status */
-#define ENUM_UART_STAT_RFCS_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RFCS: RX FIFO has less than 4 (7) entries when RFIT=0 (1) */
-#define ENUM_UART_STAT_RFCS_HI               (_ADI_MSK(0x00020000,uint32_t))  /* RFCS: RX FIFO has at least 4 (7) entries when RFIT=0 (1) */
-
-#define BITM_UART_STAT_CTS                   (_ADI_MSK(0x00010000,uint32_t))  /* Clear to Send */
-#define ENUM_UART_STAT_CTS_LO                (_ADI_MSK(0x00000000,uint32_t))  /* CTS: Not clear to send (External device not ready to receive) */
-#define ENUM_UART_STAT_CTS_HI                (_ADI_MSK(0x00010000,uint32_t))  /* CTS: Clear to send (External device ready to receive) */
-
-#define BITM_UART_STAT_SCTS                  (_ADI_MSK(0x00001000,uint32_t))  /* Sticky CTS */
-#define ENUM_UART_STAT_CTS_LO_STKY           (_ADI_MSK(0x00000000,uint32_t))  /* SCTS: CTS has not transitioned from low to high */
-#define ENUM_UART_STAT_CTS_HI_STKY           (_ADI_MSK(0x00001000,uint32_t))  /* SCTS: CTS has transitioned from low to high */
-
-#define BITM_UART_STAT_RO                    (_ADI_MSK(0x00000800,uint32_t))  /* Reception On-going */
-#define ENUM_UART_STAT_NO_RX_PROGRESS        (_ADI_MSK(0x00000000,uint32_t))  /* RO: No data reception in progress */
-#define ENUM_UART_STAT_RX_PROGRESS           (_ADI_MSK(0x00000800,uint32_t))  /* RO: Data reception in progress */
-
-#define BITM_UART_STAT_ADDR                  (_ADI_MSK(0x00000400,uint32_t))  /* Address Bit Status */
-#define ENUM_UART_STAT_ADDR_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ADDR: Address bit is low */
-#define ENUM_UART_STAT_ADDR_HI               (_ADI_MSK(0x00000400,uint32_t))  /* ADDR: Address bit is high */
-
-#define BITM_UART_STAT_ASTKY                 (_ADI_MSK(0x00000200,uint32_t))  /* Address Sticky */
-#define ENUM_UART_STAT_ADDR_LO_STKY          (_ADI_MSK(0x00000000,uint32_t))  /* ASTKY: ADDR bit has not been set */
-#define ENUM_UART_STAT_ADDR_HI_STKY          (_ADI_MSK(0x00000200,uint32_t))  /* ASTKY: ADDR bit has been set */
-
-#define BITM_UART_STAT_TFI                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmission Finished Indicator */
-#define ENUM_UART_STAT_TX_NOT_DONE           (_ADI_MSK(0x00000000,uint32_t))  /* TFI: TEMT did not transition from 0 to 1 */
-#define ENUM_UART_STAT_TX_DONE               (_ADI_MSK(0x00000100,uint32_t))  /* TFI: TEMT transition from 0 to 1 */
-
-#define BITM_UART_STAT_TEMT                  (_ADI_MSK(0x00000080,uint32_t))  /* TSR and THR Empty */
-#define ENUM_UART_STAT_TX_NOT_EMPTY          (_ADI_MSK(0x00000000,uint32_t))  /* TEMT: Not empty TSR/THR */
-#define ENUM_UART_STAT_TX_EMPTY              (_ADI_MSK(0x00000080,uint32_t))  /* TEMT: TSR/THR Empty */
-
-#define BITM_UART_STAT_THRE                  (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Hold Register Empty */
-#define ENUM_UART_STAT_THR_NOT_EMPTY         (_ADI_MSK(0x00000000,uint32_t))  /* THRE: Not empty THR/TAIP */
-#define ENUM_UART_STAT_THR_EMPTY             (_ADI_MSK(0x00000020,uint32_t))  /* THRE: Empty THR/TAIP */
-
-#define BITM_UART_STAT_BI                    (_ADI_MSK(0x00000010,uint32_t))  /* Break Indicator */
-#define ENUM_UART_STAT_NO_BREAK_INT          (_ADI_MSK(0x00000000,uint32_t))  /* BI: No break interrupt */
-#define ENUM_UART_STAT_BREAK_INT             (_ADI_MSK(0x00000010,uint32_t))  /* BI: Break interrupt */
-
-#define BITM_UART_STAT_FE                    (_ADI_MSK(0x00000008,uint32_t))  /* Framing Error */
-#define ENUM_UART_STAT_NO_FRAMING_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FE: No error */
-#define ENUM_UART_STAT_FRAMING_ERR           (_ADI_MSK(0x00000008,uint32_t))  /* FE: Invalid stop bit error */
-
-#define BITM_UART_STAT_PE                    (_ADI_MSK(0x00000004,uint32_t))  /* Parity Error */
-#define ENUM_UART_STAT_NO_PARITY_ERR         (_ADI_MSK(0x00000000,uint32_t))  /* PE: No parity error */
-#define ENUM_UART_STAT_PARITY_ERR            (_ADI_MSK(0x00000004,uint32_t))  /* PE: Parity error */
-
-#define BITM_UART_STAT_OE                    (_ADI_MSK(0x00000002,uint32_t))  /* Overrun Error */
-#define ENUM_UART_STAT_NO_OVR_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* OE: No overrun */
-#define ENUM_UART_STAT_OVR_ERR               (_ADI_MSK(0x00000002,uint32_t))  /* OE: Overrun error */
-
-#define BITM_UART_STAT_DR                    (_ADI_MSK(0x00000001,uint32_t))  /* Data Ready */
-#define ENUM_UART_STAT_NO_DATA               (_ADI_MSK(0x00000000,uint32_t))  /* DR: No new data */
-#define ENUM_UART_STAT_NEW_DATA              (_ADI_MSK(0x00000001,uint32_t))  /* DR: New data in RBR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_SCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_SCR_VALUE                   0                               /* Stored 8-bit Data */
-#define BITM_UART_SCR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Stored 8-bit Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CLK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CLK_EDBO                   31                               /* Enable Divide By One */
-#define BITP_UART_CLK_DIV                     0                               /* Divisor */
-
-#define BITM_UART_CLK_EDBO                   (_ADI_MSK(0x80000000,uint32_t))  /* Enable Divide By One */
-#define ENUM_UART_CLK_DIS_DIV_BY_ONE         (_ADI_MSK(0x00000000,uint32_t))  /* EDBO: Bit clock prescaler = 16 */
-#define ENUM_UART_CLK_EN_DIV_BY_ONE          (_ADI_MSK(0x80000000,uint32_t))  /* EDBO: Bit clock prescaler = 1 */
-#define BITM_UART_CLK_DIV                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_ETXS                   9                               /* Enable TX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ERXS                   8                               /* Enable RX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_EAWI                   7                               /* Enable Address Word Interrupt Mask Status */
-#define BITP_UART_IMSK_ERFCI                  6                               /* Enable Receive FIFO Count Interrupt Mask Status */
-#define BITP_UART_IMSK_ETFI                   5                               /* Enable Transmission Finished Interrupt Mask Status */
-#define BITP_UART_IMSK_EDTPTI                 4                               /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define BITP_UART_IMSK_EDSSI                  3                               /* Enable Modem Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ELSI                   2                               /* Enable Line Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ETBEI                  1                               /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define BITP_UART_IMSK_ERBFI                  0                               /* Enable Receive Buffer Full Interrupt Mask Status */
-
-#define BITM_UART_IMSK_ETXS                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Status */
-#define ENUM_UART_ETXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETXS: Interrupt is masked */
-#define ENUM_UART_ETXS_HI                    (_ADI_MSK(0x00000200,uint32_t))  /* ETXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERXS                  (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Status */
-#define ENUM_UART_ERXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ERXS: Interrupt is masked */
-#define ENUM_UART_ERXS_HI                    (_ADI_MSK(0x00000100,uint32_t))  /* ERXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EAWI                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Status */
-#define ENUM_UART_EAWI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* EAWI: Interrupt is masked */
-#define ENUM_UART_EAWI_HI                    (_ADI_MSK(0x00000080,uint32_t))  /* EAWI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERFCI                 (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Status */
-#define ENUM_UART_ERFCI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERFCI: Interrupt is masked */
-#define ENUM_UART_ERFCI_HI                   (_ADI_MSK(0x00000040,uint32_t))  /* ERFCI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETFI                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Status */
-#define ENUM_UART_ETFI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETFI: Interrupt is masked */
-#define ENUM_UART_ETFI_HI                    (_ADI_MSK(0x00000020,uint32_t))  /* ETFI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDTPTI                (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define ENUM_UART_EDTPTI_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* EDTPTI: Interrupt is masked */
-#define ENUM_UART_EDTPTI_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* EDTPTI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDSSI                 (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Status */
-#define ENUM_UART_EDSSI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* EDSSI: Interrupt is masked */
-#define ENUM_UART_EDSSI_HI                   (_ADI_MSK(0x00000008,uint32_t))  /* EDSSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ELSI                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Status */
-#define ENUM_UART_ELSI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ELSI: Interrupt is masked */
-#define ENUM_UART_ELSI_HI                    (_ADI_MSK(0x00000004,uint32_t))  /* ELSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETBEI                 (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define ENUM_UART_ETBEI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ETBEI: Interrupt is masked */
-#define ENUM_UART_ETBEI_HI                   (_ADI_MSK(0x00000002,uint32_t))  /* ETBEI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERBFI                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Status */
-#define ENUM_UART_ERBFI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERBFI: Interrupt is masked */
-#define ENUM_UART_ERBFI_HI                   (_ADI_MSK(0x00000001,uint32_t))  /* ERBFI: Interrupt is unmasked */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_SET_ETXS               9                               /* Enable TX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERXS               8                               /* Enable RX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EAWI               7                               /* Enable Address Word Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDSSI              3                               /* Enable Modem Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ELSI               2                               /* Enable Line Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* The fields and enumerations for UART_IMSK_SET are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_SET_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_CLR_ETXS               9                               /* Enable TX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERXS               8                               /* Enable RX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EAWI               7                               /* Enable Address Word Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDSSI              3                               /* Enable Modem Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ELSI               2                               /* Enable Line Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* The fields and enumerations for UART_IMSK_CLR are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_CLR_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RBR_VALUE                   0                               /* 8-bit data */
-#define BITM_UART_RBR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_THR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_THR_VALUE                   0                               /* 8 bit data */
-#define BITM_UART_THR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8 bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TAIP                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TAIP_VALUE                  0                               /* 8-bit data */
-#define BITM_UART_TAIP_VALUE                 (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TSR_VALUE                   0                               /* Contents of TSR */
-#define BITM_UART_TSR_VALUE                  (_ADI_MSK(0x000007FF,uint32_t))  /* Contents of TSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RSR_VALUE                   0                               /* Contents of RSR */
-#define BITM_UART_RSR_VALUE                  (_ADI_MSK(0x000003FF,uint32_t))  /* Contents of RSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_TXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_RXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ==================================================
-        General Purpose Input/Output Registers
-   ================================================== */
-
-/* =========================
-        PORTA
-   ========================= */
-#define REG_PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
-#define REG_PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
-#define REG_PORTA_FER_CLR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
-#define REG_PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
-#define REG_PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
-#define REG_PORTA_DATA_CLR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
-#define REG_PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
-#define REG_PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
-#define REG_PORTA_DIR_CLR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
-#define REG_PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
-#define REG_PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
-#define REG_PORTA_INEN_CLR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
-#define REG_PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
-#define REG_PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
-#define REG_PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Polarity Invert Register */
-#define REG_PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Polarity Invert Set Register */
-#define REG_PORTA_POL_CLR               0xFFC03040         /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
-#define REG_PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
-
-/* =========================
-        PORTB
-   ========================= */
-#define REG_PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
-#define REG_PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
-#define REG_PORTB_FER_CLR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
-#define REG_PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
-#define REG_PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
-#define REG_PORTB_DATA_CLR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
-#define REG_PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
-#define REG_PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
-#define REG_PORTB_DIR_CLR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
-#define REG_PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
-#define REG_PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
-#define REG_PORTB_INEN_CLR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
-#define REG_PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
-#define REG_PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
-#define REG_PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Polarity Invert Register */
-#define REG_PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Polarity Invert Set Register */
-#define REG_PORTB_POL_CLR               0xFFC030C0         /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
-#define REG_PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
-
-/* =========================
-        PORTC
-   ========================= */
-#define REG_PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
-#define REG_PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
-#define REG_PORTC_FER_CLR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
-#define REG_PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
-#define REG_PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
-#define REG_PORTC_DATA_CLR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
-#define REG_PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
-#define REG_PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
-#define REG_PORTC_DIR_CLR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
-#define REG_PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
-#define REG_PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
-#define REG_PORTC_INEN_CLR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
-#define REG_PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
-#define REG_PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
-#define REG_PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Polarity Invert Register */
-#define REG_PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Polarity Invert Set Register */
-#define REG_PORTC_POL_CLR               0xFFC03140         /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
-#define REG_PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
-
-/* =========================
-        PORTD
-   ========================= */
-#define REG_PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
-#define REG_PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
-#define REG_PORTD_FER_CLR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
-#define REG_PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
-#define REG_PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
-#define REG_PORTD_DATA_CLR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
-#define REG_PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
-#define REG_PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
-#define REG_PORTD_DIR_CLR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
-#define REG_PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
-#define REG_PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
-#define REG_PORTD_INEN_CLR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
-#define REG_PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
-#define REG_PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
-#define REG_PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Polarity Invert Register */
-#define REG_PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Polarity Invert Set Register */
-#define REG_PORTD_POL_CLR               0xFFC031C0         /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
-#define REG_PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
-
-/* =========================
-        PORTE
-   ========================= */
-#define REG_PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
-#define REG_PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
-#define REG_PORTE_FER_CLR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
-#define REG_PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
-#define REG_PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
-#define REG_PORTE_DATA_CLR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
-#define REG_PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
-#define REG_PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
-#define REG_PORTE_DIR_CLR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
-#define REG_PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
-#define REG_PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
-#define REG_PORTE_INEN_CLR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
-#define REG_PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
-#define REG_PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
-#define REG_PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Polarity Invert Register */
-#define REG_PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Polarity Invert Set Register */
-#define REG_PORTE_POL_CLR               0xFFC03240         /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
-#define REG_PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
-
-/* =========================
-        PORTF
-   ========================= */
-#define REG_PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
-#define REG_PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
-#define REG_PORTF_FER_CLR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
-#define REG_PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
-#define REG_PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
-#define REG_PORTF_DATA_CLR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
-#define REG_PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
-#define REG_PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
-#define REG_PORTF_DIR_CLR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
-#define REG_PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
-#define REG_PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
-#define REG_PORTF_INEN_CLR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
-#define REG_PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
-#define REG_PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
-#define REG_PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Polarity Invert Register */
-#define REG_PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Polarity Invert Set Register */
-#define REG_PORTF_POL_CLR               0xFFC032C0         /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
-#define REG_PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
-
-/* =========================
-        PORTG
-   ========================= */
-#define REG_PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
-#define REG_PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
-#define REG_PORTG_FER_CLR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
-#define REG_PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
-#define REG_PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
-#define REG_PORTG_DATA_CLR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
-#define REG_PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
-#define REG_PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
-#define REG_PORTG_DIR_CLR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
-#define REG_PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
-#define REG_PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
-#define REG_PORTG_INEN_CLR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
-#define REG_PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
-#define REG_PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
-#define REG_PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Polarity Invert Register */
-#define REG_PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Polarity Invert Set Register */
-#define REG_PORTG_POL_CLR               0xFFC03340         /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
-#define REG_PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
-
-/* =========================
-        PORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_PX15                   15                               /* Port x Bit 15 Mode */
-#define BITP_PORT_FER_PX14                   14                               /* Port x Bit 14 Mode */
-#define BITP_PORT_FER_PX13                   13                               /* Port x Bit 13 Mode */
-#define BITP_PORT_FER_PX12                   12                               /* Port x Bit 12 Mode */
-#define BITP_PORT_FER_PX11                   11                               /* Port x Bit 11 Mode */
-#define BITP_PORT_FER_PX10                   10                               /* Port x Bit 10 Mode */
-#define BITP_PORT_FER_PX9                     9                               /* Port x Bit 9 Mode */
-#define BITP_PORT_FER_PX8                     8                               /* Port x Bit 8 Mode */
-#define BITP_PORT_FER_PX7                     7                               /* Port x Bit 7 Mode */
-#define BITP_PORT_FER_PX6                     6                               /* Port x Bit 6 Mode */
-#define BITP_PORT_FER_PX5                     5                               /* Port x Bit 5 Mode */
-#define BITP_PORT_FER_PX4                     4                               /* Port x Bit 4 Mode */
-#define BITP_PORT_FER_PX3                     3                               /* Port x Bit 3 Mode */
-#define BITP_PORT_FER_PX2                     2                               /* Port x Bit 2 Mode */
-#define BITP_PORT_FER_PX1                     1                               /* Port x Bit 1 Mode */
-#define BITP_PORT_FER_PX0                     0                               /* Port x Bit 0 Mode */
-#define BITM_PORT_FER_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode */
-#define BITM_PORT_FER_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode */
-#define BITM_PORT_FER_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode */
-#define BITM_PORT_FER_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode */
-#define BITM_PORT_FER_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode */
-#define BITM_PORT_FER_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode */
-#define BITM_PORT_FER_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode */
-#define BITM_PORT_FER_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode */
-#define BITM_PORT_FER_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode */
-#define BITM_PORT_FER_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode */
-#define BITM_PORT_FER_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode */
-#define BITM_PORT_FER_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode */
-#define BITM_PORT_FER_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode */
-#define BITM_PORT_FER_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode */
-#define BITM_PORT_FER_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode */
-#define BITM_PORT_FER_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_SET_PX15               15                               /* Port x Bit 15 Mode Set */
-#define BITP_PORT_FER_SET_PX14               14                               /* Port x Bit 14 Mode Set */
-#define BITP_PORT_FER_SET_PX13               13                               /* Port x Bit 13 Mode Set */
-#define BITP_PORT_FER_SET_PX12               12                               /* Port x Bit 12 Mode Set */
-#define BITP_PORT_FER_SET_PX11               11                               /* Port x Bit 11 Mode Set */
-#define BITP_PORT_FER_SET_PX10               10                               /* Port x Bit 10 Mode Set */
-#define BITP_PORT_FER_SET_PX9                 9                               /* Port x Bit 9 Mode Set */
-#define BITP_PORT_FER_SET_PX8                 8                               /* Port x Bit 8 Mode Set */
-#define BITP_PORT_FER_SET_PX7                 7                               /* Port x Bit 7 Mode Set */
-#define BITP_PORT_FER_SET_PX6                 6                               /* Port x Bit 6 Mode Set */
-#define BITP_PORT_FER_SET_PX5                 5                               /* Port x Bit 5 Mode Set */
-#define BITP_PORT_FER_SET_PX4                 4                               /* Port x Bit 4 Mode Set */
-#define BITP_PORT_FER_SET_PX3                 3                               /* Port x Bit 3 Mode Set */
-#define BITP_PORT_FER_SET_PX2                 2                               /* Port x Bit 2 Mode Set */
-#define BITP_PORT_FER_SET_PX1                 1                               /* Port x Bit 1 Mode Set */
-#define BITP_PORT_FER_SET_PX0                 0                               /* Port x Bit 0 Mode Set */
-#define BITM_PORT_FER_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Set */
-#define BITM_PORT_FER_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Set */
-#define BITM_PORT_FER_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Set */
-#define BITM_PORT_FER_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Set */
-#define BITM_PORT_FER_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Set */
-#define BITM_PORT_FER_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Set */
-#define BITM_PORT_FER_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Set */
-#define BITM_PORT_FER_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Set */
-#define BITM_PORT_FER_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Set */
-#define BITM_PORT_FER_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Set */
-#define BITM_PORT_FER_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Set */
-#define BITM_PORT_FER_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Set */
-#define BITM_PORT_FER_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Set */
-#define BITM_PORT_FER_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Set */
-#define BITM_PORT_FER_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Set */
-#define BITM_PORT_FER_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_CLR_PX15               15                               /* Port x Bit 15 Mode Clear */
-#define BITP_PORT_FER_CLR_PX14               14                               /* Port x Bit 14 Mode Clear */
-#define BITP_PORT_FER_CLR_PX13               13                               /* Port x Bit 13 Mode Clear */
-#define BITP_PORT_FER_CLR_PX12               12                               /* Port x Bit 12 Mode Clear */
-#define BITP_PORT_FER_CLR_PX11               11                               /* Port x Bit 11 Mode Clear */
-#define BITP_PORT_FER_CLR_PX10               10                               /* Port x Bit 10 Mode Clear */
-#define BITP_PORT_FER_CLR_PX9                 9                               /* Port x Bit 9 Mode Clear */
-#define BITP_PORT_FER_CLR_PX8                 8                               /* Port x Bit 8 Mode Clear */
-#define BITP_PORT_FER_CLR_PX7                 7                               /* Port x Bit 7 Mode Clear */
-#define BITP_PORT_FER_CLR_PX6                 6                               /* Port x Bit 6 Mode Clear */
-#define BITP_PORT_FER_CLR_PX5                 5                               /* Port x Bit 5 Mode Clear */
-#define BITP_PORT_FER_CLR_PX4                 4                               /* Port x Bit 4 Mode Clear */
-#define BITP_PORT_FER_CLR_PX3                 3                               /* Port x Bit 3 Mode Clear */
-#define BITP_PORT_FER_CLR_PX2                 2                               /* Port x Bit 2 Mode Clear */
-#define BITP_PORT_FER_CLR_PX1                 1                               /* Port x Bit 1 Mode Clear */
-#define BITP_PORT_FER_CLR_PX0                 0                               /* Port x Bit 0 Mode Clear */
-#define BITM_PORT_FER_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Clear */
-#define BITM_PORT_FER_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Clear */
-#define BITM_PORT_FER_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Clear */
-#define BITM_PORT_FER_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Clear */
-#define BITM_PORT_FER_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Clear */
-#define BITM_PORT_FER_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Clear */
-#define BITM_PORT_FER_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Clear */
-#define BITM_PORT_FER_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Clear */
-#define BITM_PORT_FER_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Clear */
-#define BITM_PORT_FER_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Clear */
-#define BITM_PORT_FER_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Clear */
-#define BITM_PORT_FER_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Clear */
-#define BITM_PORT_FER_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Clear */
-#define BITM_PORT_FER_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Clear */
-#define BITM_PORT_FER_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Clear */
-#define BITM_PORT_FER_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_PX15                  15                               /* Port x Bit 15 Data */
-#define BITP_PORT_DATA_PX14                  14                               /* Port x Bit 14 Data */
-#define BITP_PORT_DATA_PX13                  13                               /* Port x Bit 13 Data */
-#define BITP_PORT_DATA_PX12                  12                               /* Port x Bit 12 Data */
-#define BITP_PORT_DATA_PX11                  11                               /* Port x Bit 11 Data */
-#define BITP_PORT_DATA_PX10                  10                               /* Port x Bit 10 Data */
-#define BITP_PORT_DATA_PX9                    9                               /* Port x Bit 9 Data */
-#define BITP_PORT_DATA_PX8                    8                               /* Port x Bit 8 Data */
-#define BITP_PORT_DATA_PX7                    7                               /* Port x Bit 7 Data */
-#define BITP_PORT_DATA_PX6                    6                               /* Port x Bit 6 Data */
-#define BITP_PORT_DATA_PX5                    5                               /* Port x Bit 5 Data */
-#define BITP_PORT_DATA_PX4                    4                               /* Port x Bit 4 Data */
-#define BITP_PORT_DATA_PX3                    3                               /* Port x Bit 3 Data */
-#define BITP_PORT_DATA_PX2                    2                               /* Port x Bit 2 Data */
-#define BITP_PORT_DATA_PX1                    1                               /* Port x Bit 1 Data */
-#define BITP_PORT_DATA_PX0                    0                               /* Port x Bit 0 Data */
-#define BITM_PORT_DATA_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data */
-#define BITM_PORT_DATA_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data */
-#define BITM_PORT_DATA_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data */
-#define BITM_PORT_DATA_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data */
-#define BITM_PORT_DATA_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data */
-#define BITM_PORT_DATA_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data */
-#define BITM_PORT_DATA_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data */
-#define BITM_PORT_DATA_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data */
-#define BITM_PORT_DATA_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data */
-#define BITM_PORT_DATA_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data */
-#define BITM_PORT_DATA_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data */
-#define BITM_PORT_DATA_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data */
-#define BITM_PORT_DATA_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data */
-#define BITM_PORT_DATA_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data */
-#define BITM_PORT_DATA_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data */
-#define BITM_PORT_DATA_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_SET_PX15              15                               /* Port x Bit 15 Data Set */
-#define BITP_PORT_DATA_SET_PX14              14                               /* Port x Bit 14 Data Set */
-#define BITP_PORT_DATA_SET_PX13              13                               /* Port x Bit 13 Data Set */
-#define BITP_PORT_DATA_SET_PX12              12                               /* Port x Bit 12 Data Set */
-#define BITP_PORT_DATA_SET_PX11              11                               /* Port x Bit 11 Data Set */
-#define BITP_PORT_DATA_SET_PX10              10                               /* Port x Bit 10 Data Set */
-#define BITP_PORT_DATA_SET_PX9                9                               /* Port x Bit 9 Data Set */
-#define BITP_PORT_DATA_SET_PX8                8                               /* Port x Bit 8 Data Set */
-#define BITP_PORT_DATA_SET_PX7                7                               /* Port x Bit 7 Data Set */
-#define BITP_PORT_DATA_SET_PX6                6                               /* Port x Bit 6 Data Set */
-#define BITP_PORT_DATA_SET_PX5                5                               /* Port x Bit 5 Data Set */
-#define BITP_PORT_DATA_SET_PX4                4                               /* Port x Bit 4 Data Set */
-#define BITP_PORT_DATA_SET_PX3                3                               /* Port x Bit 3 Data Set */
-#define BITP_PORT_DATA_SET_PX2                2                               /* Port x Bit 2 Data Set */
-#define BITP_PORT_DATA_SET_PX1                1                               /* Port x Bit 1 Data Set */
-#define BITP_PORT_DATA_SET_PX0                0                               /* Port x Bit 0 Data Set */
-#define BITM_PORT_DATA_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Set */
-#define BITM_PORT_DATA_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Set */
-#define BITM_PORT_DATA_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Set */
-#define BITM_PORT_DATA_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Set */
-#define BITM_PORT_DATA_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Set */
-#define BITM_PORT_DATA_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Set */
-#define BITM_PORT_DATA_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Set */
-#define BITM_PORT_DATA_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Set */
-#define BITM_PORT_DATA_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Set */
-#define BITM_PORT_DATA_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Set */
-#define BITM_PORT_DATA_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Set */
-#define BITM_PORT_DATA_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Set */
-#define BITM_PORT_DATA_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Set */
-#define BITM_PORT_DATA_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Set */
-#define BITM_PORT_DATA_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Set */
-#define BITM_PORT_DATA_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_CLR_PX15              15                               /* Port x Bit 15 Data Clear */
-#define BITP_PORT_DATA_CLR_PX14              14                               /* Port x Bit 14 Data Clear */
-#define BITP_PORT_DATA_CLR_PX13              13                               /* Port x Bit 13 Data Clear */
-#define BITP_PORT_DATA_CLR_PX12              12                               /* Port x Bit 12 Data Clear */
-#define BITP_PORT_DATA_CLR_PX11              11                               /* Port x Bit 11 Data Clear */
-#define BITP_PORT_DATA_CLR_PX10              10                               /* Port x Bit 10 Data Clear */
-#define BITP_PORT_DATA_CLR_PX9                9                               /* Port x Bit 9 Data Clear */
-#define BITP_PORT_DATA_CLR_PX8                8                               /* Port x Bit 8 Data Clear */
-#define BITP_PORT_DATA_CLR_PX7                7                               /* Port x Bit 7 Data Clear */
-#define BITP_PORT_DATA_CLR_PX6                6                               /* Port x Bit 6 Data Clear */
-#define BITP_PORT_DATA_CLR_PX5                5                               /* Port x Bit 5 Data Clear */
-#define BITP_PORT_DATA_CLR_PX4                4                               /* Port x Bit 4 Data Clear */
-#define BITP_PORT_DATA_CLR_PX3                3                               /* Port x Bit 3 Data Clear */
-#define BITP_PORT_DATA_CLR_PX2                2                               /* Port x Bit 2 Data Clear */
-#define BITP_PORT_DATA_CLR_PX1                1                               /* Port x Bit 1 Data Clear */
-#define BITP_PORT_DATA_CLR_PX0                0                               /* Port x Bit 0 Data Clear */
-#define BITM_PORT_DATA_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Clear */
-#define BITM_PORT_DATA_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Clear */
-#define BITM_PORT_DATA_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Clear */
-#define BITM_PORT_DATA_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Clear */
-#define BITM_PORT_DATA_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Clear */
-#define BITM_PORT_DATA_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Clear */
-#define BITM_PORT_DATA_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Clear */
-#define BITM_PORT_DATA_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Clear */
-#define BITM_PORT_DATA_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Clear */
-#define BITM_PORT_DATA_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Clear */
-#define BITM_PORT_DATA_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Clear */
-#define BITM_PORT_DATA_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Clear */
-#define BITM_PORT_DATA_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Clear */
-#define BITM_PORT_DATA_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Clear */
-#define BITM_PORT_DATA_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Clear */
-#define BITM_PORT_DATA_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_PX15                   15                               /* Port x Bit 15 Direction */
-#define BITP_PORT_DIR_PX14                   14                               /* Port x Bit 14 Direction */
-#define BITP_PORT_DIR_PX13                   13                               /* Port x Bit 13 Direction */
-#define BITP_PORT_DIR_PX12                   12                               /* Port x Bit 12 Direction */
-#define BITP_PORT_DIR_PX11                   11                               /* Port x Bit 11 Direction */
-#define BITP_PORT_DIR_PX10                   10                               /* Port x Bit 10 Direction */
-#define BITP_PORT_DIR_PX9                     9                               /* Port x Bit 9 Direction */
-#define BITP_PORT_DIR_PX8                     8                               /* Port x Bit 8 Direction */
-#define BITP_PORT_DIR_PX7                     7                               /* Port x Bit 7 Direction */
-#define BITP_PORT_DIR_PX6                     6                               /* Port x Bit 6 Direction */
-#define BITP_PORT_DIR_PX5                     5                               /* Port x Bit 5 Direction */
-#define BITP_PORT_DIR_PX4                     4                               /* Port x Bit 4 Direction */
-#define BITP_PORT_DIR_PX3                     3                               /* Port x Bit 3 Direction */
-#define BITP_PORT_DIR_PX2                     2                               /* Port x Bit 2 Direction */
-#define BITP_PORT_DIR_PX1                     1                               /* Port x Bit 1 Direction */
-#define BITP_PORT_DIR_PX0                     0                               /* Port x Bit 0 Direction */
-#define BITM_PORT_DIR_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction */
-#define BITM_PORT_DIR_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction */
-#define BITM_PORT_DIR_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction */
-#define BITM_PORT_DIR_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction */
-#define BITM_PORT_DIR_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction */
-#define BITM_PORT_DIR_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction */
-#define BITM_PORT_DIR_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction */
-#define BITM_PORT_DIR_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction */
-#define BITM_PORT_DIR_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction */
-#define BITM_PORT_DIR_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction */
-#define BITM_PORT_DIR_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction */
-#define BITM_PORT_DIR_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction */
-#define BITM_PORT_DIR_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction */
-#define BITM_PORT_DIR_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction */
-#define BITM_PORT_DIR_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction */
-#define BITM_PORT_DIR_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_SET_PX15               15                               /* Port x Bit 15 Direction Set */
-#define BITP_PORT_DIR_SET_PX14               14                               /* Port x Bit 14 Direction Set */
-#define BITP_PORT_DIR_SET_PX13               13                               /* Port x Bit 13 Direction Set */
-#define BITP_PORT_DIR_SET_PX12               12                               /* Port x Bit 12 Direction Set */
-#define BITP_PORT_DIR_SET_PX11               11                               /* Port x Bit 11 Direction Set */
-#define BITP_PORT_DIR_SET_PX10               10                               /* Port x Bit 10 Direction Set */
-#define BITP_PORT_DIR_SET_PX9                 9                               /* Port x Bit 9 Direction Set */
-#define BITP_PORT_DIR_SET_PX8                 8                               /* Port x Bit 8 Direction Set */
-#define BITP_PORT_DIR_SET_PX7                 7                               /* Port x Bit 7 Direction Set */
-#define BITP_PORT_DIR_SET_PX6                 6                               /* Port x Bit 6 Direction Set */
-#define BITP_PORT_DIR_SET_PX5                 5                               /* Port x Bit 5 Direction Set */
-#define BITP_PORT_DIR_SET_PX4                 4                               /* Port x Bit 4 Direction Set */
-#define BITP_PORT_DIR_SET_PX3                 3                               /* Port x Bit 3 Direction Set */
-#define BITP_PORT_DIR_SET_PX2                 2                               /* Port x Bit 2 Direction Set */
-#define BITP_PORT_DIR_SET_PX1                 1                               /* Port x Bit 1 Direction Set */
-#define BITP_PORT_DIR_SET_PX0                 0                               /* Port x Bit 0 Direction Set */
-#define BITM_PORT_DIR_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Set */
-#define BITM_PORT_DIR_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Set */
-#define BITM_PORT_DIR_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Set */
-#define BITM_PORT_DIR_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Set */
-#define BITM_PORT_DIR_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Set */
-#define BITM_PORT_DIR_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Set */
-#define BITM_PORT_DIR_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Set */
-#define BITM_PORT_DIR_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Set */
-#define BITM_PORT_DIR_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Set */
-#define BITM_PORT_DIR_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Set */
-#define BITM_PORT_DIR_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Set */
-#define BITM_PORT_DIR_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Set */
-#define BITM_PORT_DIR_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Set */
-#define BITM_PORT_DIR_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Set */
-#define BITM_PORT_DIR_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Set */
-#define BITM_PORT_DIR_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_CLR_PX15               15                               /* Port x Bit 15 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX14               14                               /* Port x Bit 14 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX13               13                               /* Port x Bit 13 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX12               12                               /* Port x Bit 12 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX11               11                               /* Port x Bit 11 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX10               10                               /* Port x Bit 10 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX9                 9                               /* Port x Bit 9 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX8                 8                               /* Port x Bit 8 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX7                 7                               /* Port x Bit 7 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX6                 6                               /* Port x Bit 6 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX5                 5                               /* Port x Bit 5 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX4                 4                               /* Port x Bit 4 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX3                 3                               /* Port x Bit 3 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX2                 2                               /* Port x Bit 2 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX1                 1                               /* Port x Bit 1 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX0                 0                               /* Port x Bit 0 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_PX15                  15                               /* Port x Bit 15 Input Enable */
-#define BITP_PORT_INEN_PX14                  14                               /* Port x Bit 14 Input Enable */
-#define BITP_PORT_INEN_PX13                  13                               /* Port x Bit 13 Input Enable */
-#define BITP_PORT_INEN_PX12                  12                               /* Port x Bit 12 Input Enable */
-#define BITP_PORT_INEN_PX11                  11                               /* Port x Bit 11 Input Enable */
-#define BITP_PORT_INEN_PX10                  10                               /* Port x Bit 10 Input Enable */
-#define BITP_PORT_INEN_PX9                    9                               /* Port x Bit 9 Input Enable */
-#define BITP_PORT_INEN_PX8                    8                               /* Port x Bit 8 Input Enable */
-#define BITP_PORT_INEN_PX7                    7                               /* Port x Bit 7 Input Enable */
-#define BITP_PORT_INEN_PX6                    6                               /* Port x Bit 6 Input Enable */
-#define BITP_PORT_INEN_PX5                    5                               /* Port x Bit 5 Input Enable */
-#define BITP_PORT_INEN_PX4                    4                               /* Port x Bit 4 Input Enable */
-#define BITP_PORT_INEN_PX3                    3                               /* Port x Bit 3 Input Enable */
-#define BITP_PORT_INEN_PX2                    2                               /* Port x Bit 2 Input Enable */
-#define BITP_PORT_INEN_PX1                    1                               /* Port x Bit 1 Input Enable */
-#define BITP_PORT_INEN_PX0                    0                               /* Port x Bit 0 Input Enable */
-#define BITM_PORT_INEN_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable */
-#define BITM_PORT_INEN_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable */
-#define BITM_PORT_INEN_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable */
-#define BITM_PORT_INEN_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable */
-#define BITM_PORT_INEN_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable */
-#define BITM_PORT_INEN_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable */
-#define BITM_PORT_INEN_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable */
-#define BITM_PORT_INEN_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable */
-#define BITM_PORT_INEN_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable */
-#define BITM_PORT_INEN_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable */
-#define BITM_PORT_INEN_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable */
-#define BITM_PORT_INEN_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable */
-#define BITM_PORT_INEN_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable */
-#define BITM_PORT_INEN_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable */
-#define BITM_PORT_INEN_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable */
-#define BITM_PORT_INEN_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_SET_PX15              15                               /* Port x Bit 15 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX14              14                               /* Port x Bit 14 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX13              13                               /* Port x Bit 13 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX12              12                               /* Port x Bit 12 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX11              11                               /* Port x Bit 11 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX10              10                               /* Port x Bit 10 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX9                9                               /* Port x Bit 9 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX8                8                               /* Port x Bit 8 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX7                7                               /* Port x Bit 7 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX6                6                               /* Port x Bit 6 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX5                5                               /* Port x Bit 5 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX4                4                               /* Port x Bit 4 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX3                3                               /* Port x Bit 3 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX2                2                               /* Port x Bit 2 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX1                1                               /* Port x Bit 1 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX0                0                               /* Port x Bit 0 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_CLR_PX15              15                               /* Port x Bit 15 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX14              14                               /* Port x Bit 14 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX13              13                               /* Port x Bit 13 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX12              12                               /* Port x Bit 12 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX11              11                               /* Port x Bit 11 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX10              10                               /* Port x Bit 10 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX9                9                               /* Port x Bit 9 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX8                8                               /* Port x Bit 8 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX7                7                               /* Port x Bit 7 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX6                6                               /* Port x Bit 6 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX5                5                               /* Port x Bit 5 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX4                4                               /* Port x Bit 4 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX3                3                               /* Port x Bit 3 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX2                2                               /* Port x Bit 2 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX1                1                               /* Port x Bit 1 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX0                0                               /* Port x Bit 0 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_MUX                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_MUX_MUX15                  30                               /* Mux for Port x Bit 15 */
-#define BITP_PORT_MUX_MUX14                  28                               /* Mux for Port x Bit 14 */
-#define BITP_PORT_MUX_MUX13                  26                               /* Mux for Port x Bit 13 */
-#define BITP_PORT_MUX_MUX12                  24                               /* Mux for Port x Bit 12 */
-#define BITP_PORT_MUX_MUX11                  22                               /* Mux for Port x Bit 11 */
-#define BITP_PORT_MUX_MUX10                  20                               /* Mux for Port x Bit 10 */
-#define BITP_PORT_MUX_MUX9                   18                               /* Mux for Port x Bit 9 */
-#define BITP_PORT_MUX_MUX8                   16                               /* Mux for Port x Bit 8 */
-#define BITP_PORT_MUX_MUX7                   14                               /* Mux for Port x Bit 7 */
-#define BITP_PORT_MUX_MUX6                   12                               /* Mux for Port x Bit 6 */
-#define BITP_PORT_MUX_MUX5                   10                               /* Mux for Port x Bit 5 */
-#define BITP_PORT_MUX_MUX4                    8                               /* Mux for Port x Bit 4 */
-#define BITP_PORT_MUX_MUX3                    6                               /* Mux for Port x Bit 3 */
-#define BITP_PORT_MUX_MUX2                    4                               /* Mux for Port x Bit 2 */
-#define BITP_PORT_MUX_MUX1                    2                               /* Mux for Port x Bit 1 */
-#define BITP_PORT_MUX_MUX0                    0                               /* Mux for Port x Bit 0 */
-#define BITM_PORT_MUX_MUX15                  (_ADI_MSK(0xC0000000,uint32_t))  /* Mux for Port x Bit 15 */
-#define BITM_PORT_MUX_MUX14                  (_ADI_MSK(0x30000000,uint32_t))  /* Mux for Port x Bit 14 */
-#define BITM_PORT_MUX_MUX13                  (_ADI_MSK(0x0C000000,uint32_t))  /* Mux for Port x Bit 13 */
-#define BITM_PORT_MUX_MUX12                  (_ADI_MSK(0x03000000,uint32_t))  /* Mux for Port x Bit 12 */
-#define BITM_PORT_MUX_MUX11                  (_ADI_MSK(0x00C00000,uint32_t))  /* Mux for Port x Bit 11 */
-#define BITM_PORT_MUX_MUX10                  (_ADI_MSK(0x00300000,uint32_t))  /* Mux for Port x Bit 10 */
-#define BITM_PORT_MUX_MUX9                   (_ADI_MSK(0x000C0000,uint32_t))  /* Mux for Port x Bit 9 */
-#define BITM_PORT_MUX_MUX8                   (_ADI_MSK(0x00030000,uint32_t))  /* Mux for Port x Bit 8 */
-#define BITM_PORT_MUX_MUX7                   (_ADI_MSK(0x0000C000,uint32_t))  /* Mux for Port x Bit 7 */
-#define BITM_PORT_MUX_MUX6                   (_ADI_MSK(0x00003000,uint32_t))  /* Mux for Port x Bit 6 */
-#define BITM_PORT_MUX_MUX5                   (_ADI_MSK(0x00000C00,uint32_t))  /* Mux for Port x Bit 5 */
-#define BITM_PORT_MUX_MUX4                   (_ADI_MSK(0x00000300,uint32_t))  /* Mux for Port x Bit 4 */
-#define BITM_PORT_MUX_MUX3                   (_ADI_MSK(0x000000C0,uint32_t))  /* Mux for Port x Bit 3 */
-#define BITM_PORT_MUX_MUX2                   (_ADI_MSK(0x00000030,uint32_t))  /* Mux for Port x Bit 2 */
-#define BITM_PORT_MUX_MUX1                   (_ADI_MSK(0x0000000C,uint32_t))  /* Mux for Port x Bit 1 */
-#define BITM_PORT_MUX_MUX0                   (_ADI_MSK(0x00000003,uint32_t))  /* Mux for Port x Bit 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_TGL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_TGL_PX15              15                               /* Port x Bit 15 Toggle */
-#define BITP_PORT_DATA_TGL_PX14              14                               /* Port x Bit 14 Toggle */
-#define BITP_PORT_DATA_TGL_PX13              13                               /* Port x Bit 13 Toggle */
-#define BITP_PORT_DATA_TGL_PX12              12                               /* Port x Bit 12 Toggle */
-#define BITP_PORT_DATA_TGL_PX11              11                               /* Port x Bit 11 Toggle */
-#define BITP_PORT_DATA_TGL_PX10              10                               /* Port x Bit 10 Toggle */
-#define BITP_PORT_DATA_TGL_PX9                9                               /* Port x Bit 9 Toggle */
-#define BITP_PORT_DATA_TGL_PX8                8                               /* Port x Bit 8 Toggle */
-#define BITP_PORT_DATA_TGL_PX7                7                               /* Port x Bit 7 Toggle */
-#define BITP_PORT_DATA_TGL_PX6                6                               /* Port x Bit 6 Toggle */
-#define BITP_PORT_DATA_TGL_PX5                5                               /* Port x Bit 5 Toggle */
-#define BITP_PORT_DATA_TGL_PX4                4                               /* Port x Bit 4 Toggle */
-#define BITP_PORT_DATA_TGL_PX3                3                               /* Port x Bit 3 Toggle */
-#define BITP_PORT_DATA_TGL_PX2                2                               /* Port x Bit 2 Toggle */
-#define BITP_PORT_DATA_TGL_PX1                1                               /* Port x Bit 1 Toggle */
-#define BITP_PORT_DATA_TGL_PX0                0                               /* Port x Bit 0 Toggle */
-#define BITM_PORT_DATA_TGL_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Toggle */
-#define BITM_PORT_DATA_TGL_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Toggle */
-#define BITM_PORT_DATA_TGL_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Toggle */
-#define BITM_PORT_DATA_TGL_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Toggle */
-#define BITM_PORT_DATA_TGL_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Toggle */
-#define BITM_PORT_DATA_TGL_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Toggle */
-#define BITM_PORT_DATA_TGL_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Toggle */
-#define BITM_PORT_DATA_TGL_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Toggle */
-#define BITM_PORT_DATA_TGL_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Toggle */
-#define BITM_PORT_DATA_TGL_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Toggle */
-#define BITM_PORT_DATA_TGL_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Toggle */
-#define BITM_PORT_DATA_TGL_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Toggle */
-#define BITM_PORT_DATA_TGL_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Toggle */
-#define BITM_PORT_DATA_TGL_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Toggle */
-#define BITM_PORT_DATA_TGL_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Toggle */
-#define BITM_PORT_DATA_TGL_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Toggle */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_PX15                   15                               /* Port x Bit 15 Polarity Invert */
-#define BITP_PORT_POL_PX14                   14                               /* Port x Bit 14 Polarity Invert */
-#define BITP_PORT_POL_PX13                   13                               /* Port x Bit 13 Polarity Invert */
-#define BITP_PORT_POL_PX12                   12                               /* Port x Bit 12 Polarity Invert */
-#define BITP_PORT_POL_PX11                   11                               /* Port x Bit 11 Polarity Invert */
-#define BITP_PORT_POL_PX10                   10                               /* Port x Bit 10 Polarity Invert */
-#define BITP_PORT_POL_PX9                     9                               /* Port x Bit 9 Polarity Invert */
-#define BITP_PORT_POL_PX8                     8                               /* Port x Bit 8 Polarity Invert */
-#define BITP_PORT_POL_PX7                     7                               /* Port x Bit 7 Polarity Invert */
-#define BITP_PORT_POL_PX6                     6                               /* Port x Bit 6 Polarity Invert */
-#define BITP_PORT_POL_PX5                     5                               /* Port x Bit 5 Polarity Invert */
-#define BITP_PORT_POL_PX4                     4                               /* Port x Bit 4 Polarity Invert */
-#define BITP_PORT_POL_PX3                     3                               /* Port x Bit 3 Polarity Invert */
-#define BITP_PORT_POL_PX2                     2                               /* Port x Bit 2 Polarity Invert */
-#define BITP_PORT_POL_PX1                     1                               /* Port x Bit 1 Polarity Invert */
-#define BITP_PORT_POL_PX0                     0                               /* Port x Bit 0 Polarity Invert */
-#define BITM_PORT_POL_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert */
-#define BITM_PORT_POL_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert */
-#define BITM_PORT_POL_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert */
-#define BITM_PORT_POL_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert */
-#define BITM_PORT_POL_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert */
-#define BITM_PORT_POL_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert */
-#define BITM_PORT_POL_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert */
-#define BITM_PORT_POL_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert */
-#define BITM_PORT_POL_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert */
-#define BITM_PORT_POL_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert */
-#define BITM_PORT_POL_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert */
-#define BITM_PORT_POL_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert */
-#define BITM_PORT_POL_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert */
-#define BITM_PORT_POL_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert */
-#define BITM_PORT_POL_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert */
-#define BITM_PORT_POL_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_SET_PX15               15                               /* Port x Bit 15 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX14               14                               /* Port x Bit 14 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX13               13                               /* Port x Bit 13 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX12               12                               /* Port x Bit 12 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX11               11                               /* Port x Bit 11 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX10               10                               /* Port x Bit 10 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX9                 9                               /* Port x Bit 9 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX8                 8                               /* Port x Bit 8 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX7                 7                               /* Port x Bit 7 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX6                 6                               /* Port x Bit 6 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX5                 5                               /* Port x Bit 5 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX4                 4                               /* Port x Bit 4 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX3                 3                               /* Port x Bit 3 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX2                 2                               /* Port x Bit 2 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX1                 1                               /* Port x Bit 1 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX0                 0                               /* Port x Bit 0 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_CLR_PX15               15                               /* Port x Bit 15 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX14               14                               /* Port x Bit 14 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX13               13                               /* Port x Bit 13 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX12               12                               /* Port x Bit 12 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX11               11                               /* Port x Bit 11 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX10               10                               /* Port x Bit 10 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX9                 9                               /* Port x Bit 9 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX8                 8                               /* Port x Bit 8 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX7                 7                               /* Port x Bit 7 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX6                 6                               /* Port x Bit 6 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX5                 5                               /* Port x Bit 5 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX4                 4                               /* Port x Bit 4 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX3                 3                               /* Port x Bit 3 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX2                 2                               /* Port x Bit 2 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX1                 1                               /* Port x Bit 1 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX0                 0                               /* Port x Bit 0 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_LOCK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_LOCK_LOCK                  31                               /* Lock */
-#define BITP_PORT_LOCK_POLAR                  5                               /* Polarity Lock */
-#define BITP_PORT_LOCK_INEN                   4                               /* Input Enable Lock */
-#define BITP_PORT_LOCK_DIR                    3                               /* Direction Lock */
-#define BITP_PORT_LOCK_DATA                   2                               /* Data Lock */
-#define BITP_PORT_LOCK_MUX                    1                               /* Function Multiplexer Lock */
-#define BITP_PORT_LOCK_FER                    0                               /* Function Enable Lock */
-#define BITM_PORT_LOCK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_PORT_LOCK_POLAR                 (_ADI_MSK(0x00000020,uint32_t))  /* Polarity Lock */
-#define BITM_PORT_LOCK_INEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Input Enable Lock */
-#define BITM_PORT_LOCK_DIR                   (_ADI_MSK(0x00000008,uint32_t))  /* Direction Lock */
-#define BITM_PORT_LOCK_DATA                  (_ADI_MSK(0x00000004,uint32_t))  /* Data Lock */
-#define BITM_PORT_LOCK_MUX                   (_ADI_MSK(0x00000002,uint32_t))  /* Function Multiplexer Lock */
-#define BITM_PORT_LOCK_FER                   (_ADI_MSK(0x00000001,uint32_t))  /* Function Enable Lock */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_REVID_MAJOR                 4                               /* Major ID */
-#define BITP_PORT_REVID_REV                   0                               /* Revision ID */
-#define BITM_PORT_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PORT_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID */
-
-/* ==================================================
-        Pads Controller Registers
-   ================================================== */
-
-/* =========================
-        PADS0
-   ========================= */
-#define REG_PADS0_EMAC_PTP_CLKSEL       0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
-#define REG_PADS0_TWI_VSEL              0xFFC03408         /* PADS0 TWI Voltage Selection */
-#define REG_PADS0_PORTS_HYST            0xFFC03440         /* PADS0 Hysteresis Enable Register */
-
-/* =========================
-        PADS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_EMAC_PTP_CLKSEL                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC1       2                               /* Select Clock Source for PTP Block in EMAC1 */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC0       0                               /* PTP Clock Source 0 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC1      (_ADI_MSK(0x0000000C,uint32_t))  /* Select Clock Source for PTP Block in EMAC1 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC0      (_ADI_MSK(0x00000003,uint32_t))  /* PTP Clock Source 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_TWI_VSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_TWI_VSEL_TWI1               4                               /* TWI Voltage Select 1 */
-#define BITP_PADS_TWI_VSEL_TWI0               0                               /* TWI Voltage Select 0 */
-#define BITM_PADS_TWI_VSEL_TWI1              (_ADI_MSK(0x00000070,uint32_t))  /* TWI Voltage Select 1 */
-#define BITM_PADS_TWI_VSEL_TWI0              (_ADI_MSK(0x00000007,uint32_t))  /* TWI Voltage Select 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_PORTS_HYST                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_PORTS_HYST_G                6                               /* Port G Hysteresis */
-#define BITP_PADS_PORTS_HYST_F                5                               /* Port F Hysteresis */
-#define BITP_PADS_PORTS_HYST_E                4                               /* Port E Hysteresis */
-#define BITP_PADS_PORTS_HYST_D                3                               /* Port D Hysteresis */
-#define BITP_PADS_PORTS_HYST_C                2                               /* Port C Hysteresis */
-#define BITP_PADS_PORTS_HYST_B                1                               /* Port B Hysteresis */
-#define BITP_PADS_PORTS_HYST_A                0                               /* Port A Hysteresis */
-#define BITM_PADS_PORTS_HYST_G               (_ADI_MSK(0x00000040,uint32_t))  /* Port G Hysteresis */
-#define BITM_PADS_PORTS_HYST_F               (_ADI_MSK(0x00000020,uint32_t))  /* Port F Hysteresis */
-#define BITM_PADS_PORTS_HYST_E               (_ADI_MSK(0x00000010,uint32_t))  /* Port E Hysteresis */
-#define BITM_PADS_PORTS_HYST_D               (_ADI_MSK(0x00000008,uint32_t))  /* Port D Hysteresis */
-#define BITM_PADS_PORTS_HYST_C               (_ADI_MSK(0x00000004,uint32_t))  /* Port C Hysteresis */
-#define BITM_PADS_PORTS_HYST_B               (_ADI_MSK(0x00000002,uint32_t))  /* Port B Hysteresis */
-#define BITM_PADS_PORTS_HYST_A               (_ADI_MSK(0x00000001,uint32_t))  /* Port A Hysteresis */
-
-/* ==================================================
-        PINT Registers
-   ================================================== */
-
-/* =========================
-        PINT0
-   ========================= */
-#define REG_PINT0_MSK_SET               0xFFC04000         /* PINT0 Pint Mask Set Register */
-#define REG_PINT0_MSK_CLR               0xFFC04004         /* PINT0 Pint Mask Clear Register */
-#define REG_PINT0_REQ                   0xFFC04008         /* PINT0 Pint Request Register */
-#define REG_PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
-#define REG_PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
-#define REG_PINT0_EDGE_CLR              0xFFC04014         /* PINT0 Pint Edge Clear Register */
-#define REG_PINT0_INV_SET               0xFFC04018         /* PINT0 Pint Invert Set Register */
-#define REG_PINT0_INV_CLR               0xFFC0401C         /* PINT0 Pint Invert Clear Register */
-#define REG_PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
-#define REG_PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
-
-/* =========================
-        PINT1
-   ========================= */
-#define REG_PINT1_MSK_SET               0xFFC04100         /* PINT1 Pint Mask Set Register */
-#define REG_PINT1_MSK_CLR               0xFFC04104         /* PINT1 Pint Mask Clear Register */
-#define REG_PINT1_REQ                   0xFFC04108         /* PINT1 Pint Request Register */
-#define REG_PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
-#define REG_PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
-#define REG_PINT1_EDGE_CLR              0xFFC04114         /* PINT1 Pint Edge Clear Register */
-#define REG_PINT1_INV_SET               0xFFC04118         /* PINT1 Pint Invert Set Register */
-#define REG_PINT1_INV_CLR               0xFFC0411C         /* PINT1 Pint Invert Clear Register */
-#define REG_PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
-#define REG_PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
-
-/* =========================
-        PINT2
-   ========================= */
-#define REG_PINT2_MSK_SET               0xFFC04200         /* PINT2 Pint Mask Set Register */
-#define REG_PINT2_MSK_CLR               0xFFC04204         /* PINT2 Pint Mask Clear Register */
-#define REG_PINT2_REQ                   0xFFC04208         /* PINT2 Pint Request Register */
-#define REG_PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
-#define REG_PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
-#define REG_PINT2_EDGE_CLR              0xFFC04214         /* PINT2 Pint Edge Clear Register */
-#define REG_PINT2_INV_SET               0xFFC04218         /* PINT2 Pint Invert Set Register */
-#define REG_PINT2_INV_CLR               0xFFC0421C         /* PINT2 Pint Invert Clear Register */
-#define REG_PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
-#define REG_PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
-
-/* =========================
-        PINT3
-   ========================= */
-#define REG_PINT3_MSK_SET               0xFFC04300         /* PINT3 Pint Mask Set Register */
-#define REG_PINT3_MSK_CLR               0xFFC04304         /* PINT3 Pint Mask Clear Register */
-#define REG_PINT3_REQ                   0xFFC04308         /* PINT3 Pint Request Register */
-#define REG_PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
-#define REG_PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
-#define REG_PINT3_EDGE_CLR              0xFFC04314         /* PINT3 Pint Edge Clear Register */
-#define REG_PINT3_INV_SET               0xFFC04318         /* PINT3 Pint Invert Set Register */
-#define REG_PINT3_INV_CLR               0xFFC0431C         /* PINT3 Pint Invert Clear Register */
-#define REG_PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
-#define REG_PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
-
-/* =========================
-        PINT4
-   ========================= */
-#define REG_PINT4_MSK_SET               0xFFC04400         /* PINT4 Pint Mask Set Register */
-#define REG_PINT4_MSK_CLR               0xFFC04404         /* PINT4 Pint Mask Clear Register */
-#define REG_PINT4_REQ                   0xFFC04408         /* PINT4 Pint Request Register */
-#define REG_PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
-#define REG_PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
-#define REG_PINT4_EDGE_CLR              0xFFC04414         /* PINT4 Pint Edge Clear Register */
-#define REG_PINT4_INV_SET               0xFFC04418         /* PINT4 Pint Invert Set Register */
-#define REG_PINT4_INV_CLR               0xFFC0441C         /* PINT4 Pint Invert Clear Register */
-#define REG_PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
-#define REG_PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
-
-/* =========================
-        PINT5
-   ========================= */
-#define REG_PINT5_MSK_SET               0xFFC04500         /* PINT5 Pint Mask Set Register */
-#define REG_PINT5_MSK_CLR               0xFFC04504         /* PINT5 Pint Mask Clear Register */
-#define REG_PINT5_REQ                   0xFFC04508         /* PINT5 Pint Request Register */
-#define REG_PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
-#define REG_PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
-#define REG_PINT5_EDGE_CLR              0xFFC04514         /* PINT5 Pint Edge Clear Register */
-#define REG_PINT5_INV_SET               0xFFC04518         /* PINT5 Pint Invert Set Register */
-#define REG_PINT5_INV_CLR               0xFFC0451C         /* PINT5 Pint Invert Clear Register */
-#define REG_PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
-#define REG_PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
-
-/* =========================
-        PINT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_SET_PIQ31              31                               /* Pin Interrupt 31 Unmask */
-#define BITP_PINT_MSK_SET_PIQ30              30                               /* Pin Interrupt 30 Unmask */
-#define BITP_PINT_MSK_SET_PIQ29              29                               /* Pin Interrupt 29 Unmask */
-#define BITP_PINT_MSK_SET_PIQ28              28                               /* Pin Interrupt 28 Unmask */
-#define BITP_PINT_MSK_SET_PIQ27              27                               /* Pin Interrupt 27 Unmask */
-#define BITP_PINT_MSK_SET_PIQ26              26                               /* Pin Interrupt 26 Unmask */
-#define BITP_PINT_MSK_SET_PIQ25              25                               /* Pin Interrupt 25 Unmask */
-#define BITP_PINT_MSK_SET_PIQ24              24                               /* Pin Interrupt 24 Unmask */
-#define BITP_PINT_MSK_SET_PIQ23              23                               /* Pin Interrupt 23 Unmask */
-#define BITP_PINT_MSK_SET_PIQ22              22                               /* Pin Interrupt 22 Unmask */
-#define BITP_PINT_MSK_SET_PIQ21              21                               /* Pin Interrupt 21 Unmask */
-#define BITP_PINT_MSK_SET_PIQ20              20                               /* Pin Interrupt 20 Unmask */
-#define BITP_PINT_MSK_SET_PIQ19              19                               /* Pin Interrupt 19 Unmask */
-#define BITP_PINT_MSK_SET_PIQ18              18                               /* Pin Interrupt 18 Unmask */
-#define BITP_PINT_MSK_SET_PIQ17              17                               /* Pin Interrupt 17 Unmask */
-#define BITP_PINT_MSK_SET_PIQ16              16                               /* Pin Interrupt 16 Unmask */
-#define BITP_PINT_MSK_SET_PIQ15              15                               /* Pin Interrupt 15 Unmask */
-#define BITP_PINT_MSK_SET_PIQ14              14                               /* Pin Interrupt 14 Unmask */
-#define BITP_PINT_MSK_SET_PIQ13              13                               /* Pin Interrupt 13 Unmask */
-#define BITP_PINT_MSK_SET_PIQ12              12                               /* Pin Interrupt 12 Unmask */
-#define BITP_PINT_MSK_SET_PIQ11              11                               /* Pin Interrupt 11 Unmask */
-#define BITP_PINT_MSK_SET_PIQ10              10                               /* Pin Interrupt 10 Unmask */
-#define BITP_PINT_MSK_SET_PIQ9                9                               /* Pin Interrupt 9 Unmask */
-#define BITP_PINT_MSK_SET_PIQ8                8                               /* Pin Interrupt 8 Unmask */
-#define BITP_PINT_MSK_SET_PIQ7                7                               /* Pin Interrupt 7 Unmask */
-#define BITP_PINT_MSK_SET_PIQ6                6                               /* Pin Interrupt 6 Unmask */
-#define BITP_PINT_MSK_SET_PIQ5                5                               /* Pin Interrupt 5 Unmask */
-#define BITP_PINT_MSK_SET_PIQ4                4                               /* Pin Interrupt 4 Unmask */
-#define BITP_PINT_MSK_SET_PIQ3                3                               /* Pin Interrupt 3 Unmask */
-#define BITP_PINT_MSK_SET_PIQ2                2                               /* Pin Interrupt 2 Unmask */
-#define BITP_PINT_MSK_SET_PIQ1                1                               /* Pin Interrupt 1 Unmask */
-#define BITP_PINT_MSK_SET_PIQ0                0                               /* Pin Interrupt 0 Unmask */
-#define BITM_PINT_MSK_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Unmask */
-#define BITM_PINT_MSK_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Unmask */
-#define BITM_PINT_MSK_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Unmask */
-#define BITM_PINT_MSK_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Unmask */
-#define BITM_PINT_MSK_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Unmask */
-#define BITM_PINT_MSK_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Unmask */
-#define BITM_PINT_MSK_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Unmask */
-#define BITM_PINT_MSK_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Unmask */
-#define BITM_PINT_MSK_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Unmask */
-#define BITM_PINT_MSK_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Unmask */
-#define BITM_PINT_MSK_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Unmask */
-#define BITM_PINT_MSK_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Unmask */
-#define BITM_PINT_MSK_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Unmask */
-#define BITM_PINT_MSK_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Unmask */
-#define BITM_PINT_MSK_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Unmask */
-#define BITM_PINT_MSK_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Unmask */
-#define BITM_PINT_MSK_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Unmask */
-#define BITM_PINT_MSK_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Unmask */
-#define BITM_PINT_MSK_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Unmask */
-#define BITM_PINT_MSK_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Unmask */
-#define BITM_PINT_MSK_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Unmask */
-#define BITM_PINT_MSK_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Unmask */
-#define BITM_PINT_MSK_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Unmask */
-#define BITM_PINT_MSK_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Unmask */
-#define BITM_PINT_MSK_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Unmask */
-#define BITM_PINT_MSK_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Unmask */
-#define BITM_PINT_MSK_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Unmask */
-#define BITM_PINT_MSK_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Unmask */
-#define BITM_PINT_MSK_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Unmask */
-#define BITM_PINT_MSK_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Unmask */
-#define BITM_PINT_MSK_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Unmask */
-#define BITM_PINT_MSK_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_CLR_PIQ31              31                               /* Pin Interrupt 31 Mask */
-#define BITP_PINT_MSK_CLR_PIQ30              30                               /* Pin Interrupt 30 Mask */
-#define BITP_PINT_MSK_CLR_PIQ29              29                               /* Pin Interrupt 29 Mask */
-#define BITP_PINT_MSK_CLR_PIQ28              28                               /* Pin Interrupt 28 Mask */
-#define BITP_PINT_MSK_CLR_PIQ27              27                               /* Pin Interrupt 27 Mask */
-#define BITP_PINT_MSK_CLR_PIQ26              26                               /* Pin Interrupt 26 Mask */
-#define BITP_PINT_MSK_CLR_PIQ25              25                               /* Pin Interrupt 25 Mask */
-#define BITP_PINT_MSK_CLR_PIQ24              24                               /* Pin Interrupt 24 Mask */
-#define BITP_PINT_MSK_CLR_PIQ23              23                               /* Pin Interrupt 23 Mask */
-#define BITP_PINT_MSK_CLR_PIQ22              22                               /* Pin Interrupt 22 Mask */
-#define BITP_PINT_MSK_CLR_PIQ21              21                               /* Pin Interrupt 21 Mask */
-#define BITP_PINT_MSK_CLR_PIQ20              20                               /* Pin Interrupt 20 Mask */
-#define BITP_PINT_MSK_CLR_PIQ19              19                               /* Pin Interrupt 19 Mask */
-#define BITP_PINT_MSK_CLR_PIQ18              18                               /* Pin Interrupt 18 Mask */
-#define BITP_PINT_MSK_CLR_PIQ17              17                               /* Pin Interrupt 17 Mask */
-#define BITP_PINT_MSK_CLR_PIQ16              16                               /* Pin Interrupt 16 Mask */
-#define BITP_PINT_MSK_CLR_PIQ15              15                               /* Pin Interrupt 15 Mask */
-#define BITP_PINT_MSK_CLR_PIQ14              14                               /* Pin Interrupt 14 Mask */
-#define BITP_PINT_MSK_CLR_PIQ13              13                               /* Pin Interrupt 13 Mask */
-#define BITP_PINT_MSK_CLR_PIQ12              12                               /* Pin Interrupt 12 Mask */
-#define BITP_PINT_MSK_CLR_PIQ11              11                               /* Pin Interrupt 11 Mask */
-#define BITP_PINT_MSK_CLR_PIQ10              10                               /* Pin Interrupt 10 Mask */
-#define BITP_PINT_MSK_CLR_PIQ9                9                               /* Pin Interrupt 9 Mask */
-#define BITP_PINT_MSK_CLR_PIQ8                8                               /* Pin Interrupt 8 Mask */
-#define BITP_PINT_MSK_CLR_PIQ7                7                               /* Pin Interrupt 7 Mask */
-#define BITP_PINT_MSK_CLR_PIQ6                6                               /* Pin Interrupt 6 Mask */
-#define BITP_PINT_MSK_CLR_PIQ5                5                               /* Pin Interrupt 5 Mask */
-#define BITP_PINT_MSK_CLR_PIQ4                4                               /* Pin Interrupt 4 Mask */
-#define BITP_PINT_MSK_CLR_PIQ3                3                               /* Pin Interrupt 3 Mask */
-#define BITP_PINT_MSK_CLR_PIQ2                2                               /* Pin Interrupt 2 Mask */
-#define BITP_PINT_MSK_CLR_PIQ1                1                               /* Pin Interrupt 1 Mask */
-#define BITP_PINT_MSK_CLR_PIQ0                0                               /* Pin Interrupt 0 Mask */
-#define BITM_PINT_MSK_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Mask */
-#define BITM_PINT_MSK_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Mask */
-#define BITM_PINT_MSK_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Mask */
-#define BITM_PINT_MSK_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Mask */
-#define BITM_PINT_MSK_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Mask */
-#define BITM_PINT_MSK_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Mask */
-#define BITM_PINT_MSK_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Mask */
-#define BITM_PINT_MSK_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Mask */
-#define BITM_PINT_MSK_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Mask */
-#define BITM_PINT_MSK_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Mask */
-#define BITM_PINT_MSK_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Mask */
-#define BITM_PINT_MSK_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Mask */
-#define BITM_PINT_MSK_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Mask */
-#define BITM_PINT_MSK_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Mask */
-#define BITM_PINT_MSK_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Mask */
-#define BITM_PINT_MSK_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Mask */
-#define BITM_PINT_MSK_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Mask */
-#define BITM_PINT_MSK_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Mask */
-#define BITM_PINT_MSK_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Mask */
-#define BITM_PINT_MSK_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Mask */
-#define BITM_PINT_MSK_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Mask */
-#define BITM_PINT_MSK_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Mask */
-#define BITM_PINT_MSK_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Mask */
-#define BITM_PINT_MSK_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Mask */
-#define BITM_PINT_MSK_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Mask */
-#define BITM_PINT_MSK_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Mask */
-#define BITM_PINT_MSK_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Mask */
-#define BITM_PINT_MSK_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Mask */
-#define BITM_PINT_MSK_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Mask */
-#define BITM_PINT_MSK_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Mask */
-#define BITM_PINT_MSK_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Mask */
-#define BITM_PINT_MSK_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_REQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_REQ_PIQ31                  31                               /* Pin Interrupt 31 Request */
-#define BITP_PINT_REQ_PIQ30                  30                               /* Pin Interrupt 30 Request */
-#define BITP_PINT_REQ_PIQ29                  29                               /* Pin Interrupt 29 Request */
-#define BITP_PINT_REQ_PIQ28                  28                               /* Pin Interrupt 28 Request */
-#define BITP_PINT_REQ_PIQ27                  27                               /* Pin Interrupt 27 Request */
-#define BITP_PINT_REQ_PIQ26                  26                               /* Pin Interrupt 26 Request */
-#define BITP_PINT_REQ_PIQ25                  25                               /* Pin Interrupt 25 Request */
-#define BITP_PINT_REQ_PIQ24                  24                               /* Pin Interrupt 24 Request */
-#define BITP_PINT_REQ_PIQ23                  23                               /* Pin Interrupt 23 Request */
-#define BITP_PINT_REQ_PIQ22                  22                               /* Pin Interrupt 22 Request */
-#define BITP_PINT_REQ_PIQ21                  21                               /* Pin Interrupt 21 Request */
-#define BITP_PINT_REQ_PIQ20                  20                               /* Pin Interrupt 20 Request */
-#define BITP_PINT_REQ_PIQ19                  19                               /* Pin Interrupt 19 Request */
-#define BITP_PINT_REQ_PIQ18                  18                               /* Pin Interrupt 18 Request */
-#define BITP_PINT_REQ_PIQ17                  17                               /* Pin Interrupt 17 Request */
-#define BITP_PINT_REQ_PIQ16                  16                               /* Pin Interrupt 16 Request */
-#define BITP_PINT_REQ_PIQ15                  15                               /* Pin Interrupt 15 Request */
-#define BITP_PINT_REQ_PIQ14                  14                               /* Pin Interrupt 14 Request */
-#define BITP_PINT_REQ_PIQ13                  13                               /* Pin Interrupt 13 Request */
-#define BITP_PINT_REQ_PIQ12                  12                               /* Pin Interrupt 12 Request */
-#define BITP_PINT_REQ_PIQ11                  11                               /* Pin Interrupt 11 Request */
-#define BITP_PINT_REQ_PIQ10                  10                               /* Pin Interrupt 10 Request */
-#define BITP_PINT_REQ_PIQ9                    9                               /* Pin Interrupt 9 Request */
-#define BITP_PINT_REQ_PIQ8                    8                               /* Pin Interrupt 8 Request */
-#define BITP_PINT_REQ_PIQ7                    7                               /* Pin Interrupt 7 Request */
-#define BITP_PINT_REQ_PIQ6                    6                               /* Pin Interrupt 6 Request */
-#define BITP_PINT_REQ_PIQ5                    5                               /* Pin Interrupt 5 Request */
-#define BITP_PINT_REQ_PIQ4                    4                               /* Pin Interrupt 4 Request */
-#define BITP_PINT_REQ_PIQ3                    3                               /* Pin Interrupt 3 Request */
-#define BITP_PINT_REQ_PIQ2                    2                               /* Pin Interrupt 2 Request */
-#define BITP_PINT_REQ_PIQ1                    1                               /* Pin Interrupt 1 Request */
-#define BITP_PINT_REQ_PIQ0                    0                               /* Pin Interrupt 0 Request */
-#define BITM_PINT_REQ_PIQ31                  (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Request */
-#define BITM_PINT_REQ_PIQ30                  (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Request */
-#define BITM_PINT_REQ_PIQ29                  (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Request */
-#define BITM_PINT_REQ_PIQ28                  (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Request */
-#define BITM_PINT_REQ_PIQ27                  (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Request */
-#define BITM_PINT_REQ_PIQ26                  (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Request */
-#define BITM_PINT_REQ_PIQ25                  (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Request */
-#define BITM_PINT_REQ_PIQ24                  (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Request */
-#define BITM_PINT_REQ_PIQ23                  (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Request */
-#define BITM_PINT_REQ_PIQ22                  (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Request */
-#define BITM_PINT_REQ_PIQ21                  (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Request */
-#define BITM_PINT_REQ_PIQ20                  (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Request */
-#define BITM_PINT_REQ_PIQ19                  (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Request */
-#define BITM_PINT_REQ_PIQ18                  (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Request */
-#define BITM_PINT_REQ_PIQ17                  (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Request */
-#define BITM_PINT_REQ_PIQ16                  (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Request */
-#define BITM_PINT_REQ_PIQ15                  (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Request */
-#define BITM_PINT_REQ_PIQ14                  (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Request */
-#define BITM_PINT_REQ_PIQ13                  (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Request */
-#define BITM_PINT_REQ_PIQ12                  (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Request */
-#define BITM_PINT_REQ_PIQ11                  (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Request */
-#define BITM_PINT_REQ_PIQ10                  (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Request */
-#define BITM_PINT_REQ_PIQ9                   (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Request */
-#define BITM_PINT_REQ_PIQ8                   (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Request */
-#define BITM_PINT_REQ_PIQ7                   (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Request */
-#define BITM_PINT_REQ_PIQ6                   (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Request */
-#define BITM_PINT_REQ_PIQ5                   (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Request */
-#define BITM_PINT_REQ_PIQ4                   (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Request */
-#define BITM_PINT_REQ_PIQ3                   (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Request */
-#define BITM_PINT_REQ_PIQ2                   (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Request */
-#define BITM_PINT_REQ_PIQ1                   (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Request */
-#define BITM_PINT_REQ_PIQ0                   (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_ASSIGN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_ASSIGN_B3MAP               24                               /* Byte 3 Mapping */
-#define BITP_PINT_ASSIGN_B2MAP               16                               /* Byte 2 Mapping */
-#define BITP_PINT_ASSIGN_B1MAP                8                               /* Byte 1 Mapping */
-#define BITP_PINT_ASSIGN_B0MAP                0                               /* Byte 0 Mapping */
-#define BITM_PINT_ASSIGN_B3MAP               (_ADI_MSK(0xFF000000,uint32_t))  /* Byte 3 Mapping */
-#define BITM_PINT_ASSIGN_B2MAP               (_ADI_MSK(0x00FF0000,uint32_t))  /* Byte 2 Mapping */
-#define BITM_PINT_ASSIGN_B1MAP               (_ADI_MSK(0x0000FF00,uint32_t))  /* Byte 1 Mapping */
-#define BITM_PINT_ASSIGN_B0MAP               (_ADI_MSK(0x000000FF,uint32_t))  /* Byte 0 Mapping */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_SET_PIQ31             31                               /* Pin Interrupt 31 Edge */
-#define BITP_PINT_EDGE_SET_PIQ30             30                               /* Pin Interrupt 30 Edge */
-#define BITP_PINT_EDGE_SET_PIQ29             29                               /* Pin Interrupt 29 Edge */
-#define BITP_PINT_EDGE_SET_PIQ28             28                               /* Pin Interrupt 28 Edge */
-#define BITP_PINT_EDGE_SET_PIQ27             27                               /* Pin Interrupt 27 Edge */
-#define BITP_PINT_EDGE_SET_PIQ26             26                               /* Pin Interrupt 26 Edge */
-#define BITP_PINT_EDGE_SET_PIQ25             25                               /* Pin Interrupt 25 Edge */
-#define BITP_PINT_EDGE_SET_PIQ24             24                               /* Pin Interrupt 24 Edge */
-#define BITP_PINT_EDGE_SET_PIQ23             23                               /* Pin Interrupt 23 Edge */
-#define BITP_PINT_EDGE_SET_PIQ22             22                               /* Pin Interrupt 22 Edge */
-#define BITP_PINT_EDGE_SET_PIQ21             21                               /* Pin Interrupt 21 Edge */
-#define BITP_PINT_EDGE_SET_PIQ20             20                               /* Pin Interrupt 20 Edge */
-#define BITP_PINT_EDGE_SET_PIQ19             19                               /* Pin Interrupt 19 Edge */
-#define BITP_PINT_EDGE_SET_PIQ18             18                               /* Pin Interrupt 18 Edge */
-#define BITP_PINT_EDGE_SET_PIQ17             17                               /* Pin Interrupt 17 Edge */
-#define BITP_PINT_EDGE_SET_PIQ16             16                               /* Pin Interrupt 16 Edge */
-#define BITP_PINT_EDGE_SET_PIQ15             15                               /* Pin Interrupt 15 Edge */
-#define BITP_PINT_EDGE_SET_PIQ14             14                               /* Pin Interrupt 14 Edge */
-#define BITP_PINT_EDGE_SET_PIQ13             13                               /* Pin Interrupt 13 Edge */
-#define BITP_PINT_EDGE_SET_PIQ12             12                               /* Pin Interrupt 12 Edge */
-#define BITP_PINT_EDGE_SET_PIQ11             11                               /* Pin Interrupt 11 Edge */
-#define BITP_PINT_EDGE_SET_PIQ10             10                               /* Pin Interrupt 10 Edge */
-#define BITP_PINT_EDGE_SET_PIQ9               9                               /* Pin Interrupt 9 Edge */
-#define BITP_PINT_EDGE_SET_PIQ8               8                               /* Pin Interrupt 8 Edge */
-#define BITP_PINT_EDGE_SET_PIQ7               7                               /* Pin Interrupt 7 Edge */
-#define BITP_PINT_EDGE_SET_PIQ6               6                               /* Pin Interrupt 6 Edge */
-#define BITP_PINT_EDGE_SET_PIQ5               5                               /* Pin Interrupt 5 Edge */
-#define BITP_PINT_EDGE_SET_PIQ4               4                               /* Pin Interrupt 4 Edge */
-#define BITP_PINT_EDGE_SET_PIQ3               3                               /* Pin Interrupt 3 Edge */
-#define BITP_PINT_EDGE_SET_PIQ2               2                               /* Pin Interrupt 2 Edge */
-#define BITP_PINT_EDGE_SET_PIQ1               1                               /* Pin Interrupt 1 Edge */
-#define BITP_PINT_EDGE_SET_PIQ0               0                               /* Pin Interrupt 0 Edge */
-#define BITM_PINT_EDGE_SET_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Edge */
-#define BITM_PINT_EDGE_SET_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Edge */
-#define BITM_PINT_EDGE_SET_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Edge */
-#define BITM_PINT_EDGE_SET_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Edge */
-#define BITM_PINT_EDGE_SET_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Edge */
-#define BITM_PINT_EDGE_SET_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Edge */
-#define BITM_PINT_EDGE_SET_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Edge */
-#define BITM_PINT_EDGE_SET_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Edge */
-#define BITM_PINT_EDGE_SET_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Edge */
-#define BITM_PINT_EDGE_SET_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Edge */
-#define BITM_PINT_EDGE_SET_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Edge */
-#define BITM_PINT_EDGE_SET_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Edge */
-#define BITM_PINT_EDGE_SET_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Edge */
-#define BITM_PINT_EDGE_SET_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Edge */
-#define BITM_PINT_EDGE_SET_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Edge */
-#define BITM_PINT_EDGE_SET_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Edge */
-#define BITM_PINT_EDGE_SET_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Edge */
-#define BITM_PINT_EDGE_SET_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Edge */
-#define BITM_PINT_EDGE_SET_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Edge */
-#define BITM_PINT_EDGE_SET_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Edge */
-#define BITM_PINT_EDGE_SET_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Edge */
-#define BITM_PINT_EDGE_SET_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Edge */
-#define BITM_PINT_EDGE_SET_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Edge */
-#define BITM_PINT_EDGE_SET_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Edge */
-#define BITM_PINT_EDGE_SET_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Edge */
-#define BITM_PINT_EDGE_SET_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Edge */
-#define BITM_PINT_EDGE_SET_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Edge */
-#define BITM_PINT_EDGE_SET_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Edge */
-#define BITM_PINT_EDGE_SET_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Edge */
-#define BITM_PINT_EDGE_SET_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Edge */
-#define BITM_PINT_EDGE_SET_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Edge */
-#define BITM_PINT_EDGE_SET_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Edge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_CLR_PIQ31             31                               /* Pin Interrupt 31 Level */
-#define BITP_PINT_EDGE_CLR_PIQ30             30                               /* Pin Interrupt 30 Level */
-#define BITP_PINT_EDGE_CLR_PIQ29             29                               /* Pin Interrupt 29 Level */
-#define BITP_PINT_EDGE_CLR_PIQ28             28                               /* Pin Interrupt 28 Level */
-#define BITP_PINT_EDGE_CLR_PIQ27             27                               /* Pin Interrupt 27 Level */
-#define BITP_PINT_EDGE_CLR_PIQ26             26                               /* Pin Interrupt 26 Level */
-#define BITP_PINT_EDGE_CLR_PIQ25             25                               /* Pin Interrupt 25 Level */
-#define BITP_PINT_EDGE_CLR_PIQ24             24                               /* Pin Interrupt 24 Level */
-#define BITP_PINT_EDGE_CLR_PIQ23             23                               /* Pin Interrupt 23 Level */
-#define BITP_PINT_EDGE_CLR_PIQ22             22                               /* Pin Interrupt 22 Level */
-#define BITP_PINT_EDGE_CLR_PIQ21             21                               /* Pin Interrupt 21 Level */
-#define BITP_PINT_EDGE_CLR_PIQ20             20                               /* Pin Interrupt 20 Level */
-#define BITP_PINT_EDGE_CLR_PIQ19             19                               /* Pin Interrupt 19 Level */
-#define BITP_PINT_EDGE_CLR_PIQ18             18                               /* Pin Interrupt 18 Level */
-#define BITP_PINT_EDGE_CLR_PIQ17             17                               /* Pin Interrupt 17 Level */
-#define BITP_PINT_EDGE_CLR_PIQ16             16                               /* Pin Interrupt 16 Level */
-#define BITP_PINT_EDGE_CLR_PIQ15             15                               /* Pin Interrupt 15 Level */
-#define BITP_PINT_EDGE_CLR_PIQ14             14                               /* Pin Interrupt 14 Level */
-#define BITP_PINT_EDGE_CLR_PIQ13             13                               /* Pin Interrupt 13 Level */
-#define BITP_PINT_EDGE_CLR_PIQ12             12                               /* Pin Interrupt 12 Level */
-#define BITP_PINT_EDGE_CLR_PIQ11             11                               /* Pin Interrupt 11 Level */
-#define BITP_PINT_EDGE_CLR_PIQ10             10                               /* Pin Interrupt 10 Level */
-#define BITP_PINT_EDGE_CLR_PIQ9               9                               /* Pin Interrupt 9 Level */
-#define BITP_PINT_EDGE_CLR_PIQ8               8                               /* Pin Interrupt 8 Level */
-#define BITP_PINT_EDGE_CLR_PIQ7               7                               /* Pin Interrupt 7 Level */
-#define BITP_PINT_EDGE_CLR_PIQ6               6                               /* Pin Interrupt 6 Level */
-#define BITP_PINT_EDGE_CLR_PIQ5               5                               /* Pin Interrupt 5 Level */
-#define BITP_PINT_EDGE_CLR_PIQ4               4                               /* Pin Interrupt 4 Level */
-#define BITP_PINT_EDGE_CLR_PIQ3               3                               /* Pin Interrupt 3 Level */
-#define BITP_PINT_EDGE_CLR_PIQ2               2                               /* Pin Interrupt 2 Level */
-#define BITP_PINT_EDGE_CLR_PIQ1               1                               /* Pin Interrupt 1 Level */
-#define BITP_PINT_EDGE_CLR_PIQ0               0                               /* Pin Interrupt 0 Level */
-#define BITM_PINT_EDGE_CLR_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Level */
-#define BITM_PINT_EDGE_CLR_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Level */
-#define BITM_PINT_EDGE_CLR_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Level */
-#define BITM_PINT_EDGE_CLR_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Level */
-#define BITM_PINT_EDGE_CLR_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Level */
-#define BITM_PINT_EDGE_CLR_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Level */
-#define BITM_PINT_EDGE_CLR_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Level */
-#define BITM_PINT_EDGE_CLR_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Level */
-#define BITM_PINT_EDGE_CLR_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Level */
-#define BITM_PINT_EDGE_CLR_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Level */
-#define BITM_PINT_EDGE_CLR_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Level */
-#define BITM_PINT_EDGE_CLR_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Level */
-#define BITM_PINT_EDGE_CLR_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Level */
-#define BITM_PINT_EDGE_CLR_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Level */
-#define BITM_PINT_EDGE_CLR_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Level */
-#define BITM_PINT_EDGE_CLR_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Level */
-#define BITM_PINT_EDGE_CLR_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Level */
-#define BITM_PINT_EDGE_CLR_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Level */
-#define BITM_PINT_EDGE_CLR_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Level */
-#define BITM_PINT_EDGE_CLR_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Level */
-#define BITM_PINT_EDGE_CLR_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Level */
-#define BITM_PINT_EDGE_CLR_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Level */
-#define BITM_PINT_EDGE_CLR_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Level */
-#define BITM_PINT_EDGE_CLR_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Level */
-#define BITM_PINT_EDGE_CLR_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Level */
-#define BITM_PINT_EDGE_CLR_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Level */
-#define BITM_PINT_EDGE_CLR_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Level */
-#define BITM_PINT_EDGE_CLR_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Level */
-#define BITM_PINT_EDGE_CLR_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Level */
-#define BITM_PINT_EDGE_CLR_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Level */
-#define BITM_PINT_EDGE_CLR_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Level */
-#define BITM_PINT_EDGE_CLR_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Level */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_SET_PIQ31              31                               /* Pin Interrupt 31 Invert */
-#define BITP_PINT_INV_SET_PIQ30              30                               /* Pin Interrupt 30 Invert */
-#define BITP_PINT_INV_SET_PIQ29              29                               /* Pin Interrupt 29 Invert */
-#define BITP_PINT_INV_SET_PIQ28              28                               /* Pin Interrupt 28 Invert */
-#define BITP_PINT_INV_SET_PIQ27              27                               /* Pin Interrupt 27 Invert */
-#define BITP_PINT_INV_SET_PIQ26              26                               /* Pin Interrupt 26 Invert */
-#define BITP_PINT_INV_SET_PIQ25              25                               /* Pin Interrupt 25 Invert */
-#define BITP_PINT_INV_SET_PIQ24              24                               /* Pin Interrupt 24 Invert */
-#define BITP_PINT_INV_SET_PIQ23              23                               /* Pin Interrupt 23 Invert */
-#define BITP_PINT_INV_SET_PIQ22              22                               /* Pin Interrupt 22 Invert */
-#define BITP_PINT_INV_SET_PIQ21              21                               /* Pin Interrupt 21 Invert */
-#define BITP_PINT_INV_SET_PIQ20              20                               /* Pin Interrupt 20 Invert */
-#define BITP_PINT_INV_SET_PIQ19              19                               /* Pin Interrupt 19 Invert */
-#define BITP_PINT_INV_SET_PIQ18              18                               /* Pin Interrupt 18 Invert */
-#define BITP_PINT_INV_SET_PIQ17              17                               /* Pin Interrupt 17 Invert */
-#define BITP_PINT_INV_SET_PIQ16              16                               /* Pin Interrupt 16 Invert */
-#define BITP_PINT_INV_SET_PIQ15              15                               /* Pin Interrupt 15 Invert */
-#define BITP_PINT_INV_SET_PIQ14              14                               /* Pin Interrupt 14 Invert */
-#define BITP_PINT_INV_SET_PIQ13              13                               /* Pin Interrupt 13 Invert */
-#define BITP_PINT_INV_SET_PIQ12              12                               /* Pin Interrupt 12 Invert */
-#define BITP_PINT_INV_SET_PIQ11              11                               /* Pin Interrupt 11 Invert */
-#define BITP_PINT_INV_SET_PIQ10              10                               /* Pin Interrupt 10 Invert */
-#define BITP_PINT_INV_SET_PIQ9                9                               /* Pin Interrupt 9 Invert */
-#define BITP_PINT_INV_SET_PIQ8                8                               /* Pin Interrupt 8 Invert */
-#define BITP_PINT_INV_SET_PIQ7                7                               /* Pin Interrupt 7 Invert */
-#define BITP_PINT_INV_SET_PIQ6                6                               /* Pin Interrupt 6 Invert */
-#define BITP_PINT_INV_SET_PIQ5                5                               /* Pin Interrupt 5 Invert */
-#define BITP_PINT_INV_SET_PIQ4                4                               /* Pin Interrupt 4 Invert */
-#define BITP_PINT_INV_SET_PIQ3                3                               /* Pin Interrupt 3 Invert */
-#define BITP_PINT_INV_SET_PIQ2                2                               /* Pin Interrupt 2 Invert */
-#define BITP_PINT_INV_SET_PIQ1                1                               /* Pin Interrupt 1 Invert */
-#define BITP_PINT_INV_SET_PIQ0                0                               /* Pin Interrupt 0 Invert */
-#define BITM_PINT_INV_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Invert */
-#define BITM_PINT_INV_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Invert */
-#define BITM_PINT_INV_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Invert */
-#define BITM_PINT_INV_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Invert */
-#define BITM_PINT_INV_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Invert */
-#define BITM_PINT_INV_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Invert */
-#define BITM_PINT_INV_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Invert */
-#define BITM_PINT_INV_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Invert */
-#define BITM_PINT_INV_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Invert */
-#define BITM_PINT_INV_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Invert */
-#define BITM_PINT_INV_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Invert */
-#define BITM_PINT_INV_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Invert */
-#define BITM_PINT_INV_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Invert */
-#define BITM_PINT_INV_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Invert */
-#define BITM_PINT_INV_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Invert */
-#define BITM_PINT_INV_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Invert */
-#define BITM_PINT_INV_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Invert */
-#define BITM_PINT_INV_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Invert */
-#define BITM_PINT_INV_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Invert */
-#define BITM_PINT_INV_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Invert */
-#define BITM_PINT_INV_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Invert */
-#define BITM_PINT_INV_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Invert */
-#define BITM_PINT_INV_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Invert */
-#define BITM_PINT_INV_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Invert */
-#define BITM_PINT_INV_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Invert */
-#define BITM_PINT_INV_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Invert */
-#define BITM_PINT_INV_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Invert */
-#define BITM_PINT_INV_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Invert */
-#define BITM_PINT_INV_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Invert */
-#define BITM_PINT_INV_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Invert */
-#define BITM_PINT_INV_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Invert */
-#define BITM_PINT_INV_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_CLR_PIQ31              31                               /* Pin Interrupt 31 No Invert */
-#define BITP_PINT_INV_CLR_PIQ30              30                               /* Pin Interrupt 30 No Invert */
-#define BITP_PINT_INV_CLR_PIQ29              29                               /* Pin Interrupt 29 No Invert */
-#define BITP_PINT_INV_CLR_PIQ28              28                               /* Pin Interrupt 28 No Invert */
-#define BITP_PINT_INV_CLR_PIQ27              27                               /* Pin Interrupt 27 No Invert */
-#define BITP_PINT_INV_CLR_PIQ26              26                               /* Pin Interrupt 26 No Invert */
-#define BITP_PINT_INV_CLR_PIQ25              25                               /* Pin Interrupt 25 No Invert */
-#define BITP_PINT_INV_CLR_PIQ24              24                               /* Pin Interrupt 24 No Invert */
-#define BITP_PINT_INV_CLR_PIQ23              23                               /* Pin Interrupt 23 No Invert */
-#define BITP_PINT_INV_CLR_PIQ22              22                               /* Pin Interrupt 22 No Invert */
-#define BITP_PINT_INV_CLR_PIQ21              21                               /* Pin Interrupt 21 No Invert */
-#define BITP_PINT_INV_CLR_PIQ20              20                               /* Pin Interrupt 20 No Invert */
-#define BITP_PINT_INV_CLR_PIQ19              19                               /* Pin Interrupt 19 No Invert */
-#define BITP_PINT_INV_CLR_PIQ18              18                               /* Pin Interrupt 18 No Invert */
-#define BITP_PINT_INV_CLR_PIQ17              17                               /* Pin Interrupt 17 No Invert */
-#define BITP_PINT_INV_CLR_PIQ16              16                               /* Pin Interrupt 16 No Invert */
-#define BITP_PINT_INV_CLR_PIQ15              15                               /* Pin Interrupt 15 No Invert */
-#define BITP_PINT_INV_CLR_PIQ14              14                               /* Pin Interrupt 14 No Invert */
-#define BITP_PINT_INV_CLR_PIQ13              13                               /* Pin Interrupt 13 No Invert */
-#define BITP_PINT_INV_CLR_PIQ12              12                               /* Pin Interrupt 12 No Invert */
-#define BITP_PINT_INV_CLR_PIQ11              11                               /* Pin Interrupt 11 No Invert */
-#define BITP_PINT_INV_CLR_PIQ10              10                               /* Pin Interrupt 10 No Invert */
-#define BITP_PINT_INV_CLR_PIQ9                9                               /* Pin Interrupt 9 No Invert */
-#define BITP_PINT_INV_CLR_PIQ8                8                               /* Pin Interrupt 8 No Invert */
-#define BITP_PINT_INV_CLR_PIQ7                7                               /* Pin Interrupt 7 No Invert */
-#define BITP_PINT_INV_CLR_PIQ6                6                               /* Pin Interrupt 6 No Invert */
-#define BITP_PINT_INV_CLR_PIQ5                5                               /* Pin Interrupt 5 No Invert */
-#define BITP_PINT_INV_CLR_PIQ4                4                               /* Pin Interrupt 4 No Invert */
-#define BITP_PINT_INV_CLR_PIQ3                3                               /* Pin Interrupt 3 No Invert */
-#define BITP_PINT_INV_CLR_PIQ2                2                               /* Pin Interrupt 2 No Invert */
-#define BITP_PINT_INV_CLR_PIQ1                1                               /* Pin Interrupt 1 No Invert */
-#define BITP_PINT_INV_CLR_PIQ0                0                               /* Pin Interrupt 0 No Invert */
-#define BITM_PINT_INV_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 No Invert */
-#define BITM_PINT_INV_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 No Invert */
-#define BITM_PINT_INV_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 No Invert */
-#define BITM_PINT_INV_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 No Invert */
-#define BITM_PINT_INV_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 No Invert */
-#define BITM_PINT_INV_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 No Invert */
-#define BITM_PINT_INV_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 No Invert */
-#define BITM_PINT_INV_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 No Invert */
-#define BITM_PINT_INV_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 No Invert */
-#define BITM_PINT_INV_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 No Invert */
-#define BITM_PINT_INV_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 No Invert */
-#define BITM_PINT_INV_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 No Invert */
-#define BITM_PINT_INV_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 No Invert */
-#define BITM_PINT_INV_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 No Invert */
-#define BITM_PINT_INV_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 No Invert */
-#define BITM_PINT_INV_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 No Invert */
-#define BITM_PINT_INV_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 No Invert */
-#define BITM_PINT_INV_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 No Invert */
-#define BITM_PINT_INV_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 No Invert */
-#define BITM_PINT_INV_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 No Invert */
-#define BITM_PINT_INV_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 No Invert */
-#define BITM_PINT_INV_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 No Invert */
-#define BITM_PINT_INV_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 No Invert */
-#define BITM_PINT_INV_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 No Invert */
-#define BITM_PINT_INV_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 No Invert */
-#define BITM_PINT_INV_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 No Invert */
-#define BITM_PINT_INV_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 No Invert */
-#define BITM_PINT_INV_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 No Invert */
-#define BITM_PINT_INV_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 No Invert */
-#define BITM_PINT_INV_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 No Invert */
-#define BITM_PINT_INV_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 No Invert */
-#define BITM_PINT_INV_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 No Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_PINSTATE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_PINSTATE_PIQ31             31                               /* Pin Interrupt 31 State */
-#define BITP_PINT_PINSTATE_PIQ30             30                               /* Pin Interrupt 30 State */
-#define BITP_PINT_PINSTATE_PIQ29             29                               /* Pin Interrupt 29 State */
-#define BITP_PINT_PINSTATE_PIQ28             28                               /* Pin Interrupt 28 State */
-#define BITP_PINT_PINSTATE_PIQ27             27                               /* Pin Interrupt 27 State */
-#define BITP_PINT_PINSTATE_PIQ26             26                               /* Pin Interrupt 26 State */
-#define BITP_PINT_PINSTATE_PIQ25             25                               /* Pin Interrupt 25 State */
-#define BITP_PINT_PINSTATE_PIQ24             24                               /* Pin Interrupt 24 State */
-#define BITP_PINT_PINSTATE_PIQ23             23                               /* Pin Interrupt 23 State */
-#define BITP_PINT_PINSTATE_PIQ22             22                               /* Pin Interrupt 22 State */
-#define BITP_PINT_PINSTATE_PIQ21             21                               /* Pin Interrupt 21 State */
-#define BITP_PINT_PINSTATE_PIQ20             20                               /* Pin Interrupt 20 State */
-#define BITP_PINT_PINSTATE_PIQ19             19                               /* Pin Interrupt 19 State */
-#define BITP_PINT_PINSTATE_PIQ18             18                               /* Pin Interrupt 18 State */
-#define BITP_PINT_PINSTATE_PIQ17             17                               /* Pin Interrupt 17 State */
-#define BITP_PINT_PINSTATE_PIQ16             16                               /* Pin Interrupt 16 State */
-#define BITP_PINT_PINSTATE_PIQ15             15                               /* Pin Interrupt 15 State */
-#define BITP_PINT_PINSTATE_PIQ14             14                               /* Pin Interrupt 14 State */
-#define BITP_PINT_PINSTATE_PIQ13             13                               /* Pin Interrupt 13 State */
-#define BITP_PINT_PINSTATE_PIQ12             12                               /* Pin Interrupt 12 State */
-#define BITP_PINT_PINSTATE_PIQ11             11                               /* Pin Interrupt 11 State */
-#define BITP_PINT_PINSTATE_PIQ10             10                               /* Pin Interrupt 10 State */
-#define BITP_PINT_PINSTATE_PIQ9               9                               /* Pin Interrupt 9 State */
-#define BITP_PINT_PINSTATE_PIQ8               8                               /* Pin Interrupt 8 State */
-#define BITP_PINT_PINSTATE_PIQ7               7                               /* Pin Interrupt 7 State */
-#define BITP_PINT_PINSTATE_PIQ6               6                               /* Pin Interrupt 6 State */
-#define BITP_PINT_PINSTATE_PIQ5               5                               /* Pin Interrupt 5 State */
-#define BITP_PINT_PINSTATE_PIQ4               4                               /* Pin Interrupt 4 State */
-#define BITP_PINT_PINSTATE_PIQ3               3                               /* Pin Interrupt 3 State */
-#define BITP_PINT_PINSTATE_PIQ2               2                               /* Pin Interrupt 2 State */
-#define BITP_PINT_PINSTATE_PIQ1               1                               /* Pin Interrupt 1 State */
-#define BITP_PINT_PINSTATE_PIQ0               0                               /* Pin Interrupt 0 State */
-#define BITM_PINT_PINSTATE_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 State */
-#define BITM_PINT_PINSTATE_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 State */
-#define BITM_PINT_PINSTATE_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 State */
-#define BITM_PINT_PINSTATE_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 State */
-#define BITM_PINT_PINSTATE_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 State */
-#define BITM_PINT_PINSTATE_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 State */
-#define BITM_PINT_PINSTATE_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 State */
-#define BITM_PINT_PINSTATE_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 State */
-#define BITM_PINT_PINSTATE_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 State */
-#define BITM_PINT_PINSTATE_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 State */
-#define BITM_PINT_PINSTATE_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 State */
-#define BITM_PINT_PINSTATE_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 State */
-#define BITM_PINT_PINSTATE_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 State */
-#define BITM_PINT_PINSTATE_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 State */
-#define BITM_PINT_PINSTATE_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 State */
-#define BITM_PINT_PINSTATE_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 State */
-#define BITM_PINT_PINSTATE_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 State */
-#define BITM_PINT_PINSTATE_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 State */
-#define BITM_PINT_PINSTATE_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 State */
-#define BITM_PINT_PINSTATE_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 State */
-#define BITM_PINT_PINSTATE_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 State */
-#define BITM_PINT_PINSTATE_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 State */
-#define BITM_PINT_PINSTATE_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 State */
-#define BITM_PINT_PINSTATE_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 State */
-#define BITM_PINT_PINSTATE_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 State */
-#define BITM_PINT_PINSTATE_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 State */
-#define BITM_PINT_PINSTATE_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 State */
-#define BITM_PINT_PINSTATE_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 State */
-#define BITM_PINT_PINSTATE_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 State */
-#define BITM_PINT_PINSTATE_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 State */
-#define BITM_PINT_PINSTATE_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 State */
-#define BITM_PINT_PINSTATE_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_LATCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_LATCH_PIQ31                31                               /* Pin Interrupt 31 Latch */
-#define BITP_PINT_LATCH_PIQ30                30                               /* Pin Interrupt 30 Latch */
-#define BITP_PINT_LATCH_PIQ29                29                               /* Pin Interrupt 29 Latch */
-#define BITP_PINT_LATCH_PIQ28                28                               /* Pin Interrupt 28 Latch */
-#define BITP_PINT_LATCH_PIQ27                27                               /* Pin Interrupt 27 Latch */
-#define BITP_PINT_LATCH_PIQ26                26                               /* Pin Interrupt 26 Latch */
-#define BITP_PINT_LATCH_PIQ25                25                               /* Pin Interrupt 25 Latch */
-#define BITP_PINT_LATCH_PIQ24                24                               /* Pin Interrupt 24 Latch */
-#define BITP_PINT_LATCH_PIQ23                23                               /* Pin Interrupt 23 Latch */
-#define BITP_PINT_LATCH_PIQ22                22                               /* Pin Interrupt 22 Latch */
-#define BITP_PINT_LATCH_PIQ21                21                               /* Pin Interrupt 21 Latch */
-#define BITP_PINT_LATCH_PIQ20                20                               /* Pin Interrupt 20 Latch */
-#define BITP_PINT_LATCH_PIQ19                19                               /* Pin Interrupt 19 Latch */
-#define BITP_PINT_LATCH_PIQ18                18                               /* Pin Interrupt 18 Latch */
-#define BITP_PINT_LATCH_PIQ17                17                               /* Pin Interrupt 17 Latch */
-#define BITP_PINT_LATCH_PIQ16                16                               /* Pin Interrupt 16 Latch */
-#define BITP_PINT_LATCH_PIQ15                15                               /* Pin Interrupt 15 Latch */
-#define BITP_PINT_LATCH_PIQ14                14                               /* Pin Interrupt 14 Latch */
-#define BITP_PINT_LATCH_PIQ13                13                               /* Pin Interrupt 13 Latch */
-#define BITP_PINT_LATCH_PIQ12                12                               /* Pin Interrupt 12 Latch */
-#define BITP_PINT_LATCH_PIQ11                11                               /* Pin Interrupt 11 Latch */
-#define BITP_PINT_LATCH_PIQ10                10                               /* Pin Interrupt 10 Latch */
-#define BITP_PINT_LATCH_PIQ9                  9                               /* Pin Interrupt 9 Latch */
-#define BITP_PINT_LATCH_PIQ8                  8                               /* Pin Interrupt 8 Latch */
-#define BITP_PINT_LATCH_PIQ7                  7                               /* Pin Interrupt 7 Latch */
-#define BITP_PINT_LATCH_PIQ6                  6                               /* Pin Interrupt 6 Latch */
-#define BITP_PINT_LATCH_PIQ5                  5                               /* Pin Interrupt 5 Latch */
-#define BITP_PINT_LATCH_PIQ4                  4                               /* Pin Interrupt 4 Latch */
-#define BITP_PINT_LATCH_PIQ3                  3                               /* Pin Interrupt 3 Latch */
-#define BITP_PINT_LATCH_PIQ2                  2                               /* Pin Interrupt 2 Latch */
-#define BITP_PINT_LATCH_PIQ1                  1                               /* Pin Interrupt 1 Latch */
-#define BITP_PINT_LATCH_PIQ0                  0                               /* Pin Interrupt 0 Latch */
-#define BITM_PINT_LATCH_PIQ31                (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Latch */
-#define BITM_PINT_LATCH_PIQ30                (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Latch */
-#define BITM_PINT_LATCH_PIQ29                (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Latch */
-#define BITM_PINT_LATCH_PIQ28                (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Latch */
-#define BITM_PINT_LATCH_PIQ27                (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Latch */
-#define BITM_PINT_LATCH_PIQ26                (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Latch */
-#define BITM_PINT_LATCH_PIQ25                (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Latch */
-#define BITM_PINT_LATCH_PIQ24                (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Latch */
-#define BITM_PINT_LATCH_PIQ23                (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Latch */
-#define BITM_PINT_LATCH_PIQ22                (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Latch */
-#define BITM_PINT_LATCH_PIQ21                (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Latch */
-#define BITM_PINT_LATCH_PIQ20                (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Latch */
-#define BITM_PINT_LATCH_PIQ19                (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Latch */
-#define BITM_PINT_LATCH_PIQ18                (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Latch */
-#define BITM_PINT_LATCH_PIQ17                (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Latch */
-#define BITM_PINT_LATCH_PIQ16                (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Latch */
-#define BITM_PINT_LATCH_PIQ15                (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Latch */
-#define BITM_PINT_LATCH_PIQ14                (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Latch */
-#define BITM_PINT_LATCH_PIQ13                (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Latch */
-#define BITM_PINT_LATCH_PIQ12                (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Latch */
-#define BITM_PINT_LATCH_PIQ11                (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Latch */
-#define BITM_PINT_LATCH_PIQ10                (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Latch */
-#define BITM_PINT_LATCH_PIQ9                 (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Latch */
-#define BITM_PINT_LATCH_PIQ8                 (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Latch */
-#define BITM_PINT_LATCH_PIQ7                 (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Latch */
-#define BITM_PINT_LATCH_PIQ6                 (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Latch */
-#define BITM_PINT_LATCH_PIQ5                 (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Latch */
-#define BITM_PINT_LATCH_PIQ4                 (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Latch */
-#define BITM_PINT_LATCH_PIQ3                 (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Latch */
-#define BITM_PINT_LATCH_PIQ2                 (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Latch */
-#define BITM_PINT_LATCH_PIQ1                 (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Latch */
-#define BITM_PINT_LATCH_PIQ0                 (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Latch */
-
-/* ==================================================
-        Static Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        SMC0
-   ========================= */
-#define REG_SMC0_GCTL                   0xFFC16004         /* SMC0 Grant Control Register */
-#define REG_SMC0_GSTAT                  0xFFC16008         /* SMC0 Grant Status Register */
-#define REG_SMC0_B0CTL                  0xFFC1600C         /* SMC0 Bank 0 Control Register */
-#define REG_SMC0_B0TIM                  0xFFC16010         /* SMC0 Bank 0 Timing Register */
-#define REG_SMC0_B0ETIM                 0xFFC16014         /* SMC0 Bank 0 Extended Timing Register */
-#define REG_SMC0_B1CTL                  0xFFC1601C         /* SMC0 Bank 1 Control Register */
-#define REG_SMC0_B1TIM                  0xFFC16020         /* SMC0 Bank 1 Timing Register */
-#define REG_SMC0_B1ETIM                 0xFFC16024         /* SMC0 Bank 1 Extended Timing Register */
-#define REG_SMC0_B2CTL                  0xFFC1602C         /* SMC0 Bank 2 Control Register */
-#define REG_SMC0_B2TIM                  0xFFC16030         /* SMC0 Bank 2 Timing Register */
-#define REG_SMC0_B2ETIM                 0xFFC16034         /* SMC0 Bank 2 Extended Timing Register */
-#define REG_SMC0_B3CTL                  0xFFC1603C         /* SMC0 Bank 3 Control Register */
-#define REG_SMC0_B3TIM                  0xFFC16040         /* SMC0 Bank 3 Timing Register */
-#define REG_SMC0_B3ETIM                 0xFFC16044         /* SMC0 Bank 3 Extended Timing Register */
-
-/* =========================
-        SMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GCTL_BGDIS                   4                               /* Bus Grant Disable */
-#define BITM_SMC_GCTL_BGDIS                  (_ADI_MSK(0x00000010,uint32_t))  /* Bus Grant Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GSTAT_BGHSTAT                2                               /* Bus Grant Hold Status */
-#define BITP_SMC_GSTAT_BRQSTAT                1                               /* Bus Request Status */
-#define BITP_SMC_GSTAT_BGSTAT                 0                               /* Bus Grant Status */
-#define BITM_SMC_GSTAT_BGHSTAT               (_ADI_MSK(0x00000004,uint32_t))  /* Bus Grant Hold Status */
-#define BITM_SMC_GSTAT_BRQSTAT               (_ADI_MSK(0x00000002,uint32_t))  /* Bus Request Status */
-#define BITM_SMC_GSTAT_BGSTAT                (_ADI_MSK(0x00000001,uint32_t))  /* Bus Grant Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B0CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B0CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B0CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B0CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B0CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B0CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B0CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B0CTL_EN                     0                               /* Bank 0 Enable */
-#define BITM_SMC_B0CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B0CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B0CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B0CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B0CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B0CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B0CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B0CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B0CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B0TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B0TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B0TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B0TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B0TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B0TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B0TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B0TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B0TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B0TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B0TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B0ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B0ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B0ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B0ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B0ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B0ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B0ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B0ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B0ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B1CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B1CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B1CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B1CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B1CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B1CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B1CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B1CTL_EN                     0                               /* Bank 1 Enable */
-#define BITM_SMC_B1CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B1CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B1CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B1CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B1CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B1CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B1CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B1CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B1CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 1 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B1TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B1TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B1TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B1TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B1TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B1TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B1TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B1TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B1TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B1TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B1TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B1ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B1ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B1ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B1ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B1ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B1ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B1ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B1ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B1ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B2CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B2CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B2CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B2CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B2CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B2CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B2CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B2CTL_EN                     0                               /* Bank 2 Enable */
-#define BITM_SMC_B2CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B2CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B2CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B2CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B2CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B2CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B2CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B2CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B2CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 2 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B2TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B2TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B2TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B2TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B2TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B2TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B2TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B2TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B2TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B2TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B2TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B2ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B2ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B2ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B2ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B2ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B2ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B2ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B2ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B2ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B3CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B3CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B3CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B3CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B3CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B3CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B3CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B3CTL_EN                     0                               /* Bank 3 Enable */
-#define BITM_SMC_B3CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B3CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B3CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B3CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B3CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B3CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B3CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B3CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B3CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 3 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B3TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B3TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B3TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B3TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B3TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B3TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B3TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B3TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B3TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B3TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B3TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B3ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B3ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B3ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B3ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B3ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B3ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B3ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B3ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B3ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ==================================================
-        Watch Dog Timer Unit Registers
-   ================================================== */
-
-/* =========================
-        WDOG0
-   ========================= */
-#define REG_WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
-#define REG_WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
-#define REG_WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG1
-   ========================= */
-#define REG_WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
-#define REG_WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
-#define REG_WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WDOG_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WDOG_CTL_WDRO                   15                               /* Watch Dog Rollover */
-#define BITP_WDOG_CTL_WDEN                    4                               /* Watch Dog Enable */
-
-#define BITM_WDOG_CTL_WDRO                   (_ADI_MSK(0x00008000,uint32_t))  /* Watch Dog Rollover */
-#define ENUM_WDOG_CTL_WDTEXP                 (_ADI_MSK(0x00008000,uint32_t))  /* WDRO: WDT has expired */
-#define BITM_WDOG_CTL_WDEN                   (_ADI_MSK(0x00000FF0,uint32_t))  /* Watch Dog Enable */
-
-/* ==================================================
-        EPPI Registers
-   ================================================== */
-
-/* =========================
-        EPPI0
-   ========================= */
-#define REG_EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
-#define REG_EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
-#define REG_EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
-#define REG_EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
-#define REG_EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
-#define REG_EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
-#define REG_EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
-#define REG_EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
-#define REG_EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
-#define REG_EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
-#define REG_EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
-#define REG_EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
-#define REG_EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
-
-/* =========================
-        EPPI1
-   ========================= */
-#define REG_EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
-#define REG_EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
-#define REG_EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
-#define REG_EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
-#define REG_EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
-#define REG_EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
-#define REG_EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
-#define REG_EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
-#define REG_EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
-#define REG_EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
-#define REG_EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
-#define REG_EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
-#define REG_EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
-
-/* =========================
-        EPPI2
-   ========================= */
-#define REG_EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
-#define REG_EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
-#define REG_EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
-#define REG_EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
-#define REG_EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
-#define REG_EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
-#define REG_EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
-#define REG_EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
-#define REG_EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
-#define REG_EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
-#define REG_EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
-#define REG_EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
-#define REG_EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
-
-/* =========================
-        EPPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_STAT_FLD                   15                               /* Current Field Received by EPPI */
-#define BITP_EPPI_STAT_ERRDET                14                               /* Preamble Error Detected */
-#define BITP_EPPI_STAT_PXPERR                 7                               /* PxP Ready Error */
-#define BITP_EPPI_STAT_ERRNCOR                6                               /* Preamble Error Not Corrected */
-#define BITP_EPPI_STAT_FTERRUNDR              5                               /* Frame Track Underflow */
-#define BITP_EPPI_STAT_FTERROVR               4                               /* Frame Track Overflow */
-#define BITP_EPPI_STAT_LTERRUNDR              3                               /* Line Track Underflow */
-#define BITP_EPPI_STAT_LTERROVR               2                               /* Line Track Overflow */
-#define BITP_EPPI_STAT_YFIFOERR               1                               /* Luma FIFO Error */
-#define BITP_EPPI_STAT_CFIFOERR               0                               /* Chroma FIFO Error */
-
-#define BITM_EPPI_STAT_FLD                   (_ADI_MSK(0x00008000,uint32_t))  /* Current Field Received by EPPI */
-#define ENUM_EPPI_STAT_FIELD1                (_ADI_MSK(0x00000000,uint32_t))  /* FLD: Field 1 */
-#define ENUM_EPPI_STAT_FIELD2                (_ADI_MSK(0x00008000,uint32_t))  /* FLD: Field 2 */
-
-#define BITM_EPPI_STAT_ERRDET                (_ADI_MSK(0x00004000,uint32_t))  /* Preamble Error Detected */
-#define ENUM_EPPI_STAT_NO_PRERR              (_ADI_MSK(0x00000000,uint32_t))  /* ERRDET: No preamble error detected */
-#define ENUM_EPPI_STAT_PRERR                 (_ADI_MSK(0x00004000,uint32_t))  /* ERRDET: Preamble error detected */
-#define BITM_EPPI_STAT_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error */
-
-#define BITM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* Preamble Error Not Corrected */
-#define ENUM_EPPI_STAT_NO_ERRNCOR            (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: No uncorrected preamble error has occurred */
-#define ENUM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Preamble error detected but not corrected */
-
-#define BITM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow */
-#define ENUM_EPPI_STAT_NO_FTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow */
-#define ENUM_EPPI_STAT_NO_FTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow */
-#define ENUM_EPPI_STAT_NO_LTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow */
-#define ENUM_EPPI_STAT_NO_LTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* Luma FIFO Error */
-#define ENUM_EPPI_STAT_NO_YFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Error Occurred */
-
-#define BITM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* Chroma FIFO Error */
-#define ENUM_EPPI_STAT_NO_CFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HCNT_VALUE                  0                               /* Horizontal Transfer Count */
-#define BITM_EPPI_HCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HDLY_VALUE                  0                               /* Horizontal Delay Count */
-#define BITM_EPPI_HDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VCNT_VALUE                  0                               /* Vertical Transfer Count */
-#define BITM_EPPI_VCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VDLY_VALUE                  0                               /* Vertical Delay Count */
-#define BITM_EPPI_VDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FRAME                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FRAME_VALUE                 0                               /* Lines Per Frame */
-#define BITM_EPPI_FRAME_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lines Per Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_LINE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_LINE_VALUE                  0                               /* Samples Per Line */
-#define BITM_EPPI_LINE_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Samples Per Line */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CLKDIV                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CLKDIV_VALUE                0                               /* Internal Clock Divider */
-#define BITM_EPPI_CLKDIV_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* Internal Clock Divider */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL_CLKGATEN               31                               /* Clock Gating Enable */
-#define BITP_EPPI_CTL_MUXSEL                 30                               /* MUX Select */
-#define BITP_EPPI_CTL_DMAFINEN               29                               /* DMA Finish Enable */
-#define BITP_EPPI_CTL_DMACFG                 28                               /* One or Two DMA Channels Mode */
-#define BITP_EPPI_CTL_RGBFMTEN               27                               /* RGB Formatting Enable */
-#define BITP_EPPI_CTL_SPLTWRD                26                               /* Split Word */
-#define BITP_EPPI_CTL_SUBSPLTODD             25                               /* Sub-Split Odd Samples */
-#define BITP_EPPI_CTL_SPLTEO                 24                               /* Split Even and Odd Data Samples */
-#define BITP_EPPI_CTL_SWAPEN                 23                               /* Swap Enable */
-#define BITP_EPPI_CTL_PACKEN                 22                               /* Pack/Unpack Enable */
-#define BITP_EPPI_CTL_SKIPEO                 21                               /* Skip Even or Odd */
-#define BITP_EPPI_CTL_SKIPEN                 20                               /* Skip Enable */
-#define BITP_EPPI_CTL_DMIRR                  19                               /* Data Mirroring */
-#define BITP_EPPI_CTL_DLEN                   16                               /* Data Length */
-#define BITP_EPPI_CTL_POLS                   14                               /* Frame Sync Polarity */
-#define BITP_EPPI_CTL_POLC                   12                               /* Clock Polarity */
-#define BITP_EPPI_CTL_SIGNEXT                11                               /* Sign Extension */
-#define BITP_EPPI_CTL_IFSGEN                 10                               /* Internal Frame Sync Generation */
-#define BITP_EPPI_CTL_ICLKGEN                 9                               /* Internal Clock Generation */
-#define BITP_EPPI_CTL_BLANKGEN                8                               /* king Generation (ITU Output Mode) */
-#define BITP_EPPI_CTL_ITUTYPE                 7                               /* ITU Interlace or Progressive */
-#define BITP_EPPI_CTL_FLDSEL                  6                               /* Field Select/Trigger */
-#define BITP_EPPI_CTL_FSCFG                   4                               /* Frame Sync Configuration */
-#define BITP_EPPI_CTL_XFRTYPE                 2                               /* Transfer Type ( Operating Mode) */
-#define BITP_EPPI_CTL_DIR                     1                               /* PPI Direction */
-#define BITP_EPPI_CTL_EN                      0                               /* PPI Enable */
-
-#define BITM_EPPI_CTL_CLKGATEN               (_ADI_MSK(0x80000000,uint32_t))  /* Clock Gating Enable */
-#define ENUM_EPPI_CTL_CLKGATE_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* CLKGATEN: Disable */
-#define ENUM_EPPI_CTL_CLKGATE_EN             (_ADI_MSK(0x80000000,uint32_t))  /* CLKGATEN: Enable */
-
-#define BITM_EPPI_CTL_MUXSEL                 (_ADI_MSK(0x40000000,uint32_t))  /* MUX Select */
-#define ENUM_EPPI_CTL_MUXSEL0                (_ADI_MSK(0x00000000,uint32_t))  /* MUXSEL: Normal Operation */
-#define ENUM_EPPI_CTL_MUXSEL1                (_ADI_MSK(0x40000000,uint32_t))  /* MUXSEL: Multiplexed Operation */
-
-#define BITM_EPPI_CTL_DMAFINEN               (_ADI_MSK(0x20000000,uint32_t))  /* DMA Finish Enable */
-#define ENUM_EPPI_CTL_FINISH_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* DMAFINEN: No Finish Command */
-#define ENUM_EPPI_CTL_FINISH_EN              (_ADI_MSK(0x20000000,uint32_t))  /* DMAFINEN: Enable Send Finish Command */
-
-#define BITM_EPPI_CTL_DMACFG                 (_ADI_MSK(0x10000000,uint32_t))  /* One or Two DMA Channels Mode */
-#define ENUM_EPPI_CTL_DMA1CHAN               (_ADI_MSK(0x00000000,uint32_t))  /* DMACFG: PPI uses one DMA Channel */
-#define ENUM_EPPI_CTL_DMA2CHAN               (_ADI_MSK(0x10000000,uint32_t))  /* DMACFG: PPI uses two DMA Channels */
-
-#define BITM_EPPI_CTL_RGBFMTEN               (_ADI_MSK(0x08000000,uint32_t))  /* RGB Formatting Enable */
-#define ENUM_EPPI_CTL_RGBFMT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RGBFMTEN: Disable RGB Formatted Output */
-#define ENUM_EPPI_CTL_RGBFMT_EN              (_ADI_MSK(0x08000000,uint32_t))  /* RGBFMTEN: Enable RGB Formatted Output */
-
-#define BITM_EPPI_CTL_SPLTWRD                (_ADI_MSK(0x04000000,uint32_t))  /* Split Word */
-#define ENUM_EPPI_CTL_NO_WORDSPLIT           (_ADI_MSK(0x00000000,uint32_t))  /* SPLTWRD: PPI_DATA has (DLEN-1) bits of Y or Cr or Cb */
-#define ENUM_EPPI_CTL_WORDSPLIT              (_ADI_MSK(0x04000000,uint32_t))  /* SPLTWRD: PPI_DATA contains 2 elements per word */
-
-#define BITM_EPPI_CTL_SUBSPLTODD             (_ADI_MSK(0x02000000,uint32_t))  /* Sub-Split Odd Samples */
-#define ENUM_EPPI_CTL_NO_SUBSPLIT            (_ADI_MSK(0x00000000,uint32_t))  /* SUBSPLTODD: Disable */
-#define ENUM_EPPI_CTL_SUBSPLIT_ODD           (_ADI_MSK(0x02000000,uint32_t))  /* SUBSPLTODD: Enable */
-
-#define BITM_EPPI_CTL_SPLTEO                 (_ADI_MSK(0x01000000,uint32_t))  /* Split Even and Odd Data Samples */
-#define ENUM_EPPI_CTL_SPLTEO_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SPLTEO: Do Not Split Samples */
-#define ENUM_EPPI_CTL_SPLTEO_EN              (_ADI_MSK(0x01000000,uint32_t))  /* SPLTEO: Split Even/Odd Samples */
-
-#define BITM_EPPI_CTL_SWAPEN                 (_ADI_MSK(0x00800000,uint32_t))  /* Swap Enable */
-#define ENUM_EPPI_CTL_SWAP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* SWAPEN: Disable */
-#define ENUM_EPPI_CTL_SWAP_EN                (_ADI_MSK(0x00800000,uint32_t))  /* SWAPEN: Enable */
-
-#define BITM_EPPI_CTL_PACKEN                 (_ADI_MSK(0x00400000,uint32_t))  /* Pack/Unpack Enable */
-#define ENUM_EPPI_CTL_PACK_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* PACKEN: Disable */
-#define ENUM_EPPI_CTL_PACK_EN                (_ADI_MSK(0x00400000,uint32_t))  /* PACKEN: Enable */
-
-#define BITM_EPPI_CTL_SKIPEO                 (_ADI_MSK(0x00200000,uint32_t))  /* Skip Even or Odd */
-#define ENUM_EPPI_CTL_SKIPODD                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEO: Skip Odd Samples */
-#define ENUM_EPPI_CTL_SKIPEVEN               (_ADI_MSK(0x00200000,uint32_t))  /* SKIPEO: Skip Even Samples */
-
-#define BITM_EPPI_CTL_SKIPEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Skip Enable */
-#define ENUM_EPPI_CTL_NO_SKIP                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEN: No Samples Skipping */
-#define ENUM_EPPI_CTL_SKIP                   (_ADI_MSK(0x00100000,uint32_t))  /* SKIPEN: Skip Alternate Samples */
-
-#define BITM_EPPI_CTL_DMIRR                  (_ADI_MSK(0x00080000,uint32_t))  /* Data Mirroring */
-#define ENUM_EPPI_CTL_NO_MIRROR              (_ADI_MSK(0x00000000,uint32_t))  /* DMIRR: No Data Mirroring */
-#define ENUM_EPPI_CTL_MIRROR                 (_ADI_MSK(0x00080000,uint32_t))  /* DMIRR: Data Mirroring */
-
-#define BITM_EPPI_CTL_DLEN                   (_ADI_MSK(0x00070000,uint32_t))  /* Data Length */
-#define ENUM_EPPI_CTL_DLEN08                 (_ADI_MSK(0x00000000,uint32_t))  /* DLEN: 8 bits */
-#define ENUM_EPPI_CTL_DLEN10                 (_ADI_MSK(0x00010000,uint32_t))  /* DLEN: 10 bits */
-#define ENUM_EPPI_CTL_DLEN12                 (_ADI_MSK(0x00020000,uint32_t))  /* DLEN: 12 bits */
-#define ENUM_EPPI_CTL_DLEN14                 (_ADI_MSK(0x00030000,uint32_t))  /* DLEN: 14 bits */
-#define ENUM_EPPI_CTL_DLEN16                 (_ADI_MSK(0x00040000,uint32_t))  /* DLEN: 16 bits */
-#define ENUM_EPPI_CTL_DLEN18                 (_ADI_MSK(0x00050000,uint32_t))  /* DLEN: 18 bits */
-#define ENUM_EPPI_CTL_DLEN20                 (_ADI_MSK(0x00060000,uint32_t))  /* DLEN: 20 bits */
-#define ENUM_EPPI_CTL_DLEN24                 (_ADI_MSK(0x00070000,uint32_t))  /* DLEN: 24 bits */
-
-#define BITM_EPPI_CTL_POLS                   (_ADI_MSK(0x0000C000,uint32_t))  /* Frame Sync Polarity */
-#define ENUM_EPPI_CTL_FS1HI_FS2HI            (_ADI_MSK(0x00000000,uint32_t))  /* POLS: FS1 and FS2 are active high */
-#define ENUM_EPPI_CTL_FS1LO_FS2HI            (_ADI_MSK(0x00004000,uint32_t))  /* POLS: FS1 is active low. FS2 is active high */
-#define ENUM_EPPI_CTL_FS1HI_FS2LO            (_ADI_MSK(0x00008000,uint32_t))  /* POLS: FS1 is active high. FS2 is active low */
-#define ENUM_EPPI_CTL_FS1LO_FS2LO            (_ADI_MSK(0x0000C000,uint32_t))  /* POLS: FS1 and FS2 are active low */
-
-#define BITM_EPPI_CTL_POLC                   (_ADI_MSK(0x00003000,uint32_t))  /* Clock Polarity */
-#define ENUM_EPPI_CTL_POLC00                 (_ADI_MSK(0x00000000,uint32_t))  /* POLC: Clock/Sync polarity mode 0 */
-#define ENUM_EPPI_CTL_POLC01                 (_ADI_MSK(0x00001000,uint32_t))  /* POLC: Clock/Sync polarity mode 1 */
-#define ENUM_EPPI_CTL_POLC10                 (_ADI_MSK(0x00002000,uint32_t))  /* POLC: Clock/Sync polarity mode 2 */
-#define ENUM_EPPI_CTL_POLC11                 (_ADI_MSK(0x00003000,uint32_t))  /* POLC: Clock/Sync polarity mode 3 */
-
-#define BITM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* Sign Extension */
-#define ENUM_EPPI_CTL_ZEROFILL               (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Filled */
-#define ENUM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* SIGNEXT: Sign Extended */
-
-#define BITM_EPPI_CTL_IFSGEN                 (_ADI_MSK(0x00000400,uint32_t))  /* Internal Frame Sync Generation */
-#define ENUM_EPPI_CTL_EXTFS                  (_ADI_MSK(0x00000000,uint32_t))  /* IFSGEN: External Frame Sync */
-#define ENUM_EPPI_CTL_INTFS                  (_ADI_MSK(0x00000400,uint32_t))  /* IFSGEN: Internal Frame Sync */
-
-#define BITM_EPPI_CTL_ICLKGEN                (_ADI_MSK(0x00000200,uint32_t))  /* Internal Clock Generation */
-#define ENUM_EPPI_CTL_EXTCLK                 (_ADI_MSK(0x00000000,uint32_t))  /* ICLKGEN: External Clock */
-#define ENUM_EPPI_CTL_INTCLK                 (_ADI_MSK(0x00000200,uint32_t))  /* ICLKGEN: Internal Clock */
-
-#define BITM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* king Generation (ITU Output Mode) */
-#define ENUM_EPPI_CTL_NO_BLANKGEN            (_ADI_MSK(0x00000000,uint32_t))  /* BLANKGEN: Disable */
-#define ENUM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* BLANKGEN: Enable */
-
-#define BITM_EPPI_CTL_ITUTYPE                (_ADI_MSK(0x00000080,uint32_t))  /* ITU Interlace or Progressive */
-#define ENUM_EPPI_CTL_INTERLACED             (_ADI_MSK(0x00000000,uint32_t))  /* ITUTYPE: Interlaced */
-#define ENUM_EPPI_CTL_PROGRESSIVE            (_ADI_MSK(0x00000080,uint32_t))  /* ITUTYPE: Progressive */
-
-#define BITM_EPPI_CTL_FLDSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* Field Select/Trigger */
-#define ENUM_EPPI_CTL_FLDSEL_LO              (_ADI_MSK(0x00000000,uint32_t))  /* FLDSEL: Field Mode 0 */
-#define ENUM_EPPI_CTL_FLDSEL_HI              (_ADI_MSK(0x00000040,uint32_t))  /* FLDSEL: Field Mode 1 */
-
-#define BITM_EPPI_CTL_FSCFG                  (_ADI_MSK(0x00000030,uint32_t))  /* Frame Sync Configuration */
-#define ENUM_EPPI_CTL_SYNC0                  (_ADI_MSK(0x00000000,uint32_t))  /* FSCFG: Sync Mode 0 */
-#define ENUM_EPPI_CTL_SYNC1                  (_ADI_MSK(0x00000010,uint32_t))  /* FSCFG: Sync Mode 1 */
-#define ENUM_EPPI_CTL_SYNC2                  (_ADI_MSK(0x00000020,uint32_t))  /* FSCFG: Sync Mode 2 */
-#define ENUM_EPPI_CTL_SYNC3                  (_ADI_MSK(0x00000030,uint32_t))  /* FSCFG: Sync Mode 3 */
-
-#define BITM_EPPI_CTL_XFRTYPE                (_ADI_MSK(0x0000000C,uint32_t))  /* Transfer Type ( Operating Mode) */
-#define ENUM_EPPI_CTL_ACTIVE656              (_ADI_MSK(0x00000000,uint32_t))  /* XFRTYPE: ITU656 Active Video Only Mode */
-#define ENUM_EPPI_CTL_ENTIRE656              (_ADI_MSK(0x00000004,uint32_t))  /* XFRTYPE: ITU656 Entire Field Mode */
-#define ENUM_EPPI_CTL_VERT656                (_ADI_MSK(0x00000008,uint32_t))  /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define ENUM_EPPI_CTL_NON656                 (_ADI_MSK(0x0000000C,uint32_t))  /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-
-#define BITM_EPPI_CTL_DIR                    (_ADI_MSK(0x00000002,uint32_t))  /* PPI Direction */
-#define ENUM_EPPI_CTL_RXMODE                 (_ADI_MSK(0x00000000,uint32_t))  /* DIR: Receive Mode */
-#define ENUM_EPPI_CTL_TXMODE                 (_ADI_MSK(0x00000002,uint32_t))  /* DIR: Transmit Mode */
-
-#define BITM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* PPI Enable */
-#define ENUM_EPPI_CTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_WLVB                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_WLVB_F2VBAD            24                               /* Field 2 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F2VBBD            16                               /* Field 2 Vertical Blanking Before Data */
-#define BITP_EPPI_FS2_WLVB_F1VBAD             8                               /* Field 1 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F1VBBD             0                               /* Field 1 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F2VBAD            (_ADI_MSK(0xFF000000,uint32_t))  /* Field 2 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F2VBBD            (_ADI_MSK(0x00FF0000,uint32_t))  /* Field 2 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F1VBAD            (_ADI_MSK(0x0000FF00,uint32_t))  /* Field 1 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F1VBBD            (_ADI_MSK(0x000000FF,uint32_t))  /* Field 1 Vertical Blanking Before Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_PALPF                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_PALPF_F2ACT            16                               /* Field 2 Active */
-#define BITP_EPPI_FS2_PALPF_F1ACT             0                               /* Field 1 Active */
-#define BITM_EPPI_FS2_PALPF_F2ACT            (_ADI_MSK(0xFFFF0000,uint32_t))  /* Field 2 Active */
-#define BITM_EPPI_FS2_PALPF_F1ACT            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Field 1 Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_IMSK_PXPERR                 7                               /* PxP Ready Error Interrupt Mask */
-#define BITP_EPPI_IMSK_ERRNCOR                6                               /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERRUNDR              5                               /* Frame Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERROVR               4                               /* Frame Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERRUNDR              3                               /* Line Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERROVR               2                               /* Line Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_YFIFOERR               1                               /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_CFIFOERR               0                               /* CFIFO Underflow or Overflow Error Interrupt Mask */
-
-#define BITM_EPPI_IMSK_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_PXPERR_UMSK           (_ADI_MSK(0x00000000,uint32_t))  /* PXPERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_PXPERR_MSK            (_ADI_MSK(0x00000080,uint32_t))  /* PXPERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define ENUM_EPPI_IMSK_ERRNCOR_UMSK          (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_ERRNCOR_MSK           (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERRUNDR_MSK         (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERROVR_MSK          (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERRUNDR_MSK         (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERROVR_MSK          (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_YFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_YFIFOERR_MSK          (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_CFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_CFIFOERR_MSK          (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Mask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_ODDCLIP                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_ODDCLIP_HIGHODD            16                               /* High Odd Clipping Threshold (Chroma Data) */
-#define BITP_EPPI_ODDCLIP_LOWODD              0                               /* Low Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_HIGHODD            (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_LOWODD             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Odd Clipping Threshold (Chroma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_EVENCLIP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_EVENCLIP_HIGHEVEN          16                               /* High Even Clipping Threshold (Luma Data) */
-#define BITP_EPPI_EVENCLIP_LOWEVEN            0                               /* Low Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_HIGHEVEN          (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_LOWEVEN           (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Even Clipping Threshold (Luma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL2_FS1FINEN               1                               /* HSYNC Finish Enable */
-
-#define BITM_EPPI_CTL2_FS1FINEN              (_ADI_MSK(0x00000002,uint32_t))  /* HSYNC Finish Enable */
-#define ENUM_EPPI_CTL2_FS2FIN_EN             (_ADI_MSK(0x00000000,uint32_t))  /* FS1FINEN: Finish sent after frame RX done */
-#define ENUM_EPPI_CTL2_FS1FIN_EN             (_ADI_MSK(0x00000002,uint32_t))  /* FS1FINEN: Finish sent after frame/line RX done */
-
-/* ==================================================
-        Pixel Compositor Registers
-   ================================================== */
-
-/* =========================
-        PIXC0
-   ========================= */
-#define REG_PIXC0_CTL                   0xFFC19000         /* PIXC0 Control Register */
-#define REG_PIXC0_PPL                   0xFFC19004         /* PIXC0 Pixels Per Line Register */
-#define REG_PIXC0_LPF                   0xFFC19008         /* PIXC0 Line Per Frame Register */
-#define REG_PIXC0_HSTART_A              0xFFC1900C         /* PIXC0 Overlay A Horizontal Start Register */
-#define REG_PIXC0_HEND_A                0xFFC19010         /* PIXC0 Overlay A Horizontal End Register */
-#define REG_PIXC0_VSTART_A              0xFFC19014         /* PIXC0 Overlay A Vertical Start Register */
-#define REG_PIXC0_VEND_A                0xFFC19018         /* PIXC0 Overlay A Vertical End Register */
-#define REG_PIXC0_TRANSP_A              0xFFC1901C         /* PIXC0 Overlay A Transparency Ratio Register */
-#define REG_PIXC0_HSTART_B              0xFFC19020         /* PIXC0 Overlay B Horizontal Start Register */
-#define REG_PIXC0_HEND_B                0xFFC19024         /* PIXC0 Overlay B Horizontal End Register */
-#define REG_PIXC0_VSTART_B              0xFFC19028         /* PIXC0 Overlay B Vertical Start Register */
-#define REG_PIXC0_VEND_B                0xFFC1902C         /* PIXC0 Overlay B Vertical End Register */
-#define REG_PIXC0_TRANSP_B              0xFFC19030         /* PIXC0 Overlay B Transparency Ratio Register */
-#define REG_PIXC0_IRQSTAT               0xFFC1903C         /* PIXC0 Interrupt Status Register */
-#define REG_PIXC0_CONRY                 0xFFC19040         /* PIXC0 RY Conversion Component Register */
-#define REG_PIXC0_CONGU                 0xFFC19044         /* PIXC0 GU Conversion Component Register */
-#define REG_PIXC0_CONBV                 0xFFC19048         /* PIXC0 BV Conversion Component Register */
-#define REG_PIXC0_CCBIAS                0xFFC1904C         /* PIXC0 Conversion Bias Register */
-#define REG_PIXC0_TC                    0xFFC19050         /* PIXC0 Transparency Color Register */
-#define REG_PIXC0_REVID                 0xFFC19054         /* PIXC0 Revision Id */
-
-/* =========================
-        PIXC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CTL_ORGBFRMT               10                               /* Output RGB Data Format */
-#define BITP_PIXC_CTL_IRGBFRMT                8                               /* Input Image Channel RGB Data Format */
-#define BITP_PIXC_CTL_ENTC                    7                               /* Enable Transparent Color */
-#define BITP_PIXC_CTL_UDSMOD                  6                               /* Up/Down Sampling Mode */
-#define BITP_PIXC_CTL_OUTFRMT                 5                               /* Output Data Format */
-#define BITP_PIXC_CTL_OVFRMT                  4                               /* Overlay Data Format */
-#define BITP_PIXC_CTL_IFRMT                   3                               /* Image Data Format */
-#define BITP_PIXC_CTL_OVENB                   2                               /* Overlay Block B Enable */
-#define BITP_PIXC_CTL_OVENA                   1                               /* Overlay Block A Enable */
-#define BITP_PIXC_CTL_EN                      0                               /* Overlay Manager enable (module enable) */
-#define BITM_PIXC_CTL_ORGBFRMT               (_ADI_MSK(0x00000C00,uint32_t))  /* Output RGB Data Format */
-#define BITM_PIXC_CTL_IRGBFRMT               (_ADI_MSK(0x00000300,uint32_t))  /* Input Image Channel RGB Data Format */
-#define BITM_PIXC_CTL_ENTC                   (_ADI_MSK(0x00000080,uint32_t))  /* Enable Transparent Color */
-#define BITM_PIXC_CTL_UDSMOD                 (_ADI_MSK(0x00000040,uint32_t))  /* Up/Down Sampling Mode */
-#define BITM_PIXC_CTL_OUTFRMT                (_ADI_MSK(0x00000020,uint32_t))  /* Output Data Format */
-#define BITM_PIXC_CTL_OVFRMT                 (_ADI_MSK(0x00000010,uint32_t))  /* Overlay Data Format */
-#define BITM_PIXC_CTL_IFRMT                  (_ADI_MSK(0x00000008,uint32_t))  /* Image Data Format */
-#define BITM_PIXC_CTL_OVENB                  (_ADI_MSK(0x00000004,uint32_t))  /* Overlay Block B Enable */
-#define BITM_PIXC_CTL_OVENA                  (_ADI_MSK(0x00000002,uint32_t))  /* Overlay Block A Enable */
-#define BITM_PIXC_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Overlay Manager enable (module enable) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TRANSP_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TRANSP_A_VALUE              0                               /* Overlay Transparency Ratio Values */
-#define BITM_PIXC_TRANSP_A_VALUE             (_ADI_MSK(0x0000000F,uint16_t))  /* Overlay Transparency Ratio Values */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TRANSP_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TRANSP_B_VALUE              0                               /* Overlay Transparency Ratio Values */
-#define BITM_PIXC_TRANSP_B_VALUE             (_ADI_MSK(0x0000000F,uint16_t))  /* Overlay Transparency Ratio Values */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_IRQSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_IRQSTAT_FRMSTAT             3                               /* Frame Interrupt Status */
-#define BITP_PIXC_IRQSTAT_OVSTAT              2                               /* Overlay Interrupt Status */
-#define BITP_PIXC_IRQSTAT_FRMEN               1                               /* Frame Interrupt  Enable */
-#define BITP_PIXC_IRQSTAT_OVEN                0                               /* Overlay Interrupt Enable */
-#define BITM_PIXC_IRQSTAT_FRMSTAT            (_ADI_MSK(0x00000008,uint16_t))  /* Frame Interrupt Status */
-#define BITM_PIXC_IRQSTAT_OVSTAT             (_ADI_MSK(0x00000004,uint16_t))  /* Overlay Interrupt Status */
-#define BITM_PIXC_IRQSTAT_FRMEN              (_ADI_MSK(0x00000002,uint16_t))  /* Frame Interrupt  Enable */
-#define BITM_PIXC_IRQSTAT_OVEN               (_ADI_MSK(0x00000001,uint16_t))  /* Overlay Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONRY                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONRY_RYMULT4              30                               /* Multiply the Row by 4 */
-#define BITP_PIXC_CONRY_A13                  20                               /* A13 element in the coefficient matrix */
-#define BITP_PIXC_CONRY_A12                  10                               /* A12 element in the coefficient matrix */
-#define BITP_PIXC_CONRY_A11                   0                               /* A11 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_RYMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply the Row by 4 */
-#define BITM_PIXC_CONRY_A13                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A13 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_A12                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A12 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_A11                  (_ADI_MSK(0x000003FF,uint32_t))  /* A11 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONGU                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONGU_GUMULT4              30                               /* Multiply The Row By 4 */
-#define BITP_PIXC_CONGU_A23                  20                               /* A23 element in the coefficient matrix */
-#define BITP_PIXC_CONGU_A22                  10                               /* A22 element in the coefficient matrix */
-#define BITP_PIXC_CONGU_A21                   0                               /* A21 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_GUMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply The Row By 4 */
-#define BITM_PIXC_CONGU_A23                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A23 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_A22                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A22 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_A21                  (_ADI_MSK(0x000003FF,uint32_t))  /* A21 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONBV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONBV_BVMULT4              30                               /* Multiply The Row By 4 */
-#define BITP_PIXC_CONBV_A33                  20                               /* A33 element in the coefficient matrix */
-#define BITP_PIXC_CONBV_A32                  10                               /* A32 element in the coefficient matrix */
-#define BITP_PIXC_CONBV_A31                   0                               /* A31 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_BVMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply The Row By 4 */
-#define BITM_PIXC_CONBV_A33                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A33 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_A32                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A32 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_A31                  (_ADI_MSK(0x000003FF,uint32_t))  /* A31 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CCBIAS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CCBIAS_A34                 20                               /* A34 in bias vector */
-#define BITP_PIXC_CCBIAS_A24                 10                               /* A24 in bias vector */
-#define BITP_PIXC_CCBIAS_A14                  0                               /* A14 in bias vector */
-#define BITM_PIXC_CCBIAS_A34                 (_ADI_MSK(0x3FF00000,uint32_t))  /* A34 in bias vector */
-#define BITM_PIXC_CCBIAS_A24                 (_ADI_MSK(0x000FFC00,uint32_t))  /* A24 in bias vector */
-#define BITM_PIXC_CCBIAS_A14                 (_ADI_MSK(0x000003FF,uint32_t))  /* A14 in bias vector */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TC_BVT                     16                               /* Trans. color - B/V component */
-#define BITP_PIXC_TC_GUT                      8                               /* Trans. color - G/U component */
-#define BITP_PIXC_TC_RYT                      0                               /* Trans. color - R/Y component */
-#define BITM_PIXC_TC_BVT                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Trans. color - B/V component */
-#define BITM_PIXC_TC_GUT                     (_ADI_MSK(0x0000FF00,uint32_t))  /* Trans. color - G/U component */
-#define BITM_PIXC_TC_RYT                     (_ADI_MSK(0x000000FF,uint32_t))  /* Trans. color - R/Y component */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_REVID_MAJOR                 4                               /* Major Version ID */
-#define BITP_PIXC_REVID_REV                   0                               /* Incremental Version ID */
-#define BITM_PIXC_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_PIXC_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ==================================================
-        PVP Registers
-   ================================================== */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP                             Block level enums
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define ENUM_PVP_GCFG                   0x00          /* PVP Block ID Code for GCFG */
-#define ENUM_PVP_OPF0                   0x01          /* PVP Block ID Code for OPF0 */
-#define ENUM_PVP_OPF1                   0x02          /* PVP Block ID Code for OPF1 */
-#define ENUM_PVP_OPF2                   0x03          /* PVP Block ID Code for OPF2 */
-#define ENUM_PVP_OPF3                   0x04          /* PVP Block ID Code for OPF3 */
-#define ENUM_PVP_PEC                    0x05          /* PVP Block ID Code for PEC */
-#define ENUM_PVP_IIM0                   0x06          /* PVP Block ID Code for IIM0 */
-#define ENUM_PVP_IIM1                   0x07          /* PVP Block ID Code for IIM1 */
-#define ENUM_PVP_ACU                    0x08          /* PVP Block ID Code for ACU */
-#define ENUM_PVP_UDS                    0x0A          /* PVP Block ID Code for UDS */
-#define ENUM_PVP_IPF0                   0x0C          /* PVP Block ID Code for IPF0 */
-#define ENUM_PVP_IPF1                   0x0E          /* PVP Block ID Code for IPF1 */
-#define ENUM_PVP_CNV0                   0x10          /* PVP Block ID Code for CNV0 */
-#define ENUM_PVP_CNV1                   0x14          /* PVP Block ID Code for CNV1 */
-#define ENUM_PVP_CNV2                   0x18          /* PVP Block ID Code for CNV2 */
-#define ENUM_PVP_CNV3                   0x1C          /* PVP Block ID Code for CNV3 */
-#define ENUM_PVP_THC0                   0x20          /* PVP Block ID Code for THC0 */
-#define ENUM_PVP_THC1                   0x28          /* PVP Block ID Code for THC1 */
-#define ENUM_PVP_PMA                    0x30          /* PVP Block ID Code for PMA */
-
-/* =========================
-        PVP0
-   ========================= */
-#define REG_PVP0_REVID                  0xFFC1A000         /* PVP0 Revision ID */
-#define REG_PVP0_CTL                    0xFFC1A004         /* PVP0 Control */
-#define REG_PVP0_IMSK0                  0xFFC1A008         /* PVP0 Interrupt Mask n */
-#define REG_PVP0_IMSK1                  0xFFC1A00C         /* PVP0 Interrupt Mask n */
-#define REG_PVP0_STAT                   0xFFC1A010         /* PVP0 Status */
-#define REG_PVP0_ILAT                   0xFFC1A014         /* PVP0 Interrupt Latch Status n */
-#define REG_PVP0_IREQ0                  0xFFC1A018         /* PVP0 Interrupt Request n */
-#define REG_PVP0_IREQ1                  0xFFC1A01C         /* PVP0 Interrupt Request n */
-#define REG_PVP0_OPF0_CFG               0xFFC1A020         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF1_CFG               0xFFC1A040         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF2_CFG               0xFFC1A060         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF0_CTL               0xFFC1A024         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF1_CTL               0xFFC1A044         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF2_CTL               0xFFC1A064         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF3_CFG               0xFFC1A080         /* PVP0 OPF3 (Memory Pipe) Configuration */
-#define REG_PVP0_OPF3_CTL               0xFFC1A084         /* PVP0 OPF3 (Memory Pipe) Control */
-#define REG_PVP0_PEC_CFG                0xFFC1A0A0         /* PVP0 PEC Configuration */
-#define REG_PVP0_PEC_CTL                0xFFC1A0A4         /* PVP0 PEC Control */
-#define REG_PVP0_PEC_D1TH0              0xFFC1A0A8         /* PVP0 PEC Lower Hysteresis Threshold */
-#define REG_PVP0_PEC_D1TH1              0xFFC1A0AC         /* PVP0 PEC Upper Hysteresis Threshold */
-#define REG_PVP0_PEC_D2TH0              0xFFC1A0B0         /* PVP0 PEC Weak Zero Crossing Threshold */
-#define REG_PVP0_PEC_D2TH1              0xFFC1A0B4         /* PVP0 PEC Strong Zero Crossing Threshold */
-#define REG_PVP0_IIM0_CFG               0xFFC1A0C0         /* PVP0 IIMn Configuration */
-#define REG_PVP0_IIM1_CFG               0xFFC1A0E0         /* PVP0 IIMn Configuration */
-#define REG_PVP0_IIM0_CTL               0xFFC1A0C4         /* PVP0 IIMn Control */
-#define REG_PVP0_IIM1_CTL               0xFFC1A0E4         /* PVP0 IIMn Control */
-#define REG_PVP0_IIM0_SCALE             0xFFC1A0C8         /* PVP0 IIMn Scaling Values */
-#define REG_PVP0_IIM1_SCALE             0xFFC1A0E8         /* PVP0 IIMn Scaling Values */
-#define REG_PVP0_IIM0_SOVF_STAT         0xFFC1A0CC         /* PVP0 IIMn Signed Overflow Status */
-#define REG_PVP0_IIM1_SOVF_STAT         0xFFC1A0EC         /* PVP0 IIMn Signed Overflow Status */
-#define REG_PVP0_IIM0_UOVF_STAT         0xFFC1A0D0         /* PVP0 IIMn Unsigned Overflow Status */
-#define REG_PVP0_IIM1_UOVF_STAT         0xFFC1A0F0         /* PVP0 IIMn Unsigned Overflow Status */
-#define REG_PVP0_ACU_CFG                0xFFC1A100         /* PVP0 ACU Configuration */
-#define REG_PVP0_ACU_CTL                0xFFC1A104         /* PVP0 ACU Control */
-#define REG_PVP0_ACU_OFFSET             0xFFC1A108         /* PVP0 ACU SUM Constant */
-#define REG_PVP0_ACU_FACTOR             0xFFC1A10C         /* PVP0 ACU PROD Constant */
-#define REG_PVP0_ACU_SHIFT              0xFFC1A110         /* PVP0 ACU Shift Constant */
-#define REG_PVP0_ACU_MIN                0xFFC1A114         /* PVP0 ACU Lower Sat Threshold Min */
-#define REG_PVP0_ACU_MAX                0xFFC1A118         /* PVP0 ACU Upper Sat Threshold Max */
-#define REG_PVP0_UDS_CFG                0xFFC1A140         /* PVP0 UDS Configuration */
-#define REG_PVP0_UDS_CTL                0xFFC1A144         /* PVP0 UDS Control */
-#define REG_PVP0_UDS_OHCNT              0xFFC1A148         /* PVP0 UDS Output HCNT */
-#define REG_PVP0_UDS_OVCNT              0xFFC1A14C         /* PVP0 UDS Output VCNT */
-#define REG_PVP0_UDS_HAVG               0xFFC1A150         /* PVP0 UDS HAVG */
-#define REG_PVP0_UDS_VAVG               0xFFC1A154         /* PVP0 UDS VAVG */
-#define REG_PVP0_IPF0_CFG               0xFFC1A180         /* PVP0 IPF0 (Camera Pipe) Configuration */
-#define REG_PVP0_IPF0_PIPECTL           0xFFC1A184         /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define REG_PVP0_IPF1_PIPECTL           0xFFC1A1C4         /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define REG_PVP0_IPF0_CTL               0xFFC1A188         /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define REG_PVP0_IPF1_CTL               0xFFC1A1C8         /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define REG_PVP0_IPF0_TAG               0xFFC1A18C         /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define REG_PVP0_IPF1_TAG               0xFFC1A1CC         /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define REG_PVP0_IPF0_FCNT              0xFFC1A190         /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define REG_PVP0_IPF1_FCNT              0xFFC1A1D0         /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define REG_PVP0_IPF0_HCNT              0xFFC1A194         /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define REG_PVP0_IPF1_HCNT              0xFFC1A1D4         /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define REG_PVP0_IPF0_VCNT              0xFFC1A198         /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define REG_PVP0_IPF1_VCNT              0xFFC1A1D8         /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define REG_PVP0_IPF0_HPOS              0xFFC1A19C         /* PVP0 IPF0 (Camera Pipe) Horizontal Position */
-#define REG_PVP0_IPF0_VPOS              0xFFC1A1A0         /* PVP0 IPF0 (Camera Pipe) Vertical Position */
-#define REG_PVP0_IPF0_TAG_STAT          0xFFC1A1A4         /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define REG_PVP0_IPF1_TAG_STAT          0xFFC1A1E4         /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define REG_PVP0_IPF1_CFG               0xFFC1A1C0         /* PVP0 IPF1 (Memory Pipe) Configuration */
-#define REG_PVP0_CNV0_CFG               0xFFC1A200         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV1_CFG               0xFFC1A280         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV2_CFG               0xFFC1A300         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV3_CFG               0xFFC1A380         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV0_CTL               0xFFC1A204         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV1_CTL               0xFFC1A284         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV2_CTL               0xFFC1A304         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV3_CTL               0xFFC1A384         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV0_C00C01            0xFFC1A208         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV1_C00C01            0xFFC1A288         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV2_C00C01            0xFFC1A308         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV3_C00C01            0xFFC1A388         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV0_C02C03            0xFFC1A20C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV1_C02C03            0xFFC1A28C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV2_C02C03            0xFFC1A30C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV3_C02C03            0xFFC1A38C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV0_C04               0xFFC1A210         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV1_C04               0xFFC1A290         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV2_C04               0xFFC1A310         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV3_C04               0xFFC1A390         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV0_C10C11            0xFFC1A214         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV1_C10C11            0xFFC1A294         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV2_C10C11            0xFFC1A314         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV3_C10C11            0xFFC1A394         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV0_C12C13            0xFFC1A218         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV1_C12C13            0xFFC1A298         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV2_C12C13            0xFFC1A318         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV3_C12C13            0xFFC1A398         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV0_C14               0xFFC1A21C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV1_C14               0xFFC1A29C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV2_C14               0xFFC1A31C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV3_C14               0xFFC1A39C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV0_C20C21            0xFFC1A220         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV1_C20C21            0xFFC1A2A0         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV2_C20C21            0xFFC1A320         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV3_C20C21            0xFFC1A3A0         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV0_C22C23            0xFFC1A224         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV1_C22C23            0xFFC1A2A4         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV2_C22C23            0xFFC1A324         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV3_C22C23            0xFFC1A3A4         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV0_C24               0xFFC1A228         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV1_C24               0xFFC1A2A8         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV2_C24               0xFFC1A328         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV3_C24               0xFFC1A3A8         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV0_C30C31            0xFFC1A22C         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV1_C30C31            0xFFC1A2AC         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV2_C30C31            0xFFC1A32C         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV3_C30C31            0xFFC1A3AC         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV0_C32C33            0xFFC1A230         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV1_C32C33            0xFFC1A2B0         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV2_C32C33            0xFFC1A330         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV3_C32C33            0xFFC1A3B0         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV0_C34               0xFFC1A234         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV1_C34               0xFFC1A2B4         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV2_C34               0xFFC1A334         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV3_C34               0xFFC1A3B4         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV0_C40C41            0xFFC1A238         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV1_C40C41            0xFFC1A2B8         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV2_C40C41            0xFFC1A338         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV3_C40C41            0xFFC1A3B8         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV0_C42C43            0xFFC1A23C         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV1_C42C43            0xFFC1A2BC         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV2_C42C43            0xFFC1A33C         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV3_C42C43            0xFFC1A3BC         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV0_C44               0xFFC1A240         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV1_C44               0xFFC1A2C0         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV2_C44               0xFFC1A340         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV3_C44               0xFFC1A3C0         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV0_SCALE             0xFFC1A244         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV1_SCALE             0xFFC1A2C4         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV2_SCALE             0xFFC1A344         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV3_SCALE             0xFFC1A3C4         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_THC0_CFG               0xFFC1A400         /* PVP0 THCn Configuration */
-#define REG_PVP0_THC1_CFG               0xFFC1A500         /* PVP0 THCn Configuration */
-#define REG_PVP0_THC0_CTL               0xFFC1A404         /* PVP0 THCn Control */
-#define REG_PVP0_THC1_CTL               0xFFC1A504         /* PVP0 THCn Control */
-#define REG_PVP0_THC0_HFCNT             0xFFC1A408         /* PVP0 THCn Histogram Frame Count */
-#define REG_PVP0_THC1_HFCNT             0xFFC1A508         /* PVP0 THCn Histogram Frame Count */
-#define REG_PVP0_THC0_RMAXREP           0xFFC1A40C         /* PVP0 THCn Max RLE Reports */
-#define REG_PVP0_THC1_RMAXREP           0xFFC1A50C         /* PVP0 THCn Max RLE Reports */
-#define REG_PVP0_THC0_CMINVAL           0xFFC1A410         /* PVP0 THCn Min Clip Value */
-#define REG_PVP0_THC1_CMINVAL           0xFFC1A510         /* PVP0 THCn Min Clip Value */
-#define REG_PVP0_THC0_CMINTH            0xFFC1A414         /* PVP0 THCn Clip Min Threshold */
-#define REG_PVP0_THC1_CMINTH            0xFFC1A514         /* PVP0 THCn Clip Min Threshold */
-#define REG_PVP0_THC0_CMAXTH            0xFFC1A418         /* PVP0 THCn Clip Max Threshold */
-#define REG_PVP0_THC1_CMAXTH            0xFFC1A518         /* PVP0 THCn Clip Max Threshold */
-#define REG_PVP0_THC0_CMAXVAL           0xFFC1A41C         /* PVP0 THCn Max Clip Value */
-#define REG_PVP0_THC1_CMAXVAL           0xFFC1A51C         /* PVP0 THCn Max Clip Value */
-#define REG_PVP0_THC0_TH0               0xFFC1A420         /* PVP0 THCn Threshold Value 0 */
-#define REG_PVP0_THC1_TH0               0xFFC1A520         /* PVP0 THCn Threshold Value 0 */
-#define REG_PVP0_THC0_TH1               0xFFC1A424         /* PVP0 THCn Threshold Value 1 */
-#define REG_PVP0_THC1_TH1               0xFFC1A524         /* PVP0 THCn Threshold Value 1 */
-#define REG_PVP0_THC0_TH2               0xFFC1A428         /* PVP0 THCn Threshold Value 2 */
-#define REG_PVP0_THC1_TH2               0xFFC1A528         /* PVP0 THCn Threshold Value 2 */
-#define REG_PVP0_THC0_TH3               0xFFC1A42C         /* PVP0 THCn Threshold Value 3 */
-#define REG_PVP0_THC1_TH3               0xFFC1A52C         /* PVP0 THCn Threshold Value 3 */
-#define REG_PVP0_THC0_TH4               0xFFC1A430         /* PVP0 THCn Threshold Value 4 */
-#define REG_PVP0_THC1_TH4               0xFFC1A530         /* PVP0 THCn Threshold Value 4 */
-#define REG_PVP0_THC0_TH5               0xFFC1A434         /* PVP0 THCn Threshold Value 5 */
-#define REG_PVP0_THC1_TH5               0xFFC1A534         /* PVP0 THCn Threshold Value 5 */
-#define REG_PVP0_THC0_TH6               0xFFC1A438         /* PVP0 THCn Threshold Value 6 */
-#define REG_PVP0_THC1_TH6               0xFFC1A538         /* PVP0 THCn Threshold Value 6 */
-#define REG_PVP0_THC0_TH7               0xFFC1A43C         /* PVP0 THCn Threshold Value 7 */
-#define REG_PVP0_THC1_TH7               0xFFC1A53C         /* PVP0 THCn Threshold Value 7 */
-#define REG_PVP0_THC0_TH8               0xFFC1A440         /* PVP0 THCn Threshold Value 8 */
-#define REG_PVP0_THC1_TH8               0xFFC1A540         /* PVP0 THCn Threshold Value 8 */
-#define REG_PVP0_THC0_TH9               0xFFC1A444         /* PVP0 THCn Threshold Value 9 */
-#define REG_PVP0_THC1_TH9               0xFFC1A544         /* PVP0 THCn Threshold Value 9 */
-#define REG_PVP0_THC0_TH10              0xFFC1A448         /* PVP0 THCn Threshold Value 10 */
-#define REG_PVP0_THC1_TH10              0xFFC1A548         /* PVP0 THCn Threshold Value 10 */
-#define REG_PVP0_THC0_TH11              0xFFC1A44C         /* PVP0 THCn Threshold Value 11 */
-#define REG_PVP0_THC1_TH11              0xFFC1A54C         /* PVP0 THCn Threshold Value 11 */
-#define REG_PVP0_THC0_TH12              0xFFC1A450         /* PVP0 THCn Threshold Value 12 */
-#define REG_PVP0_THC1_TH12              0xFFC1A550         /* PVP0 THCn Threshold Value 12 */
-#define REG_PVP0_THC0_TH13              0xFFC1A454         /* PVP0 THCn Threshold Value 13 */
-#define REG_PVP0_THC1_TH13              0xFFC1A554         /* PVP0 THCn Threshold Value 13 */
-#define REG_PVP0_THC0_TH14              0xFFC1A458         /* PVP0 THCn Threshold Value 14 */
-#define REG_PVP0_THC1_TH14              0xFFC1A558         /* PVP0 THCn Threshold Value 14 */
-#define REG_PVP0_THC0_TH15              0xFFC1A45C         /* PVP0 THCn Threshold Value 15 */
-#define REG_PVP0_THC1_TH15              0xFFC1A55C         /* PVP0 THCn Threshold Value 15 */
-#define REG_PVP0_THC0_HHPOS             0xFFC1A460         /* PVP0 THCn Histogram Horzontal Position */
-#define REG_PVP0_THC1_HHPOS             0xFFC1A560         /* PVP0 THCn Histogram Horzontal Position */
-#define REG_PVP0_THC0_HVPOS             0xFFC1A464         /* PVP0 THCn Histogram Vertical Position */
-#define REG_PVP0_THC1_HVPOS             0xFFC1A564         /* PVP0 THCn Histogram Vertical Position */
-#define REG_PVP0_THC0_HHCNT             0xFFC1A468         /* PVP0 THCn Histogram Horizontal Count */
-#define REG_PVP0_THC1_HHCNT             0xFFC1A568         /* PVP0 THCn Histogram Horizontal Count */
-#define REG_PVP0_THC0_HVCNT             0xFFC1A46C         /* PVP0 THCn Histogram Vertical Count */
-#define REG_PVP0_THC1_HVCNT             0xFFC1A56C         /* PVP0 THCn Histogram Vertical Count */
-#define REG_PVP0_THC0_RHPOS             0xFFC1A470         /* PVP0 THCn RLE Horizontal Position */
-#define REG_PVP0_THC1_RHPOS             0xFFC1A570         /* PVP0 THCn RLE Horizontal Position */
-#define REG_PVP0_THC0_RVPOS             0xFFC1A474         /* PVP0 THCn RLE Vertical Position */
-#define REG_PVP0_THC1_RVPOS             0xFFC1A574         /* PVP0 THCn RLE Vertical Position */
-#define REG_PVP0_THC0_RHCNT             0xFFC1A478         /* PVP0 THCn RLE Horizontal Count */
-#define REG_PVP0_THC1_RHCNT             0xFFC1A578         /* PVP0 THCn RLE Horizontal Count */
-#define REG_PVP0_THC0_RVCNT             0xFFC1A47C         /* PVP0 THCn RLE Vertical Count */
-#define REG_PVP0_THC1_RVCNT             0xFFC1A57C         /* PVP0 THCn RLE Vertical Count */
-#define REG_PVP0_THC0_HFCNT_STAT        0xFFC1A480         /* PVP0 THCn Histogram Frame Count Status */
-#define REG_PVP0_THC1_HFCNT_STAT        0xFFC1A580         /* PVP0 THCn Histogram Frame Count Status */
-#define REG_PVP0_THC0_HCNT0_STAT        0xFFC1A484         /* PVP0 THCn Histogram Counter Value 0 */
-#define REG_PVP0_THC1_HCNT0_STAT        0xFFC1A584         /* PVP0 THCn Histogram Counter Value 0 */
-#define REG_PVP0_THC0_HCNT1_STAT        0xFFC1A488         /* PVP0 THCn Histogram Counter Value 1 */
-#define REG_PVP0_THC1_HCNT1_STAT        0xFFC1A588         /* PVP0 THCn Histogram Counter Value 1 */
-#define REG_PVP0_THC0_HCNT2_STAT        0xFFC1A48C         /* PVP0 THCn Histogram Counter Value 2 */
-#define REG_PVP0_THC1_HCNT2_STAT        0xFFC1A58C         /* PVP0 THCn Histogram Counter Value 2 */
-#define REG_PVP0_THC0_HCNT3_STAT        0xFFC1A490         /* PVP0 THCn Histogram Counter Value 3 */
-#define REG_PVP0_THC1_HCNT3_STAT        0xFFC1A590         /* PVP0 THCn Histogram Counter Value 3 */
-#define REG_PVP0_THC0_HCNT4_STAT        0xFFC1A494         /* PVP0 THCn Histogram Counter Value 4 */
-#define REG_PVP0_THC1_HCNT4_STAT        0xFFC1A594         /* PVP0 THCn Histogram Counter Value 4 */
-#define REG_PVP0_THC0_HCNT5_STAT        0xFFC1A498         /* PVP0 THCn Histogram Counter Value 5 */
-#define REG_PVP0_THC1_HCNT5_STAT        0xFFC1A598         /* PVP0 THCn Histogram Counter Value 5 */
-#define REG_PVP0_THC0_HCNT6_STAT        0xFFC1A49C         /* PVP0 THCn Histogram Counter Value 6 */
-#define REG_PVP0_THC1_HCNT6_STAT        0xFFC1A59C         /* PVP0 THCn Histogram Counter Value 6 */
-#define REG_PVP0_THC0_HCNT7_STAT        0xFFC1A4A0         /* PVP0 THCn Histogram Counter Value 7 */
-#define REG_PVP0_THC1_HCNT7_STAT        0xFFC1A5A0         /* PVP0 THCn Histogram Counter Value 7 */
-#define REG_PVP0_THC0_HCNT8_STAT        0xFFC1A4A4         /* PVP0 THCn Histogram Counter Value 8 */
-#define REG_PVP0_THC1_HCNT8_STAT        0xFFC1A5A4         /* PVP0 THCn Histogram Counter Value 8 */
-#define REG_PVP0_THC0_HCNT9_STAT        0xFFC1A4A8         /* PVP0 THCn Histogram Counter Value 9 */
-#define REG_PVP0_THC1_HCNT9_STAT        0xFFC1A5A8         /* PVP0 THCn Histogram Counter Value 9 */
-#define REG_PVP0_THC0_HCNT10_STAT       0xFFC1A4AC         /* PVP0 THCn Histogram Counter Value 10 */
-#define REG_PVP0_THC1_HCNT10_STAT       0xFFC1A5AC         /* PVP0 THCn Histogram Counter Value 10 */
-#define REG_PVP0_THC0_HCNT11_STAT       0xFFC1A4B0         /* PVP0 THCn Histogram Counter Value 11 */
-#define REG_PVP0_THC1_HCNT11_STAT       0xFFC1A5B0         /* PVP0 THCn Histogram Counter Value 11 */
-#define REG_PVP0_THC0_HCNT12_STAT       0xFFC1A4B4         /* PVP0 THCn Histogram Counter Value 12 */
-#define REG_PVP0_THC1_HCNT12_STAT       0xFFC1A5B4         /* PVP0 THCn Histogram Counter Value 12 */
-#define REG_PVP0_THC0_HCNT13_STAT       0xFFC1A4B8         /* PVP0 THCn Histogram Counter Value 13 */
-#define REG_PVP0_THC1_HCNT13_STAT       0xFFC1A5B8         /* PVP0 THCn Histogram Counter Value 13 */
-#define REG_PVP0_THC0_HCNT14_STAT       0xFFC1A4BC         /* PVP0 THCn Histogram Counter Value 14 */
-#define REG_PVP0_THC1_HCNT14_STAT       0xFFC1A5BC         /* PVP0 THCn Histogram Counter Value 14 */
-#define REG_PVP0_THC0_HCNT15_STAT       0xFFC1A4C0         /* PVP0 THCn Histogram Counter Value 15 */
-#define REG_PVP0_THC1_HCNT15_STAT       0xFFC1A5C0         /* PVP0 THCn Histogram Counter Value 15 */
-#define REG_PVP0_THC0_RREP_STAT         0xFFC1A4C4         /* PVP0 THCn Number of RLE Reports */
-#define REG_PVP0_THC1_RREP_STAT         0xFFC1A5C4         /* PVP0 THCn Number of RLE Reports */
-#define REG_PVP0_PMA_CFG                0xFFC1A600         /* PVP0 PMA Configuration */
-
-/* =========================
-        PVP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_REVID_MAJOR                  4                               /* Major ID */
-#define BITP_PVP_REVID_REV                    0                               /* Revision ID for a given Major ID */
-#define BITM_PVP_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PVP_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID for a given Major ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CTL_CLKDIV                   4                               /* Clock Divisor */
-#define BITP_PVP_CTL_CPEN                     2                               /* Camera Pipe Enable */
-#define BITP_PVP_CTL_MPEN                     1                               /* Memory Pipe Enable */
-#define BITP_PVP_CTL_PVPEN                    0                               /* PVP Enable */
-
-#define BITM_PVP_CTL_CLKDIV                  (_ADI_MSK(0x00000010,uint32_t))  /* Clock Divisor */
-#define ENUM_PVP_CTL_CLKDIV1                 (_ADI_MSK(0x00000000,uint32_t))  /* CLKDIV: PVPCLK = SCLK0 */
-#define ENUM_PVP_CTL_CLKDIV2                 (_ADI_MSK(0x00000010,uint32_t))  /* CLKDIV: PVPCLK = SCLK0/2 */
-
-#define BITM_PVP_CTL_CPEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe Enable */
-#define ENUM_PVP_CTL_CPDIS                   (_ADI_MSK(0x00000000,uint32_t))  /* CPEN: Disable Camera Pipe */
-#define ENUM_PVP_CTL_CPEN                    (_ADI_MSK(0x00000004,uint32_t))  /* CPEN: Enable Camera Pipe */
-
-#define BITM_PVP_CTL_MPEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe Enable */
-#define ENUM_PVP_CTL_MPDIS                   (_ADI_MSK(0x00000000,uint32_t))  /* MPEN: Disable Memory Pipe */
-#define ENUM_PVP_CTL_MPEN                    (_ADI_MSK(0x00000002,uint32_t))  /* MPEN: Enable Memory Pipe */
-
-#define BITM_PVP_CTL_PVPEN                   (_ADI_MSK(0x00000001,uint32_t))  /* PVP Enable */
-#define ENUM_PVP_CTL_PVPDIS                  (_ADI_MSK(0x00000000,uint32_t))  /* PVPEN: Disable PVP */
-#define ENUM_PVP_CTL_PVPEN                   (_ADI_MSK(0x00000001,uint32_t))  /* PVPEN: Enable PVP */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IMSK_ACUSUMSAT              27                               /* ACU SUM Saturate Unmask */
-#define BITP_PVP_IMSK_ACUPRODSAT             26                               /* ACU PROD Saturate Unmask */
-#define BITP_PVP_IMSK_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Unmask */
-#define BITP_PVP_IMSK_ACUDIVERR              24                               /* ACU Divide By Zero Unmask */
-#define BITP_PVP_IMSK_IIM1SOVF               23                               /* IIM1 Signed Overflow Unmask */
-#define BITP_PVP_IMSK_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Unmask */
-#define BITP_PVP_IMSK_IIM0SOVF               21                               /* IIM0 Signed Overflow Unmask */
-#define BITP_PVP_IMSK_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Unmask */
-#define BITP_PVP_IMSK_THC1RDY                18                               /* THC1 Report Ready Unmask */
-#define BITP_PVP_IMSK_THC0RDY                16                               /* THC0 Report Ready Unmask */
-#define BITP_PVP_IMSK_MPRDY                  15                               /* Memory Pipe Ready Unmask */
-#define BITP_PVP_IMSK_CPRDY                  14                               /* Camera Pipe Ready Unmask */
-#define BITP_PVP_IMSK_MPDRN                  13                               /* Memory Pipe Drain Done Unmask */
-#define BITP_PVP_IMSK_CPDRN                  12                               /* Camera Pipe Drain Done Unmask */
-#define BITP_PVP_IMSK_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Unmask */
-#define BITP_PVP_IMSK_MPOPFDAT                9                               /* Memory Pipe First Pixel Unmask */
-#define BITP_PVP_IMSK_CPOPFDAT                8                               /* Camera Pipe First Pixel Unmask */
-#define BITP_PVP_IMSK_CPSTOVF                 7                               /* Status DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF2OVF                 6                               /* OPF2 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF1OVF                 5                               /* OPF1 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF0OVF                 4                               /* OPF0 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_MPWRERR                 3                               /* Memory Pipe MMR Write Error Unmask */
-#define BITP_PVP_IMSK_CPWRERR                 2                               /* Camera Pipe MMR Write Error Unmask */
-#define BITP_PVP_IMSK_MPDC                    1                               /* Memory Pipe DC Unmask */
-#define BITP_PVP_IMSK_CPDC                    0                               /* Camera Pipe DC Unmask */
-
-/* The fields and enumerations for PVP_IMSK are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_IMSK_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Unmask */
-#define BITM_PVP_IMSK_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Unmask */
-#define BITM_PVP_IMSK_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Unmask */
-#define BITM_PVP_IMSK_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Unmask */
-#define BITM_PVP_IMSK_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Unmask */
-#define BITM_PVP_IMSK_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Unmask */
-#define BITM_PVP_IMSK_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Unmask */
-#define BITM_PVP_IMSK_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Unmask */
-#define BITM_PVP_IMSK_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Unmask */
-#define BITM_PVP_IMSK_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Unmask */
-#define BITM_PVP_IMSK_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Unmask */
-#define BITM_PVP_IMSK_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Unmask */
-#define BITM_PVP_IMSK_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Unmask */
-#define BITM_PVP_IMSK_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Unmask */
-#define BITM_PVP_IMSK_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Unmask */
-#define BITM_PVP_IMSK_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Unmask */
-#define BITM_PVP_IMSK_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Unmask */
-#define BITM_PVP_IMSK_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Unmask */
-#define BITM_PVP_IMSK_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Unmask */
-#define BITM_PVP_IMSK_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Unmask */
-#define BITM_PVP_IMSK_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_STAT_ACUSUMSAT              27                               /* ACU SUM Saturate Status */
-#define BITP_PVP_STAT_ACUPRODSAT             26                               /* ACU PROD Saturate Status */
-#define BITP_PVP_STAT_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Status */
-#define BITP_PVP_STAT_ACUDIVERR              24                               /* ACU Divide By Zero Status */
-#define BITP_PVP_STAT_IIM1SOVF               23                               /* IIM1 Signed Overflow Status */
-#define BITP_PVP_STAT_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Status */
-#define BITP_PVP_STAT_IIM0SOVF               21                               /* IIM0 Signed Overflow Status */
-#define BITP_PVP_STAT_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Status */
-#define BITP_PVP_STAT_THC1RDY                18                               /* THC1 Report Ready Status */
-#define BITP_PVP_STAT_THC0RDY                16                               /* THC0 Report Ready Status */
-#define BITP_PVP_STAT_MPRDY                  15                               /* Memory Pipe Ready Status */
-#define BITP_PVP_STAT_CPRDY                  14                               /* Camera Pipe Ready Status */
-#define BITP_PVP_STAT_MPDRN                  13                               /* Memory Pipe Drain Done Status */
-#define BITP_PVP_STAT_CPDRN                  12                               /* Camera Pipe Drain Done Status */
-#define BITP_PVP_STAT_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Status */
-#define BITP_PVP_STAT_MPOPFDAT                9                               /* Memory Pipe First Pixel Status */
-#define BITP_PVP_STAT_CPOPFDAT                8                               /* Camera Pipe First Pixel Status */
-#define BITP_PVP_STAT_CPSTOVF                 7                               /* Camera Pipe DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF2OVF                 6                               /* OPF2 DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF1OVF                 5                               /* OPF1 DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF0OVF                 4                               /* OPF0 DDE Stall Error Status */
-#define BITP_PVP_STAT_MPWRERR                 3                               /* Memory Pipe MMR Write Error Status */
-#define BITP_PVP_STAT_CPWRERR                 2                               /* Camera Pipe MMR Write Error Status */
-#define BITP_PVP_STAT_MPDC                    1                               /* Memory Pipe DC Status */
-#define BITP_PVP_STAT_CPDC                    0                               /* Camera Pipe DC Status */
-
-#define BITM_PVP_STAT_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Status */
-#define ENUM_PVP_ACUSUMSAT_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUSUMSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUSUMSAT_HI                (_ADI_MSK(0x08000000,uint32_t))  /* ACUSUMSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Status */
-#define ENUM_PVP_ACUPRODSAT_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ACUPRODSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUPRODSAT_HI               (_ADI_MSK(0x04000000,uint32_t))  /* ACUPRODSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Status */
-#define ENUM_PVP_ACUOUTSAT_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUOUTSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUOUTSAT_HI                (_ADI_MSK(0x02000000,uint32_t))  /* ACUOUTSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Status */
-#define ENUM_PVP_ACUDIVERR_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUDIVERR: No Pending Interrupt */
-#define ENUM_PVP_ACUDIVERR_HI                (_ADI_MSK(0x01000000,uint32_t))  /* ACUDIVERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Status */
-#define ENUM_PVP_IIM1SOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM1SOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM1SOVF_HI                 (_ADI_MSK(0x00800000,uint32_t))  /* IIM1SOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Status */
-#define ENUM_PVP_IIM1UOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM1UOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM1UOVF_HI                 (_ADI_MSK(0x00400000,uint32_t))  /* IIM1UOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Status */
-#define ENUM_PVP_IIM0SOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM0SOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM0SOVF_HI                 (_ADI_MSK(0x00200000,uint32_t))  /* IIM0SOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Status */
-#define ENUM_PVP_IIM0UOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM0UOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM0UOVF_HI                 (_ADI_MSK(0x00100000,uint32_t))  /* IIM0UOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Status */
-#define ENUM_PVP_THC1RDY_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* THC1RDY: No Pending Interrupt */
-#define ENUM_PVP_THC1RDY_HI                  (_ADI_MSK(0x00040000,uint32_t))  /* THC1RDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Status */
-#define ENUM_PVP_THC0RDY_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* THC0RDY: No Pending Interrupt */
-#define ENUM_PVP_THC0RDY_HI                  (_ADI_MSK(0x00010000,uint32_t))  /* THC0RDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Status */
-#define ENUM_PVP_MPRDY_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* MPRDY: No Pending Interrupt */
-#define ENUM_PVP_MPRDY_HI                    (_ADI_MSK(0x00008000,uint32_t))  /* MPRDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Status */
-#define ENUM_PVP_CPRDY_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* CPRDY: No Pending Interrupt */
-#define ENUM_PVP_CPRDY_HI                    (_ADI_MSK(0x00004000,uint32_t))  /* CPRDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Status */
-#define ENUM_PVP_MPDRN_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* MPDRN: No Pending Interrupt */
-#define ENUM_PVP_MPDRN_HI                    (_ADI_MSK(0x00002000,uint32_t))  /* MPDRN: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Status */
-#define ENUM_PVP_CPDRN_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* CPDRN: No Pending Interrupt */
-#define ENUM_PVP_CPDRN_HI                    (_ADI_MSK(0x00001000,uint32_t))  /* CPDRN: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Status */
-#define ENUM_PVP_CPIPFOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* CPIPFOVF: No Pending Interrupt */
-#define ENUM_PVP_CPIPFOVF_HI                 (_ADI_MSK(0x00000400,uint32_t))  /* CPIPFOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Status */
-#define ENUM_PVP_MPOPFDAT_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* MPOPFDAT: No Pending Interrupt */
-#define ENUM_PVP_MPOPFDAT_HI                 (_ADI_MSK(0x00000200,uint32_t))  /* MPOPFDAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Status */
-#define ENUM_PVP_CPOPFDAT_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* CPOPFDAT: No Pending Interrupt */
-#define ENUM_PVP_CPOPFDAT_HI                 (_ADI_MSK(0x00000100,uint32_t))  /* CPOPFDAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Camera Pipe DDE Stall Error Status */
-#define ENUM_PVP_CPSTOVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* CPSTOVF: No Pending Interrupt */
-#define ENUM_PVP_CPSTOVF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* CPSTOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Status */
-#define ENUM_PVP_OPF2OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF2OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF2OVF_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* OPF2OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Status */
-#define ENUM_PVP_OPF1OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF1OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF1OVF_HI                  (_ADI_MSK(0x00000020,uint32_t))  /* OPF1OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Status */
-#define ENUM_PVP_OPF0OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF0OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF0OVF_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* OPF0OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Status */
-#define ENUM_PVP_MPWRERR_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MPWRERR: No Pending Interrupt */
-#define ENUM_PVP_MPWRERR_HI                  (_ADI_MSK(0x00000008,uint32_t))  /* MPWRERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Status */
-#define ENUM_PVP_CPWRERR_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* CPWRERR: No Pending Interrupt */
-#define ENUM_PVP_CPWRERR_HI                  (_ADI_MSK(0x00000004,uint32_t))  /* CPWRERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Status */
-#define ENUM_PVP_MPDC_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* MPDC: No Pending Interrupt */
-#define ENUM_PVP_MPDC_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* MPDC: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Status */
-#define ENUM_PVP_CPDC_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* CPDC: No Pending Interrupt */
-#define ENUM_PVP_CPDC_HI                     (_ADI_MSK(0x00000001,uint32_t))  /* CPDC: Pending Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ILAT_ACUSUMSAT              27                               /* ACU SUM Saturate Latch */
-#define BITP_PVP_ILAT_ACUPRODSAT             26                               /* ACU PROD Saturate Latch */
-#define BITP_PVP_ILAT_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Latch */
-#define BITP_PVP_ILAT_ACUDIVERR              24                               /* ACU Divide By Zero Latch */
-#define BITP_PVP_ILAT_IIM1SOVF               23                               /* IIM1 Signed Overflow Latch */
-#define BITP_PVP_ILAT_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Latch */
-#define BITP_PVP_ILAT_IIM0SOVF               21                               /* IIM0 Signed Overflow Latch */
-#define BITP_PVP_ILAT_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Latch */
-#define BITP_PVP_ILAT_THC1RDY                18                               /* THC1 Report Ready Latch */
-#define BITP_PVP_ILAT_THC0RDY                16                               /* THC0 Report Ready Latch */
-#define BITP_PVP_ILAT_MPRDY                  15                               /* Memory Pipe Ready Latch */
-#define BITP_PVP_ILAT_CPRDY                  14                               /* Camera Pipe Ready Latch */
-#define BITP_PVP_ILAT_MPDRN                  13                               /* Memory Pipe Drain Done Latch */
-#define BITP_PVP_ILAT_CPDRN                  12                               /* Camera Pipe Drain Done Latch */
-#define BITP_PVP_ILAT_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Latch */
-#define BITP_PVP_ILAT_MPOPFDAT                9                               /* Memory Pipe First Pixel Latch */
-#define BITP_PVP_ILAT_CPOPFDAT                8                               /* Camera Pipe First Pixel Latch */
-#define BITP_PVP_ILAT_CPSTOVF                 7                               /* Status DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF2OVF                 6                               /* OPF2 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF1OVF                 5                               /* OPF1 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF0OVF                 4                               /* OPF0 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_MPWRERR                 3                               /* Memory Pipe MMR Write Error Latch */
-#define BITP_PVP_ILAT_CPWRERR                 2                               /* Camera Pipe MMR Write Error Latch */
-#define BITP_PVP_ILAT_MPDC                    1                               /* Memory Pipe DC Mask */
-#define BITP_PVP_ILAT_CPDC                    0                               /* Camera Pipe DC Latch */
-
-/* The fields and enumerations for PVP_ILAT are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_ILAT_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Latch */
-#define BITM_PVP_ILAT_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Latch */
-#define BITM_PVP_ILAT_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Latch */
-#define BITM_PVP_ILAT_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Latch */
-#define BITM_PVP_ILAT_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Latch */
-#define BITM_PVP_ILAT_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Latch */
-#define BITM_PVP_ILAT_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Latch */
-#define BITM_PVP_ILAT_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Latch */
-#define BITM_PVP_ILAT_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Latch */
-#define BITM_PVP_ILAT_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Latch */
-#define BITM_PVP_ILAT_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Latch */
-#define BITM_PVP_ILAT_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Latch */
-#define BITM_PVP_ILAT_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Latch */
-#define BITM_PVP_ILAT_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Latch */
-#define BITM_PVP_ILAT_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Latch */
-#define BITM_PVP_ILAT_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Latch */
-#define BITM_PVP_ILAT_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Latch */
-#define BITM_PVP_ILAT_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Latch */
-#define BITM_PVP_ILAT_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Latch */
-#define BITM_PVP_ILAT_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Mask */
-#define BITM_PVP_ILAT_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IREQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IREQ_ACUSUMSAT              27                               /* ACU SUM Saturate Request */
-#define BITP_PVP_IREQ_ACUPRODSAT             26                               /* ACU PROD Saturate Request */
-#define BITP_PVP_IREQ_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Request */
-#define BITP_PVP_IREQ_ACUDIVERR              24                               /* ACU Divide By Zero Request */
-#define BITP_PVP_IREQ_IIM1SOVF               23                               /* IIM1 Signed Overflow Request */
-#define BITP_PVP_IREQ_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Request */
-#define BITP_PVP_IREQ_IIM0SOVF               21                               /* IIM0 Signed Overflow Request */
-#define BITP_PVP_IREQ_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Request */
-#define BITP_PVP_IREQ_THC1RDY                18                               /* THC1 Report Ready Request */
-#define BITP_PVP_IREQ_THC0RDY                16                               /* THC0 Report Ready Request */
-#define BITP_PVP_IREQ_MPRDY                  15                               /* Memory Pipe Ready Request */
-#define BITP_PVP_IREQ_CPRDY                  14                               /* Camera Pipe Ready Request */
-#define BITP_PVP_IREQ_MPDRN                  13                               /* Memory Pipe Drain Done Request */
-#define BITP_PVP_IREQ_CPDRN                  12                               /* Camera Pipe Drain Done Request */
-#define BITP_PVP_IREQ_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Request */
-#define BITP_PVP_IREQ_MPOPFDAT                9                               /* Memory Pipe First Pixel Request */
-#define BITP_PVP_IREQ_CPOPFDAT                8                               /* Camera Pipe First Pixel Request */
-#define BITP_PVP_IREQ_CPSTOVF                 7                               /* Status DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF2OVF                 6                               /* OPF2 DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF1OVF                 5                               /* OPF1 DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF0OVF                 4                               /* OPF0 DDE Stall Error Request */
-#define BITP_PVP_IREQ_MPWRERR                 3                               /* Memory Pipe MMR Write Error Request */
-#define BITP_PVP_IREQ_CPWRERR                 2                               /* Camera Pipe MMR Write Error Request */
-#define BITP_PVP_IREQ_MPDC                    1                               /* Memory Pipe DC Request */
-#define BITP_PVP_IREQ_CPDC                    0                               /* Camera Pipe DC Request */
-
-/* The fields and enumerations for PVP_IREQ are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_IREQ_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Request */
-#define BITM_PVP_IREQ_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Request */
-#define BITM_PVP_IREQ_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Request */
-#define BITM_PVP_IREQ_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Request */
-#define BITM_PVP_IREQ_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Request */
-#define BITM_PVP_IREQ_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Request */
-#define BITM_PVP_IREQ_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Request */
-#define BITM_PVP_IREQ_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Request */
-#define BITM_PVP_IREQ_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Request */
-#define BITM_PVP_IREQ_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Request */
-#define BITM_PVP_IREQ_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Request */
-#define BITM_PVP_IREQ_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Request */
-#define BITM_PVP_IREQ_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Request */
-#define BITM_PVP_IREQ_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Request */
-#define BITM_PVP_IREQ_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Request */
-#define BITM_PVP_IREQ_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Request */
-#define BITM_PVP_IREQ_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Request */
-#define BITM_PVP_IREQ_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Request */
-#define BITM_PVP_IREQ_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Request */
-#define BITM_PVP_IREQ_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Request */
-#define BITM_PVP_IREQ_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Request */
-#define BITM_PVP_IREQ_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_OPF_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_OPF_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_OPF_CFG_START                0                               /* Start */
-#define BITM_PVP_OPF_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_OPF_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_OPF_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_OPF_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF_CTL_FINISH              12                               /* Finish Enable */
-#define BITP_PVP_OPF_CTL_OSIZE                8                               /* Output Data Size */
-#define BITP_PVP_OPF_CTL_QFRMT                5                               /* Q Format Correction */
-#define BITP_PVP_OPF_CTL_IUP16                4                               /* Input Upper 16-Bit Data */
-#define BITP_PVP_OPF_CTL_ISIZE                0                               /* Input Data Size */
-
-#define BITM_PVP_OPF_CTL_FINISH              (_ADI_MSK(0x00001000,uint32_t))  /* Finish Enable */
-#define ENUM_PVP_OPF_CTL_NOFINISH            (_ADI_MSK(0x00000000,uint32_t))  /* FINISH: Disable Finish Signal */
-#define ENUM_PVP_OPF_CTL_FINISH              (_ADI_MSK(0x00001000,uint32_t))  /* FINISH: Enable Finish Signal */
-
-#define BITM_PVP_OPF_CTL_OSIZE               (_ADI_MSK(0x00000300,uint32_t))  /* Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE32             (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 32-Bit Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE16             (_ADI_MSK(0x00000100,uint32_t))  /* OSIZE: 16-Bit Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE8              (_ADI_MSK(0x00000200,uint32_t))  /* OSIZE: 8-Bit Output Data Size */
-
-#define BITM_PVP_OPF_CTL_QFRMT               (_ADI_MSK(0x00000020,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_OPF_CTL_NOQFRMT             (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_OPF_CTL_QFRMT               (_ADI_MSK(0x00000020,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_OPF_CTL_IUP16               (_ADI_MSK(0x00000010,uint32_t))  /* Input Upper 16-Bit Data */
-#define ENUM_PVP_OPF_CTL_LOWER16             (_ADI_MSK(0x00000000,uint32_t))  /* IUP16: Lower 16 Bits */
-#define ENUM_PVP_OPF_CTL_UPPER16             (_ADI_MSK(0x00000010,uint32_t))  /* IUP16: Upper 16 Bits */
-
-#define BITM_PVP_OPF_CTL_ISIZE               (_ADI_MSK(0x00000003,uint32_t))  /* Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE32             (_ADI_MSK(0x00000000,uint32_t))  /* ISIZE: 32-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE16             (_ADI_MSK(0x00000001,uint32_t))  /* ISIZE: 16-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE8              (_ADI_MSK(0x00000002,uint32_t))  /* ISIZE: 8-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE4              (_ADI_MSK(0x00000003,uint32_t))  /* ISIZE: 4-Bit Input Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF3_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF3_CFG_IBLOCK0             8                               /* Input Block ID */
-#define BITP_PVP_OPF3_CFG_IPORT0              4                               /* Input Port ID */
-#define BITP_PVP_OPF3_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_OPF3_CFG_START               0                               /* Start */
-#define BITM_PVP_OPF3_CFG_IBLOCK0            (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_OPF3_CFG_IPORT0             (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_OPF3_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_OPF3_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF3_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF3_CTL_FINISH             12                               /* Finish Enable */
-#define BITP_PVP_OPF3_CTL_OSIZE               8                               /* Output Data Size */
-#define BITP_PVP_OPF3_CTL_QFRMT               5                               /* Q Format Correction */
-#define BITP_PVP_OPF3_CTL_IUP16               4                               /* Input Upper 16-Bit Data */
-#define BITP_PVP_OPF3_CTL_ISIZE               0                               /* Input Data Size */
-
-#define BITM_PVP_OPF3_CTL_FINISH             (_ADI_MSK(0x00001000,uint32_t))  /* Finish Enable */
-#define ENUM_PVP_OPF3_CTL_NOFINISH           (_ADI_MSK(0x00000000,uint32_t))  /* FINISH: Disable Finish Signal */
-#define ENUM_PVP_OPF3_CTL_FINISH             (_ADI_MSK(0x00001000,uint32_t))  /* FINISH: Enable Finish Signal */
-
-#define BITM_PVP_OPF3_CTL_OSIZE              (_ADI_MSK(0x00000300,uint32_t))  /* Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE32            (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 32-Bit Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE16            (_ADI_MSK(0x00000100,uint32_t))  /* OSIZE: 16-Bit Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE8             (_ADI_MSK(0x00000200,uint32_t))  /* OSIZE: 8-Bit Output Data Size */
-
-#define BITM_PVP_OPF3_CTL_QFRMT              (_ADI_MSK(0x00000020,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_OPF3_CTL_NOQFRMT            (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_OPF3_CTL_QFRMT              (_ADI_MSK(0x00000020,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_OPF3_CTL_IUP16              (_ADI_MSK(0x00000010,uint32_t))  /* Input Upper 16-Bit Data */
-#define ENUM_PVP_OPF3_CTL_LOWER16            (_ADI_MSK(0x00000000,uint32_t))  /* IUP16: Lower 16 Bits */
-#define ENUM_PVP_OPF3_CTL_UPPER16            (_ADI_MSK(0x00000010,uint32_t))  /* IUP16: Upper 16 Bits */
-
-#define BITM_PVP_OPF3_CTL_ISIZE              (_ADI_MSK(0x00000003,uint32_t))  /* Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE32            (_ADI_MSK(0x00000000,uint32_t))  /* ISIZE: 32-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE16            (_ADI_MSK(0x00000001,uint32_t))  /* ISIZE: 16-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE8             (_ADI_MSK(0x00000002,uint32_t))  /* ISIZE: 8-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE4             (_ADI_MSK(0x00000003,uint32_t))  /* ISIZE: 4-Bit Input Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_PEC_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_PEC_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_PEC_CFG_START                0                               /* Start */
-#define BITM_PVP_PEC_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_PEC_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_PEC_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_PEC_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_PEC_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_PEC_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_CTL_IGNTH1               3                               /* Ignore TH1 Threshold for Encoding */
-#define BITP_PVP_PEC_CTL_OSIZE                2                               /* Output Data Size per Bin */
-#define BITP_PVP_PEC_CTL_ZCRSS                1                               /* Zero Cross */
-#define BITP_PVP_PEC_CTL_MODE                 0                               /* Derivative Mode Select */
-
-#define BITM_PVP_PEC_CTL_IGNTH1              (_ADI_MSK(0x00000008,uint32_t))  /* Ignore TH1 Threshold for Encoding */
-#define ENUM_PVP_PEC_CTL_ENCODEDIFF          (_ADI_MSK(0x00000000,uint32_t))  /* IGNTH1: Different Strong/Weak Edge Encoding */
-#define ENUM_PVP_PEC_CTL_ENCODESAME          (_ADI_MSK(0x00000008,uint32_t))  /* IGNTH1: Identical Strong/Weak Edge Encoding */
-
-#define BITM_PVP_PEC_CTL_OSIZE               (_ADI_MSK(0x00000004,uint32_t))  /* Output Data Size per Bin */
-#define ENUM_PVP_PEC_CTL_BIN8                (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 8 Bits Per Bin PEC Output Data Size */
-#define ENUM_PVP_PEC_CTL_BIN16               (_ADI_MSK(0x00000004,uint32_t))  /* OSIZE: 16 Bits Per Bin PEC Output Data Size */
-
-#define BITM_PVP_PEC_CTL_ZCRSS               (_ADI_MSK(0x00000002,uint32_t))  /* Zero Cross */
-#define ENUM_PVP_PEC_CTL_ANGLE               (_ADI_MSK(0x00000000,uint32_t))  /* ZCRSS: Angle Indices and Sub-Pixel Values */
-#define ENUM_PVP_PEC_CTL_ZEROCROSS           (_ADI_MSK(0x00000002,uint32_t))  /* ZCRSS: Zero Crossing Codes and Sub-Pixel Values */
-
-#define BITM_PVP_PEC_CTL_MODE                (_ADI_MSK(0x00000001,uint32_t))  /* Derivative Mode Select */
-#define ENUM_PVP_PEC_CTL_DERIV1              (_ADI_MSK(0x00000000,uint32_t))  /* MODE: 1st Derivative Mode */
-#define ENUM_PVP_PEC_CTL_DERIV2              (_ADI_MSK(0x00000001,uint32_t))  /* MODE: 2nd Derivative Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D1TH0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D1TH0_VALUE              0                               /* Lower Hysteresis Threshold */
-#define BITM_PVP_PEC_D1TH0_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lower Hysteresis Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D1TH1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D1TH1_VALUE              0                               /* Upper Hysteresis Threshold */
-#define BITM_PVP_PEC_D1TH1_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Upper Hysteresis Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D2TH0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D2TH0_VALUE              0                               /* Weak Zero Crossing Threshold */
-#define BITM_PVP_PEC_D2TH0_VALUE             (_ADI_MSK(0x00007FFF,uint32_t))  /* Weak Zero Crossing Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D2TH1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D2TH1_VALUE              0                               /* Strong Zero Crossing Threshold */
-#define BITM_PVP_PEC_D2TH1_VALUE             (_ADI_MSK(0x00007FFF,uint32_t))  /* Strong Zero Crossing Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_IIM_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_IIM_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_IIM_CFG_START                0                               /* Start */
-#define BITM_PVP_IIM_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_IIM_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_IIM_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_IIM_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_IIM_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_IIM_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_CTL_SHIFT                8                               /* Shift Select */
-#define BITP_PVP_IIM_CTL_WIDTH                2                               /* Width Select */
-#define BITP_PVP_IIM_CTL_MODE                 0                               /* Mode Select */
-#define BITM_PVP_IIM_CTL_SHIFT               (_ADI_MSK(0x00001F00,uint32_t))  /* Shift Select */
-
-#define BITM_PVP_IIM_CTL_WIDTH               (_ADI_MSK(0x0000000C,uint32_t))  /* Width Select */
-#define ENUM_PVP_IIM_CTL_SINGLE32            (_ADI_MSK(0x00000000,uint32_t))  /* WIDTH: Single 32 Bit */
-#define ENUM_PVP_IIM_CTL_DUAL16              (_ADI_MSK(0x00000004,uint32_t))  /* WIDTH: Dual 16 Bit */
-#define ENUM_PVP_IIM_CTL_QUAD8               (_ADI_MSK(0x0000000C,uint32_t))  /* WIDTH: Quad 8 Bit */
-
-#define BITM_PVP_IIM_CTL_MODE                (_ADI_MSK(0x00000003,uint32_t))  /* Mode Select */
-#define ENUM_PVP_IIM_CTL_RECTMODE            (_ADI_MSK(0x00000000,uint32_t))  /* MODE: Rectangular Mode ( SAT) */
-#define ENUM_PVP_IIM_CTL_DIAGMODE            (_ADI_MSK(0x00000001,uint32_t))  /* MODE: Diagonal Mode ( RSAT -45) */
-#define ENUM_PVP_IIM_CTL_ROWMODE             (_ADI_MSK(0x00000002,uint32_t))  /* MODE: Row Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_SCALE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_SCALE_VSCL              16                               /* Vertical Scaling Factor */
-#define BITP_PVP_IIM_SCALE_HSCL               0                               /* Horizontal Scaling Factor */
-#define BITM_PVP_IIM_SCALE_VSCL              (_ADI_MSK(0x01FF0000,uint32_t))  /* Vertical Scaling Factor */
-#define BITM_PVP_IIM_SCALE_HSCL              (_ADI_MSK(0x000003FF,uint32_t))  /* Horizontal Scaling Factor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_SOVF_STAT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_SOVF_STAT_VPOS          16                               /* Veritcal Pixel Coordinate */
-#define BITP_PVP_IIM_SOVF_STAT_HPOS           0                               /* Horizontal Pixel Coordinate */
-#define BITM_PVP_IIM_SOVF_STAT_VPOS          (_ADI_MSK(0x03FF0000,uint32_t))  /* Veritcal Pixel Coordinate */
-#define BITM_PVP_IIM_SOVF_STAT_HPOS          (_ADI_MSK(0x000007FF,uint32_t))  /* Horizontal Pixel Coordinate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_UOVF_STAT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_UOVF_STAT_VPOS          16                               /* Veritcal Pixel Coordinate */
-#define BITP_PVP_IIM_UOVF_STAT_HPOS           0                               /* Horizontal Pixel Coordinate */
-#define BITM_PVP_IIM_UOVF_STAT_VPOS          (_ADI_MSK(0x03FF0000,uint32_t))  /* Veritcal Pixel Coordinate */
-#define BITM_PVP_IIM_UOVF_STAT_HPOS          (_ADI_MSK(0x000007FF,uint32_t))  /* Horizontal Pixel Coordinate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_CFG_IBLOCK1             16                               /* Input Block 1 ID */
-#define BITP_PVP_ACU_CFG_IBLOCK0              8                               /* Input Block 0 ID */
-#define BITP_PVP_ACU_CFG_IPORT1               6                               /* Input Port 1 ID */
-#define BITP_PVP_ACU_CFG_IPORT0               4                               /* Input Port 0 ID */
-#define BITP_PVP_ACU_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_ACU_CFG_START                0                               /* Start */
-#define BITM_PVP_ACU_CFG_IBLOCK1             (_ADI_MSK(0x00FF0000,uint32_t))  /* Input Block 1 ID */
-#define BITM_PVP_ACU_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block 0 ID */
-#define BITM_PVP_ACU_CFG_IPORT1              (_ADI_MSK(0x000000C0,uint32_t))  /* Input Port 1 ID */
-#define BITM_PVP_ACU_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port 0 ID */
-
-#define BITM_PVP_ACU_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_ACU_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_ACU_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_ACU_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_CTL_SUMOP               28                               /* Sum Operation */
-#define BITP_PVP_ACU_CTL_SUMISW              27                               /* Sum Input Swap */
-#define BITP_PVP_ACU_CTL_SUMINP              24                               /* Sum Inputs for Adder */
-#define BITP_PVP_ACU_CTL_PRDOP               20                               /* Prod Operation */
-#define BITP_PVP_ACU_CTL_PRDISW              19                               /* Prod Input Swap */
-#define BITP_PVP_ACU_CTL_PRDINP              16                               /* Prod Inputs for Mult/Div */
-#define BITP_PVP_ACU_CTL_ACCFRAME            15                               /* Accumulator Frame */
-#define BITP_PVP_ACU_CTL_ACCINP               8                               /* Accumulator Input */
-#define BITP_PVP_ACU_CTL_SFTINP               0                               /* Shift Input */
-
-#define BITM_PVP_ACU_CTL_SUMOP               (_ADI_MSK(0x10000000,uint32_t))  /* Sum Operation */
-#define ENUM_PVP_ACU_CTL_ADD                 (_ADI_MSK(0x00000000,uint32_t))  /* SUMOP: Add */
-#define ENUM_PVP_ACU_CTL_SUBTRACT            (_ADI_MSK(0x10000000,uint32_t))  /* SUMOP: Subtract */
-
-#define BITM_PVP_ACU_CTL_SUMISW              (_ADI_MSK(0x08000000,uint32_t))  /* Sum Input Swap */
-#define ENUM_PVP_ACU_CTL_NOSWAPSUM           (_ADI_MSK(0x00000000,uint32_t))  /* SUMISW: Do Not Swap Operands */
-#define ENUM_PVP_ACU_CTL_SWAPSUM             (_ADI_MSK(0x08000000,uint32_t))  /* SUMISW: Swap Operands */
-
-#define BITM_PVP_ACU_CTL_SUMINP              (_ADI_MSK(0x03000000,uint32_t))  /* Sum Inputs for Adder */
-#define ENUM_PVP_ACU_CTL_SUMXY               (_ADI_MSK(0x00000000,uint32_t))  /* SUMINP: X,Y Inputs */
-#define ENUM_PVP_ACU_CTL_SUMXOFF             (_ADI_MSK(0x01000000,uint32_t))  /* SUMINP: X,OFFSET Inputs */
-#define ENUM_PVP_ACU_CTL_SUMYOFF             (_ADI_MSK(0x02000000,uint32_t))  /* SUMINP: Y,OFFSET Inputs */
-
-#define BITM_PVP_ACU_CTL_PRDOP               (_ADI_MSK(0x00300000,uint32_t))  /* Prod Operation */
-#define ENUM_PVP_ACU_CTL_MULTIPLY            (_ADI_MSK(0x00000000,uint32_t))  /* PRDOP: Multiply */
-#define ENUM_PVP_ACU_CTL_DIVQUOTIENT         (_ADI_MSK(0x00100000,uint32_t))  /* PRDOP: Divide with Quotient */
-#define ENUM_PVP_ACU_CTL_DIVMODULUS          (_ADI_MSK(0x00200000,uint32_t))  /* PRDOP: Divide with Modulus */
-
-#define BITM_PVP_ACU_CTL_PRDISW              (_ADI_MSK(0x00080000,uint32_t))  /* Prod Input Swap */
-#define ENUM_PVP_ACU_CTL_NOSWAPPROD          (_ADI_MSK(0x00000000,uint32_t))  /* PRDISW: Do Not Swap Operands */
-#define ENUM_PVP_ACU_CTL_SWAPPROD            (_ADI_MSK(0x00080000,uint32_t))  /* PRDISW: Swap Operands */
-
-#define BITM_PVP_ACU_CTL_PRDINP              (_ADI_MSK(0x00030000,uint32_t))  /* Prod Inputs for Mult/Div */
-#define ENUM_PVP_ACU_CTL_PRODXY              (_ADI_MSK(0x00000000,uint32_t))  /* PRDINP: X,Y Inputs */
-#define ENUM_PVP_ACU_CTL_PRODXFACT           (_ADI_MSK(0x00010000,uint32_t))  /* PRDINP: X,FACTOR Inputs */
-#define ENUM_PVP_ACU_CTL_PRODYFACT           (_ADI_MSK(0x00020000,uint32_t))  /* PRDINP: Y,FACTOR Inputs */
-#define ENUM_PVP_ACU_CTL_PRODSUMFACT         (_ADI_MSK(0x00030000,uint32_t))  /* PRDINP: SUM,FACTOR Inputs */
-
-#define BITM_PVP_ACU_CTL_ACCFRAME            (_ADI_MSK(0x00008000,uint32_t))  /* Accumulator Frame */
-#define ENUM_PVP_ACU_CTL_ACCUMROW            (_ADI_MSK(0x00000000,uint32_t))  /* ACCFRAME: Clear ACC After Row */
-#define ENUM_PVP_ACU_CTL_ACCUMFRAME          (_ADI_MSK(0x00008000,uint32_t))  /* ACCFRAME: Clear ACC After Frame */
-
-#define BITM_PVP_ACU_CTL_ACCINP              (_ADI_MSK(0x00000300,uint32_t))  /* Accumulator Input */
-#define ENUM_PVP_ACU_CTL_ACCUMX              (_ADI_MSK(0x00000000,uint32_t))  /* ACCINP: X Input */
-#define ENUM_PVP_ACU_CTL_ACCUMSUM            (_ADI_MSK(0x00000100,uint32_t))  /* ACCINP: SUM Input */
-#define ENUM_PVP_ACU_CTL_ACCUMPROD           (_ADI_MSK(0x00000200,uint32_t))  /* ACCINP: PROD Input */
-
-#define BITM_PVP_ACU_CTL_SFTINP              (_ADI_MSK(0x00000003,uint32_t))  /* Shift Input */
-#define ENUM_PVP_ACU_CTL_SHIFTXIN            (_ADI_MSK(0x00000000,uint32_t))  /* SFTINP: X Input */
-#define ENUM_PVP_ACU_CTL_SHIFTSUM            (_ADI_MSK(0x00000001,uint32_t))  /* SFTINP: SUM Result Input */
-#define ENUM_PVP_ACU_CTL_SHIFTPROD           (_ADI_MSK(0x00000002,uint32_t))  /* SFTINP: PROD Result Input */
-#define ENUM_PVP_ACU_CTL_SHIFTACC            (_ADI_MSK(0x00000003,uint32_t))  /* SFTINP: ACC Result Input */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_SHIFT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_SHIFT_VALUE              0                               /* SHIFT Constant */
-#define BITM_PVP_ACU_SHIFT_VALUE             (_ADI_MSK(0x0000003F,uint32_t))  /* SHIFT Constant */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_UDS_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_UDS_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_UDS_CFG_START                0                               /* Start */
-#define BITM_PVP_UDS_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_UDS_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_UDS_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_UDS_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_CTL_AAVG                 0                               /* Automatic Averaging */
-
-#define BITM_PVP_UDS_CTL_AAVG                (_ADI_MSK(0x00000001,uint32_t))  /* Automatic Averaging */
-#define ENUM_PVP_UDS_CTL_MANTAPS             (_ADI_MSK(0x00000000,uint32_t))  /* AAVG: Manual Filter Tap Selection */
-#define ENUM_PVP_UDS_CTL_AUTOTAPS            (_ADI_MSK(0x00000001,uint32_t))  /* AAVG: Auto Filter Tap Selection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_OHCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_OHCNT_VALUE              4                               /* H Dimension of Output Frame */
-#define BITM_PVP_UDS_OHCNT_VALUE             (_ADI_MSK(0x000000F0,uint32_t))  /* H Dimension of Output Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_OVCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_OVCNT_VALUE              4                               /* V Dimension of Output Frame */
-#define BITM_PVP_UDS_OVCNT_VALUE             (_ADI_MSK(0x000000F0,uint32_t))  /* V Dimension of Output Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_HAVG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_HAVG_VALUE               0                               /* H Filter Taps */
-#define BITM_PVP_UDS_HAVG_VALUE              (_ADI_MSK(0x000000FF,uint32_t))  /* H Filter Taps */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_VAVG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_VAVG_VALUE               0                               /* V Filter Taps */
-#define BITM_PVP_UDS_VAVG_VALUE              (_ADI_MSK(0x0000007F,uint32_t))  /* V Filter Taps */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_CFG_STATWCNT           24                               /* Camera Pipe DMA Status */
-#define BITP_PVP_IPF0_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_IPF0_CFG_START               0                               /* Start */
-#define BITM_PVP_IPF0_CFG_STATWCNT           (_ADI_MSK(0xFF000000,uint32_t))  /* Camera Pipe DMA Status */
-#define BITM_PVP_IPF0_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_IPF0_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_PIPECTL                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_PIPECTL_STATEN           4                               /* DMA Status Enable */
-#define BITP_PVP_IPF_PIPECTL_DRAIN            0                               /* Drain Enable */
-#define BITM_PVP_IPF_PIPECTL_STATEN          (_ADI_MSK(0x00000010,uint32_t))  /* DMA Status Enable */
-#define BITM_PVP_IPF_PIPECTL_DRAIN           (_ADI_MSK(0x00000001,uint32_t))  /* Drain Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_CTL_QFRMT               27                               /* Q Format Correction */
-#define BITP_PVP_IPF_CTL_SIGNEXT             26                               /* Sign Extend */
-#define BITP_PVP_IPF_CTL_EXTRED              25                               /* Extract Red/Green */
-#define BITP_PVP_IPF_CTL_UNPACK              24                               /* Unpack Incoming */
-#define BITP_PVP_IPF_CTL_CFRMT               16                               /* Color Space Format */
-#define BITP_PVP_IPF_CTL_OPORT2EN            12                               /* Output Port 2 Enable */
-#define BITP_PVP_IPF_CTL_OPORT1EN             8                               /* Output Port 1 Enable */
-#define BITP_PVP_IPF_CTL_OPORT0EN             4                               /* Output Port 0 Enable */
-
-#define BITM_PVP_IPF_CTL_QFRMT               (_ADI_MSK(0x08000000,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_IPF_CTL_NOQFRMT             (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_IPF_CTL_QFRMT               (_ADI_MSK(0x08000000,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_IPF_CTL_SIGNEXT             (_ADI_MSK(0x04000000,uint32_t))  /* Sign Extend */
-#define ENUM_PVP_IPF_CTL_ZEROEXT             (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Extend */
-#define ENUM_PVP_IPF_CTL_SIGNEXT             (_ADI_MSK(0x04000000,uint32_t))  /* SIGNEXT: Sign Extend */
-
-#define BITM_PVP_IPF_CTL_EXTRED              (_ADI_MSK(0x02000000,uint32_t))  /* Extract Red/Green */
-#define ENUM_PVP_IPF_CTL_EXTGREEN            (_ADI_MSK(0x00000000,uint32_t))  /* EXTRED: Extract Green */
-#define ENUM_PVP_IPF_CTL_EXTRED              (_ADI_MSK(0x02000000,uint32_t))  /* EXTRED: Extract Red */
-
-#define BITM_PVP_IPF_CTL_UNPACK              (_ADI_MSK(0x01000000,uint32_t))  /* Unpack Incoming */
-#define ENUM_PVP_IPF_CTL_UNPACKDIS           (_ADI_MSK(0x00000000,uint32_t))  /* UNPACK: No Unpacking */
-#define ENUM_PVP_IPF_CTL_UNPACKEN            (_ADI_MSK(0x01000000,uint32_t))  /* UNPACK: Unpack Data */
-
-#define BITM_PVP_IPF_CTL_CFRMT               (_ADI_MSK(0x001F0000,uint32_t))  /* Color Space Format */
-#define ENUM_PVP_IPF_CTL_RGB8                (_ADI_MSK(0x00000000,uint32_t))  /* CFRMT: RGB 8-Bit */
-#define ENUM_PVP_IPF_CTL_RGB888              (_ADI_MSK(0x00010000,uint32_t))  /* CFRMT: RGB 888 */
-#define ENUM_PVP_IPF_CTL_YUV8                (_ADI_MSK(0x00100000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 1 */
-#define ENUM_PVP_IPF_CTL_YUV8SPLT            (_ADI_MSK(0x00110000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 2 */
-#define ENUM_PVP_IPF_CTL_YUV8SUBSPLT         (_ADI_MSK(0x00120000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 3 */
-#define ENUM_PVP_IPF_CTL_YUV8IN16            (_ADI_MSK(0x00130000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Pair 16-Bit */
-#define ENUM_PVP_IPF_CTL_RGB565              (_ADI_MSK(0x00020000,uint32_t))  /* CFRMT: RGB 565 */
-#define ENUM_PVP_IPF_CTL_YUV16               (_ADI_MSK(0x00140000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 1 */
-#define ENUM_PVP_IPF_CTL_YUV16SPLT           (_ADI_MSK(0x00150000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 2 */
-#define ENUM_PVP_IPF_CTL_YUV16SUBSPLT        (_ADI_MSK(0x00160000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 3 */
-#define ENUM_PVP_IPF_CTL_Y8                  (_ADI_MSK(0x00180000,uint32_t))  /* CFRMT: Y Alone 8-Bit */
-#define ENUM_PVP_IPF_CTL_Y16                 (_ADI_MSK(0x00190000,uint32_t))  /* CFRMT: Y Alone 16-Bit */
-#define ENUM_PVP_IPF_CTL_Y24                 (_ADI_MSK(0x001A0000,uint32_t))  /* CFRMT: Y Alone 24-Bit */
-#define ENUM_PVP_IPF_CTL_WORD32              (_ADI_MSK(0x001B0000,uint32_t))  /* CFRMT: 32 Bit */
-#define ENUM_PVP_IPF_CTL_RGB666              (_ADI_MSK(0x00030000,uint32_t))  /* CFRMT: RGB 666 */
-#define ENUM_PVP_IPF_CTL_RGB16               (_ADI_MSK(0x00040000,uint32_t))  /* CFRMT: RGB 16-Bit */
-#define ENUM_PVP_IPF_CTL_BAYER1              (_ADI_MSK(0x00050000,uint32_t))  /* CFRMT: RGB Bayer Format Type-1 */
-#define ENUM_PVP_IPF_CTL_BAYER2              (_ADI_MSK(0x00060000,uint32_t))  /* CFRMT: RGB Bayer Format Type-2 */
-
-#define BITM_PVP_IPF_CTL_OPORT2EN            (_ADI_MSK(0x00001000,uint32_t))  /* Output Port 2 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT2DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT2EN: Disable OPORT2 */
-#define ENUM_PVP_IPF_CTL_OPORT2EVEN          (_ADI_MSK(0x00001000,uint32_t))  /* OPORT2EN: Enable OPORT2 (full resolution) */
-
-#define BITM_PVP_IPF_CTL_OPORT1EN            (_ADI_MSK(0x00000300,uint32_t))  /* Output Port 1 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT1DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT1EN: Disable OPORT1 */
-#define ENUM_PVP_IPF_CTL_OPORT1ODD           (_ADI_MSK(0x00000100,uint32_t))  /* OPORT1EN: Enable OPORT1 (full resolution) */
-#define ENUM_PVP_IPF_CTL_OPORT1WIN           (_ADI_MSK(0x00000200,uint32_t))  /* OPORT1EN: Enable OPORT1 (windowed resolution) */
-
-#define BITM_PVP_IPF_CTL_OPORT0EN            (_ADI_MSK(0x00000010,uint32_t))  /* Output Port 0 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT0DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT0EN: Disable OPORT0 */
-#define ENUM_PVP_IPF_CTL_OPORT0EN            (_ADI_MSK(0x00000010,uint32_t))  /* OPORT0EN: Enable OPORT0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_TAG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_TAG_VALUE                0                               /* TAG Value */
-#define BITM_PVP_IPF_TAG_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* TAG Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_HCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_HCNT_VALUE               0                               /* Effective Width of ROI */
-#define BITM_PVP_IPF_HCNT_VALUE              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Effective Width of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_VCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_VCNT_VALUE               0                               /* Effective Height of ROI */
-#define BITM_PVP_IPF_VCNT_VALUE              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Effective Height of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_HPOS                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_HPOS_VALUE              0                               /* Horizontal Delay of ROI */
-#define BITM_PVP_IPF0_HPOS_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_VPOS                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_VPOS_VALUE              0                               /* Vertical Delay of ROI */
-#define BITM_PVP_IPF0_VPOS_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_TAG_STAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_TAG_STAT_VALUE           0                               /* TAG Value */
-#define BITM_PVP_IPF_TAG_STAT_VALUE          (_ADI_MSK(0x0000FFFF,uint32_t))  /* TAG Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF1_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF1_CFG_STATWCNT           24                               /* Status Word Count */
-#define BITP_PVP_IPF1_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_IPF1_CFG_START               0                               /* Start */
-#define BITM_PVP_IPF1_CFG_STATWCNT           (_ADI_MSK(0xFF000000,uint32_t))  /* Status Word Count */
-#define BITM_PVP_IPF1_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_IPF1_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_CNV_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_CNV_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_CNV_CFG_START                0                               /* Start */
-#define BITM_PVP_CNV_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_CNV_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_CNV_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_CNV_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_CNV_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_CNV_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_CTL_SHIFT                4                               /* Shift Right */
-#define BITP_PVP_CNV_CTL_ZEROFILL             1                               /* Zero Fill */
-#define BITP_PVP_CNV_CTL_SAT32                0                               /* Saturate Output to 32 Bits */
-#define BITM_PVP_CNV_CTL_SHIFT               (_ADI_MSK(0x000001F0,uint32_t))  /* Shift Right */
-
-#define BITM_PVP_CNV_CTL_ZEROFILL            (_ADI_MSK(0x00000002,uint32_t))  /* Zero Fill */
-#define ENUM_PVP_CNV_CTL_EDGEDUP             (_ADI_MSK(0x00000000,uint32_t))  /* ZEROFILL: Duplicated Data Fill */
-#define ENUM_PVP_CNV_CTL_EDGEZFILL           (_ADI_MSK(0x00000002,uint32_t))  /* ZEROFILL: Zero Fill */
-
-#define BITM_PVP_CNV_CTL_SAT32               (_ADI_MSK(0x00000001,uint32_t))  /* Saturate Output to 32 Bits */
-#define ENUM_PVP_CNV_CTL_SIGNEXT             (_ADI_MSK(0x00000000,uint32_t))  /* SAT32: 16-Bit Saturate of Output */
-#define ENUM_PVP_CNV_CTL_SAT32               (_ADI_MSK(0x00000001,uint32_t))  /* SAT32: 32-Bit Saturate of Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C00C01                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C00C01_C01              16                               /* Coefficient 0, 1 */
-#define BITP_PVP_CNV_C00C01_C00               0                               /* Coefficient 0, 0 */
-#define BITM_PVP_CNV_C00C01_C01              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 0, 1 */
-#define BITM_PVP_CNV_C00C01_C00              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C02C03                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C02C03_C03              16                               /* Coefficient 0, 3 */
-#define BITP_PVP_CNV_C02C03_C02               0                               /* Coefficient 0, 2 */
-#define BITM_PVP_CNV_C02C03_C03              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 0, 3 */
-#define BITM_PVP_CNV_C02C03_C02              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C04                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C04_C04                  0                               /* Coefficient 0, 4 */
-#define BITM_PVP_CNV_C04_C04                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C10C11                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C10C11_C11              16                               /* Coefficient 1, 1 */
-#define BITP_PVP_CNV_C10C11_C10               0                               /* Coefficient 1, 0 */
-#define BITM_PVP_CNV_C10C11_C11              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 1, 1 */
-#define BITM_PVP_CNV_C10C11_C10              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C12C13                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C12C13_C13              16                               /* Coefficient 1, 3 */
-#define BITP_PVP_CNV_C12C13_C12               0                               /* Coefficient 1, 2 */
-#define BITM_PVP_CNV_C12C13_C13              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 1, 3 */
-#define BITM_PVP_CNV_C12C13_C12              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C14                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C14_C14                  0                               /* Coefficient 1, 4 */
-#define BITM_PVP_CNV_C14_C14                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C20C21                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C20C21_C21              16                               /* Coefficient 2, 1 */
-#define BITP_PVP_CNV_C20C21_C20               0                               /* Coefficient 2, 0 */
-#define BITM_PVP_CNV_C20C21_C21              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 2, 1 */
-#define BITM_PVP_CNV_C20C21_C20              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C22C23                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C22C23_C23              16                               /* Coefficient 2, 3 */
-#define BITP_PVP_CNV_C22C23_C22               0                               /* Coefficient 2, 2 */
-#define BITM_PVP_CNV_C22C23_C23              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 2, 3 */
-#define BITM_PVP_CNV_C22C23_C22              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C24                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C24_C24                  0                               /* Coefficient 2, 4 */
-#define BITM_PVP_CNV_C24_C24                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C30C31                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C30C31_C31              16                               /* Coefficient 3, 1 */
-#define BITP_PVP_CNV_C30C31_C30               0                               /* Coefficient 3, 0 */
-#define BITM_PVP_CNV_C30C31_C31              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 3, 1 */
-#define BITM_PVP_CNV_C30C31_C30              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C32C33                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C32C33_C33              16                               /* Coefficient 3, 3 */
-#define BITP_PVP_CNV_C32C33_C32               0                               /* Coefficient 3, 2 */
-#define BITM_PVP_CNV_C32C33_C33              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 3, 3 */
-#define BITM_PVP_CNV_C32C33_C32              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C34                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C34_C34                  0                               /* Coefficient 3, 4 */
-#define BITM_PVP_CNV_C34_C34                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C40C41                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C40C41_C41              16                               /* Coefficient 4, 1 */
-#define BITP_PVP_CNV_C40C41_C40               0                               /* Coefficient 4, 0 */
-#define BITM_PVP_CNV_C40C41_C41              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 4, 1 */
-#define BITM_PVP_CNV_C40C41_C40              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C42C43                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C42C43_C43              16                               /* Coefficient 4, 3 */
-#define BITP_PVP_CNV_C42C43_C42               0                               /* Coefficient 4, 2 */
-#define BITM_PVP_CNV_C42C43_C43              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 4, 3 */
-#define BITM_PVP_CNV_C42C43_C42              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C44                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C44_C44                  0                               /* Coefficient 4, 4 */
-#define BITM_PVP_CNV_C44_C44                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_SCALE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_SCALE_VSCL              16                               /* Vertical Scaling factor */
-#define BITP_PVP_CNV_SCALE_HSCL               0                               /* Horizontal Scaling factor */
-#define BITM_PVP_CNV_SCALE_VSCL              (_ADI_MSK(0x01FF0000,uint32_t))  /* Vertical Scaling factor */
-#define BITM_PVP_CNV_SCALE_HSCL              (_ADI_MSK(0x000003FF,uint32_t))  /* Horizontal Scaling factor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_THC_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_THC_CFG_STATWCNT            24                               /* Status Word Count */
-#define BITP_PVP_THC_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_THC_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_THC_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_THC_CFG_START                0                               /* Start */
-#define BITM_PVP_THC_CFG_STATWCNT            (_ADI_MSK(0xFF000000,uint32_t))  /* Status Word Count */
-#define BITM_PVP_THC_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_THC_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_THC_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_THC_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_THC_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_THC_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_THC_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_THC_CTL_HISTEN              16                               /* Histogram Counters Enable */
-#define BITP_PVP_THC_CTL_RLEWM               11                               /* Run-length Encoding Window Mode */
-#define BITP_PVP_THC_CTL_HISTWM               9                               /* Histogram Window Mode */
-#define BITP_PVP_THC_CTL_RLEFRAME             8                               /* Run-Length-Encode Frame */
-#define BITP_PVP_THC_CTL_OFRMT                4                               /* Output Format */
-#define BITP_PVP_THC_CTL_ZEXT                 2                               /* Zero Extend */
-#define BITP_PVP_THC_CTL_MODE                 0                               /* Mode */
-
-#define BITM_PVP_THC_CTL_HISTEN              (_ADI_MSK(0x00010000,uint32_t))  /* Histogram Counters Enable */
-#define ENUM_PVP_THC_CTL_HISTDIS             (_ADI_MSK(0x00000000,uint32_t))  /* HISTEN: Disable */
-#define ENUM_PVP_THC_CTL_HISTEN              (_ADI_MSK(0x00010000,uint32_t))  /* HISTEN: Enable */
-
-#define BITM_PVP_THC_CTL_RLEWM               (_ADI_MSK(0x00001800,uint32_t))  /* Run-length Encoding Window Mode */
-#define ENUM_PVP_THC_CTL_COMPFRAME           (_ADI_MSK(0x00000000,uint32_t))  /* RLEWM: Frame Compression */
-#define ENUM_PVP_THC_CTL_COMPWIN             (_ADI_MSK(0x00000800,uint32_t))  /* RLEWM: Window Compression */
-
-#define BITM_PVP_THC_CTL_HISTWM              (_ADI_MSK(0x00000600,uint32_t))  /* Histogram Window Mode */
-#define ENUM_PVP_THC_CTL_HISTFRAME           (_ADI_MSK(0x00000000,uint32_t))  /* HISTWM: Frame Histogram */
-#define ENUM_PVP_THC_CTL_HISTWIN             (_ADI_MSK(0x00000200,uint32_t))  /* HISTWM: Inside-Window Histogram */
-#define ENUM_PVP_THC_CTL_HISTOUTWIN          (_ADI_MSK(0x00000400,uint32_t))  /* HISTWM: Outside-Window Histogram */
-
-#define BITM_PVP_THC_CTL_RLEFRAME            (_ADI_MSK(0x00000100,uint32_t))  /* Run-Length-Encode Frame */
-#define ENUM_PVP_THC_CTL_RLELINE             (_ADI_MSK(0x00000000,uint32_t))  /* RLEFRAME: Row (Line) Compression */
-#define ENUM_PVP_THC_CTL_RLEFRAME            (_ADI_MSK(0x00000100,uint32_t))  /* RLEFRAME: Frame Compression */
-
-#define BITM_PVP_THC_CTL_OFRMT               (_ADI_MSK(0x000000F0,uint32_t))  /* Output Format */
-#define ENUM_PVP_THC_CTL_WORD32              (_ADI_MSK(0x00000000,uint32_t))  /* OFRMT: 32-Bit Word ( No Compression ) */
-#define ENUM_PVP_THC_CTL_NODATA              (_ADI_MSK(0x000000A0,uint32_t))  /* OFRMT: Disable Output/RLE */
-#define ENUM_PVP_THC_CTL_INDX4               (_ADI_MSK(0x00000020,uint32_t))  /* OFRMT: 4-Bit Index ( No Compression) */
-#define ENUM_PVP_THC_CTL_INDX4RL4            (_ADI_MSK(0x00000030,uint32_t))  /* OFRMT: 4-Bit Index / 4-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4ANGL4          (_ADI_MSK(0x00000040,uint32_t))  /* OFRMT: 4-Bit Index / 4-Bit angle ( No Compression) */
-#define ENUM_PVP_THC_CTL_INDX3RL5            (_ADI_MSK(0x00000050,uint32_t))  /* OFRMT: 3-Bit Index / 5-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4RL12           (_ADI_MSK(0x00000060,uint32_t))  /* OFRMT: 4-Bit Index / 12-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX3RL13           (_ADI_MSK(0x00000070,uint32_t))  /* OFRMT: 3-Bit Index / 13-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4RL21           (_ADI_MSK(0x00000080,uint32_t))  /* OFRMT: 4-Bit Index / 21-Bit Run Length */
-#define ENUM_PVP_THC_CTL_WORD16RL16          (_ADI_MSK(0x00000090,uint32_t))  /* OFRMT: 16-Bit Word / 16-Bit Run Length */
-
-#define BITM_PVP_THC_CTL_ZEXT                (_ADI_MSK(0x00000004,uint32_t))  /* Zero Extend */
-#define ENUM_PVP_THC_CTL_ZEXTDIS             (_ADI_MSK(0x00000000,uint32_t))  /* ZEXT: No Zero Extension */
-#define ENUM_PVP_THC_CTL_ZEXTEN              (_ADI_MSK(0x00000004,uint32_t))  /* ZEXT: Zero Extend */
-
-#define BITM_PVP_THC_CTL_MODE                (_ADI_MSK(0x00000003,uint32_t))  /* Mode */
-#define ENUM_PVP_THC_CTL_CLIPMODE            (_ADI_MSK(0x00000000,uint32_t))  /* MODE: Clipping/Saturation Mode */
-#define ENUM_PVP_THC_CTL_QUANTMODE           (_ADI_MSK(0x00000001,uint32_t))  /* MODE: Quantization Mode */
-#define ENUM_PVP_THC_CTL_HYSTMODE            (_ADI_MSK(0x00000002,uint32_t))  /* MODE: Hysteresis Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PMA_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PMA_CFG_IBLOCK1             16                               /* Input Block 1 ID */
-#define BITP_PVP_PMA_CFG_IBLOCK0              8                               /* Input Block 0 ID */
-#define BITP_PVP_PMA_CFG_IPORT1               6                               /* Input Port 1 ID */
-#define BITP_PVP_PMA_CFG_IPORT0               4                               /* Input Port 0 ID */
-#define BITP_PVP_PMA_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_PMA_CFG_START                0                               /* Start */
-#define BITM_PVP_PMA_CFG_IBLOCK1             (_ADI_MSK(0x00FF0000,uint32_t))  /* Input Block 1 ID */
-#define BITM_PVP_PMA_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block 0 ID */
-#define BITM_PVP_PMA_CFG_IPORT1              (_ADI_MSK(0x000000C0,uint32_t))  /* Input Port 1 ID */
-#define BITM_PVP_PMA_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port 0 ID */
-
-#define BITM_PVP_PMA_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_PMA_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_PMA_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_PMA_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ==================================================
-        Pulse-Width Modulator Registers
-   ================================================== */
-
-/* =========================
-        PWM0
-   ========================= */
-#define REG_PWM0_CTL                    0xFFC1B000         /* PWM0 Control Register */
-#define REG_PWM0_CHANCFG                0xFFC1B004         /* PWM0 Channel Config Register */
-#define REG_PWM0_TRIPCFG                0xFFC1B008         /* PWM0 Trip Config Register */
-#define REG_PWM0_STAT                   0xFFC1B00C         /* PWM0 Status Register */
-#define REG_PWM0_IMSK                   0xFFC1B010         /* PWM0 Interrupt Mask Register */
-#define REG_PWM0_ILAT                   0xFFC1B014         /* PWM0 Interrupt Latch Register */
-#define REG_PWM0_CHOPCFG                0xFFC1B018         /* PWM0 Chop Configuration Register */
-#define REG_PWM0_DT                     0xFFC1B01C         /* PWM0 Dead Time Register */
-#define REG_PWM0_SYNC_WID               0xFFC1B020         /* PWM0 Sync Pulse Width Register */
-#define REG_PWM0_TM0                    0xFFC1B024         /* PWM0 Timer 0 Period Register */
-#define REG_PWM0_TM1                    0xFFC1B028         /* PWM0 Timer 1 Period Register */
-#define REG_PWM0_TM2                    0xFFC1B02C         /* PWM0 Timer 2 Period Register */
-#define REG_PWM0_TM3                    0xFFC1B030         /* PWM0 Timer 3 Period Register */
-#define REG_PWM0_TM4                    0xFFC1B034         /* PWM0 Timer 4 Period Register */
-#define REG_PWM0_DLYA                   0xFFC1B038         /* PWM0 Channel A Delay Register */
-#define REG_PWM0_DLYB                   0xFFC1B03C         /* PWM0 Channel B Delay Register */
-#define REG_PWM0_DLYC                   0xFFC1B040         /* PWM0 Channel C Delay Register */
-#define REG_PWM0_DLYD                   0xFFC1B044         /* PWM0 Channel D Delay Register */
-#define REG_PWM0_ACTL                   0xFFC1B048         /* PWM0 Channel A Control Register */
-#define REG_PWM0_AH0                    0xFFC1B04C         /* PWM0 Channel A-High Duty-0 Register */
-#define REG_PWM0_AH1                    0xFFC1B050         /* PWM0 Channel A-High Duty-1 Register */
-#define REG_PWM0_AL0                    0xFFC1B05C         /* PWM0 Channel A-Low Duty-0 Register */
-#define REG_PWM0_AL1                    0xFFC1B060         /* PWM0 Channel A-Low Duty-1 Register */
-#define REG_PWM0_BCTL                   0xFFC1B064         /* PWM0 Channel B Control Register */
-#define REG_PWM0_BH0                    0xFFC1B068         /* PWM0 Channel B-High Duty-0 Register */
-#define REG_PWM0_BH1                    0xFFC1B06C         /* PWM0 Channel B-High Duty-1 Register */
-#define REG_PWM0_BL0                    0xFFC1B078         /* PWM0 Channel B-Low Duty-0 Register */
-#define REG_PWM0_BL1                    0xFFC1B07C         /* PWM0 Channel B-Low Duty-1 Register */
-#define REG_PWM0_CCTL                   0xFFC1B080         /* PWM0 Channel C Control Register */
-#define REG_PWM0_CH0                    0xFFC1B084         /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM0_CH1                    0xFFC1B088         /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM0_CL0                    0xFFC1B094         /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM0_CL1                    0xFFC1B098         /* PWM0 Channel C-Low Duty-1 Register */
-#define REG_PWM0_DCTL                   0xFFC1B09C         /* PWM0 Channel D Control Register */
-#define REG_PWM0_DH0                    0xFFC1B0A0         /* PWM0 Channel D-High Duty-0 Register */
-#define REG_PWM0_DH1                    0xFFC1B0A4         /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM0_DL0                    0xFFC1B0B0         /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM0_DL1                    0xFFC1B0B4         /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM1
-   ========================= */
-#define REG_PWM1_CTL                    0xFFC1B400         /* PWM1 Control Register */
-#define REG_PWM1_CHANCFG                0xFFC1B404         /* PWM1 Channel Config Register */
-#define REG_PWM1_TRIPCFG                0xFFC1B408         /* PWM1 Trip Config Register */
-#define REG_PWM1_STAT                   0xFFC1B40C         /* PWM1 Status Register */
-#define REG_PWM1_IMSK                   0xFFC1B410         /* PWM1 Interrupt Mask Register */
-#define REG_PWM1_ILAT                   0xFFC1B414         /* PWM1 Interrupt Latch Register */
-#define REG_PWM1_CHOPCFG                0xFFC1B418         /* PWM1 Chop Configuration Register */
-#define REG_PWM1_DT                     0xFFC1B41C         /* PWM1 Dead Time Register */
-#define REG_PWM1_SYNC_WID               0xFFC1B420         /* PWM1 Sync Pulse Width Register */
-#define REG_PWM1_TM0                    0xFFC1B424         /* PWM1 Timer 0 Period Register */
-#define REG_PWM1_TM1                    0xFFC1B428         /* PWM1 Timer 1 Period Register */
-#define REG_PWM1_TM2                    0xFFC1B42C         /* PWM1 Timer 2 Period Register */
-#define REG_PWM1_TM3                    0xFFC1B430         /* PWM1 Timer 3 Period Register */
-#define REG_PWM1_TM4                    0xFFC1B434         /* PWM1 Timer 4 Period Register */
-#define REG_PWM1_DLYA                   0xFFC1B438         /* PWM1 Channel A Delay Register */
-#define REG_PWM1_DLYB                   0xFFC1B43C         /* PWM1 Channel B Delay Register */
-#define REG_PWM1_DLYC                   0xFFC1B440         /* PWM1 Channel C Delay Register */
-#define REG_PWM1_DLYD                   0xFFC1B444         /* PWM1 Channel D Delay Register */
-#define REG_PWM1_ACTL                   0xFFC1B448         /* PWM1 Channel A Control Register */
-#define REG_PWM1_AH0                    0xFFC1B44C         /* PWM1 Channel A-High Duty-0 Register */
-#define REG_PWM1_AH1                    0xFFC1B450         /* PWM1 Channel A-High Duty-1 Register */
-#define REG_PWM1_AL0                    0xFFC1B45C         /* PWM1 Channel A-Low Duty-0 Register */
-#define REG_PWM1_AL1                    0xFFC1B460         /* PWM1 Channel A-Low Duty-1 Register */
-#define REG_PWM1_BCTL                   0xFFC1B464         /* PWM1 Channel B Control Register */
-#define REG_PWM1_BH0                    0xFFC1B468         /* PWM1 Channel B-High Duty-0 Register */
-#define REG_PWM1_BH1                    0xFFC1B46C         /* PWM1 Channel B-High Duty-1 Register */
-#define REG_PWM1_BL0                    0xFFC1B478         /* PWM1 Channel B-Low Duty-0 Register */
-#define REG_PWM1_BL1                    0xFFC1B47C         /* PWM1 Channel B-Low Duty-1 Register */
-#define REG_PWM1_CCTL                   0xFFC1B480         /* PWM1 Channel C Control Register */
-#define REG_PWM1_CH0                    0xFFC1B484         /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM1_CH1                    0xFFC1B488         /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM1_CL0                    0xFFC1B494         /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM1_CL1                    0xFFC1B498         /* PWM1 Channel C-Low Duty-1 Register */
-#define REG_PWM1_DCTL                   0xFFC1B49C         /* PWM1 Channel D Control Register */
-#define REG_PWM1_DH0                    0xFFC1B4A0         /* PWM1 Channel D-High Duty-0 Register */
-#define REG_PWM1_DH1                    0xFFC1B4A4         /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM1_DL0                    0xFFC1B4B0         /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM1_DL1                    0xFFC1B4B4         /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CTL_INTSYNCREF              18                               /* Timer reference for Internal Sync */
-#define BITP_PWM_CTL_EXTSYNCSEL              17                               /* External Sync Select */
-#define BITP_PWM_CTL_EXTSYNC                 16                               /* External Sync */
-#define BITP_PWM_CTL_DLYDEN                   7                               /* Enable Delay Counter for Channel D */
-#define BITP_PWM_CTL_DLYCEN                   6                               /* Enable Delay Counter for Channel C */
-#define BITP_PWM_CTL_DLYBEN                   5                               /* Enable Delay Counter for Channel B */
-#define BITP_PWM_CTL_DLYAEN                   4                               /* Enable Delay Counter for Channel A */
-#define BITP_PWM_CTL_SWTRIP                   2                               /* Software Trip */
-#define BITP_PWM_CTL_EMURUN                   1                               /* Output Behavior During Emulation Mode */
-#define BITP_PWM_CTL_GLOBEN                   0                               /* Module Enable */
-
-#define BITM_PWM_CTL_INTSYNCREF              (_ADI_MSK(0x001C0000,uint32_t))  /* Timer reference for Internal Sync */
-#define ENUM_PWM_CTL_INTSYNC_0               (_ADI_MSK(0x00000000,uint32_t))  /* INTSYNCREF: PWMTMR0 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_1               (_ADI_MSK(0x00040000,uint32_t))  /* INTSYNCREF: PWMTMR1 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_2               (_ADI_MSK(0x00080000,uint32_t))  /* INTSYNCREF: PWMTMR2 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_3               (_ADI_MSK(0x000C0000,uint32_t))  /* INTSYNCREF: PWMTMR3 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_4               (_ADI_MSK(0x00100000,uint32_t))  /* INTSYNCREF: PWMTMR4 provides sync reference */
-
-#define BITM_PWM_CTL_EXTSYNCSEL              (_ADI_MSK(0x00020000,uint32_t))  /* External Sync Select */
-#define ENUM_PWM_CTL_EXTSYNC_ASYNC           (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNCSEL: Asynchronous External Sync */
-#define ENUM_PWM_CTL_EXTSYNC_SYNC            (_ADI_MSK(0x00020000,uint32_t))  /* EXTSYNCSEL: Synchronous External Sync */
-
-#define BITM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* External Sync */
-#define ENUM_PWM_CTL_INTSYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNC: Internal sync used */
-#define ENUM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* EXTSYNC: External sync used */
-
-#define BITM_PWM_CTL_DLYDEN                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Delay Counter for Channel D */
-#define ENUM_PWM_CTL_DLYD_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYDEN: Disable */
-#define ENUM_PWM_CTL_DLYD_EN                 (_ADI_MSK(0x00000080,uint32_t))  /* DLYDEN: Enable */
-
-#define BITM_PWM_CTL_DLYCEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Delay Counter for Channel C */
-#define ENUM_PWM_CTL_DLYC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYCEN: Disable */
-#define ENUM_PWM_CTL_DLYC_EN                 (_ADI_MSK(0x00000040,uint32_t))  /* DLYCEN: Enable */
-
-#define BITM_PWM_CTL_DLYBEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Delay Counter for Channel B */
-#define ENUM_PWM_CTL_DLYB_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYBEN: Disable */
-#define ENUM_PWM_CTL_DLYB_EN                 (_ADI_MSK(0x00000020,uint32_t))  /* DLYBEN: Enable */
-
-#define BITM_PWM_CTL_DLYAEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable Delay Counter for Channel A */
-#define ENUM_PWM_CTL_DLYA_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYAEN: Disable */
-#define ENUM_PWM_CTL_DLYA_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* DLYAEN: Enable */
-
-#define BITM_PWM_CTL_SWTRIP                  (_ADI_MSK(0x00000004,uint32_t))  /* Software Trip */
-#define ENUM_PWM_CTL_FORCE_TRIP              (_ADI_MSK(0x00000004,uint32_t))  /* SWTRIP: Force a Fault Trip Condition */
-
-#define BITM_PWM_CTL_EMURUN                  (_ADI_MSK(0x00000002,uint32_t))  /* Output Behavior During Emulation Mode */
-#define ENUM_PWM_CTL_EMURUN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* EMURUN: Disable Outputs */
-#define ENUM_PWM_CTL_EMURUN_EN               (_ADI_MSK(0x00000002,uint32_t))  /* EMURUN: Enable Outputs */
-
-#define BITM_PWM_CTL_GLOBEN                  (_ADI_MSK(0x00000001,uint32_t))  /* Module Enable */
-#define ENUM_PWM_CTL_PWM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* GLOBEN: Disable */
-#define ENUM_PWM_CTL_PWM_EN                  (_ADI_MSK(0x00000001,uint32_t))  /* GLOBEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHANCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHANCFG_ENCHOPDL            30                               /* Channel D Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLDL               29                               /* Channel D low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPDH            27                               /* Channel D Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLDH               26                               /* Channel D High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSD             25                               /* Channel D Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRD             24                               /* Channel D Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPCL            22                               /* Channel C Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLCL               21                               /* Channel C low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPCH            19                               /* Channel C Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLCH               18                               /* Channel C High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSC             17                               /* Channel C Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRC             16                               /* Channel C Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPBL            14                               /* Channel B Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLBL               13                               /* Channel B low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPBH            11                               /* Channel B Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLBH               10                               /* Channel B High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSB              9                               /* Channel B Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRB              8                               /* Channel B Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPAL             6                               /* Channel A Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLAL                5                               /* Channel A low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPAH             3                               /* Channel A Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLAH                2                               /* Channel A High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSA              1                               /* Channel A Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRA              0                               /* Channel A Timer Reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPDL            (_ADI_MSK(0x40000000,uint32_t))  /* Channel D Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDL: Disable Chopping Channel D Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_EN           (_ADI_MSK(0x40000000,uint32_t))  /* ENCHOPDL: Enable Chopping Channel D Low Side */
-
-#define BITM_PWM_CHANCFG_POLDL               (_ADI_MSK(0x20000000,uint32_t))  /* Channel D low side Polarity */
-#define ENUM_PWM_CHANCFG_DL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDL: Active Low */
-#define ENUM_PWM_CHANCFG_DL_ACTHI            (_ADI_MSK(0x20000000,uint32_t))  /* POLDL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPDH            (_ADI_MSK(0x08000000,uint32_t))  /* Channel D Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDH: Disable Chopping Channel D High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_EN           (_ADI_MSK(0x08000000,uint32_t))  /* ENCHOPDH: Enable Chopping Channel D High Side */
-
-#define BITM_PWM_CHANCFG_POLDH               (_ADI_MSK(0x04000000,uint32_t))  /* Channel D High side Polarity */
-#define ENUM_PWM_CHANCFG_DH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDH: Active Low */
-#define ENUM_PWM_CHANCFG_DH_ACTHI            (_ADI_MSK(0x04000000,uint32_t))  /* POLDH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSD             (_ADI_MSK(0x02000000,uint32_t))  /* Channel D Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOD_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSD: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOD_IND             (_ADI_MSK(0x02000000,uint32_t))  /* MODELSD: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRD             (_ADI_MSK(0x01000000,uint32_t))  /* Channel D Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRD: PWMTMR0 is Channel D reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_1           (_ADI_MSK(0x01000000,uint32_t))  /* REFTMRD: PWMTMR1 is Channel D reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPCL            (_ADI_MSK(0x00400000,uint32_t))  /* Channel C Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCL: Disable Chopping Channel C Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_EN           (_ADI_MSK(0x00400000,uint32_t))  /* ENCHOPCL: Enable Chopping Channel C Low Side */
-
-#define BITM_PWM_CHANCFG_POLCL               (_ADI_MSK(0x00200000,uint32_t))  /* Channel C low side Polarity */
-#define ENUM_PWM_CHANCFG_CL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCL: Active Low */
-#define ENUM_PWM_CHANCFG_CL_ACTHI            (_ADI_MSK(0x00200000,uint32_t))  /* POLCL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPCH            (_ADI_MSK(0x00080000,uint32_t))  /* Channel C Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCH: Disable Chopping Channel C High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_EN           (_ADI_MSK(0x00080000,uint32_t))  /* ENCHOPCH: Enable Chopping Channel C High Side */
-
-#define BITM_PWM_CHANCFG_POLCH               (_ADI_MSK(0x00040000,uint32_t))  /* Channel C High side Polarity */
-#define ENUM_PWM_CHANCFG_CH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCH: Active Low */
-#define ENUM_PWM_CHANCFG_CH_ACTHI            (_ADI_MSK(0x00040000,uint32_t))  /* POLCH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSC             (_ADI_MSK(0x00020000,uint32_t))  /* Channel C Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOC_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSC: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOC_IND             (_ADI_MSK(0x00020000,uint32_t))  /* MODELSC: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRC             (_ADI_MSK(0x00010000,uint32_t))  /* Channel C Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRC: PWMTMR0 is Channel C reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_1           (_ADI_MSK(0x00010000,uint32_t))  /* REFTMRC: PWMTMR1 is Channel C reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPBL            (_ADI_MSK(0x00004000,uint32_t))  /* Channel B Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBL: Disable Chopping Channel B Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_EN           (_ADI_MSK(0x00004000,uint32_t))  /* ENCHOPBL: Enable Chopping Channel B Low Side */
-
-#define BITM_PWM_CHANCFG_POLBL               (_ADI_MSK(0x00002000,uint32_t))  /* Channel B low side Polarity */
-#define ENUM_PWM_CHANCFG_BL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBL: Active Low */
-#define ENUM_PWM_CHANCFG_BL_ACTHI            (_ADI_MSK(0x00002000,uint32_t))  /* POLBL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPBH            (_ADI_MSK(0x00000800,uint32_t))  /* Channel B Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBH: Disable Chopping Channel B High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_EN           (_ADI_MSK(0x00000800,uint32_t))  /* ENCHOPBH: Enable Chopping Channel B High Side */
-
-#define BITM_PWM_CHANCFG_POLBH               (_ADI_MSK(0x00000400,uint32_t))  /* Channel B High side Polarity */
-#define ENUM_PWM_CHANCFG_BH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBH: Active Low */
-#define ENUM_PWM_CHANCFG_BH_ACTHI            (_ADI_MSK(0x00000400,uint32_t))  /* POLBH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSB             (_ADI_MSK(0x00000200,uint32_t))  /* Channel B Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOB_INV             (_ADI_MSK(0x00000000,uint32_t))  /* MODELSB: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOB_IND             (_ADI_MSK(0x00000200,uint32_t))  /* MODELSB: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRB             (_ADI_MSK(0x00000100,uint32_t))  /* Channel B Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRB: PWMTMR0 is Channel  B reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_1           (_ADI_MSK(0x00000100,uint32_t))  /* REFTMRB: PWMTMR1 is Channel B reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPAL            (_ADI_MSK(0x00000040,uint32_t))  /* Channel A Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAL: Disable Chopping Channel A Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_EN           (_ADI_MSK(0x00000040,uint32_t))  /* ENCHOPAL: Enable Chopping Channel A Low Side */
-
-#define BITM_PWM_CHANCFG_POLAL               (_ADI_MSK(0x00000020,uint32_t))  /* Channel A low side Polarity */
-#define ENUM_PWM_CHANCFG_AL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAL: Active Low */
-#define ENUM_PWM_CHANCFG_AL_ACTHI            (_ADI_MSK(0x00000020,uint32_t))  /* POLAL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPAH            (_ADI_MSK(0x00000008,uint32_t))  /* Channel A Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAH: Disable Chopping Channel A High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_EN           (_ADI_MSK(0x00000008,uint32_t))  /* ENCHOPAH: Enable Chopping Channel A High Side */
-
-#define BITM_PWM_CHANCFG_POLAH               (_ADI_MSK(0x00000004,uint32_t))  /* Channel A High side Polarity */
-#define ENUM_PWM_CHANCFG_AH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAH: Active Low */
-#define ENUM_PWM_CHANCFG_AH_ACTHI            (_ADI_MSK(0x00000004,uint32_t))  /* POLAH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSA             (_ADI_MSK(0x00000002,uint32_t))  /* Channel A Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOA_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSA: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOA_IND             (_ADI_MSK(0x00000002,uint32_t))  /* MODELSA: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRA             (_ADI_MSK(0x00000001,uint32_t))  /* Channel A Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRA: PWMTMR0 is Channel A reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_1           (_ADI_MSK(0x00000001,uint32_t))  /* REFTMRA: PWMTMR1 is Channel A reference */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TRIPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TRIPCFG_MODE1D              27                               /* Mode of TRIP1 for Channel D */
-#define BITP_PWM_TRIPCFG_EN1D                26                               /* Enable TRIP1 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE0D              25                               /* Mode of TRIP0 for Channel D */
-#define BITP_PWM_TRIPCFG_EN0D                24                               /* Enable TRIP0 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE1C              19                               /* Mode of TRIP1 for Channel C */
-#define BITP_PWM_TRIPCFG_EN1C                18                               /* Enable TRIP1 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE0C              17                               /* Mode of TRIP0 for Channel C */
-#define BITP_PWM_TRIPCFG_EN0C                16                               /* Enable TRIP0 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE1B              11                               /* Mode of TRIP1 for Channel B */
-#define BITP_PWM_TRIPCFG_EN1B                10                               /* Enable TRIP1 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE0B               9                               /* Mode of TRIP0 for Channel B */
-#define BITP_PWM_TRIPCFG_EN0B                 8                               /* Enable TRIP0 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE1A               3                               /* Mode of TRIP1 for Channel A */
-#define BITP_PWM_TRIPCFG_EN1A                 2                               /* Enable TRIP1 as a trip source for Channel A */
-#define BITP_PWM_TRIPCFG_MODE0A               1                               /* Mode of TRIP0 for Channel A */
-#define BITP_PWM_TRIPCFG_EN0A                 0                               /* Enable TRIP0 as a trip source for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE1D              (_ADI_MSK(0x08000000,uint32_t))  /* Mode of TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1D: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1D_RSTRT        (_ADI_MSK(0x08000000,uint32_t))  /* MODE1D: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1D                (_ADI_MSK(0x04000000,uint32_t))  /* Enable TRIP1 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1D: Disable TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_EN           (_ADI_MSK(0x04000000,uint32_t))  /* EN1D: Enable TRIP1 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE0D              (_ADI_MSK(0x02000000,uint32_t))  /* Mode of TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0D: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0D_RSTRT        (_ADI_MSK(0x02000000,uint32_t))  /* MODE0D: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0D                (_ADI_MSK(0x01000000,uint32_t))  /* Enable TRIP0 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0D: Disable TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_EN           (_ADI_MSK(0x01000000,uint32_t))  /* EN0D: Enable TRIP0 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE1C              (_ADI_MSK(0x00080000,uint32_t))  /* Mode of TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1C: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1C_RSTRT        (_ADI_MSK(0x00080000,uint32_t))  /* MODE1C: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1C                (_ADI_MSK(0x00040000,uint32_t))  /* Enable TRIP1 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1C: Disable TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_EN           (_ADI_MSK(0x00040000,uint32_t))  /* EN1C: Enable TRIP1 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE0C              (_ADI_MSK(0x00020000,uint32_t))  /* Mode of TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0C: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0C_RSTRT        (_ADI_MSK(0x00020000,uint32_t))  /* MODE0C: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0C                (_ADI_MSK(0x00010000,uint32_t))  /* Enable TRIP0 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0C: Disable TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_EN           (_ADI_MSK(0x00010000,uint32_t))  /* EN0C: Enable TRIP0 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE1B              (_ADI_MSK(0x00000800,uint32_t))  /* Mode of TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1B: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1B_RSTRT        (_ADI_MSK(0x00000800,uint32_t))  /* MODE1B: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1B                (_ADI_MSK(0x00000400,uint32_t))  /* Enable TRIP1 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1B: Disable TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_EN           (_ADI_MSK(0x00000400,uint32_t))  /* EN1B: Enable TRIP1 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE0B              (_ADI_MSK(0x00000200,uint32_t))  /* Mode of TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0B: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0B_RSTRT        (_ADI_MSK(0x00000200,uint32_t))  /* MODE0B: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0B                (_ADI_MSK(0x00000100,uint32_t))  /* Enable TRIP0 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0B: Disable TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_EN           (_ADI_MSK(0x00000100,uint32_t))  /* EN0B: Enable TRIP0 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE1A              (_ADI_MSK(0x00000008,uint32_t))  /* Mode of TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1A: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1A_RSTRT        (_ADI_MSK(0x00000008,uint32_t))  /* MODE1A: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1A                (_ADI_MSK(0x00000004,uint32_t))  /* Enable TRIP1 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1A: Disable TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_EN           (_ADI_MSK(0x00000004,uint32_t))  /* EN1A: Enable TRIP1 for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE0A              (_ADI_MSK(0x00000002,uint32_t))  /* Mode of TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0A: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0A_RSTRT        (_ADI_MSK(0x00000002,uint32_t))  /* MODE0A: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0A                (_ADI_MSK(0x00000001,uint32_t))  /* Enable TRIP0 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0A: Disable TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_EN           (_ADI_MSK(0x00000001,uint32_t))  /* EN0A: Enable TRIP0 for Channel A */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_STAT_TMR4PHASE              28                               /* PWMTMR4 Phase Status */
-#define BITP_PWM_STAT_TMR3PHASE              27                               /* PWMTMR3 Phase Status */
-#define BITP_PWM_STAT_TMR2PHASE              26                               /* PWMTMR2 Phase Status */
-#define BITP_PWM_STAT_TMR1PHASE              25                               /* PWMTMR1 Phase Status */
-#define BITP_PWM_STAT_TMR0PHASE              24                               /* PWMTMR0 Phase Status */
-#define BITP_PWM_STAT_TMR4PER                20                               /* PWMTMR4 Period Boundary Status */
-#define BITP_PWM_STAT_TMR3PER                19                               /* PWMTMR3 Period Boundary Status */
-#define BITP_PWM_STAT_TMR2PER                18                               /* PWMTMR2 Period Boundary Status */
-#define BITP_PWM_STAT_TMR1PER                17                               /* PWMTMR1 Period Boundary Status */
-#define BITP_PWM_STAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Status */
-#define BITP_PWM_STAT_SRTRIPD                11                               /* Self-Restart Trip Status for Channel D */
-#define BITP_PWM_STAT_FLTTRIPD               10                               /* Fault Trip Status for Channel D */
-#define BITP_PWM_STAT_SRTRIPC                 9                               /* Self-Restart Trip Status for Channel C */
-#define BITP_PWM_STAT_FLTTRIPC                8                               /* Fault Trip Status for Channel C */
-#define BITP_PWM_STAT_SRTRIPB                 7                               /* Self-Restart Trip Status for Channel B */
-#define BITP_PWM_STAT_FLTTRIPB                6                               /* Fault Trip Status for Channel B */
-#define BITP_PWM_STAT_SRTRIPA                 5                               /* Self-Restart Trip Status for Channel A */
-#define BITP_PWM_STAT_FLTTRIPA                4                               /* Fault Trip Status for Channel A */
-#define BITP_PWM_STAT_RAWTRIP1                3                               /* Raw Trip 1 Status */
-#define BITP_PWM_STAT_RAWTRIP0                2                               /* Raw Trip 0 Status */
-#define BITP_PWM_STAT_TRIP1                   1                               /* Status bit set when TRIP1 is active low */
-#define BITP_PWM_STAT_TRIP0                   0                               /* Status bit set when TRIP0 is active low */
-
-#define BITM_PWM_STAT_TMR4PHASE              (_ADI_MSK(0x10000000,uint32_t))  /* PWMTMR4 Phase Status */
-#define ENUM_PWM_STAT_TMR4PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR4PH2                (_ADI_MSK(0x10000000,uint32_t))  /* TMR4PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR3PHASE              (_ADI_MSK(0x08000000,uint32_t))  /* PWMTMR3 Phase Status */
-#define ENUM_PWM_STAT_TMR3PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR3PH2                (_ADI_MSK(0x08000000,uint32_t))  /* TMR3PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR2PHASE              (_ADI_MSK(0x04000000,uint32_t))  /* PWMTMR2 Phase Status */
-#define ENUM_PWM_STAT_TMR2PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR2PH2                (_ADI_MSK(0x04000000,uint32_t))  /* TMR2PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR1PHASE              (_ADI_MSK(0x02000000,uint32_t))  /* PWMTMR1 Phase Status */
-#define ENUM_PWM_STAT_TMR1PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR1PH2                (_ADI_MSK(0x02000000,uint32_t))  /* TMR1PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR0PHASE              (_ADI_MSK(0x01000000,uint32_t))  /* PWMTMR0 Phase Status */
-#define ENUM_PWM_STAT_TMR0PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR0PH2                (_ADI_MSK(0x01000000,uint32_t))  /* TMR0PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER4               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary not reached */
-#define ENUM_PWM_STAT_PER4                   (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary reached */
-
-#define BITM_PWM_STAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER3               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary not reached */
-#define ENUM_PWM_STAT_PER3                   (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary reached */
-
-#define BITM_PWM_STAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER2               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary not reached */
-#define ENUM_PWM_STAT_PER2                   (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary reached */
-
-#define BITM_PWM_STAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER1               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary not reached */
-#define ENUM_PWM_STAT_PER1                   (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary reached */
-
-#define BITM_PWM_STAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER0               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary not reached */
-#define ENUM_PWM_STAT_PER0                   (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary reached */
-
-#define BITM_PWM_STAT_SRTRIPD                (_ADI_MSK(0x00000800,uint32_t))  /* Self-Restart Trip Status for Channel D */
-#define ENUM_PWM_STAT_SRD_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRD_TRIP               (_ADI_MSK(0x00000800,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPD               (_ADI_MSK(0x00000400,uint32_t))  /* Fault Trip Status for Channel D */
-#define ENUM_PWM_STAT_FLTD_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTD_TRIP              (_ADI_MSK(0x00000400,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPC                (_ADI_MSK(0x00000200,uint32_t))  /* Self-Restart Trip Status for Channel C */
-#define ENUM_PWM_STAT_SRC_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRC_TRIP               (_ADI_MSK(0x00000200,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPC               (_ADI_MSK(0x00000100,uint32_t))  /* Fault Trip Status for Channel C */
-#define ENUM_PWM_STAT_FLTC_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTC_TRIP              (_ADI_MSK(0x00000100,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPB                (_ADI_MSK(0x00000080,uint32_t))  /* Self-Restart Trip Status for Channel B */
-#define ENUM_PWM_STAT_SRB_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRB_TRIP               (_ADI_MSK(0x00000080,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPB               (_ADI_MSK(0x00000040,uint32_t))  /* Fault Trip Status for Channel B */
-#define ENUM_PWM_STAT_FLTB_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPB: Channel B Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTB_TRIP              (_ADI_MSK(0x00000040,uint32_t))  /* FLTTRIPB: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPA                (_ADI_MSK(0x00000020,uint32_t))  /* Self-Restart Trip Status for Channel A */
-#define ENUM_PWM_STAT_SRA_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRA_TRIP               (_ADI_MSK(0x00000020,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPA               (_ADI_MSK(0x00000010,uint32_t))  /* Fault Trip Status for Channel A */
-#define ENUM_PWM_STAT_FLTA_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTA_TRIP              (_ADI_MSK(0x00000010,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_RAWTRIP1               (_ADI_MSK(0x00000008,uint32_t))  /* Raw Trip 1 Status */
-#define ENUM_PWM_STAT_TRIP1LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP1: TRIP1 Level is Low */
-#define ENUM_PWM_STAT_TRIP1LVL_HI            (_ADI_MSK(0x00000008,uint32_t))  /* RAWTRIP1: TRIP1 Level is High */
-
-#define BITM_PWM_STAT_RAWTRIP0               (_ADI_MSK(0x00000004,uint32_t))  /* Raw Trip 0 Status */
-#define ENUM_PWM_STAT_TRIP0LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP0: TRIP0 Level is Low */
-#define ENUM_PWM_STAT_TRIP0LVL_HI            (_ADI_MSK(0x00000004,uint32_t))  /* RAWTRIP0: TRIP0 Level is High */
-
-#define BITM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* Status bit set when TRIP1 is active low */
-#define ENUM_PWM_STAT_NO_TRIP1               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: TRIP1 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: TRIP1 status is "tripped" (active low) */
-
-#define BITM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* Status bit set when TRIP0 is active low */
-#define ENUM_PWM_STAT_NO_TRIP0               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: TRIP0 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: TRIP0 status is "tripped" (active low) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_IMSK_TMR4PER                20                               /* PWMTMR4 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR3PER                19                               /* PWMTMR3 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR2PER                18                               /* PWMTMR2 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR1PER                17                               /* PWMTMR1 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP1                   1                               /* TRIP1 Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP0                   0                               /* TRIP0 Interrupt Enable */
-
-#define BITM_PWM_IMSK_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER4_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: Mask PWMTMR4 Period Interrupt */
-#define ENUM_PWM_IMSK_PER4_UMSK              (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Unmask PWMTMR4 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER3_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: Mask PWMTMR3 Period Interrupt */
-#define ENUM_PWM_IMSK_PER3_UMSK              (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Unmask PWMTMR3 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER2_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: Mask PWMTMR2 Period Interrupt */
-#define ENUM_PWM_IMSK_PER2_UMSK              (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Unmask PWMTMR2 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER1_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: Mask PWMTMR1 Period Interrupt */
-#define ENUM_PWM_IMSK_PER1_UMSK              (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Unmask PWMTMR1 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER0_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: Mask PWMTMR0 Period Interrupt */
-#define ENUM_PWM_IMSK_PER0_UMSK              (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Unmask PWMTMR0 Period Interrupt */
-
-#define BITM_PWM_IMSK_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP1_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: Mask TRIP1 Interrupt */
-#define ENUM_PWM_IMSK_TRIP1_UMSK             (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Unmask TRIP1 Interrupt */
-
-#define BITM_PWM_IMSK_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP0_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: Mask TRIP0 Interrupt */
-#define ENUM_PWM_IMSK_TRIP0_UMSK             (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Unmask TRIP0 Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ILAT_TMR4PER                20                               /* PWMTMR4 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR3PER                19                               /* PWMTMR3 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR2PER                18                               /* PWMTMR2 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR1PER                17                               /* PWMTMR1 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP1                   1                               /* TRIP1 Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP0                   0                               /* TRIP0 Interrupt Latched Status */
-
-#define BITM_PWM_ILAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER4_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER4_INTHI             (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER3_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER3_INTHI             (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER2_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER2_INTHI             (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER1_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER1_INTHI             (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define ENUM_PWM_ILAT_PER0_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER0_INTHI             (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP1_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP1_INTHI            (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP0_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP0_INTHI            (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Interrupt Latched */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHOPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHOPCFG_VALUE                0                               /* Gate Chopping Divisor */
-#define BITM_PWM_CHOPCFG_VALUE               (_ADI_MSK(0x000000FF,uint32_t))  /* Gate Chopping Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DT_VALUE                     0                               /* Dead Time */
-#define BITM_PWM_DT_VALUE                    (_ADI_MSK(0x000003FF,uint32_t))  /* Dead Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_SYNC_WID                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_SYNC_WID_VALUE               0                               /* Sync Pulse Width */
-#define BITM_PWM_SYNC_WID_VALUE              (_ADI_MSK(0x000003FF,uint32_t))  /* Sync Pulse Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM0_VALUE                    0                               /* Timer PWMTMR0 Period Value */
-#define BITM_PWM_TM0_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR0 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM1_VALUE                    0                               /* Timer PWMTMR1 Period Value */
-#define BITM_PWM_TM1_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR1 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM2_VALUE                    0                               /* Timer PWMTMR2 Period Value */
-#define BITM_PWM_TM2_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR2 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM3                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM3_VALUE                    0                               /* Timer PWMTMR3 Period Value */
-#define BITM_PWM_TM3_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR3 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM4                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM4_VALUE                    0                               /* Timer PWMTMR4 Period Value */
-#define BITM_PWM_TM4_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR4 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYA                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYA_VALUE                   0                               /* Channel A Delay Value */
-#define BITM_PWM_DLYA_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel A Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYB                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYB_VALUE                   0                               /* Channel B Delay Value */
-#define BITM_PWM_DLYB_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel B Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYC                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYC_VALUE                   0                               /* Channel C Delay Value */
-#define BITM_PWM_DLYC_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel C Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYD_VALUE                   0                               /* Channel D Delay Value */
-#define BITM_PWM_DLYD_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel D Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ACTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ACTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_ACTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_ACTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_ACTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_ACTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-#define BITM_PWM_ACTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define ENUM_PWM_SYM_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODELO: Symmetrical */
-#define ENUM_PWM_ASYM_LO                     (_ADI_MSK(0x00000400,uint32_t))  /* PULSEMODELO: Asymmetrical */
-#define ENUM_PWM_LEFT_LO                     (_ADI_MSK(0x00000800,uint32_t))  /* PULSEMODELO: Left Half */
-#define ENUM_PWM_RIGHT_LO                    (_ADI_MSK(0x00000C00,uint32_t))  /* PULSEMODELO: Right Half */
-
-#define BITM_PWM_ACTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define ENUM_PWM_SYM_HI                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODEHI: Symmetrical */
-#define ENUM_PWM_ASYM_HI                     (_ADI_MSK(0x00000100,uint32_t))  /* PULSEMODEHI: Asymmetrical */
-#define ENUM_PWM_LEFT_HI                     (_ADI_MSK(0x00000200,uint32_t))  /* PULSEMODEHI: Left Half */
-#define ENUM_PWM_RIGHT_HI                    (_ADI_MSK(0x00000300,uint32_t))  /* PULSEMODEHI: Right Half */
-
-#define BITM_PWM_ACTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define ENUM_PWM_XOVR_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* XOVR: Disable Crossover */
-#define ENUM_PWM_XOVR_EN                     (_ADI_MSK(0x00000004,uint32_t))  /* XOVR: Enable Crossover */
-
-#define BITM_PWM_ACTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define ENUM_PWM_LO_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISLO: Disable Low Side Output */
-#define ENUM_PWM_LO_EN                       (_ADI_MSK(0x00000002,uint32_t))  /* DISLO: Enable Low Side Output */
-
-#define BITM_PWM_ACTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-#define ENUM_PWM_HI_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISHI: Disable High Side Output */
-#define ENUM_PWM_HI_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* DISHI: Enable High Side Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_BCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_BCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_BCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_BCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_BCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_BCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_BCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_BCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_BCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_BCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_CCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_CCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_CCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_CCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_CCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_CCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_CCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_CCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_CCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_CCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_DCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_DCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_DCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_DCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_DCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_DCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_DCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_DCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_DCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_DCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ==================================================
-        Video Subsystem Registers Registers
-   ================================================== */
-
-/* =========================
-        VID0
-   ========================= */
-#define REG_VID0_CONN                   0xFFC1D000         /* VID0 Video Subsystem Connect Register */
-
-/* =========================
-        VID
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        VID_CONN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_VID_CONN_PPI2BCAST              23                               /* PPI_2 Broadcast Mode */
-#define BITP_VID_CONN_PPI1BCAST              22                               /* PPI_1 Broadcast Mode */
-#define BITP_VID_CONN_PPI0BCAST              21                               /* PPI_0 Broadcast Mode */
-#define BITP_VID_CONN_PPI2TX                 16                               /* PPI_2_TX Connectivity */
-#define BITP_VID_CONN_PPI1TX                 12                               /* PPI_1_TX Connectivity */
-#define BITP_VID_CONN_PPI0TX                  8                               /* PPI_0_TX Connectivity */
-#define BITP_VID_CONN_PVP0IN                  4                               /* PVP_IN Connectivity */
-#define BITP_VID_CONN_PIXC0IN                 0                               /* PIXC_IN Connectivity */
-#define BITM_VID_CONN_PPI2BCAST              (_ADI_MSK(0x00800000,uint32_t))  /* PPI_2 Broadcast Mode */
-#define BITM_VID_CONN_PPI1BCAST              (_ADI_MSK(0x00400000,uint32_t))  /* PPI_1 Broadcast Mode */
-#define BITM_VID_CONN_PPI0BCAST              (_ADI_MSK(0x00200000,uint32_t))  /* PPI_0 Broadcast Mode */
-#define BITM_VID_CONN_PPI2TX                 (_ADI_MSK(0x000F0000,uint32_t))  /* PPI_2_TX Connectivity */
-#define BITM_VID_CONN_PPI1TX                 (_ADI_MSK(0x0000F000,uint32_t))  /* PPI_1_TX Connectivity */
-#define BITM_VID_CONN_PPI0TX                 (_ADI_MSK(0x00000F00,uint32_t))  /* PPI_0_TX Connectivity */
-#define BITM_VID_CONN_PVP0IN                 (_ADI_MSK(0x000000F0,uint32_t))  /* PVP_IN Connectivity */
-#define BITM_VID_CONN_PIXC0IN                (_ADI_MSK(0x0000000F,uint32_t))  /* PIXC_IN Connectivity */
-
-/* ==================================================
-        System Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        SWU0
-   ========================= */
-#define REG_SWU0_GCTL                   0xFFC1E000         /* SWU0 Global Control Register */
-#define REG_SWU0_GSTAT                  0xFFC1E004         /* SWU0 Global Status Register */
-#define REG_SWU0_CTL0                   0xFFC1E010         /* SWU0 Control Register n */
-#define REG_SWU0_CTL1                   0xFFC1E030         /* SWU0 Control Register n */
-#define REG_SWU0_CTL2                   0xFFC1E050         /* SWU0 Control Register n */
-#define REG_SWU0_CTL3                   0xFFC1E070         /* SWU0 Control Register n */
-#define REG_SWU0_LA0                    0xFFC1E014         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA1                    0xFFC1E034         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA2                    0xFFC1E054         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA3                    0xFFC1E074         /* SWU0 Lower Address Register n */
-#define REG_SWU0_UA0                    0xFFC1E018         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA1                    0xFFC1E038         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA2                    0xFFC1E058         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA3                    0xFFC1E078         /* SWU0 Upper Address Register n */
-#define REG_SWU0_ID0                    0xFFC1E01C         /* SWU0 ID Register n */
-#define REG_SWU0_ID1                    0xFFC1E03C         /* SWU0 ID Register n */
-#define REG_SWU0_ID2                    0xFFC1E05C         /* SWU0 ID Register n */
-#define REG_SWU0_ID3                    0xFFC1E07C         /* SWU0 ID Register n */
-#define REG_SWU0_CNT0                   0xFFC1E020         /* SWU0 Count Register n */
-#define REG_SWU0_CNT1                   0xFFC1E040         /* SWU0 Count Register n */
-#define REG_SWU0_CNT2                   0xFFC1E060         /* SWU0 Count Register n */
-#define REG_SWU0_CNT3                   0xFFC1E080         /* SWU0 Count Register n */
-#define REG_SWU0_TARG0                  0xFFC1E024         /* SWU0 Target Register n */
-#define REG_SWU0_TARG1                  0xFFC1E044         /* SWU0 Target Register n */
-#define REG_SWU0_TARG2                  0xFFC1E064         /* SWU0 Target Register n */
-#define REG_SWU0_TARG3                  0xFFC1E084         /* SWU0 Target Register n */
-#define REG_SWU0_HIST0                  0xFFC1E028         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST1                  0xFFC1E048         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST2                  0xFFC1E068         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST3                  0xFFC1E088         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_CUR0                   0xFFC1E02C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR1                   0xFFC1E04C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR2                   0xFFC1E06C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR3                   0xFFC1E08C         /* SWU0 Current Register n */
-
-/* =========================
-        SWU1
-   ========================= */
-#define REG_SWU1_GCTL                   0xFFCAB000         /* SWU1 Global Control Register */
-#define REG_SWU1_GSTAT                  0xFFCAB004         /* SWU1 Global Status Register */
-#define REG_SWU1_CTL0                   0xFFCAB010         /* SWU1 Control Register n */
-#define REG_SWU1_CTL1                   0xFFCAB030         /* SWU1 Control Register n */
-#define REG_SWU1_CTL2                   0xFFCAB050         /* SWU1 Control Register n */
-#define REG_SWU1_CTL3                   0xFFCAB070         /* SWU1 Control Register n */
-#define REG_SWU1_LA0                    0xFFCAB014         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA1                    0xFFCAB034         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA2                    0xFFCAB054         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA3                    0xFFCAB074         /* SWU1 Lower Address Register n */
-#define REG_SWU1_UA0                    0xFFCAB018         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA1                    0xFFCAB038         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA2                    0xFFCAB058         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA3                    0xFFCAB078         /* SWU1 Upper Address Register n */
-#define REG_SWU1_ID0                    0xFFCAB01C         /* SWU1 ID Register n */
-#define REG_SWU1_ID1                    0xFFCAB03C         /* SWU1 ID Register n */
-#define REG_SWU1_ID2                    0xFFCAB05C         /* SWU1 ID Register n */
-#define REG_SWU1_ID3                    0xFFCAB07C         /* SWU1 ID Register n */
-#define REG_SWU1_CNT0                   0xFFCAB020         /* SWU1 Count Register n */
-#define REG_SWU1_CNT1                   0xFFCAB040         /* SWU1 Count Register n */
-#define REG_SWU1_CNT2                   0xFFCAB060         /* SWU1 Count Register n */
-#define REG_SWU1_CNT3                   0xFFCAB080         /* SWU1 Count Register n */
-#define REG_SWU1_TARG0                  0xFFCAB024         /* SWU1 Target Register n */
-#define REG_SWU1_TARG1                  0xFFCAB044         /* SWU1 Target Register n */
-#define REG_SWU1_TARG2                  0xFFCAB064         /* SWU1 Target Register n */
-#define REG_SWU1_TARG3                  0xFFCAB084         /* SWU1 Target Register n */
-#define REG_SWU1_HIST0                  0xFFCAB028         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST1                  0xFFCAB048         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST2                  0xFFCAB068         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST3                  0xFFCAB088         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_CUR0                   0xFFCAB02C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR1                   0xFFCAB04C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR2                   0xFFCAB06C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR3                   0xFFCAB08C         /* SWU1 Current Register n */
-
-/* =========================
-        SWU2
-   ========================= */
-#define REG_SWU2_GCTL                   0xFFCAC000         /* SWU2 Global Control Register */
-#define REG_SWU2_GSTAT                  0xFFCAC004         /* SWU2 Global Status Register */
-#define REG_SWU2_CTL0                   0xFFCAC010         /* SWU2 Control Register n */
-#define REG_SWU2_CTL1                   0xFFCAC030         /* SWU2 Control Register n */
-#define REG_SWU2_CTL2                   0xFFCAC050         /* SWU2 Control Register n */
-#define REG_SWU2_CTL3                   0xFFCAC070         /* SWU2 Control Register n */
-#define REG_SWU2_LA0                    0xFFCAC014         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA1                    0xFFCAC034         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA2                    0xFFCAC054         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA3                    0xFFCAC074         /* SWU2 Lower Address Register n */
-#define REG_SWU2_UA0                    0xFFCAC018         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA1                    0xFFCAC038         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA2                    0xFFCAC058         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA3                    0xFFCAC078         /* SWU2 Upper Address Register n */
-#define REG_SWU2_ID0                    0xFFCAC01C         /* SWU2 ID Register n */
-#define REG_SWU2_ID1                    0xFFCAC03C         /* SWU2 ID Register n */
-#define REG_SWU2_ID2                    0xFFCAC05C         /* SWU2 ID Register n */
-#define REG_SWU2_ID3                    0xFFCAC07C         /* SWU2 ID Register n */
-#define REG_SWU2_CNT0                   0xFFCAC020         /* SWU2 Count Register n */
-#define REG_SWU2_CNT1                   0xFFCAC040         /* SWU2 Count Register n */
-#define REG_SWU2_CNT2                   0xFFCAC060         /* SWU2 Count Register n */
-#define REG_SWU2_CNT3                   0xFFCAC080         /* SWU2 Count Register n */
-#define REG_SWU2_TARG0                  0xFFCAC024         /* SWU2 Target Register n */
-#define REG_SWU2_TARG1                  0xFFCAC044         /* SWU2 Target Register n */
-#define REG_SWU2_TARG2                  0xFFCAC064         /* SWU2 Target Register n */
-#define REG_SWU2_TARG3                  0xFFCAC084         /* SWU2 Target Register n */
-#define REG_SWU2_HIST0                  0xFFCAC028         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST1                  0xFFCAC048         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST2                  0xFFCAC068         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST3                  0xFFCAC088         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_CUR0                   0xFFCAC02C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR1                   0xFFCAC04C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR2                   0xFFCAC06C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR3                   0xFFCAC08C         /* SWU2 Current Register n */
-
-/* =========================
-        SWU3
-   ========================= */
-#define REG_SWU3_GCTL                   0xFFCAD000         /* SWU3 Global Control Register */
-#define REG_SWU3_GSTAT                  0xFFCAD004         /* SWU3 Global Status Register */
-#define REG_SWU3_CTL0                   0xFFCAD010         /* SWU3 Control Register n */
-#define REG_SWU3_CTL1                   0xFFCAD030         /* SWU3 Control Register n */
-#define REG_SWU3_CTL2                   0xFFCAD050         /* SWU3 Control Register n */
-#define REG_SWU3_CTL3                   0xFFCAD070         /* SWU3 Control Register n */
-#define REG_SWU3_LA0                    0xFFCAD014         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA1                    0xFFCAD034         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA2                    0xFFCAD054         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA3                    0xFFCAD074         /* SWU3 Lower Address Register n */
-#define REG_SWU3_UA0                    0xFFCAD018         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA1                    0xFFCAD038         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA2                    0xFFCAD058         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA3                    0xFFCAD078         /* SWU3 Upper Address Register n */
-#define REG_SWU3_ID0                    0xFFCAD01C         /* SWU3 ID Register n */
-#define REG_SWU3_ID1                    0xFFCAD03C         /* SWU3 ID Register n */
-#define REG_SWU3_ID2                    0xFFCAD05C         /* SWU3 ID Register n */
-#define REG_SWU3_ID3                    0xFFCAD07C         /* SWU3 ID Register n */
-#define REG_SWU3_CNT0                   0xFFCAD020         /* SWU3 Count Register n */
-#define REG_SWU3_CNT1                   0xFFCAD040         /* SWU3 Count Register n */
-#define REG_SWU3_CNT2                   0xFFCAD060         /* SWU3 Count Register n */
-#define REG_SWU3_CNT3                   0xFFCAD080         /* SWU3 Count Register n */
-#define REG_SWU3_TARG0                  0xFFCAD024         /* SWU3 Target Register n */
-#define REG_SWU3_TARG1                  0xFFCAD044         /* SWU3 Target Register n */
-#define REG_SWU3_TARG2                  0xFFCAD064         /* SWU3 Target Register n */
-#define REG_SWU3_TARG3                  0xFFCAD084         /* SWU3 Target Register n */
-#define REG_SWU3_HIST0                  0xFFCAD028         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST1                  0xFFCAD048         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST2                  0xFFCAD068         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST3                  0xFFCAD088         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_CUR0                   0xFFCAD02C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR1                   0xFFCAD04C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR2                   0xFFCAD06C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR3                   0xFFCAD08C         /* SWU3 Current Register n */
-
-/* =========================
-        SWU4
-   ========================= */
-#define REG_SWU4_GCTL                   0xFFCAE000         /* SWU4 Global Control Register */
-#define REG_SWU4_GSTAT                  0xFFCAE004         /* SWU4 Global Status Register */
-#define REG_SWU4_CTL0                   0xFFCAE010         /* SWU4 Control Register n */
-#define REG_SWU4_CTL1                   0xFFCAE030         /* SWU4 Control Register n */
-#define REG_SWU4_CTL2                   0xFFCAE050         /* SWU4 Control Register n */
-#define REG_SWU4_CTL3                   0xFFCAE070         /* SWU4 Control Register n */
-#define REG_SWU4_LA0                    0xFFCAE014         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA1                    0xFFCAE034         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA2                    0xFFCAE054         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA3                    0xFFCAE074         /* SWU4 Lower Address Register n */
-#define REG_SWU4_UA0                    0xFFCAE018         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA1                    0xFFCAE038         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA2                    0xFFCAE058         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA3                    0xFFCAE078         /* SWU4 Upper Address Register n */
-#define REG_SWU4_ID0                    0xFFCAE01C         /* SWU4 ID Register n */
-#define REG_SWU4_ID1                    0xFFCAE03C         /* SWU4 ID Register n */
-#define REG_SWU4_ID2                    0xFFCAE05C         /* SWU4 ID Register n */
-#define REG_SWU4_ID3                    0xFFCAE07C         /* SWU4 ID Register n */
-#define REG_SWU4_CNT0                   0xFFCAE020         /* SWU4 Count Register n */
-#define REG_SWU4_CNT1                   0xFFCAE040         /* SWU4 Count Register n */
-#define REG_SWU4_CNT2                   0xFFCAE060         /* SWU4 Count Register n */
-#define REG_SWU4_CNT3                   0xFFCAE080         /* SWU4 Count Register n */
-#define REG_SWU4_TARG0                  0xFFCAE024         /* SWU4 Target Register n */
-#define REG_SWU4_TARG1                  0xFFCAE044         /* SWU4 Target Register n */
-#define REG_SWU4_TARG2                  0xFFCAE064         /* SWU4 Target Register n */
-#define REG_SWU4_TARG3                  0xFFCAE084         /* SWU4 Target Register n */
-#define REG_SWU4_HIST0                  0xFFCAE028         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST1                  0xFFCAE048         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST2                  0xFFCAE068         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST3                  0xFFCAE088         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_CUR0                   0xFFCAE02C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR1                   0xFFCAE04C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR2                   0xFFCAE06C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR3                   0xFFCAE08C         /* SWU4 Current Register n */
-
-/* =========================
-        SWU5
-   ========================= */
-#define REG_SWU5_GCTL                   0xFFCAF000         /* SWU5 Global Control Register */
-#define REG_SWU5_GSTAT                  0xFFCAF004         /* SWU5 Global Status Register */
-#define REG_SWU5_CTL0                   0xFFCAF010         /* SWU5 Control Register n */
-#define REG_SWU5_CTL1                   0xFFCAF030         /* SWU5 Control Register n */
-#define REG_SWU5_CTL2                   0xFFCAF050         /* SWU5 Control Register n */
-#define REG_SWU5_CTL3                   0xFFCAF070         /* SWU5 Control Register n */
-#define REG_SWU5_LA0                    0xFFCAF014         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA1                    0xFFCAF034         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA2                    0xFFCAF054         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA3                    0xFFCAF074         /* SWU5 Lower Address Register n */
-#define REG_SWU5_UA0                    0xFFCAF018         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA1                    0xFFCAF038         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA2                    0xFFCAF058         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA3                    0xFFCAF078         /* SWU5 Upper Address Register n */
-#define REG_SWU5_ID0                    0xFFCAF01C         /* SWU5 ID Register n */
-#define REG_SWU5_ID1                    0xFFCAF03C         /* SWU5 ID Register n */
-#define REG_SWU5_ID2                    0xFFCAF05C         /* SWU5 ID Register n */
-#define REG_SWU5_ID3                    0xFFCAF07C         /* SWU5 ID Register n */
-#define REG_SWU5_CNT0                   0xFFCAF020         /* SWU5 Count Register n */
-#define REG_SWU5_CNT1                   0xFFCAF040         /* SWU5 Count Register n */
-#define REG_SWU5_CNT2                   0xFFCAF060         /* SWU5 Count Register n */
-#define REG_SWU5_CNT3                   0xFFCAF080         /* SWU5 Count Register n */
-#define REG_SWU5_TARG0                  0xFFCAF024         /* SWU5 Target Register n */
-#define REG_SWU5_TARG1                  0xFFCAF044         /* SWU5 Target Register n */
-#define REG_SWU5_TARG2                  0xFFCAF064         /* SWU5 Target Register n */
-#define REG_SWU5_TARG3                  0xFFCAF084         /* SWU5 Target Register n */
-#define REG_SWU5_HIST0                  0xFFCAF028         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST1                  0xFFCAF048         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST2                  0xFFCAF068         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST3                  0xFFCAF088         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_CUR0                   0xFFCAF02C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR1                   0xFFCAF04C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR2                   0xFFCAF06C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR3                   0xFFCAF08C         /* SWU5 Current Register n */
-
-/* =========================
-        SWU6
-   ========================= */
-#define REG_SWU6_GCTL                   0xFFC82000         /* SWU6 Global Control Register */
-#define REG_SWU6_GSTAT                  0xFFC82004         /* SWU6 Global Status Register */
-#define REG_SWU6_CTL0                   0xFFC82010         /* SWU6 Control Register n */
-#define REG_SWU6_CTL1                   0xFFC82030         /* SWU6 Control Register n */
-#define REG_SWU6_CTL2                   0xFFC82050         /* SWU6 Control Register n */
-#define REG_SWU6_CTL3                   0xFFC82070         /* SWU6 Control Register n */
-#define REG_SWU6_LA0                    0xFFC82014         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA1                    0xFFC82034         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA2                    0xFFC82054         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA3                    0xFFC82074         /* SWU6 Lower Address Register n */
-#define REG_SWU6_UA0                    0xFFC82018         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA1                    0xFFC82038         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA2                    0xFFC82058         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA3                    0xFFC82078         /* SWU6 Upper Address Register n */
-#define REG_SWU6_ID0                    0xFFC8201C         /* SWU6 ID Register n */
-#define REG_SWU6_ID1                    0xFFC8203C         /* SWU6 ID Register n */
-#define REG_SWU6_ID2                    0xFFC8205C         /* SWU6 ID Register n */
-#define REG_SWU6_ID3                    0xFFC8207C         /* SWU6 ID Register n */
-#define REG_SWU6_CNT0                   0xFFC82020         /* SWU6 Count Register n */
-#define REG_SWU6_CNT1                   0xFFC82040         /* SWU6 Count Register n */
-#define REG_SWU6_CNT2                   0xFFC82060         /* SWU6 Count Register n */
-#define REG_SWU6_CNT3                   0xFFC82080         /* SWU6 Count Register n */
-#define REG_SWU6_TARG0                  0xFFC82024         /* SWU6 Target Register n */
-#define REG_SWU6_TARG1                  0xFFC82044         /* SWU6 Target Register n */
-#define REG_SWU6_TARG2                  0xFFC82064         /* SWU6 Target Register n */
-#define REG_SWU6_TARG3                  0xFFC82084         /* SWU6 Target Register n */
-#define REG_SWU6_HIST0                  0xFFC82028         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST1                  0xFFC82048         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST2                  0xFFC82068         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST3                  0xFFC82088         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_CUR0                   0xFFC8202C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR1                   0xFFC8204C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR2                   0xFFC8206C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR3                   0xFFC8208C         /* SWU6 Current Register n */
-
-/* =========================
-        SWU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GCTL_RST                     1                               /* Global Reset */
-#define BITP_SWU_GCTL_EN                      0                               /* Global Enable */
-#define BITM_SWU_GCTL_RST                    (_ADI_MSK(0x00000002,uint32_t))  /* Global Reset */
-#define BITM_SWU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Global Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GSTAT_ADDRERR               30                               /* Address Error Status */
-#define BITP_SWU_GSTAT_OVRBW3                15                               /* Group 3 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW3               14                               /* Group 3 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW2                13                               /* Group 2 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW2               12                               /* Group 2 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW1                11                               /* Group 1 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW1               10                               /* Group 1 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW0                 9                               /* Group 0 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW0                8                               /* Group 0 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_INT3                   7                               /* Group 3 Interrupt Status */
-#define BITP_SWU_GSTAT_INT2                   6                               /* Group 2 Interrupt Status */
-#define BITP_SWU_GSTAT_INT1                   5                               /* Group 1 Interrupt Status */
-#define BITP_SWU_GSTAT_INT0                   4                               /* Group 0 Interrupt Status */
-#define BITP_SWU_GSTAT_MTCH3                  3                               /* Group 3 Match */
-#define BITP_SWU_GSTAT_MTCH2                  2                               /* Group 2 Match */
-#define BITP_SWU_GSTAT_MTCH1                  1                               /* Group 1 Match */
-#define BITP_SWU_GSTAT_MTCH0                  0                               /* Group 0 Match */
-#define BITM_SWU_GSTAT_ADDRERR               (_ADI_MSK(0x40000000,uint32_t))  /* Address Error Status */
-#define BITM_SWU_GSTAT_OVRBW3                (_ADI_MSK(0x00008000,uint32_t))  /* Group 3 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW3               (_ADI_MSK(0x00004000,uint32_t))  /* Group 3 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW2                (_ADI_MSK(0x00002000,uint32_t))  /* Group 2 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW2               (_ADI_MSK(0x00001000,uint32_t))  /* Group 2 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW1                (_ADI_MSK(0x00000800,uint32_t))  /* Group 1 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW1               (_ADI_MSK(0x00000400,uint32_t))  /* Group 1 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW0                (_ADI_MSK(0x00000200,uint32_t))  /* Group 0 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW0               (_ADI_MSK(0x00000100,uint32_t))  /* Group 0 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_INT3                  (_ADI_MSK(0x00000080,uint32_t))  /* Group 3 Interrupt Status */
-#define BITM_SWU_GSTAT_INT2                  (_ADI_MSK(0x00000040,uint32_t))  /* Group 2 Interrupt Status */
-#define BITM_SWU_GSTAT_INT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Group 1 Interrupt Status */
-#define BITM_SWU_GSTAT_INT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Group 0 Interrupt Status */
-#define BITM_SWU_GSTAT_MTCH3                 (_ADI_MSK(0x00000008,uint32_t))  /* Group 3 Match */
-#define BITM_SWU_GSTAT_MTCH2                 (_ADI_MSK(0x00000004,uint32_t))  /* Group 2 Match */
-#define BITM_SWU_GSTAT_MTCH1                 (_ADI_MSK(0x00000002,uint32_t))  /* Group 1 Match */
-#define BITM_SWU_GSTAT_MTCH0                 (_ADI_MSK(0x00000001,uint32_t))  /* Group 0 Match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CTL_MAXACT                  19                               /* Action for Bandwidth Above Maximum */
-#define BITP_SWU_CTL_MINACT                  18                               /* Action for Bandwidth Below Minimum */
-#define BITP_SWU_CTL_BLENINC                 17                               /* Increment Bandwidth Count by Burst Length */
-#define BITP_SWU_CTL_BWEN                    16                               /* Bandwidth Mode Enable */
-#define BITP_SWU_CTL_TMEN                    15                               /* Trace Message Enable */
-#define BITP_SWU_CTL_TRGEN                   14                               /* Trigger Enable */
-#define BITP_SWU_CTL_INTEN                   13                               /* Interrupt Enable */
-#define BITP_SWU_CTL_DBGEN                   12                               /* Debug Event Enable */
-#define BITP_SWU_CTL_CNTRPTEN                 9                               /* Count Repeat Enable */
-#define BITP_SWU_CTL_CNTEN                    8                               /* Count Enable */
-#define BITP_SWU_CTL_LCMPEN                   6                               /* Locked Comparison Enable */
-#define BITP_SWU_CTL_SCMPEN                   5                               /* Secure Comparison Enable */
-#define BITP_SWU_CTL_IDCMPEN                  4                               /* ID Comparison Enable */
-#define BITP_SWU_CTL_ACMPM                    2                               /* Address Comparison Mode */
-#define BITP_SWU_CTL_DIR                      1                               /* Transaction Direction for Match */
-#define BITP_SWU_CTL_EN                       0                               /* Enable Watchpoint */
-#define BITM_SWU_CTL_MAXACT                  (_ADI_MSK(0x00080000,uint32_t))  /* Action for Bandwidth Above Maximum */
-#define BITM_SWU_CTL_MINACT                  (_ADI_MSK(0x00040000,uint32_t))  /* Action for Bandwidth Below Minimum */
-#define BITM_SWU_CTL_BLENINC                 (_ADI_MSK(0x00020000,uint32_t))  /* Increment Bandwidth Count by Burst Length */
-#define BITM_SWU_CTL_BWEN                    (_ADI_MSK(0x00010000,uint32_t))  /* Bandwidth Mode Enable */
-#define BITM_SWU_CTL_TMEN                    (_ADI_MSK(0x00008000,uint32_t))  /* Trace Message Enable */
-#define BITM_SWU_CTL_TRGEN                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Enable */
-#define BITM_SWU_CTL_INTEN                   (_ADI_MSK(0x00002000,uint32_t))  /* Interrupt Enable */
-#define BITM_SWU_CTL_DBGEN                   (_ADI_MSK(0x00001000,uint32_t))  /* Debug Event Enable */
-#define BITM_SWU_CTL_CNTRPTEN                (_ADI_MSK(0x00000200,uint32_t))  /* Count Repeat Enable */
-#define BITM_SWU_CTL_CNTEN                   (_ADI_MSK(0x00000100,uint32_t))  /* Count Enable */
-#define BITM_SWU_CTL_LCMPEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Locked Comparison Enable */
-#define BITM_SWU_CTL_SCMPEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Secure Comparison Enable */
-#define BITM_SWU_CTL_IDCMPEN                 (_ADI_MSK(0x00000010,uint32_t))  /* ID Comparison Enable */
-#define BITM_SWU_CTL_ACMPM                   (_ADI_MSK(0x0000000C,uint32_t))  /* Address Comparison Mode */
-#define BITM_SWU_CTL_DIR                     (_ADI_MSK(0x00000002,uint32_t))  /* Transaction Direction for Match */
-#define BITM_SWU_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable Watchpoint */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_ID                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_ID_IDMASK                   16                               /* Identity Mask (for Or with ID) */
-#define BITP_SWU_ID_ID                        0                               /* Identity */
-#define BITM_SWU_ID_IDMASK                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Identity Mask (for Or with ID) */
-#define BITM_SWU_ID_ID                       (_ADI_MSK(0x0000FFFF,uint32_t))  /* Identity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CNT_COUNT                    0                               /* Count */
-#define BITM_SWU_CNT_COUNT                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_TARG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_TARG_BWMAX                  16                               /* Maximum Bandwidth Target */
-#define BITP_SWU_TARG_BWMIN                   0                               /* Minimum Bandwidth Target */
-#define BITM_SWU_TARG_BWMAX                  (_ADI_MSK(0xFFFF0000,uint32_t))  /* Maximum Bandwidth Target */
-#define BITM_SWU_TARG_BWMIN                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Minimum Bandwidth Target */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_HIST                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_HIST_BWHIST1                16                               /* Bandwidth from Window Before Last */
-#define BITP_SWU_HIST_BWHIST0                 0                               /* Bandwidth from Last Window */
-#define BITM_SWU_HIST_BWHIST1                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Bandwidth from Window Before Last */
-#define BITM_SWU_HIST_BWHIST0                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth from Last Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CUR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CUR_CURBW                   16                               /* Current Bandwidth */
-#define BITP_SWU_CUR_CURCNT                   0                               /* Current Count */
-#define BITM_SWU_CUR_CURBW                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Current Bandwidth */
-#define BITM_SWU_CUR_CURCNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Current Count */
-
-/* ==================================================
-        System Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        SDU0
-   ========================= */
-#define REG_SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
-#define REG_SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
-#define REG_SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
-#define REG_SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
-#define REG_SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
-#define REG_SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
-#define REG_SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
-#define REG_SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
-#define REG_SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
-#define REG_SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
-#define REG_SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
-#define REG_SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
-
-/* =========================
-        SDU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_IDCODE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_IDCODE_REVID                28                               /* Revision ID */
-#define BITP_SDU_IDCODE_PRID                 12                               /* Product ID */
-#define BITP_SDU_IDCODE_MFID                  1                               /* Manufacturer ID */
-#define BITM_SDU_IDCODE_REVID                (_ADI_MSK(0xF0000000,uint32_t))  /* Revision ID */
-#define BITM_SDU_IDCODE_PRID                 (_ADI_MSK(0x0FFFF000,uint32_t))  /* Product ID */
-#define BITM_SDU_IDCODE_MFID                 (_ADI_MSK(0x00000FFE,uint32_t))  /* Manufacturer ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_CTL_EHLT                     8                               /* Emulator Halt Select */
-#define BITP_SDU_CTL_EMEEN                    4                               /* Emulation Event Enable */
-#define BITP_SDU_CTL_DMAEN                    2                               /* DMA Enable */
-#define BITP_SDU_CTL_CSPEN                    1                               /* Core Scan Path Enable */
-#define BITP_SDU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_SDU_CTL_EHLT                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Emulator Halt Select */
-#define BITM_SDU_CTL_EMEEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Emulation Event Enable */
-#define BITM_SDU_CTL_DMAEN                   (_ADI_MSK(0x00000004,uint32_t))  /* DMA Enable */
-#define BITM_SDU_CTL_CSPEN                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Scan Path Enable */
-#define BITM_SDU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_STAT_CRST                   22                               /* Core Reset */
-#define BITP_SDU_STAT_CHLT                   21                               /* Core Halt */
-#define BITP_SDU_STAT_EME                    20                               /* Emulation Event */
-#define BITP_SDU_STAT_GHLTC                  17                               /* Group Halt Cause */
-#define BITP_SDU_STAT_GHLT                   16                               /* Group Halt */
-#define BITP_SDU_STAT_DMAFIFO                12                               /* DMA FIFO */
-#define BITP_SDU_STAT_ADDRERR                11                               /* Address Error */
-#define BITP_SDU_STAT_DMAWDRDY               10                               /* DMAWD Ready */
-#define BITP_SDU_STAT_DMARDRDY                9                               /* DMARD Ready */
-#define BITP_SDU_STAT_MACRDY                  8                               /* MAC Ready */
-#define BITP_SDU_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_SDU_STAT_SECURE                  3                               /* Secure Mode */
-#define BITP_SDU_STAT_DEEPSLEEP               2                               /* Deep Sleep Mode */
-#define BITP_SDU_STAT_ERR                     1                               /* Error */
-#define BITP_SDU_STAT_SYSRST                  0                               /* System Reset */
-#define BITM_SDU_STAT_CRST                   (_ADI_MSK(0x00400000,uint32_t))  /* Core Reset */
-#define BITM_SDU_STAT_CHLT                   (_ADI_MSK(0x00200000,uint32_t))  /* Core Halt */
-#define BITM_SDU_STAT_EME                    (_ADI_MSK(0x00100000,uint32_t))  /* Emulation Event */
-#define BITM_SDU_STAT_GHLTC                  (_ADI_MSK(0x000E0000,uint32_t))  /* Group Halt Cause */
-#define BITM_SDU_STAT_GHLT                   (_ADI_MSK(0x00010000,uint32_t))  /* Group Halt */
-#define BITM_SDU_STAT_DMAFIFO                (_ADI_MSK(0x00007000,uint32_t))  /* DMA FIFO */
-#define BITM_SDU_STAT_ADDRERR                (_ADI_MSK(0x00000800,uint32_t))  /* Address Error */
-#define BITM_SDU_STAT_DMAWDRDY               (_ADI_MSK(0x00000400,uint32_t))  /* DMAWD Ready */
-#define BITM_SDU_STAT_DMARDRDY               (_ADI_MSK(0x00000200,uint32_t))  /* DMARD Ready */
-#define BITM_SDU_STAT_MACRDY                 (_ADI_MSK(0x00000100,uint32_t))  /* MAC Ready */
-#define BITM_SDU_STAT_ERRC                   (_ADI_MSK(0x000000F0,uint32_t))  /* Error Cause */
-#define BITM_SDU_STAT_SECURE                 (_ADI_MSK(0x00000008,uint32_t))  /* Secure Mode */
-#define BITM_SDU_STAT_DEEPSLEEP              (_ADI_MSK(0x00000004,uint32_t))  /* Deep Sleep Mode */
-#define BITM_SDU_STAT_ERR                    (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define BITM_SDU_STAT_SYSRST                 (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MACCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MACCTL_AUTOINC               4                               /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITP_SDU_MACCTL_RNW                   3                               /* Read Not Write */
-#define BITP_SDU_MACCTL_SIZE                  0                               /* Transfer Data Size */
-#define BITM_SDU_MACCTL_AUTOINC              (_ADI_MSK(0x00000010,uint32_t))  /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITM_SDU_MACCTL_RNW                  (_ADI_MSK(0x00000008,uint32_t))  /* Read Not Write */
-#define BITM_SDU_MACCTL_SIZE                 (_ADI_MSK(0x00000007,uint32_t))  /* Transfer Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MSG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MSG_CALLERR                 31                               /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITP_SDU_MSG_CALLBACK                30                               /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITP_SDU_MSG_CALLINIT                29                               /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITP_SDU_MSG_CALLAPP                 28                               /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITP_SDU_MSG_HALTONERR               27                               /* Generate an Emulation Exception Prior to an Error Call */
-#define BITP_SDU_MSG_HALTONCALL              26                               /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITP_SDU_MSG_HALTONINIT              25                               /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITP_SDU_MSG_HALTONAPP               24                               /* Generate an Emulation Exception Prior to an Application Call */
-#define BITP_SDU_MSG_L3INIT                  23                               /* Indicates that the L3 Resource is Initialized */
-#define BITP_SDU_MSG_L2INIT                  22                               /* Indicates that the L2 Resource is Initialized */
-#define BITP_SDU_MSG_C1L1INIT                17                               /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITP_SDU_MSG_C0L1INIT                16                               /* Indicates that the Core 0 L1 Resource is Initialized */
-#define BITM_SDU_MSG_CALLERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITM_SDU_MSG_CALLBACK                (_ADI_MSK(0x40000000,uint32_t))  /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITM_SDU_MSG_CALLINIT                (_ADI_MSK(0x20000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITM_SDU_MSG_CALLAPP                 (_ADI_MSK(0x10000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITM_SDU_MSG_HALTONERR               (_ADI_MSK(0x08000000,uint32_t))  /* Generate an Emulation Exception Prior to an Error Call */
-#define BITM_SDU_MSG_HALTONCALL              (_ADI_MSK(0x04000000,uint32_t))  /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITM_SDU_MSG_HALTONINIT              (_ADI_MSK(0x02000000,uint32_t))  /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITM_SDU_MSG_HALTONAPP               (_ADI_MSK(0x01000000,uint32_t))  /* Generate an Emulation Exception Prior to an Application Call */
-#define BITM_SDU_MSG_L3INIT                  (_ADI_MSK(0x00800000,uint32_t))  /* Indicates that the L3 Resource is Initialized */
-#define BITM_SDU_MSG_L2INIT                  (_ADI_MSK(0x00400000,uint32_t))  /* Indicates that the L2 Resource is Initialized */
-#define BITM_SDU_MSG_C1L1INIT                (_ADI_MSK(0x00020000,uint32_t))  /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITM_SDU_MSG_C0L1INIT                (_ADI_MSK(0x00010000,uint32_t))  /* Indicates that the Core 0 L1 Resource is Initialized */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_GHLT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_GHLT_SS2                    18                               /* Slave Select 2 */
-#define BITP_SDU_GHLT_SS1                    17                               /* Slave Select 1 */
-#define BITP_SDU_GHLT_SS0                    16                               /* Slave Select 0 */
-#define BITP_SDU_GHLT_MS2                     2                               /* Master Select 2 */
-#define BITP_SDU_GHLT_MS1                     1                               /* Master Select 1 */
-#define BITP_SDU_GHLT_MS0                     0                               /* Master Select 0 */
-#define BITM_SDU_GHLT_SS2                    (_ADI_MSK(0x00040000,uint32_t))  /* Slave Select 2 */
-#define BITM_SDU_GHLT_SS1                    (_ADI_MSK(0x00020000,uint32_t))  /* Slave Select 1 */
-#define BITM_SDU_GHLT_SS0                    (_ADI_MSK(0x00010000,uint32_t))  /* Slave Select 0 */
-#define BITM_SDU_GHLT_MS2                    (_ADI_MSK(0x00000004,uint32_t))  /* Master Select 2 */
-#define BITM_SDU_GHLT_MS1                    (_ADI_MSK(0x00000002,uint32_t))  /* Master Select 1 */
-#define BITM_SDU_GHLT_MS0                    (_ADI_MSK(0x00000001,uint32_t))  /* Master Select 0 */
-
-/* ==================================================
-        Ethernet MAC Registers
-   ================================================== */
-
-/* =========================
-        EMAC0
-   ========================= */
-#define REG_EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
-#define REG_EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 MAC Rx Frame Filter Register */
-#define REG_EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Hash Table High Register */
-#define REG_EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Hash Table Low Register */
-#define REG_EMAC0_SMI_ADDR              0xFFC20010         /* EMAC0 SMI Address Register */
-#define REG_EMAC0_SMI_DATA              0xFFC20014         /* EMAC0 SMI Data Register */
-#define REG_EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 FLow Control Register */
-#define REG_EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
-#define REG_EMAC0_DBG                   0xFFC20024         /* EMAC0 Debug Register */
-#define REG_EMAC0_ISTAT                 0xFFC20038         /* EMAC0 Interrupt Status Register */
-#define REG_EMAC0_IMSK                  0xFFC2003C         /* EMAC0 Interrupt Mask Register */
-#define REG_EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 MAC Address 0 High Register */
-#define REG_EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 MAC Address 0 Low Register */
-#define REG_EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
-#define REG_EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC Rx Interrupt Register */
-#define REG_EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC Tx Interrupt Register */
-#define REG_EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC Rx Interrupt Mask Register */
-#define REG_EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
-#define REG_EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Tx Multicast Frames (Good) Register */
-#define REG_EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Tx Underflow Error Register */
-#define REG_EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Tx Single Collision (Good) Register */
-#define REG_EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Tx Multiple Collision (Good) Register */
-#define REG_EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Tx Deferred Register */
-#define REG_EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Tx Late Collision Register */
-#define REG_EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Tx Excess Collision Register */
-#define REG_EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Tx Carrier Error Register */
-#define REG_EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Tx Octet Count (Good) Register */
-#define REG_EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Tx Frame Count (Good) Register */
-#define REG_EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Tx Excess Deferral Register */
-#define REG_EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Tx Pause Frame Register */
-#define REG_EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Tx VLAN Frames (Good) Register */
-#define REG_EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Rx Octet Count (Good) Register */
-#define REG_EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Rx Multicast Frames (Good) Register */
-#define REG_EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Rx CRC Error Register */
-#define REG_EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Rx alignment Error Register */
-#define REG_EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Rx Runt Error Register */
-#define REG_EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Rx Jab Error Register */
-#define REG_EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Rx Undersize (Good) Register */
-#define REG_EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Rx Oversize (Good) Register */
-#define REG_EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Rx Unicast Frames (Good) Register */
-#define REG_EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Rx Length Error Register */
-#define REG_EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Rx Out Of Range Type Register */
-#define REG_EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Rx Pause Frames Register */
-#define REG_EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Rx FIFO Overflow Register */
-#define REG_EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Rx Watch Dog Error Register */
-#define REG_EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC Rx Interrupt Register */
-#define REG_EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Rx UDP Good Frames Register */
-#define REG_EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Rx UDP Error Frames Register */
-#define REG_EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Rx TCP Good Frames Register */
-#define REG_EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Rx TCP Error Frames Register */
-#define REG_EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Rx ICMP Good Frames Register */
-#define REG_EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Rx ICMP Error Frames Register */
-#define REG_EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Rx IPv6 Good Octets Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Rx IPv6 Header Errors Register */
-#define REG_EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Rx UDP Good Octets Register */
-#define REG_EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Rx UDP Error Octets Register */
-#define REG_EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Rx TCP Good Octets Register */
-#define REG_EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Rx TCP Error Octets Register */
-#define REG_EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Rx ICMP Good Octets Register */
-#define REG_EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Rx ICMP Error Octets Register */
-#define REG_EMAC0_TM_CTL                0xFFC20700         /* EMAC0 Time Stamp Control Register */
-#define REG_EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 Time Stamp Sub Second Increment Register */
-#define REG_EMAC0_TM_SEC                0xFFC20708         /* EMAC0 Time Stamp Low Seconds Register */
-#define REG_EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 Time Stamp Nano Seconds Register */
-#define REG_EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 Time Stamp Seconds Update Register */
-#define REG_EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 Time Stamp Addend Register */
-#define REG_EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 Time Stamp Target Time Seconds Register */
-#define REG_EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 Time Stamp High Second Register */
-#define REG_EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 Time Stamp Status Register */
-#define REG_EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 PPS Control Register */
-#define REG_EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC0_TM_PPSINTVL           0xFFC20760         /* EMAC0 Time Stamp PPS Interval Register */
-#define REG_EMAC0_TM_PPSWIDTH           0xFFC20764         /* EMAC0 PPS Width Register */
-#define REG_EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 DMA Bus Mode Register */
-#define REG_EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 DMA Tx Poll Demand Register */
-#define REG_EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 DMA Rx Poll Demand register */
-#define REG_EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define REG_EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define REG_EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
-#define REG_EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
-#define REG_EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
-#define REG_EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA Missed Frame Register */
-#define REG_EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 DMA SCB Bus Mode Register */
-#define REG_EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 DMA SCB Status Register */
-#define REG_EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 DMA Tx Descriptor Current Register */
-#define REG_EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 DMA Rx Descriptor Current Register */
-#define REG_EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 DMA Tx Buffer Current Register */
-#define REG_EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC1
-   ========================= */
-#define REG_EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
-#define REG_EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 MAC Rx Frame Filter Register */
-#define REG_EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Hash Table High Register */
-#define REG_EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Hash Table Low Register */
-#define REG_EMAC1_SMI_ADDR              0xFFC22010         /* EMAC1 SMI Address Register */
-#define REG_EMAC1_SMI_DATA              0xFFC22014         /* EMAC1 SMI Data Register */
-#define REG_EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 FLow Control Register */
-#define REG_EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
-#define REG_EMAC1_DBG                   0xFFC22024         /* EMAC1 Debug Register */
-#define REG_EMAC1_ISTAT                 0xFFC22038         /* EMAC1 Interrupt Status Register */
-#define REG_EMAC1_IMSK                  0xFFC2203C         /* EMAC1 Interrupt Mask Register */
-#define REG_EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 MAC Address 0 High Register */
-#define REG_EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 MAC Address 0 Low Register */
-#define REG_EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
-#define REG_EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC Rx Interrupt Register */
-#define REG_EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC Tx Interrupt Register */
-#define REG_EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC Rx Interrupt Mask Register */
-#define REG_EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
-#define REG_EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Tx Multicast Frames (Good) Register */
-#define REG_EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Tx Underflow Error Register */
-#define REG_EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Tx Single Collision (Good) Register */
-#define REG_EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Tx Multiple Collision (Good) Register */
-#define REG_EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Tx Deferred Register */
-#define REG_EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Tx Late Collision Register */
-#define REG_EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Tx Excess Collision Register */
-#define REG_EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Tx Carrier Error Register */
-#define REG_EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Tx Octet Count (Good) Register */
-#define REG_EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Tx Frame Count (Good) Register */
-#define REG_EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Tx Excess Deferral Register */
-#define REG_EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Tx Pause Frame Register */
-#define REG_EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Tx VLAN Frames (Good) Register */
-#define REG_EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Rx Octet Count (Good) Register */
-#define REG_EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Rx Multicast Frames (Good) Register */
-#define REG_EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Rx CRC Error Register */
-#define REG_EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Rx alignment Error Register */
-#define REG_EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Rx Runt Error Register */
-#define REG_EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Rx Jab Error Register */
-#define REG_EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Rx Undersize (Good) Register */
-#define REG_EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Rx Oversize (Good) Register */
-#define REG_EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Rx Unicast Frames (Good) Register */
-#define REG_EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Rx Length Error Register */
-#define REG_EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Rx Out Of Range Type Register */
-#define REG_EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Rx Pause Frames Register */
-#define REG_EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Rx FIFO Overflow Register */
-#define REG_EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Rx Watch Dog Error Register */
-#define REG_EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC Rx Interrupt Register */
-#define REG_EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Rx UDP Good Frames Register */
-#define REG_EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Rx UDP Error Frames Register */
-#define REG_EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Rx TCP Good Frames Register */
-#define REG_EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Rx TCP Error Frames Register */
-#define REG_EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Rx ICMP Good Frames Register */
-#define REG_EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Rx ICMP Error Frames Register */
-#define REG_EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Rx IPv6 Good Octets Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Rx IPv6 Header Errors Register */
-#define REG_EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Rx UDP Good Octets Register */
-#define REG_EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Rx UDP Error Octets Register */
-#define REG_EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Rx TCP Good Octets Register */
-#define REG_EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Rx TCP Error Octets Register */
-#define REG_EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Rx ICMP Good Octets Register */
-#define REG_EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Rx ICMP Error Octets Register */
-#define REG_EMAC1_TM_CTL                0xFFC22700         /* EMAC1 Time Stamp Control Register */
-#define REG_EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 Time Stamp Sub Second Increment Register */
-#define REG_EMAC1_TM_SEC                0xFFC22708         /* EMAC1 Time Stamp Low Seconds Register */
-#define REG_EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 Time Stamp Nano Seconds Register */
-#define REG_EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 Time Stamp Seconds Update Register */
-#define REG_EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 Time Stamp Addend Register */
-#define REG_EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 Time Stamp Target Time Seconds Register */
-#define REG_EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 Time Stamp High Second Register */
-#define REG_EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 Time Stamp Status Register */
-#define REG_EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 PPS Control Register */
-#define REG_EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC1_TM_PPSINTVL           0xFFC22760         /* EMAC1 Time Stamp PPS Interval Register */
-#define REG_EMAC1_TM_PPSWIDTH           0xFFC22764         /* EMAC1 PPS Width Register */
-#define REG_EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 DMA Bus Mode Register */
-#define REG_EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 DMA Tx Poll Demand Register */
-#define REG_EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 DMA Rx Poll Demand register */
-#define REG_EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define REG_EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define REG_EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
-#define REG_EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
-#define REG_EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
-#define REG_EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA Missed Frame Register */
-#define REG_EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 DMA SCB Bus Mode Register */
-#define REG_EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 DMA SCB Status Register */
-#define REG_EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 DMA Tx Descriptor Current Register */
-#define REG_EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 DMA Rx Descriptor Current Register */
-#define REG_EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 DMA Tx Buffer Current Register */
-#define REG_EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACCFG_CST                 25                               /* CRC Stripping */
-#define BITP_EMAC_MACCFG_WD                  23                               /* Watch Dog Disable */
-#define BITP_EMAC_MACCFG_JB                  22                               /* Jabber Disable */
-#define BITP_EMAC_MACCFG_JE                  20                               /* Jumbo Frame Enable */
-#define BITP_EMAC_MACCFG_IFG                 17                               /* Inter Frame Gap */
-#define BITP_EMAC_MACCFG_DCRS                16                               /* Disable Carrier Sense */
-#define BITP_EMAC_MACCFG_FES                 14                               /* Speed of Operation */
-#define BITP_EMAC_MACCFG_DO                  13                               /* Disable Receive Own */
-#define BITP_EMAC_MACCFG_LM                  12                               /* Loopback Mode */
-#define BITP_EMAC_MACCFG_DM                  11                               /* Duplex Mode */
-#define BITP_EMAC_MACCFG_IPC                 10                               /* IP Checksum */
-#define BITP_EMAC_MACCFG_DR                   9                               /* Disable Retry */
-#define BITP_EMAC_MACCFG_ACS                  7                               /* Automatic Pad/CRC Stripping */
-#define BITP_EMAC_MACCFG_BL                   5                               /* Back Off Limit */
-#define BITP_EMAC_MACCFG_DC                   4                               /* Deferral Check */
-#define BITP_EMAC_MACCFG_TE                   3                               /* Transmitter Enable */
-#define BITP_EMAC_MACCFG_RE                   2                               /* Receiver Enable */
-#define BITM_EMAC_MACCFG_CST                 (_ADI_MSK(0x02000000,uint32_t))  /* CRC Stripping */
-#define BITM_EMAC_MACCFG_WD                  (_ADI_MSK(0x00800000,uint32_t))  /* Watch Dog Disable */
-#define BITM_EMAC_MACCFG_JB                  (_ADI_MSK(0x00400000,uint32_t))  /* Jabber Disable */
-#define BITM_EMAC_MACCFG_JE                  (_ADI_MSK(0x00100000,uint32_t))  /* Jumbo Frame Enable */
-
-#define BITM_EMAC_MACCFG_IFG                 (_ADI_MSK(0x000E0000,uint32_t))  /* Inter Frame Gap */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_96        (_ADI_MSK(0x00000000,uint32_t))  /* IFG: 96 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_88        (_ADI_MSK(0x00020000,uint32_t))  /* IFG: 88 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_80        (_ADI_MSK(0x00040000,uint32_t))  /* IFG: 80 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_72        (_ADI_MSK(0x00060000,uint32_t))  /* IFG: 72 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_64        (_ADI_MSK(0x00080000,uint32_t))  /* IFG: 64 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_56        (_ADI_MSK(0x000A0000,uint32_t))  /* IFG: 56 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_48        (_ADI_MSK(0x000C0000,uint32_t))  /* IFG: 48 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_40        (_ADI_MSK(0x000E0000,uint32_t))  /* IFG: 40 bit times */
-#define BITM_EMAC_MACCFG_DCRS                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Carrier Sense */
-#define BITM_EMAC_MACCFG_FES                 (_ADI_MSK(0x00004000,uint32_t))  /* Speed of Operation */
-#define BITM_EMAC_MACCFG_DO                  (_ADI_MSK(0x00002000,uint32_t))  /* Disable Receive Own */
-#define BITM_EMAC_MACCFG_LM                  (_ADI_MSK(0x00001000,uint32_t))  /* Loopback Mode */
-#define BITM_EMAC_MACCFG_DM                  (_ADI_MSK(0x00000800,uint32_t))  /* Duplex Mode */
-#define BITM_EMAC_MACCFG_IPC                 (_ADI_MSK(0x00000400,uint32_t))  /* IP Checksum */
-
-#define BITM_EMAC_MACCFG_DR                  (_ADI_MSK(0x00000200,uint32_t))  /* Disable Retry */
-#define ENUM_EMAC_MACCFG_RETRY_ENABLED       (_ADI_MSK(0x00000000,uint32_t))  /* DR: Retry enabled */
-#define ENUM_EMAC_MACCFG_RETRY_DISABLED      (_ADI_MSK(0x00000200,uint32_t))  /* DR: Retry disabled */
-#define BITM_EMAC_MACCFG_ACS                 (_ADI_MSK(0x00000080,uint32_t))  /* Automatic Pad/CRC Stripping */
-
-#define BITM_EMAC_MACCFG_BL                  (_ADI_MSK(0x00000060,uint32_t))  /* Back Off Limit */
-#define ENUM_EMAC_MACCFG_BL_10               (_ADI_MSK(0x00000000,uint32_t))  /* BL: k = min (n, 10) */
-#define ENUM_EMAC_MACCFG_BL_8                (_ADI_MSK(0x00000020,uint32_t))  /* BL: k = min (n, 8) */
-#define ENUM_EMAC_MACCFG_BL_4                (_ADI_MSK(0x00000040,uint32_t))  /* BL: k = min (n, 4) */
-#define ENUM_EMAC_MACCFG_BL_1                (_ADI_MSK(0x00000060,uint32_t))  /* BL: k = min (n, 1) */
-#define BITM_EMAC_MACCFG_DC                  (_ADI_MSK(0x00000010,uint32_t))  /* Deferral Check */
-#define BITM_EMAC_MACCFG_TE                  (_ADI_MSK(0x00000008,uint32_t))  /* Transmitter Enable */
-#define BITM_EMAC_MACCFG_RE                  (_ADI_MSK(0x00000004,uint32_t))  /* Receiver Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACFRMFILT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACFRMFILT_RA              31                               /* Receive All Frames */
-#define BITP_EMAC_MACFRMFILT_HPF             10                               /* Hash or Perfect Filter */
-#define BITP_EMAC_MACFRMFILT_PCF              6                               /* Pass Control Frames */
-#define BITP_EMAC_MACFRMFILT_DBF              5                               /* Disable Broadcast Frames */
-#define BITP_EMAC_MACFRMFILT_PM               4                               /* Pass All Multicast Frames */
-#define BITP_EMAC_MACFRMFILT_DAIF             3                               /* Destination Address Inverse Filtering */
-#define BITP_EMAC_MACFRMFILT_HMC              2                               /* Hash Multicast */
-#define BITP_EMAC_MACFRMFILT_HUC              1                               /* Hash Unicast */
-#define BITP_EMAC_MACFRMFILT_PR               0                               /* Promiscuous Mode */
-#define BITM_EMAC_MACFRMFILT_RA              (_ADI_MSK(0x80000000,uint32_t))  /* Receive All Frames */
-#define BITM_EMAC_MACFRMFILT_HPF             (_ADI_MSK(0x00000400,uint32_t))  /* Hash or Perfect Filter */
-
-#define BITM_EMAC_MACFRMFILT_PCF             (_ADI_MSK(0x000000C0,uint32_t))  /* Pass Control Frames */
-#define ENUM_EMAC_MACFRMFILT_FILT_ALL        (_ADI_MSK(0x00000000,uint32_t))  /* PCF: Pass no control frames */
-#define ENUM_EMAC_MACFRMFILT_NO_PAUSE        (_ADI_MSK(0x00000040,uint32_t))  /* PCF: Pass no PAUSE frames */
-#define ENUM_EMAC_MACFRMFILT_FWD_ALL         (_ADI_MSK(0x00000080,uint32_t))  /* PCF: Pass all control frames */
-#define ENUM_EMAC_MACFRMFILT_PADR_FILT       (_ADI_MSK(0x000000C0,uint32_t))  /* PCF: Pass address filtered control frames */
-
-#define BITM_EMAC_MACFRMFILT_DBF             (_ADI_MSK(0x00000020,uint32_t))  /* Disable Broadcast Frames */
-#define ENUM_EMAC_MACFRMFILT_DIS_BCAST       (_ADI_MSK(0x00000000,uint32_t))  /* DBF: AFM module passes all received broadcast frames */
-#define ENUM_EMAC_MACFRMFILT_EN_BCAST        (_ADI_MSK(0x00000020,uint32_t))  /* DBF: AFM module filters all incoming broadcast frames */
-#define BITM_EMAC_MACFRMFILT_PM              (_ADI_MSK(0x00000010,uint32_t))  /* Pass All Multicast Frames */
-#define BITM_EMAC_MACFRMFILT_DAIF            (_ADI_MSK(0x00000008,uint32_t))  /* Destination Address Inverse Filtering */
-#define BITM_EMAC_MACFRMFILT_HMC             (_ADI_MSK(0x00000004,uint32_t))  /* Hash Multicast */
-#define BITM_EMAC_MACFRMFILT_HUC             (_ADI_MSK(0x00000002,uint32_t))  /* Hash Unicast */
-#define BITM_EMAC_MACFRMFILT_PR              (_ADI_MSK(0x00000001,uint32_t))  /* Promiscuous Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_ADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_ADDR_PA                11                               /* Physical Layer Address */
-#define BITP_EMAC_SMI_ADDR_SMIR               6                               /* SMI Register Address */
-#define BITP_EMAC_SMI_ADDR_CR                 2                               /* Clock Range */
-#define BITP_EMAC_SMI_ADDR_SMIW               1                               /* SMI Write */
-#define BITP_EMAC_SMI_ADDR_SMIB               0                               /* SMI Busy */
-#define BITM_EMAC_SMI_ADDR_PA                (_ADI_MSK(0x0000F800,uint32_t))  /* Physical Layer Address */
-#define BITM_EMAC_SMI_ADDR_SMIR              (_ADI_MSK(0x000007C0,uint32_t))  /* SMI Register Address */
-#define BITM_EMAC_SMI_ADDR_CR                (_ADI_MSK(0x0000003C,uint32_t))  /* Clock Range */
-#define BITM_EMAC_SMI_ADDR_SMIW              (_ADI_MSK(0x00000002,uint32_t))  /* SMI Write */
-#define BITM_EMAC_SMI_ADDR_SMIB              (_ADI_MSK(0x00000001,uint32_t))  /* SMI Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_DATA                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_DATA_SMID               0                               /* SMI Data */
-#define BITM_EMAC_SMI_DATA_SMID              (_ADI_MSK(0x0000FFFF,uint32_t))  /* SMI Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_FLOWCTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_FLOWCTL_PT                 16                               /* Pause Time */
-#define BITP_EMAC_FLOWCTL_UP                  3                               /* Unicast Pause Frame Detect */
-#define BITP_EMAC_FLOWCTL_RFE                 2                               /* Receive Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_TFE                 1                               /* Transmit Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_FCBBPA              0                               /* Initiate Pause Control Frame */
-#define BITM_EMAC_FLOWCTL_PT                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Pause Time */
-#define BITM_EMAC_FLOWCTL_UP                 (_ADI_MSK(0x00000008,uint32_t))  /* Unicast Pause Frame Detect */
-#define BITM_EMAC_FLOWCTL_RFE                (_ADI_MSK(0x00000004,uint32_t))  /* Receive Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_TFE                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_FCBBPA             (_ADI_MSK(0x00000001,uint32_t))  /* Initiate Pause Control Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_VLANTAG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_VLANTAG_ETV                16                               /* Enable Tag VLAN Comparison */
-#define BITP_EMAC_VLANTAG_VL                  0                               /* VLAN Tag Id Receive Frames */
-#define BITM_EMAC_VLANTAG_ETV                (_ADI_MSK(0x00010000,uint32_t))  /* Enable Tag VLAN Comparison */
-#define BITM_EMAC_VLANTAG_VL                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* VLAN Tag Id Receive Frames */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DBG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DBG_TXFIFOFULL             25                               /* Tx FIFO Full */
-#define BITP_EMAC_DBG_TXFIFONE               24                               /* Tx FIFO Not Empty */
-#define BITP_EMAC_DBG_TXFIFOACT              22                               /* Tx FIFO Active */
-#define BITP_EMAC_DBG_TXFIFOCTLST            20                               /* Tx FIFO Controller State */
-#define BITP_EMAC_DBG_TXPAUSE                19                               /* Tx Paused */
-#define BITP_EMAC_DBG_TXFRCTL                17                               /* Tx Frame Controller State */
-#define BITP_EMAC_DBG_MMTEA                  16                               /* MM Tx Engine Active */
-#define BITP_EMAC_DBG_RXFIFOST                8                               /* Rx FIFO State */
-#define BITP_EMAC_DBG_RXFIFOCTLST             5                               /* Rx FIFO Controller State */
-#define BITP_EMAC_DBG_RXFIFOACT               4                               /* Rx FIFO Active */
-#define BITP_EMAC_DBG_SFIFOST                 1                               /* Small FIFO State */
-#define BITP_EMAC_DBG_MMREA                   0                               /* MM Rx Engine Active */
-#define BITM_EMAC_DBG_TXFIFOFULL             (_ADI_MSK(0x02000000,uint32_t))  /* Tx FIFO Full */
-#define BITM_EMAC_DBG_TXFIFONE               (_ADI_MSK(0x01000000,uint32_t))  /* Tx FIFO Not Empty */
-#define BITM_EMAC_DBG_TXFIFOACT              (_ADI_MSK(0x00400000,uint32_t))  /* Tx FIFO Active */
-#define BITM_EMAC_DBG_TXFIFOCTLST            (_ADI_MSK(0x00300000,uint32_t))  /* Tx FIFO Controller State */
-#define BITM_EMAC_DBG_TXPAUSE                (_ADI_MSK(0x00080000,uint32_t))  /* Tx Paused */
-
-#define BITM_EMAC_DBG_TXFRCTL                (_ADI_MSK(0x00060000,uint32_t))  /* Tx Frame Controller State */
-#define ENUM_EMAC_DBG_TXFRCTL_IDLE           (_ADI_MSK(0x00000000,uint32_t))  /* TXFRCTL: Idle */
-#define ENUM_EMAC_DBG_TXFRCTL_WT_STATUS      (_ADI_MSK(0x00020000,uint32_t))  /* TXFRCTL: Wait */
-#define ENUM_EMAC_DBG_TXFRCTL_PAUSE          (_ADI_MSK(0x00040000,uint32_t))  /* TXFRCTL: Pause */
-#define ENUM_EMAC_DBG_TXFRCTL_TXFRAME        (_ADI_MSK(0x00060000,uint32_t))  /* TXFRCTL: Transmit */
-#define BITM_EMAC_DBG_MMTEA                  (_ADI_MSK(0x00010000,uint32_t))  /* MM Tx Engine Active */
-
-#define BITM_EMAC_DBG_RXFIFOST               (_ADI_MSK(0x00000300,uint32_t))  /* Rx FIFO State */
-#define ENUM_EMAC_DBG_FIFO_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOST: Rx FIFO Empty */
-#define ENUM_EMAC_DBG_FIFO_BEL_THERSHLD      (_ADI_MSK(0x00000100,uint32_t))  /* RXFIFOST: Rx FIFO Below De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_ABV_THERSHLD      (_ADI_MSK(0x00000200,uint32_t))  /* RXFIFOST: Rx FIFO Above De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_FULL              (_ADI_MSK(0x00000300,uint32_t))  /* RXFIFOST: Rx FIFO Full */
-
-#define BITM_EMAC_DBG_RXFIFOCTLST            (_ADI_MSK(0x00000060,uint32_t))  /* Rx FIFO Controller State */
-#define ENUM_EMAC_DBG_IDLE_FIFO              (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOCTLST: Idle */
-#define ENUM_EMAC_DBG_RD_DATA_FIFO           (_ADI_MSK(0x00000020,uint32_t))  /* RXFIFOCTLST: Read Data */
-#define ENUM_EMAC_DBG_RD_STS_FIFO            (_ADI_MSK(0x00000040,uint32_t))  /* RXFIFOCTLST: Read Status */
-#define ENUM_EMAC_DBG_FLUSH_FIFO             (_ADI_MSK(0x00000060,uint32_t))  /* RXFIFOCTLST: Flush */
-#define BITM_EMAC_DBG_RXFIFOACT              (_ADI_MSK(0x00000010,uint32_t))  /* Rx FIFO Active */
-#define BITM_EMAC_DBG_SFIFOST                (_ADI_MSK(0x00000006,uint32_t))  /* Small FIFO State */
-#define BITM_EMAC_DBG_MMREA                  (_ADI_MSK(0x00000001,uint32_t))  /* MM Rx Engine Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ISTAT_TS                    9                               /* Time Stamp Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRC                 7                               /* MMC Receive Checksum Offload Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCTX                 6                               /* MMC Transmit Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRX                 5                               /* MMC Receive Interrupt Status */
-#define BITP_EMAC_ISTAT_MMC                   4                               /* MMC Interrupt Status */
-#define BITM_EMAC_ISTAT_TS                   (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRC                (_ADI_MSK(0x00000080,uint32_t))  /* MMC Receive Checksum Offload Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCTX                (_ADI_MSK(0x00000040,uint32_t))  /* MMC Transmit Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRX                (_ADI_MSK(0x00000020,uint32_t))  /* MMC Receive Interrupt Status */
-#define BITM_EMAC_ISTAT_MMC                  (_ADI_MSK(0x00000010,uint32_t))  /* MMC Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IMSK_TS                     9                               /* Time Stamp Interrupt Mask */
-#define BITM_EMAC_IMSK_TS                    (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ADDR0_HI                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ADDR0_HI_ADDR               0                               /* Address */
-#define BITM_EMAC_ADDR0_HI_ADDR              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_CTL_FULLPSET            5                               /* Full Preset */
-#define BITP_EMAC_MMC_CTL_CNTRPSET            4                               /* Counter Reset/Preset */
-#define BITP_EMAC_MMC_CTL_CNTRFRZ             3                               /* Counter Freeze */
-#define BITP_EMAC_MMC_CTL_RDRST               2                               /* Read Reset */
-#define BITP_EMAC_MMC_CTL_NOROLL              1                               /* No Rollover */
-#define BITP_EMAC_MMC_CTL_RST                 0                               /* Reset */
-#define BITM_EMAC_MMC_CTL_FULLPSET           (_ADI_MSK(0x00000020,uint32_t))  /* Full Preset */
-#define BITM_EMAC_MMC_CTL_CNTRPSET           (_ADI_MSK(0x00000010,uint32_t))  /* Counter Reset/Preset */
-#define BITM_EMAC_MMC_CTL_CNTRFRZ            (_ADI_MSK(0x00000008,uint32_t))  /* Counter Freeze */
-#define BITM_EMAC_MMC_CTL_RDRST              (_ADI_MSK(0x00000004,uint32_t))  /* Read Reset */
-#define BITM_EMAC_MMC_CTL_NOROLL             (_ADI_MSK(0x00000002,uint32_t))  /* No Rollover */
-#define BITM_EMAC_MMC_CTL_RST                (_ADI_MSK(0x00000001,uint32_t))  /* Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXINT_WDOGERR          23                               /* Rx Watch Dog Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_VLANFRGB         22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_FIFOOVF          21                               /* Rx FIFO Overflow Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_PAUSEFR          20                               /* Rx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OUTRANGE         19                               /* Rx Out Of Range Type Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_LENERR           18                               /* Rx Length Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_UCASTG           17                               /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R1024TOMAX       16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R512TO1023       15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R256TO511        14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R128TO255        13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R65TO127         12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R64              11                               /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OSIZEG           10                               /* Rx Oversize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_USIZEG            9                               /* Rx Undersize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_JABERR            8                               /* Rx Jabber Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_RUNTERR           7                               /* Rx Runt Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_ALIGNERR          6                               /* Rx Alignment Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_CRCERR            5                               /* Rx CRC Error Counter Half/Full */
-#define BITP_EMAC_MMC_RXINT_MCASTG            4                               /* Rx Multicast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_BCASTG            3                               /* Rx Broadcast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTG           2                               /* Octet Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTGB          1                               /* Octet Count (Good/Bad) Half/Full */
-#define BITP_EMAC_MMC_RXINT_FRCNTGB           0                               /* Frame Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_WDOGERR          (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_VLANFRGB         (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_FIFOOVF          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_PAUSEFR          (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OUTRANGE         (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_LENERR           (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_UCASTG           (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R1024TOMAX       (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R512TO1023       (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R256TO511        (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R128TO255        (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R65TO127         (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R64              (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OSIZEG           (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_USIZEG           (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_JABERR           (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_RUNTERR          (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_ALIGNERR         (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_CRCERR           (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Counter Half/Full */
-#define BITM_EMAC_MMC_RXINT_MCASTG           (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_BCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTG          (_ADI_MSK(0x00000004,uint32_t))  /* Octet Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Octet Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_FRCNTGB          (_ADI_MSK(0x00000001,uint32_t))  /* Frame Count (Good/Bad) Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXINT_VLANFRGB         24                               /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_PAUSEFRM         23                               /* Tx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSDEF        22                               /* Tx Excess Deferred Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTG           21                               /* Tx Frame Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTG          20                               /* Tx Octet Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_CARRERR          19                               /* Tx Carrier Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSCOL        18                               /* Tx Exess Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_LATECOL          17                               /* Tx Late Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_DEFERRED         16                               /* Tx Deffered Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MULTCOLG         15                               /* Tx Multiple collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_SNGCOLG          14                               /* Tx Single Collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UNDERR           13                               /* Tx Underflow Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTGB          12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTGB          11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UCASTGB          10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T1024TOMAX        9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T512TO1023        8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T256TO511         7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T128TO255         6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T65TO127          5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T64               4                               /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTG            3                               /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTG            2                               /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTGB           1                               /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTGB          0                               /* Tx Octet Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_VLANFRGB         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_PAUSEFRM         (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSDEF        (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTG           (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTG          (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_CARRERR          (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSCOL        (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_LATECOL          (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_DEFERRED         (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deffered Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MULTCOLG         (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_SNGCOLG          (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UNDERR           (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTGB          (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTGB          (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UCASTGB          (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T1024TOMAX       (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T512TO1023       (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T256TO511        (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T128TO255        (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T65TO127         (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T64              (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTG           (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTGB          (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXIMSK_WATCHERR        23                               /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_VLANFRGB        22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FIFOOV          21                               /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_PAUSEFRM        20                               /* Rx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OUTRANGE        19                               /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_LENERR          18                               /* Rx Length Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_UCASTG          17                               /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R1024TOMAX      16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R512TO1023      15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R256TO511       14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R128TO255       13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R65TO127        12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R64             11                               /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OSIZEG          10                               /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_USIZEG           9                               /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_JABERR           8                               /* Rx Jabber Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_RUNTERR          7                               /* Rx Runt Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_ALIGNERR         6                               /* Rx Alignment Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_CRCERR           5                               /* Rx CRC Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_MCASTG           4                               /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_BCASTG           3                               /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTG          2                               /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTGB         1                               /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FRCNTGB          0                               /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_WATCHERR        (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_VLANFRGB        (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FIFOOV          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_PAUSEFRM        (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OUTRANGE        (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_LENERR          (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_UCASTG          (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R1024TOMAX      (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R512TO1023      (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R256TO511       (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R128TO255       (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R65TO127        (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R64             (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OSIZEG          (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_USIZEG          (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_JABERR          (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_RUNTERR         (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_ALIGNERR        (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_CRCERR          (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_MCASTG          (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_BCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTG         (_ADI_MSK(0x00000004,uint32_t))  /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTGB        (_ADI_MSK(0x00000002,uint32_t))  /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FRCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXIMSK_VLANFRG         24                               /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_PAUSEFRM        23                               /* Tx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSDEF       22                               /* Tx Excess Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTG          21                               /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTG         20                               /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_CARRERR         19                               /* Tx Carrier Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSCOL       18                               /* Tx Exess collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_LATECOL         17                               /* Tx Late Collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_DEFERRED        16                               /* Tx Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MULTCOLG        15                               /* Tx Multiple Collisions (Good) Count Mask */
-#define BITP_EMAC_MMC_TXIMSK_SNGCOLG         14                               /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UNDERR          13                               /* Tx Underflow Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTGB         12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTGB         11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UCASTGB         10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T1024TOMAX       9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T512TO1023       8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T256TO511        7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T128TO255        6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T65TO127         5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T64              4                               /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTG           3                               /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTG           2                               /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTGB          1                               /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTGB         0                               /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_VLANFRG         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_PAUSEFRM        (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSDEF       (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTG          (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTG         (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_CARRERR         (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSCOL       (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_LATECOL         (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_DEFERRED        (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MULTCOLG        (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple Collisions (Good) Count Mask */
-#define BITM_EMAC_MMC_TXIMSK_SNGCOLG         (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UNDERR          (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTGB         (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTGB         (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UCASTGB         (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T1024TOMAX      (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T512TO1023      (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T256TO511       (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T128TO255       (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T65TO127        (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T64             (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTG          (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTGB        (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERROCT      29                               /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGOCT        28                               /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERROCT       27                               /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGOCT         26                               /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERROCT       25                               /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGOCT         24                               /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYOCT      23                               /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERROCT      22                               /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GOCT          21                               /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLOCT      20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGOCT       19                               /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYOCT      18                               /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERROCT      17                               /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GOCT          16                               /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERRFRM      13                               /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGFRM        12                               /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERRFRM       11                               /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGFRM         10                               /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERRFRM        9                               /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGFRM          8                               /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYFRM       7                               /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERRFRM       6                               /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GFRM           5                               /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLFRM       4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGFRM        3                               /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYFRM       2                               /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERRFRM       1                               /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GFRM           0                               /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERROCT      (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGOCT        (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERROCT       (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGOCT         (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERROCT       (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGOCT         (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYOCT      (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERROCT      (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GOCT          (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLOCT      (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGOCT       (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYOCT      (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERROCT      (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GOCT          (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERRFRM      (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGFRM        (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERRFRM       (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGFRM         (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERRFRM       (_ADI_MSK(0x00000200,uint32_t))  /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGFRM         (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYFRM      (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERRFRM      (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GFRM          (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLFRM      (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGFRM       (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYFRM      (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERRFRM      (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GFRM          (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXINT_ICMPERROCT       29                               /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGOCT         28                               /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERROCT        27                               /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGOCT          26                               /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERROCT        25                               /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGOCT          24                               /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYOCT       23                               /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERROCT       22                               /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GOCT           21                               /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLOCT       20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGOCT        19                               /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYOCT       18                               /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERROCT       17                               /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GOCT           16                               /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPERRFRM       13                               /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGFRM         12                               /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERRFRM        11                               /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGFRM          10                               /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERRFRM         9                               /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGFRM           8                               /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYFRM        7                               /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERRFRM        6                               /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GFRM            5                               /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLFRM        4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGFRM         3                               /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYFRM        2                               /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERRFRM        1                               /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GFRM            0                               /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERROCT       (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGOCT         (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERROCT        (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGOCT          (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERROCT        (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGOCT          (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYOCT       (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERROCT       (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GOCT           (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLOCT       (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGOCT        (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYOCT       (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERROCT       (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GOCT           (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERRFRM       (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGFRM         (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERRFRM        (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGFRM          (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERRFRM        (_ADI_MSK(0x00000200,uint32_t))  /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGFRM          (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYFRM       (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERRFRM       (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GFRM           (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLFRM       (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGFRM        (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYFRM       (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERRFRM       (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GFRM           (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_CTL_ATSFC               24                               /* Auxilary Time Stamp FIFO Clear */
-#define BITP_EMAC_TM_CTL_TSENMACADDR         18                               /* Time Stamp Enable MAC Address */
-#define BITP_EMAC_TM_CTL_SNAPTYPSEL          16                               /* Snapshot Type Select */
-#define BITP_EMAC_TM_CTL_TSMSTRENA           15                               /* Time Stamp Master (Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSEVNTENA           14                               /* Time Stamp Event (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV4ENA           13                               /* Time Stamp IPV4 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV6ENA           12                               /* Time Stamp IPV6 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPENA             11                               /* Time Stamp IP Enable */
-#define BITP_EMAC_TM_CTL_TSVER2ENA           10                               /* Time Stamp VER2 (Snooping) Enable */
-#define BITP_EMAC_TM_CTL_TSCTRLSSR            9                               /* Time Stamp Control Nanosecond Rollover */
-#define BITP_EMAC_TM_CTL_TSENALL              8                               /* Time Stamp Enable All (Frames) */
-#define BITP_EMAC_TM_CTL_TSADDREG             5                               /* Time Stamp Addend Register Update */
-#define BITP_EMAC_TM_CTL_TSTRIG               4                               /* Time Stamp (Target Time) Trigger Enable */
-#define BITP_EMAC_TM_CTL_TSUPDT               3                               /* Time Stamp (System Time) Update */
-#define BITP_EMAC_TM_CTL_TSINIT               2                               /* Time Stamp (System Time) Initialize */
-#define BITP_EMAC_TM_CTL_TSCFUPDT             1                               /* Time Stamp (System Time) Fine/Coarse Update */
-#define BITP_EMAC_TM_CTL_TSENA                0                               /* Time Stamp (PTP) Enable */
-#define BITM_EMAC_TM_CTL_ATSFC               (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp FIFO Clear */
-
-#define BITM_EMAC_TM_CTL_TSENMACADDR         (_ADI_MSK(0x00040000,uint32_t))  /* Time Stamp Enable MAC Address */
-#define ENUM_EMAC_TM_CTL_D_PTP_ADDRFILT      (_ADI_MSK(0x00000000,uint32_t))  /* TSENMACADDR: Disable PTP MAC address filter */
-#define ENUM_EMAC_TM_CTL_E_PTP_ADDRFILT      (_ADI_MSK(0x00040000,uint32_t))  /* TSENMACADDR: Enable PTP MAC address filter */
-#define BITM_EMAC_TM_CTL_SNAPTYPSEL          (_ADI_MSK(0x00030000,uint32_t))  /* Snapshot Type Select */
-
-#define BITM_EMAC_TM_CTL_TSMSTRENA           (_ADI_MSK(0x00008000,uint32_t))  /* Time Stamp Master (Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_SLVSNPT_MSGS      (_ADI_MSK(0x00000000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Slave Messages */
-#define ENUM_EMAC_TM_CTL_E_MSSNPST_MSGS      (_ADI_MSK(0x00008000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Master Messages */
-
-#define BITM_EMAC_TM_CTL_TSEVNTENA           (_ADI_MSK(0x00004000,uint32_t))  /* Time Stamp Event (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_ATSTMP_MSGS       (_ADI_MSK(0x00000000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for All Messages */
-#define ENUM_EMAC_TM_CTL_E_ETSTMP_MSGS       (_ADI_MSK(0x00004000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for Event Messages Only */
-
-#define BITM_EMAC_TM_CTL_TSIPV4ENA           (_ADI_MSK(0x00002000,uint32_t))  /* Time Stamp IPV4 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV4        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV4ENA: Disable Time Stamp for PTP Over IPv4 Frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV4        (_ADI_MSK(0x00002000,uint32_t))  /* TSIPV4ENA: Enable Time Stamp for PTP Over IPv4 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPV6ENA           (_ADI_MSK(0x00001000,uint32_t))  /* Time Stamp IPV6 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV6        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV6ENA: Disable Time Stamp for PTP Over IPv6 frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV6        (_ADI_MSK(0x00001000,uint32_t))  /* TSIPV6ENA: Enable Time Stamp for PTP Over IPv6 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPENA             (_ADI_MSK(0x00000800,uint32_t))  /* Time Stamp IP Enable */
-#define ENUM_EMAC_TM_CTL_D_PTP_OV_ETHER      (_ADI_MSK(0x00000000,uint32_t))  /* TSIPENA: Disable PTP Over Ethernet Frames */
-#define ENUM_EMAC_TM_CTL_E_PTP_OV_ETHER      (_ADI_MSK(0x00000800,uint32_t))  /* TSIPENA: Enable PTP Over Ethernet Frames */
-
-#define BITM_EMAC_TM_CTL_TSVER2ENA           (_ADI_MSK(0x00000400,uint32_t))  /* Time Stamp VER2 (Snooping) Enable */
-#define ENUM_EMAC_TM_CTL_D_PKT_SNOOP_V2      (_ADI_MSK(0x00000000,uint32_t))  /* TSVER2ENA: Disable packet snooping for V2 frames */
-#define ENUM_EMAC_TM_CTL_E_PKT_SNOOP_V2      (_ADI_MSK(0x00000400,uint32_t))  /* TSVER2ENA: Enable packet snooping for V2 frames */
-
-#define BITM_EMAC_TM_CTL_TSCTRLSSR           (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Control Nanosecond Rollover */
-#define ENUM_EMAC_TM_CTL_RO_SUBSEC_RES       (_ADI_MSK(0x00000000,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x7FFFFFFF */
-#define ENUM_EMAC_TM_CTL_RO_NANO_RES         (_ADI_MSK(0x00000200,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x3B9AC9FF */
-
-#define BITM_EMAC_TM_CTL_TSENALL             (_ADI_MSK(0x00000100,uint32_t))  /* Time Stamp Enable All (Frames) */
-#define ENUM_EMAC_TM_CTL_D_TSALL_FRAMES      (_ADI_MSK(0x00000000,uint32_t))  /* TSENALL: Disable timestamp for all frames */
-#define ENUM_EMAC_TM_CTL_E_TSALL_FRAMES      (_ADI_MSK(0x00000100,uint32_t))  /* TSENALL: Enable timestamp for all frames */
-#define BITM_EMAC_TM_CTL_TSADDREG            (_ADI_MSK(0x00000020,uint32_t))  /* Time Stamp Addend Register Update */
-
-#define BITM_EMAC_TM_CTL_TSTRIG              (_ADI_MSK(0x00000010,uint32_t))  /* Time Stamp (Target Time) Trigger Enable */
-#define ENUM_EMAC_TM_CTL_EN_TRIGGER          (_ADI_MSK(0x00000010,uint32_t))  /* TSTRIG: Interrupt (TS) if system time is greater than target time register */
-
-#define BITM_EMAC_TM_CTL_TSUPDT              (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp (System Time) Update */
-#define ENUM_EMAC_TM_CTL_EN_UPDATE           (_ADI_MSK(0x00000008,uint32_t))  /* TSUPDT: System time updated with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSINIT              (_ADI_MSK(0x00000004,uint32_t))  /* Time Stamp (System Time) Initialize */
-#define ENUM_EMAC_TM_CTL_EN_TS_INIT          (_ADI_MSK(0x00000004,uint32_t))  /* TSINIT: System time initialized with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSCFUPDT            (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp (System Time) Fine/Coarse Update */
-#define ENUM_EMAC_TM_CTL_EN_COARSE_UPDT      (_ADI_MSK(0x00000000,uint32_t))  /* TSCFUPDT: Use Coarse Correction Method for System Time Update */
-#define ENUM_EMAC_TM_CTL_EN_FINE_UPDT        (_ADI_MSK(0x00000002,uint32_t))  /* TSCFUPDT: Use Fine Correction Method for System Time Update */
-
-#define BITM_EMAC_TM_CTL_TSENA               (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp (PTP) Enable */
-#define ENUM_EMAC_TM_CTL_DTS                 (_ADI_MSK(0x00000000,uint32_t))  /* TSENA: Disable PTP Module */
-#define ENUM_EMAC_TM_CTL_TS                  (_ADI_MSK(0x00000001,uint32_t))  /* TSENA: Enable PTP Module */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_SUBSEC                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_SUBSEC_SSINC             0                               /* Sub-Second Increment Value */
-#define BITM_EMAC_TM_SUBSEC_SSINC            (_ADI_MSK(0x000000FF,uint32_t))  /* Sub-Second Increment Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSEC                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSEC_TSSS                0                               /* Time Stamp Nanoseconds */
-#define BITM_EMAC_TM_NSEC_TSSS               (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Nanoseconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSECUPDT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSECUPDT_ADDSUB         31                               /* Add or Subtract the Time */
-#define BITP_EMAC_TM_NSECUPDT_TSSS            0                               /* Time Stamp Sub Second Initialize/Increment */
-#define BITM_EMAC_TM_NSECUPDT_ADDSUB         (_ADI_MSK(0x80000000,uint32_t))  /* Add or Subtract the Time */
-#define BITM_EMAC_TM_NSECUPDT_TSSS           (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Sub Second Initialize/Increment */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NTGTM                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NTGTM_TSTRBUSY          31                               /* Target Time Register Busy */
-#define BITP_EMAC_TM_NTGTM_TSTR               0                               /* Target Time Nano Seconds */
-#define BITM_EMAC_TM_NTGTM_TSTRBUSY          (_ADI_MSK(0x80000000,uint32_t))  /* Target Time Register Busy */
-#define BITM_EMAC_TM_NTGTM_TSTR              (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Target Time Nano Seconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_HISEC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_HISEC_TSHWR              0                               /* Time Stamp Higher Word Seconds Register */
-#define BITM_EMAC_TM_HISEC_TSHWR             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Time Stamp Higher Word Seconds Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_STMPSTAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_STMPSTAT_ATSNS          25                               /* Auxilary Time Stamp Number of Snapshots */
-#define BITP_EMAC_TM_STMPSTAT_ATSSTM         24                               /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITP_EMAC_TM_STMPSTAT_TSTRGTERR       3                               /* Time Stamp Target Time Programming Error */
-#define BITP_EMAC_TM_STMPSTAT_ATSTS           2                               /* Auxilary Time Stamp Trigger Snapshot */
-#define BITP_EMAC_TM_STMPSTAT_TSTARGT         1                               /* Time Stamp Target Time Reached */
-#define BITP_EMAC_TM_STMPSTAT_TSSOVF          0                               /* Time Stamp Seconds Overflow */
-#define BITM_EMAC_TM_STMPSTAT_ATSNS          (_ADI_MSK(0x0E000000,uint32_t))  /* Auxilary Time Stamp Number of Snapshots */
-#define BITM_EMAC_TM_STMPSTAT_ATSSTM         (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITM_EMAC_TM_STMPSTAT_TSTRGTERR      (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp Target Time Programming Error */
-#define BITM_EMAC_TM_STMPSTAT_ATSTS          (_ADI_MSK(0x00000004,uint32_t))  /* Auxilary Time Stamp Trigger Snapshot */
-#define BITM_EMAC_TM_STMPSTAT_TSTARGT        (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp Target Time Reached */
-#define BITM_EMAC_TM_STMPSTAT_TSSOVF         (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp Seconds Overflow */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_PPSCTL                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_PPSCTL_TRGTMODSEL        5                               /* Target Time Register Mode */
-#define BITP_EMAC_TM_PPSCTL_PPSEN             4                               /* Enable the flexible PPS output mode */
-#define BITP_EMAC_TM_PPSCTL_PPSCTL            0                               /* PPS Frequency Control */
-#define BITM_EMAC_TM_PPSCTL_TRGTMODSEL       (_ADI_MSK(0x00000060,uint32_t))  /* Target Time Register Mode */
-#define BITM_EMAC_TM_PPSCTL_PPSEN            (_ADI_MSK(0x00000010,uint32_t))  /* Enable the flexible PPS output mode */
-#define BITM_EMAC_TM_PPSCTL_PPSCTL           (_ADI_MSK(0x0000000F,uint32_t))  /* PPS Frequency Control */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BUSMODE                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BUSMODE_AAL            25                               /* Address Aligned Bursts */
-#define BITP_EMAC_DMA_BUSMODE_PBL8           24                               /* PBL * 8 */
-#define BITP_EMAC_DMA_BUSMODE_USP            23                               /* Use Separate PBL */
-#define BITP_EMAC_DMA_BUSMODE_RPBL           17                               /* Receive Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_FB             16                               /* Fixed Burst */
-#define BITP_EMAC_DMA_BUSMODE_PBL             8                               /* Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_ATDS            7                               /* Alternate Descriptor Size */
-#define BITP_EMAC_DMA_BUSMODE_DSL             2                               /* Descriptor Skip Length */
-#define BITP_EMAC_DMA_BUSMODE_SWR             0                               /* Software Reset */
-#define BITM_EMAC_DMA_BUSMODE_AAL            (_ADI_MSK(0x02000000,uint32_t))  /* Address Aligned Bursts */
-#define BITM_EMAC_DMA_BUSMODE_PBL8           (_ADI_MSK(0x01000000,uint32_t))  /* PBL * 8 */
-#define BITM_EMAC_DMA_BUSMODE_USP            (_ADI_MSK(0x00800000,uint32_t))  /* Use Separate PBL */
-#define BITM_EMAC_DMA_BUSMODE_RPBL           (_ADI_MSK(0x007E0000,uint32_t))  /* Receive Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_FB             (_ADI_MSK(0x00010000,uint32_t))  /* Fixed Burst */
-#define BITM_EMAC_DMA_BUSMODE_PBL            (_ADI_MSK(0x00003F00,uint32_t))  /* Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_ATDS           (_ADI_MSK(0x00000080,uint32_t))  /* Alternate Descriptor Size */
-#define BITM_EMAC_DMA_BUSMODE_DSL            (_ADI_MSK(0x0000007C,uint32_t))  /* Descriptor Skip Length */
-#define BITM_EMAC_DMA_BUSMODE_SWR            (_ADI_MSK(0x00000001,uint32_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_STAT_TTI               29                               /* Time Stamp Trigger Interrupt */
-#define BITP_EMAC_DMA_STAT_MCI               27                               /* MAC MMC Interrupt */
-#define BITP_EMAC_DMA_STAT_EB                23                               /* Error Bits */
-#define BITP_EMAC_DMA_STAT_TS                20                               /* Transmit Process State */
-#define BITP_EMAC_DMA_STAT_RS                17                               /* Receive Process State */
-#define BITP_EMAC_DMA_STAT_NIS               16                               /* Normal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_AIS               15                               /* Abnormal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_ERI               14                               /* Early Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_FBI               13                               /* Fatal Bus Error Interrupt */
-#define BITP_EMAC_DMA_STAT_ETI               10                               /* Early Transmit Interrupt */
-#define BITP_EMAC_DMA_STAT_RWT                9                               /* Receive WatchDog Timeout */
-#define BITP_EMAC_DMA_STAT_RPS                8                               /* Receive Process Stopped */
-#define BITP_EMAC_DMA_STAT_RU                 7                               /* Receive Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_RI                 6                               /* Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_UNF                5                               /* Transmit Buffer Underflow */
-#define BITP_EMAC_DMA_STAT_OVF                4                               /* Receive Buffer Overflow */
-#define BITP_EMAC_DMA_STAT_TJT                3                               /* Transmit Jabber Timeout */
-#define BITP_EMAC_DMA_STAT_TU                 2                               /* Transmit Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_TPS                1                               /* Transmit Process Stopped */
-#define BITP_EMAC_DMA_STAT_TI                 0                               /* Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_TTI               (_ADI_MSK(0x20000000,uint32_t))  /* Time Stamp Trigger Interrupt */
-#define BITM_EMAC_DMA_STAT_MCI               (_ADI_MSK(0x08000000,uint32_t))  /* MAC MMC Interrupt */
-#define BITM_EMAC_DMA_STAT_EB                (_ADI_MSK(0x03800000,uint32_t))  /* Error Bits */
-
-#define BITM_EMAC_DMA_STAT_TS                (_ADI_MSK(0x00700000,uint32_t))  /* Transmit Process State */
-#define ENUM_EMAC_DMA_STAT_TS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* TS: Stopped; Reset or Stop Transmit Command issued */
-#define ENUM_EMAC_DMA_STAT_TS_R_FTD          (_ADI_MSK(0x00100000,uint32_t))  /* TS: Running; Fetching Transmit Transfer Descriptor */
-#define ENUM_EMAC_DMA_STAT_TS_R_WSTAT        (_ADI_MSK(0x00200000,uint32_t))  /* TS: Running; Waiting for status */
-#define ENUM_EMAC_DMA_STAT_TS_R_TXHMBUF      (_ADI_MSK(0x00300000,uint32_t))  /* TS: Reading Data from host memory buffer and queuing it to TX buffer */
-#define ENUM_EMAC_DMA_STAT_TS_WR_TSTMP       (_ADI_MSK(0x00400000,uint32_t))  /* TS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_TS_SUSPENDED      (_ADI_MSK(0x00600000,uint32_t))  /* TS: Suspended; Transmit Descriptor Unavailable or TX Buffer Underflow */
-#define ENUM_EMAC_DMA_STAT_TS_R_CLSTD        (_ADI_MSK(0x00700000,uint32_t))  /* TS: Closing Transmit Descriptor */
-
-#define BITM_EMAC_DMA_STAT_RS                (_ADI_MSK(0x000E0000,uint32_t))  /* Receive Process State */
-#define ENUM_EMAC_DMA_STAT_RS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* RS: Stopped: Reset or Stop Receive Command issued. */
-#define ENUM_EMAC_DMA_STAT_RS_R_FRD          (_ADI_MSK(0x00020000,uint32_t))  /* RS: Running: Fetching Receive Transfer Descriptor. */
-#define ENUM_EMAC_DMA_STAT_RS_R_WTRX         (_ADI_MSK(0x00060000,uint32_t))  /* RS: Running: Waiting for receive packet */
-#define ENUM_EMAC_DMA_STAT_RS_SUSPENDED      (_ADI_MSK(0x00080000,uint32_t))  /* RS: Suspended: Receive Descriptor Unavailable */
-#define ENUM_EMAC_DMA_STAT_RS_R_CLSRD        (_ADI_MSK(0x000A0000,uint32_t))  /* RS: Running: Closing Receive Descriptor */
-#define ENUM_EMAC_DMA_STAT_RS_WR_TSTMP       (_ADI_MSK(0x000C0000,uint32_t))  /* RS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_RS_R_RXWRHM       (_ADI_MSK(0x000E0000,uint32_t))  /* RS: Running: Transferring RX packet data from RX buffer to host memory */
-#define BITM_EMAC_DMA_STAT_NIS               (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_AIS               (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_ERI               (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_FBI               (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Interrupt */
-#define BITM_EMAC_DMA_STAT_ETI               (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_RWT               (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchDog Timeout */
-#define BITM_EMAC_DMA_STAT_RPS               (_ADI_MSK(0x00000100,uint32_t))  /* Receive Process Stopped */
-#define BITM_EMAC_DMA_STAT_RU                (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_RI                (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_UNF               (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Buffer Underflow */
-#define BITM_EMAC_DMA_STAT_OVF               (_ADI_MSK(0x00000010,uint32_t))  /* Receive Buffer Overflow */
-#define BITM_EMAC_DMA_STAT_TJT               (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout */
-#define BITM_EMAC_DMA_STAT_TU                (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_TPS               (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Process Stopped */
-#define BITM_EMAC_DMA_STAT_TI                (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_OPMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_OPMODE_DT              26                               /* Disable Dropping TCP/IP Errors */
-#define BITP_EMAC_DMA_OPMODE_RSF             25                               /* Receive Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_DFF             24                               /* Disable Flushing of received Frames */
-#define BITP_EMAC_DMA_OPMODE_TSF             21                               /* Transmit Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_FTF             20                               /* Flush Transmit FIFO */
-#define BITP_EMAC_DMA_OPMODE_TTC             14                               /* Transmit Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_ST              13                               /* Start/Stop Transmission */
-#define BITP_EMAC_DMA_OPMODE_FEF              7                               /* Forward Error Frames */
-#define BITP_EMAC_DMA_OPMODE_FUF              6                               /* Forward Undersized good Frames */
-#define BITP_EMAC_DMA_OPMODE_RTC              3                               /* Receive Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_OSF              2                               /* Operate on Second Frame */
-#define BITP_EMAC_DMA_OPMODE_SR               1                               /* Start/Stop Receive */
-#define BITM_EMAC_DMA_OPMODE_DT              (_ADI_MSK(0x04000000,uint32_t))  /* Disable Dropping TCP/IP Errors */
-#define BITM_EMAC_DMA_OPMODE_RSF             (_ADI_MSK(0x02000000,uint32_t))  /* Receive Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_DFF             (_ADI_MSK(0x01000000,uint32_t))  /* Disable Flushing of received Frames */
-#define BITM_EMAC_DMA_OPMODE_TSF             (_ADI_MSK(0x00200000,uint32_t))  /* Transmit Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_FTF             (_ADI_MSK(0x00100000,uint32_t))  /* Flush Transmit FIFO */
-
-#define BITM_EMAC_DMA_OPMODE_TTC             (_ADI_MSK(0x0001C000,uint32_t))  /* Transmit Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_TTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* TTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_128         (_ADI_MSK(0x00004000,uint32_t))  /* TTC: 128 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_192         (_ADI_MSK(0x00008000,uint32_t))  /* TTC: 192 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_256         (_ADI_MSK(0x0000C000,uint32_t))  /* TTC: 256 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_40          (_ADI_MSK(0x00010000,uint32_t))  /* TTC: 40 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_32          (_ADI_MSK(0x00014000,uint32_t))  /* TTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_24          (_ADI_MSK(0x00018000,uint32_t))  /* TTC: 24 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_16          (_ADI_MSK(0x0001C000,uint32_t))  /* TTC: 16 */
-#define BITM_EMAC_DMA_OPMODE_ST              (_ADI_MSK(0x00002000,uint32_t))  /* Start/Stop Transmission */
-#define BITM_EMAC_DMA_OPMODE_FEF             (_ADI_MSK(0x00000080,uint32_t))  /* Forward Error Frames */
-#define BITM_EMAC_DMA_OPMODE_FUF             (_ADI_MSK(0x00000040,uint32_t))  /* Forward Undersized good Frames */
-
-#define BITM_EMAC_DMA_OPMODE_RTC             (_ADI_MSK(0x00000018,uint32_t))  /* Receive Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_RTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* RTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_32          (_ADI_MSK(0x00000008,uint32_t))  /* RTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_96          (_ADI_MSK(0x00000010,uint32_t))  /* RTC: 96 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_128         (_ADI_MSK(0x00000018,uint32_t))  /* RTC: 128 */
-#define BITM_EMAC_DMA_OPMODE_OSF             (_ADI_MSK(0x00000004,uint32_t))  /* Operate on Second Frame */
-#define BITM_EMAC_DMA_OPMODE_SR              (_ADI_MSK(0x00000002,uint32_t))  /* Start/Stop Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_IEN                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_IEN_NIS                16                               /* Normal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_AIS                15                               /* Abnormal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_ERI                14                               /* Early Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_FBI                13                               /* Fatal Bus Error Enable */
-#define BITP_EMAC_DMA_IEN_ETI                10                               /* Early Transmit Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_RWT                 9                               /* Receive WatchdogTimeout Enable */
-#define BITP_EMAC_DMA_IEN_RPS                 8                               /* Receive Stopped Enable */
-#define BITP_EMAC_DMA_IEN_RU                  7                               /* Receive Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_RI                  6                               /* Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_UNF                 5                               /* Underflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_OVF                 4                               /* Overflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_TJT                 3                               /* Transmit Jabber Timeout Enable */
-#define BITP_EMAC_DMA_IEN_TU                  2                               /* Transmit Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_TPS                 1                               /* Transmit Stopped Enable */
-#define BITP_EMAC_DMA_IEN_TI                  0                               /* Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_NIS                (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_AIS                (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_ERI                (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_FBI                (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Enable */
-#define BITM_EMAC_DMA_IEN_ETI                (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_RWT                (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchdogTimeout Enable */
-#define BITM_EMAC_DMA_IEN_RPS                (_ADI_MSK(0x00000100,uint32_t))  /* Receive Stopped Enable */
-#define BITM_EMAC_DMA_IEN_RU                 (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_RI                 (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_UNF                (_ADI_MSK(0x00000020,uint32_t))  /* Underflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_OVF                (_ADI_MSK(0x00000010,uint32_t))  /* Overflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_TJT                (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout Enable */
-#define BITM_EMAC_DMA_IEN_TU                 (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_TPS                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Stopped Enable */
-#define BITM_EMAC_DMA_IEN_TI                 (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_MISS_FRM                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_MISS_FRM_OVFFIFO       28                               /* Overflow bit for FIFO Overflow Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFROV      17                               /* Missed Frames Buffer Overflow */
-#define BITP_EMAC_DMA_MISS_FRM_OVFMISS       16                               /* Overflow bit for Missed Frame Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFRUN       0                               /* Missed Frames Unavailable Buffer */
-#define BITM_EMAC_DMA_MISS_FRM_OVFFIFO       (_ADI_MSK(0x10000000,uint32_t))  /* Overflow bit for FIFO Overflow Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFROV      (_ADI_MSK(0x0FFE0000,uint32_t))  /* Missed Frames Buffer Overflow */
-#define BITM_EMAC_DMA_MISS_FRM_OVFMISS       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow bit for Missed Frame Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFRUN      (_ADI_MSK(0x0000FFFF,uint32_t))  /* Missed Frames Unavailable Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_RXIWDOG                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_RXIWDOG_RIWT            0                               /* RI WatchDog Timer Count */
-#define BITM_EMAC_DMA_RXIWDOG_RIWT           (_ADI_MSK(0x000000FF,uint32_t))  /* RI WatchDog Timer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMMODE_WROSRLMT        20                               /* SCB Maximum Write Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_RDOSRLMT        16                               /* SCB Maximum Read Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_AAL             12                               /* Address Aligned Beats */
-#define BITP_EMAC_DMA_BMMODE_BLEN16           3                               /* SCB Burst Length 16 */
-#define BITP_EMAC_DMA_BMMODE_BLEN8            2                               /* SCB Burst Length 8 */
-#define BITP_EMAC_DMA_BMMODE_BLEN4            1                               /* SCB Burst Length 4 */
-#define BITP_EMAC_DMA_BMMODE_UNDEF            0                               /* SCB Undefined Burst Length */
-#define BITM_EMAC_DMA_BMMODE_WROSRLMT        (_ADI_MSK(0x00700000,uint32_t))  /* SCB Maximum Write Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_RDOSRLMT        (_ADI_MSK(0x00070000,uint32_t))  /* SCB Maximum Read Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_AAL             (_ADI_MSK(0x00001000,uint32_t))  /* Address Aligned Beats */
-#define BITM_EMAC_DMA_BMMODE_BLEN16          (_ADI_MSK(0x00000008,uint32_t))  /* SCB Burst Length 16 */
-#define BITM_EMAC_DMA_BMMODE_BLEN8           (_ADI_MSK(0x00000004,uint32_t))  /* SCB Burst Length 8 */
-#define BITM_EMAC_DMA_BMMODE_BLEN4           (_ADI_MSK(0x00000002,uint32_t))  /* SCB Burst Length 4 */
-#define BITM_EMAC_DMA_BMMODE_UNDEF           (_ADI_MSK(0x00000001,uint32_t))  /* SCB Undefined Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMSTAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMSTAT_BUSRD            1                               /* Bus (SCB master) Read Active */
-#define BITP_EMAC_DMA_BMSTAT_BUSWR            0                               /* Bus (SCB master) Write Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSRD           (_ADI_MSK(0x00000002,uint32_t))  /* Bus (SCB master) Read Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSWR           (_ADI_MSK(0x00000001,uint32_t))  /* Bus (SCB master) Write Active */
-
-/* ==================================================
-        Serial Port Registers
-   ================================================== */
-
-/* =========================
-        SPORT0
-   ========================= */
-#define REG_SPORT0_CTL_A                0xFFC40000         /* SPORT0 Half SPORT 'A' Control Register */
-#define REG_SPORT0_DIV_A                0xFFC40004         /* SPORT0 Half SPORT 'A' Divisor Register */
-#define REG_SPORT0_MCTL_A               0xFFC40008         /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT0_CS0_A                0xFFC4000C         /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_A                0xFFC40010         /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_A                0xFFC40014         /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT0_CS3_A                0xFFC40018         /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT0_ERR_A                0xFFC40020         /* SPORT0 Half SPORT 'A' Error Register */
-#define REG_SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_A               0xFFC40028         /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT0_CTL_B                0xFFC40080         /* SPORT0 Half SPORT 'B' Control Register */
-#define REG_SPORT0_DIV_B                0xFFC40084         /* SPORT0 Half SPORT 'B' Divisor Register */
-#define REG_SPORT0_MCTL_B               0xFFC40088         /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT0_CS0_B                0xFFC4008C         /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_B                0xFFC40090         /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_B                0xFFC40094         /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT0_CS3_B                0xFFC40098         /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT0_ERR_B                0xFFC400A0         /* SPORT0 Half SPORT 'B' Error Register */
-#define REG_SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT1
-   ========================= */
-#define REG_SPORT1_CTL_A                0xFFC40100         /* SPORT1 Half SPORT 'A' Control Register */
-#define REG_SPORT1_DIV_A                0xFFC40104         /* SPORT1 Half SPORT 'A' Divisor Register */
-#define REG_SPORT1_MCTL_A               0xFFC40108         /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT1_CS0_A                0xFFC4010C         /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_A                0xFFC40110         /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_A                0xFFC40114         /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT1_CS3_A                0xFFC40118         /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT1_ERR_A                0xFFC40120         /* SPORT1 Half SPORT 'A' Error Register */
-#define REG_SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_A               0xFFC40128         /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT1_CTL_B                0xFFC40180         /* SPORT1 Half SPORT 'B' Control Register */
-#define REG_SPORT1_DIV_B                0xFFC40184         /* SPORT1 Half SPORT 'B' Divisor Register */
-#define REG_SPORT1_MCTL_B               0xFFC40188         /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT1_CS0_B                0xFFC4018C         /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_B                0xFFC40190         /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_B                0xFFC40194         /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT1_CS3_B                0xFFC40198         /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT1_ERR_B                0xFFC401A0         /* SPORT1 Half SPORT 'B' Error Register */
-#define REG_SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT2
-   ========================= */
-#define REG_SPORT2_CTL_A                0xFFC40200         /* SPORT2 Half SPORT 'A' Control Register */
-#define REG_SPORT2_DIV_A                0xFFC40204         /* SPORT2 Half SPORT 'A' Divisor Register */
-#define REG_SPORT2_MCTL_A               0xFFC40208         /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT2_CS0_A                0xFFC4020C         /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_A                0xFFC40210         /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_A                0xFFC40214         /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT2_CS3_A                0xFFC40218         /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT2_ERR_A                0xFFC40220         /* SPORT2 Half SPORT 'A' Error Register */
-#define REG_SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_A               0xFFC40228         /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT2_CTL_B                0xFFC40280         /* SPORT2 Half SPORT 'B' Control Register */
-#define REG_SPORT2_DIV_B                0xFFC40284         /* SPORT2 Half SPORT 'B' Divisor Register */
-#define REG_SPORT2_MCTL_B               0xFFC40288         /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT2_CS0_B                0xFFC4028C         /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_B                0xFFC40290         /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_B                0xFFC40294         /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT2_CS3_B                0xFFC40298         /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT2_ERR_B                0xFFC402A0         /* SPORT2 Half SPORT 'B' Error Register */
-#define REG_SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_A_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_DXSPRI                30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_A_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_DERRPRI               29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_A_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_DXSSEC                27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_A_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_DERRSEC               26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_A_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_SPTRAN                25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_A_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_SPENSEC               24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_A_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_GCLKEN                21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_A_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_TFIEN                 20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_A_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_FSED                  19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_A_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_RJUST                 18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_A_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_LAFS                  17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_A_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_LFS                   16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_A_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_DIFS                  15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_A_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_IFS                   14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_A_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_FSR                   13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_A_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_CKRE                  12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_A_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_OPMODE                11                               /* Operation mode */
-#define BITP_SPORT_CTL_A_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_ICLK                  10                               /* Internal Clock */
-#define BITP_SPORT_CTL_A_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_PACK                   9                               /* Packing Enable */
-#define BITP_SPORT_CTL_A_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_SLEN                   4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_A_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_LSBF                   3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_A_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_DTYPE                  1                               /* Data Type */
-#define BITP_SPORT_CTL_A_SPENPRI              0                               /* Serial Port Enable (Primary) */
-#define BITP_SPORT_CTL_SPENPRI                0                               /* Serial Port Enable (Primary) */
-
-#define BITM_SPORT_CTL_A_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_DXSPRI                (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSPRI: Empty */
-#define ENUM_SPORT_CTL_PRM_PART_FULL         (_ADI_MSK(0x80000000,uint32_t))  /* DXSPRI: Partially full */
-#define ENUM_SPORT_CTL_PRM_FULL              (_ADI_MSK(0xC0000000,uint32_t))  /* DXSPRI: Full */
-
-#define BITM_SPORT_CTL_A_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_DERRPRI               (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRPRI: No error */
-#define ENUM_SPORT_CTL_PRM_ERR               (_ADI_MSK(0x20000000,uint32_t))  /* DERRPRI: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_DXSSEC                (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSSEC: Empty */
-#define ENUM_SPORT_CTL_SEC_PART_FULL         (_ADI_MSK(0x10000000,uint32_t))  /* DXSSEC: Partially full */
-#define ENUM_SPORT_CTL_SEC_FULL              (_ADI_MSK(0x18000000,uint32_t))  /* DXSSEC: Full */
-
-#define BITM_SPORT_CTL_A_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_DERRSEC               (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRSEC: No error */
-#define ENUM_SPORT_CTL_SEC_ERR               (_ADI_MSK(0x04000000,uint32_t))  /* DERRSEC: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_SPTRAN                (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define ENUM_SPORT_CTL_RX                    (_ADI_MSK(0x00000000,uint32_t))  /* SPTRAN: Receive */
-#define ENUM_SPORT_CTL_TX                    (_ADI_MSK(0x02000000,uint32_t))  /* SPTRAN: Transmit */
-
-#define BITM_SPORT_CTL_A_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_SPENSEC               (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define ENUM_SPORT_CTL_SECONDARY_DIS         (_ADI_MSK(0x00000000,uint32_t))  /* SPENSEC: Disable */
-#define ENUM_SPORT_CTL_SECONDARY_EN          (_ADI_MSK(0x01000000,uint32_t))  /* SPENSEC: Enable */
-
-#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_GCLKEN                (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define ENUM_SPORT_CTL_GCLK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* GCLKEN: Disable */
-#define ENUM_SPORT_CTL_GCLK_EN               (_ADI_MSK(0x00200000,uint32_t))  /* GCLKEN: Enable */
-
-#define BITM_SPORT_CTL_A_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_TFIEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define ENUM_SPORT_CTL_TXFIN_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TFIEN: Last word sent (DMA count done) interrupt */
-#define ENUM_SPORT_CTL_TXFIN_EN              (_ADI_MSK(0x00100000,uint32_t))  /* TFIEN: Last bit sent (Tx buffer done) interrupt */
-
-#define BITM_SPORT_CTL_A_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_FSED                  (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define ENUM_SPORT_CTL_LEVEL_FS              (_ADI_MSK(0x00000000,uint32_t))  /* FSED: Level detect frame sync */
-#define ENUM_SPORT_CTL_EDGE_FS               (_ADI_MSK(0x00080000,uint32_t))  /* FSED: Edge detect frame sync */
-
-#define BITM_SPORT_CTL_A_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_RJUST                 (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define ENUM_SPORT_CTL_RJUST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RJUST: Disable */
-#define ENUM_SPORT_CTL_RJUST_EN              (_ADI_MSK(0x00040000,uint32_t))  /* RJUST: Enable */
-
-#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_LAFS                  (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define ENUM_SPORT_CTL_EARLY_FS              (_ADI_MSK(0x00000000,uint32_t))  /* LAFS: Early frame sync */
-#define ENUM_SPORT_CTL_LATE_FS               (_ADI_MSK(0x00020000,uint32_t))  /* LAFS: Late frame sync */
-
-#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_LFS                   (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define ENUM_SPORT_CTL_FS_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* LFS: Active high frame sync (DSP standard mode) */
-#define ENUM_SPORT_CTL_FS_HI                 (_ADI_MSK(0x00010000,uint32_t))  /* LFS: Active low frame sync (DSP standard mode) */
-
-#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_DIFS                  (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define ENUM_SPORT_CTL_DATA_DEP_FS           (_ADI_MSK(0x00000000,uint32_t))  /* DIFS: Data-dependent frame sync */
-#define ENUM_SPORT_CTL_DATA_INDP_FS          (_ADI_MSK(0x00008000,uint32_t))  /* DIFS: Data-independent frame sync */
-
-#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_IFS                   (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define ENUM_SPORT_CTL_EXTERNAL_FS           (_ADI_MSK(0x00000000,uint32_t))  /* IFS: External frame sync */
-#define ENUM_SPORT_CTL_INTERNAL_FS           (_ADI_MSK(0x00004000,uint32_t))  /* IFS: Internal frame sync */
-
-#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_FSR                   (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define ENUM_SPORT_CTL_FS_NOT_REQ            (_ADI_MSK(0x00000000,uint32_t))  /* FSR: No frame sync required */
-#define ENUM_SPORT_CTL_FS_REQ                (_ADI_MSK(0x00002000,uint32_t))  /* FSR: Frame sync required */
-
-#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_CKRE                  (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define ENUM_SPORT_CTL_CLK_FALL_EDGE         (_ADI_MSK(0x00000000,uint32_t))  /* CKRE: Clock falling edge */
-#define ENUM_SPORT_CTL_CLK_RISE_EDGE         (_ADI_MSK(0x00001000,uint32_t))  /* CKRE: Clock rising edge */
-
-#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_OPMODE                (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define ENUM_SPORT_CTL_SERIAL_MC_MODE        (_ADI_MSK(0x00000000,uint32_t))  /* OPMODE: DSP standard/multi-channel mode */
-#define ENUM_SPORT_CTL_I2S_MODE              (_ADI_MSK(0x00000800,uint32_t))  /* OPMODE: I2S/packed/left-justified mode */
-
-#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_ICLK                  (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define ENUM_SPORT_CTL_EXTERNAL_CLK          (_ADI_MSK(0x00000000,uint32_t))  /* ICLK: External clock */
-#define ENUM_SPORT_CTL_INTERNAL_CLK          (_ADI_MSK(0x00000400,uint32_t))  /* ICLK: Internal clock */
-
-#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_PACK                  (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define ENUM_SPORT_CTL_PACK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* PACK: Disable */
-#define ENUM_SPORT_CTL_PACK_EN               (_ADI_MSK(0x00000200,uint32_t))  /* PACK: Enable */
-#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_SLEN                  (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-
-#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_LSBF                  (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define ENUM_SPORT_CTL_MSB_FIRST             (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB first sent/received (big endian) */
-#define ENUM_SPORT_CTL_LSB_FIRST             (_ADI_MSK(0x00000008,uint32_t))  /* LSBF: LSB first sent/received (little endian) */
-
-#define BITM_SPORT_CTL_A_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_DTYPE                 (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define ENUM_SPORT_CTL_RJUSTIFY_ZFILL        (_ADI_MSK(0x00000000,uint32_t))  /* DTYPE: Right-justify data, zero-fill unused MSBs */
-#define ENUM_SPORT_CTL_RJUSTIFY_SFILL        (_ADI_MSK(0x00000002,uint32_t))  /* DTYPE: Right-justify data, sign-extend unused MSBs */
-#define ENUM_SPORT_CTL_USE_U_LAW             (_ADI_MSK(0x00000004,uint32_t))  /* DTYPE: m-law compand data */
-#define ENUM_SPORT_CTL_USE_A_LAW             (_ADI_MSK(0x00000006,uint32_t))  /* DTYPE: A-law compand data */
-
-#define BITM_SPORT_CTL_A_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define BITM_SPORT_CTL_SPENPRI               (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define ENUM_SPORT_CTL_DIS                   (_ADI_MSK(0x00000000,uint32_t))  /* SPENPRI: Disable */
-#define ENUM_SPORT_CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* SPENPRI: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_A_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_FSDIV                 16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_A_CLKDIV               0                               /* Clock Divisor */
-#define BITP_SPORT_DIV_CLKDIV                 0                               /* Clock Divisor */
-#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_FSDIV                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-#define BITM_SPORT_DIV_CLKDIV                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_A_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_WOFFSET              16                               /* Window Offset */
-#define BITP_SPORT_MCTL_A_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_WSIZE                 8                               /* Window Size */
-#define BITP_SPORT_MCTL_A_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_MFD                   4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_A_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_MCPDE                 2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_A_MCE                 0                               /* Multichannel enable */
-#define BITP_SPORT_MCTL_MCE                   0                               /* Multichannel enable */
-#define BITM_SPORT_MCTL_A_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_WOFFSET              (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_A_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_WSIZE                (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_A_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_MFD                  (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-
-#define BITM_SPORT_MCTL_A_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_MCPDE                (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define ENUM_SPORT_MCTL_MCPD_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* MCPDE: Disable */
-#define ENUM_SPORT_MCTL_MCPD_EN              (_ADI_MSK(0x00000004,uint32_t))  /* MCPDE: Enable */
-
-#define BITM_SPORT_MCTL_A_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define BITM_SPORT_MCTL_MCE                  (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define ENUM_SPORT_MCTL_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* MCE: Disable */
-#define ENUM_SPORT_MCTL_EN                   (_ADI_MSK(0x00000001,uint32_t))  /* MCE: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_A_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_FSERRSTAT              6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_A_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_DERRSSTAT              5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_A_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_DERRPSTAT              4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_A_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_FSERRMSK               2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRSMSK               1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRPMSK               0                               /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_FSERRSTAT             (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_A_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_DERRSSTAT             (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_A_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_DERRPSTAT             (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_A_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_FSERRMSK              (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRSMSK              (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRPMSK              (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_A_CURCHAN            0                               /* Current Channel */
-#define BITP_SPORT_MSTAT_CURCHAN              0                               /* Current Channel */
-#define BITM_SPORT_MSTAT_A_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-#define BITM_SPORT_MSTAT_CURCHAN             (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_A_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_CKMUXSEL              1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_A_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-#define BITP_SPORT_CTL2_FSMUXSEL              0                               /* Frame Sync Multiplexer Select */
-
-#define BITM_SPORT_CTL2_A_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_CKMUXSEL             (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define ENUM_SPORT_CTL2_CLK_MUX_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* CKMUXSEL: Disable serial clock multiplexing */
-#define ENUM_SPORT_CTL2_CLK_MUX_EN           (_ADI_MSK(0x00000002,uint32_t))  /* CKMUXSEL: Enable serial clock multiplexing */
-
-#define BITM_SPORT_CTL2_A_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define BITM_SPORT_CTL2_FSMUXSEL             (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define ENUM_SPORT_CTL2_FS_MUX_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* FSMUXSEL: Disable frame sync multiplexing */
-#define ENUM_SPORT_CTL2_FS_MUX_EN            (_ADI_MSK(0x00000001,uint32_t))  /* FSMUXSEL: Enable frame sync multiplexing */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_B_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_B_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_B_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_B_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_B_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_B_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_B_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_B_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_B_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_B_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_B_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_B_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_B_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_B_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_B_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_B_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_B_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_B_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_B_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_B_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_B_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_B_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_B_SPENPRI              0                               /* Serial Port Enable (Primary) */
-
-/* The fields and enumerations for SPORT_CTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL_A */
-
-#define BITM_SPORT_CTL_B_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_B_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_B_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_B_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_B_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_B_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_B_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_B_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_B_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_B_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_B_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_B_CLKDIV               0                               /* Clock Divisor */
-
-/* The fields and enumerations for SPORT_DIV_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_DIV_A */
-
-#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_B_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_B_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_B_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_B_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_B_MCE                 0                               /* Multi-Channel Enable */
-
-/* The fields and enumerations for SPORT_MCTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MCTL_A */
-
-#define BITM_SPORT_MCTL_B_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_B_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_B_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_B_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_B_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multi-Channel Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_B_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_B_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_B_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_B_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-
-/* The fields and enumerations for SPORT_ERR_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_ERR_A */
-
-#define BITM_SPORT_ERR_B_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_B_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_B_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_B_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_B_CURCHAN            0                               /* Current Channel */
-
-/* The fields and enumerations for SPORT_MSTAT_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MSTAT_A */
-
-#define BITM_SPORT_MSTAT_B_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_B_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_B_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-
-/* The fields and enumerations for SPORT_CTL2_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL2_A */
-
-#define BITM_SPORT_CTL2_B_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_B_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-
-/* ==================================================
-        Serial Peripheral Interface Registers
-   ================================================== */
-
-/* =========================
-        SPI0
-   ========================= */
-#define REG_SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
-#define REG_SPI0_RXCTL                  0xFFC40408         /* SPI0 Receive Control Register */
-#define REG_SPI0_TXCTL                  0xFFC4040C         /* SPI0 Transmit Control Register */
-#define REG_SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
-#define REG_SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
-#define REG_SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
-#define REG_SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word Count Register */
-#define REG_SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word Count Reload Register */
-#define REG_SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word Count Register */
-#define REG_SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word Count Reload Register */
-#define REG_SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
-#define REG_SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
-#define REG_SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
-#define REG_SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
-#define REG_SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
-#define REG_SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
-#define REG_SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
-#define REG_SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
-        SPI1
-   ========================= */
-#define REG_SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
-#define REG_SPI1_RXCTL                  0xFFC40508         /* SPI1 Receive Control Register */
-#define REG_SPI1_TXCTL                  0xFFC4050C         /* SPI1 Transmit Control Register */
-#define REG_SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
-#define REG_SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
-#define REG_SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
-#define REG_SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word Count Register */
-#define REG_SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word Count Reload Register */
-#define REG_SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word Count Register */
-#define REG_SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word Count Reload Register */
-#define REG_SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
-#define REG_SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
-#define REG_SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
-#define REG_SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
-#define REG_SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
-#define REG_SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
-#define REG_SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
-#define REG_SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
-        SPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CTL_SOSI                    22                               /* Start on MOSI */
-#define BITP_SPI_CTL_MIOM                    20                               /* Multiple I/O Mode */
-#define BITP_SPI_CTL_FMODE                   18                               /* Fast-Mode Enable */
-#define BITP_SPI_CTL_FCWM                    16                               /* Flow Control Watermark */
-#define BITP_SPI_CTL_FCPL                    15                               /* Flow Control Polarity */
-#define BITP_SPI_CTL_FCCH                    14                               /* Flow Control Channel Selection */
-#define BITP_SPI_CTL_FCEN                    13                               /* Flow Control Enable */
-#define BITP_SPI_CTL_LSBF                    12                               /* Least Significant Bit First */
-#define BITP_SPI_CTL_SIZE                     9                               /* Word Transfer Size */
-#define BITP_SPI_CTL_EMISO                    8                               /* Enable MISO */
-#define BITP_SPI_CTL_SELST                    7                               /* Slave Select Polarity Between Transfers */
-#define BITP_SPI_CTL_ASSEL                    6                               /* Slave Select Pin Control */
-#define BITP_SPI_CTL_CPOL                     5                               /* Clock Polarity */
-#define BITP_SPI_CTL_CPHA                     4                               /* Clock Phase */
-#define BITP_SPI_CTL_ODM                      3                               /* Open Drain Mode */
-#define BITP_SPI_CTL_PSSE                     2                               /* Protected Slave Select Enable */
-#define BITP_SPI_CTL_MSTR                     1                               /* Master / Slave */
-#define BITP_SPI_CTL_EN                       0                               /* Enable */
-
-#define BITM_SPI_CTL_SOSI                    (_ADI_MSK(0x00400000,uint32_t))  /* Start on MOSI */
-#define ENUM_SPI_CTL_STMISO                  (_ADI_MSK(0x00000000,uint32_t))  /* SOSI: Bit 1 on MISO (DIOM) or on D3 (QIOM) */
-#define ENUM_SPI_CTL_STMOSI                  (_ADI_MSK(0x00400000,uint32_t))  /* SOSI: Bit 1 on MOSI (DIOM and QIOM) */
-
-#define BITM_SPI_CTL_MIOM                    (_ADI_MSK(0x00300000,uint32_t))  /* Multiple I/O Mode */
-#define ENUM_SPI_CTL_MIO_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* MIOM: No MIOM (disabled) */
-#define ENUM_SPI_CTL_MIO_DUAL                (_ADI_MSK(0x00100000,uint32_t))  /* MIOM: DIOM operation */
-#define ENUM_SPI_CTL_MIO_QUAD                (_ADI_MSK(0x00200000,uint32_t))  /* MIOM: QIOM operation */
-
-#define BITM_SPI_CTL_FMODE                   (_ADI_MSK(0x00040000,uint32_t))  /* Fast-Mode Enable */
-#define ENUM_SPI_CTL_FAST_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FMODE: Disable */
-#define ENUM_SPI_CTL_FAST_EN                 (_ADI_MSK(0x00040000,uint32_t))  /* FMODE: Enable */
-
-#define BITM_SPI_CTL_FCWM                    (_ADI_MSK(0x00030000,uint32_t))  /* Flow Control Watermark */
-#define ENUM_SPI_CTL_FIFO0                   (_ADI_MSK(0x00000000,uint32_t))  /* FCWM: TFIFO empty or RFIFO full */
-#define ENUM_SPI_CTL_FIFO1                   (_ADI_MSK(0x00010000,uint32_t))  /* FCWM: TFIFO 75% or more empty, or RFIFO full */
-#define ENUM_SPI_CTL_FIFO2                   (_ADI_MSK(0x00020000,uint32_t))  /* FCWM: TFIFO 50% or more empty, or RFIFO full */
-
-#define BITM_SPI_CTL_FCPL                    (_ADI_MSK(0x00008000,uint32_t))  /* Flow Control Polarity */
-#define ENUM_SPI_CTL_FLOW_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* FCPL: Active-low RDY */
-#define ENUM_SPI_CTL_FLOW_HI                 (_ADI_MSK(0x00008000,uint32_t))  /* FCPL: Active-high RDY */
-
-#define BITM_SPI_CTL_FCCH                    (_ADI_MSK(0x00004000,uint32_t))  /* Flow Control Channel Selection */
-#define ENUM_SPI_CTL_FLOW_RX                 (_ADI_MSK(0x00000000,uint32_t))  /* FCCH: Flow control on RX buffer */
-#define ENUM_SPI_CTL_FLOW_TX                 (_ADI_MSK(0x00004000,uint32_t))  /* FCCH: Flow control on TX buffer */
-
-#define BITM_SPI_CTL_FCEN                    (_ADI_MSK(0x00002000,uint32_t))  /* Flow Control Enable */
-#define ENUM_SPI_CTL_FLOW_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FCEN: Disable */
-#define ENUM_SPI_CTL_FLOW_EN                 (_ADI_MSK(0x00002000,uint32_t))  /* FCEN: Enable */
-
-#define BITM_SPI_CTL_LSBF                    (_ADI_MSK(0x00001000,uint32_t))  /* Least Significant Bit First */
-#define ENUM_SPI_CTL_MSB_FIRST               (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB sent/received first (big endian) */
-#define ENUM_SPI_CTL_LSB_FIRST               (_ADI_MSK(0x00001000,uint32_t))  /* LSBF: LSB sent/received first (little endian) */
-
-#define BITM_SPI_CTL_SIZE                    (_ADI_MSK(0x00000600,uint32_t))  /* Word Transfer Size */
-#define ENUM_SPI_CTL_SIZE08                  (_ADI_MSK(0x00000000,uint32_t))  /* SIZE: 8-bit word */
-#define ENUM_SPI_CTL_SIZE16                  (_ADI_MSK(0x00000200,uint32_t))  /* SIZE: 16-bit word */
-#define ENUM_SPI_CTL_SIZE32                  (_ADI_MSK(0x00000400,uint32_t))  /* SIZE: 32-bit word */
-
-#define BITM_SPI_CTL_EMISO                   (_ADI_MSK(0x00000100,uint32_t))  /* Enable MISO */
-#define ENUM_SPI_CTL_MISO_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EMISO: Disable */
-#define ENUM_SPI_CTL_MISO_EN                 (_ADI_MSK(0x00000100,uint32_t))  /* EMISO: Enable */
-
-#define BITM_SPI_CTL_SELST                   (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select Polarity Between Transfers */
-#define ENUM_SPI_CTL_DEASSRT_SSEL            (_ADI_MSK(0x00000000,uint32_t))  /* SELST: De-assert slave select (high) */
-#define ENUM_SPI_CTL_ASSRT_SSEL              (_ADI_MSK(0x00000080,uint32_t))  /* SELST: Assert slave select (low) */
-
-#define BITM_SPI_CTL_ASSEL                   (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select Pin Control */
-#define ENUM_SPI_CTL_SW_SSEL                 (_ADI_MSK(0x00000000,uint32_t))  /* ASSEL: Software Slave Select Control */
-#define ENUM_SPI_CTL_HW_SSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* ASSEL: Hardware Slave Select Control */
-
-#define BITM_SPI_CTL_CPOL                    (_ADI_MSK(0x00000020,uint32_t))  /* Clock Polarity */
-#define ENUM_SPI_CTL_SCKHI                   (_ADI_MSK(0x00000000,uint32_t))  /* CPOL: Active-high SPI CLK */
-#define ENUM_SPI_CTL_SCKLO                   (_ADI_MSK(0x00000020,uint32_t))  /* CPOL: Active-low SPI CLK */
-
-#define BITM_SPI_CTL_CPHA                    (_ADI_MSK(0x00000010,uint32_t))  /* Clock Phase */
-#define ENUM_SPI_CTL_SCKMID                  (_ADI_MSK(0x00000000,uint32_t))  /* CPHA: SPI CLK toggles from middle */
-#define ENUM_SPI_CTL_SCKBEG                  (_ADI_MSK(0x00000010,uint32_t))  /* CPHA: SPI CLK toggles from start */
-
-#define BITM_SPI_CTL_ODM                     (_ADI_MSK(0x00000008,uint32_t))  /* Open Drain Mode */
-#define ENUM_SPI_CTL_ODM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* ODM: Disable */
-#define ENUM_SPI_CTL_ODM_EN                  (_ADI_MSK(0x00000008,uint32_t))  /* ODM: Enable */
-
-#define BITM_SPI_CTL_PSSE                    (_ADI_MSK(0x00000004,uint32_t))  /* Protected Slave Select Enable */
-#define ENUM_SPI_CTL_PSSE_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* PSSE: Disable */
-#define ENUM_SPI_CTL_PSSE_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* PSSE: Enable */
-
-#define BITM_SPI_CTL_MSTR                    (_ADI_MSK(0x00000002,uint32_t))  /* Master / Slave */
-#define ENUM_SPI_CTL_SLAVE                   (_ADI_MSK(0x00000000,uint32_t))  /* MSTR: Slave */
-#define ENUM_SPI_CTL_MASTER                  (_ADI_MSK(0x00000002,uint32_t))  /* MSTR: Master */
-
-#define BITM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SPI_CTL_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable SPI module */
-#define ENUM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RXCTL_RUWM                  16                               /* Receive FIFO Urgent Watermark */
-#define BITP_SPI_RXCTL_RRWM                  12                               /* Receive FIFO Regular Watermark */
-#define BITP_SPI_RXCTL_RDO                    8                               /* Receive Data Overrun */
-#define BITP_SPI_RXCTL_RDR                    4                               /* Receive Data Request */
-#define BITP_SPI_RXCTL_RWCEN                  3                               /* Receive Word Counter Enable */
-#define BITP_SPI_RXCTL_RTI                    2                               /* Receive Transfer Initiate */
-#define BITP_SPI_RXCTL_REN                    0                               /* Receive Enable */
-
-#define BITM_SPI_RXCTL_RUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* Receive FIFO Urgent Watermark */
-#define ENUM_SPI_RXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disabled */
-#define ENUM_SPI_RXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* RUWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* RUWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* RUWM: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_FULL              (_ADI_MSK(0x00040000,uint32_t))  /* RUWM: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* Receive FIFO Regular Watermark */
-#define ENUM_SPI_RXCTL_RWM_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RRWM: Empty RFIFO */
-#define ENUM_SPI_RXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* RRWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* RRWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* RRWM: 75% full RFIFO */
-
-#define BITM_SPI_RXCTL_RDO                   (_ADI_MSK(0x00000100,uint32_t))  /* Receive Data Overrun */
-#define ENUM_SPI_RXCTL_DISCARD               (_ADI_MSK(0x00000000,uint32_t))  /* RDO: KeDiscard incoming data if SPI_RFIFO is full */
-#define ENUM_SPI_RXCTL_OVERWRITE             (_ADI_MSK(0x00000100,uint32_t))  /* RDO: Overwrite old data if SPI_RFIFO is full */
-
-#define BITM_SPI_RXCTL_RDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Receive Data Request */
-#define ENUM_SPI_RXCTL_RDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RDR: Disabled */
-#define ENUM_SPI_RXCTL_RDR_NE                (_ADI_MSK(0x00000010,uint32_t))  /* RDR: Not empty RFIFO */
-#define ENUM_SPI_RXCTL_RDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* RDR: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* RDR: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* RDR: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_FULL              (_ADI_MSK(0x00000050,uint32_t))  /* RDR: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Receive Word Counter Enable */
-#define ENUM_SPI_RXCTL_RWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RWCEN: Disable */
-#define ENUM_SPI_RXCTL_RWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* RWCEN: Enable */
-
-#define BITM_SPI_RXCTL_RTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Receive Transfer Initiate */
-#define ENUM_SPI_RXCTL_RTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RTI: Disable */
-#define ENUM_SPI_RXCTL_RTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* RTI: Enable */
-
-#define BITM_SPI_RXCTL_REN                   (_ADI_MSK(0x00000001,uint32_t))  /* Receive Enable */
-#define ENUM_SPI_RXCTL_RX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* REN: Disable */
-#define ENUM_SPI_RXCTL_RX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* REN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TXCTL_TUWM                  16                               /* FIFO Urgent Watermark */
-#define BITP_SPI_TXCTL_TRWM                  12                               /* FIFO Regular Watermark */
-#define BITP_SPI_TXCTL_TDU                    8                               /* Transmit Data Under-run */
-#define BITP_SPI_TXCTL_TDR                    4                               /* Transmit Data Request */
-#define BITP_SPI_TXCTL_TWCEN                  3                               /* Transmit Word Counter Enable */
-#define BITP_SPI_TXCTL_TTI                    2                               /* Transmit Transfer Initiate */
-#define BITP_SPI_TXCTL_TEN                    0                               /* Transmit Enable */
-
-#define BITM_SPI_TXCTL_TUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Urgent Watermark */
-#define ENUM_SPI_TXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disabled */
-#define ENUM_SPI_TXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* TUWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* TUWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* TUWM: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_EMPTY             (_ADI_MSK(0x00040000,uint32_t))  /* TUWM: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* FIFO Regular Watermark */
-#define ENUM_SPI_TXCTL_RWM_FULL              (_ADI_MSK(0x00000000,uint32_t))  /* TRWM: Full TFIFO */
-#define ENUM_SPI_TXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* TRWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* TRWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* TRWM: 75% empty TFIFO */
-
-#define BITM_SPI_TXCTL_TDU                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Data Under-run */
-#define ENUM_SPI_TXCTL_LASTWD                (_ADI_MSK(0x00000000,uint32_t))  /* TDU: Send last word when SPI_TFIFO is empty */
-#define ENUM_SPI_TXCTL_ZERO                  (_ADI_MSK(0x00000100,uint32_t))  /* TDU: Send zeros when SPI_TFIFO is empty */
-
-#define BITM_SPI_TXCTL_TDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Transmit Data Request */
-#define ENUM_SPI_TXCTL_TDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TDR: Disabled */
-#define ENUM_SPI_TXCTL_TDR_NF                (_ADI_MSK(0x00000010,uint32_t))  /* TDR: Not full TFIFO */
-#define ENUM_SPI_TXCTL_TDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* TDR: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* TDR: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* TDR: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_EMPTY             (_ADI_MSK(0x00000050,uint32_t))  /* TDR: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Word Counter Enable */
-#define ENUM_SPI_TXCTL_TWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TWCEN: Disable */
-#define ENUM_SPI_TXCTL_TWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* TWCEN: Enable */
-
-#define BITM_SPI_TXCTL_TTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Transfer Initiate */
-#define ENUM_SPI_TXCTL_TTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TTI: Disable */
-#define ENUM_SPI_TXCTL_TTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* TTI: Enable */
-
-#define BITM_SPI_TXCTL_TEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Enable */
-#define ENUM_SPI_TXCTL_TX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* TEN: Disable */
-#define ENUM_SPI_TXCTL_TX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* TEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CLK_BAUD                     0                               /* Baud Rate */
-#define BITM_SPI_CLK_BAUD                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Baud Rate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_DLY                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_DLY_LAGX                     9                               /* Extended SPI Clock Lag Control */
-#define BITP_SPI_DLY_LEADX                    8                               /* Extended SPI Clock Lead Control */
-#define BITP_SPI_DLY_STOP                     0                               /* Transfer delay time in multiples of SPI clock period */
-#define BITM_SPI_DLY_LAGX                    (_ADI_MSK(0x00000200,uint32_t))  /* Extended SPI Clock Lag Control */
-#define BITM_SPI_DLY_LEADX                   (_ADI_MSK(0x00000100,uint32_t))  /* Extended SPI Clock Lead Control */
-#define BITM_SPI_DLY_STOP                    (_ADI_MSK(0x000000FF,uint32_t))  /* Transfer delay time in multiples of SPI clock period */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_SLVSEL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_SLVSEL_SSEL7                15                               /* Slave Select 7 Input */
-#define BITP_SPI_SLVSEL_SSEL6                14                               /* Slave Select 6 Input */
-#define BITP_SPI_SLVSEL_SSEL5                13                               /* Slave Select 5 Input */
-#define BITP_SPI_SLVSEL_SSEL4                12                               /* Slave Select 4 Input */
-#define BITP_SPI_SLVSEL_SSEL3                11                               /* Slave Select 3 Input */
-#define BITP_SPI_SLVSEL_SSEL2                10                               /* Slave Select 2 Input */
-#define BITP_SPI_SLVSEL_SSEL1                 9                               /* Slave Select 1 Input */
-#define BITP_SPI_SLVSEL_SSE7                  7                               /* Slave Select 7 Enable */
-#define BITP_SPI_SLVSEL_SSE6                  6                               /* Slave Select 6 Enable */
-#define BITP_SPI_SLVSEL_SSE5                  5                               /* Slave Select 5 Enable */
-#define BITP_SPI_SLVSEL_SSE4                  4                               /* Slave Select 4 Enable */
-#define BITP_SPI_SLVSEL_SSE3                  3                               /* Slave Select 3 Enable */
-#define BITP_SPI_SLVSEL_SSE2                  2                               /* Slave Select 2 Enable */
-#define BITP_SPI_SLVSEL_SSE1                  1                               /* Slave Select 1 Enable */
-
-#define BITM_SPI_SLVSEL_SSEL7                (_ADI_MSK(0x00008000,uint32_t))  /* Slave Select 7 Input */
-#define ENUM_SPI_SLVSEL_SSEL7_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL7: Low */
-#define ENUM_SPI_SLVSEL_SSEL7_HI             (_ADI_MSK(0x00008000,uint32_t))  /* SSEL7: High */
-
-#define BITM_SPI_SLVSEL_SSEL6                (_ADI_MSK(0x00004000,uint32_t))  /* Slave Select 6 Input */
-#define ENUM_SPI_SLVSEL_SSEL6_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL6: Low */
-#define ENUM_SPI_SLVSEL_SSEL6_HI             (_ADI_MSK(0x00004000,uint32_t))  /* SSEL6: High */
-
-#define BITM_SPI_SLVSEL_SSEL5                (_ADI_MSK(0x00002000,uint32_t))  /* Slave Select 5 Input */
-#define ENUM_SPI_SLVSEL_SSEL5_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL5: Low */
-#define ENUM_SPI_SLVSEL_SSEL5_HI             (_ADI_MSK(0x00002000,uint32_t))  /* SSEL5: High */
-
-#define BITM_SPI_SLVSEL_SSEL4                (_ADI_MSK(0x00001000,uint32_t))  /* Slave Select 4 Input */
-#define ENUM_SPI_SLVSEL_SSEL4_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL4: Low */
-#define ENUM_SPI_SLVSEL_SSEL4_HI             (_ADI_MSK(0x00001000,uint32_t))  /* SSEL4: High */
-
-#define BITM_SPI_SLVSEL_SSEL3                (_ADI_MSK(0x00000800,uint32_t))  /* Slave Select 3 Input */
-#define ENUM_SPI_SLVSEL_SSEL3_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL3: Low */
-#define ENUM_SPI_SLVSEL_SSEL3_HI             (_ADI_MSK(0x00000800,uint32_t))  /* SSEL3: High */
-
-#define BITM_SPI_SLVSEL_SSEL2                (_ADI_MSK(0x00000400,uint32_t))  /* Slave Select 2 Input */
-#define ENUM_SPI_SLVSEL_SSEL2_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL2: Low */
-#define ENUM_SPI_SLVSEL_SSEL2_HI             (_ADI_MSK(0x00000400,uint32_t))  /* SSEL2: High */
-
-#define BITM_SPI_SLVSEL_SSEL1                (_ADI_MSK(0x00000200,uint32_t))  /* Slave Select 1 Input */
-#define ENUM_SPI_SLVSEL_SSEL1_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL1: Low */
-#define ENUM_SPI_SLVSEL_SSEL1_HI             (_ADI_MSK(0x00000200,uint32_t))  /* SSEL1: High */
-
-#define BITM_SPI_SLVSEL_SSE7                 (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select 7 Enable */
-#define ENUM_SPI_SLVSEL_SSEL7_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE7: Disable */
-#define ENUM_SPI_SLVSEL_SSEL7_EN             (_ADI_MSK(0x00000080,uint32_t))  /* SSE7: Enable */
-
-#define BITM_SPI_SLVSEL_SSE6                 (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select 6 Enable */
-#define ENUM_SPI_SLVSEL_SSEL6_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE6: Disable */
-#define ENUM_SPI_SLVSEL_SSEL6_EN             (_ADI_MSK(0x00000040,uint32_t))  /* SSE6: Enable */
-
-#define BITM_SPI_SLVSEL_SSE5                 (_ADI_MSK(0x00000020,uint32_t))  /* Slave Select 5 Enable */
-#define ENUM_SPI_SLVSEL_SSEL5_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE5: Disable */
-#define ENUM_SPI_SLVSEL_SSEL5_EN             (_ADI_MSK(0x00000020,uint32_t))  /* SSE5: Enable */
-
-#define BITM_SPI_SLVSEL_SSE4                 (_ADI_MSK(0x00000010,uint32_t))  /* Slave Select 4 Enable */
-#define ENUM_SPI_SLVSEL_SSEL4_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE4: Disable */
-#define ENUM_SPI_SLVSEL_SSEL4_EN             (_ADI_MSK(0x00000010,uint32_t))  /* SSE4: Enable */
-
-#define BITM_SPI_SLVSEL_SSE3                 (_ADI_MSK(0x00000008,uint32_t))  /* Slave Select 3 Enable */
-#define ENUM_SPI_SLVSEL_SSEL3_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE3: Disable */
-#define ENUM_SPI_SLVSEL_SSEL3_EN             (_ADI_MSK(0x00000008,uint32_t))  /* SSE3: Enable */
-
-#define BITM_SPI_SLVSEL_SSE2                 (_ADI_MSK(0x00000004,uint32_t))  /* Slave Select 2 Enable */
-#define ENUM_SPI_SLVSEL_SSEL2_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE2: Disable */
-#define ENUM_SPI_SLVSEL_SSEL2_EN             (_ADI_MSK(0x00000004,uint32_t))  /* SSE2: Enable */
-
-#define BITM_SPI_SLVSEL_SSE1                 (_ADI_MSK(0x00000002,uint32_t))  /* Slave Select 1 Enable */
-#define ENUM_SPI_SLVSEL_SSEL1_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE1: Disable */
-#define ENUM_SPI_SLVSEL_SSEL1_EN             (_ADI_MSK(0x00000002,uint32_t))  /* SSE1: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWC_VALUE                    0                               /* Received Word Count */
-#define BITM_SPI_RWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWCR_VALUE                   0                               /* Received Word Count Reload */
-#define BITM_SPI_RWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWC_VALUE                    0                               /* Transmitted Word Count */
-#define BITM_SPI_TWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWCR_VALUE                   0                               /* Transmitted Word Count Reload */
-#define BITM_SPI_TWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_TF                     11                               /* Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_RF                     10                               /* Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_TS                      9                               /* Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_RS                      8                               /* Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_MF                      7                               /* Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_TC                      6                               /* Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_TUR                     5                               /* Transmit Underrun Interrupt Mask */
-#define BITP_SPI_IMSK_ROR                     4                               /* Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_RUWM                    1                               /* Receive Urgent Watermark Interrupt Mask */
-
-#define BITM_SPI_IMSK_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Mask */
-#define ENUM_SPI_TF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TF: Disable (mask) interrupt */
-#define ENUM_SPI_TF_HI                       (_ADI_MSK(0x00000800,uint32_t))  /* TF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Mask */
-#define ENUM_SPI_RF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RF: Disable (mask) interrupt */
-#define ENUM_SPI_RF_HI                       (_ADI_MSK(0x00000400,uint32_t))  /* RF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Mask */
-#define ENUM_SPI_TS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TS: Disable (mask) interrupt */
-#define ENUM_SPI_TS_HI                       (_ADI_MSK(0x00000200,uint32_t))  /* TS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Mask */
-#define ENUM_SPI_RS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RS: Disable (mask) interrupt */
-#define ENUM_SPI_RS_HI                       (_ADI_MSK(0x00000100,uint32_t))  /* RS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Mask */
-#define ENUM_SPI_MF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* MF: Disable (mask) interrupt */
-#define ENUM_SPI_MF_HI                       (_ADI_MSK(0x00000080,uint32_t))  /* MF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Mask */
-#define ENUM_SPI_TC_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TC: Disable (mask) interrupt */
-#define ENUM_SPI_TC_HI                       (_ADI_MSK(0x00000040,uint32_t))  /* TC: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Interrupt Mask */
-#define ENUM_SPI_TUR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* TUR: Disable (mask) interrupt */
-#define ENUM_SPI_TUR_HI                      (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Mask */
-#define ENUM_SPI_ROR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* ROR: Disable (mask) interrupt */
-#define ENUM_SPI_ROR_HI                      (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_TUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disable (mask) interrupt */
-#define ENUM_SPI_TUWM_HI                     (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_RUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disable (mask) interrupt */
-#define ENUM_SPI_RUWM_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RF                 10                               /* Clear Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TS                  9                               /* Clear Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RS                  8                               /* Clear Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_MF                  7                               /* Clear Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_SET_TF                 11                               /* Set Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RF                 10                               /* Set Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TS                  9                               /* Set Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RS                  8                               /* Set Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_MF                  7                               /* Set Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TC                  6                               /* Set Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUR                 5                               /* Set Transmit Under-run  Interrupt Mask */
-#define BITP_SPI_IMSK_SET_ROR                 4                               /* Set Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUWM                2                               /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RUWM                1                               /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_SET are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_SET_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Set Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Set Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Set Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Set Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Set Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Set Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Set Transmit Under-run  Interrupt Mask */
-#define BITM_SPI_IMSK_SET_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Set Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_STAT_TFF                    23                               /* SPI_TFIFO Full */
-#define BITP_SPI_STAT_RFE                    22                               /* SPI_RFIFO Empty */
-#define BITP_SPI_STAT_FCS                    20                               /* Flow Control Stall Indication */
-#define BITP_SPI_STAT_TFS                    16                               /* SPI_TFIFO Status */
-#define BITP_SPI_STAT_RFS                    12                               /* SPI_RFIFO Status */
-#define BITP_SPI_STAT_TF                     11                               /* Transmit Finish Indication */
-#define BITP_SPI_STAT_RF                     10                               /* Receive Finish Indication */
-#define BITP_SPI_STAT_TS                      9                               /* Transmit Start */
-#define BITP_SPI_STAT_RS                      8                               /* Receive Start */
-#define BITP_SPI_STAT_MF                      7                               /* Mode Fault Indication */
-#define BITP_SPI_STAT_TC                      6                               /* Transmit Collision Indication */
-#define BITP_SPI_STAT_TUR                     5                               /* Transmit Underrun Indication */
-#define BITP_SPI_STAT_ROR                     4                               /* Receive Overrun Indication */
-#define BITP_SPI_STAT_TUWM                    2                               /* Transmit Urgent Watermark Breached */
-#define BITP_SPI_STAT_RUWM                    1                               /* Receive Urgent Watermark Breached */
-#define BITP_SPI_STAT_SPIF                    0                               /* SPI Finished */
-
-#define BITM_SPI_STAT_TFF                    (_ADI_MSK(0x00800000,uint32_t))  /* SPI_TFIFO Full */
-#define ENUM_SPI_STAT_TFIFO_NF               (_ADI_MSK(0x00000000,uint32_t))  /* TFF: Not full Tx FIFO */
-#define ENUM_SPI_STAT_TFIFO_F                (_ADI_MSK(0x00800000,uint32_t))  /* TFF: Full Tx FIFO */
-
-#define BITM_SPI_STAT_RFE                    (_ADI_MSK(0x00400000,uint32_t))  /* SPI_RFIFO Empty */
-#define ENUM_SPI_STAT_RFIFO_E                (_ADI_MSK(0x00000000,uint32_t))  /* RFE: Empty Rx FIFO */
-#define ENUM_SPI_STAT_RFIFO_NE               (_ADI_MSK(0x00400000,uint32_t))  /* RFE: Not empty Rx FIFO */
-
-#define BITM_SPI_STAT_FCS                    (_ADI_MSK(0x00100000,uint32_t))  /* Flow Control Stall Indication */
-#define ENUM_SPI_STAT_STALL                  (_ADI_MSK(0x00000000,uint32_t))  /* FCS: Stall (RDY pin asserted) */
-#define ENUM_SPI_STAT_NOSTALL                (_ADI_MSK(0x00100000,uint32_t))  /* FCS: No stall (RDY pin de-asserted) */
-
-#define BITM_SPI_STAT_TFS                    (_ADI_MSK(0x00070000,uint32_t))  /* SPI_TFIFO Status */
-#define ENUM_SPI_STAT_TFIFO_FULL             (_ADI_MSK(0x00000000,uint32_t))  /* TFS: Full TFIFO */
-#define ENUM_SPI_STAT_TFIFO_25               (_ADI_MSK(0x00010000,uint32_t))  /* TFS: 25% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_50               (_ADI_MSK(0x00020000,uint32_t))  /* TFS: 50% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_75               (_ADI_MSK(0x00030000,uint32_t))  /* TFS: 75% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_EMPTY            (_ADI_MSK(0x00040000,uint32_t))  /* TFS: Empty TFIFO */
-
-#define BITM_SPI_STAT_RFS                    (_ADI_MSK(0x00007000,uint32_t))  /* SPI_RFIFO Status */
-#define ENUM_SPI_STAT_RFIFO_EMPTY            (_ADI_MSK(0x00000000,uint32_t))  /* RFS: Empty RFIFO */
-#define ENUM_SPI_STAT_RFIFO_25               (_ADI_MSK(0x00001000,uint32_t))  /* RFS: 25% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_50               (_ADI_MSK(0x00002000,uint32_t))  /* RFS: 50% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_75               (_ADI_MSK(0x00003000,uint32_t))  /* RFS: 75% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_FULL             (_ADI_MSK(0x00004000,uint32_t))  /* RFS: Full RFIFO */
-
-#define BITM_SPI_STAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Indication */
-#define ENUM_SPI_STAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No status */
-#define ENUM_SPI_STAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Transmit finish detected */
-
-#define BITM_SPI_STAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Indication */
-#define ENUM_SPI_STAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No status */
-#define ENUM_SPI_STAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Receive finish detected */
-
-#define BITM_SPI_STAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start */
-#define ENUM_SPI_STAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No status */
-#define ENUM_SPI_STAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Transmit start detected */
-
-#define BITM_SPI_STAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start */
-#define ENUM_SPI_STAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No status */
-#define ENUM_SPI_STAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Receive start detected */
-
-#define BITM_SPI_STAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Indication */
-#define ENUM_SPI_STAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No status */
-#define ENUM_SPI_STAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Mode fault occurred */
-
-#define BITM_SPI_STAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Indication */
-#define ENUM_SPI_STAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No status */
-#define ENUM_SPI_STAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Transmit collision occurred */
-
-#define BITM_SPI_STAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Indication */
-#define ENUM_SPI_STAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No status */
-#define ENUM_SPI_STAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Transmit underrun occurred */
-
-#define BITM_SPI_STAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Indication */
-#define ENUM_SPI_STAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No status */
-#define ENUM_SPI_STAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Receive overrun occurred */
-
-#define BITM_SPI_STAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Breached */
-#define ENUM_SPI_STAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: TX Regular Watermark reached */
-#define ENUM_SPI_STAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: TX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Breached */
-#define ENUM_SPI_STAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: RX Regular Watermark reached */
-#define ENUM_SPI_STAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: RX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_SPIF                   (_ADI_MSK(0x00000001,uint32_t))  /* SPI Finished */
-#define ENUM_SPI_STAT_SPIF_LO                (_ADI_MSK(0x00000000,uint32_t))  /* SPIF: No status */
-#define ENUM_SPI_STAT_SPIF_HI                (_ADI_MSK(0x00000001,uint32_t))  /* SPIF: Completed single-word transfer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_TF                     11                               /* Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_RF                     10                               /* Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_TS                      9                               /* Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_RS                      8                               /* Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_MF                      7                               /* Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_TC                      6                               /* Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_TUR                     5                               /* Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_ROR                     4                               /* Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_RUWM                    1                               /* Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-
-#define BITM_SPI_ILAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No interrupt */
-#define ENUM_SPI_ILAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Latched interrupt */
-
-#define BITM_SPI_ILAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No interrupt */
-#define ENUM_SPI_ILAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Latch */
-#define ENUM_SPI_ILAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No interrupt */
-#define ENUM_SPI_ILAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Latched interrupt */
-
-#define BITM_SPI_ILAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Latch */
-#define ENUM_SPI_ILAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No interrupt */
-#define ENUM_SPI_ILAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Latched interrupt */
-
-#define BITM_SPI_ILAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Latch */
-#define ENUM_SPI_ILAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No interrupt */
-#define ENUM_SPI_ILAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Latch */
-#define ENUM_SPI_ILAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No interrupt */
-#define ENUM_SPI_ILAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Under-run Interrupt Latch */
-#define ENUM_SPI_ILAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No interrupt */
-#define ENUM_SPI_ILAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Latched interrupt */
-
-#define BITM_SPI_ILAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Latch */
-#define ENUM_SPI_ILAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No interrupt */
-#define ENUM_SPI_ILAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: No interrupt */
-#define ENUM_SPI_ILAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Latched interrupt */
-
-#define BITM_SPI_ILAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: No interrupt */
-#define ENUM_SPI_ILAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Latched interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RF                 10                               /* Clear Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TS                  9                               /* Clear Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RS                  8                               /* Clear Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_MF                  7                               /* Clear Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_ILAT_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* ==================================================
-        DMA Channel Registers
-   ================================================== */
-
-/* =========================
-        DMA0
-   ========================= */
-#define REG_DMA0_DSCPTR_NXT             0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
-#define REG_DMA0_ADDRSTART              0xFFC41004         /* DMA0 Start Address of Current Buffer */
-#define REG_DMA0_CFG                    0xFFC41008         /* DMA0 Configuration Register */
-#define REG_DMA0_XCNT                   0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
-#define REG_DMA0_XMOD                   0xFFC41010         /* DMA0 Inner Loop Address Increment */
-#define REG_DMA0_YCNT                   0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
-#define REG_DMA0_YMOD                   0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
-#define REG_DMA0_DSCPTR_CUR             0xFFC41024         /* DMA0 Current Descriptor Pointer */
-#define REG_DMA0_DSCPTR_PRV             0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
-#define REG_DMA0_ADDR_CUR               0xFFC4102C         /* DMA0 Current Address */
-#define REG_DMA0_STAT                   0xFFC41030         /* DMA0 Status Register */
-#define REG_DMA0_XCNT_CUR               0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA0_YCNT_CUR               0xFFC41038         /* DMA0 Current Row Count (2D only) */
-#define REG_DMA0_BWLCNT                 0xFFC41040         /* DMA0 Bandwidth Limit Count */
-#define REG_DMA0_BWLCNT_CUR             0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
-#define REG_DMA0_BWMCNT                 0xFFC41048         /* DMA0 Bandwidth Monitor Count */
-#define REG_DMA0_BWMCNT_CUR             0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA1
-   ========================= */
-#define REG_DMA1_DSCPTR_NXT             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
-#define REG_DMA1_ADDRSTART              0xFFC41084         /* DMA1 Start Address of Current Buffer */
-#define REG_DMA1_CFG                    0xFFC41088         /* DMA1 Configuration Register */
-#define REG_DMA1_XCNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
-#define REG_DMA1_XMOD                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
-#define REG_DMA1_YCNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
-#define REG_DMA1_YMOD                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
-#define REG_DMA1_DSCPTR_CUR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
-#define REG_DMA1_DSCPTR_PRV             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
-#define REG_DMA1_ADDR_CUR               0xFFC410AC         /* DMA1 Current Address */
-#define REG_DMA1_STAT                   0xFFC410B0         /* DMA1 Status Register */
-#define REG_DMA1_XCNT_CUR               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA1_YCNT_CUR               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
-#define REG_DMA1_BWLCNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
-#define REG_DMA1_BWLCNT_CUR             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
-#define REG_DMA1_BWMCNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
-#define REG_DMA1_BWMCNT_CUR             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA2
-   ========================= */
-#define REG_DMA2_DSCPTR_NXT             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
-#define REG_DMA2_ADDRSTART              0xFFC41104         /* DMA2 Start Address of Current Buffer */
-#define REG_DMA2_CFG                    0xFFC41108         /* DMA2 Configuration Register */
-#define REG_DMA2_XCNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
-#define REG_DMA2_XMOD                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
-#define REG_DMA2_YCNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
-#define REG_DMA2_YMOD                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
-#define REG_DMA2_DSCPTR_CUR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
-#define REG_DMA2_DSCPTR_PRV             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
-#define REG_DMA2_ADDR_CUR               0xFFC4112C         /* DMA2 Current Address */
-#define REG_DMA2_STAT                   0xFFC41130         /* DMA2 Status Register */
-#define REG_DMA2_XCNT_CUR               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA2_YCNT_CUR               0xFFC41138         /* DMA2 Current Row Count (2D only) */
-#define REG_DMA2_BWLCNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
-#define REG_DMA2_BWLCNT_CUR             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
-#define REG_DMA2_BWMCNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
-#define REG_DMA2_BWMCNT_CUR             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA3
-   ========================= */
-#define REG_DMA3_DSCPTR_NXT             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
-#define REG_DMA3_ADDRSTART              0xFFC41184         /* DMA3 Start Address of Current Buffer */
-#define REG_DMA3_CFG                    0xFFC41188         /* DMA3 Configuration Register */
-#define REG_DMA3_XCNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
-#define REG_DMA3_XMOD                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
-#define REG_DMA3_YCNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
-#define REG_DMA3_YMOD                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
-#define REG_DMA3_DSCPTR_CUR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
-#define REG_DMA3_DSCPTR_PRV             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
-#define REG_DMA3_ADDR_CUR               0xFFC411AC         /* DMA3 Current Address */
-#define REG_DMA3_STAT                   0xFFC411B0         /* DMA3 Status Register */
-#define REG_DMA3_XCNT_CUR               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA3_YCNT_CUR               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
-#define REG_DMA3_BWLCNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
-#define REG_DMA3_BWLCNT_CUR             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
-#define REG_DMA3_BWMCNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
-#define REG_DMA3_BWMCNT_CUR             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA4
-   ========================= */
-#define REG_DMA4_DSCPTR_NXT             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
-#define REG_DMA4_ADDRSTART              0xFFC41204         /* DMA4 Start Address of Current Buffer */
-#define REG_DMA4_CFG                    0xFFC41208         /* DMA4 Configuration Register */
-#define REG_DMA4_XCNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
-#define REG_DMA4_XMOD                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
-#define REG_DMA4_YCNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
-#define REG_DMA4_YMOD                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
-#define REG_DMA4_DSCPTR_CUR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
-#define REG_DMA4_DSCPTR_PRV             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
-#define REG_DMA4_ADDR_CUR               0xFFC4122C         /* DMA4 Current Address */
-#define REG_DMA4_STAT                   0xFFC41230         /* DMA4 Status Register */
-#define REG_DMA4_XCNT_CUR               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA4_YCNT_CUR               0xFFC41238         /* DMA4 Current Row Count (2D only) */
-#define REG_DMA4_BWLCNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
-#define REG_DMA4_BWLCNT_CUR             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
-#define REG_DMA4_BWMCNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
-#define REG_DMA4_BWMCNT_CUR             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA5
-   ========================= */
-#define REG_DMA5_DSCPTR_NXT             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
-#define REG_DMA5_ADDRSTART              0xFFC41284         /* DMA5 Start Address of Current Buffer */
-#define REG_DMA5_CFG                    0xFFC41288         /* DMA5 Configuration Register */
-#define REG_DMA5_XCNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
-#define REG_DMA5_XMOD                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
-#define REG_DMA5_YCNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
-#define REG_DMA5_YMOD                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
-#define REG_DMA5_DSCPTR_CUR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
-#define REG_DMA5_DSCPTR_PRV             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
-#define REG_DMA5_ADDR_CUR               0xFFC412AC         /* DMA5 Current Address */
-#define REG_DMA5_STAT                   0xFFC412B0         /* DMA5 Status Register */
-#define REG_DMA5_XCNT_CUR               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA5_YCNT_CUR               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
-#define REG_DMA5_BWLCNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
-#define REG_DMA5_BWLCNT_CUR             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
-#define REG_DMA5_BWMCNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
-#define REG_DMA5_BWMCNT_CUR             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA6
-   ========================= */
-#define REG_DMA6_DSCPTR_NXT             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
-#define REG_DMA6_ADDRSTART              0xFFC41304         /* DMA6 Start Address of Current Buffer */
-#define REG_DMA6_CFG                    0xFFC41308         /* DMA6 Configuration Register */
-#define REG_DMA6_XCNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
-#define REG_DMA6_XMOD                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
-#define REG_DMA6_YCNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
-#define REG_DMA6_YMOD                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
-#define REG_DMA6_DSCPTR_CUR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
-#define REG_DMA6_DSCPTR_PRV             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
-#define REG_DMA6_ADDR_CUR               0xFFC4132C         /* DMA6 Current Address */
-#define REG_DMA6_STAT                   0xFFC41330         /* DMA6 Status Register */
-#define REG_DMA6_XCNT_CUR               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA6_YCNT_CUR               0xFFC41338         /* DMA6 Current Row Count (2D only) */
-#define REG_DMA6_BWLCNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
-#define REG_DMA6_BWLCNT_CUR             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
-#define REG_DMA6_BWMCNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
-#define REG_DMA6_BWMCNT_CUR             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA7
-   ========================= */
-#define REG_DMA7_DSCPTR_NXT             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
-#define REG_DMA7_ADDRSTART              0xFFC41384         /* DMA7 Start Address of Current Buffer */
-#define REG_DMA7_CFG                    0xFFC41388         /* DMA7 Configuration Register */
-#define REG_DMA7_XCNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
-#define REG_DMA7_XMOD                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
-#define REG_DMA7_YCNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
-#define REG_DMA7_YMOD                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
-#define REG_DMA7_DSCPTR_CUR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
-#define REG_DMA7_DSCPTR_PRV             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
-#define REG_DMA7_ADDR_CUR               0xFFC413AC         /* DMA7 Current Address */
-#define REG_DMA7_STAT                   0xFFC413B0         /* DMA7 Status Register */
-#define REG_DMA7_XCNT_CUR               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA7_YCNT_CUR               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
-#define REG_DMA7_BWLCNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
-#define REG_DMA7_BWLCNT_CUR             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
-#define REG_DMA7_BWMCNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
-#define REG_DMA7_BWMCNT_CUR             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA8
-   ========================= */
-#define REG_DMA8_DSCPTR_NXT             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
-#define REG_DMA8_ADDRSTART              0xFFC41404         /* DMA8 Start Address of Current Buffer */
-#define REG_DMA8_CFG                    0xFFC41408         /* DMA8 Configuration Register */
-#define REG_DMA8_XCNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
-#define REG_DMA8_XMOD                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
-#define REG_DMA8_YCNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
-#define REG_DMA8_YMOD                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
-#define REG_DMA8_DSCPTR_CUR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
-#define REG_DMA8_DSCPTR_PRV             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
-#define REG_DMA8_ADDR_CUR               0xFFC4142C         /* DMA8 Current Address */
-#define REG_DMA8_STAT                   0xFFC41430         /* DMA8 Status Register */
-#define REG_DMA8_XCNT_CUR               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA8_YCNT_CUR               0xFFC41438         /* DMA8 Current Row Count (2D only) */
-#define REG_DMA8_BWLCNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
-#define REG_DMA8_BWLCNT_CUR             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
-#define REG_DMA8_BWMCNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
-#define REG_DMA8_BWMCNT_CUR             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA9
-   ========================= */
-#define REG_DMA9_DSCPTR_NXT             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
-#define REG_DMA9_ADDRSTART              0xFFC41484         /* DMA9 Start Address of Current Buffer */
-#define REG_DMA9_CFG                    0xFFC41488         /* DMA9 Configuration Register */
-#define REG_DMA9_XCNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
-#define REG_DMA9_XMOD                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
-#define REG_DMA9_YCNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
-#define REG_DMA9_YMOD                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
-#define REG_DMA9_DSCPTR_CUR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
-#define REG_DMA9_DSCPTR_PRV             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
-#define REG_DMA9_ADDR_CUR               0xFFC414AC         /* DMA9 Current Address */
-#define REG_DMA9_STAT                   0xFFC414B0         /* DMA9 Status Register */
-#define REG_DMA9_XCNT_CUR               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA9_YCNT_CUR               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
-#define REG_DMA9_BWLCNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
-#define REG_DMA9_BWLCNT_CUR             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
-#define REG_DMA9_BWMCNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
-#define REG_DMA9_BWMCNT_CUR             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA10
-   ========================= */
-#define REG_DMA10_DSCPTR_NXT            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
-#define REG_DMA10_ADDRSTART             0xFFC05004         /* DMA10 Start Address of Current Buffer */
-#define REG_DMA10_CFG                   0xFFC05008         /* DMA10 Configuration Register */
-#define REG_DMA10_XCNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
-#define REG_DMA10_XMOD                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
-#define REG_DMA10_YCNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
-#define REG_DMA10_YMOD                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
-#define REG_DMA10_DSCPTR_CUR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
-#define REG_DMA10_DSCPTR_PRV            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
-#define REG_DMA10_ADDR_CUR              0xFFC0502C         /* DMA10 Current Address */
-#define REG_DMA10_STAT                  0xFFC05030         /* DMA10 Status Register */
-#define REG_DMA10_XCNT_CUR              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA10_YCNT_CUR              0xFFC05038         /* DMA10 Current Row Count (2D only) */
-#define REG_DMA10_BWLCNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
-#define REG_DMA10_BWLCNT_CUR            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
-#define REG_DMA10_BWMCNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
-#define REG_DMA10_BWMCNT_CUR            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA11
-   ========================= */
-#define REG_DMA11_DSCPTR_NXT            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
-#define REG_DMA11_ADDRSTART             0xFFC05084         /* DMA11 Start Address of Current Buffer */
-#define REG_DMA11_CFG                   0xFFC05088         /* DMA11 Configuration Register */
-#define REG_DMA11_XCNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
-#define REG_DMA11_XMOD                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
-#define REG_DMA11_YCNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
-#define REG_DMA11_YMOD                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
-#define REG_DMA11_DSCPTR_CUR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
-#define REG_DMA11_DSCPTR_PRV            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
-#define REG_DMA11_ADDR_CUR              0xFFC050AC         /* DMA11 Current Address */
-#define REG_DMA11_STAT                  0xFFC050B0         /* DMA11 Status Register */
-#define REG_DMA11_XCNT_CUR              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA11_YCNT_CUR              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
-#define REG_DMA11_BWLCNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
-#define REG_DMA11_BWLCNT_CUR            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
-#define REG_DMA11_BWMCNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
-#define REG_DMA11_BWMCNT_CUR            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA12
-   ========================= */
-#define REG_DMA12_DSCPTR_NXT            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
-#define REG_DMA12_ADDRSTART             0xFFC05104         /* DMA12 Start Address of Current Buffer */
-#define REG_DMA12_CFG                   0xFFC05108         /* DMA12 Configuration Register */
-#define REG_DMA12_XCNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
-#define REG_DMA12_XMOD                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
-#define REG_DMA12_YCNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
-#define REG_DMA12_YMOD                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
-#define REG_DMA12_DSCPTR_CUR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
-#define REG_DMA12_DSCPTR_PRV            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
-#define REG_DMA12_ADDR_CUR              0xFFC0512C         /* DMA12 Current Address */
-#define REG_DMA12_STAT                  0xFFC05130         /* DMA12 Status Register */
-#define REG_DMA12_XCNT_CUR              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA12_YCNT_CUR              0xFFC05138         /* DMA12 Current Row Count (2D only) */
-#define REG_DMA12_BWLCNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
-#define REG_DMA12_BWLCNT_CUR            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
-#define REG_DMA12_BWMCNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
-#define REG_DMA12_BWMCNT_CUR            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA13
-   ========================= */
-#define REG_DMA13_DSCPTR_NXT            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
-#define REG_DMA13_ADDRSTART             0xFFC07004         /* DMA13 Start Address of Current Buffer */
-#define REG_DMA13_CFG                   0xFFC07008         /* DMA13 Configuration Register */
-#define REG_DMA13_XCNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
-#define REG_DMA13_XMOD                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
-#define REG_DMA13_YCNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
-#define REG_DMA13_YMOD                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
-#define REG_DMA13_DSCPTR_CUR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
-#define REG_DMA13_DSCPTR_PRV            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
-#define REG_DMA13_ADDR_CUR              0xFFC0702C         /* DMA13 Current Address */
-#define REG_DMA13_STAT                  0xFFC07030         /* DMA13 Status Register */
-#define REG_DMA13_XCNT_CUR              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA13_YCNT_CUR              0xFFC07038         /* DMA13 Current Row Count (2D only) */
-#define REG_DMA13_BWLCNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
-#define REG_DMA13_BWLCNT_CUR            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
-#define REG_DMA13_BWMCNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
-#define REG_DMA13_BWMCNT_CUR            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA14
-   ========================= */
-#define REG_DMA14_DSCPTR_NXT            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
-#define REG_DMA14_ADDRSTART             0xFFC07084         /* DMA14 Start Address of Current Buffer */
-#define REG_DMA14_CFG                   0xFFC07088         /* DMA14 Configuration Register */
-#define REG_DMA14_XCNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
-#define REG_DMA14_XMOD                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
-#define REG_DMA14_YCNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
-#define REG_DMA14_YMOD                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
-#define REG_DMA14_DSCPTR_CUR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
-#define REG_DMA14_DSCPTR_PRV            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
-#define REG_DMA14_ADDR_CUR              0xFFC070AC         /* DMA14 Current Address */
-#define REG_DMA14_STAT                  0xFFC070B0         /* DMA14 Status Register */
-#define REG_DMA14_XCNT_CUR              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA14_YCNT_CUR              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
-#define REG_DMA14_BWLCNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
-#define REG_DMA14_BWLCNT_CUR            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
-#define REG_DMA14_BWMCNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
-#define REG_DMA14_BWMCNT_CUR            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA15
-   ========================= */
-#define REG_DMA15_DSCPTR_NXT            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
-#define REG_DMA15_ADDRSTART             0xFFC07104         /* DMA15 Start Address of Current Buffer */
-#define REG_DMA15_CFG                   0xFFC07108         /* DMA15 Configuration Register */
-#define REG_DMA15_XCNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
-#define REG_DMA15_XMOD                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
-#define REG_DMA15_YCNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
-#define REG_DMA15_YMOD                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
-#define REG_DMA15_DSCPTR_CUR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
-#define REG_DMA15_DSCPTR_PRV            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
-#define REG_DMA15_ADDR_CUR              0xFFC0712C         /* DMA15 Current Address */
-#define REG_DMA15_STAT                  0xFFC07130         /* DMA15 Status Register */
-#define REG_DMA15_XCNT_CUR              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA15_YCNT_CUR              0xFFC07138         /* DMA15 Current Row Count (2D only) */
-#define REG_DMA15_BWLCNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
-#define REG_DMA15_BWLCNT_CUR            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
-#define REG_DMA15_BWMCNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
-#define REG_DMA15_BWMCNT_CUR            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA16
-   ========================= */
-#define REG_DMA16_DSCPTR_NXT            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
-#define REG_DMA16_ADDRSTART             0xFFC07184         /* DMA16 Start Address of Current Buffer */
-#define REG_DMA16_CFG                   0xFFC07188         /* DMA16 Configuration Register */
-#define REG_DMA16_XCNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
-#define REG_DMA16_XMOD                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
-#define REG_DMA16_YCNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
-#define REG_DMA16_YMOD                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
-#define REG_DMA16_DSCPTR_CUR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
-#define REG_DMA16_DSCPTR_PRV            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
-#define REG_DMA16_ADDR_CUR              0xFFC071AC         /* DMA16 Current Address */
-#define REG_DMA16_STAT                  0xFFC071B0         /* DMA16 Status Register */
-#define REG_DMA16_XCNT_CUR              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA16_YCNT_CUR              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
-#define REG_DMA16_BWLCNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
-#define REG_DMA16_BWLCNT_CUR            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
-#define REG_DMA16_BWMCNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
-#define REG_DMA16_BWMCNT_CUR            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA17
-   ========================= */
-#define REG_DMA17_DSCPTR_NXT            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
-#define REG_DMA17_ADDRSTART             0xFFC07204         /* DMA17 Start Address of Current Buffer */
-#define REG_DMA17_CFG                   0xFFC07208         /* DMA17 Configuration Register */
-#define REG_DMA17_XCNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
-#define REG_DMA17_XMOD                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
-#define REG_DMA17_YCNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
-#define REG_DMA17_YMOD                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
-#define REG_DMA17_DSCPTR_CUR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
-#define REG_DMA17_DSCPTR_PRV            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
-#define REG_DMA17_ADDR_CUR              0xFFC0722C         /* DMA17 Current Address */
-#define REG_DMA17_STAT                  0xFFC07230         /* DMA17 Status Register */
-#define REG_DMA17_XCNT_CUR              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA17_YCNT_CUR              0xFFC07238         /* DMA17 Current Row Count (2D only) */
-#define REG_DMA17_BWLCNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
-#define REG_DMA17_BWLCNT_CUR            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
-#define REG_DMA17_BWMCNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
-#define REG_DMA17_BWMCNT_CUR            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA18
-   ========================= */
-#define REG_DMA18_DSCPTR_NXT            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
-#define REG_DMA18_ADDRSTART             0xFFC07284         /* DMA18 Start Address of Current Buffer */
-#define REG_DMA18_CFG                   0xFFC07288         /* DMA18 Configuration Register */
-#define REG_DMA18_XCNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
-#define REG_DMA18_XMOD                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
-#define REG_DMA18_YCNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
-#define REG_DMA18_YMOD                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
-#define REG_DMA18_DSCPTR_CUR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
-#define REG_DMA18_DSCPTR_PRV            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
-#define REG_DMA18_ADDR_CUR              0xFFC072AC         /* DMA18 Current Address */
-#define REG_DMA18_STAT                  0xFFC072B0         /* DMA18 Status Register */
-#define REG_DMA18_XCNT_CUR              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA18_YCNT_CUR              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
-#define REG_DMA18_BWLCNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
-#define REG_DMA18_BWLCNT_CUR            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
-#define REG_DMA18_BWMCNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
-#define REG_DMA18_BWMCNT_CUR            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA19
-   ========================= */
-#define REG_DMA19_DSCPTR_NXT            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
-#define REG_DMA19_ADDRSTART             0xFFC07304         /* DMA19 Start Address of Current Buffer */
-#define REG_DMA19_CFG                   0xFFC07308         /* DMA19 Configuration Register */
-#define REG_DMA19_XCNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
-#define REG_DMA19_XMOD                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
-#define REG_DMA19_YCNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
-#define REG_DMA19_YMOD                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
-#define REG_DMA19_DSCPTR_CUR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
-#define REG_DMA19_DSCPTR_PRV            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
-#define REG_DMA19_ADDR_CUR              0xFFC0732C         /* DMA19 Current Address */
-#define REG_DMA19_STAT                  0xFFC07330         /* DMA19 Status Register */
-#define REG_DMA19_XCNT_CUR              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA19_YCNT_CUR              0xFFC07338         /* DMA19 Current Row Count (2D only) */
-#define REG_DMA19_BWLCNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
-#define REG_DMA19_BWLCNT_CUR            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
-#define REG_DMA19_BWMCNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
-#define REG_DMA19_BWMCNT_CUR            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA20
-   ========================= */
-#define REG_DMA20_DSCPTR_NXT            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
-#define REG_DMA20_ADDRSTART             0xFFC07384         /* DMA20 Start Address of Current Buffer */
-#define REG_DMA20_CFG                   0xFFC07388         /* DMA20 Configuration Register */
-#define REG_DMA20_XCNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
-#define REG_DMA20_XMOD                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
-#define REG_DMA20_YCNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
-#define REG_DMA20_YMOD                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
-#define REG_DMA20_DSCPTR_CUR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
-#define REG_DMA20_DSCPTR_PRV            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
-#define REG_DMA20_ADDR_CUR              0xFFC073AC         /* DMA20 Current Address */
-#define REG_DMA20_STAT                  0xFFC073B0         /* DMA20 Status Register */
-#define REG_DMA20_XCNT_CUR              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA20_YCNT_CUR              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
-#define REG_DMA20_BWLCNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
-#define REG_DMA20_BWLCNT_CUR            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
-#define REG_DMA20_BWMCNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
-#define REG_DMA20_BWMCNT_CUR            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA21
-   ========================= */
-#define REG_DMA21_DSCPTR_NXT            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
-#define REG_DMA21_ADDRSTART             0xFFC09004         /* DMA21 Start Address of Current Buffer */
-#define REG_DMA21_CFG                   0xFFC09008         /* DMA21 Configuration Register */
-#define REG_DMA21_XCNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
-#define REG_DMA21_XMOD                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
-#define REG_DMA21_YCNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
-#define REG_DMA21_YMOD                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
-#define REG_DMA21_DSCPTR_CUR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
-#define REG_DMA21_DSCPTR_PRV            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
-#define REG_DMA21_ADDR_CUR              0xFFC0902C         /* DMA21 Current Address */
-#define REG_DMA21_STAT                  0xFFC09030         /* DMA21 Status Register */
-#define REG_DMA21_XCNT_CUR              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA21_YCNT_CUR              0xFFC09038         /* DMA21 Current Row Count (2D only) */
-#define REG_DMA21_BWLCNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
-#define REG_DMA21_BWLCNT_CUR            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
-#define REG_DMA21_BWMCNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
-#define REG_DMA21_BWMCNT_CUR            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA22
-   ========================= */
-#define REG_DMA22_DSCPTR_NXT            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
-#define REG_DMA22_ADDRSTART             0xFFC09084         /* DMA22 Start Address of Current Buffer */
-#define REG_DMA22_CFG                   0xFFC09088         /* DMA22 Configuration Register */
-#define REG_DMA22_XCNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
-#define REG_DMA22_XMOD                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
-#define REG_DMA22_YCNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
-#define REG_DMA22_YMOD                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
-#define REG_DMA22_DSCPTR_CUR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
-#define REG_DMA22_DSCPTR_PRV            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
-#define REG_DMA22_ADDR_CUR              0xFFC090AC         /* DMA22 Current Address */
-#define REG_DMA22_STAT                  0xFFC090B0         /* DMA22 Status Register */
-#define REG_DMA22_XCNT_CUR              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA22_YCNT_CUR              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
-#define REG_DMA22_BWLCNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
-#define REG_DMA22_BWLCNT_CUR            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
-#define REG_DMA22_BWMCNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
-#define REG_DMA22_BWMCNT_CUR            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA23
-   ========================= */
-#define REG_DMA23_DSCPTR_NXT            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
-#define REG_DMA23_ADDRSTART             0xFFC09104         /* DMA23 Start Address of Current Buffer */
-#define REG_DMA23_CFG                   0xFFC09108         /* DMA23 Configuration Register */
-#define REG_DMA23_XCNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
-#define REG_DMA23_XMOD                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
-#define REG_DMA23_YCNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
-#define REG_DMA23_YMOD                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
-#define REG_DMA23_DSCPTR_CUR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
-#define REG_DMA23_DSCPTR_PRV            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
-#define REG_DMA23_ADDR_CUR              0xFFC0912C         /* DMA23 Current Address */
-#define REG_DMA23_STAT                  0xFFC09130         /* DMA23 Status Register */
-#define REG_DMA23_XCNT_CUR              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA23_YCNT_CUR              0xFFC09138         /* DMA23 Current Row Count (2D only) */
-#define REG_DMA23_BWLCNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
-#define REG_DMA23_BWLCNT_CUR            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
-#define REG_DMA23_BWMCNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
-#define REG_DMA23_BWMCNT_CUR            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA24
-   ========================= */
-#define REG_DMA24_DSCPTR_NXT            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
-#define REG_DMA24_ADDRSTART             0xFFC09184         /* DMA24 Start Address of Current Buffer */
-#define REG_DMA24_CFG                   0xFFC09188         /* DMA24 Configuration Register */
-#define REG_DMA24_XCNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
-#define REG_DMA24_XMOD                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
-#define REG_DMA24_YCNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
-#define REG_DMA24_YMOD                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
-#define REG_DMA24_DSCPTR_CUR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
-#define REG_DMA24_DSCPTR_PRV            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
-#define REG_DMA24_ADDR_CUR              0xFFC091AC         /* DMA24 Current Address */
-#define REG_DMA24_STAT                  0xFFC091B0         /* DMA24 Status Register */
-#define REG_DMA24_XCNT_CUR              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA24_YCNT_CUR              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
-#define REG_DMA24_BWLCNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
-#define REG_DMA24_BWLCNT_CUR            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
-#define REG_DMA24_BWMCNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
-#define REG_DMA24_BWMCNT_CUR            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA25
-   ========================= */
-#define REG_DMA25_DSCPTR_NXT            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
-#define REG_DMA25_ADDRSTART             0xFFC09204         /* DMA25 Start Address of Current Buffer */
-#define REG_DMA25_CFG                   0xFFC09208         /* DMA25 Configuration Register */
-#define REG_DMA25_XCNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
-#define REG_DMA25_XMOD                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
-#define REG_DMA25_YCNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
-#define REG_DMA25_YMOD                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
-#define REG_DMA25_DSCPTR_CUR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
-#define REG_DMA25_DSCPTR_PRV            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
-#define REG_DMA25_ADDR_CUR              0xFFC0922C         /* DMA25 Current Address */
-#define REG_DMA25_STAT                  0xFFC09230         /* DMA25 Status Register */
-#define REG_DMA25_XCNT_CUR              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA25_YCNT_CUR              0xFFC09238         /* DMA25 Current Row Count (2D only) */
-#define REG_DMA25_BWLCNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
-#define REG_DMA25_BWLCNT_CUR            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
-#define REG_DMA25_BWMCNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
-#define REG_DMA25_BWMCNT_CUR            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA26
-   ========================= */
-#define REG_DMA26_DSCPTR_NXT            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
-#define REG_DMA26_ADDRSTART             0xFFC09284         /* DMA26 Start Address of Current Buffer */
-#define REG_DMA26_CFG                   0xFFC09288         /* DMA26 Configuration Register */
-#define REG_DMA26_XCNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
-#define REG_DMA26_XMOD                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
-#define REG_DMA26_YCNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
-#define REG_DMA26_YMOD                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
-#define REG_DMA26_DSCPTR_CUR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
-#define REG_DMA26_DSCPTR_PRV            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
-#define REG_DMA26_ADDR_CUR              0xFFC092AC         /* DMA26 Current Address */
-#define REG_DMA26_STAT                  0xFFC092B0         /* DMA26 Status Register */
-#define REG_DMA26_XCNT_CUR              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA26_YCNT_CUR              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
-#define REG_DMA26_BWLCNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
-#define REG_DMA26_BWLCNT_CUR            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
-#define REG_DMA26_BWMCNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
-#define REG_DMA26_BWMCNT_CUR            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA27
-   ========================= */
-#define REG_DMA27_DSCPTR_NXT            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
-#define REG_DMA27_ADDRSTART             0xFFC09304         /* DMA27 Start Address of Current Buffer */
-#define REG_DMA27_CFG                   0xFFC09308         /* DMA27 Configuration Register */
-#define REG_DMA27_XCNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
-#define REG_DMA27_XMOD                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
-#define REG_DMA27_YCNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
-#define REG_DMA27_YMOD                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
-#define REG_DMA27_DSCPTR_CUR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
-#define REG_DMA27_DSCPTR_PRV            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
-#define REG_DMA27_ADDR_CUR              0xFFC0932C         /* DMA27 Current Address */
-#define REG_DMA27_STAT                  0xFFC09330         /* DMA27 Status Register */
-#define REG_DMA27_XCNT_CUR              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA27_YCNT_CUR              0xFFC09338         /* DMA27 Current Row Count (2D only) */
-#define REG_DMA27_BWLCNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
-#define REG_DMA27_BWLCNT_CUR            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
-#define REG_DMA27_BWMCNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
-#define REG_DMA27_BWMCNT_CUR            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA28
-   ========================= */
-#define REG_DMA28_DSCPTR_NXT            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
-#define REG_DMA28_ADDRSTART             0xFFC09384         /* DMA28 Start Address of Current Buffer */
-#define REG_DMA28_CFG                   0xFFC09388         /* DMA28 Configuration Register */
-#define REG_DMA28_XCNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
-#define REG_DMA28_XMOD                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
-#define REG_DMA28_YCNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
-#define REG_DMA28_YMOD                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
-#define REG_DMA28_DSCPTR_CUR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
-#define REG_DMA28_DSCPTR_PRV            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
-#define REG_DMA28_ADDR_CUR              0xFFC093AC         /* DMA28 Current Address */
-#define REG_DMA28_STAT                  0xFFC093B0         /* DMA28 Status Register */
-#define REG_DMA28_XCNT_CUR              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA28_YCNT_CUR              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
-#define REG_DMA28_BWLCNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
-#define REG_DMA28_BWLCNT_CUR            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
-#define REG_DMA28_BWMCNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
-#define REG_DMA28_BWMCNT_CUR            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA29
-   ========================= */
-#define REG_DMA29_DSCPTR_NXT            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
-#define REG_DMA29_ADDRSTART             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
-#define REG_DMA29_CFG                   0xFFC0B008         /* DMA29 Configuration Register */
-#define REG_DMA29_XCNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
-#define REG_DMA29_XMOD                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
-#define REG_DMA29_YCNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
-#define REG_DMA29_YMOD                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
-#define REG_DMA29_DSCPTR_CUR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
-#define REG_DMA29_DSCPTR_PRV            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
-#define REG_DMA29_ADDR_CUR              0xFFC0B02C         /* DMA29 Current Address */
-#define REG_DMA29_STAT                  0xFFC0B030         /* DMA29 Status Register */
-#define REG_DMA29_XCNT_CUR              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA29_YCNT_CUR              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
-#define REG_DMA29_BWLCNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
-#define REG_DMA29_BWLCNT_CUR            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
-#define REG_DMA29_BWMCNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
-#define REG_DMA29_BWMCNT_CUR            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA30
-   ========================= */
-#define REG_DMA30_DSCPTR_NXT            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
-#define REG_DMA30_ADDRSTART             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
-#define REG_DMA30_CFG                   0xFFC0B088         /* DMA30 Configuration Register */
-#define REG_DMA30_XCNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
-#define REG_DMA30_XMOD                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
-#define REG_DMA30_YCNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
-#define REG_DMA30_YMOD                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
-#define REG_DMA30_DSCPTR_CUR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
-#define REG_DMA30_DSCPTR_PRV            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
-#define REG_DMA30_ADDR_CUR              0xFFC0B0AC         /* DMA30 Current Address */
-#define REG_DMA30_STAT                  0xFFC0B0B0         /* DMA30 Status Register */
-#define REG_DMA30_XCNT_CUR              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA30_YCNT_CUR              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
-#define REG_DMA30_BWLCNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
-#define REG_DMA30_BWLCNT_CUR            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
-#define REG_DMA30_BWMCNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
-#define REG_DMA30_BWMCNT_CUR            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA31
-   ========================= */
-#define REG_DMA31_DSCPTR_NXT            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
-#define REG_DMA31_ADDRSTART             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
-#define REG_DMA31_CFG                   0xFFC0B108         /* DMA31 Configuration Register */
-#define REG_DMA31_XCNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
-#define REG_DMA31_XMOD                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
-#define REG_DMA31_YCNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
-#define REG_DMA31_YMOD                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
-#define REG_DMA31_DSCPTR_CUR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
-#define REG_DMA31_DSCPTR_PRV            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
-#define REG_DMA31_ADDR_CUR              0xFFC0B12C         /* DMA31 Current Address */
-#define REG_DMA31_STAT                  0xFFC0B130         /* DMA31 Status Register */
-#define REG_DMA31_XCNT_CUR              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA31_YCNT_CUR              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
-#define REG_DMA31_BWLCNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
-#define REG_DMA31_BWLCNT_CUR            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
-#define REG_DMA31_BWMCNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
-#define REG_DMA31_BWMCNT_CUR            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA32
-   ========================= */
-#define REG_DMA32_DSCPTR_NXT            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
-#define REG_DMA32_ADDRSTART             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
-#define REG_DMA32_CFG                   0xFFC0B188         /* DMA32 Configuration Register */
-#define REG_DMA32_XCNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
-#define REG_DMA32_XMOD                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
-#define REG_DMA32_YCNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
-#define REG_DMA32_YMOD                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
-#define REG_DMA32_DSCPTR_CUR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
-#define REG_DMA32_DSCPTR_PRV            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
-#define REG_DMA32_ADDR_CUR              0xFFC0B1AC         /* DMA32 Current Address */
-#define REG_DMA32_STAT                  0xFFC0B1B0         /* DMA32 Status Register */
-#define REG_DMA32_XCNT_CUR              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA32_YCNT_CUR              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
-#define REG_DMA32_BWLCNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
-#define REG_DMA32_BWLCNT_CUR            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
-#define REG_DMA32_BWMCNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
-#define REG_DMA32_BWMCNT_CUR            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA33
-   ========================= */
-#define REG_DMA33_DSCPTR_NXT            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
-#define REG_DMA33_ADDRSTART             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
-#define REG_DMA33_CFG                   0xFFC0D008         /* DMA33 Configuration Register */
-#define REG_DMA33_XCNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
-#define REG_DMA33_XMOD                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
-#define REG_DMA33_YCNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
-#define REG_DMA33_YMOD                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
-#define REG_DMA33_DSCPTR_CUR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
-#define REG_DMA33_DSCPTR_PRV            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
-#define REG_DMA33_ADDR_CUR              0xFFC0D02C         /* DMA33 Current Address */
-#define REG_DMA33_STAT                  0xFFC0D030         /* DMA33 Status Register */
-#define REG_DMA33_XCNT_CUR              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA33_YCNT_CUR              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
-#define REG_DMA33_BWLCNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
-#define REG_DMA33_BWLCNT_CUR            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
-#define REG_DMA33_BWMCNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
-#define REG_DMA33_BWMCNT_CUR            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA34
-   ========================= */
-#define REG_DMA34_DSCPTR_NXT            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
-#define REG_DMA34_ADDRSTART             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
-#define REG_DMA34_CFG                   0xFFC0D088         /* DMA34 Configuration Register */
-#define REG_DMA34_XCNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
-#define REG_DMA34_XMOD                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
-#define REG_DMA34_YCNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
-#define REG_DMA34_YMOD                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
-#define REG_DMA34_DSCPTR_CUR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
-#define REG_DMA34_DSCPTR_PRV            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
-#define REG_DMA34_ADDR_CUR              0xFFC0D0AC         /* DMA34 Current Address */
-#define REG_DMA34_STAT                  0xFFC0D0B0         /* DMA34 Status Register */
-#define REG_DMA34_XCNT_CUR              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA34_YCNT_CUR              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
-#define REG_DMA34_BWLCNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
-#define REG_DMA34_BWLCNT_CUR            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
-#define REG_DMA34_BWMCNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
-#define REG_DMA34_BWMCNT_CUR            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA35
-   ========================= */
-#define REG_DMA35_DSCPTR_NXT            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
-#define REG_DMA35_ADDRSTART             0xFFC10004         /* DMA35 Start Address of Current Buffer */
-#define REG_DMA35_CFG                   0xFFC10008         /* DMA35 Configuration Register */
-#define REG_DMA35_XCNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
-#define REG_DMA35_XMOD                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
-#define REG_DMA35_YCNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
-#define REG_DMA35_YMOD                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
-#define REG_DMA35_DSCPTR_CUR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
-#define REG_DMA35_DSCPTR_PRV            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
-#define REG_DMA35_ADDR_CUR              0xFFC1002C         /* DMA35 Current Address */
-#define REG_DMA35_STAT                  0xFFC10030         /* DMA35 Status Register */
-#define REG_DMA35_XCNT_CUR              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA35_YCNT_CUR              0xFFC10038         /* DMA35 Current Row Count (2D only) */
-#define REG_DMA35_BWLCNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
-#define REG_DMA35_BWLCNT_CUR            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
-#define REG_DMA35_BWMCNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
-#define REG_DMA35_BWMCNT_CUR            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA36
-   ========================= */
-#define REG_DMA36_DSCPTR_NXT            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
-#define REG_DMA36_ADDRSTART             0xFFC10084         /* DMA36 Start Address of Current Buffer */
-#define REG_DMA36_CFG                   0xFFC10088         /* DMA36 Configuration Register */
-#define REG_DMA36_XCNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
-#define REG_DMA36_XMOD                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
-#define REG_DMA36_YCNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
-#define REG_DMA36_YMOD                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
-#define REG_DMA36_DSCPTR_CUR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
-#define REG_DMA36_DSCPTR_PRV            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
-#define REG_DMA36_ADDR_CUR              0xFFC100AC         /* DMA36 Current Address */
-#define REG_DMA36_STAT                  0xFFC100B0         /* DMA36 Status Register */
-#define REG_DMA36_XCNT_CUR              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA36_YCNT_CUR              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
-#define REG_DMA36_BWLCNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
-#define REG_DMA36_BWLCNT_CUR            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
-#define REG_DMA36_BWMCNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
-#define REG_DMA36_BWMCNT_CUR            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA37
-   ========================= */
-#define REG_DMA37_DSCPTR_NXT            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
-#define REG_DMA37_ADDRSTART             0xFFC10104         /* DMA37 Start Address of Current Buffer */
-#define REG_DMA37_CFG                   0xFFC10108         /* DMA37 Configuration Register */
-#define REG_DMA37_XCNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
-#define REG_DMA37_XMOD                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
-#define REG_DMA37_YCNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
-#define REG_DMA37_YMOD                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
-#define REG_DMA37_DSCPTR_CUR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
-#define REG_DMA37_DSCPTR_PRV            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
-#define REG_DMA37_ADDR_CUR              0xFFC1012C         /* DMA37 Current Address */
-#define REG_DMA37_STAT                  0xFFC10130         /* DMA37 Status Register */
-#define REG_DMA37_XCNT_CUR              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA37_YCNT_CUR              0xFFC10138         /* DMA37 Current Row Count (2D only) */
-#define REG_DMA37_BWLCNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
-#define REG_DMA37_BWLCNT_CUR            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
-#define REG_DMA37_BWMCNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
-#define REG_DMA37_BWMCNT_CUR            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA38
-   ========================= */
-#define REG_DMA38_DSCPTR_NXT            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
-#define REG_DMA38_ADDRSTART             0xFFC12004         /* DMA38 Start Address of Current Buffer */
-#define REG_DMA38_CFG                   0xFFC12008         /* DMA38 Configuration Register */
-#define REG_DMA38_XCNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
-#define REG_DMA38_XMOD                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
-#define REG_DMA38_YCNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
-#define REG_DMA38_YMOD                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
-#define REG_DMA38_DSCPTR_CUR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
-#define REG_DMA38_DSCPTR_PRV            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
-#define REG_DMA38_ADDR_CUR              0xFFC1202C         /* DMA38 Current Address */
-#define REG_DMA38_STAT                  0xFFC12030         /* DMA38 Status Register */
-#define REG_DMA38_XCNT_CUR              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA38_YCNT_CUR              0xFFC12038         /* DMA38 Current Row Count (2D only) */
-#define REG_DMA38_BWLCNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
-#define REG_DMA38_BWLCNT_CUR            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
-#define REG_DMA38_BWMCNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
-#define REG_DMA38_BWMCNT_CUR            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA39
-   ========================= */
-#define REG_DMA39_DSCPTR_NXT            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
-#define REG_DMA39_ADDRSTART             0xFFC12084         /* DMA39 Start Address of Current Buffer */
-#define REG_DMA39_CFG                   0xFFC12088         /* DMA39 Configuration Register */
-#define REG_DMA39_XCNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
-#define REG_DMA39_XMOD                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
-#define REG_DMA39_YCNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
-#define REG_DMA39_YMOD                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
-#define REG_DMA39_DSCPTR_CUR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
-#define REG_DMA39_DSCPTR_PRV            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
-#define REG_DMA39_ADDR_CUR              0xFFC120AC         /* DMA39 Current Address */
-#define REG_DMA39_STAT                  0xFFC120B0         /* DMA39 Status Register */
-#define REG_DMA39_XCNT_CUR              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA39_YCNT_CUR              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
-#define REG_DMA39_BWLCNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
-#define REG_DMA39_BWLCNT_CUR            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
-#define REG_DMA39_BWMCNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
-#define REG_DMA39_BWMCNT_CUR            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA40
-   ========================= */
-#define REG_DMA40_DSCPTR_NXT            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
-#define REG_DMA40_ADDRSTART             0xFFC12104         /* DMA40 Start Address of Current Buffer */
-#define REG_DMA40_CFG                   0xFFC12108         /* DMA40 Configuration Register */
-#define REG_DMA40_XCNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
-#define REG_DMA40_XMOD                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
-#define REG_DMA40_YCNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
-#define REG_DMA40_YMOD                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
-#define REG_DMA40_DSCPTR_CUR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
-#define REG_DMA40_DSCPTR_PRV            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
-#define REG_DMA40_ADDR_CUR              0xFFC1212C         /* DMA40 Current Address */
-#define REG_DMA40_STAT                  0xFFC12130         /* DMA40 Status Register */
-#define REG_DMA40_XCNT_CUR              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA40_YCNT_CUR              0xFFC12138         /* DMA40 Current Row Count (2D only) */
-#define REG_DMA40_BWLCNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
-#define REG_DMA40_BWLCNT_CUR            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
-#define REG_DMA40_BWMCNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
-#define REG_DMA40_BWMCNT_CUR            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA41
-   ========================= */
-#define REG_DMA41_DSCPTR_NXT            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
-#define REG_DMA41_ADDRSTART             0xFFC12184         /* DMA41 Start Address of Current Buffer */
-#define REG_DMA41_CFG                   0xFFC12188         /* DMA41 Configuration Register */
-#define REG_DMA41_XCNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
-#define REG_DMA41_XMOD                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
-#define REG_DMA41_YCNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
-#define REG_DMA41_YMOD                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
-#define REG_DMA41_DSCPTR_CUR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
-#define REG_DMA41_DSCPTR_PRV            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
-#define REG_DMA41_ADDR_CUR              0xFFC121AC         /* DMA41 Current Address */
-#define REG_DMA41_STAT                  0xFFC121B0         /* DMA41 Status Register */
-#define REG_DMA41_XCNT_CUR              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA41_YCNT_CUR              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
-#define REG_DMA41_BWLCNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
-#define REG_DMA41_BWLCNT_CUR            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
-#define REG_DMA41_BWMCNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
-#define REG_DMA41_BWMCNT_CUR            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA42
-   ========================= */
-#define REG_DMA42_DSCPTR_NXT            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
-#define REG_DMA42_ADDRSTART             0xFFC14004         /* DMA42 Start Address of Current Buffer */
-#define REG_DMA42_CFG                   0xFFC14008         /* DMA42 Configuration Register */
-#define REG_DMA42_XCNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
-#define REG_DMA42_XMOD                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
-#define REG_DMA42_YCNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
-#define REG_DMA42_YMOD                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
-#define REG_DMA42_DSCPTR_CUR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
-#define REG_DMA42_DSCPTR_PRV            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
-#define REG_DMA42_ADDR_CUR              0xFFC1402C         /* DMA42 Current Address */
-#define REG_DMA42_STAT                  0xFFC14030         /* DMA42 Status Register */
-#define REG_DMA42_XCNT_CUR              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA42_YCNT_CUR              0xFFC14038         /* DMA42 Current Row Count (2D only) */
-#define REG_DMA42_BWLCNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
-#define REG_DMA42_BWLCNT_CUR            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
-#define REG_DMA42_BWMCNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
-#define REG_DMA42_BWMCNT_CUR            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA43
-   ========================= */
-#define REG_DMA43_DSCPTR_NXT            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
-#define REG_DMA43_ADDRSTART             0xFFC14084         /* DMA43 Start Address of Current Buffer */
-#define REG_DMA43_CFG                   0xFFC14088         /* DMA43 Configuration Register */
-#define REG_DMA43_XCNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
-#define REG_DMA43_XMOD                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
-#define REG_DMA43_YCNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
-#define REG_DMA43_YMOD                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
-#define REG_DMA43_DSCPTR_CUR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
-#define REG_DMA43_DSCPTR_PRV            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
-#define REG_DMA43_ADDR_CUR              0xFFC140AC         /* DMA43 Current Address */
-#define REG_DMA43_STAT                  0xFFC140B0         /* DMA43 Status Register */
-#define REG_DMA43_XCNT_CUR              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA43_YCNT_CUR              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
-#define REG_DMA43_BWLCNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
-#define REG_DMA43_BWLCNT_CUR            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
-#define REG_DMA43_BWMCNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
-#define REG_DMA43_BWMCNT_CUR            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA44
-   ========================= */
-#define REG_DMA44_DSCPTR_NXT            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
-#define REG_DMA44_ADDRSTART             0xFFC14104         /* DMA44 Start Address of Current Buffer */
-#define REG_DMA44_CFG                   0xFFC14108         /* DMA44 Configuration Register */
-#define REG_DMA44_XCNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
-#define REG_DMA44_XMOD                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
-#define REG_DMA44_YCNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
-#define REG_DMA44_YMOD                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
-#define REG_DMA44_DSCPTR_CUR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
-#define REG_DMA44_DSCPTR_PRV            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
-#define REG_DMA44_ADDR_CUR              0xFFC1412C         /* DMA44 Current Address */
-#define REG_DMA44_STAT                  0xFFC14130         /* DMA44 Status Register */
-#define REG_DMA44_XCNT_CUR              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA44_YCNT_CUR              0xFFC14138         /* DMA44 Current Row Count (2D only) */
-#define REG_DMA44_BWLCNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
-#define REG_DMA44_BWLCNT_CUR            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
-#define REG_DMA44_BWMCNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
-#define REG_DMA44_BWMCNT_CUR            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA45
-   ========================= */
-#define REG_DMA45_DSCPTR_NXT            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
-#define REG_DMA45_ADDRSTART             0xFFC14184         /* DMA45 Start Address of Current Buffer */
-#define REG_DMA45_CFG                   0xFFC14188         /* DMA45 Configuration Register */
-#define REG_DMA45_XCNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
-#define REG_DMA45_XMOD                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
-#define REG_DMA45_YCNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
-#define REG_DMA45_YMOD                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
-#define REG_DMA45_DSCPTR_CUR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
-#define REG_DMA45_DSCPTR_PRV            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
-#define REG_DMA45_ADDR_CUR              0xFFC141AC         /* DMA45 Current Address */
-#define REG_DMA45_STAT                  0xFFC141B0         /* DMA45 Status Register */
-#define REG_DMA45_XCNT_CUR              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA45_YCNT_CUR              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
-#define REG_DMA45_BWLCNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
-#define REG_DMA45_BWLCNT_CUR            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
-#define REG_DMA45_BWMCNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
-#define REG_DMA45_BWMCNT_CUR            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA46
-   ========================= */
-#define REG_DMA46_DSCPTR_NXT            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
-#define REG_DMA46_ADDRSTART             0xFFC14204         /* DMA46 Start Address of Current Buffer */
-#define REG_DMA46_CFG                   0xFFC14208         /* DMA46 Configuration Register */
-#define REG_DMA46_XCNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
-#define REG_DMA46_XMOD                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
-#define REG_DMA46_YCNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
-#define REG_DMA46_YMOD                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
-#define REG_DMA46_DSCPTR_CUR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
-#define REG_DMA46_DSCPTR_PRV            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
-#define REG_DMA46_ADDR_CUR              0xFFC1422C         /* DMA46 Current Address */
-#define REG_DMA46_STAT                  0xFFC14230         /* DMA46 Status Register */
-#define REG_DMA46_XCNT_CUR              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA46_YCNT_CUR              0xFFC14238         /* DMA46 Current Row Count (2D only) */
-#define REG_DMA46_BWLCNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
-#define REG_DMA46_BWLCNT_CUR            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
-#define REG_DMA46_BWMCNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
-#define REG_DMA46_BWMCNT_CUR            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_CFG_PDRF                    28                               /* Peripheral Data Request Forward */
-#define BITP_DMA_CFG_TWOD                    26                               /* Two Dimension Addressing Enable */
-#define BITP_DMA_CFG_DESCIDCPY               25                               /* Descriptor ID Copy Control */
-#define BITP_DMA_CFG_TOVEN                   24                               /* Trigger Overrun Error Enable */
-#define BITP_DMA_CFG_TRIG                    22                               /* Generate Outgoing Trigger */
-#define BITP_DMA_CFG_INT                     20                               /* Generate Interrupt */
-#define BITP_DMA_CFG_NDSIZE                  16                               /* Next Descriptor Set Size */
-#define BITP_DMA_CFG_TWAIT                   15                               /* Wait for Trigger */
-#define BITP_DMA_CFG_FLOW                    12                               /* Next Operation */
-#define BITP_DMA_CFG_MSIZE                    8                               /* Memory Transfer Word Size */
-#define BITP_DMA_CFG_PSIZE                    4                               /* Peripheral Transfer Word Size */
-#define BITP_DMA_CFG_CADDR                    3                               /* Use Current Address */
-#define BITP_DMA_CFG_SYNC                     2                               /* Synchronize Work Unit Transitions */
-#define BITP_DMA_CFG_WNR                      1                               /* Write/Read Channel Direction */
-#define BITP_DMA_CFG_EN                       0                               /* DMA Channel Enable */
-
-#define BITM_DMA_CFG_PDRF                    (_ADI_MSK(0x10000000,uint32_t))  /* Peripheral Data Request Forward */
-#define ENUM_DMA_CFG_PDAT_NOTFWD             (_ADI_MSK(0x00000000,uint32_t))  /* PDRF: Peripheral Data Request Not Forwarded */
-#define ENUM_DMA_CFG_PDAT_FWD                (_ADI_MSK(0x10000000,uint32_t))  /* PDRF: Peripheral Data Request Forwarded */
-
-#define BITM_DMA_CFG_TWOD                    (_ADI_MSK(0x04000000,uint32_t))  /* Two Dimension Addressing Enable */
-#define ENUM_DMA_CFG_ADDR1D                  (_ADI_MSK(0x00000000,uint32_t))  /* TWOD: One-Dimensional Addressing */
-#define ENUM_DMA_CFG_ADDR2D                  (_ADI_MSK(0x04000000,uint32_t))  /* TWOD: Two-Dimensional Addressing */
-
-#define BITM_DMA_CFG_DESCIDCPY               (_ADI_MSK(0x02000000,uint32_t))  /* Descriptor ID Copy Control */
-#define ENUM_DMA_CFG_NO_COPY                 (_ADI_MSK(0x00000000,uint32_t))  /* DESCIDCPY: Never Copy */
-#define ENUM_DMA_CFG_COPY                    (_ADI_MSK(0x02000000,uint32_t))  /* DESCIDCPY: Copy on Work Unit Complete */
-
-#define BITM_DMA_CFG_TOVEN                   (_ADI_MSK(0x01000000,uint32_t))  /* Trigger Overrun Error Enable */
-#define ENUM_DMA_CFG_TOV_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* TOVEN: Ignore Trigger Overrun */
-#define ENUM_DMA_CFG_TOV_EN                  (_ADI_MSK(0x01000000,uint32_t))  /* TOVEN: Error on Trigger Overrun */
-
-#define BITM_DMA_CFG_TRIG                    (_ADI_MSK(0x00C00000,uint32_t))  /* Generate Outgoing Trigger */
-#define ENUM_DMA_CFG_NO_TRIG                 (_ADI_MSK(0x00000000,uint32_t))  /* TRIG: Never assert Trigger */
-#define ENUM_DMA_CFG_XCNT_TRIG               (_ADI_MSK(0x00400000,uint32_t))  /* TRIG: Trigger when XCNTCUR reaches 0 */
-#define ENUM_DMA_CFG_YCNT_TRIG               (_ADI_MSK(0x00800000,uint32_t))  /* TRIG: Trigger when YCNTCUR reaches 0 */
-
-#define BITM_DMA_CFG_INT                     (_ADI_MSK(0x00300000,uint32_t))  /* Generate Interrupt */
-#define ENUM_DMA_CFG_NO_INT                  (_ADI_MSK(0x00000000,uint32_t))  /* INT: Never assert Interrupt */
-#define ENUM_DMA_CFG_XCNT_INT                (_ADI_MSK(0x00100000,uint32_t))  /* INT: Interrupt when X Count Expires */
-#define ENUM_DMA_CFG_YCNT_INT                (_ADI_MSK(0x00200000,uint32_t))  /* INT: Interrupt when Y Count Expires */
-#define ENUM_DMA_CFG_PERIPH_INT              (_ADI_MSK(0x00300000,uint32_t))  /* INT: Peripheral Interrupt */
-
-#define BITM_DMA_CFG_NDSIZE                  (_ADI_MSK(0x00070000,uint32_t))  /* Next Descriptor Set Size */
-#define ENUM_DMA_CFG_FETCH01                 (_ADI_MSK(0x00000000,uint32_t))  /* NDSIZE: Fetch one Descriptor Element */
-#define ENUM_DMA_CFG_FETCH02                 (_ADI_MSK(0x00010000,uint32_t))  /* NDSIZE: Fetch two Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH03                 (_ADI_MSK(0x00020000,uint32_t))  /* NDSIZE: Fetch three Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH04                 (_ADI_MSK(0x00030000,uint32_t))  /* NDSIZE: Fetch four Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH05                 (_ADI_MSK(0x00040000,uint32_t))  /* NDSIZE: Fetch five Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH06                 (_ADI_MSK(0x00050000,uint32_t))  /* NDSIZE: Fetch six Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH07                 (_ADI_MSK(0x00060000,uint32_t))  /* NDSIZE: Fetch seven Descriptor Elements */
-
-#define BITM_DMA_CFG_TWAIT                   (_ADI_MSK(0x00008000,uint32_t))  /* Wait for Trigger */
-#define ENUM_DMA_CFG_NO_TRGWAIT              (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: Begin Work Unit Automatically (No Wait) */
-#define ENUM_DMA_CFG_TRGWAIT                 (_ADI_MSK(0x00008000,uint32_t))  /* TWAIT: Wait for Trigger (Halt before Work Unit) */
-
-#define BITM_DMA_CFG_FLOW                    (_ADI_MSK(0x00007000,uint32_t))  /* Next Operation */
-#define ENUM_DMA_CFG_STOP                    (_ADI_MSK(0x00000000,uint32_t))  /* FLOW: STOP - Stop */
-#define ENUM_DMA_CFG_AUTO                    (_ADI_MSK(0x00001000,uint32_t))  /* FLOW: AUTO - Autobuffer */
-#define ENUM_DMA_CFG_DSCLIST                 (_ADI_MSK(0x00004000,uint32_t))  /* FLOW: DSCL - Descriptor List */
-#define ENUM_DMA_CFG_DSCARRAY                (_ADI_MSK(0x00005000,uint32_t))  /* FLOW: DSCA - Descriptor Array */
-#define ENUM_DMA_CFG_DODLIST                 (_ADI_MSK(0x00006000,uint32_t))  /* FLOW: Descriptor On Demand List */
-#define ENUM_DMA_CFG_DODARRAY                (_ADI_MSK(0x00007000,uint32_t))  /* FLOW: Descriptor On Demand Array */
-
-#define BITM_DMA_CFG_MSIZE                   (_ADI_MSK(0x00000700,uint32_t))  /* Memory Transfer Word Size */
-#define ENUM_DMA_CFG_MSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* MSIZE: 1 Byte */
-#define ENUM_DMA_CFG_MSIZE02                 (_ADI_MSK(0x00000100,uint32_t))  /* MSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_MSIZE04                 (_ADI_MSK(0x00000200,uint32_t))  /* MSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_MSIZE08                 (_ADI_MSK(0x00000300,uint32_t))  /* MSIZE: 8 Bytes */
-#define ENUM_DMA_CFG_MSIZE16                 (_ADI_MSK(0x00000400,uint32_t))  /* MSIZE: 16 Bytes */
-#define ENUM_DMA_CFG_MSIZE32                 (_ADI_MSK(0x00000500,uint32_t))  /* MSIZE: 32 Bytes */
-
-#define BITM_DMA_CFG_PSIZE                   (_ADI_MSK(0x00000070,uint32_t))  /* Peripheral Transfer Word Size */
-#define ENUM_DMA_CFG_PSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 Byte */
-#define ENUM_DMA_CFG_PSIZE02                 (_ADI_MSK(0x00000010,uint32_t))  /* PSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_PSIZE04                 (_ADI_MSK(0x00000020,uint32_t))  /* PSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_PSIZE08                 (_ADI_MSK(0x00000030,uint32_t))  /* PSIZE: 8 Bytes */
-
-#define BITM_DMA_CFG_CADDR                   (_ADI_MSK(0x00000008,uint32_t))  /* Use Current Address */
-#define ENUM_DMA_CFG_LD_STARTADDR            (_ADI_MSK(0x00000000,uint32_t))  /* CADDR: Load Starting Address */
-#define ENUM_DMA_CFG_LD_CURADDR              (_ADI_MSK(0x00000008,uint32_t))  /* CADDR: Use Current Address */
-
-#define BITM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* Synchronize Work Unit Transitions */
-#define ENUM_DMA_CFG_NO_SYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* SYNC: No Synchronization */
-#define ENUM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* SYNC: Synchronize  Channel */
-
-#define BITM_DMA_CFG_WNR                     (_ADI_MSK(0x00000002,uint32_t))  /* Write/Read Channel Direction */
-#define ENUM_DMA_CFG_READ                    (_ADI_MSK(0x00000000,uint32_t))  /* WNR: Transmit (Read from memory) */
-#define ENUM_DMA_CFG_WRITE                   (_ADI_MSK(0x00000002,uint32_t))  /* WNR: Receive (Write to memory) */
-
-#define BITM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* DMA Channel Enable */
-#define ENUM_DMA_CFG_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_DSCPTR_PRV                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_DSCPTR_PRV_DESCPPREV         2                               /* Pointer for Previous Descriptor Element */
-#define BITP_DMA_DSCPTR_PRV_PDPO              0                               /* Previous Descriptor Pointer Overrun */
-#define BITM_DMA_DSCPTR_PRV_DESCPPREV        (_ADI_MSK(0xFFFFFFFC,uint32_t))  /* Pointer for Previous Descriptor Element */
-#define BITM_DMA_DSCPTR_PRV_PDPO             (_ADI_MSK(0x00000001,uint32_t))  /* Previous Descriptor Pointer Overrun */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_STAT_TWAIT                  20                               /* Trigger Wait Status */
-#define BITP_DMA_STAT_FIFOFILL               16                               /* FIFO Fill Status */
-#define BITP_DMA_STAT_MBWID                  14                               /* Memory Bus Width */
-#define BITP_DMA_STAT_PBWID                  12                               /* Peripheral Bus Width */
-#define BITP_DMA_STAT_RUN                     8                               /* Run Status */
-#define BITP_DMA_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_DMA_STAT_PIRQ                    2                               /* Peripheral Interrupt Request */
-#define BITP_DMA_STAT_IRQERR                  1                               /* Error Interrupt */
-#define BITP_DMA_STAT_IRQDONE                 0                               /* Work Unit/Row Done Interrupt */
-
-#define BITM_DMA_STAT_TWAIT                  (_ADI_MSK(0x00100000,uint32_t))  /* Trigger Wait Status */
-#define ENUM_DMA_STAT_NOTRIGRX               (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: No trigger received */
-#define ENUM_DMA_STAT_TRIGRX                 (_ADI_MSK(0x00100000,uint32_t))  /* TWAIT: Trigger received */
-
-#define BITM_DMA_STAT_FIFOFILL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Fill Status */
-#define ENUM_DMA_STAT_FIFOEMPTY              (_ADI_MSK(0x00000000,uint32_t))  /* FIFOFILL: Empty */
-#define ENUM_DMA_STAT_FIFO25                 (_ADI_MSK(0x00010000,uint32_t))  /* FIFOFILL: Empty < FIFO = 1/4 Full */
-#define ENUM_DMA_STAT_FIFO50                 (_ADI_MSK(0x00020000,uint32_t))  /* FIFOFILL: 1/4 Full < FIFO = 1/2 Full */
-#define ENUM_DMA_STAT_FIFO75                 (_ADI_MSK(0x00030000,uint32_t))  /* FIFOFILL: 1/2 Full < FIFO = 3/4 Full */
-#define ENUM_DMA_STAT_FIFONEARFULL           (_ADI_MSK(0x00040000,uint32_t))  /* FIFOFILL: 3/4 Full < FIFO = Full */
-#define ENUM_DMA_STAT_FIFOFULL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFOFILL: Full */
-
-#define BITM_DMA_STAT_MBWID                  (_ADI_MSK(0x0000C000,uint32_t))  /* Memory Bus Width */
-#define ENUM_DMA_STAT_MBUS02                 (_ADI_MSK(0x00000000,uint32_t))  /* MBWID: 2 Bytes */
-#define ENUM_DMA_STAT_MBUS04                 (_ADI_MSK(0x00004000,uint32_t))  /* MBWID: 4 Bytes */
-#define ENUM_DMA_STAT_MBUS08                 (_ADI_MSK(0x00008000,uint32_t))  /* MBWID: 8 Bytes */
-#define ENUM_DMA_STAT_MBUS16                 (_ADI_MSK(0x0000C000,uint32_t))  /* MBWID: 16 Bytes */
-
-#define BITM_DMA_STAT_PBWID                  (_ADI_MSK(0x00003000,uint32_t))  /* Peripheral Bus Width */
-#define ENUM_DMA_STAT_PBUS01                 (_ADI_MSK(0x00000000,uint32_t))  /* PBWID: 1 Byte */
-#define ENUM_DMA_STAT_PBUS02                 (_ADI_MSK(0x00001000,uint32_t))  /* PBWID: 2 Bytes */
-#define ENUM_DMA_STAT_PBUS04                 (_ADI_MSK(0x00002000,uint32_t))  /* PBWID: 4 Bytes */
-#define ENUM_DMA_STAT_PBUS08                 (_ADI_MSK(0x00003000,uint32_t))  /* PBWID: 8 Bytes */
-
-#define BITM_DMA_STAT_RUN                    (_ADI_MSK(0x00000700,uint32_t))  /* Run Status */
-#define ENUM_DMA_STAT_STOPPED                (_ADI_MSK(0x00000000,uint32_t))  /* RUN: Idle/Stop State */
-#define ENUM_DMA_STAT_DSCFETCH               (_ADI_MSK(0x00000100,uint32_t))  /* RUN: Descriptor Fetch */
-#define ENUM_DMA_STAT_DATAXFER               (_ADI_MSK(0x00000200,uint32_t))  /* RUN: Data Transfer */
-#define ENUM_DMA_STAT_TRGWAIT                (_ADI_MSK(0x00000300,uint32_t))  /* RUN: Waiting for Trigger */
-#define ENUM_DMA_STAT_ACKWAIT                (_ADI_MSK(0x00000400,uint32_t))  /* RUN: Waiting for Write ACK/FIFO Drain to Peripheral */
-
-#define BITM_DMA_STAT_ERRC                   (_ADI_MSK(0x00000070,uint32_t))  /* Error Cause */
-#define ENUM_DMA_STAT_CFGERR                 (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Configuration Error */
-#define ENUM_DMA_STAT_ILLWRERR               (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Illegal Write Occurred While Channel Running */
-#define ENUM_DMA_STAT_ALGNERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: Address Alignment Error */
-#define ENUM_DMA_STAT_MEMERR                 (_ADI_MSK(0x00000030,uint32_t))  /* ERRC: Memory Access/Fabric Error */
-#define ENUM_DMA_STAT_TRGOVERR               (_ADI_MSK(0x00000050,uint32_t))  /* ERRC: Trigger Overrun */
-#define ENUM_DMA_STAT_BWMONERR               (_ADI_MSK(0x00000060,uint32_t))  /* ERRC: Bandwidth Monitor Error */
-
-#define BITM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* Peripheral Interrupt Request */
-#define ENUM_DMA_STAT_NO_PIRQ                (_ADI_MSK(0x00000000,uint32_t))  /* PIRQ: No Interrupt */
-#define ENUM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* PIRQ: Interrupt Signaled by Peripheral */
-
-#define BITM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Interrupt */
-#define ENUM_DMA_STAT_NO_IRQERR              (_ADI_MSK(0x00000000,uint32_t))  /* IRQERR: No Error */
-#define ENUM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* IRQERR: Error Occurred */
-
-#define BITM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* Work Unit/Row Done Interrupt */
-#define ENUM_DMA_STAT_NO_IRQ                 (_ADI_MSK(0x00000000,uint32_t))  /* IRQDONE: Inactive */
-#define ENUM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* IRQDONE: Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_VALUE                 0                               /* Bandwidth Limit Count */
-#define BITM_DMA_BWLCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT_CUR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_CUR_VALUE             0                               /* Bandwidth Limit Count Current */
-#define BITM_DMA_BWLCNT_CUR_VALUE            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count Current */
-
-/* ==================================================
-        ACM Registers
-   ================================================== */
-
-/* =========================
-        ACM0
-   ========================= */
-#define REG_ACM0_CTL                    0xFFC45000         /* ACM0 ACM Control Register */
-#define REG_ACM0_TC0                    0xFFC45004         /* ACM0 ACM Timing Configuration 0 Register */
-#define REG_ACM0_TC1                    0xFFC45008         /* ACM0 ACM Timing Configuration 1 Register */
-#define REG_ACM0_STAT                   0xFFC4500C         /* ACM0 ACM Status Register */
-#define REG_ACM0_EVSTAT                 0xFFC45010         /* ACM0 ACM Event Status Register */
-#define REG_ACM0_EVMSK                  0xFFC45014         /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define REG_ACM0_MEVSTAT                0xFFC45018         /* ACM0 ACM Missed Event Status Register */
-#define REG_ACM0_MEVMSK                 0xFFC4501C         /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define REG_ACM0_EVCTL0                 0xFFC45020         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL1                 0xFFC45024         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL2                 0xFFC45028         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL3                 0xFFC4502C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL4                 0xFFC45030         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL5                 0xFFC45034         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL6                 0xFFC45038         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL7                 0xFFC4503C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL8                 0xFFC45040         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL9                 0xFFC45044         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL10                0xFFC45048         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL11                0xFFC4504C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL12                0xFFC45050         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL13                0xFFC45054         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL14                0xFFC45058         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL15                0xFFC4505C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVTIME0                0xFFC45060         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME1                0xFFC45064         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME2                0xFFC45068         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME3                0xFFC4506C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME4                0xFFC45070         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME5                0xFFC45074         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME6                0xFFC45078         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME7                0xFFC4507C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME8                0xFFC45080         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME9                0xFFC45084         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME10               0xFFC45088         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME11               0xFFC4508C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME12               0xFFC45090         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME13               0xFFC45094         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME14               0xFFC45098         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME15               0xFFC4509C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVORD0                 0xFFC450A0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD1                 0xFFC450A4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD2                 0xFFC450A8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD3                 0xFFC450AC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD4                 0xFFC450B0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD5                 0xFFC450B4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD6                 0xFFC450B8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD7                 0xFFC450BC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD8                 0xFFC450C0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD9                 0xFFC450C4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD10                0xFFC450C8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD11                0xFFC450CC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD12                0xFFC450D0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD13                0xFFC450D4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD14                0xFFC450D8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD15                0xFFC450DC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_TMR0                   0xFFC450E8         /* ACM0 ACM Timer 0 Register */
-#define REG_ACM0_TMR1                   0xFFC450EC         /* ACM0 ACM Timer 1 Register */
-
-/* =========================
-        ACM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_CTL_EPS                     15                               /* External Peripheral Select */
-#define BITP_ACM_CTL_OTSEL                   14                               /* Trigger Select for Order Register Reset */
-#define BITP_ACM_CTL_AOREN                   13                               /* Automatic Order Reset Enable */
-#define BITP_ACM_CTL_ORST                    12                               /* Order Register Reset Bit */
-#define BITP_ACM_CTL_CLKMOD                  11                               /* ADC Clock Mode */
-#define BITP_ACM_CTL_CLKPOL                  10                               /* ADC_CLK Polarity */
-#define BITP_ACM_CTL_CSPOL                    9                               /* CS Polarity */
-#define BITP_ACM_CTL_TRGPOL1                  8                               /* Trigger Polarity for Timer1 Triggers */
-#define BITP_ACM_CTL_TRGPOL0                  7                               /* Trigger Polarity for Timer0 Triggers */
-#define BITP_ACM_CTL_TRGSEL1                  5                               /* Trigger Select 1 */
-#define BITP_ACM_CTL_TRGSEL0                  3                               /* Trigger Select 0 */
-#define BITP_ACM_CTL_TMR1EN                   2                               /* Enable ACM Timer1 */
-#define BITP_ACM_CTL_TMR0EN                   1                               /* Enable ACM Timer0 */
-#define BITP_ACM_CTL_EN                       0                               /* ACM Enable */
-#define BITM_ACM_CTL_EPS                     (_ADI_MSK(0x00008000,uint32_t))  /* External Peripheral Select */
-#define BITM_ACM_CTL_OTSEL                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Select for Order Register Reset */
-#define BITM_ACM_CTL_AOREN                   (_ADI_MSK(0x00002000,uint32_t))  /* Automatic Order Reset Enable */
-#define BITM_ACM_CTL_ORST                    (_ADI_MSK(0x00001000,uint32_t))  /* Order Register Reset Bit */
-#define BITM_ACM_CTL_CLKMOD                  (_ADI_MSK(0x00000800,uint32_t))  /* ADC Clock Mode */
-#define BITM_ACM_CTL_CLKPOL                  (_ADI_MSK(0x00000400,uint32_t))  /* ADC_CLK Polarity */
-#define BITM_ACM_CTL_CSPOL                   (_ADI_MSK(0x00000200,uint32_t))  /* CS Polarity */
-#define BITM_ACM_CTL_TRGPOL1                 (_ADI_MSK(0x00000100,uint32_t))  /* Trigger Polarity for Timer1 Triggers */
-#define BITM_ACM_CTL_TRGPOL0                 (_ADI_MSK(0x00000080,uint32_t))  /* Trigger Polarity for Timer0 Triggers */
-#define BITM_ACM_CTL_TRGSEL1                 (_ADI_MSK(0x00000060,uint32_t))  /* Trigger Select 1 */
-#define BITM_ACM_CTL_TRGSEL0                 (_ADI_MSK(0x00000018,uint32_t))  /* Trigger Select 0 */
-#define BITM_ACM_CTL_TMR1EN                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable ACM Timer1 */
-#define BITM_ACM_CTL_TMR0EN                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable ACM Timer0 */
-#define BITM_ACM_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* ACM Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC0_SC                      16                               /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITP_ACM_TC0_CKDIV                    0                               /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-#define BITM_ACM_TC0_SC                      (_ADI_MSK(0x0FFF0000,uint32_t))  /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITM_ACM_TC0_CKDIV                   (_ADI_MSK(0x000000FF,uint32_t))  /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC1_ZC                      12                               /* Zero Cycle - ADC Control zero duration */
-#define BITP_ACM_TC1_HC                       8                               /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITP_ACM_TC1_CSW                      0                               /* CS Width. Active duration of CS in ACLK cycles */
-#define BITM_ACM_TC1_ZC                      (_ADI_MSK(0x0000F000,uint32_t))  /* Zero Cycle - ADC Control zero duration */
-#define BITM_ACM_TC1_HC                      (_ADI_MSK(0x00000F00,uint32_t))  /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITM_ACM_TC1_CSW                     (_ADI_MSK(0x000000FF,uint32_t))  /* CS Width. Active duration of CS in ACLK cycles */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_STAT_CEVNT                   4                               /* Current Event. */
-#define BITP_ACM_STAT_ECOM1                   3                               /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_ECOM0                   2                               /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_EMISS                   1                               /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITP_ACM_STAT_BSY                     0                               /* ACM Busy */
-#define BITM_ACM_STAT_CEVNT                  (_ADI_MSK(0x000000F0,uint32_t))  /* Current Event. */
-#define BITM_ACM_STAT_ECOM1                  (_ADI_MSK(0x00000008,uint32_t))  /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_ECOM0                  (_ADI_MSK(0x00000004,uint32_t))  /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_EMISS                  (_ADI_MSK(0x00000002,uint32_t))  /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITM_ACM_STAT_BSY                    (_ADI_MSK(0x00000001,uint32_t))  /* ACM Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVSTAT_ECOM1S               17                               /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_ECOM0S               16                               /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_EV15                 15                               /* Event15 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV14                 14                               /* Event14 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV13                 13                               /* Event13 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV12                 12                               /* Event12 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV11                 11                               /* Event11 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV10                 10                               /* Event10 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV9                   9                               /* Event9 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV8                   8                               /* Event8 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV7                   7                               /* Event7 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV6                   6                               /* Event6 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV5                   5                               /* Event5 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV4                   4                               /* Event4 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV3                   3                               /* Event3 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV2                   2                               /* Event2 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV1                   1                               /* Event1 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV0                   0                               /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-#define BITM_ACM_EVSTAT_ECOM1S               (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_ECOM0S               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVMSK_IECOM1                17                               /* Timer1 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_IECOM0                16                               /* Timer0 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV15                  15                               /* Event15 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV14                  14                               /* Event14 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV13                  13                               /* Event13 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV12                  12                               /* Event12 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV11                  11                               /* Event11 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV10                  10                               /* Event10 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV9                    9                               /* Event9 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV8                    8                               /* Event8 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV7                    7                               /* Event7 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV6                    6                               /* Event6 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV5                    5                               /* Event5 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV4                    4                               /* Event4 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV3                    3                               /* Event3 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV2                    2                               /* Event2 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV1                    1                               /* Event1 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV0                    0                               /* Event0 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM1                (_ADI_MSK(0x00020000,uint32_t))  /* Timer1 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM0                (_ADI_MSK(0x00010000,uint32_t))  /* Timer0 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV15                  (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV14                  (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV13                  (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV12                  (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV11                  (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV10                  (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV9                   (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV8                   (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV7                   (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV6                   (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV5                   (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV4                   (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV3                   (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV2                   (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV1                   (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV0                   (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVSTAT_EV15                15                               /* Event15 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV14                14                               /* Event14 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV13                13                               /* Event13 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV12                12                               /* Event12 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV11                11                               /* Event11 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV10                10                               /* Event10 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV9                  9                               /* Event9 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV8                  8                               /* Event8 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV7                  7                               /* Event7 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV6                  6                               /* Event6 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV5                  5                               /* Event5 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV4                  4                               /* Event4 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV3                  3                               /* Event3 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV2                  2                               /* Event2 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV1                  1                               /* Event1 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV0                  0                               /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-#define BITM_ACM_MEVSTAT_EV15                (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV14                (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV13                (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV12                (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV11                (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV10                (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV9                 (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV8                 (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV7                 (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV6                 (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV5                 (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV4                 (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV3                 (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV2                 (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV1                 (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV0                 (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVMSK                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVMSK_EV15                 15                               /* Event15 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV14                 14                               /* Event14 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV13                 13                               /* Event13 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV12                 12                               /* Event12 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV11                 11                               /* Event11 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV10                 10                               /* Event10 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV9                   9                               /* Event9 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV8                   8                               /* Event8 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV7                   7                               /* Event7 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV6                   6                               /* Event6 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV5                   5                               /* Event5 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV4                   4                               /* Event4 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV3                   3                               /* Event3 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV2                   2                               /* Event2 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV1                   1                               /* Event1 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV0                   0                               /* Event0 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVCTL_EPF                    1                               /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITP_ACM_EVCTL_ENAEV                  0                               /* Enable Event */
-#define BITM_ACM_EVCTL_EPF                   (_ADI_MSK(0x0000003E,uint32_t))  /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITM_ACM_EVCTL_ENAEV                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Event */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVORD                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVORD_EVSTAT                17                               /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITP_ACM_EVORD_MEVSTAT               16                               /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITP_ACM_EVORD_ORD                    0                               /* Order of Event Completion */
-#define BITM_ACM_EVORD_EVSTAT                (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITM_ACM_EVORD_MEVSTAT               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITM_ACM_EVORD_ORD                   (_ADI_MSK(0x000000FF,uint32_t))  /* Order of Event Completion */
-
-/* ==================================================
-        DDR Registers
-   ================================================== */
-
-/* =========================
-        DMC0
-   ========================= */
-#define REG_DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
-#define REG_DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
-#define REG_DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Control Register */
-#define REG_DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
-#define REG_DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask Register */
-#define REG_DMC0_CFG                    0xFFC80040         /* DMC0 Configuration Register */
-#define REG_DMC0_TR0                    0xFFC80044         /* DMC0 Timing 0 Register */
-#define REG_DMC0_TR1                    0xFFC80048         /* DMC0 Timing 1 Register */
-#define REG_DMC0_TR2                    0xFFC8004C         /* DMC0 Timing 2 Register */
-#define REG_DMC0_MSK                    0xFFC8005C         /* DMC0 Mask (Mode Register Shadow) Register */
-#define REG_DMC0_MR                     0xFFC80060         /* DMC0 Shadow MR Register */
-#define REG_DMC0_EMR1                   0xFFC80064         /* DMC0 Shadow EMR1 Register */
-#define REG_DMC0_EMR2                   0xFFC80068         /* DMC0 Shadow EMR2 Register */
-#define REG_DMC0_EMR3                   0xFFC8006C         /* DMC0 Shadow EMR3 Register */
-#define REG_DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
-#define REG_DMC0_PHY_CTL0               0xFFC80090         /* DMC0 PHY Control 0 Register */
-#define REG_DMC0_PHY_CTL1               0xFFC80094         /* DMC0 PHY Control 1 Register */
-#define REG_DMC0_PHY_CTL2               0xFFC80098         /* DMC0 PHY Control 2 Register */
-#define REG_DMC0_PHY_CTL3               0xFFC8009C         /* DMC0 PHY Control 3 Register */
-#define REG_DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register */
-
-/* =========================
-        DMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CTL_DLLCAL                  13                               /* DLL Calibration Start */
-#define BITP_DMC_CTL_PPREF                   12                               /* Postpone Refresh */
-#define BITP_DMC_CTL_RDTOWR                   9                               /* Read-to-Write Cycle */
-#define BITP_DMC_CTL_ADDRMODE                 8                               /* Addressing (Page/Bank) Mode */
-#define BITP_DMC_CTL_PREC                     6                               /* Precharge */
-#define BITP_DMC_CTL_DPDREQ                   5                               /* Deep Power Down Request */
-#define BITP_DMC_CTL_PDREQ                    4                               /* Power Down Request */
-#define BITP_DMC_CTL_SRREQ                    3                               /* Self Refresh Request */
-#define BITP_DMC_CTL_INIT                     2                               /* Initialize DRAM Start */
-#define BITP_DMC_CTL_LPDDR                    1                               /* Low Power DDR Mode */
-#define BITM_DMC_CTL_DLLCAL                  (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Start */
-#define BITM_DMC_CTL_PPREF                   (_ADI_MSK(0x00001000,uint32_t))  /* Postpone Refresh */
-
-#define BITM_DMC_CTL_RDTOWR                  (_ADI_MSK(0x00000E00,uint32_t))  /* Read-to-Write Cycle */
-#define ENUM_DMC_CTL_RDTOWR0                 (_ADI_MSK(0x00000000,uint32_t))  /* RDTOWR: 0 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR1                 (_ADI_MSK(0x00000200,uint32_t))  /* RDTOWR: 1 Cycle Added */
-#define ENUM_DMC_CTL_RDTOWR2                 (_ADI_MSK(0x00000400,uint32_t))  /* RDTOWR: 2 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR3                 (_ADI_MSK(0x00000600,uint32_t))  /* RDTOWR: 3 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR4                 (_ADI_MSK(0x00000800,uint32_t))  /* RDTOWR: 4 Cycles Added */
-#define BITM_DMC_CTL_ADDRMODE                (_ADI_MSK(0x00000100,uint32_t))  /* Addressing (Page/Bank) Mode */
-#define BITM_DMC_CTL_PREC                    (_ADI_MSK(0x00000040,uint32_t))  /* Precharge */
-#define BITM_DMC_CTL_DPDREQ                  (_ADI_MSK(0x00000020,uint32_t))  /* Deep Power Down Request */
-#define BITM_DMC_CTL_PDREQ                   (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Request */
-#define BITM_DMC_CTL_SRREQ                   (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Request */
-#define BITM_DMC_CTL_INIT                    (_ADI_MSK(0x00000004,uint32_t))  /* Initialize DRAM Start */
-#define BITM_DMC_CTL_LPDDR                   (_ADI_MSK(0x00000002,uint32_t))  /* Low Power DDR Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_STAT_PHYRDPHASE             20                               /* PHY Read Phase */
-#define BITP_DMC_STAT_PENDREF                16                               /* Pending Refresh */
-#define BITP_DMC_STAT_DLLCALDONE             13                               /* DLL Calibration Done */
-#define BITP_DMC_STAT_DPDACK                  5                               /* Deep Powerdown Acknowledge */
-#define BITP_DMC_STAT_PDACK                   4                               /* Power Down Acknowledge */
-#define BITP_DMC_STAT_SRACK                   3                               /* Self Refresh Acknowledge */
-#define BITP_DMC_STAT_MEMINITDONE             1                               /* Memory Initialization Done */
-#define BITP_DMC_STAT_IDLE                    0                               /* Idle State */
-#define BITM_DMC_STAT_PHYRDPHASE             (_ADI_MSK(0x00F00000,uint32_t))  /* PHY Read Phase */
-#define BITM_DMC_STAT_PENDREF                (_ADI_MSK(0x000F0000,uint32_t))  /* Pending Refresh */
-#define BITM_DMC_STAT_DLLCALDONE             (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Done */
-#define BITM_DMC_STAT_DPDACK                 (_ADI_MSK(0x00000020,uint32_t))  /* Deep Powerdown Acknowledge */
-#define BITM_DMC_STAT_PDACK                  (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Acknowledge */
-#define BITM_DMC_STAT_SRACK                  (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Acknowledge */
-#define BITM_DMC_STAT_MEMINITDONE            (_ADI_MSK(0x00000002,uint32_t))  /* Memory Initialization Done */
-#define BITM_DMC_STAT_IDLE                   (_ADI_MSK(0x00000001,uint32_t))  /* Idle State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EFFCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EFFCTL_IDLECYC              20                               /* Idle Cycle */
-#define BITP_DMC_EFFCTL_NUMREF               16                               /* Number of Refresh Commands */
-#define BITP_DMC_EFFCTL_PRECBANK7            15                               /* Precharge Bank 7 */
-#define BITP_DMC_EFFCTL_PRECBANK6            14                               /* Precharge Bank 6 */
-#define BITP_DMC_EFFCTL_PRECBANK5            13                               /* Precharge Bank 5 */
-#define BITP_DMC_EFFCTL_PRECBANK4            12                               /* Precharge Bank 4 */
-#define BITP_DMC_EFFCTL_PRECBANK3            11                               /* Precharge Bank 3 */
-#define BITP_DMC_EFFCTL_PRECBANK2            10                               /* Precharge Bank 2 */
-#define BITP_DMC_EFFCTL_PRECBANK1             9                               /* Precharge Bank 1 */
-#define BITP_DMC_EFFCTL_PRECBANK0             8                               /* Precharge Bank 0 */
-#define BITP_DMC_EFFCTL_WAITWRDATA            7                               /* Wait in Write Data Snapshot */
-#define BITP_DMC_EFFCTL_FULLWRDATA            6                               /* Wait for Full Write Data */
-#define BITM_DMC_EFFCTL_IDLECYC              (_ADI_MSK(0x00F00000,uint32_t))  /* Idle Cycle */
-#define BITM_DMC_EFFCTL_NUMREF               (_ADI_MSK(0x000F0000,uint32_t))  /* Number of Refresh Commands */
-#define BITM_DMC_EFFCTL_PRECBANK7            (_ADI_MSK(0x00008000,uint32_t))  /* Precharge Bank 7 */
-#define BITM_DMC_EFFCTL_PRECBANK6            (_ADI_MSK(0x00004000,uint32_t))  /* Precharge Bank 6 */
-#define BITM_DMC_EFFCTL_PRECBANK5            (_ADI_MSK(0x00002000,uint32_t))  /* Precharge Bank 5 */
-#define BITM_DMC_EFFCTL_PRECBANK4            (_ADI_MSK(0x00001000,uint32_t))  /* Precharge Bank 4 */
-#define BITM_DMC_EFFCTL_PRECBANK3            (_ADI_MSK(0x00000800,uint32_t))  /* Precharge Bank 3 */
-#define BITM_DMC_EFFCTL_PRECBANK2            (_ADI_MSK(0x00000400,uint32_t))  /* Precharge Bank 2 */
-#define BITM_DMC_EFFCTL_PRECBANK1            (_ADI_MSK(0x00000200,uint32_t))  /* Precharge Bank 1 */
-#define BITM_DMC_EFFCTL_PRECBANK0            (_ADI_MSK(0x00000100,uint32_t))  /* Precharge Bank 0 */
-#define BITM_DMC_EFFCTL_WAITWRDATA           (_ADI_MSK(0x00000080,uint32_t))  /* Wait in Write Data Snapshot */
-#define BITM_DMC_EFFCTL_FULLWRDATA           (_ADI_MSK(0x00000040,uint32_t))  /* Wait for Full Write Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIO                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIO_ID2                    16                               /* ID2 Requiring Elevated Priority */
-#define BITP_DMC_PRIO_ID1                     0                               /* ID1 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID2                    (_ADI_MSK(0xFFFF0000,uint32_t))  /* ID2 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID1                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* ID1 Requiring Elevated Priority */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIOMSK                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIOMSK_ID2MSK              16                               /* Mask for ID2 */
-#define BITP_DMC_PRIOMSK_ID1MSK               0                               /* Mask for ID1 */
-#define BITM_DMC_PRIOMSK_ID2MSK              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Mask for ID2 */
-#define BITM_DMC_PRIOMSK_ID1MSK              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Mask for ID1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CFG_EXTBANK                 12                               /* External Banks */
-#define BITP_DMC_CFG_SDRSIZE                  8                               /* SDRAM Size */
-#define BITP_DMC_CFG_SDRWID                   4                               /* SDRAM Width */
-#define BITP_DMC_CFG_IFWID                    0                               /* Interface Width */
-
-#define BITM_DMC_CFG_EXTBANK                 (_ADI_MSK(0x0000F000,uint32_t))  /* External Banks */
-#define ENUM_DMC_CFG_EXTBANK1                (_ADI_MSK(0x00000000,uint32_t))  /* EXTBANK: 1 External Bank */
-
-#define BITM_DMC_CFG_SDRSIZE                 (_ADI_MSK(0x00000F00,uint32_t))  /* SDRAM Size */
-#define ENUM_DMC_CFG_SDRSIZE64               (_ADI_MSK(0x00000000,uint32_t))  /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE128              (_ADI_MSK(0x00000100,uint32_t))  /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE256              (_ADI_MSK(0x00000200,uint32_t))  /* SDRSIZE: 256M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE512              (_ADI_MSK(0x00000300,uint32_t))  /* SDRSIZE: 512M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE1G               (_ADI_MSK(0x00000400,uint32_t))  /* SDRSIZE: 1G Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE2G               (_ADI_MSK(0x00000500,uint32_t))  /* SDRSIZE: 2G Bit SDRAM */
-
-#define BITM_DMC_CFG_SDRWID                  (_ADI_MSK(0x000000F0,uint32_t))  /* SDRAM Width */
-#define ENUM_DMC_CFG_SDRWID16                (_ADI_MSK(0x00000020,uint32_t))  /* SDRWID: 16-Bit Wide SDRAM */
-
-#define BITM_DMC_CFG_IFWID                   (_ADI_MSK(0x0000000F,uint32_t))  /* Interface Width */
-#define ENUM_DMC_CFG_IFWID16                 (_ADI_MSK(0x00000002,uint32_t))  /* IFWID: 16-Bit Wide Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR0_TMRD                    28                               /* Timing Mode Register Delay */
-#define BITP_DMC_TR0_TRC                     20                               /* Timing Row Cycle */
-#define BITP_DMC_TR0_TRAS                    12                               /* Timing Row Active Time */
-#define BITP_DMC_TR0_TRP                      8                               /* Timing RAS Precharge. */
-#define BITP_DMC_TR0_TWTR                     4                               /* Timing Write to Read */
-#define BITP_DMC_TR0_TRCD                     0                               /* Timing RAS to CAS Delay */
-#define BITM_DMC_TR0_TMRD                    (_ADI_MSK(0xF0000000,uint32_t))  /* Timing Mode Register Delay */
-#define BITM_DMC_TR0_TRC                     (_ADI_MSK(0x03F00000,uint32_t))  /* Timing Row Cycle */
-#define BITM_DMC_TR0_TRAS                    (_ADI_MSK(0x0001F000,uint32_t))  /* Timing Row Active Time */
-#define BITM_DMC_TR0_TRP                     (_ADI_MSK(0x00000F00,uint32_t))  /* Timing RAS Precharge. */
-#define BITM_DMC_TR0_TWTR                    (_ADI_MSK(0x000000F0,uint32_t))  /* Timing Write to Read */
-#define BITM_DMC_TR0_TRCD                    (_ADI_MSK(0x0000000F,uint32_t))  /* Timing RAS to CAS Delay */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR1_TRRD                    28                               /* Timing Read-Read Delay */
-#define BITP_DMC_TR1_TRFC                    16                               /* Timing Refresh-to-Command */
-#define BITP_DMC_TR1_TREF                     0                               /* Timing Refresh Interval */
-#define BITM_DMC_TR1_TRRD                    (_ADI_MSK(0x70000000,uint32_t))  /* Timing Read-Read Delay */
-#define BITM_DMC_TR1_TRFC                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Timing Refresh-to-Command */
-#define BITM_DMC_TR1_TREF                    (_ADI_MSK(0x00003FFF,uint32_t))  /* Timing Refresh Interval */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR2_TCKE                    20                               /* Timing Clock Enable */
-#define BITP_DMC_TR2_TXP                     16                               /* Timing Exit Powerdown */
-#define BITP_DMC_TR2_TWR                     12                               /* Timing Write Recovery */
-#define BITP_DMC_TR2_TRTP                     8                               /* Timing Read-to-Precharge */
-#define BITP_DMC_TR2_TFAW                     0                               /* Timing Four-Activated-Window */
-#define BITM_DMC_TR2_TCKE                    (_ADI_MSK(0x00F00000,uint32_t))  /* Timing Clock Enable */
-#define BITM_DMC_TR2_TXP                     (_ADI_MSK(0x000F0000,uint32_t))  /* Timing Exit Powerdown */
-#define BITM_DMC_TR2_TWR                     (_ADI_MSK(0x0000F000,uint32_t))  /* Timing Write Recovery */
-#define BITM_DMC_TR2_TRTP                    (_ADI_MSK(0x00000F00,uint32_t))  /* Timing Read-to-Precharge */
-#define BITM_DMC_TR2_TFAW                    (_ADI_MSK(0x0000001F,uint32_t))  /* Timing Four-Activated-Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MSK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MSK_EMR3                    11                               /* Shadow EMR3 Unmask */
-#define BITP_DMC_MSK_EMR2                    10                               /* Shadow EMR2 Unmask */
-#define BITP_DMC_MSK_EMR1                     9                               /* Shadow EMR1 Unmask */
-#define BITP_DMC_MSK_MR                       8                               /* Shadow MR Unmask */
-#define BITM_DMC_MSK_EMR3                    (_ADI_MSK(0x00000800,uint32_t))  /* Shadow EMR3 Unmask */
-#define BITM_DMC_MSK_EMR2                    (_ADI_MSK(0x00000400,uint32_t))  /* Shadow EMR2 Unmask */
-#define BITM_DMC_MSK_EMR1                    (_ADI_MSK(0x00000200,uint32_t))  /* Shadow EMR1 Unmask */
-#define BITM_DMC_MSK_MR                      (_ADI_MSK(0x00000100,uint32_t))  /* Shadow MR Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MR                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MR_PD                       12                               /* Active Powerdown Mode */
-#define BITP_DMC_MR_WRRECOV                   9                               /* Write Recovery */
-#define BITP_DMC_MR_DLLRST                    8                               /* DLL Reset */
-#define BITP_DMC_MR_CL                        4                               /* CAS Latency */
-#define BITP_DMC_MR_BLEN                      0                               /* Burst Length */
-#define BITM_DMC_MR_PD                       (_ADI_MSK(0x00001000,uint32_t))  /* Active Powerdown Mode */
-#define BITM_DMC_MR_WRRECOV                  (_ADI_MSK(0x00000E00,uint32_t))  /* Write Recovery */
-#define BITM_DMC_MR_DLLRST                   (_ADI_MSK(0x00000100,uint32_t))  /* DLL Reset */
-
-#define BITM_DMC_MR_CL                       (_ADI_MSK(0x00000070,uint32_t))  /* CAS Latency */
-#define ENUM_DMC_MR_CL2                      (_ADI_MSK(0x00000020,uint32_t))  /* CL: 2 clock cycle latency */
-#define ENUM_DMC_MR_CL3                      (_ADI_MSK(0x00000030,uint32_t))  /* CL: 3 clock cycle latency */
-#define ENUM_DMC_MR_CL4                      (_ADI_MSK(0x00000040,uint32_t))  /* CL: 4 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL5                      (_ADI_MSK(0x00000050,uint32_t))  /* CL: 5 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL6                      (_ADI_MSK(0x00000060,uint32_t))  /* CL: 6 clock cycle latency (DDR2) */
-
-#define BITM_DMC_MR_BLEN                     (_ADI_MSK(0x00000007,uint32_t))  /* Burst Length */
-#define ENUM_DMC_MR_BLEN4                    (_ADI_MSK(0x00000002,uint32_t))  /* BLEN: 4-Bit Burst Length */
-#define ENUM_DMC_MR_BLEN8                    (_ADI_MSK(0x00000003,uint32_t))  /* BLEN: 8-Bit Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR1_QOFF                   12                               /* Output Buffer Enable */
-#define BITP_DMC_EMR1_DQS                    10                               /* DQS Enable */
-#define BITP_DMC_EMR1_RTT1                    6                               /* Termination Resistance 1 */
-#define BITP_DMC_EMR1_AL                      3                               /* Additive Latency */
-#define BITP_DMC_EMR1_RTT0                    2                               /* Termination Resistance 0. */
-#define BITP_DMC_EMR1_DIC                     1                               /* Output Driver Impedance Control */
-#define BITP_DMC_EMR1_DLLEN                   0                               /* DLL Enable */
-#define BITM_DMC_EMR1_QOFF                   (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Enable */
-#define BITM_DMC_EMR1_DQS                    (_ADI_MSK(0x00000400,uint32_t))  /* DQS Enable */
-
-#define BITM_DMC_EMR1_RTT1                   (_ADI_MSK(0x00000040,uint32_t))  /* Termination Resistance 1 */
-#define ENUM_DMC_EMR1_RTT1_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT1: Disable RTT1 */
-#define ENUM_DMC_EMR1_RTT1_1                 (_ADI_MSK(0x00000040,uint32_t))  /* RTT1: Enable RTT1 */
-#define BITM_DMC_EMR1_AL                     (_ADI_MSK(0x00000038,uint32_t))  /* Additive Latency */
-
-#define BITM_DMC_EMR1_RTT0                   (_ADI_MSK(0x00000004,uint32_t))  /* Termination Resistance 0. */
-#define ENUM_DMC_EMR1_RTT0_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT0: Disable RTT0 */
-#define ENUM_DMC_EMR1_RTT0_1                 (_ADI_MSK(0x00000004,uint32_t))  /* RTT0: Enable RTT0 */
-#define BITM_DMC_EMR1_DIC                    (_ADI_MSK(0x00000002,uint32_t))  /* Output Driver Impedance Control */
-#define BITM_DMC_EMR1_DLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* DLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR2_SRF                     7                               /* High Temp. Self Refresh */
-#define BITP_DMC_EMR2_DS                      5                               /* Drive Strength */
-#define BITP_DMC_EMR2_TCSR                    3                               /* Temp. Comp. Self Refresh */
-#define BITP_DMC_EMR2_PASR                    0                               /* Partial Array Self Refresh */
-#define BITM_DMC_EMR2_SRF                    (_ADI_MSK(0x00000080,uint32_t))  /* High Temp. Self Refresh */
-#define BITM_DMC_EMR2_DS                     (_ADI_MSK(0x00000060,uint32_t))  /* Drive Strength */
-#define BITM_DMC_EMR2_TCSR                   (_ADI_MSK(0x00000018,uint32_t))  /* Temp. Comp. Self Refresh */
-#define BITM_DMC_EMR2_PASR                   (_ADI_MSK(0x00000007,uint32_t))  /* Partial Array Self Refresh */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_DLLCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_DLLCTL_DATACYC               8                               /* Data Cycles */
-#define BITP_DMC_DLLCTL_DLLCALRDCNT           0                               /* DLL Calibration RD Count */
-
-#define BITM_DMC_DLLCTL_DATACYC              (_ADI_MSK(0x00000F00,uint32_t))  /* Data Cycles */
-#define ENUM_DMC_DLLCTL_DATACYC2             (_ADI_MSK(0x00000200,uint32_t))  /* DATACYC: 2 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC3             (_ADI_MSK(0x00000300,uint32_t))  /* DATACYC: 3 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC4             (_ADI_MSK(0x00000400,uint32_t))  /* DATACYC: 4 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC5             (_ADI_MSK(0x00000500,uint32_t))  /* DATACYC: 5 Clock Cycles Latency */
-#define BITM_DMC_DLLCTL_DLLCALRDCNT          (_ADI_MSK(0x000000FF,uint32_t))  /* DLL Calibration RD Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL1                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL1_CONTODTVAL         19                               /* Select ODT value on controller */
-
-#define BITM_DMC_PHY_CTL1_CONTODTVAL         (_ADI_MSK(0x00080000,uint32_t))  /* Select ODT value on controller */
-#define ENUM_DMC_PHY_CTL1_ODT_75             (_ADI_MSK(0x00000000,uint32_t))  /* CONTODTVAL: 75 Ohms Termination */
-#define ENUM_DMC_PHY_CTL1_ODT_150            (_ADI_MSK(0x00080000,uint32_t))  /* CONTODTVAL: 150 Ohms Termination */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL3                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL3_OFST1              26                               /* Offset Parameter 1 */
-#define BITP_DMC_PHY_CTL3_OFST0              24                               /* Offset Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQS           10                               /* Enables controller ODT on read of DQS */
-#define BITP_DMC_PHY_CTL3_TMG1                7                               /* Timing Parameter 1 */
-#define BITP_DMC_PHY_CTL3_TMG0                6                               /* Timing Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQ             2                               /* Enables controller ODT on read of DQ */
-#define BITM_DMC_PHY_CTL3_OFST1              (_ADI_MSK(0x04000000,uint32_t))  /* Offset Parameter 1 */
-#define BITM_DMC_PHY_CTL3_OFST0              (_ADI_MSK(0x01000000,uint32_t))  /* Offset Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQS           (_ADI_MSK(0x00000400,uint32_t))  /* Enables controller ODT on read of DQS */
-#define BITM_DMC_PHY_CTL3_TMG1               (_ADI_MSK(0x00000080,uint32_t))  /* Timing Parameter 1 */
-#define BITM_DMC_PHY_CTL3_TMG0               (_ADI_MSK(0x00000040,uint32_t))  /* Timing Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQ            (_ADI_MSK(0x00000004,uint32_t))  /* Enables controller ODT on read of DQ */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PADCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PADCTL_CKEOE                19                               /* CKE Output Enable */
-#define BITP_DMC_PADCTL_CKEPWD               18                               /* CKE pad receiver power down. */
-#define BITP_DMC_PADCTL_CKEODS               16                               /* CKE Output Drive Strength */
-#define BITP_DMC_PADCTL_CMDOE                15                               /* CMD Output Enable */
-#define BITP_DMC_PADCTL_CMDPWD               14                               /* CMD Powerdown */
-#define BITP_DMC_PADCTL_CMDODS               12                               /* CMD Output Drive Strength */
-#define BITP_DMC_PADCTL_CLKOE                11                               /* CLK Output Enable */
-#define BITP_DMC_PADCTL_CLKPWD               10                               /* CLK Powerdown */
-#define BITP_DMC_PADCTL_CLKODS                8                               /* Clock Output Drive Strength */
-#define BITP_DMC_PADCTL_DQSPWD                6                               /* DQ/DQS Powerdown */
-#define BITP_DMC_PADCTL_DQSODS                4                               /* DQS Output Drive Strength */
-#define BITP_DMC_PADCTL_DQPWD                 2                               /* DQ Powerdown. */
-#define BITP_DMC_PADCTL_DQODS                 0                               /* DQ Output Drive Strength */
-#define BITM_DMC_PADCTL_CKEOE                (_ADI_MSK(0x00080000,uint32_t))  /* CKE Output Enable */
-#define BITM_DMC_PADCTL_CKEPWD               (_ADI_MSK(0x00040000,uint32_t))  /* CKE pad receiver power down. */
-#define BITM_DMC_PADCTL_CKEODS               (_ADI_MSK(0x00030000,uint32_t))  /* CKE Output Drive Strength */
-#define BITM_DMC_PADCTL_CMDOE                (_ADI_MSK(0x00008000,uint32_t))  /* CMD Output Enable */
-#define BITM_DMC_PADCTL_CMDPWD               (_ADI_MSK(0x00004000,uint32_t))  /* CMD Powerdown */
-#define BITM_DMC_PADCTL_CMDODS               (_ADI_MSK(0x00003000,uint32_t))  /* CMD Output Drive Strength */
-#define BITM_DMC_PADCTL_CLKOE                (_ADI_MSK(0x00000800,uint32_t))  /* CLK Output Enable */
-#define BITM_DMC_PADCTL_CLKPWD               (_ADI_MSK(0x00000400,uint32_t))  /* CLK Powerdown */
-#define BITM_DMC_PADCTL_CLKODS               (_ADI_MSK(0x00000300,uint32_t))  /* Clock Output Drive Strength */
-#define BITM_DMC_PADCTL_DQSPWD               (_ADI_MSK(0x00000040,uint32_t))  /* DQ/DQS Powerdown */
-#define BITM_DMC_PADCTL_DQSODS               (_ADI_MSK(0x00000030,uint32_t))  /* DQS Output Drive Strength */
-#define BITM_DMC_PADCTL_DQPWD                (_ADI_MSK(0x00000004,uint32_t))  /* DQ Powerdown. */
-#define BITM_DMC_PADCTL_DQODS                (_ADI_MSK(0x00000003,uint32_t))  /* DQ Output Drive Strength */
-
-/* ==================================================
-        System Cross Bar Registers
-   ================================================== */
-
-/* =========================
-        SCB0
-   ========================= */
-#define REG_SCB0_ARBR0                  0xFFCA2408         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR1                  0xFFCA2428         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR2                  0xFFCA2448         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR3                  0xFFCA2468         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR4                  0xFFCA2488         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR5                  0xFFCA24A8         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBW0                  0xFFCA240C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW1                  0xFFCA242C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW2                  0xFFCA244C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW3                  0xFFCA246C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW4                  0xFFCA248C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW5                  0xFFCA24AC         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_SLAVES                 0xFFCA2FC0         /* SCB0 Slave Interfaces Number Register */
-#define REG_SCB0_MASTERS                0xFFCA2FC4         /* SCB0 Master Interfaces Number Register */
-
-/* =========================
-        SCB1
-   ========================= */
-#define REG_SCB1_ARBR0                  0xFFC42408         /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB1_ARBW0                  0xFFC4240C         /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB1_SLAVES                 0xFFC42FC0         /* SCB1 Slave Interfaces Number Register */
-#define REG_SCB1_MASTERS                0xFFC42FC4         /* SCB1 Master Interfaces Number Register */
-
-/* =========================
-        SCB2
-   ========================= */
-#define REG_SCB2_ARBR0                  0xFFC06408         /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB2_ARBW0                  0xFFC0640C         /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB2_SLAVES                 0xFFC06FC0         /* SCB2 Slave Interfaces Number Register */
-#define REG_SCB2_MASTERS                0xFFC06FC4         /* SCB2 Master Interfaces Number Register */
-
-/* =========================
-        SCB3
-   ========================= */
-#define REG_SCB3_ARBR0                  0xFFC08408         /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB3_ARBW0                  0xFFC0840C         /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB3_SLAVES                 0xFFC08FC0         /* SCB3 Slave Interfaces Number Register */
-#define REG_SCB3_MASTERS                0xFFC08FC4         /* SCB3 Master Interfaces Number Register */
-
-/* =========================
-        SCB4
-   ========================= */
-#define REG_SCB4_ARBR0                  0xFFC0A408         /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB4_ARBW0                  0xFFC0A40C         /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB4_SLAVES                 0xFFC0AFC0         /* SCB4 Slave Interfaces Number Register */
-#define REG_SCB4_MASTERS                0xFFC0AFC4         /* SCB4 Master Interfaces Number Register */
-
-/* =========================
-        SCB5
-   ========================= */
-#define REG_SCB5_ARBR0                  0xFFC0C408         /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB5_ARBW0                  0xFFC0C40C         /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB5_SLAVES                 0xFFC0CFC0         /* SCB5 Slave Interfaces Number Register */
-#define REG_SCB5_MASTERS                0xFFC0CFC4         /* SCB5 Master Interfaces Number Register */
-
-/* =========================
-        SCB6
-   ========================= */
-#define REG_SCB6_ARBR0                  0xFFC0E408         /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB6_ARBW0                  0xFFC0E40C         /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB6_SLAVES                 0xFFC0EFC0         /* SCB6 Slave Interfaces Number Register */
-#define REG_SCB6_MASTERS                0xFFC0EFC4         /* SCB6 Master Interfaces Number Register */
-
-/* =========================
-        SCB7
-   ========================= */
-#define REG_SCB7_ARBR0                  0xFFC11408         /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB7_ARBW0                  0xFFC1140C         /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB7_SLAVES                 0xFFC11FC0         /* SCB7 Slave Interfaces Number Register */
-#define REG_SCB7_MASTERS                0xFFC11FC4         /* SCB7 Master Interfaces Number Register */
-
-/* =========================
-        SCB8
-   ========================= */
-#define REG_SCB8_ARBR0                  0xFFC13408         /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB8_ARBW0                  0xFFC1340C         /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB8_SLAVES                 0xFFC13FC0         /* SCB8 Slave Interfaces Number Register */
-#define REG_SCB8_MASTERS                0xFFC13FC4         /* SCB8 Master Interfaces Number Register */
-
-/* =========================
-        SCB9
-   ========================= */
-#define REG_SCB9_ARBR0                  0xFFC15408         /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB9_ARBW0                  0xFFC1540C         /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB9_SLAVES                 0xFFC15FC0         /* SCB9 Slave Interfaces Number Register */
-#define REG_SCB9_MASTERS                0xFFC15FC4         /* SCB9 Master Interfaces Number Register */
-
-/* =========================
-        SCB10
-   ========================= */
-#define REG_SCB10_ARBR0                 0xFFCA1408         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR1                 0xFFCA1428         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR2                 0xFFCA1448         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBW0                 0xFFCA140C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW1                 0xFFCA142C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW2                 0xFFCA144C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_SLAVES                0xFFCA1FC0         /* SCB10 Slave Interfaces Number Register */
-#define REG_SCB10_MASTERS               0xFFCA1FC4         /* SCB10 Master Interfaces Number Register */
-
-/* =========================
-        SCB11
-   ========================= */
-#define REG_SCB11_ARBR0                 0xFFCA0408         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR1                 0xFFCA0428         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR2                 0xFFCA0448         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR3                 0xFFCA0468         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR4                 0xFFCA0488         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR5                 0xFFCA04A8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR6                 0xFFCA04C8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBW0                 0xFFCA040C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW1                 0xFFCA042C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW2                 0xFFCA044C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW3                 0xFFCA046C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW4                 0xFFCA048C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW5                 0xFFCA04AC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW6                 0xFFCA04CC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_SLAVES                0xFFCA0FC0         /* SCB11 Slave Interfaces Number Register */
-#define REG_SCB11_MASTERS               0xFFCA0FC4         /* SCB11 Master Interfaces Number Register */
-
-/* =========================
-        SCB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBR_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBR_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBR_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBR_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBW                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBW_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBW_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBW_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBW_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_SLAVES                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_SLAVES_SI                    0                               /* Slave Interface Value */
-#define BITM_SCB_SLAVES_SI                   (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_MASTERS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_MASTERS_MI                   0                               /* Master Interface Value */
-#define BITM_SCB_MASTERS_MI                  (_ADI_MSK(0x000000FF,uint32_t))  /* Master Interface Value */
-
-/* ==================================================
-        L2 Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        L2CTL0
-   ========================= */
-#define REG_L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 Control Register */
-#define REG_L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 Access Control Core 0 Register */
-#define REG_L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 Access Control Core 1 Register */
-#define REG_L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 Access Control System Register */
-#define REG_L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 Status Register */
-#define REG_L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 Read Priority Count Register */
-#define REG_L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 Write Priority Count Register */
-#define REG_L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 Refresh Address Register */
-#define REG_L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 ECC Error Address 0 Register */
-#define REG_L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 ECC Error Address 1 Register */
-#define REG_L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 ECC Error Address 2 Register */
-#define REG_L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 ECC Error Address 3 Register */
-#define REG_L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 ECC Error Address 4 Register */
-#define REG_L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 ECC Error Address 5 Register */
-#define REG_L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 ECC Error Address 6 Register */
-#define REG_L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 ECC Error Address 7 Register */
-#define REG_L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 Error Type 0 Register */
-#define REG_L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 Error Type 0 Address Register */
-#define REG_L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 Error Type 1 Register */
-#define REG_L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 Error Type 1 Address Register */
-
-/* =========================
-        L2CTL
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_CTL_LOCK                  31                               /* Lock */
-#define BITP_L2CTL_CTL_DISURP                16                               /* Disable Urgent Request Priority */
-#define BITP_L2CTL_CTL_ECCMAP7               15                               /* ECC Map Bank 7 */
-#define BITP_L2CTL_CTL_ECCMAP6               14                               /* ECC Map Bank 6 */
-#define BITP_L2CTL_CTL_ECCMAP5               13                               /* ECC Map Bank 5 */
-#define BITP_L2CTL_CTL_ECCMAP4               12                               /* ECC Map Bank 4 */
-#define BITP_L2CTL_CTL_ECCMAP3               11                               /* ECC Map Bank 3 */
-#define BITP_L2CTL_CTL_ECCMAP2               10                               /* ECC Map Bank 2 */
-#define BITP_L2CTL_CTL_ECCMAP1                9                               /* ECC Map Bank 1 */
-#define BITP_L2CTL_CTL_ECCMAP0                8                               /* ECC Map Bank 0 */
-#define BITP_L2CTL_CTL_BK7EDIS                7                               /* Bank 7 ECC Disable */
-#define BITP_L2CTL_CTL_BK6EDIS                6                               /* Bank 6 ECC Disable */
-#define BITP_L2CTL_CTL_BK5EDIS                5                               /* Bank 5 ECC Disable */
-#define BITP_L2CTL_CTL_BK4EDIS                4                               /* Bank 4 ECC Disable */
-#define BITP_L2CTL_CTL_BK3EDIS                3                               /* Bank 3 ECC Disable */
-#define BITP_L2CTL_CTL_BK2EDIS                2                               /* Bank 2 ECC Disable */
-#define BITP_L2CTL_CTL_BK1EDIS                1                               /* Bank 1 ECC Disable */
-#define BITP_L2CTL_CTL_BK0EDIS                0                               /* Bank 0 ECC Disable */
-#define BITM_L2CTL_CTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_CTL_DISURP                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Urgent Request Priority */
-#define BITM_L2CTL_CTL_ECCMAP7               (_ADI_MSK(0x00008000,uint32_t))  /* ECC Map Bank 7 */
-#define BITM_L2CTL_CTL_ECCMAP6               (_ADI_MSK(0x00004000,uint32_t))  /* ECC Map Bank 6 */
-#define BITM_L2CTL_CTL_ECCMAP5               (_ADI_MSK(0x00002000,uint32_t))  /* ECC Map Bank 5 */
-#define BITM_L2CTL_CTL_ECCMAP4               (_ADI_MSK(0x00001000,uint32_t))  /* ECC Map Bank 4 */
-#define BITM_L2CTL_CTL_ECCMAP3               (_ADI_MSK(0x00000800,uint32_t))  /* ECC Map Bank 3 */
-#define BITM_L2CTL_CTL_ECCMAP2               (_ADI_MSK(0x00000400,uint32_t))  /* ECC Map Bank 2 */
-#define BITM_L2CTL_CTL_ECCMAP1               (_ADI_MSK(0x00000200,uint32_t))  /* ECC Map Bank 1 */
-#define BITM_L2CTL_CTL_ECCMAP0               (_ADI_MSK(0x00000100,uint32_t))  /* ECC Map Bank 0 */
-#define BITM_L2CTL_CTL_BK7EDIS               (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 ECC Disable */
-#define BITM_L2CTL_CTL_BK6EDIS               (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 ECC Disable */
-#define BITM_L2CTL_CTL_BK5EDIS               (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 ECC Disable */
-#define BITM_L2CTL_CTL_BK4EDIS               (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 ECC Disable */
-#define BITM_L2CTL_CTL_BK3EDIS               (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 ECC Disable */
-#define BITM_L2CTL_CTL_BK2EDIS               (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 ECC Disable */
-#define BITM_L2CTL_CTL_BK1EDIS               (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 ECC Disable */
-#define BITM_L2CTL_CTL_BK0EDIS               (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 ECC Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C0_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C0_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C0_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C0_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C1_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C1_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C1_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C1_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_SYS                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_SYS_LOCK             31                               /* Lock */
-#define BITP_L2CTL_ACTL_SYS_BK7WDIS           7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK6WDIS           6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK5WDIS           5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK4WDIS           4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK3WDIS           3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK2WDIS           2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK1WDIS           1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK0WDIS           0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_LOCK             (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_SYS_BK7WDIS          (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK6WDIS          (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK5WDIS          (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK4WDIS          (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK3WDIS          (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK2WDIS          (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK1WDIS          (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK0WDIS          (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_STAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_STAT_ECCERR7              15                               /* ECC Error Bank 7 */
-#define BITP_L2CTL_STAT_ECCERR6              14                               /* ECC Error Bank 6 */
-#define BITP_L2CTL_STAT_ECCERR5              13                               /* ECC Error Bank 5 */
-#define BITP_L2CTL_STAT_ECCERR4              12                               /* ECC Error Bank 4 */
-#define BITP_L2CTL_STAT_ECCERR3              11                               /* ECC Error Bank 3 */
-#define BITP_L2CTL_STAT_ECCERR2              10                               /* ECC Error Bank 2 */
-#define BITP_L2CTL_STAT_ECCERR1               9                               /* ECC Error Bank 1 */
-#define BITP_L2CTL_STAT_ECCERR0               8                               /* ECC Error Bank 0 */
-#define BITP_L2CTL_STAT_RFRS                  4                               /* Refresh Register Status */
-#define BITP_L2CTL_STAT_ERR1                  1                               /* Error Port 1 */
-#define BITP_L2CTL_STAT_ERR0                  0                               /* Error Port 0 */
-#define BITM_L2CTL_STAT_ECCERR7              (_ADI_MSK(0x00008000,uint32_t))  /* ECC Error Bank 7 */
-#define BITM_L2CTL_STAT_ECCERR6              (_ADI_MSK(0x00004000,uint32_t))  /* ECC Error Bank 6 */
-#define BITM_L2CTL_STAT_ECCERR5              (_ADI_MSK(0x00002000,uint32_t))  /* ECC Error Bank 5 */
-#define BITM_L2CTL_STAT_ECCERR4              (_ADI_MSK(0x00001000,uint32_t))  /* ECC Error Bank 4 */
-#define BITM_L2CTL_STAT_ECCERR3              (_ADI_MSK(0x00000800,uint32_t))  /* ECC Error Bank 3 */
-#define BITM_L2CTL_STAT_ECCERR2              (_ADI_MSK(0x00000400,uint32_t))  /* ECC Error Bank 2 */
-#define BITM_L2CTL_STAT_ECCERR1              (_ADI_MSK(0x00000200,uint32_t))  /* ECC Error Bank 1 */
-#define BITM_L2CTL_STAT_ECCERR0              (_ADI_MSK(0x00000100,uint32_t))  /* ECC Error Bank 0 */
-#define BITM_L2CTL_STAT_RFRS                 (_ADI_MSK(0x00000010,uint32_t))  /* Refresh Register Status */
-#define BITM_L2CTL_STAT_ERR1                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Port 1 */
-#define BITM_L2CTL_STAT_ERR0                 (_ADI_MSK(0x00000001,uint32_t))  /* Error Port 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RPCR_RPC1                  8                               /* Read Priority Count 1 */
-#define BITP_L2CTL_RPCR_RPC0                  0                               /* Read Priority Count 0 */
-#define BITM_L2CTL_RPCR_RPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Read Priority Count 1 */
-#define BITM_L2CTL_RPCR_RPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Read Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_WPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_WPCR_WPC1                  8                               /* Write Priority Count 1 */
-#define BITP_L2CTL_WPCR_WPC0                  0                               /* Write Priority Count 0 */
-#define BITM_L2CTL_WPCR_WPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Write Priority Count 1 */
-#define BITM_L2CTL_WPCR_WPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Write Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RFA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RFA_ADDRHI                16                               /* Address High */
-#define BITP_L2CTL_RFA_ADDRLO                 0                               /* Address Low */
-#define BITM_L2CTL_RFA_ADDRHI                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Address High */
-#define BITM_L2CTL_RFA_ADDRLO                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address Low */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET0_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET0_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET0_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET0_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET0_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET0_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET0_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET0_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET0_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET0_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET0_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET0_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET1_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET1_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET1_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET1_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET1_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET1_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET1_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET1_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET1_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET1_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET1_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET1_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ==================================================
-        System Event Controller Registers
-   ================================================== */
-
-/* =========================
-        SEC0
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Core Interface (SCI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_CCTL0                  0xFFCA4400         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CCTL1                  0xFFCA4440         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CSTAT0                 0xFFCA4404         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CSTAT1                 0xFFCA4444         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CPND0                  0xFFCA4408         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CPND1                  0xFFCA4448         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CACT0                  0xFFCA440C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CACT1                  0xFFCA444C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CPMSK0                 0xFFCA4410         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CPMSK1                 0xFFCA4450         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CGMSK0                 0xFFCA4414         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CGMSK1                 0xFFCA4454         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CPLVL0                 0xFFCA4418         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CPLVL1                 0xFFCA4458         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CSID0                  0xFFCA441C         /* SEC0 SCI Source ID Register n */
-#define REG_SEC0_CSID1                  0xFFCA445C         /* SEC0 SCI Source ID Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Fault Management Interface (SFI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_FCTL                   0xFFCA4010         /* SEC0 Fault Control Register */
-#define REG_SEC0_FSTAT                  0xFFCA4014         /* SEC0 Fault Status Register */
-#define REG_SEC0_FSID                   0xFFCA4018         /* SEC0 Fault Source ID Register */
-#define REG_SEC0_FEND                   0xFFCA401C         /* SEC0 Fault End Register */
-#define REG_SEC0_FDLY                   0xFFCA4020         /* SEC0 Fault Delay Register */
-#define REG_SEC0_FDLY_CUR               0xFFCA4024         /* SEC0 Fault Delay Current Register */
-#define REG_SEC0_FSRDLY                 0xFFCA4028         /* SEC0 Fault System Reset Delay Register */
-#define REG_SEC0_FSRDLY_CUR             0xFFCA402C         /* SEC0 Fault System Reset Delay Current Register */
-#define REG_SEC0_FCOPP                  0xFFCA4030         /* SEC0 Fault COP Period Register */
-#define REG_SEC0_FCOPP_CUR              0xFFCA4034         /* SEC0 Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Global Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_GCTL                   0xFFCA4000         /* SEC0 Global Control Register */
-#define REG_SEC0_GSTAT                  0xFFCA4004         /* SEC0 Global Status Register */
-#define REG_SEC0_RAISE                  0xFFCA4008         /* SEC0 Global Raise Register */
-#define REG_SEC0_END                    0xFFCA400C         /* SEC0 Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Source Interface (SSI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_SCTL0                  0xFFCA4800         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL1                  0xFFCA4808         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL2                  0xFFCA4810         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL3                  0xFFCA4818         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL4                  0xFFCA4820         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL5                  0xFFCA4828         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL6                  0xFFCA4830         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL7                  0xFFCA4838         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL8                  0xFFCA4840         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL9                  0xFFCA4848         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL10                 0xFFCA4850         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL11                 0xFFCA4858         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL12                 0xFFCA4860         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL13                 0xFFCA4868         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL14                 0xFFCA4870         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL15                 0xFFCA4878         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL16                 0xFFCA4880         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL17                 0xFFCA4888         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL18                 0xFFCA4890         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL19                 0xFFCA4898         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL20                 0xFFCA48A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL21                 0xFFCA48A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL22                 0xFFCA48B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL23                 0xFFCA48B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL24                 0xFFCA48C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL25                 0xFFCA48C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL26                 0xFFCA48D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL27                 0xFFCA48D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL28                 0xFFCA48E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL29                 0xFFCA48E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL30                 0xFFCA48F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL31                 0xFFCA48F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL32                 0xFFCA4900         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL33                 0xFFCA4908         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL34                 0xFFCA4910         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL35                 0xFFCA4918         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL36                 0xFFCA4920         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL37                 0xFFCA4928         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL38                 0xFFCA4930         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL39                 0xFFCA4938         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL40                 0xFFCA4940         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL41                 0xFFCA4948         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL42                 0xFFCA4950         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL43                 0xFFCA4958         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL44                 0xFFCA4960         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL45                 0xFFCA4968         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL46                 0xFFCA4970         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL47                 0xFFCA4978         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL48                 0xFFCA4980         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL49                 0xFFCA4988         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL50                 0xFFCA4990         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL51                 0xFFCA4998         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL52                 0xFFCA49A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL53                 0xFFCA49A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL54                 0xFFCA49B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL55                 0xFFCA49B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL56                 0xFFCA49C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL57                 0xFFCA49C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL58                 0xFFCA49D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL59                 0xFFCA49D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL60                 0xFFCA49E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL61                 0xFFCA49E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL62                 0xFFCA49F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL63                 0xFFCA49F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL64                 0xFFCA4A00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL65                 0xFFCA4A08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL66                 0xFFCA4A10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL67                 0xFFCA4A18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL68                 0xFFCA4A20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL69                 0xFFCA4A28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL70                 0xFFCA4A30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL71                 0xFFCA4A38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL72                 0xFFCA4A40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL73                 0xFFCA4A48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL74                 0xFFCA4A50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL75                 0xFFCA4A58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL76                 0xFFCA4A60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL77                 0xFFCA4A68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL78                 0xFFCA4A70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL79                 0xFFCA4A78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL80                 0xFFCA4A80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL81                 0xFFCA4A88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL82                 0xFFCA4A90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL83                 0xFFCA4A98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL84                 0xFFCA4AA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL85                 0xFFCA4AA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL86                 0xFFCA4AB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL87                 0xFFCA4AB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL88                 0xFFCA4AC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL89                 0xFFCA4AC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL90                 0xFFCA4AD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL91                 0xFFCA4AD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL92                 0xFFCA4AE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL93                 0xFFCA4AE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL94                 0xFFCA4AF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL95                 0xFFCA4AF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL96                 0xFFCA4B00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL97                 0xFFCA4B08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL98                 0xFFCA4B10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL99                 0xFFCA4B18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL100                0xFFCA4B20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL101                0xFFCA4B28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL102                0xFFCA4B30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL103                0xFFCA4B38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL104                0xFFCA4B40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL105                0xFFCA4B48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL106                0xFFCA4B50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL107                0xFFCA4B58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL108                0xFFCA4B60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL109                0xFFCA4B68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL110                0xFFCA4B70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL111                0xFFCA4B78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL112                0xFFCA4B80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL113                0xFFCA4B88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL114                0xFFCA4B90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL115                0xFFCA4B98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL116                0xFFCA4BA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL117                0xFFCA4BA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL118                0xFFCA4BB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL119                0xFFCA4BB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL120                0xFFCA4BC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL121                0xFFCA4BC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL122                0xFFCA4BD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL123                0xFFCA4BD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL124                0xFFCA4BE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL125                0xFFCA4BE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL126                0xFFCA4BF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL127                0xFFCA4BF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL128                0xFFCA4C00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL129                0xFFCA4C08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL130                0xFFCA4C10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL131                0xFFCA4C18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL132                0xFFCA4C20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL133                0xFFCA4C28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL134                0xFFCA4C30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL135                0xFFCA4C38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL136                0xFFCA4C40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL137                0xFFCA4C48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL138                0xFFCA4C50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL139                0xFFCA4C58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SSTAT0                 0xFFCA4804         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT1                 0xFFCA480C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT2                 0xFFCA4814         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT3                 0xFFCA481C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT4                 0xFFCA4824         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT5                 0xFFCA482C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT6                 0xFFCA4834         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT7                 0xFFCA483C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT8                 0xFFCA4844         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT9                 0xFFCA484C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT10                0xFFCA4854         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT11                0xFFCA485C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT12                0xFFCA4864         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT13                0xFFCA486C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT14                0xFFCA4874         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT15                0xFFCA487C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT16                0xFFCA4884         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT17                0xFFCA488C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT18                0xFFCA4894         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT19                0xFFCA489C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT20                0xFFCA48A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT21                0xFFCA48AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT22                0xFFCA48B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT23                0xFFCA48BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT24                0xFFCA48C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT25                0xFFCA48CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT26                0xFFCA48D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT27                0xFFCA48DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT28                0xFFCA48E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT29                0xFFCA48EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT30                0xFFCA48F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT31                0xFFCA48FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT32                0xFFCA4904         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT33                0xFFCA490C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT34                0xFFCA4914         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT35                0xFFCA491C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT36                0xFFCA4924         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT37                0xFFCA492C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT38                0xFFCA4934         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT39                0xFFCA493C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT40                0xFFCA4944         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT41                0xFFCA494C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT42                0xFFCA4954         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT43                0xFFCA495C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT44                0xFFCA4964         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT45                0xFFCA496C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT46                0xFFCA4974         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT47                0xFFCA497C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT48                0xFFCA4984         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT49                0xFFCA498C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT50                0xFFCA4994         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT51                0xFFCA499C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT52                0xFFCA49A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT53                0xFFCA49AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT54                0xFFCA49B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT55                0xFFCA49BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT56                0xFFCA49C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT57                0xFFCA49CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT58                0xFFCA49D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT59                0xFFCA49DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT60                0xFFCA49E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT61                0xFFCA49EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT62                0xFFCA49F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT63                0xFFCA49FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT64                0xFFCA4A04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT65                0xFFCA4A0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT66                0xFFCA4A14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT67                0xFFCA4A1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT68                0xFFCA4A24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT69                0xFFCA4A2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT70                0xFFCA4A34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT71                0xFFCA4A3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT72                0xFFCA4A44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT73                0xFFCA4A4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT74                0xFFCA4A54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT75                0xFFCA4A5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT76                0xFFCA4A64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT77                0xFFCA4A6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT78                0xFFCA4A74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT79                0xFFCA4A7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT80                0xFFCA4A84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT81                0xFFCA4A8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT82                0xFFCA4A94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT83                0xFFCA4A9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT84                0xFFCA4AA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT85                0xFFCA4AAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT86                0xFFCA4AB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT87                0xFFCA4ABC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT88                0xFFCA4AC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT89                0xFFCA4ACC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT90                0xFFCA4AD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT91                0xFFCA4ADC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT92                0xFFCA4AE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT93                0xFFCA4AEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT94                0xFFCA4AF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT95                0xFFCA4AFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT96                0xFFCA4B04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT97                0xFFCA4B0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT98                0xFFCA4B14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT99                0xFFCA4B1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT100               0xFFCA4B24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT101               0xFFCA4B2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT102               0xFFCA4B34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT103               0xFFCA4B3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT104               0xFFCA4B44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT105               0xFFCA4B4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT106               0xFFCA4B54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT107               0xFFCA4B5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT108               0xFFCA4B64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT109               0xFFCA4B6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT110               0xFFCA4B74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT111               0xFFCA4B7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT112               0xFFCA4B84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT113               0xFFCA4B8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT114               0xFFCA4B94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT115               0xFFCA4B9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT116               0xFFCA4BA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT117               0xFFCA4BAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT118               0xFFCA4BB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT119               0xFFCA4BBC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT120               0xFFCA4BC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT121               0xFFCA4BCC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT122               0xFFCA4BD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT123               0xFFCA4BDC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT124               0xFFCA4BE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT125               0xFFCA4BEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT126               0xFFCA4BF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT127               0xFFCA4BFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT128               0xFFCA4C04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT129               0xFFCA4C0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT130               0xFFCA4C14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT131               0xFFCA4C1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT132               0xFFCA4C24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT133               0xFFCA4C2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT134               0xFFCA4C34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT135               0xFFCA4C3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT136               0xFFCA4C44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT137               0xFFCA4C4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT138               0xFFCA4C54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT139               0xFFCA4C5C         /* SEC0 Source Status Register n */
-
-/* =========================
-        SEC
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_CCTL_NMIEN                  16                               /* NMI Enable */
-#define BITP_SEC_CCTL_WFI                    12                               /* Wait For Idle */
-#define BITP_SEC_CCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_CCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CCTL_NMIEN                  (_ADI_MSK(0x00010000,uint32_t))  /* NMI Enable */
-#define ENUM_SEC_CCTL_NMI_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* NMIEN: Disable */
-#define ENUM_SEC_CCTL_NMI_EN                 (_ADI_MSK(0x00010000,uint32_t))  /* NMIEN: Enable */
-
-#define BITM_SEC_CCTL_WFI                    (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CCTL_NO_WAITIDLE            (_ADI_MSK(0x00000000,uint32_t))  /* WFI: No Action */
-#define ENUM_SEC_CCTL_WAITIDLE               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Wait for Idle */
-
-#define BITM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_CCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_CCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSTAT_NMI                   16                               /* NMI */
-#define BITP_SEC_CSTAT_WFI                   12                               /* Wait For Idle */
-#define BITP_SEC_CSTAT_SIDV                  10                               /* SID Valid */
-#define BITP_SEC_CSTAT_ACTV                   9                               /* ACT Valid */
-#define BITP_SEC_CSTAT_PNDV                   8                               /* PND Valid */
-#define BITP_SEC_CSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_CSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI */
-#define ENUM_SEC_CSTAT_NO_NMI                (_ADI_MSK(0x00000000,uint32_t))  /* NMI: No NMI Occured */
-#define ENUM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI: NMI Occurred */
-
-#define BITM_SEC_CSTAT_WFI                   (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CSTAT_NOT_WAITING           (_ADI_MSK(0x00000000,uint32_t))  /* WFI: Not Waiting */
-#define ENUM_SEC_CSTAT_WAITING               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Waiting */
-
-#define BITM_SEC_CSTAT_SIDV                  (_ADI_MSK(0x00000400,uint32_t))  /* SID Valid */
-#define ENUM_SEC_CSTAT_INVALID_SID           (_ADI_MSK(0x00000000,uint32_t))  /* SIDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_SID             (_ADI_MSK(0x00000400,uint32_t))  /* SIDV: Valid */
-
-#define BITM_SEC_CSTAT_ACTV                  (_ADI_MSK(0x00000200,uint32_t))  /* ACT Valid */
-#define ENUM_SEC_CSTAT_INVALID_ACT           (_ADI_MSK(0x00000000,uint32_t))  /* ACTV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_ACT             (_ADI_MSK(0x00000200,uint32_t))  /* ACTV: Valid */
-
-#define BITM_SEC_CSTAT_PNDV                  (_ADI_MSK(0x00000100,uint32_t))  /* PND Valid */
-#define ENUM_SEC_CSTAT_INVALID_PND           (_ADI_MSK(0x00000000,uint32_t))  /* PNDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_PND             (_ADI_MSK(0x00000100,uint32_t))  /* PNDV: Valid */
-
-#define BITM_SEC_CSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_CSTAT_ACKERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Acknowledge Error */
-
-#define BITM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_CSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPND_PRIO                    8                               /* Highest Pending IRQ Priority */
-#define BITP_SEC_CPND_SID                     0                               /* Highest Pending IRQ Source ID */
-#define BITM_SEC_CPND_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Pending IRQ Priority */
-#define BITM_SEC_CPND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CACT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CACT_PRIO                    8                               /* Highest Active IRQ Priority */
-#define BITP_SEC_CACT_SID                     0                               /* Highest Active IRQ Source ID */
-#define BITM_SEC_CACT_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Active IRQ Priority */
-#define BITM_SEC_CACT_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPMSK_PRIO                   0                               /* IRQ Priority Mask */
-
-#define BITM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPMSK_PRIO                  (_ADI_MSK(0x000000FF,uint32_t))  /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CGMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CGMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CGMSK_UGRP                   8                               /* Ungrouped Mask */
-#define BITP_SEC_CGMSK_GRP                    0                               /* Grouped Mask */
-
-#define BITM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CGMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CGMSK_UGRP                  (_ADI_MSK(0x00000100,uint32_t))  /* Ungrouped Mask */
-#define ENUM_SEC_CGMSK_UNMASK                (_ADI_MSK(0x00000000,uint32_t))  /* UGRP: Unmask Ungrouped Sources */
-#define ENUM_SEC_CGMSK_MASK                  (_ADI_MSK(0x00000100,uint32_t))  /* UGRP: Mask Ungrouped Sources */
-#define BITM_SEC_CGMSK_GRP                   (_ADI_MSK(0x0000000F,uint32_t))  /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPLVL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPLVL_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPLVL_PLVL                   0                               /* Priority Levels */
-
-#define BITM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPLVL_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPLVL_PLVL                  (_ADI_MSK(0x00000007,uint32_t))  /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSID_SID                     0                               /* Source ID */
-#define BITM_SEC_CSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_FCTL_TES                    13                               /* Trigger Event Select */
-#define BITP_SEC_FCTL_CMS                    12                               /* COP Mode Select */
-#define BITP_SEC_FCTL_FIEN                    7                               /* Fault Input Enable */
-#define BITP_SEC_FCTL_SREN                    6                               /* System Reset Enable */
-#define BITP_SEC_FCTL_TOEN                    5                               /* Trigger Output Enable */
-#define BITP_SEC_FCTL_FOEN                    4                               /* Fault Output Enable */
-#define BITP_SEC_FCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_FCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_FCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: UnLock */
-#define ENUM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_FCTL_TES                    (_ADI_MSK(0x00002000,uint32_t))  /* Trigger Event Select */
-#define ENUM_SEC_FCTL_FLTACT_MODE            (_ADI_MSK(0x00000000,uint32_t))  /* TES: Fault Active Mode */
-#define ENUM_SEC_FCTL_FLTPND_MODE            (_ADI_MSK(0x00002000,uint32_t))  /* TES: Fault Pending Mode */
-
-#define BITM_SEC_FCTL_CMS                    (_ADI_MSK(0x00001000,uint32_t))  /* COP Mode Select */
-#define ENUM_SEC_FCTL_FLT_MODE               (_ADI_MSK(0x00000000,uint32_t))  /* CMS: Fault Mode */
-#define ENUM_SEC_FCTL_COP_MODE               (_ADI_MSK(0x00001000,uint32_t))  /* CMS: COP Mode */
-
-#define BITM_SEC_FCTL_FIEN                   (_ADI_MSK(0x00000080,uint32_t))  /* Fault Input Enable */
-#define ENUM_SEC_FCTL_FLTIN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FIEN: Disable */
-#define ENUM_SEC_FCTL_FLTIN_EN               (_ADI_MSK(0x00000080,uint32_t))  /* FIEN: Enable */
-
-#define BITM_SEC_FCTL_SREN                   (_ADI_MSK(0x00000040,uint32_t))  /* System Reset Enable */
-#define ENUM_SEC_FCTL_SYSRST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SREN: Disable */
-#define ENUM_SEC_FCTL_SYSRST_EN              (_ADI_MSK(0x00000040,uint32_t))  /* SREN: Enable */
-
-#define BITM_SEC_FCTL_TOEN                   (_ADI_MSK(0x00000020,uint32_t))  /* Trigger Output Enable */
-#define ENUM_SEC_FCTL_TRGOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TOEN: Disable */
-#define ENUM_SEC_FCTL_TRGOUT_EN              (_ADI_MSK(0x00000020,uint32_t))  /* TOEN: Enable */
-
-#define BITM_SEC_FCTL_FOEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Fault Output Enable */
-#define ENUM_SEC_FCTL_FLTOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* FOEN: Disable */
-#define ENUM_SEC_FCTL_FLTOUT_EN              (_ADI_MSK(0x00000010,uint32_t))  /* FOEN: Enable */
-
-#define BITM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_FCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_FCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSTAT_NPND                  10                               /* Next Pending Fault */
-#define BITP_SEC_FSTAT_ACT                    9                               /* Fault Active */
-#define BITP_SEC_FSTAT_PND                    8                               /* Pending Fault */
-#define BITP_SEC_FSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_FSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_FSTAT_NPND                  (_ADI_MSK(0x00000400,uint32_t))  /* Next Pending Fault */
-#define ENUM_SEC_FSTAT_NO_NXTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* NPND: Not Pending */
-#define ENUM_SEC_FSTAT_NXTFLT                (_ADI_MSK(0x00000400,uint32_t))  /* NPND: Pending */
-
-#define BITM_SEC_FSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Fault Active */
-#define ENUM_SEC_FSTAT_NO_FLTACT             (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Fault */
-#define ENUM_SEC_FSTAT_FLTACT                (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Fault */
-
-#define BITM_SEC_FSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Fault */
-#define ENUM_SEC_FSTAT_NO_FLTPND             (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_FSTAT_FLTPND                (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_FSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_FSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_FSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSID_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FSID_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FSID_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FSID_SRC_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FSID_SRC_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FEND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FEND_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FEND_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FEND_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FEND_END_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FEND_END_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FEND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_GCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_GCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_GCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_GCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_GCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GSTAT_LWERR                 31                               /* Lock Write Error */
-#define BITP_SEC_GSTAT_ADRERR                30                               /* Address Error */
-#define BITP_SEC_GSTAT_SID                   16                               /* Source ID for SSI Error */
-#define BITP_SEC_GSTAT_SCI                    8                               /* SCI ID for SCI Error */
-#define BITP_SEC_GSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_GSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define ENUM_SEC_GSTAT_NO_LWERR              (_ADI_MSK(0x00000000,uint32_t))  /* LWERR: No Error */
-#define ENUM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* LWERR: Error Occurred */
-
-#define BITM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define ENUM_SEC_GSTAT_NO_ADRERR             (_ADI_MSK(0x00000000,uint32_t))  /* ADRERR: No Error */
-#define ENUM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* ADRERR: Error Occurred */
-#define BITM_SEC_GSTAT_SID                   (_ADI_MSK(0x00FF0000,uint32_t))  /* Source ID for SSI Error */
-#define BITM_SEC_GSTAT_SCI                   (_ADI_MSK(0x00000F00,uint32_t))  /* SCI ID for SCI Error */
-
-#define BITM_SEC_GSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_GSTAT_SFIERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: SFI Error */
-#define ENUM_SEC_GSTAT_SCIERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: SCI Error */
-#define ENUM_SEC_GSTAT_SSIERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: SSI Error */
-
-#define BITM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_GSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_RAISE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_RAISE_SID                    0                               /* Source ID IRQ Set to Pending */
-#define BITM_SEC_RAISE_SID                   (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_END                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_END_SID                      0                               /* Source ID IRQ to End */
-#define BITM_SEC_END_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_SCTL_CTG                    24                               /* Core Target Select */
-#define BITP_SEC_SCTL_GRP                    16                               /* Group Select */
-#define BITP_SEC_SCTL_PRIO                    8                               /* Priority Level Select */
-#define BITP_SEC_SCTL_ERREN                   4                               /* Error Enable */
-#define BITP_SEC_SCTL_ES                      3                               /* Edge Select */
-#define BITP_SEC_SCTL_SEN                     2                               /* Source (signal) Enable */
-#define BITP_SEC_SCTL_FEN                     1                               /* Fault Enable */
-#define BITP_SEC_SCTL_IEN                     0                               /* Interrupt Enable */
-
-#define BITM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_SCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_SCTL_CTG                    (_ADI_MSK(0x0F000000,uint32_t))  /* Core Target Select */
-#define BITM_SEC_SCTL_GRP                    (_ADI_MSK(0x000F0000,uint32_t))  /* Group Select */
-#define BITM_SEC_SCTL_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Priority Level Select */
-
-#define BITM_SEC_SCTL_ERREN                  (_ADI_MSK(0x00000010,uint32_t))  /* Error Enable */
-#define ENUM_SEC_SCTL_ERR_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* ERREN: Disable */
-#define ENUM_SEC_SCTL_ERR_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* ERREN: Enable */
-
-#define BITM_SEC_SCTL_ES                     (_ADI_MSK(0x00000008,uint32_t))  /* Edge Select */
-#define ENUM_SEC_SCTL_LEVEL                  (_ADI_MSK(0x00000000,uint32_t))  /* ES: Level Sensitive */
-#define ENUM_SEC_SCTL_EDGE                   (_ADI_MSK(0x00000008,uint32_t))  /* ES: Edge Sensitive */
-
-#define BITM_SEC_SCTL_SEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Source (signal) Enable */
-#define ENUM_SEC_SCTL_SRC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* SEN: Disable */
-#define ENUM_SEC_SCTL_SRC_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* SEN: Enable */
-
-#define BITM_SEC_SCTL_FEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Fault Enable */
-#define ENUM_SEC_SCTL_FAULT_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FEN: Disable */
-#define ENUM_SEC_SCTL_FAULT_EN               (_ADI_MSK(0x00000002,uint32_t))  /* FEN: Enable */
-
-#define BITM_SEC_SCTL_IEN                    (_ADI_MSK(0x00000001,uint32_t))  /* Interrupt Enable */
-#define ENUM_SEC_SCTL_INT_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* IEN: Disable */
-#define ENUM_SEC_SCTL_INT_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SSTAT_CHID                  16                               /* Channel ID */
-#define BITP_SEC_SSTAT_ACT                    9                               /* Active Source */
-#define BITP_SEC_SSTAT_PND                    8                               /* Pending Source */
-#define BITP_SEC_SSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_SSTAT_ERR                    1                               /* Error */
-#define BITM_SEC_SSTAT_CHID                  (_ADI_MSK(0x00FF0000,uint32_t))  /* Channel ID */
-
-#define BITM_SEC_SSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Active Source */
-#define ENUM_SEC_SSTAT_NO_SRC                (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Source */
-#define ENUM_SEC_SSTAT_ACTIVE_SRC            (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Source */
-
-#define BITM_SEC_SSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Source */
-#define ENUM_SEC_SSTAT_NOTPENDING            (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_SSTAT_PENDING               (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_SSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_SSTAT_SOVFERR               (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Source Overflow Error */
-#define ENUM_SEC_SSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_SSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ==================================================
-        Trigger Routing Unit Registers
-   ================================================== */
-
-/* =========================
-        TRU0
-   ========================= */
-#define REG_TRU0_SSR0                   0xFFCA5000         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR1                   0xFFCA5004         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR2                   0xFFCA5008         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR3                   0xFFCA500C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR4                   0xFFCA5010         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR5                   0xFFCA5014         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR6                   0xFFCA5018         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR7                   0xFFCA501C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR8                   0xFFCA5020         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR9                   0xFFCA5024         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR10                  0xFFCA5028         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR11                  0xFFCA502C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR12                  0xFFCA5030         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR13                  0xFFCA5034         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR14                  0xFFCA5038         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR15                  0xFFCA503C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR16                  0xFFCA5040         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR17                  0xFFCA5044         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR18                  0xFFCA5048         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR19                  0xFFCA504C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR20                  0xFFCA5050         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR21                  0xFFCA5054         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR22                  0xFFCA5058         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR23                  0xFFCA505C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR24                  0xFFCA5060         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR25                  0xFFCA5064         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR26                  0xFFCA5068         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR27                  0xFFCA506C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR28                  0xFFCA5070         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR29                  0xFFCA5074         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR30                  0xFFCA5078         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR31                  0xFFCA507C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR32                  0xFFCA5080         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR33                  0xFFCA5084         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR34                  0xFFCA5088         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR35                  0xFFCA508C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR36                  0xFFCA5090         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR37                  0xFFCA5094         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR38                  0xFFCA5098         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR39                  0xFFCA509C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR40                  0xFFCA50A0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR41                  0xFFCA50A4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR42                  0xFFCA50A8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR43                  0xFFCA50AC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR44                  0xFFCA50B0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR45                  0xFFCA50B4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR46                  0xFFCA50B8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR47                  0xFFCA50BC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR48                  0xFFCA50C0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR49                  0xFFCA50C4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR50                  0xFFCA50C8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR51                  0xFFCA50CC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR52                  0xFFCA50D0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR53                  0xFFCA50D4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR54                  0xFFCA50D8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR55                  0xFFCA50DC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR56                  0xFFCA50E0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR57                  0xFFCA50E4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR58                  0xFFCA50E8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR59                  0xFFCA50EC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR60                  0xFFCA50F0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR61                  0xFFCA50F4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR62                  0xFFCA50F8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR63                  0xFFCA50FC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR64                  0xFFCA5100         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR65                  0xFFCA5104         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR66                  0xFFCA5108         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR67                  0xFFCA510C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR68                  0xFFCA5110         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR69                  0xFFCA5114         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR70                  0xFFCA5118         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR71                  0xFFCA511C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR72                  0xFFCA5120         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR73                  0xFFCA5124         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR74                  0xFFCA5128         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR75                  0xFFCA512C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR76                  0xFFCA5130         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR77                  0xFFCA5134         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR78                  0xFFCA5138         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR79                  0xFFCA513C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR80                  0xFFCA5140         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR81                  0xFFCA5144         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR82                  0xFFCA5148         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR83                  0xFFCA514C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR84                  0xFFCA5150         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR85                  0xFFCA5154         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR86                  0xFFCA5158         /* TRU0 Slave Select Register */
-#define REG_TRU0_MTR                    0xFFCA57E0         /* TRU0 Master Trigger Register */
-#define REG_TRU0_ERRADDR                0xFFCA57E8         /* TRU0 Error Address Register */
-#define REG_TRU0_STAT                   0xFFCA57EC         /* TRU0 Status Information Register */
-#define REG_TRU0_REVID                  0xFFCA57F0         /* TRU0 Revision ID Register */
-#define REG_TRU0_GCTL                   0xFFCA57F4         /* TRU0 Global Control Register */
-
-/* =========================
-        TRU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_SSR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_SSR_LOCK                    31                               /* SSRn Lock */
-#define BITP_TRU_SSR_SSR                      0                               /* SSRn Slave Select */
-#define BITM_TRU_SSR_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* SSRn Lock */
-#define BITM_TRU_SSR_SSR                     (_ADI_MSK(0x000000FF,uint32_t))  /* SSRn Slave Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_MTR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_MTR_MTR3                    24                               /* Master Trigger Register 3 */
-#define BITP_TRU_MTR_MTR2                    16                               /* Master Trigger Register 2 */
-#define BITP_TRU_MTR_MTR1                     8                               /* Master Trigger Register 1 */
-#define BITP_TRU_MTR_MTR0                     0                               /* Master Trigger Register 0 */
-#define BITM_TRU_MTR_MTR3                    (_ADI_MSK(0xFF000000,uint32_t))  /* Master Trigger Register 3 */
-#define BITM_TRU_MTR_MTR2                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Master Trigger Register 2 */
-#define BITM_TRU_MTR_MTR1                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Master Trigger Register 1 */
-#define BITM_TRU_MTR_MTR0                    (_ADI_MSK(0x000000FF,uint32_t))  /* Master Trigger Register 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_ERRADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_ERRADDR_ADDR                 0                               /* Error Address */
-#define BITM_TRU_ERRADDR_ADDR                (_ADI_MSK(0x00000FFF,uint32_t))  /* Error Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_STAT_ADDRERR                 1                               /* Address Error Status */
-#define BITP_TRU_STAT_LWERR                   0                               /* Lock Write Error Status */
-#define BITM_TRU_STAT_ADDRERR                (_ADI_MSK(0x00000002,uint32_t))  /* Address Error Status */
-#define BITM_TRU_STAT_LWERR                  (_ADI_MSK(0x00000001,uint32_t))  /* Lock Write Error Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_REVID_MAJOR                  4                               /* Major Version ID */
-#define BITP_TRU_REVID_REV                    0                               /* Incremental Version ID */
-#define BITM_TRU_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_TRU_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_GCTL_LOCK                   31                               /* GCTL Lock Bit */
-#define BITP_TRU_GCTL_MTRL                    2                               /* MTR Lock Bit */
-#define BITP_TRU_GCTL_RESET                   1                               /* Soft Reset */
-#define BITP_TRU_GCTL_EN                      0                               /* Non-MMR Enable */
-#define BITM_TRU_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* GCTL Lock Bit */
-#define BITM_TRU_GCTL_MTRL                   (_ADI_MSK(0x00000004,uint32_t))  /* MTR Lock Bit */
-#define BITM_TRU_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Soft Reset */
-#define BITM_TRU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Non-MMR Enable */
-
-/* ==================================================
-        Reset Control Unit Registers
-   ================================================== */
-
-/* =========================
-        RCU0
-   ========================= */
-#define REG_RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
-#define REG_RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
-#define REG_RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
-#define REG_RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
-#define REG_RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
-#define REG_RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
-#define REG_RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
-#define REG_RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
-#define REG_RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
-#define REG_RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
-
-/* =========================
-        RCU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CTL_LOCK                    31                               /* Lock */
-#define BITP_RCU_CTL_RSTOUTDSRT               2                               /* Reset Out Deassert */
-#define BITP_RCU_CTL_RSTOUTASRT               1                               /* Reset Out Assert */
-#define BITP_RCU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_RCU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CTL_RSTOUTDSRT              (_ADI_MSK(0x00000004,uint32_t))  /* Reset Out Deassert */
-#define BITM_RCU_CTL_RSTOUTASRT              (_ADI_MSK(0x00000002,uint32_t))  /* Reset Out Assert */
-#define BITM_RCU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_STAT_RSTOUTERR              18                               /* Reset Out Error */
-#define BITP_RCU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_RCU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_RCU_STAT_BMODE                   8                               /* Boot Mode */
-#define BITP_RCU_STAT_RSTOUT                  5                               /* Reset Out Status */
-#define BITP_RCU_STAT_SWRST                   3                               /* Software Reset */
-#define BITP_RCU_STAT_SSRST                   2                               /* System Source Reset */
-#define BITP_RCU_STAT_HBRST                   1                               /* Hibernate Reset */
-#define BITP_RCU_STAT_HWRST                   0                               /* Hardware Reset */
-#define BITM_RCU_STAT_RSTOUTERR              (_ADI_MSK(0x00040000,uint32_t))  /* Reset Out Error */
-#define BITM_RCU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_RCU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_RCU_STAT_BMODE                  (_ADI_MSK(0x00000F00,uint32_t))  /* Boot Mode */
-#define BITM_RCU_STAT_RSTOUT                 (_ADI_MSK(0x00000020,uint32_t))  /* Reset Out Status */
-#define BITM_RCU_STAT_SWRST                  (_ADI_MSK(0x00000008,uint32_t))  /* Software Reset */
-#define BITM_RCU_STAT_SSRST                  (_ADI_MSK(0x00000004,uint32_t))  /* System Source Reset */
-#define BITM_RCU_STAT_HBRST                  (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Reset */
-#define BITM_RCU_STAT_HWRST                  (_ADI_MSK(0x00000001,uint32_t))  /* Hardware Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRCTL_LOCK                  31                               /* Lock */
-#define BITP_RCU_CRCTL_CR0                    0                               /* Core Reset n */
-#define BITP_RCU_CRCTL_CR1                    1                               /* Core Reset n */
-#define BITM_RCU_CRCTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CRCTL_CR0                   (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRCTL_CR1                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRSTAT_CR0                   0                               /* Core Reset n */
-#define BITP_RCU_CRSTAT_CR1                   1                               /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR0                  (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR1                  (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SIDIS                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SIDIS_LOCK                  31                               /* Lock */
-#define BITP_RCU_SIDIS_SI0                    0                               /* System Interface n */
-#define BITP_RCU_SIDIS_SI1                    1                               /* System Interface n */
-#define BITM_RCU_SIDIS_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SIDIS_SI0                   (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SIDIS_SI1                   (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SISTAT_SI0                   0                               /* System Interface n */
-#define BITP_RCU_SISTAT_SI1                   1                               /* System Interface n */
-#define BITM_RCU_SISTAT_SI0                  (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SISTAT_SI1                  (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SVECT_LCK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SVECT_LCK_LOCK              31                               /* Lock */
-#define BITP_RCU_SVECT_LCK_SVECT0             0                               /* Software Vector Register n */
-#define BITP_RCU_SVECT_LCK_SVECT1             1                               /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SVECT_LCK_SVECT0            (_ADI_MSK(0x00000001,uint32_t))  /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_SVECT1            (_ADI_MSK(0x00000002,uint32_t))  /* Software Vector Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_BCODE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_BCODE_LOCK                  31                               /* Lock */
-#define BITP_RCU_BCODE_BCODE                  0                               /* Boot Code */
-#define BITM_RCU_BCODE_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_BCODE_BCODE                 (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Boot Code */
-
-/* ==================================================
-        System Protection Unit Registers
-   ================================================== */
-
-/* =========================
-        SPU0
-   ========================= */
-#define REG_SPU0_CTL                    0xFFCA7000         /* SPU0 Control Register */
-#define REG_SPU0_STAT                   0xFFCA7004         /* SPU0 Status Register */
-#define REG_SPU0_WP0                    0xFFCA7400         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP1                    0xFFCA7404         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP2                    0xFFCA7408         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP3                    0xFFCA740C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP4                    0xFFCA7410         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP5                    0xFFCA7414         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP6                    0xFFCA7418         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP7                    0xFFCA741C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP8                    0xFFCA7420         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP9                    0xFFCA7424         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP10                   0xFFCA7428         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP11                   0xFFCA742C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP12                   0xFFCA7430         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP13                   0xFFCA7434         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP14                   0xFFCA7438         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP15                   0xFFCA743C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP16                   0xFFCA7440         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP17                   0xFFCA7444         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP18                   0xFFCA7448         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP19                   0xFFCA744C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP20                   0xFFCA7450         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP21                   0xFFCA7454         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP22                   0xFFCA7458         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP23                   0xFFCA745C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP24                   0xFFCA7460         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP25                   0xFFCA7464         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP26                   0xFFCA7468         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP27                   0xFFCA746C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP28                   0xFFCA7470         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP29                   0xFFCA7474         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP30                   0xFFCA7478         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP31                   0xFFCA747C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP32                   0xFFCA7480         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP33                   0xFFCA7484         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP34                   0xFFCA7488         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP35                   0xFFCA748C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP36                   0xFFCA7490         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP37                   0xFFCA7494         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP38                   0xFFCA7498         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP39                   0xFFCA749C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP40                   0xFFCA74A0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP41                   0xFFCA74A4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP42                   0xFFCA74A8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP43                   0xFFCA74AC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP44                   0xFFCA74B0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP45                   0xFFCA74B4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP46                   0xFFCA74B8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP47                   0xFFCA74BC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP48                   0xFFCA74C0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP49                   0xFFCA74C4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP50                   0xFFCA74C8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP51                   0xFFCA74CC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP52                   0xFFCA74D0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP53                   0xFFCA74D4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP54                   0xFFCA74D8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP55                   0xFFCA74DC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP56                   0xFFCA74E0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP57                   0xFFCA74E4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP58                   0xFFCA74E8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP59                   0xFFCA74EC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP60                   0xFFCA74F0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP61                   0xFFCA74F4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP62                   0xFFCA74F8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP63                   0xFFCA74FC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP64                   0xFFCA7500         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP65                   0xFFCA7504         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP66                   0xFFCA7508         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP67                   0xFFCA750C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP68                   0xFFCA7510         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP69                   0xFFCA7514         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP70                   0xFFCA7518         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP71                   0xFFCA751C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP72                   0xFFCA7520         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP73                   0xFFCA7524         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP74                   0xFFCA7528         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP75                   0xFFCA752C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP76                   0xFFCA7530         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP77                   0xFFCA7534         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP78                   0xFFCA7538         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP79                   0xFFCA753C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP80                   0xFFCA7540         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP81                   0xFFCA7544         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP82                   0xFFCA7548         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP83                   0xFFCA754C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP84                   0xFFCA7550         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP85                   0xFFCA7554         /* SPU0 Write Protect Register n */
-
-/* =========================
-        SPU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_CTL_WPLCK                   16                               /* Write Protect Register Lock */
-#define BITP_SPU_CTL_GLCK                     0                               /* Global Lock Disable */
-#define BITM_SPU_CTL_WPLCK                   (_ADI_MSK(0x00010000,uint32_t))  /* Write Protect Register Lock */
-#define BITM_SPU_CTL_GLCK                    (_ADI_MSK(0x000000FF,uint32_t))  /* Global Lock Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_STAT_LWERR                  31                               /* Lock Write Error */
-#define BITP_SPU_STAT_ADDRERR                30                               /* Address Error */
-#define BITP_SPU_STAT_GLCK                    0                               /* Global Lock Status */
-#define BITM_SPU_STAT_LWERR                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define BITM_SPU_STAT_ADDRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define BITM_SPU_STAT_GLCK                   (_ADI_MSK(0x00000001,uint32_t))  /* Global Lock Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_WP                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_WP_SM0                      16                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_SM1                      17                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_CM0                       0                               /* Core Master x Write Protect Enable */
-#define BITP_SPU_WP_CM1                       1                               /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_SM0                      (_ADI_MSK(0x00010000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_SM1                      (_ADI_MSK(0x00020000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_CM0                      (_ADI_MSK(0x00000001,uint32_t))  /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_CM1                      (_ADI_MSK(0x00000002,uint32_t))  /* Core Master x Write Protect Enable */
-
-/* ==================================================
-        Clock Generation Unit Registers
-   ================================================== */
-
-/* =========================
-        CGU0
-   ========================= */
-#define REG_CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
-#define REG_CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
-#define REG_CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
-#define REG_CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
-
-/* =========================
-        CGU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CTL_LOCK                    31                               /* Lock */
-#define BITP_CGU_CTL_WFI                     30                               /* Wait For Idle */
-#define BITP_CGU_CTL_MSEL                     8                               /* Multiplier Select */
-#define BITP_CGU_CTL_DF                       0                               /* Divide Frequency */
-#define BITM_CGU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_CTL_WFI                     (_ADI_MSK(0x40000000,uint32_t))  /* Wait For Idle */
-
-#define BITM_CGU_CTL_MSEL                    (_ADI_MSK(0x00007F00,uint32_t))  /* Multiplier Select */
-#define ENUM_CGU_CTL_MSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* MSEL: MSEL = 1 to 127 */
-#define BITM_CGU_CTL_DF                      (_ADI_MSK(0x00000001,uint32_t))  /* Divide Frequency */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_STAT_PLOCKERR               21                               /* PLL Lock Error */
-#define BITP_CGU_STAT_WDIVERR                20                               /* Write to DIV Error */
-#define BITP_CGU_STAT_WDFMSERR               19                               /* Write to DF or MSEL Error */
-#define BITP_CGU_STAT_DIVERR                 18                               /* DIV Error */
-#define BITP_CGU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_CGU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_CGU_STAT_OCBF                    9                               /* OUTCLK Buffer Status */
-#define BITP_CGU_STAT_DCBF                    8                               /* DCLK Buffer Status */
-#define BITP_CGU_STAT_SCBF1                   7                               /* SCLK1 Buffer Status */
-#define BITP_CGU_STAT_SCBF0                   6                               /* SCLK0 Buffer Status */
-#define BITP_CGU_STAT_CCBF1                   5                               /* CCLK1 Buffer Status */
-#define BITP_CGU_STAT_CCBF0                   4                               /* CCLK0 Buffer Status */
-#define BITP_CGU_STAT_CLKSALGN                3                               /* Clock Alignment */
-#define BITP_CGU_STAT_PLOCK                   2                               /* PLL Lock */
-#define BITP_CGU_STAT_PLLBP                   1                               /* PLL Bypass */
-#define BITP_CGU_STAT_PLLEN                   0                               /* PLL Enable */
-#define BITM_CGU_STAT_PLOCKERR               (_ADI_MSK(0x00200000,uint32_t))  /* PLL Lock Error */
-#define BITM_CGU_STAT_WDIVERR                (_ADI_MSK(0x00100000,uint32_t))  /* Write to DIV Error */
-#define BITM_CGU_STAT_WDFMSERR               (_ADI_MSK(0x00080000,uint32_t))  /* Write to DF or MSEL Error */
-#define BITM_CGU_STAT_DIVERR                 (_ADI_MSK(0x00040000,uint32_t))  /* DIV Error */
-#define BITM_CGU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_CGU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_CGU_STAT_OCBF                   (_ADI_MSK(0x00000200,uint32_t))  /* OUTCLK Buffer Status */
-#define BITM_CGU_STAT_DCBF                   (_ADI_MSK(0x00000100,uint32_t))  /* DCLK Buffer Status */
-#define BITM_CGU_STAT_SCBF1                  (_ADI_MSK(0x00000080,uint32_t))  /* SCLK1 Buffer Status */
-#define BITM_CGU_STAT_SCBF0                  (_ADI_MSK(0x00000040,uint32_t))  /* SCLK0 Buffer Status */
-#define BITM_CGU_STAT_CCBF1                  (_ADI_MSK(0x00000020,uint32_t))  /* CCLK1 Buffer Status */
-#define BITM_CGU_STAT_CCBF0                  (_ADI_MSK(0x00000010,uint32_t))  /* CCLK0 Buffer Status */
-#define BITM_CGU_STAT_CLKSALGN               (_ADI_MSK(0x00000008,uint32_t))  /* Clock Alignment */
-#define BITM_CGU_STAT_PLOCK                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Lock */
-#define BITM_CGU_STAT_PLLBP                  (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass */
-#define BITM_CGU_STAT_PLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* PLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_DIV                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_DIV_LOCK                    31                               /* Lock */
-#define BITP_CGU_DIV_UPDT                    30                               /* Update Clock Divisors */
-#define BITP_CGU_DIV_ALGN                    29                               /* Align */
-#define BITP_CGU_DIV_OSEL                    22                               /* OUTCLK Divisor */
-#define BITP_CGU_DIV_DSEL                    16                               /* DCLK Divisor */
-#define BITP_CGU_DIV_S1SEL                   13                               /* SCLK 1 Divisor */
-#define BITP_CGU_DIV_SYSSEL                   8                               /* SYSCLK Divisor */
-#define BITP_CGU_DIV_S0SEL                    5                               /* SCLK 0 Divisor */
-#define BITP_CGU_DIV_CSEL                     0                               /* CCLK Divisor */
-#define BITM_CGU_DIV_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_DIV_UPDT                    (_ADI_MSK(0x40000000,uint32_t))  /* Update Clock Divisors */
-#define BITM_CGU_DIV_ALGN                    (_ADI_MSK(0x20000000,uint32_t))  /* Align */
-
-#define BITM_CGU_DIV_OSEL                    (_ADI_MSK(0x1FC00000,uint32_t))  /* OUTCLK Divisor */
-#define ENUM_CGU_DIV_OSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* OSEL: OSEL = 1 to 127 */
-
-#define BITM_CGU_DIV_DSEL                    (_ADI_MSK(0x001F0000,uint32_t))  /* DCLK Divisor */
-#define ENUM_CGU_DIV_DSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* DSEL: DSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S1SEL                   (_ADI_MSK(0x0000E000,uint32_t))  /* SCLK 1 Divisor */
-#define ENUM_CGU_DIV_S1SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S1SEL: S1SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_SYSSEL                  (_ADI_MSK(0x00001F00,uint32_t))  /* SYSCLK Divisor */
-#define ENUM_CGU_DIV_SYSSEL1TO31             (_ADI_MSK(0x00000000,uint32_t))  /* SYSSEL: SYSSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S0SEL                   (_ADI_MSK(0x000000E0,uint32_t))  /* SCLK 0 Divisor */
-#define ENUM_CGU_DIV_S0SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S0SEL: S0SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_CSEL                    (_ADI_MSK(0x0000001F,uint32_t))  /* CCLK Divisor */
-#define ENUM_CGU_DIV_CSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* CSEL: CSEL= 1 to 31 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CLKOUTSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CLKOUTSEL_LOCK              31                               /* Lock */
-#define BITP_CGU_CLKOUTSEL_CLKOUTSEL          0                               /* CLKOUT Select */
-
-#define BITM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_CGU_CLKOUTSEL_UNLOCK            (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_CGU_CLKOUTSEL_CLKOUTSEL         (_ADI_MSK(0x0000000F,uint32_t))  /* CLKOUT Select */
-#define ENUM_CGU_CLKOUTSEL_CLKIN             (_ADI_MSK(0x00000000,uint32_t))  /* CLKOUTSEL: CLKIN */
-#define ENUM_CGU_CLKOUTSEL_CCLKDIV4          (_ADI_MSK(0x00000001,uint32_t))  /* CLKOUTSEL: CCLKn/4 */
-#define ENUM_CGU_CLKOUTSEL_GNDDIS            (_ADI_MSK(0x0000000B,uint32_t))  /* CLKOUTSEL: GND (Disable OUTCLK) */
-#define ENUM_CGU_CLKOUTSEL_SYSCLKDIV2        (_ADI_MSK(0x00000002,uint32_t))  /* CLKOUTSEL: SYSCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_SCLK0             (_ADI_MSK(0x00000003,uint32_t))  /* CLKOUTSEL: SCLK0 */
-#define ENUM_CGU_CLKOUTSEL_SCLK1             (_ADI_MSK(0x00000004,uint32_t))  /* CLKOUTSEL: SCLK1 */
-#define ENUM_CGU_CLKOUTSEL_DCLKDIV2          (_ADI_MSK(0x00000005,uint32_t))  /* CLKOUTSEL: DCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_OUTCLK            (_ADI_MSK(0x00000007,uint32_t))  /* CLKOUTSEL: OUTCLK */
-
-/* ==================================================
-        Dynamic Power Management Registers
-   ================================================== */
-
-/* =========================
-        DPM0
-   ========================= */
-#define REG_DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
-#define REG_DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
-#define REG_DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
-#define REG_DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
-#define REG_DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
-#define REG_DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
-#define REG_DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
-#define REG_DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
-#define REG_DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
-#define REG_DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
-#define REG_DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
-#define REG_DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
-#define REG_DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore n Register */
-
-/* =========================
-        DPM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CTL_LOCK                    31                               /* Lock */
-#define BITP_DPM_CTL_HIBERNATE                4                               /* Hibernate */
-#define BITP_DPM_CTL_DEEPSLEEP                3                               /* Deep Sleep */
-#define BITP_DPM_CTL_PLLDIS                   2                               /* PLL Disable */
-#define BITP_DPM_CTL_PLLBPCL                  1                               /* PLL Bypass Clear */
-#define BITP_DPM_CTL_PLLBPST                  0                               /* PLL Bypass Set */
-#define BITM_DPM_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CTL_HIBERNATE               (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate */
-#define BITM_DPM_CTL_DEEPSLEEP               (_ADI_MSK(0x00000008,uint32_t))  /* Deep Sleep */
-#define BITM_DPM_CTL_PLLDIS                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Disable */
-#define BITM_DPM_CTL_PLLBPCL                 (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass Clear */
-#define BITM_DPM_CTL_PLLBPST                 (_ADI_MSK(0x00000001,uint32_t))  /* PLL Bypass Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_STAT_PLLCFGERR              19                               /* PLL Configuration Error */
-#define BITP_DPM_STAT_HVBSYERR               18                               /* HV Busy Error */
-#define BITP_DPM_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_DPM_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_DPM_STAT_HVBSY                   9                               /* HV Busy */
-#define BITP_DPM_STAT_CCLKDIS                 8                               /* Core Clock(s) Disabled */
-#define BITP_DPM_STAT_PRVMODE                 4                               /* Previous Mode */
-#define BITP_DPM_STAT_CURMODE                 0                               /* Current Mode */
-#define BITM_DPM_STAT_PLLCFGERR              (_ADI_MSK(0x00080000,uint32_t))  /* PLL Configuration Error */
-#define BITM_DPM_STAT_HVBSYERR               (_ADI_MSK(0x00040000,uint32_t))  /* HV Busy Error */
-#define BITM_DPM_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_DPM_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_DPM_STAT_HVBSY                  (_ADI_MSK(0x00000200,uint32_t))  /* HV Busy */
-#define BITM_DPM_STAT_CCLKDIS                (_ADI_MSK(0x00000100,uint32_t))  /* Core Clock(s) Disabled */
-#define BITM_DPM_STAT_PRVMODE                (_ADI_MSK(0x000000F0,uint32_t))  /* Previous Mode */
-#define BITM_DPM_STAT_CURMODE                (_ADI_MSK(0x0000000F,uint32_t))  /* Current Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_CCBF_DIS_CCBF0               0                               /* Core Clock Buffer n Disable */
-#define BITP_DPM_CCBF_DIS_CCBF1               1                               /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_DIS_CCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_CCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_CCBF_EN_CCBF0                0                               /* Core Clock Buffer n Enable */
-#define BITP_DPM_CCBF_EN_CCBF1                1                               /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_EN_CCBF0               (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_CCBF1               (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_CCBF0              0                               /* Core Clock Buffer n Status */
-#define BITP_DPM_CCBF_STAT_CCBF1              1                               /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF0             (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF1             (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT_STKY                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF0         0                               /* Core Clock Buffer n Status - Sticky */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF1         1                               /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF0        (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF1        (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_SCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_SCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_SCBF_DIS_SCBF0               0                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF1               1                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF2               2                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF3               3                               /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_SCBF_DIS_SCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF2              (_ADI_MSK(0x00000004,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF3              (_ADI_MSK(0x00000008,uint32_t))  /* System Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_WAKE_EN_WS0                  0                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS1                  1                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS2                  2                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS3                  3                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS4                  4                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS5                  5                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS6                  6                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS7                  7                               /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_EN_WS0                 (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS1                 (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS2                 (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS3                 (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS4                 (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS5                 (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS6                 (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS7                 (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_POL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_POL_LOCK               31                               /* Lock */
-#define BITP_DPM_WAKE_POL_WS0                 0                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS1                 1                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS2                 2                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS3                 3                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS4                 4                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS5                 5                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS6                 6                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS7                 7                               /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_POL_WS0                (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS1                (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS2                (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS3                (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS4                (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS5                (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS6                (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS7                (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Polarity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_STAT_WS0                0                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS1                1                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS2                2                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS3                3                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS4                4                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS5                5                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS6                6                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS7                7                               /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS0               (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS1               (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS2               (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS3               (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS4               (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS5               (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS6               (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS7               (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_HIB_DIS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_HIB_DIS_LOCK                31                               /* Lock */
-#define BITP_DPM_HIB_DIS_HD0                  0                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD1                  1                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD2                  2                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD3                  3                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD4                  4                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD5                  5                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD6                  6                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD7                  7                               /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_HIB_DIS_HD0                 (_ADI_MSK(0x00000001,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD1                 (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD2                 (_ADI_MSK(0x00000004,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD3                 (_ADI_MSK(0x00000008,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD4                 (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD5                 (_ADI_MSK(0x00000020,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD6                 (_ADI_MSK(0x00000040,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD7                 (_ADI_MSK(0x00000080,uint32_t))  /* Hibernate Disable n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_PGCNTR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_PGCNTR_LOCK                 31                               /* Lock */
-#define BITP_DPM_PGCNTR_CNT                   0                               /* Power Good Count */
-#define BITM_DPM_PGCNTR_LOCK                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_PGCNTR_CNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Power Good Count */
-
-/* ==================================================
-        eFUSE Controller Registers
-   ================================================== */
-
-/* =========================
-        EFS0
-   ========================= */
-#define REG_EFS0_CTL                    0xFFCC0000         /* EFS0 Control Register */
-#define REG_EFS0_DAT0                   0xFFCC0008         /* EFS0 Data Register 0 */
-#define REG_EFS0_DAT1                   0xFFCC000C         /* EFS0 Data Register 1 */
-#define REG_EFS0_DAT2                   0xFFCC0010         /* EFS0 Data Register 2 */
-#define REG_EFS0_DAT3                   0xFFCC0014         /* EFS0 Data Register 3 */
-#define REG_EFS0_DAT4                   0xFFCC0018         /* EFS0 Data Register 4 */
-#define REG_EFS0_DAT5                   0xFFCC001C         /* EFS0 Data Register 5 */
-#define REG_EFS0_DAT6                   0xFFCC0020         /* EFS0 Data Register 6 */
-#define REG_EFS0_DAT7                   0xFFCC0024         /* EFS0 Data Register 7 */
-
-/* =========================
-        EFS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EFS_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EFS_CTL_READ                     0                               /* Read */
-#define BITM_EFS_CTL_READ                    (_ADI_MSK(0x00000001,uint32_t))  /* Read */
-
-/* ==================================================
-        Universal Serial Bus Controller Registers
-   ================================================== */
-
-/* =========================
-        USB0
-   ========================= */
-#define REG_USB0_FADDR                  0xFFCC1000         /* USB0 Function Address Register */
-#define REG_USB0_POWER                  0xFFCC1001         /* USB0 Power and Device Control Register */
-#define REG_USB0_INTRTX                 0xFFCC1002         /* USB0 Transmit Interrupt Register */
-#define REG_USB0_INTRRX                 0xFFCC1004         /* USB0 Receive Interrupt Register */
-#define REG_USB0_INTRTXE                0xFFCC1006         /* USB0 Transmit Interrupt Enable Register */
-#define REG_USB0_INTRRXE                0xFFCC1008         /* USB0 Receive Interrupt Enable Register */
-#define REG_USB0_IRQ                    0xFFCC100A         /* USB0 Common Interrupts Register */
-#define REG_USB0_IEN                    0xFFCC100B         /* USB0 Common Interrupts Enable Register */
-#define REG_USB0_FRAME                  0xFFCC100C         /* USB0 Frame Number Register */
-#define REG_USB0_INDEX                  0xFFCC100E         /* USB0 Index Register */
-#define REG_USB0_TESTMODE               0xFFCC100F         /* USB0 Testmode Register */
-#define REG_USB0_EPI_TXMAXP0            0xFFCC1010         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EPI_TXCSR_P0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EPI_TXCSR_H0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0I_CSR0_P            0xFFCC1012         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CSR0_H            0xFFCC1012         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXMAXP0            0xFFCC1014         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EPI_RXCSR_H0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXCSR_P0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CNT0              0xFFCC1018         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EPI_RXCNT0             0xFFCC1018         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EPI_TXTYPE0            0xFFCC101A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0I_TYPE0             0xFFCC101A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EPI_TXINTERVAL0        0xFFCC101B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0I_NAKLIMIT0         0xFFCC101B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EPI_RXTYPE0            0xFFCC101C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EPI_RXINTERVAL0        0xFFCC101D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0I_CFGDATA0          0xFFCC101F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_FIFOB0                 0xFFCC1020         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB1                 0xFFCC1024         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB2                 0xFFCC1028         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB3                 0xFFCC102C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB4                 0xFFCC1030         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB5                 0xFFCC1034         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB6                 0xFFCC1038         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB7                 0xFFCC103C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB8                 0xFFCC1040         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB9                 0xFFCC1044         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB10                0xFFCC1048         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB11                0xFFCC104C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOH0                 0xFFCC1020         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH1                 0xFFCC1024         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH2                 0xFFCC1028         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH3                 0xFFCC102C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH4                 0xFFCC1030         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH5                 0xFFCC1034         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH6                 0xFFCC1038         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH7                 0xFFCC103C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH8                 0xFFCC1040         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH9                 0xFFCC1044         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH10                0xFFCC1048         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH11                0xFFCC104C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFO0                  0xFFCC1020         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO1                  0xFFCC1024         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO2                  0xFFCC1028         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO3                  0xFFCC102C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO4                  0xFFCC1030         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO5                  0xFFCC1034         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO6                  0xFFCC1038         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO7                  0xFFCC103C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO8                  0xFFCC1040         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO9                  0xFFCC1044         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO10                 0xFFCC1048         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO11                 0xFFCC104C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_DEV_CTL                0xFFCC1060         /* USB0 Device Control Register */
-#define REG_USB0_TXFIFOSZ               0xFFCC1062         /* USB0 Transmit FIFO Size Register */
-#define REG_USB0_RXFIFOSZ               0xFFCC1063         /* USB0 Receive FIFO Size Register */
-#define REG_USB0_TXFIFOADDR             0xFFCC1064         /* USB0 Transmit FIFO Address Register */
-#define REG_USB0_RXFIFOADDR             0xFFCC1066         /* USB0 Receive FIFO Address Register */
-#define REG_USB0_EPINFO                 0xFFCC1078         /* USB0 Endpoint Information Register */
-#define REG_USB0_RAMINFO                0xFFCC1079         /* USB0 RAM Information Register */
-#define REG_USB0_LINKINFO               0xFFCC107A         /* USB0 Link Information Register */
-#define REG_USB0_VPLEN                  0xFFCC107B         /* USB0 VBUS Pulse Length Register */
-#define REG_USB0_HS_EOF1                0xFFCC107C         /* USB0 High-Speed EOF 1 Register */
-#define REG_USB0_FS_EOF1                0xFFCC107D         /* USB0 Full-Speed EOF 1 Register */
-#define REG_USB0_LS_EOF1                0xFFCC107E         /* USB0 Low-Speed EOF 1 Register */
-#define REG_USB0_SOFT_RST               0xFFCC107F         /* USB0 Software Reset Register */
-#define REG_USB0_MP0_TXFUNCADDR         0xFFCC1080         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP1_TXFUNCADDR         0xFFCC1088         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP2_TXFUNCADDR         0xFFCC1090         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP3_TXFUNCADDR         0xFFCC1098         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP4_TXFUNCADDR         0xFFCC10A0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP5_TXFUNCADDR         0xFFCC10A8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP6_TXFUNCADDR         0xFFCC10B0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP7_TXFUNCADDR         0xFFCC10B8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP8_TXFUNCADDR         0xFFCC10C0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP9_TXFUNCADDR         0xFFCC10C8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP10_TXFUNCADDR        0xFFCC10D0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP11_TXFUNCADDR        0xFFCC10D8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP0_TXHUBADDR          0xFFCC1082         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP1_TXHUBADDR          0xFFCC108A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP2_TXHUBADDR          0xFFCC1092         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP3_TXHUBADDR          0xFFCC109A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP4_TXHUBADDR          0xFFCC10A2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP5_TXHUBADDR          0xFFCC10AA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP6_TXHUBADDR          0xFFCC10B2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP7_TXHUBADDR          0xFFCC10BA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP8_TXHUBADDR          0xFFCC10C2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP9_TXHUBADDR          0xFFCC10CA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP10_TXHUBADDR         0xFFCC10D2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP11_TXHUBADDR         0xFFCC10DA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP0_TXHUBPORT          0xFFCC1083         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP1_TXHUBPORT          0xFFCC108B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP2_TXHUBPORT          0xFFCC1093         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP3_TXHUBPORT          0xFFCC109B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP4_TXHUBPORT          0xFFCC10A3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP5_TXHUBPORT          0xFFCC10AB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP6_TXHUBPORT          0xFFCC10B3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP7_TXHUBPORT          0xFFCC10BB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP8_TXHUBPORT          0xFFCC10C3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP9_TXHUBPORT          0xFFCC10CB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP10_TXHUBPORT         0xFFCC10D3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP11_TXHUBPORT         0xFFCC10DB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP0_RXFUNCADDR         0xFFCC1084         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP1_RXFUNCADDR         0xFFCC108C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP2_RXFUNCADDR         0xFFCC1094         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP3_RXFUNCADDR         0xFFCC109C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP4_RXFUNCADDR         0xFFCC10A4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP5_RXFUNCADDR         0xFFCC10AC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP6_RXFUNCADDR         0xFFCC10B4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP7_RXFUNCADDR         0xFFCC10BC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP8_RXFUNCADDR         0xFFCC10C4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP9_RXFUNCADDR         0xFFCC10CC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP10_RXFUNCADDR        0xFFCC10D4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP11_RXFUNCADDR        0xFFCC10DC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP0_RXHUBADDR          0xFFCC1086         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP1_RXHUBADDR          0xFFCC108E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP2_RXHUBADDR          0xFFCC1096         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP3_RXHUBADDR          0xFFCC109E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP4_RXHUBADDR          0xFFCC10A6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP5_RXHUBADDR          0xFFCC10AE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP6_RXHUBADDR          0xFFCC10B6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP7_RXHUBADDR          0xFFCC10BE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP8_RXHUBADDR          0xFFCC10C6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP9_RXHUBADDR          0xFFCC10CE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP10_RXHUBADDR         0xFFCC10D6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP11_RXHUBADDR         0xFFCC10DE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP0_RXHUBPORT          0xFFCC1087         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP1_RXHUBPORT          0xFFCC108F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP2_RXHUBPORT          0xFFCC1097         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP3_RXHUBPORT          0xFFCC109F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP4_RXHUBPORT          0xFFCC10A7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP5_RXHUBPORT          0xFFCC10AF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP6_RXHUBPORT          0xFFCC10B7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP7_RXHUBPORT          0xFFCC10BF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP8_RXHUBPORT          0xFFCC10C7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP9_RXHUBPORT          0xFFCC10CF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP10_RXHUBPORT         0xFFCC10D7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP11_RXHUBPORT         0xFFCC10DF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_EP0_TXMAXP             0xFFCC1100         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP1_TXMAXP             0xFFCC1110         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP2_TXMAXP             0xFFCC1120         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP3_TXMAXP             0xFFCC1130         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP4_TXMAXP             0xFFCC1140         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP5_TXMAXP             0xFFCC1150         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP6_TXMAXP             0xFFCC1160         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP7_TXMAXP             0xFFCC1170         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP8_TXMAXP             0xFFCC1180         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP9_TXMAXP             0xFFCC1190         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP10_TXMAXP            0xFFCC11A0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP11_TXMAXP            0xFFCC11B0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP0_CSR0_H             0xFFCC1102         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EP0_TXCSR_H            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP1_TXCSR_H            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP2_TXCSR_H            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP3_TXCSR_H            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP4_TXCSR_H            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP5_TXCSR_H            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP6_TXCSR_H            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP7_TXCSR_H            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP8_TXCSR_H            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP9_TXCSR_H            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP10_TXCSR_H           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP11_TXCSR_H           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0_CSR0_P             0xFFCC1102         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_TXCSR_P            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_TXCSR_P            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_TXCSR_P            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_TXCSR_P            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_TXCSR_P            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_TXCSR_P            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_TXCSR_P            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_TXCSR_P            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_TXCSR_P            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_TXCSR_P            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_TXCSR_P           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_TXCSR_P           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_RXMAXP             0xFFCC1104         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP1_RXMAXP             0xFFCC1114         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP2_RXMAXP             0xFFCC1124         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP3_RXMAXP             0xFFCC1134         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP4_RXMAXP             0xFFCC1144         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP5_RXMAXP             0xFFCC1154         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP6_RXMAXP             0xFFCC1164         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP7_RXMAXP             0xFFCC1174         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP8_RXMAXP             0xFFCC1184         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP9_RXMAXP             0xFFCC1194         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP10_RXMAXP            0xFFCC11A4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP11_RXMAXP            0xFFCC11B4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP0_RXCSR_H            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP1_RXCSR_H            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP2_RXCSR_H            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP3_RXCSR_H            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP4_RXCSR_H            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP5_RXCSR_H            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP6_RXCSR_H            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP7_RXCSR_H            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP8_RXCSR_H            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP9_RXCSR_H            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP10_RXCSR_H           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP11_RXCSR_H           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP0_RXCSR_P            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_RXCSR_P            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_RXCSR_P            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_RXCSR_P            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_RXCSR_P            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_RXCSR_P            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_RXCSR_P            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_RXCSR_P            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_RXCSR_P            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_RXCSR_P            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_RXCSR_P           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_RXCSR_P           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_CNT0               0xFFCC1108         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EP0_RXCNT              0xFFCC1108         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP1_RXCNT              0xFFCC1118         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP2_RXCNT              0xFFCC1128         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP3_RXCNT              0xFFCC1138         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP4_RXCNT              0xFFCC1148         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP5_RXCNT              0xFFCC1158         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP6_RXCNT              0xFFCC1168         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP7_RXCNT              0xFFCC1178         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP8_RXCNT              0xFFCC1188         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP9_RXCNT              0xFFCC1198         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP10_RXCNT             0xFFCC11A8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP11_RXCNT             0xFFCC11B8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP0_TYPE0              0xFFCC110A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EP0_TXTYPE             0xFFCC110A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP1_TXTYPE             0xFFCC111A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP2_TXTYPE             0xFFCC112A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP3_TXTYPE             0xFFCC113A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP4_TXTYPE             0xFFCC114A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP5_TXTYPE             0xFFCC115A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP6_TXTYPE             0xFFCC116A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP7_TXTYPE             0xFFCC117A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP8_TXTYPE             0xFFCC118A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP9_TXTYPE             0xFFCC119A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP10_TXTYPE            0xFFCC11AA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP11_TXTYPE            0xFFCC11BA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0_NAKLIMIT0          0xFFCC110B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EP0_TXINTERVAL         0xFFCC110B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP1_TXINTERVAL         0xFFCC111B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP2_TXINTERVAL         0xFFCC112B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP3_TXINTERVAL         0xFFCC113B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP4_TXINTERVAL         0xFFCC114B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP5_TXINTERVAL         0xFFCC115B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP6_TXINTERVAL         0xFFCC116B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP7_TXINTERVAL         0xFFCC117B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP8_TXINTERVAL         0xFFCC118B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP9_TXINTERVAL         0xFFCC119B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP10_TXINTERVAL        0xFFCC11AB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP11_TXINTERVAL        0xFFCC11BB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0_RXTYPE             0xFFCC110C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP1_RXTYPE             0xFFCC111C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP2_RXTYPE             0xFFCC112C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP3_RXTYPE             0xFFCC113C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP4_RXTYPE             0xFFCC114C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP5_RXTYPE             0xFFCC115C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP6_RXTYPE             0xFFCC116C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP7_RXTYPE             0xFFCC117C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP8_RXTYPE             0xFFCC118C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP9_RXTYPE             0xFFCC119C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP10_RXTYPE            0xFFCC11AC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP11_RXTYPE            0xFFCC11BC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP0_RXINTERVAL         0xFFCC110D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP1_RXINTERVAL         0xFFCC111D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP2_RXINTERVAL         0xFFCC112D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP3_RXINTERVAL         0xFFCC113D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP4_RXINTERVAL         0xFFCC114D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP5_RXINTERVAL         0xFFCC115D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP6_RXINTERVAL         0xFFCC116D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP7_RXINTERVAL         0xFFCC117D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP8_RXINTERVAL         0xFFCC118D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP9_RXINTERVAL         0xFFCC119D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP10_RXINTERVAL        0xFFCC11AD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP11_RXINTERVAL        0xFFCC11BD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0_CFGDATA0           0xFFCC110F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_DMA_IRQ                0xFFCC1200         /* USB0 DMA Interrupt Register */
-#define REG_USB0_DMA0_CTL               0xFFCC1204         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA1_CTL               0xFFCC1214         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA2_CTL               0xFFCC1224         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA3_CTL               0xFFCC1234         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA4_CTL               0xFFCC1244         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA5_CTL               0xFFCC1254         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA6_CTL               0xFFCC1264         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA7_CTL               0xFFCC1274         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA0_ADDR              0xFFCC1208         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA1_ADDR              0xFFCC1218         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA2_ADDR              0xFFCC1228         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA3_ADDR              0xFFCC1238         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA4_ADDR              0xFFCC1248         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA5_ADDR              0xFFCC1258         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA6_ADDR              0xFFCC1268         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA7_ADDR              0xFFCC1278         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA0_CNT               0xFFCC120C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA1_CNT               0xFFCC121C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA2_CNT               0xFFCC122C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA3_CNT               0xFFCC123C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA4_CNT               0xFFCC124C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA5_CNT               0xFFCC125C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA6_CNT               0xFFCC126C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA7_CNT               0xFFCC127C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_RQPKTCNT0              0xFFCC1300         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT1              0xFFCC1304         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT2              0xFFCC1308         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT3              0xFFCC130C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT4              0xFFCC1310         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT5              0xFFCC1314         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT6              0xFFCC1318         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT7              0xFFCC131C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT8              0xFFCC1320         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT9              0xFFCC1324         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT10             0xFFCC1328         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_CT_UCH                 0xFFCC1344         /* USB0 Chirp Timeout Register */
-#define REG_USB0_CT_HHSRTN              0xFFCC1346         /* USB0 Host High Speed Return to Normal Register */
-#define REG_USB0_CT_HSBT                0xFFCC1348         /* USB0 High Speed Timeout Register */
-#define REG_USB0_LPM_ATTR               0xFFCC1360         /* USB0 LPM Attribute Register */
-#define REG_USB0_LPM_CTL                0xFFCC1362         /* USB0 LPM Control Register */
-#define REG_USB0_LPM_IEN                0xFFCC1363         /* USB0 LPM Interrupt Enable Register */
-#define REG_USB0_LPM_IRQ                0xFFCC1364         /* USB0 LPM Interrupt Status Register */
-#define REG_USB0_LPM_FADDR              0xFFCC1365         /* USB0 LPM Function Address Register */
-#define REG_USB0_VBUS_CTL               0xFFCC1380         /* USB0 VBUS Control Register */
-#define REG_USB0_BAT_CHG                0xFFCC1381         /* USB0 Battery Charging Control Register */
-#define REG_USB0_PHY_CTL                0xFFCC1394         /* USB0 PHY Control Register */
-#define REG_USB0_PLL_OSC                0xFFCC1398         /* USB0 PLL and Oscillator Control Register */
-
-/* =========================
-        USB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FADDR                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FADDR_VALUE                  0                               /* Function Address Value */
-#define BITM_USB_FADDR_VALUE                 (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_POWER                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_POWER_ISOUPDT                7                               /* ISO Update Enable */
-#define BITP_USB_POWER_SOFTCONN               6                               /* Soft Connect/Disconnect Enable */
-#define BITP_USB_POWER_HSEN                   5                               /* High Speed Mode Enable */
-#define BITP_USB_POWER_HSMODE                 4                               /* High Speed Mode */
-#define BITP_USB_POWER_RESET                  3                               /* Reset USB */
-#define BITP_USB_POWER_RESUME                 2                               /* Resume Mode */
-#define BITP_USB_POWER_SUSPEND                1                               /* Suspend Mode */
-#define BITP_USB_POWER_SUSEN                  0                               /* SUSPENDM Output Enable */
-
-#define BITM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISO Update Enable */
-#define ENUM_USB_POWER_NO_ISOUPDT            (_ADI_MSK(0x00000000,uint8_t))   /* ISOUPDT: Disable ISO Update */
-#define ENUM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISOUPDT: Enable ISO Update */
-
-#define BITM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* Soft Connect/Disconnect Enable */
-#define ENUM_USB_POWER_NO_SOFTCONN           (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCONN: Disable Soft Connect/Disconnect */
-#define ENUM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* SOFTCONN: Enable Soft Connect/Disconnect */
-
-#define BITM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* High Speed Mode Enable */
-#define ENUM_USB_POWER_HSDIS                 (_ADI_MSK(0x00000000,uint8_t))   /* HSEN: Disable Negotiation for HS Mode */
-#define ENUM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* HSEN: Enable Negotiation for HS Mode */
-
-#define BITM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* High Speed Mode */
-#define ENUM_USB_POWER_NO_HSMODE             (_ADI_MSK(0x00000000,uint8_t))   /* HSMODE: Full Speed Mode (HS fail during reset) */
-#define ENUM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* HSMODE: High Speed Mode (HS success during reset) */
-
-#define BITM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* Reset USB */
-#define ENUM_USB_POWER_NO_RESET              (_ADI_MSK(0x00000000,uint8_t))   /* RESET: No Reset */
-#define ENUM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* RESET: Reset USB */
-
-#define BITM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* Resume Mode */
-#define ENUM_USB_POWER_NO_RESUME             (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Resume Signaling */
-#define ENUM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* RESUME: Enable Resume Signaling */
-
-#define BITM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* Suspend Mode */
-#define ENUM_USB_POWER_NO_SUSPEND            (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Suspend Mode (Host) */
-#define ENUM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* SUSPEND: Enable Suspend Mode (Host) */
-
-#define BITM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPENDM Output Enable */
-#define ENUM_USB_POWER_SUSDIS                (_ADI_MSK(0x00000000,uint8_t))   /* SUSEN: Disable SUSPENDM Output */
-#define ENUM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSEN: Enable SUSPENDM Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTX_EP11                 11                               /* End Point 11 Tx Interrupt */
-#define BITP_USB_INTRTX_EP10                 10                               /* End Point 10 Tx Interrupt */
-#define BITP_USB_INTRTX_EP9                   9                               /* End Point 9 Tx Interrupt */
-#define BITP_USB_INTRTX_EP8                   8                               /* End Point 8 Tx Interrupt */
-#define BITP_USB_INTRTX_EP7                   7                               /* End Point 7 Tx Interrupt */
-#define BITP_USB_INTRTX_EP6                   6                               /* End Point 6 Tx Interrupt */
-#define BITP_USB_INTRTX_EP5                   5                               /* End Point 5 Tx Interrupt */
-#define BITP_USB_INTRTX_EP4                   4                               /* End Point 4 Tx Interrupt */
-#define BITP_USB_INTRTX_EP3                   3                               /* End Point 3 Tx Interrupt */
-#define BITP_USB_INTRTX_EP2                   2                               /* End Point 2 Tx Interrupt */
-#define BITP_USB_INTRTX_EP1                   1                               /* End Point 1 Tx Interrupt */
-#define BITP_USB_INTRTX_EP0                   0                               /* End Point 0 Tx Interrupt */
-#define BITM_USB_INTRTX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt */
-#define BITM_USB_INTRTX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt */
-#define BITM_USB_INTRTX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt */
-#define BITM_USB_INTRTX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt */
-#define BITM_USB_INTRTX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt */
-#define BITM_USB_INTRTX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt */
-#define BITM_USB_INTRTX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt */
-#define BITM_USB_INTRTX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt */
-#define BITM_USB_INTRTX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt */
-#define BITM_USB_INTRTX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt */
-#define BITM_USB_INTRTX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt */
-#define BITM_USB_INTRTX_EP0                  (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRX_EP11                 11                               /* End Point 11 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP10                 10                               /* End Point 10 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP9                   9                               /* End Point 9 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP8                   8                               /* End Point 8 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP7                   7                               /* End Point 7 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP6                   6                               /* End Point 6 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP5                   5                               /* End Point 5 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP4                   4                               /* End Point 4 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP3                   3                               /* End Point 3 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP2                   2                               /* End Point 2 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP1                   1                               /* End Point 1 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTXE_EP11                11                               /* End Point 11 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP10                10                               /* End Point 10 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP9                  9                               /* End Point 9 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP8                  8                               /* End Point 8 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP7                  7                               /* End Point 7 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP6                  6                               /* End Point 6 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP5                  5                               /* End Point 5 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP4                  4                               /* End Point 4 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP3                  3                               /* End Point 3 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP2                  2                               /* End Point 2 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP1                  1                               /* End Point 1 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP0                  0                               /* End Point 0 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP0                 (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRXE_EP11                11                               /* End Point 11 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP10                10                               /* End Point 10 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP9                  9                               /* End Point 9 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP8                  8                               /* End Point 8 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP7                  7                               /* End Point 7 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP6                  6                               /* End Point 6 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP5                  5                               /* End Point 5 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP4                  4                               /* End Point 4 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP3                  3                               /* End Point 3 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP2                  2                               /* End Point 2 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP1                  1                               /* End Point 1 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IRQ                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IRQ_VBUSERR                  7                               /* VBUS Threshold Indicator */
-#define BITP_USB_IRQ_SESSREQ                  6                               /* Session Request Indicator */
-#define BITP_USB_IRQ_DISCON                   5                               /* Disconnect Indicator */
-#define BITP_USB_IRQ_CON                      4                               /* Connection Indicator */
-#define BITP_USB_IRQ_SOF                      3                               /* Start-of-frame Indicator */
-#define BITP_USB_IRQ_RSTBABBLE                2                               /* Reset/Babble Indicator */
-#define BITP_USB_IRQ_RESUME                   1                               /* Resume Indicator */
-#define BITP_USB_IRQ_SUSPEND                  0                               /* Suspend Indicator */
-
-#define BITM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator */
-#define ENUM_USB_IRQ_NO_VBUSERR              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: No Interrupt */
-#define ENUM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Interrupt Pending */
-
-#define BITM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator */
-#define ENUM_USB_IRQ_NO_SESSREQ              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: No Interrupt */
-#define ENUM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Interrupt Pending */
-
-#define BITM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator */
-#define ENUM_USB_IRQ_NO_DISCON               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: No Interrupt */
-#define ENUM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Interrupt Pending */
-
-#define BITM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator */
-#define ENUM_USB_IRQ_NO_CON                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: No Interrupt */
-#define ENUM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* CON: Interrupt Pending */
-
-#define BITM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator */
-#define ENUM_USB_IRQ_NO_SOF                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: No Interrupt */
-#define ENUM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Interrupt Pending */
-
-#define BITM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator */
-#define ENUM_USB_IRQ_NO_RSTBABBLE            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: No Interrupt */
-#define ENUM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Interrupt Pending */
-
-#define BITM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator */
-#define ENUM_USB_IRQ_NO_RESUME               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: No Interrupt */
-#define ENUM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Interrupt Pending */
-
-#define BITM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator */
-#define ENUM_USB_IRQ_NO_SUSPEND              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: No Interrupt */
-#define ENUM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IEN                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IEN_VBUSERR                  7                               /* VBUS Threshold Indicator Interrupt Enable */
-#define BITP_USB_IEN_SESSREQ                  6                               /* Session Request Indicator Interrupt Enable */
-#define BITP_USB_IEN_DISCON                   5                               /* Disconnect Indicator Interrupt Enable */
-#define BITP_USB_IEN_CON                      4                               /* Connection Indicator Interrupt Enable */
-#define BITP_USB_IEN_SOF                      3                               /* Start-of-frame Indicator Interrupt Enable */
-#define BITP_USB_IEN_RSTBABBLE                2                               /* Reset/Babble Indicator Interrupt Enable */
-#define BITP_USB_IEN_RESUME                   1                               /* Resume Indicator Interrupt Enable */
-#define BITP_USB_IEN_SUSPEND                  0                               /* Suspend Indicator Interrupt Enable */
-
-#define BITM_USB_IEN_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator Interrupt Enable */
-#define ENUM_USB_IEN_VBUSERRDIS              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: Disable Interrupt */
-#define ENUM_USB_IEN_VBUSERREN               (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Enable Interrupt */
-
-#define BITM_USB_IEN_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SESSREQDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: Disable Interrupt */
-#define ENUM_USB_IEN_SESSREQEN               (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Enable Interrupt */
-
-#define BITM_USB_IEN_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator Interrupt Enable */
-#define ENUM_USB_IEN_DISCONDIS               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: Disable Interrupt */
-#define ENUM_USB_IEN_DISCONEN                (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Enable Interrupt */
-
-#define BITM_USB_IEN_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator Interrupt Enable */
-#define ENUM_USB_IEN_CONDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: Disable Interrupt */
-#define ENUM_USB_IEN_CONEN                   (_ADI_MSK(0x00000010,uint8_t))   /* CON: Enable Interrupt */
-
-#define BITM_USB_IEN_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SOFDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: Disable Interrupt */
-#define ENUM_USB_IEN_SOFEN                   (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Enable Interrupt */
-
-#define BITM_USB_IEN_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RSTBABBLEDIS            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: Disable Interrupt */
-#define ENUM_USB_IEN_RSTBABBLEEN             (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Enable Interrupt */
-
-#define BITM_USB_IEN_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RESUMEDIS               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Interrupt */
-#define ENUM_USB_IEN_RESUMEEN                (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Enable Interrupt */
-
-#define BITM_USB_IEN_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SUSPENDDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Interrupt */
-#define ENUM_USB_IEN_SUSPENDEN               (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Enable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FRAME                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FRAME_VALUE                  0                               /* Frame Number Value */
-#define BITM_USB_FRAME_VALUE                 (_ADI_MSK(0x000007FF,uint16_t))  /* Frame Number Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INDEX                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INDEX_EP                     0                               /* Endpoint Index */
-#define BITM_USB_INDEX_EP                    (_ADI_MSK(0x0000000F,uint8_t))   /* Endpoint Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TESTMODE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TESTMODE_FIFOACCESS          6                               /* FIFO Access */
-#define BITP_USB_TESTMODE_TESTPACKET          3                               /* Test_Packet Mode */
-#define BITP_USB_TESTMODE_TESTK               2                               /* Test_K Mode */
-#define BITP_USB_TESTMODE_TESTJ               1                               /* Test_J Mode */
-#define BITP_USB_TESTMODE_TESTSE0NAK          0                               /* Test SE0 NAK */
-#define BITM_USB_TESTMODE_FIFOACCESS         (_ADI_MSK(0x00000040,uint8_t))   /* FIFO Access */
-#define BITM_USB_TESTMODE_TESTPACKET         (_ADI_MSK(0x00000008,uint8_t))   /* Test_Packet Mode */
-#define BITM_USB_TESTMODE_TESTK              (_ADI_MSK(0x00000004,uint8_t))   /* Test_K Mode */
-#define BITM_USB_TESTMODE_TESTJ              (_ADI_MSK(0x00000002,uint8_t))   /* Test_J Mode */
-#define BITM_USB_TESTMODE_TESTSE0NAK         (_ADI_MSK(0x00000001,uint8_t))   /* Test SE0 NAK */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_TXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_TXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_TXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_P_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_P_ISO             14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EPI_TXCSR_P_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_P_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_P_INCOMPTX         7                               /* Incomplete Tx */
-#define BITP_USB_EPI_TXCSR_P_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_SENTSTALL        5                               /* Sent STALL */
-#define BITP_USB_EPI_TXCSR_P_SENDSTALL        4                               /* Send STALL */
-#define BITP_USB_EPI_TXCSR_P_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_P_URUNERR          2                               /* Underrun Error */
-#define BITP_USB_EPI_TXCSR_P_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_P_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_P_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EPI_TXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EPI_TXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_P_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_P_INCOMPTX        (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EPI_TXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EPI_TXCSR_P_INCOMP          (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EPI_TXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_P_SENTSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_P_STALSNT         (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_TXCSR_P_SENDSTALL       (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EPI_TXCSR_P_STALL           (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EPI_TXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_P_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EPI_TXCSR_P_NO_URUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EPI_TXCSR_P_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FIFONE       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_P_FIFONE          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_P_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_H_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_H_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_H_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_H_DATGLEN          9                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_TXCSR_H_DATGL            8                               /* Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_NAKTOINCMP       7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EPI_TXCSR_H_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_RXSTALL          5                               /* Rx STALL */
-#define BITP_USB_EPI_TXCSR_H_SETUPPKT         4                               /* Setup Packet */
-#define BITP_USB_EPI_TXCSR_H_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXTOERR          2                               /* Tx Timeout Error */
-#define BITP_USB_EPI_TXCSR_H_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_H_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGLEN      (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EPI_TXCSR_H_NAKTOINCMP      (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EPI_TXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EPI_TXCSR_H_NAKTO           (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EPI_TXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_TXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EPI_TXCSR_H_NO_SETUPPK      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EPI_TXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_H_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EPI_TXCSR_H_NO_TXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_NEFIFO       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_H_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_P_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_P_SSETUPEND         7                               /* Service Setup End */
-#define BITP_USB_EP0I_CSR_P_SPKTRDY           6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_SENDSTALL         5                               /* Send Stall */
-#define BITP_USB_EP0I_CSR_P_SETUPEND          4                               /* Setup End */
-#define BITP_USB_EP0I_CSR_P_DATAEND           3                               /* Data End */
-#define BITP_USB_EP0I_CSR_P_SENTSTALL         2                               /* Sent Stall */
-#define BITP_USB_EP0I_CSR_P_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_P_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_P_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0I_CSR_P_NOSSETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_SPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0I_CSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0I_CSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0I_CSR_P_NO_SETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0I_CSR_P_NO_DATAEND       (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0I_CSR_P_SENTSTALL        (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_P_STALSNT          (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0I_CSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_H_DISPING          11                               /* Disable Ping */
-#define BITP_USB_EP0I_CSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0I_CSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP0I_CSR_H_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_H_NAKTO             7                               /* NAK Timeout */
-#define BITP_USB_EP0I_CSR_H_STATUSPKT         6                               /* Status Packet */
-#define BITP_USB_EP0I_CSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP0I_CSR_H_TOERR             4                               /* Timeout Error */
-#define BITP_USB_EP0I_CSR_H_SETUPPKT          3                               /* Setup Packet */
-#define BITP_USB_EP0I_CSR_H_RXSTALL           2                               /* Rx Stall */
-#define BITP_USB_EP0I_CSR_H_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0I_CSR_H_NO_DISPING       (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0I_CSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0I_CSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0I_CSR_H_NO_DATATGL       (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0I_CSR_H_DATATGL          (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0I_CSR_H_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_H_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0I_CSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0I_CSR_H_STATUSPKT        (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_STATPKT       (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_STATPKT          (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0I_CSR_H_NO_TOERR         (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_SETUPPKT      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0I_CSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_RXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_RXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_RXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_RXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_H_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_AUTOREQ         14                               /* Auto Request Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_H_PIDERR          12                               /* Packet ID Error */
-#define BITP_USB_EPI_RXCSR_H_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_H_DATGLEN         10                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_RXCSR_H_DATGL            9                               /* Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_H_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_RXSTALL          6                               /* Rx STALL */
-#define BITP_USB_EPI_RXCSR_H_REQPKT           5                               /* Request Packet */
-#define BITP_USB_EPI_RXCSR_H_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_H_NAKTODERR        3                               /* NAK Timeout Data Error */
-#define BITP_USB_EPI_RXCSR_H_RXTOERR          2                               /* Rx Timeout Error */
-#define BITP_USB_EPI_RXCSR_H_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_H_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOREQ      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_PIDERR       (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_RXCSR_H_DATGLDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EPI_RXCSR_H_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_H_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_H_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_H_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EPI_RXCSR_H_NO_REQPKT       (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EPI_RXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_H_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_H_NAKTODERR       (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_NAKTO           (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EPI_RXCSR_H_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_H_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_H_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_P_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_P_ISO             14                               /* Isochronous Transfers */
-#define BITP_USB_EPI_RXCSR_P_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_P_DNYETPERR       12                               /* Disable NYET Handshake */
-#define BITP_USB_EPI_RXCSR_P_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_P_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_P_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_P_SENTSTALL        6                               /* Sent STALL */
-#define BITP_USB_EPI_RXCSR_P_SENDSTALL        5                               /* Send STALL */
-#define BITP_USB_EPI_RXCSR_P_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_P_DATAERR          3                               /* Data Error */
-#define BITP_USB_EPI_RXCSR_P_ORUNERR          2                               /* OUT Run Error */
-#define BITP_USB_EPI_RXCSR_P_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_P_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_P_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EPI_RXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EPI_RXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_P_DNYETPERR       (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERREN       (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERRDIS      (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_P_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_P_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_P_SENTSTALL       (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_STALSNT         (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_RXCSR_P_SENDSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_STALL           (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_P_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_DATAERR      (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_ORUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EPI_RXCSR_P_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_P_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_P_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CNT_RXCNT               0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0I_CNT_RXCNT              (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCNT_EPRXCNT            0                               /* EP Rx Count */
-#define BITM_USB_EPI_RXCNT_EPRXCNT           (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_TXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_TXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_TXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_TXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_TXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_TXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_TXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_TXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_TXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_TXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_TXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_TXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_TXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_TXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_TYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_TYPE_SPEED              0                               /* Speed of Operation Value */
-#define BITM_USB_EP0I_TYPE_SPEED             (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_NAKLIMIT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_NAKLIMIT_VALUE          0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0I_NAKLIMIT_VALUE         (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_RXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_RXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_RXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_RXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_RXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_RXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_RXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_RXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_RXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_RXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_RXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_RXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_RXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_RXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CFGDATA                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CFGDATA_MPRX            7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_MPTX            6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_BIGEND          5                               /* Big Endian Data */
-#define BITP_USB_EP0I_CFGDATA_HBRX            4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_HBTX            3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_DYNFIFO         2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0I_CFGDATA_SOFTCON         1                               /* Soft Connect Enable */
-#define BITP_USB_EP0I_CFGDATA_UTMIWID         0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0I_CFGDATA_MPRX           (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPRXEN         (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_MPTX           (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPTXEN         (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_BIGEND         (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDDIS      (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDEN       (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0I_CFGDATA_HBRX           (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0I_CFGDATA_HBRXEN         (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0I_CFGDATA_HBTX           (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0I_CFGDATA_HBTXEN         (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0I_CFGDATA_DYNFIFO        (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZDIS       (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZEN        (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0I_CFGDATA_SOFTCON        (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONDIS      (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONEN       (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0I_CFGDATA_UTMIWID        (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID8       (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID16      (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DEV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DEV_CTL_BDEVICE              7                               /* A or B Devices Indicator */
-#define BITP_USB_DEV_CTL_FSDEV                6                               /* Full or High-Speed Indicator */
-#define BITP_USB_DEV_CTL_LSDEV                5                               /* Low-Speed Indicator */
-#define BITP_USB_DEV_CTL_VBUS                 3                               /* VBUS Level Indicator */
-#define BITP_USB_DEV_CTL_HOSTMODE             2                               /* Host Mode Indicator */
-#define BITP_USB_DEV_CTL_HOSTREQ              1                               /* Host Negotiation Request */
-#define BITP_USB_DEV_CTL_SESSION              0                               /* Session Indicator */
-
-#define BITM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* A or B Devices Indicator */
-#define ENUM_USB_DEV_CTL_ADEVICE             (_ADI_MSK(0x00000000,uint8_t))   /* BDEVICE: A Device Detected */
-#define ENUM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* BDEVICE: B Device Detected */
-
-#define BITM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* Full or High-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_FSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* FSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* FSDEV: Full or High Speed Detected */
-
-#define BITM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* Low-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_LSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* LSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* LSDEV: Low Speed Detected */
-
-#define BITM_USB_DEV_CTL_VBUS                (_ADI_MSK(0x00000018,uint8_t))   /* VBUS Level Indicator */
-#define ENUM_USB_DEV_CTL_VBUS_BS             (_ADI_MSK(0x00000000,uint8_t))   /* VBUS: Below SessionEnd */
-#define ENUM_USB_DEV_CTL_VBUS_ASBA           (_ADI_MSK(0x00000008,uint8_t))   /* VBUS: Above SessionEnd, below AValid */
-#define ENUM_USB_DEV_CTL_VBUS_AABV           (_ADI_MSK(0x00000010,uint8_t))   /* VBUS: Above AValid, below VBUSValid */
-#define ENUM_USB_DEV_CTL_VBUS_AV             (_ADI_MSK(0x00000018,uint8_t))   /* VBUS: Above VBUSValid */
-
-#define BITM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* Host Mode Indicator */
-#define ENUM_USB_DEV_CTL_NO_HOSTMODE         (_ADI_MSK(0x00000000,uint8_t))   /* HOSTMODE: Peripheral Mode */
-#define ENUM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* HOSTMODE: Host Mode */
-
-#define BITM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* Host Negotiation Request */
-#define ENUM_USB_DEV_CTL_NO_HOSTREQ          (_ADI_MSK(0x00000000,uint8_t))   /* HOSTREQ: No Request */
-#define ENUM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* HOSTREQ: Place Request */
-
-#define BITM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* Session Indicator */
-#define ENUM_USB_DEV_CTL_NO_SESSION          (_ADI_MSK(0x00000000,uint8_t))   /* SESSION: Not Detected */
-#define ENUM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* SESSION: Detected Session */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_TXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_TXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_TXFIFOSZ_DPNDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_TXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_TXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_TXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_TXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_TXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_TXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_TXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_TXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_TXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_TXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_TXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_TXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_RXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_RXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_RXFIFOSZ_DPBDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_RXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_RXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_RXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_RXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_RXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_RXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_RXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_RXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_RXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_RXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_RXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_RXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOADDR_VALUE             0                               /* Tx FIFO Start Address */
-#define BITM_USB_TXFIFOADDR_VALUE            (_ADI_MSK(0x00001FFF,uint16_t))  /* Tx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOADDR_VALUE             0                               /* Rx FIFO Start Address */
-#define BITM_USB_RXFIFOADDR_VALUE            (_ADI_MSK(0x00000FFF,uint16_t))  /* Rx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPINFO                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPINFO_RXEP                  4                               /* Rx Endpoints */
-#define BITP_USB_EPINFO_TXEP                  0                               /* Tx Endpoints */
-#define BITM_USB_EPINFO_RXEP                 (_ADI_MSK(0x000000F0,uint8_t))   /* Rx Endpoints */
-#define BITM_USB_EPINFO_TXEP                 (_ADI_MSK(0x0000000F,uint8_t))   /* Tx Endpoints */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RAMINFO                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RAMINFO_DMACHANS             4                               /* DMA Channels */
-#define BITP_USB_RAMINFO_RAMBITS              0                               /* RAM Address Bits */
-#define BITM_USB_RAMINFO_DMACHANS            (_ADI_MSK(0x000000F0,uint8_t))   /* DMA Channels */
-#define BITM_USB_RAMINFO_RAMBITS             (_ADI_MSK(0x0000000F,uint8_t))   /* RAM Address Bits */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LINKINFO                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LINKINFO_WTCON               4                               /* Wait for Connect/Disconnect */
-#define BITP_USB_LINKINFO_WTID                0                               /* Wait from ID Pull-up */
-#define BITM_USB_LINKINFO_WTCON              (_ADI_MSK(0x000000F0,uint8_t))   /* Wait for Connect/Disconnect */
-#define BITM_USB_LINKINFO_WTID               (_ADI_MSK(0x0000000F,uint8_t))   /* Wait from ID Pull-up */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_SOFT_RST                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_SOFT_RST_RSTX                1                               /* Reset USB XCLK Domain */
-#define BITP_USB_SOFT_RST_RST                 0                               /* Reset USB CLK Domain */
-
-#define BITM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* Reset USB XCLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RSTX            (_ADI_MSK(0x00000000,uint8_t))   /* RSTX: No Reset */
-#define ENUM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* RSTX: Reset USB XCLK Domain */
-
-#define BITM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* Reset USB CLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RST             (_ADI_MSK(0x00000000,uint8_t))   /* RST: No Reset */
-#define ENUM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* RST: Reset USB CLK Domain */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXFUNCADDR_VALUE          0                               /* Tx Function Address Value */
-#define BITM_USB_MP_TXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Tx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_TXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_TXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_TXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_TXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXFUNCADDR_VALUE          0                               /* Rx Function Address Value */
-#define BITM_USB_MP_RXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Rx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_RXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_RXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_RXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_RXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_TXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_TXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_TXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_H                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_H_DISPING           11                               /* Disable Ping */
-#define BITP_USB_EP0_CSR_H_DATGLEN           10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0_CSR_H_DATGL              9                               /* Data Toggle */
-#define BITP_USB_EP0_CSR_H_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_H_NAKTO              7                               /* NAK Timeout */
-#define BITP_USB_EP0_CSR_H_STATUSPKT          6                               /* Status Packet */
-#define BITP_USB_EP0_CSR_H_REQPKT             5                               /* Request Packet */
-#define BITP_USB_EP0_CSR_H_TOERR              4                               /* Timeout Error */
-#define BITP_USB_EP0_CSR_H_SETUPPKT           3                               /* Setup Packet */
-#define BITP_USB_EP0_CSR_H_RXSTALL            2                               /* Rx Stall */
-#define BITP_USB_EP0_CSR_H_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_H_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0_CSR_H_NO_DISPING        (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0_CSR_H_NO_DATGLEN        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0_CSR_H_DATGL             (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0_CSR_H_NO_DATATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0_CSR_H_DATATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0_CSR_H_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_H_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_H_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0_CSR_H_NO_NAKTO          (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0_CSR_H_STATUSPKT         (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0_CSR_H_NO_STATPKT        (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_STATPKT           (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0_CSR_H_NO_REQPKT         (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0_CSR_H_NO_TOERR          (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0_CSR_H_NO_SETUPPKT       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0_CSR_H_NO_RXSTALL        (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_RXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_H_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_H_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_H_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_H_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_H_DATGLEN           9                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_TXCSR_H_DATGL             8                               /* Data Toggle */
-#define BITP_USB_EP_TXCSR_H_NAKTOINCMP        7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EP_TXCSR_H_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_H_RXSTALL           5                               /* Rx STALL */
-#define BITP_USB_EP_TXCSR_H_SETUPPKT          4                               /* Setup Packet */
-#define BITP_USB_EP_TXCSR_H_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_H_TXTOERR           2                               /* Tx Timeout Error */
-#define BITP_USB_EP_TXCSR_H_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_H_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_H_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EP_TXCSR_H_NAKTOINCMP       (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EP_TXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EP_TXCSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EP_TXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_TXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP_TXCSR_H_NO_SETUPPK       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EP_TXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_H_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EP_TXCSR_H_NO_TXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_NEFIFO        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_H_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_P                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_P_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_P_SSETUPEND          7                               /* Service Setup End */
-#define BITP_USB_EP0_CSR_P_SPKTRDY            6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0_CSR_P_SENDSTALL          5                               /* Send Stall */
-#define BITP_USB_EP0_CSR_P_SETUPEND           4                               /* Setup End */
-#define BITP_USB_EP0_CSR_P_DATAEND            3                               /* Data End */
-#define BITP_USB_EP0_CSR_P_SENTSTALL          2                               /* Sent Stall */
-#define BITP_USB_EP0_CSR_P_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_P_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_P_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_P_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_P_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0_CSR_P_NOSSETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_SPKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0_CSR_P_SENDSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALL          (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0_CSR_P_STALL             (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0_CSR_P_NO_SETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0_CSR_P_NO_DATAEND        (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0_CSR_P_SENTSTALL         (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALSNT        (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0_CSR_P_STALSNT           (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0_CSR_P_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_PKTRDY         (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_P_PKTRDY            (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_P_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_P_ISO              14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EP_TXCSR_P_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_P_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_P_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_P_INCOMPTX          7                               /* Incomplete Tx */
-#define BITP_USB_EP_TXCSR_P_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_P_SENTSTALL         5                               /* Sent STALL */
-#define BITP_USB_EP_TXCSR_P_SENDSTALL         4                               /* Send STALL */
-#define BITP_USB_EP_TXCSR_P_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_P_URUNERR           2                               /* Underrun Error */
-#define BITP_USB_EP_TXCSR_P_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_P_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_P_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EP_TXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EP_TXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_P_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_P_INCOMPTX         (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EP_TXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EP_TXCSR_P_INCOMP           (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EP_TXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_P_SENTSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_P_STALSNT          (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_TXCSR_P_SENDSTALL        (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EP_TXCSR_P_STALL            (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EP_TXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_P_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EP_TXCSR_P_NO_URUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EP_TXCSR_P_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FIFONE        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_P_FIFONE           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_P_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_RXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_RXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_RXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_H_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_H_AUTOREQ          14                               /* Auto Request Clear Enable */
-#define BITP_USB_EP_RXCSR_H_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_H_PIDERR           12                               /* Packet ID Error */
-#define BITP_USB_EP_RXCSR_H_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_RXCSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP_RXCSR_H_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_H_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_H_RXSTALL           6                               /* Rx STALL */
-#define BITP_USB_EP_RXCSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP_RXCSR_H_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_H_NAKTODERR         3                               /* NAK Timeout Data Error */
-#define BITP_USB_EP_RXCSR_H_RXTOERR           2                               /* Rx Timeout Error */
-#define BITP_USB_EP_RXCSR_H_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOREQ       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EP_RXCSR_H_NO_PIDERR        (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_RXCSR_H_DATGLDIS         (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP_RXCSR_H_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_H_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_H_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_H_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_RXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP_RXCSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP_RXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_H_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_H_NAKTODERR        (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EP_RXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_NAKTO            (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EP_RXCSR_H_NO_RXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EP_RXCSR_H_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_H_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_H_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_P_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_P_ISO              14                               /* Isochronous Transfers */
-#define BITP_USB_EP_RXCSR_P_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_P_DNYETPERR        12                               /* Disable NYET Handshake */
-#define BITP_USB_EP_RXCSR_P_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_P_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_P_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_P_SENTSTALL         6                               /* Sent STALL */
-#define BITP_USB_EP_RXCSR_P_SENDSTALL         5                               /* Send STALL */
-#define BITP_USB_EP_RXCSR_P_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_P_DATAERR           3                               /* Data Error */
-#define BITP_USB_EP_RXCSR_P_ORUNERR           2                               /* OUT Run Error */
-#define BITP_USB_EP_RXCSR_P_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_P_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EP_RXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EP_RXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_P_DNYETPERR        (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERREN        (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERRDIS       (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_P_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_P_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_P_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_P_SENTSTALL        (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_P_STALSNT          (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_RXCSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP_RXCSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EP_RXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_P_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EP_RXCSR_P_NO_DATAERR       (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EP_RXCSR_P_NO_ORUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EP_RXCSR_P_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_P_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_P_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CNT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CNT_RXCNT                0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0_CNT_RXCNT               (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCNT_EPRXCNT             0                               /* EP Rx Count */
-#define BITM_USB_EP_RXCNT_EPRXCNT            (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_TYPE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_TYPE_SPEED               0                               /* Speed of Operation Value */
-#define BITM_USB_EP0_TYPE_SPEED              (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_TXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_TXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_TXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_TXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_TXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_TXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_TXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_TXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_TXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_TXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_TXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_TXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_TXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_TXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_TXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_TXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_TXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_TXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_TXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_TXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_TXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_TXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_TXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_TXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_TXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_TXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_TXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_TXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_TXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_NAKLIMIT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_NAKLIMIT_VALUE           0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0_NAKLIMIT_VALUE          (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_RXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_RXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_RXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_RXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_RXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_RXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_RXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_RXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_RXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_RXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_RXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_RXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_RXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_RXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_RXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_RXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_RXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_RXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_RXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_RXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_RXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_RXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_RXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_RXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_RXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_RXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_RXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_RXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_RXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CFGDATA                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CFGDATA_MPRX             7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0_CFGDATA_MPTX             6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0_CFGDATA_BIGEND           5                               /* Big Endian Data */
-#define BITP_USB_EP0_CFGDATA_HBRX             4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0_CFGDATA_HBTX             3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0_CFGDATA_DYNFIFO          2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0_CFGDATA_SOFTCON          1                               /* Soft Connect Enable */
-#define BITP_USB_EP0_CFGDATA_UTMIWID          0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0_CFGDATA_MPRX            (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPRXEN          (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_MPTX            (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPTXEN          (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_BIGEND          (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0_CFGDATA_BIGENDDIS       (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0_CFGDATA_BIGENDEN        (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0_CFGDATA_HBRX            (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0_CFGDATA_HBRXEN          (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0_CFGDATA_HBTX            (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0_CFGDATA_HBTXEN          (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0_CFGDATA_DYNFIFO         (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0_CFGDATA_DYNSZDIS        (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0_CFGDATA_DYNSZEN         (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0_CFGDATA_SOFTCON         (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0_CFGDATA_SFTCONDIS       (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0_CFGDATA_SFTCONEN        (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0_CFGDATA_UTMIWID         (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID8        (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID16       (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_IRQ_D7                   7                               /* DMA 7 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D6                   6                               /* DMA 6 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D5                   5                               /* DMA 5 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D4                   4                               /* DMA 4 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D3                   3                               /* DMA 3 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D2                   2                               /* DMA 2 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D1                   1                               /* DMA 1 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D0                   0                               /* DMA 0 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D7                  (_ADI_MSK(0x00000080,uint8_t))   /* DMA 7 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D6                  (_ADI_MSK(0x00000040,uint8_t))   /* DMA 6 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D5                  (_ADI_MSK(0x00000020,uint8_t))   /* DMA 5 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D4                  (_ADI_MSK(0x00000010,uint8_t))   /* DMA 4 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D3                  (_ADI_MSK(0x00000008,uint8_t))   /* DMA 3 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D2                  (_ADI_MSK(0x00000004,uint8_t))   /* DMA 2 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D1                  (_ADI_MSK(0x00000002,uint8_t))   /* DMA 1 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D0                  (_ADI_MSK(0x00000001,uint8_t))   /* DMA 0 Interrupt Pending Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_CTL_BRSTM                9                               /* Burst Mode */
-#define BITP_USB_DMA_CTL_ERR                  8                               /* Bus Error */
-#define BITP_USB_DMA_CTL_EP                   4                               /* DMA Channel Endpoint Assignment */
-#define BITP_USB_DMA_CTL_IE                   3                               /* DMA Interrupt Enable */
-#define BITP_USB_DMA_CTL_MODE                 2                               /* DMA Mode */
-#define BITP_USB_DMA_CTL_DIR                  1                               /* DMA Transfer Direction */
-#define BITP_USB_DMA_CTL_EN                   0                               /* DMA Enable */
-
-#define BITM_USB_DMA_CTL_BRSTM               (_ADI_MSK(0x00000600,uint16_t))  /* Burst Mode */
-#define ENUM_USB_DMA_CTL_BRSTM00             (_ADI_MSK(0x00000000,uint16_t))  /* BRSTM: Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM01             (_ADI_MSK(0x00000200,uint16_t))  /* BRSTM: INCR4 or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM10             (_ADI_MSK(0x00000400,uint16_t))  /* BRSTM: INCR8, INCR4, or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM11             (_ADI_MSK(0x00000600,uint16_t))  /* BRSTM: INCR16, INCR8, INCR4, or Unspecified Length */
-
-#define BITM_USB_DMA_CTL_ERR                 (_ADI_MSK(0x00000100,uint16_t))  /* Bus Error */
-#define ENUM_USB_DMA_CTL_NO_DMAERR           (_ADI_MSK(0x00000000,uint16_t))  /* ERR: No Status */
-#define ENUM_USB_DMA_CTL_DMAERR              (_ADI_MSK(0x00000100,uint16_t))  /* ERR: Bus Error */
-
-#define BITM_USB_DMA_CTL_EP                  (_ADI_MSK(0x000000F0,uint16_t))  /* DMA Channel Endpoint Assignment */
-#define ENUM_USB_DMA_CTL_DMAEP0              (_ADI_MSK(0x00000000,uint16_t))  /* EP: Endpoint 0 */
-#define ENUM_USB_DMA_CTL_DMAEP1              (_ADI_MSK(0x00000010,uint16_t))  /* EP: Endpoint 1 */
-#define ENUM_USB_DMA_CTL_DMAEP10             (_ADI_MSK(0x000000A0,uint16_t))  /* EP: Endpoint 10 */
-#define ENUM_USB_DMA_CTL_DMAEP11             (_ADI_MSK(0x000000B0,uint16_t))  /* EP: Endpoint 11 */
-#define ENUM_USB_DMA_CTL_DMAEP12             (_ADI_MSK(0x000000C0,uint16_t))  /* EP: Endpoint 12 */
-#define ENUM_USB_DMA_CTL_DMAEP13             (_ADI_MSK(0x000000D0,uint16_t))  /* EP: Endpoint 13 */
-#define ENUM_USB_DMA_CTL_DMAEP14             (_ADI_MSK(0x000000E0,uint16_t))  /* EP: Endpoint 14 */
-#define ENUM_USB_DMA_CTL_DMAEP15             (_ADI_MSK(0x000000F0,uint16_t))  /* EP: Endpoint 15 */
-#define ENUM_USB_DMA_CTL_DMAEP2              (_ADI_MSK(0x00000020,uint16_t))  /* EP: Endpoint 2 */
-#define ENUM_USB_DMA_CTL_DMAEP3              (_ADI_MSK(0x00000030,uint16_t))  /* EP: Endpoint 3 */
-#define ENUM_USB_DMA_CTL_DMAEP4              (_ADI_MSK(0x00000040,uint16_t))  /* EP: Endpoint 4 */
-#define ENUM_USB_DMA_CTL_DMAEP5              (_ADI_MSK(0x00000050,uint16_t))  /* EP: Endpoint 5 */
-#define ENUM_USB_DMA_CTL_DMAEP6              (_ADI_MSK(0x00000060,uint16_t))  /* EP: Endpoint 6 */
-#define ENUM_USB_DMA_CTL_DMAEP7              (_ADI_MSK(0x00000070,uint16_t))  /* EP: Endpoint 7 */
-#define ENUM_USB_DMA_CTL_DMAEP8              (_ADI_MSK(0x00000080,uint16_t))  /* EP: Endpoint 8 */
-#define ENUM_USB_DMA_CTL_DMAEP9              (_ADI_MSK(0x00000090,uint16_t))  /* EP: Endpoint 9 */
-
-#define BITM_USB_DMA_CTL_IE                  (_ADI_MSK(0x00000008,uint16_t))  /* DMA Interrupt Enable */
-#define ENUM_USB_DMA_CTL_DMAINTDIS           (_ADI_MSK(0x00000000,uint16_t))  /* IE: Disable Interrupt */
-#define ENUM_USB_DMA_CTL_DMAINTEN            (_ADI_MSK(0x00000008,uint16_t))  /* IE: Enable Interrupt */
-
-#define BITM_USB_DMA_CTL_MODE                (_ADI_MSK(0x00000004,uint16_t))  /* DMA Mode */
-#define ENUM_USB_DMA_CTL_DMAMODE0            (_ADI_MSK(0x00000000,uint16_t))  /* MODE: DMA Mode 0 */
-#define ENUM_USB_DMA_CTL_DMAMODE1            (_ADI_MSK(0x00000004,uint16_t))  /* MODE: DMA Mode 1 */
-
-#define BITM_USB_DMA_CTL_DIR                 (_ADI_MSK(0x00000002,uint16_t))  /* DMA Transfer Direction */
-#define ENUM_USB_DMA_CTL_DMADIR_RX           (_ADI_MSK(0x00000000,uint16_t))  /* DIR: DMA Write (for Rx Endpoint) */
-#define ENUM_USB_DMA_CTL_DMADIR_TX           (_ADI_MSK(0x00000002,uint16_t))  /* DIR: DMA Read (for Tx Endpoint) */
-
-#define BITM_USB_DMA_CTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* DMA Enable */
-#define ENUM_USB_DMA_CTL_DMADIS              (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable DMA */
-#define ENUM_USB_DMA_CTL_DMAEN               (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable DMA (Start Transfer) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_UCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_UCH_VALUE                 0                               /* Chirp Timeout Value */
-#define BITM_USB_CT_UCH_VALUE                (_ADI_MSK(0x00007FFF,uint16_t))  /* Chirp Timeout Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HHSRTN                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HHSRTN_VALUE              0                               /* Host High Speed Return to Normal Value */
-#define BITM_USB_CT_HHSRTN_VALUE             (_ADI_MSK(0x00007FFF,uint16_t))  /* Host High Speed Return to Normal Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HSBT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HSBT_VALUE                0                               /* HS Timeout Adder */
-#define BITM_USB_CT_HSBT_VALUE               (_ADI_MSK(0x0000000F,uint16_t))  /* HS Timeout Adder */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_ATTR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_ATTR_EP                 12                               /* Endpoint */
-#define BITP_USB_LPM_ATTR_RMTWAK              8                               /* Remote Wakeup Enable */
-#define BITP_USB_LPM_ATTR_HIRD                4                               /* Host Initiated Resume Duration */
-#define BITP_USB_LPM_ATTR_LINKSTATE           0                               /* Link State */
-#define BITM_USB_LPM_ATTR_EP                 (_ADI_MSK(0x0000F000,uint16_t))  /* Endpoint */
-
-#define BITM_USB_LPM_ATTR_RMTWAK             (_ADI_MSK(0x00000100,uint16_t))  /* Remote Wakeup Enable */
-#define ENUM_USB_LPM_ATTR_RMTWAKDIS          (_ADI_MSK(0x00000000,uint16_t))  /* RMTWAK: Disable Remote Wakeup */
-#define ENUM_USB_LPM_ATTR_RMTWAKEN           (_ADI_MSK(0x00000100,uint16_t))  /* RMTWAK: Enable Remote Wakeup */
-#define BITM_USB_LPM_ATTR_HIRD               (_ADI_MSK(0x000000F0,uint16_t))  /* Host Initiated Resume Duration */
-
-#define BITM_USB_LPM_ATTR_LINKSTATE          (_ADI_MSK(0x0000000F,uint16_t))  /* Link State */
-#define ENUM_USB_LPM_ATTR_LNKSTATE_SSL1      (_ADI_MSK(0x00000001,uint16_t))  /* LINKSTATE: Sleep State (L1) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_CTL_NAK                  4                               /* LPM NAK Enable */
-#define BITP_USB_LPM_CTL_EN                   2                               /* LPM Enable */
-#define BITP_USB_LPM_CTL_RESUME               1                               /* LPM Resume (Remote Wakeup) */
-#define BITP_USB_LPM_CTL_TX                   0                               /* LPM Transmit */
-#define BITM_USB_LPM_CTL_NAK                 (_ADI_MSK(0x00000010,uint8_t))   /* LPM NAK Enable */
-#define BITM_USB_LPM_CTL_EN                  (_ADI_MSK(0x0000000C,uint8_t))   /* LPM Enable */
-#define BITM_USB_LPM_CTL_RESUME              (_ADI_MSK(0x00000002,uint8_t))   /* LPM Resume (Remote Wakeup) */
-#define BITM_USB_LPM_CTL_TX                  (_ADI_MSK(0x00000001,uint8_t))   /* LPM Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IEN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IEN_LPMERR               5                               /* LPM Error Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMRES               4                               /* LPM Resume Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNC                3                               /* LPM NYET Control Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMACK               2                               /* LPM ACK Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNY                1                               /* LPM NYET Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMST                0                               /* LPM STALL Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMST               (_ADI_MSK(0x00000001,uint8_t))   /* LPM STALL Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IRQ_LPMERR               5                               /* LPM Error Interrupt */
-#define BITP_USB_LPM_IRQ_LPMRES               4                               /* LPM Resume Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNC                3                               /* LPM NYET Control Interrupt */
-#define BITP_USB_LPM_IRQ_LPMACK               2                               /* LPM ACK Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNY                1                               /* LPM NYET Interrupt */
-#define BITP_USB_LPM_IRQ_LPMST                0
-#define BITM_USB_LPM_IRQ_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt */
-#define BITM_USB_LPM_IRQ_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt */
-#define BITM_USB_LPM_IRQ_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt */
-#define BITM_USB_LPM_IRQ_LPMST               (_ADI_MSK(0x00000001,uint8_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_FADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_FADDR_VALUE              0                               /* Function Address Value */
-#define BITM_USB_LPM_FADDR_VALUE             (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_VBUS_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_VBUS_CTL_DRV                 4                               /* VBUS Drive */
-#define BITP_USB_VBUS_CTL_DRVINT              3                               /* VBUS Drive Interrupt */
-#define BITP_USB_VBUS_CTL_DRVIEN              2                               /* VBUS Drive Interrupt Enable */
-#define BITP_USB_VBUS_CTL_DRVOD               1                               /* VBUS Drive Open Drain */
-#define BITP_USB_VBUS_CTL_INVDRV              0                               /* VBUS Invert Drive */
-#define BITM_USB_VBUS_CTL_DRV                (_ADI_MSK(0x00000010,uint8_t))   /* VBUS Drive */
-#define BITM_USB_VBUS_CTL_DRVINT             (_ADI_MSK(0x00000008,uint8_t))   /* VBUS Drive Interrupt */
-#define BITM_USB_VBUS_CTL_DRVIEN             (_ADI_MSK(0x00000004,uint8_t))   /* VBUS Drive Interrupt Enable */
-#define BITM_USB_VBUS_CTL_DRVOD              (_ADI_MSK(0x00000002,uint8_t))   /* VBUS Drive Open Drain */
-#define BITM_USB_VBUS_CTL_INVDRV             (_ADI_MSK(0x00000001,uint8_t))   /* VBUS Invert Drive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_BAT_CHG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_BAT_CHG_DEDCHG               4                               /* Dedicated Charging Port */
-#define BITP_USB_BAT_CHG_CHGDET               3                               /* Charging Port Detected */
-#define BITP_USB_BAT_CHG_SNSCHGDET            2                               /* Sense Charger Detection */
-#define BITP_USB_BAT_CHG_CONDET               1                               /* Connected Detected */
-#define BITP_USB_BAT_CHG_SNSCONDET            0                               /* Sense Connection Detection */
-#define BITM_USB_BAT_CHG_DEDCHG              (_ADI_MSK(0x00000010,uint8_t))   /* Dedicated Charging Port */
-#define BITM_USB_BAT_CHG_CHGDET              (_ADI_MSK(0x00000008,uint8_t))   /* Charging Port Detected */
-#define BITM_USB_BAT_CHG_SNSCHGDET           (_ADI_MSK(0x00000004,uint8_t))   /* Sense Charger Detection */
-#define BITM_USB_BAT_CHG_CONDET              (_ADI_MSK(0x00000002,uint8_t))   /* Connected Detected */
-#define BITM_USB_BAT_CHG_SNSCONDET           (_ADI_MSK(0x00000001,uint8_t))   /* Sense Connection Detection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PHY_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PHY_CTL_EN                   7                               /* PHY Enable */
-#define BITP_USB_PHY_CTL_RESTORE              1                               /* Restore from Hibernate */
-#define BITP_USB_PHY_CTL_HIBER                0                               /* Hibernate */
-#define BITM_USB_PHY_CTL_EN                  (_ADI_MSK(0x00000080,uint8_t))   /* PHY Enable */
-#define BITM_USB_PHY_CTL_RESTORE             (_ADI_MSK(0x00000002,uint8_t))   /* Restore from Hibernate */
-#define BITM_USB_PHY_CTL_HIBER               (_ADI_MSK(0x00000001,uint8_t))   /* Hibernate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PLL_OSC                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PLL_OSC_PLLMSEL              7                               /* PLL Multiplier Select */
-#define BITP_USB_PLL_OSC_PLLM                 1                               /* PLL Multiplier Value */
-#define BITP_USB_PLL_OSC_DIVCLKIN             0                               /* Divide CLKIN */
-#define BITM_USB_PLL_OSC_PLLMSEL             (_ADI_MSK(0x00000080,uint16_t))  /* PLL Multiplier Select */
-#define BITM_USB_PLL_OSC_PLLM                (_ADI_MSK(0x0000007E,uint16_t))  /* PLL Multiplier Value */
-#define BITM_USB_PLL_OSC_DIVCLKIN            (_ADI_MSK(0x00000001,uint16_t))  /* Divide CLKIN */
-
-/* ==================================================
-        Data Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1DM0
-   ========================= */
-#define SRAM_BASE_ADDRESS               0xFFE00000         /* SRAM Base Address */
-#define DMEM_CONTROL                    0xFFE00004         /* Data memory control */
-#define DCPLB_STATUS                    0xFFE00008         /* Data Cacheability Protection Lookaside Buffer Status */
-#define DCPLB_FAULT_STATUS              0xFFE00008         /*     Older definition or alias of above */
-#define DCPLB_FAULT_ADDR                0xFFE0000C         /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define DCPLB_ADDR0                     0xFFE00100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR1                     0xFFE00104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR2                     0xFFE00108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR3                     0xFFE0010C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR4                     0xFFE00110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR5                     0xFFE00114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR6                     0xFFE00118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR7                     0xFFE0011C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR8                     0xFFE00120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR9                     0xFFE00124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR10                    0xFFE00128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR11                    0xFFE0012C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR12                    0xFFE00130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR13                    0xFFE00134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR14                    0xFFE00138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR15                    0xFFE0013C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_DATA0                     0xFFE00200         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA1                     0xFFE00204         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA2                     0xFFE00208         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA3                     0xFFE0020C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA4                     0xFFE00210         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA5                     0xFFE00214         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA6                     0xFFE00218         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA7                     0xFFE0021C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA8                     0xFFE00220         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA9                     0xFFE00224         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA10                    0xFFE00228         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA11                    0xFFE0022C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA12                    0xFFE00230         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA13                    0xFFE00234         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA14                    0xFFE00238         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA15                    0xFFE0023C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DTEST_COMMAND                   0xFFE00300         /* Data Test Command Register */
-#define DTEST_DATA0                     0xFFE00400         /* Data Test Data Register */
-#define DTEST_DATA1                     0xFFE00404         /* Data Test Data Register */
-#define L1DBNKA_PELOC                   0xFFE00408         /* Data Bank A Parity Error Location */
-#define L1DBNKB_PELOC                   0xFFE0040C         /* Data Bank B Parity Error Location */
-
-/* =========================
-        L1DM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SRAM_BASE_ADDRESS                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SRAM_BASE_ADDRESS_ADDR          22                               /* SRAM Base Address */
-#define BITM_SRAM_BASE_ADDRESS_ADDR          (_ADI_MSK(0xFFC00000,uint32_t))  /* SRAM Base Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMEM_CONTROL_PARCTL             15                               /* L1 Scratch Parity Control */
-#define BITP_DMEM_CONTROL_PARSEL             14                               /* L1 Scratch Parity Select */
-#define BITP_DMEM_CONTROL_PPREF1             13                               /* DAG1 Port Preference */
-#define BITP_DMEM_CONTROL_PPREF0             12                               /* DAG0 Port Preference */
-#define BITP_DMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_DMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_DMEM_CONTROL_DCBS                4                               /* L1 Data Cache Bank Select */
-#define BITP_DMEM_CONTROL_CFG                 2                               /* Data Memory Configuration */
-#define BITP_DMEM_CONTROL_ENCPLB              1                               /* Enable DCPLB */
-
-#define BITM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* L1 Scratch Parity Control */
-#define ENUM_DMEM_CONTROL_NO_PARCTL          (_ADI_MSK(0x00000000,uint32_t))  /* PARCTL: No Parity Control  (Normal Behavior for L1 RD / L1 WT) */
-#define ENUM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* PARCTL: Parity Control Enabled */
-#define BITM_DMEM_CONTROL_PARSEL             (_ADI_MSK(0x00004000,uint32_t))  /* L1 Scratch Parity Select */
-
-#define BITM_DMEM_CONTROL_PPREF1             (_ADI_MSK(0x00002000,uint32_t))  /* DAG1 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF1A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF1B            (_ADI_MSK(0x00002000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_PPREF0             (_ADI_MSK(0x00001000,uint32_t))  /* DAG0 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF0A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF0B            (_ADI_MSK(0x00001000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_DMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_DMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_DMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_DMEM_CONTROL_DCBS               (_ADI_MSK(0x00000010,uint32_t))  /* L1 Data Cache Bank Select */
-#define ENUM_DMEM_CONTROL_DCBS14             (_ADI_MSK(0x00000000,uint32_t))  /* DCBS: Address bit 14 used to select Bank A or B for cache access */
-#define ENUM_DMEM_CONTROL_DCBS23             (_ADI_MSK(0x00000010,uint32_t))  /* DCBS: Address bit 23 used to select Bank A or B for cache access */
-
-#define BITM_DMEM_CONTROL_CFG                (_ADI_MSK(0x0000000C,uint32_t))  /* Data Memory Configuration */
-#define ENUM_DMEM_CONTROL_ASRAM_BSRAM        (_ADI_MSK(0x00000000,uint32_t))  /* CFG: A SRAM, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BSRAM       (_ADI_MSK(0x00000008,uint32_t))  /* CFG: A Cache, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BCACHE      (_ADI_MSK(0x0000000C,uint32_t))  /* CFG: A Cache, B Cache */
-
-#define BITM_DMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable DCPLB */
-#define ENUM_DMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs Disabled */
-#define ENUM_DMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs Enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_DCPLB_STATUS_DAG                18                               /* Access DAG */
-#define BITP_DCPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_DCPLB_STATUS_RW                 16                               /* Access Read/Write */
-#define BITP_DCPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_DCPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_DCPLB_STATUS_DAG                (_ADI_MSK(0x00040000,uint32_t))  /* Access DAG */
-#define BITM_DCPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_DCPLB_STATUS_RW                 (_ADI_MSK(0x00010000,uint32_t))  /* Access Read/Write */
-#define BITM_DCPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_DCPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_DCPLB_DATA_WT                   14                               /* CPLB Write Through */
-#define BITP_DCPLB_DATA_L2_CHBL              13                               /* CPLB L2 Cacheable */
-#define BITP_DCPLB_DATA_L1_CHBL              12                               /* CPLB L1 Cacheable */
-#define BITP_DCPLB_DATA_DIRTY                 7                               /* CPLB DIRTY */
-#define BITP_DCPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_DCPLB_DATA_SWRITE                4                               /* CPLB Supervisor Write */
-#define BITP_DCPLB_DATA_UWRITE                3                               /* CPLB User Write */
-#define BITP_DCPLB_DATA_UREAD                 2                               /* CPLB User Read */
-#define BITP_DCPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_DCPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_DCPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_DCPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_DCPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_DCPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_DCPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_DCPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_DCPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_DCPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_DCPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* CPLB Write Through */
-#define ENUM_DCPLB_DATA_WB                   (_ADI_MSK(0x00000000,uint32_t))  /* WT: Write-back */
-#define ENUM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* WT: Write-through */
-
-#define BITM_DCPLB_DATA_L2_CHBL              (_ADI_MSK(0x00002000,uint32_t))  /* CPLB L2 Cacheable */
-#define ENUM_DCPLB_DATA_L2CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L2CHBL: Non-cacheable in L2 */
-#define ENUM_DCPLB_DATA_L2CHBL_EN            (_ADI_MSK(0x00002000,uint32_t))  /* L2CHBL: Cacheable in L2 */
-
-#define BITM_DCPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* CPLB L1 Cacheable */
-#define ENUM_DCPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_DCPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* CPLB DIRTY */
-#define ENUM_DCPLB_DATA_CLEAN                (_ADI_MSK(0x00000000,uint32_t))  /* DIRTY: Clean */
-#define ENUM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* DIRTY: Dirty */
-#define BITM_DCPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* CPLB Supervisor Write */
-#define ENUM_DCPLB_DATA_NO_SWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* SWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* SWRITE: Write Access Allowed (Supervisor Mode) */
-
-#define BITM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* CPLB User Write */
-#define ENUM_DCPLB_DATA_NO_UWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* UWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* UWRITE: Write Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* CPLB User Read */
-#define ENUM_DCPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_DCPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_DCPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_DCPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid Entry */
-#define ENUM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DTEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DTEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_DTEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_DTEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bit 11 */
-#define BITP_DTEST_COMMAND_IDSEL             24                               /* Instruction/Data Access */
-#define BITP_DTEST_COMMAND_BNKSEL            23                               /* Data Bank Access */
-#define BITP_DTEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_DTEST_COMMAND_SEL16K            14                               /* Address bit 14 */
-#define BITP_DTEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_DTEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_DTEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_DTEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_DTEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_DTEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_DTEST_COMMAND_WAYSEL            (_ADI_MSK(0x04000000,uint32_t))  /* Access Way/Instruction Address Bit 11 */
-#define BITM_DTEST_COMMAND_IDSEL             (_ADI_MSK(0x01000000,uint32_t))  /* Instruction/Data Access */
-#define BITM_DTEST_COMMAND_BNKSEL            (_ADI_MSK(0x00800000,uint32_t))  /* Data Bank Access */
-#define BITM_DTEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_DTEST_COMMAND_SEL16K            (_ADI_MSK(0x00004000,uint32_t))  /* Address bit 14 */
-#define BITM_DTEST_COMMAND_SET               (_ADI_MSK(0x000007E0,uint32_t))  /* Set Index */
-#define BITM_DTEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_DTEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_DTEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKA_PELOC_SCRATCH_MEM       12                               /* Scratch Memory Parity Status */
-#define BITP_L1DBNKA_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_SCRATCH_MEM       (_ADI_MSK(0x00001000,uint32_t))  /* Scratch Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKB_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKB_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Instruction Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1IM0
-   ========================= */
-#define IMEM_CONTROL                    0xFFE01004         /* Instruction memory control */
-#define ICPLB_STATUS                    0xFFE01008         /* Cacheability Protection Lookaside Buffer Status */
-#define CODE_FAULT_STATUS               0xFFE01008         /*     Older definition or alias of above */
-#define ICPLB_FAULT_ADDR                0xFFE0100C         /* Cacheability Protection Lookaside Buffer Fault Address */
-#define CODE_FAULT_ADDR                 0xFFE0100C         /*     Older definition or alias of above */
-#define ICPLB_ADDR0                     0xFFE01100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR1                     0xFFE01104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR2                     0xFFE01108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR3                     0xFFE0110C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR4                     0xFFE01110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR5                     0xFFE01114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR6                     0xFFE01118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR7                     0xFFE0111C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR8                     0xFFE01120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR9                     0xFFE01124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR10                    0xFFE01128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR11                    0xFFE0112C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR12                    0xFFE01130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR13                    0xFFE01134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR14                    0xFFE01138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR15                    0xFFE0113C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_DATA0                     0xFFE01200         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA1                     0xFFE01204         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA2                     0xFFE01208         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA3                     0xFFE0120C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA4                     0xFFE01210         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA5                     0xFFE01214         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA6                     0xFFE01218         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA7                     0xFFE0121C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA8                     0xFFE01220         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA9                     0xFFE01224         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA10                    0xFFE01228         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA11                    0xFFE0122C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA12                    0xFFE01230         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA13                    0xFFE01234         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA14                    0xFFE01238         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA15                    0xFFE0123C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ITEST_COMMAND                   0xFFE01300         /* Instruction Test Command Register */
-#define ITEST_DATA0                     0xFFE01400         /* Instruction Test Data Register */
-#define ITEST_DATA1                     0xFFE01404         /* Instruction Test Data Register */
-#define L1IBNKA_PELOC                   0xFFE01408         /* Instruction Bank A Parity Error Location */
-#define L1IBNKB_PELOC                   0xFFE0140C         /* Instruction Bank B Parity Error Location */
-#define L1IBNKC_PELOC                   0xFFE01410         /* Instruction Bank C Parity Error Location */
-
-/* =========================
-        L1IM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMEM_CONTROL_LRUPRIORST         13                               /* LRU Priority Reset */
-#define BITP_IMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_IMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_IMEM_CONTROL_LOC                 3                               /* Cache Way Lock */
-#define BITP_IMEM_CONTROL_CFG                 2                               /* Configure L1 code memory as cache */
-#define BITP_IMEM_CONTROL_ENCPLB              1                               /* Enable ICPLB */
-
-#define BITM_IMEM_CONTROL_LRUPRIORST         (_ADI_MSK(0x00002000,uint32_t))  /* LRU Priority Reset */
-#define ENUM_IMEM_CONTROL_LRUPRIO_EN         (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIORST: LRU Priority functionality is enabled */
-#define ENUM_IMEM_CONTROL_LRUPRIO_CLR        (_ADI_MSK(0x00002000,uint32_t))  /* LRUPRIORST: All cached LRU priority bits are cleared */
-
-#define BITM_IMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_IMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_IMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_IMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_IMEM_CONTROL_LOC                (_ADI_MSK(0x00000078,uint32_t))  /* Cache Way Lock */
-#define ENUM_IMEM_CONTROL_WAYLOCK_NONE       (_ADI_MSK(0x00000000,uint32_t))  /* LOC: All Ways Not Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_0          (_ADI_MSK(0x00000008,uint32_t))  /* LOC: Way3, Way2, Way1 Not Locked, Way0 Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_ALL        (_ADI_MSK(0x00000078,uint32_t))  /* LOC: All Ways Locked */
-
-#define BITM_IMEM_CONTROL_CFG                (_ADI_MSK(0x00000004,uint32_t))  /* Configure L1 code memory as cache */
-#define ENUM_IMEM_CONTROL_CFG_SRAM           (_ADI_MSK(0x00000000,uint32_t))  /* CFG: L1 Instruction Memory Configured as SRAM */
-#define ENUM_IMEM_CONTROL_CFG_CACHE          (_ADI_MSK(0x00000004,uint32_t))  /* CFG: L1 Instruction Memory Configures as Cache */
-
-#define BITM_IMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable ICPLB */
-#define ENUM_IMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs disabled */
-#define ENUM_IMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_ICPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_ICPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_ICPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_ICPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_ICPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_ICPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_ICPLB_DATA_L1_CHBL              12                               /* L1 Cacheable */
-#define BITP_ICPLB_DATA_LRUPRIO               8                               /* Least Recently Used Priority */
-#define BITP_ICPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_ICPLB_DATA_UREAD                 2                               /* Allow User Read */
-#define BITP_ICPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_ICPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_ICPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_ICPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_ICPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_ICPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_ICPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_ICPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_ICPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_ICPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_ICPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_ICPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* L1 Cacheable */
-#define ENUM_ICPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_ICPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_ICPLB_DATA_LRUPRIO              (_ADI_MSK(0x00000100,uint32_t))  /* Least Recently Used Priority */
-#define ENUM_ICPLB_DATA_LRUPRIO_LO           (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIO: Low Importance */
-#define ENUM_ICPLB_DATA_LRUPRIO_HI           (_ADI_MSK(0x00000100,uint32_t))  /* LRUPRIO: High Importance */
-#define BITM_ICPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* Allow User Read */
-#define ENUM_ICPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_ICPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_ICPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_ICPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_ICPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid (disabled) CPLB Entry */
-#define ENUM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid (enabled) CPLB Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ITEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ITEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_ITEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_ITEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bits 11:10 */
-#define BITP_ITEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_ITEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_ITEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_ITEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_ITEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_ITEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_ITEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_ITEST_COMMAND_WAYSEL            (_ADI_MSK(0x0C000000,uint32_t))  /* Access Way/Instruction Address Bits 11:10 */
-#define BITM_ITEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_ITEST_COMMAND_SET               (_ADI_MSK(0x000003E0,uint32_t))  /* Set Index */
-#define BITM_ITEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_ITEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_ITEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKC_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKC_PELOC_TAGPAIR            4                               /* Tag Parity Status */
-#define BITP_L1IBNKC_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKC_PELOC_TAGPAIR           (_ADI_MSK(0x00000030,uint32_t))  /* Tag Parity Status */
-#define BITM_L1IBNKC_PELOC_MEMBLK            (_ADI_MSK(0x0000000F,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Interrupt Controller Registers
-   ================================================== */
-
-/* =========================
-        ICU0
-   ========================= */
-#define EVT0                            0xFFE02000         /* Event Vector */
-#define EVT1                            0xFFE02004         /* Event Vector */
-#define EVT2                            0xFFE02008         /* Event Vector */
-#define EVT3                            0xFFE0200C         /* Event Vector */
-#define EVT4                            0xFFE02010         /* Event Vector */
-#define EVT5                            0xFFE02014         /* Event Vector */
-#define EVT6                            0xFFE02018         /* Event Vector */
-#define EVT7                            0xFFE0201C         /* Event Vector */
-#define EVT8                            0xFFE02020         /* Event Vector */
-#define EVT9                            0xFFE02024         /* Event Vector */
-#define EVT10                           0xFFE02028         /* Event Vector */
-#define EVT11                           0xFFE0202C         /* Event Vector */
-#define EVT12                           0xFFE02030         /* Event Vector */
-#define EVT13                           0xFFE02034         /* Event Vector */
-#define EVT14                           0xFFE02038         /* Event Vector */
-#define EVT15                           0xFFE0203C         /* Event Vector */
-#define IMASK                           0xFFE02104         /* Interrupt Mask Register */
-#define IPEND                           0xFFE02108         /* Interrupts Pending Register */
-#define ILAT                            0xFFE0210C         /* Interrupt Latch Register */
-#define IPRIO                           0xFFE02110         /* Interrupt Priority Register */
-#define CEC_SID                         0xFFE02118         /* Core System Interrupt ID */
-
-/* =========================
-        ICU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMASK                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMASK_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IMASK_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IMASK_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IMASK_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IMASK_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IMASK_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IMASK_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IMASK_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IMASK_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IMASK_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IMASK_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IMASK_UNMASKABLE                 0                               /* Unmaskable interrupts */
-#define BITM_IMASK_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IMASK_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IMASK_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IMASK_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IMASK_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IMASK_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IMASK_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IMASK_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IMASK_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IMASK_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IMASK_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IMASK_UNMASKABLE                (_ADI_MSK(0x0000001F,uint32_t))  /* Unmaskable interrupts */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPEND                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPEND_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IPEND_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IPEND_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IPEND_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IPEND_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IPEND_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IPEND_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IPEND_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IPEND_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IPEND_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IPEND_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IPEND_IRPTEN                     4                               /* Global interrupt enable bit position */
-#define BITP_IPEND_EVX                        3                               /* Exception bit position */
-#define BITP_IPEND_NMI                        2                               /* Non Maskable interrupt bit position */
-#define BITP_IPEND_RST                        1                               /* Reset interrupt bit position */
-#define BITP_IPEND_EMU                        0                               /* Emulator interrupt bit position */
-#define BITM_IPEND_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IPEND_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IPEND_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IPEND_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IPEND_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IPEND_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IPEND_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IPEND_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IPEND_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IPEND_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IPEND_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IPEND_IRPTEN                    (_ADI_MSK(0x00000010,uint32_t))  /* Global interrupt enable bit position */
-#define BITM_IPEND_EVX                       (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_IPEND_NMI                       (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_IPEND_RST                       (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_IPEND_EMU                       (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ILAT                                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ILAT_IVG15                      15                               /* IVG15 interrupt bit position */
-#define BITP_ILAT_IVG14                      14                               /* IVG14 interrupt bit position */
-#define BITP_ILAT_IVG13                      13                               /* IVG13 interrupt bit position */
-#define BITP_ILAT_IVG12                      12                               /* IVG12 interrupt bit position */
-#define BITP_ILAT_IVG11                      11                               /* IVG11 interrupt bit position */
-#define BITP_ILAT_IVG10                      10                               /* IVG10 interrupt bit position */
-#define BITP_ILAT_IVG9                        9                               /* IVG9 interrupt bit position */
-#define BITP_ILAT_IVG8                        8                               /* IVG8 interrupt bit position */
-#define BITP_ILAT_IVG7                        7                               /* IVG7 interrupt bit position */
-#define BITP_ILAT_IVTMR                       6                               /* Timer interrupt bit position */
-#define BITP_ILAT_IVHW                        5                               /* Hardware Error interrupt bit position */
-#define BITP_ILAT_EVX                         3                               /* Exception bit position */
-#define BITP_ILAT_NMI                         2                               /* Non Maskable interrupt bit position */
-#define BITP_ILAT_RST                         1                               /* Reset interrupt bit position */
-#define BITP_ILAT_EMU                         0                               /* Emulator interrupt bit position */
-#define BITM_ILAT_IVG15                      (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_ILAT_IVG14                      (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_ILAT_IVG13                      (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_ILAT_IVG12                      (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_ILAT_IVG11                      (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_ILAT_IVG10                      (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_ILAT_IVG9                       (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_ILAT_IVG8                       (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_ILAT_IVG7                       (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_ILAT_IVTMR                      (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_ILAT_IVHW                       (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_ILAT_EVX                        (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_ILAT_NMI                        (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_ILAT_RST                        (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_ILAT_EMU                        (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPRIO                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPRIO_IPRIO_MARK                 0                               /* Priority Watermark */
-#define BITM_IPRIO_IPRIO_MARK                (_ADI_MSK(0x0000000F,uint32_t))  /* Priority Watermark */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CEC_SID                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CEC_SID_SID                      0                               /* System Interrupt ID */
-#define BITM_CEC_SID_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* System Interrupt ID */
-
-/* ==================================================
-        Core Timer Registers
-   ================================================== */
-
-/* =========================
-        TMR0
-   ========================= */
-#define TCNTL                           0xFFE03000         /* Timer Control Register */
-#define TPERIOD                         0xFFE03004         /* Timer Period Register */
-#define TSCALE                          0xFFE03008         /* Timer Scale Register */
-#define TCOUNT                          0xFFE0300C         /* Timer Count Register */
-
-/* =========================
-        TMR
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TCNTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TCNTL_INT                        3                               /* Interrupt Status (sticky) */
-#define BITP_TCNTL_AUTORLD                    2                               /* Auto Reload Enable */
-#define BITP_TCNTL_EN                         1                               /* Timer Enable */
-#define BITP_TCNTL_PWR                        0                               /* Low Power Mode Select */
-#define BITM_TCNTL_INT                       (_ADI_MSK(0x00000008,uint32_t))  /* Interrupt Status (sticky) */
-#define BITM_TCNTL_AUTORLD                   (_ADI_MSK(0x00000004,uint32_t))  /* Auto Reload Enable */
-#define BITM_TCNTL_EN                        (_ADI_MSK(0x00000002,uint32_t))  /* Timer Enable */
-#define BITM_TCNTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Low Power Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TSCALE                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TSCALE_SCALE                     0                               /* Timer Scaling Value */
-#define BITM_TSCALE_SCALE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Timer Scaling Value */
-
-/* ==================================================
-        Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        DBG0
-   ========================= */
-#define DSPID                           0xFFE05000         /* DSP Identification Register */
-
-/* =========================
-        DBG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DSPID                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DSPID_COMPANY                   24                               /* Analog Devices, Inc. */
-#define BITP_DSPID_MAJOR                     16                               /* Major Architectural Change */
-#define BITP_DSPID_COREID                     0                               /* Core ID */
-#define BITM_DSPID_COMPANY                   (_ADI_MSK(0xFF000000,uint32_t))  /* Analog Devices, Inc. */
-
-#define BITM_DSPID_MAJOR                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Major Architectural Change */
-#define ENUM_DSPID_BF533                     (_ADI_MSK(0x00040000,uint32_t))  /* MAJOR: ADSP-BF533 Core Compatible */
-#define BITM_DSPID_COREID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Core ID */
-
-/* ==================================================
-        Trace Unit Registers
-   ================================================== */
-
-/* =========================
-        TB0
-   ========================= */
-#define TBUFCTL                         0xFFE06000         /* Trace Buffer Control Register */
-#define TBUFSTAT                        0xFFE06004         /* Trace Buffer Status Register */
-#define TBUF                            0xFFE06100         /* Trace Buffer */
-
-/* =========================
-        TB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFCTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFCTL_COMPRESS                 3                               /* Trace Buffer Compression */
-#define BITP_TBUFCTL_OVF                      2                               /* Trace Buffer Overflow */
-#define BITP_TBUFCTL_EN                       1                               /* Trace Buffer Enable */
-#define BITP_TBUFCTL_PWR                      0                               /* Trace Buffer Power */
-#define BITM_TBUFCTL_COMPRESS                (_ADI_MSK(0x00000018,uint32_t))  /* Trace Buffer Compression */
-#define BITM_TBUFCTL_OVF                     (_ADI_MSK(0x00000004,uint32_t))  /* Trace Buffer Overflow */
-#define BITM_TBUFCTL_EN                      (_ADI_MSK(0x00000002,uint32_t))  /* Trace Buffer Enable */
-#define BITM_TBUFCTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Trace Buffer Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFSTAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFSTAT_CNT                     0                               /* Trace Buffer Count */
-#define BITM_TBUFSTAT_CNT                    (_ADI_MSK(0x0000001F,uint32_t))  /* Trace Buffer Count */
-
-/* ==================================================
-        Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        WP0
-   ========================= */
-#define WPIACTL                         0xFFE07000         /* Watchpoint Instruction Address Control Register 01 */
-#define WPIA0                           0xFFE07040         /* Watchpoint Instruction Address Register */
-#define WPIA1                           0xFFE07044         /* Watchpoint Instruction Address Register */
-#define WPIA2                           0xFFE07048         /* Watchpoint Instruction Address Register */
-#define WPIA3                           0xFFE0704C         /* Watchpoint Instruction Address Register */
-#define WPIA4                           0xFFE07050         /* Watchpoint Instruction Address Register */
-#define WPIA5                           0xFFE07054         /* Watchpoint Instruction Address Register */
-#define WPIACNT0                        0xFFE07080         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT1                        0xFFE07084         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT2                        0xFFE07088         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT3                        0xFFE0708C         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT4                        0xFFE07090         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT5                        0xFFE07094         /* Watchpoint Instruction Address Count Register */
-#define WPDACTL                         0xFFE07100         /* Watchpoint Data Address Control Register */
-#define WPDA0                           0xFFE07140         /* Watchpoint Data Address Register */
-#define WPDA1                           0xFFE07144         /* Watchpoint Data Address Register */
-#define WPDACNT0                        0xFFE07180         /* Watchpoint Data Address Count Value Register */
-#define WPDACNT1                        0xFFE07184         /* Watchpoint Data Address Count Value Register */
-#define WPSTAT                          0xFFE07200         /* Watchpoint Status Register */
-
-/* =========================
-        WP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACTL_WPAND                   25                               /* And Triggers */
-#define BITP_WPIACTL_ACT5                    24                               /* Action field for WPIA5 */
-#define BITP_WPIACTL_ACT4                    23                               /* Action field for WPIA4 */
-#define BITP_WPIACTL_ENCNT5                  22                               /* Enable Counter for WPIA5 */
-#define BITP_WPIACTL_ENCNT4                  21                               /* Enable Counter for WPIA4 */
-#define BITP_WPIACTL_ENIA5                   20                               /* Enable WPIA5 */
-#define BITP_WPIACTL_ENIA4                   19                               /* Enable WPIA4 */
-#define BITP_WPIACTL_INVIR45                 18                               /* Invert Instruction Range 45 */
-#define BITP_WPIACTL_ENIR45                  17                               /* Enable Instruction Range 45 */
-#define BITP_WPIACTL_ACT3                    16                               /* Action field for WPIA3 */
-#define BITP_WPIACTL_ACT2                    15                               /* Action field for WPIA2 */
-#define BITP_WPIACTL_ENCNT3                  14                               /* Enable Counter for WPIA3 */
-#define BITP_WPIACTL_ENCNT2                  13                               /* Enable Counter for WPIA2 */
-#define BITP_WPIACTL_ENIA3                   12                               /* Enable WPIA3 */
-#define BITP_WPIACTL_ENIA2                   11                               /* Enable WPIA2 */
-#define BITP_WPIACTL_INVIR23                 10                               /* Invert Instruction Range 23 */
-#define BITP_WPIACTL_ENIR23                   9                               /* Enable Instruction Range 23 */
-#define BITP_WPIACTL_ACT1                     8                               /* Action field for WPIA1 */
-#define BITP_WPIACTL_ACT0                     7                               /* Action field for WPIA0 */
-#define BITP_WPIACTL_ENCNT1                   6                               /* Enable Counter for WPIA1 */
-#define BITP_WPIACTL_ENCNT0                   5                               /* Enable Counter for WPIA0 */
-#define BITP_WPIACTL_ENIA1                    4                               /* Enable WPIA1 */
-#define BITP_WPIACTL_ENIA0                    3                               /* Enable WPIA0 */
-#define BITP_WPIACTL_INVIR01                  2                               /* Invert Instruction Range 01 */
-#define BITP_WPIACTL_ENIR01                   1                               /* Enable Instruction Range 01 */
-#define BITP_WPIACTL_PWR                      0                               /* Power */
-#define BITM_WPIACTL_WPAND                   (_ADI_MSK(0x02000000,uint32_t))  /* And Triggers */
-#define BITM_WPIACTL_ACT5                    (_ADI_MSK(0x01000000,uint32_t))  /* Action field for WPIA5 */
-#define BITM_WPIACTL_ACT4                    (_ADI_MSK(0x00800000,uint32_t))  /* Action field for WPIA4 */
-#define BITM_WPIACTL_ENCNT5                  (_ADI_MSK(0x00400000,uint32_t))  /* Enable Counter for WPIA5 */
-#define BITM_WPIACTL_ENCNT4                  (_ADI_MSK(0x00200000,uint32_t))  /* Enable Counter for WPIA4 */
-#define BITM_WPIACTL_ENIA5                   (_ADI_MSK(0x00100000,uint32_t))  /* Enable WPIA5 */
-#define BITM_WPIACTL_ENIA4                   (_ADI_MSK(0x00080000,uint32_t))  /* Enable WPIA4 */
-#define BITM_WPIACTL_INVIR45                 (_ADI_MSK(0x00040000,uint32_t))  /* Invert Instruction Range 45 */
-#define BITM_WPIACTL_ENIR45                  (_ADI_MSK(0x00020000,uint32_t))  /* Enable Instruction Range 45 */
-#define BITM_WPIACTL_ACT3                    (_ADI_MSK(0x00010000,uint32_t))  /* Action field for WPIA3 */
-#define BITM_WPIACTL_ACT2                    (_ADI_MSK(0x00008000,uint32_t))  /* Action field for WPIA2 */
-#define BITM_WPIACTL_ENCNT3                  (_ADI_MSK(0x00004000,uint32_t))  /* Enable Counter for WPIA3 */
-#define BITM_WPIACTL_ENCNT2                  (_ADI_MSK(0x00002000,uint32_t))  /* Enable Counter for WPIA2 */
-#define BITM_WPIACTL_ENIA3                   (_ADI_MSK(0x00001000,uint32_t))  /* Enable WPIA3 */
-#define BITM_WPIACTL_ENIA2                   (_ADI_MSK(0x00000800,uint32_t))  /* Enable WPIA2 */
-#define BITM_WPIACTL_INVIR23                 (_ADI_MSK(0x00000400,uint32_t))  /* Invert Instruction Range 23 */
-#define BITM_WPIACTL_ENIR23                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable Instruction Range 23 */
-#define BITM_WPIACTL_ACT1                    (_ADI_MSK(0x00000100,uint32_t))  /* Action field for WPIA1 */
-#define BITM_WPIACTL_ACT0                    (_ADI_MSK(0x00000080,uint32_t))  /* Action field for WPIA0 */
-#define BITM_WPIACTL_ENCNT1                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Counter for WPIA1 */
-#define BITM_WPIACTL_ENCNT0                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Counter for WPIA0 */
-#define BITM_WPIACTL_ENIA1                   (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPIA1 */
-#define BITM_WPIACTL_ENIA0                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPIA0 */
-#define BITM_WPIACTL_INVIR01                 (_ADI_MSK(0x00000004,uint32_t))  /* Invert Instruction Range 01 */
-#define BITM_WPIACTL_ENIR01                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable Instruction Range 01 */
-#define BITM_WPIACTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACNT_CNT                      0                               /* Count Value */
-#define BITM_WPIACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACTL_ACC1                    12                               /* Access type for WPDA1 */
-#define BITP_WPDACTL_SRC1                    10                               /* DAG Source for WPDA1 */
-#define BITP_WPDACTL_ACC0                     8                               /* Access type for WPDA0 */
-#define BITP_WPDACTL_SRC0                     6                               /* DAG Source for WPDA0 */
-#define BITP_WPDACTL_ENCNT1                   5                               /* Enable WPDA1 Counter */
-#define BITP_WPDACTL_ENCNT0                   4                               /* Enable WPDA0 Counter */
-#define BITP_WPDACTL_ENDA1                    3                               /* Enable WPDA1 */
-#define BITP_WPDACTL_ENDA0                    2                               /* Enable WPDA0 */
-#define BITP_WPDACTL_INVR                     1                               /* Invert Range Comparision */
-#define BITP_WPDACTL_ENR                      0                               /* Enable Range Comparison */
-#define BITM_WPDACTL_ACC1                    (_ADI_MSK(0x00003000,uint32_t))  /* Access type for WPDA1 */
-#define BITM_WPDACTL_SRC1                    (_ADI_MSK(0x00000C00,uint32_t))  /* DAG Source for WPDA1 */
-#define BITM_WPDACTL_ACC0                    (_ADI_MSK(0x00000300,uint32_t))  /* Access type for WPDA0 */
-#define BITM_WPDACTL_SRC0                    (_ADI_MSK(0x000000C0,uint32_t))  /* DAG Source for WPDA0 */
-#define BITM_WPDACTL_ENCNT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable WPDA1 Counter */
-#define BITM_WPDACTL_ENCNT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPDA0 Counter */
-#define BITM_WPDACTL_ENDA1                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPDA1 */
-#define BITM_WPDACTL_ENDA0                   (_ADI_MSK(0x00000004,uint32_t))  /* Enable WPDA0 */
-#define BITM_WPDACTL_INVR                    (_ADI_MSK(0x00000002,uint32_t))  /* Invert Range Comparision */
-#define BITM_WPDACTL_ENR                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable Range Comparison */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACNT_CNT                      0                               /* Count Value */
-#define BITM_WPDACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPSTAT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPSTAT_DA1                       7                               /* WPDA1 match */
-#define BITP_WPSTAT_DA0                       6                               /* WPDA0 or WPDA0:1 range match */
-#define BITP_WPSTAT_IA5                       5                               /* WPIA5 match */
-#define BITP_WPSTAT_IA4                       4                               /* WPIA4 or WPIA4:5 range match */
-#define BITP_WPSTAT_IA3                       3                               /* WPIA3 match */
-#define BITP_WPSTAT_IA2                       2                               /* WPIA2 or WPIA2:3 range match */
-#define BITP_WPSTAT_IA1                       1                               /* WPIA1 match */
-#define BITP_WPSTAT_IA0                       0                               /* WPIA0 or WPIA0:1 range match */
-#define BITM_WPSTAT_DA1                      (_ADI_MSK(0x00000080,uint32_t))  /* WPDA1 match */
-#define BITM_WPSTAT_DA0                      (_ADI_MSK(0x00000040,uint32_t))  /* WPDA0 or WPDA0:1 range match */
-#define BITM_WPSTAT_IA5                      (_ADI_MSK(0x00000020,uint32_t))  /* WPIA5 match */
-#define BITM_WPSTAT_IA4                      (_ADI_MSK(0x00000010,uint32_t))  /* WPIA4 or WPIA4:5 range match */
-#define BITM_WPSTAT_IA3                      (_ADI_MSK(0x00000008,uint32_t))  /* WPIA3 match */
-#define BITM_WPSTAT_IA2                      (_ADI_MSK(0x00000004,uint32_t))  /* WPIA2 or WPIA2:3 range match */
-#define BITM_WPSTAT_IA1                      (_ADI_MSK(0x00000002,uint32_t))  /* WPIA1 match */
-#define BITM_WPSTAT_IA0                      (_ADI_MSK(0x00000001,uint32_t))  /* WPIA0 or WPIA0:1 range match */
-
-/* ==================================================
-        Performance Monitor Registers
-   ================================================== */
-
-/* =========================
-        PF0
-   ========================= */
-#define PFCTL                           0xFFE08000         /* Performance Monitor Control Register */
-#define PFCNTR0                         0xFFE08100         /* Performance Monitor Counter 0 */
-#define PFCNTR1                         0xFFE08104         /* Performance Monitor Counter 1 */
-
-/* =========================
-        PF
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PFCTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PFCTL_CNT1                      25                               /* Count Cycles or Edges 1 */
-#define BITP_PFCTL_CNT0                      24                               /* Count Cycles or Edges 0 */
-#define BITP_PFCTL_MON1                      16                               /* Monitor 1 Events */
-#define BITP_PFCTL_ENA1                      14                               /* Enable Monitor 1 */
-#define BITP_PFCTL_EVENT1                    13                               /* Emulator or Exception Event 1 */
-#define BITP_PFCTL_MON0                       5                               /* Monitor 0 Events */
-#define BITP_PFCTL_ENA0                       3                               /* Enable Monitor 0 */
-#define BITP_PFCTL_EVENT0                     2                               /* Emulator or Exception Event 0 */
-#define BITP_PFCTL_PWR                        0                               /* Power */
-#define BITM_PFCTL_CNT1                      (_ADI_MSK(0x02000000,uint32_t))  /* Count Cycles or Edges 1 */
-#define BITM_PFCTL_CNT0                      (_ADI_MSK(0x01000000,uint32_t))  /* Count Cycles or Edges 0 */
-#define BITM_PFCTL_MON1                      (_ADI_MSK(0x00FF0000,uint32_t))  /* Monitor 1 Events */
-#define BITM_PFCTL_ENA1                      (_ADI_MSK(0x0000C000,uint32_t))  /* Enable Monitor 1 */
-#define BITM_PFCTL_EVENT1                    (_ADI_MSK(0x00002000,uint32_t))  /* Emulator or Exception Event 1 */
-#define BITM_PFCTL_MON0                      (_ADI_MSK(0x00001FE0,uint32_t))  /* Monitor 0 Events */
-#define BITM_PFCTL_ENA0                      (_ADI_MSK(0x00000018,uint32_t))  /* Enable Monitor 0 */
-#define BITM_PFCTL_EVENT0                    (_ADI_MSK(0x00000004,uint32_t))  /* Emulator or Exception Event 0 */
-#define BITM_PFCTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ==================================
-       DMA Alias Definitions
-   ================================== */
-#define SPORT0_A_DMA_DSCPTR_NXT              (REG_DMA0_DSCPTR_NXT)
-#define SPORT0_A_DMA_ADDRSTART               (REG_DMA0_ADDRSTART)
-#define SPORT0_A_DMA_CFG                     (REG_DMA0_CFG)
-#define SPORT0_A_DMA_XCNT                    (REG_DMA0_XCNT)
-#define SPORT0_A_DMA_XMOD                    (REG_DMA0_XMOD)
-#define SPORT0_A_DMA_YCNT                    (REG_DMA0_YCNT)
-#define SPORT0_A_DMA_YMOD                    (REG_DMA0_YMOD)
-#define SPORT0_A_DMA_DSCPTR_CUR              (REG_DMA0_DSCPTR_CUR)
-#define SPORT0_A_DMA_DSCPTR_PRV              (REG_DMA0_DSCPTR_PRV)
-#define SPORT0_A_DMA_ADDR_CUR                (REG_DMA0_ADDR_CUR)
-#define SPORT0_A_DMA_STAT                    (REG_DMA0_STAT)
-#define SPORT0_A_DMA_XCNT_CUR                (REG_DMA0_XCNT_CUR)
-#define SPORT0_A_DMA_YCNT_CUR                (REG_DMA0_YCNT_CUR)
-#define SPORT0_A_DMA_BWLCNT                  (REG_DMA0_BWLCNT)
-#define SPORT0_A_DMA_BWLCNT_CUR              (REG_DMA0_BWLCNT_CUR)
-#define SPORT0_A_DMA_BWMCNT                  (REG_DMA0_BWMCNT)
-#define SPORT0_A_DMA_BWMCNT_CUR              (REG_DMA0_BWMCNT_CUR)
-#define SPORT0_B_DMA_DSCPTR_NXT              (REG_DMA1_DSCPTR_NXT)
-#define SPORT0_B_DMA_ADDRSTART               (REG_DMA1_ADDRSTART)
-#define SPORT0_B_DMA_CFG                     (REG_DMA1_CFG)
-#define SPORT0_B_DMA_XCNT                    (REG_DMA1_XCNT)
-#define SPORT0_B_DMA_XMOD                    (REG_DMA1_XMOD)
-#define SPORT0_B_DMA_YCNT                    (REG_DMA1_YCNT)
-#define SPORT0_B_DMA_YMOD                    (REG_DMA1_YMOD)
-#define SPORT0_B_DMA_DSCPTR_CUR              (REG_DMA1_DSCPTR_CUR)
-#define SPORT0_B_DMA_DSCPTR_PRV              (REG_DMA1_DSCPTR_PRV)
-#define SPORT0_B_DMA_ADDR_CUR                (REG_DMA1_ADDR_CUR)
-#define SPORT0_B_DMA_STAT                    (REG_DMA1_STAT)
-#define SPORT0_B_DMA_XCNT_CUR                (REG_DMA1_XCNT_CUR)
-#define SPORT0_B_DMA_YCNT_CUR                (REG_DMA1_YCNT_CUR)
-#define SPORT0_B_DMA_BWLCNT                  (REG_DMA1_BWLCNT)
-#define SPORT0_B_DMA_BWLCNT_CUR              (REG_DMA1_BWLCNT_CUR)
-#define SPORT0_B_DMA_BWMCNT                  (REG_DMA1_BWMCNT)
-#define SPORT0_B_DMA_BWMCNT_CUR              (REG_DMA1_BWMCNT_CUR)
-#define SPORT1_A_DMA_DSCPTR_NXT              (REG_DMA2_DSCPTR_NXT)
-#define SPORT1_A_DMA_ADDRSTART               (REG_DMA2_ADDRSTART)
-#define SPORT1_A_DMA_CFG                     (REG_DMA2_CFG)
-#define SPORT1_A_DMA_XCNT                    (REG_DMA2_XCNT)
-#define SPORT1_A_DMA_XMOD                    (REG_DMA2_XMOD)
-#define SPORT1_A_DMA_YCNT                    (REG_DMA2_YCNT)
-#define SPORT1_A_DMA_YMOD                    (REG_DMA2_YMOD)
-#define SPORT1_A_DMA_DSCPTR_CUR              (REG_DMA2_DSCPTR_CUR)
-#define SPORT1_A_DMA_DSCPTR_PRV              (REG_DMA2_DSCPTR_PRV)
-#define SPORT1_A_DMA_ADDR_CUR                (REG_DMA2_ADDR_CUR)
-#define SPORT1_A_DMA_STAT                    (REG_DMA2_STAT)
-#define SPORT1_A_DMA_XCNT_CUR                (REG_DMA2_XCNT_CUR)
-#define SPORT1_A_DMA_YCNT_CUR                (REG_DMA2_YCNT_CUR)
-#define SPORT1_A_DMA_BWLCNT                  (REG_DMA2_BWLCNT)
-#define SPORT1_A_DMA_BWLCNT_CUR              (REG_DMA2_BWLCNT_CUR)
-#define SPORT1_A_DMA_BWMCNT                  (REG_DMA2_BWMCNT)
-#define SPORT1_A_DMA_BWMCNT_CUR              (REG_DMA2_BWMCNT_CUR)
-#define SPORT1_B_DMA_DSCPTR_NXT              (REG_DMA3_DSCPTR_NXT)
-#define SPORT1_B_DMA_ADDRSTART               (REG_DMA3_ADDRSTART)
-#define SPORT1_B_DMA_CFG                     (REG_DMA3_CFG)
-#define SPORT1_B_DMA_XCNT                    (REG_DMA3_XCNT)
-#define SPORT1_B_DMA_XMOD                    (REG_DMA3_XMOD)
-#define SPORT1_B_DMA_YCNT                    (REG_DMA3_YCNT)
-#define SPORT1_B_DMA_YMOD                    (REG_DMA3_YMOD)
-#define SPORT1_B_DMA_DSCPTR_CUR              (REG_DMA3_DSCPTR_CUR)
-#define SPORT1_B_DMA_DSCPTR_PRV              (REG_DMA3_DSCPTR_PRV)
-#define SPORT1_B_DMA_ADDR_CUR                (REG_DMA3_ADDR_CUR)
-#define SPORT1_B_DMA_STAT                    (REG_DMA3_STAT)
-#define SPORT1_B_DMA_XCNT_CUR                (REG_DMA3_XCNT_CUR)
-#define SPORT1_B_DMA_YCNT_CUR                (REG_DMA3_YCNT_CUR)
-#define SPORT1_B_DMA_BWLCNT                  (REG_DMA3_BWLCNT)
-#define SPORT1_B_DMA_BWLCNT_CUR              (REG_DMA3_BWLCNT_CUR)
-#define SPORT1_B_DMA_BWMCNT                  (REG_DMA3_BWMCNT)
-#define SPORT1_B_DMA_BWMCNT_CUR              (REG_DMA3_BWMCNT_CUR)
-#define SPORT2_A_DMA_DSCPTR_NXT              (REG_DMA4_DSCPTR_NXT)
-#define SPORT2_A_DMA_ADDRSTART               (REG_DMA4_ADDRSTART)
-#define SPORT2_A_DMA_CFG                     (REG_DMA4_CFG)
-#define SPORT2_A_DMA_XCNT                    (REG_DMA4_XCNT)
-#define SPORT2_A_DMA_XMOD                    (REG_DMA4_XMOD)
-#define SPORT2_A_DMA_YCNT                    (REG_DMA4_YCNT)
-#define SPORT2_A_DMA_YMOD                    (REG_DMA4_YMOD)
-#define SPORT2_A_DMA_DSCPTR_CUR              (REG_DMA4_DSCPTR_CUR)
-#define SPORT2_A_DMA_DSCPTR_PRV              (REG_DMA4_DSCPTR_PRV)
-#define SPORT2_A_DMA_ADDR_CUR                (REG_DMA4_ADDR_CUR)
-#define SPORT2_A_DMA_STAT                    (REG_DMA4_STAT)
-#define SPORT2_A_DMA_XCNT_CUR                (REG_DMA4_XCNT_CUR)
-#define SPORT2_A_DMA_YCNT_CUR                (REG_DMA4_YCNT_CUR)
-#define SPORT2_A_DMA_BWLCNT                  (REG_DMA4_BWLCNT)
-#define SPORT2_A_DMA_BWLCNT_CUR              (REG_DMA4_BWLCNT_CUR)
-#define SPORT2_A_DMA_BWMCNT                  (REG_DMA4_BWMCNT)
-#define SPORT2_A_DMA_BWMCNT_CUR              (REG_DMA4_BWMCNT_CUR)
-#define SPORT2_B_DMA_DSCPTR_NXT              (REG_DMA5_DSCPTR_NXT)
-#define SPORT2_B_DMA_ADDRSTART               (REG_DMA5_ADDRSTART)
-#define SPORT2_B_DMA_CFG                     (REG_DMA5_CFG)
-#define SPORT2_B_DMA_XCNT                    (REG_DMA5_XCNT)
-#define SPORT2_B_DMA_XMOD                    (REG_DMA5_XMOD)
-#define SPORT2_B_DMA_YCNT                    (REG_DMA5_YCNT)
-#define SPORT2_B_DMA_YMOD                    (REG_DMA5_YMOD)
-#define SPORT2_B_DMA_DSCPTR_CUR              (REG_DMA5_DSCPTR_CUR)
-#define SPORT2_B_DMA_DSCPTR_PRV              (REG_DMA5_DSCPTR_PRV)
-#define SPORT2_B_DMA_ADDR_CUR                (REG_DMA5_ADDR_CUR)
-#define SPORT2_B_DMA_STAT                    (REG_DMA5_STAT)
-#define SPORT2_B_DMA_XCNT_CUR                (REG_DMA5_XCNT_CUR)
-#define SPORT2_B_DMA_YCNT_CUR                (REG_DMA5_YCNT_CUR)
-#define SPORT2_B_DMA_BWLCNT                  (REG_DMA5_BWLCNT)
-#define SPORT2_B_DMA_BWLCNT_CUR              (REG_DMA5_BWLCNT_CUR)
-#define SPORT2_B_DMA_BWMCNT                  (REG_DMA5_BWMCNT)
-#define SPORT2_B_DMA_BWMCNT_CUR              (REG_DMA5_BWMCNT_CUR)
-#define SPI0_TXDMA_DSCPTR_NXT                (REG_DMA6_DSCPTR_NXT)
-#define SPI0_TXDMA_ADDRSTART                 (REG_DMA6_ADDRSTART)
-#define SPI0_TXDMA_CFG                       (REG_DMA6_CFG)
-#define SPI0_TXDMA_XCNT                      (REG_DMA6_XCNT)
-#define SPI0_TXDMA_XMOD                      (REG_DMA6_XMOD)
-#define SPI0_TXDMA_YCNT                      (REG_DMA6_YCNT)
-#define SPI0_TXDMA_YMOD                      (REG_DMA6_YMOD)
-#define SPI0_TXDMA_DSCPTR_CUR                (REG_DMA6_DSCPTR_CUR)
-#define SPI0_TXDMA_DSCPTR_PRV                (REG_DMA6_DSCPTR_PRV)
-#define SPI0_TXDMA_ADDR_CUR                  (REG_DMA6_ADDR_CUR)
-#define SPI0_TXDMA_STAT                      (REG_DMA6_STAT)
-#define SPI0_TXDMA_XCNT_CUR                  (REG_DMA6_XCNT_CUR)
-#define SPI0_TXDMA_YCNT_CUR                  (REG_DMA6_YCNT_CUR)
-#define SPI0_TXDMA_BWLCNT                    (REG_DMA6_BWLCNT)
-#define SPI0_TXDMA_BWLCNT_CUR                (REG_DMA6_BWLCNT_CUR)
-#define SPI0_TXDMA_BWMCNT                    (REG_DMA6_BWMCNT)
-#define SPI0_TXDMA_BWMCNT_CUR                (REG_DMA6_BWMCNT_CUR)
-#define SPI0_RXDMA_DSCPTR_NXT                (REG_DMA7_DSCPTR_NXT)
-#define SPI0_RXDMA_ADDRSTART                 (REG_DMA7_ADDRSTART)
-#define SPI0_RXDMA_CFG                       (REG_DMA7_CFG)
-#define SPI0_RXDMA_XCNT                      (REG_DMA7_XCNT)
-#define SPI0_RXDMA_XMOD                      (REG_DMA7_XMOD)
-#define SPI0_RXDMA_YCNT                      (REG_DMA7_YCNT)
-#define SPI0_RXDMA_YMOD                      (REG_DMA7_YMOD)
-#define SPI0_RXDMA_DSCPTR_CUR                (REG_DMA7_DSCPTR_CUR)
-#define SPI0_RXDMA_DSCPTR_PRV                (REG_DMA7_DSCPTR_PRV)
-#define SPI0_RXDMA_ADDR_CUR                  (REG_DMA7_ADDR_CUR)
-#define SPI0_RXDMA_STAT                      (REG_DMA7_STAT)
-#define SPI0_RXDMA_XCNT_CUR                  (REG_DMA7_XCNT_CUR)
-#define SPI0_RXDMA_YCNT_CUR                  (REG_DMA7_YCNT_CUR)
-#define SPI0_RXDMA_BWLCNT                    (REG_DMA7_BWLCNT)
-#define SPI0_RXDMA_BWLCNT_CUR                (REG_DMA7_BWLCNT_CUR)
-#define SPI0_RXDMA_BWMCNT                    (REG_DMA7_BWMCNT)
-#define SPI0_RXDMA_BWMCNT_CUR                (REG_DMA7_BWMCNT_CUR)
-#define SPI1_TXDMA_DSCPTR_NXT                (REG_DMA8_DSCPTR_NXT)
-#define SPI1_TXDMA_ADDRSTART                 (REG_DMA8_ADDRSTART)
-#define SPI1_TXDMA_CFG                       (REG_DMA8_CFG)
-#define SPI1_TXDMA_XCNT                      (REG_DMA8_XCNT)
-#define SPI1_TXDMA_XMOD                      (REG_DMA8_XMOD)
-#define SPI1_TXDMA_YCNT                      (REG_DMA8_YCNT)
-#define SPI1_TXDMA_YMOD                      (REG_DMA8_YMOD)
-#define SPI1_TXDMA_DSCPTR_CUR                (REG_DMA8_DSCPTR_CUR)
-#define SPI1_TXDMA_DSCPTR_PRV                (REG_DMA8_DSCPTR_PRV)
-#define SPI1_TXDMA_ADDR_CUR                  (REG_DMA8_ADDR_CUR)
-#define SPI1_TXDMA_STAT                      (REG_DMA8_STAT)
-#define SPI1_TXDMA_XCNT_CUR                  (REG_DMA8_XCNT_CUR)
-#define SPI1_TXDMA_YCNT_CUR                  (REG_DMA8_YCNT_CUR)
-#define SPI1_TXDMA_BWLCNT                    (REG_DMA8_BWLCNT)
-#define SPI1_TXDMA_BWLCNT_CUR                (REG_DMA8_BWLCNT_CUR)
-#define SPI1_TXDMA_BWMCNT                    (REG_DMA8_BWMCNT)
-#define SPI1_TXDMA_BWMCNT_CUR                (REG_DMA8_BWMCNT_CUR)
-#define SPI1_RXDMA_DSCPTR_NXT                (REG_DMA9_DSCPTR_NXT)
-#define SPI1_RXDMA_ADDRSTART                 (REG_DMA9_ADDRSTART)
-#define SPI1_RXDMA_CFG                       (REG_DMA9_CFG)
-#define SPI1_RXDMA_XCNT                      (REG_DMA9_XCNT)
-#define SPI1_RXDMA_XMOD                      (REG_DMA9_XMOD)
-#define SPI1_RXDMA_YCNT                      (REG_DMA9_YCNT)
-#define SPI1_RXDMA_YMOD                      (REG_DMA9_YMOD)
-#define SPI1_RXDMA_DSCPTR_CUR                (REG_DMA9_DSCPTR_CUR)
-#define SPI1_RXDMA_DSCPTR_PRV                (REG_DMA9_DSCPTR_PRV)
-#define SPI1_RXDMA_ADDR_CUR                  (REG_DMA9_ADDR_CUR)
-#define SPI1_RXDMA_STAT                      (REG_DMA9_STAT)
-#define SPI1_RXDMA_XCNT_CUR                  (REG_DMA9_XCNT_CUR)
-#define SPI1_RXDMA_YCNT_CUR                  (REG_DMA9_YCNT_CUR)
-#define SPI1_RXDMA_BWLCNT                    (REG_DMA9_BWLCNT)
-#define SPI1_RXDMA_BWLCNT_CUR                (REG_DMA9_BWLCNT_CUR)
-#define SPI1_RXDMA_BWMCNT                    (REG_DMA9_BWMCNT)
-#define SPI1_RXDMA_BWMCNT_CUR                (REG_DMA9_BWMCNT_CUR)
-#define RSI0_DMA_DSCPTR_NXT                  (REG_DMA10_DSCPTR_NXT)
-#define RSI0_DMA_ADDRSTART                   (REG_DMA10_ADDRSTART)
-#define RSI0_DMA_CFG                         (REG_DMA10_CFG)
-#define RSI0_DMA_XCNT                        (REG_DMA10_XCNT)
-#define RSI0_DMA_XMOD                        (REG_DMA10_XMOD)
-#define RSI0_DMA_YCNT                        (REG_DMA10_YCNT)
-#define RSI0_DMA_YMOD                        (REG_DMA10_YMOD)
-#define RSI0_DMA_DSCPTR_CUR                  (REG_DMA10_DSCPTR_CUR)
-#define RSI0_DMA_DSCPTR_PRV                  (REG_DMA10_DSCPTR_PRV)
-#define RSI0_DMA_ADDR_CUR                    (REG_DMA10_ADDR_CUR)
-#define RSI0_DMA_STAT                        (REG_DMA10_STAT)
-#define RSI0_DMA_XCNT_CUR                    (REG_DMA10_XCNT_CUR)
-#define RSI0_DMA_YCNT_CUR                    (REG_DMA10_YCNT_CUR)
-#define RSI0_DMA_BWLCNT                      (REG_DMA10_BWLCNT)
-#define RSI0_DMA_BWLCNT_CUR                  (REG_DMA10_BWLCNT_CUR)
-#define RSI0_DMA_BWMCNT                      (REG_DMA10_BWMCNT)
-#define RSI0_DMA_BWMCNT_CUR                  (REG_DMA10_BWMCNT_CUR)
-#define SDU0_DMA_DSCPTR_NXT                  (REG_DMA11_DSCPTR_NXT)
-#define SDU0_DMA_ADDRSTART                   (REG_DMA11_ADDRSTART)
-#define SDU0_DMA_CFG                         (REG_DMA11_CFG)
-#define SDU0_DMA_XCNT                        (REG_DMA11_XCNT)
-#define SDU0_DMA_XMOD                        (REG_DMA11_XMOD)
-#define SDU0_DMA_YCNT                        (REG_DMA11_YCNT)
-#define SDU0_DMA_YMOD                        (REG_DMA11_YMOD)
-#define SDU0_DMA_DSCPTR_CUR                  (REG_DMA11_DSCPTR_CUR)
-#define SDU0_DMA_DSCPTR_PRV                  (REG_DMA11_DSCPTR_PRV)
-#define SDU0_DMA_ADDR_CUR                    (REG_DMA11_ADDR_CUR)
-#define SDU0_DMA_STAT                        (REG_DMA11_STAT)
-#define SDU0_DMA_XCNT_CUR                    (REG_DMA11_XCNT_CUR)
-#define SDU0_DMA_YCNT_CUR                    (REG_DMA11_YCNT_CUR)
-#define SDU0_DMA_BWLCNT                      (REG_DMA11_BWLCNT)
-#define SDU0_DMA_BWLCNT_CUR                  (REG_DMA11_BWLCNT_CUR)
-#define SDU0_DMA_BWMCNT                      (REG_DMA11_BWMCNT)
-#define SDU0_DMA_BWMCNT_CUR                  (REG_DMA11_BWMCNT_CUR)
-#define LP0_DMA_DSCPTR_NXT                   (REG_DMA13_DSCPTR_NXT)
-#define LP0_DMA_ADDRSTART                    (REG_DMA13_ADDRSTART)
-#define LP0_DMA_CFG                          (REG_DMA13_CFG)
-#define LP0_DMA_XCNT                         (REG_DMA13_XCNT)
-#define LP0_DMA_XMOD                         (REG_DMA13_XMOD)
-#define LP0_DMA_YCNT                         (REG_DMA13_YCNT)
-#define LP0_DMA_YMOD                         (REG_DMA13_YMOD)
-#define LP0_DMA_DSCPTR_CUR                   (REG_DMA13_DSCPTR_CUR)
-#define LP0_DMA_DSCPTR_PRV                   (REG_DMA13_DSCPTR_PRV)
-#define LP0_DMA_ADDR_CUR                     (REG_DMA13_ADDR_CUR)
-#define LP0_DMA_STAT                         (REG_DMA13_STAT)
-#define LP0_DMA_XCNT_CUR                     (REG_DMA13_XCNT_CUR)
-#define LP0_DMA_YCNT_CUR                     (REG_DMA13_YCNT_CUR)
-#define LP0_DMA_BWLCNT                       (REG_DMA13_BWLCNT)
-#define LP0_DMA_BWLCNT_CUR                   (REG_DMA13_BWLCNT_CUR)
-#define LP0_DMA_BWMCNT                       (REG_DMA13_BWMCNT)
-#define LP0_DMA_BWMCNT_CUR                   (REG_DMA13_BWMCNT_CUR)
-#define LP1_DMA_DSCPTR_NXT                   (REG_DMA14_DSCPTR_NXT)
-#define LP1_DMA_ADDRSTART                    (REG_DMA14_ADDRSTART)
-#define LP1_DMA_CFG                          (REG_DMA14_CFG)
-#define LP1_DMA_XCNT                         (REG_DMA14_XCNT)
-#define LP1_DMA_XMOD                         (REG_DMA14_XMOD)
-#define LP1_DMA_YCNT                         (REG_DMA14_YCNT)
-#define LP1_DMA_YMOD                         (REG_DMA14_YMOD)
-#define LP1_DMA_DSCPTR_CUR                   (REG_DMA14_DSCPTR_CUR)
-#define LP1_DMA_DSCPTR_PRV                   (REG_DMA14_DSCPTR_PRV)
-#define LP1_DMA_ADDR_CUR                     (REG_DMA14_ADDR_CUR)
-#define LP1_DMA_STAT                         (REG_DMA14_STAT)
-#define LP1_DMA_XCNT_CUR                     (REG_DMA14_XCNT_CUR)
-#define LP1_DMA_YCNT_CUR                     (REG_DMA14_YCNT_CUR)
-#define LP1_DMA_BWLCNT                       (REG_DMA14_BWLCNT)
-#define LP1_DMA_BWLCNT_CUR                   (REG_DMA14_BWLCNT_CUR)
-#define LP1_DMA_BWMCNT                       (REG_DMA14_BWMCNT)
-#define LP1_DMA_BWMCNT_CUR                   (REG_DMA14_BWMCNT_CUR)
-#define LP2_DMA_DSCPTR_NXT                   (REG_DMA15_DSCPTR_NXT)
-#define LP2_DMA_ADDRSTART                    (REG_DMA15_ADDRSTART)
-#define LP2_DMA_CFG                          (REG_DMA15_CFG)
-#define LP2_DMA_XCNT                         (REG_DMA15_XCNT)
-#define LP2_DMA_XMOD                         (REG_DMA15_XMOD)
-#define LP2_DMA_YCNT                         (REG_DMA15_YCNT)
-#define LP2_DMA_YMOD                         (REG_DMA15_YMOD)
-#define LP2_DMA_DSCPTR_CUR                   (REG_DMA15_DSCPTR_CUR)
-#define LP2_DMA_DSCPTR_PRV                   (REG_DMA15_DSCPTR_PRV)
-#define LP2_DMA_ADDR_CUR                     (REG_DMA15_ADDR_CUR)
-#define LP2_DMA_STAT                         (REG_DMA15_STAT)
-#define LP2_DMA_XCNT_CUR                     (REG_DMA15_XCNT_CUR)
-#define LP2_DMA_YCNT_CUR                     (REG_DMA15_YCNT_CUR)
-#define LP2_DMA_BWLCNT                       (REG_DMA15_BWLCNT)
-#define LP2_DMA_BWLCNT_CUR                   (REG_DMA15_BWLCNT_CUR)
-#define LP2_DMA_BWMCNT                       (REG_DMA15_BWMCNT)
-#define LP2_DMA_BWMCNT_CUR                   (REG_DMA15_BWMCNT_CUR)
-#define LP3_DMA_DSCPTR_NXT                   (REG_DMA16_DSCPTR_NXT)
-#define LP3_DMA_ADDRSTART                    (REG_DMA16_ADDRSTART)
-#define LP3_DMA_CFG                          (REG_DMA16_CFG)
-#define LP3_DMA_XCNT                         (REG_DMA16_XCNT)
-#define LP3_DMA_XMOD                         (REG_DMA16_XMOD)
-#define LP3_DMA_YCNT                         (REG_DMA16_YCNT)
-#define LP3_DMA_YMOD                         (REG_DMA16_YMOD)
-#define LP3_DMA_DSCPTR_CUR                   (REG_DMA16_DSCPTR_CUR)
-#define LP3_DMA_DSCPTR_PRV                   (REG_DMA16_DSCPTR_PRV)
-#define LP3_DMA_ADDR_CUR                     (REG_DMA16_ADDR_CUR)
-#define LP3_DMA_STAT                         (REG_DMA16_STAT)
-#define LP3_DMA_XCNT_CUR                     (REG_DMA16_XCNT_CUR)
-#define LP3_DMA_YCNT_CUR                     (REG_DMA16_YCNT_CUR)
-#define LP3_DMA_BWLCNT                       (REG_DMA16_BWLCNT)
-#define LP3_DMA_BWLCNT_CUR                   (REG_DMA16_BWLCNT_CUR)
-#define LP3_DMA_BWMCNT                       (REG_DMA16_BWMCNT)
-#define LP3_DMA_BWMCNT_CUR                   (REG_DMA16_BWMCNT_CUR)
-#define UART0_TXDMA_DSCPTR_NXT               (REG_DMA17_DSCPTR_NXT)
-#define UART0_TXDMA_ADDRSTART                (REG_DMA17_ADDRSTART)
-#define UART0_TXDMA_CFG                      (REG_DMA17_CFG)
-#define UART0_TXDMA_XCNT                     (REG_DMA17_XCNT)
-#define UART0_TXDMA_XMOD                     (REG_DMA17_XMOD)
-#define UART0_TXDMA_YCNT                     (REG_DMA17_YCNT)
-#define UART0_TXDMA_YMOD                     (REG_DMA17_YMOD)
-#define UART0_TXDMA_DSCPTR_CUR               (REG_DMA17_DSCPTR_CUR)
-#define UART0_TXDMA_DSCPTR_PRV               (REG_DMA17_DSCPTR_PRV)
-#define UART0_TXDMA_ADDR_CUR                 (REG_DMA17_ADDR_CUR)
-#define UART0_TXDMA_STAT                     (REG_DMA17_STAT)
-#define UART0_TXDMA_XCNT_CUR                 (REG_DMA17_XCNT_CUR)
-#define UART0_TXDMA_YCNT_CUR                 (REG_DMA17_YCNT_CUR)
-#define UART0_TXDMA_BWLCNT                   (REG_DMA17_BWLCNT)
-#define UART0_TXDMA_BWLCNT_CUR               (REG_DMA17_BWLCNT_CUR)
-#define UART0_TXDMA_BWMCNT                   (REG_DMA17_BWMCNT)
-#define UART0_TXDMA_BWMCNT_CUR               (REG_DMA17_BWMCNT_CUR)
-#define UART0_RXDMA_DSCPTR_NXT               (REG_DMA18_DSCPTR_NXT)
-#define UART0_RXDMA_ADDRSTART                (REG_DMA18_ADDRSTART)
-#define UART0_RXDMA_CFG                      (REG_DMA18_CFG)
-#define UART0_RXDMA_XCNT                     (REG_DMA18_XCNT)
-#define UART0_RXDMA_XMOD                     (REG_DMA18_XMOD)
-#define UART0_RXDMA_YCNT                     (REG_DMA18_YCNT)
-#define UART0_RXDMA_YMOD                     (REG_DMA18_YMOD)
-#define UART0_RXDMA_DSCPTR_CUR               (REG_DMA18_DSCPTR_CUR)
-#define UART0_RXDMA_DSCPTR_PRV               (REG_DMA18_DSCPTR_PRV)
-#define UART0_RXDMA_ADDR_CUR                 (REG_DMA18_ADDR_CUR)
-#define UART0_RXDMA_STAT                     (REG_DMA18_STAT)
-#define UART0_RXDMA_XCNT_CUR                 (REG_DMA18_XCNT_CUR)
-#define UART0_RXDMA_YCNT_CUR                 (REG_DMA18_YCNT_CUR)
-#define UART0_RXDMA_BWLCNT                   (REG_DMA18_BWLCNT)
-#define UART0_RXDMA_BWLCNT_CUR               (REG_DMA18_BWLCNT_CUR)
-#define UART0_RXDMA_BWMCNT                   (REG_DMA18_BWMCNT)
-#define UART0_RXDMA_BWMCNT_CUR               (REG_DMA18_BWMCNT_CUR)
-#define UART1_TXDMA_DSCPTR_NXT               (REG_DMA19_DSCPTR_NXT)
-#define UART1_TXDMA_ADDRSTART                (REG_DMA19_ADDRSTART)
-#define UART1_TXDMA_CFG                      (REG_DMA19_CFG)
-#define UART1_TXDMA_XCNT                     (REG_DMA19_XCNT)
-#define UART1_TXDMA_XMOD                     (REG_DMA19_XMOD)
-#define UART1_TXDMA_YCNT                     (REG_DMA19_YCNT)
-#define UART1_TXDMA_YMOD                     (REG_DMA19_YMOD)
-#define UART1_TXDMA_DSCPTR_CUR               (REG_DMA19_DSCPTR_CUR)
-#define UART1_TXDMA_DSCPTR_PRV               (REG_DMA19_DSCPTR_PRV)
-#define UART1_TXDMA_ADDR_CUR                 (REG_DMA19_ADDR_CUR)
-#define UART1_TXDMA_STAT                     (REG_DMA19_STAT)
-#define UART1_TXDMA_XCNT_CUR                 (REG_DMA19_XCNT_CUR)
-#define UART1_TXDMA_YCNT_CUR                 (REG_DMA19_YCNT_CUR)
-#define UART1_TXDMA_BWLCNT                   (REG_DMA19_BWLCNT)
-#define UART1_TXDMA_BWLCNT_CUR               (REG_DMA19_BWLCNT_CUR)
-#define UART1_TXDMA_BWMCNT                   (REG_DMA19_BWMCNT)
-#define UART1_TXDMA_BWMCNT_CUR               (REG_DMA19_BWMCNT_CUR)
-#define UART1_RXDMA_DSCPTR_NXT               (REG_DMA20_DSCPTR_NXT)
-#define UART1_RXDMA_ADDRSTART                (REG_DMA20_ADDRSTART)
-#define UART1_RXDMA_CFG                      (REG_DMA20_CFG)
-#define UART1_RXDMA_XCNT                     (REG_DMA20_XCNT)
-#define UART1_RXDMA_XMOD                     (REG_DMA20_XMOD)
-#define UART1_RXDMA_YCNT                     (REG_DMA20_YCNT)
-#define UART1_RXDMA_YMOD                     (REG_DMA20_YMOD)
-#define UART1_RXDMA_DSCPTR_CUR               (REG_DMA20_DSCPTR_CUR)
-#define UART1_RXDMA_DSCPTR_PRV               (REG_DMA20_DSCPTR_PRV)
-#define UART1_RXDMA_ADDR_CUR                 (REG_DMA20_ADDR_CUR)
-#define UART1_RXDMA_STAT                     (REG_DMA20_STAT)
-#define UART1_RXDMA_XCNT_CUR                 (REG_DMA20_XCNT_CUR)
-#define UART1_RXDMA_YCNT_CUR                 (REG_DMA20_YCNT_CUR)
-#define UART1_RXDMA_BWLCNT                   (REG_DMA20_BWLCNT)
-#define UART1_RXDMA_BWLCNT_CUR               (REG_DMA20_BWLCNT_CUR)
-#define UART1_RXDMA_BWMCNT                   (REG_DMA20_BWMCNT)
-#define UART1_RXDMA_BWMCNT_CUR               (REG_DMA20_BWMCNT_CUR)
-#define MDMA0_SRC_DSCPTR_NXT                 (REG_DMA21_DSCPTR_NXT)
-#define MDMA0_SRC_ADDRSTART                  (REG_DMA21_ADDRSTART)
-#define MDMA0_SRC_CFG                        (REG_DMA21_CFG)
-#define MDMA0_SRC_XCNT                       (REG_DMA21_XCNT)
-#define MDMA0_SRC_XMOD                       (REG_DMA21_XMOD)
-#define MDMA0_SRC_YCNT                       (REG_DMA21_YCNT)
-#define MDMA0_SRC_YMOD                       (REG_DMA21_YMOD)
-#define MDMA0_SRC_DSCPTR_CUR                 (REG_DMA21_DSCPTR_CUR)
-#define MDMA0_SRC_DSCPTR_PRV                 (REG_DMA21_DSCPTR_PRV)
-#define MDMA0_SRC_ADDR_CUR                   (REG_DMA21_ADDR_CUR)
-#define MDMA0_SRC_STAT                       (REG_DMA21_STAT)
-#define MDMA0_SRC_XCNT_CUR                   (REG_DMA21_XCNT_CUR)
-#define MDMA0_SRC_YCNT_CUR                   (REG_DMA21_YCNT_CUR)
-#define MDMA0_SRC_BWLCNT                     (REG_DMA21_BWLCNT)
-#define MDMA0_SRC_BWLCNT_CUR                 (REG_DMA21_BWLCNT_CUR)
-#define MDMA0_SRC_BWMCNT                     (REG_DMA21_BWMCNT)
-#define MDMA0_SRC_BWMCNT_CUR                 (REG_DMA21_BWMCNT_CUR)
-#define MDMA0_DST_DSCPTR_NXT                 (REG_DMA22_DSCPTR_NXT)
-#define MDMA0_DST_ADDRSTART                  (REG_DMA22_ADDRSTART)
-#define MDMA0_DST_CFG                        (REG_DMA22_CFG)
-#define MDMA0_DST_XCNT                       (REG_DMA22_XCNT)
-#define MDMA0_DST_XMOD                       (REG_DMA22_XMOD)
-#define MDMA0_DST_YCNT                       (REG_DMA22_YCNT)
-#define MDMA0_DST_YMOD                       (REG_DMA22_YMOD)
-#define MDMA0_DST_DSCPTR_CUR                 (REG_DMA22_DSCPTR_CUR)
-#define MDMA0_DST_DSCPTR_PRV                 (REG_DMA22_DSCPTR_PRV)
-#define MDMA0_DST_ADDR_CUR                   (REG_DMA22_ADDR_CUR)
-#define MDMA0_DST_STAT                       (REG_DMA22_STAT)
-#define MDMA0_DST_XCNT_CUR                   (REG_DMA22_XCNT_CUR)
-#define MDMA0_DST_YCNT_CUR                   (REG_DMA22_YCNT_CUR)
-#define MDMA0_DST_BWLCNT                     (REG_DMA22_BWLCNT)
-#define MDMA0_DST_BWLCNT_CUR                 (REG_DMA22_BWLCNT_CUR)
-#define MDMA0_DST_BWMCNT                     (REG_DMA22_BWMCNT)
-#define MDMA0_DST_BWMCNT_CUR                 (REG_DMA22_BWMCNT_CUR)
-#define MDMA1_SRC_DSCPTR_NXT                 (REG_DMA23_DSCPTR_NXT)
-#define MDMA1_SRC_ADDRSTART                  (REG_DMA23_ADDRSTART)
-#define MDMA1_SRC_CFG                        (REG_DMA23_CFG)
-#define MDMA1_SRC_XCNT                       (REG_DMA23_XCNT)
-#define MDMA1_SRC_XMOD                       (REG_DMA23_XMOD)
-#define MDMA1_SRC_YCNT                       (REG_DMA23_YCNT)
-#define MDMA1_SRC_YMOD                       (REG_DMA23_YMOD)
-#define MDMA1_SRC_DSCPTR_CUR                 (REG_DMA23_DSCPTR_CUR)
-#define MDMA1_SRC_DSCPTR_PRV                 (REG_DMA23_DSCPTR_PRV)
-#define MDMA1_SRC_ADDR_CUR                   (REG_DMA23_ADDR_CUR)
-#define MDMA1_SRC_STAT                       (REG_DMA23_STAT)
-#define MDMA1_SRC_XCNT_CUR                   (REG_DMA23_XCNT_CUR)
-#define MDMA1_SRC_YCNT_CUR                   (REG_DMA23_YCNT_CUR)
-#define MDMA1_SRC_BWLCNT                     (REG_DMA23_BWLCNT)
-#define MDMA1_SRC_BWLCNT_CUR                 (REG_DMA23_BWLCNT_CUR)
-#define MDMA1_SRC_BWMCNT                     (REG_DMA23_BWMCNT)
-#define MDMA1_SRC_BWMCNT_CUR                 (REG_DMA23_BWMCNT_CUR)
-#define MDMA1_DST_DSCPTR_NXT                 (REG_DMA24_DSCPTR_NXT)
-#define MDMA1_DST_ADDRSTART                  (REG_DMA24_ADDRSTART)
-#define MDMA1_DST_CFG                        (REG_DMA24_CFG)
-#define MDMA1_DST_XCNT                       (REG_DMA24_XCNT)
-#define MDMA1_DST_XMOD                       (REG_DMA24_XMOD)
-#define MDMA1_DST_YCNT                       (REG_DMA24_YCNT)
-#define MDMA1_DST_YMOD                       (REG_DMA24_YMOD)
-#define MDMA1_DST_DSCPTR_CUR                 (REG_DMA24_DSCPTR_CUR)
-#define MDMA1_DST_DSCPTR_PRV                 (REG_DMA24_DSCPTR_PRV)
-#define MDMA1_DST_ADDR_CUR                   (REG_DMA24_ADDR_CUR)
-#define MDMA1_DST_STAT                       (REG_DMA24_STAT)
-#define MDMA1_DST_XCNT_CUR                   (REG_DMA24_XCNT_CUR)
-#define MDMA1_DST_YCNT_CUR                   (REG_DMA24_YCNT_CUR)
-#define MDMA1_DST_BWLCNT                     (REG_DMA24_BWLCNT)
-#define MDMA1_DST_BWLCNT_CUR                 (REG_DMA24_BWLCNT_CUR)
-#define MDMA1_DST_BWMCNT                     (REG_DMA24_BWMCNT)
-#define MDMA1_DST_BWMCNT_CUR                 (REG_DMA24_BWMCNT_CUR)
-#define MDMA2_SRC_DSCPTR_NXT                 (REG_DMA25_DSCPTR_NXT)
-#define MDMA2_SRC_ADDRSTART                  (REG_DMA25_ADDRSTART)
-#define MDMA2_SRC_CFG                        (REG_DMA25_CFG)
-#define MDMA2_SRC_XCNT                       (REG_DMA25_XCNT)
-#define MDMA2_SRC_XMOD                       (REG_DMA25_XMOD)
-#define MDMA2_SRC_YCNT                       (REG_DMA25_YCNT)
-#define MDMA2_SRC_YMOD                       (REG_DMA25_YMOD)
-#define MDMA2_SRC_DSCPTR_CUR                 (REG_DMA25_DSCPTR_CUR)
-#define MDMA2_SRC_DSCPTR_PRV                 (REG_DMA25_DSCPTR_PRV)
-#define MDMA2_SRC_ADDR_CUR                   (REG_DMA25_ADDR_CUR)
-#define MDMA2_SRC_STAT                       (REG_DMA25_STAT)
-#define MDMA2_SRC_XCNT_CUR                   (REG_DMA25_XCNT_CUR)
-#define MDMA2_SRC_YCNT_CUR                   (REG_DMA25_YCNT_CUR)
-#define MDMA2_SRC_BWLCNT                     (REG_DMA25_BWLCNT)
-#define MDMA2_SRC_BWLCNT_CUR                 (REG_DMA25_BWLCNT_CUR)
-#define MDMA2_SRC_BWMCNT                     (REG_DMA25_BWMCNT)
-#define MDMA2_SRC_BWMCNT_CUR                 (REG_DMA25_BWMCNT_CUR)
-#define MDMA2_DST_DSCPTR_NXT                 (REG_DMA26_DSCPTR_NXT)
-#define MDMA2_DST_ADDRSTART                  (REG_DMA26_ADDRSTART)
-#define MDMA2_DST_CFG                        (REG_DMA26_CFG)
-#define MDMA2_DST_XCNT                       (REG_DMA26_XCNT)
-#define MDMA2_DST_XMOD                       (REG_DMA26_XMOD)
-#define MDMA2_DST_YCNT                       (REG_DMA26_YCNT)
-#define MDMA2_DST_YMOD                       (REG_DMA26_YMOD)
-#define MDMA2_DST_DSCPTR_CUR                 (REG_DMA26_DSCPTR_CUR)
-#define MDMA2_DST_DSCPTR_PRV                 (REG_DMA26_DSCPTR_PRV)
-#define MDMA2_DST_ADDR_CUR                   (REG_DMA26_ADDR_CUR)
-#define MDMA2_DST_STAT                       (REG_DMA26_STAT)
-#define MDMA2_DST_XCNT_CUR                   (REG_DMA26_XCNT_CUR)
-#define MDMA2_DST_YCNT_CUR                   (REG_DMA26_YCNT_CUR)
-#define MDMA2_DST_BWLCNT                     (REG_DMA26_BWLCNT)
-#define MDMA2_DST_BWLCNT_CUR                 (REG_DMA26_BWLCNT_CUR)
-#define MDMA2_DST_BWMCNT                     (REG_DMA26_BWMCNT)
-#define MDMA2_DST_BWMCNT_CUR                 (REG_DMA26_BWMCNT_CUR)
-#define MDMA3_SRC_DSCPTR_NXT                 (REG_DMA27_DSCPTR_NXT)
-#define MDMA3_SRC_ADDRSTART                  (REG_DMA27_ADDRSTART)
-#define MDMA3_SRC_CFG                        (REG_DMA27_CFG)
-#define MDMA3_SRC_XCNT                       (REG_DMA27_XCNT)
-#define MDMA3_SRC_XMOD                       (REG_DMA27_XMOD)
-#define MDMA3_SRC_YCNT                       (REG_DMA27_YCNT)
-#define MDMA3_SRC_YMOD                       (REG_DMA27_YMOD)
-#define MDMA3_SRC_DSCPTR_CUR                 (REG_DMA27_DSCPTR_CUR)
-#define MDMA3_SRC_DSCPTR_PRV                 (REG_DMA27_DSCPTR_PRV)
-#define MDMA3_SRC_ADDR_CUR                   (REG_DMA27_ADDR_CUR)
-#define MDMA3_SRC_STAT                       (REG_DMA27_STAT)
-#define MDMA3_SRC_XCNT_CUR                   (REG_DMA27_XCNT_CUR)
-#define MDMA3_SRC_YCNT_CUR                   (REG_DMA27_YCNT_CUR)
-#define MDMA3_SRC_BWLCNT                     (REG_DMA27_BWLCNT)
-#define MDMA3_SRC_BWLCNT_CUR                 (REG_DMA27_BWLCNT_CUR)
-#define MDMA3_SRC_BWMCNT                     (REG_DMA27_BWMCNT)
-#define MDMA3_SRC_BWMCNT_CUR                 (REG_DMA27_BWMCNT_CUR)
-#define MDMA3_DST_DSCPTR_NXT                 (REG_DMA28_DSCPTR_NXT)
-#define MDMA3_DST_ADDRSTART                  (REG_DMA28_ADDRSTART)
-#define MDMA3_DST_CFG                        (REG_DMA28_CFG)
-#define MDMA3_DST_XCNT                       (REG_DMA28_XCNT)
-#define MDMA3_DST_XMOD                       (REG_DMA28_XMOD)
-#define MDMA3_DST_YCNT                       (REG_DMA28_YCNT)
-#define MDMA3_DST_YMOD                       (REG_DMA28_YMOD)
-#define MDMA3_DST_DSCPTR_CUR                 (REG_DMA28_DSCPTR_CUR)
-#define MDMA3_DST_DSCPTR_PRV                 (REG_DMA28_DSCPTR_PRV)
-#define MDMA3_DST_ADDR_CUR                   (REG_DMA28_ADDR_CUR)
-#define MDMA3_DST_STAT                       (REG_DMA28_STAT)
-#define MDMA3_DST_XCNT_CUR                   (REG_DMA28_XCNT_CUR)
-#define MDMA3_DST_YCNT_CUR                   (REG_DMA28_YCNT_CUR)
-#define MDMA3_DST_BWLCNT                     (REG_DMA28_BWLCNT)
-#define MDMA3_DST_BWLCNT_CUR                 (REG_DMA28_BWLCNT_CUR)
-#define MDMA3_DST_BWMCNT                     (REG_DMA28_BWMCNT)
-#define MDMA3_DST_BWMCNT_CUR                 (REG_DMA28_BWMCNT_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_NXT             (REG_DMA29_DSCPTR_NXT)
-#define EPPI0_CH0_DMA_ADDRSTART              (REG_DMA29_ADDRSTART)
-#define EPPI0_CH0_DMA_CFG                    (REG_DMA29_CFG)
-#define EPPI0_CH0_DMA_XCNT                   (REG_DMA29_XCNT)
-#define EPPI0_CH0_DMA_XMOD                   (REG_DMA29_XMOD)
-#define EPPI0_CH0_DMA_YCNT                   (REG_DMA29_YCNT)
-#define EPPI0_CH0_DMA_YMOD                   (REG_DMA29_YMOD)
-#define EPPI0_CH0_DMA_DSCPTR_CUR             (REG_DMA29_DSCPTR_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_PRV             (REG_DMA29_DSCPTR_PRV)
-#define EPPI0_CH0_DMA_ADDR_CUR               (REG_DMA29_ADDR_CUR)
-#define EPPI0_CH0_DMA_STAT                   (REG_DMA29_STAT)
-#define EPPI0_CH0_DMA_XCNT_CUR               (REG_DMA29_XCNT_CUR)
-#define EPPI0_CH0_DMA_YCNT_CUR               (REG_DMA29_YCNT_CUR)
-#define EPPI0_CH0_DMA_BWLCNT                 (REG_DMA29_BWLCNT)
-#define EPPI0_CH0_DMA_BWLCNT_CUR             (REG_DMA29_BWLCNT_CUR)
-#define EPPI0_CH0_DMA_BWMCNT                 (REG_DMA29_BWMCNT)
-#define EPPI0_CH0_DMA_BWMCNT_CUR             (REG_DMA29_BWMCNT_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_NXT             (REG_DMA30_DSCPTR_NXT)
-#define EPPI0_CH1_DMA_ADDRSTART              (REG_DMA30_ADDRSTART)
-#define EPPI0_CH1_DMA_CFG                    (REG_DMA30_CFG)
-#define EPPI0_CH1_DMA_XCNT                   (REG_DMA30_XCNT)
-#define EPPI0_CH1_DMA_XMOD                   (REG_DMA30_XMOD)
-#define EPPI0_CH1_DMA_YCNT                   (REG_DMA30_YCNT)
-#define EPPI0_CH1_DMA_YMOD                   (REG_DMA30_YMOD)
-#define EPPI0_CH1_DMA_DSCPTR_CUR             (REG_DMA30_DSCPTR_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_PRV             (REG_DMA30_DSCPTR_PRV)
-#define EPPI0_CH1_DMA_ADDR_CUR               (REG_DMA30_ADDR_CUR)
-#define EPPI0_CH1_DMA_STAT                   (REG_DMA30_STAT)
-#define EPPI0_CH1_DMA_XCNT_CUR               (REG_DMA30_XCNT_CUR)
-#define EPPI0_CH1_DMA_YCNT_CUR               (REG_DMA30_YCNT_CUR)
-#define EPPI0_CH1_DMA_BWLCNT                 (REG_DMA30_BWLCNT)
-#define EPPI0_CH1_DMA_BWLCNT_CUR             (REG_DMA30_BWLCNT_CUR)
-#define EPPI0_CH1_DMA_BWMCNT                 (REG_DMA30_BWMCNT)
-#define EPPI0_CH1_DMA_BWMCNT_CUR             (REG_DMA30_BWMCNT_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_NXT             (REG_DMA31_DSCPTR_NXT)
-#define EPPI2_CH0_DMA_ADDRSTART              (REG_DMA31_ADDRSTART)
-#define EPPI2_CH0_DMA_CFG                    (REG_DMA31_CFG)
-#define EPPI2_CH0_DMA_XCNT                   (REG_DMA31_XCNT)
-#define EPPI2_CH0_DMA_XMOD                   (REG_DMA31_XMOD)
-#define EPPI2_CH0_DMA_YCNT                   (REG_DMA31_YCNT)
-#define EPPI2_CH0_DMA_YMOD                   (REG_DMA31_YMOD)
-#define EPPI2_CH0_DMA_DSCPTR_CUR             (REG_DMA31_DSCPTR_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_PRV             (REG_DMA31_DSCPTR_PRV)
-#define EPPI2_CH0_DMA_ADDR_CUR               (REG_DMA31_ADDR_CUR)
-#define EPPI2_CH0_DMA_STAT                   (REG_DMA31_STAT)
-#define EPPI2_CH0_DMA_XCNT_CUR               (REG_DMA31_XCNT_CUR)
-#define EPPI2_CH0_DMA_YCNT_CUR               (REG_DMA31_YCNT_CUR)
-#define EPPI2_CH0_DMA_BWLCNT                 (REG_DMA31_BWLCNT)
-#define EPPI2_CH0_DMA_BWLCNT_CUR             (REG_DMA31_BWLCNT_CUR)
-#define EPPI2_CH0_DMA_BWMCNT                 (REG_DMA31_BWMCNT)
-#define EPPI2_CH0_DMA_BWMCNT_CUR             (REG_DMA31_BWMCNT_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_NXT             (REG_DMA32_DSCPTR_NXT)
-#define EPPI2_CH1_DMA_ADDRSTART              (REG_DMA32_ADDRSTART)
-#define EPPI2_CH1_DMA_CFG                    (REG_DMA32_CFG)
-#define EPPI2_CH1_DMA_XCNT                   (REG_DMA32_XCNT)
-#define EPPI2_CH1_DMA_XMOD                   (REG_DMA32_XMOD)
-#define EPPI2_CH1_DMA_YCNT                   (REG_DMA32_YCNT)
-#define EPPI2_CH1_DMA_YMOD                   (REG_DMA32_YMOD)
-#define EPPI2_CH1_DMA_DSCPTR_CUR             (REG_DMA32_DSCPTR_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_PRV             (REG_DMA32_DSCPTR_PRV)
-#define EPPI2_CH1_DMA_ADDR_CUR               (REG_DMA32_ADDR_CUR)
-#define EPPI2_CH1_DMA_STAT                   (REG_DMA32_STAT)
-#define EPPI2_CH1_DMA_XCNT_CUR               (REG_DMA32_XCNT_CUR)
-#define EPPI2_CH1_DMA_YCNT_CUR               (REG_DMA32_YCNT_CUR)
-#define EPPI2_CH1_DMA_BWLCNT                 (REG_DMA32_BWLCNT)
-#define EPPI2_CH1_DMA_BWLCNT_CUR             (REG_DMA32_BWLCNT_CUR)
-#define EPPI2_CH1_DMA_BWMCNT                 (REG_DMA32_BWMCNT)
-#define EPPI2_CH1_DMA_BWMCNT_CUR             (REG_DMA32_BWMCNT_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_NXT             (REG_DMA33_DSCPTR_NXT)
-#define EPPI1_CH0_DMA_ADDRSTART              (REG_DMA33_ADDRSTART)
-#define EPPI1_CH0_DMA_CFG                    (REG_DMA33_CFG)
-#define EPPI1_CH0_DMA_XCNT                   (REG_DMA33_XCNT)
-#define EPPI1_CH0_DMA_XMOD                   (REG_DMA33_XMOD)
-#define EPPI1_CH0_DMA_YCNT                   (REG_DMA33_YCNT)
-#define EPPI1_CH0_DMA_YMOD                   (REG_DMA33_YMOD)
-#define EPPI1_CH0_DMA_DSCPTR_CUR             (REG_DMA33_DSCPTR_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_PRV             (REG_DMA33_DSCPTR_PRV)
-#define EPPI1_CH0_DMA_ADDR_CUR               (REG_DMA33_ADDR_CUR)
-#define EPPI1_CH0_DMA_STAT                   (REG_DMA33_STAT)
-#define EPPI1_CH0_DMA_XCNT_CUR               (REG_DMA33_XCNT_CUR)
-#define EPPI1_CH0_DMA_YCNT_CUR               (REG_DMA33_YCNT_CUR)
-#define EPPI1_CH0_DMA_BWLCNT                 (REG_DMA33_BWLCNT)
-#define EPPI1_CH0_DMA_BWLCNT_CUR             (REG_DMA33_BWLCNT_CUR)
-#define EPPI1_CH0_DMA_BWMCNT                 (REG_DMA33_BWMCNT)
-#define EPPI1_CH0_DMA_BWMCNT_CUR             (REG_DMA33_BWMCNT_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_NXT             (REG_DMA34_DSCPTR_NXT)
-#define EPPI1_CH1_DMA_ADDRSTART              (REG_DMA34_ADDRSTART)
-#define EPPI1_CH1_DMA_CFG                    (REG_DMA34_CFG)
-#define EPPI1_CH1_DMA_XCNT                   (REG_DMA34_XCNT)
-#define EPPI1_CH1_DMA_XMOD                   (REG_DMA34_XMOD)
-#define EPPI1_CH1_DMA_YCNT                   (REG_DMA34_YCNT)
-#define EPPI1_CH1_DMA_YMOD                   (REG_DMA34_YMOD)
-#define EPPI1_CH1_DMA_DSCPTR_CUR             (REG_DMA34_DSCPTR_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_PRV             (REG_DMA34_DSCPTR_PRV)
-#define EPPI1_CH1_DMA_ADDR_CUR               (REG_DMA34_ADDR_CUR)
-#define EPPI1_CH1_DMA_STAT                   (REG_DMA34_STAT)
-#define EPPI1_CH1_DMA_XCNT_CUR               (REG_DMA34_XCNT_CUR)
-#define EPPI1_CH1_DMA_YCNT_CUR               (REG_DMA34_YCNT_CUR)
-#define EPPI1_CH1_DMA_BWLCNT                 (REG_DMA34_BWLCNT)
-#define EPPI1_CH1_DMA_BWLCNT_CUR             (REG_DMA34_BWLCNT_CUR)
-#define EPPI1_CH1_DMA_BWMCNT                 (REG_DMA34_BWMCNT)
-#define EPPI1_CH1_DMA_BWMCNT_CUR             (REG_DMA34_BWMCNT_CUR)
-#define PIXC0_CH0_DMA_DSCPTR_NXT             (REG_DMA35_DSCPTR_NXT)
-#define PIXC0_CH0_DMA_ADDRSTART              (REG_DMA35_ADDRSTART)
-#define PIXC0_CH0_DMA_CFG                    (REG_DMA35_CFG)
-#define PIXC0_CH0_DMA_XCNT                   (REG_DMA35_XCNT)
-#define PIXC0_CH0_DMA_XMOD                   (REG_DMA35_XMOD)
-#define PIXC0_CH0_DMA_YCNT                   (REG_DMA35_YCNT)
-#define PIXC0_CH0_DMA_YMOD                   (REG_DMA35_YMOD)
-#define PIXC0_CH0_DMA_DSCPTR_CUR             (REG_DMA35_DSCPTR_CUR)
-#define PIXC0_CH0_DMA_DSCPTR_PRV             (REG_DMA35_DSCPTR_PRV)
-#define PIXC0_CH0_DMA_ADDR_CUR               (REG_DMA35_ADDR_CUR)
-#define PIXC0_CH0_DMA_STAT                   (REG_DMA35_STAT)
-#define PIXC0_CH0_DMA_XCNT_CUR               (REG_DMA35_XCNT_CUR)
-#define PIXC0_CH0_DMA_YCNT_CUR               (REG_DMA35_YCNT_CUR)
-#define PIXC0_CH0_DMA_BWLCNT                 (REG_DMA35_BWLCNT)
-#define PIXC0_CH0_DMA_BWLCNT_CUR             (REG_DMA35_BWLCNT_CUR)
-#define PIXC0_CH0_DMA_BWMCNT                 (REG_DMA35_BWMCNT)
-#define PIXC0_CH0_DMA_BWMCNT_CUR             (REG_DMA35_BWMCNT_CUR)
-#define PIXC0_CH1_DMA_DSCPTR_NXT             (REG_DMA36_DSCPTR_NXT)
-#define PIXC0_CH1_DMA_ADDRSTART              (REG_DMA36_ADDRSTART)
-#define PIXC0_CH1_DMA_CFG                    (REG_DMA36_CFG)
-#define PIXC0_CH1_DMA_XCNT                   (REG_DMA36_XCNT)
-#define PIXC0_CH1_DMA_XMOD                   (REG_DMA36_XMOD)
-#define PIXC0_CH1_DMA_YCNT                   (REG_DMA36_YCNT)
-#define PIXC0_CH1_DMA_YMOD                   (REG_DMA36_YMOD)
-#define PIXC0_CH1_DMA_DSCPTR_CUR             (REG_DMA36_DSCPTR_CUR)
-#define PIXC0_CH1_DMA_DSCPTR_PRV             (REG_DMA36_DSCPTR_PRV)
-#define PIXC0_CH1_DMA_ADDR_CUR               (REG_DMA36_ADDR_CUR)
-#define PIXC0_CH1_DMA_STAT                   (REG_DMA36_STAT)
-#define PIXC0_CH1_DMA_XCNT_CUR               (REG_DMA36_XCNT_CUR)
-#define PIXC0_CH1_DMA_YCNT_CUR               (REG_DMA36_YCNT_CUR)
-#define PIXC0_CH1_DMA_BWLCNT                 (REG_DMA36_BWLCNT)
-#define PIXC0_CH1_DMA_BWLCNT_CUR             (REG_DMA36_BWLCNT_CUR)
-#define PIXC0_CH1_DMA_BWMCNT                 (REG_DMA36_BWMCNT)
-#define PIXC0_CH1_DMA_BWMCNT_CUR             (REG_DMA36_BWMCNT_CUR)
-#define PIXC0_CH2_DMA_DSCPTR_NXT             (REG_DMA37_DSCPTR_NXT)
-#define PIXC0_CH2_DMA_ADDRSTART              (REG_DMA37_ADDRSTART)
-#define PIXC0_CH2_DMA_CFG                    (REG_DMA37_CFG)
-#define PIXC0_CH2_DMA_XCNT                   (REG_DMA37_XCNT)
-#define PIXC0_CH2_DMA_XMOD                   (REG_DMA37_XMOD)
-#define PIXC0_CH2_DMA_YCNT                   (REG_DMA37_YCNT)
-#define PIXC0_CH2_DMA_YMOD                   (REG_DMA37_YMOD)
-#define PIXC0_CH2_DMA_DSCPTR_CUR             (REG_DMA37_DSCPTR_CUR)
-#define PIXC0_CH2_DMA_DSCPTR_PRV             (REG_DMA37_DSCPTR_PRV)
-#define PIXC0_CH2_DMA_ADDR_CUR               (REG_DMA37_ADDR_CUR)
-#define PIXC0_CH2_DMA_STAT                   (REG_DMA37_STAT)
-#define PIXC0_CH2_DMA_XCNT_CUR               (REG_DMA37_XCNT_CUR)
-#define PIXC0_CH2_DMA_YCNT_CUR               (REG_DMA37_YCNT_CUR)
-#define PIXC0_CH2_DMA_BWLCNT                 (REG_DMA37_BWLCNT)
-#define PIXC0_CH2_DMA_BWLCNT_CUR             (REG_DMA37_BWLCNT_CUR)
-#define PIXC0_CH2_DMA_BWMCNT                 (REG_DMA37_BWMCNT)
-#define PIXC0_CH2_DMA_BWMCNT_CUR             (REG_DMA37_BWMCNT_CUR)
-#define PVP0_CPDOB_DMA_DSCPTR_NXT            (REG_DMA38_DSCPTR_NXT)
-#define PVP0_CPDOB_DMA_ADDRSTART             (REG_DMA38_ADDRSTART)
-#define PVP0_CPDOB_DMA_CFG                   (REG_DMA38_CFG)
-#define PVP0_CPDOB_DMA_XCNT                  (REG_DMA38_XCNT)
-#define PVP0_CPDOB_DMA_XMOD                  (REG_DMA38_XMOD)
-#define PVP0_CPDOB_DMA_YCNT                  (REG_DMA38_YCNT)
-#define PVP0_CPDOB_DMA_YMOD                  (REG_DMA38_YMOD)
-#define PVP0_CPDOB_DMA_DSCPTR_CUR            (REG_DMA38_DSCPTR_CUR)
-#define PVP0_CPDOB_DMA_DSCPTR_PRV            (REG_DMA38_DSCPTR_PRV)
-#define PVP0_CPDOB_DMA_ADDR_CUR              (REG_DMA38_ADDR_CUR)
-#define PVP0_CPDOB_DMA_STAT                  (REG_DMA38_STAT)
-#define PVP0_CPDOB_DMA_XCNT_CUR              (REG_DMA38_XCNT_CUR)
-#define PVP0_CPDOB_DMA_YCNT_CUR              (REG_DMA38_YCNT_CUR)
-#define PVP0_CPDOB_DMA_BWLCNT                (REG_DMA38_BWLCNT)
-#define PVP0_CPDOB_DMA_BWLCNT_CUR            (REG_DMA38_BWLCNT_CUR)
-#define PVP0_CPDOB_DMA_BWMCNT                (REG_DMA38_BWMCNT)
-#define PVP0_CPDOB_DMA_BWMCNT_CUR            (REG_DMA38_BWMCNT_CUR)
-#define PVP0_CPDOC_DMA_DSCPTR_NXT            (REG_DMA39_DSCPTR_NXT)
-#define PVP0_CPDOC_DMA_ADDRSTART             (REG_DMA39_ADDRSTART)
-#define PVP0_CPDOC_DMA_CFG                   (REG_DMA39_CFG)
-#define PVP0_CPDOC_DMA_XCNT                  (REG_DMA39_XCNT)
-#define PVP0_CPDOC_DMA_XMOD                  (REG_DMA39_XMOD)
-#define PVP0_CPDOC_DMA_YCNT                  (REG_DMA39_YCNT)
-#define PVP0_CPDOC_DMA_YMOD                  (REG_DMA39_YMOD)
-#define PVP0_CPDOC_DMA_DSCPTR_CUR            (REG_DMA39_DSCPTR_CUR)
-#define PVP0_CPDOC_DMA_DSCPTR_PRV            (REG_DMA39_DSCPTR_PRV)
-#define PVP0_CPDOC_DMA_ADDR_CUR              (REG_DMA39_ADDR_CUR)
-#define PVP0_CPDOC_DMA_STAT                  (REG_DMA39_STAT)
-#define PVP0_CPDOC_DMA_XCNT_CUR              (REG_DMA39_XCNT_CUR)
-#define PVP0_CPDOC_DMA_YCNT_CUR              (REG_DMA39_YCNT_CUR)
-#define PVP0_CPDOC_DMA_BWLCNT                (REG_DMA39_BWLCNT)
-#define PVP0_CPDOC_DMA_BWLCNT_CUR            (REG_DMA39_BWLCNT_CUR)
-#define PVP0_CPDOC_DMA_BWMCNT                (REG_DMA39_BWMCNT)
-#define PVP0_CPDOC_DMA_BWMCNT_CUR            (REG_DMA39_BWMCNT_CUR)
-#define PVP0_CPSTAT_DMA_DSCPTR_NXT           (REG_DMA40_DSCPTR_NXT)
-#define PVP0_CPSTAT_DMA_ADDRSTART            (REG_DMA40_ADDRSTART)
-#define PVP0_CPSTAT_DMA_CFG                  (REG_DMA40_CFG)
-#define PVP0_CPSTAT_DMA_XCNT                 (REG_DMA40_XCNT)
-#define PVP0_CPSTAT_DMA_XMOD                 (REG_DMA40_XMOD)
-#define PVP0_CPSTAT_DMA_YCNT                 (REG_DMA40_YCNT)
-#define PVP0_CPSTAT_DMA_YMOD                 (REG_DMA40_YMOD)
-#define PVP0_CPSTAT_DMA_DSCPTR_CUR           (REG_DMA40_DSCPTR_CUR)
-#define PVP0_CPSTAT_DMA_DSCPTR_PRV           (REG_DMA40_DSCPTR_PRV)
-#define PVP0_CPSTAT_DMA_ADDR_CUR             (REG_DMA40_ADDR_CUR)
-#define PVP0_CPSTAT_DMA_STAT                 (REG_DMA40_STAT)
-#define PVP0_CPSTAT_DMA_XCNT_CUR             (REG_DMA40_XCNT_CUR)
-#define PVP0_CPSTAT_DMA_YCNT_CUR             (REG_DMA40_YCNT_CUR)
-#define PVP0_CPSTAT_DMA_BWLCNT               (REG_DMA40_BWLCNT)
-#define PVP0_CPSTAT_DMA_BWLCNT_CUR           (REG_DMA40_BWLCNT_CUR)
-#define PVP0_CPSTAT_DMA_BWMCNT               (REG_DMA40_BWMCNT)
-#define PVP0_CPSTAT_DMA_BWMCNT_CUR           (REG_DMA40_BWMCNT_CUR)
-#define PVP0_CPCI_DMA_DSCPTR_NXT             (REG_DMA41_DSCPTR_NXT)
-#define PVP0_CPCI_DMA_ADDRSTART              (REG_DMA41_ADDRSTART)
-#define PVP0_CPCI_DMA_CFG                    (REG_DMA41_CFG)
-#define PVP0_CPCI_DMA_XCNT                   (REG_DMA41_XCNT)
-#define PVP0_CPCI_DMA_XMOD                   (REG_DMA41_XMOD)
-#define PVP0_CPCI_DMA_YCNT                   (REG_DMA41_YCNT)
-#define PVP0_CPCI_DMA_YMOD                   (REG_DMA41_YMOD)
-#define PVP0_CPCI_DMA_DSCPTR_CUR             (REG_DMA41_DSCPTR_CUR)
-#define PVP0_CPCI_DMA_DSCPTR_PRV             (REG_DMA41_DSCPTR_PRV)
-#define PVP0_CPCI_DMA_ADDR_CUR               (REG_DMA41_ADDR_CUR)
-#define PVP0_CPCI_DMA_STAT                   (REG_DMA41_STAT)
-#define PVP0_CPCI_DMA_XCNT_CUR               (REG_DMA41_XCNT_CUR)
-#define PVP0_CPCI_DMA_YCNT_CUR               (REG_DMA41_YCNT_CUR)
-#define PVP0_CPCI_DMA_BWLCNT                 (REG_DMA41_BWLCNT)
-#define PVP0_CPCI_DMA_BWLCNT_CUR             (REG_DMA41_BWLCNT_CUR)
-#define PVP0_CPCI_DMA_BWMCNT                 (REG_DMA41_BWMCNT)
-#define PVP0_CPCI_DMA_BWMCNT_CUR             (REG_DMA41_BWMCNT_CUR)
-#define PVP0_MPDO_DMA_DSCPTR_NXT             (REG_DMA42_DSCPTR_NXT)
-#define PVP0_MPDO_DMA_ADDRSTART              (REG_DMA42_ADDRSTART)
-#define PVP0_MPDO_DMA_CFG                    (REG_DMA42_CFG)
-#define PVP0_MPDO_DMA_XCNT                   (REG_DMA42_XCNT)
-#define PVP0_MPDO_DMA_XMOD                   (REG_DMA42_XMOD)
-#define PVP0_MPDO_DMA_YCNT                   (REG_DMA42_YCNT)
-#define PVP0_MPDO_DMA_YMOD                   (REG_DMA42_YMOD)
-#define PVP0_MPDO_DMA_DSCPTR_CUR             (REG_DMA42_DSCPTR_CUR)
-#define PVP0_MPDO_DMA_DSCPTR_PRV             (REG_DMA42_DSCPTR_PRV)
-#define PVP0_MPDO_DMA_ADDR_CUR               (REG_DMA42_ADDR_CUR)
-#define PVP0_MPDO_DMA_STAT                   (REG_DMA42_STAT)
-#define PVP0_MPDO_DMA_XCNT_CUR               (REG_DMA42_XCNT_CUR)
-#define PVP0_MPDO_DMA_YCNT_CUR               (REG_DMA42_YCNT_CUR)
-#define PVP0_MPDO_DMA_BWLCNT                 (REG_DMA42_BWLCNT)
-#define PVP0_MPDO_DMA_BWLCNT_CUR             (REG_DMA42_BWLCNT_CUR)
-#define PVP0_MPDO_DMA_BWMCNT                 (REG_DMA42_BWMCNT)
-#define PVP0_MPDO_DMA_BWMCNT_CUR             (REG_DMA42_BWMCNT_CUR)
-#define PVP0_MPDI_DMA_DSCPTR_NXT             (REG_DMA43_DSCPTR_NXT)
-#define PVP0_MPDI_DMA_ADDRSTART              (REG_DMA43_ADDRSTART)
-#define PVP0_MPDI_DMA_CFG                    (REG_DMA43_CFG)
-#define PVP0_MPDI_DMA_XCNT                   (REG_DMA43_XCNT)
-#define PVP0_MPDI_DMA_XMOD                   (REG_DMA43_XMOD)
-#define PVP0_MPDI_DMA_YCNT                   (REG_DMA43_YCNT)
-#define PVP0_MPDI_DMA_YMOD                   (REG_DMA43_YMOD)
-#define PVP0_MPDI_DMA_DSCPTR_CUR             (REG_DMA43_DSCPTR_CUR)
-#define PVP0_MPDI_DMA_DSCPTR_PRV             (REG_DMA43_DSCPTR_PRV)
-#define PVP0_MPDI_DMA_ADDR_CUR               (REG_DMA43_ADDR_CUR)
-#define PVP0_MPDI_DMA_STAT                   (REG_DMA43_STAT)
-#define PVP0_MPDI_DMA_XCNT_CUR               (REG_DMA43_XCNT_CUR)
-#define PVP0_MPDI_DMA_YCNT_CUR               (REG_DMA43_YCNT_CUR)
-#define PVP0_MPDI_DMA_BWLCNT                 (REG_DMA43_BWLCNT)
-#define PVP0_MPDI_DMA_BWLCNT_CUR             (REG_DMA43_BWLCNT_CUR)
-#define PVP0_MPDI_DMA_BWMCNT                 (REG_DMA43_BWMCNT)
-#define PVP0_MPDI_DMA_BWMCNT_CUR             (REG_DMA43_BWMCNT_CUR)
-#define PVP0_MPSTAT_DMA_DSCPTR_NXT           (REG_DMA44_DSCPTR_NXT)
-#define PVP0_MPSTAT_DMA_ADDRSTART            (REG_DMA44_ADDRSTART)
-#define PVP0_MPSTAT_DMA_CFG                  (REG_DMA44_CFG)
-#define PVP0_MPSTAT_DMA_XCNT                 (REG_DMA44_XCNT)
-#define PVP0_MPSTAT_DMA_XMOD                 (REG_DMA44_XMOD)
-#define PVP0_MPSTAT_DMA_YCNT                 (REG_DMA44_YCNT)
-#define PVP0_MPSTAT_DMA_YMOD                 (REG_DMA44_YMOD)
-#define PVP0_MPSTAT_DMA_DSCPTR_CUR           (REG_DMA44_DSCPTR_CUR)
-#define PVP0_MPSTAT_DMA_DSCPTR_PRV           (REG_DMA44_DSCPTR_PRV)
-#define PVP0_MPSTAT_DMA_ADDR_CUR             (REG_DMA44_ADDR_CUR)
-#define PVP0_MPSTAT_DMA_STAT                 (REG_DMA44_STAT)
-#define PVP0_MPSTAT_DMA_XCNT_CUR             (REG_DMA44_XCNT_CUR)
-#define PVP0_MPSTAT_DMA_YCNT_CUR             (REG_DMA44_YCNT_CUR)
-#define PVP0_MPSTAT_DMA_BWLCNT               (REG_DMA44_BWLCNT)
-#define PVP0_MPSTAT_DMA_BWLCNT_CUR           (REG_DMA44_BWLCNT_CUR)
-#define PVP0_MPSTAT_DMA_BWMCNT               (REG_DMA44_BWMCNT)
-#define PVP0_MPSTAT_DMA_BWMCNT_CUR           (REG_DMA44_BWMCNT_CUR)
-#define PVP0_MPCI_DMA_DSCPTR_NXT             (REG_DMA45_DSCPTR_NXT)
-#define PVP0_MPCI_DMA_ADDRSTART              (REG_DMA45_ADDRSTART)
-#define PVP0_MPCI_DMA_CFG                    (REG_DMA45_CFG)
-#define PVP0_MPCI_DMA_XCNT                   (REG_DMA45_XCNT)
-#define PVP0_MPCI_DMA_XMOD                   (REG_DMA45_XMOD)
-#define PVP0_MPCI_DMA_YCNT                   (REG_DMA45_YCNT)
-#define PVP0_MPCI_DMA_YMOD                   (REG_DMA45_YMOD)
-#define PVP0_MPCI_DMA_DSCPTR_CUR             (REG_DMA45_DSCPTR_CUR)
-#define PVP0_MPCI_DMA_DSCPTR_PRV             (REG_DMA45_DSCPTR_PRV)
-#define PVP0_MPCI_DMA_ADDR_CUR               (REG_DMA45_ADDR_CUR)
-#define PVP0_MPCI_DMA_STAT                   (REG_DMA45_STAT)
-#define PVP0_MPCI_DMA_XCNT_CUR               (REG_DMA45_XCNT_CUR)
-#define PVP0_MPCI_DMA_YCNT_CUR               (REG_DMA45_YCNT_CUR)
-#define PVP0_MPCI_DMA_BWLCNT                 (REG_DMA45_BWLCNT)
-#define PVP0_MPCI_DMA_BWLCNT_CUR             (REG_DMA45_BWLCNT_CUR)
-#define PVP0_MPCI_DMA_BWMCNT                 (REG_DMA45_BWMCNT)
-#define PVP0_MPCI_DMA_BWMCNT_CUR             (REG_DMA45_BWMCNT_CUR)
-#define PVP0_CPDOA_DMA_DSCPTR_NXT            (REG_DMA46_DSCPTR_NXT)
-#define PVP0_CPDOA_DMA_ADDRSTART             (REG_DMA46_ADDRSTART)
-#define PVP0_CPDOA_DMA_CFG                   (REG_DMA46_CFG)
-#define PVP0_CPDOA_DMA_XCNT                  (REG_DMA46_XCNT)
-#define PVP0_CPDOA_DMA_XMOD                  (REG_DMA46_XMOD)
-#define PVP0_CPDOA_DMA_YCNT                  (REG_DMA46_YCNT)
-#define PVP0_CPDOA_DMA_YMOD                  (REG_DMA46_YMOD)
-#define PVP0_CPDOA_DMA_DSCPTR_CUR            (REG_DMA46_DSCPTR_CUR)
-#define PVP0_CPDOA_DMA_DSCPTR_PRV            (REG_DMA46_DSCPTR_PRV)
-#define PVP0_CPDOA_DMA_ADDR_CUR              (REG_DMA46_ADDR_CUR)
-#define PVP0_CPDOA_DMA_STAT                  (REG_DMA46_STAT)
-#define PVP0_CPDOA_DMA_XCNT_CUR              (REG_DMA46_XCNT_CUR)
-#define PVP0_CPDOA_DMA_YCNT_CUR              (REG_DMA46_YCNT_CUR)
-#define PVP0_CPDOA_DMA_BWLCNT                (REG_DMA46_BWLCNT)
-#define PVP0_CPDOA_DMA_BWLCNT_CUR            (REG_DMA46_BWLCNT_CUR)
-#define PVP0_CPDOA_DMA_BWMCNT                (REG_DMA46_BWMCNT)
-#define PVP0_CPDOA_DMA_BWMCNT_CUR            (REG_DMA46_BWMCNT_CUR)
-
-/* ==================================
-       DMA Error CHID Definitions
-   ================================== */
-#define CHID_SPORT0_A_DMA                      0           /* Channel A DMA */
-#define CHID_SPORT0_B_DMA                      1           /* Channel B DMA */
-#define CHID_SPORT1_A_DMA                      2           /* Channel A DMA */
-#define CHID_SPORT1_B_DMA                      3           /* Channel B DMA */
-#define CHID_SPORT2_A_DMA                      4           /* Channel A DMA */
-#define CHID_SPORT2_B_DMA                      5           /* Channel B DMA */
-#define CHID_SPI0_TXDMA                        6           /* TX DMA Channel */
-#define CHID_SPI0_RXDMA                        7           /* RX DMA Channel */
-#define CHID_SPI1_TXDMA                        8           /* TX DMA Channel */
-#define CHID_SPI1_RXDMA                        9           /* RX DMA Channel */
-#define CHID_RSI0_DMA                         10           /* DMA Channel */
-#define CHID_SDU0_DMA                         11           /* DMA */
-/*      -- RESERVED --                        12  */
-#define CHID_LP0_DMA                          13           /* DMA Channel */
-#define CHID_LP1_DMA                          14           /* DMA Channel */
-#define CHID_LP2_DMA                          15           /* DMA Channel */
-#define CHID_LP3_DMA                          16           /* DMA Channel */
-#define CHID_UART0_TXDMA                      17           /* Transmit DMA */
-#define CHID_UART0_RXDMA                      18           /* Receive DMA */
-#define CHID_UART1_TXDMA                      19           /* Transmit DMA */
-#define CHID_UART1_RXDMA                      20           /* Receive DMA */
-#define CHID_MDMA0_SRC                        21           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define CHID_MDMA0_DST                        22           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define CHID_MDMA1_SRC                        23           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define CHID_MDMA1_DST                        24           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define CHID_MDMA2_SRC                        25           /* Memory DMA Stream 2 Source Channel */
-#define CHID_MDMA2_DST                        26           /* Memory DMA Stream 2 Destination Channel */
-#define CHID_MDMA3_SRC                        27           /* Memory DMA Stream 3 Source Channel */
-#define CHID_MDMA3_DST                        28           /* Memory DMA Stream 3 Destination Channel */
-#define CHID_EPPI0_CH0_DMA                    29           /* Channel 0 DMA */
-#define CHID_EPPI0_CH1_DMA                    30           /* Channel 1 DMA */
-#define CHID_EPPI2_CH0_DMA                    31           /* Channel 0 DMA */
-#define CHID_EPPI2_CH1_DMA                    32           /* Channel 1 DMA */
-#define CHID_EPPI1_CH0_DMA                    33           /* Channel 0 DMA */
-#define CHID_EPPI1_CH1_DMA                    34           /* Channel 1 DMA */
-#define CHID_PIXC0_CH0_DMA                    35           /* Channel 0 DMA */
-#define CHID_PIXC0_CH1_DMA                    36           /* Channel 1 DMA */
-#define CHID_PIXC0_CH2_DMA                    37           /* Channel 2 DMA */
-#define CHID_PVP0_CPDOB_DMA                   38           /* Camera Pipe Data Out B DMA Channel */
-#define CHID_PVP0_CPDOC_DMA                   39           /* Camera Pipe Data Out C DMA Channel */
-#define CHID_PVP0_CPSTAT_DMA                  40           /* Camera Pipe Status Out DMA Channel */
-#define CHID_PVP0_CPCI_DMA                    41           /* Camera Pipe Control In DMA Channel */
-#define CHID_PVP0_MPDO_DMA                    42           /* Memory Pipe Data Out DMA Channel */
-#define CHID_PVP0_MPDI_DMA                    43           /* Memory Pipe Data In DMA Channel */
-#define CHID_PVP0_MPSTAT_DMA                  44           /* Memory Pipe Status Out DMA Channel */
-#define CHID_PVP0_MPCI_DMA                    45           /* Memory Pipe Control In DMA Channel */
-#define CHID_PVP0_CPDOA_DMA                   46           /* Camera Pipe Data Out A DMA Channel */
-
-/* ==============================
-       Interrupt Definitions
-   ============================== */
-#define INTR_SEC0_ERR                          0           /* Error */
-#define INTR_CGU0_EVT                          1           /* Event */
-#define INTR_WDOG0_EXP                         2           /* Expiration */
-#define INTR_WDOG1_EXP                         3           /* Expiration */
-#define INTR_L2CTL0_ECC_ERR                    4           /* ECC Error */
-#define INTR_L2CTL0_ECC_WARNING                5           /* ECC Warning */
-#define INTR_C0_DBL_FAULT                      6           /* Core 0 Double Fault */
-#define INTR_C1_DBL_FAULT                      7           /* Core 1 Double Fault */
-#define INTR_C0_HW_ERR                         8           /* Core 0 Hardware Error */
-#define INTR_C1_HW_ERR                         9           /* Core 1 Hardware Error */
-#define INTR_C0_NMI_L1_PARITY_ERR             10           /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_C1_NMI_L1_PARITY_ERR             11           /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_TIMER0_TMR0                      12           /* Timer 0 */
-#define INTR_TIMER0_TMR1                      13           /* Timer 1 */
-#define INTR_TIMER0_TMR2                      14           /* Timer 2 */
-#define INTR_TIMER0_TMR3                      15           /* Timer 3 */
-#define INTR_TIMER0_TMR4                      16           /* Timer 4 */
-#define INTR_TIMER0_TMR5                      17           /* Timer 5 */
-#define INTR_TIMER0_TMR6                      18           /* Timer 6 */
-#define INTR_TIMER0_TMR7                      19           /* Timer 7 */
-#define INTR_TIMER0_STAT                      20           /* Status */
-#define INTR_PINT0_BLOCK                      21           /* Pin Interrupt Block */
-#define INTR_PINT1_BLOCK                      22           /* Pin Interrupt Block */
-#define INTR_PINT2_BLOCK                      23           /* Pin Interrupt Block */
-#define INTR_PINT3_BLOCK                      24           /* Pin Interrupt Block */
-#define INTR_PINT4_BLOCK                      25           /* Pin Interrupt Block */
-#define INTR_PINT5_BLOCK                      26           /* Pin Interrupt Block */
-#define INTR_CNT0_STAT                        27           /* Status */
-#define INTR_PWM0_SYNC                        28           /* PWMTMR Group */
-#define INTR_PWM0_TRIP                        29           /* Trip */
-#define INTR_PWM1_SYNC                        30           /* PWMTMR Group */
-#define INTR_PWM1_TRIP                        31           /* Trip */
-#define INTR_TWI0_DATA                        32           /* Data Interrupt */
-#define INTR_TWI1_DATA                        33           /* Data Interrupt */
-#define INTR_SOFT0                            34           /* Software-driven Interrupt 0 */
-#define INTR_SOFT1                            35           /* Software-driven Interrupt 1 */
-#define INTR_SOFT2                            36           /* Software-driven Interrupt 2 */
-#define INTR_SOFT3                            37           /* Software-driven Interrupt 3 */
-#define INTR_ACM0_EVT_MISS                    38           /* Event Miss */
-#define INTR_ACM0_EVT_COMPLETE                39           /* Event Complete */
-#define INTR_CAN0_RX                          40           /* Receive */
-#define INTR_CAN0_TX                          41           /* Transmit */
-#define INTR_CAN0_STAT                        42           /* Status */
-#define INTR_SPORT0_A_DMA                     43           /* Channel A DMA */
-#define INTR_SPORT0_A_STAT                    44           /* Channel A Status */
-#define INTR_SPORT0_B_DMA                     45           /* Channel B DMA */
-#define INTR_SPORT0_B_STAT                    46           /* Channel B Status */
-#define INTR_SPORT1_A_DMA                     47           /* Channel A DMA */
-#define INTR_SPORT1_A_STAT                    48           /* Channel A Status */
-#define INTR_SPORT1_B_DMA                     49           /* Channel B DMA */
-#define INTR_SPORT1_B_STAT                    50           /* Channel B Status */
-#define INTR_SPORT2_A_DMA                     51           /* Channel A DMA */
-#define INTR_SPORT2_A_STAT                    52           /* Channel A Status */
-#define INTR_SPORT2_B_DMA                     53           /* Channel B DMA */
-#define INTR_SPORT2_B_STAT                    54           /* Channel B Status */
-#define INTR_SPI0_TXDMA                       55           /* TX DMA Channel */
-#define INTR_SPI0_RXDMA                       56           /* RX DMA Channel */
-#define INTR_SPI0_STAT                        57           /* Status */
-#define INTR_SPI1_TXDMA                       58           /* TX DMA Channel */
-#define INTR_SPI1_RXDMA                       59           /* RX DMA Channel */
-#define INTR_SPI1_STAT                        60           /* Status */
-#define INTR_RSI0_DMA                         61           /* DMA Channel */
-#define INTR_RSI0_INT0                        62           /* Interrupt 0 */
-#define INTR_RSI0_INT1                        63           /* Interrupt 1 */
-#define INTR_SDU0_DMA                         64           /* DMA */
-/*      -- RESERVED --                        65  */
-/*      -- RESERVED --                        66  */
-/*      -- RESERVED --                        67  */
-#define INTR_EMAC0_STAT                       68           /* Status */
-/*      -- RESERVED --                        69  */
-#define INTR_EMAC1_STAT                       70           /* Status */
-/*      -- RESERVED --                        71  */
-#define INTR_LP0_DMA                          72           /* DMA Channel */
-#define INTR_LP0_STAT                         73           /* Status */
-#define INTR_LP1_DMA                          74           /* DMA Channel */
-#define INTR_LP1_STAT                         75           /* Status */
-#define INTR_LP2_DMA                          76           /* DMA Channel */
-#define INTR_LP2_STAT                         77           /* Status */
-#define INTR_LP3_DMA                          78           /* DMA Channel */
-#define INTR_LP3_STAT                         79           /* Status */
-#define INTR_UART0_TXDMA                      80           /* Transmit DMA */
-#define INTR_UART0_RXDMA                      81           /* Receive DMA */
-#define INTR_UART0_STAT                       82           /* Status */
-#define INTR_UART1_TXDMA                      83           /* Transmit DMA */
-#define INTR_UART1_RXDMA                      84           /* Receive DMA */
-#define INTR_UART1_STAT                       85           /* Status */
-#define INTR_MDMA0_SRC                        86           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define INTR_MDMA0_DST                        87           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define INTR_CRC0_DCNTEXP                     88           /* Datacount expiration */
-#define INTR_CRC0_ERR                         89           /* Error */
-#define INTR_MDMA1_SRC                        90           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define INTR_MDMA1_DST                        91           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define INTR_CRC1_DCNTEXP                     92           /* Datacount expiration */
-#define INTR_CRC1_ERR                         93           /* Error */
-#define INTR_MDMA2_SRC                        94           /* Memory DMA Stream 2 Source Channel */
-#define INTR_MDMA2_DST                        95           /* Memory DMA Stream 2 Destination Channel */
-#define INTR_MDMA3_SRC                        96           /* Memory DMA Stream 3 Source Channel */
-#define INTR_MDMA3_DST                        97           /* Memory DMA Stream 3 Destination Channel */
-#define INTR_EPPI0_CH0_DMA                    98           /* Channel 0 DMA */
-#define INTR_EPPI0_CH1_DMA                    99           /* Channel 1 DMA */
-#define INTR_EPPI0_STAT                      100           /* Status */
-#define INTR_EPPI2_CH0_DMA                   101           /* Channel 0 DMA */
-#define INTR_EPPI2_CH1_DMA                   102           /* Channel 1 DMA */
-#define INTR_EPPI2_STAT                      103           /* Status */
-#define INTR_EPPI1_CH0_DMA                   104           /* Channel 0 DMA */
-#define INTR_EPPI1_CH1_DMA                   105           /* Channel 1 DMA */
-#define INTR_EPPI1_STAT                      106           /* Status */
-#define INTR_PIXC0_CH0_DMA                   107           /* Channel 0 DMA */
-#define INTR_PIXC0_CH1_DMA                   108           /* Channel 1 DMA */
-#define INTR_PIXC0_CH2_DMA                   109           /* Channel 2 DMA */
-#define INTR_PIXC0_STAT                      110           /* Status */
-#define INTR_PVP0_CPDOB_DMA                  111           /* Camera Pipe Data Out B DMA Channel */
-#define INTR_PVP0_CPDOC_DMA                  112           /* Camera Pipe Data Out C DMA Channel */
-#define INTR_PVP0_CPSTAT_DMA                 113           /* Camera Pipe Status Out DMA Channel */
-#define INTR_PVP0_CPCI_DMA                   114           /* Camera Pipe Control In DMA Channel */
-#define INTR_PVP0_STAT0                      115           /* Status 0 */
-#define INTR_PVP0_MPDO_DMA                   116           /* Memory Pipe Data Out DMA Channel */
-#define INTR_PVP0_MPDI_DMA                   117           /* Memory Pipe Data In DMA Channel */
-#define INTR_PVP0_MPSTAT_DMA                 118           /* Memory Pipe Status Out DMA Channel */
-#define INTR_PVP0_MPCI_DMA                   119           /* Memory Pipe Control In DMA Channel */
-#define INTR_PVP0_CPDOA_DMA                  120           /* Camera Pipe Data Out A DMA Channel */
-#define INTR_PVP0_STAT1                      121           /* Status 1 */
-#define INTR_USB0_STAT                       122           /* Status/FIFO Data Ready */
-#define INTR_USB0_DATA                       123           /* DMA Status/Transfer Complete */
-#define INTR_TRU0_INT0                       124           /* Interrupt 0 */
-#define INTR_TRU0_INT1                       125           /* Interrupt 1 */
-#define INTR_TRU0_INT2                       126           /* Interrupt 2 */
-#define INTR_TRU0_INT3                       127           /* Interrupt 3 */
-#define INTR_DMAC_ERR                        128           /* DMA Controller Error */
-#define INTR_CGU0_ERR                        129           /* Error */
-/*      -- RESERVED --                       130  */
-#define INTR_DPM0_EVT                        131           /* Event */
-/*      -- RESERVED --                       132  */
-#define INTR_SWU0_EVT                        133           /* Event */
-#define INTR_SWU1_EVT                        134           /* Event */
-#define INTR_SWU2_EVT                        135           /* Event */
-#define INTR_SWU3_EVT                        136           /* Event */
-#define INTR_SWU4_EVT                        137           /* Event */
-#define INTR_SWU5_EVT                        138           /* Event */
-#define INTR_SWU6_EVT                        139           /* Event */
-
-/* ==============================
-       Parameters
-   ============================== */
-
-
-/* Generic System Module Parameters */
-
-#define PARAM_SYS0_NUM_BMODE                          3
-#define PARAM_SYS0_NUM_CORES                          2
-#define PARAM_SYS0_NUM_MDMA_STREAMS                   4
-#define PARAM_SYS0_NUM_RSVD_INT                       7
-#define PARAM_SYS0_NUM_RSVD_TRIG                      6
-#define PARAM_SYS0_NUM_SW_INT                         4
-#define PARAM_SYS0_NUM_SW_TRIG                        6
-
-
-
-
-/* RSI Parameters */
-
-#define PARAM_RSI0_NUM_DATA                           8
-#define PARAM_RSI0_NUM_INT                            2
-
-
-
-/* Link Port Parameters */
-
-#define PARAM_LP0_NUM_DATA                            8
-#define PARAM_LP1_NUM_DATA                            8
-#define PARAM_LP2_NUM_DATA                            8
-#define PARAM_LP3_NUM_DATA                            8
-
-
-/* General Purpose Timer Block Parameters */
-
-#define PARAM_TIMER0_NUMTIMERS                        8
-
-
-
-
-
-/* General Purpose Input/Output Parameters */
-
-#define PARAM_PORTA_PORT_WIDTH                       16
-#define PARAM_PORTB_PORT_WIDTH                       16
-#define PARAM_PORTC_PORT_WIDTH                       16
-#define PARAM_PORTD_PORT_WIDTH                       16
-#define PARAM_PORTE_PORT_WIDTH                       16
-#define PARAM_PORTF_PORT_WIDTH                       16
-#define PARAM_PORTG_PORT_WIDTH                       16
-
-
-
-
-/* Static Memory Controller Parameters */
-
-#define PARAM_SMC0_NUM_ABE                            2
-#define PARAM_SMC0_NUM_ADDR                          26
-#define PARAM_SMC0_NUM_AMS                            4
-#define PARAM_SMC0_NUM_DATA                          16
-
-
-
-/* EPPI Parameters */
-
-#define PARAM_EPPI0_MAXWIDTH                         24
-#define PARAM_EPPI0_NUM_DATA                         24
-#define PARAM_EPPI1_MAXWIDTH                         24
-#define PARAM_EPPI1_NUM_DATA                         18
-#define PARAM_EPPI2_MAXWIDTH                         24
-#define PARAM_EPPI2_NUM_DATA                         18
-
-
-
-
-/* Pulse-Width Modulator Parameters */
-
-#define PARAM_PWM0_ASYM_DEADTIME                      0
-#define PARAM_PWM0_COMPRESS                           1
-#define PARAM_PWM0_DOUBLE_UPDATE                      0
-#define PARAM_PWM0_FULL_DUTY_REGS                     0
-#define PARAM_PWM0_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM0_LO_HP_REGS                         0
-#define PARAM_PWM0_NUM_TRIP                           2
-#define PARAM_PWM0_NUM_TRIP_PINS                      2
-#define PARAM_PWM0_NUM_TRIP_TRIG                      0
-#define PARAM_PWM0_REVID_MAJOR                        0
-#define PARAM_PWM0_REVID_REV                          0
-#define PARAM_PWM1_ASYM_DEADTIME                      0
-#define PARAM_PWM1_COMPRESS                           1
-#define PARAM_PWM1_DOUBLE_UPDATE                      0
-#define PARAM_PWM1_FULL_DUTY_REGS                     0
-#define PARAM_PWM1_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM1_LO_HP_REGS                         0
-#define PARAM_PWM1_NUM_TRIP                           2
-#define PARAM_PWM1_NUM_TRIP_PINS                      2
-#define PARAM_PWM1_NUM_TRIP_TRIG                      0
-#define PARAM_PWM1_REVID_MAJOR                        0
-#define PARAM_PWM1_REVID_REV                          0
-
-
-/* Video Subsystem Registers Parameters */
-
-#define PARAM_VID0_PIXC_ABSENT                        0
-#define PARAM_VID0_PVP_ABSENT                         0
-
-
-
-/* System Debug Unit Parameters */
-
-#define PARAM_SDU0_IDCODE_PRID                        0
-#define PARAM_SDU0_IDCODE_REVID                       0
-
-
-/* Ethernet MAC Parameters */
-
-#define PARAM_EMAC0_NUM_RX                            2
-#define PARAM_EMAC0_NUM_TX                            2
-#define PARAM_EMAC1_NUM_RX                            2
-#define PARAM_EMAC1_NUM_TX                            2
-
-
-
-/* Serial Peripheral Interface Parameters */
-
-#define PARAM_SPI0_MEM_MAPPED                         0
-#define PARAM_SPI0_NUM_SEL                            7
-#define PARAM_SPI0_PTM_EXISTS                         1
-#define PARAM_SPI0_REVID_MAJOR                        3
-#define PARAM_SPI0_REVID_REV                          0
-#define PARAM_SPI1_MEM_MAPPED                         0
-#define PARAM_SPI1_NUM_SEL                            7
-#define PARAM_SPI1_PTM_EXISTS                         1
-#define PARAM_SPI1_REVID_MAJOR                        3
-#define PARAM_SPI1_REVID_REV                          0
-
-
-
-/* ACM Parameters */
-
-#define PARAM_ACM0_NUM_ADDR                           5
-#define PARAM_ACM0_NUM_TRIG                           2
-
-
-/* DDR Parameters */
-
-#define PARAM_DMC0_NUM_ADDR                          14
-#define PARAM_DMC0_NUM_BA                             3
-#define PARAM_DMC0_NUM_CS                             1
-#define PARAM_DMC0_NUM_DATA                          16
-
-
-/* System Cross Bar Parameters */
-
-#define PARAM_SCB0_NUM_MASTERS                        6
-#define PARAM_SCB0_NUM_SLOTS                         32
-#define PARAM_SCB1_NUM_MASTERS                        1
-#define PARAM_SCB1_NUM_SLOTS                         32
-#define PARAM_SCB2_NUM_MASTERS                        1
-#define PARAM_SCB2_NUM_SLOTS                         32
-#define PARAM_SCB3_NUM_MASTERS                        1
-#define PARAM_SCB3_NUM_SLOTS                         32
-#define PARAM_SCB4_NUM_MASTERS                        1
-#define PARAM_SCB4_NUM_SLOTS                         32
-#define PARAM_SCB5_NUM_MASTERS                        1
-#define PARAM_SCB5_NUM_SLOTS                         32
-#define PARAM_SCB6_NUM_MASTERS                        1
-#define PARAM_SCB6_NUM_SLOTS                         32
-#define PARAM_SCB7_NUM_MASTERS                        1
-#define PARAM_SCB7_NUM_SLOTS                         32
-#define PARAM_SCB8_NUM_MASTERS                        1
-#define PARAM_SCB8_NUM_SLOTS                         32
-#define PARAM_SCB9_NUM_MASTERS                        1
-#define PARAM_SCB9_NUM_SLOTS                         32
-#define PARAM_SCB10_NUM_MASTERS                       3
-#define PARAM_SCB10_NUM_SLOTS                        32
-#define PARAM_SCB11_NUM_MASTERS                       7
-#define PARAM_SCB11_NUM_SLOTS                        32
-
-
-
-/* System Event Controller Parameters */
-
-#define PARAM_SEC0_CCOUNT                             2
-#define PARAM_SEC0_SCOUNT                           140
-
-
-/* Trigger Routing Unit Parameters */
-
-#define PARAM_TRU0_NUM_INTS                           4
-#define PARAM_TRU0_NUM_TRIGS                          4
-#define PARAM_TRU0_SSRCOUNT                          87
-
-
-/* Reset Control Unit Parameters */
-
-#define PARAM_RCU0_CCOUNT                             2
-#define PARAM_RCU0_CRCTL_CR_INIT                      2
-#define PARAM_RCU0_CRSTAT_CR_INIT                     3
-#define PARAM_RCU0_SICOUNT                            2
-#define PARAM_RCU0_SVECT_INIT                     65440
-
-
-/* System Protection Unit Parameters */
-
-#define PARAM_SPU0_CM_COUNT                           2
-#define PARAM_SPU0_END_POINT_COUNT                   86
-#define PARAM_SPU0_SM_COUNT                           2
-
-
-/* Clock Generation Unit Parameters */
-
-#define PARAM_CGU0_CSEL_DEFAULT                       4
-#define PARAM_CGU0_DSEL_DEFAULT                       8
-#define PARAM_CGU0_MSEL_DEFAULT                      16
-#define PARAM_CGU0_OSEL_DEFAULT                      16
-#define PARAM_CGU0_PLLBP_DEFAULT                      0
-#define PARAM_CGU0_S0SEL_DEFAULT                      2
-#define PARAM_CGU0_S1SEL_DEFAULT                      2
-#define PARAM_CGU0_SYSSEL_DEFAULT                     8
-
-
-/* Dynamic Power Management Parameters */
-
-#define PARAM_DPM0_NUM_CCLK                           2
-#define PARAM_DPM0_NUM_HV                             8
-#define PARAM_DPM0_NUM_SCLK                           4
-#define PARAM_DPM0_NUM_WAKE                           8
-
-
-
-/* Universal Serial Bus Controller Parameters */
-
-#define PARAM_USB0_DMA_CHAN                           8
-#define PARAM_USB0_DYN_FIFO_SIZE                      1
-#define PARAM_USB0_FS_PHY                             0
-#define PARAM_USB0_HS_PHY                             1
-#define PARAM_USB0_LOOPBACK                           1
-#define PARAM_USB0_NUM_ENDPTS                        12
-#define PARAM_USB0_NUM_ENDPTS_MINUS_1                11
-
-
-/* Data Memory Unit Parameters */
-
-#define PARAM_L1DM0_L1_BASE_ADDRESS          1111111110
-
-
-
-
-
-
-
-
-/* ===================================
-       Trigger Master Definitions
-   =================================== */
-/*      -- RESERVED --                         0  */
-#define TRGM_CGU0_EVT                          1           /* Event */
-#define TRGM_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGM_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGM_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGM_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGM_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGM_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGM_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGM_TIMER0_TMR7                       9           /* Timer 7 */
-#define TRGM_PINT0_BLOCK                      10           /* Pin Interrupt Block */
-#define TRGM_PINT1_BLOCK                      11           /* Pin Interrupt Block */
-#define TRGM_PINT2_BLOCK                      12           /* Pin Interrupt Block */
-#define TRGM_PINT3_BLOCK                      13           /* Pin Interrupt Block */
-#define TRGM_PINT4_BLOCK                      14           /* Pin Interrupt Block */
-#define TRGM_PINT5_BLOCK                      15           /* Pin Interrupt Block */
-#define TRGM_CNT0_STAT                        16           /* Status */
-#define TRGM_PWM0_SYNC                        17           /* PWMTMR Group */
-#define TRGM_PWM1_SYNC                        18           /* PWMTMR Group */
-#define TRGM_ACM0_EVT_COMPLETE                19           /* Event Complete */
-#define TRGM_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGM_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGM_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGM_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGM_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGM_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGM_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGM_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGM_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGM_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGM_RSI0_DMA                         30           /* DMA Channel */
-#define TRGM_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGM_EMAC0_STAT                       33           /* Status */
-#define TRGM_EMAC1_STAT                       34           /* Status */
-#define TRGM_LP0_DMA                          35           /* DMA Channel */
-#define TRGM_LP1_DMA                          36           /* DMA Channel */
-#define TRGM_LP2_DMA                          37           /* DMA Channel */
-#define TRGM_LP3_DMA                          38           /* DMA Channel */
-#define TRGM_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGM_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGM_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGM_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGM_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGM_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGM_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGM_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGM_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGM_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGM_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGM_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGM_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGM_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGM_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGM_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGM_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGM_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGM_PIXC0_CH0_DMA                    57           /* Channel 0 DMA */
-#define TRGM_PIXC0_CH1_DMA                    58           /* Channel 1 DMA */
-#define TRGM_PIXC0_CH2_DMA                    59           /* Channel 2 DMA */
-#define TRGM_PVP0_CPDOB_DMA                   60           /* Camera Pipe Data Out B DMA Channel */
-#define TRGM_PVP0_CPDOC_DMA                   61           /* Camera Pipe Data Out C DMA Channel */
-#define TRGM_PVP0_CPSTAT_DMA                  62           /* Camera Pipe Status Out DMA Channel */
-#define TRGM_PVP0_CPCI_DMA                    63           /* Camera Pipe Control In DMA Channel */
-#define TRGM_PVP0_MPDO_DMA                    64           /* Memory Pipe Data Out DMA Channel */
-#define TRGM_PVP0_MPDI_DMA                    65           /* Memory Pipe Data In DMA Channel */
-#define TRGM_PVP0_MPSTAT_DMA                  66           /* Memory Pipe Status Out DMA Channel */
-#define TRGM_PVP0_MPCI_DMA                    67           /* Memory Pipe Control In DMA Channel */
-#define TRGM_PVP0_CPDOA_DMA                   68           /* Camera Pipe Data Out A DMA Channel */
-#define TRGM_USB0_DATA                        69           /* DMA Status/Transfer Complete */
-/*      -- RESERVED --                        70  */
-#define TRGM_SEC0_FAULT                       71           /* Fault */
-#define TRGM_SOFT0                            72           /* Software-driven Trigger 0 */
-#define TRGM_SOFT1                            73           /* Software-driven Trigger 1 */
-#define TRGM_SOFT2                            74           /* Software-driven Trigger 2 */
-#define TRGM_SOFT3                            75           /* Software-driven Trigger 3 */
-#define TRGM_SOFT4                            76           /* Software-driven Trigger 4 */
-#define TRGM_SOFT5                            77           /* Software-driven Trigger 5 */
-#define TRGM_PVP0_STAT0                       78           /* Status 0 */
-#define TRGM_PVP0_STAT1                       79           /* Status 1 */
-#define TRGM_SWU0_EVT                         80           /* Event */
-#define TRGM_SWU1_EVT                         81           /* Event */
-#define TRGM_SWU2_EVT                         82           /* Event */
-#define TRGM_SWU3_EVT                         83           /* Event */
-#define TRGM_SWU4_EVT                         84           /* Event */
-#define TRGM_SWU5_EVT                         85           /* Event */
-#define TRGM_SWU6_EVT                         86           /* Event */
-
-/* ===================================
-       Trigger Slave Definitions
-   =================================== */
-#define TRGS_RCU0_SYSRST0                      0           /* System Reset 0 */
-#define TRGS_RCU0_SYSRST1                      1           /* System Reset 1 */
-#define TRGS_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGS_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGS_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGS_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGS_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGS_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGS_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGS_TIMER0_TMR7                       9           /* Timer 7 */
-/*      -- RESERVED --                        10  */
-/*      -- RESERVED --                        11  */
-#define TRGS_C0_NMI_S0                        12           /* NMI (Core 0) Slave 0 */
-#define TRGS_C0_NMI_S1                        13           /* NMI (Core 0) Slave 1 */
-#define TRGS_C1_NMI_S0                        14           /* NMI (Core 1) Slave 0 */
-#define TRGS_C1_NMI_S1                        15           /* NMI (Core 1) Slave 1 */
-#define TRGS_TRU0_IRQ0                        16           /* Interrupt Request 0 */
-#define TRGS_TRU0_IRQ1                        17           /* Interrupt Request 1 */
-#define TRGS_TRU0_IRQ2                        18           /* Interrupt Request 2 */
-#define TRGS_TRU0_IRQ3                        19           /* Interrupt Request 3 */
-#define TRGS_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGS_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGS_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGS_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGS_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGS_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGS_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGS_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGS_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGS_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGS_RSI0_DMA                         30           /* DMA Channel */
-#define TRGS_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGS_ACM0_TRIG2                       33           /* Trigger Input 2 */
-#define TRGS_ACM0_TRIG3                       34           /* Trigger Input 3 */
-#define TRGS_LP0_DMA                          35           /* DMA Channel */
-#define TRGS_LP1_DMA                          36           /* DMA Channel */
-#define TRGS_LP2_DMA                          37           /* DMA Channel */
-#define TRGS_LP3_DMA                          38           /* DMA Channel */
-#define TRGS_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGS_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGS_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGS_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGS_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGS_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGS_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGS_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGS_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGS_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGS_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGS_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGS_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGS_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGS_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGS_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGS_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGS_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGS_PIXC0_CH0_DMA                    57           /* Channel 0 DMA */
-#define TRGS_PIXC0_CH1_DMA                    58           /* Channel 1 DMA */
-#define TRGS_PIXC0_CH2_DMA                    59           /* Channel 2 DMA */
-#define TRGS_PVP0_CPDOB_DMA                   60           /* Camera Pipe Data Out B DMA Channel */
-#define TRGS_PVP0_CPDOC_DMA                   61           /* Camera Pipe Data Out C DMA Channel */
-#define TRGS_PVP0_CPSTAT_DMA                  62           /* Camera Pipe Status Out DMA Channel */
-#define TRGS_PVP0_CPCI_DMA                    63           /* Camera Pipe Control In DMA Channel */
-#define TRGS_PVP0_MPDO_DMA                    64           /* Memory Pipe Data Out DMA Channel */
-#define TRGS_PVP0_MPDI_DMA                    65           /* Memory Pipe Data In DMA Channel */
-#define TRGS_PVP0_MPSTAT_DMA                  66           /* Memory Pipe Status Out DMA Channel */
-#define TRGS_PVP0_MPCI_DMA                    67           /* Memory Pipe Control In DMA Channel */
-#define TRGS_PVP0_CPDOA_DMA                   68           /* Camera Pipe Data Out A DMA Channel */
-#define TRGS_SDU0_SLAVE                       69           /* Slave Trigger */
-/*      -- RESERVED --                        70  */
-#define TRGS_C0_WAKE0                         71           /* Core 0 Wakeup Input 0 */
-#define TRGS_C0_WAKE1                         72           /* Core 0 Wakeup Input 1 */
-#define TRGS_C0_WAKE2                         73           /* Core 0 Wakeup Input 2 */
-#define TRGS_C0_WAKE3                         74           /* Core 0 Wakeup Input 3 */
-#define TRGS_C1_WAKE0                         75           /* Core 1 Wakeup Input 0 */
-#define TRGS_C1_WAKE1                         76           /* Core 1 Wakeup Input 1 */
-#define TRGS_C1_WAKE2                         77           /* Core 1 Wakeup Input 2 */
-#define TRGS_C1_WAKE3                         78           /* Core 1 Wakeup Input 3 */
-/*      -- RESERVED --                        79  */
-#define TRGS_SWU0_EVT                         80           /* Event */
-#define TRGS_SWU1_EVT                         81           /* Event */
-#define TRGS_SWU2_EVT                         82           /* Event */
-#define TRGS_SWU3_EVT                         83           /* Event */
-#define TRGS_SWU4_EVT                         84           /* Event */
-#define TRGS_SWU5_EVT                         85           /* Event */
-#define TRGS_SWU6_EVT                         86           /* Event */
-
-
-/* ============================================================================
-       Memory Map Macros
-   ============================================================================ */
-
-/* ADSP-BF608 is a multi-core processor */
-
-#define MEM_NUM_CORES                   2
-
-/* Internal memory range */
-
-#define MEM_BASE_INTERNAL               0xC0000000
-#define MEM_END_INTERNAL                0xFFFFFFFF
-#define MEM_SIZE_INTERNAL               0x40000000
-
-/* External memory range */
-
-#define MEM_BASE_EXTERNAL               0x00000000
-#define MEM_END_EXTERNAL                0xBFFFFFFF
-#define MEM_SIZE_EXTERNAL               0xC0000000
-
-/* Shared DDR2 or LPDDR Memory (256 MB) */
-
-#define MEM_BASE_DDR                    0x00000000
-#define MEM_END_DDR                     0x0FFFFFFF
-#define MEM_SIZE_DDR                    0x10000000
-
-/* Shared Async Memory (256 MB) */
-
-#define MEM_BASE_ASYNC                  0xB0000000
-#define MEM_END_ASYNC                   0xBFFFFFFF
-#define MEM_SIZE_ASYNC                  0x10000000
-
-/* Shared Async Memory Bank 0 (64 MB) */
-
-#define MEM_BASE_ASYNC_0                0xB0000000
-#define MEM_END_ASYNC_0                 0xB3FFFFFF
-#define MEM_SIZE_ASYNC_0                0x4000000
-
-/* Shared Async Memory Bank 1 (64 MB) */
-
-#define MEM_BASE_ASYNC_1                0xB4000000
-#define MEM_END_ASYNC_1                 0xB7FFFFFF
-#define MEM_SIZE_ASYNC_1                0x4000000
-
-/* Shared Async Memory Bank 2 (64 MB) */
-
-#define MEM_BASE_ASYNC_2                0xB8000000
-#define MEM_END_ASYNC_2                 0xBBFFFFFF
-#define MEM_SIZE_ASYNC_2                0x4000000
-
-/* Shared Async Memory Bank 3 (64 MB) */
-
-#define MEM_BASE_ASYNC_3                0xBC000000
-#define MEM_END_ASYNC_3                 0xBFFFFFFF
-#define MEM_SIZE_ASYNC_3                0x4000000
-
-/* Shared L2 ROM (32 KB) */
-
-#define MEM_BASE_L2_ROM                 0xC8000000
-#define MEM_END_L2_ROM                  0xC8007FFF
-#define MEM_SIZE_L2_ROM                 0x8000
-
-/* Shared L2 SRAM (256 KB) */
-
-#define MEM_BASE_L2_SRAM                0xC8080000
-#define MEM_END_L2_SRAM                 0xC80BFFFF
-#define MEM_SIZE_L2_SRAM                0x40000
-
-/* Core 1 L1 Data Bank A (32 KB) */
-
-#define MEM_C1_BASE_L1DM_A              0xFF400000
-#define MEM_C1_END_L1DM_A               0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A              0x8000
-
-/* Core 1 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM         0xFF400000
-#define MEM_C1_END_L1DM_A_SRAM          0xFF403FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 1 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM_CACHE   0xFF404000
-#define MEM_C1_END_L1DM_A_SRAM_CACHE    0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Data Bank B (32 KB) */
-
-#define MEM_C1_BASE_L1DM_B              0xFF500000
-#define MEM_C1_END_L1DM_B               0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B              0x8000
-
-/* Core 1 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM         0xFF500000
-#define MEM_C1_END_L1DM_B_SRAM          0xFF503FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 1 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM_CACHE   0xFF504000
-#define MEM_C1_END_L1DM_B_SRAM_CACHE    0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Instruction (80 KB) */
-
-#define MEM_C1_BASE_L1IM                0xFF600000
-#define MEM_C1_END_L1IM                 0xFF613FFF
-#define MEM_C1_SIZE_L1IM                0x14000
-
-/* Core 1 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM           0xFF600000
-#define MEM_C1_END_L1IM_SRAM            0xFF60FFFF
-#define MEM_C1_SIZE_L1IM_SRAM           0x10000
-
-/* Core 1 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM_CACHE     0xFF610000
-#define MEM_C1_END_L1IM_SRAM_CACHE      0xFF613FFF
-#define MEM_C1_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 1 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C1_BASE_L1_XPAD_SRAM        0xFF700000
-#define MEM_C1_END_L1_XPAD_SRAM         0xFF700FFF
-#define MEM_C1_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Core 0 L1 Data Bank A (32 KB) */
-
-#define MEM_C0_BASE_L1DM_A              0xFF800000
-#define MEM_C0_END_L1DM_A               0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A              0x8000
-
-/* Core 0 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM         0xFF800000
-#define MEM_C0_END_L1DM_A_SRAM          0xFF803FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 0 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM_CACHE   0xFF804000
-#define MEM_C0_END_L1DM_A_SRAM_CACHE    0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Data Bank B (32 KB) */
-
-#define MEM_C0_BASE_L1DM_B              0xFF900000
-#define MEM_C0_END_L1DM_B               0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B              0x8000
-
-/* Core 0 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM         0xFF900000
-#define MEM_C0_END_L1DM_B_SRAM          0xFF903FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 0 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM_CACHE   0xFF904000
-#define MEM_C0_END_L1DM_B_SRAM_CACHE    0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Instruction (80 KB) */
-
-#define MEM_C0_BASE_L1IM                0xFFA00000
-#define MEM_C0_END_L1IM                 0xFFA13FFF
-#define MEM_C0_SIZE_L1IM                0x14000
-
-/* Core 0 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM           0xFFA00000
-#define MEM_C0_END_L1IM_SRAM            0xFFA0FFFF
-#define MEM_C0_SIZE_L1IM_SRAM           0x10000
-
-/* Core 0 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM_CACHE     0xFFA10000
-#define MEM_C0_END_L1IM_SRAM_CACHE      0xFFA13FFF
-#define MEM_C0_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 0 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C0_BASE_L1_XPAD_SRAM        0xFFB00000
-#define MEM_C0_END_L1_XPAD_SRAM         0xFFB00FFF
-#define MEM_C0_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Shared System MMR Registers (2 MB) */
-
-#define MEM_BASE_MMR_SYSTEM             0xFFC00000
-#define MEM_END_MMR_SYSTEM              0xFFDFFFFF
-#define MEM_SIZE_MMR_SYSTEM             0x200000
-
-/* Core 0 Core MMR Registers (2 MB) */
-
-#define MEM_C0_BASE_MMR_CORE            0xFFE00000
-#define MEM_C0_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C0_SIZE_MMR_CORE            0x200000
-
-/* Core 1 Core MMR Registers (2 MB) */
-
-#define MEM_C1_BASE_MMR_CORE            0xFFE00000
-#define MEM_C1_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C1_SIZE_MMR_CORE            0x200000
-
-
-#endif	/* end ifndef _DEF_BF608_H */
diff --git a/libgloss/bfin/include/defBF609.h b/libgloss/bfin/include/defBF609.h
deleted file mode 100644
index 6c41ed838..000000000
--- a/libgloss/bfin/include/defBF609.h
+++ /dev/null
@@ -1,19426 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* ================================================================================
-
-     Project      :   ADSP-BF609
-     File         :   defBF609.h
-     Description  :   Register Definitions
-
-     Date         :   06-07-2012
-     Tag          :   BF60X_TOOLS_CCES_1_0_1
-
-     Copyright (c) 2011-2012 Analog Devices, Inc.  All Rights Reserved.
-     This software is proprietary and confidential to Analog Devices, Inc. and
-     its licensors.
-
-     This file was auto-generated. Do not make local changes to this file.
-
-   ================================================================================ */
-
-#ifndef _DEF_BF609_H
-#define _DEF_BF609_H
-
-#if defined (_MISRA_RULES)
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros")
-#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators")
-#endif /* _MISRA_RULES */
-
-/* do not add casts to literal constants in assembly code */
-#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__)
-#define _ADI_MSK( mask, type ) (mask) /* Make a bitmask */
-#else
-#define _ADI_MSK( mask, type ) ((type)(mask)) /* Make a bitmask */
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#ifndef __ADI_GENERATED_DEF_HEADERS__
-#define __ADI_GENERATED_DEF_HEADERS__    1
-#endif
-
-/* MMR modules defined for the ADSP-BF609 */
-
-#define __ADI_HAS_SYS__           1
-#define __ADI_HAS_SIMENV__        1
-#define __ADI_HAS_CNT__           1
-#define __ADI_HAS_RSI__           1
-#define __ADI_HAS_CAN__           1
-#define __ADI_HAS_LP__            1
-#define __ADI_HAS_TIMER__         1
-#define __ADI_HAS_CRC__           1
-#define __ADI_HAS_TWI__           1
-#define __ADI_HAS_UART__          1
-#define __ADI_HAS_PORT__          1
-#define __ADI_HAS_PADS__          1
-#define __ADI_HAS_PINT__          1
-#define __ADI_HAS_SMC__           1
-#define __ADI_HAS_WDOG__          1
-#define __ADI_HAS_EPPI__          1
-#define __ADI_HAS_PIXC__          1
-#define __ADI_HAS_PVP__           1
-#define __ADI_HAS_PWM__           1
-#define __ADI_HAS_VID__           1
-#define __ADI_HAS_SWU__           1
-#define __ADI_HAS_SDU__           1
-#define __ADI_HAS_EMAC__          1
-#define __ADI_HAS_SPORT__         1
-#define __ADI_HAS_SPI__           1
-#define __ADI_HAS_DMA__           1
-#define __ADI_HAS_ACM__           1
-#define __ADI_HAS_DMC__           1
-#define __ADI_HAS_SCB__           1
-#define __ADI_HAS_L2CTL__         1
-#define __ADI_HAS_SEC__           1
-#define __ADI_HAS_TRU__           1
-#define __ADI_HAS_RCU__           1
-#define __ADI_HAS_SPU__           1
-#define __ADI_HAS_CGU__           1
-#define __ADI_HAS_DPM__           1
-#define __ADI_HAS_EFS__           1
-#define __ADI_HAS_USB__           1
-#define __ADI_HAS_L1DM__          1
-#define __ADI_HAS_L1IM__          1
-#define __ADI_HAS_ICU__           1
-#define __ADI_HAS_TMR__           1
-#define __ADI_HAS_DBG__           1
-#define __ADI_HAS_TB__            1
-#define __ADI_HAS_WP__            1
-#define __ADI_HAS_PF__            1
-
-/* =========================
-        REGFILE
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ASTAT                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ASTAT_VS                        25                               /* Sticky version of ASTAT_V */
-#define BITP_ASTAT_V                         24                               /* Overflow Flag */
-#define BITP_ASTAT_AV1S                      19                               /* Sticky Overflow Flag 1 */
-#define BITP_ASTAT_AV1                       18                               /* Overflow Flag 1 */
-#define BITP_ASTAT_AV0S                      17                               /* Sticky Overflow Flag 0 */
-#define BITP_ASTAT_AV0                       16                               /* Overflow Flag 0 */
-#define BITP_ASTAT_AC1                       13                               /* Carry Flag 1 */
-#define BITP_ASTAT_AC0                       12                               /* Carry Flag 0 */
-#define BITP_ASTAT_RND_MOD                    8                               /* Rounding Mode */
-#define BITP_ASTAT_AQ                         6                               /* Quotient Bit */
-#define BITP_ASTAT_CC                         5                               /* Condition Code */
-#define BITP_ASTAT_V_COPY                     3                               /* Overflow Flag */
-#define BITP_ASTAT_AC0_COPY                   2                               /* Carry Flag 0 */
-#define BITP_ASTAT_AN                         1                               /* Negative Flag */
-#define BITP_ASTAT_AZ                         0                               /* Zero Flag */
-#define BITM_ASTAT_VS                        (_ADI_MSK(0x02000000,uint32_t))  /* Sticky version of ASTAT_V */
-#define BITM_ASTAT_V                         (_ADI_MSK(0x01000000,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AV1S                      (_ADI_MSK(0x00080000,uint32_t))  /* Sticky Overflow Flag 1 */
-#define BITM_ASTAT_AV1                       (_ADI_MSK(0x00040000,uint32_t))  /* Overflow Flag 1 */
-#define BITM_ASTAT_AV0S                      (_ADI_MSK(0x00020000,uint32_t))  /* Sticky Overflow Flag 0 */
-#define BITM_ASTAT_AV0                       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow Flag 0 */
-#define BITM_ASTAT_AC1                       (_ADI_MSK(0x00002000,uint32_t))  /* Carry Flag 1 */
-#define BITM_ASTAT_AC0                       (_ADI_MSK(0x00001000,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_RND_MOD                   (_ADI_MSK(0x00000100,uint32_t))  /* Rounding Mode */
-#define BITM_ASTAT_AQ                        (_ADI_MSK(0x00000040,uint32_t))  /* Quotient Bit */
-#define BITM_ASTAT_CC                        (_ADI_MSK(0x00000020,uint32_t))  /* Condition Code */
-#define BITM_ASTAT_V_COPY                    (_ADI_MSK(0x00000008,uint32_t))  /* Overflow Flag */
-#define BITM_ASTAT_AC0_COPY                  (_ADI_MSK(0x00000004,uint32_t))  /* Carry Flag 0 */
-#define BITM_ASTAT_AN                        (_ADI_MSK(0x00000002,uint32_t))  /* Negative Flag */
-#define BITM_ASTAT_AZ                        (_ADI_MSK(0x00000001,uint32_t))  /* Zero Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LT                                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LT_ADDR                          1                               /* Loop Top Address */
-#define BITP_LT_LSB                           0
-#define BITM_LT_ADDR                         (_ADI_MSK(0xFFFFFFFE,uint32_t))  /* Loop Top Address */
-#define BITM_LT_LSB                          (_ADI_MSK(0x00000001,uint32_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEQSTAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEQSTAT_NSPECABT                19                               /* Nonspeculative access was aborted */
-#define BITP_SEQSTAT_HWERRCAUSE              14                               /* Holds cause of last hardware error generated by the core */
-#define BITP_SEQSTAT_SFTRESET                13                               /* Indicates whether the last reset was a software reset */
-#define BITP_SEQSTAT_ITESTABT                12                               /* ITEST_COMMAND was aborted */
-#define BITP_SEQSTAT_DTESTABT                11                               /* DTEST_COMMAND was aborted */
-#define BITP_SEQSTAT_SYSNMI                  10                               /* System NMI Input Active */
-#define BITP_SEQSTAT_PEIC                     9                               /* Parity Error on Instruction L1 Read for Core */
-#define BITP_SEQSTAT_PEDC                     8                               /* Parity Error on Data L1 Read for Core */
-#define BITP_SEQSTAT_PEIX                     7                               /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_PEDX                     6                               /* Parity Error on Data L1 Read for L2 Transfer */
-#define BITP_SEQSTAT_EXCAUSE                  0                               /* Holds cause of last-executed exception */
-#define BITM_SEQSTAT_NSPECABT                (_ADI_MSK(0x00080000,uint32_t))  /* Nonspeculative access was aborted */
-#define BITM_SEQSTAT_HWERRCAUSE              (_ADI_MSK(0x0007C000,uint32_t))  /* Holds cause of last hardware error generated by the core */
-#define BITM_SEQSTAT_SFTRESET                (_ADI_MSK(0x00002000,uint32_t))  /* Indicates whether the last reset was a software reset */
-#define BITM_SEQSTAT_ITESTABT                (_ADI_MSK(0x00001000,uint32_t))  /* ITEST_COMMAND was aborted */
-#define BITM_SEQSTAT_DTESTABT                (_ADI_MSK(0x00000800,uint32_t))  /* DTEST_COMMAND was aborted */
-#define BITM_SEQSTAT_SYSNMI                  (_ADI_MSK(0x00000400,uint32_t))  /* System NMI Input Active */
-#define BITM_SEQSTAT_PEIC                    (_ADI_MSK(0x00000200,uint32_t))  /* Parity Error on Instruction L1 Read for Core */
-#define BITM_SEQSTAT_PEDC                    (_ADI_MSK(0x00000100,uint32_t))  /* Parity Error on Data L1 Read for Core */
-#define BITM_SEQSTAT_PEIX                    (_ADI_MSK(0x00000080,uint32_t))  /* Parity Error on Instruction L1 Read for L2 Transfer */
-#define BITM_SEQSTAT_PEDX                    (_ADI_MSK(0x00000040,uint32_t))  /* Parity Error on Data L1 Read for L2 Transfer */
-
-#define BITM_SEQSTAT_EXCAUSE                 (_ADI_MSK(0x0000003F,uint32_t))  /* Holds cause of last-executed exception */
-#define ENUM_SEQSTAT_EXINST                  (_ADI_MSK(0x00000000,uint32_t))  /* EXCAUSE: EXCPT Instruction */
-#define ENUM_SEQSTAT_SSTEP                   (_ADI_MSK(0x00000010,uint32_t))  /* EXCAUSE: Single Step */
-#define ENUM_SEQSTAT_EMUTROV                 (_ADI_MSK(0x00000011,uint32_t))  /* EXCAUSE: Trace Buffer */
-#define ENUM_SEQSTAT_UNDEFINST               (_ADI_MSK(0x00000021,uint32_t))  /* EXCAUSE: Undefined Instruction */
-#define ENUM_SEQSTAT_ILLCOMB                 (_ADI_MSK(0x00000022,uint32_t))  /* EXCAUSE: Illegal Combination */
-#define ENUM_SEQSTAT_DAGPROTVIOL             (_ADI_MSK(0x00000023,uint32_t))  /* EXCAUSE: DAG Protection Violation */
-#define ENUM_SEQSTAT_DAGALGN                 (_ADI_MSK(0x00000024,uint32_t))  /* EXCAUSE: DAG Misaligned Access */
-#define ENUM_SEQSTAT_UNRECOVER               (_ADI_MSK(0x00000025,uint32_t))  /* EXCAUSE: Unrecoverable Event */
-#define ENUM_SEQSTAT_DAGCPLBMISS             (_ADI_MSK(0x00000026,uint32_t))  /* EXCAUSE: DAG CPLB Miss */
-#define ENUM_SEQSTAT_DAGMCPLBH               (_ADI_MSK(0x00000027,uint32_t))  /* EXCAUSE: DAG Multiple CPLB Hits */
-#define ENUM_SEQSTAT_EMUWPMATCH              (_ADI_MSK(0x00000028,uint32_t))  /* EXCAUSE: Watchpoint Match */
-#define ENUM_SEQSTAT_IFALGN                  (_ADI_MSK(0x0000002A,uint32_t))  /* EXCAUSE: I-Fetch Misaligned Access */
-#define ENUM_SEQSTAT_IFPROTVIOL              (_ADI_MSK(0x0000002B,uint32_t))  /* EXCAUSE: I-Fetch Protection Violation */
-#define ENUM_SEQSTAT_IFCPLBMISS              (_ADI_MSK(0x0000002C,uint32_t))  /* EXCAUSE: I-Fetch CPLB Miss */
-#define ENUM_SEQSTAT_IFMCPLBH                (_ADI_MSK(0x0000002D,uint32_t))  /* EXCAUSE: I-Fetch Multiple CPLB Hits */
-#define ENUM_SEQSTAT_PROTVIOL                (_ADI_MSK(0x0000002E,uint32_t))  /* EXCAUSE: Illegal use superv. res */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SYSCFG                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SYSCFG_SNEN                      2                               /* Self-Nesting Interrupt Enable */
-#define BITP_SYSCFG_CCEN                      1                               /* Enable cycle counter */
-#define BITP_SYSCFG_SSSTEP                    0                               /* Supervisor single step */
-#define BITM_SYSCFG_SNEN                     (_ADI_MSK(0x00000004,uint32_t))  /* Self-Nesting Interrupt Enable */
-#define BITM_SYSCFG_CCEN                     (_ADI_MSK(0x00000002,uint32_t))  /* Enable cycle counter */
-#define BITM_SYSCFG_SSSTEP                   (_ADI_MSK(0x00000001,uint32_t))  /* Supervisor single step */
-
-/* ==================================================
-        CNT Registers
-   ================================================== */
-
-/* =========================
-        CNT0
-   ========================= */
-#define REG_CNT0_CFG                    0xFFC00400         /* CNT0 Configuration Register */
-#define REG_CNT0_IMSK                   0xFFC00404         /* CNT0 Interrupt Mask Register */
-#define REG_CNT0_STAT                   0xFFC00408         /* CNT0 Status Register */
-#define REG_CNT0_CMD                    0xFFC0040C         /* CNT0 Command Register */
-#define REG_CNT0_DEBNCE                 0xFFC00410         /* CNT0 Debounce Register */
-#define REG_CNT0_CNTR                   0xFFC00414         /* CNT0 Counter Register */
-#define REG_CNT0_MAX                    0xFFC00418         /* CNT0 Maximum Count Register */
-#define REG_CNT0_MIN                    0xFFC0041C         /* CNT0 Minimum Count Register */
-
-/* =========================
-        CNT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CFG_INPDIS                  15                               /* CUD and CDG Pin Input Disable */
-#define BITP_CNT_CFG_BNDMODE                 12                               /* Boundary Register Mode */
-#define BITP_CNT_CFG_ZMZC                    11                               /* CZM Zeroes Counter Enable */
-#define BITP_CNT_CFG_CNTMODE                  8                               /* Counter Operating Mode */
-#define BITP_CNT_CFG_CZMINV                   6                               /* CZM Pin Polarity Invert */
-#define BITP_CNT_CFG_CUDINV                   5                               /* CUD Pin Polarity Invert */
-#define BITP_CNT_CFG_CDGINV                   4                               /* CDG Pin Polarity Invert */
-#define BITP_CNT_CFG_DEBEN                    1                               /* Debounce Enable */
-#define BITP_CNT_CFG_EN                       0                               /* Counter Enable */
-
-#define BITM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* CUD and CDG Pin Input Disable */
-#define ENUM_CNT_CFG_NO_INPDIS               (_ADI_MSK(0x00000000,uint16_t))  /* INPDIS: Enable */
-#define ENUM_CNT_CFG_INPDIS                  (_ADI_MSK(0x00008000,uint16_t))  /* INPDIS: Pin Input Disable */
-
-#define BITM_CNT_CFG_BNDMODE                 (_ADI_MSK(0x00003000,uint16_t))  /* Boundary Register Mode */
-#define ENUM_CNT_CFG_BNDMODE_BNDCOMP         (_ADI_MSK(0x00000000,uint16_t))  /* BNDMODE: BND_COMP */
-#define ENUM_CNT_CFG_BNDMODE_BINENC          (_ADI_MSK(0x00001000,uint16_t))  /* BNDMODE: BIN_ENC */
-#define ENUM_CNT_CFG_BNDMODE_BNDCAPT         (_ADI_MSK(0x00002000,uint16_t))  /* BNDMODE: BND_CAPT */
-#define ENUM_CNT_CFG_BNDMODE_BNDAEXT         (_ADI_MSK(0x00003000,uint16_t))  /* BNDMODE: BND_AEXT */
-
-#define BITM_CNT_CFG_ZMZC                    (_ADI_MSK(0x00000800,uint16_t))  /* CZM Zeroes Counter Enable */
-#define ENUM_CNT_CFG_ZMZC_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* ZMZC: Disable */
-#define ENUM_CNT_CFG_ZMZC_EN                 (_ADI_MSK(0x00000800,uint16_t))  /* ZMZC: Enable */
-
-#define BITM_CNT_CFG_CNTMODE                 (_ADI_MSK(0x00000700,uint16_t))  /* Counter Operating Mode */
-#define ENUM_CNT_CFG_CNTMODE_QUADENC         (_ADI_MSK(0x00000000,uint16_t))  /* CNTMODE: QUAD_ENC */
-#define ENUM_CNT_CFG_CNTMODE_BINENC          (_ADI_MSK(0x00000100,uint16_t))  /* CNTMODE: BIN_ENC */
-#define ENUM_CNT_CFG_CNTMODE_UDCNT           (_ADI_MSK(0x00000200,uint16_t))  /* CNTMODE: UD_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRCNT          (_ADI_MSK(0x00000400,uint16_t))  /* CNTMODE: DIR_CNT */
-#define ENUM_CNT_CFG_CNTMODE_DIRTMR          (_ADI_MSK(0x00000500,uint16_t))  /* CNTMODE: DIR_TMR */
-
-#define BITM_CNT_CFG_CZMINV                  (_ADI_MSK(0x00000040,uint16_t))  /* CZM Pin Polarity Invert */
-#define ENUM_CNT_CFG_CZMINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CZMINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CZMINV_ALO              (_ADI_MSK(0x00000040,uint16_t))  /* CZMINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CUDINV                  (_ADI_MSK(0x00000020,uint16_t))  /* CUD Pin Polarity Invert */
-#define ENUM_CNT_CFG_CUDINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CUDINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CUDINV_ALO              (_ADI_MSK(0x00000020,uint16_t))  /* CUDINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_CDGINV                  (_ADI_MSK(0x00000010,uint16_t))  /* CDG Pin Polarity Invert */
-#define ENUM_CNT_CFG_CDGINV_AHI              (_ADI_MSK(0x00000000,uint16_t))  /* CDGINV: Active High, Rising Edge */
-#define ENUM_CNT_CFG_CDGINV_ALO              (_ADI_MSK(0x00000010,uint16_t))  /* CDGINV: Active Low, Falling Edge */
-
-#define BITM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* Debounce Enable */
-#define ENUM_CNT_CFG_DEBDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* DEBEN: Disable */
-#define ENUM_CNT_CFG_DEBEN                   (_ADI_MSK(0x00000002,uint16_t))  /* DEBEN: Enable */
-
-#define BITM_CNT_CFG_EN                      (_ADI_MSK(0x00000001,uint16_t))  /* Counter Enable */
-#define ENUM_CNT_CFG_CNTDIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Counter Disable */
-#define ENUM_CNT_CFG_CNTEN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Counter Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_IMSK_CZMZ                   10                               /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define BITP_CNT_IMSK_CZME                    9                               /* Zero Marker Error Interrupt Enable */
-#define BITP_CNT_IMSK_CZM                     8                               /* CZM Pin / Pushbutton Interrupt Enable */
-#define BITP_CNT_IMSK_CZERO                   7                               /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define BITP_CNT_IMSK_COV15                   6                               /* Bit 15 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_COV31                   5                               /* Bit 31 Overflow Interrupt Enable */
-#define BITP_CNT_IMSK_MAXC                    4                               /* Max Count Interrupt Enable */
-#define BITP_CNT_IMSK_MINC                    3                               /* Min Count Interrupt Enable */
-#define BITP_CNT_IMSK_DC                      2                               /* Downcount Interrupt enable */
-#define BITP_CNT_IMSK_UC                      1                               /* Upcount Interrupt Enable */
-#define BITP_CNT_IMSK_IC                      0                               /* Illegal Gray/Binary Code Interrupt Enable */
-
-#define BITM_CNT_IMSK_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed by Zero Marker Interrupt Enable */
-#define ENUM_CNT_IMSK_CZMZ_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZMZ: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZMZ_UMSK              (_ADI_MSK(0x00000400,uint16_t))  /* CZMZ: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error Interrupt Enable */
-#define ENUM_CNT_IMSK_CZME_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* CZME: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZME_UMSK              (_ADI_MSK(0x00000200,uint16_t))  /* CZME: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin / Pushbutton Interrupt Enable */
-#define ENUM_CNT_IMSK_CZM_MSK                (_ADI_MSK(0x00000000,uint16_t))  /* CZM: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZM_UMSK               (_ADI_MSK(0x00000100,uint16_t))  /* CZM: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero Interrupt Enable */
-#define ENUM_CNT_IMSK_CZERO_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* CZERO: Mask Interrupt */
-#define ENUM_CNT_IMSK_CZERO_UMSK             (_ADI_MSK(0x00000080,uint16_t))  /* CZERO: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV15_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV15: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV15_UMSK             (_ADI_MSK(0x00000040,uint16_t))  /* COV15: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 Overflow Interrupt Enable */
-#define ENUM_CNT_IMSK_COV31_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* COV31: Mask Interrupt */
-#define ENUM_CNT_IMSK_COV31_UMSK             (_ADI_MSK(0x00000020,uint16_t))  /* COV31: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MAXC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MAXC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MAXC_UMSK              (_ADI_MSK(0x00000010,uint16_t))  /* MAXC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min Count Interrupt Enable */
-#define ENUM_CNT_IMSK_MINC_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MINC: Mask Interrupt */
-#define ENUM_CNT_IMSK_MINC_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* MINC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount Interrupt enable */
-#define ENUM_CNT_IMSK_DC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* DC: Mask Interrupt */
-#define ENUM_CNT_IMSK_DC_UMSK                (_ADI_MSK(0x00000004,uint16_t))  /* DC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount Interrupt Enable */
-#define ENUM_CNT_IMSK_UC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* UC: Mask Interrupt */
-#define ENUM_CNT_IMSK_UC_UMSK                (_ADI_MSK(0x00000002,uint16_t))  /* UC: Unmask Interrupt */
-
-#define BITM_CNT_IMSK_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal Gray/Binary Code Interrupt Enable */
-#define ENUM_CNT_IMSK_IC_MSK                 (_ADI_MSK(0x00000000,uint16_t))  /* IC: Mask Interrupt */
-#define ENUM_CNT_IMSK_IC_UMSK                (_ADI_MSK(0x00000001,uint16_t))  /* IC: Unmask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_STAT_CZMZ                   10                               /* Counter Zeroed By Zero Marker interrupt */
-#define BITP_CNT_STAT_CZME                    9                               /* Zero Marker Error interrupt */
-#define BITP_CNT_STAT_CZM                     8                               /* CZM Pin/Pushbutton interrupt */
-#define BITP_CNT_STAT_CZERO                   7                               /* CNT_CNTR Counts To Zero interrupt */
-#define BITP_CNT_STAT_COV15                   6                               /* Bit 15 overflow interrupt */
-#define BITP_CNT_STAT_COV31                   5                               /* Bit 31 overflow interrupt */
-#define BITP_CNT_STAT_MAXC                    4                               /* Max interrupt */
-#define BITP_CNT_STAT_MINC                    3                               /* Min interrupt */
-#define BITP_CNT_STAT_DC                      2                               /* Downcount interrupt */
-#define BITP_CNT_STAT_UC                      1                               /* Upcount interrupt */
-#define BITP_CNT_STAT_IC                      0                               /* Illegal gray/binary code interrupt */
-#define BITM_CNT_STAT_CZMZ                   (_ADI_MSK(0x00000400,uint16_t))  /* Counter Zeroed By Zero Marker interrupt */
-#define BITM_CNT_STAT_CZME                   (_ADI_MSK(0x00000200,uint16_t))  /* Zero Marker Error interrupt */
-#define BITM_CNT_STAT_CZM                    (_ADI_MSK(0x00000100,uint16_t))  /* CZM Pin/Pushbutton interrupt */
-#define BITM_CNT_STAT_CZERO                  (_ADI_MSK(0x00000080,uint16_t))  /* CNT_CNTR Counts To Zero interrupt */
-#define BITM_CNT_STAT_COV15                  (_ADI_MSK(0x00000040,uint16_t))  /* Bit 15 overflow interrupt */
-#define BITM_CNT_STAT_COV31                  (_ADI_MSK(0x00000020,uint16_t))  /* Bit 31 overflow interrupt */
-#define BITM_CNT_STAT_MAXC                   (_ADI_MSK(0x00000010,uint16_t))  /* Max interrupt */
-#define BITM_CNT_STAT_MINC                   (_ADI_MSK(0x00000008,uint16_t))  /* Min interrupt */
-#define BITM_CNT_STAT_DC                     (_ADI_MSK(0x00000004,uint16_t))  /* Downcount interrupt */
-#define BITM_CNT_STAT_UC                     (_ADI_MSK(0x00000002,uint16_t))  /* Upcount interrupt */
-#define BITM_CNT_STAT_IC                     (_ADI_MSK(0x00000001,uint16_t))  /* Illegal gray/binary code interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_CMD_W1ZMONCE                12                               /* Write 1 Zero Marker Clear Once Enable */
-#define BITP_CNT_CMD_W1LMAXMIN               10                               /* Write 1 MAX copy from MIN */
-#define BITP_CNT_CMD_W1LMAXCNT                9                               /* Write 1 MAX capture from CNTR */
-#define BITP_CNT_CMD_W1LMAXZERO               8                               /* Write 1 MAX to zero */
-#define BITP_CNT_CMD_W1LMINMAX                7                               /* Write 1 MIN copy from MAX */
-#define BITP_CNT_CMD_W1LMINCNT                5                               /* Write 1 MIN capture from CNTR */
-#define BITP_CNT_CMD_W1LMINZERO               4                               /* Write 1 MIN to zero */
-#define BITP_CNT_CMD_W1LCNTMAX                3                               /* Write 1 CNTR load from MAX */
-#define BITP_CNT_CMD_W1LCNTMIN                2                               /* Write 1 CNTR load from MIN */
-#define BITP_CNT_CMD_W1LCNTZERO               0                               /* Write 1 CNTR to zero */
-#define BITM_CNT_CMD_W1ZMONCE                (_ADI_MSK(0x00001000,uint16_t))  /* Write 1 Zero Marker Clear Once Enable */
-#define BITM_CNT_CMD_W1LMAXMIN               (_ADI_MSK(0x00000400,uint16_t))  /* Write 1 MAX copy from MIN */
-#define BITM_CNT_CMD_W1LMAXCNT               (_ADI_MSK(0x00000200,uint16_t))  /* Write 1 MAX capture from CNTR */
-#define BITM_CNT_CMD_W1LMAXZERO              (_ADI_MSK(0x00000100,uint16_t))  /* Write 1 MAX to zero */
-#define BITM_CNT_CMD_W1LMINMAX               (_ADI_MSK(0x00000080,uint16_t))  /* Write 1 MIN copy from MAX */
-#define BITM_CNT_CMD_W1LMINCNT               (_ADI_MSK(0x00000020,uint16_t))  /* Write 1 MIN capture from CNTR */
-#define BITM_CNT_CMD_W1LMINZERO              (_ADI_MSK(0x00000010,uint16_t))  /* Write 1 MIN to zero */
-#define BITM_CNT_CMD_W1LCNTMAX               (_ADI_MSK(0x00000008,uint16_t))  /* Write 1 CNTR load from MAX */
-#define BITM_CNT_CMD_W1LCNTMIN               (_ADI_MSK(0x00000004,uint16_t))  /* Write 1 CNTR load from MIN */
-#define BITM_CNT_CMD_W1LCNTZERO              (_ADI_MSK(0x00000001,uint16_t))  /* Write 1 CNTR to zero */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CNT_DEBNCE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CNT_DEBNCE_DPRESCALE             0                               /* Debounce Prescale */
-#define BITM_CNT_DEBNCE_DPRESCALE            (_ADI_MSK(0x0000001F,uint16_t))  /* Debounce Prescale */
-
-/* ==================================================
-        RSI Registers
-   ================================================== */
-
-/* =========================
-        RSI0
-   ========================= */
-#define REG_RSI0_CTL                    0xFFC00604         /* RSI0 Control Register */
-#define REG_RSI0_ARG                    0xFFC00608         /* RSI0 Argument Register */
-#define REG_RSI0_CMD                    0xFFC0060C         /* RSI0 Command Register */
-#define REG_RSI0_RESP_CMD               0xFFC00610         /* RSI0 Response Command Register */
-#define REG_RSI0_RESP0                  0xFFC00614         /* RSI0 Response 0 Register */
-#define REG_RSI0_RESP1                  0xFFC00618         /* RSI0 Response 1 Register */
-#define REG_RSI0_RESP2                  0xFFC0061C         /* RSI0 Response 2 Register */
-#define REG_RSI0_RESP3                  0xFFC00620         /* RSI0 Response 3 Register */
-#define REG_RSI0_DATA_TMR               0xFFC00624         /* RSI0 Data Timer Register */
-#define REG_RSI0_DATA_LEN               0xFFC00628         /* RSI0 Data Length Register */
-#define REG_RSI0_DATA_CTL               0xFFC0062C         /* RSI0 Data Control Register */
-#define REG_RSI0_DATA_CNT               0xFFC00630         /* RSI0 Data Count Register */
-#define REG_RSI0_XFRSTAT                0xFFC00634         /* RSI0 Status Register */
-#define REG_RSI0_XFRSTAT_CLR            0xFFC00638         /* RSI0 Status Clear Register */
-#define REG_RSI0_XFR_IMSK0              0xFFC0063C         /* RSI0 Interrupt 0 Mask Register */
-#define REG_RSI0_XFR_IMSK1              0xFFC00640         /* RSI0 Interrupt 1 Mask Register */
-#define REG_RSI0_FIFO_CNT               0xFFC00648         /* RSI0 FIFO Counter Register */
-#define REG_RSI0_CEATA                  0xFFC0064C         /* RSI0 This register contains bit to dis CCS gen */
-#define REG_RSI0_BOOT_TCNTR             0xFFC00650         /* RSI0 Boot Timing Counter Register */
-#define REG_RSI0_BACK_TOUT              0xFFC00654         /* RSI0 Boot Acknowledge Timeout Register */
-#define REG_RSI0_SLP_WKUP_TOUT          0xFFC00658         /* RSI0 Sleep Wakeup Timeout Register */
-#define REG_RSI0_BLKSZ                  0xFFC0065C         /* RSI0 Block Size Register */
-#define REG_RSI0_FIFO                   0xFFC00680         /* RSI0 Data FIFO Register */
-#define REG_RSI0_STAT0                  0xFFC006C0         /* RSI0 Exception Status Register */
-#define REG_RSI0_IMSK0                  0xFFC006C4         /* RSI0 Exception Mask Register */
-#define REG_RSI0_CFG                    0xFFC006C8         /* RSI0 Configuration Register */
-#define REG_RSI0_RD_WAIT                0xFFC006CC         /* RSI0 Read Wait Enable Register */
-#define REG_RSI0_PID0                   0xFFC006D0         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID1                   0xFFC006D4         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID2                   0xFFC006D8         /* RSI0 Peripheral Identification Register */
-#define REG_RSI0_PID3                   0xFFC006DC         /* RSI0 Peripheral Identification Register */
-
-/* =========================
-        RSI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CTL_CARDTYPE                13                               /* Type of Card */
-#define BITP_RSI_CTL_BUSWID                  11                               /* Wide Bus Mode Enable */
-#define BITP_RSI_CTL_BYPASS                  10                               /* Bypass clock divisor */
-#define BITP_RSI_CTL_PWRSAVE                  9                               /* Power Save Enable */
-#define BITP_RSI_CTL_CLKEN                    8                               /* RSI_CLK Bus Clock Enable */
-#define BITP_RSI_CTL_CLKDIV                   0                               /* RSI_CLK Divisor */
-#define BITM_RSI_CTL_CARDTYPE                (_ADI_MSK(0x0000E000,uint16_t))  /* Type of Card */
-#define BITM_RSI_CTL_BUSWID                  (_ADI_MSK(0x00001800,uint16_t))  /* Wide Bus Mode Enable */
-#define BITM_RSI_CTL_BYPASS                  (_ADI_MSK(0x00000400,uint16_t))  /* Bypass clock divisor */
-#define BITM_RSI_CTL_PWRSAVE                 (_ADI_MSK(0x00000200,uint16_t))  /* Power Save Enable */
-#define BITM_RSI_CTL_CLKEN                   (_ADI_MSK(0x00000100,uint16_t))  /* RSI_CLK Bus Clock Enable */
-#define BITM_RSI_CTL_CLKDIV                  (_ADI_MSK(0x000000FF,uint16_t))  /* RSI_CLK Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CMD                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CMD_CHKBUSY                 12                               /* Check Busy Condition */
-#define BITP_RSI_CMD_CRCDIS                  11                               /* Disable CRC Check */
-#define BITP_RSI_CMD_EN                      10                               /* Command Enable */
-#define BITP_RSI_CMD_PNDEN                    9                               /* Command Pending enabled */
-#define BITP_RSI_CMD_IEN                      8                               /* Command Interrupt Enabled */
-#define BITP_RSI_CMD_LRSP                     7                               /* Long Response */
-#define BITP_RSI_CMD_RSP                      6                               /* Response */
-#define BITP_RSI_CMD_IDX                      0                               /* Command Index */
-#define BITM_RSI_CMD_CHKBUSY                 (_ADI_MSK(0x00001000,uint16_t))  /* Check Busy Condition */
-#define BITM_RSI_CMD_CRCDIS                  (_ADI_MSK(0x00000800,uint16_t))  /* Disable CRC Check */
-#define BITM_RSI_CMD_EN                      (_ADI_MSK(0x00000400,uint16_t))  /* Command Enable */
-#define BITM_RSI_CMD_PNDEN                   (_ADI_MSK(0x00000200,uint16_t))  /* Command Pending enabled */
-#define BITM_RSI_CMD_IEN                     (_ADI_MSK(0x00000100,uint16_t))  /* Command Interrupt Enabled */
-#define BITM_RSI_CMD_LRSP                    (_ADI_MSK(0x00000080,uint16_t))  /* Long Response */
-#define BITM_RSI_CMD_RSP                     (_ADI_MSK(0x00000040,uint16_t))  /* Response */
-#define BITM_RSI_CMD_IDX                     (_ADI_MSK(0x0000003F,uint16_t))  /* Command Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RESP_CMD                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RESP_CMD_VALUE               0                               /* Response Command */
-#define BITM_RSI_RESP_CMD_VALUE              (_ADI_MSK(0x0000003F,uint16_t))  /* Response Command */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_DATA_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_DATA_CTL_CEATAIEN            9                               /* Ceata Command Completion Interrupt Enable */
-#define BITP_RSI_DATA_CTL_CEATAMODE           8                               /* Ceata Mode enable */
-#define BITP_RSI_DATA_CTL_DMAEN               3                               /* Data Transfer DMA Enable */
-#define BITP_RSI_DATA_CTL_DATMODE             2                               /* Data Transfer Mode */
-#define BITP_RSI_DATA_CTL_DATDIR              1                               /* Data Transfer Direction */
-#define BITP_RSI_DATA_CTL_DATEN               0                               /* Data Transfer Enable */
-#define BITM_RSI_DATA_CTL_CEATAIEN           (_ADI_MSK(0x00000200,uint16_t))  /* Ceata Command Completion Interrupt Enable */
-#define BITM_RSI_DATA_CTL_CEATAMODE          (_ADI_MSK(0x00000100,uint16_t))  /* Ceata Mode enable */
-#define BITM_RSI_DATA_CTL_DMAEN              (_ADI_MSK(0x00000008,uint16_t))  /* Data Transfer DMA Enable */
-#define BITM_RSI_DATA_CTL_DATMODE            (_ADI_MSK(0x00000004,uint16_t))  /* Data Transfer Mode */
-#define BITM_RSI_DATA_CTL_DATDIR             (_ADI_MSK(0x00000002,uint16_t))  /* Data Transfer Direction */
-#define BITM_RSI_DATA_CTL_DATEN              (_ADI_MSK(0x00000001,uint16_t))  /* Data Transfer Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_RXFIFORDY           21                               /* Receive FIFO Available */
-#define BITP_RSI_XFRSTAT_TXFIFORDY           20                               /* Transmit FIFO Available */
-#define BITP_RSI_XFRSTAT_RXFIFOZERO          19                               /* Receive FIFO Empty */
-#define BITP_RSI_XFRSTAT_TXFIFOZERO          18                               /* Transmit FIFO Empty */
-#define BITP_RSI_XFRSTAT_RXFIFOFULL          17                               /* Receive FIFO Full */
-#define BITP_RSI_XFRSTAT_TXFIFOFULL          16                               /* Transmit FIFO Full */
-#define BITP_RSI_XFRSTAT_RXFIFOSTAT          15                               /* Receive FIFO Status */
-#define BITP_RSI_XFRSTAT_TXFIFOSTAT          14                               /* Transmit FIFO Status */
-#define BITP_RSI_XFRSTAT_RXACT               13                               /* Receive Active */
-#define BITP_RSI_XFRSTAT_TXACT               12                               /* Transmit Active */
-#define BITP_RSI_XFRSTAT_CMDACT              11                               /* Command Active */
-#define BITP_RSI_XFRSTAT_DATBLKEND           10                               /* Data Block End */
-#define BITP_RSI_XFRSTAT_SBITERR              9                               /* Start Bit Error */
-#define BITP_RSI_XFRSTAT_DATEND               8                               /* Data End */
-#define BITP_RSI_XFRSTAT_CMDSENT              7                               /* Command Sent */
-#define BITP_RSI_XFRSTAT_RESPEND              6                               /* Command Response End */
-#define BITP_RSI_XFRSTAT_RXOVER               5                               /* Receive Over run */
-#define BITP_RSI_XFRSTAT_TXUNDR               4                               /* Transmit Under run */
-#define BITP_RSI_XFRSTAT_DATTO                3                               /* Data Timeout */
-#define BITP_RSI_XFRSTAT_CMDTO                2                               /* CMD Timeout */
-#define BITP_RSI_XFRSTAT_DATCRCFAIL           1                               /* Data CRC Fail */
-#define BITP_RSI_XFRSTAT_CMDCRCFAIL           0                               /* CMD CRC Fail */
-#define BITM_RSI_XFRSTAT_RXFIFORDY           (_ADI_MSK(0x00200000,uint32_t))  /* Receive FIFO Available */
-#define BITM_RSI_XFRSTAT_TXFIFORDY           (_ADI_MSK(0x00100000,uint32_t))  /* Transmit FIFO Available */
-#define BITM_RSI_XFRSTAT_RXFIFOZERO          (_ADI_MSK(0x00080000,uint32_t))  /* Receive FIFO Empty */
-#define BITM_RSI_XFRSTAT_TXFIFOZERO          (_ADI_MSK(0x00040000,uint32_t))  /* Transmit FIFO Empty */
-#define BITM_RSI_XFRSTAT_RXFIFOFULL          (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Full */
-#define BITM_RSI_XFRSTAT_TXFIFOFULL          (_ADI_MSK(0x00010000,uint32_t))  /* Transmit FIFO Full */
-#define BITM_RSI_XFRSTAT_RXFIFOSTAT          (_ADI_MSK(0x00008000,uint32_t))  /* Receive FIFO Status */
-#define BITM_RSI_XFRSTAT_TXFIFOSTAT          (_ADI_MSK(0x00004000,uint32_t))  /* Transmit FIFO Status */
-#define BITM_RSI_XFRSTAT_RXACT               (_ADI_MSK(0x00002000,uint32_t))  /* Receive Active */
-#define BITM_RSI_XFRSTAT_TXACT               (_ADI_MSK(0x00001000,uint32_t))  /* Transmit Active */
-#define BITM_RSI_XFRSTAT_CMDACT              (_ADI_MSK(0x00000800,uint32_t))  /* Command Active */
-#define BITM_RSI_XFRSTAT_DATBLKEND           (_ADI_MSK(0x00000400,uint32_t))  /* Data Block End */
-#define BITM_RSI_XFRSTAT_SBITERR             (_ADI_MSK(0x00000200,uint32_t))  /* Start Bit Error */
-#define BITM_RSI_XFRSTAT_DATEND              (_ADI_MSK(0x00000100,uint32_t))  /* Data End */
-#define BITM_RSI_XFRSTAT_CMDSENT             (_ADI_MSK(0x00000080,uint32_t))  /* Command Sent */
-#define BITM_RSI_XFRSTAT_RESPEND             (_ADI_MSK(0x00000040,uint32_t))  /* Command Response End */
-#define BITM_RSI_XFRSTAT_RXOVER              (_ADI_MSK(0x00000020,uint32_t))  /* Receive Over run */
-#define BITM_RSI_XFRSTAT_TXUNDR              (_ADI_MSK(0x00000010,uint32_t))  /* Transmit Under run */
-#define BITM_RSI_XFRSTAT_DATTO               (_ADI_MSK(0x00000008,uint32_t))  /* Data Timeout */
-#define BITM_RSI_XFRSTAT_CMDTO               (_ADI_MSK(0x00000004,uint32_t))  /* CMD Timeout */
-#define BITM_RSI_XFRSTAT_DATCRCFAIL          (_ADI_MSK(0x00000002,uint32_t))  /* Data CRC Fail */
-#define BITM_RSI_XFRSTAT_CMDCRCFAIL          (_ADI_MSK(0x00000001,uint32_t))  /* CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFRSTAT_CLR                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFRSTAT_CLR_DATBLKEND       10                               /* Data Block End Status */
-#define BITP_RSI_XFRSTAT_CLR_STRTBITERR       9                               /* Start Bit Error Status */
-#define BITP_RSI_XFRSTAT_CLR_DATEND           8                               /* Data End Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDSENT          7                               /* Command Sent Status */
-#define BITP_RSI_XFRSTAT_CLR_RESPEND          6                               /* Command Response End Status */
-#define BITP_RSI_XFRSTAT_CLR_RXOVER           5                               /* Receive Over run Status */
-#define BITP_RSI_XFRSTAT_CLR_TXUNDR           4                               /* Transmit Under run Status */
-#define BITP_RSI_XFRSTAT_CLR_DATTO            3                               /* Data Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDTO            2                               /* CMD Timeout Status */
-#define BITP_RSI_XFRSTAT_CLR_DATCRCFAIL       1                               /* Data CRC Fail Status */
-#define BITP_RSI_XFRSTAT_CLR_CMDCRCFAIL       0                               /* CMD CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_DATBLKEND       (_ADI_MSK(0x00000400,uint16_t))  /* Data Block End Status */
-#define BITM_RSI_XFRSTAT_CLR_STRTBITERR      (_ADI_MSK(0x00000200,uint16_t))  /* Start Bit Error Status */
-#define BITM_RSI_XFRSTAT_CLR_DATEND          (_ADI_MSK(0x00000100,uint16_t))  /* Data End Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDSENT         (_ADI_MSK(0x00000080,uint16_t))  /* Command Sent Status */
-#define BITM_RSI_XFRSTAT_CLR_RESPEND         (_ADI_MSK(0x00000040,uint16_t))  /* Command Response End Status */
-#define BITM_RSI_XFRSTAT_CLR_RXOVER          (_ADI_MSK(0x00000020,uint16_t))  /* Receive Over run Status */
-#define BITM_RSI_XFRSTAT_CLR_TXUNDR          (_ADI_MSK(0x00000010,uint16_t))  /* Transmit Under run Status */
-#define BITM_RSI_XFRSTAT_CLR_DATTO           (_ADI_MSK(0x00000008,uint16_t))  /* Data Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDTO           (_ADI_MSK(0x00000004,uint16_t))  /* CMD Timeout Status */
-#define BITM_RSI_XFRSTAT_CLR_DATCRCFAIL      (_ADI_MSK(0x00000002,uint16_t))  /* Data CRC Fail Status */
-#define BITM_RSI_XFRSTAT_CLR_CMDCRCFAIL      (_ADI_MSK(0x00000001,uint16_t))  /* CMD CRC Fail Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK0_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK0_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK0_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK0_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK0_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK0_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK0_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK0_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK0_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK0_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK0_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK0_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK0_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK0_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK0_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK0_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK0_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK0_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK0_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK0_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK0_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK0_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK0_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK0_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK0_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK0_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK0_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK0_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK0_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK0_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK0_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK0_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK0_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK0_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK0_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK0_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK0_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK0_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK0_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK0_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK0_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK0_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_XFR_IMSK1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_XFR_IMSK1_RXFIFORDY         21                               /* Enable Interrupt for Receive FIFO Available */
-#define BITP_RSI_XFR_IMSK1_TXFIFORDY         20                               /* Enable Interrupt for Transmit FIFO Available */
-#define BITP_RSI_XFR_IMSK1_RXFIFOZERO        19                               /* Enable Interrupt for Receive FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_TXFIFOZERO        18                               /* Enable Interrupt for Transmit FIFO Empty */
-#define BITP_RSI_XFR_IMSK1_RXFIFOFULL        17                               /* Enable Interrupt for Receive FIFO Full */
-#define BITP_RSI_XFR_IMSK1_TXFIFOFULL        16                               /* Enable Interrupt for Transmit FIFO Full */
-#define BITP_RSI_XFR_IMSK1_RXFIFOSTAT        15                               /* Enable Interrupt for Receive FIFO Status */
-#define BITP_RSI_XFR_IMSK1_TXFIFOSTAT        14                               /* Enable Interrupt for Transmit FIFO Status */
-#define BITP_RSI_XFR_IMSK1_RXACT             13                               /* Enable Interrupt for Receive Active */
-#define BITP_RSI_XFR_IMSK1_TXACT             12                               /* Enable Interrupt for Transmit Active */
-#define BITP_RSI_XFR_IMSK1_CMDACT            11                               /* Enable Interrupt for Command Active */
-#define BITP_RSI_XFR_IMSK1_DATBLKEND         10                               /* Enable Interrupt for Data Block End */
-#define BITP_RSI_XFR_IMSK1_STRTBITERR         9                               /* Enable Interrupt for Start Bit Error */
-#define BITP_RSI_XFR_IMSK1_DATEND             8                               /* Enable Interrupt for Data End */
-#define BITP_RSI_XFR_IMSK1_CMDSENT            7                               /* Enable Interrupt for Command Sent */
-#define BITP_RSI_XFR_IMSK1_RESPEND            6                               /* Enable Interrupt for Command Response End */
-#define BITP_RSI_XFR_IMSK1_RXOVER             5                               /* Enable Interrupt for Receive Over run */
-#define BITP_RSI_XFR_IMSK1_TXUNDR             4                               /* Enable Interrupt for Transmit Under run */
-#define BITP_RSI_XFR_IMSK1_DATTO              3                               /* Enable Interrupt for Data Timeout */
-#define BITP_RSI_XFR_IMSK1_CMDTO              2                               /* Enable Interrupt for CMD Timeout */
-#define BITP_RSI_XFR_IMSK1_DATCRCFAIL         1                               /* Enable Interrupt for Data CRC Fail */
-#define BITP_RSI_XFR_IMSK1_CMDCRCFAIL         0                               /* Enable Interrupt for CMD CRC Fail */
-#define BITM_RSI_XFR_IMSK1_RXFIFORDY         (_ADI_MSK(0x00200000,uint32_t))  /* Enable Interrupt for Receive FIFO Available */
-#define BITM_RSI_XFR_IMSK1_TXFIFORDY         (_ADI_MSK(0x00100000,uint32_t))  /* Enable Interrupt for Transmit FIFO Available */
-#define BITM_RSI_XFR_IMSK1_RXFIFOZERO        (_ADI_MSK(0x00080000,uint32_t))  /* Enable Interrupt for Receive FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_TXFIFOZERO        (_ADI_MSK(0x00040000,uint32_t))  /* Enable Interrupt for Transmit FIFO Empty */
-#define BITM_RSI_XFR_IMSK1_RXFIFOFULL        (_ADI_MSK(0x00020000,uint32_t))  /* Enable Interrupt for Receive FIFO Full */
-#define BITM_RSI_XFR_IMSK1_TXFIFOFULL        (_ADI_MSK(0x00010000,uint32_t))  /* Enable Interrupt for Transmit FIFO Full */
-#define BITM_RSI_XFR_IMSK1_RXFIFOSTAT        (_ADI_MSK(0x00008000,uint32_t))  /* Enable Interrupt for Receive FIFO Status */
-#define BITM_RSI_XFR_IMSK1_TXFIFOSTAT        (_ADI_MSK(0x00004000,uint32_t))  /* Enable Interrupt for Transmit FIFO Status */
-#define BITM_RSI_XFR_IMSK1_RXACT             (_ADI_MSK(0x00002000,uint32_t))  /* Enable Interrupt for Receive Active */
-#define BITM_RSI_XFR_IMSK1_TXACT             (_ADI_MSK(0x00001000,uint32_t))  /* Enable Interrupt for Transmit Active */
-#define BITM_RSI_XFR_IMSK1_CMDACT            (_ADI_MSK(0x00000800,uint32_t))  /* Enable Interrupt for Command Active */
-#define BITM_RSI_XFR_IMSK1_DATBLKEND         (_ADI_MSK(0x00000400,uint32_t))  /* Enable Interrupt for Data Block End */
-#define BITM_RSI_XFR_IMSK1_STRTBITERR        (_ADI_MSK(0x00000200,uint32_t))  /* Enable Interrupt for Start Bit Error */
-#define BITM_RSI_XFR_IMSK1_DATEND            (_ADI_MSK(0x00000100,uint32_t))  /* Enable Interrupt for Data End */
-#define BITM_RSI_XFR_IMSK1_CMDSENT           (_ADI_MSK(0x00000080,uint32_t))  /* Enable Interrupt for Command Sent */
-#define BITM_RSI_XFR_IMSK1_RESPEND           (_ADI_MSK(0x00000040,uint32_t))  /* Enable Interrupt for Command Response End */
-#define BITM_RSI_XFR_IMSK1_RXOVER            (_ADI_MSK(0x00000020,uint32_t))  /* Enable Interrupt for Receive Over run */
-#define BITM_RSI_XFR_IMSK1_TXUNDR            (_ADI_MSK(0x00000010,uint32_t))  /* Enable Interrupt for Transmit Under run */
-#define BITM_RSI_XFR_IMSK1_DATTO             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Interrupt for Data Timeout */
-#define BITM_RSI_XFR_IMSK1_CMDTO             (_ADI_MSK(0x00000004,uint32_t))  /* Enable Interrupt for CMD Timeout */
-#define BITM_RSI_XFR_IMSK1_DATCRCFAIL        (_ADI_MSK(0x00000002,uint32_t))  /* Enable Interrupt for Data CRC Fail */
-#define BITM_RSI_XFR_IMSK1_CMDCRCFAIL        (_ADI_MSK(0x00000001,uint32_t))  /* Enable Interrupt for CMD CRC Fail */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_FIFO_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_FIFO_CNT_VALUE               0                               /* FIFO Count */
-#define BITM_RSI_FIFO_CNT_VALUE              (_ADI_MSK(0x00007FFF,uint16_t))  /* FIFO Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CEATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CEATA_INT_DIS                0                               /* CEATA Disable Interrupt */
-#define BITM_RSI_CEATA_INT_DIS               (_ADI_MSK(0x00000001,uint32_t))  /* CEATA Disable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BOOT_TCNTR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BOOT_TCNTR_HOLD              8                               /* Boot Hold Time */
-#define BITP_RSI_BOOT_TCNTR_SETUP             0                               /* Boot Setup Time */
-#define BITM_RSI_BOOT_TCNTR_HOLD             (_ADI_MSK(0x0000FF00,uint16_t))  /* Boot Hold Time */
-#define BITM_RSI_BOOT_TCNTR_SETUP            (_ADI_MSK(0x000000FF,uint16_t))  /* Boot Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_BLKSZ                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_BLKSZ_VALUE                  0                               /* Size of Each Block of Data */
-#define BITM_RSI_BLKSZ_VALUE                 (_ADI_MSK(0x00001FFF,uint16_t))  /* Size of Each Block of Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_STAT0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_STAT0_BUSYMODE              31                               /* Card is in Busy mode */
-#define BITP_RSI_STAT0_SLPMODE               30                               /* Card in Sleep Mode */
-#define BITP_RSI_STAT0_CARDRDY               17                               /* Card Ready */
-#define BITP_RSI_STAT0_SLPWKPTOUT            16                               /* Sleep Wakeup Timer Expired */
-#define BITP_RSI_STAT0_WKPDONE               15                               /* Card Entered Standby state */
-#define BITP_RSI_STAT0_SLPDONE               14                               /* Card Entered Sleep State */
-#define BITP_RSI_STAT0_BACKDONE              13                               /* Correct Boot Ack is received */
-#define BITP_RSI_STAT0_BACKBAD               12                               /* Boot Ack received is corrupted */
-#define BITP_RSI_STAT0_BACKTO                11                               /* Boot Acknowledge Timeout */
-#define BITP_RSI_STAT0_BDATTO                10                               /* Boot Data Timeout */
-#define BITP_RSI_STAT0_BHOLDEXP               9                               /* Boot Hold Time Expiry */
-#define BITP_RSI_STAT0_BSETUPEXP              8                               /* Boot Setup Time Expiry */
-#define BITP_RSI_STAT0_CEATAINT               5                               /* CEATA Interrupt */
-#define BITP_RSI_STAT0_SDCARD                 4                               /* SD Card Detected */
-#define BITP_RSI_STAT0_SDIOINT                1                               /* SDIO Interrupt */
-#define BITM_RSI_STAT0_BUSYMODE              (_ADI_MSK(0x80000000,uint32_t))  /* Card is in Busy mode */
-#define BITM_RSI_STAT0_SLPMODE               (_ADI_MSK(0x40000000,uint32_t))  /* Card in Sleep Mode */
-#define BITM_RSI_STAT0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Card Ready */
-#define BITM_RSI_STAT0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Sleep Wakeup Timer Expired */
-#define BITM_RSI_STAT0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Card Entered Standby state */
-#define BITM_RSI_STAT0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Card Entered Sleep State */
-#define BITM_RSI_STAT0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Correct Boot Ack is received */
-#define BITM_RSI_STAT0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Boot Ack received is corrupted */
-#define BITM_RSI_STAT0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Boot Acknowledge Timeout */
-#define BITM_RSI_STAT0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Boot Data Timeout */
-#define BITM_RSI_STAT0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Boot Hold Time Expiry */
-#define BITM_RSI_STAT0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Boot Setup Time Expiry */
-#define BITM_RSI_STAT0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* CEATA Interrupt */
-#define BITM_RSI_STAT0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* SD Card Detected */
-#define BITM_RSI_STAT0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_IMSK0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_IMSK0_CARDRDY               17                               /* Mask Interrupt for Card Ready */
-#define BITP_RSI_IMSK0_SLPWKPTOUT            16                               /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITP_RSI_IMSK0_WKPDONE               15                               /* Mask Interrupt for Card Entered Standby state */
-#define BITP_RSI_IMSK0_SLPDONE               14                               /* Mask Interrupt for Card Entered Sleep State */
-#define BITP_RSI_IMSK0_BACKDONE              13                               /* Mask Interrupt for Correct Boot Ack is received */
-#define BITP_RSI_IMSK0_BACKBAD               12                               /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITP_RSI_IMSK0_BACKTO                11                               /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITP_RSI_IMSK0_BDATTO                10                               /* Mask Interrupt for Boot Data Timeout */
-#define BITP_RSI_IMSK0_BHOLDEXP               9                               /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITP_RSI_IMSK0_BSETUPEXP              8                               /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITP_RSI_IMSK0_CEATAINT               5                               /* Mask CEATA Interrupt */
-#define BITP_RSI_IMSK0_SDCARD                 4                               /* Mask Interrupt for SD Card Detected */
-#define BITP_RSI_IMSK0_SDIOINT                1                               /* Mask SDIO Interrupt */
-#define BITM_RSI_IMSK0_CARDRDY               (_ADI_MSK(0x00020000,uint32_t))  /* Mask Interrupt for Card Ready */
-#define BITM_RSI_IMSK0_SLPWKPTOUT            (_ADI_MSK(0x00010000,uint32_t))  /* Mask Interrupt for Sleep Wakeup Timer Expired */
-#define BITM_RSI_IMSK0_WKPDONE               (_ADI_MSK(0x00008000,uint32_t))  /* Mask Interrupt for Card Entered Standby state */
-#define BITM_RSI_IMSK0_SLPDONE               (_ADI_MSK(0x00004000,uint32_t))  /* Mask Interrupt for Card Entered Sleep State */
-#define BITM_RSI_IMSK0_BACKDONE              (_ADI_MSK(0x00002000,uint32_t))  /* Mask Interrupt for Correct Boot Ack is received */
-#define BITM_RSI_IMSK0_BACKBAD               (_ADI_MSK(0x00001000,uint32_t))  /* Mask Interrupt for Boot Ack received is corrupted */
-#define BITM_RSI_IMSK0_BACKTO                (_ADI_MSK(0x00000800,uint32_t))  /* Mask Interrupt for Boot Acknowledge Timeout */
-#define BITM_RSI_IMSK0_BDATTO                (_ADI_MSK(0x00000400,uint32_t))  /* Mask Interrupt for Boot Data Timeout */
-#define BITM_RSI_IMSK0_BHOLDEXP              (_ADI_MSK(0x00000200,uint32_t))  /* Mask Interrupt for Boot Hold Time Expiry */
-#define BITM_RSI_IMSK0_BSETUPEXP             (_ADI_MSK(0x00000100,uint32_t))  /* Mask Interrupt for Boot Setup Time Expiry */
-#define BITM_RSI_IMSK0_CEATAINT              (_ADI_MSK(0x00000020,uint32_t))  /* Mask CEATA Interrupt */
-#define BITM_RSI_IMSK0_SDCARD                (_ADI_MSK(0x00000010,uint32_t))  /* Mask Interrupt for SD Card Detected */
-#define BITM_RSI_IMSK0_SDIOINT               (_ADI_MSK(0x00000002,uint32_t))  /* Mask SDIO Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_CFG_BACKEN                  14                               /* Boot Acknowledge enabled */
-#define BITP_RSI_CFG_MMCBMODE                13                               /* MMC Boot Mode select */
-#define BITP_RSI_CFG_MMCBEN                  12                               /* MMC Boot Enabled */
-#define BITP_RSI_CFG_OPENDRAIN               11                               /* MC_CMD Output Control */
-#define BITP_RSI_CFG_PWRON                    9                               /* 11 - RSI Enabled */
-#define BITP_RSI_CFG_IEBYPDIS                 8                               /* Disabled IE Bypass */
-#define BITP_RSI_CFG_DAT3PUP                  6                               /* Pull-Up SD_DAT3 */
-#define BITP_RSI_CFG_DATPUP                   5                               /* Pull-Up SD_DAT */
-#define BITP_RSI_CFG_RST                      4                               /* SDMMC Reset */
-#define BITP_RSI_CFG_MWINEN                   3                               /* Moving Window Enable */
-#define BITP_RSI_CFG_SD4EN                    2                               /* SDIO 4-Bit Enable */
-#define BITP_RSI_CFG_CLKSEN                   0                               /* Clocks Enable */
-#define BITM_RSI_CFG_BACKEN                  (_ADI_MSK(0x00004000,uint16_t))  /* Boot Acknowledge enabled */
-#define BITM_RSI_CFG_MMCBMODE                (_ADI_MSK(0x00002000,uint16_t))  /* MMC Boot Mode select */
-#define BITM_RSI_CFG_MMCBEN                  (_ADI_MSK(0x00001000,uint16_t))  /* MMC Boot Enabled */
-#define BITM_RSI_CFG_OPENDRAIN               (_ADI_MSK(0x00000800,uint16_t))  /* MC_CMD Output Control */
-#define BITM_RSI_CFG_PWRON                   (_ADI_MSK(0x00000600,uint16_t))  /* 11 - RSI Enabled */
-#define BITM_RSI_CFG_IEBYPDIS                (_ADI_MSK(0x00000100,uint16_t))  /* Disabled IE Bypass */
-#define BITM_RSI_CFG_DAT3PUP                 (_ADI_MSK(0x00000040,uint16_t))  /* Pull-Up SD_DAT3 */
-#define BITM_RSI_CFG_DATPUP                  (_ADI_MSK(0x00000020,uint16_t))  /* Pull-Up SD_DAT */
-#define BITM_RSI_CFG_RST                     (_ADI_MSK(0x00000010,uint16_t))  /* SDMMC Reset */
-#define BITM_RSI_CFG_MWINEN                  (_ADI_MSK(0x00000008,uint16_t))  /* Moving Window Enable */
-#define BITM_RSI_CFG_SD4EN                   (_ADI_MSK(0x00000004,uint16_t))  /* SDIO 4-Bit Enable */
-#define BITM_RSI_CFG_CLKSEN                  (_ADI_MSK(0x00000001,uint16_t))  /* Clocks Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_RD_WAIT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_RD_WAIT_REQUEST              0                               /* Read Wait Request */
-#define BITM_RSI_RD_WAIT_REQUEST             (_ADI_MSK(0x00000001,uint16_t))  /* Read Wait Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID0                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID0_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID0_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID1_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID1_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID2_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID2_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RSI_PID3                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RSI_PID3_VALUE                   0                               /* Peripheral Identification */
-#define BITM_RSI_PID3_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Peripheral Identification */
-
-/* ==================================================
-        Controller Area Network Registers
-   ================================================== */
-
-/* =========================
-        CAN0
-   ========================= */
-#define REG_CAN0_MC1                    0xFFC00A00         /* CAN0 Mailbox Configuration 1 Register */
-#define REG_CAN0_MD1                    0xFFC00A04         /* CAN0 Mailbox Direction 1 Register */
-#define REG_CAN0_TRS1                   0xFFC00A08         /* CAN0 Transmission Request Set 1 Register */
-#define REG_CAN0_TRR1                   0xFFC00A0C         /* CAN0 Transmission Request Reset 1 Register */
-#define REG_CAN0_TA1                    0xFFC00A10         /* CAN0 Transmission Acknowledge 1 Register */
-#define REG_CAN0_AA1                    0xFFC00A14         /* CAN0 Abort Acknowledge 1 Register */
-#define REG_CAN0_RMP1                   0xFFC00A18         /* CAN0 Receive Message Pending 1 Register */
-#define REG_CAN0_RML1                   0xFFC00A1C         /* CAN0 Receive Message Lost 1 Register */
-#define REG_CAN0_MBTIF1                 0xFFC00A20         /* CAN0 Mailbox Transmit Interrupt Flag 1 Register */
-#define REG_CAN0_MBRIF1                 0xFFC00A24         /* CAN0 Mailbox Receive Interrupt Flag 1 Register */
-#define REG_CAN0_MBIM1                  0xFFC00A28         /* CAN0 Mailbox Interrupt Mask 1 Register */
-#define REG_CAN0_RFH1                   0xFFC00A2C         /* CAN0 Remote Frame Handling 1 Register */
-#define REG_CAN0_OPSS1                  0xFFC00A30         /* CAN0 Overwrite Protection/Single Shot Transmission 1 Register */
-#define REG_CAN0_MC2                    0xFFC00A40         /* CAN0 Mailbox Configuration 2 Register */
-#define REG_CAN0_MD2                    0xFFC00A44         /* CAN0 Mailbox Direction 2 Register */
-#define REG_CAN0_TRS2                   0xFFC00A48         /* CAN0 Transmission Request Set 2 Register */
-#define REG_CAN0_TRR2                   0xFFC00A4C         /* CAN0 Transmission Request Reset 2 Register */
-#define REG_CAN0_TA2                    0xFFC00A50         /* CAN0 Transmission Acknowledge 2 Register */
-#define REG_CAN0_AA2                    0xFFC00A54         /* CAN0 Abort Acknowledge 2 Register */
-#define REG_CAN0_RMP2                   0xFFC00A58         /* CAN0 Receive Message Pending 2 Register */
-#define REG_CAN0_RML2                   0xFFC00A5C         /* CAN0 Receive Message Lost 2 Register */
-#define REG_CAN0_MBTIF2                 0xFFC00A60         /* CAN0 Mailbox Transmit Interrupt Flag 2 Register */
-#define REG_CAN0_MBRIF2                 0xFFC00A64         /* CAN0 Mailbox Receive Interrupt Flag 2 Register */
-#define REG_CAN0_MBIM2                  0xFFC00A68         /* CAN0 Mailbox Interrupt Mask 2 Register */
-#define REG_CAN0_RFH2                   0xFFC00A6C         /* CAN0 Remote Frame Handling 2 Register */
-#define REG_CAN0_OPSS2                  0xFFC00A70         /* CAN0 Overwrite Protection/Single Shot Transmission 2 Register */
-#define REG_CAN0_CLK                    0xFFC00A80         /* CAN0 Clock Register */
-#define REG_CAN0_TIMING                 0xFFC00A84         /* CAN0 Timing Register */
-#define REG_CAN0_DBG                    0xFFC00A88         /* CAN0 Debug Register */
-#define REG_CAN0_STAT                   0xFFC00A8C         /* CAN0 Status Register */
-#define REG_CAN0_CEC                    0xFFC00A90         /* CAN0 Error Counter Register */
-#define REG_CAN0_GIS                    0xFFC00A94         /* CAN0 Global CAN Interrupt Status Register */
-#define REG_CAN0_GIM                    0xFFC00A98         /* CAN0 Global CAN Interrupt Mask Register */
-#define REG_CAN0_GIF                    0xFFC00A9C         /* CAN0 Global CAN Interrupt Flag Register */
-#define REG_CAN0_CTL                    0xFFC00AA0         /* CAN0 CAN Master Control Register */
-#define REG_CAN0_INT                    0xFFC00AA4         /* CAN0 Interrupt Pending Register */
-#define REG_CAN0_MBTD                   0xFFC00AAC         /* CAN0 Temporary Mailbox Disable Register */
-#define REG_CAN0_EWR                    0xFFC00AB0         /* CAN0 Error Counter Warning Level Register */
-#define REG_CAN0_ESR                    0xFFC00AB4         /* CAN0 Error Status Register */
-#define REG_CAN0_UCCNT                  0xFFC00AC4         /* CAN0 Universal Counter Register */
-#define REG_CAN0_UCRC                   0xFFC00AC8         /* CAN0 Universal Counter Reload/Capture Register */
-#define REG_CAN0_UCCNF                  0xFFC00ACC         /* CAN0 Universal Counter Configuration Mode Register */
-#define REG_CAN0_AM00L                  0xFFC00B00         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM01L                  0xFFC00B08         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM02L                  0xFFC00B10         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM03L                  0xFFC00B18         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM04L                  0xFFC00B20         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM05L                  0xFFC00B28         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM06L                  0xFFC00B30         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM07L                  0xFFC00B38         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM08L                  0xFFC00B40         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM09L                  0xFFC00B48         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM10L                  0xFFC00B50         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM11L                  0xFFC00B58         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM12L                  0xFFC00B60         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM13L                  0xFFC00B68         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM14L                  0xFFC00B70         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM15L                  0xFFC00B78         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM16L                  0xFFC00B80         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM17L                  0xFFC00B88         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM18L                  0xFFC00B90         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM19L                  0xFFC00B98         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM20L                  0xFFC00BA0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM21L                  0xFFC00BA8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM22L                  0xFFC00BB0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM23L                  0xFFC00BB8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM24L                  0xFFC00BC0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM25L                  0xFFC00BC8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM26L                  0xFFC00BD0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM27L                  0xFFC00BD8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM28L                  0xFFC00BE0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM29L                  0xFFC00BE8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM30L                  0xFFC00BF0         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM31L                  0xFFC00BF8         /* CAN0 Acceptance Mask (L) Register */
-#define REG_CAN0_AM00H                  0xFFC00B04         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM01H                  0xFFC00B0C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM02H                  0xFFC00B14         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM03H                  0xFFC00B1C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM04H                  0xFFC00B24         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM05H                  0xFFC00B2C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM06H                  0xFFC00B34         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM07H                  0xFFC00B3C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM08H                  0xFFC00B44         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM09H                  0xFFC00B4C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM10H                  0xFFC00B54         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM11H                  0xFFC00B5C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM12H                  0xFFC00B64         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM13H                  0xFFC00B6C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM14H                  0xFFC00B74         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM15H                  0xFFC00B7C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM16H                  0xFFC00B84         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM17H                  0xFFC00B8C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM18H                  0xFFC00B94         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM19H                  0xFFC00B9C         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM20H                  0xFFC00BA4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM21H                  0xFFC00BAC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM22H                  0xFFC00BB4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM23H                  0xFFC00BBC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM24H                  0xFFC00BC4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM25H                  0xFFC00BCC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM26H                  0xFFC00BD4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM27H                  0xFFC00BDC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM28H                  0xFFC00BE4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM29H                  0xFFC00BEC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM30H                  0xFFC00BF4         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_AM31H                  0xFFC00BFC         /* CAN0 Acceptance Mask (H) Register */
-#define REG_CAN0_MB00_DATA0             0xFFC00C00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB01_DATA0             0xFFC00C20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB02_DATA0             0xFFC00C40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB03_DATA0             0xFFC00C60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB04_DATA0             0xFFC00C80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB05_DATA0             0xFFC00CA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB06_DATA0             0xFFC00CC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB07_DATA0             0xFFC00CE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB08_DATA0             0xFFC00D00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB09_DATA0             0xFFC00D20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB10_DATA0             0xFFC00D40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB11_DATA0             0xFFC00D60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB12_DATA0             0xFFC00D80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB13_DATA0             0xFFC00DA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB14_DATA0             0xFFC00DC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB15_DATA0             0xFFC00DE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB16_DATA0             0xFFC00E00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB17_DATA0             0xFFC00E20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB18_DATA0             0xFFC00E40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB19_DATA0             0xFFC00E60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB20_DATA0             0xFFC00E80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB21_DATA0             0xFFC00EA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB22_DATA0             0xFFC00EC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB23_DATA0             0xFFC00EE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB24_DATA0             0xFFC00F00         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB25_DATA0             0xFFC00F20         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB26_DATA0             0xFFC00F40         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB27_DATA0             0xFFC00F60         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB28_DATA0             0xFFC00F80         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB29_DATA0             0xFFC00FA0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB30_DATA0             0xFFC00FC0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB31_DATA0             0xFFC00FE0         /* CAN0 Mailbox Word 0 Register */
-#define REG_CAN0_MB00_DATA1             0xFFC00C04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB01_DATA1             0xFFC00C24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB02_DATA1             0xFFC00C44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB03_DATA1             0xFFC00C64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB04_DATA1             0xFFC00C84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB05_DATA1             0xFFC00CA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB06_DATA1             0xFFC00CC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB07_DATA1             0xFFC00CE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB08_DATA1             0xFFC00D04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB09_DATA1             0xFFC00D24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB10_DATA1             0xFFC00D44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB11_DATA1             0xFFC00D64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB12_DATA1             0xFFC00D84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB13_DATA1             0xFFC00DA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB14_DATA1             0xFFC00DC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB15_DATA1             0xFFC00DE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB16_DATA1             0xFFC00E04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB17_DATA1             0xFFC00E24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB18_DATA1             0xFFC00E44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB19_DATA1             0xFFC00E64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB20_DATA1             0xFFC00E84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB21_DATA1             0xFFC00EA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB22_DATA1             0xFFC00EC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB23_DATA1             0xFFC00EE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB24_DATA1             0xFFC00F04         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB25_DATA1             0xFFC00F24         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB26_DATA1             0xFFC00F44         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB27_DATA1             0xFFC00F64         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB28_DATA1             0xFFC00F84         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB29_DATA1             0xFFC00FA4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB30_DATA1             0xFFC00FC4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB31_DATA1             0xFFC00FE4         /* CAN0 Mailbox Word 1 Register */
-#define REG_CAN0_MB00_DATA2             0xFFC00C08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB01_DATA2             0xFFC00C28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB02_DATA2             0xFFC00C48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB03_DATA2             0xFFC00C68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB04_DATA2             0xFFC00C88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB05_DATA2             0xFFC00CA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB06_DATA2             0xFFC00CC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB07_DATA2             0xFFC00CE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB08_DATA2             0xFFC00D08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB09_DATA2             0xFFC00D28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB10_DATA2             0xFFC00D48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB11_DATA2             0xFFC00D68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB12_DATA2             0xFFC00D88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB13_DATA2             0xFFC00DA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB14_DATA2             0xFFC00DC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB15_DATA2             0xFFC00DE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB16_DATA2             0xFFC00E08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB17_DATA2             0xFFC00E28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB18_DATA2             0xFFC00E48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB19_DATA2             0xFFC00E68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB20_DATA2             0xFFC00E88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB21_DATA2             0xFFC00EA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB22_DATA2             0xFFC00EC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB23_DATA2             0xFFC00EE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB24_DATA2             0xFFC00F08         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB25_DATA2             0xFFC00F28         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB26_DATA2             0xFFC00F48         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB27_DATA2             0xFFC00F68         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB28_DATA2             0xFFC00F88         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB29_DATA2             0xFFC00FA8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB30_DATA2             0xFFC00FC8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB31_DATA2             0xFFC00FE8         /* CAN0 Mailbox Word 2 Register */
-#define REG_CAN0_MB00_DATA3             0xFFC00C0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB01_DATA3             0xFFC00C2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB02_DATA3             0xFFC00C4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB03_DATA3             0xFFC00C6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB04_DATA3             0xFFC00C8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB05_DATA3             0xFFC00CAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB06_DATA3             0xFFC00CCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB07_DATA3             0xFFC00CEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB08_DATA3             0xFFC00D0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB09_DATA3             0xFFC00D2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB10_DATA3             0xFFC00D4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB11_DATA3             0xFFC00D6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB12_DATA3             0xFFC00D8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB13_DATA3             0xFFC00DAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB14_DATA3             0xFFC00DCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB15_DATA3             0xFFC00DEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB16_DATA3             0xFFC00E0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB17_DATA3             0xFFC00E2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB18_DATA3             0xFFC00E4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB19_DATA3             0xFFC00E6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB20_DATA3             0xFFC00E8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB21_DATA3             0xFFC00EAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB22_DATA3             0xFFC00ECC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB23_DATA3             0xFFC00EEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB24_DATA3             0xFFC00F0C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB25_DATA3             0xFFC00F2C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB26_DATA3             0xFFC00F4C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB27_DATA3             0xFFC00F6C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB28_DATA3             0xFFC00F8C         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB29_DATA3             0xFFC00FAC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB30_DATA3             0xFFC00FCC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB31_DATA3             0xFFC00FEC         /* CAN0 Mailbox Word 3 Register */
-#define REG_CAN0_MB00_LENGTH            0xFFC00C10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB01_LENGTH            0xFFC00C30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB02_LENGTH            0xFFC00C50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB03_LENGTH            0xFFC00C70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB04_LENGTH            0xFFC00C90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB05_LENGTH            0xFFC00CB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB06_LENGTH            0xFFC00CD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB07_LENGTH            0xFFC00CF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB08_LENGTH            0xFFC00D10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB09_LENGTH            0xFFC00D30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB10_LENGTH            0xFFC00D50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB11_LENGTH            0xFFC00D70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB12_LENGTH            0xFFC00D90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB13_LENGTH            0xFFC00DB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB14_LENGTH            0xFFC00DD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB15_LENGTH            0xFFC00DF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB16_LENGTH            0xFFC00E10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB17_LENGTH            0xFFC00E30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB18_LENGTH            0xFFC00E50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB19_LENGTH            0xFFC00E70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB20_LENGTH            0xFFC00E90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB21_LENGTH            0xFFC00EB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB22_LENGTH            0xFFC00ED0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB23_LENGTH            0xFFC00EF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB24_LENGTH            0xFFC00F10         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB25_LENGTH            0xFFC00F30         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB26_LENGTH            0xFFC00F50         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB27_LENGTH            0xFFC00F70         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB28_LENGTH            0xFFC00F90         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB29_LENGTH            0xFFC00FB0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB30_LENGTH            0xFFC00FD0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB31_LENGTH            0xFFC00FF0         /* CAN0 Mailbox Length Register */
-#define REG_CAN0_MB00_TIMESTAMP         0xFFC00C14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB01_TIMESTAMP         0xFFC00C34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB02_TIMESTAMP         0xFFC00C54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB03_TIMESTAMP         0xFFC00C74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB04_TIMESTAMP         0xFFC00C94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB05_TIMESTAMP         0xFFC00CB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB06_TIMESTAMP         0xFFC00CD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB07_TIMESTAMP         0xFFC00CF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB08_TIMESTAMP         0xFFC00D14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB09_TIMESTAMP         0xFFC00D34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB10_TIMESTAMP         0xFFC00D54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB11_TIMESTAMP         0xFFC00D74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB12_TIMESTAMP         0xFFC00D94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB13_TIMESTAMP         0xFFC00DB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB14_TIMESTAMP         0xFFC00DD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB15_TIMESTAMP         0xFFC00DF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB16_TIMESTAMP         0xFFC00E14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB17_TIMESTAMP         0xFFC00E34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB18_TIMESTAMP         0xFFC00E54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB19_TIMESTAMP         0xFFC00E74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB20_TIMESTAMP         0xFFC00E94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB21_TIMESTAMP         0xFFC00EB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB22_TIMESTAMP         0xFFC00ED4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB23_TIMESTAMP         0xFFC00EF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB24_TIMESTAMP         0xFFC00F14         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB25_TIMESTAMP         0xFFC00F34         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB26_TIMESTAMP         0xFFC00F54         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB27_TIMESTAMP         0xFFC00F74         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB28_TIMESTAMP         0xFFC00F94         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB29_TIMESTAMP         0xFFC00FB4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB30_TIMESTAMP         0xFFC00FD4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB31_TIMESTAMP         0xFFC00FF4         /* CAN0 Mailbox Timestamp Register */
-#define REG_CAN0_MB00_ID0               0xFFC00C18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB01_ID0               0xFFC00C38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB02_ID0               0xFFC00C58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB03_ID0               0xFFC00C78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB04_ID0               0xFFC00C98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB05_ID0               0xFFC00CB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB06_ID0               0xFFC00CD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB07_ID0               0xFFC00CF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB08_ID0               0xFFC00D18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB09_ID0               0xFFC00D38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB10_ID0               0xFFC00D58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB11_ID0               0xFFC00D78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB12_ID0               0xFFC00D98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB13_ID0               0xFFC00DB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB14_ID0               0xFFC00DD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB15_ID0               0xFFC00DF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB16_ID0               0xFFC00E18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB17_ID0               0xFFC00E38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB18_ID0               0xFFC00E58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB19_ID0               0xFFC00E78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB20_ID0               0xFFC00E98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB21_ID0               0xFFC00EB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB22_ID0               0xFFC00ED8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB23_ID0               0xFFC00EF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB24_ID0               0xFFC00F18         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB25_ID0               0xFFC00F38         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB26_ID0               0xFFC00F58         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB27_ID0               0xFFC00F78         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB28_ID0               0xFFC00F98         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB29_ID0               0xFFC00FB8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB30_ID0               0xFFC00FD8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB31_ID0               0xFFC00FF8         /* CAN0 Mailbox ID 0 Register */
-#define REG_CAN0_MB00_ID1               0xFFC00C1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB01_ID1               0xFFC00C3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB02_ID1               0xFFC00C5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB03_ID1               0xFFC00C7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB04_ID1               0xFFC00C9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB05_ID1               0xFFC00CBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB06_ID1               0xFFC00CDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB07_ID1               0xFFC00CFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB08_ID1               0xFFC00D1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB09_ID1               0xFFC00D3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB10_ID1               0xFFC00D5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB11_ID1               0xFFC00D7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB12_ID1               0xFFC00D9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB13_ID1               0xFFC00DBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB14_ID1               0xFFC00DDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB15_ID1               0xFFC00DFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB16_ID1               0xFFC00E1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB17_ID1               0xFFC00E3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB18_ID1               0xFFC00E5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB19_ID1               0xFFC00E7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB20_ID1               0xFFC00E9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB21_ID1               0xFFC00EBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB22_ID1               0xFFC00EDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB23_ID1               0xFFC00EFC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB24_ID1               0xFFC00F1C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB25_ID1               0xFFC00F3C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB26_ID1               0xFFC00F5C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB27_ID1               0xFFC00F7C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB28_ID1               0xFFC00F9C         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB29_ID1               0xFFC00FBC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB30_ID1               0xFFC00FDC         /* CAN0 Mailbox ID 1 Register */
-#define REG_CAN0_MB31_ID1               0xFFC00FFC         /* CAN0 Mailbox ID 1 Register */
-
-/* =========================
-        CAN
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC1_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC1_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD1_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD1_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS1_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS1_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR1_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR1_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA1_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA1_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA1_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA1_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA1_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP1_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP1_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML1_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML1_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF1_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF1_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF1                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF1_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF1_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF1_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM1_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM1_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH1_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH1_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH1_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS1_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS1_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS1_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MC2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MC2_MB00                     0                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB01                     1                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB02                     2                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB03                     3                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB04                     4                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB05                     5                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB06                     6                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB07                     7                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB08                     8                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB09                     9                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB10                    10                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB11                    11                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB12                    12                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB13                    13                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB14                    14                               /* Mailbox n Enable/Disable */
-#define BITP_CAN_MC2_MB15                    15                               /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Enable/Disable */
-#define BITM_CAN_MC2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Enable/Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MD2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MD2_MB00                     0                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB01                     1                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB02                     2                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB03                     3                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB04                     4                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB05                     5                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB06                     6                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB07                     7                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB08                     8                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB09                     9                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB10                    10                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB11                    11                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB12                    12                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB13                    13                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB14                    14                               /* Mailbox n Transmit/Receive */
-#define BITP_CAN_MD2_MB15                    15                               /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit/Receive */
-#define BITM_CAN_MD2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit/Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRS2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRS2_MB00                    0                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB01                    1                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB02                    2                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB03                    3                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB04                    4                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB05                    5                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB06                    6                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB07                    7                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB08                    8                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB09                    9                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB10                   10                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB11                   11                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB12                   12                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB13                   13                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB14                   14                               /* Mailbox n Transmit Request */
-#define BITP_CAN_TRS2_MB15                   15                               /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Request */
-#define BITM_CAN_TRS2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TRR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TRR2_MB00                    0                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB01                    1                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB02                    2                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB03                    3                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB04                    4                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB05                    5                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB06                    6                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB07                    7                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB08                    8                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB09                    9                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB10                   10                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB11                   11                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB12                   12                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB13                   13                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB14                   14                               /* Mailbox n Transmit Abort */
-#define BITP_CAN_TRR2_MB15                   15                               /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Abort */
-#define BITM_CAN_TRR2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Abort */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TA2_MB00                     0                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB01                     1                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB02                     2                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB03                     3                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB04                     4                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB05                     5                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB06                     6                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB07                     7                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB08                     8                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB09                     9                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB10                    10                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB11                    11                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB12                    12                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB13                    13                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB14                    14                               /* Mailbox n Transmit Acknowledge */
-#define BITP_CAN_TA2_MB15                    15                               /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-#define BITM_CAN_TA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AA2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AA2_MB00                     0                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB01                     1                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB02                     2                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB03                     3                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB04                     4                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB05                     5                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB06                     6                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB07                     7                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB08                     8                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB09                     9                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB10                    10                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB11                    11                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB12                    12                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB13                    13                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB14                    14                               /* Mailbox n Abort Acknowledge */
-#define BITP_CAN_AA2_MB15                    15                               /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB00                    (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB01                    (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB02                    (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB03                    (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB04                    (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB05                    (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB06                    (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB07                    (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB08                    (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB09                    (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB10                    (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB11                    (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB12                    (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB13                    (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB14                    (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Abort Acknowledge */
-#define BITM_CAN_AA2_MB15                    (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Abort Acknowledge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RMP2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RMP2_MB00                    0                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB01                    1                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB02                    2                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB03                    3                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB04                    4                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB05                    5                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB06                    6                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB07                    7                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB08                    8                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB09                    9                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB10                   10                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB11                   11                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB12                   12                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB13                   13                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB14                   14                               /* Mailbox n Message Pending */
-#define BITP_CAN_RMP2_MB15                   15                               /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Pending */
-#define BITM_CAN_RMP2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RML2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RML2_MB00                    0                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB01                    1                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB02                    2                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB03                    3                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB04                    4                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB05                    5                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB06                    6                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB07                    7                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB08                    8                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB09                    9                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB10                   10                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB11                   11                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB12                   12                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB13                   13                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB14                   14                               /* Mailbox n Message Lost */
-#define BITP_CAN_RML2_MB15                   15                               /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Message Lost */
-#define BITM_CAN_RML2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Message Lost */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTIF2_MB00                  0                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB01                  1                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB02                  2                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB03                  3                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB04                  4                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB05                  5                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB06                  6                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB07                  7                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB08                  8                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB09                  9                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB10                 10                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB11                 11                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB12                 12                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB13                 13                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB14                 14                               /* Mailbox n Transmit Interrupt Pending */
-#define BITP_CAN_MBTIF2_MB15                 15                               /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-#define BITM_CAN_MBTIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBRIF2                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBRIF2_MB00                  0                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB01                  1                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB02                  2                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB03                  3                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB04                  4                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB05                  5                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB06                  6                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB07                  7                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB08                  8                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB09                  9                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB10                 10                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB11                 11                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB12                 12                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB13                 13                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB14                 14                               /* Mailbox n Receive Interrupt Pending */
-#define BITP_CAN_MBRIF2_MB15                 15                               /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB00                 (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB01                 (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB02                 (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB03                 (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB04                 (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB05                 (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB06                 (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB07                 (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB08                 (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB09                 (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB10                 (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB11                 (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB12                 (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB13                 (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB14                 (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-#define BITM_CAN_MBRIF2_MB15                 (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Receive Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBIM2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBIM2_MB00                   0                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB01                   1                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB02                   2                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB03                   3                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB04                   4                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB05                   5                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB06                   6                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB07                   7                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB08                   8                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB09                   9                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB10                  10                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB11                  11                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB12                  12                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB13                  13                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB14                  14                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITP_CAN_MBIM2_MB15                  15                               /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-#define BITM_CAN_MBIM2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Transmit and Receive Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_RFH2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_RFH2_MB00                    0                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB01                    1                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB02                    2                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB03                    3                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB04                    4                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB05                    5                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB06                    6                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB07                    7                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB08                    8                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB09                    9                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB10                   10                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB11                   11                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB12                   12                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB13                   13                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB14                   14                               /* Mailbox n Remote Frame Handling Enable */
-#define BITP_CAN_RFH2_MB15                   15                               /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB00                   (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB01                   (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB02                   (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB03                   (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB04                   (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB05                   (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB06                   (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB07                   (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB08                   (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB09                   (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB10                   (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB11                   (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB12                   (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB13                   (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB14                   (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-#define BITM_CAN_RFH2_MB15                   (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Remote Frame Handling Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_OPSS2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_OPSS2_MB00                   0                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB01                   1                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB02                   2                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB03                   3                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB04                   4                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB05                   5                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB06                   6                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB07                   7                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB08                   8                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB09                   9                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB10                  10                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB11                  11                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB12                  12                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB13                  13                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB14                  14                               /* Mailbox n Overwrite Protection Enable */
-#define BITP_CAN_OPSS2_MB15                  15                               /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB00                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB01                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB02                  (_ADI_MSK(0x00000004,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB03                  (_ADI_MSK(0x00000008,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB04                  (_ADI_MSK(0x00000010,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB05                  (_ADI_MSK(0x00000020,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB06                  (_ADI_MSK(0x00000040,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB07                  (_ADI_MSK(0x00000080,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB08                  (_ADI_MSK(0x00000100,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB09                  (_ADI_MSK(0x00000200,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB10                  (_ADI_MSK(0x00000400,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB11                  (_ADI_MSK(0x00000800,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB12                  (_ADI_MSK(0x00001000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB13                  (_ADI_MSK(0x00002000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB14                  (_ADI_MSK(0x00004000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-#define BITM_CAN_OPSS2_MB15                  (_ADI_MSK(0x00008000,uint16_t))  /* Mailbox n Overwrite Protection Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CLK_BRP                      0                               /* Bit Rate Prescaler */
-#define BITM_CAN_CLK_BRP                     (_ADI_MSK(0x000003FF,uint16_t))  /* Bit Rate Prescaler */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_TIMING                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_TIMING_SJW                   8                               /* Synchronization Jump Width */
-#define BITP_CAN_TIMING_SAM                   7                               /* Sampling */
-#define BITP_CAN_TIMING_TSEG2                 4                               /* Time Segment 2 */
-#define BITP_CAN_TIMING_TSEG1                 0                               /* Time Segment 1 */
-#define BITM_CAN_TIMING_SJW                  (_ADI_MSK(0x00000300,uint16_t))  /* Synchronization Jump Width */
-#define BITM_CAN_TIMING_SAM                  (_ADI_MSK(0x00000080,uint16_t))  /* Sampling */
-#define BITM_CAN_TIMING_TSEG2                (_ADI_MSK(0x00000070,uint16_t))  /* Time Segment 2 */
-#define BITM_CAN_TIMING_TSEG1                (_ADI_MSK(0x0000000F,uint16_t))  /* Time Segment 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_DBG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_DBG_CDE                     15                               /* CAN Debug Mode Enable */
-#define BITP_CAN_DBG_MRB                      5                               /* Mode Read Back */
-#define BITP_CAN_DBG_MAA                      4                               /* Mode Auto Acknowledge */
-#define BITP_CAN_DBG_DIL                      3                               /* Disable Internal Loop */
-#define BITP_CAN_DBG_DTO                      2                               /* Disable Tx Output Pin */
-#define BITP_CAN_DBG_DRI                      1                               /* Disable Receive Input Pin */
-#define BITP_CAN_DBG_DEC                      0                               /* Disable Transmit and Receive Error Counters */
-#define BITM_CAN_DBG_CDE                     (_ADI_MSK(0x00008000,uint16_t))  /* CAN Debug Mode Enable */
-#define BITM_CAN_DBG_MRB                     (_ADI_MSK(0x00000020,uint16_t))  /* Mode Read Back */
-#define BITM_CAN_DBG_MAA                     (_ADI_MSK(0x00000010,uint16_t))  /* Mode Auto Acknowledge */
-#define BITM_CAN_DBG_DIL                     (_ADI_MSK(0x00000008,uint16_t))  /* Disable Internal Loop */
-#define BITM_CAN_DBG_DTO                     (_ADI_MSK(0x00000004,uint16_t))  /* Disable Tx Output Pin */
-#define BITM_CAN_DBG_DRI                     (_ADI_MSK(0x00000002,uint16_t))  /* Disable Receive Input Pin */
-#define BITM_CAN_DBG_DEC                     (_ADI_MSK(0x00000001,uint16_t))  /* Disable Transmit and Receive Error Counters */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_STAT_REC                    15                               /* Receive Mode */
-#define BITP_CAN_STAT_TRM                    14                               /* Transmit Mode */
-#define BITP_CAN_STAT_MBPTR                   8                               /* Mailbox Pointer */
-#define BITP_CAN_STAT_CCA                     7                               /* CAN Configuration Mode Acknowledge */
-#define BITP_CAN_STAT_CSA                     6                               /* CAN Suspend Mode Acknowledge */
-#define BITP_CAN_STAT_EBO                     3                               /* CAN Error Bus Off Mode */
-#define BITP_CAN_STAT_EP                      2                               /* CAN Error Passive Mode */
-#define BITP_CAN_STAT_WR                      1                               /* CAN Receive Warning Flag */
-#define BITP_CAN_STAT_WT                      0                               /* CAN Transmit Warning Flag */
-#define BITM_CAN_STAT_REC                    (_ADI_MSK(0x00008000,uint16_t))  /* Receive Mode */
-#define BITM_CAN_STAT_TRM                    (_ADI_MSK(0x00004000,uint16_t))  /* Transmit Mode */
-#define BITM_CAN_STAT_MBPTR                  (_ADI_MSK(0x00001F00,uint16_t))  /* Mailbox Pointer */
-#define BITM_CAN_STAT_CCA                    (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Acknowledge */
-#define BITM_CAN_STAT_CSA                    (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Acknowledge */
-#define BITM_CAN_STAT_EBO                    (_ADI_MSK(0x00000008,uint16_t))  /* CAN Error Bus Off Mode */
-#define BITM_CAN_STAT_EP                     (_ADI_MSK(0x00000004,uint16_t))  /* CAN Error Passive Mode */
-#define BITM_CAN_STAT_WR                     (_ADI_MSK(0x00000002,uint16_t))  /* CAN Receive Warning Flag */
-#define BITM_CAN_STAT_WT                     (_ADI_MSK(0x00000001,uint16_t))  /* CAN Transmit Warning Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CEC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CEC_TXECNT                   8                               /* Transmit Error Counter */
-#define BITP_CAN_CEC_RXECNT                   0                               /* Receive Error Counter */
-#define BITM_CAN_CEC_TXECNT                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Counter */
-#define BITM_CAN_CEC_RXECNT                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Counter */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIS                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIS_ADIS                    10                               /* Access Denied Interrupt Status */
-#define BITP_CAN_GIS_UCEIS                    8                               /* Universal Counter Exceeded Interrupt Status */
-#define BITP_CAN_GIS_RMLIS                    7                               /* Receive Message Lost Interrupt Status */
-#define BITP_CAN_GIS_AAIS                     6                               /* Abort Acknowledge Interrupt Status */
-#define BITP_CAN_GIS_UIAIS                    5                               /* Unimplemented Address Interrupt Status */
-#define BITP_CAN_GIS_WUIS                     4                               /* Wake Up Interrupt Status */
-#define BITP_CAN_GIS_BOIS                     3                               /* Bus Off Interrupt Status */
-#define BITP_CAN_GIS_EPIS                     2                               /* Error Passive Interrupt Status */
-#define BITP_CAN_GIS_EWRIS                    1                               /* Error Warning Receive  Interrupt Status */
-#define BITP_CAN_GIS_EWTIS                    0                               /* Error Warning Transmit Interrupt Status */
-#define BITM_CAN_GIS_ADIS                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Status */
-#define BITM_CAN_GIS_UCEIS                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Status */
-#define BITM_CAN_GIS_RMLIS                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Status */
-#define BITM_CAN_GIS_AAIS                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Status */
-#define BITM_CAN_GIS_UIAIS                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Status */
-#define BITM_CAN_GIS_WUIS                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Status */
-#define BITM_CAN_GIS_BOIS                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Status */
-#define BITM_CAN_GIS_EPIS                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Status */
-#define BITM_CAN_GIS_EWRIS                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive  Interrupt Status */
-#define BITM_CAN_GIS_EWTIS                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIM                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIM_ADIM                    10                               /* Access Denied Interrupt Mask */
-#define BITP_CAN_GIM_UCEIM                    8                               /* Universal Counter Exceeded Interrupt Mask */
-#define BITP_CAN_GIM_RMLIM                    7                               /* Receive Message Lost Interrupt Mask */
-#define BITP_CAN_GIM_AAIM                     6                               /* Abort Acknowledge Interrupt Mask */
-#define BITP_CAN_GIM_UIAIM                    5                               /* Unimplemented Address Interrupt Mask */
-#define BITP_CAN_GIM_WUIM                     4                               /* Wake Up Interrupt Mask */
-#define BITP_CAN_GIM_BOIM                     3                               /* Bus Off Interrupt Mask */
-#define BITP_CAN_GIM_EPIM                     2                               /* Error Passive Interrupt Mask */
-#define BITP_CAN_GIM_EWRIM                    1                               /* Error Warning Receive Interrupt Mask */
-#define BITP_CAN_GIM_EWTIM                    0                               /* Error Warning Transmit Interrupt Mask */
-#define BITM_CAN_GIM_ADIM                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Mask */
-#define BITM_CAN_GIM_UCEIM                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Mask */
-#define BITM_CAN_GIM_RMLIM                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Mask */
-#define BITM_CAN_GIM_AAIM                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Mask */
-#define BITM_CAN_GIM_UIAIM                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Mask */
-#define BITM_CAN_GIM_WUIM                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Mask */
-#define BITM_CAN_GIM_BOIM                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Mask */
-#define BITM_CAN_GIM_EPIM                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Mask */
-#define BITM_CAN_GIM_EWRIM                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Mask */
-#define BITM_CAN_GIM_EWTIM                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_GIF                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_GIF_ADIF                    10                               /* Access Denied Interrupt Flag */
-#define BITP_CAN_GIF_UCEIF                    8                               /* Universal Counter Exceeded Interrupt Flag */
-#define BITP_CAN_GIF_RMLIF                    7                               /* Receive Message Lost Interrupt Flag */
-#define BITP_CAN_GIF_AAIF                     6                               /* Abort Acknowledge Interrupt Flag */
-#define BITP_CAN_GIF_UIAIF                    5                               /* Unimplemented Address Interrupt Flag */
-#define BITP_CAN_GIF_WUIF                     4                               /* Wake Up Interrupt Flag */
-#define BITP_CAN_GIF_BOIF                     3                               /* Bus Off Interrupt Flag */
-#define BITP_CAN_GIF_EPIF                     2                               /* Error Passive Interrupt Flag */
-#define BITP_CAN_GIF_EWRIF                    1                               /* Error Warning Receive Interrupt Flag */
-#define BITP_CAN_GIF_EWTIF                    0                               /* Error Warning Transmit Interrupt Flag */
-#define BITM_CAN_GIF_ADIF                    (_ADI_MSK(0x00000400,uint16_t))  /* Access Denied Interrupt Flag */
-#define BITM_CAN_GIF_UCEIF                   (_ADI_MSK(0x00000100,uint16_t))  /* Universal Counter Exceeded Interrupt Flag */
-#define BITM_CAN_GIF_RMLIF                   (_ADI_MSK(0x00000080,uint16_t))  /* Receive Message Lost Interrupt Flag */
-#define BITM_CAN_GIF_AAIF                    (_ADI_MSK(0x00000040,uint16_t))  /* Abort Acknowledge Interrupt Flag */
-#define BITM_CAN_GIF_UIAIF                   (_ADI_MSK(0x00000020,uint16_t))  /* Unimplemented Address Interrupt Flag */
-#define BITM_CAN_GIF_WUIF                    (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up Interrupt Flag */
-#define BITM_CAN_GIF_BOIF                    (_ADI_MSK(0x00000008,uint16_t))  /* Bus Off Interrupt Flag */
-#define BITM_CAN_GIF_EPIF                    (_ADI_MSK(0x00000004,uint16_t))  /* Error Passive Interrupt Flag */
-#define BITM_CAN_GIF_EWRIF                   (_ADI_MSK(0x00000002,uint16_t))  /* Error Warning Receive Interrupt Flag */
-#define BITM_CAN_GIF_EWTIF                   (_ADI_MSK(0x00000001,uint16_t))  /* Error Warning Transmit Interrupt Flag */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_CTL_CCR                      7                               /* CAN Configuration Mode Request */
-#define BITP_CAN_CTL_CSR                      6                               /* CAN Suspend Mode Request */
-#define BITP_CAN_CTL_SMR                      5                               /* Sleep Mode Request */
-#define BITP_CAN_CTL_WBA                      4                               /* Wake Up on CAN Bus Activity */
-#define BITP_CAN_CTL_ABO                      2                               /* Auto Bus On */
-#define BITP_CAN_CTL_DNM                      1                               /* Device Net Mode */
-#define BITP_CAN_CTL_SRS                      0                               /* Software Reset */
-#define BITM_CAN_CTL_CCR                     (_ADI_MSK(0x00000080,uint16_t))  /* CAN Configuration Mode Request */
-#define BITM_CAN_CTL_CSR                     (_ADI_MSK(0x00000040,uint16_t))  /* CAN Suspend Mode Request */
-#define BITM_CAN_CTL_SMR                     (_ADI_MSK(0x00000020,uint16_t))  /* Sleep Mode Request */
-#define BITM_CAN_CTL_WBA                     (_ADI_MSK(0x00000010,uint16_t))  /* Wake Up on CAN Bus Activity */
-#define BITM_CAN_CTL_ABO                     (_ADI_MSK(0x00000004,uint16_t))  /* Auto Bus On */
-#define BITM_CAN_CTL_DNM                     (_ADI_MSK(0x00000002,uint16_t))  /* Device Net Mode */
-#define BITM_CAN_CTL_SRS                     (_ADI_MSK(0x00000001,uint16_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_INT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_INT_CANRX                    7                               /* Serial Input From Transceiver */
-#define BITP_CAN_INT_CANTX                    6                               /* Serial Input To Transceiver */
-#define BITP_CAN_INT_SMACK                    3                               /* Sleep Mode Acknowledge */
-#define BITP_CAN_INT_GIRQ                     2                               /* Global CAN Interrupt Output */
-#define BITP_CAN_INT_MBTIRQ                   1                               /* Mailbox Transmit Interrupt Output */
-#define BITP_CAN_INT_MBRIRQ                   0                               /* Mailbox Receive Interrupt Output */
-#define BITM_CAN_INT_CANRX                   (_ADI_MSK(0x00000080,uint16_t))  /* Serial Input From Transceiver */
-#define BITM_CAN_INT_CANTX                   (_ADI_MSK(0x00000040,uint16_t))  /* Serial Input To Transceiver */
-#define BITM_CAN_INT_SMACK                   (_ADI_MSK(0x00000008,uint16_t))  /* Sleep Mode Acknowledge */
-#define BITM_CAN_INT_GIRQ                    (_ADI_MSK(0x00000004,uint16_t))  /* Global CAN Interrupt Output */
-#define BITM_CAN_INT_MBTIRQ                  (_ADI_MSK(0x00000002,uint16_t))  /* Mailbox Transmit Interrupt Output */
-#define BITM_CAN_INT_MBRIRQ                  (_ADI_MSK(0x00000001,uint16_t))  /* Mailbox Receive Interrupt Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBTD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MBTD_TDR                     7                               /* Temporary Disable Request */
-#define BITP_CAN_MBTD_TDA                     6                               /* Temporary Disable Acknowledge */
-#define BITP_CAN_MBTD_TDPTR                   0                               /* Temporary Disable Pointer */
-#define BITM_CAN_MBTD_TDR                    (_ADI_MSK(0x00000080,uint16_t))  /* Temporary Disable Request */
-#define BITM_CAN_MBTD_TDA                    (_ADI_MSK(0x00000040,uint16_t))  /* Temporary Disable Acknowledge */
-#define BITM_CAN_MBTD_TDPTR                  (_ADI_MSK(0x0000001F,uint16_t))  /* Temporary Disable Pointer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_EWR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_EWR_EWLTEC                   8                               /* Transmit Error Warning Limit */
-#define BITP_CAN_EWR_EWLREC                   0                               /* Receive Error Warning Limit */
-#define BITM_CAN_EWR_EWLTEC                  (_ADI_MSK(0x0000FF00,uint16_t))  /* Transmit Error Warning Limit */
-#define BITM_CAN_EWR_EWLREC                  (_ADI_MSK(0x000000FF,uint16_t))  /* Receive Error Warning Limit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_ESR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_ESR_FER                      7                               /* Form Error */
-#define BITP_CAN_ESR_BEF                      6                               /* Bit Error Flag */
-#define BITP_CAN_ESR_SAO                      5                               /* Stuck at Dominant */
-#define BITP_CAN_ESR_CRCE                     4                               /* CRC Error */
-#define BITP_CAN_ESR_SER                      3                               /* Stuff Bit Error */
-#define BITP_CAN_ESR_ACKE                     2                               /* Acknowledge Error */
-#define BITM_CAN_ESR_FER                     (_ADI_MSK(0x00000080,uint16_t))  /* Form Error */
-#define BITM_CAN_ESR_BEF                     (_ADI_MSK(0x00000040,uint16_t))  /* Bit Error Flag */
-#define BITM_CAN_ESR_SAO                     (_ADI_MSK(0x00000020,uint16_t))  /* Stuck at Dominant */
-#define BITM_CAN_ESR_CRCE                    (_ADI_MSK(0x00000010,uint16_t))  /* CRC Error */
-#define BITM_CAN_ESR_SER                     (_ADI_MSK(0x00000008,uint16_t))  /* Stuff Bit Error */
-#define BITM_CAN_ESR_ACKE                    (_ADI_MSK(0x00000004,uint16_t))  /* Acknowledge Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_UCCNF                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_UCCNF_UCE                    7                               /* Universal Counter Enable */
-#define BITP_CAN_UCCNF_UCCT                   6                               /* Universal Counter CAN Trigger */
-#define BITP_CAN_UCCNF_UCRC                   5                               /* Universal Counter Reload/Clear */
-#define BITP_CAN_UCCNF_UCCNF                  0                               /* Universal Counter Configuration */
-#define BITM_CAN_UCCNF_UCE                   (_ADI_MSK(0x00000080,uint16_t))  /* Universal Counter Enable */
-#define BITM_CAN_UCCNF_UCCT                  (_ADI_MSK(0x00000040,uint16_t))  /* Universal Counter CAN Trigger */
-#define BITM_CAN_UCCNF_UCRC                  (_ADI_MSK(0x00000020,uint16_t))  /* Universal Counter Reload/Clear */
-#define BITM_CAN_UCCNF_UCCNF                 (_ADI_MSK(0x0000000F,uint16_t))  /* Universal Counter Configuration */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_AMnH                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_AMH_FDF                     15                               /* Filter on Delay Field */
-#define BITP_CAN_AMH_FMD                     14                               /* Full Mask Data */
-#define BITP_CAN_AMH_AMIDE                   13                               /* Acceptance Mask Identifier Extension */
-#define BITP_CAN_AMH_BASEID                   2                               /* Base Identifier */
-#define BITP_CAN_AMH_EXTID                    0                               /* Extended Identifier */
-#define BITM_CAN_AMH_FDF                     (_ADI_MSK(0x00008000,uint16_t))  /* Filter on Delay Field */
-#define BITM_CAN_AMH_FMD                     (_ADI_MSK(0x00004000,uint16_t))  /* Full Mask Data */
-#define BITM_CAN_AMH_AMIDE                   (_ADI_MSK(0x00002000,uint16_t))  /* Acceptance Mask Identifier Extension */
-#define BITM_CAN_AMH_BASEID                  (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_AMH_EXTID                   (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA0_DFB6                8                               /* Data Field Byte 6 */
-#define BITP_CAN_MB_DATA0_DFB7                0                               /* Data Field Byte 7 */
-#define BITM_CAN_MB_DATA0_DFB6               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 6 */
-#define BITM_CAN_MB_DATA0_DFB7               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 7 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA1_DFB4                8                               /* Data Field Byte 4 */
-#define BITP_CAN_MB_DATA1_DFB5                0                               /* Data Field Byte 5 */
-#define BITM_CAN_MB_DATA1_DFB4               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 4 */
-#define BITM_CAN_MB_DATA1_DFB5               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 5 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA2                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA2_DFB2                8                               /* Data Field Byte 2 */
-#define BITP_CAN_MB_DATA2_DFB3                0                               /* Data Field Byte 3 */
-#define BITM_CAN_MB_DATA2_DFB2               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 2 */
-#define BITM_CAN_MB_DATA2_DFB3               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 3 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_DATA3                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_DATA3_DFB0                8                               /* Data Field Byte 0 */
-#define BITP_CAN_MB_DATA3_DFB1                0                               /* Data Field Byte 1 */
-#define BITM_CAN_MB_DATA3_DFB0               (_ADI_MSK(0x0000FF00,uint16_t))  /* Data Field Byte 0 */
-#define BITM_CAN_MB_DATA3_DFB1               (_ADI_MSK(0x000000FF,uint16_t))  /* Data Field Byte 1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_LENGTH                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_LENGTH_DLC                0                               /* Data Length Code */
-#define BITM_CAN_MB_LENGTH_DLC               (_ADI_MSK(0x0000000F,uint16_t))  /* Data Length Code */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CAN_MBn_ID1                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CAN_MB_ID1_AME                  15                               /* Acceptance Mask Enable */
-#define BITP_CAN_MB_ID1_RTR                  14                               /* Remote Transmission Request */
-#define BITP_CAN_MB_ID1_IDE                  13                               /* Identifier Extension */
-#define BITP_CAN_MB_ID1_BASEID                2                               /* Base Identifier */
-#define BITP_CAN_MB_ID1_EXTID                 0                               /* Extended Identifier */
-#define BITM_CAN_MB_ID1_AME                  (_ADI_MSK(0x00008000,uint16_t))  /* Acceptance Mask Enable */
-#define BITM_CAN_MB_ID1_RTR                  (_ADI_MSK(0x00004000,uint16_t))  /* Remote Transmission Request */
-#define BITM_CAN_MB_ID1_IDE                  (_ADI_MSK(0x00002000,uint16_t))  /* Identifier Extension */
-#define BITM_CAN_MB_ID1_BASEID               (_ADI_MSK(0x00001FFC,uint16_t))  /* Base Identifier */
-#define BITM_CAN_MB_ID1_EXTID                (_ADI_MSK(0x00000003,uint16_t))  /* Extended Identifier */
-
-/* ==================================================
-        Link Port Registers
-   ================================================== */
-
-/* =========================
-        LP0
-   ========================= */
-#define REG_LP0_CTL                     0xFFC01000         /* LP0 Control Register */
-#define REG_LP0_STAT                    0xFFC01004         /* LP0 Status Register */
-#define REG_LP0_DIV                     0xFFC01008         /* LP0 Clock Divider Value */
-#define REG_LP0_TX                      0xFFC01010         /* LP0 Transmit Buffer */
-#define REG_LP0_RX                      0xFFC01014         /* LP0 Receive Buffer */
-#define REG_LP0_TXIN_SHDW               0xFFC01018         /* LP0 Shadow Input Transmit Buffer */
-#define REG_LP0_TXOUT_SHDW              0xFFC0101C         /* LP0 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP1
-   ========================= */
-#define REG_LP1_CTL                     0xFFC01100         /* LP1 Control Register */
-#define REG_LP1_STAT                    0xFFC01104         /* LP1 Status Register */
-#define REG_LP1_DIV                     0xFFC01108         /* LP1 Clock Divider Value */
-#define REG_LP1_TX                      0xFFC01110         /* LP1 Transmit Buffer */
-#define REG_LP1_RX                      0xFFC01114         /* LP1 Receive Buffer */
-#define REG_LP1_TXIN_SHDW               0xFFC01118         /* LP1 Shadow Input Transmit Buffer */
-#define REG_LP1_TXOUT_SHDW              0xFFC0111C         /* LP1 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP2
-   ========================= */
-#define REG_LP2_CTL                     0xFFC01200         /* LP2 Control Register */
-#define REG_LP2_STAT                    0xFFC01204         /* LP2 Status Register */
-#define REG_LP2_DIV                     0xFFC01208         /* LP2 Clock Divider Value */
-#define REG_LP2_TX                      0xFFC01210         /* LP2 Transmit Buffer */
-#define REG_LP2_RX                      0xFFC01214         /* LP2 Receive Buffer */
-#define REG_LP2_TXIN_SHDW               0xFFC01218         /* LP2 Shadow Input Transmit Buffer */
-#define REG_LP2_TXOUT_SHDW              0xFFC0121C         /* LP2 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP3
-   ========================= */
-#define REG_LP3_CTL                     0xFFC01300         /* LP3 Control Register */
-#define REG_LP3_STAT                    0xFFC01304         /* LP3 Status Register */
-#define REG_LP3_DIV                     0xFFC01308         /* LP3 Clock Divider Value */
-#define REG_LP3_TX                      0xFFC01310         /* LP3 Transmit Buffer */
-#define REG_LP3_RX                      0xFFC01314         /* LP3 Receive Buffer */
-#define REG_LP3_TXIN_SHDW               0xFFC01318         /* LP3 Shadow Input Transmit Buffer */
-#define REG_LP3_TXOUT_SHDW              0xFFC0131C         /* LP3 Shadow Output Transmit Buffer */
-
-/* =========================
-        LP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_CTL                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_CTL_ITMSK                    11                               /* Receive FIFO Overflow Interrupt Mask */
-#define BITP_LP_CTL_RRQMSK                    9                               /* Receive Request Interrupt Mask */
-#define BITP_LP_CTL_TRQMSK                    8                               /* Transmit Request Interrupt Mask */
-#define BITP_LP_CTL_TRAN                      3                               /* Transfer Direction */
-#define BITP_LP_CTL_EN                        0                               /* Enable */
-
-#define BITM_LP_CTL_ITMSK                    (_ADI_MSK(0x00000800,uint32_t))  /* Receive FIFO Overflow Interrupt Mask */
-#define ENUM_LP_CTL_RX_OVF_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* ITMSK: Mask */
-#define ENUM_LP_CTL_RX_OVF_EN                (_ADI_MSK(0x00000800,uint32_t))  /* ITMSK: Unmask */
-
-#define BITM_LP_CTL_RRQMSK                   (_ADI_MSK(0x00000200,uint32_t))  /* Receive Request Interrupt Mask */
-#define ENUM_LP_CTL_RRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* RRQMSK: Mask */
-#define ENUM_LP_CTL_RRQ_EN                   (_ADI_MSK(0x00000200,uint32_t))  /* RRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRQMSK                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Request Interrupt Mask */
-#define ENUM_LP_CTL_TRQ_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* TRQMSK: Mask */
-#define ENUM_LP_CTL_TRQ_EN                   (_ADI_MSK(0x00000100,uint32_t))  /* TRQMSK: Unmask */
-
-#define BITM_LP_CTL_TRAN                     (_ADI_MSK(0x00000008,uint32_t))  /* Transfer Direction */
-#define ENUM_LP_CTL_RX                       (_ADI_MSK(0x00000000,uint32_t))  /* TRAN: Receive */
-#define ENUM_LP_CTL_TX                       (_ADI_MSK(0x00000008,uint32_t))  /* TRAN: Transmit */
-
-#define BITM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_LP_CTL_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_LP_CTL_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable   linkport */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_STAT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_STAT_LPBS                     8                               /* Bus Status */
-#define BITP_LP_STAT_LERR                     7                               /* Buffer Pack Error Status */
-#define BITP_LP_STAT_FFST                     4                               /* FIFO Status */
-#define BITP_LP_STAT_LPIT                     3                               /* Receive FIFO Overflow Interrupt */
-#define BITP_LP_STAT_LRRQ                     1                               /* Receive Request */
-#define BITP_LP_STAT_LTRQ                     0                               /* Transmit Request */
-
-#define BITM_LP_STAT_LPBS                    (_ADI_MSK(0x00000100,uint32_t))  /* Bus Status */
-#define ENUM_LP_STAT_IDLE                    (_ADI_MSK(0x00000000,uint32_t))  /* LPBS: Bus is Idle */
-#define ENUM_LP_STAT_BUSY                    (_ADI_MSK(0x00000100,uint32_t))  /* LPBS: Bus Busy */
-
-#define BITM_LP_STAT_LERR                    (_ADI_MSK(0x00000080,uint32_t))  /* Buffer Pack Error Status */
-#define ENUM_LP_STAT_PACK_DONE               (_ADI_MSK(0x00000000,uint32_t))  /* LERR: Packing Complete */
-#define ENUM_LP_STAT_PACK_PROG               (_ADI_MSK(0x00000080,uint32_t))  /* LERR: Packing Incomplete */
-
-#define BITM_LP_STAT_FFST                    (_ADI_MSK(0x00000070,uint32_t))  /* FIFO Status */
-#define ENUM_LP_STAT_RX0_TX0                 (_ADI_MSK(0x00000000,uint32_t))  /* FFST: TX - Empty; RX -Empty */
-#define ENUM_LP_STAT_RX1_TXR                 (_ADI_MSK(0x00000010,uint32_t))  /* FFST: TX - reserved ; RX - One Word */
-#define ENUM_LP_STAT_RX2_TXR                 (_ADI_MSK(0x00000020,uint32_t))  /* FFST: TX - reserved; RX - Two Word */
-#define ENUM_LP_STAT_RX3_TXR                 (_ADI_MSK(0x00000030,uint32_t))  /* FFST: TX - reserved; RX - Three Word */
-#define ENUM_LP_STAT_RX4_TX1                 (_ADI_MSK(0x00000040,uint32_t))  /* FFST: TX - One Word; RX - Four word */
-#define ENUM_LP_STAT_RXR1_TXR1               (_ADI_MSK(0x00000050,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define ENUM_LP_STAT_RXR2_TXR2               (_ADI_MSK(0x00000060,uint32_t))  /* FFST: TX - FIFO Full; RX - Reserved */
-#define ENUM_LP_STAT_RXR3_TXR3               (_ADI_MSK(0x00000070,uint32_t))  /* FFST: TX - Reserved; RX - Reserved */
-#define BITM_LP_STAT_LPIT                    (_ADI_MSK(0x00000008,uint32_t))  /* Receive FIFO Overflow Interrupt */
-#define BITM_LP_STAT_LRRQ                    (_ADI_MSK(0x00000002,uint32_t))  /* Receive Request */
-#define BITM_LP_STAT_LTRQ                    (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        LP_DIV                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_LP_DIV_VALUE                     0                               /* Divisor Value */
-#define BITM_LP_DIV_VALUE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Divisor Value */
-
-/* ==================================================
-        General Purpose Timer Block Registers
-   ================================================== */
-
-/* =========================
-        TIMER0
-   ========================= */
-#define REG_TIMER0_REVID                0xFFC01400         /* TIMER0 Revision ID Register */
-#define REG_TIMER0_RUN                  0xFFC01404         /* TIMER0 Run Register */
-#define REG_TIMER0_RUN_SET              0xFFC01408         /* TIMER0 Run Set Register */
-#define REG_TIMER0_RUN_CLR              0xFFC0140C         /* TIMER0 Run Clear Register */
-#define REG_TIMER0_STOP_CFG             0xFFC01410         /* TIMER0 Stop Configuration Register */
-#define REG_TIMER0_STOP_CFG_SET         0xFFC01414         /* TIMER0 Stop Configuration Set Register */
-#define REG_TIMER0_STOP_CFG_CLR         0xFFC01418         /* TIMER0 Stop Configuration Clear Register */
-#define REG_TIMER0_DATA_IMSK            0xFFC0141C         /* TIMER0 Data Interrupt Mask Register */
-#define REG_TIMER0_STAT_IMSK            0xFFC01420         /* TIMER0 Status Interrupt Mask Register */
-#define REG_TIMER0_TRG_MSK              0xFFC01424         /* TIMER0 Trigger Master Mask Register */
-#define REG_TIMER0_TRG_IE               0xFFC01428         /* TIMER0 Trigger Slave Enable Register */
-#define REG_TIMER0_DATA_ILAT            0xFFC0142C         /* TIMER0 Data Interrupt Latch Register */
-#define REG_TIMER0_STAT_ILAT            0xFFC01430         /* TIMER0 Status Interrupt Latch Register */
-#define REG_TIMER0_ERR_TYPE             0xFFC01434         /* TIMER0 Error Type Status Register */
-#define REG_TIMER0_BCAST_PER            0xFFC01438         /* TIMER0 Broadcast Period Register */
-#define REG_TIMER0_BCAST_WID            0xFFC0143C         /* TIMER0 Broadcast Width Register */
-#define REG_TIMER0_BCAST_DLY            0xFFC01440         /* TIMER0 Broadcast Delay Register */
-#define REG_TIMER0_TMR0_CFG             0xFFC01460         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR1_CFG             0xFFC01480         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR2_CFG             0xFFC014A0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR3_CFG             0xFFC014C0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR4_CFG             0xFFC014E0         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR5_CFG             0xFFC01500         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR6_CFG             0xFFC01520         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR7_CFG             0xFFC01540         /* TIMER0 Timer n Configuration Register */
-#define REG_TIMER0_TMR0_CNT             0xFFC01464         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR1_CNT             0xFFC01484         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR2_CNT             0xFFC014A4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR3_CNT             0xFFC014C4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR4_CNT             0xFFC014E4         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR5_CNT             0xFFC01504         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR6_CNT             0xFFC01524         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR7_CNT             0xFFC01544         /* TIMER0 Timer n Counter Register */
-#define REG_TIMER0_TMR0_PER             0xFFC01468         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR1_PER             0xFFC01488         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR2_PER             0xFFC014A8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR3_PER             0xFFC014C8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR4_PER             0xFFC014E8         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR5_PER             0xFFC01508         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR6_PER             0xFFC01528         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR7_PER             0xFFC01548         /* TIMER0 Timer n Period Register */
-#define REG_TIMER0_TMR0_WID             0xFFC0146C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR1_WID             0xFFC0148C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR2_WID             0xFFC014AC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR3_WID             0xFFC014CC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR4_WID             0xFFC014EC         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR5_WID             0xFFC0150C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR6_WID             0xFFC0152C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR7_WID             0xFFC0154C         /* TIMER0 Timer n Width Register */
-#define REG_TIMER0_TMR0_DLY             0xFFC01470         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR1_DLY             0xFFC01490         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR2_DLY             0xFFC014B0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR3_DLY             0xFFC014D0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR4_DLY             0xFFC014F0         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR5_DLY             0xFFC01510         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR6_DLY             0xFFC01530         /* TIMER0 Timer n Delay Register */
-#define REG_TIMER0_TMR7_DLY             0xFFC01550         /* TIMER0 Timer n Delay Register */
-
-/* =========================
-        TIMER
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_REVID                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_REVID_MAJOR                4                               /* Major Revision ID */
-#define BITP_TIMER_REVID_REV                  0                               /* Incremental Revision ID */
-#define BITM_TIMER_REVID_MAJOR               (_ADI_MSK(0x000000F0,uint16_t))  /* Major Revision ID */
-#define BITM_TIMER_REVID_REV                 (_ADI_MSK(0x0000000F,uint16_t))  /* Incremental Revision ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_TMR00                  0                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR01                  1                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR02                  2                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR03                  3                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR04                  4                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR05                  5                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR06                  6                               /* Start/Stop Timer n */
-#define BITP_TIMER_RUN_TMR07                  7                               /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR00                 (_ADI_MSK(0x00000001,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR01                 (_ADI_MSK(0x00000002,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR02                 (_ADI_MSK(0x00000004,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR03                 (_ADI_MSK(0x00000008,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR04                 (_ADI_MSK(0x00000010,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR05                 (_ADI_MSK(0x00000020,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR06                 (_ADI_MSK(0x00000040,uint16_t))  /* Start/Stop Timer n */
-#define BITM_TIMER_RUN_TMR07                 (_ADI_MSK(0x00000080,uint16_t))  /* Start/Stop Timer n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_SET_TMR00              0                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR01              1                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR02              2                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR03              3                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR04              4                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR05              5                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR06              6                               /* RUN Set Alias */
-#define BITP_TIMER_RUN_SET_TMR07              7                               /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Set Alias */
-#define BITM_TIMER_RUN_SET_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_RUN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_RUN_CLR_TMR00              0                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR01              1                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR02              2                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR03              3                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR04              4                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR05              5                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR06              6                               /* RUN Clear Alias */
-#define BITP_TIMER_RUN_CLR_TMR07              7                               /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* RUN Clear Alias */
-#define BITM_TIMER_RUN_CLR_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* RUN Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_TMR00             0                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR01             1                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR02             2                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR03             3                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR04             4                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR05             5                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR06             6                               /* Stop Mode Select */
-#define BITP_TIMER_STOP_CFG_TMR07             7                               /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR00            (_ADI_MSK(0x00000001,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR01            (_ADI_MSK(0x00000002,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR02            (_ADI_MSK(0x00000004,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR03            (_ADI_MSK(0x00000008,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR04            (_ADI_MSK(0x00000010,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR05            (_ADI_MSK(0x00000020,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR06            (_ADI_MSK(0x00000040,uint16_t))  /* Stop Mode Select */
-#define BITM_TIMER_STOP_CFG_TMR07            (_ADI_MSK(0x00000080,uint16_t))  /* Stop Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_SET                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_SET_TMR00         0                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR01         1                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR02         2                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR03         3                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR04         4                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR05         5                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR06         6                               /* STOP_CFG Set Alias */
-#define BITP_TIMER_STOP_CFG_SET_TMR07         7                               /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Set Alias */
-#define BITM_TIMER_STOP_CFG_SET_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Set Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STOP_CFG_CLR                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STOP_CFG_CLR_TMR00         0                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR01         1                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR02         2                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR03         3                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR04         4                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR05         5                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR06         6                               /* STOP_CFG Clear Alias */
-#define BITP_TIMER_STOP_CFG_CLR_TMR07         7                               /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR00        (_ADI_MSK(0x00000001,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR01        (_ADI_MSK(0x00000002,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR02        (_ADI_MSK(0x00000004,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR03        (_ADI_MSK(0x00000008,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR04        (_ADI_MSK(0x00000010,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR05        (_ADI_MSK(0x00000020,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR06        (_ADI_MSK(0x00000040,uint16_t))  /* STOP_CFG Clear Alias */
-#define BITM_TIMER_STOP_CFG_CLR_TMR07        (_ADI_MSK(0x00000080,uint16_t))  /* STOP_CFG Clear Alias */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_IMSK_TMR00            0                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR01            1                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR02            2                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR03            3                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR04            4                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR05            5                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR06            6                               /* Data Interrupt Mask */
-#define BITP_TIMER_DATA_IMSK_TMR07            7                               /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Mask */
-#define BITM_TIMER_DATA_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_IMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_IMSK_TMR00            0                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR01            1                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR02            2                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR03            3                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR04            4                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR05            5                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR06            6                               /* Status Interrupt Mask */
-#define BITP_TIMER_STAT_IMSK_TMR07            7                               /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Mask */
-#define BITM_TIMER_STAT_IMSK_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_MSK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_MSK_TMR00              0                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR01              1                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR02              2                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR03              3                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR04              4                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR05              5                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR06              6                               /* Trigger Output Mask */
-#define BITP_TIMER_TRG_MSK_TMR07              7                               /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR00             (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR01             (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR02             (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR03             (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR04             (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR05             (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR06             (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Output Mask */
-#define BITM_TIMER_TRG_MSK_TMR07             (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Output Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TRG_IE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TRG_IE_TMR00               0                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR01               1                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR02               2                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR03               3                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR04               4                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR05               5                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR06               6                               /* Trigger Input Enable */
-#define BITP_TIMER_TRG_IE_TMR07               7                               /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR00              (_ADI_MSK(0x00000001,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR01              (_ADI_MSK(0x00000002,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR02              (_ADI_MSK(0x00000004,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR03              (_ADI_MSK(0x00000008,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR04              (_ADI_MSK(0x00000010,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR05              (_ADI_MSK(0x00000020,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR06              (_ADI_MSK(0x00000040,uint16_t))  /* Trigger Input Enable */
-#define BITM_TIMER_TRG_IE_TMR07              (_ADI_MSK(0x00000080,uint16_t))  /* Trigger Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_DATA_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_DATA_ILAT_TMR00            0                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR01            1                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR02            2                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR03            3                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR04            4                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR05            5                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR06            6                               /* Data Interrupt Latch */
-#define BITP_TIMER_DATA_ILAT_TMR07            7                               /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Data Interrupt Latch */
-#define BITM_TIMER_DATA_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Data Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_STAT_ILAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_STAT_ILAT_TMR00            0                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR01            1                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR02            2                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR03            3                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR04            4                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR05            5                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR06            6                               /* Status Interrupt Latch */
-#define BITP_TIMER_STAT_ILAT_TMR07            7                               /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR00           (_ADI_MSK(0x00000001,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR01           (_ADI_MSK(0x00000002,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR02           (_ADI_MSK(0x00000004,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR03           (_ADI_MSK(0x00000008,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR04           (_ADI_MSK(0x00000010,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR05           (_ADI_MSK(0x00000020,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR06           (_ADI_MSK(0x00000040,uint16_t))  /* Status Interrupt Latch */
-#define BITM_TIMER_STAT_ILAT_TMR07           (_ADI_MSK(0x00000080,uint16_t))  /* Status Interrupt Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_ERR_TYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_ERR_TYPE_TERR7            14                               /* Error type for Timer 7 */
-#define BITP_TIMER_ERR_TYPE_TERR6            12                               /* Error type for Timer 6 */
-#define BITP_TIMER_ERR_TYPE_TERR5            10                               /* Error type for Timer 5 */
-#define BITP_TIMER_ERR_TYPE_TERR4             8                               /* Error type for Timer 4 */
-#define BITP_TIMER_ERR_TYPE_TERR3             6                               /* Error type for Timer 3 */
-#define BITP_TIMER_ERR_TYPE_TERR2             4                               /* Error type for Timer 2 */
-#define BITP_TIMER_ERR_TYPE_TERR1             2                               /* Error type for Timer 1 */
-#define BITP_TIMER_ERR_TYPE_TERR0             0                               /* Error type for Timer 0 */
-
-#define BITM_TIMER_ERR_TYPE_TERR7            (_ADI_MSK(0x0000C000,uint32_t))  /* Error type for Timer 7 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR7          (_ADI_MSK(0x00000000,uint32_t))  /* TERR7: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF7          (_ADI_MSK(0x00004000,uint32_t))  /* TERR7: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG7          (_ADI_MSK(0x00008000,uint32_t))  /* TERR7: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG7        (_ADI_MSK(0x0000C000,uint32_t))  /* TERR7: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR6            (_ADI_MSK(0x00003000,uint32_t))  /* Error type for Timer 6 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR6          (_ADI_MSK(0x00000000,uint32_t))  /* TERR6: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF6          (_ADI_MSK(0x00001000,uint32_t))  /* TERR6: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG6          (_ADI_MSK(0x00002000,uint32_t))  /* TERR6: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG6        (_ADI_MSK(0x00003000,uint32_t))  /* TERR6: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR5            (_ADI_MSK(0x00000C00,uint32_t))  /* Error type for Timer 5 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR5          (_ADI_MSK(0x00000000,uint32_t))  /* TERR5: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF5          (_ADI_MSK(0x00000400,uint32_t))  /* TERR5: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG5          (_ADI_MSK(0x00000800,uint32_t))  /* TERR5: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG5        (_ADI_MSK(0x00000C00,uint32_t))  /* TERR5: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR4            (_ADI_MSK(0x00000300,uint32_t))  /* Error type for Timer 4 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR4          (_ADI_MSK(0x00000000,uint32_t))  /* TERR4: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF4          (_ADI_MSK(0x00000100,uint32_t))  /* TERR4: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG4          (_ADI_MSK(0x00000200,uint32_t))  /* TERR4: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG4        (_ADI_MSK(0x00000300,uint32_t))  /* TERR4: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR3            (_ADI_MSK(0x000000C0,uint32_t))  /* Error type for Timer 3 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR3          (_ADI_MSK(0x00000000,uint32_t))  /* TERR3: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF3          (_ADI_MSK(0x00000040,uint32_t))  /* TERR3: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG3          (_ADI_MSK(0x00000080,uint32_t))  /* TERR3: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG3        (_ADI_MSK(0x000000C0,uint32_t))  /* TERR3: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR2            (_ADI_MSK(0x00000030,uint32_t))  /* Error type for Timer 2 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR2          (_ADI_MSK(0x00000000,uint32_t))  /* TERR2: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF2          (_ADI_MSK(0x00000010,uint32_t))  /* TERR2: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG2          (_ADI_MSK(0x00000020,uint32_t))  /* TERR2: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG2        (_ADI_MSK(0x00000030,uint32_t))  /* TERR2: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR1            (_ADI_MSK(0x0000000C,uint32_t))  /* Error type for Timer 1 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR1          (_ADI_MSK(0x00000000,uint32_t))  /* TERR1: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF1          (_ADI_MSK(0x00000004,uint32_t))  /* TERR1: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG1          (_ADI_MSK(0x00000008,uint32_t))  /* TERR1: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG1        (_ADI_MSK(0x0000000C,uint32_t))  /* TERR1: WID or DLY Register Programming Error */
-
-#define BITM_TIMER_ERR_TYPE_TERR0            (_ADI_MSK(0x00000003,uint32_t))  /* Error type for Timer 0 */
-#define ENUM_TIMER_ERR_TYPE_NO_ERR0          (_ADI_MSK(0x00000000,uint32_t))  /* TERR0: No Error */
-#define ENUM_TIMER_ERR_TYPE_CNTOVF0          (_ADI_MSK(0x00000001,uint32_t))  /* TERR0: Counter Overflow Error */
-#define ENUM_TIMER_ERR_TYPE_PERPRG0          (_ADI_MSK(0x00000002,uint32_t))  /* TERR0: PER Register Programming Error */
-#define ENUM_TIMER_ERR_TYPE_PULSEPRG0        (_ADI_MSK(0x00000003,uint32_t))  /* TERR0: WID or DLY Register Programming Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TIMER_TMR_CFG                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TIMER_TMR_CFG_EMURUN            15                               /* Run Timer (Counter) During Emulation */
-#define BITP_TIMER_TMR_CFG_BPEREN            14                               /* Broadcast Period Enable */
-#define BITP_TIMER_TMR_CFG_BWIDEN            13                               /* Broadcast Width Enable */
-#define BITP_TIMER_TMR_CFG_BDLYEN            12                               /* Broadcast Delay Enable */
-#define BITP_TIMER_TMR_CFG_OUTDIS            11                               /* Output Disable */
-#define BITP_TIMER_TMR_CFG_TINSEL            10                               /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define BITP_TIMER_TMR_CFG_CLKSEL             8                               /* Clock Select */
-#define BITP_TIMER_TMR_CFG_PULSEHI            7                               /* Polarity Response Select */
-#define BITP_TIMER_TMR_CFG_SLAVETRIG          6                               /* Slave Trigger Response */
-#define BITP_TIMER_TMR_CFG_IRQMODE            4                               /* Interrupt Modes */
-#define BITP_TIMER_TMR_CFG_TMODE              0                               /* Timer Mode Select */
-
-#define BITM_TIMER_TMR_CFG_EMURUN            (_ADI_MSK(0x00008000,uint16_t))  /* Run Timer (Counter) During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_NOCNT         (_ADI_MSK(0x00000000,uint16_t))  /* EMURUN: Stop Timer During Emulation */
-#define ENUM_TIMER_TMR_CFG_EMU_CNT           (_ADI_MSK(0x00008000,uint16_t))  /* EMURUN: Run Timer During Emulation */
-
-#define BITM_TIMER_TMR_CFG_BPEREN            (_ADI_MSK(0x00004000,uint16_t))  /* Broadcast Period Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BPEREN: Disable Broadcast to PER Register */
-#define ENUM_TIMER_TMR_CFG_BCASTPER_EN       (_ADI_MSK(0x00004000,uint16_t))  /* BPEREN: Enable Broadcast to PER Register */
-
-#define BITM_TIMER_TMR_CFG_BWIDEN            (_ADI_MSK(0x00002000,uint16_t))  /* Broadcast Width Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BWIDEN: Disable Broadcast to WID Register */
-#define ENUM_TIMER_TMR_CFG_BCASTWID_EN       (_ADI_MSK(0x00002000,uint16_t))  /* BWIDEN: Enable Broadcast to WID Register */
-
-#define BITM_TIMER_TMR_CFG_BDLYEN            (_ADI_MSK(0x00001000,uint16_t))  /* Broadcast Delay Enable */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_DIS      (_ADI_MSK(0x00000000,uint16_t))  /* BDLYEN: Disable Broadcast to DLY Register */
-#define ENUM_TIMER_TMR_CFG_BCASTDLY_EN       (_ADI_MSK(0x00001000,uint16_t))  /* BDLYEN: Enable Broadcast to DLY Register */
-
-#define BITM_TIMER_TMR_CFG_OUTDIS            (_ADI_MSK(0x00000800,uint16_t))  /* Output Disable */
-#define ENUM_TIMER_TMR_CFG_PADOUT_EN         (_ADI_MSK(0x00000000,uint16_t))  /* OUTDIS: Enable TMR pin output buffer */
-#define ENUM_TIMER_TMR_CFG_PADOUT_DIS        (_ADI_MSK(0x00000800,uint16_t))  /* OUTDIS: Disable TMR pin output buffer */
-
-#define BITM_TIMER_TMR_CFG_TINSEL            (_ADI_MSK(0x00000400,uint16_t))  /* Timer Input Select (for WIDCAP, WATCHDOG, PININT modes) */
-#define ENUM_TIMER_TMR_CFG_TINSEL_TMR        (_ADI_MSK(0x00000000,uint16_t))  /* TINSEL: Use TMR pin input */
-#define ENUM_TIMER_TMR_CFG_TINSEL_AUX        (_ADI_MSK(0x00000400,uint16_t))  /* TINSEL: Use TMR Alternate Capture Input */
-
-#define BITM_TIMER_TMR_CFG_CLKSEL            (_ADI_MSK(0x00000300,uint16_t))  /* Clock Select */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_SCLK       (_ADI_MSK(0x00000000,uint16_t))  /* CLKSEL: Use SCLK */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT0       (_ADI_MSK(0x00000100,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK0 as the TMR clock */
-#define ENUM_TIMER_TMR_CFG_CLKSEL_ALT1       (_ADI_MSK(0x00000300,uint16_t))  /* CLKSEL: Use TMR_ALT_CLK1 as the TMR clock */
-
-#define BITM_TIMER_TMR_CFG_PULSEHI           (_ADI_MSK(0x00000080,uint16_t))  /* Polarity Response Select */
-#define ENUM_TIMER_TMR_CFG_NEG_EDGE          (_ADI_MSK(0x00000000,uint16_t))  /* PULSEHI: Negative Response/Pulse */
-#define ENUM_TIMER_TMR_CFG_POS_EDGE          (_ADI_MSK(0x00000080,uint16_t))  /* PULSEHI: Positive  Response/Pulse */
-
-#define BITM_TIMER_TMR_CFG_SLAVETRIG         (_ADI_MSK(0x00000040,uint16_t))  /* Slave Trigger Response */
-#define ENUM_TIMER_TMR_CFG_TRIGSTOP          (_ADI_MSK(0x00000000,uint16_t))  /* SLAVETRIG: Pulse stops timer if it is running */
-#define ENUM_TIMER_TMR_CFG_TRIGSTART         (_ADI_MSK(0x00000040,uint16_t))  /* SLAVETRIG: Pulse starts timer if it is stopped */
-
-#define BITM_TIMER_TMR_CFG_IRQMODE           (_ADI_MSK(0x00000030,uint16_t))  /* Interrupt Modes */
-#define ENUM_TIMER_TMR_CFG_IRQMODE0          (_ADI_MSK(0x00000000,uint16_t))  /* IRQMODE: Active Edge Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE1          (_ADI_MSK(0x00000010,uint16_t))  /* IRQMODE: Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE2          (_ADI_MSK(0x00000020,uint16_t))  /* IRQMODE: Width Plus Delay Expired Mode */
-#define ENUM_TIMER_TMR_CFG_IRQMODE3          (_ADI_MSK(0x00000030,uint16_t))  /* IRQMODE: Period Expired Mode */
-
-#define BITM_TIMER_TMR_CFG_TMODE             (_ADI_MSK(0x0000000F,uint16_t))  /* Timer Mode Select */
-#define ENUM_TIMER_TMR_CFG_IDLE_MODE         (_ADI_MSK(0x00000000,uint16_t))  /* TMODE: Idle Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP0_MODE      (_ADI_MSK(0x0000000A,uint16_t))  /* TMODE: Width Capture Asserted Mode */
-#define ENUM_TIMER_TMR_CFG_WIDCAP1_MODE      (_ADI_MSK(0x0000000B,uint16_t))  /* TMODE: Width Capture Deasserted Mode */
-#define ENUM_TIMER_TMR_CFG_PWMCONT_MODE      (_ADI_MSK(0x0000000C,uint16_t))  /* TMODE: Continuous PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_PWMSING_MODE      (_ADI_MSK(0x0000000D,uint16_t))  /* TMODE: Single pulse PWMOUT mode */
-#define ENUM_TIMER_TMR_CFG_EXTCLK_MODE       (_ADI_MSK(0x0000000E,uint16_t))  /* TMODE: EXTCLK mode */
-#define ENUM_TIMER_TMR_CFG_PININT_MODE       (_ADI_MSK(0x0000000F,uint16_t))  /* TMODE: PININT (pin interrupt) mode */
-#define ENUM_TIMER_TMR_CFG_WDPER_MODE        (_ADI_MSK(0x00000008,uint16_t))  /* TMODE: Period Watchdog Mode */
-#define ENUM_TIMER_TMR_CFG_WDWID_MODE        (_ADI_MSK(0x00000009,uint16_t))  /* TMODE: Width Watchdog Mode */
-
-/* ==================================================
-        Cyclic Redundancy Check Unit Registers
-   ================================================== */
-
-/* =========================
-        CRC0
-   ========================= */
-#define REG_CRC0_CTL                    0xFFC01C00         /* CRC0 Control Register */
-#define REG_CRC0_DCNT                   0xFFC01C04         /* CRC0 Data Word Count Register */
-#define REG_CRC0_DCNTRLD                0xFFC01C08         /* CRC0 Data Word Count Reload Register */
-#define REG_CRC0_COMP                   0xFFC01C14         /* CRC0 Data Compare Register */
-#define REG_CRC0_FILLVAL                0xFFC01C18         /* CRC0 Fill Value Register */
-#define REG_CRC0_DFIFO                  0xFFC01C1C         /* CRC0 Data FIFO Register */
-#define REG_CRC0_INEN                   0xFFC01C20         /* CRC0 Interrupt Enable Register */
-#define REG_CRC0_INEN_SET               0xFFC01C24         /* CRC0 Interrupt Enable Set Register */
-#define REG_CRC0_INEN_CLR               0xFFC01C28         /* CRC0 Interrupt Enable Clear Register */
-#define REG_CRC0_POLY                   0xFFC01C2C         /* CRC0 Polynomial Register */
-#define REG_CRC0_STAT                   0xFFC01C40         /* CRC0 Status Register */
-#define REG_CRC0_DCNTCAP                0xFFC01C44         /* CRC0 Data Count Capture Register */
-#define REG_CRC0_RESULT_FIN             0xFFC01C4C         /* CRC0 CRC Final Result Register */
-#define REG_CRC0_RESULT_CUR             0xFFC01C50         /* CRC0 CRC Current Result Register */
-#define REG_CRC0_REVID                  0xFFC01C60         /* CRC0 Revision ID Register */
-
-/* =========================
-        CRC1
-   ========================= */
-#define REG_CRC1_CTL                    0xFFC01D00         /* CRC1 Control Register */
-#define REG_CRC1_DCNT                   0xFFC01D04         /* CRC1 Data Word Count Register */
-#define REG_CRC1_DCNTRLD                0xFFC01D08         /* CRC1 Data Word Count Reload Register */
-#define REG_CRC1_COMP                   0xFFC01D14         /* CRC1 Data Compare Register */
-#define REG_CRC1_FILLVAL                0xFFC01D18         /* CRC1 Fill Value Register */
-#define REG_CRC1_DFIFO                  0xFFC01D1C         /* CRC1 Data FIFO Register */
-#define REG_CRC1_INEN                   0xFFC01D20         /* CRC1 Interrupt Enable Register */
-#define REG_CRC1_INEN_SET               0xFFC01D24         /* CRC1 Interrupt Enable Set Register */
-#define REG_CRC1_INEN_CLR               0xFFC01D28         /* CRC1 Interrupt Enable Clear Register */
-#define REG_CRC1_POLY                   0xFFC01D2C         /* CRC1 Polynomial Register */
-#define REG_CRC1_STAT                   0xFFC01D40         /* CRC1 Status Register */
-#define REG_CRC1_DCNTCAP                0xFFC01D44         /* CRC1 Data Count Capture Register */
-#define REG_CRC1_RESULT_FIN             0xFFC01D4C         /* CRC1 CRC Final Result Register */
-#define REG_CRC1_RESULT_CUR             0xFFC01D50         /* CRC1 CRC Current Result Register */
-#define REG_CRC1_REVID                  0xFFC01D60         /* CRC1 Revision ID Register */
-
-/* =========================
-        CRC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_CTL_CMPMIRR                 22                               /* COMPARE Register Mirroring */
-#define BITP_CRC_CTL_POLYMIRR                21                               /* Polynomial Register Mirroring */
-#define BITP_CRC_CTL_RSLTMIRR                20                               /* Result Register Mirroring */
-#define BITP_CRC_CTL_FDSEL                   19                               /* FIFO Data Select */
-#define BITP_CRC_CTL_W16SWP                  18                               /* Word16 Swapping */
-#define BITP_CRC_CTL_BYTMIRR                 17                               /* Byte Mirroring */
-#define BITP_CRC_CTL_BITMIRR                 16                               /* Bit Mirroring */
-#define BITP_CRC_CTL_IRRSTALL                13                               /* Intermediate Result Ready Stall */
-#define BITP_CRC_CTL_OBRSTALL                12                               /* Output Buffer Ready Stall */
-#define BITP_CRC_CTL_AUTOCLRF                 9                               /* Auto Clear to One */
-#define BITP_CRC_CTL_AUTOCLRZ                 8                               /* Auto Clear to Zero */
-#define BITP_CRC_CTL_OPMODE                   4                               /* Operation Mode */
-#define BITP_CRC_CTL_BLKEN                    0                               /* Block Enable */
-#define BITM_CRC_CTL_CMPMIRR                 (_ADI_MSK(0x00400000,uint32_t))  /* COMPARE Register Mirroring */
-#define BITM_CRC_CTL_POLYMIRR                (_ADI_MSK(0x00200000,uint32_t))  /* Polynomial Register Mirroring */
-#define BITM_CRC_CTL_RSLTMIRR                (_ADI_MSK(0x00100000,uint32_t))  /* Result Register Mirroring */
-#define BITM_CRC_CTL_FDSEL                   (_ADI_MSK(0x00080000,uint32_t))  /* FIFO Data Select */
-#define BITM_CRC_CTL_W16SWP                  (_ADI_MSK(0x00040000,uint32_t))  /* Word16 Swapping */
-#define BITM_CRC_CTL_BYTMIRR                 (_ADI_MSK(0x00020000,uint32_t))  /* Byte Mirroring */
-#define BITM_CRC_CTL_BITMIRR                 (_ADI_MSK(0x00010000,uint32_t))  /* Bit Mirroring */
-#define BITM_CRC_CTL_IRRSTALL                (_ADI_MSK(0x00002000,uint32_t))  /* Intermediate Result Ready Stall */
-#define BITM_CRC_CTL_OBRSTALL                (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Ready Stall */
-#define BITM_CRC_CTL_AUTOCLRF                (_ADI_MSK(0x00000200,uint32_t))  /* Auto Clear to One */
-#define BITM_CRC_CTL_AUTOCLRZ                (_ADI_MSK(0x00000100,uint32_t))  /* Auto Clear to Zero */
-#define BITM_CRC_CTL_OPMODE                  (_ADI_MSK(0x000000F0,uint32_t))  /* Operation Mode */
-#define BITM_CRC_CTL_BLKEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Block Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_DCNTEXP                 4                               /* Data Count Expired (Status) Interrupt Enable */
-#define BITP_CRC_INEN_CMPERR                  1                               /* Compare Error Interrupt Enable */
-
-#define BITM_CRC_INEN_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable */
-#define ENUM_CRC_INEN_DCNTEXP_MSK            (_ADI_MSK(0x00000000,uint32_t))  /* DCNTEXP: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_DCNTEXP_UMSK           (_ADI_MSK(0x00000010,uint32_t))  /* DCNTEXP: Enable (unmask) interrupt */
-
-#define BITM_CRC_INEN_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable */
-#define ENUM_CRC_INEN_CMPERR_MSK             (_ADI_MSK(0x00000000,uint32_t))  /* CMPERR: Disable (mask) interrupt */
-#define ENUM_CRC_INEN_CMPERR_UMSK            (_ADI_MSK(0x00000002,uint32_t))  /* CMPERR: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_SET_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITP_CRC_INEN_SET_CMPERR              1                               /* Compare Error Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Set */
-#define BITM_CRC_INEN_SET_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_INEN_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_INEN_CLR_DCNTEXP             4                               /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITP_CRC_INEN_CLR_CMPERR              1                               /* Compare Error Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_DCNTEXP            (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired (Status) Interrupt Enable Clear */
-#define BITM_CRC_INEN_CLR_CMPERR             (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error Interrupt Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_STAT_FSTAT                  20                               /* FIFO Status */
-#define BITP_CRC_STAT_LUTDONE                19                               /* Look Up Table Done */
-#define BITP_CRC_STAT_IRR                    18                               /* Intermediate Result Ready */
-#define BITP_CRC_STAT_OBR                    17                               /* Output Buffer Ready */
-#define BITP_CRC_STAT_IBR                    16                               /* Input Buffer Ready */
-#define BITP_CRC_STAT_DCNTEXP                 4                               /* Data Count Expired */
-#define BITP_CRC_STAT_CMPERR                  1                               /* Compare Error */
-#define BITM_CRC_STAT_FSTAT                  (_ADI_MSK(0x00700000,uint32_t))  /* FIFO Status */
-#define BITM_CRC_STAT_LUTDONE                (_ADI_MSK(0x00080000,uint32_t))  /* Look Up Table Done */
-#define BITM_CRC_STAT_IRR                    (_ADI_MSK(0x00040000,uint32_t))  /* Intermediate Result Ready */
-#define BITM_CRC_STAT_OBR                    (_ADI_MSK(0x00020000,uint32_t))  /* Output Buffer Ready */
-#define BITM_CRC_STAT_IBR                    (_ADI_MSK(0x00010000,uint32_t))  /* Input Buffer Ready */
-#define BITM_CRC_STAT_DCNTEXP                (_ADI_MSK(0x00000010,uint32_t))  /* Data Count Expired */
-#define BITM_CRC_STAT_CMPERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Compare Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CRC_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CRC_REVID_MAJOR                  4                               /* Major Revision ID */
-#define BITP_CRC_REVID_REV                    0                               /* Incremental Revision ID */
-#define BITM_CRC_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Revision ID */
-#define BITM_CRC_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Revision ID */
-
-/* ==================================================
-        2-Wire Interface Registers
-   ================================================== */
-
-/* =========================
-        TWI0
-   ========================= */
-#define REG_TWI0_CLKDIV                 0xFFC01E00         /* TWI0 SCL Clock Divider Register */
-#define REG_TWI0_CTL                    0xFFC01E04         /* TWI0 Control Register */
-#define REG_TWI0_SLVCTL                 0xFFC01E08         /* TWI0 Slave Mode Control Register */
-#define REG_TWI0_SLVSTAT                0xFFC01E0C         /* TWI0 Slave Mode Status Register */
-#define REG_TWI0_SLVADDR                0xFFC01E10         /* TWI0 Slave Mode Address Register */
-#define REG_TWI0_MSTRCTL                0xFFC01E14         /* TWI0 Master Mode Control Registers */
-#define REG_TWI0_MSTRSTAT               0xFFC01E18         /* TWI0 Master Mode Status Register */
-#define REG_TWI0_MSTRADDR               0xFFC01E1C         /* TWI0 Master Mode Address Register */
-#define REG_TWI0_ISTAT                  0xFFC01E20         /* TWI0 Interrupt Status Register */
-#define REG_TWI0_IMSK                   0xFFC01E24         /* TWI0 Interrupt Mask Register */
-#define REG_TWI0_FIFOCTL                0xFFC01E28         /* TWI0 FIFO Control Register */
-#define REG_TWI0_FIFOSTAT               0xFFC01E2C         /* TWI0 FIFO Status Register */
-#define REG_TWI0_TXDATA8                0xFFC01E80         /* TWI0 Tx Data Single-Byte Register */
-#define REG_TWI0_TXDATA16               0xFFC01E84         /* TWI0 Tx Data Double-Byte Register */
-#define REG_TWI0_RXDATA8                0xFFC01E88         /* TWI0 Rx Data Single-Byte Register */
-#define REG_TWI0_RXDATA16               0xFFC01E8C         /* TWI0 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI1
-   ========================= */
-#define REG_TWI1_CLKDIV                 0xFFC01F00         /* TWI1 SCL Clock Divider Register */
-#define REG_TWI1_CTL                    0xFFC01F04         /* TWI1 Control Register */
-#define REG_TWI1_SLVCTL                 0xFFC01F08         /* TWI1 Slave Mode Control Register */
-#define REG_TWI1_SLVSTAT                0xFFC01F0C         /* TWI1 Slave Mode Status Register */
-#define REG_TWI1_SLVADDR                0xFFC01F10         /* TWI1 Slave Mode Address Register */
-#define REG_TWI1_MSTRCTL                0xFFC01F14         /* TWI1 Master Mode Control Registers */
-#define REG_TWI1_MSTRSTAT               0xFFC01F18         /* TWI1 Master Mode Status Register */
-#define REG_TWI1_MSTRADDR               0xFFC01F1C         /* TWI1 Master Mode Address Register */
-#define REG_TWI1_ISTAT                  0xFFC01F20         /* TWI1 Interrupt Status Register */
-#define REG_TWI1_IMSK                   0xFFC01F24         /* TWI1 Interrupt Mask Register */
-#define REG_TWI1_FIFOCTL                0xFFC01F28         /* TWI1 FIFO Control Register */
-#define REG_TWI1_FIFOSTAT               0xFFC01F2C         /* TWI1 FIFO Status Register */
-#define REG_TWI1_TXDATA8                0xFFC01F80         /* TWI1 Tx Data Single-Byte Register */
-#define REG_TWI1_TXDATA16               0xFFC01F84         /* TWI1 Tx Data Double-Byte Register */
-#define REG_TWI1_RXDATA8                0xFFC01F88         /* TWI1 Rx Data Single-Byte Register */
-#define REG_TWI1_RXDATA16               0xFFC01F8C         /* TWI1 Rx Data Double-Byte Register */
-
-/* =========================
-        TWI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CLKDIV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CLKDIV_CLKHI                 8                               /* SCL Clock High Periods */
-#define BITP_TWI_CLKDIV_CLKLO                 0                               /* SCL Clock Low Periods */
-#define BITM_TWI_CLKDIV_CLKHI                (_ADI_MSK(0x0000FF00,uint16_t))  /* SCL Clock High Periods */
-#define BITM_TWI_CLKDIV_CLKLO                (_ADI_MSK(0x000000FF,uint16_t))  /* SCL Clock Low Periods */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_CTL_SCCB                     9                               /* SCCB Compatibility */
-#define BITP_TWI_CTL_EN                       7                               /* Enable Module */
-#define BITP_TWI_CTL_PRESCALE                 0                               /* SCLK Prescale Value */
-
-#define BITM_TWI_CTL_SCCB                    (_ADI_MSK(0x00000200,uint16_t))  /* SCCB Compatibility */
-#define ENUM_TWI_CTL_SCCB_DIS                (_ADI_MSK(0x00000000,uint16_t))  /* SCCB: Disable SCCB compatibility */
-#define ENUM_TWI_CTL_SCCB_EN                 (_ADI_MSK(0x00000200,uint16_t))  /* SCCB: Enable SCCB compatibility */
-
-#define BITM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* Enable Module */
-#define ENUM_TWI_CTL_DIS                     (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_CTL_EN                      (_ADI_MSK(0x00000080,uint16_t))  /* EN: Enable */
-#define BITM_TWI_CTL_PRESCALE                (_ADI_MSK(0x0000007F,uint16_t))  /* SCLK Prescale Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVCTL_GEN                   4                               /* General Call Enable */
-#define BITP_TWI_SLVCTL_NAK                   3                               /* Not Acknowledge */
-#define BITP_TWI_SLVCTL_TDVAL                 2                               /* Transmit Data Valid for Slave */
-#define BITP_TWI_SLVCTL_EN                    0                               /* Enable Slave Mode */
-
-#define BITM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* General Call Enable */
-#define ENUM_TWI_SLVCTL_GDIS                 (_ADI_MSK(0x00000000,uint16_t))  /* GEN: Disable General Call Matching */
-#define ENUM_TWI_SLVCTL_GEN                  (_ADI_MSK(0x00000010,uint16_t))  /* GEN: Enable General Call Matching */
-
-#define BITM_TWI_SLVCTL_NAK                  (_ADI_MSK(0x00000008,uint16_t))  /* Not Acknowledge */
-#define ENUM_TWI_SLVCTL_ACKGEN               (_ADI_MSK(0x00000000,uint16_t))  /* NAK: Generate ACK */
-#define ENUM_TWI_SLVCTL_NAKGEN               (_ADI_MSK(0x00000008,uint16_t))  /* NAK: Generate NAK */
-
-#define BITM_TWI_SLVCTL_TDVAL                (_ADI_MSK(0x00000004,uint16_t))  /* Transmit Data Valid for Slave */
-#define ENUM_TWI_SLVCTL_INVALID              (_ADI_MSK(0x00000000,uint16_t))  /* TDVAL: Data Invalid for Slave Tx */
-#define ENUM_TWI_SLVCTL_VALID                (_ADI_MSK(0x00000004,uint16_t))  /* TDVAL: Data Valid for Slave Tx */
-
-#define BITM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* Enable Slave Mode */
-#define ENUM_TWI_SLVCTL_DIS                  (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_SLVCTL_EN                   (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVSTAT_GCALL                1                               /* General Call */
-#define BITP_TWI_SLVSTAT_DIR                  0                               /* Transfer Direction for Slave */
-
-#define BITM_TWI_SLVSTAT_GCALL               (_ADI_MSK(0x00000002,uint16_t))  /* General Call */
-#define ENUM_TWI_SLVSTAT_NO                  (_ADI_MSK(0x00000000,uint16_t))  /* GCALL: Not a General Call Address */
-#define ENUM_TWI_SLVSTAT_YES                 (_ADI_MSK(0x00000002,uint16_t))  /* GCALL: General Call Address */
-
-#define BITM_TWI_SLVSTAT_DIR                 (_ADI_MSK(0x00000001,uint16_t))  /* Transfer Direction for Slave */
-#define ENUM_TWI_SLVSTAT_RX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Slave Receive */
-#define ENUM_TWI_SLVSTAT_TX                  (_ADI_MSK(0x00000001,uint16_t))  /* DIR: Slave Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_SLVADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_SLVADDR_ADDR                 0                               /* Slave Mode Address */
-#define BITM_TWI_SLVADDR_ADDR                (_ADI_MSK(0x0000007F,uint16_t))  /* Slave Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRCTL_SCLOVR              15                               /* Serial Clock Override */
-#define BITP_TWI_MSTRCTL_SDAOVR              14                               /* Serial Data Override */
-#define BITP_TWI_MSTRCTL_DCNT                 6                               /* Data Transfer Count */
-#define BITP_TWI_MSTRCTL_RSTART               5                               /* Repeat Start */
-#define BITP_TWI_MSTRCTL_STOP                 4                               /* Issue Stop Condition */
-#define BITP_TWI_MSTRCTL_FAST                 3                               /* Fast Mode */
-#define BITP_TWI_MSTRCTL_DIR                  2                               /* Transfer Direction for Master */
-#define BITP_TWI_MSTRCTL_EN                   0                               /* Enable Master Mode */
-
-#define BITM_TWI_MSTRCTL_SCLOVR              (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Override */
-#define ENUM_TWI_MSTRCTL_SCLNORM             (_ADI_MSK(0x00000000,uint16_t))  /* SCLOVR: Permit Normal SCL Operation */
-#define ENUM_TWI_MSTRCTL_SCLOVER             (_ADI_MSK(0x00008000,uint16_t))  /* SCLOVR: Override Normal SCL Operation */
-
-#define BITM_TWI_MSTRCTL_SDAOVR              (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Override */
-#define ENUM_TWI_MSTRCTL_SDANORM             (_ADI_MSK(0x00000000,uint16_t))  /* SDAOVR: Permit Normal SDA Operation */
-#define ENUM_TWI_MSTRCTL_SDAOVER             (_ADI_MSK(0x00004000,uint16_t))  /* SDAOVR: Override Normal SDA Operation */
-#define BITM_TWI_MSTRCTL_DCNT                (_ADI_MSK(0x00003FC0,uint16_t))  /* Data Transfer Count */
-
-#define BITM_TWI_MSTRCTL_RSTART              (_ADI_MSK(0x00000020,uint16_t))  /* Repeat Start */
-#define ENUM_TWI_MSTRCTL_END                 (_ADI_MSK(0x00000000,uint16_t))  /* RSTART: Disable Repeat Start */
-#define ENUM_TWI_MSTRCTL_RPT                 (_ADI_MSK(0x00000020,uint16_t))  /* RSTART: Enable Repeat Start */
-
-#define BITM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* Issue Stop Condition */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* STOP: Permit Normal Operation */
-#define ENUM_TWI_MSTRCTL_STOP                (_ADI_MSK(0x00000010,uint16_t))  /* STOP: Issue Stop */
-
-#define BITM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* Fast Mode */
-#define ENUM_TWI_MSTRCTL_NORM                (_ADI_MSK(0x00000000,uint16_t))  /* FAST: Select Standard Mode */
-#define ENUM_TWI_MSTRCTL_FAST                (_ADI_MSK(0x00000008,uint16_t))  /* FAST: Select Fast Mode */
-
-#define BITM_TWI_MSTRCTL_DIR                 (_ADI_MSK(0x00000004,uint16_t))  /* Transfer Direction for Master */
-#define ENUM_TWI_MSTRCTL_TX                  (_ADI_MSK(0x00000000,uint16_t))  /* DIR: Master Transmit */
-#define ENUM_TWI_MSTRCTL_RX                  (_ADI_MSK(0x00000004,uint16_t))  /* DIR: Master Receive */
-
-#define BITM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* Enable Master Mode */
-#define ENUM_TWI_MSTRCTL_DIS                 (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable */
-#define ENUM_TWI_MSTRCTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRSTAT_BUSBUSY             8                               /* Bus Busy */
-#define BITP_TWI_MSTRSTAT_SCLSEN              7                               /* Serial Clock Sense */
-#define BITP_TWI_MSTRSTAT_SDASEN              6                               /* Serial Data Sense */
-#define BITP_TWI_MSTRSTAT_BUFWRERR            5                               /* Buffer Write Error */
-#define BITP_TWI_MSTRSTAT_BUFRDERR            4                               /* Buffer Read Error */
-#define BITP_TWI_MSTRSTAT_DNAK                3                               /* Data Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_ANAK                2                               /* Address Not Acknowledged */
-#define BITP_TWI_MSTRSTAT_LOSTARB             1                               /* Lost Arbitration */
-#define BITP_TWI_MSTRSTAT_MPROG               0                               /* Master Transfer in Progress */
-
-#define BITM_TWI_MSTRSTAT_BUSBUSY            (_ADI_MSK(0x00000100,uint16_t))  /* Bus Busy */
-#define ENUM_TWI_MSTRSTAT_FREE               (_ADI_MSK(0x00000000,uint16_t))  /* BUSBUSY: Bus Free */
-#define ENUM_TWI_MSTRSTAT_BUSY               (_ADI_MSK(0x00000100,uint16_t))  /* BUSBUSY: Bus Busy */
-
-#define BITM_TWI_MSTRSTAT_SCLSEN             (_ADI_MSK(0x00000080,uint16_t))  /* Serial Clock Sense */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SCLSEN: SCL Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SCLSEN_YES         (_ADI_MSK(0x00000080,uint16_t))  /* SCLSEN: SCL Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_SDASEN             (_ADI_MSK(0x00000040,uint16_t))  /* Serial Data Sense */
-#define ENUM_TWI_MSTRSTAT_SDASEN_NO          (_ADI_MSK(0x00000000,uint16_t))  /* SDASEN: SDA Inactive "One" */
-#define ENUM_TWI_MSTRSTAT_SDASEN_YES         (_ADI_MSK(0x00000040,uint16_t))  /* SDASEN: SDA Active "Zero" */
-
-#define BITM_TWI_MSTRSTAT_BUFWRERR           (_ADI_MSK(0x00000020,uint16_t))  /* Buffer Write Error */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFWRERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFWRERR_YES       (_ADI_MSK(0x00000020,uint16_t))  /* BUFWRERR: Buffer Write Error */
-
-#define BITM_TWI_MSTRSTAT_BUFRDERR           (_ADI_MSK(0x00000010,uint16_t))  /* Buffer Read Error */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_NO        (_ADI_MSK(0x00000000,uint16_t))  /* BUFRDERR: No Status */
-#define ENUM_TWI_MSTRSTAT_BUFRDERR_YES       (_ADI_MSK(0x00000010,uint16_t))  /* BUFRDERR: Buffer Read Error */
-
-#define BITM_TWI_MSTRSTAT_DNAK               (_ADI_MSK(0x00000008,uint16_t))  /* Data Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_DNAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* DNAK: No Status */
-#define ENUM_TWI_MSTRSTAT_DNAK_YES           (_ADI_MSK(0x00000008,uint16_t))  /* DNAK: Data NAK */
-
-#define BITM_TWI_MSTRSTAT_ANAK               (_ADI_MSK(0x00000004,uint16_t))  /* Address Not Acknowledged */
-#define ENUM_TWI_MSTRSTAT_ANAK_NO            (_ADI_MSK(0x00000000,uint16_t))  /* ANAK: No Status */
-#define ENUM_TWI_MSTRSTAT_ANAK_YES           (_ADI_MSK(0x00000004,uint16_t))  /* ANAK: Address NAK */
-
-#define BITM_TWI_MSTRSTAT_LOSTARB            (_ADI_MSK(0x00000002,uint16_t))  /* Lost Arbitration */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_NO         (_ADI_MSK(0x00000000,uint16_t))  /* LOSTARB: No Status */
-#define ENUM_TWI_MSTRSTAT_LOSTARB_YES        (_ADI_MSK(0x00000002,uint16_t))  /* LOSTARB: Lost Arbitration */
-
-#define BITM_TWI_MSTRSTAT_MPROG              (_ADI_MSK(0x00000001,uint16_t))  /* Master Transfer in Progress */
-#define ENUM_TWI_MSTRSTAT_MPROG_NO           (_ADI_MSK(0x00000000,uint16_t))  /* MPROG: No Status */
-#define ENUM_TWI_MSTRSTAT_MPROG_YES          (_ADI_MSK(0x00000001,uint16_t))  /* MPROG: Master Transfer in Progress */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_MSTRADDR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_MSTRADDR_ADDR                0                               /* Master Mode Address */
-#define BITM_TWI_MSTRADDR_ADDR               (_ADI_MSK(0x0000007F,uint16_t))  /* Master Mode Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_ISTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_ISTAT_SCLI                  15                               /* Serial Clock Interrupt */
-#define BITP_TWI_ISTAT_SDAI                  14                               /* Serial Data Interrupt */
-#define BITP_TWI_ISTAT_RXSERV                 7                               /* Rx FIFO Service */
-#define BITP_TWI_ISTAT_TXSERV                 6                               /* Tx FIFO Service */
-#define BITP_TWI_ISTAT_MERR                   5                               /* Master Transfer Error */
-#define BITP_TWI_ISTAT_MCOMP                  4                               /* Master Transfer Complete */
-#define BITP_TWI_ISTAT_SOVF                   3                               /* Slave Overflow */
-#define BITP_TWI_ISTAT_SERR                   2                               /* Slave Transfer Error */
-#define BITP_TWI_ISTAT_SCOMP                  1                               /* Slave Transfer Complete */
-#define BITP_TWI_ISTAT_SINIT                  0                               /* Slave Transfer Initiated */
-
-#define BITM_TWI_ISTAT_SCLI                  (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: No Interrupt */
-#define ENUM_TWI_ISTAT_SCLI_YES              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SDAI                  (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: No Interrupt */
-#define ENUM_TWI_ISTAT_SDAI_YES              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_RXSERV                (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service */
-#define ENUM_TWI_ISTAT_RXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_RXSERV_YES            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_TXSERV                (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service */
-#define ENUM_TWI_ISTAT_TXSERV_NO             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: No Interrupt */
-#define ENUM_TWI_ISTAT_TXSERV_YES            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MERR                  (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error */
-#define ENUM_TWI_ISTAT_MERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: No Interrupt */
-#define ENUM_TWI_ISTAT_MERR_YES              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_MCOMP                 (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete */
-#define ENUM_TWI_ISTAT_MCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_MCOMP_YES             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SOVF                  (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow */
-#define ENUM_TWI_ISTAT_SOVF_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: No Interrupt */
-#define ENUM_TWI_ISTAT_SOVF_YES              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SERR                  (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error */
-#define ENUM_TWI_ISTAT_SERR_NO               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: No Interrupt */
-#define ENUM_TWI_ISTAT_SERR_YES              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SCOMP                 (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete */
-#define ENUM_TWI_ISTAT_SCOMP_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: No Interrupt */
-#define ENUM_TWI_ISTAT_SCOMP_YES             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Interrupt Detected */
-
-#define BITM_TWI_ISTAT_SINIT                 (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated */
-#define ENUM_TWI_ISTAT_SINIT_NO              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: No Interrupt */
-#define ENUM_TWI_ISTAT_SINIT_YES             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Interrupt Detected */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_IMSK_SCLI                   15                               /* Serial Clock Interrupt Mask */
-#define BITP_TWI_IMSK_SDAI                   14                               /* Serial Data Interrupt Mask */
-#define BITP_TWI_IMSK_RXSERV                  7                               /* Rx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_TXSERV                  6                               /* Tx FIFO Service Interrupt Mask */
-#define BITP_TWI_IMSK_MERR                    5                               /* Master Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_MCOMP                   4                               /* Master Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SOVF                    3                               /* Slave Overflow Interrupt Mask */
-#define BITP_TWI_IMSK_SERR                    2                               /* Slave Transfer Error Interrupt Mask */
-#define BITP_TWI_IMSK_SCOMP                   1                               /* Slave Transfer Complete Interrupt Mask */
-#define BITP_TWI_IMSK_SINIT                   0                               /* Slave Transfer Initiated Interrupt Mask */
-
-#define BITM_TWI_IMSK_SCLI                   (_ADI_MSK(0x00008000,uint16_t))  /* Serial Clock Interrupt Mask */
-#define ENUM_TWI_IMSK_SCLI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SCLI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCLI_UMSK              (_ADI_MSK(0x00008000,uint16_t))  /* SCLI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SDAI                   (_ADI_MSK(0x00004000,uint16_t))  /* Serial Data Interrupt Mask */
-#define ENUM_TWI_IMSK_SDAI_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SDAI: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SDAI_UMSK              (_ADI_MSK(0x00004000,uint16_t))  /* SDAI: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_RXSERV                 (_ADI_MSK(0x00000080,uint16_t))  /* Rx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_RXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* RXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_RXSERV_UMSK            (_ADI_MSK(0x00000080,uint16_t))  /* RXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_TXSERV                 (_ADI_MSK(0x00000040,uint16_t))  /* Tx FIFO Service Interrupt Mask */
-#define ENUM_TWI_IMSK_TXSERV_MSK             (_ADI_MSK(0x00000000,uint16_t))  /* TXSERV: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_TXSERV_UMSK            (_ADI_MSK(0x00000040,uint16_t))  /* TXSERV: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MERR                   (_ADI_MSK(0x00000020,uint16_t))  /* Master Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_MERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* MERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MERR_UMSK              (_ADI_MSK(0x00000020,uint16_t))  /* MERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_MCOMP                  (_ADI_MSK(0x00000010,uint16_t))  /* Master Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_MCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* MCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_MCOMP_UMSK             (_ADI_MSK(0x00000010,uint16_t))  /* MCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SOVF                   (_ADI_MSK(0x00000008,uint16_t))  /* Slave Overflow Interrupt Mask */
-#define ENUM_TWI_IMSK_SOVF_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SOVF: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SOVF_UMSK              (_ADI_MSK(0x00000008,uint16_t))  /* SOVF: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SERR                   (_ADI_MSK(0x00000004,uint16_t))  /* Slave Transfer Error Interrupt Mask */
-#define ENUM_TWI_IMSK_SERR_MSK               (_ADI_MSK(0x00000000,uint16_t))  /* SERR: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SERR_UMSK              (_ADI_MSK(0x00000004,uint16_t))  /* SERR: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SCOMP                  (_ADI_MSK(0x00000002,uint16_t))  /* Slave Transfer Complete Interrupt Mask */
-#define ENUM_TWI_IMSK_SCOMP_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SCOMP: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SCOMP_UMSK             (_ADI_MSK(0x00000002,uint16_t))  /* SCOMP: Unmask (Enable) Interrupt */
-
-#define BITM_TWI_IMSK_SINIT                  (_ADI_MSK(0x00000001,uint16_t))  /* Slave Transfer Initiated Interrupt Mask */
-#define ENUM_TWI_IMSK_SINIT_MSK              (_ADI_MSK(0x00000000,uint16_t))  /* SINIT: Mask (Disable) Interrupt */
-#define ENUM_TWI_IMSK_SINIT_UMSK             (_ADI_MSK(0x00000001,uint16_t))  /* SINIT: Unmask (Enable) Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOCTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOCTL_RXILEN               3                               /* Rx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_TXILEN               2                               /* Tx Buffer Interrupt Length */
-#define BITP_TWI_FIFOCTL_RXFLUSH              1                               /* Rx Buffer Flush */
-#define BITP_TWI_FIFOCTL_TXFLUSH              0                               /* Tx Buffer Flush */
-
-#define BITM_TWI_FIFOCTL_RXILEN              (_ADI_MSK(0x00000008,uint16_t))  /* Rx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_RXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* RXILEN: RXSERVI on 1 or 2 Bytes in FIFO */
-#define ENUM_TWI_FIFOCTL_RXTWOBYTE           (_ADI_MSK(0x00000008,uint16_t))  /* RXILEN: RXSERVI on 2 Bytes in FIFO */
-
-#define BITM_TWI_FIFOCTL_TXILEN              (_ADI_MSK(0x00000004,uint16_t))  /* Tx Buffer Interrupt Length */
-#define ENUM_TWI_FIFOCTL_TXONEBYTE           (_ADI_MSK(0x00000000,uint16_t))  /* TXILEN: TXSERVI on 1 Byte of FIFO Empty */
-#define ENUM_TWI_FIFOCTL_TXTWOBYTE           (_ADI_MSK(0x00000004,uint16_t))  /* TXILEN: TXSERVI on 2 Bytes of FIFO Empty */
-
-#define BITM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* Rx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_RXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* RXFLUSH: Normal Operation of Rx Buffer */
-#define ENUM_TWI_FIFOCTL_RXFLUSH             (_ADI_MSK(0x00000002,uint16_t))  /* RXFLUSH: Flush Rx Buffer */
-
-#define BITM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* Tx Buffer Flush */
-#define ENUM_TWI_FIFOCTL_TXNORM              (_ADI_MSK(0x00000000,uint16_t))  /* TXFLUSH: Normal Operation of Tx Buffer */
-#define ENUM_TWI_FIFOCTL_TXFLUSH             (_ADI_MSK(0x00000001,uint16_t))  /* TXFLUSH: Flush Tx Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_FIFOSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_FIFOSTAT_RXSTAT              2                               /* Rx FIFO Status */
-#define BITP_TWI_FIFOSTAT_TXSTAT              0                               /* Tx FIFO Status */
-#define BITM_TWI_FIFOSTAT_RXSTAT             (_ADI_MSK(0x0000000C,uint16_t))  /* Rx FIFO Status */
-#define BITM_TWI_FIFOSTAT_TXSTAT             (_ADI_MSK(0x00000003,uint16_t))  /* Tx FIFO Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_TXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_TXDATA8_VALUE                0                               /* Tx Data 8-Bit Value */
-#define BITM_TWI_TXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Tx Data 8-Bit Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TWI_RXDATA8                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TWI_RXDATA8_VALUE                0                               /* Rx Data 8-Bit Value */
-#define BITM_TWI_RXDATA8_VALUE               (_ADI_MSK(0x000000FF,uint16_t))  /* Rx Data 8-Bit Value */
-
-/* ==================================================
-        UART Registers
-   ================================================== */
-
-/* =========================
-        UART0
-   ========================= */
-#define REG_UART0_REVID                 0xFFC02000         /* UART0 Revision ID Register */
-#define REG_UART0_CTL                   0xFFC02004         /* UART0 Control Register */
-#define REG_UART0_STAT                  0xFFC02008         /* UART0 Status Register */
-#define REG_UART0_SCR                   0xFFC0200C         /* UART0 Scratch Register */
-#define REG_UART0_CLK                   0xFFC02010         /* UART0 Clock Rate Register */
-#define REG_UART0_IMSK                  0xFFC02014         /* UART0 Interrupt Mask Register */
-#define REG_UART0_IMSK_SET              0xFFC02018         /* UART0 Interrupt Mask Set Register */
-#define REG_UART0_IMSK_CLR              0xFFC0201C         /* UART0 Interrupt Mask Clear Register */
-#define REG_UART0_RBR                   0xFFC02020         /* UART0 Receive Buffer Register */
-#define REG_UART0_THR                   0xFFC02024         /* UART0 Transmit Hold Register */
-#define REG_UART0_TAIP                  0xFFC02028         /* UART0 Transmit Address/Insert Pulse Register */
-#define REG_UART0_TSR                   0xFFC0202C         /* UART0 Transmit Shift Register */
-#define REG_UART0_RSR                   0xFFC02030         /* UART0 Receive Shift Register */
-#define REG_UART0_TXCNT                 0xFFC02034         /* UART0 Transmit Counter Register */
-#define REG_UART0_RXCNT                 0xFFC02038         /* UART0 Receive Counter Register */
-
-/* =========================
-        UART1
-   ========================= */
-#define REG_UART1_REVID                 0xFFC02400         /* UART1 Revision ID Register */
-#define REG_UART1_CTL                   0xFFC02404         /* UART1 Control Register */
-#define REG_UART1_STAT                  0xFFC02408         /* UART1 Status Register */
-#define REG_UART1_SCR                   0xFFC0240C         /* UART1 Scratch Register */
-#define REG_UART1_CLK                   0xFFC02410         /* UART1 Clock Rate Register */
-#define REG_UART1_IMSK                  0xFFC02414         /* UART1 Interrupt Mask Register */
-#define REG_UART1_IMSK_SET              0xFFC02418         /* UART1 Interrupt Mask Set Register */
-#define REG_UART1_IMSK_CLR              0xFFC0241C         /* UART1 Interrupt Mask Clear Register */
-#define REG_UART1_RBR                   0xFFC02420         /* UART1 Receive Buffer Register */
-#define REG_UART1_THR                   0xFFC02424         /* UART1 Transmit Hold Register */
-#define REG_UART1_TAIP                  0xFFC02428         /* UART1 Transmit Address/Insert Pulse Register */
-#define REG_UART1_TSR                   0xFFC0242C         /* UART1 Transmit Shift Register */
-#define REG_UART1_RSR                   0xFFC02430         /* UART1 Receive Shift Register */
-#define REG_UART1_TXCNT                 0xFFC02434         /* UART1 Transmit Counter Register */
-#define REG_UART1_RXCNT                 0xFFC02438         /* UART1 Receive Counter Register */
-
-/* =========================
-        UART
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_REVID_MAJOR                 4                               /* Major Version */
-#define BITP_UART_REVID_REV                   0                               /* Incremental Version */
-#define BITM_UART_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version */
-#define BITM_UART_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CTL_RFRT                   30                               /* Receive FIFO RTS Threshold */
-#define BITP_UART_CTL_RFIT                   29                               /* Receive FIFO IRQ Threshold */
-#define BITP_UART_CTL_ACTS                   28                               /* Automatic CTS */
-#define BITP_UART_CTL_ARTS                   27                               /* Automatic RTS */
-#define BITP_UART_CTL_XOFF                   26                               /* Transmitter off */
-#define BITP_UART_CTL_MRTS                   25                               /* Manual Request to Send */
-#define BITP_UART_CTL_TPOLC                  24                               /* IrDA TX Polarity Change */
-#define BITP_UART_CTL_RPOLC                  23                               /* IrDA RX Polarity Change */
-#define BITP_UART_CTL_FCPOL                  22                               /* Flow Control Pin Polarity */
-#define BITP_UART_CTL_SB                     19                               /* Set Break */
-#define BITP_UART_CTL_FFE                    18                               /* Force Framing Error on Transmit */
-#define BITP_UART_CTL_FPE                    17                               /* Force Parity Error on Transmit */
-#define BITP_UART_CTL_STP                    16                               /* Sticky Parity */
-#define BITP_UART_CTL_EPS                    15                               /* Even Parity Select */
-#define BITP_UART_CTL_PEN                    14                               /* Parity Enable */
-#define BITP_UART_CTL_STBH                   13                               /* Stop Bits (Half Bit Time) */
-#define BITP_UART_CTL_STB                    12                               /* Stop Bits */
-#define BITP_UART_CTL_WLS                     8                               /* Word Length Select */
-#define BITP_UART_CTL_MOD                     4                               /* Mode of Operation */
-#define BITP_UART_CTL_LOOP_EN                 1                               /* Loopback Enable */
-#define BITP_UART_CTL_EN                      0                               /* Enable UART */
-
-#define BITM_UART_CTL_RFRT                   (_ADI_MSK(0x40000000,uint32_t))  /* Receive FIFO RTS Threshold */
-#define ENUM_UART_CTL_RX_RTS_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 4; assert if <= 4 */
-#define ENUM_UART_CTL_RX_RTS_TH7             (_ADI_MSK(0x40000000,uint32_t))  /* RFRT: De-assert RTS if RX FIFO word count > 7; assert if <= 7 */
-
-#define BITM_UART_CTL_RFIT                   (_ADI_MSK(0x20000000,uint32_t))  /* Receive FIFO IRQ Threshold */
-#define ENUM_UART_CTL_RX_IRQ_TH4             (_ADI_MSK(0x00000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 4 */
-#define ENUM_UART_CTL_RX_IRQ_TH7             (_ADI_MSK(0x20000000,uint32_t))  /* RFIT: Set RFCS=1 if RX FIFO count >= 7 */
-
-#define BITM_UART_CTL_ACTS                   (_ADI_MSK(0x10000000,uint32_t))  /* Automatic CTS */
-#define ENUM_UART_CTL_CTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ACTS: Disable TX handshaking protocol */
-#define ENUM_UART_CTL_CTS_AUTO               (_ADI_MSK(0x10000000,uint32_t))  /* ACTS: Enable TX handshaking protocol */
-
-#define BITM_UART_CTL_ARTS                   (_ADI_MSK(0x08000000,uint32_t))  /* Automatic RTS */
-#define ENUM_UART_CTL_RTS_MAN                (_ADI_MSK(0x00000000,uint32_t))  /* ARTS: Disable RX handshaking protocol. */
-#define ENUM_UART_CTL_RTS_AUTO               (_ADI_MSK(0x08000000,uint32_t))  /* ARTS: Enable RX handshaking protocol. */
-
-#define BITM_UART_CTL_XOFF                   (_ADI_MSK(0x04000000,uint32_t))  /* Transmitter off */
-#define ENUM_UART_CTL_TX_ON                  (_ADI_MSK(0x00000000,uint32_t))  /* XOFF: Transmission ON, if ACTS=0 */
-#define ENUM_UART_CTL_TX_OFF                 (_ADI_MSK(0x04000000,uint32_t))  /* XOFF: Transmission OFF, if ACTS=0 */
-
-#define BITM_UART_CTL_MRTS                   (_ADI_MSK(0x02000000,uint32_t))  /* Manual Request to Send */
-#define ENUM_UART_CTL_RTS_DEASSERT           (_ADI_MSK(0x00000000,uint32_t))  /* MRTS: De-assert RTS pin when ARTS=0 */
-#define ENUM_UART_CTL_RTS_ASSERT             (_ADI_MSK(0x02000000,uint32_t))  /* MRTS: Assert RTS pin  when ARTS=0 */
-
-#define BITM_UART_CTL_TPOLC                  (_ADI_MSK(0x01000000,uint32_t))  /* IrDA TX Polarity Change */
-#define ENUM_UART_CTL_TPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* TPOLC: Active-low TX polarity setting */
-#define ENUM_UART_CTL_TPOLC_HI               (_ADI_MSK(0x01000000,uint32_t))  /* TPOLC: Active-high TX polarity setting */
-
-#define BITM_UART_CTL_RPOLC                  (_ADI_MSK(0x00800000,uint32_t))  /* IrDA RX Polarity Change */
-#define ENUM_UART_CTL_RPOLC_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RPOLC: Active-low RX polarity setting */
-#define ENUM_UART_CTL_RPOLC_HI               (_ADI_MSK(0x00800000,uint32_t))  /* RPOLC: Active-high RX polarity setting */
-
-#define BITM_UART_CTL_FCPOL                  (_ADI_MSK(0x00400000,uint32_t))  /* Flow Control Pin Polarity */
-#define ENUM_UART_CTL_FCPOL_LO               (_ADI_MSK(0x00000000,uint32_t))  /* FCPOL: Active low CTS/RTS */
-#define ENUM_UART_CTL_FCPOL_HI               (_ADI_MSK(0x00400000,uint32_t))  /* FCPOL: Active high CTS/RTS */
-
-#define BITM_UART_CTL_SB                     (_ADI_MSK(0x00080000,uint32_t))  /* Set Break */
-#define ENUM_UART_CTL_NORM_BREAK             (_ADI_MSK(0x00000000,uint32_t))  /* SB: No force */
-#define ENUM_UART_CTL_FORCE_BREAK            (_ADI_MSK(0x00080000,uint32_t))  /* SB: Force TX pin to 0 */
-
-#define BITM_UART_CTL_FFE                    (_ADI_MSK(0x00040000,uint32_t))  /* Force Framing Error on Transmit */
-#define ENUM_UART_CTL_NORM_FRM_ERR           (_ADI_MSK(0x00000000,uint32_t))  /* FFE: Normal operation */
-#define ENUM_UART_CTL_FORCE_FRM_ERR          (_ADI_MSK(0x00040000,uint32_t))  /* FFE: Force error */
-
-#define BITM_UART_CTL_FPE                    (_ADI_MSK(0x00020000,uint32_t))  /* Force Parity Error on Transmit */
-#define ENUM_UART_CTL_NORM_PARITY_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FPE: Normal operation */
-#define ENUM_UART_CTL_FORCE_PARITY_ERR       (_ADI_MSK(0x00020000,uint32_t))  /* FPE: Force parity error */
-
-#define BITM_UART_CTL_STP                    (_ADI_MSK(0x00010000,uint32_t))  /* Sticky Parity */
-#define ENUM_UART_CTL_NORM_PARITY            (_ADI_MSK(0x00000000,uint32_t))  /* STP: No Forced Parity */
-#define ENUM_UART_CTL_STICKY_PARITY          (_ADI_MSK(0x00010000,uint32_t))  /* STP: Force (Stick) Parity to Defined Value (if PEN=1) */
-
-#define BITM_UART_CTL_EPS                    (_ADI_MSK(0x00008000,uint32_t))  /* Even Parity Select */
-#define ENUM_UART_CTL_ODD_PARITY             (_ADI_MSK(0x00000000,uint32_t))  /* EPS: Odd parity */
-#define ENUM_UART_CTL_EVEN_PARITY            (_ADI_MSK(0x00008000,uint32_t))  /* EPS: Even parity */
-
-#define BITM_UART_CTL_PEN                    (_ADI_MSK(0x00004000,uint32_t))  /* Parity Enable */
-#define ENUM_UART_CTL_PARITY_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* PEN: Disable */
-#define ENUM_UART_CTL_PARITY_EN              (_ADI_MSK(0x00004000,uint32_t))  /* PEN: Enable parity transmit and check */
-
-#define BITM_UART_CTL_STBH                   (_ADI_MSK(0x00002000,uint32_t))  /* Stop Bits (Half Bit Time) */
-#define ENUM_UART_CTL_NO_EXTRA_STBH          (_ADI_MSK(0x00000000,uint32_t))  /* STBH: 0 half-bit-time stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STBH           (_ADI_MSK(0x00002000,uint32_t))  /* STBH: 1 half-bit-time stop bit */
-
-#define BITM_UART_CTL_STB                    (_ADI_MSK(0x00001000,uint32_t))  /* Stop Bits */
-#define ENUM_UART_CTL_NO_EXTRA_STB           (_ADI_MSK(0x00000000,uint32_t))  /* STB: 1 stop bit */
-#define ENUM_UART_CTL_1_EXTRA_STB            (_ADI_MSK(0x00001000,uint32_t))  /* STB: 2 stop bits */
-
-#define BITM_UART_CTL_WLS                    (_ADI_MSK(0x00000300,uint32_t))  /* Word Length Select */
-#define ENUM_UART_CTL_WL5BITS                (_ADI_MSK(0x00000000,uint32_t))  /* WLS: 5-bit Word */
-#define ENUM_UART_CTL_WL6BITS                (_ADI_MSK(0x00000100,uint32_t))  /* WLS: 6-bit Word */
-#define ENUM_UART_CTL_WL7BITS                (_ADI_MSK(0x00000200,uint32_t))  /* WLS: 7-bit Word */
-#define ENUM_UART_CTL_WL8BITS                (_ADI_MSK(0x00000300,uint32_t))  /* WLS: 8-bit Word */
-
-#define BITM_UART_CTL_MOD                    (_ADI_MSK(0x00000030,uint32_t))  /* Mode of Operation */
-#define ENUM_UART_CTL_UART_MODE              (_ADI_MSK(0x00000000,uint32_t))  /* MOD: UART Mode */
-#define ENUM_UART_CTL_MDB_MODE               (_ADI_MSK(0x00000010,uint32_t))  /* MOD: MDB Mode */
-#define ENUM_UART_CTL_IRDA_MODE              (_ADI_MSK(0x00000020,uint32_t))  /* MOD: IrDA SIR Mode */
-
-#define BITM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* Loopback Enable */
-#define ENUM_UART_CTL_LOOP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* LOOP_EN: Disable */
-#define ENUM_UART_CTL_LOOP_EN                (_ADI_MSK(0x00000002,uint32_t))  /* LOOP_EN: Enable */
-
-#define BITM_UART_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable UART */
-#define ENUM_UART_CTL_CLK_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_UART_CTL_CLK_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_STAT_RFCS                  17                               /* Receive FIFO Count Status */
-#define BITP_UART_STAT_CTS                   16                               /* Clear to Send */
-#define BITP_UART_STAT_SCTS                  12                               /* Sticky CTS */
-#define BITP_UART_STAT_RO                    11                               /* Reception On-going */
-#define BITP_UART_STAT_ADDR                  10                               /* Address Bit Status */
-#define BITP_UART_STAT_ASTKY                  9                               /* Address Sticky */
-#define BITP_UART_STAT_TFI                    8                               /* Transmission Finished Indicator */
-#define BITP_UART_STAT_TEMT                   7                               /* TSR and THR Empty */
-#define BITP_UART_STAT_THRE                   5                               /* Transmit Hold Register Empty */
-#define BITP_UART_STAT_BI                     4                               /* Break Indicator */
-#define BITP_UART_STAT_FE                     3                               /* Framing Error */
-#define BITP_UART_STAT_PE                     2                               /* Parity Error */
-#define BITP_UART_STAT_OE                     1                               /* Overrun Error */
-#define BITP_UART_STAT_DR                     0                               /* Data Ready */
-
-#define BITM_UART_STAT_RFCS                  (_ADI_MSK(0x00020000,uint32_t))  /* Receive FIFO Count Status */
-#define ENUM_UART_STAT_RFCS_LO               (_ADI_MSK(0x00000000,uint32_t))  /* RFCS: RX FIFO has less than 4 (7) entries when RFIT=0 (1) */
-#define ENUM_UART_STAT_RFCS_HI               (_ADI_MSK(0x00020000,uint32_t))  /* RFCS: RX FIFO has at least 4 (7) entries when RFIT=0 (1) */
-
-#define BITM_UART_STAT_CTS                   (_ADI_MSK(0x00010000,uint32_t))  /* Clear to Send */
-#define ENUM_UART_STAT_CTS_LO                (_ADI_MSK(0x00000000,uint32_t))  /* CTS: Not clear to send (External device not ready to receive) */
-#define ENUM_UART_STAT_CTS_HI                (_ADI_MSK(0x00010000,uint32_t))  /* CTS: Clear to send (External device ready to receive) */
-
-#define BITM_UART_STAT_SCTS                  (_ADI_MSK(0x00001000,uint32_t))  /* Sticky CTS */
-#define ENUM_UART_STAT_CTS_LO_STKY           (_ADI_MSK(0x00000000,uint32_t))  /* SCTS: CTS has not transitioned from low to high */
-#define ENUM_UART_STAT_CTS_HI_STKY           (_ADI_MSK(0x00001000,uint32_t))  /* SCTS: CTS has transitioned from low to high */
-
-#define BITM_UART_STAT_RO                    (_ADI_MSK(0x00000800,uint32_t))  /* Reception On-going */
-#define ENUM_UART_STAT_NO_RX_PROGRESS        (_ADI_MSK(0x00000000,uint32_t))  /* RO: No data reception in progress */
-#define ENUM_UART_STAT_RX_PROGRESS           (_ADI_MSK(0x00000800,uint32_t))  /* RO: Data reception in progress */
-
-#define BITM_UART_STAT_ADDR                  (_ADI_MSK(0x00000400,uint32_t))  /* Address Bit Status */
-#define ENUM_UART_STAT_ADDR_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ADDR: Address bit is low */
-#define ENUM_UART_STAT_ADDR_HI               (_ADI_MSK(0x00000400,uint32_t))  /* ADDR: Address bit is high */
-
-#define BITM_UART_STAT_ASTKY                 (_ADI_MSK(0x00000200,uint32_t))  /* Address Sticky */
-#define ENUM_UART_STAT_ADDR_LO_STKY          (_ADI_MSK(0x00000000,uint32_t))  /* ASTKY: ADDR bit has not been set */
-#define ENUM_UART_STAT_ADDR_HI_STKY          (_ADI_MSK(0x00000200,uint32_t))  /* ASTKY: ADDR bit has been set */
-
-#define BITM_UART_STAT_TFI                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmission Finished Indicator */
-#define ENUM_UART_STAT_TX_NOT_DONE           (_ADI_MSK(0x00000000,uint32_t))  /* TFI: TEMT did not transition from 0 to 1 */
-#define ENUM_UART_STAT_TX_DONE               (_ADI_MSK(0x00000100,uint32_t))  /* TFI: TEMT transition from 0 to 1 */
-
-#define BITM_UART_STAT_TEMT                  (_ADI_MSK(0x00000080,uint32_t))  /* TSR and THR Empty */
-#define ENUM_UART_STAT_TX_NOT_EMPTY          (_ADI_MSK(0x00000000,uint32_t))  /* TEMT: Not empty TSR/THR */
-#define ENUM_UART_STAT_TX_EMPTY              (_ADI_MSK(0x00000080,uint32_t))  /* TEMT: TSR/THR Empty */
-
-#define BITM_UART_STAT_THRE                  (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Hold Register Empty */
-#define ENUM_UART_STAT_THR_NOT_EMPTY         (_ADI_MSK(0x00000000,uint32_t))  /* THRE: Not empty THR/TAIP */
-#define ENUM_UART_STAT_THR_EMPTY             (_ADI_MSK(0x00000020,uint32_t))  /* THRE: Empty THR/TAIP */
-
-#define BITM_UART_STAT_BI                    (_ADI_MSK(0x00000010,uint32_t))  /* Break Indicator */
-#define ENUM_UART_STAT_NO_BREAK_INT          (_ADI_MSK(0x00000000,uint32_t))  /* BI: No break interrupt */
-#define ENUM_UART_STAT_BREAK_INT             (_ADI_MSK(0x00000010,uint32_t))  /* BI: Break interrupt */
-
-#define BITM_UART_STAT_FE                    (_ADI_MSK(0x00000008,uint32_t))  /* Framing Error */
-#define ENUM_UART_STAT_NO_FRAMING_ERR        (_ADI_MSK(0x00000000,uint32_t))  /* FE: No error */
-#define ENUM_UART_STAT_FRAMING_ERR           (_ADI_MSK(0x00000008,uint32_t))  /* FE: Invalid stop bit error */
-
-#define BITM_UART_STAT_PE                    (_ADI_MSK(0x00000004,uint32_t))  /* Parity Error */
-#define ENUM_UART_STAT_NO_PARITY_ERR         (_ADI_MSK(0x00000000,uint32_t))  /* PE: No parity error */
-#define ENUM_UART_STAT_PARITY_ERR            (_ADI_MSK(0x00000004,uint32_t))  /* PE: Parity error */
-
-#define BITM_UART_STAT_OE                    (_ADI_MSK(0x00000002,uint32_t))  /* Overrun Error */
-#define ENUM_UART_STAT_NO_OVR_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* OE: No overrun */
-#define ENUM_UART_STAT_OVR_ERR               (_ADI_MSK(0x00000002,uint32_t))  /* OE: Overrun error */
-
-#define BITM_UART_STAT_DR                    (_ADI_MSK(0x00000001,uint32_t))  /* Data Ready */
-#define ENUM_UART_STAT_NO_DATA               (_ADI_MSK(0x00000000,uint32_t))  /* DR: No new data */
-#define ENUM_UART_STAT_NEW_DATA              (_ADI_MSK(0x00000001,uint32_t))  /* DR: New data in RBR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_SCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_SCR_VALUE                   0                               /* Stored 8-bit Data */
-#define BITM_UART_SCR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Stored 8-bit Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_CLK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_CLK_EDBO                   31                               /* Enable Divide By One */
-#define BITP_UART_CLK_DIV                     0                               /* Divisor */
-
-#define BITM_UART_CLK_EDBO                   (_ADI_MSK(0x80000000,uint32_t))  /* Enable Divide By One */
-#define ENUM_UART_CLK_DIS_DIV_BY_ONE         (_ADI_MSK(0x00000000,uint32_t))  /* EDBO: Bit clock prescaler = 16 */
-#define ENUM_UART_CLK_EN_DIV_BY_ONE          (_ADI_MSK(0x80000000,uint32_t))  /* EDBO: Bit clock prescaler = 1 */
-#define BITM_UART_CLK_DIV                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_ETXS                   9                               /* Enable TX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ERXS                   8                               /* Enable RX to Status Interrupt Mask Status */
-#define BITP_UART_IMSK_EAWI                   7                               /* Enable Address Word Interrupt Mask Status */
-#define BITP_UART_IMSK_ERFCI                  6                               /* Enable Receive FIFO Count Interrupt Mask Status */
-#define BITP_UART_IMSK_ETFI                   5                               /* Enable Transmission Finished Interrupt Mask Status */
-#define BITP_UART_IMSK_EDTPTI                 4                               /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define BITP_UART_IMSK_EDSSI                  3                               /* Enable Modem Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ELSI                   2                               /* Enable Line Status Interrupt Mask Status */
-#define BITP_UART_IMSK_ETBEI                  1                               /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define BITP_UART_IMSK_ERBFI                  0                               /* Enable Receive Buffer Full Interrupt Mask Status */
-
-#define BITM_UART_IMSK_ETXS                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Status */
-#define ENUM_UART_ETXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETXS: Interrupt is masked */
-#define ENUM_UART_ETXS_HI                    (_ADI_MSK(0x00000200,uint32_t))  /* ETXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERXS                  (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Status */
-#define ENUM_UART_ERXS_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ERXS: Interrupt is masked */
-#define ENUM_UART_ERXS_HI                    (_ADI_MSK(0x00000100,uint32_t))  /* ERXS: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EAWI                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Status */
-#define ENUM_UART_EAWI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* EAWI: Interrupt is masked */
-#define ENUM_UART_EAWI_HI                    (_ADI_MSK(0x00000080,uint32_t))  /* EAWI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERFCI                 (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Status */
-#define ENUM_UART_ERFCI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERFCI: Interrupt is masked */
-#define ENUM_UART_ERFCI_HI                   (_ADI_MSK(0x00000040,uint32_t))  /* ERFCI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETFI                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Status */
-#define ENUM_UART_ETFI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ETFI: Interrupt is masked */
-#define ENUM_UART_ETFI_HI                    (_ADI_MSK(0x00000020,uint32_t))  /* ETFI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDTPTI                (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Trigerred Interrupt Mask Status */
-#define ENUM_UART_EDTPTI_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* EDTPTI: Interrupt is masked */
-#define ENUM_UART_EDTPTI_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* EDTPTI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_EDSSI                 (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Status */
-#define ENUM_UART_EDSSI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* EDSSI: Interrupt is masked */
-#define ENUM_UART_EDSSI_HI                   (_ADI_MSK(0x00000008,uint32_t))  /* EDSSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ELSI                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Status */
-#define ENUM_UART_ELSI_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* ELSI: Interrupt is masked */
-#define ENUM_UART_ELSI_HI                    (_ADI_MSK(0x00000004,uint32_t))  /* ELSI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ETBEI                 (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Status */
-#define ENUM_UART_ETBEI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ETBEI: Interrupt is masked */
-#define ENUM_UART_ETBEI_HI                   (_ADI_MSK(0x00000002,uint32_t))  /* ETBEI: Interrupt is unmasked */
-
-#define BITM_UART_IMSK_ERBFI                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Status */
-#define ENUM_UART_ERBFI_LO                   (_ADI_MSK(0x00000000,uint32_t))  /* ERBFI: Interrupt is masked */
-#define ENUM_UART_ERBFI_HI                   (_ADI_MSK(0x00000001,uint32_t))  /* ERBFI: Interrupt is unmasked */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_SET_ETXS               9                               /* Enable TX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERXS               8                               /* Enable RX to Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EAWI               7                               /* Enable Address Word Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_EDSSI              3                               /* Enable Modem Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ELSI               2                               /* Enable Line Status Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITP_UART_IMSK_SET_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* The fields and enumerations for UART_IMSK_SET are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_SET_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Set */
-#define BITM_UART_IMSK_SET_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_IMSK_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_IMSK_CLR_ETXS               9                               /* Enable TX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERXS               8                               /* Enable RX to Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EAWI               7                               /* Enable Address Word Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERFCI              6                               /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETFI               5                               /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDTPTI             4                               /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_EDSSI              3                               /* Enable Modem Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ELSI               2                               /* Enable Line Status Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ETBEI              1                               /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITP_UART_IMSK_CLR_ERBFI              0                               /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* The fields and enumerations for UART_IMSK_CLR are also in UART - see the common set of ENUM_UART_* #defines located with register UART_IMSK */
-
-#define BITM_UART_IMSK_CLR_ETXS              (_ADI_MSK(0x00000200,uint32_t))  /* Enable TX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERXS              (_ADI_MSK(0x00000100,uint32_t))  /* Enable RX to Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EAWI              (_ADI_MSK(0x00000080,uint32_t))  /* Enable Address Word Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERFCI             (_ADI_MSK(0x00000040,uint32_t))  /* Enable Receive FIFO Count Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETFI              (_ADI_MSK(0x00000020,uint32_t))  /* Enable Transmission Finished Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDTPTI            (_ADI_MSK(0x00000010,uint32_t))  /* Enable DMA TX Peripheral Triggered Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_EDSSI             (_ADI_MSK(0x00000008,uint32_t))  /* Enable Modem Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ELSI              (_ADI_MSK(0x00000004,uint32_t))  /* Enable Line Status Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ETBEI             (_ADI_MSK(0x00000002,uint32_t))  /* Enable Transmit Buffer Empty Interrupt Mask Clear */
-#define BITM_UART_IMSK_CLR_ERBFI             (_ADI_MSK(0x00000001,uint32_t))  /* Enable Receive Buffer Full Interrupt Mask Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RBR_VALUE                   0                               /* 8-bit data */
-#define BITM_UART_RBR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_THR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_THR_VALUE                   0                               /* 8 bit data */
-#define BITM_UART_THR_VALUE                  (_ADI_MSK(0x000000FF,uint32_t))  /* 8 bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TAIP                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TAIP_VALUE                  0                               /* 8-bit data */
-#define BITM_UART_TAIP_VALUE                 (_ADI_MSK(0x000000FF,uint32_t))  /* 8-bit data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TSR_VALUE                   0                               /* Contents of TSR */
-#define BITM_UART_TSR_VALUE                  (_ADI_MSK(0x000007FF,uint32_t))  /* Contents of TSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RSR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RSR_VALUE                   0                               /* Contents of RSR */
-#define BITM_UART_RSR_VALUE                  (_ADI_MSK(0x000003FF,uint32_t))  /* Contents of RSR */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_TXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_TXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_TXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        UART_RXCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_UART_RXCNT_VALUE                 0                               /* 16-bit Counter Value */
-#define BITM_UART_RXCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* 16-bit Counter Value */
-
-/* ==================================================
-        General Purpose Input/Output Registers
-   ================================================== */
-
-/* =========================
-        PORTA
-   ========================= */
-#define REG_PORTA_FER                   0xFFC03000         /* PORTA Port x Function Enable Register */
-#define REG_PORTA_FER_SET               0xFFC03004         /* PORTA Port x Function Enable Set Register */
-#define REG_PORTA_FER_CLR               0xFFC03008         /* PORTA Port x Function Enable Clear Register */
-#define REG_PORTA_DATA                  0xFFC0300C         /* PORTA Port x GPIO Data Register */
-#define REG_PORTA_DATA_SET              0xFFC03010         /* PORTA Port x GPIO Data Set Register */
-#define REG_PORTA_DATA_CLR              0xFFC03014         /* PORTA Port x GPIO Data Clear Register */
-#define REG_PORTA_DIR                   0xFFC03018         /* PORTA Port x GPIO Direction Register */
-#define REG_PORTA_DIR_SET               0xFFC0301C         /* PORTA Port x GPIO Direction Set Register */
-#define REG_PORTA_DIR_CLR               0xFFC03020         /* PORTA Port x GPIO Direction Clear Register */
-#define REG_PORTA_INEN                  0xFFC03024         /* PORTA Port x GPIO Input Enable Register */
-#define REG_PORTA_INEN_SET              0xFFC03028         /* PORTA Port x GPIO Input Enable Set Register */
-#define REG_PORTA_INEN_CLR              0xFFC0302C         /* PORTA Port x GPIO Input Enable Clear Register */
-#define REG_PORTA_MUX                   0xFFC03030         /* PORTA Port x Multiplexer Control Register */
-#define REG_PORTA_DATA_TGL              0xFFC03034         /* PORTA Port x GPIO Input Enable Toggle Register */
-#define REG_PORTA_POL                   0xFFC03038         /* PORTA Port x GPIO Polarity Invert Register */
-#define REG_PORTA_POL_SET               0xFFC0303C         /* PORTA Port x GPIO Polarity Invert Set Register */
-#define REG_PORTA_POL_CLR               0xFFC03040         /* PORTA Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTA_LOCK                  0xFFC03044         /* PORTA Port x GPIO Lock Register */
-#define REG_PORTA_REVID                 0xFFC0307C         /* PORTA Port x GPIO Revision ID */
-
-/* =========================
-        PORTB
-   ========================= */
-#define REG_PORTB_FER                   0xFFC03080         /* PORTB Port x Function Enable Register */
-#define REG_PORTB_FER_SET               0xFFC03084         /* PORTB Port x Function Enable Set Register */
-#define REG_PORTB_FER_CLR               0xFFC03088         /* PORTB Port x Function Enable Clear Register */
-#define REG_PORTB_DATA                  0xFFC0308C         /* PORTB Port x GPIO Data Register */
-#define REG_PORTB_DATA_SET              0xFFC03090         /* PORTB Port x GPIO Data Set Register */
-#define REG_PORTB_DATA_CLR              0xFFC03094         /* PORTB Port x GPIO Data Clear Register */
-#define REG_PORTB_DIR                   0xFFC03098         /* PORTB Port x GPIO Direction Register */
-#define REG_PORTB_DIR_SET               0xFFC0309C         /* PORTB Port x GPIO Direction Set Register */
-#define REG_PORTB_DIR_CLR               0xFFC030A0         /* PORTB Port x GPIO Direction Clear Register */
-#define REG_PORTB_INEN                  0xFFC030A4         /* PORTB Port x GPIO Input Enable Register */
-#define REG_PORTB_INEN_SET              0xFFC030A8         /* PORTB Port x GPIO Input Enable Set Register */
-#define REG_PORTB_INEN_CLR              0xFFC030AC         /* PORTB Port x GPIO Input Enable Clear Register */
-#define REG_PORTB_MUX                   0xFFC030B0         /* PORTB Port x Multiplexer Control Register */
-#define REG_PORTB_DATA_TGL              0xFFC030B4         /* PORTB Port x GPIO Input Enable Toggle Register */
-#define REG_PORTB_POL                   0xFFC030B8         /* PORTB Port x GPIO Polarity Invert Register */
-#define REG_PORTB_POL_SET               0xFFC030BC         /* PORTB Port x GPIO Polarity Invert Set Register */
-#define REG_PORTB_POL_CLR               0xFFC030C0         /* PORTB Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTB_LOCK                  0xFFC030C4         /* PORTB Port x GPIO Lock Register */
-#define REG_PORTB_REVID                 0xFFC030FC         /* PORTB Port x GPIO Revision ID */
-
-/* =========================
-        PORTC
-   ========================= */
-#define REG_PORTC_FER                   0xFFC03100         /* PORTC Port x Function Enable Register */
-#define REG_PORTC_FER_SET               0xFFC03104         /* PORTC Port x Function Enable Set Register */
-#define REG_PORTC_FER_CLR               0xFFC03108         /* PORTC Port x Function Enable Clear Register */
-#define REG_PORTC_DATA                  0xFFC0310C         /* PORTC Port x GPIO Data Register */
-#define REG_PORTC_DATA_SET              0xFFC03110         /* PORTC Port x GPIO Data Set Register */
-#define REG_PORTC_DATA_CLR              0xFFC03114         /* PORTC Port x GPIO Data Clear Register */
-#define REG_PORTC_DIR                   0xFFC03118         /* PORTC Port x GPIO Direction Register */
-#define REG_PORTC_DIR_SET               0xFFC0311C         /* PORTC Port x GPIO Direction Set Register */
-#define REG_PORTC_DIR_CLR               0xFFC03120         /* PORTC Port x GPIO Direction Clear Register */
-#define REG_PORTC_INEN                  0xFFC03124         /* PORTC Port x GPIO Input Enable Register */
-#define REG_PORTC_INEN_SET              0xFFC03128         /* PORTC Port x GPIO Input Enable Set Register */
-#define REG_PORTC_INEN_CLR              0xFFC0312C         /* PORTC Port x GPIO Input Enable Clear Register */
-#define REG_PORTC_MUX                   0xFFC03130         /* PORTC Port x Multiplexer Control Register */
-#define REG_PORTC_DATA_TGL              0xFFC03134         /* PORTC Port x GPIO Input Enable Toggle Register */
-#define REG_PORTC_POL                   0xFFC03138         /* PORTC Port x GPIO Polarity Invert Register */
-#define REG_PORTC_POL_SET               0xFFC0313C         /* PORTC Port x GPIO Polarity Invert Set Register */
-#define REG_PORTC_POL_CLR               0xFFC03140         /* PORTC Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTC_LOCK                  0xFFC03144         /* PORTC Port x GPIO Lock Register */
-#define REG_PORTC_REVID                 0xFFC0317C         /* PORTC Port x GPIO Revision ID */
-
-/* =========================
-        PORTD
-   ========================= */
-#define REG_PORTD_FER                   0xFFC03180         /* PORTD Port x Function Enable Register */
-#define REG_PORTD_FER_SET               0xFFC03184         /* PORTD Port x Function Enable Set Register */
-#define REG_PORTD_FER_CLR               0xFFC03188         /* PORTD Port x Function Enable Clear Register */
-#define REG_PORTD_DATA                  0xFFC0318C         /* PORTD Port x GPIO Data Register */
-#define REG_PORTD_DATA_SET              0xFFC03190         /* PORTD Port x GPIO Data Set Register */
-#define REG_PORTD_DATA_CLR              0xFFC03194         /* PORTD Port x GPIO Data Clear Register */
-#define REG_PORTD_DIR                   0xFFC03198         /* PORTD Port x GPIO Direction Register */
-#define REG_PORTD_DIR_SET               0xFFC0319C         /* PORTD Port x GPIO Direction Set Register */
-#define REG_PORTD_DIR_CLR               0xFFC031A0         /* PORTD Port x GPIO Direction Clear Register */
-#define REG_PORTD_INEN                  0xFFC031A4         /* PORTD Port x GPIO Input Enable Register */
-#define REG_PORTD_INEN_SET              0xFFC031A8         /* PORTD Port x GPIO Input Enable Set Register */
-#define REG_PORTD_INEN_CLR              0xFFC031AC         /* PORTD Port x GPIO Input Enable Clear Register */
-#define REG_PORTD_MUX                   0xFFC031B0         /* PORTD Port x Multiplexer Control Register */
-#define REG_PORTD_DATA_TGL              0xFFC031B4         /* PORTD Port x GPIO Input Enable Toggle Register */
-#define REG_PORTD_POL                   0xFFC031B8         /* PORTD Port x GPIO Polarity Invert Register */
-#define REG_PORTD_POL_SET               0xFFC031BC         /* PORTD Port x GPIO Polarity Invert Set Register */
-#define REG_PORTD_POL_CLR               0xFFC031C0         /* PORTD Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTD_LOCK                  0xFFC031C4         /* PORTD Port x GPIO Lock Register */
-#define REG_PORTD_REVID                 0xFFC031FC         /* PORTD Port x GPIO Revision ID */
-
-/* =========================
-        PORTE
-   ========================= */
-#define REG_PORTE_FER                   0xFFC03200         /* PORTE Port x Function Enable Register */
-#define REG_PORTE_FER_SET               0xFFC03204         /* PORTE Port x Function Enable Set Register */
-#define REG_PORTE_FER_CLR               0xFFC03208         /* PORTE Port x Function Enable Clear Register */
-#define REG_PORTE_DATA                  0xFFC0320C         /* PORTE Port x GPIO Data Register */
-#define REG_PORTE_DATA_SET              0xFFC03210         /* PORTE Port x GPIO Data Set Register */
-#define REG_PORTE_DATA_CLR              0xFFC03214         /* PORTE Port x GPIO Data Clear Register */
-#define REG_PORTE_DIR                   0xFFC03218         /* PORTE Port x GPIO Direction Register */
-#define REG_PORTE_DIR_SET               0xFFC0321C         /* PORTE Port x GPIO Direction Set Register */
-#define REG_PORTE_DIR_CLR               0xFFC03220         /* PORTE Port x GPIO Direction Clear Register */
-#define REG_PORTE_INEN                  0xFFC03224         /* PORTE Port x GPIO Input Enable Register */
-#define REG_PORTE_INEN_SET              0xFFC03228         /* PORTE Port x GPIO Input Enable Set Register */
-#define REG_PORTE_INEN_CLR              0xFFC0322C         /* PORTE Port x GPIO Input Enable Clear Register */
-#define REG_PORTE_MUX                   0xFFC03230         /* PORTE Port x Multiplexer Control Register */
-#define REG_PORTE_DATA_TGL              0xFFC03234         /* PORTE Port x GPIO Input Enable Toggle Register */
-#define REG_PORTE_POL                   0xFFC03238         /* PORTE Port x GPIO Polarity Invert Register */
-#define REG_PORTE_POL_SET               0xFFC0323C         /* PORTE Port x GPIO Polarity Invert Set Register */
-#define REG_PORTE_POL_CLR               0xFFC03240         /* PORTE Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTE_LOCK                  0xFFC03244         /* PORTE Port x GPIO Lock Register */
-#define REG_PORTE_REVID                 0xFFC0327C         /* PORTE Port x GPIO Revision ID */
-
-/* =========================
-        PORTF
-   ========================= */
-#define REG_PORTF_FER                   0xFFC03280         /* PORTF Port x Function Enable Register */
-#define REG_PORTF_FER_SET               0xFFC03284         /* PORTF Port x Function Enable Set Register */
-#define REG_PORTF_FER_CLR               0xFFC03288         /* PORTF Port x Function Enable Clear Register */
-#define REG_PORTF_DATA                  0xFFC0328C         /* PORTF Port x GPIO Data Register */
-#define REG_PORTF_DATA_SET              0xFFC03290         /* PORTF Port x GPIO Data Set Register */
-#define REG_PORTF_DATA_CLR              0xFFC03294         /* PORTF Port x GPIO Data Clear Register */
-#define REG_PORTF_DIR                   0xFFC03298         /* PORTF Port x GPIO Direction Register */
-#define REG_PORTF_DIR_SET               0xFFC0329C         /* PORTF Port x GPIO Direction Set Register */
-#define REG_PORTF_DIR_CLR               0xFFC032A0         /* PORTF Port x GPIO Direction Clear Register */
-#define REG_PORTF_INEN                  0xFFC032A4         /* PORTF Port x GPIO Input Enable Register */
-#define REG_PORTF_INEN_SET              0xFFC032A8         /* PORTF Port x GPIO Input Enable Set Register */
-#define REG_PORTF_INEN_CLR              0xFFC032AC         /* PORTF Port x GPIO Input Enable Clear Register */
-#define REG_PORTF_MUX                   0xFFC032B0         /* PORTF Port x Multiplexer Control Register */
-#define REG_PORTF_DATA_TGL              0xFFC032B4         /* PORTF Port x GPIO Input Enable Toggle Register */
-#define REG_PORTF_POL                   0xFFC032B8         /* PORTF Port x GPIO Polarity Invert Register */
-#define REG_PORTF_POL_SET               0xFFC032BC         /* PORTF Port x GPIO Polarity Invert Set Register */
-#define REG_PORTF_POL_CLR               0xFFC032C0         /* PORTF Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTF_LOCK                  0xFFC032C4         /* PORTF Port x GPIO Lock Register */
-#define REG_PORTF_REVID                 0xFFC032FC         /* PORTF Port x GPIO Revision ID */
-
-/* =========================
-        PORTG
-   ========================= */
-#define REG_PORTG_FER                   0xFFC03300         /* PORTG Port x Function Enable Register */
-#define REG_PORTG_FER_SET               0xFFC03304         /* PORTG Port x Function Enable Set Register */
-#define REG_PORTG_FER_CLR               0xFFC03308         /* PORTG Port x Function Enable Clear Register */
-#define REG_PORTG_DATA                  0xFFC0330C         /* PORTG Port x GPIO Data Register */
-#define REG_PORTG_DATA_SET              0xFFC03310         /* PORTG Port x GPIO Data Set Register */
-#define REG_PORTG_DATA_CLR              0xFFC03314         /* PORTG Port x GPIO Data Clear Register */
-#define REG_PORTG_DIR                   0xFFC03318         /* PORTG Port x GPIO Direction Register */
-#define REG_PORTG_DIR_SET               0xFFC0331C         /* PORTG Port x GPIO Direction Set Register */
-#define REG_PORTG_DIR_CLR               0xFFC03320         /* PORTG Port x GPIO Direction Clear Register */
-#define REG_PORTG_INEN                  0xFFC03324         /* PORTG Port x GPIO Input Enable Register */
-#define REG_PORTG_INEN_SET              0xFFC03328         /* PORTG Port x GPIO Input Enable Set Register */
-#define REG_PORTG_INEN_CLR              0xFFC0332C         /* PORTG Port x GPIO Input Enable Clear Register */
-#define REG_PORTG_MUX                   0xFFC03330         /* PORTG Port x Multiplexer Control Register */
-#define REG_PORTG_DATA_TGL              0xFFC03334         /* PORTG Port x GPIO Input Enable Toggle Register */
-#define REG_PORTG_POL                   0xFFC03338         /* PORTG Port x GPIO Polarity Invert Register */
-#define REG_PORTG_POL_SET               0xFFC0333C         /* PORTG Port x GPIO Polarity Invert Set Register */
-#define REG_PORTG_POL_CLR               0xFFC03340         /* PORTG Port x GPIO Polarity Invert Clear Register */
-#define REG_PORTG_LOCK                  0xFFC03344         /* PORTG Port x GPIO Lock Register */
-#define REG_PORTG_REVID                 0xFFC0337C         /* PORTG Port x GPIO Revision ID */
-
-/* =========================
-        PORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_PX15                   15                               /* Port x Bit 15 Mode */
-#define BITP_PORT_FER_PX14                   14                               /* Port x Bit 14 Mode */
-#define BITP_PORT_FER_PX13                   13                               /* Port x Bit 13 Mode */
-#define BITP_PORT_FER_PX12                   12                               /* Port x Bit 12 Mode */
-#define BITP_PORT_FER_PX11                   11                               /* Port x Bit 11 Mode */
-#define BITP_PORT_FER_PX10                   10                               /* Port x Bit 10 Mode */
-#define BITP_PORT_FER_PX9                     9                               /* Port x Bit 9 Mode */
-#define BITP_PORT_FER_PX8                     8                               /* Port x Bit 8 Mode */
-#define BITP_PORT_FER_PX7                     7                               /* Port x Bit 7 Mode */
-#define BITP_PORT_FER_PX6                     6                               /* Port x Bit 6 Mode */
-#define BITP_PORT_FER_PX5                     5                               /* Port x Bit 5 Mode */
-#define BITP_PORT_FER_PX4                     4                               /* Port x Bit 4 Mode */
-#define BITP_PORT_FER_PX3                     3                               /* Port x Bit 3 Mode */
-#define BITP_PORT_FER_PX2                     2                               /* Port x Bit 2 Mode */
-#define BITP_PORT_FER_PX1                     1                               /* Port x Bit 1 Mode */
-#define BITP_PORT_FER_PX0                     0                               /* Port x Bit 0 Mode */
-#define BITM_PORT_FER_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode */
-#define BITM_PORT_FER_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode */
-#define BITM_PORT_FER_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode */
-#define BITM_PORT_FER_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode */
-#define BITM_PORT_FER_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode */
-#define BITM_PORT_FER_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode */
-#define BITM_PORT_FER_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode */
-#define BITM_PORT_FER_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode */
-#define BITM_PORT_FER_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode */
-#define BITM_PORT_FER_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode */
-#define BITM_PORT_FER_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode */
-#define BITM_PORT_FER_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode */
-#define BITM_PORT_FER_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode */
-#define BITM_PORT_FER_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode */
-#define BITM_PORT_FER_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode */
-#define BITM_PORT_FER_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_SET_PX15               15                               /* Port x Bit 15 Mode Set */
-#define BITP_PORT_FER_SET_PX14               14                               /* Port x Bit 14 Mode Set */
-#define BITP_PORT_FER_SET_PX13               13                               /* Port x Bit 13 Mode Set */
-#define BITP_PORT_FER_SET_PX12               12                               /* Port x Bit 12 Mode Set */
-#define BITP_PORT_FER_SET_PX11               11                               /* Port x Bit 11 Mode Set */
-#define BITP_PORT_FER_SET_PX10               10                               /* Port x Bit 10 Mode Set */
-#define BITP_PORT_FER_SET_PX9                 9                               /* Port x Bit 9 Mode Set */
-#define BITP_PORT_FER_SET_PX8                 8                               /* Port x Bit 8 Mode Set */
-#define BITP_PORT_FER_SET_PX7                 7                               /* Port x Bit 7 Mode Set */
-#define BITP_PORT_FER_SET_PX6                 6                               /* Port x Bit 6 Mode Set */
-#define BITP_PORT_FER_SET_PX5                 5                               /* Port x Bit 5 Mode Set */
-#define BITP_PORT_FER_SET_PX4                 4                               /* Port x Bit 4 Mode Set */
-#define BITP_PORT_FER_SET_PX3                 3                               /* Port x Bit 3 Mode Set */
-#define BITP_PORT_FER_SET_PX2                 2                               /* Port x Bit 2 Mode Set */
-#define BITP_PORT_FER_SET_PX1                 1                               /* Port x Bit 1 Mode Set */
-#define BITP_PORT_FER_SET_PX0                 0                               /* Port x Bit 0 Mode Set */
-#define BITM_PORT_FER_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Set */
-#define BITM_PORT_FER_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Set */
-#define BITM_PORT_FER_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Set */
-#define BITM_PORT_FER_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Set */
-#define BITM_PORT_FER_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Set */
-#define BITM_PORT_FER_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Set */
-#define BITM_PORT_FER_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Set */
-#define BITM_PORT_FER_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Set */
-#define BITM_PORT_FER_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Set */
-#define BITM_PORT_FER_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Set */
-#define BITM_PORT_FER_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Set */
-#define BITM_PORT_FER_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Set */
-#define BITM_PORT_FER_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Set */
-#define BITM_PORT_FER_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Set */
-#define BITM_PORT_FER_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Set */
-#define BITM_PORT_FER_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_FER_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_FER_CLR_PX15               15                               /* Port x Bit 15 Mode Clear */
-#define BITP_PORT_FER_CLR_PX14               14                               /* Port x Bit 14 Mode Clear */
-#define BITP_PORT_FER_CLR_PX13               13                               /* Port x Bit 13 Mode Clear */
-#define BITP_PORT_FER_CLR_PX12               12                               /* Port x Bit 12 Mode Clear */
-#define BITP_PORT_FER_CLR_PX11               11                               /* Port x Bit 11 Mode Clear */
-#define BITP_PORT_FER_CLR_PX10               10                               /* Port x Bit 10 Mode Clear */
-#define BITP_PORT_FER_CLR_PX9                 9                               /* Port x Bit 9 Mode Clear */
-#define BITP_PORT_FER_CLR_PX8                 8                               /* Port x Bit 8 Mode Clear */
-#define BITP_PORT_FER_CLR_PX7                 7                               /* Port x Bit 7 Mode Clear */
-#define BITP_PORT_FER_CLR_PX6                 6                               /* Port x Bit 6 Mode Clear */
-#define BITP_PORT_FER_CLR_PX5                 5                               /* Port x Bit 5 Mode Clear */
-#define BITP_PORT_FER_CLR_PX4                 4                               /* Port x Bit 4 Mode Clear */
-#define BITP_PORT_FER_CLR_PX3                 3                               /* Port x Bit 3 Mode Clear */
-#define BITP_PORT_FER_CLR_PX2                 2                               /* Port x Bit 2 Mode Clear */
-#define BITP_PORT_FER_CLR_PX1                 1                               /* Port x Bit 1 Mode Clear */
-#define BITP_PORT_FER_CLR_PX0                 0                               /* Port x Bit 0 Mode Clear */
-#define BITM_PORT_FER_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Mode Clear */
-#define BITM_PORT_FER_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Mode Clear */
-#define BITM_PORT_FER_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Mode Clear */
-#define BITM_PORT_FER_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Mode Clear */
-#define BITM_PORT_FER_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Mode Clear */
-#define BITM_PORT_FER_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Mode Clear */
-#define BITM_PORT_FER_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Mode Clear */
-#define BITM_PORT_FER_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Mode Clear */
-#define BITM_PORT_FER_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Mode Clear */
-#define BITM_PORT_FER_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Mode Clear */
-#define BITM_PORT_FER_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Mode Clear */
-#define BITM_PORT_FER_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Mode Clear */
-#define BITM_PORT_FER_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Mode Clear */
-#define BITM_PORT_FER_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Mode Clear */
-#define BITM_PORT_FER_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Mode Clear */
-#define BITM_PORT_FER_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Mode Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_PX15                  15                               /* Port x Bit 15 Data */
-#define BITP_PORT_DATA_PX14                  14                               /* Port x Bit 14 Data */
-#define BITP_PORT_DATA_PX13                  13                               /* Port x Bit 13 Data */
-#define BITP_PORT_DATA_PX12                  12                               /* Port x Bit 12 Data */
-#define BITP_PORT_DATA_PX11                  11                               /* Port x Bit 11 Data */
-#define BITP_PORT_DATA_PX10                  10                               /* Port x Bit 10 Data */
-#define BITP_PORT_DATA_PX9                    9                               /* Port x Bit 9 Data */
-#define BITP_PORT_DATA_PX8                    8                               /* Port x Bit 8 Data */
-#define BITP_PORT_DATA_PX7                    7                               /* Port x Bit 7 Data */
-#define BITP_PORT_DATA_PX6                    6                               /* Port x Bit 6 Data */
-#define BITP_PORT_DATA_PX5                    5                               /* Port x Bit 5 Data */
-#define BITP_PORT_DATA_PX4                    4                               /* Port x Bit 4 Data */
-#define BITP_PORT_DATA_PX3                    3                               /* Port x Bit 3 Data */
-#define BITP_PORT_DATA_PX2                    2                               /* Port x Bit 2 Data */
-#define BITP_PORT_DATA_PX1                    1                               /* Port x Bit 1 Data */
-#define BITP_PORT_DATA_PX0                    0                               /* Port x Bit 0 Data */
-#define BITM_PORT_DATA_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data */
-#define BITM_PORT_DATA_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data */
-#define BITM_PORT_DATA_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data */
-#define BITM_PORT_DATA_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data */
-#define BITM_PORT_DATA_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data */
-#define BITM_PORT_DATA_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data */
-#define BITM_PORT_DATA_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data */
-#define BITM_PORT_DATA_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data */
-#define BITM_PORT_DATA_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data */
-#define BITM_PORT_DATA_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data */
-#define BITM_PORT_DATA_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data */
-#define BITM_PORT_DATA_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data */
-#define BITM_PORT_DATA_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data */
-#define BITM_PORT_DATA_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data */
-#define BITM_PORT_DATA_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data */
-#define BITM_PORT_DATA_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_SET_PX15              15                               /* Port x Bit 15 Data Set */
-#define BITP_PORT_DATA_SET_PX14              14                               /* Port x Bit 14 Data Set */
-#define BITP_PORT_DATA_SET_PX13              13                               /* Port x Bit 13 Data Set */
-#define BITP_PORT_DATA_SET_PX12              12                               /* Port x Bit 12 Data Set */
-#define BITP_PORT_DATA_SET_PX11              11                               /* Port x Bit 11 Data Set */
-#define BITP_PORT_DATA_SET_PX10              10                               /* Port x Bit 10 Data Set */
-#define BITP_PORT_DATA_SET_PX9                9                               /* Port x Bit 9 Data Set */
-#define BITP_PORT_DATA_SET_PX8                8                               /* Port x Bit 8 Data Set */
-#define BITP_PORT_DATA_SET_PX7                7                               /* Port x Bit 7 Data Set */
-#define BITP_PORT_DATA_SET_PX6                6                               /* Port x Bit 6 Data Set */
-#define BITP_PORT_DATA_SET_PX5                5                               /* Port x Bit 5 Data Set */
-#define BITP_PORT_DATA_SET_PX4                4                               /* Port x Bit 4 Data Set */
-#define BITP_PORT_DATA_SET_PX3                3                               /* Port x Bit 3 Data Set */
-#define BITP_PORT_DATA_SET_PX2                2                               /* Port x Bit 2 Data Set */
-#define BITP_PORT_DATA_SET_PX1                1                               /* Port x Bit 1 Data Set */
-#define BITP_PORT_DATA_SET_PX0                0                               /* Port x Bit 0 Data Set */
-#define BITM_PORT_DATA_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Set */
-#define BITM_PORT_DATA_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Set */
-#define BITM_PORT_DATA_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Set */
-#define BITM_PORT_DATA_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Set */
-#define BITM_PORT_DATA_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Set */
-#define BITM_PORT_DATA_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Set */
-#define BITM_PORT_DATA_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Set */
-#define BITM_PORT_DATA_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Set */
-#define BITM_PORT_DATA_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Set */
-#define BITM_PORT_DATA_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Set */
-#define BITM_PORT_DATA_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Set */
-#define BITM_PORT_DATA_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Set */
-#define BITM_PORT_DATA_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Set */
-#define BITM_PORT_DATA_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Set */
-#define BITM_PORT_DATA_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Set */
-#define BITM_PORT_DATA_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_CLR_PX15              15                               /* Port x Bit 15 Data Clear */
-#define BITP_PORT_DATA_CLR_PX14              14                               /* Port x Bit 14 Data Clear */
-#define BITP_PORT_DATA_CLR_PX13              13                               /* Port x Bit 13 Data Clear */
-#define BITP_PORT_DATA_CLR_PX12              12                               /* Port x Bit 12 Data Clear */
-#define BITP_PORT_DATA_CLR_PX11              11                               /* Port x Bit 11 Data Clear */
-#define BITP_PORT_DATA_CLR_PX10              10                               /* Port x Bit 10 Data Clear */
-#define BITP_PORT_DATA_CLR_PX9                9                               /* Port x Bit 9 Data Clear */
-#define BITP_PORT_DATA_CLR_PX8                8                               /* Port x Bit 8 Data Clear */
-#define BITP_PORT_DATA_CLR_PX7                7                               /* Port x Bit 7 Data Clear */
-#define BITP_PORT_DATA_CLR_PX6                6                               /* Port x Bit 6 Data Clear */
-#define BITP_PORT_DATA_CLR_PX5                5                               /* Port x Bit 5 Data Clear */
-#define BITP_PORT_DATA_CLR_PX4                4                               /* Port x Bit 4 Data Clear */
-#define BITP_PORT_DATA_CLR_PX3                3                               /* Port x Bit 3 Data Clear */
-#define BITP_PORT_DATA_CLR_PX2                2                               /* Port x Bit 2 Data Clear */
-#define BITP_PORT_DATA_CLR_PX1                1                               /* Port x Bit 1 Data Clear */
-#define BITP_PORT_DATA_CLR_PX0                0                               /* Port x Bit 0 Data Clear */
-#define BITM_PORT_DATA_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Data Clear */
-#define BITM_PORT_DATA_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Data Clear */
-#define BITM_PORT_DATA_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Data Clear */
-#define BITM_PORT_DATA_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Data Clear */
-#define BITM_PORT_DATA_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Data Clear */
-#define BITM_PORT_DATA_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Data Clear */
-#define BITM_PORT_DATA_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Data Clear */
-#define BITM_PORT_DATA_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Data Clear */
-#define BITM_PORT_DATA_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Data Clear */
-#define BITM_PORT_DATA_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Data Clear */
-#define BITM_PORT_DATA_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Data Clear */
-#define BITM_PORT_DATA_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Data Clear */
-#define BITM_PORT_DATA_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Data Clear */
-#define BITM_PORT_DATA_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Data Clear */
-#define BITM_PORT_DATA_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Data Clear */
-#define BITM_PORT_DATA_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Data Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_PX15                   15                               /* Port x Bit 15 Direction */
-#define BITP_PORT_DIR_PX14                   14                               /* Port x Bit 14 Direction */
-#define BITP_PORT_DIR_PX13                   13                               /* Port x Bit 13 Direction */
-#define BITP_PORT_DIR_PX12                   12                               /* Port x Bit 12 Direction */
-#define BITP_PORT_DIR_PX11                   11                               /* Port x Bit 11 Direction */
-#define BITP_PORT_DIR_PX10                   10                               /* Port x Bit 10 Direction */
-#define BITP_PORT_DIR_PX9                     9                               /* Port x Bit 9 Direction */
-#define BITP_PORT_DIR_PX8                     8                               /* Port x Bit 8 Direction */
-#define BITP_PORT_DIR_PX7                     7                               /* Port x Bit 7 Direction */
-#define BITP_PORT_DIR_PX6                     6                               /* Port x Bit 6 Direction */
-#define BITP_PORT_DIR_PX5                     5                               /* Port x Bit 5 Direction */
-#define BITP_PORT_DIR_PX4                     4                               /* Port x Bit 4 Direction */
-#define BITP_PORT_DIR_PX3                     3                               /* Port x Bit 3 Direction */
-#define BITP_PORT_DIR_PX2                     2                               /* Port x Bit 2 Direction */
-#define BITP_PORT_DIR_PX1                     1                               /* Port x Bit 1 Direction */
-#define BITP_PORT_DIR_PX0                     0                               /* Port x Bit 0 Direction */
-#define BITM_PORT_DIR_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction */
-#define BITM_PORT_DIR_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction */
-#define BITM_PORT_DIR_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction */
-#define BITM_PORT_DIR_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction */
-#define BITM_PORT_DIR_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction */
-#define BITM_PORT_DIR_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction */
-#define BITM_PORT_DIR_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction */
-#define BITM_PORT_DIR_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction */
-#define BITM_PORT_DIR_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction */
-#define BITM_PORT_DIR_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction */
-#define BITM_PORT_DIR_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction */
-#define BITM_PORT_DIR_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction */
-#define BITM_PORT_DIR_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction */
-#define BITM_PORT_DIR_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction */
-#define BITM_PORT_DIR_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction */
-#define BITM_PORT_DIR_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_SET_PX15               15                               /* Port x Bit 15 Direction Set */
-#define BITP_PORT_DIR_SET_PX14               14                               /* Port x Bit 14 Direction Set */
-#define BITP_PORT_DIR_SET_PX13               13                               /* Port x Bit 13 Direction Set */
-#define BITP_PORT_DIR_SET_PX12               12                               /* Port x Bit 12 Direction Set */
-#define BITP_PORT_DIR_SET_PX11               11                               /* Port x Bit 11 Direction Set */
-#define BITP_PORT_DIR_SET_PX10               10                               /* Port x Bit 10 Direction Set */
-#define BITP_PORT_DIR_SET_PX9                 9                               /* Port x Bit 9 Direction Set */
-#define BITP_PORT_DIR_SET_PX8                 8                               /* Port x Bit 8 Direction Set */
-#define BITP_PORT_DIR_SET_PX7                 7                               /* Port x Bit 7 Direction Set */
-#define BITP_PORT_DIR_SET_PX6                 6                               /* Port x Bit 6 Direction Set */
-#define BITP_PORT_DIR_SET_PX5                 5                               /* Port x Bit 5 Direction Set */
-#define BITP_PORT_DIR_SET_PX4                 4                               /* Port x Bit 4 Direction Set */
-#define BITP_PORT_DIR_SET_PX3                 3                               /* Port x Bit 3 Direction Set */
-#define BITP_PORT_DIR_SET_PX2                 2                               /* Port x Bit 2 Direction Set */
-#define BITP_PORT_DIR_SET_PX1                 1                               /* Port x Bit 1 Direction Set */
-#define BITP_PORT_DIR_SET_PX0                 0                               /* Port x Bit 0 Direction Set */
-#define BITM_PORT_DIR_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Set */
-#define BITM_PORT_DIR_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Set */
-#define BITM_PORT_DIR_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Set */
-#define BITM_PORT_DIR_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Set */
-#define BITM_PORT_DIR_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Set */
-#define BITM_PORT_DIR_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Set */
-#define BITM_PORT_DIR_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Set */
-#define BITM_PORT_DIR_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Set */
-#define BITM_PORT_DIR_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Set */
-#define BITM_PORT_DIR_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Set */
-#define BITM_PORT_DIR_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Set */
-#define BITM_PORT_DIR_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Set */
-#define BITM_PORT_DIR_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Set */
-#define BITM_PORT_DIR_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Set */
-#define BITM_PORT_DIR_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Set */
-#define BITM_PORT_DIR_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DIR_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DIR_CLR_PX15               15                               /* Port x Bit 15 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX14               14                               /* Port x Bit 14 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX13               13                               /* Port x Bit 13 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX12               12                               /* Port x Bit 12 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX11               11                               /* Port x Bit 11 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX10               10                               /* Port x Bit 10 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX9                 9                               /* Port x Bit 9 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX8                 8                               /* Port x Bit 8 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX7                 7                               /* Port x Bit 7 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX6                 6                               /* Port x Bit 6 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX5                 5                               /* Port x Bit 5 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX4                 4                               /* Port x Bit 4 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX3                 3                               /* Port x Bit 3 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX2                 2                               /* Port x Bit 2 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX1                 1                               /* Port x Bit 1 Direction Clear */
-#define BITP_PORT_DIR_CLR_PX0                 0                               /* Port x Bit 0 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Direction Clear */
-#define BITM_PORT_DIR_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Direction Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_PX15                  15                               /* Port x Bit 15 Input Enable */
-#define BITP_PORT_INEN_PX14                  14                               /* Port x Bit 14 Input Enable */
-#define BITP_PORT_INEN_PX13                  13                               /* Port x Bit 13 Input Enable */
-#define BITP_PORT_INEN_PX12                  12                               /* Port x Bit 12 Input Enable */
-#define BITP_PORT_INEN_PX11                  11                               /* Port x Bit 11 Input Enable */
-#define BITP_PORT_INEN_PX10                  10                               /* Port x Bit 10 Input Enable */
-#define BITP_PORT_INEN_PX9                    9                               /* Port x Bit 9 Input Enable */
-#define BITP_PORT_INEN_PX8                    8                               /* Port x Bit 8 Input Enable */
-#define BITP_PORT_INEN_PX7                    7                               /* Port x Bit 7 Input Enable */
-#define BITP_PORT_INEN_PX6                    6                               /* Port x Bit 6 Input Enable */
-#define BITP_PORT_INEN_PX5                    5                               /* Port x Bit 5 Input Enable */
-#define BITP_PORT_INEN_PX4                    4                               /* Port x Bit 4 Input Enable */
-#define BITP_PORT_INEN_PX3                    3                               /* Port x Bit 3 Input Enable */
-#define BITP_PORT_INEN_PX2                    2                               /* Port x Bit 2 Input Enable */
-#define BITP_PORT_INEN_PX1                    1                               /* Port x Bit 1 Input Enable */
-#define BITP_PORT_INEN_PX0                    0                               /* Port x Bit 0 Input Enable */
-#define BITM_PORT_INEN_PX15                  (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable */
-#define BITM_PORT_INEN_PX14                  (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable */
-#define BITM_PORT_INEN_PX13                  (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable */
-#define BITM_PORT_INEN_PX12                  (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable */
-#define BITM_PORT_INEN_PX11                  (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable */
-#define BITM_PORT_INEN_PX10                  (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable */
-#define BITM_PORT_INEN_PX9                   (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable */
-#define BITM_PORT_INEN_PX8                   (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable */
-#define BITM_PORT_INEN_PX7                   (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable */
-#define BITM_PORT_INEN_PX6                   (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable */
-#define BITM_PORT_INEN_PX5                   (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable */
-#define BITM_PORT_INEN_PX4                   (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable */
-#define BITM_PORT_INEN_PX3                   (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable */
-#define BITM_PORT_INEN_PX2                   (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable */
-#define BITM_PORT_INEN_PX1                   (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable */
-#define BITM_PORT_INEN_PX0                   (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_SET_PX15              15                               /* Port x Bit 15 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX14              14                               /* Port x Bit 14 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX13              13                               /* Port x Bit 13 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX12              12                               /* Port x Bit 12 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX11              11                               /* Port x Bit 11 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX10              10                               /* Port x Bit 10 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX9                9                               /* Port x Bit 9 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX8                8                               /* Port x Bit 8 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX7                7                               /* Port x Bit 7 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX6                6                               /* Port x Bit 6 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX5                5                               /* Port x Bit 5 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX4                4                               /* Port x Bit 4 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX3                3                               /* Port x Bit 3 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX2                2                               /* Port x Bit 2 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX1                1                               /* Port x Bit 1 Input Enable Set */
-#define BITP_PORT_INEN_SET_PX0                0                               /* Port x Bit 0 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Set */
-#define BITM_PORT_INEN_SET_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_INEN_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_INEN_CLR_PX15              15                               /* Port x Bit 15 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX14              14                               /* Port x Bit 14 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX13              13                               /* Port x Bit 13 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX12              12                               /* Port x Bit 12 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX11              11                               /* Port x Bit 11 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX10              10                               /* Port x Bit 10 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX9                9                               /* Port x Bit 9 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX8                8                               /* Port x Bit 8 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX7                7                               /* Port x Bit 7 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX6                6                               /* Port x Bit 6 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX5                5                               /* Port x Bit 5 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX4                4                               /* Port x Bit 4 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX3                3                               /* Port x Bit 3 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX2                2                               /* Port x Bit 2 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX1                1                               /* Port x Bit 1 Input Enable Clear */
-#define BITP_PORT_INEN_CLR_PX0                0                               /* Port x Bit 0 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Input Enable Clear */
-#define BITM_PORT_INEN_CLR_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Input Enable Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_MUX                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_MUX_MUX15                  30                               /* Mux for Port x Bit 15 */
-#define BITP_PORT_MUX_MUX14                  28                               /* Mux for Port x Bit 14 */
-#define BITP_PORT_MUX_MUX13                  26                               /* Mux for Port x Bit 13 */
-#define BITP_PORT_MUX_MUX12                  24                               /* Mux for Port x Bit 12 */
-#define BITP_PORT_MUX_MUX11                  22                               /* Mux for Port x Bit 11 */
-#define BITP_PORT_MUX_MUX10                  20                               /* Mux for Port x Bit 10 */
-#define BITP_PORT_MUX_MUX9                   18                               /* Mux for Port x Bit 9 */
-#define BITP_PORT_MUX_MUX8                   16                               /* Mux for Port x Bit 8 */
-#define BITP_PORT_MUX_MUX7                   14                               /* Mux for Port x Bit 7 */
-#define BITP_PORT_MUX_MUX6                   12                               /* Mux for Port x Bit 6 */
-#define BITP_PORT_MUX_MUX5                   10                               /* Mux for Port x Bit 5 */
-#define BITP_PORT_MUX_MUX4                    8                               /* Mux for Port x Bit 4 */
-#define BITP_PORT_MUX_MUX3                    6                               /* Mux for Port x Bit 3 */
-#define BITP_PORT_MUX_MUX2                    4                               /* Mux for Port x Bit 2 */
-#define BITP_PORT_MUX_MUX1                    2                               /* Mux for Port x Bit 1 */
-#define BITP_PORT_MUX_MUX0                    0                               /* Mux for Port x Bit 0 */
-#define BITM_PORT_MUX_MUX15                  (_ADI_MSK(0xC0000000,uint32_t))  /* Mux for Port x Bit 15 */
-#define BITM_PORT_MUX_MUX14                  (_ADI_MSK(0x30000000,uint32_t))  /* Mux for Port x Bit 14 */
-#define BITM_PORT_MUX_MUX13                  (_ADI_MSK(0x0C000000,uint32_t))  /* Mux for Port x Bit 13 */
-#define BITM_PORT_MUX_MUX12                  (_ADI_MSK(0x03000000,uint32_t))  /* Mux for Port x Bit 12 */
-#define BITM_PORT_MUX_MUX11                  (_ADI_MSK(0x00C00000,uint32_t))  /* Mux for Port x Bit 11 */
-#define BITM_PORT_MUX_MUX10                  (_ADI_MSK(0x00300000,uint32_t))  /* Mux for Port x Bit 10 */
-#define BITM_PORT_MUX_MUX9                   (_ADI_MSK(0x000C0000,uint32_t))  /* Mux for Port x Bit 9 */
-#define BITM_PORT_MUX_MUX8                   (_ADI_MSK(0x00030000,uint32_t))  /* Mux for Port x Bit 8 */
-#define BITM_PORT_MUX_MUX7                   (_ADI_MSK(0x0000C000,uint32_t))  /* Mux for Port x Bit 7 */
-#define BITM_PORT_MUX_MUX6                   (_ADI_MSK(0x00003000,uint32_t))  /* Mux for Port x Bit 6 */
-#define BITM_PORT_MUX_MUX5                   (_ADI_MSK(0x00000C00,uint32_t))  /* Mux for Port x Bit 5 */
-#define BITM_PORT_MUX_MUX4                   (_ADI_MSK(0x00000300,uint32_t))  /* Mux for Port x Bit 4 */
-#define BITM_PORT_MUX_MUX3                   (_ADI_MSK(0x000000C0,uint32_t))  /* Mux for Port x Bit 3 */
-#define BITM_PORT_MUX_MUX2                   (_ADI_MSK(0x00000030,uint32_t))  /* Mux for Port x Bit 2 */
-#define BITM_PORT_MUX_MUX1                   (_ADI_MSK(0x0000000C,uint32_t))  /* Mux for Port x Bit 1 */
-#define BITM_PORT_MUX_MUX0                   (_ADI_MSK(0x00000003,uint32_t))  /* Mux for Port x Bit 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_DATA_TGL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_DATA_TGL_PX15              15                               /* Port x Bit 15 Toggle */
-#define BITP_PORT_DATA_TGL_PX14              14                               /* Port x Bit 14 Toggle */
-#define BITP_PORT_DATA_TGL_PX13              13                               /* Port x Bit 13 Toggle */
-#define BITP_PORT_DATA_TGL_PX12              12                               /* Port x Bit 12 Toggle */
-#define BITP_PORT_DATA_TGL_PX11              11                               /* Port x Bit 11 Toggle */
-#define BITP_PORT_DATA_TGL_PX10              10                               /* Port x Bit 10 Toggle */
-#define BITP_PORT_DATA_TGL_PX9                9                               /* Port x Bit 9 Toggle */
-#define BITP_PORT_DATA_TGL_PX8                8                               /* Port x Bit 8 Toggle */
-#define BITP_PORT_DATA_TGL_PX7                7                               /* Port x Bit 7 Toggle */
-#define BITP_PORT_DATA_TGL_PX6                6                               /* Port x Bit 6 Toggle */
-#define BITP_PORT_DATA_TGL_PX5                5                               /* Port x Bit 5 Toggle */
-#define BITP_PORT_DATA_TGL_PX4                4                               /* Port x Bit 4 Toggle */
-#define BITP_PORT_DATA_TGL_PX3                3                               /* Port x Bit 3 Toggle */
-#define BITP_PORT_DATA_TGL_PX2                2                               /* Port x Bit 2 Toggle */
-#define BITP_PORT_DATA_TGL_PX1                1                               /* Port x Bit 1 Toggle */
-#define BITP_PORT_DATA_TGL_PX0                0                               /* Port x Bit 0 Toggle */
-#define BITM_PORT_DATA_TGL_PX15              (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Toggle */
-#define BITM_PORT_DATA_TGL_PX14              (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Toggle */
-#define BITM_PORT_DATA_TGL_PX13              (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Toggle */
-#define BITM_PORT_DATA_TGL_PX12              (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Toggle */
-#define BITM_PORT_DATA_TGL_PX11              (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Toggle */
-#define BITM_PORT_DATA_TGL_PX10              (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Toggle */
-#define BITM_PORT_DATA_TGL_PX9               (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Toggle */
-#define BITM_PORT_DATA_TGL_PX8               (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Toggle */
-#define BITM_PORT_DATA_TGL_PX7               (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Toggle */
-#define BITM_PORT_DATA_TGL_PX6               (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Toggle */
-#define BITM_PORT_DATA_TGL_PX5               (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Toggle */
-#define BITM_PORT_DATA_TGL_PX4               (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Toggle */
-#define BITM_PORT_DATA_TGL_PX3               (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Toggle */
-#define BITM_PORT_DATA_TGL_PX2               (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Toggle */
-#define BITM_PORT_DATA_TGL_PX1               (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Toggle */
-#define BITM_PORT_DATA_TGL_PX0               (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Toggle */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_PX15                   15                               /* Port x Bit 15 Polarity Invert */
-#define BITP_PORT_POL_PX14                   14                               /* Port x Bit 14 Polarity Invert */
-#define BITP_PORT_POL_PX13                   13                               /* Port x Bit 13 Polarity Invert */
-#define BITP_PORT_POL_PX12                   12                               /* Port x Bit 12 Polarity Invert */
-#define BITP_PORT_POL_PX11                   11                               /* Port x Bit 11 Polarity Invert */
-#define BITP_PORT_POL_PX10                   10                               /* Port x Bit 10 Polarity Invert */
-#define BITP_PORT_POL_PX9                     9                               /* Port x Bit 9 Polarity Invert */
-#define BITP_PORT_POL_PX8                     8                               /* Port x Bit 8 Polarity Invert */
-#define BITP_PORT_POL_PX7                     7                               /* Port x Bit 7 Polarity Invert */
-#define BITP_PORT_POL_PX6                     6                               /* Port x Bit 6 Polarity Invert */
-#define BITP_PORT_POL_PX5                     5                               /* Port x Bit 5 Polarity Invert */
-#define BITP_PORT_POL_PX4                     4                               /* Port x Bit 4 Polarity Invert */
-#define BITP_PORT_POL_PX3                     3                               /* Port x Bit 3 Polarity Invert */
-#define BITP_PORT_POL_PX2                     2                               /* Port x Bit 2 Polarity Invert */
-#define BITP_PORT_POL_PX1                     1                               /* Port x Bit 1 Polarity Invert */
-#define BITP_PORT_POL_PX0                     0                               /* Port x Bit 0 Polarity Invert */
-#define BITM_PORT_POL_PX15                   (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert */
-#define BITM_PORT_POL_PX14                   (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert */
-#define BITM_PORT_POL_PX13                   (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert */
-#define BITM_PORT_POL_PX12                   (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert */
-#define BITM_PORT_POL_PX11                   (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert */
-#define BITM_PORT_POL_PX10                   (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert */
-#define BITM_PORT_POL_PX9                    (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert */
-#define BITM_PORT_POL_PX8                    (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert */
-#define BITM_PORT_POL_PX7                    (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert */
-#define BITM_PORT_POL_PX6                    (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert */
-#define BITM_PORT_POL_PX5                    (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert */
-#define BITM_PORT_POL_PX4                    (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert */
-#define BITM_PORT_POL_PX3                    (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert */
-#define BITM_PORT_POL_PX2                    (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert */
-#define BITM_PORT_POL_PX1                    (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert */
-#define BITM_PORT_POL_PX0                    (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_SET_PX15               15                               /* Port x Bit 15 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX14               14                               /* Port x Bit 14 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX13               13                               /* Port x Bit 13 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX12               12                               /* Port x Bit 12 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX11               11                               /* Port x Bit 11 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX10               10                               /* Port x Bit 10 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX9                 9                               /* Port x Bit 9 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX8                 8                               /* Port x Bit 8 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX7                 7                               /* Port x Bit 7 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX6                 6                               /* Port x Bit 6 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX5                 5                               /* Port x Bit 5 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX4                 4                               /* Port x Bit 4 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX3                 3                               /* Port x Bit 3 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX2                 2                               /* Port x Bit 2 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX1                 1                               /* Port x Bit 1 Polarity Invert Set */
-#define BITP_PORT_POL_SET_PX0                 0                               /* Port x Bit 0 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Set */
-#define BITM_PORT_POL_SET_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_POL_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_POL_CLR_PX15               15                               /* Port x Bit 15 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX14               14                               /* Port x Bit 14 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX13               13                               /* Port x Bit 13 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX12               12                               /* Port x Bit 12 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX11               11                               /* Port x Bit 11 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX10               10                               /* Port x Bit 10 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX9                 9                               /* Port x Bit 9 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX8                 8                               /* Port x Bit 8 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX7                 7                               /* Port x Bit 7 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX6                 6                               /* Port x Bit 6 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX5                 5                               /* Port x Bit 5 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX4                 4                               /* Port x Bit 4 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX3                 3                               /* Port x Bit 3 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX2                 2                               /* Port x Bit 2 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX1                 1                               /* Port x Bit 1 Polarity Invert Clear */
-#define BITP_PORT_POL_CLR_PX0                 0                               /* Port x Bit 0 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX15               (_ADI_MSK(0x00008000,uint32_t))  /* Port x Bit 15 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX14               (_ADI_MSK(0x00004000,uint32_t))  /* Port x Bit 14 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX13               (_ADI_MSK(0x00002000,uint32_t))  /* Port x Bit 13 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX12               (_ADI_MSK(0x00001000,uint32_t))  /* Port x Bit 12 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX11               (_ADI_MSK(0x00000800,uint32_t))  /* Port x Bit 11 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX10               (_ADI_MSK(0x00000400,uint32_t))  /* Port x Bit 10 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX9                (_ADI_MSK(0x00000200,uint32_t))  /* Port x Bit 9 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX8                (_ADI_MSK(0x00000100,uint32_t))  /* Port x Bit 8 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX7                (_ADI_MSK(0x00000080,uint32_t))  /* Port x Bit 7 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX6                (_ADI_MSK(0x00000040,uint32_t))  /* Port x Bit 6 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX5                (_ADI_MSK(0x00000020,uint32_t))  /* Port x Bit 5 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX4                (_ADI_MSK(0x00000010,uint32_t))  /* Port x Bit 4 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX3                (_ADI_MSK(0x00000008,uint32_t))  /* Port x Bit 3 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX2                (_ADI_MSK(0x00000004,uint32_t))  /* Port x Bit 2 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX1                (_ADI_MSK(0x00000002,uint32_t))  /* Port x Bit 1 Polarity Invert Clear */
-#define BITM_PORT_POL_CLR_PX0                (_ADI_MSK(0x00000001,uint32_t))  /* Port x Bit 0 Polarity Invert Clear */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_LOCK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_LOCK_LOCK                  31                               /* Lock */
-#define BITP_PORT_LOCK_POLAR                  5                               /* Polarity Lock */
-#define BITP_PORT_LOCK_INEN                   4                               /* Input Enable Lock */
-#define BITP_PORT_LOCK_DIR                    3                               /* Direction Lock */
-#define BITP_PORT_LOCK_DATA                   2                               /* Data Lock */
-#define BITP_PORT_LOCK_MUX                    1                               /* Function Multiplexer Lock */
-#define BITP_PORT_LOCK_FER                    0                               /* Function Enable Lock */
-#define BITM_PORT_LOCK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_PORT_LOCK_POLAR                 (_ADI_MSK(0x00000020,uint32_t))  /* Polarity Lock */
-#define BITM_PORT_LOCK_INEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Input Enable Lock */
-#define BITM_PORT_LOCK_DIR                   (_ADI_MSK(0x00000008,uint32_t))  /* Direction Lock */
-#define BITM_PORT_LOCK_DATA                  (_ADI_MSK(0x00000004,uint32_t))  /* Data Lock */
-#define BITM_PORT_LOCK_MUX                   (_ADI_MSK(0x00000002,uint32_t))  /* Function Multiplexer Lock */
-#define BITM_PORT_LOCK_FER                   (_ADI_MSK(0x00000001,uint32_t))  /* Function Enable Lock */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PORT_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PORT_REVID_MAJOR                 4                               /* Major ID */
-#define BITP_PORT_REVID_REV                   0                               /* Revision ID */
-#define BITM_PORT_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PORT_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID */
-
-/* ==================================================
-        Pads Controller Registers
-   ================================================== */
-
-/* =========================
-        PADS0
-   ========================= */
-#define REG_PADS0_EMAC_PTP_CLKSEL       0xFFC03404         /* PADS0 Clock Selection for EMAC and PTP */
-#define REG_PADS0_TWI_VSEL              0xFFC03408         /* PADS0 TWI Voltage Selection */
-#define REG_PADS0_PORTS_HYST            0xFFC03440         /* PADS0 Hysteresis Enable Register */
-
-/* =========================
-        PADS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_EMAC_PTP_CLKSEL                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC1       2                               /* Select Clock Source for PTP Block in EMAC1 */
-#define BITP_PADS_EMAC_PTP_CLKSEL_EMAC0       0                               /* PTP Clock Source 0 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC1      (_ADI_MSK(0x0000000C,uint32_t))  /* Select Clock Source for PTP Block in EMAC1 */
-#define BITM_PADS_EMAC_PTP_CLKSEL_EMAC0      (_ADI_MSK(0x00000003,uint32_t))  /* PTP Clock Source 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_TWI_VSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_TWI_VSEL_TWI1               4                               /* TWI Voltage Select 1 */
-#define BITP_PADS_TWI_VSEL_TWI0               0                               /* TWI Voltage Select 0 */
-#define BITM_PADS_TWI_VSEL_TWI1              (_ADI_MSK(0x00000070,uint32_t))  /* TWI Voltage Select 1 */
-#define BITM_PADS_TWI_VSEL_TWI0              (_ADI_MSK(0x00000007,uint32_t))  /* TWI Voltage Select 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PADS_PORTS_HYST                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PADS_PORTS_HYST_G                6                               /* Port G Hysteresis */
-#define BITP_PADS_PORTS_HYST_F                5                               /* Port F Hysteresis */
-#define BITP_PADS_PORTS_HYST_E                4                               /* Port E Hysteresis */
-#define BITP_PADS_PORTS_HYST_D                3                               /* Port D Hysteresis */
-#define BITP_PADS_PORTS_HYST_C                2                               /* Port C Hysteresis */
-#define BITP_PADS_PORTS_HYST_B                1                               /* Port B Hysteresis */
-#define BITP_PADS_PORTS_HYST_A                0                               /* Port A Hysteresis */
-#define BITM_PADS_PORTS_HYST_G               (_ADI_MSK(0x00000040,uint32_t))  /* Port G Hysteresis */
-#define BITM_PADS_PORTS_HYST_F               (_ADI_MSK(0x00000020,uint32_t))  /* Port F Hysteresis */
-#define BITM_PADS_PORTS_HYST_E               (_ADI_MSK(0x00000010,uint32_t))  /* Port E Hysteresis */
-#define BITM_PADS_PORTS_HYST_D               (_ADI_MSK(0x00000008,uint32_t))  /* Port D Hysteresis */
-#define BITM_PADS_PORTS_HYST_C               (_ADI_MSK(0x00000004,uint32_t))  /* Port C Hysteresis */
-#define BITM_PADS_PORTS_HYST_B               (_ADI_MSK(0x00000002,uint32_t))  /* Port B Hysteresis */
-#define BITM_PADS_PORTS_HYST_A               (_ADI_MSK(0x00000001,uint32_t))  /* Port A Hysteresis */
-
-/* ==================================================
-        PINT Registers
-   ================================================== */
-
-/* =========================
-        PINT0
-   ========================= */
-#define REG_PINT0_MSK_SET               0xFFC04000         /* PINT0 Pint Mask Set Register */
-#define REG_PINT0_MSK_CLR               0xFFC04004         /* PINT0 Pint Mask Clear Register */
-#define REG_PINT0_REQ                   0xFFC04008         /* PINT0 Pint Request Register */
-#define REG_PINT0_ASSIGN                0xFFC0400C         /* PINT0 Pint Assign Register */
-#define REG_PINT0_EDGE_SET              0xFFC04010         /* PINT0 Pint Edge Set Register */
-#define REG_PINT0_EDGE_CLR              0xFFC04014         /* PINT0 Pint Edge Clear Register */
-#define REG_PINT0_INV_SET               0xFFC04018         /* PINT0 Pint Invert Set Register */
-#define REG_PINT0_INV_CLR               0xFFC0401C         /* PINT0 Pint Invert Clear Register */
-#define REG_PINT0_PINSTATE              0xFFC04020         /* PINT0 Pint Pinstate Register */
-#define REG_PINT0_LATCH                 0xFFC04024         /* PINT0 Pint Latch Register */
-
-/* =========================
-        PINT1
-   ========================= */
-#define REG_PINT1_MSK_SET               0xFFC04100         /* PINT1 Pint Mask Set Register */
-#define REG_PINT1_MSK_CLR               0xFFC04104         /* PINT1 Pint Mask Clear Register */
-#define REG_PINT1_REQ                   0xFFC04108         /* PINT1 Pint Request Register */
-#define REG_PINT1_ASSIGN                0xFFC0410C         /* PINT1 Pint Assign Register */
-#define REG_PINT1_EDGE_SET              0xFFC04110         /* PINT1 Pint Edge Set Register */
-#define REG_PINT1_EDGE_CLR              0xFFC04114         /* PINT1 Pint Edge Clear Register */
-#define REG_PINT1_INV_SET               0xFFC04118         /* PINT1 Pint Invert Set Register */
-#define REG_PINT1_INV_CLR               0xFFC0411C         /* PINT1 Pint Invert Clear Register */
-#define REG_PINT1_PINSTATE              0xFFC04120         /* PINT1 Pint Pinstate Register */
-#define REG_PINT1_LATCH                 0xFFC04124         /* PINT1 Pint Latch Register */
-
-/* =========================
-        PINT2
-   ========================= */
-#define REG_PINT2_MSK_SET               0xFFC04200         /* PINT2 Pint Mask Set Register */
-#define REG_PINT2_MSK_CLR               0xFFC04204         /* PINT2 Pint Mask Clear Register */
-#define REG_PINT2_REQ                   0xFFC04208         /* PINT2 Pint Request Register */
-#define REG_PINT2_ASSIGN                0xFFC0420C         /* PINT2 Pint Assign Register */
-#define REG_PINT2_EDGE_SET              0xFFC04210         /* PINT2 Pint Edge Set Register */
-#define REG_PINT2_EDGE_CLR              0xFFC04214         /* PINT2 Pint Edge Clear Register */
-#define REG_PINT2_INV_SET               0xFFC04218         /* PINT2 Pint Invert Set Register */
-#define REG_PINT2_INV_CLR               0xFFC0421C         /* PINT2 Pint Invert Clear Register */
-#define REG_PINT2_PINSTATE              0xFFC04220         /* PINT2 Pint Pinstate Register */
-#define REG_PINT2_LATCH                 0xFFC04224         /* PINT2 Pint Latch Register */
-
-/* =========================
-        PINT3
-   ========================= */
-#define REG_PINT3_MSK_SET               0xFFC04300         /* PINT3 Pint Mask Set Register */
-#define REG_PINT3_MSK_CLR               0xFFC04304         /* PINT3 Pint Mask Clear Register */
-#define REG_PINT3_REQ                   0xFFC04308         /* PINT3 Pint Request Register */
-#define REG_PINT3_ASSIGN                0xFFC0430C         /* PINT3 Pint Assign Register */
-#define REG_PINT3_EDGE_SET              0xFFC04310         /* PINT3 Pint Edge Set Register */
-#define REG_PINT3_EDGE_CLR              0xFFC04314         /* PINT3 Pint Edge Clear Register */
-#define REG_PINT3_INV_SET               0xFFC04318         /* PINT3 Pint Invert Set Register */
-#define REG_PINT3_INV_CLR               0xFFC0431C         /* PINT3 Pint Invert Clear Register */
-#define REG_PINT3_PINSTATE              0xFFC04320         /* PINT3 Pint Pinstate Register */
-#define REG_PINT3_LATCH                 0xFFC04324         /* PINT3 Pint Latch Register */
-
-/* =========================
-        PINT4
-   ========================= */
-#define REG_PINT4_MSK_SET               0xFFC04400         /* PINT4 Pint Mask Set Register */
-#define REG_PINT4_MSK_CLR               0xFFC04404         /* PINT4 Pint Mask Clear Register */
-#define REG_PINT4_REQ                   0xFFC04408         /* PINT4 Pint Request Register */
-#define REG_PINT4_ASSIGN                0xFFC0440C         /* PINT4 Pint Assign Register */
-#define REG_PINT4_EDGE_SET              0xFFC04410         /* PINT4 Pint Edge Set Register */
-#define REG_PINT4_EDGE_CLR              0xFFC04414         /* PINT4 Pint Edge Clear Register */
-#define REG_PINT4_INV_SET               0xFFC04418         /* PINT4 Pint Invert Set Register */
-#define REG_PINT4_INV_CLR               0xFFC0441C         /* PINT4 Pint Invert Clear Register */
-#define REG_PINT4_PINSTATE              0xFFC04420         /* PINT4 Pint Pinstate Register */
-#define REG_PINT4_LATCH                 0xFFC04424         /* PINT4 Pint Latch Register */
-
-/* =========================
-        PINT5
-   ========================= */
-#define REG_PINT5_MSK_SET               0xFFC04500         /* PINT5 Pint Mask Set Register */
-#define REG_PINT5_MSK_CLR               0xFFC04504         /* PINT5 Pint Mask Clear Register */
-#define REG_PINT5_REQ                   0xFFC04508         /* PINT5 Pint Request Register */
-#define REG_PINT5_ASSIGN                0xFFC0450C         /* PINT5 Pint Assign Register */
-#define REG_PINT5_EDGE_SET              0xFFC04510         /* PINT5 Pint Edge Set Register */
-#define REG_PINT5_EDGE_CLR              0xFFC04514         /* PINT5 Pint Edge Clear Register */
-#define REG_PINT5_INV_SET               0xFFC04518         /* PINT5 Pint Invert Set Register */
-#define REG_PINT5_INV_CLR               0xFFC0451C         /* PINT5 Pint Invert Clear Register */
-#define REG_PINT5_PINSTATE              0xFFC04520         /* PINT5 Pint Pinstate Register */
-#define REG_PINT5_LATCH                 0xFFC04524         /* PINT5 Pint Latch Register */
-
-/* =========================
-        PINT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_SET_PIQ31              31                               /* Pin Interrupt 31 Unmask */
-#define BITP_PINT_MSK_SET_PIQ30              30                               /* Pin Interrupt 30 Unmask */
-#define BITP_PINT_MSK_SET_PIQ29              29                               /* Pin Interrupt 29 Unmask */
-#define BITP_PINT_MSK_SET_PIQ28              28                               /* Pin Interrupt 28 Unmask */
-#define BITP_PINT_MSK_SET_PIQ27              27                               /* Pin Interrupt 27 Unmask */
-#define BITP_PINT_MSK_SET_PIQ26              26                               /* Pin Interrupt 26 Unmask */
-#define BITP_PINT_MSK_SET_PIQ25              25                               /* Pin Interrupt 25 Unmask */
-#define BITP_PINT_MSK_SET_PIQ24              24                               /* Pin Interrupt 24 Unmask */
-#define BITP_PINT_MSK_SET_PIQ23              23                               /* Pin Interrupt 23 Unmask */
-#define BITP_PINT_MSK_SET_PIQ22              22                               /* Pin Interrupt 22 Unmask */
-#define BITP_PINT_MSK_SET_PIQ21              21                               /* Pin Interrupt 21 Unmask */
-#define BITP_PINT_MSK_SET_PIQ20              20                               /* Pin Interrupt 20 Unmask */
-#define BITP_PINT_MSK_SET_PIQ19              19                               /* Pin Interrupt 19 Unmask */
-#define BITP_PINT_MSK_SET_PIQ18              18                               /* Pin Interrupt 18 Unmask */
-#define BITP_PINT_MSK_SET_PIQ17              17                               /* Pin Interrupt 17 Unmask */
-#define BITP_PINT_MSK_SET_PIQ16              16                               /* Pin Interrupt 16 Unmask */
-#define BITP_PINT_MSK_SET_PIQ15              15                               /* Pin Interrupt 15 Unmask */
-#define BITP_PINT_MSK_SET_PIQ14              14                               /* Pin Interrupt 14 Unmask */
-#define BITP_PINT_MSK_SET_PIQ13              13                               /* Pin Interrupt 13 Unmask */
-#define BITP_PINT_MSK_SET_PIQ12              12                               /* Pin Interrupt 12 Unmask */
-#define BITP_PINT_MSK_SET_PIQ11              11                               /* Pin Interrupt 11 Unmask */
-#define BITP_PINT_MSK_SET_PIQ10              10                               /* Pin Interrupt 10 Unmask */
-#define BITP_PINT_MSK_SET_PIQ9                9                               /* Pin Interrupt 9 Unmask */
-#define BITP_PINT_MSK_SET_PIQ8                8                               /* Pin Interrupt 8 Unmask */
-#define BITP_PINT_MSK_SET_PIQ7                7                               /* Pin Interrupt 7 Unmask */
-#define BITP_PINT_MSK_SET_PIQ6                6                               /* Pin Interrupt 6 Unmask */
-#define BITP_PINT_MSK_SET_PIQ5                5                               /* Pin Interrupt 5 Unmask */
-#define BITP_PINT_MSK_SET_PIQ4                4                               /* Pin Interrupt 4 Unmask */
-#define BITP_PINT_MSK_SET_PIQ3                3                               /* Pin Interrupt 3 Unmask */
-#define BITP_PINT_MSK_SET_PIQ2                2                               /* Pin Interrupt 2 Unmask */
-#define BITP_PINT_MSK_SET_PIQ1                1                               /* Pin Interrupt 1 Unmask */
-#define BITP_PINT_MSK_SET_PIQ0                0                               /* Pin Interrupt 0 Unmask */
-#define BITM_PINT_MSK_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Unmask */
-#define BITM_PINT_MSK_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Unmask */
-#define BITM_PINT_MSK_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Unmask */
-#define BITM_PINT_MSK_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Unmask */
-#define BITM_PINT_MSK_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Unmask */
-#define BITM_PINT_MSK_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Unmask */
-#define BITM_PINT_MSK_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Unmask */
-#define BITM_PINT_MSK_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Unmask */
-#define BITM_PINT_MSK_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Unmask */
-#define BITM_PINT_MSK_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Unmask */
-#define BITM_PINT_MSK_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Unmask */
-#define BITM_PINT_MSK_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Unmask */
-#define BITM_PINT_MSK_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Unmask */
-#define BITM_PINT_MSK_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Unmask */
-#define BITM_PINT_MSK_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Unmask */
-#define BITM_PINT_MSK_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Unmask */
-#define BITM_PINT_MSK_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Unmask */
-#define BITM_PINT_MSK_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Unmask */
-#define BITM_PINT_MSK_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Unmask */
-#define BITM_PINT_MSK_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Unmask */
-#define BITM_PINT_MSK_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Unmask */
-#define BITM_PINT_MSK_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Unmask */
-#define BITM_PINT_MSK_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Unmask */
-#define BITM_PINT_MSK_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Unmask */
-#define BITM_PINT_MSK_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Unmask */
-#define BITM_PINT_MSK_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Unmask */
-#define BITM_PINT_MSK_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Unmask */
-#define BITM_PINT_MSK_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Unmask */
-#define BITM_PINT_MSK_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Unmask */
-#define BITM_PINT_MSK_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Unmask */
-#define BITM_PINT_MSK_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Unmask */
-#define BITM_PINT_MSK_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_MSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_MSK_CLR_PIQ31              31                               /* Pin Interrupt 31 Mask */
-#define BITP_PINT_MSK_CLR_PIQ30              30                               /* Pin Interrupt 30 Mask */
-#define BITP_PINT_MSK_CLR_PIQ29              29                               /* Pin Interrupt 29 Mask */
-#define BITP_PINT_MSK_CLR_PIQ28              28                               /* Pin Interrupt 28 Mask */
-#define BITP_PINT_MSK_CLR_PIQ27              27                               /* Pin Interrupt 27 Mask */
-#define BITP_PINT_MSK_CLR_PIQ26              26                               /* Pin Interrupt 26 Mask */
-#define BITP_PINT_MSK_CLR_PIQ25              25                               /* Pin Interrupt 25 Mask */
-#define BITP_PINT_MSK_CLR_PIQ24              24                               /* Pin Interrupt 24 Mask */
-#define BITP_PINT_MSK_CLR_PIQ23              23                               /* Pin Interrupt 23 Mask */
-#define BITP_PINT_MSK_CLR_PIQ22              22                               /* Pin Interrupt 22 Mask */
-#define BITP_PINT_MSK_CLR_PIQ21              21                               /* Pin Interrupt 21 Mask */
-#define BITP_PINT_MSK_CLR_PIQ20              20                               /* Pin Interrupt 20 Mask */
-#define BITP_PINT_MSK_CLR_PIQ19              19                               /* Pin Interrupt 19 Mask */
-#define BITP_PINT_MSK_CLR_PIQ18              18                               /* Pin Interrupt 18 Mask */
-#define BITP_PINT_MSK_CLR_PIQ17              17                               /* Pin Interrupt 17 Mask */
-#define BITP_PINT_MSK_CLR_PIQ16              16                               /* Pin Interrupt 16 Mask */
-#define BITP_PINT_MSK_CLR_PIQ15              15                               /* Pin Interrupt 15 Mask */
-#define BITP_PINT_MSK_CLR_PIQ14              14                               /* Pin Interrupt 14 Mask */
-#define BITP_PINT_MSK_CLR_PIQ13              13                               /* Pin Interrupt 13 Mask */
-#define BITP_PINT_MSK_CLR_PIQ12              12                               /* Pin Interrupt 12 Mask */
-#define BITP_PINT_MSK_CLR_PIQ11              11                               /* Pin Interrupt 11 Mask */
-#define BITP_PINT_MSK_CLR_PIQ10              10                               /* Pin Interrupt 10 Mask */
-#define BITP_PINT_MSK_CLR_PIQ9                9                               /* Pin Interrupt 9 Mask */
-#define BITP_PINT_MSK_CLR_PIQ8                8                               /* Pin Interrupt 8 Mask */
-#define BITP_PINT_MSK_CLR_PIQ7                7                               /* Pin Interrupt 7 Mask */
-#define BITP_PINT_MSK_CLR_PIQ6                6                               /* Pin Interrupt 6 Mask */
-#define BITP_PINT_MSK_CLR_PIQ5                5                               /* Pin Interrupt 5 Mask */
-#define BITP_PINT_MSK_CLR_PIQ4                4                               /* Pin Interrupt 4 Mask */
-#define BITP_PINT_MSK_CLR_PIQ3                3                               /* Pin Interrupt 3 Mask */
-#define BITP_PINT_MSK_CLR_PIQ2                2                               /* Pin Interrupt 2 Mask */
-#define BITP_PINT_MSK_CLR_PIQ1                1                               /* Pin Interrupt 1 Mask */
-#define BITP_PINT_MSK_CLR_PIQ0                0                               /* Pin Interrupt 0 Mask */
-#define BITM_PINT_MSK_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Mask */
-#define BITM_PINT_MSK_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Mask */
-#define BITM_PINT_MSK_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Mask */
-#define BITM_PINT_MSK_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Mask */
-#define BITM_PINT_MSK_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Mask */
-#define BITM_PINT_MSK_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Mask */
-#define BITM_PINT_MSK_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Mask */
-#define BITM_PINT_MSK_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Mask */
-#define BITM_PINT_MSK_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Mask */
-#define BITM_PINT_MSK_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Mask */
-#define BITM_PINT_MSK_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Mask */
-#define BITM_PINT_MSK_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Mask */
-#define BITM_PINT_MSK_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Mask */
-#define BITM_PINT_MSK_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Mask */
-#define BITM_PINT_MSK_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Mask */
-#define BITM_PINT_MSK_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Mask */
-#define BITM_PINT_MSK_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Mask */
-#define BITM_PINT_MSK_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Mask */
-#define BITM_PINT_MSK_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Mask */
-#define BITM_PINT_MSK_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Mask */
-#define BITM_PINT_MSK_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Mask */
-#define BITM_PINT_MSK_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Mask */
-#define BITM_PINT_MSK_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Mask */
-#define BITM_PINT_MSK_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Mask */
-#define BITM_PINT_MSK_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Mask */
-#define BITM_PINT_MSK_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Mask */
-#define BITM_PINT_MSK_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Mask */
-#define BITM_PINT_MSK_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Mask */
-#define BITM_PINT_MSK_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Mask */
-#define BITM_PINT_MSK_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Mask */
-#define BITM_PINT_MSK_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Mask */
-#define BITM_PINT_MSK_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_REQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_REQ_PIQ31                  31                               /* Pin Interrupt 31 Request */
-#define BITP_PINT_REQ_PIQ30                  30                               /* Pin Interrupt 30 Request */
-#define BITP_PINT_REQ_PIQ29                  29                               /* Pin Interrupt 29 Request */
-#define BITP_PINT_REQ_PIQ28                  28                               /* Pin Interrupt 28 Request */
-#define BITP_PINT_REQ_PIQ27                  27                               /* Pin Interrupt 27 Request */
-#define BITP_PINT_REQ_PIQ26                  26                               /* Pin Interrupt 26 Request */
-#define BITP_PINT_REQ_PIQ25                  25                               /* Pin Interrupt 25 Request */
-#define BITP_PINT_REQ_PIQ24                  24                               /* Pin Interrupt 24 Request */
-#define BITP_PINT_REQ_PIQ23                  23                               /* Pin Interrupt 23 Request */
-#define BITP_PINT_REQ_PIQ22                  22                               /* Pin Interrupt 22 Request */
-#define BITP_PINT_REQ_PIQ21                  21                               /* Pin Interrupt 21 Request */
-#define BITP_PINT_REQ_PIQ20                  20                               /* Pin Interrupt 20 Request */
-#define BITP_PINT_REQ_PIQ19                  19                               /* Pin Interrupt 19 Request */
-#define BITP_PINT_REQ_PIQ18                  18                               /* Pin Interrupt 18 Request */
-#define BITP_PINT_REQ_PIQ17                  17                               /* Pin Interrupt 17 Request */
-#define BITP_PINT_REQ_PIQ16                  16                               /* Pin Interrupt 16 Request */
-#define BITP_PINT_REQ_PIQ15                  15                               /* Pin Interrupt 15 Request */
-#define BITP_PINT_REQ_PIQ14                  14                               /* Pin Interrupt 14 Request */
-#define BITP_PINT_REQ_PIQ13                  13                               /* Pin Interrupt 13 Request */
-#define BITP_PINT_REQ_PIQ12                  12                               /* Pin Interrupt 12 Request */
-#define BITP_PINT_REQ_PIQ11                  11                               /* Pin Interrupt 11 Request */
-#define BITP_PINT_REQ_PIQ10                  10                               /* Pin Interrupt 10 Request */
-#define BITP_PINT_REQ_PIQ9                    9                               /* Pin Interrupt 9 Request */
-#define BITP_PINT_REQ_PIQ8                    8                               /* Pin Interrupt 8 Request */
-#define BITP_PINT_REQ_PIQ7                    7                               /* Pin Interrupt 7 Request */
-#define BITP_PINT_REQ_PIQ6                    6                               /* Pin Interrupt 6 Request */
-#define BITP_PINT_REQ_PIQ5                    5                               /* Pin Interrupt 5 Request */
-#define BITP_PINT_REQ_PIQ4                    4                               /* Pin Interrupt 4 Request */
-#define BITP_PINT_REQ_PIQ3                    3                               /* Pin Interrupt 3 Request */
-#define BITP_PINT_REQ_PIQ2                    2                               /* Pin Interrupt 2 Request */
-#define BITP_PINT_REQ_PIQ1                    1                               /* Pin Interrupt 1 Request */
-#define BITP_PINT_REQ_PIQ0                    0                               /* Pin Interrupt 0 Request */
-#define BITM_PINT_REQ_PIQ31                  (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Request */
-#define BITM_PINT_REQ_PIQ30                  (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Request */
-#define BITM_PINT_REQ_PIQ29                  (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Request */
-#define BITM_PINT_REQ_PIQ28                  (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Request */
-#define BITM_PINT_REQ_PIQ27                  (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Request */
-#define BITM_PINT_REQ_PIQ26                  (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Request */
-#define BITM_PINT_REQ_PIQ25                  (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Request */
-#define BITM_PINT_REQ_PIQ24                  (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Request */
-#define BITM_PINT_REQ_PIQ23                  (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Request */
-#define BITM_PINT_REQ_PIQ22                  (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Request */
-#define BITM_PINT_REQ_PIQ21                  (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Request */
-#define BITM_PINT_REQ_PIQ20                  (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Request */
-#define BITM_PINT_REQ_PIQ19                  (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Request */
-#define BITM_PINT_REQ_PIQ18                  (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Request */
-#define BITM_PINT_REQ_PIQ17                  (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Request */
-#define BITM_PINT_REQ_PIQ16                  (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Request */
-#define BITM_PINT_REQ_PIQ15                  (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Request */
-#define BITM_PINT_REQ_PIQ14                  (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Request */
-#define BITM_PINT_REQ_PIQ13                  (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Request */
-#define BITM_PINT_REQ_PIQ12                  (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Request */
-#define BITM_PINT_REQ_PIQ11                  (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Request */
-#define BITM_PINT_REQ_PIQ10                  (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Request */
-#define BITM_PINT_REQ_PIQ9                   (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Request */
-#define BITM_PINT_REQ_PIQ8                   (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Request */
-#define BITM_PINT_REQ_PIQ7                   (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Request */
-#define BITM_PINT_REQ_PIQ6                   (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Request */
-#define BITM_PINT_REQ_PIQ5                   (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Request */
-#define BITM_PINT_REQ_PIQ4                   (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Request */
-#define BITM_PINT_REQ_PIQ3                   (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Request */
-#define BITM_PINT_REQ_PIQ2                   (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Request */
-#define BITM_PINT_REQ_PIQ1                   (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Request */
-#define BITM_PINT_REQ_PIQ0                   (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_ASSIGN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_ASSIGN_B3MAP               24                               /* Byte 3 Mapping */
-#define BITP_PINT_ASSIGN_B2MAP               16                               /* Byte 2 Mapping */
-#define BITP_PINT_ASSIGN_B1MAP                8                               /* Byte 1 Mapping */
-#define BITP_PINT_ASSIGN_B0MAP                0                               /* Byte 0 Mapping */
-#define BITM_PINT_ASSIGN_B3MAP               (_ADI_MSK(0xFF000000,uint32_t))  /* Byte 3 Mapping */
-#define BITM_PINT_ASSIGN_B2MAP               (_ADI_MSK(0x00FF0000,uint32_t))  /* Byte 2 Mapping */
-#define BITM_PINT_ASSIGN_B1MAP               (_ADI_MSK(0x0000FF00,uint32_t))  /* Byte 1 Mapping */
-#define BITM_PINT_ASSIGN_B0MAP               (_ADI_MSK(0x000000FF,uint32_t))  /* Byte 0 Mapping */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_SET                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_SET_PIQ31             31                               /* Pin Interrupt 31 Edge */
-#define BITP_PINT_EDGE_SET_PIQ30             30                               /* Pin Interrupt 30 Edge */
-#define BITP_PINT_EDGE_SET_PIQ29             29                               /* Pin Interrupt 29 Edge */
-#define BITP_PINT_EDGE_SET_PIQ28             28                               /* Pin Interrupt 28 Edge */
-#define BITP_PINT_EDGE_SET_PIQ27             27                               /* Pin Interrupt 27 Edge */
-#define BITP_PINT_EDGE_SET_PIQ26             26                               /* Pin Interrupt 26 Edge */
-#define BITP_PINT_EDGE_SET_PIQ25             25                               /* Pin Interrupt 25 Edge */
-#define BITP_PINT_EDGE_SET_PIQ24             24                               /* Pin Interrupt 24 Edge */
-#define BITP_PINT_EDGE_SET_PIQ23             23                               /* Pin Interrupt 23 Edge */
-#define BITP_PINT_EDGE_SET_PIQ22             22                               /* Pin Interrupt 22 Edge */
-#define BITP_PINT_EDGE_SET_PIQ21             21                               /* Pin Interrupt 21 Edge */
-#define BITP_PINT_EDGE_SET_PIQ20             20                               /* Pin Interrupt 20 Edge */
-#define BITP_PINT_EDGE_SET_PIQ19             19                               /* Pin Interrupt 19 Edge */
-#define BITP_PINT_EDGE_SET_PIQ18             18                               /* Pin Interrupt 18 Edge */
-#define BITP_PINT_EDGE_SET_PIQ17             17                               /* Pin Interrupt 17 Edge */
-#define BITP_PINT_EDGE_SET_PIQ16             16                               /* Pin Interrupt 16 Edge */
-#define BITP_PINT_EDGE_SET_PIQ15             15                               /* Pin Interrupt 15 Edge */
-#define BITP_PINT_EDGE_SET_PIQ14             14                               /* Pin Interrupt 14 Edge */
-#define BITP_PINT_EDGE_SET_PIQ13             13                               /* Pin Interrupt 13 Edge */
-#define BITP_PINT_EDGE_SET_PIQ12             12                               /* Pin Interrupt 12 Edge */
-#define BITP_PINT_EDGE_SET_PIQ11             11                               /* Pin Interrupt 11 Edge */
-#define BITP_PINT_EDGE_SET_PIQ10             10                               /* Pin Interrupt 10 Edge */
-#define BITP_PINT_EDGE_SET_PIQ9               9                               /* Pin Interrupt 9 Edge */
-#define BITP_PINT_EDGE_SET_PIQ8               8                               /* Pin Interrupt 8 Edge */
-#define BITP_PINT_EDGE_SET_PIQ7               7                               /* Pin Interrupt 7 Edge */
-#define BITP_PINT_EDGE_SET_PIQ6               6                               /* Pin Interrupt 6 Edge */
-#define BITP_PINT_EDGE_SET_PIQ5               5                               /* Pin Interrupt 5 Edge */
-#define BITP_PINT_EDGE_SET_PIQ4               4                               /* Pin Interrupt 4 Edge */
-#define BITP_PINT_EDGE_SET_PIQ3               3                               /* Pin Interrupt 3 Edge */
-#define BITP_PINT_EDGE_SET_PIQ2               2                               /* Pin Interrupt 2 Edge */
-#define BITP_PINT_EDGE_SET_PIQ1               1                               /* Pin Interrupt 1 Edge */
-#define BITP_PINT_EDGE_SET_PIQ0               0                               /* Pin Interrupt 0 Edge */
-#define BITM_PINT_EDGE_SET_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Edge */
-#define BITM_PINT_EDGE_SET_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Edge */
-#define BITM_PINT_EDGE_SET_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Edge */
-#define BITM_PINT_EDGE_SET_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Edge */
-#define BITM_PINT_EDGE_SET_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Edge */
-#define BITM_PINT_EDGE_SET_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Edge */
-#define BITM_PINT_EDGE_SET_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Edge */
-#define BITM_PINT_EDGE_SET_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Edge */
-#define BITM_PINT_EDGE_SET_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Edge */
-#define BITM_PINT_EDGE_SET_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Edge */
-#define BITM_PINT_EDGE_SET_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Edge */
-#define BITM_PINT_EDGE_SET_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Edge */
-#define BITM_PINT_EDGE_SET_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Edge */
-#define BITM_PINT_EDGE_SET_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Edge */
-#define BITM_PINT_EDGE_SET_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Edge */
-#define BITM_PINT_EDGE_SET_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Edge */
-#define BITM_PINT_EDGE_SET_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Edge */
-#define BITM_PINT_EDGE_SET_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Edge */
-#define BITM_PINT_EDGE_SET_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Edge */
-#define BITM_PINT_EDGE_SET_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Edge */
-#define BITM_PINT_EDGE_SET_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Edge */
-#define BITM_PINT_EDGE_SET_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Edge */
-#define BITM_PINT_EDGE_SET_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Edge */
-#define BITM_PINT_EDGE_SET_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Edge */
-#define BITM_PINT_EDGE_SET_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Edge */
-#define BITM_PINT_EDGE_SET_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Edge */
-#define BITM_PINT_EDGE_SET_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Edge */
-#define BITM_PINT_EDGE_SET_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Edge */
-#define BITM_PINT_EDGE_SET_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Edge */
-#define BITM_PINT_EDGE_SET_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Edge */
-#define BITM_PINT_EDGE_SET_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Edge */
-#define BITM_PINT_EDGE_SET_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Edge */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_EDGE_CLR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_EDGE_CLR_PIQ31             31                               /* Pin Interrupt 31 Level */
-#define BITP_PINT_EDGE_CLR_PIQ30             30                               /* Pin Interrupt 30 Level */
-#define BITP_PINT_EDGE_CLR_PIQ29             29                               /* Pin Interrupt 29 Level */
-#define BITP_PINT_EDGE_CLR_PIQ28             28                               /* Pin Interrupt 28 Level */
-#define BITP_PINT_EDGE_CLR_PIQ27             27                               /* Pin Interrupt 27 Level */
-#define BITP_PINT_EDGE_CLR_PIQ26             26                               /* Pin Interrupt 26 Level */
-#define BITP_PINT_EDGE_CLR_PIQ25             25                               /* Pin Interrupt 25 Level */
-#define BITP_PINT_EDGE_CLR_PIQ24             24                               /* Pin Interrupt 24 Level */
-#define BITP_PINT_EDGE_CLR_PIQ23             23                               /* Pin Interrupt 23 Level */
-#define BITP_PINT_EDGE_CLR_PIQ22             22                               /* Pin Interrupt 22 Level */
-#define BITP_PINT_EDGE_CLR_PIQ21             21                               /* Pin Interrupt 21 Level */
-#define BITP_PINT_EDGE_CLR_PIQ20             20                               /* Pin Interrupt 20 Level */
-#define BITP_PINT_EDGE_CLR_PIQ19             19                               /* Pin Interrupt 19 Level */
-#define BITP_PINT_EDGE_CLR_PIQ18             18                               /* Pin Interrupt 18 Level */
-#define BITP_PINT_EDGE_CLR_PIQ17             17                               /* Pin Interrupt 17 Level */
-#define BITP_PINT_EDGE_CLR_PIQ16             16                               /* Pin Interrupt 16 Level */
-#define BITP_PINT_EDGE_CLR_PIQ15             15                               /* Pin Interrupt 15 Level */
-#define BITP_PINT_EDGE_CLR_PIQ14             14                               /* Pin Interrupt 14 Level */
-#define BITP_PINT_EDGE_CLR_PIQ13             13                               /* Pin Interrupt 13 Level */
-#define BITP_PINT_EDGE_CLR_PIQ12             12                               /* Pin Interrupt 12 Level */
-#define BITP_PINT_EDGE_CLR_PIQ11             11                               /* Pin Interrupt 11 Level */
-#define BITP_PINT_EDGE_CLR_PIQ10             10                               /* Pin Interrupt 10 Level */
-#define BITP_PINT_EDGE_CLR_PIQ9               9                               /* Pin Interrupt 9 Level */
-#define BITP_PINT_EDGE_CLR_PIQ8               8                               /* Pin Interrupt 8 Level */
-#define BITP_PINT_EDGE_CLR_PIQ7               7                               /* Pin Interrupt 7 Level */
-#define BITP_PINT_EDGE_CLR_PIQ6               6                               /* Pin Interrupt 6 Level */
-#define BITP_PINT_EDGE_CLR_PIQ5               5                               /* Pin Interrupt 5 Level */
-#define BITP_PINT_EDGE_CLR_PIQ4               4                               /* Pin Interrupt 4 Level */
-#define BITP_PINT_EDGE_CLR_PIQ3               3                               /* Pin Interrupt 3 Level */
-#define BITP_PINT_EDGE_CLR_PIQ2               2                               /* Pin Interrupt 2 Level */
-#define BITP_PINT_EDGE_CLR_PIQ1               1                               /* Pin Interrupt 1 Level */
-#define BITP_PINT_EDGE_CLR_PIQ0               0                               /* Pin Interrupt 0 Level */
-#define BITM_PINT_EDGE_CLR_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Level */
-#define BITM_PINT_EDGE_CLR_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Level */
-#define BITM_PINT_EDGE_CLR_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Level */
-#define BITM_PINT_EDGE_CLR_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Level */
-#define BITM_PINT_EDGE_CLR_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Level */
-#define BITM_PINT_EDGE_CLR_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Level */
-#define BITM_PINT_EDGE_CLR_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Level */
-#define BITM_PINT_EDGE_CLR_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Level */
-#define BITM_PINT_EDGE_CLR_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Level */
-#define BITM_PINT_EDGE_CLR_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Level */
-#define BITM_PINT_EDGE_CLR_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Level */
-#define BITM_PINT_EDGE_CLR_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Level */
-#define BITM_PINT_EDGE_CLR_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Level */
-#define BITM_PINT_EDGE_CLR_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Level */
-#define BITM_PINT_EDGE_CLR_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Level */
-#define BITM_PINT_EDGE_CLR_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Level */
-#define BITM_PINT_EDGE_CLR_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Level */
-#define BITM_PINT_EDGE_CLR_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Level */
-#define BITM_PINT_EDGE_CLR_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Level */
-#define BITM_PINT_EDGE_CLR_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Level */
-#define BITM_PINT_EDGE_CLR_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Level */
-#define BITM_PINT_EDGE_CLR_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Level */
-#define BITM_PINT_EDGE_CLR_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Level */
-#define BITM_PINT_EDGE_CLR_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Level */
-#define BITM_PINT_EDGE_CLR_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Level */
-#define BITM_PINT_EDGE_CLR_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Level */
-#define BITM_PINT_EDGE_CLR_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Level */
-#define BITM_PINT_EDGE_CLR_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Level */
-#define BITM_PINT_EDGE_CLR_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Level */
-#define BITM_PINT_EDGE_CLR_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Level */
-#define BITM_PINT_EDGE_CLR_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Level */
-#define BITM_PINT_EDGE_CLR_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Level */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_SET_PIQ31              31                               /* Pin Interrupt 31 Invert */
-#define BITP_PINT_INV_SET_PIQ30              30                               /* Pin Interrupt 30 Invert */
-#define BITP_PINT_INV_SET_PIQ29              29                               /* Pin Interrupt 29 Invert */
-#define BITP_PINT_INV_SET_PIQ28              28                               /* Pin Interrupt 28 Invert */
-#define BITP_PINT_INV_SET_PIQ27              27                               /* Pin Interrupt 27 Invert */
-#define BITP_PINT_INV_SET_PIQ26              26                               /* Pin Interrupt 26 Invert */
-#define BITP_PINT_INV_SET_PIQ25              25                               /* Pin Interrupt 25 Invert */
-#define BITP_PINT_INV_SET_PIQ24              24                               /* Pin Interrupt 24 Invert */
-#define BITP_PINT_INV_SET_PIQ23              23                               /* Pin Interrupt 23 Invert */
-#define BITP_PINT_INV_SET_PIQ22              22                               /* Pin Interrupt 22 Invert */
-#define BITP_PINT_INV_SET_PIQ21              21                               /* Pin Interrupt 21 Invert */
-#define BITP_PINT_INV_SET_PIQ20              20                               /* Pin Interrupt 20 Invert */
-#define BITP_PINT_INV_SET_PIQ19              19                               /* Pin Interrupt 19 Invert */
-#define BITP_PINT_INV_SET_PIQ18              18                               /* Pin Interrupt 18 Invert */
-#define BITP_PINT_INV_SET_PIQ17              17                               /* Pin Interrupt 17 Invert */
-#define BITP_PINT_INV_SET_PIQ16              16                               /* Pin Interrupt 16 Invert */
-#define BITP_PINT_INV_SET_PIQ15              15                               /* Pin Interrupt 15 Invert */
-#define BITP_PINT_INV_SET_PIQ14              14                               /* Pin Interrupt 14 Invert */
-#define BITP_PINT_INV_SET_PIQ13              13                               /* Pin Interrupt 13 Invert */
-#define BITP_PINT_INV_SET_PIQ12              12                               /* Pin Interrupt 12 Invert */
-#define BITP_PINT_INV_SET_PIQ11              11                               /* Pin Interrupt 11 Invert */
-#define BITP_PINT_INV_SET_PIQ10              10                               /* Pin Interrupt 10 Invert */
-#define BITP_PINT_INV_SET_PIQ9                9                               /* Pin Interrupt 9 Invert */
-#define BITP_PINT_INV_SET_PIQ8                8                               /* Pin Interrupt 8 Invert */
-#define BITP_PINT_INV_SET_PIQ7                7                               /* Pin Interrupt 7 Invert */
-#define BITP_PINT_INV_SET_PIQ6                6                               /* Pin Interrupt 6 Invert */
-#define BITP_PINT_INV_SET_PIQ5                5                               /* Pin Interrupt 5 Invert */
-#define BITP_PINT_INV_SET_PIQ4                4                               /* Pin Interrupt 4 Invert */
-#define BITP_PINT_INV_SET_PIQ3                3                               /* Pin Interrupt 3 Invert */
-#define BITP_PINT_INV_SET_PIQ2                2                               /* Pin Interrupt 2 Invert */
-#define BITP_PINT_INV_SET_PIQ1                1                               /* Pin Interrupt 1 Invert */
-#define BITP_PINT_INV_SET_PIQ0                0                               /* Pin Interrupt 0 Invert */
-#define BITM_PINT_INV_SET_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Invert */
-#define BITM_PINT_INV_SET_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Invert */
-#define BITM_PINT_INV_SET_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Invert */
-#define BITM_PINT_INV_SET_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Invert */
-#define BITM_PINT_INV_SET_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Invert */
-#define BITM_PINT_INV_SET_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Invert */
-#define BITM_PINT_INV_SET_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Invert */
-#define BITM_PINT_INV_SET_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Invert */
-#define BITM_PINT_INV_SET_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Invert */
-#define BITM_PINT_INV_SET_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Invert */
-#define BITM_PINT_INV_SET_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Invert */
-#define BITM_PINT_INV_SET_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Invert */
-#define BITM_PINT_INV_SET_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Invert */
-#define BITM_PINT_INV_SET_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Invert */
-#define BITM_PINT_INV_SET_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Invert */
-#define BITM_PINT_INV_SET_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Invert */
-#define BITM_PINT_INV_SET_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Invert */
-#define BITM_PINT_INV_SET_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Invert */
-#define BITM_PINT_INV_SET_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Invert */
-#define BITM_PINT_INV_SET_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Invert */
-#define BITM_PINT_INV_SET_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Invert */
-#define BITM_PINT_INV_SET_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Invert */
-#define BITM_PINT_INV_SET_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Invert */
-#define BITM_PINT_INV_SET_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Invert */
-#define BITM_PINT_INV_SET_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Invert */
-#define BITM_PINT_INV_SET_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Invert */
-#define BITM_PINT_INV_SET_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Invert */
-#define BITM_PINT_INV_SET_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Invert */
-#define BITM_PINT_INV_SET_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Invert */
-#define BITM_PINT_INV_SET_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Invert */
-#define BITM_PINT_INV_SET_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Invert */
-#define BITM_PINT_INV_SET_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_INV_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_INV_CLR_PIQ31              31                               /* Pin Interrupt 31 No Invert */
-#define BITP_PINT_INV_CLR_PIQ30              30                               /* Pin Interrupt 30 No Invert */
-#define BITP_PINT_INV_CLR_PIQ29              29                               /* Pin Interrupt 29 No Invert */
-#define BITP_PINT_INV_CLR_PIQ28              28                               /* Pin Interrupt 28 No Invert */
-#define BITP_PINT_INV_CLR_PIQ27              27                               /* Pin Interrupt 27 No Invert */
-#define BITP_PINT_INV_CLR_PIQ26              26                               /* Pin Interrupt 26 No Invert */
-#define BITP_PINT_INV_CLR_PIQ25              25                               /* Pin Interrupt 25 No Invert */
-#define BITP_PINT_INV_CLR_PIQ24              24                               /* Pin Interrupt 24 No Invert */
-#define BITP_PINT_INV_CLR_PIQ23              23                               /* Pin Interrupt 23 No Invert */
-#define BITP_PINT_INV_CLR_PIQ22              22                               /* Pin Interrupt 22 No Invert */
-#define BITP_PINT_INV_CLR_PIQ21              21                               /* Pin Interrupt 21 No Invert */
-#define BITP_PINT_INV_CLR_PIQ20              20                               /* Pin Interrupt 20 No Invert */
-#define BITP_PINT_INV_CLR_PIQ19              19                               /* Pin Interrupt 19 No Invert */
-#define BITP_PINT_INV_CLR_PIQ18              18                               /* Pin Interrupt 18 No Invert */
-#define BITP_PINT_INV_CLR_PIQ17              17                               /* Pin Interrupt 17 No Invert */
-#define BITP_PINT_INV_CLR_PIQ16              16                               /* Pin Interrupt 16 No Invert */
-#define BITP_PINT_INV_CLR_PIQ15              15                               /* Pin Interrupt 15 No Invert */
-#define BITP_PINT_INV_CLR_PIQ14              14                               /* Pin Interrupt 14 No Invert */
-#define BITP_PINT_INV_CLR_PIQ13              13                               /* Pin Interrupt 13 No Invert */
-#define BITP_PINT_INV_CLR_PIQ12              12                               /* Pin Interrupt 12 No Invert */
-#define BITP_PINT_INV_CLR_PIQ11              11                               /* Pin Interrupt 11 No Invert */
-#define BITP_PINT_INV_CLR_PIQ10              10                               /* Pin Interrupt 10 No Invert */
-#define BITP_PINT_INV_CLR_PIQ9                9                               /* Pin Interrupt 9 No Invert */
-#define BITP_PINT_INV_CLR_PIQ8                8                               /* Pin Interrupt 8 No Invert */
-#define BITP_PINT_INV_CLR_PIQ7                7                               /* Pin Interrupt 7 No Invert */
-#define BITP_PINT_INV_CLR_PIQ6                6                               /* Pin Interrupt 6 No Invert */
-#define BITP_PINT_INV_CLR_PIQ5                5                               /* Pin Interrupt 5 No Invert */
-#define BITP_PINT_INV_CLR_PIQ4                4                               /* Pin Interrupt 4 No Invert */
-#define BITP_PINT_INV_CLR_PIQ3                3                               /* Pin Interrupt 3 No Invert */
-#define BITP_PINT_INV_CLR_PIQ2                2                               /* Pin Interrupt 2 No Invert */
-#define BITP_PINT_INV_CLR_PIQ1                1                               /* Pin Interrupt 1 No Invert */
-#define BITP_PINT_INV_CLR_PIQ0                0                               /* Pin Interrupt 0 No Invert */
-#define BITM_PINT_INV_CLR_PIQ31              (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 No Invert */
-#define BITM_PINT_INV_CLR_PIQ30              (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 No Invert */
-#define BITM_PINT_INV_CLR_PIQ29              (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 No Invert */
-#define BITM_PINT_INV_CLR_PIQ28              (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 No Invert */
-#define BITM_PINT_INV_CLR_PIQ27              (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 No Invert */
-#define BITM_PINT_INV_CLR_PIQ26              (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 No Invert */
-#define BITM_PINT_INV_CLR_PIQ25              (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 No Invert */
-#define BITM_PINT_INV_CLR_PIQ24              (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 No Invert */
-#define BITM_PINT_INV_CLR_PIQ23              (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 No Invert */
-#define BITM_PINT_INV_CLR_PIQ22              (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 No Invert */
-#define BITM_PINT_INV_CLR_PIQ21              (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 No Invert */
-#define BITM_PINT_INV_CLR_PIQ20              (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 No Invert */
-#define BITM_PINT_INV_CLR_PIQ19              (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 No Invert */
-#define BITM_PINT_INV_CLR_PIQ18              (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 No Invert */
-#define BITM_PINT_INV_CLR_PIQ17              (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 No Invert */
-#define BITM_PINT_INV_CLR_PIQ16              (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 No Invert */
-#define BITM_PINT_INV_CLR_PIQ15              (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 No Invert */
-#define BITM_PINT_INV_CLR_PIQ14              (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 No Invert */
-#define BITM_PINT_INV_CLR_PIQ13              (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 No Invert */
-#define BITM_PINT_INV_CLR_PIQ12              (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 No Invert */
-#define BITM_PINT_INV_CLR_PIQ11              (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 No Invert */
-#define BITM_PINT_INV_CLR_PIQ10              (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 No Invert */
-#define BITM_PINT_INV_CLR_PIQ9               (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 No Invert */
-#define BITM_PINT_INV_CLR_PIQ8               (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 No Invert */
-#define BITM_PINT_INV_CLR_PIQ7               (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 No Invert */
-#define BITM_PINT_INV_CLR_PIQ6               (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 No Invert */
-#define BITM_PINT_INV_CLR_PIQ5               (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 No Invert */
-#define BITM_PINT_INV_CLR_PIQ4               (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 No Invert */
-#define BITM_PINT_INV_CLR_PIQ3               (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 No Invert */
-#define BITM_PINT_INV_CLR_PIQ2               (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 No Invert */
-#define BITM_PINT_INV_CLR_PIQ1               (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 No Invert */
-#define BITM_PINT_INV_CLR_PIQ0               (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 No Invert */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_PINSTATE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_PINSTATE_PIQ31             31                               /* Pin Interrupt 31 State */
-#define BITP_PINT_PINSTATE_PIQ30             30                               /* Pin Interrupt 30 State */
-#define BITP_PINT_PINSTATE_PIQ29             29                               /* Pin Interrupt 29 State */
-#define BITP_PINT_PINSTATE_PIQ28             28                               /* Pin Interrupt 28 State */
-#define BITP_PINT_PINSTATE_PIQ27             27                               /* Pin Interrupt 27 State */
-#define BITP_PINT_PINSTATE_PIQ26             26                               /* Pin Interrupt 26 State */
-#define BITP_PINT_PINSTATE_PIQ25             25                               /* Pin Interrupt 25 State */
-#define BITP_PINT_PINSTATE_PIQ24             24                               /* Pin Interrupt 24 State */
-#define BITP_PINT_PINSTATE_PIQ23             23                               /* Pin Interrupt 23 State */
-#define BITP_PINT_PINSTATE_PIQ22             22                               /* Pin Interrupt 22 State */
-#define BITP_PINT_PINSTATE_PIQ21             21                               /* Pin Interrupt 21 State */
-#define BITP_PINT_PINSTATE_PIQ20             20                               /* Pin Interrupt 20 State */
-#define BITP_PINT_PINSTATE_PIQ19             19                               /* Pin Interrupt 19 State */
-#define BITP_PINT_PINSTATE_PIQ18             18                               /* Pin Interrupt 18 State */
-#define BITP_PINT_PINSTATE_PIQ17             17                               /* Pin Interrupt 17 State */
-#define BITP_PINT_PINSTATE_PIQ16             16                               /* Pin Interrupt 16 State */
-#define BITP_PINT_PINSTATE_PIQ15             15                               /* Pin Interrupt 15 State */
-#define BITP_PINT_PINSTATE_PIQ14             14                               /* Pin Interrupt 14 State */
-#define BITP_PINT_PINSTATE_PIQ13             13                               /* Pin Interrupt 13 State */
-#define BITP_PINT_PINSTATE_PIQ12             12                               /* Pin Interrupt 12 State */
-#define BITP_PINT_PINSTATE_PIQ11             11                               /* Pin Interrupt 11 State */
-#define BITP_PINT_PINSTATE_PIQ10             10                               /* Pin Interrupt 10 State */
-#define BITP_PINT_PINSTATE_PIQ9               9                               /* Pin Interrupt 9 State */
-#define BITP_PINT_PINSTATE_PIQ8               8                               /* Pin Interrupt 8 State */
-#define BITP_PINT_PINSTATE_PIQ7               7                               /* Pin Interrupt 7 State */
-#define BITP_PINT_PINSTATE_PIQ6               6                               /* Pin Interrupt 6 State */
-#define BITP_PINT_PINSTATE_PIQ5               5                               /* Pin Interrupt 5 State */
-#define BITP_PINT_PINSTATE_PIQ4               4                               /* Pin Interrupt 4 State */
-#define BITP_PINT_PINSTATE_PIQ3               3                               /* Pin Interrupt 3 State */
-#define BITP_PINT_PINSTATE_PIQ2               2                               /* Pin Interrupt 2 State */
-#define BITP_PINT_PINSTATE_PIQ1               1                               /* Pin Interrupt 1 State */
-#define BITP_PINT_PINSTATE_PIQ0               0                               /* Pin Interrupt 0 State */
-#define BITM_PINT_PINSTATE_PIQ31             (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 State */
-#define BITM_PINT_PINSTATE_PIQ30             (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 State */
-#define BITM_PINT_PINSTATE_PIQ29             (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 State */
-#define BITM_PINT_PINSTATE_PIQ28             (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 State */
-#define BITM_PINT_PINSTATE_PIQ27             (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 State */
-#define BITM_PINT_PINSTATE_PIQ26             (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 State */
-#define BITM_PINT_PINSTATE_PIQ25             (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 State */
-#define BITM_PINT_PINSTATE_PIQ24             (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 State */
-#define BITM_PINT_PINSTATE_PIQ23             (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 State */
-#define BITM_PINT_PINSTATE_PIQ22             (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 State */
-#define BITM_PINT_PINSTATE_PIQ21             (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 State */
-#define BITM_PINT_PINSTATE_PIQ20             (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 State */
-#define BITM_PINT_PINSTATE_PIQ19             (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 State */
-#define BITM_PINT_PINSTATE_PIQ18             (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 State */
-#define BITM_PINT_PINSTATE_PIQ17             (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 State */
-#define BITM_PINT_PINSTATE_PIQ16             (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 State */
-#define BITM_PINT_PINSTATE_PIQ15             (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 State */
-#define BITM_PINT_PINSTATE_PIQ14             (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 State */
-#define BITM_PINT_PINSTATE_PIQ13             (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 State */
-#define BITM_PINT_PINSTATE_PIQ12             (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 State */
-#define BITM_PINT_PINSTATE_PIQ11             (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 State */
-#define BITM_PINT_PINSTATE_PIQ10             (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 State */
-#define BITM_PINT_PINSTATE_PIQ9              (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 State */
-#define BITM_PINT_PINSTATE_PIQ8              (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 State */
-#define BITM_PINT_PINSTATE_PIQ7              (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 State */
-#define BITM_PINT_PINSTATE_PIQ6              (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 State */
-#define BITM_PINT_PINSTATE_PIQ5              (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 State */
-#define BITM_PINT_PINSTATE_PIQ4              (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 State */
-#define BITM_PINT_PINSTATE_PIQ3              (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 State */
-#define BITM_PINT_PINSTATE_PIQ2              (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 State */
-#define BITM_PINT_PINSTATE_PIQ1              (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 State */
-#define BITM_PINT_PINSTATE_PIQ0              (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PINT_LATCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PINT_LATCH_PIQ31                31                               /* Pin Interrupt 31 Latch */
-#define BITP_PINT_LATCH_PIQ30                30                               /* Pin Interrupt 30 Latch */
-#define BITP_PINT_LATCH_PIQ29                29                               /* Pin Interrupt 29 Latch */
-#define BITP_PINT_LATCH_PIQ28                28                               /* Pin Interrupt 28 Latch */
-#define BITP_PINT_LATCH_PIQ27                27                               /* Pin Interrupt 27 Latch */
-#define BITP_PINT_LATCH_PIQ26                26                               /* Pin Interrupt 26 Latch */
-#define BITP_PINT_LATCH_PIQ25                25                               /* Pin Interrupt 25 Latch */
-#define BITP_PINT_LATCH_PIQ24                24                               /* Pin Interrupt 24 Latch */
-#define BITP_PINT_LATCH_PIQ23                23                               /* Pin Interrupt 23 Latch */
-#define BITP_PINT_LATCH_PIQ22                22                               /* Pin Interrupt 22 Latch */
-#define BITP_PINT_LATCH_PIQ21                21                               /* Pin Interrupt 21 Latch */
-#define BITP_PINT_LATCH_PIQ20                20                               /* Pin Interrupt 20 Latch */
-#define BITP_PINT_LATCH_PIQ19                19                               /* Pin Interrupt 19 Latch */
-#define BITP_PINT_LATCH_PIQ18                18                               /* Pin Interrupt 18 Latch */
-#define BITP_PINT_LATCH_PIQ17                17                               /* Pin Interrupt 17 Latch */
-#define BITP_PINT_LATCH_PIQ16                16                               /* Pin Interrupt 16 Latch */
-#define BITP_PINT_LATCH_PIQ15                15                               /* Pin Interrupt 15 Latch */
-#define BITP_PINT_LATCH_PIQ14                14                               /* Pin Interrupt 14 Latch */
-#define BITP_PINT_LATCH_PIQ13                13                               /* Pin Interrupt 13 Latch */
-#define BITP_PINT_LATCH_PIQ12                12                               /* Pin Interrupt 12 Latch */
-#define BITP_PINT_LATCH_PIQ11                11                               /* Pin Interrupt 11 Latch */
-#define BITP_PINT_LATCH_PIQ10                10                               /* Pin Interrupt 10 Latch */
-#define BITP_PINT_LATCH_PIQ9                  9                               /* Pin Interrupt 9 Latch */
-#define BITP_PINT_LATCH_PIQ8                  8                               /* Pin Interrupt 8 Latch */
-#define BITP_PINT_LATCH_PIQ7                  7                               /* Pin Interrupt 7 Latch */
-#define BITP_PINT_LATCH_PIQ6                  6                               /* Pin Interrupt 6 Latch */
-#define BITP_PINT_LATCH_PIQ5                  5                               /* Pin Interrupt 5 Latch */
-#define BITP_PINT_LATCH_PIQ4                  4                               /* Pin Interrupt 4 Latch */
-#define BITP_PINT_LATCH_PIQ3                  3                               /* Pin Interrupt 3 Latch */
-#define BITP_PINT_LATCH_PIQ2                  2                               /* Pin Interrupt 2 Latch */
-#define BITP_PINT_LATCH_PIQ1                  1                               /* Pin Interrupt 1 Latch */
-#define BITP_PINT_LATCH_PIQ0                  0                               /* Pin Interrupt 0 Latch */
-#define BITM_PINT_LATCH_PIQ31                (_ADI_MSK(0x80000000,uint32_t))  /* Pin Interrupt 31 Latch */
-#define BITM_PINT_LATCH_PIQ30                (_ADI_MSK(0x40000000,uint32_t))  /* Pin Interrupt 30 Latch */
-#define BITM_PINT_LATCH_PIQ29                (_ADI_MSK(0x20000000,uint32_t))  /* Pin Interrupt 29 Latch */
-#define BITM_PINT_LATCH_PIQ28                (_ADI_MSK(0x10000000,uint32_t))  /* Pin Interrupt 28 Latch */
-#define BITM_PINT_LATCH_PIQ27                (_ADI_MSK(0x08000000,uint32_t))  /* Pin Interrupt 27 Latch */
-#define BITM_PINT_LATCH_PIQ26                (_ADI_MSK(0x04000000,uint32_t))  /* Pin Interrupt 26 Latch */
-#define BITM_PINT_LATCH_PIQ25                (_ADI_MSK(0x02000000,uint32_t))  /* Pin Interrupt 25 Latch */
-#define BITM_PINT_LATCH_PIQ24                (_ADI_MSK(0x01000000,uint32_t))  /* Pin Interrupt 24 Latch */
-#define BITM_PINT_LATCH_PIQ23                (_ADI_MSK(0x00800000,uint32_t))  /* Pin Interrupt 23 Latch */
-#define BITM_PINT_LATCH_PIQ22                (_ADI_MSK(0x00400000,uint32_t))  /* Pin Interrupt 22 Latch */
-#define BITM_PINT_LATCH_PIQ21                (_ADI_MSK(0x00200000,uint32_t))  /* Pin Interrupt 21 Latch */
-#define BITM_PINT_LATCH_PIQ20                (_ADI_MSK(0x00100000,uint32_t))  /* Pin Interrupt 20 Latch */
-#define BITM_PINT_LATCH_PIQ19                (_ADI_MSK(0x00080000,uint32_t))  /* Pin Interrupt 19 Latch */
-#define BITM_PINT_LATCH_PIQ18                (_ADI_MSK(0x00040000,uint32_t))  /* Pin Interrupt 18 Latch */
-#define BITM_PINT_LATCH_PIQ17                (_ADI_MSK(0x00020000,uint32_t))  /* Pin Interrupt 17 Latch */
-#define BITM_PINT_LATCH_PIQ16                (_ADI_MSK(0x00010000,uint32_t))  /* Pin Interrupt 16 Latch */
-#define BITM_PINT_LATCH_PIQ15                (_ADI_MSK(0x00008000,uint32_t))  /* Pin Interrupt 15 Latch */
-#define BITM_PINT_LATCH_PIQ14                (_ADI_MSK(0x00004000,uint32_t))  /* Pin Interrupt 14 Latch */
-#define BITM_PINT_LATCH_PIQ13                (_ADI_MSK(0x00002000,uint32_t))  /* Pin Interrupt 13 Latch */
-#define BITM_PINT_LATCH_PIQ12                (_ADI_MSK(0x00001000,uint32_t))  /* Pin Interrupt 12 Latch */
-#define BITM_PINT_LATCH_PIQ11                (_ADI_MSK(0x00000800,uint32_t))  /* Pin Interrupt 11 Latch */
-#define BITM_PINT_LATCH_PIQ10                (_ADI_MSK(0x00000400,uint32_t))  /* Pin Interrupt 10 Latch */
-#define BITM_PINT_LATCH_PIQ9                 (_ADI_MSK(0x00000200,uint32_t))  /* Pin Interrupt 9 Latch */
-#define BITM_PINT_LATCH_PIQ8                 (_ADI_MSK(0x00000100,uint32_t))  /* Pin Interrupt 8 Latch */
-#define BITM_PINT_LATCH_PIQ7                 (_ADI_MSK(0x00000080,uint32_t))  /* Pin Interrupt 7 Latch */
-#define BITM_PINT_LATCH_PIQ6                 (_ADI_MSK(0x00000040,uint32_t))  /* Pin Interrupt 6 Latch */
-#define BITM_PINT_LATCH_PIQ5                 (_ADI_MSK(0x00000020,uint32_t))  /* Pin Interrupt 5 Latch */
-#define BITM_PINT_LATCH_PIQ4                 (_ADI_MSK(0x00000010,uint32_t))  /* Pin Interrupt 4 Latch */
-#define BITM_PINT_LATCH_PIQ3                 (_ADI_MSK(0x00000008,uint32_t))  /* Pin Interrupt 3 Latch */
-#define BITM_PINT_LATCH_PIQ2                 (_ADI_MSK(0x00000004,uint32_t))  /* Pin Interrupt 2 Latch */
-#define BITM_PINT_LATCH_PIQ1                 (_ADI_MSK(0x00000002,uint32_t))  /* Pin Interrupt 1 Latch */
-#define BITM_PINT_LATCH_PIQ0                 (_ADI_MSK(0x00000001,uint32_t))  /* Pin Interrupt 0 Latch */
-
-/* ==================================================
-        Static Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        SMC0
-   ========================= */
-#define REG_SMC0_GCTL                   0xFFC16004         /* SMC0 Grant Control Register */
-#define REG_SMC0_GSTAT                  0xFFC16008         /* SMC0 Grant Status Register */
-#define REG_SMC0_B0CTL                  0xFFC1600C         /* SMC0 Bank 0 Control Register */
-#define REG_SMC0_B0TIM                  0xFFC16010         /* SMC0 Bank 0 Timing Register */
-#define REG_SMC0_B0ETIM                 0xFFC16014         /* SMC0 Bank 0 Extended Timing Register */
-#define REG_SMC0_B1CTL                  0xFFC1601C         /* SMC0 Bank 1 Control Register */
-#define REG_SMC0_B1TIM                  0xFFC16020         /* SMC0 Bank 1 Timing Register */
-#define REG_SMC0_B1ETIM                 0xFFC16024         /* SMC0 Bank 1 Extended Timing Register */
-#define REG_SMC0_B2CTL                  0xFFC1602C         /* SMC0 Bank 2 Control Register */
-#define REG_SMC0_B2TIM                  0xFFC16030         /* SMC0 Bank 2 Timing Register */
-#define REG_SMC0_B2ETIM                 0xFFC16034         /* SMC0 Bank 2 Extended Timing Register */
-#define REG_SMC0_B3CTL                  0xFFC1603C         /* SMC0 Bank 3 Control Register */
-#define REG_SMC0_B3TIM                  0xFFC16040         /* SMC0 Bank 3 Timing Register */
-#define REG_SMC0_B3ETIM                 0xFFC16044         /* SMC0 Bank 3 Extended Timing Register */
-
-/* =========================
-        SMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GCTL_BGDIS                   4                               /* Bus Grant Disable */
-#define BITM_SMC_GCTL_BGDIS                  (_ADI_MSK(0x00000010,uint32_t))  /* Bus Grant Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_GSTAT_BGHSTAT                2                               /* Bus Grant Hold Status */
-#define BITP_SMC_GSTAT_BRQSTAT                1                               /* Bus Request Status */
-#define BITP_SMC_GSTAT_BGSTAT                 0                               /* Bus Grant Status */
-#define BITM_SMC_GSTAT_BGHSTAT               (_ADI_MSK(0x00000004,uint32_t))  /* Bus Grant Hold Status */
-#define BITM_SMC_GSTAT_BRQSTAT               (_ADI_MSK(0x00000002,uint32_t))  /* Bus Request Status */
-#define BITM_SMC_GSTAT_BGSTAT                (_ADI_MSK(0x00000001,uint32_t))  /* Bus Grant Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B0CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B0CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B0CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B0CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B0CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B0CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B0CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B0CTL_EN                     0                               /* Bank 0 Enable */
-#define BITM_SMC_B0CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B0CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B0CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B0CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B0CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B0CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B0CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B0CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B0CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B0TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B0TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B0TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B0TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B0TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B0TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B0TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B0TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B0TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B0TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B0TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B0ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B0ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B0ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B0ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B0ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B0ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B0ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B0ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B0ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B0ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B0ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B1CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B1CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B1CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B1CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B1CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B1CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B1CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B1CTL_EN                     0                               /* Bank 1 Enable */
-#define BITM_SMC_B1CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B1CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B1CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B1CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B1CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B1CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B1CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B1CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B1CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 1 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B1TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B1TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B1TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B1TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B1TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B1TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B1TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B1TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B1TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B1TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B1TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B1ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B1ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B1ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B1ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B1ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B1ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B1ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B1ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B1ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B1ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B1ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B2CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B2CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B2CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B2CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B2CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B2CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B2CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B2CTL_EN                     0                               /* Bank 2 Enable */
-#define BITM_SMC_B2CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B2CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B2CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B2CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B2CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B2CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B2CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B2CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B2CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 2 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B2TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B2TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B2TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B2TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B2TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B2TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B2TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B2TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B2TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B2TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B2TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B2ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B2ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B2ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B2ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B2ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B2ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B2ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B2ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B2ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B2ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B2ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3CTL_BTYPE                 26                               /* Burst Type for Flash */
-#define BITP_SMC_B3CTL_BCLK                  24                               /* Burst Clock Frequency Divisor */
-#define BITP_SMC_B3CTL_PGSZ                  20                               /* Flash Page Size */
-#define BITP_SMC_B3CTL_RDYABTEN              14                               /* ARDY Abort Enable */
-#define BITP_SMC_B3CTL_RDYPOL                13                               /* ARDY Polarity */
-#define BITP_SMC_B3CTL_RDYEN                 12                               /* ARDY Enable */
-#define BITP_SMC_B3CTL_SELCTRL                8                               /* Select Control */
-#define BITP_SMC_B3CTL_MODE                   4                               /* Memory Access Mode */
-#define BITP_SMC_B3CTL_EN                     0                               /* Bank 3 Enable */
-#define BITM_SMC_B3CTL_BTYPE                 (_ADI_MSK(0x04000000,uint32_t))  /* Burst Type for Flash */
-#define BITM_SMC_B3CTL_BCLK                  (_ADI_MSK(0x03000000,uint32_t))  /* Burst Clock Frequency Divisor */
-#define BITM_SMC_B3CTL_PGSZ                  (_ADI_MSK(0x00300000,uint32_t))  /* Flash Page Size */
-#define BITM_SMC_B3CTL_RDYABTEN              (_ADI_MSK(0x00004000,uint32_t))  /* ARDY Abort Enable */
-#define BITM_SMC_B3CTL_RDYPOL                (_ADI_MSK(0x00002000,uint32_t))  /* ARDY Polarity */
-#define BITM_SMC_B3CTL_RDYEN                 (_ADI_MSK(0x00001000,uint32_t))  /* ARDY Enable */
-#define BITM_SMC_B3CTL_SELCTRL               (_ADI_MSK(0x00000300,uint32_t))  /* Select Control */
-#define BITM_SMC_B3CTL_MODE                  (_ADI_MSK(0x00000030,uint32_t))  /* Memory Access Mode */
-#define BITM_SMC_B3CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* Bank 3 Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3TIM                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3TIM_RAT                   24                               /* Read Access Time */
-#define BITP_SMC_B3TIM_RHT                   20                               /* Read Hold Time */
-#define BITP_SMC_B3TIM_RST                   16                               /* Read Setup Time */
-#define BITP_SMC_B3TIM_WAT                    8                               /* Write Access Time */
-#define BITP_SMC_B3TIM_WHT                    4                               /* Write Hold Time */
-#define BITP_SMC_B3TIM_WST                    0                               /* Write Setup Time */
-#define BITM_SMC_B3TIM_RAT                   (_ADI_MSK(0x3F000000,uint32_t))  /* Read Access Time */
-#define BITM_SMC_B3TIM_RHT                   (_ADI_MSK(0x00700000,uint32_t))  /* Read Hold Time */
-#define BITM_SMC_B3TIM_RST                   (_ADI_MSK(0x00070000,uint32_t))  /* Read Setup Time */
-#define BITM_SMC_B3TIM_WAT                   (_ADI_MSK(0x00003F00,uint32_t))  /* Write Access Time */
-#define BITM_SMC_B3TIM_WHT                   (_ADI_MSK(0x00000070,uint32_t))  /* Write Hold Time */
-#define BITM_SMC_B3TIM_WST                   (_ADI_MSK(0x00000007,uint32_t))  /* Write Setup Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SMC_B3ETIM                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SMC_B3ETIM_PGWS                 16                               /* Page Wait States */
-#define BITP_SMC_B3ETIM_IT                   12                               /* Idle Time */
-#define BITP_SMC_B3ETIM_TT                    8                               /* Transition Time */
-#define BITP_SMC_B3ETIM_PREAT                 4                               /* Pre Access Time */
-#define BITP_SMC_B3ETIM_PREST                 0                               /* Pre Setup Time */
-#define BITM_SMC_B3ETIM_PGWS                 (_ADI_MSK(0x000F0000,uint32_t))  /* Page Wait States */
-#define BITM_SMC_B3ETIM_IT                   (_ADI_MSK(0x00007000,uint32_t))  /* Idle Time */
-#define BITM_SMC_B3ETIM_TT                   (_ADI_MSK(0x00000700,uint32_t))  /* Transition Time */
-#define BITM_SMC_B3ETIM_PREAT                (_ADI_MSK(0x00000030,uint32_t))  /* Pre Access Time */
-#define BITM_SMC_B3ETIM_PREST                (_ADI_MSK(0x00000003,uint32_t))  /* Pre Setup Time */
-
-/* ==================================================
-        Watch Dog Timer Unit Registers
-   ================================================== */
-
-/* =========================
-        WDOG0
-   ========================= */
-#define REG_WDOG0_CTL                   0xFFC17000         /* WDOG0 Control Register */
-#define REG_WDOG0_CNT                   0xFFC17004         /* WDOG0 Count Register */
-#define REG_WDOG0_STAT                  0xFFC17008         /* WDOG0 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG1
-   ========================= */
-#define REG_WDOG1_CTL                   0xFFC17800         /* WDOG1 Control Register */
-#define REG_WDOG1_CNT                   0xFFC17804         /* WDOG1 Count Register */
-#define REG_WDOG1_STAT                  0xFFC17808         /* WDOG1 Watchdog Timer Status Register */
-
-/* =========================
-        WDOG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WDOG_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WDOG_CTL_WDRO                   15                               /* Watch Dog Rollover */
-#define BITP_WDOG_CTL_WDEN                    4                               /* Watch Dog Enable */
-
-#define BITM_WDOG_CTL_WDRO                   (_ADI_MSK(0x00008000,uint32_t))  /* Watch Dog Rollover */
-#define ENUM_WDOG_CTL_WDTEXP                 (_ADI_MSK(0x00008000,uint32_t))  /* WDRO: WDT has expired */
-#define BITM_WDOG_CTL_WDEN                   (_ADI_MSK(0x00000FF0,uint32_t))  /* Watch Dog Enable */
-
-/* ==================================================
-        EPPI Registers
-   ================================================== */
-
-/* =========================
-        EPPI0
-   ========================= */
-#define REG_EPPI0_STAT                  0xFFC18000         /* EPPI0 Status Register */
-#define REG_EPPI0_HCNT                  0xFFC18004         /* EPPI0 Horizontal Transfer Count Register */
-#define REG_EPPI0_HDLY                  0xFFC18008         /* EPPI0 Horizontal Delay Count Register */
-#define REG_EPPI0_VCNT                  0xFFC1800C         /* EPPI0 Vertical Transfer Count Register */
-#define REG_EPPI0_VDLY                  0xFFC18010         /* EPPI0 Vertical Delay Count Register */
-#define REG_EPPI0_FRAME                 0xFFC18014         /* EPPI0 Lines Per Frame Register */
-#define REG_EPPI0_LINE                  0xFFC18018         /* EPPI0 Samples Per Line Register */
-#define REG_EPPI0_CLKDIV                0xFFC1801C         /* EPPI0 Clock Divide Register */
-#define REG_EPPI0_CTL                   0xFFC18020         /* EPPI0 Control Register */
-#define REG_EPPI0_FS1_WLHB              0xFFC18024         /* EPPI0 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI0_FS1_PASPL             0xFFC18028         /* EPPI0 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI0_FS2_WLVB              0xFFC1802C         /* EPPI0 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI0_FS2_PALPF             0xFFC18030         /* EPPI0 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI0_IMSK                  0xFFC18034         /* EPPI0 Interrupt Mask Register */
-#define REG_EPPI0_ODDCLIP               0xFFC1803C         /* EPPI0 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI0_EVENCLIP              0xFFC18040         /* EPPI0 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI0_FS1_DLY               0xFFC18044         /* EPPI0 Frame Sync 1 Delay Value */
-#define REG_EPPI0_FS2_DLY               0xFFC18048         /* EPPI0 Frame Sync 2 Delay Value */
-#define REG_EPPI0_CTL2                  0xFFC1804C         /* EPPI0 Control Register 2 */
-
-/* =========================
-        EPPI1
-   ========================= */
-#define REG_EPPI1_STAT                  0xFFC18400         /* EPPI1 Status Register */
-#define REG_EPPI1_HCNT                  0xFFC18404         /* EPPI1 Horizontal Transfer Count Register */
-#define REG_EPPI1_HDLY                  0xFFC18408         /* EPPI1 Horizontal Delay Count Register */
-#define REG_EPPI1_VCNT                  0xFFC1840C         /* EPPI1 Vertical Transfer Count Register */
-#define REG_EPPI1_VDLY                  0xFFC18410         /* EPPI1 Vertical Delay Count Register */
-#define REG_EPPI1_FRAME                 0xFFC18414         /* EPPI1 Lines Per Frame Register */
-#define REG_EPPI1_LINE                  0xFFC18418         /* EPPI1 Samples Per Line Register */
-#define REG_EPPI1_CLKDIV                0xFFC1841C         /* EPPI1 Clock Divide Register */
-#define REG_EPPI1_CTL                   0xFFC18420         /* EPPI1 Control Register */
-#define REG_EPPI1_FS1_WLHB              0xFFC18424         /* EPPI1 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI1_FS1_PASPL             0xFFC18428         /* EPPI1 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI1_FS2_WLVB              0xFFC1842C         /* EPPI1 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI1_FS2_PALPF             0xFFC18430         /* EPPI1 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI1_IMSK                  0xFFC18434         /* EPPI1 Interrupt Mask Register */
-#define REG_EPPI1_ODDCLIP               0xFFC1843C         /* EPPI1 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI1_EVENCLIP              0xFFC18440         /* EPPI1 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI1_FS1_DLY               0xFFC18444         /* EPPI1 Frame Sync 1 Delay Value */
-#define REG_EPPI1_FS2_DLY               0xFFC18448         /* EPPI1 Frame Sync 2 Delay Value */
-#define REG_EPPI1_CTL2                  0xFFC1844C         /* EPPI1 Control Register 2 */
-
-/* =========================
-        EPPI2
-   ========================= */
-#define REG_EPPI2_STAT                  0xFFC18800         /* EPPI2 Status Register */
-#define REG_EPPI2_HCNT                  0xFFC18804         /* EPPI2 Horizontal Transfer Count Register */
-#define REG_EPPI2_HDLY                  0xFFC18808         /* EPPI2 Horizontal Delay Count Register */
-#define REG_EPPI2_VCNT                  0xFFC1880C         /* EPPI2 Vertical Transfer Count Register */
-#define REG_EPPI2_VDLY                  0xFFC18810         /* EPPI2 Vertical Delay Count Register */
-#define REG_EPPI2_FRAME                 0xFFC18814         /* EPPI2 Lines Per Frame Register */
-#define REG_EPPI2_LINE                  0xFFC18818         /* EPPI2 Samples Per Line Register */
-#define REG_EPPI2_CLKDIV                0xFFC1881C         /* EPPI2 Clock Divide Register */
-#define REG_EPPI2_CTL                   0xFFC18820         /* EPPI2 Control Register */
-#define REG_EPPI2_FS1_WLHB              0xFFC18824         /* EPPI2 FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register */
-#define REG_EPPI2_FS1_PASPL             0xFFC18828         /* EPPI2 FS1 Period Register / EPPI Active Samples Per Line Register */
-#define REG_EPPI2_FS2_WLVB              0xFFC1882C         /* EPPI2 FS2 Width Register / EPPI Lines Of Vertical Blanking Register */
-#define REG_EPPI2_FS2_PALPF             0xFFC18830         /* EPPI2 FS2 Period Register / EPPI Active Lines Per Field Register */
-#define REG_EPPI2_IMSK                  0xFFC18834         /* EPPI2 Interrupt Mask Register */
-#define REG_EPPI2_ODDCLIP               0xFFC1883C         /* EPPI2 Clipping Register for ODD (Chroma) Data */
-#define REG_EPPI2_EVENCLIP              0xFFC18840         /* EPPI2 Clipping Register for EVEN (Luma) Data */
-#define REG_EPPI2_FS1_DLY               0xFFC18844         /* EPPI2 Frame Sync 1 Delay Value */
-#define REG_EPPI2_FS2_DLY               0xFFC18848         /* EPPI2 Frame Sync 2 Delay Value */
-#define REG_EPPI2_CTL2                  0xFFC1884C         /* EPPI2 Control Register 2 */
-
-/* =========================
-        EPPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_STAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_STAT_FLD                   15                               /* Current Field Received by EPPI */
-#define BITP_EPPI_STAT_ERRDET                14                               /* Preamble Error Detected */
-#define BITP_EPPI_STAT_PXPERR                 7                               /* PxP Ready Error */
-#define BITP_EPPI_STAT_ERRNCOR                6                               /* Preamble Error Not Corrected */
-#define BITP_EPPI_STAT_FTERRUNDR              5                               /* Frame Track Underflow */
-#define BITP_EPPI_STAT_FTERROVR               4                               /* Frame Track Overflow */
-#define BITP_EPPI_STAT_LTERRUNDR              3                               /* Line Track Underflow */
-#define BITP_EPPI_STAT_LTERROVR               2                               /* Line Track Overflow */
-#define BITP_EPPI_STAT_YFIFOERR               1                               /* Luma FIFO Error */
-#define BITP_EPPI_STAT_CFIFOERR               0                               /* Chroma FIFO Error */
-
-#define BITM_EPPI_STAT_FLD                   (_ADI_MSK(0x00008000,uint32_t))  /* Current Field Received by EPPI */
-#define ENUM_EPPI_STAT_FIELD1                (_ADI_MSK(0x00000000,uint32_t))  /* FLD: Field 1 */
-#define ENUM_EPPI_STAT_FIELD2                (_ADI_MSK(0x00008000,uint32_t))  /* FLD: Field 2 */
-
-#define BITM_EPPI_STAT_ERRDET                (_ADI_MSK(0x00004000,uint32_t))  /* Preamble Error Detected */
-#define ENUM_EPPI_STAT_NO_PRERR              (_ADI_MSK(0x00000000,uint32_t))  /* ERRDET: No preamble error detected */
-#define ENUM_EPPI_STAT_PRERR                 (_ADI_MSK(0x00004000,uint32_t))  /* ERRDET: Preamble error detected */
-#define BITM_EPPI_STAT_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error */
-
-#define BITM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* Preamble Error Not Corrected */
-#define ENUM_EPPI_STAT_NO_ERRNCOR            (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: No uncorrected preamble error has occurred */
-#define ENUM_EPPI_STAT_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Preamble error detected but not corrected */
-
-#define BITM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow */
-#define ENUM_EPPI_STAT_NO_FTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow */
-#define ENUM_EPPI_STAT_NO_FTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow */
-#define ENUM_EPPI_STAT_NO_LTERRUNDR          (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Error Occurred */
-
-#define BITM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow */
-#define ENUM_EPPI_STAT_NO_LTERROVR           (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: No Error Detected */
-#define ENUM_EPPI_STAT_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Error Occurred */
-
-#define BITM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* Luma FIFO Error */
-#define ENUM_EPPI_STAT_NO_YFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Error Occurred */
-
-#define BITM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* Chroma FIFO Error */
-#define ENUM_EPPI_STAT_NO_CFIFOERR           (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: No Error Detected */
-#define ENUM_EPPI_STAT_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HCNT_VALUE                  0                               /* Horizontal Transfer Count */
-#define BITM_EPPI_HCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_HDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_HDLY_VALUE                  0                               /* Horizontal Delay Count */
-#define BITM_EPPI_HDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VCNT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VCNT_VALUE                  0                               /* Vertical Transfer Count */
-#define BITM_EPPI_VCNT_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Transfer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_VDLY                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_VDLY_VALUE                  0                               /* Vertical Delay Count */
-#define BITM_EPPI_VDLY_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FRAME                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FRAME_VALUE                 0                               /* Lines Per Frame */
-#define BITM_EPPI_FRAME_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lines Per Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_LINE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_LINE_VALUE                  0                               /* Samples Per Line */
-#define BITM_EPPI_LINE_VALUE                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Samples Per Line */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CLKDIV                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CLKDIV_VALUE                0                               /* Internal Clock Divider */
-#define BITM_EPPI_CLKDIV_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* Internal Clock Divider */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL_CLKGATEN               31                               /* Clock Gating Enable */
-#define BITP_EPPI_CTL_MUXSEL                 30                               /* MUX Select */
-#define BITP_EPPI_CTL_DMAFINEN               29                               /* DMA Finish Enable */
-#define BITP_EPPI_CTL_DMACFG                 28                               /* One or Two DMA Channels Mode */
-#define BITP_EPPI_CTL_RGBFMTEN               27                               /* RGB Formatting Enable */
-#define BITP_EPPI_CTL_SPLTWRD                26                               /* Split Word */
-#define BITP_EPPI_CTL_SUBSPLTODD             25                               /* Sub-Split Odd Samples */
-#define BITP_EPPI_CTL_SPLTEO                 24                               /* Split Even and Odd Data Samples */
-#define BITP_EPPI_CTL_SWAPEN                 23                               /* Swap Enable */
-#define BITP_EPPI_CTL_PACKEN                 22                               /* Pack/Unpack Enable */
-#define BITP_EPPI_CTL_SKIPEO                 21                               /* Skip Even or Odd */
-#define BITP_EPPI_CTL_SKIPEN                 20                               /* Skip Enable */
-#define BITP_EPPI_CTL_DMIRR                  19                               /* Data Mirroring */
-#define BITP_EPPI_CTL_DLEN                   16                               /* Data Length */
-#define BITP_EPPI_CTL_POLS                   14                               /* Frame Sync Polarity */
-#define BITP_EPPI_CTL_POLC                   12                               /* Clock Polarity */
-#define BITP_EPPI_CTL_SIGNEXT                11                               /* Sign Extension */
-#define BITP_EPPI_CTL_IFSGEN                 10                               /* Internal Frame Sync Generation */
-#define BITP_EPPI_CTL_ICLKGEN                 9                               /* Internal Clock Generation */
-#define BITP_EPPI_CTL_BLANKGEN                8                               /* king Generation (ITU Output Mode) */
-#define BITP_EPPI_CTL_ITUTYPE                 7                               /* ITU Interlace or Progressive */
-#define BITP_EPPI_CTL_FLDSEL                  6                               /* Field Select/Trigger */
-#define BITP_EPPI_CTL_FSCFG                   4                               /* Frame Sync Configuration */
-#define BITP_EPPI_CTL_XFRTYPE                 2                               /* Transfer Type ( Operating Mode) */
-#define BITP_EPPI_CTL_DIR                     1                               /* PPI Direction */
-#define BITP_EPPI_CTL_EN                      0                               /* PPI Enable */
-
-#define BITM_EPPI_CTL_CLKGATEN               (_ADI_MSK(0x80000000,uint32_t))  /* Clock Gating Enable */
-#define ENUM_EPPI_CTL_CLKGATE_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* CLKGATEN: Disable */
-#define ENUM_EPPI_CTL_CLKGATE_EN             (_ADI_MSK(0x80000000,uint32_t))  /* CLKGATEN: Enable */
-
-#define BITM_EPPI_CTL_MUXSEL                 (_ADI_MSK(0x40000000,uint32_t))  /* MUX Select */
-#define ENUM_EPPI_CTL_MUXSEL0                (_ADI_MSK(0x00000000,uint32_t))  /* MUXSEL: Normal Operation */
-#define ENUM_EPPI_CTL_MUXSEL1                (_ADI_MSK(0x40000000,uint32_t))  /* MUXSEL: Multiplexed Operation */
-
-#define BITM_EPPI_CTL_DMAFINEN               (_ADI_MSK(0x20000000,uint32_t))  /* DMA Finish Enable */
-#define ENUM_EPPI_CTL_FINISH_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* DMAFINEN: No Finish Command */
-#define ENUM_EPPI_CTL_FINISH_EN              (_ADI_MSK(0x20000000,uint32_t))  /* DMAFINEN: Enable Send Finish Command */
-
-#define BITM_EPPI_CTL_DMACFG                 (_ADI_MSK(0x10000000,uint32_t))  /* One or Two DMA Channels Mode */
-#define ENUM_EPPI_CTL_DMA1CHAN               (_ADI_MSK(0x00000000,uint32_t))  /* DMACFG: PPI uses one DMA Channel */
-#define ENUM_EPPI_CTL_DMA2CHAN               (_ADI_MSK(0x10000000,uint32_t))  /* DMACFG: PPI uses two DMA Channels */
-
-#define BITM_EPPI_CTL_RGBFMTEN               (_ADI_MSK(0x08000000,uint32_t))  /* RGB Formatting Enable */
-#define ENUM_EPPI_CTL_RGBFMT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RGBFMTEN: Disable RGB Formatted Output */
-#define ENUM_EPPI_CTL_RGBFMT_EN              (_ADI_MSK(0x08000000,uint32_t))  /* RGBFMTEN: Enable RGB Formatted Output */
-
-#define BITM_EPPI_CTL_SPLTWRD                (_ADI_MSK(0x04000000,uint32_t))  /* Split Word */
-#define ENUM_EPPI_CTL_NO_WORDSPLIT           (_ADI_MSK(0x00000000,uint32_t))  /* SPLTWRD: PPI_DATA has (DLEN-1) bits of Y or Cr or Cb */
-#define ENUM_EPPI_CTL_WORDSPLIT              (_ADI_MSK(0x04000000,uint32_t))  /* SPLTWRD: PPI_DATA contains 2 elements per word */
-
-#define BITM_EPPI_CTL_SUBSPLTODD             (_ADI_MSK(0x02000000,uint32_t))  /* Sub-Split Odd Samples */
-#define ENUM_EPPI_CTL_NO_SUBSPLIT            (_ADI_MSK(0x00000000,uint32_t))  /* SUBSPLTODD: Disable */
-#define ENUM_EPPI_CTL_SUBSPLIT_ODD           (_ADI_MSK(0x02000000,uint32_t))  /* SUBSPLTODD: Enable */
-
-#define BITM_EPPI_CTL_SPLTEO                 (_ADI_MSK(0x01000000,uint32_t))  /* Split Even and Odd Data Samples */
-#define ENUM_EPPI_CTL_SPLTEO_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SPLTEO: Do Not Split Samples */
-#define ENUM_EPPI_CTL_SPLTEO_EN              (_ADI_MSK(0x01000000,uint32_t))  /* SPLTEO: Split Even/Odd Samples */
-
-#define BITM_EPPI_CTL_SWAPEN                 (_ADI_MSK(0x00800000,uint32_t))  /* Swap Enable */
-#define ENUM_EPPI_CTL_SWAP_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* SWAPEN: Disable */
-#define ENUM_EPPI_CTL_SWAP_EN                (_ADI_MSK(0x00800000,uint32_t))  /* SWAPEN: Enable */
-
-#define BITM_EPPI_CTL_PACKEN                 (_ADI_MSK(0x00400000,uint32_t))  /* Pack/Unpack Enable */
-#define ENUM_EPPI_CTL_PACK_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* PACKEN: Disable */
-#define ENUM_EPPI_CTL_PACK_EN                (_ADI_MSK(0x00400000,uint32_t))  /* PACKEN: Enable */
-
-#define BITM_EPPI_CTL_SKIPEO                 (_ADI_MSK(0x00200000,uint32_t))  /* Skip Even or Odd */
-#define ENUM_EPPI_CTL_SKIPODD                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEO: Skip Odd Samples */
-#define ENUM_EPPI_CTL_SKIPEVEN               (_ADI_MSK(0x00200000,uint32_t))  /* SKIPEO: Skip Even Samples */
-
-#define BITM_EPPI_CTL_SKIPEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Skip Enable */
-#define ENUM_EPPI_CTL_NO_SKIP                (_ADI_MSK(0x00000000,uint32_t))  /* SKIPEN: No Samples Skipping */
-#define ENUM_EPPI_CTL_SKIP                   (_ADI_MSK(0x00100000,uint32_t))  /* SKIPEN: Skip Alternate Samples */
-
-#define BITM_EPPI_CTL_DMIRR                  (_ADI_MSK(0x00080000,uint32_t))  /* Data Mirroring */
-#define ENUM_EPPI_CTL_NO_MIRROR              (_ADI_MSK(0x00000000,uint32_t))  /* DMIRR: No Data Mirroring */
-#define ENUM_EPPI_CTL_MIRROR                 (_ADI_MSK(0x00080000,uint32_t))  /* DMIRR: Data Mirroring */
-
-#define BITM_EPPI_CTL_DLEN                   (_ADI_MSK(0x00070000,uint32_t))  /* Data Length */
-#define ENUM_EPPI_CTL_DLEN08                 (_ADI_MSK(0x00000000,uint32_t))  /* DLEN: 8 bits */
-#define ENUM_EPPI_CTL_DLEN10                 (_ADI_MSK(0x00010000,uint32_t))  /* DLEN: 10 bits */
-#define ENUM_EPPI_CTL_DLEN12                 (_ADI_MSK(0x00020000,uint32_t))  /* DLEN: 12 bits */
-#define ENUM_EPPI_CTL_DLEN14                 (_ADI_MSK(0x00030000,uint32_t))  /* DLEN: 14 bits */
-#define ENUM_EPPI_CTL_DLEN16                 (_ADI_MSK(0x00040000,uint32_t))  /* DLEN: 16 bits */
-#define ENUM_EPPI_CTL_DLEN18                 (_ADI_MSK(0x00050000,uint32_t))  /* DLEN: 18 bits */
-#define ENUM_EPPI_CTL_DLEN20                 (_ADI_MSK(0x00060000,uint32_t))  /* DLEN: 20 bits */
-#define ENUM_EPPI_CTL_DLEN24                 (_ADI_MSK(0x00070000,uint32_t))  /* DLEN: 24 bits */
-
-#define BITM_EPPI_CTL_POLS                   (_ADI_MSK(0x0000C000,uint32_t))  /* Frame Sync Polarity */
-#define ENUM_EPPI_CTL_FS1HI_FS2HI            (_ADI_MSK(0x00000000,uint32_t))  /* POLS: FS1 and FS2 are active high */
-#define ENUM_EPPI_CTL_FS1LO_FS2HI            (_ADI_MSK(0x00004000,uint32_t))  /* POLS: FS1 is active low. FS2 is active high */
-#define ENUM_EPPI_CTL_FS1HI_FS2LO            (_ADI_MSK(0x00008000,uint32_t))  /* POLS: FS1 is active high. FS2 is active low */
-#define ENUM_EPPI_CTL_FS1LO_FS2LO            (_ADI_MSK(0x0000C000,uint32_t))  /* POLS: FS1 and FS2 are active low */
-
-#define BITM_EPPI_CTL_POLC                   (_ADI_MSK(0x00003000,uint32_t))  /* Clock Polarity */
-#define ENUM_EPPI_CTL_POLC00                 (_ADI_MSK(0x00000000,uint32_t))  /* POLC: Clock/Sync polarity mode 0 */
-#define ENUM_EPPI_CTL_POLC01                 (_ADI_MSK(0x00001000,uint32_t))  /* POLC: Clock/Sync polarity mode 1 */
-#define ENUM_EPPI_CTL_POLC10                 (_ADI_MSK(0x00002000,uint32_t))  /* POLC: Clock/Sync polarity mode 2 */
-#define ENUM_EPPI_CTL_POLC11                 (_ADI_MSK(0x00003000,uint32_t))  /* POLC: Clock/Sync polarity mode 3 */
-
-#define BITM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* Sign Extension */
-#define ENUM_EPPI_CTL_ZEROFILL               (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Filled */
-#define ENUM_EPPI_CTL_SIGNEXT                (_ADI_MSK(0x00000800,uint32_t))  /* SIGNEXT: Sign Extended */
-
-#define BITM_EPPI_CTL_IFSGEN                 (_ADI_MSK(0x00000400,uint32_t))  /* Internal Frame Sync Generation */
-#define ENUM_EPPI_CTL_EXTFS                  (_ADI_MSK(0x00000000,uint32_t))  /* IFSGEN: External Frame Sync */
-#define ENUM_EPPI_CTL_INTFS                  (_ADI_MSK(0x00000400,uint32_t))  /* IFSGEN: Internal Frame Sync */
-
-#define BITM_EPPI_CTL_ICLKGEN                (_ADI_MSK(0x00000200,uint32_t))  /* Internal Clock Generation */
-#define ENUM_EPPI_CTL_EXTCLK                 (_ADI_MSK(0x00000000,uint32_t))  /* ICLKGEN: External Clock */
-#define ENUM_EPPI_CTL_INTCLK                 (_ADI_MSK(0x00000200,uint32_t))  /* ICLKGEN: Internal Clock */
-
-#define BITM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* king Generation (ITU Output Mode) */
-#define ENUM_EPPI_CTL_NO_BLANKGEN            (_ADI_MSK(0x00000000,uint32_t))  /* BLANKGEN: Disable */
-#define ENUM_EPPI_CTL_BLANKGEN               (_ADI_MSK(0x00000100,uint32_t))  /* BLANKGEN: Enable */
-
-#define BITM_EPPI_CTL_ITUTYPE                (_ADI_MSK(0x00000080,uint32_t))  /* ITU Interlace or Progressive */
-#define ENUM_EPPI_CTL_INTERLACED             (_ADI_MSK(0x00000000,uint32_t))  /* ITUTYPE: Interlaced */
-#define ENUM_EPPI_CTL_PROGRESSIVE            (_ADI_MSK(0x00000080,uint32_t))  /* ITUTYPE: Progressive */
-
-#define BITM_EPPI_CTL_FLDSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* Field Select/Trigger */
-#define ENUM_EPPI_CTL_FLDSEL_LO              (_ADI_MSK(0x00000000,uint32_t))  /* FLDSEL: Field Mode 0 */
-#define ENUM_EPPI_CTL_FLDSEL_HI              (_ADI_MSK(0x00000040,uint32_t))  /* FLDSEL: Field Mode 1 */
-
-#define BITM_EPPI_CTL_FSCFG                  (_ADI_MSK(0x00000030,uint32_t))  /* Frame Sync Configuration */
-#define ENUM_EPPI_CTL_SYNC0                  (_ADI_MSK(0x00000000,uint32_t))  /* FSCFG: Sync Mode 0 */
-#define ENUM_EPPI_CTL_SYNC1                  (_ADI_MSK(0x00000010,uint32_t))  /* FSCFG: Sync Mode 1 */
-#define ENUM_EPPI_CTL_SYNC2                  (_ADI_MSK(0x00000020,uint32_t))  /* FSCFG: Sync Mode 2 */
-#define ENUM_EPPI_CTL_SYNC3                  (_ADI_MSK(0x00000030,uint32_t))  /* FSCFG: Sync Mode 3 */
-
-#define BITM_EPPI_CTL_XFRTYPE                (_ADI_MSK(0x0000000C,uint32_t))  /* Transfer Type ( Operating Mode) */
-#define ENUM_EPPI_CTL_ACTIVE656              (_ADI_MSK(0x00000000,uint32_t))  /* XFRTYPE: ITU656 Active Video Only Mode */
-#define ENUM_EPPI_CTL_ENTIRE656              (_ADI_MSK(0x00000004,uint32_t))  /* XFRTYPE: ITU656 Entire Field Mode */
-#define ENUM_EPPI_CTL_VERT656                (_ADI_MSK(0x00000008,uint32_t))  /* XFRTYPE: ITU656 Vertical Blanking Only Mode */
-#define ENUM_EPPI_CTL_NON656                 (_ADI_MSK(0x0000000C,uint32_t))  /* XFRTYPE: Non-ITU656 Mode (GP Mode) */
-
-#define BITM_EPPI_CTL_DIR                    (_ADI_MSK(0x00000002,uint32_t))  /* PPI Direction */
-#define ENUM_EPPI_CTL_RXMODE                 (_ADI_MSK(0x00000000,uint32_t))  /* DIR: Receive Mode */
-#define ENUM_EPPI_CTL_TXMODE                 (_ADI_MSK(0x00000002,uint32_t))  /* DIR: Transmit Mode */
-
-#define BITM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* PPI Enable */
-#define ENUM_EPPI_CTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_EPPI_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_WLVB                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_WLVB_F2VBAD            24                               /* Field 2 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F2VBBD            16                               /* Field 2 Vertical Blanking Before Data */
-#define BITP_EPPI_FS2_WLVB_F1VBAD             8                               /* Field 1 Vertical Blanking After Data */
-#define BITP_EPPI_FS2_WLVB_F1VBBD             0                               /* Field 1 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F2VBAD            (_ADI_MSK(0xFF000000,uint32_t))  /* Field 2 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F2VBBD            (_ADI_MSK(0x00FF0000,uint32_t))  /* Field 2 Vertical Blanking Before Data */
-#define BITM_EPPI_FS2_WLVB_F1VBAD            (_ADI_MSK(0x0000FF00,uint32_t))  /* Field 1 Vertical Blanking After Data */
-#define BITM_EPPI_FS2_WLVB_F1VBBD            (_ADI_MSK(0x000000FF,uint32_t))  /* Field 1 Vertical Blanking Before Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_FS2_PALPF                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_FS2_PALPF_F2ACT            16                               /* Field 2 Active */
-#define BITP_EPPI_FS2_PALPF_F1ACT             0                               /* Field 1 Active */
-#define BITM_EPPI_FS2_PALPF_F2ACT            (_ADI_MSK(0xFFFF0000,uint32_t))  /* Field 2 Active */
-#define BITM_EPPI_FS2_PALPF_F1ACT            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Field 1 Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_IMSK_PXPERR                 7                               /* PxP Ready Error Interrupt Mask */
-#define BITP_EPPI_IMSK_ERRNCOR                6                               /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERRUNDR              5                               /* Frame Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_FTERROVR               4                               /* Frame Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERRUNDR              3                               /* Line Track Underflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_LTERROVR               2                               /* Line Track Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_YFIFOERR               1                               /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define BITP_EPPI_IMSK_CFIFOERR               0                               /* CFIFO Underflow or Overflow Error Interrupt Mask */
-
-#define BITM_EPPI_IMSK_PXPERR                (_ADI_MSK(0x00000080,uint32_t))  /* PxP Ready Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_PXPERR_UMSK           (_ADI_MSK(0x00000000,uint32_t))  /* PXPERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_PXPERR_MSK            (_ADI_MSK(0x00000080,uint32_t))  /* PXPERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_ERRNCOR               (_ADI_MSK(0x00000040,uint32_t))  /* ITU Preamble Error Not Corrected Interrupt Mask */
-#define ENUM_EPPI_IMSK_ERRNCOR_UMSK          (_ADI_MSK(0x00000000,uint32_t))  /* ERRNCOR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_ERRNCOR_MSK           (_ADI_MSK(0x00000040,uint32_t))  /* ERRNCOR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERRUNDR             (_ADI_MSK(0x00000020,uint32_t))  /* Frame Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* FTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERRUNDR_MSK         (_ADI_MSK(0x00000020,uint32_t))  /* FTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_FTERROVR              (_ADI_MSK(0x00000010,uint32_t))  /* Frame Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_FTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* FTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_FTERROVR_MSK          (_ADI_MSK(0x00000010,uint32_t))  /* FTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERRUNDR             (_ADI_MSK(0x00000008,uint32_t))  /* Line Track Underflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERRUNDR_UMSK        (_ADI_MSK(0x00000000,uint32_t))  /* LTERRUNDR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERRUNDR_MSK         (_ADI_MSK(0x00000008,uint32_t))  /* LTERRUNDR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_LTERROVR              (_ADI_MSK(0x00000004,uint32_t))  /* Line Track Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_LTERROVR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* LTERROVR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_LTERROVR_MSK          (_ADI_MSK(0x00000004,uint32_t))  /* LTERROVR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_YFIFOERR              (_ADI_MSK(0x00000002,uint32_t))  /* YFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_YFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* YFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_YFIFOERR_MSK          (_ADI_MSK(0x00000002,uint32_t))  /* YFIFOERR: Mask Interrupt */
-
-#define BITM_EPPI_IMSK_CFIFOERR              (_ADI_MSK(0x00000001,uint32_t))  /* CFIFO Underflow or Overflow Error Interrupt Mask */
-#define ENUM_EPPI_IMSK_CFIFOERR_UMSK         (_ADI_MSK(0x00000000,uint32_t))  /* CFIFOERR: Unmask Interrupt */
-#define ENUM_EPPI_IMSK_CFIFOERR_MSK          (_ADI_MSK(0x00000001,uint32_t))  /* CFIFOERR: Mask Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_ODDCLIP                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_ODDCLIP_HIGHODD            16                               /* High Odd Clipping Threshold (Chroma Data) */
-#define BITP_EPPI_ODDCLIP_LOWODD              0                               /* Low Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_HIGHODD            (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Odd Clipping Threshold (Chroma Data) */
-#define BITM_EPPI_ODDCLIP_LOWODD             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Odd Clipping Threshold (Chroma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_EVENCLIP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_EVENCLIP_HIGHEVEN          16                               /* High Even Clipping Threshold (Luma Data) */
-#define BITP_EPPI_EVENCLIP_LOWEVEN            0                               /* Low Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_HIGHEVEN          (_ADI_MSK(0xFFFF0000,uint32_t))  /* High Even Clipping Threshold (Luma Data) */
-#define BITM_EPPI_EVENCLIP_LOWEVEN           (_ADI_MSK(0x0000FFFF,uint32_t))  /* Low Even Clipping Threshold (Luma Data) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EPPI_CTL2                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EPPI_CTL2_FS1FINEN               1                               /* HSYNC Finish Enable */
-
-#define BITM_EPPI_CTL2_FS1FINEN              (_ADI_MSK(0x00000002,uint32_t))  /* HSYNC Finish Enable */
-#define ENUM_EPPI_CTL2_FS2FIN_EN             (_ADI_MSK(0x00000000,uint32_t))  /* FS1FINEN: Finish sent after frame RX done */
-#define ENUM_EPPI_CTL2_FS1FIN_EN             (_ADI_MSK(0x00000002,uint32_t))  /* FS1FINEN: Finish sent after frame/line RX done */
-
-/* ==================================================
-        Pixel Compositor Registers
-   ================================================== */
-
-/* =========================
-        PIXC0
-   ========================= */
-#define REG_PIXC0_CTL                   0xFFC19000         /* PIXC0 Control Register */
-#define REG_PIXC0_PPL                   0xFFC19004         /* PIXC0 Pixels Per Line Register */
-#define REG_PIXC0_LPF                   0xFFC19008         /* PIXC0 Line Per Frame Register */
-#define REG_PIXC0_HSTART_A              0xFFC1900C         /* PIXC0 Overlay A Horizontal Start Register */
-#define REG_PIXC0_HEND_A                0xFFC19010         /* PIXC0 Overlay A Horizontal End Register */
-#define REG_PIXC0_VSTART_A              0xFFC19014         /* PIXC0 Overlay A Vertical Start Register */
-#define REG_PIXC0_VEND_A                0xFFC19018         /* PIXC0 Overlay A Vertical End Register */
-#define REG_PIXC0_TRANSP_A              0xFFC1901C         /* PIXC0 Overlay A Transparency Ratio Register */
-#define REG_PIXC0_HSTART_B              0xFFC19020         /* PIXC0 Overlay B Horizontal Start Register */
-#define REG_PIXC0_HEND_B                0xFFC19024         /* PIXC0 Overlay B Horizontal End Register */
-#define REG_PIXC0_VSTART_B              0xFFC19028         /* PIXC0 Overlay B Vertical Start Register */
-#define REG_PIXC0_VEND_B                0xFFC1902C         /* PIXC0 Overlay B Vertical End Register */
-#define REG_PIXC0_TRANSP_B              0xFFC19030         /* PIXC0 Overlay B Transparency Ratio Register */
-#define REG_PIXC0_IRQSTAT               0xFFC1903C         /* PIXC0 Interrupt Status Register */
-#define REG_PIXC0_CONRY                 0xFFC19040         /* PIXC0 RY Conversion Component Register */
-#define REG_PIXC0_CONGU                 0xFFC19044         /* PIXC0 GU Conversion Component Register */
-#define REG_PIXC0_CONBV                 0xFFC19048         /* PIXC0 BV Conversion Component Register */
-#define REG_PIXC0_CCBIAS                0xFFC1904C         /* PIXC0 Conversion Bias Register */
-#define REG_PIXC0_TC                    0xFFC19050         /* PIXC0 Transparency Color Register */
-#define REG_PIXC0_REVID                 0xFFC19054         /* PIXC0 Revision Id */
-
-/* =========================
-        PIXC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CTL_ORGBFRMT               10                               /* Output RGB Data Format */
-#define BITP_PIXC_CTL_IRGBFRMT                8                               /* Input Image Channel RGB Data Format */
-#define BITP_PIXC_CTL_ENTC                    7                               /* Enable Transparent Color */
-#define BITP_PIXC_CTL_UDSMOD                  6                               /* Up/Down Sampling Mode */
-#define BITP_PIXC_CTL_OUTFRMT                 5                               /* Output Data Format */
-#define BITP_PIXC_CTL_OVFRMT                  4                               /* Overlay Data Format */
-#define BITP_PIXC_CTL_IFRMT                   3                               /* Image Data Format */
-#define BITP_PIXC_CTL_OVENB                   2                               /* Overlay Block B Enable */
-#define BITP_PIXC_CTL_OVENA                   1                               /* Overlay Block A Enable */
-#define BITP_PIXC_CTL_EN                      0                               /* Overlay Manager enable (module enable) */
-#define BITM_PIXC_CTL_ORGBFRMT               (_ADI_MSK(0x00000C00,uint32_t))  /* Output RGB Data Format */
-#define BITM_PIXC_CTL_IRGBFRMT               (_ADI_MSK(0x00000300,uint32_t))  /* Input Image Channel RGB Data Format */
-#define BITM_PIXC_CTL_ENTC                   (_ADI_MSK(0x00000080,uint32_t))  /* Enable Transparent Color */
-#define BITM_PIXC_CTL_UDSMOD                 (_ADI_MSK(0x00000040,uint32_t))  /* Up/Down Sampling Mode */
-#define BITM_PIXC_CTL_OUTFRMT                (_ADI_MSK(0x00000020,uint32_t))  /* Output Data Format */
-#define BITM_PIXC_CTL_OVFRMT                 (_ADI_MSK(0x00000010,uint32_t))  /* Overlay Data Format */
-#define BITM_PIXC_CTL_IFRMT                  (_ADI_MSK(0x00000008,uint32_t))  /* Image Data Format */
-#define BITM_PIXC_CTL_OVENB                  (_ADI_MSK(0x00000004,uint32_t))  /* Overlay Block B Enable */
-#define BITM_PIXC_CTL_OVENA                  (_ADI_MSK(0x00000002,uint32_t))  /* Overlay Block A Enable */
-#define BITM_PIXC_CTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Overlay Manager enable (module enable) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TRANSP_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TRANSP_A_VALUE              0                               /* Overlay Transparency Ratio Values */
-#define BITM_PIXC_TRANSP_A_VALUE             (_ADI_MSK(0x0000000F,uint16_t))  /* Overlay Transparency Ratio Values */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TRANSP_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TRANSP_B_VALUE              0                               /* Overlay Transparency Ratio Values */
-#define BITM_PIXC_TRANSP_B_VALUE             (_ADI_MSK(0x0000000F,uint16_t))  /* Overlay Transparency Ratio Values */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_IRQSTAT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_IRQSTAT_FRMSTAT             3                               /* Frame Interrupt Status */
-#define BITP_PIXC_IRQSTAT_OVSTAT              2                               /* Overlay Interrupt Status */
-#define BITP_PIXC_IRQSTAT_FRMEN               1                               /* Frame Interrupt  Enable */
-#define BITP_PIXC_IRQSTAT_OVEN                0                               /* Overlay Interrupt Enable */
-#define BITM_PIXC_IRQSTAT_FRMSTAT            (_ADI_MSK(0x00000008,uint16_t))  /* Frame Interrupt Status */
-#define BITM_PIXC_IRQSTAT_OVSTAT             (_ADI_MSK(0x00000004,uint16_t))  /* Overlay Interrupt Status */
-#define BITM_PIXC_IRQSTAT_FRMEN              (_ADI_MSK(0x00000002,uint16_t))  /* Frame Interrupt  Enable */
-#define BITM_PIXC_IRQSTAT_OVEN               (_ADI_MSK(0x00000001,uint16_t))  /* Overlay Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONRY                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONRY_RYMULT4              30                               /* Multiply the Row by 4 */
-#define BITP_PIXC_CONRY_A13                  20                               /* A13 element in the coefficient matrix */
-#define BITP_PIXC_CONRY_A12                  10                               /* A12 element in the coefficient matrix */
-#define BITP_PIXC_CONRY_A11                   0                               /* A11 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_RYMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply the Row by 4 */
-#define BITM_PIXC_CONRY_A13                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A13 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_A12                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A12 element in the coefficient matrix */
-#define BITM_PIXC_CONRY_A11                  (_ADI_MSK(0x000003FF,uint32_t))  /* A11 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONGU                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONGU_GUMULT4              30                               /* Multiply The Row By 4 */
-#define BITP_PIXC_CONGU_A23                  20                               /* A23 element in the coefficient matrix */
-#define BITP_PIXC_CONGU_A22                  10                               /* A22 element in the coefficient matrix */
-#define BITP_PIXC_CONGU_A21                   0                               /* A21 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_GUMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply The Row By 4 */
-#define BITM_PIXC_CONGU_A23                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A23 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_A22                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A22 element in the coefficient matrix */
-#define BITM_PIXC_CONGU_A21                  (_ADI_MSK(0x000003FF,uint32_t))  /* A21 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CONBV                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CONBV_BVMULT4              30                               /* Multiply The Row By 4 */
-#define BITP_PIXC_CONBV_A33                  20                               /* A33 element in the coefficient matrix */
-#define BITP_PIXC_CONBV_A32                  10                               /* A32 element in the coefficient matrix */
-#define BITP_PIXC_CONBV_A31                   0                               /* A31 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_BVMULT4              (_ADI_MSK(0x40000000,uint32_t))  /* Multiply The Row By 4 */
-#define BITM_PIXC_CONBV_A33                  (_ADI_MSK(0x3FF00000,uint32_t))  /* A33 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_A32                  (_ADI_MSK(0x000FFC00,uint32_t))  /* A32 element in the coefficient matrix */
-#define BITM_PIXC_CONBV_A31                  (_ADI_MSK(0x000003FF,uint32_t))  /* A31 element in the coefficient matrix */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_CCBIAS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_CCBIAS_A34                 20                               /* A34 in bias vector */
-#define BITP_PIXC_CCBIAS_A24                 10                               /* A24 in bias vector */
-#define BITP_PIXC_CCBIAS_A14                  0                               /* A14 in bias vector */
-#define BITM_PIXC_CCBIAS_A34                 (_ADI_MSK(0x3FF00000,uint32_t))  /* A34 in bias vector */
-#define BITM_PIXC_CCBIAS_A24                 (_ADI_MSK(0x000FFC00,uint32_t))  /* A24 in bias vector */
-#define BITM_PIXC_CCBIAS_A14                 (_ADI_MSK(0x000003FF,uint32_t))  /* A14 in bias vector */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_TC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_TC_BVT                     16                               /* Trans. color - B/V component */
-#define BITP_PIXC_TC_GUT                      8                               /* Trans. color - G/U component */
-#define BITP_PIXC_TC_RYT                      0                               /* Trans. color - R/Y component */
-#define BITM_PIXC_TC_BVT                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Trans. color - B/V component */
-#define BITM_PIXC_TC_GUT                     (_ADI_MSK(0x0000FF00,uint32_t))  /* Trans. color - G/U component */
-#define BITM_PIXC_TC_RYT                     (_ADI_MSK(0x000000FF,uint32_t))  /* Trans. color - R/Y component */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PIXC_REVID                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PIXC_REVID_MAJOR                 4                               /* Major Version ID */
-#define BITP_PIXC_REVID_REV                   0                               /* Incremental Version ID */
-#define BITM_PIXC_REVID_MAJOR                (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_PIXC_REVID_REV                  (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ==================================================
-        PVP Registers
-   ================================================== */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP                             Block level enums
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define ENUM_PVP_GCFG                   0x00          /* PVP Block ID Code for GCFG */
-#define ENUM_PVP_OPF0                   0x01          /* PVP Block ID Code for OPF0 */
-#define ENUM_PVP_OPF1                   0x02          /* PVP Block ID Code for OPF1 */
-#define ENUM_PVP_OPF2                   0x03          /* PVP Block ID Code for OPF2 */
-#define ENUM_PVP_OPF3                   0x04          /* PVP Block ID Code for OPF3 */
-#define ENUM_PVP_PEC                    0x05          /* PVP Block ID Code for PEC */
-#define ENUM_PVP_IIM0                   0x06          /* PVP Block ID Code for IIM0 */
-#define ENUM_PVP_IIM1                   0x07          /* PVP Block ID Code for IIM1 */
-#define ENUM_PVP_ACU                    0x08          /* PVP Block ID Code for ACU */
-#define ENUM_PVP_UDS                    0x0A          /* PVP Block ID Code for UDS */
-#define ENUM_PVP_IPF0                   0x0C          /* PVP Block ID Code for IPF0 */
-#define ENUM_PVP_IPF1                   0x0E          /* PVP Block ID Code for IPF1 */
-#define ENUM_PVP_CNV0                   0x10          /* PVP Block ID Code for CNV0 */
-#define ENUM_PVP_CNV1                   0x14          /* PVP Block ID Code for CNV1 */
-#define ENUM_PVP_CNV2                   0x18          /* PVP Block ID Code for CNV2 */
-#define ENUM_PVP_CNV3                   0x1C          /* PVP Block ID Code for CNV3 */
-#define ENUM_PVP_THC0                   0x20          /* PVP Block ID Code for THC0 */
-#define ENUM_PVP_THC1                   0x28          /* PVP Block ID Code for THC1 */
-#define ENUM_PVP_PMA                    0x30          /* PVP Block ID Code for PMA */
-
-/* =========================
-        PVP0
-   ========================= */
-#define REG_PVP0_REVID                  0xFFC1A000         /* PVP0 Revision ID */
-#define REG_PVP0_CTL                    0xFFC1A004         /* PVP0 Control */
-#define REG_PVP0_IMSK0                  0xFFC1A008         /* PVP0 Interrupt Mask n */
-#define REG_PVP0_IMSK1                  0xFFC1A00C         /* PVP0 Interrupt Mask n */
-#define REG_PVP0_STAT                   0xFFC1A010         /* PVP0 Status */
-#define REG_PVP0_ILAT                   0xFFC1A014         /* PVP0 Interrupt Latch Status n */
-#define REG_PVP0_IREQ0                  0xFFC1A018         /* PVP0 Interrupt Request n */
-#define REG_PVP0_IREQ1                  0xFFC1A01C         /* PVP0 Interrupt Request n */
-#define REG_PVP0_OPF0_CFG               0xFFC1A020         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF1_CFG               0xFFC1A040         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF2_CFG               0xFFC1A060         /* PVP0 OPFn (Camera Pipe) Configuration */
-#define REG_PVP0_OPF0_CTL               0xFFC1A024         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF1_CTL               0xFFC1A044         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF2_CTL               0xFFC1A064         /* PVP0 OPFn (Camera Pipe) Control */
-#define REG_PVP0_OPF3_CFG               0xFFC1A080         /* PVP0 OPF3 (Memory Pipe) Configuration */
-#define REG_PVP0_OPF3_CTL               0xFFC1A084         /* PVP0 OPF3 (Memory Pipe) Control */
-#define REG_PVP0_PEC_CFG                0xFFC1A0A0         /* PVP0 PEC Configuration */
-#define REG_PVP0_PEC_CTL                0xFFC1A0A4         /* PVP0 PEC Control */
-#define REG_PVP0_PEC_D1TH0              0xFFC1A0A8         /* PVP0 PEC Lower Hysteresis Threshold */
-#define REG_PVP0_PEC_D1TH1              0xFFC1A0AC         /* PVP0 PEC Upper Hysteresis Threshold */
-#define REG_PVP0_PEC_D2TH0              0xFFC1A0B0         /* PVP0 PEC Weak Zero Crossing Threshold */
-#define REG_PVP0_PEC_D2TH1              0xFFC1A0B4         /* PVP0 PEC Strong Zero Crossing Threshold */
-#define REG_PVP0_IIM0_CFG               0xFFC1A0C0         /* PVP0 IIMn Configuration */
-#define REG_PVP0_IIM1_CFG               0xFFC1A0E0         /* PVP0 IIMn Configuration */
-#define REG_PVP0_IIM0_CTL               0xFFC1A0C4         /* PVP0 IIMn Control */
-#define REG_PVP0_IIM1_CTL               0xFFC1A0E4         /* PVP0 IIMn Control */
-#define REG_PVP0_IIM0_SCALE             0xFFC1A0C8         /* PVP0 IIMn Scaling Values */
-#define REG_PVP0_IIM1_SCALE             0xFFC1A0E8         /* PVP0 IIMn Scaling Values */
-#define REG_PVP0_IIM0_SOVF_STAT         0xFFC1A0CC         /* PVP0 IIMn Signed Overflow Status */
-#define REG_PVP0_IIM1_SOVF_STAT         0xFFC1A0EC         /* PVP0 IIMn Signed Overflow Status */
-#define REG_PVP0_IIM0_UOVF_STAT         0xFFC1A0D0         /* PVP0 IIMn Unsigned Overflow Status */
-#define REG_PVP0_IIM1_UOVF_STAT         0xFFC1A0F0         /* PVP0 IIMn Unsigned Overflow Status */
-#define REG_PVP0_ACU_CFG                0xFFC1A100         /* PVP0 ACU Configuration */
-#define REG_PVP0_ACU_CTL                0xFFC1A104         /* PVP0 ACU Control */
-#define REG_PVP0_ACU_OFFSET             0xFFC1A108         /* PVP0 ACU SUM Constant */
-#define REG_PVP0_ACU_FACTOR             0xFFC1A10C         /* PVP0 ACU PROD Constant */
-#define REG_PVP0_ACU_SHIFT              0xFFC1A110         /* PVP0 ACU Shift Constant */
-#define REG_PVP0_ACU_MIN                0xFFC1A114         /* PVP0 ACU Lower Sat Threshold Min */
-#define REG_PVP0_ACU_MAX                0xFFC1A118         /* PVP0 ACU Upper Sat Threshold Max */
-#define REG_PVP0_UDS_CFG                0xFFC1A140         /* PVP0 UDS Configuration */
-#define REG_PVP0_UDS_CTL                0xFFC1A144         /* PVP0 UDS Control */
-#define REG_PVP0_UDS_OHCNT              0xFFC1A148         /* PVP0 UDS Output HCNT */
-#define REG_PVP0_UDS_OVCNT              0xFFC1A14C         /* PVP0 UDS Output VCNT */
-#define REG_PVP0_UDS_HAVG               0xFFC1A150         /* PVP0 UDS HAVG */
-#define REG_PVP0_UDS_VAVG               0xFFC1A154         /* PVP0 UDS VAVG */
-#define REG_PVP0_IPF0_CFG               0xFFC1A180         /* PVP0 IPF0 (Camera Pipe) Configuration */
-#define REG_PVP0_IPF0_PIPECTL           0xFFC1A184         /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define REG_PVP0_IPF1_PIPECTL           0xFFC1A1C4         /* PVP0 IPFn (Camera/Memory Pipe) Pipe Control */
-#define REG_PVP0_IPF0_CTL               0xFFC1A188         /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define REG_PVP0_IPF1_CTL               0xFFC1A1C8         /* PVP0 IPFn (Camera/Memory Pipe) Control */
-#define REG_PVP0_IPF0_TAG               0xFFC1A18C         /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define REG_PVP0_IPF1_TAG               0xFFC1A1CC         /* PVP0 IPFn (Camera/Memory Pipe) TAG Value */
-#define REG_PVP0_IPF0_FCNT              0xFFC1A190         /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define REG_PVP0_IPF1_FCNT              0xFFC1A1D0         /* PVP0 IPFn (Camera/Memory Pipe) Frame Count */
-#define REG_PVP0_IPF0_HCNT              0xFFC1A194         /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define REG_PVP0_IPF1_HCNT              0xFFC1A1D4         /* PVP0 IPFn (Camera/Memory Pipe) Horizontal Count */
-#define REG_PVP0_IPF0_VCNT              0xFFC1A198         /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define REG_PVP0_IPF1_VCNT              0xFFC1A1D8         /* PVP0 IPFn (Camera/Memory Pipe) Vertical Count */
-#define REG_PVP0_IPF0_HPOS              0xFFC1A19C         /* PVP0 IPF0 (Camera Pipe) Horizontal Position */
-#define REG_PVP0_IPF0_VPOS              0xFFC1A1A0         /* PVP0 IPF0 (Camera Pipe) Vertical Position */
-#define REG_PVP0_IPF0_TAG_STAT          0xFFC1A1A4         /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define REG_PVP0_IPF1_TAG_STAT          0xFFC1A1E4         /* PVP0 IPFn (Camera/Memory Pipe) TAG Status */
-#define REG_PVP0_IPF1_CFG               0xFFC1A1C0         /* PVP0 IPF1 (Memory Pipe) Configuration */
-#define REG_PVP0_CNV0_CFG               0xFFC1A200         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV1_CFG               0xFFC1A280         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV2_CFG               0xFFC1A300         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV3_CFG               0xFFC1A380         /* PVP0 CNVn Configuration */
-#define REG_PVP0_CNV0_CTL               0xFFC1A204         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV1_CTL               0xFFC1A284         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV2_CTL               0xFFC1A304         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV3_CTL               0xFFC1A384         /* PVP0 CNVn Control */
-#define REG_PVP0_CNV0_C00C01            0xFFC1A208         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV1_C00C01            0xFFC1A288         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV2_C00C01            0xFFC1A308         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV3_C00C01            0xFFC1A388         /* PVP0 CNVn Coefficients 0,0 and 0,1 */
-#define REG_PVP0_CNV0_C02C03            0xFFC1A20C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV1_C02C03            0xFFC1A28C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV2_C02C03            0xFFC1A30C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV3_C02C03            0xFFC1A38C         /* PVP0 CNVn Coefficients 0,2 and 0,3 */
-#define REG_PVP0_CNV0_C04               0xFFC1A210         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV1_C04               0xFFC1A290         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV2_C04               0xFFC1A310         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV3_C04               0xFFC1A390         /* PVP0 CNVn Coefficient 0,4 */
-#define REG_PVP0_CNV0_C10C11            0xFFC1A214         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV1_C10C11            0xFFC1A294         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV2_C10C11            0xFFC1A314         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV3_C10C11            0xFFC1A394         /* PVP0 CNVn Coefficients 1,0 and 1,1 */
-#define REG_PVP0_CNV0_C12C13            0xFFC1A218         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV1_C12C13            0xFFC1A298         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV2_C12C13            0xFFC1A318         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV3_C12C13            0xFFC1A398         /* PVP0 CNVn Coefficients 1,2 and 1,3 */
-#define REG_PVP0_CNV0_C14               0xFFC1A21C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV1_C14               0xFFC1A29C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV2_C14               0xFFC1A31C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV3_C14               0xFFC1A39C         /* PVP0 CNVn Coefficient 1,4 */
-#define REG_PVP0_CNV0_C20C21            0xFFC1A220         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV1_C20C21            0xFFC1A2A0         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV2_C20C21            0xFFC1A320         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV3_C20C21            0xFFC1A3A0         /* PVP0 CNVn Coefficients 2,0 and 2,1 */
-#define REG_PVP0_CNV0_C22C23            0xFFC1A224         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV1_C22C23            0xFFC1A2A4         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV2_C22C23            0xFFC1A324         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV3_C22C23            0xFFC1A3A4         /* PVP0 CNVn Coefficients 2,2 and 2,3 */
-#define REG_PVP0_CNV0_C24               0xFFC1A228         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV1_C24               0xFFC1A2A8         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV2_C24               0xFFC1A328         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV3_C24               0xFFC1A3A8         /* PVP0 CNVn Coefficient 2,4 */
-#define REG_PVP0_CNV0_C30C31            0xFFC1A22C         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV1_C30C31            0xFFC1A2AC         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV2_C30C31            0xFFC1A32C         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV3_C30C31            0xFFC1A3AC         /* PVP0 CNVn Coefficients 3,0 and 3,1 */
-#define REG_PVP0_CNV0_C32C33            0xFFC1A230         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV1_C32C33            0xFFC1A2B0         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV2_C32C33            0xFFC1A330         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV3_C32C33            0xFFC1A3B0         /* PVP0 CNVn Coefficients 3,2 and 3,3 */
-#define REG_PVP0_CNV0_C34               0xFFC1A234         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV1_C34               0xFFC1A2B4         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV2_C34               0xFFC1A334         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV3_C34               0xFFC1A3B4         /* PVP0 CNVn Coefficient 3,4 */
-#define REG_PVP0_CNV0_C40C41            0xFFC1A238         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV1_C40C41            0xFFC1A2B8         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV2_C40C41            0xFFC1A338         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV3_C40C41            0xFFC1A3B8         /* PVP0 CNVn Coefficients 4,0 and 4,1 */
-#define REG_PVP0_CNV0_C42C43            0xFFC1A23C         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV1_C42C43            0xFFC1A2BC         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV2_C42C43            0xFFC1A33C         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV3_C42C43            0xFFC1A3BC         /* PVP0 CNVn Coefficients 4,2 and 4,3 */
-#define REG_PVP0_CNV0_C44               0xFFC1A240         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV1_C44               0xFFC1A2C0         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV2_C44               0xFFC1A340         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV3_C44               0xFFC1A3C0         /* PVP0 CNVn Coefficient 4,4 */
-#define REG_PVP0_CNV0_SCALE             0xFFC1A244         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV1_SCALE             0xFFC1A2C4         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV2_SCALE             0xFFC1A344         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_CNV3_SCALE             0xFFC1A3C4         /* PVP0 CNVn Scaling Factor */
-#define REG_PVP0_THC0_CFG               0xFFC1A400         /* PVP0 THCn Configuration */
-#define REG_PVP0_THC1_CFG               0xFFC1A500         /* PVP0 THCn Configuration */
-#define REG_PVP0_THC0_CTL               0xFFC1A404         /* PVP0 THCn Control */
-#define REG_PVP0_THC1_CTL               0xFFC1A504         /* PVP0 THCn Control */
-#define REG_PVP0_THC0_HFCNT             0xFFC1A408         /* PVP0 THCn Histogram Frame Count */
-#define REG_PVP0_THC1_HFCNT             0xFFC1A508         /* PVP0 THCn Histogram Frame Count */
-#define REG_PVP0_THC0_RMAXREP           0xFFC1A40C         /* PVP0 THCn Max RLE Reports */
-#define REG_PVP0_THC1_RMAXREP           0xFFC1A50C         /* PVP0 THCn Max RLE Reports */
-#define REG_PVP0_THC0_CMINVAL           0xFFC1A410         /* PVP0 THCn Min Clip Value */
-#define REG_PVP0_THC1_CMINVAL           0xFFC1A510         /* PVP0 THCn Min Clip Value */
-#define REG_PVP0_THC0_CMINTH            0xFFC1A414         /* PVP0 THCn Clip Min Threshold */
-#define REG_PVP0_THC1_CMINTH            0xFFC1A514         /* PVP0 THCn Clip Min Threshold */
-#define REG_PVP0_THC0_CMAXTH            0xFFC1A418         /* PVP0 THCn Clip Max Threshold */
-#define REG_PVP0_THC1_CMAXTH            0xFFC1A518         /* PVP0 THCn Clip Max Threshold */
-#define REG_PVP0_THC0_CMAXVAL           0xFFC1A41C         /* PVP0 THCn Max Clip Value */
-#define REG_PVP0_THC1_CMAXVAL           0xFFC1A51C         /* PVP0 THCn Max Clip Value */
-#define REG_PVP0_THC0_TH0               0xFFC1A420         /* PVP0 THCn Threshold Value 0 */
-#define REG_PVP0_THC1_TH0               0xFFC1A520         /* PVP0 THCn Threshold Value 0 */
-#define REG_PVP0_THC0_TH1               0xFFC1A424         /* PVP0 THCn Threshold Value 1 */
-#define REG_PVP0_THC1_TH1               0xFFC1A524         /* PVP0 THCn Threshold Value 1 */
-#define REG_PVP0_THC0_TH2               0xFFC1A428         /* PVP0 THCn Threshold Value 2 */
-#define REG_PVP0_THC1_TH2               0xFFC1A528         /* PVP0 THCn Threshold Value 2 */
-#define REG_PVP0_THC0_TH3               0xFFC1A42C         /* PVP0 THCn Threshold Value 3 */
-#define REG_PVP0_THC1_TH3               0xFFC1A52C         /* PVP0 THCn Threshold Value 3 */
-#define REG_PVP0_THC0_TH4               0xFFC1A430         /* PVP0 THCn Threshold Value 4 */
-#define REG_PVP0_THC1_TH4               0xFFC1A530         /* PVP0 THCn Threshold Value 4 */
-#define REG_PVP0_THC0_TH5               0xFFC1A434         /* PVP0 THCn Threshold Value 5 */
-#define REG_PVP0_THC1_TH5               0xFFC1A534         /* PVP0 THCn Threshold Value 5 */
-#define REG_PVP0_THC0_TH6               0xFFC1A438         /* PVP0 THCn Threshold Value 6 */
-#define REG_PVP0_THC1_TH6               0xFFC1A538         /* PVP0 THCn Threshold Value 6 */
-#define REG_PVP0_THC0_TH7               0xFFC1A43C         /* PVP0 THCn Threshold Value 7 */
-#define REG_PVP0_THC1_TH7               0xFFC1A53C         /* PVP0 THCn Threshold Value 7 */
-#define REG_PVP0_THC0_TH8               0xFFC1A440         /* PVP0 THCn Threshold Value 8 */
-#define REG_PVP0_THC1_TH8               0xFFC1A540         /* PVP0 THCn Threshold Value 8 */
-#define REG_PVP0_THC0_TH9               0xFFC1A444         /* PVP0 THCn Threshold Value 9 */
-#define REG_PVP0_THC1_TH9               0xFFC1A544         /* PVP0 THCn Threshold Value 9 */
-#define REG_PVP0_THC0_TH10              0xFFC1A448         /* PVP0 THCn Threshold Value 10 */
-#define REG_PVP0_THC1_TH10              0xFFC1A548         /* PVP0 THCn Threshold Value 10 */
-#define REG_PVP0_THC0_TH11              0xFFC1A44C         /* PVP0 THCn Threshold Value 11 */
-#define REG_PVP0_THC1_TH11              0xFFC1A54C         /* PVP0 THCn Threshold Value 11 */
-#define REG_PVP0_THC0_TH12              0xFFC1A450         /* PVP0 THCn Threshold Value 12 */
-#define REG_PVP0_THC1_TH12              0xFFC1A550         /* PVP0 THCn Threshold Value 12 */
-#define REG_PVP0_THC0_TH13              0xFFC1A454         /* PVP0 THCn Threshold Value 13 */
-#define REG_PVP0_THC1_TH13              0xFFC1A554         /* PVP0 THCn Threshold Value 13 */
-#define REG_PVP0_THC0_TH14              0xFFC1A458         /* PVP0 THCn Threshold Value 14 */
-#define REG_PVP0_THC1_TH14              0xFFC1A558         /* PVP0 THCn Threshold Value 14 */
-#define REG_PVP0_THC0_TH15              0xFFC1A45C         /* PVP0 THCn Threshold Value 15 */
-#define REG_PVP0_THC1_TH15              0xFFC1A55C         /* PVP0 THCn Threshold Value 15 */
-#define REG_PVP0_THC0_HHPOS             0xFFC1A460         /* PVP0 THCn Histogram Horzontal Position */
-#define REG_PVP0_THC1_HHPOS             0xFFC1A560         /* PVP0 THCn Histogram Horzontal Position */
-#define REG_PVP0_THC0_HVPOS             0xFFC1A464         /* PVP0 THCn Histogram Vertical Position */
-#define REG_PVP0_THC1_HVPOS             0xFFC1A564         /* PVP0 THCn Histogram Vertical Position */
-#define REG_PVP0_THC0_HHCNT             0xFFC1A468         /* PVP0 THCn Histogram Horizontal Count */
-#define REG_PVP0_THC1_HHCNT             0xFFC1A568         /* PVP0 THCn Histogram Horizontal Count */
-#define REG_PVP0_THC0_HVCNT             0xFFC1A46C         /* PVP0 THCn Histogram Vertical Count */
-#define REG_PVP0_THC1_HVCNT             0xFFC1A56C         /* PVP0 THCn Histogram Vertical Count */
-#define REG_PVP0_THC0_RHPOS             0xFFC1A470         /* PVP0 THCn RLE Horizontal Position */
-#define REG_PVP0_THC1_RHPOS             0xFFC1A570         /* PVP0 THCn RLE Horizontal Position */
-#define REG_PVP0_THC0_RVPOS             0xFFC1A474         /* PVP0 THCn RLE Vertical Position */
-#define REG_PVP0_THC1_RVPOS             0xFFC1A574         /* PVP0 THCn RLE Vertical Position */
-#define REG_PVP0_THC0_RHCNT             0xFFC1A478         /* PVP0 THCn RLE Horizontal Count */
-#define REG_PVP0_THC1_RHCNT             0xFFC1A578         /* PVP0 THCn RLE Horizontal Count */
-#define REG_PVP0_THC0_RVCNT             0xFFC1A47C         /* PVP0 THCn RLE Vertical Count */
-#define REG_PVP0_THC1_RVCNT             0xFFC1A57C         /* PVP0 THCn RLE Vertical Count */
-#define REG_PVP0_THC0_HFCNT_STAT        0xFFC1A480         /* PVP0 THCn Histogram Frame Count Status */
-#define REG_PVP0_THC1_HFCNT_STAT        0xFFC1A580         /* PVP0 THCn Histogram Frame Count Status */
-#define REG_PVP0_THC0_HCNT0_STAT        0xFFC1A484         /* PVP0 THCn Histogram Counter Value 0 */
-#define REG_PVP0_THC1_HCNT0_STAT        0xFFC1A584         /* PVP0 THCn Histogram Counter Value 0 */
-#define REG_PVP0_THC0_HCNT1_STAT        0xFFC1A488         /* PVP0 THCn Histogram Counter Value 1 */
-#define REG_PVP0_THC1_HCNT1_STAT        0xFFC1A588         /* PVP0 THCn Histogram Counter Value 1 */
-#define REG_PVP0_THC0_HCNT2_STAT        0xFFC1A48C         /* PVP0 THCn Histogram Counter Value 2 */
-#define REG_PVP0_THC1_HCNT2_STAT        0xFFC1A58C         /* PVP0 THCn Histogram Counter Value 2 */
-#define REG_PVP0_THC0_HCNT3_STAT        0xFFC1A490         /* PVP0 THCn Histogram Counter Value 3 */
-#define REG_PVP0_THC1_HCNT3_STAT        0xFFC1A590         /* PVP0 THCn Histogram Counter Value 3 */
-#define REG_PVP0_THC0_HCNT4_STAT        0xFFC1A494         /* PVP0 THCn Histogram Counter Value 4 */
-#define REG_PVP0_THC1_HCNT4_STAT        0xFFC1A594         /* PVP0 THCn Histogram Counter Value 4 */
-#define REG_PVP0_THC0_HCNT5_STAT        0xFFC1A498         /* PVP0 THCn Histogram Counter Value 5 */
-#define REG_PVP0_THC1_HCNT5_STAT        0xFFC1A598         /* PVP0 THCn Histogram Counter Value 5 */
-#define REG_PVP0_THC0_HCNT6_STAT        0xFFC1A49C         /* PVP0 THCn Histogram Counter Value 6 */
-#define REG_PVP0_THC1_HCNT6_STAT        0xFFC1A59C         /* PVP0 THCn Histogram Counter Value 6 */
-#define REG_PVP0_THC0_HCNT7_STAT        0xFFC1A4A0         /* PVP0 THCn Histogram Counter Value 7 */
-#define REG_PVP0_THC1_HCNT7_STAT        0xFFC1A5A0         /* PVP0 THCn Histogram Counter Value 7 */
-#define REG_PVP0_THC0_HCNT8_STAT        0xFFC1A4A4         /* PVP0 THCn Histogram Counter Value 8 */
-#define REG_PVP0_THC1_HCNT8_STAT        0xFFC1A5A4         /* PVP0 THCn Histogram Counter Value 8 */
-#define REG_PVP0_THC0_HCNT9_STAT        0xFFC1A4A8         /* PVP0 THCn Histogram Counter Value 9 */
-#define REG_PVP0_THC1_HCNT9_STAT        0xFFC1A5A8         /* PVP0 THCn Histogram Counter Value 9 */
-#define REG_PVP0_THC0_HCNT10_STAT       0xFFC1A4AC         /* PVP0 THCn Histogram Counter Value 10 */
-#define REG_PVP0_THC1_HCNT10_STAT       0xFFC1A5AC         /* PVP0 THCn Histogram Counter Value 10 */
-#define REG_PVP0_THC0_HCNT11_STAT       0xFFC1A4B0         /* PVP0 THCn Histogram Counter Value 11 */
-#define REG_PVP0_THC1_HCNT11_STAT       0xFFC1A5B0         /* PVP0 THCn Histogram Counter Value 11 */
-#define REG_PVP0_THC0_HCNT12_STAT       0xFFC1A4B4         /* PVP0 THCn Histogram Counter Value 12 */
-#define REG_PVP0_THC1_HCNT12_STAT       0xFFC1A5B4         /* PVP0 THCn Histogram Counter Value 12 */
-#define REG_PVP0_THC0_HCNT13_STAT       0xFFC1A4B8         /* PVP0 THCn Histogram Counter Value 13 */
-#define REG_PVP0_THC1_HCNT13_STAT       0xFFC1A5B8         /* PVP0 THCn Histogram Counter Value 13 */
-#define REG_PVP0_THC0_HCNT14_STAT       0xFFC1A4BC         /* PVP0 THCn Histogram Counter Value 14 */
-#define REG_PVP0_THC1_HCNT14_STAT       0xFFC1A5BC         /* PVP0 THCn Histogram Counter Value 14 */
-#define REG_PVP0_THC0_HCNT15_STAT       0xFFC1A4C0         /* PVP0 THCn Histogram Counter Value 15 */
-#define REG_PVP0_THC1_HCNT15_STAT       0xFFC1A5C0         /* PVP0 THCn Histogram Counter Value 15 */
-#define REG_PVP0_THC0_RREP_STAT         0xFFC1A4C4         /* PVP0 THCn Number of RLE Reports */
-#define REG_PVP0_THC1_RREP_STAT         0xFFC1A5C4         /* PVP0 THCn Number of RLE Reports */
-#define REG_PVP0_PMA_CFG                0xFFC1A600         /* PVP0 PMA Configuration */
-
-/* =========================
-        PVP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_REVID_MAJOR                  4                               /* Major ID */
-#define BITP_PVP_REVID_REV                    0                               /* Revision ID for a given Major ID */
-#define BITM_PVP_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major ID */
-#define BITM_PVP_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Revision ID for a given Major ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CTL_CLKDIV                   4                               /* Clock Divisor */
-#define BITP_PVP_CTL_CPEN                     2                               /* Camera Pipe Enable */
-#define BITP_PVP_CTL_MPEN                     1                               /* Memory Pipe Enable */
-#define BITP_PVP_CTL_PVPEN                    0                               /* PVP Enable */
-
-#define BITM_PVP_CTL_CLKDIV                  (_ADI_MSK(0x00000010,uint32_t))  /* Clock Divisor */
-#define ENUM_PVP_CTL_CLKDIV1                 (_ADI_MSK(0x00000000,uint32_t))  /* CLKDIV: PVPCLK = SCLK0 */
-#define ENUM_PVP_CTL_CLKDIV2                 (_ADI_MSK(0x00000010,uint32_t))  /* CLKDIV: PVPCLK = SCLK0/2 */
-
-#define BITM_PVP_CTL_CPEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe Enable */
-#define ENUM_PVP_CTL_CPDIS                   (_ADI_MSK(0x00000000,uint32_t))  /* CPEN: Disable Camera Pipe */
-#define ENUM_PVP_CTL_CPEN                    (_ADI_MSK(0x00000004,uint32_t))  /* CPEN: Enable Camera Pipe */
-
-#define BITM_PVP_CTL_MPEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe Enable */
-#define ENUM_PVP_CTL_MPDIS                   (_ADI_MSK(0x00000000,uint32_t))  /* MPEN: Disable Memory Pipe */
-#define ENUM_PVP_CTL_MPEN                    (_ADI_MSK(0x00000002,uint32_t))  /* MPEN: Enable Memory Pipe */
-
-#define BITM_PVP_CTL_PVPEN                   (_ADI_MSK(0x00000001,uint32_t))  /* PVP Enable */
-#define ENUM_PVP_CTL_PVPDIS                  (_ADI_MSK(0x00000000,uint32_t))  /* PVPEN: Disable PVP */
-#define ENUM_PVP_CTL_PVPEN                   (_ADI_MSK(0x00000001,uint32_t))  /* PVPEN: Enable PVP */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IMSK_ACUSUMSAT              27                               /* ACU SUM Saturate Unmask */
-#define BITP_PVP_IMSK_ACUPRODSAT             26                               /* ACU PROD Saturate Unmask */
-#define BITP_PVP_IMSK_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Unmask */
-#define BITP_PVP_IMSK_ACUDIVERR              24                               /* ACU Divide By Zero Unmask */
-#define BITP_PVP_IMSK_IIM1SOVF               23                               /* IIM1 Signed Overflow Unmask */
-#define BITP_PVP_IMSK_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Unmask */
-#define BITP_PVP_IMSK_IIM0SOVF               21                               /* IIM0 Signed Overflow Unmask */
-#define BITP_PVP_IMSK_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Unmask */
-#define BITP_PVP_IMSK_THC1RDY                18                               /* THC1 Report Ready Unmask */
-#define BITP_PVP_IMSK_THC0RDY                16                               /* THC0 Report Ready Unmask */
-#define BITP_PVP_IMSK_MPRDY                  15                               /* Memory Pipe Ready Unmask */
-#define BITP_PVP_IMSK_CPRDY                  14                               /* Camera Pipe Ready Unmask */
-#define BITP_PVP_IMSK_MPDRN                  13                               /* Memory Pipe Drain Done Unmask */
-#define BITP_PVP_IMSK_CPDRN                  12                               /* Camera Pipe Drain Done Unmask */
-#define BITP_PVP_IMSK_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Unmask */
-#define BITP_PVP_IMSK_MPOPFDAT                9                               /* Memory Pipe First Pixel Unmask */
-#define BITP_PVP_IMSK_CPOPFDAT                8                               /* Camera Pipe First Pixel Unmask */
-#define BITP_PVP_IMSK_CPSTOVF                 7                               /* Status DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF2OVF                 6                               /* OPF2 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF1OVF                 5                               /* OPF1 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_OPF0OVF                 4                               /* OPF0 DDE Stall Error Unmask */
-#define BITP_PVP_IMSK_MPWRERR                 3                               /* Memory Pipe MMR Write Error Unmask */
-#define BITP_PVP_IMSK_CPWRERR                 2                               /* Camera Pipe MMR Write Error Unmask */
-#define BITP_PVP_IMSK_MPDC                    1                               /* Memory Pipe DC Unmask */
-#define BITP_PVP_IMSK_CPDC                    0                               /* Camera Pipe DC Unmask */
-
-/* The fields and enumerations for PVP_IMSK are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_IMSK_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Unmask */
-#define BITM_PVP_IMSK_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Unmask */
-#define BITM_PVP_IMSK_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Unmask */
-#define BITM_PVP_IMSK_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Unmask */
-#define BITM_PVP_IMSK_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Unmask */
-#define BITM_PVP_IMSK_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Unmask */
-#define BITM_PVP_IMSK_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Unmask */
-#define BITM_PVP_IMSK_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Unmask */
-#define BITM_PVP_IMSK_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Unmask */
-#define BITM_PVP_IMSK_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Unmask */
-#define BITM_PVP_IMSK_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Unmask */
-#define BITM_PVP_IMSK_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Unmask */
-#define BITM_PVP_IMSK_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Unmask */
-#define BITM_PVP_IMSK_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Unmask */
-#define BITM_PVP_IMSK_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Unmask */
-#define BITM_PVP_IMSK_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Unmask */
-#define BITM_PVP_IMSK_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Unmask */
-#define BITM_PVP_IMSK_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Unmask */
-#define BITM_PVP_IMSK_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Unmask */
-#define BITM_PVP_IMSK_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Unmask */
-#define BITM_PVP_IMSK_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Unmask */
-#define BITM_PVP_IMSK_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_STAT_ACUSUMSAT              27                               /* ACU SUM Saturate Status */
-#define BITP_PVP_STAT_ACUPRODSAT             26                               /* ACU PROD Saturate Status */
-#define BITP_PVP_STAT_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Status */
-#define BITP_PVP_STAT_ACUDIVERR              24                               /* ACU Divide By Zero Status */
-#define BITP_PVP_STAT_IIM1SOVF               23                               /* IIM1 Signed Overflow Status */
-#define BITP_PVP_STAT_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Status */
-#define BITP_PVP_STAT_IIM0SOVF               21                               /* IIM0 Signed Overflow Status */
-#define BITP_PVP_STAT_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Status */
-#define BITP_PVP_STAT_THC1RDY                18                               /* THC1 Report Ready Status */
-#define BITP_PVP_STAT_THC0RDY                16                               /* THC0 Report Ready Status */
-#define BITP_PVP_STAT_MPRDY                  15                               /* Memory Pipe Ready Status */
-#define BITP_PVP_STAT_CPRDY                  14                               /* Camera Pipe Ready Status */
-#define BITP_PVP_STAT_MPDRN                  13                               /* Memory Pipe Drain Done Status */
-#define BITP_PVP_STAT_CPDRN                  12                               /* Camera Pipe Drain Done Status */
-#define BITP_PVP_STAT_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Status */
-#define BITP_PVP_STAT_MPOPFDAT                9                               /* Memory Pipe First Pixel Status */
-#define BITP_PVP_STAT_CPOPFDAT                8                               /* Camera Pipe First Pixel Status */
-#define BITP_PVP_STAT_CPSTOVF                 7                               /* Camera Pipe DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF2OVF                 6                               /* OPF2 DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF1OVF                 5                               /* OPF1 DDE Stall Error Status */
-#define BITP_PVP_STAT_OPF0OVF                 4                               /* OPF0 DDE Stall Error Status */
-#define BITP_PVP_STAT_MPWRERR                 3                               /* Memory Pipe MMR Write Error Status */
-#define BITP_PVP_STAT_CPWRERR                 2                               /* Camera Pipe MMR Write Error Status */
-#define BITP_PVP_STAT_MPDC                    1                               /* Memory Pipe DC Status */
-#define BITP_PVP_STAT_CPDC                    0                               /* Camera Pipe DC Status */
-
-#define BITM_PVP_STAT_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Status */
-#define ENUM_PVP_ACUSUMSAT_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUSUMSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUSUMSAT_HI                (_ADI_MSK(0x08000000,uint32_t))  /* ACUSUMSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Status */
-#define ENUM_PVP_ACUPRODSAT_LO               (_ADI_MSK(0x00000000,uint32_t))  /* ACUPRODSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUPRODSAT_HI               (_ADI_MSK(0x04000000,uint32_t))  /* ACUPRODSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Status */
-#define ENUM_PVP_ACUOUTSAT_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUOUTSAT: No Pending Interrupt */
-#define ENUM_PVP_ACUOUTSAT_HI                (_ADI_MSK(0x02000000,uint32_t))  /* ACUOUTSAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Status */
-#define ENUM_PVP_ACUDIVERR_LO                (_ADI_MSK(0x00000000,uint32_t))  /* ACUDIVERR: No Pending Interrupt */
-#define ENUM_PVP_ACUDIVERR_HI                (_ADI_MSK(0x01000000,uint32_t))  /* ACUDIVERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Status */
-#define ENUM_PVP_IIM1SOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM1SOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM1SOVF_HI                 (_ADI_MSK(0x00800000,uint32_t))  /* IIM1SOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Status */
-#define ENUM_PVP_IIM1UOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM1UOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM1UOVF_HI                 (_ADI_MSK(0x00400000,uint32_t))  /* IIM1UOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Status */
-#define ENUM_PVP_IIM0SOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM0SOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM0SOVF_HI                 (_ADI_MSK(0x00200000,uint32_t))  /* IIM0SOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Status */
-#define ENUM_PVP_IIM0UOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* IIM0UOVF: No Pending Interrupt */
-#define ENUM_PVP_IIM0UOVF_HI                 (_ADI_MSK(0x00100000,uint32_t))  /* IIM0UOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Status */
-#define ENUM_PVP_THC1RDY_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* THC1RDY: No Pending Interrupt */
-#define ENUM_PVP_THC1RDY_HI                  (_ADI_MSK(0x00040000,uint32_t))  /* THC1RDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Status */
-#define ENUM_PVP_THC0RDY_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* THC0RDY: No Pending Interrupt */
-#define ENUM_PVP_THC0RDY_HI                  (_ADI_MSK(0x00010000,uint32_t))  /* THC0RDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Status */
-#define ENUM_PVP_MPRDY_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* MPRDY: No Pending Interrupt */
-#define ENUM_PVP_MPRDY_HI                    (_ADI_MSK(0x00008000,uint32_t))  /* MPRDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Status */
-#define ENUM_PVP_CPRDY_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* CPRDY: No Pending Interrupt */
-#define ENUM_PVP_CPRDY_HI                    (_ADI_MSK(0x00004000,uint32_t))  /* CPRDY: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Status */
-#define ENUM_PVP_MPDRN_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* MPDRN: No Pending Interrupt */
-#define ENUM_PVP_MPDRN_HI                    (_ADI_MSK(0x00002000,uint32_t))  /* MPDRN: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Status */
-#define ENUM_PVP_CPDRN_LO                    (_ADI_MSK(0x00000000,uint32_t))  /* CPDRN: No Pending Interrupt */
-#define ENUM_PVP_CPDRN_HI                    (_ADI_MSK(0x00001000,uint32_t))  /* CPDRN: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Status */
-#define ENUM_PVP_CPIPFOVF_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* CPIPFOVF: No Pending Interrupt */
-#define ENUM_PVP_CPIPFOVF_HI                 (_ADI_MSK(0x00000400,uint32_t))  /* CPIPFOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Status */
-#define ENUM_PVP_MPOPFDAT_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* MPOPFDAT: No Pending Interrupt */
-#define ENUM_PVP_MPOPFDAT_HI                 (_ADI_MSK(0x00000200,uint32_t))  /* MPOPFDAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Status */
-#define ENUM_PVP_CPOPFDAT_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* CPOPFDAT: No Pending Interrupt */
-#define ENUM_PVP_CPOPFDAT_HI                 (_ADI_MSK(0x00000100,uint32_t))  /* CPOPFDAT: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Camera Pipe DDE Stall Error Status */
-#define ENUM_PVP_CPSTOVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* CPSTOVF: No Pending Interrupt */
-#define ENUM_PVP_CPSTOVF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* CPSTOVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Status */
-#define ENUM_PVP_OPF2OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF2OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF2OVF_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* OPF2OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Status */
-#define ENUM_PVP_OPF1OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF1OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF1OVF_HI                  (_ADI_MSK(0x00000020,uint32_t))  /* OPF1OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Status */
-#define ENUM_PVP_OPF0OVF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* OPF0OVF: No Pending Interrupt */
-#define ENUM_PVP_OPF0OVF_HI                  (_ADI_MSK(0x00000010,uint32_t))  /* OPF0OVF: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Status */
-#define ENUM_PVP_MPWRERR_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MPWRERR: No Pending Interrupt */
-#define ENUM_PVP_MPWRERR_HI                  (_ADI_MSK(0x00000008,uint32_t))  /* MPWRERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Status */
-#define ENUM_PVP_CPWRERR_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* CPWRERR: No Pending Interrupt */
-#define ENUM_PVP_CPWRERR_HI                  (_ADI_MSK(0x00000004,uint32_t))  /* CPWRERR: Pending Interrupt */
-
-#define BITM_PVP_STAT_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Status */
-#define ENUM_PVP_MPDC_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* MPDC: No Pending Interrupt */
-#define ENUM_PVP_MPDC_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* MPDC: Pending Interrupt */
-
-#define BITM_PVP_STAT_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Status */
-#define ENUM_PVP_CPDC_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* CPDC: No Pending Interrupt */
-#define ENUM_PVP_CPDC_HI                     (_ADI_MSK(0x00000001,uint32_t))  /* CPDC: Pending Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ILAT_ACUSUMSAT              27                               /* ACU SUM Saturate Latch */
-#define BITP_PVP_ILAT_ACUPRODSAT             26                               /* ACU PROD Saturate Latch */
-#define BITP_PVP_ILAT_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Latch */
-#define BITP_PVP_ILAT_ACUDIVERR              24                               /* ACU Divide By Zero Latch */
-#define BITP_PVP_ILAT_IIM1SOVF               23                               /* IIM1 Signed Overflow Latch */
-#define BITP_PVP_ILAT_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Latch */
-#define BITP_PVP_ILAT_IIM0SOVF               21                               /* IIM0 Signed Overflow Latch */
-#define BITP_PVP_ILAT_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Latch */
-#define BITP_PVP_ILAT_THC1RDY                18                               /* THC1 Report Ready Latch */
-#define BITP_PVP_ILAT_THC0RDY                16                               /* THC0 Report Ready Latch */
-#define BITP_PVP_ILAT_MPRDY                  15                               /* Memory Pipe Ready Latch */
-#define BITP_PVP_ILAT_CPRDY                  14                               /* Camera Pipe Ready Latch */
-#define BITP_PVP_ILAT_MPDRN                  13                               /* Memory Pipe Drain Done Latch */
-#define BITP_PVP_ILAT_CPDRN                  12                               /* Camera Pipe Drain Done Latch */
-#define BITP_PVP_ILAT_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Latch */
-#define BITP_PVP_ILAT_MPOPFDAT                9                               /* Memory Pipe First Pixel Latch */
-#define BITP_PVP_ILAT_CPOPFDAT                8                               /* Camera Pipe First Pixel Latch */
-#define BITP_PVP_ILAT_CPSTOVF                 7                               /* Status DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF2OVF                 6                               /* OPF2 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF1OVF                 5                               /* OPF1 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_OPF0OVF                 4                               /* OPF0 DDE Stall Error Latch */
-#define BITP_PVP_ILAT_MPWRERR                 3                               /* Memory Pipe MMR Write Error Latch */
-#define BITP_PVP_ILAT_CPWRERR                 2                               /* Camera Pipe MMR Write Error Latch */
-#define BITP_PVP_ILAT_MPDC                    1                               /* Memory Pipe DC Mask */
-#define BITP_PVP_ILAT_CPDC                    0                               /* Camera Pipe DC Latch */
-
-/* The fields and enumerations for PVP_ILAT are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_ILAT_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Latch */
-#define BITM_PVP_ILAT_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Latch */
-#define BITM_PVP_ILAT_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Latch */
-#define BITM_PVP_ILAT_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Latch */
-#define BITM_PVP_ILAT_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Latch */
-#define BITM_PVP_ILAT_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Latch */
-#define BITM_PVP_ILAT_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Latch */
-#define BITM_PVP_ILAT_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Latch */
-#define BITM_PVP_ILAT_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Latch */
-#define BITM_PVP_ILAT_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Latch */
-#define BITM_PVP_ILAT_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Latch */
-#define BITM_PVP_ILAT_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Latch */
-#define BITM_PVP_ILAT_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Latch */
-#define BITM_PVP_ILAT_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Latch */
-#define BITM_PVP_ILAT_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Latch */
-#define BITM_PVP_ILAT_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Latch */
-#define BITM_PVP_ILAT_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Latch */
-#define BITM_PVP_ILAT_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Latch */
-#define BITM_PVP_ILAT_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Latch */
-#define BITM_PVP_ILAT_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Latch */
-#define BITM_PVP_ILAT_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Mask */
-#define BITM_PVP_ILAT_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Latch */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IREQ                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IREQ_ACUSUMSAT              27                               /* ACU SUM Saturate Request */
-#define BITP_PVP_IREQ_ACUPRODSAT             26                               /* ACU PROD Saturate Request */
-#define BITP_PVP_IREQ_ACUOUTSAT              25                               /* ACU MIN/MAX Saturate Request */
-#define BITP_PVP_IREQ_ACUDIVERR              24                               /* ACU Divide By Zero Request */
-#define BITP_PVP_IREQ_IIM1SOVF               23                               /* IIM1 Signed Overflow Request */
-#define BITP_PVP_IREQ_IIM1UOVF               22                               /* IIM1 Unsigned Overflow Request */
-#define BITP_PVP_IREQ_IIM0SOVF               21                               /* IIM0 Signed Overflow Request */
-#define BITP_PVP_IREQ_IIM0UOVF               20                               /* IIM0 Unsigned Overflow Request */
-#define BITP_PVP_IREQ_THC1RDY                18                               /* THC1 Report Ready Request */
-#define BITP_PVP_IREQ_THC0RDY                16                               /* THC0 Report Ready Request */
-#define BITP_PVP_IREQ_MPRDY                  15                               /* Memory Pipe Ready Request */
-#define BITP_PVP_IREQ_CPRDY                  14                               /* Camera Pipe Ready Request */
-#define BITP_PVP_IREQ_MPDRN                  13                               /* Memory Pipe Drain Done Request */
-#define BITP_PVP_IREQ_CPDRN                  12                               /* Camera Pipe Drain Done Request */
-#define BITP_PVP_IREQ_CPIPFOVF               10                               /* Camera Pipe Pixel Overrun Request */
-#define BITP_PVP_IREQ_MPOPFDAT                9                               /* Memory Pipe First Pixel Request */
-#define BITP_PVP_IREQ_CPOPFDAT                8                               /* Camera Pipe First Pixel Request */
-#define BITP_PVP_IREQ_CPSTOVF                 7                               /* Status DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF2OVF                 6                               /* OPF2 DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF1OVF                 5                               /* OPF1 DDE Stall Error Request */
-#define BITP_PVP_IREQ_OPF0OVF                 4                               /* OPF0 DDE Stall Error Request */
-#define BITP_PVP_IREQ_MPWRERR                 3                               /* Memory Pipe MMR Write Error Request */
-#define BITP_PVP_IREQ_CPWRERR                 2                               /* Camera Pipe MMR Write Error Request */
-#define BITP_PVP_IREQ_MPDC                    1                               /* Memory Pipe DC Request */
-#define BITP_PVP_IREQ_CPDC                    0                               /* Camera Pipe DC Request */
-
-/* The fields and enumerations for PVP_IREQ are also in PVP - see the common set of ENUM_PVP_* #defines located with register PVP_STAT */
-
-#define BITM_PVP_IREQ_ACUSUMSAT              (_ADI_MSK(0x08000000,uint32_t))  /* ACU SUM Saturate Request */
-#define BITM_PVP_IREQ_ACUPRODSAT             (_ADI_MSK(0x04000000,uint32_t))  /* ACU PROD Saturate Request */
-#define BITM_PVP_IREQ_ACUOUTSAT              (_ADI_MSK(0x02000000,uint32_t))  /* ACU MIN/MAX Saturate Request */
-#define BITM_PVP_IREQ_ACUDIVERR              (_ADI_MSK(0x01000000,uint32_t))  /* ACU Divide By Zero Request */
-#define BITM_PVP_IREQ_IIM1SOVF               (_ADI_MSK(0x00800000,uint32_t))  /* IIM1 Signed Overflow Request */
-#define BITM_PVP_IREQ_IIM1UOVF               (_ADI_MSK(0x00400000,uint32_t))  /* IIM1 Unsigned Overflow Request */
-#define BITM_PVP_IREQ_IIM0SOVF               (_ADI_MSK(0x00200000,uint32_t))  /* IIM0 Signed Overflow Request */
-#define BITM_PVP_IREQ_IIM0UOVF               (_ADI_MSK(0x00100000,uint32_t))  /* IIM0 Unsigned Overflow Request */
-#define BITM_PVP_IREQ_THC1RDY                (_ADI_MSK(0x00040000,uint32_t))  /* THC1 Report Ready Request */
-#define BITM_PVP_IREQ_THC0RDY                (_ADI_MSK(0x00010000,uint32_t))  /* THC0 Report Ready Request */
-#define BITM_PVP_IREQ_MPRDY                  (_ADI_MSK(0x00008000,uint32_t))  /* Memory Pipe Ready Request */
-#define BITM_PVP_IREQ_CPRDY                  (_ADI_MSK(0x00004000,uint32_t))  /* Camera Pipe Ready Request */
-#define BITM_PVP_IREQ_MPDRN                  (_ADI_MSK(0x00002000,uint32_t))  /* Memory Pipe Drain Done Request */
-#define BITM_PVP_IREQ_CPDRN                  (_ADI_MSK(0x00001000,uint32_t))  /* Camera Pipe Drain Done Request */
-#define BITM_PVP_IREQ_CPIPFOVF               (_ADI_MSK(0x00000400,uint32_t))  /* Camera Pipe Pixel Overrun Request */
-#define BITM_PVP_IREQ_MPOPFDAT               (_ADI_MSK(0x00000200,uint32_t))  /* Memory Pipe First Pixel Request */
-#define BITM_PVP_IREQ_CPOPFDAT               (_ADI_MSK(0x00000100,uint32_t))  /* Camera Pipe First Pixel Request */
-#define BITM_PVP_IREQ_CPSTOVF                (_ADI_MSK(0x00000080,uint32_t))  /* Status DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF2OVF                (_ADI_MSK(0x00000040,uint32_t))  /* OPF2 DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF1OVF                (_ADI_MSK(0x00000020,uint32_t))  /* OPF1 DDE Stall Error Request */
-#define BITM_PVP_IREQ_OPF0OVF                (_ADI_MSK(0x00000010,uint32_t))  /* OPF0 DDE Stall Error Request */
-#define BITM_PVP_IREQ_MPWRERR                (_ADI_MSK(0x00000008,uint32_t))  /* Memory Pipe MMR Write Error Request */
-#define BITM_PVP_IREQ_CPWRERR                (_ADI_MSK(0x00000004,uint32_t))  /* Camera Pipe MMR Write Error Request */
-#define BITM_PVP_IREQ_MPDC                   (_ADI_MSK(0x00000002,uint32_t))  /* Memory Pipe DC Request */
-#define BITM_PVP_IREQ_CPDC                   (_ADI_MSK(0x00000001,uint32_t))  /* Camera Pipe DC Request */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_OPF_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_OPF_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_OPF_CFG_START                0                               /* Start */
-#define BITM_PVP_OPF_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_OPF_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_OPF_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_OPF_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF_CTL_FINISH              12                               /* Finish Enable */
-#define BITP_PVP_OPF_CTL_OSIZE                8                               /* Output Data Size */
-#define BITP_PVP_OPF_CTL_QFRMT                5                               /* Q Format Correction */
-#define BITP_PVP_OPF_CTL_IUP16                4                               /* Input Upper 16-Bit Data */
-#define BITP_PVP_OPF_CTL_ISIZE                0                               /* Input Data Size */
-
-#define BITM_PVP_OPF_CTL_FINISH              (_ADI_MSK(0x00001000,uint32_t))  /* Finish Enable */
-#define ENUM_PVP_OPF_CTL_NOFINISH            (_ADI_MSK(0x00000000,uint32_t))  /* FINISH: Disable Finish Signal */
-#define ENUM_PVP_OPF_CTL_FINISH              (_ADI_MSK(0x00001000,uint32_t))  /* FINISH: Enable Finish Signal */
-
-#define BITM_PVP_OPF_CTL_OSIZE               (_ADI_MSK(0x00000300,uint32_t))  /* Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE32             (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 32-Bit Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE16             (_ADI_MSK(0x00000100,uint32_t))  /* OSIZE: 16-Bit Output Data Size */
-#define ENUM_PVP_OPF_CTL_OSIZE8              (_ADI_MSK(0x00000200,uint32_t))  /* OSIZE: 8-Bit Output Data Size */
-
-#define BITM_PVP_OPF_CTL_QFRMT               (_ADI_MSK(0x00000020,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_OPF_CTL_NOQFRMT             (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_OPF_CTL_QFRMT               (_ADI_MSK(0x00000020,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_OPF_CTL_IUP16               (_ADI_MSK(0x00000010,uint32_t))  /* Input Upper 16-Bit Data */
-#define ENUM_PVP_OPF_CTL_LOWER16             (_ADI_MSK(0x00000000,uint32_t))  /* IUP16: Lower 16 Bits */
-#define ENUM_PVP_OPF_CTL_UPPER16             (_ADI_MSK(0x00000010,uint32_t))  /* IUP16: Upper 16 Bits */
-
-#define BITM_PVP_OPF_CTL_ISIZE               (_ADI_MSK(0x00000003,uint32_t))  /* Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE32             (_ADI_MSK(0x00000000,uint32_t))  /* ISIZE: 32-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE16             (_ADI_MSK(0x00000001,uint32_t))  /* ISIZE: 16-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE8              (_ADI_MSK(0x00000002,uint32_t))  /* ISIZE: 8-Bit Input Data Size */
-#define ENUM_PVP_OPF_CTL_ISIZE4              (_ADI_MSK(0x00000003,uint32_t))  /* ISIZE: 4-Bit Input Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF3_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF3_CFG_IBLOCK0             8                               /* Input Block ID */
-#define BITP_PVP_OPF3_CFG_IPORT0              4                               /* Input Port ID */
-#define BITP_PVP_OPF3_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_OPF3_CFG_START               0                               /* Start */
-#define BITM_PVP_OPF3_CFG_IBLOCK0            (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_OPF3_CFG_IPORT0             (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_OPF3_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_OPF3_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_OPF3_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_OPF3_CTL_FINISH             12                               /* Finish Enable */
-#define BITP_PVP_OPF3_CTL_OSIZE               8                               /* Output Data Size */
-#define BITP_PVP_OPF3_CTL_QFRMT               5                               /* Q Format Correction */
-#define BITP_PVP_OPF3_CTL_IUP16               4                               /* Input Upper 16-Bit Data */
-#define BITP_PVP_OPF3_CTL_ISIZE               0                               /* Input Data Size */
-
-#define BITM_PVP_OPF3_CTL_FINISH             (_ADI_MSK(0x00001000,uint32_t))  /* Finish Enable */
-#define ENUM_PVP_OPF3_CTL_NOFINISH           (_ADI_MSK(0x00000000,uint32_t))  /* FINISH: Disable Finish Signal */
-#define ENUM_PVP_OPF3_CTL_FINISH             (_ADI_MSK(0x00001000,uint32_t))  /* FINISH: Enable Finish Signal */
-
-#define BITM_PVP_OPF3_CTL_OSIZE              (_ADI_MSK(0x00000300,uint32_t))  /* Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE32            (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 32-Bit Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE16            (_ADI_MSK(0x00000100,uint32_t))  /* OSIZE: 16-Bit Output Data Size */
-#define ENUM_PVP_OPF3_CTL_OSIZE8             (_ADI_MSK(0x00000200,uint32_t))  /* OSIZE: 8-Bit Output Data Size */
-
-#define BITM_PVP_OPF3_CTL_QFRMT              (_ADI_MSK(0x00000020,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_OPF3_CTL_NOQFRMT            (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_OPF3_CTL_QFRMT              (_ADI_MSK(0x00000020,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_OPF3_CTL_IUP16              (_ADI_MSK(0x00000010,uint32_t))  /* Input Upper 16-Bit Data */
-#define ENUM_PVP_OPF3_CTL_LOWER16            (_ADI_MSK(0x00000000,uint32_t))  /* IUP16: Lower 16 Bits */
-#define ENUM_PVP_OPF3_CTL_UPPER16            (_ADI_MSK(0x00000010,uint32_t))  /* IUP16: Upper 16 Bits */
-
-#define BITM_PVP_OPF3_CTL_ISIZE              (_ADI_MSK(0x00000003,uint32_t))  /* Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE32            (_ADI_MSK(0x00000000,uint32_t))  /* ISIZE: 32-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE16            (_ADI_MSK(0x00000001,uint32_t))  /* ISIZE: 16-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE8             (_ADI_MSK(0x00000002,uint32_t))  /* ISIZE: 8-Bit Input Data Size */
-#define ENUM_PVP_OPF3_CTL_ISIZE4             (_ADI_MSK(0x00000003,uint32_t))  /* ISIZE: 4-Bit Input Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_PEC_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_PEC_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_PEC_CFG_START                0                               /* Start */
-#define BITM_PVP_PEC_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_PEC_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_PEC_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_PEC_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_PEC_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_PEC_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_CTL_IGNTH1               3                               /* Ignore TH1 Threshold for Encoding */
-#define BITP_PVP_PEC_CTL_OSIZE                2                               /* Output Data Size per Bin */
-#define BITP_PVP_PEC_CTL_ZCRSS                1                               /* Zero Cross */
-#define BITP_PVP_PEC_CTL_MODE                 0                               /* Derivative Mode Select */
-
-#define BITM_PVP_PEC_CTL_IGNTH1              (_ADI_MSK(0x00000008,uint32_t))  /* Ignore TH1 Threshold for Encoding */
-#define ENUM_PVP_PEC_CTL_ENCODEDIFF          (_ADI_MSK(0x00000000,uint32_t))  /* IGNTH1: Different Strong/Weak Edge Encoding */
-#define ENUM_PVP_PEC_CTL_ENCODESAME          (_ADI_MSK(0x00000008,uint32_t))  /* IGNTH1: Identical Strong/Weak Edge Encoding */
-
-#define BITM_PVP_PEC_CTL_OSIZE               (_ADI_MSK(0x00000004,uint32_t))  /* Output Data Size per Bin */
-#define ENUM_PVP_PEC_CTL_BIN8                (_ADI_MSK(0x00000000,uint32_t))  /* OSIZE: 8 Bits Per Bin PEC Output Data Size */
-#define ENUM_PVP_PEC_CTL_BIN16               (_ADI_MSK(0x00000004,uint32_t))  /* OSIZE: 16 Bits Per Bin PEC Output Data Size */
-
-#define BITM_PVP_PEC_CTL_ZCRSS               (_ADI_MSK(0x00000002,uint32_t))  /* Zero Cross */
-#define ENUM_PVP_PEC_CTL_ANGLE               (_ADI_MSK(0x00000000,uint32_t))  /* ZCRSS: Angle Indices and Sub-Pixel Values */
-#define ENUM_PVP_PEC_CTL_ZEROCROSS           (_ADI_MSK(0x00000002,uint32_t))  /* ZCRSS: Zero Crossing Codes and Sub-Pixel Values */
-
-#define BITM_PVP_PEC_CTL_MODE                (_ADI_MSK(0x00000001,uint32_t))  /* Derivative Mode Select */
-#define ENUM_PVP_PEC_CTL_DERIV1              (_ADI_MSK(0x00000000,uint32_t))  /* MODE: 1st Derivative Mode */
-#define ENUM_PVP_PEC_CTL_DERIV2              (_ADI_MSK(0x00000001,uint32_t))  /* MODE: 2nd Derivative Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D1TH0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D1TH0_VALUE              0                               /* Lower Hysteresis Threshold */
-#define BITM_PVP_PEC_D1TH0_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Lower Hysteresis Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D1TH1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D1TH1_VALUE              0                               /* Upper Hysteresis Threshold */
-#define BITM_PVP_PEC_D1TH1_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Upper Hysteresis Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D2TH0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D2TH0_VALUE              0                               /* Weak Zero Crossing Threshold */
-#define BITM_PVP_PEC_D2TH0_VALUE             (_ADI_MSK(0x00007FFF,uint32_t))  /* Weak Zero Crossing Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PEC_D2TH1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PEC_D2TH1_VALUE              0                               /* Strong Zero Crossing Threshold */
-#define BITM_PVP_PEC_D2TH1_VALUE             (_ADI_MSK(0x00007FFF,uint32_t))  /* Strong Zero Crossing Threshold */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_IIM_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_IIM_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_IIM_CFG_START                0                               /* Start */
-#define BITM_PVP_IIM_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_IIM_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_IIM_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_IIM_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_IIM_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_IIM_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_CTL_SHIFT                8                               /* Shift Select */
-#define BITP_PVP_IIM_CTL_WIDTH                2                               /* Width Select */
-#define BITP_PVP_IIM_CTL_MODE                 0                               /* Mode Select */
-#define BITM_PVP_IIM_CTL_SHIFT               (_ADI_MSK(0x00001F00,uint32_t))  /* Shift Select */
-
-#define BITM_PVP_IIM_CTL_WIDTH               (_ADI_MSK(0x0000000C,uint32_t))  /* Width Select */
-#define ENUM_PVP_IIM_CTL_SINGLE32            (_ADI_MSK(0x00000000,uint32_t))  /* WIDTH: Single 32 Bit */
-#define ENUM_PVP_IIM_CTL_DUAL16              (_ADI_MSK(0x00000004,uint32_t))  /* WIDTH: Dual 16 Bit */
-#define ENUM_PVP_IIM_CTL_QUAD8               (_ADI_MSK(0x0000000C,uint32_t))  /* WIDTH: Quad 8 Bit */
-
-#define BITM_PVP_IIM_CTL_MODE                (_ADI_MSK(0x00000003,uint32_t))  /* Mode Select */
-#define ENUM_PVP_IIM_CTL_RECTMODE            (_ADI_MSK(0x00000000,uint32_t))  /* MODE: Rectangular Mode ( SAT) */
-#define ENUM_PVP_IIM_CTL_DIAGMODE            (_ADI_MSK(0x00000001,uint32_t))  /* MODE: Diagonal Mode ( RSAT -45) */
-#define ENUM_PVP_IIM_CTL_ROWMODE             (_ADI_MSK(0x00000002,uint32_t))  /* MODE: Row Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_SCALE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_SCALE_VSCL              16                               /* Vertical Scaling Factor */
-#define BITP_PVP_IIM_SCALE_HSCL               0                               /* Horizontal Scaling Factor */
-#define BITM_PVP_IIM_SCALE_VSCL              (_ADI_MSK(0x01FF0000,uint32_t))  /* Vertical Scaling Factor */
-#define BITM_PVP_IIM_SCALE_HSCL              (_ADI_MSK(0x000003FF,uint32_t))  /* Horizontal Scaling Factor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_SOVF_STAT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_SOVF_STAT_VPOS          16                               /* Veritcal Pixel Coordinate */
-#define BITP_PVP_IIM_SOVF_STAT_HPOS           0                               /* Horizontal Pixel Coordinate */
-#define BITM_PVP_IIM_SOVF_STAT_VPOS          (_ADI_MSK(0x03FF0000,uint32_t))  /* Veritcal Pixel Coordinate */
-#define BITM_PVP_IIM_SOVF_STAT_HPOS          (_ADI_MSK(0x000007FF,uint32_t))  /* Horizontal Pixel Coordinate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IIM_UOVF_STAT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IIM_UOVF_STAT_VPOS          16                               /* Veritcal Pixel Coordinate */
-#define BITP_PVP_IIM_UOVF_STAT_HPOS           0                               /* Horizontal Pixel Coordinate */
-#define BITM_PVP_IIM_UOVF_STAT_VPOS          (_ADI_MSK(0x03FF0000,uint32_t))  /* Veritcal Pixel Coordinate */
-#define BITM_PVP_IIM_UOVF_STAT_HPOS          (_ADI_MSK(0x000007FF,uint32_t))  /* Horizontal Pixel Coordinate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_CFG_IBLOCK1             16                               /* Input Block 1 ID */
-#define BITP_PVP_ACU_CFG_IBLOCK0              8                               /* Input Block 0 ID */
-#define BITP_PVP_ACU_CFG_IPORT1               6                               /* Input Port 1 ID */
-#define BITP_PVP_ACU_CFG_IPORT0               4                               /* Input Port 0 ID */
-#define BITP_PVP_ACU_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_ACU_CFG_START                0                               /* Start */
-#define BITM_PVP_ACU_CFG_IBLOCK1             (_ADI_MSK(0x00FF0000,uint32_t))  /* Input Block 1 ID */
-#define BITM_PVP_ACU_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block 0 ID */
-#define BITM_PVP_ACU_CFG_IPORT1              (_ADI_MSK(0x000000C0,uint32_t))  /* Input Port 1 ID */
-#define BITM_PVP_ACU_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port 0 ID */
-
-#define BITM_PVP_ACU_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_ACU_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_ACU_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_ACU_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_CTL_SUMOP               28                               /* Sum Operation */
-#define BITP_PVP_ACU_CTL_SUMISW              27                               /* Sum Input Swap */
-#define BITP_PVP_ACU_CTL_SUMINP              24                               /* Sum Inputs for Adder */
-#define BITP_PVP_ACU_CTL_PRDOP               20                               /* Prod Operation */
-#define BITP_PVP_ACU_CTL_PRDISW              19                               /* Prod Input Swap */
-#define BITP_PVP_ACU_CTL_PRDINP              16                               /* Prod Inputs for Mult/Div */
-#define BITP_PVP_ACU_CTL_ACCFRAME            15                               /* Accumulator Frame */
-#define BITP_PVP_ACU_CTL_ACCINP               8                               /* Accumulator Input */
-#define BITP_PVP_ACU_CTL_SFTINP               0                               /* Shift Input */
-
-#define BITM_PVP_ACU_CTL_SUMOP               (_ADI_MSK(0x10000000,uint32_t))  /* Sum Operation */
-#define ENUM_PVP_ACU_CTL_ADD                 (_ADI_MSK(0x00000000,uint32_t))  /* SUMOP: Add */
-#define ENUM_PVP_ACU_CTL_SUBTRACT            (_ADI_MSK(0x10000000,uint32_t))  /* SUMOP: Subtract */
-
-#define BITM_PVP_ACU_CTL_SUMISW              (_ADI_MSK(0x08000000,uint32_t))  /* Sum Input Swap */
-#define ENUM_PVP_ACU_CTL_NOSWAPSUM           (_ADI_MSK(0x00000000,uint32_t))  /* SUMISW: Do Not Swap Operands */
-#define ENUM_PVP_ACU_CTL_SWAPSUM             (_ADI_MSK(0x08000000,uint32_t))  /* SUMISW: Swap Operands */
-
-#define BITM_PVP_ACU_CTL_SUMINP              (_ADI_MSK(0x03000000,uint32_t))  /* Sum Inputs for Adder */
-#define ENUM_PVP_ACU_CTL_SUMXY               (_ADI_MSK(0x00000000,uint32_t))  /* SUMINP: X,Y Inputs */
-#define ENUM_PVP_ACU_CTL_SUMXOFF             (_ADI_MSK(0x01000000,uint32_t))  /* SUMINP: X,OFFSET Inputs */
-#define ENUM_PVP_ACU_CTL_SUMYOFF             (_ADI_MSK(0x02000000,uint32_t))  /* SUMINP: Y,OFFSET Inputs */
-
-#define BITM_PVP_ACU_CTL_PRDOP               (_ADI_MSK(0x00300000,uint32_t))  /* Prod Operation */
-#define ENUM_PVP_ACU_CTL_MULTIPLY            (_ADI_MSK(0x00000000,uint32_t))  /* PRDOP: Multiply */
-#define ENUM_PVP_ACU_CTL_DIVQUOTIENT         (_ADI_MSK(0x00100000,uint32_t))  /* PRDOP: Divide with Quotient */
-#define ENUM_PVP_ACU_CTL_DIVMODULUS          (_ADI_MSK(0x00200000,uint32_t))  /* PRDOP: Divide with Modulus */
-
-#define BITM_PVP_ACU_CTL_PRDISW              (_ADI_MSK(0x00080000,uint32_t))  /* Prod Input Swap */
-#define ENUM_PVP_ACU_CTL_NOSWAPPROD          (_ADI_MSK(0x00000000,uint32_t))  /* PRDISW: Do Not Swap Operands */
-#define ENUM_PVP_ACU_CTL_SWAPPROD            (_ADI_MSK(0x00080000,uint32_t))  /* PRDISW: Swap Operands */
-
-#define BITM_PVP_ACU_CTL_PRDINP              (_ADI_MSK(0x00030000,uint32_t))  /* Prod Inputs for Mult/Div */
-#define ENUM_PVP_ACU_CTL_PRODXY              (_ADI_MSK(0x00000000,uint32_t))  /* PRDINP: X,Y Inputs */
-#define ENUM_PVP_ACU_CTL_PRODXFACT           (_ADI_MSK(0x00010000,uint32_t))  /* PRDINP: X,FACTOR Inputs */
-#define ENUM_PVP_ACU_CTL_PRODYFACT           (_ADI_MSK(0x00020000,uint32_t))  /* PRDINP: Y,FACTOR Inputs */
-#define ENUM_PVP_ACU_CTL_PRODSUMFACT         (_ADI_MSK(0x00030000,uint32_t))  /* PRDINP: SUM,FACTOR Inputs */
-
-#define BITM_PVP_ACU_CTL_ACCFRAME            (_ADI_MSK(0x00008000,uint32_t))  /* Accumulator Frame */
-#define ENUM_PVP_ACU_CTL_ACCUMROW            (_ADI_MSK(0x00000000,uint32_t))  /* ACCFRAME: Clear ACC After Row */
-#define ENUM_PVP_ACU_CTL_ACCUMFRAME          (_ADI_MSK(0x00008000,uint32_t))  /* ACCFRAME: Clear ACC After Frame */
-
-#define BITM_PVP_ACU_CTL_ACCINP              (_ADI_MSK(0x00000300,uint32_t))  /* Accumulator Input */
-#define ENUM_PVP_ACU_CTL_ACCUMX              (_ADI_MSK(0x00000000,uint32_t))  /* ACCINP: X Input */
-#define ENUM_PVP_ACU_CTL_ACCUMSUM            (_ADI_MSK(0x00000100,uint32_t))  /* ACCINP: SUM Input */
-#define ENUM_PVP_ACU_CTL_ACCUMPROD           (_ADI_MSK(0x00000200,uint32_t))  /* ACCINP: PROD Input */
-
-#define BITM_PVP_ACU_CTL_SFTINP              (_ADI_MSK(0x00000003,uint32_t))  /* Shift Input */
-#define ENUM_PVP_ACU_CTL_SHIFTXIN            (_ADI_MSK(0x00000000,uint32_t))  /* SFTINP: X Input */
-#define ENUM_PVP_ACU_CTL_SHIFTSUM            (_ADI_MSK(0x00000001,uint32_t))  /* SFTINP: SUM Result Input */
-#define ENUM_PVP_ACU_CTL_SHIFTPROD           (_ADI_MSK(0x00000002,uint32_t))  /* SFTINP: PROD Result Input */
-#define ENUM_PVP_ACU_CTL_SHIFTACC            (_ADI_MSK(0x00000003,uint32_t))  /* SFTINP: ACC Result Input */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_ACU_SHIFT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_ACU_SHIFT_VALUE              0                               /* SHIFT Constant */
-#define BITM_PVP_ACU_SHIFT_VALUE             (_ADI_MSK(0x0000003F,uint32_t))  /* SHIFT Constant */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_UDS_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_UDS_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_UDS_CFG_START                0                               /* Start */
-#define BITM_PVP_UDS_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_UDS_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-#define BITM_PVP_UDS_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_UDS_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_CTL_AAVG                 0                               /* Automatic Averaging */
-
-#define BITM_PVP_UDS_CTL_AAVG                (_ADI_MSK(0x00000001,uint32_t))  /* Automatic Averaging */
-#define ENUM_PVP_UDS_CTL_MANTAPS             (_ADI_MSK(0x00000000,uint32_t))  /* AAVG: Manual Filter Tap Selection */
-#define ENUM_PVP_UDS_CTL_AUTOTAPS            (_ADI_MSK(0x00000001,uint32_t))  /* AAVG: Auto Filter Tap Selection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_OHCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_OHCNT_VALUE              4                               /* H Dimension of Output Frame */
-#define BITM_PVP_UDS_OHCNT_VALUE             (_ADI_MSK(0x000000F0,uint32_t))  /* H Dimension of Output Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_OVCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_OVCNT_VALUE              4                               /* V Dimension of Output Frame */
-#define BITM_PVP_UDS_OVCNT_VALUE             (_ADI_MSK(0x000000F0,uint32_t))  /* V Dimension of Output Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_HAVG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_HAVG_VALUE               0                               /* H Filter Taps */
-#define BITM_PVP_UDS_HAVG_VALUE              (_ADI_MSK(0x000000FF,uint32_t))  /* H Filter Taps */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_UDS_VAVG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_UDS_VAVG_VALUE               0                               /* V Filter Taps */
-#define BITM_PVP_UDS_VAVG_VALUE              (_ADI_MSK(0x0000007F,uint32_t))  /* V Filter Taps */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_CFG_STATWCNT           24                               /* Camera Pipe DMA Status */
-#define BITP_PVP_IPF0_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_IPF0_CFG_START               0                               /* Start */
-#define BITM_PVP_IPF0_CFG_STATWCNT           (_ADI_MSK(0xFF000000,uint32_t))  /* Camera Pipe DMA Status */
-#define BITM_PVP_IPF0_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_IPF0_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_PIPECTL                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_PIPECTL_STATEN           4                               /* DMA Status Enable */
-#define BITP_PVP_IPF_PIPECTL_DRAIN            0                               /* Drain Enable */
-#define BITM_PVP_IPF_PIPECTL_STATEN          (_ADI_MSK(0x00000010,uint32_t))  /* DMA Status Enable */
-#define BITM_PVP_IPF_PIPECTL_DRAIN           (_ADI_MSK(0x00000001,uint32_t))  /* Drain Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_CTL_QFRMT               27                               /* Q Format Correction */
-#define BITP_PVP_IPF_CTL_SIGNEXT             26                               /* Sign Extend */
-#define BITP_PVP_IPF_CTL_EXTRED              25                               /* Extract Red/Green */
-#define BITP_PVP_IPF_CTL_UNPACK              24                               /* Unpack Incoming */
-#define BITP_PVP_IPF_CTL_CFRMT               16                               /* Color Space Format */
-#define BITP_PVP_IPF_CTL_OPORT2EN            12                               /* Output Port 2 Enable */
-#define BITP_PVP_IPF_CTL_OPORT1EN             8                               /* Output Port 1 Enable */
-#define BITP_PVP_IPF_CTL_OPORT0EN             4                               /* Output Port 0 Enable */
-
-#define BITM_PVP_IPF_CTL_QFRMT               (_ADI_MSK(0x08000000,uint32_t))  /* Q Format Correction */
-#define ENUM_PVP_IPF_CTL_NOQFRMT             (_ADI_MSK(0x00000000,uint32_t))  /* QFRMT: Disable Q Format Correction */
-#define ENUM_PVP_IPF_CTL_QFRMT               (_ADI_MSK(0x08000000,uint32_t))  /* QFRMT: Enable Q Format Correction */
-
-#define BITM_PVP_IPF_CTL_SIGNEXT             (_ADI_MSK(0x04000000,uint32_t))  /* Sign Extend */
-#define ENUM_PVP_IPF_CTL_ZEROEXT             (_ADI_MSK(0x00000000,uint32_t))  /* SIGNEXT: Zero Extend */
-#define ENUM_PVP_IPF_CTL_SIGNEXT             (_ADI_MSK(0x04000000,uint32_t))  /* SIGNEXT: Sign Extend */
-
-#define BITM_PVP_IPF_CTL_EXTRED              (_ADI_MSK(0x02000000,uint32_t))  /* Extract Red/Green */
-#define ENUM_PVP_IPF_CTL_EXTGREEN            (_ADI_MSK(0x00000000,uint32_t))  /* EXTRED: Extract Green */
-#define ENUM_PVP_IPF_CTL_EXTRED              (_ADI_MSK(0x02000000,uint32_t))  /* EXTRED: Extract Red */
-
-#define BITM_PVP_IPF_CTL_UNPACK              (_ADI_MSK(0x01000000,uint32_t))  /* Unpack Incoming */
-#define ENUM_PVP_IPF_CTL_UNPACKDIS           (_ADI_MSK(0x00000000,uint32_t))  /* UNPACK: No Unpacking */
-#define ENUM_PVP_IPF_CTL_UNPACKEN            (_ADI_MSK(0x01000000,uint32_t))  /* UNPACK: Unpack Data */
-
-#define BITM_PVP_IPF_CTL_CFRMT               (_ADI_MSK(0x001F0000,uint32_t))  /* Color Space Format */
-#define ENUM_PVP_IPF_CTL_RGB8                (_ADI_MSK(0x00000000,uint32_t))  /* CFRMT: RGB 8-Bit */
-#define ENUM_PVP_IPF_CTL_RGB888              (_ADI_MSK(0x00010000,uint32_t))  /* CFRMT: RGB 888 */
-#define ENUM_PVP_IPF_CTL_YUV8                (_ADI_MSK(0x00100000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 1 */
-#define ENUM_PVP_IPF_CTL_YUV8SPLT            (_ADI_MSK(0x00110000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 2 */
-#define ENUM_PVP_IPF_CTL_YUV8SUBSPLT         (_ADI_MSK(0x00120000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Type 3 */
-#define ENUM_PVP_IPF_CTL_YUV8IN16            (_ADI_MSK(0x00130000,uint32_t))  /* CFRMT: YUV 4:2:2 8-Bit Pair 16-Bit */
-#define ENUM_PVP_IPF_CTL_RGB565              (_ADI_MSK(0x00020000,uint32_t))  /* CFRMT: RGB 565 */
-#define ENUM_PVP_IPF_CTL_YUV16               (_ADI_MSK(0x00140000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 1 */
-#define ENUM_PVP_IPF_CTL_YUV16SPLT           (_ADI_MSK(0x00150000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 2 */
-#define ENUM_PVP_IPF_CTL_YUV16SUBSPLT        (_ADI_MSK(0x00160000,uint32_t))  /* CFRMT: YUV 4:2:2 16-Bit Type 3 */
-#define ENUM_PVP_IPF_CTL_Y8                  (_ADI_MSK(0x00180000,uint32_t))  /* CFRMT: Y Alone 8-Bit */
-#define ENUM_PVP_IPF_CTL_Y16                 (_ADI_MSK(0x00190000,uint32_t))  /* CFRMT: Y Alone 16-Bit */
-#define ENUM_PVP_IPF_CTL_Y24                 (_ADI_MSK(0x001A0000,uint32_t))  /* CFRMT: Y Alone 24-Bit */
-#define ENUM_PVP_IPF_CTL_WORD32              (_ADI_MSK(0x001B0000,uint32_t))  /* CFRMT: 32 Bit */
-#define ENUM_PVP_IPF_CTL_RGB666              (_ADI_MSK(0x00030000,uint32_t))  /* CFRMT: RGB 666 */
-#define ENUM_PVP_IPF_CTL_RGB16               (_ADI_MSK(0x00040000,uint32_t))  /* CFRMT: RGB 16-Bit */
-#define ENUM_PVP_IPF_CTL_BAYER1              (_ADI_MSK(0x00050000,uint32_t))  /* CFRMT: RGB Bayer Format Type-1 */
-#define ENUM_PVP_IPF_CTL_BAYER2              (_ADI_MSK(0x00060000,uint32_t))  /* CFRMT: RGB Bayer Format Type-2 */
-
-#define BITM_PVP_IPF_CTL_OPORT2EN            (_ADI_MSK(0x00001000,uint32_t))  /* Output Port 2 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT2DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT2EN: Disable OPORT2 */
-#define ENUM_PVP_IPF_CTL_OPORT2EVEN          (_ADI_MSK(0x00001000,uint32_t))  /* OPORT2EN: Enable OPORT2 (full resolution) */
-
-#define BITM_PVP_IPF_CTL_OPORT1EN            (_ADI_MSK(0x00000300,uint32_t))  /* Output Port 1 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT1DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT1EN: Disable OPORT1 */
-#define ENUM_PVP_IPF_CTL_OPORT1ODD           (_ADI_MSK(0x00000100,uint32_t))  /* OPORT1EN: Enable OPORT1 (full resolution) */
-#define ENUM_PVP_IPF_CTL_OPORT1WIN           (_ADI_MSK(0x00000200,uint32_t))  /* OPORT1EN: Enable OPORT1 (windowed resolution) */
-
-#define BITM_PVP_IPF_CTL_OPORT0EN            (_ADI_MSK(0x00000010,uint32_t))  /* Output Port 0 Enable */
-#define ENUM_PVP_IPF_CTL_OPORT0DIS           (_ADI_MSK(0x00000000,uint32_t))  /* OPORT0EN: Disable OPORT0 */
-#define ENUM_PVP_IPF_CTL_OPORT0EN            (_ADI_MSK(0x00000010,uint32_t))  /* OPORT0EN: Enable OPORT0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_TAG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_TAG_VALUE                0                               /* TAG Value */
-#define BITM_PVP_IPF_TAG_VALUE               (_ADI_MSK(0x0000FFFF,uint32_t))  /* TAG Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_HCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_HCNT_VALUE               0                               /* Effective Width of ROI */
-#define BITM_PVP_IPF_HCNT_VALUE              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Effective Width of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_VCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_VCNT_VALUE               0                               /* Effective Height of ROI */
-#define BITM_PVP_IPF_VCNT_VALUE              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Effective Height of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_HPOS                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_HPOS_VALUE              0                               /* Horizontal Delay of ROI */
-#define BITM_PVP_IPF0_HPOS_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Horizontal Delay of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF0_VPOS                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF0_VPOS_VALUE              0                               /* Vertical Delay of ROI */
-#define BITM_PVP_IPF0_VPOS_VALUE             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Vertical Delay of ROI */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF_TAG_STAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF_TAG_STAT_VALUE           0                               /* TAG Value */
-#define BITM_PVP_IPF_TAG_STAT_VALUE          (_ADI_MSK(0x0000FFFF,uint32_t))  /* TAG Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_IPF1_CFG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_IPF1_CFG_STATWCNT           24                               /* Status Word Count */
-#define BITP_PVP_IPF1_CFG_MPIPE               2                               /* Memory Pipe */
-#define BITP_PVP_IPF1_CFG_START               0                               /* Start */
-#define BITM_PVP_IPF1_CFG_STATWCNT           (_ADI_MSK(0xFF000000,uint32_t))  /* Status Word Count */
-#define BITM_PVP_IPF1_CFG_MPIPE              (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define BITM_PVP_IPF1_CFG_START              (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_CNV_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_CNV_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_CNV_CFG_START                0                               /* Start */
-#define BITM_PVP_CNV_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_CNV_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_CNV_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_CNV_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_CNV_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_CNV_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_CTL_SHIFT                4                               /* Shift Right */
-#define BITP_PVP_CNV_CTL_ZEROFILL             1                               /* Zero Fill */
-#define BITP_PVP_CNV_CTL_SAT32                0                               /* Saturate Output to 32 Bits */
-#define BITM_PVP_CNV_CTL_SHIFT               (_ADI_MSK(0x000001F0,uint32_t))  /* Shift Right */
-
-#define BITM_PVP_CNV_CTL_ZEROFILL            (_ADI_MSK(0x00000002,uint32_t))  /* Zero Fill */
-#define ENUM_PVP_CNV_CTL_EDGEDUP             (_ADI_MSK(0x00000000,uint32_t))  /* ZEROFILL: Duplicated Data Fill */
-#define ENUM_PVP_CNV_CTL_EDGEZFILL           (_ADI_MSK(0x00000002,uint32_t))  /* ZEROFILL: Zero Fill */
-
-#define BITM_PVP_CNV_CTL_SAT32               (_ADI_MSK(0x00000001,uint32_t))  /* Saturate Output to 32 Bits */
-#define ENUM_PVP_CNV_CTL_SIGNEXT             (_ADI_MSK(0x00000000,uint32_t))  /* SAT32: 16-Bit Saturate of Output */
-#define ENUM_PVP_CNV_CTL_SAT32               (_ADI_MSK(0x00000001,uint32_t))  /* SAT32: 32-Bit Saturate of Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C00C01                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C00C01_C01              16                               /* Coefficient 0, 1 */
-#define BITP_PVP_CNV_C00C01_C00               0                               /* Coefficient 0, 0 */
-#define BITM_PVP_CNV_C00C01_C01              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 0, 1 */
-#define BITM_PVP_CNV_C00C01_C00              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C02C03                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C02C03_C03              16                               /* Coefficient 0, 3 */
-#define BITP_PVP_CNV_C02C03_C02               0                               /* Coefficient 0, 2 */
-#define BITM_PVP_CNV_C02C03_C03              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 0, 3 */
-#define BITM_PVP_CNV_C02C03_C02              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C04                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C04_C04                  0                               /* Coefficient 0, 4 */
-#define BITM_PVP_CNV_C04_C04                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 0, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C10C11                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C10C11_C11              16                               /* Coefficient 1, 1 */
-#define BITP_PVP_CNV_C10C11_C10               0                               /* Coefficient 1, 0 */
-#define BITM_PVP_CNV_C10C11_C11              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 1, 1 */
-#define BITM_PVP_CNV_C10C11_C10              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C12C13                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C12C13_C13              16                               /* Coefficient 1, 3 */
-#define BITP_PVP_CNV_C12C13_C12               0                               /* Coefficient 1, 2 */
-#define BITM_PVP_CNV_C12C13_C13              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 1, 3 */
-#define BITM_PVP_CNV_C12C13_C12              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C14                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C14_C14                  0                               /* Coefficient 1, 4 */
-#define BITM_PVP_CNV_C14_C14                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 1, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C20C21                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C20C21_C21              16                               /* Coefficient 2, 1 */
-#define BITP_PVP_CNV_C20C21_C20               0                               /* Coefficient 2, 0 */
-#define BITM_PVP_CNV_C20C21_C21              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 2, 1 */
-#define BITM_PVP_CNV_C20C21_C20              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C22C23                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C22C23_C23              16                               /* Coefficient 2, 3 */
-#define BITP_PVP_CNV_C22C23_C22               0                               /* Coefficient 2, 2 */
-#define BITM_PVP_CNV_C22C23_C23              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 2, 3 */
-#define BITM_PVP_CNV_C22C23_C22              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C24                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C24_C24                  0                               /* Coefficient 2, 4 */
-#define BITM_PVP_CNV_C24_C24                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 2, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C30C31                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C30C31_C31              16                               /* Coefficient 3, 1 */
-#define BITP_PVP_CNV_C30C31_C30               0                               /* Coefficient 3, 0 */
-#define BITM_PVP_CNV_C30C31_C31              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 3, 1 */
-#define BITM_PVP_CNV_C30C31_C30              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C32C33                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C32C33_C33              16                               /* Coefficient 3, 3 */
-#define BITP_PVP_CNV_C32C33_C32               0                               /* Coefficient 3, 2 */
-#define BITM_PVP_CNV_C32C33_C33              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 3, 3 */
-#define BITM_PVP_CNV_C32C33_C32              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C34                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C34_C34                  0                               /* Coefficient 3, 4 */
-#define BITM_PVP_CNV_C34_C34                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 3, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C40C41                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C40C41_C41              16                               /* Coefficient 4, 1 */
-#define BITP_PVP_CNV_C40C41_C40               0                               /* Coefficient 4, 0 */
-#define BITM_PVP_CNV_C40C41_C41              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 4, 1 */
-#define BITM_PVP_CNV_C40C41_C40              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C42C43                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C42C43_C43              16                               /* Coefficient 4, 3 */
-#define BITP_PVP_CNV_C42C43_C42               0                               /* Coefficient 4, 2 */
-#define BITM_PVP_CNV_C42C43_C43              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Coefficient 4, 3 */
-#define BITM_PVP_CNV_C42C43_C42              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 2 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_C44                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_C44_C44                  0                               /* Coefficient 4, 4 */
-#define BITM_PVP_CNV_C44_C44                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* Coefficient 4, 4 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_CNV_SCALE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_CNV_SCALE_VSCL              16                               /* Vertical Scaling factor */
-#define BITP_PVP_CNV_SCALE_HSCL               0                               /* Horizontal Scaling factor */
-#define BITM_PVP_CNV_SCALE_VSCL              (_ADI_MSK(0x01FF0000,uint32_t))  /* Vertical Scaling factor */
-#define BITM_PVP_CNV_SCALE_HSCL              (_ADI_MSK(0x000003FF,uint32_t))  /* Horizontal Scaling factor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_THC_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_THC_CFG_STATWCNT            24                               /* Status Word Count */
-#define BITP_PVP_THC_CFG_IBLOCK0              8                               /* Input Block ID */
-#define BITP_PVP_THC_CFG_IPORT0               4                               /* Input Port ID */
-#define BITP_PVP_THC_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_THC_CFG_START                0                               /* Start */
-#define BITM_PVP_THC_CFG_STATWCNT            (_ADI_MSK(0xFF000000,uint32_t))  /* Status Word Count */
-#define BITM_PVP_THC_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block ID */
-#define BITM_PVP_THC_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port ID */
-
-#define BITM_PVP_THC_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_THC_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_THC_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_THC_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_THC_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_THC_CTL_HISTEN              16                               /* Histogram Counters Enable */
-#define BITP_PVP_THC_CTL_RLEWM               11                               /* Run-length Encoding Window Mode */
-#define BITP_PVP_THC_CTL_HISTWM               9                               /* Histogram Window Mode */
-#define BITP_PVP_THC_CTL_RLEFRAME             8                               /* Run-Length-Encode Frame */
-#define BITP_PVP_THC_CTL_OFRMT                4                               /* Output Format */
-#define BITP_PVP_THC_CTL_ZEXT                 2                               /* Zero Extend */
-#define BITP_PVP_THC_CTL_MODE                 0                               /* Mode */
-
-#define BITM_PVP_THC_CTL_HISTEN              (_ADI_MSK(0x00010000,uint32_t))  /* Histogram Counters Enable */
-#define ENUM_PVP_THC_CTL_HISTDIS             (_ADI_MSK(0x00000000,uint32_t))  /* HISTEN: Disable */
-#define ENUM_PVP_THC_CTL_HISTEN              (_ADI_MSK(0x00010000,uint32_t))  /* HISTEN: Enable */
-
-#define BITM_PVP_THC_CTL_RLEWM               (_ADI_MSK(0x00001800,uint32_t))  /* Run-length Encoding Window Mode */
-#define ENUM_PVP_THC_CTL_COMPFRAME           (_ADI_MSK(0x00000000,uint32_t))  /* RLEWM: Frame Compression */
-#define ENUM_PVP_THC_CTL_COMPWIN             (_ADI_MSK(0x00000800,uint32_t))  /* RLEWM: Window Compression */
-
-#define BITM_PVP_THC_CTL_HISTWM              (_ADI_MSK(0x00000600,uint32_t))  /* Histogram Window Mode */
-#define ENUM_PVP_THC_CTL_HISTFRAME           (_ADI_MSK(0x00000000,uint32_t))  /* HISTWM: Frame Histogram */
-#define ENUM_PVP_THC_CTL_HISTWIN             (_ADI_MSK(0x00000200,uint32_t))  /* HISTWM: Inside-Window Histogram */
-#define ENUM_PVP_THC_CTL_HISTOUTWIN          (_ADI_MSK(0x00000400,uint32_t))  /* HISTWM: Outside-Window Histogram */
-
-#define BITM_PVP_THC_CTL_RLEFRAME            (_ADI_MSK(0x00000100,uint32_t))  /* Run-Length-Encode Frame */
-#define ENUM_PVP_THC_CTL_RLELINE             (_ADI_MSK(0x00000000,uint32_t))  /* RLEFRAME: Row (Line) Compression */
-#define ENUM_PVP_THC_CTL_RLEFRAME            (_ADI_MSK(0x00000100,uint32_t))  /* RLEFRAME: Frame Compression */
-
-#define BITM_PVP_THC_CTL_OFRMT               (_ADI_MSK(0x000000F0,uint32_t))  /* Output Format */
-#define ENUM_PVP_THC_CTL_WORD32              (_ADI_MSK(0x00000000,uint32_t))  /* OFRMT: 32-Bit Word ( No Compression ) */
-#define ENUM_PVP_THC_CTL_NODATA              (_ADI_MSK(0x000000A0,uint32_t))  /* OFRMT: Disable Output/RLE */
-#define ENUM_PVP_THC_CTL_INDX4               (_ADI_MSK(0x00000020,uint32_t))  /* OFRMT: 4-Bit Index ( No Compression) */
-#define ENUM_PVP_THC_CTL_INDX4RL4            (_ADI_MSK(0x00000030,uint32_t))  /* OFRMT: 4-Bit Index / 4-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4ANGL4          (_ADI_MSK(0x00000040,uint32_t))  /* OFRMT: 4-Bit Index / 4-Bit angle ( No Compression) */
-#define ENUM_PVP_THC_CTL_INDX3RL5            (_ADI_MSK(0x00000050,uint32_t))  /* OFRMT: 3-Bit Index / 5-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4RL12           (_ADI_MSK(0x00000060,uint32_t))  /* OFRMT: 4-Bit Index / 12-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX3RL13           (_ADI_MSK(0x00000070,uint32_t))  /* OFRMT: 3-Bit Index / 13-Bit Run Length */
-#define ENUM_PVP_THC_CTL_INDX4RL21           (_ADI_MSK(0x00000080,uint32_t))  /* OFRMT: 4-Bit Index / 21-Bit Run Length */
-#define ENUM_PVP_THC_CTL_WORD16RL16          (_ADI_MSK(0x00000090,uint32_t))  /* OFRMT: 16-Bit Word / 16-Bit Run Length */
-
-#define BITM_PVP_THC_CTL_ZEXT                (_ADI_MSK(0x00000004,uint32_t))  /* Zero Extend */
-#define ENUM_PVP_THC_CTL_ZEXTDIS             (_ADI_MSK(0x00000000,uint32_t))  /* ZEXT: No Zero Extension */
-#define ENUM_PVP_THC_CTL_ZEXTEN              (_ADI_MSK(0x00000004,uint32_t))  /* ZEXT: Zero Extend */
-
-#define BITM_PVP_THC_CTL_MODE                (_ADI_MSK(0x00000003,uint32_t))  /* Mode */
-#define ENUM_PVP_THC_CTL_CLIPMODE            (_ADI_MSK(0x00000000,uint32_t))  /* MODE: Clipping/Saturation Mode */
-#define ENUM_PVP_THC_CTL_QUANTMODE           (_ADI_MSK(0x00000001,uint32_t))  /* MODE: Quantization Mode */
-#define ENUM_PVP_THC_CTL_HYSTMODE            (_ADI_MSK(0x00000002,uint32_t))  /* MODE: Hysteresis Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PVP_PMA_CFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PVP_PMA_CFG_IBLOCK1             16                               /* Input Block 1 ID */
-#define BITP_PVP_PMA_CFG_IBLOCK0              8                               /* Input Block 0 ID */
-#define BITP_PVP_PMA_CFG_IPORT1               6                               /* Input Port 1 ID */
-#define BITP_PVP_PMA_CFG_IPORT0               4                               /* Input Port 0 ID */
-#define BITP_PVP_PMA_CFG_MPIPE                2                               /* Memory Pipe */
-#define BITP_PVP_PMA_CFG_START                0                               /* Start */
-#define BITM_PVP_PMA_CFG_IBLOCK1             (_ADI_MSK(0x00FF0000,uint32_t))  /* Input Block 1 ID */
-#define BITM_PVP_PMA_CFG_IBLOCK0             (_ADI_MSK(0x0000FF00,uint32_t))  /* Input Block 0 ID */
-#define BITM_PVP_PMA_CFG_IPORT1              (_ADI_MSK(0x000000C0,uint32_t))  /* Input Port 1 ID */
-#define BITM_PVP_PMA_CFG_IPORT0              (_ADI_MSK(0x00000030,uint32_t))  /* Input Port 0 ID */
-
-#define BITM_PVP_PMA_CFG_MPIPE               (_ADI_MSK(0x00000004,uint32_t))  /* Memory Pipe */
-#define ENUM_PVP_PMA_CFG_CAMPIPE             (_ADI_MSK(0x00000000,uint32_t))  /* MPIPE: Camera Pipe */
-#define ENUM_PVP_PMA_CFG_MEMPIPE             (_ADI_MSK(0x00000004,uint32_t))  /* MPIPE: Memory Pipe */
-#define BITM_PVP_PMA_CFG_START               (_ADI_MSK(0x00000001,uint32_t))  /* Start */
-
-/* ==================================================
-        Pulse-Width Modulator Registers
-   ================================================== */
-
-/* =========================
-        PWM0
-   ========================= */
-#define REG_PWM0_CTL                    0xFFC1B000         /* PWM0 Control Register */
-#define REG_PWM0_CHANCFG                0xFFC1B004         /* PWM0 Channel Config Register */
-#define REG_PWM0_TRIPCFG                0xFFC1B008         /* PWM0 Trip Config Register */
-#define REG_PWM0_STAT                   0xFFC1B00C         /* PWM0 Status Register */
-#define REG_PWM0_IMSK                   0xFFC1B010         /* PWM0 Interrupt Mask Register */
-#define REG_PWM0_ILAT                   0xFFC1B014         /* PWM0 Interrupt Latch Register */
-#define REG_PWM0_CHOPCFG                0xFFC1B018         /* PWM0 Chop Configuration Register */
-#define REG_PWM0_DT                     0xFFC1B01C         /* PWM0 Dead Time Register */
-#define REG_PWM0_SYNC_WID               0xFFC1B020         /* PWM0 Sync Pulse Width Register */
-#define REG_PWM0_TM0                    0xFFC1B024         /* PWM0 Timer 0 Period Register */
-#define REG_PWM0_TM1                    0xFFC1B028         /* PWM0 Timer 1 Period Register */
-#define REG_PWM0_TM2                    0xFFC1B02C         /* PWM0 Timer 2 Period Register */
-#define REG_PWM0_TM3                    0xFFC1B030         /* PWM0 Timer 3 Period Register */
-#define REG_PWM0_TM4                    0xFFC1B034         /* PWM0 Timer 4 Period Register */
-#define REG_PWM0_DLYA                   0xFFC1B038         /* PWM0 Channel A Delay Register */
-#define REG_PWM0_DLYB                   0xFFC1B03C         /* PWM0 Channel B Delay Register */
-#define REG_PWM0_DLYC                   0xFFC1B040         /* PWM0 Channel C Delay Register */
-#define REG_PWM0_DLYD                   0xFFC1B044         /* PWM0 Channel D Delay Register */
-#define REG_PWM0_ACTL                   0xFFC1B048         /* PWM0 Channel A Control Register */
-#define REG_PWM0_AH0                    0xFFC1B04C         /* PWM0 Channel A-High Duty-0 Register */
-#define REG_PWM0_AH1                    0xFFC1B050         /* PWM0 Channel A-High Duty-1 Register */
-#define REG_PWM0_AL0                    0xFFC1B05C         /* PWM0 Channel A-Low Duty-0 Register */
-#define REG_PWM0_AL1                    0xFFC1B060         /* PWM0 Channel A-Low Duty-1 Register */
-#define REG_PWM0_BCTL                   0xFFC1B064         /* PWM0 Channel B Control Register */
-#define REG_PWM0_BH0                    0xFFC1B068         /* PWM0 Channel B-High Duty-0 Register */
-#define REG_PWM0_BH1                    0xFFC1B06C         /* PWM0 Channel B-High Duty-1 Register */
-#define REG_PWM0_BL0                    0xFFC1B078         /* PWM0 Channel B-Low Duty-0 Register */
-#define REG_PWM0_BL1                    0xFFC1B07C         /* PWM0 Channel B-Low Duty-1 Register */
-#define REG_PWM0_CCTL                   0xFFC1B080         /* PWM0 Channel C Control Register */
-#define REG_PWM0_CH0                    0xFFC1B084         /* PWM0 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM0_CH1                    0xFFC1B088         /* PWM0 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM0_CL0                    0xFFC1B094         /* PWM0 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM0_CL1                    0xFFC1B098         /* PWM0 Channel C-Low Duty-1 Register */
-#define REG_PWM0_DCTL                   0xFFC1B09C         /* PWM0 Channel D Control Register */
-#define REG_PWM0_DH0                    0xFFC1B0A0         /* PWM0 Channel D-High Duty-0 Register */
-#define REG_PWM0_DH1                    0xFFC1B0A4         /* PWM0 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM0_DL0                    0xFFC1B0B0         /* PWM0 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM0_DL1                    0xFFC1B0B4         /* PWM0 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM1
-   ========================= */
-#define REG_PWM1_CTL                    0xFFC1B400         /* PWM1 Control Register */
-#define REG_PWM1_CHANCFG                0xFFC1B404         /* PWM1 Channel Config Register */
-#define REG_PWM1_TRIPCFG                0xFFC1B408         /* PWM1 Trip Config Register */
-#define REG_PWM1_STAT                   0xFFC1B40C         /* PWM1 Status Register */
-#define REG_PWM1_IMSK                   0xFFC1B410         /* PWM1 Interrupt Mask Register */
-#define REG_PWM1_ILAT                   0xFFC1B414         /* PWM1 Interrupt Latch Register */
-#define REG_PWM1_CHOPCFG                0xFFC1B418         /* PWM1 Chop Configuration Register */
-#define REG_PWM1_DT                     0xFFC1B41C         /* PWM1 Dead Time Register */
-#define REG_PWM1_SYNC_WID               0xFFC1B420         /* PWM1 Sync Pulse Width Register */
-#define REG_PWM1_TM0                    0xFFC1B424         /* PWM1 Timer 0 Period Register */
-#define REG_PWM1_TM1                    0xFFC1B428         /* PWM1 Timer 1 Period Register */
-#define REG_PWM1_TM2                    0xFFC1B42C         /* PWM1 Timer 2 Period Register */
-#define REG_PWM1_TM3                    0xFFC1B430         /* PWM1 Timer 3 Period Register */
-#define REG_PWM1_TM4                    0xFFC1B434         /* PWM1 Timer 4 Period Register */
-#define REG_PWM1_DLYA                   0xFFC1B438         /* PWM1 Channel A Delay Register */
-#define REG_PWM1_DLYB                   0xFFC1B43C         /* PWM1 Channel B Delay Register */
-#define REG_PWM1_DLYC                   0xFFC1B440         /* PWM1 Channel C Delay Register */
-#define REG_PWM1_DLYD                   0xFFC1B444         /* PWM1 Channel D Delay Register */
-#define REG_PWM1_ACTL                   0xFFC1B448         /* PWM1 Channel A Control Register */
-#define REG_PWM1_AH0                    0xFFC1B44C         /* PWM1 Channel A-High Duty-0 Register */
-#define REG_PWM1_AH1                    0xFFC1B450         /* PWM1 Channel A-High Duty-1 Register */
-#define REG_PWM1_AL0                    0xFFC1B45C         /* PWM1 Channel A-Low Duty-0 Register */
-#define REG_PWM1_AL1                    0xFFC1B460         /* PWM1 Channel A-Low Duty-1 Register */
-#define REG_PWM1_BCTL                   0xFFC1B464         /* PWM1 Channel B Control Register */
-#define REG_PWM1_BH0                    0xFFC1B468         /* PWM1 Channel B-High Duty-0 Register */
-#define REG_PWM1_BH1                    0xFFC1B46C         /* PWM1 Channel B-High Duty-1 Register */
-#define REG_PWM1_BL0                    0xFFC1B478         /* PWM1 Channel B-Low Duty-0 Register */
-#define REG_PWM1_BL1                    0xFFC1B47C         /* PWM1 Channel B-Low Duty-1 Register */
-#define REG_PWM1_CCTL                   0xFFC1B480         /* PWM1 Channel C Control Register */
-#define REG_PWM1_CH0                    0xFFC1B484         /* PWM1 Channel C-High Pulse Duty Register 0 */
-#define REG_PWM1_CH1                    0xFFC1B488         /* PWM1 Channel C-High Pulse Duty Register 1 */
-#define REG_PWM1_CL0                    0xFFC1B494         /* PWM1 Channel C-Low Pulse Duty Register 0 */
-#define REG_PWM1_CL1                    0xFFC1B498         /* PWM1 Channel C-Low Duty-1 Register */
-#define REG_PWM1_DCTL                   0xFFC1B49C         /* PWM1 Channel D Control Register */
-#define REG_PWM1_DH0                    0xFFC1B4A0         /* PWM1 Channel D-High Duty-0 Register */
-#define REG_PWM1_DH1                    0xFFC1B4A4         /* PWM1 Channel D-High Pulse Duty Register 1 */
-#define REG_PWM1_DL0                    0xFFC1B4B0         /* PWM1 Channel D-Low Pulse Duty Register 0 */
-#define REG_PWM1_DL1                    0xFFC1B4B4         /* PWM1 Channel D-Low Pulse Duty Register 1 */
-
-/* =========================
-        PWM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CTL_INTSYNCREF              18                               /* Timer reference for Internal Sync */
-#define BITP_PWM_CTL_EXTSYNCSEL              17                               /* External Sync Select */
-#define BITP_PWM_CTL_EXTSYNC                 16                               /* External Sync */
-#define BITP_PWM_CTL_DLYDEN                   7                               /* Enable Delay Counter for Channel D */
-#define BITP_PWM_CTL_DLYCEN                   6                               /* Enable Delay Counter for Channel C */
-#define BITP_PWM_CTL_DLYBEN                   5                               /* Enable Delay Counter for Channel B */
-#define BITP_PWM_CTL_DLYAEN                   4                               /* Enable Delay Counter for Channel A */
-#define BITP_PWM_CTL_SWTRIP                   2                               /* Software Trip */
-#define BITP_PWM_CTL_EMURUN                   1                               /* Output Behavior During Emulation Mode */
-#define BITP_PWM_CTL_GLOBEN                   0                               /* Module Enable */
-
-#define BITM_PWM_CTL_INTSYNCREF              (_ADI_MSK(0x001C0000,uint32_t))  /* Timer reference for Internal Sync */
-#define ENUM_PWM_CTL_INTSYNC_0               (_ADI_MSK(0x00000000,uint32_t))  /* INTSYNCREF: PWMTMR0 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_1               (_ADI_MSK(0x00040000,uint32_t))  /* INTSYNCREF: PWMTMR1 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_2               (_ADI_MSK(0x00080000,uint32_t))  /* INTSYNCREF: PWMTMR2 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_3               (_ADI_MSK(0x000C0000,uint32_t))  /* INTSYNCREF: PWMTMR3 provides sync reference */
-#define ENUM_PWM_CTL_INTSYNC_4               (_ADI_MSK(0x00100000,uint32_t))  /* INTSYNCREF: PWMTMR4 provides sync reference */
-
-#define BITM_PWM_CTL_EXTSYNCSEL              (_ADI_MSK(0x00020000,uint32_t))  /* External Sync Select */
-#define ENUM_PWM_CTL_EXTSYNC_ASYNC           (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNCSEL: Asynchronous External Sync */
-#define ENUM_PWM_CTL_EXTSYNC_SYNC            (_ADI_MSK(0x00020000,uint32_t))  /* EXTSYNCSEL: Synchronous External Sync */
-
-#define BITM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* External Sync */
-#define ENUM_PWM_CTL_INTSYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* EXTSYNC: Internal sync used */
-#define ENUM_PWM_CTL_EXTSYNC                 (_ADI_MSK(0x00010000,uint32_t))  /* EXTSYNC: External sync used */
-
-#define BITM_PWM_CTL_DLYDEN                  (_ADI_MSK(0x00000080,uint32_t))  /* Enable Delay Counter for Channel D */
-#define ENUM_PWM_CTL_DLYD_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYDEN: Disable */
-#define ENUM_PWM_CTL_DLYD_EN                 (_ADI_MSK(0x00000080,uint32_t))  /* DLYDEN: Enable */
-
-#define BITM_PWM_CTL_DLYCEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Delay Counter for Channel C */
-#define ENUM_PWM_CTL_DLYC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYCEN: Disable */
-#define ENUM_PWM_CTL_DLYC_EN                 (_ADI_MSK(0x00000040,uint32_t))  /* DLYCEN: Enable */
-
-#define BITM_PWM_CTL_DLYBEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Delay Counter for Channel B */
-#define ENUM_PWM_CTL_DLYB_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYBEN: Disable */
-#define ENUM_PWM_CTL_DLYB_EN                 (_ADI_MSK(0x00000020,uint32_t))  /* DLYBEN: Enable */
-
-#define BITM_PWM_CTL_DLYAEN                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable Delay Counter for Channel A */
-#define ENUM_PWM_CTL_DLYA_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* DLYAEN: Disable */
-#define ENUM_PWM_CTL_DLYA_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* DLYAEN: Enable */
-
-#define BITM_PWM_CTL_SWTRIP                  (_ADI_MSK(0x00000004,uint32_t))  /* Software Trip */
-#define ENUM_PWM_CTL_FORCE_TRIP              (_ADI_MSK(0x00000004,uint32_t))  /* SWTRIP: Force a Fault Trip Condition */
-
-#define BITM_PWM_CTL_EMURUN                  (_ADI_MSK(0x00000002,uint32_t))  /* Output Behavior During Emulation Mode */
-#define ENUM_PWM_CTL_EMURUN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* EMURUN: Disable Outputs */
-#define ENUM_PWM_CTL_EMURUN_EN               (_ADI_MSK(0x00000002,uint32_t))  /* EMURUN: Enable Outputs */
-
-#define BITM_PWM_CTL_GLOBEN                  (_ADI_MSK(0x00000001,uint32_t))  /* Module Enable */
-#define ENUM_PWM_CTL_PWM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* GLOBEN: Disable */
-#define ENUM_PWM_CTL_PWM_EN                  (_ADI_MSK(0x00000001,uint32_t))  /* GLOBEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHANCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHANCFG_ENCHOPDL            30                               /* Channel D Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLDL               29                               /* Channel D low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPDH            27                               /* Channel D Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLDH               26                               /* Channel D High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSD             25                               /* Channel D Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRD             24                               /* Channel D Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPCL            22                               /* Channel C Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLCL               21                               /* Channel C low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPCH            19                               /* Channel C Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLCH               18                               /* Channel C High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSC             17                               /* Channel C Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRC             16                               /* Channel C Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPBL            14                               /* Channel B Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLBL               13                               /* Channel B low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPBH            11                               /* Channel B Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLBH               10                               /* Channel B High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSB              9                               /* Channel B Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRB              8                               /* Channel B Timer Reference */
-#define BITP_PWM_CHANCFG_ENCHOPAL             6                               /* Channel A Gate Chopping Enable Low Side */
-#define BITP_PWM_CHANCFG_POLAL                5                               /* Channel A low side Polarity */
-#define BITP_PWM_CHANCFG_ENCHOPAH             3                               /* Channel A Gate Chopping Enable High Side */
-#define BITP_PWM_CHANCFG_POLAH                2                               /* Channel A High side Polarity */
-#define BITP_PWM_CHANCFG_MODELSA              1                               /* Channel A Mode of low Side Output */
-#define BITP_PWM_CHANCFG_REFTMRA              0                               /* Channel A Timer Reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPDL            (_ADI_MSK(0x40000000,uint32_t))  /* Channel D Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDL: Disable Chopping Channel D Low Side */
-#define ENUM_PWM_CHANCFG_CHOPDL_EN           (_ADI_MSK(0x40000000,uint32_t))  /* ENCHOPDL: Enable Chopping Channel D Low Side */
-
-#define BITM_PWM_CHANCFG_POLDL               (_ADI_MSK(0x20000000,uint32_t))  /* Channel D low side Polarity */
-#define ENUM_PWM_CHANCFG_DL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDL: Active Low */
-#define ENUM_PWM_CHANCFG_DL_ACTHI            (_ADI_MSK(0x20000000,uint32_t))  /* POLDL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPDH            (_ADI_MSK(0x08000000,uint32_t))  /* Channel D Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPDH: Disable Chopping Channel D High Side */
-#define ENUM_PWM_CHANCFG_CHOPDH_EN           (_ADI_MSK(0x08000000,uint32_t))  /* ENCHOPDH: Enable Chopping Channel D High Side */
-
-#define BITM_PWM_CHANCFG_POLDH               (_ADI_MSK(0x04000000,uint32_t))  /* Channel D High side Polarity */
-#define ENUM_PWM_CHANCFG_DH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLDH: Active Low */
-#define ENUM_PWM_CHANCFG_DH_ACTHI            (_ADI_MSK(0x04000000,uint32_t))  /* POLDH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSD             (_ADI_MSK(0x02000000,uint32_t))  /* Channel D Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOD_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSD: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOD_IND             (_ADI_MSK(0x02000000,uint32_t))  /* MODELSD: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRD             (_ADI_MSK(0x01000000,uint32_t))  /* Channel D Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRD: PWMTMR0 is Channel D reference */
-#define ENUM_PWM_CHANCFG_REFTMRD_1           (_ADI_MSK(0x01000000,uint32_t))  /* REFTMRD: PWMTMR1 is Channel D reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPCL            (_ADI_MSK(0x00400000,uint32_t))  /* Channel C Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCL: Disable Chopping Channel C Low Side */
-#define ENUM_PWM_CHANCFG_CHOPCL_EN           (_ADI_MSK(0x00400000,uint32_t))  /* ENCHOPCL: Enable Chopping Channel C Low Side */
-
-#define BITM_PWM_CHANCFG_POLCL               (_ADI_MSK(0x00200000,uint32_t))  /* Channel C low side Polarity */
-#define ENUM_PWM_CHANCFG_CL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCL: Active Low */
-#define ENUM_PWM_CHANCFG_CL_ACTHI            (_ADI_MSK(0x00200000,uint32_t))  /* POLCL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPCH            (_ADI_MSK(0x00080000,uint32_t))  /* Channel C Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPCH: Disable Chopping Channel C High Side */
-#define ENUM_PWM_CHANCFG_CHOPCH_EN           (_ADI_MSK(0x00080000,uint32_t))  /* ENCHOPCH: Enable Chopping Channel C High Side */
-
-#define BITM_PWM_CHANCFG_POLCH               (_ADI_MSK(0x00040000,uint32_t))  /* Channel C High side Polarity */
-#define ENUM_PWM_CHANCFG_CH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLCH: Active Low */
-#define ENUM_PWM_CHANCFG_CH_ACTHI            (_ADI_MSK(0x00040000,uint32_t))  /* POLCH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSC             (_ADI_MSK(0x00020000,uint32_t))  /* Channel C Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOC_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSC: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOC_IND             (_ADI_MSK(0x00020000,uint32_t))  /* MODELSC: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRC             (_ADI_MSK(0x00010000,uint32_t))  /* Channel C Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRC: PWMTMR0 is Channel C reference */
-#define ENUM_PWM_CHANCFG_REFTMRC_1           (_ADI_MSK(0x00010000,uint32_t))  /* REFTMRC: PWMTMR1 is Channel C reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPBL            (_ADI_MSK(0x00004000,uint32_t))  /* Channel B Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBL: Disable Chopping Channel B Low Side */
-#define ENUM_PWM_CHANCFG_CHOPBL_EN           (_ADI_MSK(0x00004000,uint32_t))  /* ENCHOPBL: Enable Chopping Channel B Low Side */
-
-#define BITM_PWM_CHANCFG_POLBL               (_ADI_MSK(0x00002000,uint32_t))  /* Channel B low side Polarity */
-#define ENUM_PWM_CHANCFG_BL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBL: Active Low */
-#define ENUM_PWM_CHANCFG_BL_ACTHI            (_ADI_MSK(0x00002000,uint32_t))  /* POLBL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPBH            (_ADI_MSK(0x00000800,uint32_t))  /* Channel B Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPBH: Disable Chopping Channel B High Side */
-#define ENUM_PWM_CHANCFG_CHOPBH_EN           (_ADI_MSK(0x00000800,uint32_t))  /* ENCHOPBH: Enable Chopping Channel B High Side */
-
-#define BITM_PWM_CHANCFG_POLBH               (_ADI_MSK(0x00000400,uint32_t))  /* Channel B High side Polarity */
-#define ENUM_PWM_CHANCFG_BH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLBH: Active Low */
-#define ENUM_PWM_CHANCFG_BH_ACTHI            (_ADI_MSK(0x00000400,uint32_t))  /* POLBH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSB             (_ADI_MSK(0x00000200,uint32_t))  /* Channel B Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOB_INV             (_ADI_MSK(0x00000000,uint32_t))  /* MODELSB: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOB_IND             (_ADI_MSK(0x00000200,uint32_t))  /* MODELSB: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRB             (_ADI_MSK(0x00000100,uint32_t))  /* Channel B Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRB: PWMTMR0 is Channel  B reference */
-#define ENUM_PWM_CHANCFG_REFTMRB_1           (_ADI_MSK(0x00000100,uint32_t))  /* REFTMRB: PWMTMR1 is Channel B reference */
-
-#define BITM_PWM_CHANCFG_ENCHOPAL            (_ADI_MSK(0x00000040,uint32_t))  /* Channel A Gate Chopping Enable Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAL: Disable Chopping Channel A Low Side */
-#define ENUM_PWM_CHANCFG_CHOPAL_EN           (_ADI_MSK(0x00000040,uint32_t))  /* ENCHOPAL: Enable Chopping Channel A Low Side */
-
-#define BITM_PWM_CHANCFG_POLAL               (_ADI_MSK(0x00000020,uint32_t))  /* Channel A low side Polarity */
-#define ENUM_PWM_CHANCFG_AL_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAL: Active Low */
-#define ENUM_PWM_CHANCFG_AL_ACTHI            (_ADI_MSK(0x00000020,uint32_t))  /* POLAL: Active High */
-
-#define BITM_PWM_CHANCFG_ENCHOPAH            (_ADI_MSK(0x00000008,uint32_t))  /* Channel A Gate Chopping Enable High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* ENCHOPAH: Disable Chopping Channel A High Side */
-#define ENUM_PWM_CHANCFG_CHOPAH_EN           (_ADI_MSK(0x00000008,uint32_t))  /* ENCHOPAH: Enable Chopping Channel A High Side */
-
-#define BITM_PWM_CHANCFG_POLAH               (_ADI_MSK(0x00000004,uint32_t))  /* Channel A High side Polarity */
-#define ENUM_PWM_CHANCFG_AH_ACTLO            (_ADI_MSK(0x00000000,uint32_t))  /* POLAH: Active Low */
-#define ENUM_PWM_CHANCFG_AH_ACTHI            (_ADI_MSK(0x00000004,uint32_t))  /* POLAH: Active High */
-
-#define BITM_PWM_CHANCFG_MODELSA             (_ADI_MSK(0x00000002,uint32_t))  /* Channel A Mode of low Side Output */
-#define ENUM_PWM_CHANCFG_LOA_INVHI           (_ADI_MSK(0x00000000,uint32_t))  /* MODELSA: Invert of high output */
-#define ENUM_PWM_CHANCFG_LOA_IND             (_ADI_MSK(0x00000002,uint32_t))  /* MODELSA: Independent control */
-
-#define BITM_PWM_CHANCFG_REFTMRA             (_ADI_MSK(0x00000001,uint32_t))  /* Channel A Timer Reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_0           (_ADI_MSK(0x00000000,uint32_t))  /* REFTMRA: PWMTMR0 is Channel A reference */
-#define ENUM_PWM_CHANCFG_REFTMRA_1           (_ADI_MSK(0x00000001,uint32_t))  /* REFTMRA: PWMTMR1 is Channel A reference */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TRIPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TRIPCFG_MODE1D              27                               /* Mode of TRIP1 for Channel D */
-#define BITP_PWM_TRIPCFG_EN1D                26                               /* Enable TRIP1 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE0D              25                               /* Mode of TRIP0 for Channel D */
-#define BITP_PWM_TRIPCFG_EN0D                24                               /* Enable TRIP0 as a trip source for Channel D */
-#define BITP_PWM_TRIPCFG_MODE1C              19                               /* Mode of TRIP1 for Channel C */
-#define BITP_PWM_TRIPCFG_EN1C                18                               /* Enable TRIP1 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE0C              17                               /* Mode of TRIP0 for Channel C */
-#define BITP_PWM_TRIPCFG_EN0C                16                               /* Enable TRIP0 as a trip source for Channel C */
-#define BITP_PWM_TRIPCFG_MODE1B              11                               /* Mode of TRIP1 for Channel B */
-#define BITP_PWM_TRIPCFG_EN1B                10                               /* Enable TRIP1 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE0B               9                               /* Mode of TRIP0 for Channel B */
-#define BITP_PWM_TRIPCFG_EN0B                 8                               /* Enable TRIP0 as a trip source for Channel B */
-#define BITP_PWM_TRIPCFG_MODE1A               3                               /* Mode of TRIP1 for Channel A */
-#define BITP_PWM_TRIPCFG_EN1A                 2                               /* Enable TRIP1 as a trip source for Channel A */
-#define BITP_PWM_TRIPCFG_MODE0A               1                               /* Mode of TRIP0 for Channel A */
-#define BITP_PWM_TRIPCFG_EN0A                 0                               /* Enable TRIP0 as a trip source for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE1D              (_ADI_MSK(0x08000000,uint32_t))  /* Mode of TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1D: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1D_RSTRT        (_ADI_MSK(0x08000000,uint32_t))  /* MODE1D: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1D                (_ADI_MSK(0x04000000,uint32_t))  /* Enable TRIP1 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1D: Disable TRIP1 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP1D_EN           (_ADI_MSK(0x04000000,uint32_t))  /* EN1D: Enable TRIP1 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE0D              (_ADI_MSK(0x02000000,uint32_t))  /* Mode of TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0D: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0D_RSTRT        (_ADI_MSK(0x02000000,uint32_t))  /* MODE0D: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0D                (_ADI_MSK(0x01000000,uint32_t))  /* Enable TRIP0 as a trip source for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0D: Disable TRIP0 for Channel D */
-#define ENUM_PWM_TRIPCFG_TRIP0D_EN           (_ADI_MSK(0x01000000,uint32_t))  /* EN0D: Enable TRIP0 for Channel D */
-
-#define BITM_PWM_TRIPCFG_MODE1C              (_ADI_MSK(0x00080000,uint32_t))  /* Mode of TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1C: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1C_RSTRT        (_ADI_MSK(0x00080000,uint32_t))  /* MODE1C: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1C                (_ADI_MSK(0x00040000,uint32_t))  /* Enable TRIP1 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1C: Disable TRIP1 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP1C_EN           (_ADI_MSK(0x00040000,uint32_t))  /* EN1C: Enable TRIP1 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE0C              (_ADI_MSK(0x00020000,uint32_t))  /* Mode of TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0C: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0C_RSTRT        (_ADI_MSK(0x00020000,uint32_t))  /* MODE0C: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0C                (_ADI_MSK(0x00010000,uint32_t))  /* Enable TRIP0 as a trip source for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0C: Disable TRIP0 for Channel C */
-#define ENUM_PWM_TRIPCFG_TRIP0C_EN           (_ADI_MSK(0x00010000,uint32_t))  /* EN0C: Enable TRIP0 for Channel C */
-
-#define BITM_PWM_TRIPCFG_MODE1B              (_ADI_MSK(0x00000800,uint32_t))  /* Mode of TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1B: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1B_RSTRT        (_ADI_MSK(0x00000800,uint32_t))  /* MODE1B: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1B                (_ADI_MSK(0x00000400,uint32_t))  /* Enable TRIP1 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1B: Disable TRIP1 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP1B_EN           (_ADI_MSK(0x00000400,uint32_t))  /* EN1B: Enable TRIP1 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE0B              (_ADI_MSK(0x00000200,uint32_t))  /* Mode of TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0B: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0B_RSTRT        (_ADI_MSK(0x00000200,uint32_t))  /* MODE0B: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0B                (_ADI_MSK(0x00000100,uint32_t))  /* Enable TRIP0 as a trip source for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0B: Disable TRIP0 for Channel B */
-#define ENUM_PWM_TRIPCFG_TRIP0B_EN           (_ADI_MSK(0x00000100,uint32_t))  /* EN0B: Enable TRIP0 for Channel B */
-
-#define BITM_PWM_TRIPCFG_MODE1A              (_ADI_MSK(0x00000008,uint32_t))  /* Mode of TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE1A: Fault Trip on TRIP1 Input */
-#define ENUM_PWM_TRIPCFG_TRIP1A_RSTRT        (_ADI_MSK(0x00000008,uint32_t))  /* MODE1A: Self Restart on TRIP1 Input */
-
-#define BITM_PWM_TRIPCFG_EN1A                (_ADI_MSK(0x00000004,uint32_t))  /* Enable TRIP1 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN1A: Disable TRIP1 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP1A_EN           (_ADI_MSK(0x00000004,uint32_t))  /* EN1A: Enable TRIP1 for Channel A */
-
-#define BITM_PWM_TRIPCFG_MODE0A              (_ADI_MSK(0x00000002,uint32_t))  /* Mode of TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_FLT          (_ADI_MSK(0x00000000,uint32_t))  /* MODE0A: Fault Trip on TRIP0 Input */
-#define ENUM_PWM_TRIPCFG_TRIP0A_RSTRT        (_ADI_MSK(0x00000002,uint32_t))  /* MODE0A: Self Restart on TRIP0 Input */
-
-#define BITM_PWM_TRIPCFG_EN0A                (_ADI_MSK(0x00000001,uint32_t))  /* Enable TRIP0 as a trip source for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* EN0A: Disable TRIP0 for Channel A */
-#define ENUM_PWM_TRIPCFG_TRIP0A_EN           (_ADI_MSK(0x00000001,uint32_t))  /* EN0A: Enable TRIP0 for Channel A */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_STAT_TMR4PHASE              28                               /* PWMTMR4 Phase Status */
-#define BITP_PWM_STAT_TMR3PHASE              27                               /* PWMTMR3 Phase Status */
-#define BITP_PWM_STAT_TMR2PHASE              26                               /* PWMTMR2 Phase Status */
-#define BITP_PWM_STAT_TMR1PHASE              25                               /* PWMTMR1 Phase Status */
-#define BITP_PWM_STAT_TMR0PHASE              24                               /* PWMTMR0 Phase Status */
-#define BITP_PWM_STAT_TMR4PER                20                               /* PWMTMR4 Period Boundary Status */
-#define BITP_PWM_STAT_TMR3PER                19                               /* PWMTMR3 Period Boundary Status */
-#define BITP_PWM_STAT_TMR2PER                18                               /* PWMTMR2 Period Boundary Status */
-#define BITP_PWM_STAT_TMR1PER                17                               /* PWMTMR1 Period Boundary Status */
-#define BITP_PWM_STAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Status */
-#define BITP_PWM_STAT_SRTRIPD                11                               /* Self-Restart Trip Status for Channel D */
-#define BITP_PWM_STAT_FLTTRIPD               10                               /* Fault Trip Status for Channel D */
-#define BITP_PWM_STAT_SRTRIPC                 9                               /* Self-Restart Trip Status for Channel C */
-#define BITP_PWM_STAT_FLTTRIPC                8                               /* Fault Trip Status for Channel C */
-#define BITP_PWM_STAT_SRTRIPB                 7                               /* Self-Restart Trip Status for Channel B */
-#define BITP_PWM_STAT_FLTTRIPB                6                               /* Fault Trip Status for Channel B */
-#define BITP_PWM_STAT_SRTRIPA                 5                               /* Self-Restart Trip Status for Channel A */
-#define BITP_PWM_STAT_FLTTRIPA                4                               /* Fault Trip Status for Channel A */
-#define BITP_PWM_STAT_RAWTRIP1                3                               /* Raw Trip 1 Status */
-#define BITP_PWM_STAT_RAWTRIP0                2                               /* Raw Trip 0 Status */
-#define BITP_PWM_STAT_TRIP1                   1                               /* Status bit set when TRIP1 is active low */
-#define BITP_PWM_STAT_TRIP0                   0                               /* Status bit set when TRIP0 is active low */
-
-#define BITM_PWM_STAT_TMR4PHASE              (_ADI_MSK(0x10000000,uint32_t))  /* PWMTMR4 Phase Status */
-#define ENUM_PWM_STAT_TMR4PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR4PH2                (_ADI_MSK(0x10000000,uint32_t))  /* TMR4PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR3PHASE              (_ADI_MSK(0x08000000,uint32_t))  /* PWMTMR3 Phase Status */
-#define ENUM_PWM_STAT_TMR3PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR3PH2                (_ADI_MSK(0x08000000,uint32_t))  /* TMR3PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR2PHASE              (_ADI_MSK(0x04000000,uint32_t))  /* PWMTMR2 Phase Status */
-#define ENUM_PWM_STAT_TMR2PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR2PH2                (_ADI_MSK(0x04000000,uint32_t))  /* TMR2PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR1PHASE              (_ADI_MSK(0x02000000,uint32_t))  /* PWMTMR1 Phase Status */
-#define ENUM_PWM_STAT_TMR1PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR1PH2                (_ADI_MSK(0x02000000,uint32_t))  /* TMR1PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR0PHASE              (_ADI_MSK(0x01000000,uint32_t))  /* PWMTMR0 Phase Status */
-#define ENUM_PWM_STAT_TMR0PH1                (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PHASE: 1st Half Phase */
-#define ENUM_PWM_STAT_TMR0PH2                (_ADI_MSK(0x01000000,uint32_t))  /* TMR0PHASE: 2nd Half Phase */
-
-#define BITM_PWM_STAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER4               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary not reached */
-#define ENUM_PWM_STAT_PER4                   (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: PWMTMR4 period boundary reached */
-
-#define BITM_PWM_STAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER3               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary not reached */
-#define ENUM_PWM_STAT_PER3                   (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: PWMTMR3 period boundary reached */
-
-#define BITM_PWM_STAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER2               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary not reached */
-#define ENUM_PWM_STAT_PER2                   (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: PWMTMR2 period boundary reached */
-
-#define BITM_PWM_STAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER1               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary not reached */
-#define ENUM_PWM_STAT_PER1                   (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: PWMTMR1 period boundary reached */
-
-#define BITM_PWM_STAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Status */
-#define ENUM_PWM_STAT_NOT_PER0               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary not reached */
-#define ENUM_PWM_STAT_PER0                   (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: PWMTMR0 period boundary reached */
-
-#define BITM_PWM_STAT_SRTRIPD                (_ADI_MSK(0x00000800,uint32_t))  /* Self-Restart Trip Status for Channel D */
-#define ENUM_PWM_STAT_SRD_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRD_TRIP               (_ADI_MSK(0x00000800,uint32_t))  /* SRTRIPD: Channel D Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPD               (_ADI_MSK(0x00000400,uint32_t))  /* Fault Trip Status for Channel D */
-#define ENUM_PWM_STAT_FLTD_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTD_TRIP              (_ADI_MSK(0x00000400,uint32_t))  /* FLTTRIPD: Channel D Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPC                (_ADI_MSK(0x00000200,uint32_t))  /* Self-Restart Trip Status for Channel C */
-#define ENUM_PWM_STAT_SRC_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRC_TRIP               (_ADI_MSK(0x00000200,uint32_t))  /* SRTRIPC: Channel C Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPC               (_ADI_MSK(0x00000100,uint32_t))  /* Fault Trip Status for Channel C */
-#define ENUM_PWM_STAT_FLTC_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTC_TRIP              (_ADI_MSK(0x00000100,uint32_t))  /* FLTTRIPC: Channel C Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPB                (_ADI_MSK(0x00000080,uint32_t))  /* Self-Restart Trip Status for Channel B */
-#define ENUM_PWM_STAT_SRB_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRB_TRIP               (_ADI_MSK(0x00000080,uint32_t))  /* SRTRIPB: Channel B Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPB               (_ADI_MSK(0x00000040,uint32_t))  /* Fault Trip Status for Channel B */
-#define ENUM_PWM_STAT_FLTB_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPB: Channel B Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTB_TRIP              (_ADI_MSK(0x00000040,uint32_t))  /* FLTTRIPB: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_SRTRIPA                (_ADI_MSK(0x00000020,uint32_t))  /* Self-Restart Trip Status for Channel A */
-#define ENUM_PWM_STAT_SRA_NOTRIP             (_ADI_MSK(0x00000000,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_SRA_TRIP               (_ADI_MSK(0x00000020,uint32_t))  /* SRTRIPA: Channel A Self-Restart Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_FLTTRIPA               (_ADI_MSK(0x00000010,uint32_t))  /* Fault Trip Status for Channel A */
-#define ENUM_PWM_STAT_FLTA_NOTRIP            (_ADI_MSK(0x00000000,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "not tripped" */
-#define ENUM_PWM_STAT_FLTA_TRIP              (_ADI_MSK(0x00000010,uint32_t))  /* FLTTRIPA: Channel A Fault Trip Status is "tripped" */
-
-#define BITM_PWM_STAT_RAWTRIP1               (_ADI_MSK(0x00000008,uint32_t))  /* Raw Trip 1 Status */
-#define ENUM_PWM_STAT_TRIP1LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP1: TRIP1 Level is Low */
-#define ENUM_PWM_STAT_TRIP1LVL_HI            (_ADI_MSK(0x00000008,uint32_t))  /* RAWTRIP1: TRIP1 Level is High */
-
-#define BITM_PWM_STAT_RAWTRIP0               (_ADI_MSK(0x00000004,uint32_t))  /* Raw Trip 0 Status */
-#define ENUM_PWM_STAT_TRIP0LVL_LO            (_ADI_MSK(0x00000000,uint32_t))  /* RAWTRIP0: TRIP0 Level is Low */
-#define ENUM_PWM_STAT_TRIP0LVL_HI            (_ADI_MSK(0x00000004,uint32_t))  /* RAWTRIP0: TRIP0 Level is High */
-
-#define BITM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* Status bit set when TRIP1 is active low */
-#define ENUM_PWM_STAT_NO_TRIP1               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: TRIP1 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: TRIP1 status is "tripped" (active low) */
-
-#define BITM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* Status bit set when TRIP0 is active low */
-#define ENUM_PWM_STAT_NO_TRIP0               (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: TRIP0 status is "not tripped" */
-#define ENUM_PWM_STAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: TRIP0 status is "tripped" (active low) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_IMSK_TMR4PER                20                               /* PWMTMR4 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR3PER                19                               /* PWMTMR3 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR2PER                18                               /* PWMTMR2 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR1PER                17                               /* PWMTMR1 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP1                   1                               /* TRIP1 Interrupt Enable */
-#define BITP_PWM_IMSK_TRIP0                   0                               /* TRIP0 Interrupt Enable */
-
-#define BITM_PWM_IMSK_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER4_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: Mask PWMTMR4 Period Interrupt */
-#define ENUM_PWM_IMSK_PER4_UMSK              (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Unmask PWMTMR4 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER3_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: Mask PWMTMR3 Period Interrupt */
-#define ENUM_PWM_IMSK_PER3_UMSK              (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Unmask PWMTMR3 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER2_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: Mask PWMTMR2 Period Interrupt */
-#define ENUM_PWM_IMSK_PER2_UMSK              (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Unmask PWMTMR2 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER1_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: Mask PWMTMR1 Period Interrupt */
-#define ENUM_PWM_IMSK_PER1_UMSK              (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Unmask PWMTMR1 Period Interrupt */
-
-#define BITM_PWM_IMSK_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Enable */
-#define ENUM_PWM_IMSK_PER0_MSK               (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: Mask PWMTMR0 Period Interrupt */
-#define ENUM_PWM_IMSK_PER0_UMSK              (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Unmask PWMTMR0 Period Interrupt */
-
-#define BITM_PWM_IMSK_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP1_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: Mask TRIP1 Interrupt */
-#define ENUM_PWM_IMSK_TRIP1_UMSK             (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Unmask TRIP1 Interrupt */
-
-#define BITM_PWM_IMSK_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Enable */
-#define ENUM_PWM_IMSK_TRIP0_MSK              (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: Mask TRIP0 Interrupt */
-#define ENUM_PWM_IMSK_TRIP0_UMSK             (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Unmask TRIP0 Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ILAT_TMR4PER                20                               /* PWMTMR4 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR3PER                19                               /* PWMTMR3 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR2PER                18                               /* PWMTMR2 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR1PER                17                               /* PWMTMR1 Period Latched Interrupt Status */
-#define BITP_PWM_ILAT_TMR0PER                16                               /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP1                   1                               /* TRIP1 Interrupt Latched Status */
-#define BITP_PWM_ILAT_TRIP0                   0                               /* TRIP0 Interrupt Latched Status */
-
-#define BITM_PWM_ILAT_TMR4PER                (_ADI_MSK(0x00100000,uint32_t))  /* PWMTMR4 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER4_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR4PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER4_INTHI             (_ADI_MSK(0x00100000,uint32_t))  /* TMR4PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR3PER                (_ADI_MSK(0x00080000,uint32_t))  /* PWMTMR3 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER3_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR3PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER3_INTHI             (_ADI_MSK(0x00080000,uint32_t))  /* TMR3PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR2PER                (_ADI_MSK(0x00040000,uint32_t))  /* PWMTMR2 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER2_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR2PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER2_INTHI             (_ADI_MSK(0x00040000,uint32_t))  /* TMR2PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR1PER                (_ADI_MSK(0x00020000,uint32_t))  /* PWMTMR1 Period Latched Interrupt Status */
-#define ENUM_PWM_ILAT_PER1_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR1PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER1_INTHI             (_ADI_MSK(0x00020000,uint32_t))  /* TMR1PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TMR0PER                (_ADI_MSK(0x00010000,uint32_t))  /* PWMTMR0 Period Boundary Interrupt Latched Status */
-#define ENUM_PWM_ILAT_PER0_INTLO             (_ADI_MSK(0x00000000,uint32_t))  /* TMR0PER: No Interrupt Latched */
-#define ENUM_PWM_ILAT_PER0_INTHI             (_ADI_MSK(0x00010000,uint32_t))  /* TMR0PER: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP1                  (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP1_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP1: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP1_INTHI            (_ADI_MSK(0x00000002,uint32_t))  /* TRIP1: Interrupt Latched */
-
-#define BITM_PWM_ILAT_TRIP0                  (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0 Interrupt Latched Status */
-#define ENUM_PWM_ILAT_TRIP0_INTLO            (_ADI_MSK(0x00000000,uint32_t))  /* TRIP0: No Interrupt Latched */
-#define ENUM_PWM_ILAT_TRIP0_INTHI            (_ADI_MSK(0x00000001,uint32_t))  /* TRIP0: Interrupt Latched */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CHOPCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CHOPCFG_VALUE                0                               /* Gate Chopping Divisor */
-#define BITM_PWM_CHOPCFG_VALUE               (_ADI_MSK(0x000000FF,uint32_t))  /* Gate Chopping Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DT_VALUE                     0                               /* Dead Time */
-#define BITM_PWM_DT_VALUE                    (_ADI_MSK(0x000003FF,uint32_t))  /* Dead Time */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_SYNC_WID                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_SYNC_WID_VALUE               0                               /* Sync Pulse Width */
-#define BITM_PWM_SYNC_WID_VALUE              (_ADI_MSK(0x000003FF,uint32_t))  /* Sync Pulse Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM0_VALUE                    0                               /* Timer PWMTMR0 Period Value */
-#define BITM_PWM_TM0_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR0 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM1_VALUE                    0                               /* Timer PWMTMR1 Period Value */
-#define BITM_PWM_TM1_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR1 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM2_VALUE                    0                               /* Timer PWMTMR2 Period Value */
-#define BITM_PWM_TM2_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR2 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM3                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM3_VALUE                    0                               /* Timer PWMTMR3 Period Value */
-#define BITM_PWM_TM3_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR3 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_TM4                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_TM4_VALUE                    0                               /* Timer PWMTMR4 Period Value */
-#define BITM_PWM_TM4_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Timer PWMTMR4 Period Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYA                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYA_VALUE                   0                               /* Channel A Delay Value */
-#define BITM_PWM_DLYA_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel A Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYB                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYB_VALUE                   0                               /* Channel B Delay Value */
-#define BITM_PWM_DLYB_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel B Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYC                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYC_VALUE                   0                               /* Channel C Delay Value */
-#define BITM_PWM_DLYC_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel C Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DLYD                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DLYD_VALUE                   0                               /* Channel D Delay Value */
-#define BITM_PWM_DLYD_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Channel D Delay Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_ACTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_ACTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_ACTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_ACTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_ACTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_ACTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-#define BITM_PWM_ACTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define ENUM_PWM_SYM_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODELO: Symmetrical */
-#define ENUM_PWM_ASYM_LO                     (_ADI_MSK(0x00000400,uint32_t))  /* PULSEMODELO: Asymmetrical */
-#define ENUM_PWM_LEFT_LO                     (_ADI_MSK(0x00000800,uint32_t))  /* PULSEMODELO: Left Half */
-#define ENUM_PWM_RIGHT_LO                    (_ADI_MSK(0x00000C00,uint32_t))  /* PULSEMODELO: Right Half */
-
-#define BITM_PWM_ACTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define ENUM_PWM_SYM_HI                      (_ADI_MSK(0x00000000,uint32_t))  /* PULSEMODEHI: Symmetrical */
-#define ENUM_PWM_ASYM_HI                     (_ADI_MSK(0x00000100,uint32_t))  /* PULSEMODEHI: Asymmetrical */
-#define ENUM_PWM_LEFT_HI                     (_ADI_MSK(0x00000200,uint32_t))  /* PULSEMODEHI: Left Half */
-#define ENUM_PWM_RIGHT_HI                    (_ADI_MSK(0x00000300,uint32_t))  /* PULSEMODEHI: Right Half */
-
-#define BITM_PWM_ACTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define ENUM_PWM_XOVR_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* XOVR: Disable Crossover */
-#define ENUM_PWM_XOVR_EN                     (_ADI_MSK(0x00000004,uint32_t))  /* XOVR: Enable Crossover */
-
-#define BITM_PWM_ACTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define ENUM_PWM_LO_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISLO: Disable Low Side Output */
-#define ENUM_PWM_LO_EN                       (_ADI_MSK(0x00000002,uint32_t))  /* DISLO: Enable Low Side Output */
-
-#define BITM_PWM_ACTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-#define ENUM_PWM_HI_DIS                      (_ADI_MSK(0x00000000,uint32_t))  /* DISHI: Disable High Side Output */
-#define ENUM_PWM_HI_EN                       (_ADI_MSK(0x00000001,uint32_t))  /* DISHI: Enable High Side Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_AL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_AL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_AL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_AL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_BCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_BCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_BCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_BCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_BCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_BCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_BCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_BCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_BCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_BCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_BL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_BL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_BL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_BL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_CCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_CCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_CCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_CCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_CCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_CCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_CCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_CCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_CCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_CCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_CL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_CL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_CL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_CL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DCTL_PULSEMODELO            10                               /* Low Side Output Pulse Position */
-#define BITP_PWM_DCTL_PULSEMODEHI             8                               /* High Side Output Pulse Position */
-#define BITP_PWM_DCTL_XOVR                    2                               /* high-low Crossover Enable */
-#define BITP_PWM_DCTL_DISLO                   1                               /* Channel Low Side Output Disable */
-#define BITP_PWM_DCTL_DISHI                   0                               /* Channel High Side Output Disable */
-
-/* The fields and enumerations for PWM_DCTL are also in PWM - see the common set of ENUM_PWM_* #defines located with register PWM_ACTL */
-
-#define BITM_PWM_DCTL_PULSEMODELO            (_ADI_MSK(0x00000C00,uint32_t))  /* Low Side Output Pulse Position */
-#define BITM_PWM_DCTL_PULSEMODEHI            (_ADI_MSK(0x00000300,uint32_t))  /* High Side Output Pulse Position */
-#define BITM_PWM_DCTL_XOVR                   (_ADI_MSK(0x00000004,uint32_t))  /* high-low Crossover Enable */
-#define BITM_PWM_DCTL_DISLO                  (_ADI_MSK(0x00000002,uint32_t))  /* Channel Low Side Output Disable */
-#define BITM_PWM_DCTL_DISHI                  (_ADI_MSK(0x00000001,uint32_t))  /* Channel High Side Output Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DH0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DH1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DH1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DH1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL0_DUTY                     0                               /* Duty Cycle Asserted Count */
-#define BITM_PWM_DL0_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle Asserted Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        PWM_DL1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PWM_DL1_DUTY                     0                               /* Duty Cycle De-Asserted Count */
-#define BITM_PWM_DL1_DUTY                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Duty Cycle De-Asserted Count */
-
-/* ==================================================
-        Video Subsystem Registers Registers
-   ================================================== */
-
-/* =========================
-        VID0
-   ========================= */
-#define REG_VID0_CONN                   0xFFC1D000         /* VID0 Video Subsystem Connect Register */
-
-/* =========================
-        VID
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        VID_CONN                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_VID_CONN_PPI2BCAST              23                               /* PPI_2 Broadcast Mode */
-#define BITP_VID_CONN_PPI1BCAST              22                               /* PPI_1 Broadcast Mode */
-#define BITP_VID_CONN_PPI0BCAST              21                               /* PPI_0 Broadcast Mode */
-#define BITP_VID_CONN_PPI2TX                 16                               /* PPI_2_TX Connectivity */
-#define BITP_VID_CONN_PPI1TX                 12                               /* PPI_1_TX Connectivity */
-#define BITP_VID_CONN_PPI0TX                  8                               /* PPI_0_TX Connectivity */
-#define BITP_VID_CONN_PVP0IN                  4                               /* PVP_IN Connectivity */
-#define BITP_VID_CONN_PIXC0IN                 0                               /* PIXC_IN Connectivity */
-#define BITM_VID_CONN_PPI2BCAST              (_ADI_MSK(0x00800000,uint32_t))  /* PPI_2 Broadcast Mode */
-#define BITM_VID_CONN_PPI1BCAST              (_ADI_MSK(0x00400000,uint32_t))  /* PPI_1 Broadcast Mode */
-#define BITM_VID_CONN_PPI0BCAST              (_ADI_MSK(0x00200000,uint32_t))  /* PPI_0 Broadcast Mode */
-#define BITM_VID_CONN_PPI2TX                 (_ADI_MSK(0x000F0000,uint32_t))  /* PPI_2_TX Connectivity */
-#define BITM_VID_CONN_PPI1TX                 (_ADI_MSK(0x0000F000,uint32_t))  /* PPI_1_TX Connectivity */
-#define BITM_VID_CONN_PPI0TX                 (_ADI_MSK(0x00000F00,uint32_t))  /* PPI_0_TX Connectivity */
-#define BITM_VID_CONN_PVP0IN                 (_ADI_MSK(0x000000F0,uint32_t))  /* PVP_IN Connectivity */
-#define BITM_VID_CONN_PIXC0IN                (_ADI_MSK(0x0000000F,uint32_t))  /* PIXC_IN Connectivity */
-
-/* ==================================================
-        System Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        SWU0
-   ========================= */
-#define REG_SWU0_GCTL                   0xFFC1E000         /* SWU0 Global Control Register */
-#define REG_SWU0_GSTAT                  0xFFC1E004         /* SWU0 Global Status Register */
-#define REG_SWU0_CTL0                   0xFFC1E010         /* SWU0 Control Register n */
-#define REG_SWU0_CTL1                   0xFFC1E030         /* SWU0 Control Register n */
-#define REG_SWU0_CTL2                   0xFFC1E050         /* SWU0 Control Register n */
-#define REG_SWU0_CTL3                   0xFFC1E070         /* SWU0 Control Register n */
-#define REG_SWU0_LA0                    0xFFC1E014         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA1                    0xFFC1E034         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA2                    0xFFC1E054         /* SWU0 Lower Address Register n */
-#define REG_SWU0_LA3                    0xFFC1E074         /* SWU0 Lower Address Register n */
-#define REG_SWU0_UA0                    0xFFC1E018         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA1                    0xFFC1E038         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA2                    0xFFC1E058         /* SWU0 Upper Address Register n */
-#define REG_SWU0_UA3                    0xFFC1E078         /* SWU0 Upper Address Register n */
-#define REG_SWU0_ID0                    0xFFC1E01C         /* SWU0 ID Register n */
-#define REG_SWU0_ID1                    0xFFC1E03C         /* SWU0 ID Register n */
-#define REG_SWU0_ID2                    0xFFC1E05C         /* SWU0 ID Register n */
-#define REG_SWU0_ID3                    0xFFC1E07C         /* SWU0 ID Register n */
-#define REG_SWU0_CNT0                   0xFFC1E020         /* SWU0 Count Register n */
-#define REG_SWU0_CNT1                   0xFFC1E040         /* SWU0 Count Register n */
-#define REG_SWU0_CNT2                   0xFFC1E060         /* SWU0 Count Register n */
-#define REG_SWU0_CNT3                   0xFFC1E080         /* SWU0 Count Register n */
-#define REG_SWU0_TARG0                  0xFFC1E024         /* SWU0 Target Register n */
-#define REG_SWU0_TARG1                  0xFFC1E044         /* SWU0 Target Register n */
-#define REG_SWU0_TARG2                  0xFFC1E064         /* SWU0 Target Register n */
-#define REG_SWU0_TARG3                  0xFFC1E084         /* SWU0 Target Register n */
-#define REG_SWU0_HIST0                  0xFFC1E028         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST1                  0xFFC1E048         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST2                  0xFFC1E068         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_HIST3                  0xFFC1E088         /* SWU0 Bandwidth History Register n */
-#define REG_SWU0_CUR0                   0xFFC1E02C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR1                   0xFFC1E04C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR2                   0xFFC1E06C         /* SWU0 Current Register n */
-#define REG_SWU0_CUR3                   0xFFC1E08C         /* SWU0 Current Register n */
-
-/* =========================
-        SWU1
-   ========================= */
-#define REG_SWU1_GCTL                   0xFFCAB000         /* SWU1 Global Control Register */
-#define REG_SWU1_GSTAT                  0xFFCAB004         /* SWU1 Global Status Register */
-#define REG_SWU1_CTL0                   0xFFCAB010         /* SWU1 Control Register n */
-#define REG_SWU1_CTL1                   0xFFCAB030         /* SWU1 Control Register n */
-#define REG_SWU1_CTL2                   0xFFCAB050         /* SWU1 Control Register n */
-#define REG_SWU1_CTL3                   0xFFCAB070         /* SWU1 Control Register n */
-#define REG_SWU1_LA0                    0xFFCAB014         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA1                    0xFFCAB034         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA2                    0xFFCAB054         /* SWU1 Lower Address Register n */
-#define REG_SWU1_LA3                    0xFFCAB074         /* SWU1 Lower Address Register n */
-#define REG_SWU1_UA0                    0xFFCAB018         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA1                    0xFFCAB038         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA2                    0xFFCAB058         /* SWU1 Upper Address Register n */
-#define REG_SWU1_UA3                    0xFFCAB078         /* SWU1 Upper Address Register n */
-#define REG_SWU1_ID0                    0xFFCAB01C         /* SWU1 ID Register n */
-#define REG_SWU1_ID1                    0xFFCAB03C         /* SWU1 ID Register n */
-#define REG_SWU1_ID2                    0xFFCAB05C         /* SWU1 ID Register n */
-#define REG_SWU1_ID3                    0xFFCAB07C         /* SWU1 ID Register n */
-#define REG_SWU1_CNT0                   0xFFCAB020         /* SWU1 Count Register n */
-#define REG_SWU1_CNT1                   0xFFCAB040         /* SWU1 Count Register n */
-#define REG_SWU1_CNT2                   0xFFCAB060         /* SWU1 Count Register n */
-#define REG_SWU1_CNT3                   0xFFCAB080         /* SWU1 Count Register n */
-#define REG_SWU1_TARG0                  0xFFCAB024         /* SWU1 Target Register n */
-#define REG_SWU1_TARG1                  0xFFCAB044         /* SWU1 Target Register n */
-#define REG_SWU1_TARG2                  0xFFCAB064         /* SWU1 Target Register n */
-#define REG_SWU1_TARG3                  0xFFCAB084         /* SWU1 Target Register n */
-#define REG_SWU1_HIST0                  0xFFCAB028         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST1                  0xFFCAB048         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST2                  0xFFCAB068         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_HIST3                  0xFFCAB088         /* SWU1 Bandwidth History Register n */
-#define REG_SWU1_CUR0                   0xFFCAB02C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR1                   0xFFCAB04C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR2                   0xFFCAB06C         /* SWU1 Current Register n */
-#define REG_SWU1_CUR3                   0xFFCAB08C         /* SWU1 Current Register n */
-
-/* =========================
-        SWU2
-   ========================= */
-#define REG_SWU2_GCTL                   0xFFCAC000         /* SWU2 Global Control Register */
-#define REG_SWU2_GSTAT                  0xFFCAC004         /* SWU2 Global Status Register */
-#define REG_SWU2_CTL0                   0xFFCAC010         /* SWU2 Control Register n */
-#define REG_SWU2_CTL1                   0xFFCAC030         /* SWU2 Control Register n */
-#define REG_SWU2_CTL2                   0xFFCAC050         /* SWU2 Control Register n */
-#define REG_SWU2_CTL3                   0xFFCAC070         /* SWU2 Control Register n */
-#define REG_SWU2_LA0                    0xFFCAC014         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA1                    0xFFCAC034         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA2                    0xFFCAC054         /* SWU2 Lower Address Register n */
-#define REG_SWU2_LA3                    0xFFCAC074         /* SWU2 Lower Address Register n */
-#define REG_SWU2_UA0                    0xFFCAC018         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA1                    0xFFCAC038         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA2                    0xFFCAC058         /* SWU2 Upper Address Register n */
-#define REG_SWU2_UA3                    0xFFCAC078         /* SWU2 Upper Address Register n */
-#define REG_SWU2_ID0                    0xFFCAC01C         /* SWU2 ID Register n */
-#define REG_SWU2_ID1                    0xFFCAC03C         /* SWU2 ID Register n */
-#define REG_SWU2_ID2                    0xFFCAC05C         /* SWU2 ID Register n */
-#define REG_SWU2_ID3                    0xFFCAC07C         /* SWU2 ID Register n */
-#define REG_SWU2_CNT0                   0xFFCAC020         /* SWU2 Count Register n */
-#define REG_SWU2_CNT1                   0xFFCAC040         /* SWU2 Count Register n */
-#define REG_SWU2_CNT2                   0xFFCAC060         /* SWU2 Count Register n */
-#define REG_SWU2_CNT3                   0xFFCAC080         /* SWU2 Count Register n */
-#define REG_SWU2_TARG0                  0xFFCAC024         /* SWU2 Target Register n */
-#define REG_SWU2_TARG1                  0xFFCAC044         /* SWU2 Target Register n */
-#define REG_SWU2_TARG2                  0xFFCAC064         /* SWU2 Target Register n */
-#define REG_SWU2_TARG3                  0xFFCAC084         /* SWU2 Target Register n */
-#define REG_SWU2_HIST0                  0xFFCAC028         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST1                  0xFFCAC048         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST2                  0xFFCAC068         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_HIST3                  0xFFCAC088         /* SWU2 Bandwidth History Register n */
-#define REG_SWU2_CUR0                   0xFFCAC02C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR1                   0xFFCAC04C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR2                   0xFFCAC06C         /* SWU2 Current Register n */
-#define REG_SWU2_CUR3                   0xFFCAC08C         /* SWU2 Current Register n */
-
-/* =========================
-        SWU3
-   ========================= */
-#define REG_SWU3_GCTL                   0xFFCAD000         /* SWU3 Global Control Register */
-#define REG_SWU3_GSTAT                  0xFFCAD004         /* SWU3 Global Status Register */
-#define REG_SWU3_CTL0                   0xFFCAD010         /* SWU3 Control Register n */
-#define REG_SWU3_CTL1                   0xFFCAD030         /* SWU3 Control Register n */
-#define REG_SWU3_CTL2                   0xFFCAD050         /* SWU3 Control Register n */
-#define REG_SWU3_CTL3                   0xFFCAD070         /* SWU3 Control Register n */
-#define REG_SWU3_LA0                    0xFFCAD014         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA1                    0xFFCAD034         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA2                    0xFFCAD054         /* SWU3 Lower Address Register n */
-#define REG_SWU3_LA3                    0xFFCAD074         /* SWU3 Lower Address Register n */
-#define REG_SWU3_UA0                    0xFFCAD018         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA1                    0xFFCAD038         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA2                    0xFFCAD058         /* SWU3 Upper Address Register n */
-#define REG_SWU3_UA3                    0xFFCAD078         /* SWU3 Upper Address Register n */
-#define REG_SWU3_ID0                    0xFFCAD01C         /* SWU3 ID Register n */
-#define REG_SWU3_ID1                    0xFFCAD03C         /* SWU3 ID Register n */
-#define REG_SWU3_ID2                    0xFFCAD05C         /* SWU3 ID Register n */
-#define REG_SWU3_ID3                    0xFFCAD07C         /* SWU3 ID Register n */
-#define REG_SWU3_CNT0                   0xFFCAD020         /* SWU3 Count Register n */
-#define REG_SWU3_CNT1                   0xFFCAD040         /* SWU3 Count Register n */
-#define REG_SWU3_CNT2                   0xFFCAD060         /* SWU3 Count Register n */
-#define REG_SWU3_CNT3                   0xFFCAD080         /* SWU3 Count Register n */
-#define REG_SWU3_TARG0                  0xFFCAD024         /* SWU3 Target Register n */
-#define REG_SWU3_TARG1                  0xFFCAD044         /* SWU3 Target Register n */
-#define REG_SWU3_TARG2                  0xFFCAD064         /* SWU3 Target Register n */
-#define REG_SWU3_TARG3                  0xFFCAD084         /* SWU3 Target Register n */
-#define REG_SWU3_HIST0                  0xFFCAD028         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST1                  0xFFCAD048         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST2                  0xFFCAD068         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_HIST3                  0xFFCAD088         /* SWU3 Bandwidth History Register n */
-#define REG_SWU3_CUR0                   0xFFCAD02C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR1                   0xFFCAD04C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR2                   0xFFCAD06C         /* SWU3 Current Register n */
-#define REG_SWU3_CUR3                   0xFFCAD08C         /* SWU3 Current Register n */
-
-/* =========================
-        SWU4
-   ========================= */
-#define REG_SWU4_GCTL                   0xFFCAE000         /* SWU4 Global Control Register */
-#define REG_SWU4_GSTAT                  0xFFCAE004         /* SWU4 Global Status Register */
-#define REG_SWU4_CTL0                   0xFFCAE010         /* SWU4 Control Register n */
-#define REG_SWU4_CTL1                   0xFFCAE030         /* SWU4 Control Register n */
-#define REG_SWU4_CTL2                   0xFFCAE050         /* SWU4 Control Register n */
-#define REG_SWU4_CTL3                   0xFFCAE070         /* SWU4 Control Register n */
-#define REG_SWU4_LA0                    0xFFCAE014         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA1                    0xFFCAE034         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA2                    0xFFCAE054         /* SWU4 Lower Address Register n */
-#define REG_SWU4_LA3                    0xFFCAE074         /* SWU4 Lower Address Register n */
-#define REG_SWU4_UA0                    0xFFCAE018         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA1                    0xFFCAE038         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA2                    0xFFCAE058         /* SWU4 Upper Address Register n */
-#define REG_SWU4_UA3                    0xFFCAE078         /* SWU4 Upper Address Register n */
-#define REG_SWU4_ID0                    0xFFCAE01C         /* SWU4 ID Register n */
-#define REG_SWU4_ID1                    0xFFCAE03C         /* SWU4 ID Register n */
-#define REG_SWU4_ID2                    0xFFCAE05C         /* SWU4 ID Register n */
-#define REG_SWU4_ID3                    0xFFCAE07C         /* SWU4 ID Register n */
-#define REG_SWU4_CNT0                   0xFFCAE020         /* SWU4 Count Register n */
-#define REG_SWU4_CNT1                   0xFFCAE040         /* SWU4 Count Register n */
-#define REG_SWU4_CNT2                   0xFFCAE060         /* SWU4 Count Register n */
-#define REG_SWU4_CNT3                   0xFFCAE080         /* SWU4 Count Register n */
-#define REG_SWU4_TARG0                  0xFFCAE024         /* SWU4 Target Register n */
-#define REG_SWU4_TARG1                  0xFFCAE044         /* SWU4 Target Register n */
-#define REG_SWU4_TARG2                  0xFFCAE064         /* SWU4 Target Register n */
-#define REG_SWU4_TARG3                  0xFFCAE084         /* SWU4 Target Register n */
-#define REG_SWU4_HIST0                  0xFFCAE028         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST1                  0xFFCAE048         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST2                  0xFFCAE068         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_HIST3                  0xFFCAE088         /* SWU4 Bandwidth History Register n */
-#define REG_SWU4_CUR0                   0xFFCAE02C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR1                   0xFFCAE04C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR2                   0xFFCAE06C         /* SWU4 Current Register n */
-#define REG_SWU4_CUR3                   0xFFCAE08C         /* SWU4 Current Register n */
-
-/* =========================
-        SWU5
-   ========================= */
-#define REG_SWU5_GCTL                   0xFFCAF000         /* SWU5 Global Control Register */
-#define REG_SWU5_GSTAT                  0xFFCAF004         /* SWU5 Global Status Register */
-#define REG_SWU5_CTL0                   0xFFCAF010         /* SWU5 Control Register n */
-#define REG_SWU5_CTL1                   0xFFCAF030         /* SWU5 Control Register n */
-#define REG_SWU5_CTL2                   0xFFCAF050         /* SWU5 Control Register n */
-#define REG_SWU5_CTL3                   0xFFCAF070         /* SWU5 Control Register n */
-#define REG_SWU5_LA0                    0xFFCAF014         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA1                    0xFFCAF034         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA2                    0xFFCAF054         /* SWU5 Lower Address Register n */
-#define REG_SWU5_LA3                    0xFFCAF074         /* SWU5 Lower Address Register n */
-#define REG_SWU5_UA0                    0xFFCAF018         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA1                    0xFFCAF038         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA2                    0xFFCAF058         /* SWU5 Upper Address Register n */
-#define REG_SWU5_UA3                    0xFFCAF078         /* SWU5 Upper Address Register n */
-#define REG_SWU5_ID0                    0xFFCAF01C         /* SWU5 ID Register n */
-#define REG_SWU5_ID1                    0xFFCAF03C         /* SWU5 ID Register n */
-#define REG_SWU5_ID2                    0xFFCAF05C         /* SWU5 ID Register n */
-#define REG_SWU5_ID3                    0xFFCAF07C         /* SWU5 ID Register n */
-#define REG_SWU5_CNT0                   0xFFCAF020         /* SWU5 Count Register n */
-#define REG_SWU5_CNT1                   0xFFCAF040         /* SWU5 Count Register n */
-#define REG_SWU5_CNT2                   0xFFCAF060         /* SWU5 Count Register n */
-#define REG_SWU5_CNT3                   0xFFCAF080         /* SWU5 Count Register n */
-#define REG_SWU5_TARG0                  0xFFCAF024         /* SWU5 Target Register n */
-#define REG_SWU5_TARG1                  0xFFCAF044         /* SWU5 Target Register n */
-#define REG_SWU5_TARG2                  0xFFCAF064         /* SWU5 Target Register n */
-#define REG_SWU5_TARG3                  0xFFCAF084         /* SWU5 Target Register n */
-#define REG_SWU5_HIST0                  0xFFCAF028         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST1                  0xFFCAF048         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST2                  0xFFCAF068         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_HIST3                  0xFFCAF088         /* SWU5 Bandwidth History Register n */
-#define REG_SWU5_CUR0                   0xFFCAF02C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR1                   0xFFCAF04C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR2                   0xFFCAF06C         /* SWU5 Current Register n */
-#define REG_SWU5_CUR3                   0xFFCAF08C         /* SWU5 Current Register n */
-
-/* =========================
-        SWU6
-   ========================= */
-#define REG_SWU6_GCTL                   0xFFC82000         /* SWU6 Global Control Register */
-#define REG_SWU6_GSTAT                  0xFFC82004         /* SWU6 Global Status Register */
-#define REG_SWU6_CTL0                   0xFFC82010         /* SWU6 Control Register n */
-#define REG_SWU6_CTL1                   0xFFC82030         /* SWU6 Control Register n */
-#define REG_SWU6_CTL2                   0xFFC82050         /* SWU6 Control Register n */
-#define REG_SWU6_CTL3                   0xFFC82070         /* SWU6 Control Register n */
-#define REG_SWU6_LA0                    0xFFC82014         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA1                    0xFFC82034         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA2                    0xFFC82054         /* SWU6 Lower Address Register n */
-#define REG_SWU6_LA3                    0xFFC82074         /* SWU6 Lower Address Register n */
-#define REG_SWU6_UA0                    0xFFC82018         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA1                    0xFFC82038         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA2                    0xFFC82058         /* SWU6 Upper Address Register n */
-#define REG_SWU6_UA3                    0xFFC82078         /* SWU6 Upper Address Register n */
-#define REG_SWU6_ID0                    0xFFC8201C         /* SWU6 ID Register n */
-#define REG_SWU6_ID1                    0xFFC8203C         /* SWU6 ID Register n */
-#define REG_SWU6_ID2                    0xFFC8205C         /* SWU6 ID Register n */
-#define REG_SWU6_ID3                    0xFFC8207C         /* SWU6 ID Register n */
-#define REG_SWU6_CNT0                   0xFFC82020         /* SWU6 Count Register n */
-#define REG_SWU6_CNT1                   0xFFC82040         /* SWU6 Count Register n */
-#define REG_SWU6_CNT2                   0xFFC82060         /* SWU6 Count Register n */
-#define REG_SWU6_CNT3                   0xFFC82080         /* SWU6 Count Register n */
-#define REG_SWU6_TARG0                  0xFFC82024         /* SWU6 Target Register n */
-#define REG_SWU6_TARG1                  0xFFC82044         /* SWU6 Target Register n */
-#define REG_SWU6_TARG2                  0xFFC82064         /* SWU6 Target Register n */
-#define REG_SWU6_TARG3                  0xFFC82084         /* SWU6 Target Register n */
-#define REG_SWU6_HIST0                  0xFFC82028         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST1                  0xFFC82048         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST2                  0xFFC82068         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_HIST3                  0xFFC82088         /* SWU6 Bandwidth History Register n */
-#define REG_SWU6_CUR0                   0xFFC8202C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR1                   0xFFC8204C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR2                   0xFFC8206C         /* SWU6 Current Register n */
-#define REG_SWU6_CUR3                   0xFFC8208C         /* SWU6 Current Register n */
-
-/* =========================
-        SWU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GCTL_RST                     1                               /* Global Reset */
-#define BITP_SWU_GCTL_EN                      0                               /* Global Enable */
-#define BITM_SWU_GCTL_RST                    (_ADI_MSK(0x00000002,uint32_t))  /* Global Reset */
-#define BITM_SWU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Global Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_GSTAT_ADDRERR               30                               /* Address Error Status */
-#define BITP_SWU_GSTAT_OVRBW3                15                               /* Group 3 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW3               14                               /* Group 3 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW2                13                               /* Group 2 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW2               12                               /* Group 2 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW1                11                               /* Group 1 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW1               10                               /* Group 1 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_OVRBW0                 9                               /* Group 0 Bandwidth Above Maximum Target */
-#define BITP_SWU_GSTAT_UNDRBW0                8                               /* Group 0 Bandwidth Below Minimum Target */
-#define BITP_SWU_GSTAT_INT3                   7                               /* Group 3 Interrupt Status */
-#define BITP_SWU_GSTAT_INT2                   6                               /* Group 2 Interrupt Status */
-#define BITP_SWU_GSTAT_INT1                   5                               /* Group 1 Interrupt Status */
-#define BITP_SWU_GSTAT_INT0                   4                               /* Group 0 Interrupt Status */
-#define BITP_SWU_GSTAT_MTCH3                  3                               /* Group 3 Match */
-#define BITP_SWU_GSTAT_MTCH2                  2                               /* Group 2 Match */
-#define BITP_SWU_GSTAT_MTCH1                  1                               /* Group 1 Match */
-#define BITP_SWU_GSTAT_MTCH0                  0                               /* Group 0 Match */
-#define BITM_SWU_GSTAT_ADDRERR               (_ADI_MSK(0x40000000,uint32_t))  /* Address Error Status */
-#define BITM_SWU_GSTAT_OVRBW3                (_ADI_MSK(0x00008000,uint32_t))  /* Group 3 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW3               (_ADI_MSK(0x00004000,uint32_t))  /* Group 3 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW2                (_ADI_MSK(0x00002000,uint32_t))  /* Group 2 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW2               (_ADI_MSK(0x00001000,uint32_t))  /* Group 2 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW1                (_ADI_MSK(0x00000800,uint32_t))  /* Group 1 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW1               (_ADI_MSK(0x00000400,uint32_t))  /* Group 1 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_OVRBW0                (_ADI_MSK(0x00000200,uint32_t))  /* Group 0 Bandwidth Above Maximum Target */
-#define BITM_SWU_GSTAT_UNDRBW0               (_ADI_MSK(0x00000100,uint32_t))  /* Group 0 Bandwidth Below Minimum Target */
-#define BITM_SWU_GSTAT_INT3                  (_ADI_MSK(0x00000080,uint32_t))  /* Group 3 Interrupt Status */
-#define BITM_SWU_GSTAT_INT2                  (_ADI_MSK(0x00000040,uint32_t))  /* Group 2 Interrupt Status */
-#define BITM_SWU_GSTAT_INT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Group 1 Interrupt Status */
-#define BITM_SWU_GSTAT_INT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Group 0 Interrupt Status */
-#define BITM_SWU_GSTAT_MTCH3                 (_ADI_MSK(0x00000008,uint32_t))  /* Group 3 Match */
-#define BITM_SWU_GSTAT_MTCH2                 (_ADI_MSK(0x00000004,uint32_t))  /* Group 2 Match */
-#define BITM_SWU_GSTAT_MTCH1                 (_ADI_MSK(0x00000002,uint32_t))  /* Group 1 Match */
-#define BITM_SWU_GSTAT_MTCH0                 (_ADI_MSK(0x00000001,uint32_t))  /* Group 0 Match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CTL_MAXACT                  19                               /* Action for Bandwidth Above Maximum */
-#define BITP_SWU_CTL_MINACT                  18                               /* Action for Bandwidth Below Minimum */
-#define BITP_SWU_CTL_BLENINC                 17                               /* Increment Bandwidth Count by Burst Length */
-#define BITP_SWU_CTL_BWEN                    16                               /* Bandwidth Mode Enable */
-#define BITP_SWU_CTL_TMEN                    15                               /* Trace Message Enable */
-#define BITP_SWU_CTL_TRGEN                   14                               /* Trigger Enable */
-#define BITP_SWU_CTL_INTEN                   13                               /* Interrupt Enable */
-#define BITP_SWU_CTL_DBGEN                   12                               /* Debug Event Enable */
-#define BITP_SWU_CTL_CNTRPTEN                 9                               /* Count Repeat Enable */
-#define BITP_SWU_CTL_CNTEN                    8                               /* Count Enable */
-#define BITP_SWU_CTL_LCMPEN                   6                               /* Locked Comparison Enable */
-#define BITP_SWU_CTL_SCMPEN                   5                               /* Secure Comparison Enable */
-#define BITP_SWU_CTL_IDCMPEN                  4                               /* ID Comparison Enable */
-#define BITP_SWU_CTL_ACMPM                    2                               /* Address Comparison Mode */
-#define BITP_SWU_CTL_DIR                      1                               /* Transaction Direction for Match */
-#define BITP_SWU_CTL_EN                       0                               /* Enable Watchpoint */
-#define BITM_SWU_CTL_MAXACT                  (_ADI_MSK(0x00080000,uint32_t))  /* Action for Bandwidth Above Maximum */
-#define BITM_SWU_CTL_MINACT                  (_ADI_MSK(0x00040000,uint32_t))  /* Action for Bandwidth Below Minimum */
-#define BITM_SWU_CTL_BLENINC                 (_ADI_MSK(0x00020000,uint32_t))  /* Increment Bandwidth Count by Burst Length */
-#define BITM_SWU_CTL_BWEN                    (_ADI_MSK(0x00010000,uint32_t))  /* Bandwidth Mode Enable */
-#define BITM_SWU_CTL_TMEN                    (_ADI_MSK(0x00008000,uint32_t))  /* Trace Message Enable */
-#define BITM_SWU_CTL_TRGEN                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Enable */
-#define BITM_SWU_CTL_INTEN                   (_ADI_MSK(0x00002000,uint32_t))  /* Interrupt Enable */
-#define BITM_SWU_CTL_DBGEN                   (_ADI_MSK(0x00001000,uint32_t))  /* Debug Event Enable */
-#define BITM_SWU_CTL_CNTRPTEN                (_ADI_MSK(0x00000200,uint32_t))  /* Count Repeat Enable */
-#define BITM_SWU_CTL_CNTEN                   (_ADI_MSK(0x00000100,uint32_t))  /* Count Enable */
-#define BITM_SWU_CTL_LCMPEN                  (_ADI_MSK(0x00000040,uint32_t))  /* Locked Comparison Enable */
-#define BITM_SWU_CTL_SCMPEN                  (_ADI_MSK(0x00000020,uint32_t))  /* Secure Comparison Enable */
-#define BITM_SWU_CTL_IDCMPEN                 (_ADI_MSK(0x00000010,uint32_t))  /* ID Comparison Enable */
-#define BITM_SWU_CTL_ACMPM                   (_ADI_MSK(0x0000000C,uint32_t))  /* Address Comparison Mode */
-#define BITM_SWU_CTL_DIR                     (_ADI_MSK(0x00000002,uint32_t))  /* Transaction Direction for Match */
-#define BITM_SWU_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable Watchpoint */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_ID                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_ID_IDMASK                   16                               /* Identity Mask (for Or with ID) */
-#define BITP_SWU_ID_ID                        0                               /* Identity */
-#define BITM_SWU_ID_IDMASK                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Identity Mask (for Or with ID) */
-#define BITM_SWU_ID_ID                       (_ADI_MSK(0x0000FFFF,uint32_t))  /* Identity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CNT_COUNT                    0                               /* Count */
-#define BITM_SWU_CNT_COUNT                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_TARG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_TARG_BWMAX                  16                               /* Maximum Bandwidth Target */
-#define BITP_SWU_TARG_BWMIN                   0                               /* Minimum Bandwidth Target */
-#define BITM_SWU_TARG_BWMAX                  (_ADI_MSK(0xFFFF0000,uint32_t))  /* Maximum Bandwidth Target */
-#define BITM_SWU_TARG_BWMIN                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Minimum Bandwidth Target */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_HIST                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_HIST_BWHIST1                16                               /* Bandwidth from Window Before Last */
-#define BITP_SWU_HIST_BWHIST0                 0                               /* Bandwidth from Last Window */
-#define BITM_SWU_HIST_BWHIST1                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Bandwidth from Window Before Last */
-#define BITM_SWU_HIST_BWHIST0                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth from Last Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SWU_CUR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SWU_CUR_CURBW                   16                               /* Current Bandwidth */
-#define BITP_SWU_CUR_CURCNT                   0                               /* Current Count */
-#define BITM_SWU_CUR_CURBW                   (_ADI_MSK(0xFFFF0000,uint32_t))  /* Current Bandwidth */
-#define BITM_SWU_CUR_CURCNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Current Count */
-
-/* ==================================================
-        System Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        SDU0
-   ========================= */
-#define REG_SDU0_IDCODE                 0xFFC1F020         /* SDU0 ID Code Register */
-#define REG_SDU0_CTL                    0xFFC1F050         /* SDU0 Control Register */
-#define REG_SDU0_STAT                   0xFFC1F054         /* SDU0 Status Register */
-#define REG_SDU0_MACCTL                 0xFFC1F058         /* SDU0 Memory Access Control Register */
-#define REG_SDU0_MACADDR                0xFFC1F05C         /* SDU0 Memory Access Address Register */
-#define REG_SDU0_MACDATA                0xFFC1F060         /* SDU0 Memory Access Data Register */
-#define REG_SDU0_DMARD                  0xFFC1F064         /* SDU0 DMA Read Data Register */
-#define REG_SDU0_DMAWD                  0xFFC1F068         /* SDU0 DMA Write Data Register */
-#define REG_SDU0_MSG                    0xFFC1F080         /* SDU0 Message Register */
-#define REG_SDU0_MSG_SET                0xFFC1F084         /* SDU0 Message Set Register */
-#define REG_SDU0_MSG_CLR                0xFFC1F088         /* SDU0 Message Clear Register */
-#define REG_SDU0_GHLT                   0xFFC1F08C         /* SDU0 Group Halt Register */
-
-/* =========================
-        SDU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_IDCODE                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_IDCODE_REVID                28                               /* Revision ID */
-#define BITP_SDU_IDCODE_PRID                 12                               /* Product ID */
-#define BITP_SDU_IDCODE_MFID                  1                               /* Manufacturer ID */
-#define BITM_SDU_IDCODE_REVID                (_ADI_MSK(0xF0000000,uint32_t))  /* Revision ID */
-#define BITM_SDU_IDCODE_PRID                 (_ADI_MSK(0x0FFFF000,uint32_t))  /* Product ID */
-#define BITM_SDU_IDCODE_MFID                 (_ADI_MSK(0x00000FFE,uint32_t))  /* Manufacturer ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_CTL_EHLT                     8                               /* Emulator Halt Select */
-#define BITP_SDU_CTL_EMEEN                    4                               /* Emulation Event Enable */
-#define BITP_SDU_CTL_DMAEN                    2                               /* DMA Enable */
-#define BITP_SDU_CTL_CSPEN                    1                               /* Core Scan Path Enable */
-#define BITP_SDU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_SDU_CTL_EHLT                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Emulator Halt Select */
-#define BITM_SDU_CTL_EMEEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Emulation Event Enable */
-#define BITM_SDU_CTL_DMAEN                   (_ADI_MSK(0x00000004,uint32_t))  /* DMA Enable */
-#define BITM_SDU_CTL_CSPEN                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Scan Path Enable */
-#define BITM_SDU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_STAT_CRST                   22                               /* Core Reset */
-#define BITP_SDU_STAT_CHLT                   21                               /* Core Halt */
-#define BITP_SDU_STAT_EME                    20                               /* Emulation Event */
-#define BITP_SDU_STAT_GHLTC                  17                               /* Group Halt Cause */
-#define BITP_SDU_STAT_GHLT                   16                               /* Group Halt */
-#define BITP_SDU_STAT_DMAFIFO                12                               /* DMA FIFO */
-#define BITP_SDU_STAT_ADDRERR                11                               /* Address Error */
-#define BITP_SDU_STAT_DMAWDRDY               10                               /* DMAWD Ready */
-#define BITP_SDU_STAT_DMARDRDY                9                               /* DMARD Ready */
-#define BITP_SDU_STAT_MACRDY                  8                               /* MAC Ready */
-#define BITP_SDU_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_SDU_STAT_SECURE                  3                               /* Secure Mode */
-#define BITP_SDU_STAT_DEEPSLEEP               2                               /* Deep Sleep Mode */
-#define BITP_SDU_STAT_ERR                     1                               /* Error */
-#define BITP_SDU_STAT_SYSRST                  0                               /* System Reset */
-#define BITM_SDU_STAT_CRST                   (_ADI_MSK(0x00400000,uint32_t))  /* Core Reset */
-#define BITM_SDU_STAT_CHLT                   (_ADI_MSK(0x00200000,uint32_t))  /* Core Halt */
-#define BITM_SDU_STAT_EME                    (_ADI_MSK(0x00100000,uint32_t))  /* Emulation Event */
-#define BITM_SDU_STAT_GHLTC                  (_ADI_MSK(0x000E0000,uint32_t))  /* Group Halt Cause */
-#define BITM_SDU_STAT_GHLT                   (_ADI_MSK(0x00010000,uint32_t))  /* Group Halt */
-#define BITM_SDU_STAT_DMAFIFO                (_ADI_MSK(0x00007000,uint32_t))  /* DMA FIFO */
-#define BITM_SDU_STAT_ADDRERR                (_ADI_MSK(0x00000800,uint32_t))  /* Address Error */
-#define BITM_SDU_STAT_DMAWDRDY               (_ADI_MSK(0x00000400,uint32_t))  /* DMAWD Ready */
-#define BITM_SDU_STAT_DMARDRDY               (_ADI_MSK(0x00000200,uint32_t))  /* DMARD Ready */
-#define BITM_SDU_STAT_MACRDY                 (_ADI_MSK(0x00000100,uint32_t))  /* MAC Ready */
-#define BITM_SDU_STAT_ERRC                   (_ADI_MSK(0x000000F0,uint32_t))  /* Error Cause */
-#define BITM_SDU_STAT_SECURE                 (_ADI_MSK(0x00000008,uint32_t))  /* Secure Mode */
-#define BITM_SDU_STAT_DEEPSLEEP              (_ADI_MSK(0x00000004,uint32_t))  /* Deep Sleep Mode */
-#define BITM_SDU_STAT_ERR                    (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define BITM_SDU_STAT_SYSRST                 (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MACCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MACCTL_AUTOINC               4                               /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITP_SDU_MACCTL_RNW                   3                               /* Read Not Write */
-#define BITP_SDU_MACCTL_SIZE                  0                               /* Transfer Data Size */
-#define BITM_SDU_MACCTL_AUTOINC              (_ADI_MSK(0x00000010,uint32_t))  /* Auto (Post) Increment MACADDR (by SIZE) */
-#define BITM_SDU_MACCTL_RNW                  (_ADI_MSK(0x00000008,uint32_t))  /* Read Not Write */
-#define BITM_SDU_MACCTL_SIZE                 (_ADI_MSK(0x00000007,uint32_t))  /* Transfer Data Size */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_MSG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_MSG_CALLERR                 31                               /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITP_SDU_MSG_CALLBACK                30                               /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITP_SDU_MSG_CALLINIT                29                               /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITP_SDU_MSG_CALLAPP                 28                               /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITP_SDU_MSG_HALTONERR               27                               /* Generate an Emulation Exception Prior to an Error Call */
-#define BITP_SDU_MSG_HALTONCALL              26                               /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITP_SDU_MSG_HALTONINIT              25                               /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITP_SDU_MSG_HALTONAPP               24                               /* Generate an Emulation Exception Prior to an Application Call */
-#define BITP_SDU_MSG_L3INIT                  23                               /* Indicates that the L3 Resource is Initialized */
-#define BITP_SDU_MSG_L2INIT                  22                               /* Indicates that the L2 Resource is Initialized */
-#define BITP_SDU_MSG_C1L1INIT                17                               /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITP_SDU_MSG_C0L1INIT                16                               /* Indicates that the Core 0 L1 Resource is Initialized */
-#define BITM_SDU_MSG_CALLERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Error Call */
-#define BITM_SDU_MSG_CALLBACK                (_ADI_MSK(0x40000000,uint32_t))  /* Flag Set by the Boot Code Prior to a Callback Call */
-#define BITM_SDU_MSG_CALLINIT                (_ADI_MSK(0x20000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Initcode Call */
-#define BITM_SDU_MSG_CALLAPP                 (_ADI_MSK(0x10000000,uint32_t))  /* Flag Set by the Boot Code Prior to an Application Call */
-#define BITM_SDU_MSG_HALTONERR               (_ADI_MSK(0x08000000,uint32_t))  /* Generate an Emulation Exception Prior to an Error Call */
-#define BITM_SDU_MSG_HALTONCALL              (_ADI_MSK(0x04000000,uint32_t))  /* Generate an Emulation Exception Prior to a Callback Call */
-#define BITM_SDU_MSG_HALTONINIT              (_ADI_MSK(0x02000000,uint32_t))  /* Generate an Emulation Exception Prior to an Initcode Call */
-#define BITM_SDU_MSG_HALTONAPP               (_ADI_MSK(0x01000000,uint32_t))  /* Generate an Emulation Exception Prior to an Application Call */
-#define BITM_SDU_MSG_L3INIT                  (_ADI_MSK(0x00800000,uint32_t))  /* Indicates that the L3 Resource is Initialized */
-#define BITM_SDU_MSG_L2INIT                  (_ADI_MSK(0x00400000,uint32_t))  /* Indicates that the L2 Resource is Initialized */
-#define BITM_SDU_MSG_C1L1INIT                (_ADI_MSK(0x00020000,uint32_t))  /* Indicates that the Core 1 L1 Resource is Initialized */
-#define BITM_SDU_MSG_C0L1INIT                (_ADI_MSK(0x00010000,uint32_t))  /* Indicates that the Core 0 L1 Resource is Initialized */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SDU_GHLT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SDU_GHLT_SS2                    18                               /* Slave Select 2 */
-#define BITP_SDU_GHLT_SS1                    17                               /* Slave Select 1 */
-#define BITP_SDU_GHLT_SS0                    16                               /* Slave Select 0 */
-#define BITP_SDU_GHLT_MS2                     2                               /* Master Select 2 */
-#define BITP_SDU_GHLT_MS1                     1                               /* Master Select 1 */
-#define BITP_SDU_GHLT_MS0                     0                               /* Master Select 0 */
-#define BITM_SDU_GHLT_SS2                    (_ADI_MSK(0x00040000,uint32_t))  /* Slave Select 2 */
-#define BITM_SDU_GHLT_SS1                    (_ADI_MSK(0x00020000,uint32_t))  /* Slave Select 1 */
-#define BITM_SDU_GHLT_SS0                    (_ADI_MSK(0x00010000,uint32_t))  /* Slave Select 0 */
-#define BITM_SDU_GHLT_MS2                    (_ADI_MSK(0x00000004,uint32_t))  /* Master Select 2 */
-#define BITM_SDU_GHLT_MS1                    (_ADI_MSK(0x00000002,uint32_t))  /* Master Select 1 */
-#define BITM_SDU_GHLT_MS0                    (_ADI_MSK(0x00000001,uint32_t))  /* Master Select 0 */
-
-/* ==================================================
-        Ethernet MAC Registers
-   ================================================== */
-
-/* =========================
-        EMAC0
-   ========================= */
-#define REG_EMAC0_MACCFG                0xFFC20000         /* EMAC0 MAC Configuration Register */
-#define REG_EMAC0_MACFRMFILT            0xFFC20004         /* EMAC0 MAC Rx Frame Filter Register */
-#define REG_EMAC0_HASHTBL_HI            0xFFC20008         /* EMAC0 Hash Table High Register */
-#define REG_EMAC0_HASHTBL_LO            0xFFC2000C         /* EMAC0 Hash Table Low Register */
-#define REG_EMAC0_SMI_ADDR              0xFFC20010         /* EMAC0 SMI Address Register */
-#define REG_EMAC0_SMI_DATA              0xFFC20014         /* EMAC0 SMI Data Register */
-#define REG_EMAC0_FLOWCTL               0xFFC20018         /* EMAC0 FLow Control Register */
-#define REG_EMAC0_VLANTAG               0xFFC2001C         /* EMAC0 VLAN Tag Register */
-#define REG_EMAC0_DBG                   0xFFC20024         /* EMAC0 Debug Register */
-#define REG_EMAC0_ISTAT                 0xFFC20038         /* EMAC0 Interrupt Status Register */
-#define REG_EMAC0_IMSK                  0xFFC2003C         /* EMAC0 Interrupt Mask Register */
-#define REG_EMAC0_ADDR0_HI              0xFFC20040         /* EMAC0 MAC Address 0 High Register */
-#define REG_EMAC0_ADDR0_LO              0xFFC20044         /* EMAC0 MAC Address 0 Low Register */
-#define REG_EMAC0_MMC_CTL               0xFFC20100         /* EMAC0 MMC Control Register */
-#define REG_EMAC0_MMC_RXINT             0xFFC20104         /* EMAC0 MMC Rx Interrupt Register */
-#define REG_EMAC0_MMC_TXINT             0xFFC20108         /* EMAC0 MMC Tx Interrupt Register */
-#define REG_EMAC0_MMC_RXIMSK            0xFFC2010C         /* EMAC0 MMC Rx Interrupt Mask Register */
-#define REG_EMAC0_MMC_TXIMSK            0xFFC20110         /* EMAC0 MMC TX Interrupt Mask Register */
-#define REG_EMAC0_TXOCTCNT_GB           0xFFC20114         /* EMAC0 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC0_TXFRMCNT_GB           0xFFC20118         /* EMAC0 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_G          0xFFC2011C         /* EMAC0 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC0_TXMCASTFRM_G          0xFFC20120         /* EMAC0 Tx Multicast Frames (Good) Register */
-#define REG_EMAC0_TX64_GB               0xFFC20124         /* EMAC0 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX65TO127_GB          0xFFC20128         /* EMAC0 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX128TO255_GB         0xFFC2012C         /* EMAC0 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX256TO511_GB         0xFFC20130         /* EMAC0 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX512TO1023_GB        0xFFC20134         /* EMAC0 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TX1024TOMAX_GB        0xFFC20138         /* EMAC0 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUCASTFRM_GB         0xFFC2013C         /* EMAC0 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXMCASTFRM_GB         0xFFC20140         /* EMAC0 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXBCASTFRM_GB         0xFFC20144         /* EMAC0 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC0_TXUNDR_ERR            0xFFC20148         /* EMAC0 Tx Underflow Error Register */
-#define REG_EMAC0_TXSNGCOL_G            0xFFC2014C         /* EMAC0 Tx Single Collision (Good) Register */
-#define REG_EMAC0_TXMULTCOL_G           0xFFC20150         /* EMAC0 Tx Multiple Collision (Good) Register */
-#define REG_EMAC0_TXDEFERRED            0xFFC20154         /* EMAC0 Tx Deferred Register */
-#define REG_EMAC0_TXLATECOL             0xFFC20158         /* EMAC0 Tx Late Collision Register */
-#define REG_EMAC0_TXEXCESSCOL           0xFFC2015C         /* EMAC0 Tx Excess Collision Register */
-#define REG_EMAC0_TXCARR_ERR            0xFFC20160         /* EMAC0 Tx Carrier Error Register */
-#define REG_EMAC0_TXOCTCNT_G            0xFFC20164         /* EMAC0 Tx Octet Count (Good) Register */
-#define REG_EMAC0_TXFRMCNT_G            0xFFC20168         /* EMAC0 Tx Frame Count (Good) Register */
-#define REG_EMAC0_TXEXCESSDEF           0xFFC2016C         /* EMAC0 Tx Excess Deferral Register */
-#define REG_EMAC0_TXPAUSEFRM            0xFFC20170         /* EMAC0 Tx Pause Frame Register */
-#define REG_EMAC0_TXVLANFRM_G           0xFFC20174         /* EMAC0 Tx VLAN Frames (Good) Register */
-#define REG_EMAC0_RXFRMCNT_GB           0xFFC20180         /* EMAC0 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_GB           0xFFC20184         /* EMAC0 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC0_RXOCTCNT_G            0xFFC20188         /* EMAC0 Rx Octet Count (Good) Register */
-#define REG_EMAC0_RXBCASTFRM_G          0xFFC2018C         /* EMAC0 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC0_RXMCASTFRM_G          0xFFC20190         /* EMAC0 Rx Multicast Frames (Good) Register */
-#define REG_EMAC0_RXCRC_ERR             0xFFC20194         /* EMAC0 Rx CRC Error Register */
-#define REG_EMAC0_RXALIGN_ERR           0xFFC20198         /* EMAC0 Rx alignment Error Register */
-#define REG_EMAC0_RXRUNT_ERR            0xFFC2019C         /* EMAC0 Rx Runt Error Register */
-#define REG_EMAC0_RXJAB_ERR             0xFFC201A0         /* EMAC0 Rx Jab Error Register */
-#define REG_EMAC0_RXUSIZE_G             0xFFC201A4         /* EMAC0 Rx Undersize (Good) Register */
-#define REG_EMAC0_RXOSIZE_G             0xFFC201A8         /* EMAC0 Rx Oversize (Good) Register */
-#define REG_EMAC0_RX64_GB               0xFFC201AC         /* EMAC0 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX65TO127_GB          0xFFC201B0         /* EMAC0 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX128TO255_GB         0xFFC201B4         /* EMAC0 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX256TO511_GB         0xFFC201B8         /* EMAC0 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX512TO1023_GB        0xFFC201BC         /* EMAC0 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RX1024TOMAX_GB        0xFFC201C0         /* EMAC0 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC0_RXUCASTFRM_G          0xFFC201C4         /* EMAC0 Rx Unicast Frames (Good) Register */
-#define REG_EMAC0_RXLEN_ERR             0xFFC201C8         /* EMAC0 Rx Length Error Register */
-#define REG_EMAC0_RXOORTYPE             0xFFC201CC         /* EMAC0 Rx Out Of Range Type Register */
-#define REG_EMAC0_RXPAUSEFRM            0xFFC201D0         /* EMAC0 Rx Pause Frames Register */
-#define REG_EMAC0_RXFIFO_OVF            0xFFC201D4         /* EMAC0 Rx FIFO Overflow Register */
-#define REG_EMAC0_RXVLANFRM_GB          0xFFC201D8         /* EMAC0 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC0_RXWDOG_ERR            0xFFC201DC         /* EMAC0 Rx Watch Dog Error Register */
-#define REG_EMAC0_IPC_RXIMSK            0xFFC20200         /* EMAC0 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC0_IPC_RXINT             0xFFC20208         /* EMAC0 MMC IPC Rx Interrupt Register */
-#define REG_EMAC0_RXIPV4_GD_FRM         0xFFC20210         /* EMAC0 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_FRM    0xFFC20214         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_FRM      0xFFC20218         /* EMAC0 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC0_RXIPV4_FRAG_FRM       0xFFC2021C         /* EMAC0 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC0_RXIPV4_UDSBL_FRM      0xFFC20220         /* EMAC0 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC0_RXIPV6_GD_FRM         0xFFC20224         /* EMAC0 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_FRM    0xFFC20228         /* EMAC0 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC0_RXIPV6_NOPAY_FRM      0xFFC2022C         /* EMAC0 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC0_RXUDP_GD_FRM          0xFFC20230         /* EMAC0 Rx UDP Good Frames Register */
-#define REG_EMAC0_RXUDP_ERR_FRM         0xFFC20234         /* EMAC0 Rx UDP Error Frames Register */
-#define REG_EMAC0_RXTCP_GD_FRM          0xFFC20238         /* EMAC0 Rx TCP Good Frames Register */
-#define REG_EMAC0_RXTCP_ERR_FRM         0xFFC2023C         /* EMAC0 Rx TCP Error Frames Register */
-#define REG_EMAC0_RXICMP_GD_FRM         0xFFC20240         /* EMAC0 Rx ICMP Good Frames Register */
-#define REG_EMAC0_RXICMP_ERR_FRM        0xFFC20244         /* EMAC0 Rx ICMP Error Frames Register */
-#define REG_EMAC0_RXIPV4_GD_OCT         0xFFC20250         /* EMAC0 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC0_RXIPV4_HDR_ERR_OCT    0xFFC20254         /* EMAC0 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC0_RXIPV4_NOPAY_OCT      0xFFC20258         /* EMAC0 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC0_RXIPV4_FRAG_OCT       0xFFC2025C         /* EMAC0 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC0_RXIPV4_UDSBL_OCT      0xFFC20260         /* EMAC0 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC0_RXIPV6_GD_OCT         0xFFC20264         /* EMAC0 Rx IPv6 Good Octets Register */
-#define REG_EMAC0_RXIPV6_HDR_ERR_OCT    0xFFC20268         /* EMAC0 Rx IPv6 Header Errors Register */
-#define REG_EMAC0_RXIPV6_NOPAY_OCT      0xFFC2026C         /* EMAC0 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC0_RXUDP_GD_OCT          0xFFC20270         /* EMAC0 Rx UDP Good Octets Register */
-#define REG_EMAC0_RXUDP_ERR_OCT         0xFFC20274         /* EMAC0 Rx UDP Error Octets Register */
-#define REG_EMAC0_RXTCP_GD_OCT          0xFFC20278         /* EMAC0 Rx TCP Good Octets Register */
-#define REG_EMAC0_RXTCP_ERR_OCT         0xFFC2027C         /* EMAC0 Rx TCP Error Octets Register */
-#define REG_EMAC0_RXICMP_GD_OCT         0xFFC20280         /* EMAC0 Rx ICMP Good Octets Register */
-#define REG_EMAC0_RXICMP_ERR_OCT        0xFFC20284         /* EMAC0 Rx ICMP Error Octets Register */
-#define REG_EMAC0_TM_CTL                0xFFC20700         /* EMAC0 Time Stamp Control Register */
-#define REG_EMAC0_TM_SUBSEC             0xFFC20704         /* EMAC0 Time Stamp Sub Second Increment Register */
-#define REG_EMAC0_TM_SEC                0xFFC20708         /* EMAC0 Time Stamp Low Seconds Register */
-#define REG_EMAC0_TM_NSEC               0xFFC2070C         /* EMAC0 Time Stamp Nano Seconds Register */
-#define REG_EMAC0_TM_SECUPDT            0xFFC20710         /* EMAC0 Time Stamp Seconds Update Register */
-#define REG_EMAC0_TM_NSECUPDT           0xFFC20714         /* EMAC0 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC0_TM_ADDEND             0xFFC20718         /* EMAC0 Time Stamp Addend Register */
-#define REG_EMAC0_TM_TGTM               0xFFC2071C         /* EMAC0 Time Stamp Target Time Seconds Register */
-#define REG_EMAC0_TM_NTGTM              0xFFC20720         /* EMAC0 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC0_TM_HISEC              0xFFC20724         /* EMAC0 Time Stamp High Second Register */
-#define REG_EMAC0_TM_STMPSTAT           0xFFC20728         /* EMAC0 Time Stamp Status Register */
-#define REG_EMAC0_TM_PPSCTL             0xFFC2072C         /* EMAC0 PPS Control Register */
-#define REG_EMAC0_TM_AUXSTMP_NSEC       0xFFC20730         /* EMAC0 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC0_TM_AUXSTMP_SEC        0xFFC20734         /* EMAC0 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC0_TM_PPSINTVL           0xFFC20760         /* EMAC0 Time Stamp PPS Interval Register */
-#define REG_EMAC0_TM_PPSWIDTH           0xFFC20764         /* EMAC0 PPS Width Register */
-#define REG_EMAC0_DMA_BUSMODE           0xFFC21000         /* EMAC0 DMA Bus Mode Register */
-#define REG_EMAC0_DMA_TXPOLL            0xFFC21004         /* EMAC0 DMA Tx Poll Demand Register */
-#define REG_EMAC0_DMA_RXPOLL            0xFFC21008         /* EMAC0 DMA Rx Poll Demand register */
-#define REG_EMAC0_DMA_RXDSC_ADDR        0xFFC2100C         /* EMAC0 DMA Rx Descriptor List Address Register */
-#define REG_EMAC0_DMA_TXDSC_ADDR        0xFFC21010         /* EMAC0 DMA Tx Descriptor List Address Register */
-#define REG_EMAC0_DMA_STAT              0xFFC21014         /* EMAC0 DMA Status Register */
-#define REG_EMAC0_DMA_OPMODE            0xFFC21018         /* EMAC0 DMA Operation Mode Register */
-#define REG_EMAC0_DMA_IEN               0xFFC2101C         /* EMAC0 DMA Interrupt Enable Register */
-#define REG_EMAC0_DMA_MISS_FRM          0xFFC21020         /* EMAC0 DMA Missed Frame Register */
-#define REG_EMAC0_DMA_RXIWDOG           0xFFC21024         /* EMAC0 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC0_DMA_BMMODE            0xFFC21028         /* EMAC0 DMA SCB Bus Mode Register */
-#define REG_EMAC0_DMA_BMSTAT            0xFFC2102C         /* EMAC0 DMA SCB Status Register */
-#define REG_EMAC0_DMA_TXDSC_CUR         0xFFC21048         /* EMAC0 DMA Tx Descriptor Current Register */
-#define REG_EMAC0_DMA_RXDSC_CUR         0xFFC2104C         /* EMAC0 DMA Rx Descriptor Current Register */
-#define REG_EMAC0_DMA_TXBUF_CUR         0xFFC21050         /* EMAC0 DMA Tx Buffer Current Register */
-#define REG_EMAC0_DMA_RXBUF_CUR         0xFFC21054         /* EMAC0 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC1
-   ========================= */
-#define REG_EMAC1_MACCFG                0xFFC22000         /* EMAC1 MAC Configuration Register */
-#define REG_EMAC1_MACFRMFILT            0xFFC22004         /* EMAC1 MAC Rx Frame Filter Register */
-#define REG_EMAC1_HASHTBL_HI            0xFFC22008         /* EMAC1 Hash Table High Register */
-#define REG_EMAC1_HASHTBL_LO            0xFFC2200C         /* EMAC1 Hash Table Low Register */
-#define REG_EMAC1_SMI_ADDR              0xFFC22010         /* EMAC1 SMI Address Register */
-#define REG_EMAC1_SMI_DATA              0xFFC22014         /* EMAC1 SMI Data Register */
-#define REG_EMAC1_FLOWCTL               0xFFC22018         /* EMAC1 FLow Control Register */
-#define REG_EMAC1_VLANTAG               0xFFC2201C         /* EMAC1 VLAN Tag Register */
-#define REG_EMAC1_DBG                   0xFFC22024         /* EMAC1 Debug Register */
-#define REG_EMAC1_ISTAT                 0xFFC22038         /* EMAC1 Interrupt Status Register */
-#define REG_EMAC1_IMSK                  0xFFC2203C         /* EMAC1 Interrupt Mask Register */
-#define REG_EMAC1_ADDR0_HI              0xFFC22040         /* EMAC1 MAC Address 0 High Register */
-#define REG_EMAC1_ADDR0_LO              0xFFC22044         /* EMAC1 MAC Address 0 Low Register */
-#define REG_EMAC1_MMC_CTL               0xFFC22100         /* EMAC1 MMC Control Register */
-#define REG_EMAC1_MMC_RXINT             0xFFC22104         /* EMAC1 MMC Rx Interrupt Register */
-#define REG_EMAC1_MMC_TXINT             0xFFC22108         /* EMAC1 MMC Tx Interrupt Register */
-#define REG_EMAC1_MMC_RXIMSK            0xFFC2210C         /* EMAC1 MMC Rx Interrupt Mask Register */
-#define REG_EMAC1_MMC_TXIMSK            0xFFC22110         /* EMAC1 MMC TX Interrupt Mask Register */
-#define REG_EMAC1_TXOCTCNT_GB           0xFFC22114         /* EMAC1 Tx OCT Count (Good/Bad) Register */
-#define REG_EMAC1_TXFRMCNT_GB           0xFFC22118         /* EMAC1 Tx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_G          0xFFC2211C         /* EMAC1 Tx Broadcast Frames (Good) Register */
-#define REG_EMAC1_TXMCASTFRM_G          0xFFC22120         /* EMAC1 Tx Multicast Frames (Good) Register */
-#define REG_EMAC1_TX64_GB               0xFFC22124         /* EMAC1 Tx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX65TO127_GB          0xFFC22128         /* EMAC1 Tx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX128TO255_GB         0xFFC2212C         /* EMAC1 Tx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX256TO511_GB         0xFFC22130         /* EMAC1 Tx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX512TO1023_GB        0xFFC22134         /* EMAC1 Tx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TX1024TOMAX_GB        0xFFC22138         /* EMAC1 Tx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUCASTFRM_GB         0xFFC2213C         /* EMAC1 Tx Unicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXMCASTFRM_GB         0xFFC22140         /* EMAC1 Tx Multicast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXBCASTFRM_GB         0xFFC22144         /* EMAC1 Tx Broadcast Frames (Good/Bad) Register */
-#define REG_EMAC1_TXUNDR_ERR            0xFFC22148         /* EMAC1 Tx Underflow Error Register */
-#define REG_EMAC1_TXSNGCOL_G            0xFFC2214C         /* EMAC1 Tx Single Collision (Good) Register */
-#define REG_EMAC1_TXMULTCOL_G           0xFFC22150         /* EMAC1 Tx Multiple Collision (Good) Register */
-#define REG_EMAC1_TXDEFERRED            0xFFC22154         /* EMAC1 Tx Deferred Register */
-#define REG_EMAC1_TXLATECOL             0xFFC22158         /* EMAC1 Tx Late Collision Register */
-#define REG_EMAC1_TXEXCESSCOL           0xFFC2215C         /* EMAC1 Tx Excess Collision Register */
-#define REG_EMAC1_TXCARR_ERR            0xFFC22160         /* EMAC1 Tx Carrier Error Register */
-#define REG_EMAC1_TXOCTCNT_G            0xFFC22164         /* EMAC1 Tx Octet Count (Good) Register */
-#define REG_EMAC1_TXFRMCNT_G            0xFFC22168         /* EMAC1 Tx Frame Count (Good) Register */
-#define REG_EMAC1_TXEXCESSDEF           0xFFC2216C         /* EMAC1 Tx Excess Deferral Register */
-#define REG_EMAC1_TXPAUSEFRM            0xFFC22170         /* EMAC1 Tx Pause Frame Register */
-#define REG_EMAC1_TXVLANFRM_G           0xFFC22174         /* EMAC1 Tx VLAN Frames (Good) Register */
-#define REG_EMAC1_RXFRMCNT_GB           0xFFC22180         /* EMAC1 Rx Frame Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_GB           0xFFC22184         /* EMAC1 Rx Octet Count (Good/Bad) Register */
-#define REG_EMAC1_RXOCTCNT_G            0xFFC22188         /* EMAC1 Rx Octet Count (Good) Register */
-#define REG_EMAC1_RXBCASTFRM_G          0xFFC2218C         /* EMAC1 Rx Broadcast Frames (Good) Register */
-#define REG_EMAC1_RXMCASTFRM_G          0xFFC22190         /* EMAC1 Rx Multicast Frames (Good) Register */
-#define REG_EMAC1_RXCRC_ERR             0xFFC22194         /* EMAC1 Rx CRC Error Register */
-#define REG_EMAC1_RXALIGN_ERR           0xFFC22198         /* EMAC1 Rx alignment Error Register */
-#define REG_EMAC1_RXRUNT_ERR            0xFFC2219C         /* EMAC1 Rx Runt Error Register */
-#define REG_EMAC1_RXJAB_ERR             0xFFC221A0         /* EMAC1 Rx Jab Error Register */
-#define REG_EMAC1_RXUSIZE_G             0xFFC221A4         /* EMAC1 Rx Undersize (Good) Register */
-#define REG_EMAC1_RXOSIZE_G             0xFFC221A8         /* EMAC1 Rx Oversize (Good) Register */
-#define REG_EMAC1_RX64_GB               0xFFC221AC         /* EMAC1 Rx 64-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX65TO127_GB          0xFFC221B0         /* EMAC1 Rx 65- to 127-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX128TO255_GB         0xFFC221B4         /* EMAC1 Rx 128- to 255-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX256TO511_GB         0xFFC221B8         /* EMAC1 Rx 256- to 511-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX512TO1023_GB        0xFFC221BC         /* EMAC1 Rx 512- to 1023-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RX1024TOMAX_GB        0xFFC221C0         /* EMAC1 Rx 1024- to Max-Byte Frames (Good/Bad) Register */
-#define REG_EMAC1_RXUCASTFRM_G          0xFFC221C4         /* EMAC1 Rx Unicast Frames (Good) Register */
-#define REG_EMAC1_RXLEN_ERR             0xFFC221C8         /* EMAC1 Rx Length Error Register */
-#define REG_EMAC1_RXOORTYPE             0xFFC221CC         /* EMAC1 Rx Out Of Range Type Register */
-#define REG_EMAC1_RXPAUSEFRM            0xFFC221D0         /* EMAC1 Rx Pause Frames Register */
-#define REG_EMAC1_RXFIFO_OVF            0xFFC221D4         /* EMAC1 Rx FIFO Overflow Register */
-#define REG_EMAC1_RXVLANFRM_GB          0xFFC221D8         /* EMAC1 Rx VLAN Frames (Good/Bad) Register */
-#define REG_EMAC1_RXWDOG_ERR            0xFFC221DC         /* EMAC1 Rx Watch Dog Error Register */
-#define REG_EMAC1_IPC_RXIMSK            0xFFC22200         /* EMAC1 MMC IPC Rx Interrupt Mask Register */
-#define REG_EMAC1_IPC_RXINT             0xFFC22208         /* EMAC1 MMC IPC Rx Interrupt Register */
-#define REG_EMAC1_RXIPV4_GD_FRM         0xFFC22210         /* EMAC1 Rx IPv4 Datagrams (Good) Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_FRM    0xFFC22214         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_FRM      0xFFC22218         /* EMAC1 Rx IPv4 Datagrams No Payload Frame Register */
-#define REG_EMAC1_RXIPV4_FRAG_FRM       0xFFC2221C         /* EMAC1 Rx IPv4 Datagrams Fragmented Frames Register */
-#define REG_EMAC1_RXIPV4_UDSBL_FRM      0xFFC22220         /* EMAC1 Rx IPv4 UDP Disabled Frames Register */
-#define REG_EMAC1_RXIPV6_GD_FRM         0xFFC22224         /* EMAC1 Rx IPv6 Datagrams Good Frames Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_FRM    0xFFC22228         /* EMAC1 Rx IPv6 Datagrams Header Error Frames Register */
-#define REG_EMAC1_RXIPV6_NOPAY_FRM      0xFFC2222C         /* EMAC1 Rx IPv6 Datagrams No Payload Frames Register */
-#define REG_EMAC1_RXUDP_GD_FRM          0xFFC22230         /* EMAC1 Rx UDP Good Frames Register */
-#define REG_EMAC1_RXUDP_ERR_FRM         0xFFC22234         /* EMAC1 Rx UDP Error Frames Register */
-#define REG_EMAC1_RXTCP_GD_FRM          0xFFC22238         /* EMAC1 Rx TCP Good Frames Register */
-#define REG_EMAC1_RXTCP_ERR_FRM         0xFFC2223C         /* EMAC1 Rx TCP Error Frames Register */
-#define REG_EMAC1_RXICMP_GD_FRM         0xFFC22240         /* EMAC1 Rx ICMP Good Frames Register */
-#define REG_EMAC1_RXICMP_ERR_FRM        0xFFC22244         /* EMAC1 Rx ICMP Error Frames Register */
-#define REG_EMAC1_RXIPV4_GD_OCT         0xFFC22250         /* EMAC1 Rx IPv4 Datagrams Good Octets Register */
-#define REG_EMAC1_RXIPV4_HDR_ERR_OCT    0xFFC22254         /* EMAC1 Rx IPv4 Datagrams Header Errors Register */
-#define REG_EMAC1_RXIPV4_NOPAY_OCT      0xFFC22258         /* EMAC1 Rx IPv4 Datagrams No Payload Octets Register */
-#define REG_EMAC1_RXIPV4_FRAG_OCT       0xFFC2225C         /* EMAC1 Rx IPv4 Datagrams Fragmented Octets Register */
-#define REG_EMAC1_RXIPV4_UDSBL_OCT      0xFFC22260         /* EMAC1 Rx IPv4 UDP Disabled Octets Register */
-#define REG_EMAC1_RXIPV6_GD_OCT         0xFFC22264         /* EMAC1 Rx IPv6 Good Octets Register */
-#define REG_EMAC1_RXIPV6_HDR_ERR_OCT    0xFFC22268         /* EMAC1 Rx IPv6 Header Errors Register */
-#define REG_EMAC1_RXIPV6_NOPAY_OCT      0xFFC2226C         /* EMAC1 Rx IPv6 No Payload Octets Register */
-#define REG_EMAC1_RXUDP_GD_OCT          0xFFC22270         /* EMAC1 Rx UDP Good Octets Register */
-#define REG_EMAC1_RXUDP_ERR_OCT         0xFFC22274         /* EMAC1 Rx UDP Error Octets Register */
-#define REG_EMAC1_RXTCP_GD_OCT          0xFFC22278         /* EMAC1 Rx TCP Good Octets Register */
-#define REG_EMAC1_RXTCP_ERR_OCT         0xFFC2227C         /* EMAC1 Rx TCP Error Octets Register */
-#define REG_EMAC1_RXICMP_GD_OCT         0xFFC22280         /* EMAC1 Rx ICMP Good Octets Register */
-#define REG_EMAC1_RXICMP_ERR_OCT        0xFFC22284         /* EMAC1 Rx ICMP Error Octets Register */
-#define REG_EMAC1_TM_CTL                0xFFC22700         /* EMAC1 Time Stamp Control Register */
-#define REG_EMAC1_TM_SUBSEC             0xFFC22704         /* EMAC1 Time Stamp Sub Second Increment Register */
-#define REG_EMAC1_TM_SEC                0xFFC22708         /* EMAC1 Time Stamp Low Seconds Register */
-#define REG_EMAC1_TM_NSEC               0xFFC2270C         /* EMAC1 Time Stamp Nano Seconds Register */
-#define REG_EMAC1_TM_SECUPDT            0xFFC22710         /* EMAC1 Time Stamp Seconds Update Register */
-#define REG_EMAC1_TM_NSECUPDT           0xFFC22714         /* EMAC1 Time Stamp Nano Seconds Update Register */
-#define REG_EMAC1_TM_ADDEND             0xFFC22718         /* EMAC1 Time Stamp Addend Register */
-#define REG_EMAC1_TM_TGTM               0xFFC2271C         /* EMAC1 Time Stamp Target Time Seconds Register */
-#define REG_EMAC1_TM_NTGTM              0xFFC22720         /* EMAC1 Time Stamp Target Time Nano Seconds Register */
-#define REG_EMAC1_TM_HISEC              0xFFC22724         /* EMAC1 Time Stamp High Second Register */
-#define REG_EMAC1_TM_STMPSTAT           0xFFC22728         /* EMAC1 Time Stamp Status Register */
-#define REG_EMAC1_TM_PPSCTL             0xFFC2272C         /* EMAC1 PPS Control Register */
-#define REG_EMAC1_TM_AUXSTMP_NSEC       0xFFC22730         /* EMAC1 Time Stamp Auxilary TS Nano Seconds Register */
-#define REG_EMAC1_TM_AUXSTMP_SEC        0xFFC22734         /* EMAC1 Time Stamp Auxilary TM Seconds Register */
-#define REG_EMAC1_TM_PPSINTVL           0xFFC22760         /* EMAC1 Time Stamp PPS Interval Register */
-#define REG_EMAC1_TM_PPSWIDTH           0xFFC22764         /* EMAC1 PPS Width Register */
-#define REG_EMAC1_DMA_BUSMODE           0xFFC23000         /* EMAC1 DMA Bus Mode Register */
-#define REG_EMAC1_DMA_TXPOLL            0xFFC23004         /* EMAC1 DMA Tx Poll Demand Register */
-#define REG_EMAC1_DMA_RXPOLL            0xFFC23008         /* EMAC1 DMA Rx Poll Demand register */
-#define REG_EMAC1_DMA_RXDSC_ADDR        0xFFC2300C         /* EMAC1 DMA Rx Descriptor List Address Register */
-#define REG_EMAC1_DMA_TXDSC_ADDR        0xFFC23010         /* EMAC1 DMA Tx Descriptor List Address Register */
-#define REG_EMAC1_DMA_STAT              0xFFC23014         /* EMAC1 DMA Status Register */
-#define REG_EMAC1_DMA_OPMODE            0xFFC23018         /* EMAC1 DMA Operation Mode Register */
-#define REG_EMAC1_DMA_IEN               0xFFC2301C         /* EMAC1 DMA Interrupt Enable Register */
-#define REG_EMAC1_DMA_MISS_FRM          0xFFC23020         /* EMAC1 DMA Missed Frame Register */
-#define REG_EMAC1_DMA_RXIWDOG           0xFFC23024         /* EMAC1 DMA Rx Interrupt Watch Dog Register */
-#define REG_EMAC1_DMA_BMMODE            0xFFC23028         /* EMAC1 DMA SCB Bus Mode Register */
-#define REG_EMAC1_DMA_BMSTAT            0xFFC2302C         /* EMAC1 DMA SCB Status Register */
-#define REG_EMAC1_DMA_TXDSC_CUR         0xFFC23048         /* EMAC1 DMA Tx Descriptor Current Register */
-#define REG_EMAC1_DMA_RXDSC_CUR         0xFFC2304C         /* EMAC1 DMA Rx Descriptor Current Register */
-#define REG_EMAC1_DMA_TXBUF_CUR         0xFFC23050         /* EMAC1 DMA Tx Buffer Current Register */
-#define REG_EMAC1_DMA_RXBUF_CUR         0xFFC23054         /* EMAC1 DMA Rx Buffer Current Register */
-
-/* =========================
-        EMAC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACCFG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACCFG_CST                 25                               /* CRC Stripping */
-#define BITP_EMAC_MACCFG_WD                  23                               /* Watch Dog Disable */
-#define BITP_EMAC_MACCFG_JB                  22                               /* Jabber Disable */
-#define BITP_EMAC_MACCFG_JE                  20                               /* Jumbo Frame Enable */
-#define BITP_EMAC_MACCFG_IFG                 17                               /* Inter Frame Gap */
-#define BITP_EMAC_MACCFG_DCRS                16                               /* Disable Carrier Sense */
-#define BITP_EMAC_MACCFG_FES                 14                               /* Speed of Operation */
-#define BITP_EMAC_MACCFG_DO                  13                               /* Disable Receive Own */
-#define BITP_EMAC_MACCFG_LM                  12                               /* Loopback Mode */
-#define BITP_EMAC_MACCFG_DM                  11                               /* Duplex Mode */
-#define BITP_EMAC_MACCFG_IPC                 10                               /* IP Checksum */
-#define BITP_EMAC_MACCFG_DR                   9                               /* Disable Retry */
-#define BITP_EMAC_MACCFG_ACS                  7                               /* Automatic Pad/CRC Stripping */
-#define BITP_EMAC_MACCFG_BL                   5                               /* Back Off Limit */
-#define BITP_EMAC_MACCFG_DC                   4                               /* Deferral Check */
-#define BITP_EMAC_MACCFG_TE                   3                               /* Transmitter Enable */
-#define BITP_EMAC_MACCFG_RE                   2                               /* Receiver Enable */
-#define BITM_EMAC_MACCFG_CST                 (_ADI_MSK(0x02000000,uint32_t))  /* CRC Stripping */
-#define BITM_EMAC_MACCFG_WD                  (_ADI_MSK(0x00800000,uint32_t))  /* Watch Dog Disable */
-#define BITM_EMAC_MACCFG_JB                  (_ADI_MSK(0x00400000,uint32_t))  /* Jabber Disable */
-#define BITM_EMAC_MACCFG_JE                  (_ADI_MSK(0x00100000,uint32_t))  /* Jumbo Frame Enable */
-
-#define BITM_EMAC_MACCFG_IFG                 (_ADI_MSK(0x000E0000,uint32_t))  /* Inter Frame Gap */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_96        (_ADI_MSK(0x00000000,uint32_t))  /* IFG: 96 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_88        (_ADI_MSK(0x00020000,uint32_t))  /* IFG: 88 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_80        (_ADI_MSK(0x00040000,uint32_t))  /* IFG: 80 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_72        (_ADI_MSK(0x00060000,uint32_t))  /* IFG: 72 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_64        (_ADI_MSK(0x00080000,uint32_t))  /* IFG: 64 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_56        (_ADI_MSK(0x000A0000,uint32_t))  /* IFG: 56 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_48        (_ADI_MSK(0x000C0000,uint32_t))  /* IFG: 48 bit times */
-#define ENUM_EMAC_MACCFG_BIT_TIMES_40        (_ADI_MSK(0x000E0000,uint32_t))  /* IFG: 40 bit times */
-#define BITM_EMAC_MACCFG_DCRS                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Carrier Sense */
-#define BITM_EMAC_MACCFG_FES                 (_ADI_MSK(0x00004000,uint32_t))  /* Speed of Operation */
-#define BITM_EMAC_MACCFG_DO                  (_ADI_MSK(0x00002000,uint32_t))  /* Disable Receive Own */
-#define BITM_EMAC_MACCFG_LM                  (_ADI_MSK(0x00001000,uint32_t))  /* Loopback Mode */
-#define BITM_EMAC_MACCFG_DM                  (_ADI_MSK(0x00000800,uint32_t))  /* Duplex Mode */
-#define BITM_EMAC_MACCFG_IPC                 (_ADI_MSK(0x00000400,uint32_t))  /* IP Checksum */
-
-#define BITM_EMAC_MACCFG_DR                  (_ADI_MSK(0x00000200,uint32_t))  /* Disable Retry */
-#define ENUM_EMAC_MACCFG_RETRY_ENABLED       (_ADI_MSK(0x00000000,uint32_t))  /* DR: Retry enabled */
-#define ENUM_EMAC_MACCFG_RETRY_DISABLED      (_ADI_MSK(0x00000200,uint32_t))  /* DR: Retry disabled */
-#define BITM_EMAC_MACCFG_ACS                 (_ADI_MSK(0x00000080,uint32_t))  /* Automatic Pad/CRC Stripping */
-
-#define BITM_EMAC_MACCFG_BL                  (_ADI_MSK(0x00000060,uint32_t))  /* Back Off Limit */
-#define ENUM_EMAC_MACCFG_BL_10               (_ADI_MSK(0x00000000,uint32_t))  /* BL: k = min (n, 10) */
-#define ENUM_EMAC_MACCFG_BL_8                (_ADI_MSK(0x00000020,uint32_t))  /* BL: k = min (n, 8) */
-#define ENUM_EMAC_MACCFG_BL_4                (_ADI_MSK(0x00000040,uint32_t))  /* BL: k = min (n, 4) */
-#define ENUM_EMAC_MACCFG_BL_1                (_ADI_MSK(0x00000060,uint32_t))  /* BL: k = min (n, 1) */
-#define BITM_EMAC_MACCFG_DC                  (_ADI_MSK(0x00000010,uint32_t))  /* Deferral Check */
-#define BITM_EMAC_MACCFG_TE                  (_ADI_MSK(0x00000008,uint32_t))  /* Transmitter Enable */
-#define BITM_EMAC_MACCFG_RE                  (_ADI_MSK(0x00000004,uint32_t))  /* Receiver Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MACFRMFILT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MACFRMFILT_RA              31                               /* Receive All Frames */
-#define BITP_EMAC_MACFRMFILT_HPF             10                               /* Hash or Perfect Filter */
-#define BITP_EMAC_MACFRMFILT_PCF              6                               /* Pass Control Frames */
-#define BITP_EMAC_MACFRMFILT_DBF              5                               /* Disable Broadcast Frames */
-#define BITP_EMAC_MACFRMFILT_PM               4                               /* Pass All Multicast Frames */
-#define BITP_EMAC_MACFRMFILT_DAIF             3                               /* Destination Address Inverse Filtering */
-#define BITP_EMAC_MACFRMFILT_HMC              2                               /* Hash Multicast */
-#define BITP_EMAC_MACFRMFILT_HUC              1                               /* Hash Unicast */
-#define BITP_EMAC_MACFRMFILT_PR               0                               /* Promiscuous Mode */
-#define BITM_EMAC_MACFRMFILT_RA              (_ADI_MSK(0x80000000,uint32_t))  /* Receive All Frames */
-#define BITM_EMAC_MACFRMFILT_HPF             (_ADI_MSK(0x00000400,uint32_t))  /* Hash or Perfect Filter */
-
-#define BITM_EMAC_MACFRMFILT_PCF             (_ADI_MSK(0x000000C0,uint32_t))  /* Pass Control Frames */
-#define ENUM_EMAC_MACFRMFILT_FILT_ALL        (_ADI_MSK(0x00000000,uint32_t))  /* PCF: Pass no control frames */
-#define ENUM_EMAC_MACFRMFILT_NO_PAUSE        (_ADI_MSK(0x00000040,uint32_t))  /* PCF: Pass no PAUSE frames */
-#define ENUM_EMAC_MACFRMFILT_FWD_ALL         (_ADI_MSK(0x00000080,uint32_t))  /* PCF: Pass all control frames */
-#define ENUM_EMAC_MACFRMFILT_PADR_FILT       (_ADI_MSK(0x000000C0,uint32_t))  /* PCF: Pass address filtered control frames */
-
-#define BITM_EMAC_MACFRMFILT_DBF             (_ADI_MSK(0x00000020,uint32_t))  /* Disable Broadcast Frames */
-#define ENUM_EMAC_MACFRMFILT_DIS_BCAST       (_ADI_MSK(0x00000000,uint32_t))  /* DBF: AFM module passes all received broadcast frames */
-#define ENUM_EMAC_MACFRMFILT_EN_BCAST        (_ADI_MSK(0x00000020,uint32_t))  /* DBF: AFM module filters all incoming broadcast frames */
-#define BITM_EMAC_MACFRMFILT_PM              (_ADI_MSK(0x00000010,uint32_t))  /* Pass All Multicast Frames */
-#define BITM_EMAC_MACFRMFILT_DAIF            (_ADI_MSK(0x00000008,uint32_t))  /* Destination Address Inverse Filtering */
-#define BITM_EMAC_MACFRMFILT_HMC             (_ADI_MSK(0x00000004,uint32_t))  /* Hash Multicast */
-#define BITM_EMAC_MACFRMFILT_HUC             (_ADI_MSK(0x00000002,uint32_t))  /* Hash Unicast */
-#define BITM_EMAC_MACFRMFILT_PR              (_ADI_MSK(0x00000001,uint32_t))  /* Promiscuous Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_ADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_ADDR_PA                11                               /* Physical Layer Address */
-#define BITP_EMAC_SMI_ADDR_SMIR               6                               /* SMI Register Address */
-#define BITP_EMAC_SMI_ADDR_CR                 2                               /* Clock Range */
-#define BITP_EMAC_SMI_ADDR_SMIW               1                               /* SMI Write */
-#define BITP_EMAC_SMI_ADDR_SMIB               0                               /* SMI Busy */
-#define BITM_EMAC_SMI_ADDR_PA                (_ADI_MSK(0x0000F800,uint32_t))  /* Physical Layer Address */
-#define BITM_EMAC_SMI_ADDR_SMIR              (_ADI_MSK(0x000007C0,uint32_t))  /* SMI Register Address */
-#define BITM_EMAC_SMI_ADDR_CR                (_ADI_MSK(0x0000003C,uint32_t))  /* Clock Range */
-#define BITM_EMAC_SMI_ADDR_SMIW              (_ADI_MSK(0x00000002,uint32_t))  /* SMI Write */
-#define BITM_EMAC_SMI_ADDR_SMIB              (_ADI_MSK(0x00000001,uint32_t))  /* SMI Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_SMI_DATA                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_SMI_DATA_SMID               0                               /* SMI Data */
-#define BITM_EMAC_SMI_DATA_SMID              (_ADI_MSK(0x0000FFFF,uint32_t))  /* SMI Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_FLOWCTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_FLOWCTL_PT                 16                               /* Pause Time */
-#define BITP_EMAC_FLOWCTL_UP                  3                               /* Unicast Pause Frame Detect */
-#define BITP_EMAC_FLOWCTL_RFE                 2                               /* Receive Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_TFE                 1                               /* Transmit Flow Control Enable */
-#define BITP_EMAC_FLOWCTL_FCBBPA              0                               /* Initiate Pause Control Frame */
-#define BITM_EMAC_FLOWCTL_PT                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Pause Time */
-#define BITM_EMAC_FLOWCTL_UP                 (_ADI_MSK(0x00000008,uint32_t))  /* Unicast Pause Frame Detect */
-#define BITM_EMAC_FLOWCTL_RFE                (_ADI_MSK(0x00000004,uint32_t))  /* Receive Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_TFE                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Flow Control Enable */
-#define BITM_EMAC_FLOWCTL_FCBBPA             (_ADI_MSK(0x00000001,uint32_t))  /* Initiate Pause Control Frame */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_VLANTAG                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_VLANTAG_ETV                16                               /* Enable Tag VLAN Comparison */
-#define BITP_EMAC_VLANTAG_VL                  0                               /* VLAN Tag Id Receive Frames */
-#define BITM_EMAC_VLANTAG_ETV                (_ADI_MSK(0x00010000,uint32_t))  /* Enable Tag VLAN Comparison */
-#define BITM_EMAC_VLANTAG_VL                 (_ADI_MSK(0x0000FFFF,uint32_t))  /* VLAN Tag Id Receive Frames */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DBG                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DBG_TXFIFOFULL             25                               /* Tx FIFO Full */
-#define BITP_EMAC_DBG_TXFIFONE               24                               /* Tx FIFO Not Empty */
-#define BITP_EMAC_DBG_TXFIFOACT              22                               /* Tx FIFO Active */
-#define BITP_EMAC_DBG_TXFIFOCTLST            20                               /* Tx FIFO Controller State */
-#define BITP_EMAC_DBG_TXPAUSE                19                               /* Tx Paused */
-#define BITP_EMAC_DBG_TXFRCTL                17                               /* Tx Frame Controller State */
-#define BITP_EMAC_DBG_MMTEA                  16                               /* MM Tx Engine Active */
-#define BITP_EMAC_DBG_RXFIFOST                8                               /* Rx FIFO State */
-#define BITP_EMAC_DBG_RXFIFOCTLST             5                               /* Rx FIFO Controller State */
-#define BITP_EMAC_DBG_RXFIFOACT               4                               /* Rx FIFO Active */
-#define BITP_EMAC_DBG_SFIFOST                 1                               /* Small FIFO State */
-#define BITP_EMAC_DBG_MMREA                   0                               /* MM Rx Engine Active */
-#define BITM_EMAC_DBG_TXFIFOFULL             (_ADI_MSK(0x02000000,uint32_t))  /* Tx FIFO Full */
-#define BITM_EMAC_DBG_TXFIFONE               (_ADI_MSK(0x01000000,uint32_t))  /* Tx FIFO Not Empty */
-#define BITM_EMAC_DBG_TXFIFOACT              (_ADI_MSK(0x00400000,uint32_t))  /* Tx FIFO Active */
-#define BITM_EMAC_DBG_TXFIFOCTLST            (_ADI_MSK(0x00300000,uint32_t))  /* Tx FIFO Controller State */
-#define BITM_EMAC_DBG_TXPAUSE                (_ADI_MSK(0x00080000,uint32_t))  /* Tx Paused */
-
-#define BITM_EMAC_DBG_TXFRCTL                (_ADI_MSK(0x00060000,uint32_t))  /* Tx Frame Controller State */
-#define ENUM_EMAC_DBG_TXFRCTL_IDLE           (_ADI_MSK(0x00000000,uint32_t))  /* TXFRCTL: Idle */
-#define ENUM_EMAC_DBG_TXFRCTL_WT_STATUS      (_ADI_MSK(0x00020000,uint32_t))  /* TXFRCTL: Wait */
-#define ENUM_EMAC_DBG_TXFRCTL_PAUSE          (_ADI_MSK(0x00040000,uint32_t))  /* TXFRCTL: Pause */
-#define ENUM_EMAC_DBG_TXFRCTL_TXFRAME        (_ADI_MSK(0x00060000,uint32_t))  /* TXFRCTL: Transmit */
-#define BITM_EMAC_DBG_MMTEA                  (_ADI_MSK(0x00010000,uint32_t))  /* MM Tx Engine Active */
-
-#define BITM_EMAC_DBG_RXFIFOST               (_ADI_MSK(0x00000300,uint32_t))  /* Rx FIFO State */
-#define ENUM_EMAC_DBG_FIFO_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOST: Rx FIFO Empty */
-#define ENUM_EMAC_DBG_FIFO_BEL_THERSHLD      (_ADI_MSK(0x00000100,uint32_t))  /* RXFIFOST: Rx FIFO Below De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_ABV_THERSHLD      (_ADI_MSK(0x00000200,uint32_t))  /* RXFIFOST: Rx FIFO Above De-activate FCT */
-#define ENUM_EMAC_DBG_FIFO_FULL              (_ADI_MSK(0x00000300,uint32_t))  /* RXFIFOST: Rx FIFO Full */
-
-#define BITM_EMAC_DBG_RXFIFOCTLST            (_ADI_MSK(0x00000060,uint32_t))  /* Rx FIFO Controller State */
-#define ENUM_EMAC_DBG_IDLE_FIFO              (_ADI_MSK(0x00000000,uint32_t))  /* RXFIFOCTLST: Idle */
-#define ENUM_EMAC_DBG_RD_DATA_FIFO           (_ADI_MSK(0x00000020,uint32_t))  /* RXFIFOCTLST: Read Data */
-#define ENUM_EMAC_DBG_RD_STS_FIFO            (_ADI_MSK(0x00000040,uint32_t))  /* RXFIFOCTLST: Read Status */
-#define ENUM_EMAC_DBG_FLUSH_FIFO             (_ADI_MSK(0x00000060,uint32_t))  /* RXFIFOCTLST: Flush */
-#define BITM_EMAC_DBG_RXFIFOACT              (_ADI_MSK(0x00000010,uint32_t))  /* Rx FIFO Active */
-#define BITM_EMAC_DBG_SFIFOST                (_ADI_MSK(0x00000006,uint32_t))  /* Small FIFO State */
-#define BITM_EMAC_DBG_MMREA                  (_ADI_MSK(0x00000001,uint32_t))  /* MM Rx Engine Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ISTAT_TS                    9                               /* Time Stamp Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRC                 7                               /* MMC Receive Checksum Offload Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCTX                 6                               /* MMC Transmit Interrupt Status */
-#define BITP_EMAC_ISTAT_MMCRX                 5                               /* MMC Receive Interrupt Status */
-#define BITP_EMAC_ISTAT_MMC                   4                               /* MMC Interrupt Status */
-#define BITM_EMAC_ISTAT_TS                   (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRC                (_ADI_MSK(0x00000080,uint32_t))  /* MMC Receive Checksum Offload Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCTX                (_ADI_MSK(0x00000040,uint32_t))  /* MMC Transmit Interrupt Status */
-#define BITM_EMAC_ISTAT_MMCRX                (_ADI_MSK(0x00000020,uint32_t))  /* MMC Receive Interrupt Status */
-#define BITM_EMAC_ISTAT_MMC                  (_ADI_MSK(0x00000010,uint32_t))  /* MMC Interrupt Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IMSK_TS                     9                               /* Time Stamp Interrupt Mask */
-#define BITM_EMAC_IMSK_TS                    (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_ADDR0_HI                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_ADDR0_HI_ADDR               0                               /* Address */
-#define BITM_EMAC_ADDR0_HI_ADDR              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_CTL_FULLPSET            5                               /* Full Preset */
-#define BITP_EMAC_MMC_CTL_CNTRPSET            4                               /* Counter Reset/Preset */
-#define BITP_EMAC_MMC_CTL_CNTRFRZ             3                               /* Counter Freeze */
-#define BITP_EMAC_MMC_CTL_RDRST               2                               /* Read Reset */
-#define BITP_EMAC_MMC_CTL_NOROLL              1                               /* No Rollover */
-#define BITP_EMAC_MMC_CTL_RST                 0                               /* Reset */
-#define BITM_EMAC_MMC_CTL_FULLPSET           (_ADI_MSK(0x00000020,uint32_t))  /* Full Preset */
-#define BITM_EMAC_MMC_CTL_CNTRPSET           (_ADI_MSK(0x00000010,uint32_t))  /* Counter Reset/Preset */
-#define BITM_EMAC_MMC_CTL_CNTRFRZ            (_ADI_MSK(0x00000008,uint32_t))  /* Counter Freeze */
-#define BITM_EMAC_MMC_CTL_RDRST              (_ADI_MSK(0x00000004,uint32_t))  /* Read Reset */
-#define BITM_EMAC_MMC_CTL_NOROLL             (_ADI_MSK(0x00000002,uint32_t))  /* No Rollover */
-#define BITM_EMAC_MMC_CTL_RST                (_ADI_MSK(0x00000001,uint32_t))  /* Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXINT_WDOGERR          23                               /* Rx Watch Dog Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_VLANFRGB         22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_FIFOOVF          21                               /* Rx FIFO Overflow Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_PAUSEFR          20                               /* Rx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OUTRANGE         19                               /* Rx Out Of Range Type Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_LENERR           18                               /* Rx Length Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_UCASTG           17                               /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R1024TOMAX       16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R512TO1023       15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R256TO511        14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R128TO255        13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R65TO127         12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_R64              11                               /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_OSIZEG           10                               /* Rx Oversize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_USIZEG            9                               /* Rx Undersize (Good) Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_JABERR            8                               /* Rx Jabber Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_RUNTERR           7                               /* Rx Runt Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_ALIGNERR          6                               /* Rx Alignment Error Count Half/Full */
-#define BITP_EMAC_MMC_RXINT_CRCERR            5                               /* Rx CRC Error Counter Half/Full */
-#define BITP_EMAC_MMC_RXINT_MCASTG            4                               /* Rx Multicast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_BCASTG            3                               /* Rx Broadcast Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTG           2                               /* Octet Count (Good) Half/Full */
-#define BITP_EMAC_MMC_RXINT_OCTCNTGB          1                               /* Octet Count (Good/Bad) Half/Full */
-#define BITP_EMAC_MMC_RXINT_FRCNTGB           0                               /* Frame Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_WDOGERR          (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_VLANFRGB         (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_FIFOOVF          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_PAUSEFR          (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OUTRANGE         (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_LENERR           (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_UCASTG           (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R1024TOMAX       (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R512TO1023       (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R256TO511        (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R128TO255        (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R65TO127         (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_R64              (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_OSIZEG           (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_USIZEG           (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_JABERR           (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_RUNTERR          (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_ALIGNERR         (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full */
-#define BITM_EMAC_MMC_RXINT_CRCERR           (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Counter Half/Full */
-#define BITM_EMAC_MMC_RXINT_MCASTG           (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_BCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTG          (_ADI_MSK(0x00000004,uint32_t))  /* Octet Count (Good) Half/Full */
-#define BITM_EMAC_MMC_RXINT_OCTCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Octet Count (Good/Bad) Half/Full */
-#define BITM_EMAC_MMC_RXINT_FRCNTGB          (_ADI_MSK(0x00000001,uint32_t))  /* Frame Count (Good/Bad) Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXINT_VLANFRGB         24                               /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_PAUSEFRM         23                               /* Tx Pause Frames Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSDEF        22                               /* Tx Excess Deferred Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTG           21                               /* Tx Frame Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTG          20                               /* Tx Octet Count (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_CARRERR          19                               /* Tx Carrier Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_EXCESSCOL        18                               /* Tx Exess Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_LATECOL          17                               /* Tx Late Collision Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_DEFERRED         16                               /* Tx Deffered Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MULTCOLG         15                               /* Tx Multiple collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_SNGCOLG          14                               /* Tx Single Collision (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UNDERR           13                               /* Tx Underflow Error Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTGB          12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTGB          11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_UCASTGB          10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T1024TOMAX        9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T512TO1023        8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T256TO511         7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T128TO255         6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T65TO127          5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_T64               4                               /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_MCASTG            3                               /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_BCASTG            2                               /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_FRCNTGB           1                               /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITP_EMAC_MMC_TXINT_OCTCNTGB          0                               /* Tx Octet Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_VLANFRGB         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_PAUSEFRM         (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSDEF        (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTG           (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTG          (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_CARRERR          (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_EXCESSCOL        (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_LATECOL          (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_DEFERRED         (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deffered Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MULTCOLG         (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_SNGCOLG          (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UNDERR           (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTGB          (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTGB          (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_UCASTGB          (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T1024TOMAX       (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T512TO1023       (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T256TO511        (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T128TO255        (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T65TO127         (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_T64              (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_MCASTG           (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_BCASTG           (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_FRCNTGB          (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full */
-#define BITM_EMAC_MMC_TXINT_OCTCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_RXIMSK_WATCHERR        23                               /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_VLANFRGB        22                               /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FIFOOV          21                               /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_PAUSEFRM        20                               /* Rx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OUTRANGE        19                               /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_LENERR          18                               /* Rx Length Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_UCASTG          17                               /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R1024TOMAX      16                               /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R512TO1023      15                               /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R256TO511       14                               /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R128TO255       13                               /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R65TO127        12                               /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_R64             11                               /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OSIZEG          10                               /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_USIZEG           9                               /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_JABERR           8                               /* Rx Jabber Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_RUNTERR          7                               /* Rx Runt Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_ALIGNERR         6                               /* Rx Alignment Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_CRCERR           5                               /* Rx CRC Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_MCASTG           4                               /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_BCASTG           3                               /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTG          2                               /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_OCTCNTGB         1                               /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_RXIMSK_FRCNTGB          0                               /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_WATCHERR        (_ADI_MSK(0x00800000,uint32_t))  /* Rx Watch Dog Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_VLANFRGB        (_ADI_MSK(0x00400000,uint32_t))  /* Rx VLAN Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FIFOOV          (_ADI_MSK(0x00200000,uint32_t))  /* Rx FIFO Overflow Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_PAUSEFRM        (_ADI_MSK(0x00100000,uint32_t))  /* Rx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OUTRANGE        (_ADI_MSK(0x00080000,uint32_t))  /* Rx Out Of Range Type Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_LENERR          (_ADI_MSK(0x00040000,uint32_t))  /* Rx Length Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_UCASTG          (_ADI_MSK(0x00020000,uint32_t))  /* Rx Unicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R1024TOMAX      (_ADI_MSK(0x00010000,uint32_t))  /* Rx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R512TO1023      (_ADI_MSK(0x00008000,uint32_t))  /* Rx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R256TO511       (_ADI_MSK(0x00004000,uint32_t))  /* Rx 255-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R128TO255       (_ADI_MSK(0x00002000,uint32_t))  /* Rx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R65TO127        (_ADI_MSK(0x00001000,uint32_t))  /* Rx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_R64             (_ADI_MSK(0x00000800,uint32_t))  /* Rx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OSIZEG          (_ADI_MSK(0x00000400,uint32_t))  /* Rx Oversize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_USIZEG          (_ADI_MSK(0x00000200,uint32_t))  /* Rx Undersize (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_JABERR          (_ADI_MSK(0x00000100,uint32_t))  /* Rx Jabber Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_RUNTERR         (_ADI_MSK(0x00000080,uint32_t))  /* Rx Runt Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_ALIGNERR        (_ADI_MSK(0x00000040,uint32_t))  /* Rx Alignment Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_CRCERR          (_ADI_MSK(0x00000020,uint32_t))  /* Rx CRC Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_MCASTG          (_ADI_MSK(0x00000010,uint32_t))  /* Rx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_BCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Rx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTG         (_ADI_MSK(0x00000004,uint32_t))  /* Rx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_OCTCNTGB        (_ADI_MSK(0x00000002,uint32_t))  /* Rx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_RXIMSK_FRCNTGB         (_ADI_MSK(0x00000001,uint32_t))  /* Rx Frame Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_MMC_TXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_MMC_TXIMSK_VLANFRG         24                               /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_PAUSEFRM        23                               /* Tx Pause Frames Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSDEF       22                               /* Tx Excess Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTG          21                               /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTG         20                               /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_CARRERR         19                               /* Tx Carrier Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_EXCESSCOL       18                               /* Tx Exess collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_LATECOL         17                               /* Tx Late Collision Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_DEFERRED        16                               /* Tx Deferred Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MULTCOLG        15                               /* Tx Multiple Collisions (Good) Count Mask */
-#define BITP_EMAC_MMC_TXIMSK_SNGCOLG         14                               /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UNDERR          13                               /* Tx Underflow Error Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTGB         12                               /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTGB         11                               /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_UCASTGB         10                               /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T1024TOMAX       9                               /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T512TO1023       8                               /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T256TO511        7                               /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T128TO255        6                               /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T65TO127         5                               /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_T64              4                               /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_MCASTG           3                               /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_BCASTG           2                               /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_FRCNTGB          1                               /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITP_EMAC_MMC_TXIMSK_OCTCNTGB         0                               /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_VLANFRG         (_ADI_MSK(0x01000000,uint32_t))  /* Tx VLAN Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_PAUSEFRM        (_ADI_MSK(0x00800000,uint32_t))  /* Tx Pause Frames Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSDEF       (_ADI_MSK(0x00400000,uint32_t))  /* Tx Excess Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTG          (_ADI_MSK(0x00200000,uint32_t))  /* Tx Frame Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTG         (_ADI_MSK(0x00100000,uint32_t))  /* Tx Octet Count (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_CARRERR         (_ADI_MSK(0x00080000,uint32_t))  /* Tx Carrier Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_EXCESSCOL       (_ADI_MSK(0x00040000,uint32_t))  /* Tx Exess collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_LATECOL         (_ADI_MSK(0x00020000,uint32_t))  /* Tx Late Collision Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_DEFERRED        (_ADI_MSK(0x00010000,uint32_t))  /* Tx Deferred Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MULTCOLG        (_ADI_MSK(0x00008000,uint32_t))  /* Tx Multiple Collisions (Good) Count Mask */
-#define BITM_EMAC_MMC_TXIMSK_SNGCOLG         (_ADI_MSK(0x00004000,uint32_t))  /* Tx Single Collision (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UNDERR          (_ADI_MSK(0x00002000,uint32_t))  /* Tx Underflow Error Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTGB         (_ADI_MSK(0x00001000,uint32_t))  /* Tx Broadcast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTGB         (_ADI_MSK(0x00000800,uint32_t))  /* Tx Multicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_UCASTGB         (_ADI_MSK(0x00000400,uint32_t))  /* Tx Unicast Frames (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T1024TOMAX      (_ADI_MSK(0x00000200,uint32_t))  /* Tx 1024-to-max Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T512TO1023      (_ADI_MSK(0x00000100,uint32_t))  /* Tx 512-to-1023 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T256TO511       (_ADI_MSK(0x00000080,uint32_t))  /* Tx 256-to-511 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T128TO255       (_ADI_MSK(0x00000040,uint32_t))  /* Tx 128-to-255 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T65TO127        (_ADI_MSK(0x00000020,uint32_t))  /* Tx 65-to-127 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_T64             (_ADI_MSK(0x00000010,uint32_t))  /* Tx 64 Octets (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_MCASTG          (_ADI_MSK(0x00000008,uint32_t))  /* Tx Multicast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_BCASTG          (_ADI_MSK(0x00000004,uint32_t))  /* Tx Broadcast Frames (Good) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_FRCNTGB         (_ADI_MSK(0x00000002,uint32_t))  /* Tx Frame Count (Good/Bad) Count Half/Full Mask */
-#define BITM_EMAC_MMC_TXIMSK_OCTCNTGB        (_ADI_MSK(0x00000001,uint32_t))  /* Tx Octet Count (Good/Bad) Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXIMSK                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERROCT      29                               /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGOCT        28                               /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERROCT       27                               /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGOCT         26                               /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERROCT       25                               /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGOCT         24                               /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYOCT      23                               /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERROCT      22                               /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GOCT          21                               /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLOCT      20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGOCT       19                               /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYOCT      18                               /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERROCT      17                               /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GOCT          16                               /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPERRFRM      13                               /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_ICMPGFRM        12                               /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPERRFRM       11                               /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_TCPGFRM         10                               /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPERRFRM        9                               /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_UDPGFRM          8                               /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6NOPAYFRM       7                               /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6HDERRFRM       6                               /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V6GFRM           5                               /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4UDSBLFRM       4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4FRAGFRM        3                               /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4NOPAYFRM       2                               /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4HDERRFRM       1                               /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITP_EMAC_IPC_RXIMSK_V4GFRM           0                               /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERROCT      (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGOCT        (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERROCT       (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGOCT         (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERROCT       (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGOCT         (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYOCT      (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERROCT      (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GOCT          (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLOCT      (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGOCT       (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYOCT      (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERROCT      (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GOCT          (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPERRFRM      (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_ICMPGFRM        (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPERRFRM       (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_TCPGFRM         (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPERRFRM       (_ADI_MSK(0x00000200,uint32_t))  /* Rx UDP Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_UDPGFRM         (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6NOPAYFRM      (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6HDERRFRM      (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V6GFRM          (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4UDSBLFRM      (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4FRAGFRM       (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4NOPAYFRM      (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4HDERRFRM      (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frame Count Half/Full Mask */
-#define BITM_EMAC_IPC_RXIMSK_V4GFRM          (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_IPC_RXINT                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_IPC_RXINT_ICMPERROCT       29                               /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGOCT         28                               /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERROCT        27                               /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGOCT          26                               /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERROCT        25                               /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGOCT          24                               /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYOCT       23                               /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERROCT       22                               /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GOCT           21                               /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLOCT       20                               /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGOCT        19                               /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYOCT       18                               /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERROCT       17                               /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GOCT           16                               /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPERRFRM       13                               /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_ICMPGFRM         12                               /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPERRFRM        11                               /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_TCPGFRM          10                               /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPERRFRM         9                               /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_UDPGFRM           8                               /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6NOPAYFRM        7                               /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6HDERRFRM        6                               /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V6GFRM            5                               /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4UDSBLFRM        4                               /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4FRAGFRM         3                               /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4NOPAYFRM        2                               /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4HDERRFRM        1                               /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITP_EMAC_IPC_RXINT_V4GFRM            0                               /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERROCT       (_ADI_MSK(0x20000000,uint32_t))  /* Rx ICMP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGOCT         (_ADI_MSK(0x10000000,uint32_t))  /* Rx ICMP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERROCT        (_ADI_MSK(0x08000000,uint32_t))  /* Rx TCP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGOCT          (_ADI_MSK(0x04000000,uint32_t))  /* Rx TCP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERROCT        (_ADI_MSK(0x02000000,uint32_t))  /* Rx UDP Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGOCT          (_ADI_MSK(0x01000000,uint32_t))  /* Rx UDP (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYOCT       (_ADI_MSK(0x00800000,uint32_t))  /* Rx IPv6 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERROCT       (_ADI_MSK(0x00400000,uint32_t))  /* Rx IPv6 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GOCT           (_ADI_MSK(0x00200000,uint32_t))  /* Rx IPv6 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLOCT       (_ADI_MSK(0x00100000,uint32_t))  /* Rx IPv4 UDS Disable Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGOCT        (_ADI_MSK(0x00080000,uint32_t))  /* Rx IPv4 Fragmented Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYOCT       (_ADI_MSK(0x00040000,uint32_t))  /* Rx IPv4 No Payload Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERROCT       (_ADI_MSK(0x00020000,uint32_t))  /* Rx IPv4 Header Error Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GOCT           (_ADI_MSK(0x00010000,uint32_t))  /* Rx IPv4 (Good) Octets Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPERRFRM       (_ADI_MSK(0x00002000,uint32_t))  /* Rx ICMP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_ICMPGFRM         (_ADI_MSK(0x00001000,uint32_t))  /* Rx ICMP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPERRFRM        (_ADI_MSK(0x00000800,uint32_t))  /* Rx TCP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_TCPGFRM          (_ADI_MSK(0x00000400,uint32_t))  /* Rx TCP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPERRFRM        (_ADI_MSK(0x00000200,uint32_t))  /* Rx IDP Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_UDPGFRM          (_ADI_MSK(0x00000100,uint32_t))  /* Rx UDP (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6NOPAYFRM       (_ADI_MSK(0x00000080,uint32_t))  /* Rx IPv6 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6HDERRFRM       (_ADI_MSK(0x00000040,uint32_t))  /* Rx IPv6 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V6GFRM           (_ADI_MSK(0x00000020,uint32_t))  /* Rx IPv6 (Good) Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4UDSBLFRM       (_ADI_MSK(0x00000010,uint32_t))  /* Rx IPv4 UDS Disable Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4FRAGFRM        (_ADI_MSK(0x00000008,uint32_t))  /* Rx IPv4 Fragmented Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4NOPAYFRM       (_ADI_MSK(0x00000004,uint32_t))  /* Rx IPv4 No Payload Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4HDERRFRM       (_ADI_MSK(0x00000002,uint32_t))  /* Rx IPv4 Header Error Frames Count Half/Full Interrupt */
-#define BITM_EMAC_IPC_RXINT_V4GFRM           (_ADI_MSK(0x00000001,uint32_t))  /* Rx IPv4 (Good) Frames Count Half/Full Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_CTL_ATSFC               24                               /* Auxilary Time Stamp FIFO Clear */
-#define BITP_EMAC_TM_CTL_TSENMACADDR         18                               /* Time Stamp Enable MAC Address */
-#define BITP_EMAC_TM_CTL_SNAPTYPSEL          16                               /* Snapshot Type Select */
-#define BITP_EMAC_TM_CTL_TSMSTRENA           15                               /* Time Stamp Master (Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSEVNTENA           14                               /* Time Stamp Event (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV4ENA           13                               /* Time Stamp IPV4 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPV6ENA           12                               /* Time Stamp IPV6 (PTP Frames) Enable */
-#define BITP_EMAC_TM_CTL_TSIPENA             11                               /* Time Stamp IP Enable */
-#define BITP_EMAC_TM_CTL_TSVER2ENA           10                               /* Time Stamp VER2 (Snooping) Enable */
-#define BITP_EMAC_TM_CTL_TSCTRLSSR            9                               /* Time Stamp Control Nanosecond Rollover */
-#define BITP_EMAC_TM_CTL_TSENALL              8                               /* Time Stamp Enable All (Frames) */
-#define BITP_EMAC_TM_CTL_TSADDREG             5                               /* Time Stamp Addend Register Update */
-#define BITP_EMAC_TM_CTL_TSTRIG               4                               /* Time Stamp (Target Time) Trigger Enable */
-#define BITP_EMAC_TM_CTL_TSUPDT               3                               /* Time Stamp (System Time) Update */
-#define BITP_EMAC_TM_CTL_TSINIT               2                               /* Time Stamp (System Time) Initialize */
-#define BITP_EMAC_TM_CTL_TSCFUPDT             1                               /* Time Stamp (System Time) Fine/Coarse Update */
-#define BITP_EMAC_TM_CTL_TSENA                0                               /* Time Stamp (PTP) Enable */
-#define BITM_EMAC_TM_CTL_ATSFC               (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp FIFO Clear */
-
-#define BITM_EMAC_TM_CTL_TSENMACADDR         (_ADI_MSK(0x00040000,uint32_t))  /* Time Stamp Enable MAC Address */
-#define ENUM_EMAC_TM_CTL_D_PTP_ADDRFILT      (_ADI_MSK(0x00000000,uint32_t))  /* TSENMACADDR: Disable PTP MAC address filter */
-#define ENUM_EMAC_TM_CTL_E_PTP_ADDRFILT      (_ADI_MSK(0x00040000,uint32_t))  /* TSENMACADDR: Enable PTP MAC address filter */
-#define BITM_EMAC_TM_CTL_SNAPTYPSEL          (_ADI_MSK(0x00030000,uint32_t))  /* Snapshot Type Select */
-
-#define BITM_EMAC_TM_CTL_TSMSTRENA           (_ADI_MSK(0x00008000,uint32_t))  /* Time Stamp Master (Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_SLVSNPT_MSGS      (_ADI_MSK(0x00000000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Slave Messages */
-#define ENUM_EMAC_TM_CTL_E_MSSNPST_MSGS      (_ADI_MSK(0x00008000,uint32_t))  /* TSMSTRENA: Enable Snapshot for Master Messages */
-
-#define BITM_EMAC_TM_CTL_TSEVNTENA           (_ADI_MSK(0x00004000,uint32_t))  /* Time Stamp Event (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_E_ATSTMP_MSGS       (_ADI_MSK(0x00000000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for All Messages */
-#define ENUM_EMAC_TM_CTL_E_ETSTMP_MSGS       (_ADI_MSK(0x00004000,uint32_t))  /* TSEVNTENA: Enable Time Stamp for Event Messages Only */
-
-#define BITM_EMAC_TM_CTL_TSIPV4ENA           (_ADI_MSK(0x00002000,uint32_t))  /* Time Stamp IPV4 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV4        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV4ENA: Disable Time Stamp for PTP Over IPv4 Frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV4        (_ADI_MSK(0x00002000,uint32_t))  /* TSIPV4ENA: Enable Time Stamp for PTP Over IPv4 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPV6ENA           (_ADI_MSK(0x00001000,uint32_t))  /* Time Stamp IPV6 (PTP Frames) Enable */
-#define ENUM_EMAC_TM_CTL_D_TSTMP_IPV6        (_ADI_MSK(0x00000000,uint32_t))  /* TSIPV6ENA: Disable Time Stamp for PTP Over IPv6 frames */
-#define ENUM_EMAC_TM_CTL_E_TSTMP_IPV6        (_ADI_MSK(0x00001000,uint32_t))  /* TSIPV6ENA: Enable Time Stamp for PTP Over IPv6 Frames */
-
-#define BITM_EMAC_TM_CTL_TSIPENA             (_ADI_MSK(0x00000800,uint32_t))  /* Time Stamp IP Enable */
-#define ENUM_EMAC_TM_CTL_D_PTP_OV_ETHER      (_ADI_MSK(0x00000000,uint32_t))  /* TSIPENA: Disable PTP Over Ethernet Frames */
-#define ENUM_EMAC_TM_CTL_E_PTP_OV_ETHER      (_ADI_MSK(0x00000800,uint32_t))  /* TSIPENA: Enable PTP Over Ethernet Frames */
-
-#define BITM_EMAC_TM_CTL_TSVER2ENA           (_ADI_MSK(0x00000400,uint32_t))  /* Time Stamp VER2 (Snooping) Enable */
-#define ENUM_EMAC_TM_CTL_D_PKT_SNOOP_V2      (_ADI_MSK(0x00000000,uint32_t))  /* TSVER2ENA: Disable packet snooping for V2 frames */
-#define ENUM_EMAC_TM_CTL_E_PKT_SNOOP_V2      (_ADI_MSK(0x00000400,uint32_t))  /* TSVER2ENA: Enable packet snooping for V2 frames */
-
-#define BITM_EMAC_TM_CTL_TSCTRLSSR           (_ADI_MSK(0x00000200,uint32_t))  /* Time Stamp Control Nanosecond Rollover */
-#define ENUM_EMAC_TM_CTL_RO_SUBSEC_RES       (_ADI_MSK(0x00000000,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x7FFFFFFF */
-#define ENUM_EMAC_TM_CTL_RO_NANO_RES         (_ADI_MSK(0x00000200,uint32_t))  /* TSCTRLSSR: Roll Over Nanosecond After 0x3B9AC9FF */
-
-#define BITM_EMAC_TM_CTL_TSENALL             (_ADI_MSK(0x00000100,uint32_t))  /* Time Stamp Enable All (Frames) */
-#define ENUM_EMAC_TM_CTL_D_TSALL_FRAMES      (_ADI_MSK(0x00000000,uint32_t))  /* TSENALL: Disable timestamp for all frames */
-#define ENUM_EMAC_TM_CTL_E_TSALL_FRAMES      (_ADI_MSK(0x00000100,uint32_t))  /* TSENALL: Enable timestamp for all frames */
-#define BITM_EMAC_TM_CTL_TSADDREG            (_ADI_MSK(0x00000020,uint32_t))  /* Time Stamp Addend Register Update */
-
-#define BITM_EMAC_TM_CTL_TSTRIG              (_ADI_MSK(0x00000010,uint32_t))  /* Time Stamp (Target Time) Trigger Enable */
-#define ENUM_EMAC_TM_CTL_EN_TRIGGER          (_ADI_MSK(0x00000010,uint32_t))  /* TSTRIG: Interrupt (TS) if system time is greater than target time register */
-
-#define BITM_EMAC_TM_CTL_TSUPDT              (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp (System Time) Update */
-#define ENUM_EMAC_TM_CTL_EN_UPDATE           (_ADI_MSK(0x00000008,uint32_t))  /* TSUPDT: System time updated with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSINIT              (_ADI_MSK(0x00000004,uint32_t))  /* Time Stamp (System Time) Initialize */
-#define ENUM_EMAC_TM_CTL_EN_TS_INIT          (_ADI_MSK(0x00000004,uint32_t))  /* TSINIT: System time initialized with Time stamp register values */
-
-#define BITM_EMAC_TM_CTL_TSCFUPDT            (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp (System Time) Fine/Coarse Update */
-#define ENUM_EMAC_TM_CTL_EN_COARSE_UPDT      (_ADI_MSK(0x00000000,uint32_t))  /* TSCFUPDT: Use Coarse Correction Method for System Time Update */
-#define ENUM_EMAC_TM_CTL_EN_FINE_UPDT        (_ADI_MSK(0x00000002,uint32_t))  /* TSCFUPDT: Use Fine Correction Method for System Time Update */
-
-#define BITM_EMAC_TM_CTL_TSENA               (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp (PTP) Enable */
-#define ENUM_EMAC_TM_CTL_DTS                 (_ADI_MSK(0x00000000,uint32_t))  /* TSENA: Disable PTP Module */
-#define ENUM_EMAC_TM_CTL_TS                  (_ADI_MSK(0x00000001,uint32_t))  /* TSENA: Enable PTP Module */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_SUBSEC                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_SUBSEC_SSINC             0                               /* Sub-Second Increment Value */
-#define BITM_EMAC_TM_SUBSEC_SSINC            (_ADI_MSK(0x000000FF,uint32_t))  /* Sub-Second Increment Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSEC                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSEC_TSSS                0                               /* Time Stamp Nanoseconds */
-#define BITM_EMAC_TM_NSEC_TSSS               (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Nanoseconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NSECUPDT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NSECUPDT_ADDSUB         31                               /* Add or Subtract the Time */
-#define BITP_EMAC_TM_NSECUPDT_TSSS            0                               /* Time Stamp Sub Second Initialize/Increment */
-#define BITM_EMAC_TM_NSECUPDT_ADDSUB         (_ADI_MSK(0x80000000,uint32_t))  /* Add or Subtract the Time */
-#define BITM_EMAC_TM_NSECUPDT_TSSS           (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Time Stamp Sub Second Initialize/Increment */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_NTGTM                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_NTGTM_TSTRBUSY          31                               /* Target Time Register Busy */
-#define BITP_EMAC_TM_NTGTM_TSTR               0                               /* Target Time Nano Seconds */
-#define BITM_EMAC_TM_NTGTM_TSTRBUSY          (_ADI_MSK(0x80000000,uint32_t))  /* Target Time Register Busy */
-#define BITM_EMAC_TM_NTGTM_TSTR              (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Target Time Nano Seconds */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_HISEC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_HISEC_TSHWR              0                               /* Time Stamp Higher Word Seconds Register */
-#define BITM_EMAC_TM_HISEC_TSHWR             (_ADI_MSK(0x0000FFFF,uint32_t))  /* Time Stamp Higher Word Seconds Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_STMPSTAT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_STMPSTAT_ATSNS          25                               /* Auxilary Time Stamp Number of Snapshots */
-#define BITP_EMAC_TM_STMPSTAT_ATSSTM         24                               /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITP_EMAC_TM_STMPSTAT_TSTRGTERR       3                               /* Time Stamp Target Time Programming Error */
-#define BITP_EMAC_TM_STMPSTAT_ATSTS           2                               /* Auxilary Time Stamp Trigger Snapshot */
-#define BITP_EMAC_TM_STMPSTAT_TSTARGT         1                               /* Time Stamp Target Time Reached */
-#define BITP_EMAC_TM_STMPSTAT_TSSOVF          0                               /* Time Stamp Seconds Overflow */
-#define BITM_EMAC_TM_STMPSTAT_ATSNS          (_ADI_MSK(0x0E000000,uint32_t))  /* Auxilary Time Stamp Number of Snapshots */
-#define BITM_EMAC_TM_STMPSTAT_ATSSTM         (_ADI_MSK(0x01000000,uint32_t))  /* Auxilary Time Stamp Snapshot Trigger Missed */
-#define BITM_EMAC_TM_STMPSTAT_TSTRGTERR      (_ADI_MSK(0x00000008,uint32_t))  /* Time Stamp Target Time Programming Error */
-#define BITM_EMAC_TM_STMPSTAT_ATSTS          (_ADI_MSK(0x00000004,uint32_t))  /* Auxilary Time Stamp Trigger Snapshot */
-#define BITM_EMAC_TM_STMPSTAT_TSTARGT        (_ADI_MSK(0x00000002,uint32_t))  /* Time Stamp Target Time Reached */
-#define BITM_EMAC_TM_STMPSTAT_TSSOVF         (_ADI_MSK(0x00000001,uint32_t))  /* Time Stamp Seconds Overflow */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_TM_PPSCTL                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_TM_PPSCTL_TRGTMODSEL        5                               /* Target Time Register Mode */
-#define BITP_EMAC_TM_PPSCTL_PPSEN             4                               /* Enable the flexible PPS output mode */
-#define BITP_EMAC_TM_PPSCTL_PPSCTL            0                               /* PPS Frequency Control */
-#define BITM_EMAC_TM_PPSCTL_TRGTMODSEL       (_ADI_MSK(0x00000060,uint32_t))  /* Target Time Register Mode */
-#define BITM_EMAC_TM_PPSCTL_PPSEN            (_ADI_MSK(0x00000010,uint32_t))  /* Enable the flexible PPS output mode */
-#define BITM_EMAC_TM_PPSCTL_PPSCTL           (_ADI_MSK(0x0000000F,uint32_t))  /* PPS Frequency Control */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BUSMODE                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BUSMODE_AAL            25                               /* Address Aligned Bursts */
-#define BITP_EMAC_DMA_BUSMODE_PBL8           24                               /* PBL * 8 */
-#define BITP_EMAC_DMA_BUSMODE_USP            23                               /* Use Separate PBL */
-#define BITP_EMAC_DMA_BUSMODE_RPBL           17                               /* Receive Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_FB             16                               /* Fixed Burst */
-#define BITP_EMAC_DMA_BUSMODE_PBL             8                               /* Programmable Burst Length */
-#define BITP_EMAC_DMA_BUSMODE_ATDS            7                               /* Alternate Descriptor Size */
-#define BITP_EMAC_DMA_BUSMODE_DSL             2                               /* Descriptor Skip Length */
-#define BITP_EMAC_DMA_BUSMODE_SWR             0                               /* Software Reset */
-#define BITM_EMAC_DMA_BUSMODE_AAL            (_ADI_MSK(0x02000000,uint32_t))  /* Address Aligned Bursts */
-#define BITM_EMAC_DMA_BUSMODE_PBL8           (_ADI_MSK(0x01000000,uint32_t))  /* PBL * 8 */
-#define BITM_EMAC_DMA_BUSMODE_USP            (_ADI_MSK(0x00800000,uint32_t))  /* Use Separate PBL */
-#define BITM_EMAC_DMA_BUSMODE_RPBL           (_ADI_MSK(0x007E0000,uint32_t))  /* Receive Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_FB             (_ADI_MSK(0x00010000,uint32_t))  /* Fixed Burst */
-#define BITM_EMAC_DMA_BUSMODE_PBL            (_ADI_MSK(0x00003F00,uint32_t))  /* Programmable Burst Length */
-#define BITM_EMAC_DMA_BUSMODE_ATDS           (_ADI_MSK(0x00000080,uint32_t))  /* Alternate Descriptor Size */
-#define BITM_EMAC_DMA_BUSMODE_DSL            (_ADI_MSK(0x0000007C,uint32_t))  /* Descriptor Skip Length */
-#define BITM_EMAC_DMA_BUSMODE_SWR            (_ADI_MSK(0x00000001,uint32_t))  /* Software Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_STAT_TTI               29                               /* Time Stamp Trigger Interrupt */
-#define BITP_EMAC_DMA_STAT_MCI               27                               /* MAC MMC Interrupt */
-#define BITP_EMAC_DMA_STAT_EB                23                               /* Error Bits */
-#define BITP_EMAC_DMA_STAT_TS                20                               /* Transmit Process State */
-#define BITP_EMAC_DMA_STAT_RS                17                               /* Receive Process State */
-#define BITP_EMAC_DMA_STAT_NIS               16                               /* Normal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_AIS               15                               /* Abnormal Interrupt Summary */
-#define BITP_EMAC_DMA_STAT_ERI               14                               /* Early Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_FBI               13                               /* Fatal Bus Error Interrupt */
-#define BITP_EMAC_DMA_STAT_ETI               10                               /* Early Transmit Interrupt */
-#define BITP_EMAC_DMA_STAT_RWT                9                               /* Receive WatchDog Timeout */
-#define BITP_EMAC_DMA_STAT_RPS                8                               /* Receive Process Stopped */
-#define BITP_EMAC_DMA_STAT_RU                 7                               /* Receive Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_RI                 6                               /* Receive Interrupt */
-#define BITP_EMAC_DMA_STAT_UNF                5                               /* Transmit Buffer Underflow */
-#define BITP_EMAC_DMA_STAT_OVF                4                               /* Receive Buffer Overflow */
-#define BITP_EMAC_DMA_STAT_TJT                3                               /* Transmit Jabber Timeout */
-#define BITP_EMAC_DMA_STAT_TU                 2                               /* Transmit Buffer Unavailable */
-#define BITP_EMAC_DMA_STAT_TPS                1                               /* Transmit Process Stopped */
-#define BITP_EMAC_DMA_STAT_TI                 0                               /* Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_TTI               (_ADI_MSK(0x20000000,uint32_t))  /* Time Stamp Trigger Interrupt */
-#define BITM_EMAC_DMA_STAT_MCI               (_ADI_MSK(0x08000000,uint32_t))  /* MAC MMC Interrupt */
-#define BITM_EMAC_DMA_STAT_EB                (_ADI_MSK(0x03800000,uint32_t))  /* Error Bits */
-
-#define BITM_EMAC_DMA_STAT_TS                (_ADI_MSK(0x00700000,uint32_t))  /* Transmit Process State */
-#define ENUM_EMAC_DMA_STAT_TS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* TS: Stopped; Reset or Stop Transmit Command issued */
-#define ENUM_EMAC_DMA_STAT_TS_R_FTD          (_ADI_MSK(0x00100000,uint32_t))  /* TS: Running; Fetching Transmit Transfer Descriptor */
-#define ENUM_EMAC_DMA_STAT_TS_R_WSTAT        (_ADI_MSK(0x00200000,uint32_t))  /* TS: Running; Waiting for status */
-#define ENUM_EMAC_DMA_STAT_TS_R_TXHMBUF      (_ADI_MSK(0x00300000,uint32_t))  /* TS: Reading Data from host memory buffer and queuing it to TX buffer */
-#define ENUM_EMAC_DMA_STAT_TS_WR_TSTMP       (_ADI_MSK(0x00400000,uint32_t))  /* TS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_TS_SUSPENDED      (_ADI_MSK(0x00600000,uint32_t))  /* TS: Suspended; Transmit Descriptor Unavailable or TX Buffer Underflow */
-#define ENUM_EMAC_DMA_STAT_TS_R_CLSTD        (_ADI_MSK(0x00700000,uint32_t))  /* TS: Closing Transmit Descriptor */
-
-#define BITM_EMAC_DMA_STAT_RS                (_ADI_MSK(0x000E0000,uint32_t))  /* Receive Process State */
-#define ENUM_EMAC_DMA_STAT_RS_STOPPED        (_ADI_MSK(0x00000000,uint32_t))  /* RS: Stopped: Reset or Stop Receive Command issued. */
-#define ENUM_EMAC_DMA_STAT_RS_R_FRD          (_ADI_MSK(0x00020000,uint32_t))  /* RS: Running: Fetching Receive Transfer Descriptor. */
-#define ENUM_EMAC_DMA_STAT_RS_R_WTRX         (_ADI_MSK(0x00060000,uint32_t))  /* RS: Running: Waiting for receive packet */
-#define ENUM_EMAC_DMA_STAT_RS_SUSPENDED      (_ADI_MSK(0x00080000,uint32_t))  /* RS: Suspended: Receive Descriptor Unavailable */
-#define ENUM_EMAC_DMA_STAT_RS_R_CLSRD        (_ADI_MSK(0x000A0000,uint32_t))  /* RS: Running: Closing Receive Descriptor */
-#define ENUM_EMAC_DMA_STAT_RS_WR_TSTMP       (_ADI_MSK(0x000C0000,uint32_t))  /* RS: TIME_STAMP write state */
-#define ENUM_EMAC_DMA_STAT_RS_R_RXWRHM       (_ADI_MSK(0x000E0000,uint32_t))  /* RS: Running: Transferring RX packet data from RX buffer to host memory */
-#define BITM_EMAC_DMA_STAT_NIS               (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_AIS               (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary */
-#define BITM_EMAC_DMA_STAT_ERI               (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_FBI               (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Interrupt */
-#define BITM_EMAC_DMA_STAT_ETI               (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt */
-#define BITM_EMAC_DMA_STAT_RWT               (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchDog Timeout */
-#define BITM_EMAC_DMA_STAT_RPS               (_ADI_MSK(0x00000100,uint32_t))  /* Receive Process Stopped */
-#define BITM_EMAC_DMA_STAT_RU                (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_RI                (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt */
-#define BITM_EMAC_DMA_STAT_UNF               (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Buffer Underflow */
-#define BITM_EMAC_DMA_STAT_OVF               (_ADI_MSK(0x00000010,uint32_t))  /* Receive Buffer Overflow */
-#define BITM_EMAC_DMA_STAT_TJT               (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout */
-#define BITM_EMAC_DMA_STAT_TU                (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable */
-#define BITM_EMAC_DMA_STAT_TPS               (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Process Stopped */
-#define BITM_EMAC_DMA_STAT_TI                (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_OPMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_OPMODE_DT              26                               /* Disable Dropping TCP/IP Errors */
-#define BITP_EMAC_DMA_OPMODE_RSF             25                               /* Receive Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_DFF             24                               /* Disable Flushing of received Frames */
-#define BITP_EMAC_DMA_OPMODE_TSF             21                               /* Transmit Store and Forward */
-#define BITP_EMAC_DMA_OPMODE_FTF             20                               /* Flush Transmit FIFO */
-#define BITP_EMAC_DMA_OPMODE_TTC             14                               /* Transmit Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_ST              13                               /* Start/Stop Transmission */
-#define BITP_EMAC_DMA_OPMODE_FEF              7                               /* Forward Error Frames */
-#define BITP_EMAC_DMA_OPMODE_FUF              6                               /* Forward Undersized good Frames */
-#define BITP_EMAC_DMA_OPMODE_RTC              3                               /* Receive Threshold Control */
-#define BITP_EMAC_DMA_OPMODE_OSF              2                               /* Operate on Second Frame */
-#define BITP_EMAC_DMA_OPMODE_SR               1                               /* Start/Stop Receive */
-#define BITM_EMAC_DMA_OPMODE_DT              (_ADI_MSK(0x04000000,uint32_t))  /* Disable Dropping TCP/IP Errors */
-#define BITM_EMAC_DMA_OPMODE_RSF             (_ADI_MSK(0x02000000,uint32_t))  /* Receive Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_DFF             (_ADI_MSK(0x01000000,uint32_t))  /* Disable Flushing of received Frames */
-#define BITM_EMAC_DMA_OPMODE_TSF             (_ADI_MSK(0x00200000,uint32_t))  /* Transmit Store and Forward */
-#define BITM_EMAC_DMA_OPMODE_FTF             (_ADI_MSK(0x00100000,uint32_t))  /* Flush Transmit FIFO */
-
-#define BITM_EMAC_DMA_OPMODE_TTC             (_ADI_MSK(0x0001C000,uint32_t))  /* Transmit Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_TTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* TTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_128         (_ADI_MSK(0x00004000,uint32_t))  /* TTC: 128 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_192         (_ADI_MSK(0x00008000,uint32_t))  /* TTC: 192 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_256         (_ADI_MSK(0x0000C000,uint32_t))  /* TTC: 256 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_40          (_ADI_MSK(0x00010000,uint32_t))  /* TTC: 40 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_32          (_ADI_MSK(0x00014000,uint32_t))  /* TTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_24          (_ADI_MSK(0x00018000,uint32_t))  /* TTC: 24 */
-#define ENUM_EMAC_DMA_OPMODE_TTC_16          (_ADI_MSK(0x0001C000,uint32_t))  /* TTC: 16 */
-#define BITM_EMAC_DMA_OPMODE_ST              (_ADI_MSK(0x00002000,uint32_t))  /* Start/Stop Transmission */
-#define BITM_EMAC_DMA_OPMODE_FEF             (_ADI_MSK(0x00000080,uint32_t))  /* Forward Error Frames */
-#define BITM_EMAC_DMA_OPMODE_FUF             (_ADI_MSK(0x00000040,uint32_t))  /* Forward Undersized good Frames */
-
-#define BITM_EMAC_DMA_OPMODE_RTC             (_ADI_MSK(0x00000018,uint32_t))  /* Receive Threshold Control */
-#define ENUM_EMAC_DMA_OPMODE_RTC_64          (_ADI_MSK(0x00000000,uint32_t))  /* RTC: 64 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_32          (_ADI_MSK(0x00000008,uint32_t))  /* RTC: 32 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_96          (_ADI_MSK(0x00000010,uint32_t))  /* RTC: 96 */
-#define ENUM_EMAC_DMA_OPMODE_RTC_128         (_ADI_MSK(0x00000018,uint32_t))  /* RTC: 128 */
-#define BITM_EMAC_DMA_OPMODE_OSF             (_ADI_MSK(0x00000004,uint32_t))  /* Operate on Second Frame */
-#define BITM_EMAC_DMA_OPMODE_SR              (_ADI_MSK(0x00000002,uint32_t))  /* Start/Stop Receive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_IEN                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_IEN_NIS                16                               /* Normal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_AIS                15                               /* Abnormal Interrupt Summary Enable */
-#define BITP_EMAC_DMA_IEN_ERI                14                               /* Early Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_FBI                13                               /* Fatal Bus Error Enable */
-#define BITP_EMAC_DMA_IEN_ETI                10                               /* Early Transmit Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_RWT                 9                               /* Receive WatchdogTimeout Enable */
-#define BITP_EMAC_DMA_IEN_RPS                 8                               /* Receive Stopped Enable */
-#define BITP_EMAC_DMA_IEN_RU                  7                               /* Receive Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_RI                  6                               /* Receive Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_UNF                 5                               /* Underflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_OVF                 4                               /* Overflow Interrupt Enable */
-#define BITP_EMAC_DMA_IEN_TJT                 3                               /* Transmit Jabber Timeout Enable */
-#define BITP_EMAC_DMA_IEN_TU                  2                               /* Transmit Buffer Unavailable Enable */
-#define BITP_EMAC_DMA_IEN_TPS                 1                               /* Transmit Stopped Enable */
-#define BITP_EMAC_DMA_IEN_TI                  0                               /* Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_NIS                (_ADI_MSK(0x00010000,uint32_t))  /* Normal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_AIS                (_ADI_MSK(0x00008000,uint32_t))  /* Abnormal Interrupt Summary Enable */
-#define BITM_EMAC_DMA_IEN_ERI                (_ADI_MSK(0x00004000,uint32_t))  /* Early Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_FBI                (_ADI_MSK(0x00002000,uint32_t))  /* Fatal Bus Error Enable */
-#define BITM_EMAC_DMA_IEN_ETI                (_ADI_MSK(0x00000400,uint32_t))  /* Early Transmit Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_RWT                (_ADI_MSK(0x00000200,uint32_t))  /* Receive WatchdogTimeout Enable */
-#define BITM_EMAC_DMA_IEN_RPS                (_ADI_MSK(0x00000100,uint32_t))  /* Receive Stopped Enable */
-#define BITM_EMAC_DMA_IEN_RU                 (_ADI_MSK(0x00000080,uint32_t))  /* Receive Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_RI                 (_ADI_MSK(0x00000040,uint32_t))  /* Receive Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_UNF                (_ADI_MSK(0x00000020,uint32_t))  /* Underflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_OVF                (_ADI_MSK(0x00000010,uint32_t))  /* Overflow Interrupt Enable */
-#define BITM_EMAC_DMA_IEN_TJT                (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Jabber Timeout Enable */
-#define BITM_EMAC_DMA_IEN_TU                 (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Buffer Unavailable Enable */
-#define BITM_EMAC_DMA_IEN_TPS                (_ADI_MSK(0x00000002,uint32_t))  /* Transmit Stopped Enable */
-#define BITM_EMAC_DMA_IEN_TI                 (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_MISS_FRM                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_MISS_FRM_OVFFIFO       28                               /* Overflow bit for FIFO Overflow Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFROV      17                               /* Missed Frames Buffer Overflow */
-#define BITP_EMAC_DMA_MISS_FRM_OVFMISS       16                               /* Overflow bit for Missed Frame Counter */
-#define BITP_EMAC_DMA_MISS_FRM_MISSFRUN       0                               /* Missed Frames Unavailable Buffer */
-#define BITM_EMAC_DMA_MISS_FRM_OVFFIFO       (_ADI_MSK(0x10000000,uint32_t))  /* Overflow bit for FIFO Overflow Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFROV      (_ADI_MSK(0x0FFE0000,uint32_t))  /* Missed Frames Buffer Overflow */
-#define BITM_EMAC_DMA_MISS_FRM_OVFMISS       (_ADI_MSK(0x00010000,uint32_t))  /* Overflow bit for Missed Frame Counter */
-#define BITM_EMAC_DMA_MISS_FRM_MISSFRUN      (_ADI_MSK(0x0000FFFF,uint32_t))  /* Missed Frames Unavailable Buffer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_RXIWDOG                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_RXIWDOG_RIWT            0                               /* RI WatchDog Timer Count */
-#define BITM_EMAC_DMA_RXIWDOG_RIWT           (_ADI_MSK(0x000000FF,uint32_t))  /* RI WatchDog Timer Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMMODE                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMMODE_WROSRLMT        20                               /* SCB Maximum Write Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_RDOSRLMT        16                               /* SCB Maximum Read Outstanding Request */
-#define BITP_EMAC_DMA_BMMODE_AAL             12                               /* Address Aligned Beats */
-#define BITP_EMAC_DMA_BMMODE_BLEN16           3                               /* SCB Burst Length 16 */
-#define BITP_EMAC_DMA_BMMODE_BLEN8            2                               /* SCB Burst Length 8 */
-#define BITP_EMAC_DMA_BMMODE_BLEN4            1                               /* SCB Burst Length 4 */
-#define BITP_EMAC_DMA_BMMODE_UNDEF            0                               /* SCB Undefined Burst Length */
-#define BITM_EMAC_DMA_BMMODE_WROSRLMT        (_ADI_MSK(0x00700000,uint32_t))  /* SCB Maximum Write Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_RDOSRLMT        (_ADI_MSK(0x00070000,uint32_t))  /* SCB Maximum Read Outstanding Request */
-#define BITM_EMAC_DMA_BMMODE_AAL             (_ADI_MSK(0x00001000,uint32_t))  /* Address Aligned Beats */
-#define BITM_EMAC_DMA_BMMODE_BLEN16          (_ADI_MSK(0x00000008,uint32_t))  /* SCB Burst Length 16 */
-#define BITM_EMAC_DMA_BMMODE_BLEN8           (_ADI_MSK(0x00000004,uint32_t))  /* SCB Burst Length 8 */
-#define BITM_EMAC_DMA_BMMODE_BLEN4           (_ADI_MSK(0x00000002,uint32_t))  /* SCB Burst Length 4 */
-#define BITM_EMAC_DMA_BMMODE_UNDEF           (_ADI_MSK(0x00000001,uint32_t))  /* SCB Undefined Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        EMAC_DMA_BMSTAT                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EMAC_DMA_BMSTAT_BUSRD            1                               /* Bus (SCB master) Read Active */
-#define BITP_EMAC_DMA_BMSTAT_BUSWR            0                               /* Bus (SCB master) Write Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSRD           (_ADI_MSK(0x00000002,uint32_t))  /* Bus (SCB master) Read Active */
-#define BITM_EMAC_DMA_BMSTAT_BUSWR           (_ADI_MSK(0x00000001,uint32_t))  /* Bus (SCB master) Write Active */
-
-/* ==================================================
-        Serial Port Registers
-   ================================================== */
-
-/* =========================
-        SPORT0
-   ========================= */
-#define REG_SPORT0_CTL_A                0xFFC40000         /* SPORT0 Half SPORT 'A' Control Register */
-#define REG_SPORT0_DIV_A                0xFFC40004         /* SPORT0 Half SPORT 'A' Divisor Register */
-#define REG_SPORT0_MCTL_A               0xFFC40008         /* SPORT0 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT0_CS0_A                0xFFC4000C         /* SPORT0 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_A                0xFFC40010         /* SPORT0 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_A                0xFFC40014         /* SPORT0 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT0_CS3_A                0xFFC40018         /* SPORT0 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT0_ERR_A                0xFFC40020         /* SPORT0 Half SPORT 'A' Error Register */
-#define REG_SPORT0_MSTAT_A              0xFFC40024         /* SPORT0 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_A               0xFFC40028         /* SPORT0 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT0_TXPRI_A              0xFFC40040         /* SPORT0 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_A              0xFFC40044         /* SPORT0 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_A              0xFFC40048         /* SPORT0 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_A              0xFFC4004C         /* SPORT0 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT0_CTL_B                0xFFC40080         /* SPORT0 Half SPORT 'B' Control Register */
-#define REG_SPORT0_DIV_B                0xFFC40084         /* SPORT0 Half SPORT 'B' Divisor Register */
-#define REG_SPORT0_MCTL_B               0xFFC40088         /* SPORT0 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT0_CS0_B                0xFFC4008C         /* SPORT0 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT0_CS1_B                0xFFC40090         /* SPORT0 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT0_CS2_B                0xFFC40094         /* SPORT0 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT0_CS3_B                0xFFC40098         /* SPORT0 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT0_ERR_B                0xFFC400A0         /* SPORT0 Half SPORT 'B' Error Register */
-#define REG_SPORT0_MSTAT_B              0xFFC400A4         /* SPORT0 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT0_CTL2_B               0xFFC400A8         /* SPORT0 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT0_TXPRI_B              0xFFC400C0         /* SPORT0 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT0_RXPRI_B              0xFFC400C4         /* SPORT0 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT0_TXSEC_B              0xFFC400C8         /* SPORT0 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT0_RXSEC_B              0xFFC400CC         /* SPORT0 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT1
-   ========================= */
-#define REG_SPORT1_CTL_A                0xFFC40100         /* SPORT1 Half SPORT 'A' Control Register */
-#define REG_SPORT1_DIV_A                0xFFC40104         /* SPORT1 Half SPORT 'A' Divisor Register */
-#define REG_SPORT1_MCTL_A               0xFFC40108         /* SPORT1 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT1_CS0_A                0xFFC4010C         /* SPORT1 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_A                0xFFC40110         /* SPORT1 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_A                0xFFC40114         /* SPORT1 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT1_CS3_A                0xFFC40118         /* SPORT1 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT1_ERR_A                0xFFC40120         /* SPORT1 Half SPORT 'A' Error Register */
-#define REG_SPORT1_MSTAT_A              0xFFC40124         /* SPORT1 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_A               0xFFC40128         /* SPORT1 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT1_TXPRI_A              0xFFC40140         /* SPORT1 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_A              0xFFC40144         /* SPORT1 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_A              0xFFC40148         /* SPORT1 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_A              0xFFC4014C         /* SPORT1 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT1_CTL_B                0xFFC40180         /* SPORT1 Half SPORT 'B' Control Register */
-#define REG_SPORT1_DIV_B                0xFFC40184         /* SPORT1 Half SPORT 'B' Divisor Register */
-#define REG_SPORT1_MCTL_B               0xFFC40188         /* SPORT1 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT1_CS0_B                0xFFC4018C         /* SPORT1 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT1_CS1_B                0xFFC40190         /* SPORT1 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT1_CS2_B                0xFFC40194         /* SPORT1 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT1_CS3_B                0xFFC40198         /* SPORT1 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT1_ERR_B                0xFFC401A0         /* SPORT1 Half SPORT 'B' Error Register */
-#define REG_SPORT1_MSTAT_B              0xFFC401A4         /* SPORT1 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT1_CTL2_B               0xFFC401A8         /* SPORT1 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT1_TXPRI_B              0xFFC401C0         /* SPORT1 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT1_RXPRI_B              0xFFC401C4         /* SPORT1 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT1_TXSEC_B              0xFFC401C8         /* SPORT1 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT1_RXSEC_B              0xFFC401CC         /* SPORT1 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT2
-   ========================= */
-#define REG_SPORT2_CTL_A                0xFFC40200         /* SPORT2 Half SPORT 'A' Control Register */
-#define REG_SPORT2_DIV_A                0xFFC40204         /* SPORT2 Half SPORT 'A' Divisor Register */
-#define REG_SPORT2_MCTL_A               0xFFC40208         /* SPORT2 Half SPORT 'A' Multi-channel Control Register */
-#define REG_SPORT2_CS0_A                0xFFC4020C         /* SPORT2 Half SPORT 'A' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_A                0xFFC40210         /* SPORT2 Half SPORT 'A' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_A                0xFFC40214         /* SPORT2 Half SPORT 'A' Multi-channel 64-95 Select Register */
-#define REG_SPORT2_CS3_A                0xFFC40218         /* SPORT2 Half SPORT 'A' Multi-channel 96-127 Select Register */
-#define REG_SPORT2_ERR_A                0xFFC40220         /* SPORT2 Half SPORT 'A' Error Register */
-#define REG_SPORT2_MSTAT_A              0xFFC40224         /* SPORT2 Half SPORT 'A' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_A               0xFFC40228         /* SPORT2 Half SPORT 'A' Control 2 Register */
-#define REG_SPORT2_TXPRI_A              0xFFC40240         /* SPORT2 Half SPORT 'A' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_A              0xFFC40244         /* SPORT2 Half SPORT 'A' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_A              0xFFC40248         /* SPORT2 Half SPORT 'A' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_A              0xFFC4024C         /* SPORT2 Half SPORT 'A' Rx Buffer (Secondary) Register */
-#define REG_SPORT2_CTL_B                0xFFC40280         /* SPORT2 Half SPORT 'B' Control Register */
-#define REG_SPORT2_DIV_B                0xFFC40284         /* SPORT2 Half SPORT 'B' Divisor Register */
-#define REG_SPORT2_MCTL_B               0xFFC40288         /* SPORT2 Half SPORT 'B' Multi-channel Control Register */
-#define REG_SPORT2_CS0_B                0xFFC4028C         /* SPORT2 Half SPORT 'B' Multi-channel 0-31 Select Register */
-#define REG_SPORT2_CS1_B                0xFFC40290         /* SPORT2 Half SPORT 'B' Multi-channel 32-63 Select Register */
-#define REG_SPORT2_CS2_B                0xFFC40294         /* SPORT2 Half SPORT 'B' Multichannel 64-95 Select Register */
-#define REG_SPORT2_CS3_B                0xFFC40298         /* SPORT2 Half SPORT 'B' Multichannel 96-127 Select Register */
-#define REG_SPORT2_ERR_B                0xFFC402A0         /* SPORT2 Half SPORT 'B' Error Register */
-#define REG_SPORT2_MSTAT_B              0xFFC402A4         /* SPORT2 Half SPORT 'B' Multi-channel Status Register */
-#define REG_SPORT2_CTL2_B               0xFFC402A8         /* SPORT2 Half SPORT 'B' Control 2 Register */
-#define REG_SPORT2_TXPRI_B              0xFFC402C0         /* SPORT2 Half SPORT 'B' Tx Buffer (Primary) Register */
-#define REG_SPORT2_RXPRI_B              0xFFC402C4         /* SPORT2 Half SPORT 'B' Rx Buffer (Primary) Register */
-#define REG_SPORT2_TXSEC_B              0xFFC402C8         /* SPORT2 Half SPORT 'B' Tx Buffer (Secondary) Register */
-#define REG_SPORT2_RXSEC_B              0xFFC402CC         /* SPORT2 Half SPORT 'B' Rx Buffer (Secondary) Register */
-
-/* =========================
-        SPORT
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_A_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_DXSPRI                30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_A_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_DERRPRI               29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_A_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_DXSSEC                27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_A_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_DERRSEC               26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_A_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_SPTRAN                25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_A_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_SPENSEC               24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_A_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_GCLKEN                21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_A_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_TFIEN                 20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_A_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_FSED                  19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_A_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_RJUST                 18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_A_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_LAFS                  17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_A_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_LFS                   16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_A_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_DIFS                  15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_A_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_IFS                   14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_A_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_FSR                   13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_A_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_CKRE                  12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_A_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_OPMODE                11                               /* Operation mode */
-#define BITP_SPORT_CTL_A_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_ICLK                  10                               /* Internal Clock */
-#define BITP_SPORT_CTL_A_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_PACK                   9                               /* Packing Enable */
-#define BITP_SPORT_CTL_A_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_SLEN                   4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_A_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_LSBF                   3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_A_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_DTYPE                  1                               /* Data Type */
-#define BITP_SPORT_CTL_A_SPENPRI              0                               /* Serial Port Enable (Primary) */
-#define BITP_SPORT_CTL_SPENPRI                0                               /* Serial Port Enable (Primary) */
-
-#define BITM_SPORT_CTL_A_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_DXSPRI                (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSPRI: Empty */
-#define ENUM_SPORT_CTL_PRM_PART_FULL         (_ADI_MSK(0x80000000,uint32_t))  /* DXSPRI: Partially full */
-#define ENUM_SPORT_CTL_PRM_FULL              (_ADI_MSK(0xC0000000,uint32_t))  /* DXSPRI: Full */
-
-#define BITM_SPORT_CTL_A_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_DERRPRI               (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define ENUM_SPORT_CTL_PRM_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRPRI: No error */
-#define ENUM_SPORT_CTL_PRM_ERR               (_ADI_MSK(0x20000000,uint32_t))  /* DERRPRI: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_DXSSEC                (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_EMPTY             (_ADI_MSK(0x00000000,uint32_t))  /* DXSSEC: Empty */
-#define ENUM_SPORT_CTL_SEC_PART_FULL         (_ADI_MSK(0x10000000,uint32_t))  /* DXSSEC: Partially full */
-#define ENUM_SPORT_CTL_SEC_FULL              (_ADI_MSK(0x18000000,uint32_t))  /* DXSSEC: Full */
-
-#define BITM_SPORT_CTL_A_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_DERRSEC               (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define ENUM_SPORT_CTL_SEC_NO_ERR            (_ADI_MSK(0x00000000,uint32_t))  /* DERRSEC: No error */
-#define ENUM_SPORT_CTL_SEC_ERR               (_ADI_MSK(0x04000000,uint32_t))  /* DERRSEC: Error (Tx underflow or Rx overflow) */
-
-#define BITM_SPORT_CTL_A_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_SPTRAN                (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define ENUM_SPORT_CTL_RX                    (_ADI_MSK(0x00000000,uint32_t))  /* SPTRAN: Receive */
-#define ENUM_SPORT_CTL_TX                    (_ADI_MSK(0x02000000,uint32_t))  /* SPTRAN: Transmit */
-
-#define BITM_SPORT_CTL_A_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_SPENSEC               (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define ENUM_SPORT_CTL_SECONDARY_DIS         (_ADI_MSK(0x00000000,uint32_t))  /* SPENSEC: Disable */
-#define ENUM_SPORT_CTL_SECONDARY_EN          (_ADI_MSK(0x01000000,uint32_t))  /* SPENSEC: Enable */
-
-#define BITM_SPORT_CTL_A_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_GCLKEN                (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define ENUM_SPORT_CTL_GCLK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* GCLKEN: Disable */
-#define ENUM_SPORT_CTL_GCLK_EN               (_ADI_MSK(0x00200000,uint32_t))  /* GCLKEN: Enable */
-
-#define BITM_SPORT_CTL_A_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_TFIEN                 (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define ENUM_SPORT_CTL_TXFIN_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TFIEN: Last word sent (DMA count done) interrupt */
-#define ENUM_SPORT_CTL_TXFIN_EN              (_ADI_MSK(0x00100000,uint32_t))  /* TFIEN: Last bit sent (Tx buffer done) interrupt */
-
-#define BITM_SPORT_CTL_A_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_FSED                  (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define ENUM_SPORT_CTL_LEVEL_FS              (_ADI_MSK(0x00000000,uint32_t))  /* FSED: Level detect frame sync */
-#define ENUM_SPORT_CTL_EDGE_FS               (_ADI_MSK(0x00080000,uint32_t))  /* FSED: Edge detect frame sync */
-
-#define BITM_SPORT_CTL_A_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_RJUST                 (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define ENUM_SPORT_CTL_RJUST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* RJUST: Disable */
-#define ENUM_SPORT_CTL_RJUST_EN              (_ADI_MSK(0x00040000,uint32_t))  /* RJUST: Enable */
-
-#define BITM_SPORT_CTL_A_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_LAFS                  (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define ENUM_SPORT_CTL_EARLY_FS              (_ADI_MSK(0x00000000,uint32_t))  /* LAFS: Early frame sync */
-#define ENUM_SPORT_CTL_LATE_FS               (_ADI_MSK(0x00020000,uint32_t))  /* LAFS: Late frame sync */
-
-#define BITM_SPORT_CTL_A_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_LFS                   (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define ENUM_SPORT_CTL_FS_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* LFS: Active high frame sync (DSP standard mode) */
-#define ENUM_SPORT_CTL_FS_HI                 (_ADI_MSK(0x00010000,uint32_t))  /* LFS: Active low frame sync (DSP standard mode) */
-
-#define BITM_SPORT_CTL_A_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_DIFS                  (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define ENUM_SPORT_CTL_DATA_DEP_FS           (_ADI_MSK(0x00000000,uint32_t))  /* DIFS: Data-dependent frame sync */
-#define ENUM_SPORT_CTL_DATA_INDP_FS          (_ADI_MSK(0x00008000,uint32_t))  /* DIFS: Data-independent frame sync */
-
-#define BITM_SPORT_CTL_A_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_IFS                   (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define ENUM_SPORT_CTL_EXTERNAL_FS           (_ADI_MSK(0x00000000,uint32_t))  /* IFS: External frame sync */
-#define ENUM_SPORT_CTL_INTERNAL_FS           (_ADI_MSK(0x00004000,uint32_t))  /* IFS: Internal frame sync */
-
-#define BITM_SPORT_CTL_A_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_FSR                   (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define ENUM_SPORT_CTL_FS_NOT_REQ            (_ADI_MSK(0x00000000,uint32_t))  /* FSR: No frame sync required */
-#define ENUM_SPORT_CTL_FS_REQ                (_ADI_MSK(0x00002000,uint32_t))  /* FSR: Frame sync required */
-
-#define BITM_SPORT_CTL_A_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_CKRE                  (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define ENUM_SPORT_CTL_CLK_FALL_EDGE         (_ADI_MSK(0x00000000,uint32_t))  /* CKRE: Clock falling edge */
-#define ENUM_SPORT_CTL_CLK_RISE_EDGE         (_ADI_MSK(0x00001000,uint32_t))  /* CKRE: Clock rising edge */
-
-#define BITM_SPORT_CTL_A_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_OPMODE                (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define ENUM_SPORT_CTL_SERIAL_MC_MODE        (_ADI_MSK(0x00000000,uint32_t))  /* OPMODE: DSP standard/multi-channel mode */
-#define ENUM_SPORT_CTL_I2S_MODE              (_ADI_MSK(0x00000800,uint32_t))  /* OPMODE: I2S/packed/left-justified mode */
-
-#define BITM_SPORT_CTL_A_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_ICLK                  (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define ENUM_SPORT_CTL_EXTERNAL_CLK          (_ADI_MSK(0x00000000,uint32_t))  /* ICLK: External clock */
-#define ENUM_SPORT_CTL_INTERNAL_CLK          (_ADI_MSK(0x00000400,uint32_t))  /* ICLK: Internal clock */
-
-#define BITM_SPORT_CTL_A_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_PACK                  (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define ENUM_SPORT_CTL_PACK_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* PACK: Disable */
-#define ENUM_SPORT_CTL_PACK_EN               (_ADI_MSK(0x00000200,uint32_t))  /* PACK: Enable */
-#define BITM_SPORT_CTL_A_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_SLEN                  (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-
-#define BITM_SPORT_CTL_A_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_LSBF                  (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define ENUM_SPORT_CTL_MSB_FIRST             (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB first sent/received (big endian) */
-#define ENUM_SPORT_CTL_LSB_FIRST             (_ADI_MSK(0x00000008,uint32_t))  /* LSBF: LSB first sent/received (little endian) */
-
-#define BITM_SPORT_CTL_A_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_DTYPE                 (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define ENUM_SPORT_CTL_RJUSTIFY_ZFILL        (_ADI_MSK(0x00000000,uint32_t))  /* DTYPE: Right-justify data, zero-fill unused MSBs */
-#define ENUM_SPORT_CTL_RJUSTIFY_SFILL        (_ADI_MSK(0x00000002,uint32_t))  /* DTYPE: Right-justify data, sign-extend unused MSBs */
-#define ENUM_SPORT_CTL_USE_U_LAW             (_ADI_MSK(0x00000004,uint32_t))  /* DTYPE: m-law compand data */
-#define ENUM_SPORT_CTL_USE_A_LAW             (_ADI_MSK(0x00000006,uint32_t))  /* DTYPE: A-law compand data */
-
-#define BITM_SPORT_CTL_A_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define BITM_SPORT_CTL_SPENPRI               (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-#define ENUM_SPORT_CTL_DIS                   (_ADI_MSK(0x00000000,uint32_t))  /* SPENPRI: Disable */
-#define ENUM_SPORT_CTL_EN                    (_ADI_MSK(0x00000001,uint32_t))  /* SPENPRI: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_A_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_FSDIV                 16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_A_CLKDIV               0                               /* Clock Divisor */
-#define BITP_SPORT_DIV_CLKDIV                 0                               /* Clock Divisor */
-#define BITM_SPORT_DIV_A_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_FSDIV                 (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_A_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-#define BITM_SPORT_DIV_CLKDIV                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_A_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_WOFFSET              16                               /* Window Offset */
-#define BITP_SPORT_MCTL_A_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_WSIZE                 8                               /* Window Size */
-#define BITP_SPORT_MCTL_A_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_MFD                   4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_A_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_MCPDE                 2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_A_MCE                 0                               /* Multichannel enable */
-#define BITP_SPORT_MCTL_MCE                   0                               /* Multichannel enable */
-#define BITM_SPORT_MCTL_A_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_WOFFSET              (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_A_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_WSIZE                (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_A_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_MFD                  (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-
-#define BITM_SPORT_MCTL_A_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_MCPDE                (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define ENUM_SPORT_MCTL_MCPD_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* MCPDE: Disable */
-#define ENUM_SPORT_MCTL_MCPD_EN              (_ADI_MSK(0x00000004,uint32_t))  /* MCPDE: Enable */
-
-#define BITM_SPORT_MCTL_A_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define BITM_SPORT_MCTL_MCE                  (_ADI_MSK(0x00000001,uint32_t))  /* Multichannel enable */
-#define ENUM_SPORT_MCTL_DIS                  (_ADI_MSK(0x00000000,uint32_t))  /* MCE: Disable */
-#define ENUM_SPORT_MCTL_EN                   (_ADI_MSK(0x00000001,uint32_t))  /* MCE: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_A                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_A_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_FSERRSTAT              6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_A_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_DERRSSTAT              5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_A_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_DERRPSTAT              4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_A_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_FSERRMSK               2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRSMSK               1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_A_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-#define BITP_SPORT_ERR_DERRPMSK               0                               /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_FSERRSTAT             (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_A_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_DERRSSTAT             (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_A_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_DERRPSTAT             (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_A_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_FSERRMSK              (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRSMSK              (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_A_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-#define BITM_SPORT_ERR_DERRPMSK              (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_A                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_A_CURCHAN            0                               /* Current Channel */
-#define BITP_SPORT_MSTAT_CURCHAN              0                               /* Current Channel */
-#define BITM_SPORT_MSTAT_A_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-#define BITM_SPORT_MSTAT_CURCHAN             (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_A                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_A_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_CKMUXSEL              1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_A_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-#define BITP_SPORT_CTL2_FSMUXSEL              0                               /* Frame Sync Multiplexer Select */
-
-#define BITM_SPORT_CTL2_A_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_CKMUXSEL             (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define ENUM_SPORT_CTL2_CLK_MUX_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* CKMUXSEL: Disable serial clock multiplexing */
-#define ENUM_SPORT_CTL2_CLK_MUX_EN           (_ADI_MSK(0x00000002,uint32_t))  /* CKMUXSEL: Enable serial clock multiplexing */
-
-#define BITM_SPORT_CTL2_A_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define BITM_SPORT_CTL2_FSMUXSEL             (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-#define ENUM_SPORT_CTL2_FS_MUX_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* FSMUXSEL: Disable frame sync multiplexing */
-#define ENUM_SPORT_CTL2_FS_MUX_EN            (_ADI_MSK(0x00000001,uint32_t))  /* FSMUXSEL: Enable frame sync multiplexing */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL_B_DXSPRI              30                               /* Data Transfer Buffer Status (Primary) */
-#define BITP_SPORT_CTL_B_DERRPRI             29                               /* Data Error Status (Primary) */
-#define BITP_SPORT_CTL_B_DXSSEC              27                               /* Data Transfer Buffer Status (Secondary) */
-#define BITP_SPORT_CTL_B_DERRSEC             26                               /* Data Error Status (Secondary) */
-#define BITP_SPORT_CTL_B_SPTRAN              25                               /* Serial Port Transfer Direction */
-#define BITP_SPORT_CTL_B_SPENSEC             24                               /* Serial Port Enable (Secondary) */
-#define BITP_SPORT_CTL_B_GCLKEN              21                               /* Gated Clock Enable */
-#define BITP_SPORT_CTL_B_TFIEN               20                               /* Transmit Finish Interrupt Enable */
-#define BITP_SPORT_CTL_B_FSED                19                               /* Frame Sync Edge Detect */
-#define BITP_SPORT_CTL_B_RJUST               18                               /* Right-Justified Operation Mode */
-#define BITP_SPORT_CTL_B_LAFS                17                               /* Late Frame Sync / OPMODE2 */
-#define BITP_SPORT_CTL_B_LFS                 16                               /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITP_SPORT_CTL_B_DIFS                15                               /* Data-Independent Frame Sync */
-#define BITP_SPORT_CTL_B_IFS                 14                               /* Internal Frame Sync */
-#define BITP_SPORT_CTL_B_FSR                 13                               /* Frame Sync Required */
-#define BITP_SPORT_CTL_B_CKRE                12                               /* Clock Rising Edge */
-#define BITP_SPORT_CTL_B_OPMODE              11                               /* Operation mode */
-#define BITP_SPORT_CTL_B_ICLK                10                               /* Internal Clock */
-#define BITP_SPORT_CTL_B_PACK                 9                               /* Packing Enable */
-#define BITP_SPORT_CTL_B_SLEN                 4                               /* Serial Word Length */
-#define BITP_SPORT_CTL_B_LSBF                 3                               /* Least-Significant Bit First */
-#define BITP_SPORT_CTL_B_DTYPE                1                               /* Data Type */
-#define BITP_SPORT_CTL_B_SPENPRI              0                               /* Serial Port Enable (Primary) */
-
-/* The fields and enumerations for SPORT_CTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL_A */
-
-#define BITM_SPORT_CTL_B_DXSPRI              (_ADI_MSK(0xC0000000,uint32_t))  /* Data Transfer Buffer Status (Primary) */
-#define BITM_SPORT_CTL_B_DERRPRI             (_ADI_MSK(0x20000000,uint32_t))  /* Data Error Status (Primary) */
-#define BITM_SPORT_CTL_B_DXSSEC              (_ADI_MSK(0x18000000,uint32_t))  /* Data Transfer Buffer Status (Secondary) */
-#define BITM_SPORT_CTL_B_DERRSEC             (_ADI_MSK(0x04000000,uint32_t))  /* Data Error Status (Secondary) */
-#define BITM_SPORT_CTL_B_SPTRAN              (_ADI_MSK(0x02000000,uint32_t))  /* Serial Port Transfer Direction */
-#define BITM_SPORT_CTL_B_SPENSEC             (_ADI_MSK(0x01000000,uint32_t))  /* Serial Port Enable (Secondary) */
-#define BITM_SPORT_CTL_B_GCLKEN              (_ADI_MSK(0x00200000,uint32_t))  /* Gated Clock Enable */
-#define BITM_SPORT_CTL_B_TFIEN               (_ADI_MSK(0x00100000,uint32_t))  /* Transmit Finish Interrupt Enable */
-#define BITM_SPORT_CTL_B_FSED                (_ADI_MSK(0x00080000,uint32_t))  /* Frame Sync Edge Detect */
-#define BITM_SPORT_CTL_B_RJUST               (_ADI_MSK(0x00040000,uint32_t))  /* Right-Justified Operation Mode */
-#define BITM_SPORT_CTL_B_LAFS                (_ADI_MSK(0x00020000,uint32_t))  /* Late Frame Sync / OPMODE2 */
-#define BITM_SPORT_CTL_B_LFS                 (_ADI_MSK(0x00010000,uint32_t))  /* Active-Low Frame Sync / L_FIRST / PLFS */
-#define BITM_SPORT_CTL_B_DIFS                (_ADI_MSK(0x00008000,uint32_t))  /* Data-Independent Frame Sync */
-#define BITM_SPORT_CTL_B_IFS                 (_ADI_MSK(0x00004000,uint32_t))  /* Internal Frame Sync */
-#define BITM_SPORT_CTL_B_FSR                 (_ADI_MSK(0x00002000,uint32_t))  /* Frame Sync Required */
-#define BITM_SPORT_CTL_B_CKRE                (_ADI_MSK(0x00001000,uint32_t))  /* Clock Rising Edge */
-#define BITM_SPORT_CTL_B_OPMODE              (_ADI_MSK(0x00000800,uint32_t))  /* Operation mode */
-#define BITM_SPORT_CTL_B_ICLK                (_ADI_MSK(0x00000400,uint32_t))  /* Internal Clock */
-#define BITM_SPORT_CTL_B_PACK                (_ADI_MSK(0x00000200,uint32_t))  /* Packing Enable */
-#define BITM_SPORT_CTL_B_SLEN                (_ADI_MSK(0x000001F0,uint32_t))  /* Serial Word Length */
-#define BITM_SPORT_CTL_B_LSBF                (_ADI_MSK(0x00000008,uint32_t))  /* Least-Significant Bit First */
-#define BITM_SPORT_CTL_B_DTYPE               (_ADI_MSK(0x00000006,uint32_t))  /* Data Type */
-#define BITM_SPORT_CTL_B_SPENPRI             (_ADI_MSK(0x00000001,uint32_t))  /* Serial Port Enable (Primary) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_DIV_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_DIV_B_FSDIV               16                               /* Frame Sync Divisor */
-#define BITP_SPORT_DIV_B_CLKDIV               0                               /* Clock Divisor */
-
-/* The fields and enumerations for SPORT_DIV_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_DIV_A */
-
-#define BITM_SPORT_DIV_B_FSDIV               (_ADI_MSK(0xFFFF0000,uint32_t))  /* Frame Sync Divisor */
-#define BITM_SPORT_DIV_B_CLKDIV              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Clock Divisor */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MCTL_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MCTL_B_WOFFSET            16                               /* Window Offset */
-#define BITP_SPORT_MCTL_B_WSIZE               8                               /* Window Size */
-#define BITP_SPORT_MCTL_B_MFD                 4                               /* Multi-channel Frame Delay */
-#define BITP_SPORT_MCTL_B_MCPDE               2                               /* Multi-Channel Packing DMA Enable */
-#define BITP_SPORT_MCTL_B_MCE                 0                               /* Multi-Channel Enable */
-
-/* The fields and enumerations for SPORT_MCTL_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MCTL_A */
-
-#define BITM_SPORT_MCTL_B_WOFFSET            (_ADI_MSK(0x03FF0000,uint32_t))  /* Window Offset */
-#define BITM_SPORT_MCTL_B_WSIZE              (_ADI_MSK(0x00007F00,uint32_t))  /* Window Size */
-#define BITM_SPORT_MCTL_B_MFD                (_ADI_MSK(0x000000F0,uint32_t))  /* Multi-channel Frame Delay */
-#define BITM_SPORT_MCTL_B_MCPDE              (_ADI_MSK(0x00000004,uint32_t))  /* Multi-Channel Packing DMA Enable */
-#define BITM_SPORT_MCTL_B_MCE                (_ADI_MSK(0x00000001,uint32_t))  /* Multi-Channel Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_ERR_B                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_ERR_B_FSERRSTAT            6                               /* Frame Sync Error Status */
-#define BITP_SPORT_ERR_B_DERRSSTAT            5                               /* Data Error Secondary Status */
-#define BITP_SPORT_ERR_B_DERRPSTAT            4                               /* Data Error Primary Status */
-#define BITP_SPORT_ERR_B_FSERRMSK             2                               /* Frame Sync Error (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRSMSK             1                               /* Data Error Secondary (Interrupt) Mask */
-#define BITP_SPORT_ERR_B_DERRPMSK             0                               /* Data Error Primary (Interrupt) Mask */
-
-/* The fields and enumerations for SPORT_ERR_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_ERR_A */
-
-#define BITM_SPORT_ERR_B_FSERRSTAT           (_ADI_MSK(0x00000040,uint32_t))  /* Frame Sync Error Status */
-#define BITM_SPORT_ERR_B_DERRSSTAT           (_ADI_MSK(0x00000020,uint32_t))  /* Data Error Secondary Status */
-#define BITM_SPORT_ERR_B_DERRPSTAT           (_ADI_MSK(0x00000010,uint32_t))  /* Data Error Primary Status */
-#define BITM_SPORT_ERR_B_FSERRMSK            (_ADI_MSK(0x00000004,uint32_t))  /* Frame Sync Error (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRSMSK            (_ADI_MSK(0x00000002,uint32_t))  /* Data Error Secondary (Interrupt) Mask */
-#define BITM_SPORT_ERR_B_DERRPMSK            (_ADI_MSK(0x00000001,uint32_t))  /* Data Error Primary (Interrupt) Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_MSTAT_B                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_MSTAT_B_CURCHAN            0                               /* Current Channel */
-
-/* The fields and enumerations for SPORT_MSTAT_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_MSTAT_A */
-
-#define BITM_SPORT_MSTAT_B_CURCHAN           (_ADI_MSK(0x000003FF,uint32_t))  /* Current Channel */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPORT_CTL2_B                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPORT_CTL2_B_CKMUXSEL            1                               /* Clock Multiplexer Select */
-#define BITP_SPORT_CTL2_B_FSMUXSEL            0                               /* Frame Sync Multiplexer Select */
-
-/* The fields and enumerations for SPORT_CTL2_B are also in SPORT - see the common set of ENUM_SPORT_* #defines located with register SPORT_CTL2_A */
-
-#define BITM_SPORT_CTL2_B_CKMUXSEL           (_ADI_MSK(0x00000002,uint32_t))  /* Clock Multiplexer Select */
-#define BITM_SPORT_CTL2_B_FSMUXSEL           (_ADI_MSK(0x00000001,uint32_t))  /* Frame Sync Multiplexer Select */
-
-/* ==================================================
-        Serial Peripheral Interface Registers
-   ================================================== */
-
-/* =========================
-        SPI0
-   ========================= */
-#define REG_SPI0_CTL                    0xFFC40404         /* SPI0 Control Register */
-#define REG_SPI0_RXCTL                  0xFFC40408         /* SPI0 Receive Control Register */
-#define REG_SPI0_TXCTL                  0xFFC4040C         /* SPI0 Transmit Control Register */
-#define REG_SPI0_CLK                    0xFFC40410         /* SPI0 Clock Rate Register */
-#define REG_SPI0_DLY                    0xFFC40414         /* SPI0 Delay Register */
-#define REG_SPI0_SLVSEL                 0xFFC40418         /* SPI0 Slave Select Register */
-#define REG_SPI0_RWC                    0xFFC4041C         /* SPI0 Received Word Count Register */
-#define REG_SPI0_RWCR                   0xFFC40420         /* SPI0 Received Word Count Reload Register */
-#define REG_SPI0_TWC                    0xFFC40424         /* SPI0 Transmitted Word Count Register */
-#define REG_SPI0_TWCR                   0xFFC40428         /* SPI0 Transmitted Word Count Reload Register */
-#define REG_SPI0_IMSK                   0xFFC40430         /* SPI0 Interrupt Mask Register */
-#define REG_SPI0_IMSK_CLR               0xFFC40434         /* SPI0 Interrupt Mask Clear Register */
-#define REG_SPI0_IMSK_SET               0xFFC40438         /* SPI0 Interrupt Mask Set Register */
-#define REG_SPI0_STAT                   0xFFC40440         /* SPI0 Status Register */
-#define REG_SPI0_ILAT                   0xFFC40444         /* SPI0 Masked Interrupt Condition Register */
-#define REG_SPI0_ILAT_CLR               0xFFC40448         /* SPI0 Masked Interrupt Clear Register */
-#define REG_SPI0_RFIFO                  0xFFC40450         /* SPI0 Receive FIFO Data Register */
-#define REG_SPI0_TFIFO                  0xFFC40458         /* SPI0 Transmit FIFO Data Register */
-
-/* =========================
-        SPI1
-   ========================= */
-#define REG_SPI1_CTL                    0xFFC40504         /* SPI1 Control Register */
-#define REG_SPI1_RXCTL                  0xFFC40508         /* SPI1 Receive Control Register */
-#define REG_SPI1_TXCTL                  0xFFC4050C         /* SPI1 Transmit Control Register */
-#define REG_SPI1_CLK                    0xFFC40510         /* SPI1 Clock Rate Register */
-#define REG_SPI1_DLY                    0xFFC40514         /* SPI1 Delay Register */
-#define REG_SPI1_SLVSEL                 0xFFC40518         /* SPI1 Slave Select Register */
-#define REG_SPI1_RWC                    0xFFC4051C         /* SPI1 Received Word Count Register */
-#define REG_SPI1_RWCR                   0xFFC40520         /* SPI1 Received Word Count Reload Register */
-#define REG_SPI1_TWC                    0xFFC40524         /* SPI1 Transmitted Word Count Register */
-#define REG_SPI1_TWCR                   0xFFC40528         /* SPI1 Transmitted Word Count Reload Register */
-#define REG_SPI1_IMSK                   0xFFC40530         /* SPI1 Interrupt Mask Register */
-#define REG_SPI1_IMSK_CLR               0xFFC40534         /* SPI1 Interrupt Mask Clear Register */
-#define REG_SPI1_IMSK_SET               0xFFC40538         /* SPI1 Interrupt Mask Set Register */
-#define REG_SPI1_STAT                   0xFFC40540         /* SPI1 Status Register */
-#define REG_SPI1_ILAT                   0xFFC40544         /* SPI1 Masked Interrupt Condition Register */
-#define REG_SPI1_ILAT_CLR               0xFFC40548         /* SPI1 Masked Interrupt Clear Register */
-#define REG_SPI1_RFIFO                  0xFFC40550         /* SPI1 Receive FIFO Data Register */
-#define REG_SPI1_TFIFO                  0xFFC40558         /* SPI1 Transmit FIFO Data Register */
-
-/* =========================
-        SPI
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CTL_SOSI                    22                               /* Start on MOSI */
-#define BITP_SPI_CTL_MIOM                    20                               /* Multiple I/O Mode */
-#define BITP_SPI_CTL_FMODE                   18                               /* Fast-Mode Enable */
-#define BITP_SPI_CTL_FCWM                    16                               /* Flow Control Watermark */
-#define BITP_SPI_CTL_FCPL                    15                               /* Flow Control Polarity */
-#define BITP_SPI_CTL_FCCH                    14                               /* Flow Control Channel Selection */
-#define BITP_SPI_CTL_FCEN                    13                               /* Flow Control Enable */
-#define BITP_SPI_CTL_LSBF                    12                               /* Least Significant Bit First */
-#define BITP_SPI_CTL_SIZE                     9                               /* Word Transfer Size */
-#define BITP_SPI_CTL_EMISO                    8                               /* Enable MISO */
-#define BITP_SPI_CTL_SELST                    7                               /* Slave Select Polarity Between Transfers */
-#define BITP_SPI_CTL_ASSEL                    6                               /* Slave Select Pin Control */
-#define BITP_SPI_CTL_CPOL                     5                               /* Clock Polarity */
-#define BITP_SPI_CTL_CPHA                     4                               /* Clock Phase */
-#define BITP_SPI_CTL_ODM                      3                               /* Open Drain Mode */
-#define BITP_SPI_CTL_PSSE                     2                               /* Protected Slave Select Enable */
-#define BITP_SPI_CTL_MSTR                     1                               /* Master / Slave */
-#define BITP_SPI_CTL_EN                       0                               /* Enable */
-
-#define BITM_SPI_CTL_SOSI                    (_ADI_MSK(0x00400000,uint32_t))  /* Start on MOSI */
-#define ENUM_SPI_CTL_STMISO                  (_ADI_MSK(0x00000000,uint32_t))  /* SOSI: Bit 1 on MISO (DIOM) or on D3 (QIOM) */
-#define ENUM_SPI_CTL_STMOSI                  (_ADI_MSK(0x00400000,uint32_t))  /* SOSI: Bit 1 on MOSI (DIOM and QIOM) */
-
-#define BITM_SPI_CTL_MIOM                    (_ADI_MSK(0x00300000,uint32_t))  /* Multiple I/O Mode */
-#define ENUM_SPI_CTL_MIO_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* MIOM: No MIOM (disabled) */
-#define ENUM_SPI_CTL_MIO_DUAL                (_ADI_MSK(0x00100000,uint32_t))  /* MIOM: DIOM operation */
-#define ENUM_SPI_CTL_MIO_QUAD                (_ADI_MSK(0x00200000,uint32_t))  /* MIOM: QIOM operation */
-
-#define BITM_SPI_CTL_FMODE                   (_ADI_MSK(0x00040000,uint32_t))  /* Fast-Mode Enable */
-#define ENUM_SPI_CTL_FAST_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FMODE: Disable */
-#define ENUM_SPI_CTL_FAST_EN                 (_ADI_MSK(0x00040000,uint32_t))  /* FMODE: Enable */
-
-#define BITM_SPI_CTL_FCWM                    (_ADI_MSK(0x00030000,uint32_t))  /* Flow Control Watermark */
-#define ENUM_SPI_CTL_FIFO0                   (_ADI_MSK(0x00000000,uint32_t))  /* FCWM: TFIFO empty or RFIFO full */
-#define ENUM_SPI_CTL_FIFO1                   (_ADI_MSK(0x00010000,uint32_t))  /* FCWM: TFIFO 75% or more empty, or RFIFO full */
-#define ENUM_SPI_CTL_FIFO2                   (_ADI_MSK(0x00020000,uint32_t))  /* FCWM: TFIFO 50% or more empty, or RFIFO full */
-
-#define BITM_SPI_CTL_FCPL                    (_ADI_MSK(0x00008000,uint32_t))  /* Flow Control Polarity */
-#define ENUM_SPI_CTL_FLOW_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* FCPL: Active-low RDY */
-#define ENUM_SPI_CTL_FLOW_HI                 (_ADI_MSK(0x00008000,uint32_t))  /* FCPL: Active-high RDY */
-
-#define BITM_SPI_CTL_FCCH                    (_ADI_MSK(0x00004000,uint32_t))  /* Flow Control Channel Selection */
-#define ENUM_SPI_CTL_FLOW_RX                 (_ADI_MSK(0x00000000,uint32_t))  /* FCCH: Flow control on RX buffer */
-#define ENUM_SPI_CTL_FLOW_TX                 (_ADI_MSK(0x00004000,uint32_t))  /* FCCH: Flow control on TX buffer */
-
-#define BITM_SPI_CTL_FCEN                    (_ADI_MSK(0x00002000,uint32_t))  /* Flow Control Enable */
-#define ENUM_SPI_CTL_FLOW_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* FCEN: Disable */
-#define ENUM_SPI_CTL_FLOW_EN                 (_ADI_MSK(0x00002000,uint32_t))  /* FCEN: Enable */
-
-#define BITM_SPI_CTL_LSBF                    (_ADI_MSK(0x00001000,uint32_t))  /* Least Significant Bit First */
-#define ENUM_SPI_CTL_MSB_FIRST               (_ADI_MSK(0x00000000,uint32_t))  /* LSBF: MSB sent/received first (big endian) */
-#define ENUM_SPI_CTL_LSB_FIRST               (_ADI_MSK(0x00001000,uint32_t))  /* LSBF: LSB sent/received first (little endian) */
-
-#define BITM_SPI_CTL_SIZE                    (_ADI_MSK(0x00000600,uint32_t))  /* Word Transfer Size */
-#define ENUM_SPI_CTL_SIZE08                  (_ADI_MSK(0x00000000,uint32_t))  /* SIZE: 8-bit word */
-#define ENUM_SPI_CTL_SIZE16                  (_ADI_MSK(0x00000200,uint32_t))  /* SIZE: 16-bit word */
-#define ENUM_SPI_CTL_SIZE32                  (_ADI_MSK(0x00000400,uint32_t))  /* SIZE: 32-bit word */
-
-#define BITM_SPI_CTL_EMISO                   (_ADI_MSK(0x00000100,uint32_t))  /* Enable MISO */
-#define ENUM_SPI_CTL_MISO_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* EMISO: Disable */
-#define ENUM_SPI_CTL_MISO_EN                 (_ADI_MSK(0x00000100,uint32_t))  /* EMISO: Enable */
-
-#define BITM_SPI_CTL_SELST                   (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select Polarity Between Transfers */
-#define ENUM_SPI_CTL_DEASSRT_SSEL            (_ADI_MSK(0x00000000,uint32_t))  /* SELST: De-assert slave select (high) */
-#define ENUM_SPI_CTL_ASSRT_SSEL              (_ADI_MSK(0x00000080,uint32_t))  /* SELST: Assert slave select (low) */
-
-#define BITM_SPI_CTL_ASSEL                   (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select Pin Control */
-#define ENUM_SPI_CTL_SW_SSEL                 (_ADI_MSK(0x00000000,uint32_t))  /* ASSEL: Software Slave Select Control */
-#define ENUM_SPI_CTL_HW_SSEL                 (_ADI_MSK(0x00000040,uint32_t))  /* ASSEL: Hardware Slave Select Control */
-
-#define BITM_SPI_CTL_CPOL                    (_ADI_MSK(0x00000020,uint32_t))  /* Clock Polarity */
-#define ENUM_SPI_CTL_SCKHI                   (_ADI_MSK(0x00000000,uint32_t))  /* CPOL: Active-high SPI CLK */
-#define ENUM_SPI_CTL_SCKLO                   (_ADI_MSK(0x00000020,uint32_t))  /* CPOL: Active-low SPI CLK */
-
-#define BITM_SPI_CTL_CPHA                    (_ADI_MSK(0x00000010,uint32_t))  /* Clock Phase */
-#define ENUM_SPI_CTL_SCKMID                  (_ADI_MSK(0x00000000,uint32_t))  /* CPHA: SPI CLK toggles from middle */
-#define ENUM_SPI_CTL_SCKBEG                  (_ADI_MSK(0x00000010,uint32_t))  /* CPHA: SPI CLK toggles from start */
-
-#define BITM_SPI_CTL_ODM                     (_ADI_MSK(0x00000008,uint32_t))  /* Open Drain Mode */
-#define ENUM_SPI_CTL_ODM_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* ODM: Disable */
-#define ENUM_SPI_CTL_ODM_EN                  (_ADI_MSK(0x00000008,uint32_t))  /* ODM: Enable */
-
-#define BITM_SPI_CTL_PSSE                    (_ADI_MSK(0x00000004,uint32_t))  /* Protected Slave Select Enable */
-#define ENUM_SPI_CTL_PSSE_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* PSSE: Disable */
-#define ENUM_SPI_CTL_PSSE_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* PSSE: Enable */
-
-#define BITM_SPI_CTL_MSTR                    (_ADI_MSK(0x00000002,uint32_t))  /* Master / Slave */
-#define ENUM_SPI_CTL_SLAVE                   (_ADI_MSK(0x00000000,uint32_t))  /* MSTR: Slave */
-#define ENUM_SPI_CTL_MASTER                  (_ADI_MSK(0x00000002,uint32_t))  /* MSTR: Master */
-
-#define BITM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SPI_CTL_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable SPI module */
-#define ENUM_SPI_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RXCTL_RUWM                  16                               /* Receive FIFO Urgent Watermark */
-#define BITP_SPI_RXCTL_RRWM                  12                               /* Receive FIFO Regular Watermark */
-#define BITP_SPI_RXCTL_RDO                    8                               /* Receive Data Overrun */
-#define BITP_SPI_RXCTL_RDR                    4                               /* Receive Data Request */
-#define BITP_SPI_RXCTL_RWCEN                  3                               /* Receive Word Counter Enable */
-#define BITP_SPI_RXCTL_RTI                    2                               /* Receive Transfer Initiate */
-#define BITP_SPI_RXCTL_REN                    0                               /* Receive Enable */
-
-#define BITM_SPI_RXCTL_RUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* Receive FIFO Urgent Watermark */
-#define ENUM_SPI_RXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disabled */
-#define ENUM_SPI_RXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* RUWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* RUWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* RUWM: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_UWM_FULL              (_ADI_MSK(0x00040000,uint32_t))  /* RUWM: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* Receive FIFO Regular Watermark */
-#define ENUM_SPI_RXCTL_RWM_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RRWM: Empty RFIFO */
-#define ENUM_SPI_RXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* RRWM: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* RRWM: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* RRWM: 75% full RFIFO */
-
-#define BITM_SPI_RXCTL_RDO                   (_ADI_MSK(0x00000100,uint32_t))  /* Receive Data Overrun */
-#define ENUM_SPI_RXCTL_DISCARD               (_ADI_MSK(0x00000000,uint32_t))  /* RDO: KeDiscard incoming data if SPI_RFIFO is full */
-#define ENUM_SPI_RXCTL_OVERWRITE             (_ADI_MSK(0x00000100,uint32_t))  /* RDO: Overwrite old data if SPI_RFIFO is full */
-
-#define BITM_SPI_RXCTL_RDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Receive Data Request */
-#define ENUM_SPI_RXCTL_RDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RDR: Disabled */
-#define ENUM_SPI_RXCTL_RDR_NE                (_ADI_MSK(0x00000010,uint32_t))  /* RDR: Not empty RFIFO */
-#define ENUM_SPI_RXCTL_RDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* RDR: 25% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* RDR: 50% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* RDR: 75% full RFIFO */
-#define ENUM_SPI_RXCTL_RDR_FULL              (_ADI_MSK(0x00000050,uint32_t))  /* RDR: Full RFIFO */
-
-#define BITM_SPI_RXCTL_RWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Receive Word Counter Enable */
-#define ENUM_SPI_RXCTL_RWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RWCEN: Disable */
-#define ENUM_SPI_RXCTL_RWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* RWCEN: Enable */
-
-#define BITM_SPI_RXCTL_RTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Receive Transfer Initiate */
-#define ENUM_SPI_RXCTL_RTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* RTI: Disable */
-#define ENUM_SPI_RXCTL_RTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* RTI: Enable */
-
-#define BITM_SPI_RXCTL_REN                   (_ADI_MSK(0x00000001,uint32_t))  /* Receive Enable */
-#define ENUM_SPI_RXCTL_RX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* REN: Disable */
-#define ENUM_SPI_RXCTL_RX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* REN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TXCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TXCTL_TUWM                  16                               /* FIFO Urgent Watermark */
-#define BITP_SPI_TXCTL_TRWM                  12                               /* FIFO Regular Watermark */
-#define BITP_SPI_TXCTL_TDU                    8                               /* Transmit Data Under-run */
-#define BITP_SPI_TXCTL_TDR                    4                               /* Transmit Data Request */
-#define BITP_SPI_TXCTL_TWCEN                  3                               /* Transmit Word Counter Enable */
-#define BITP_SPI_TXCTL_TTI                    2                               /* Transmit Transfer Initiate */
-#define BITP_SPI_TXCTL_TEN                    0                               /* Transmit Enable */
-
-#define BITM_SPI_TXCTL_TUWM                  (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Urgent Watermark */
-#define ENUM_SPI_TXCTL_UWM_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disabled */
-#define ENUM_SPI_TXCTL_UWM_25                (_ADI_MSK(0x00010000,uint32_t))  /* TUWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_50                (_ADI_MSK(0x00020000,uint32_t))  /* TUWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_75                (_ADI_MSK(0x00030000,uint32_t))  /* TUWM: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_UWM_EMPTY             (_ADI_MSK(0x00040000,uint32_t))  /* TUWM: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TRWM                  (_ADI_MSK(0x00003000,uint32_t))  /* FIFO Regular Watermark */
-#define ENUM_SPI_TXCTL_RWM_FULL              (_ADI_MSK(0x00000000,uint32_t))  /* TRWM: Full TFIFO */
-#define ENUM_SPI_TXCTL_RWM_25                (_ADI_MSK(0x00001000,uint32_t))  /* TRWM: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_50                (_ADI_MSK(0x00002000,uint32_t))  /* TRWM: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_RWM_75                (_ADI_MSK(0x00003000,uint32_t))  /* TRWM: 75% empty TFIFO */
-
-#define BITM_SPI_TXCTL_TDU                   (_ADI_MSK(0x00000100,uint32_t))  /* Transmit Data Under-run */
-#define ENUM_SPI_TXCTL_LASTWD                (_ADI_MSK(0x00000000,uint32_t))  /* TDU: Send last word when SPI_TFIFO is empty */
-#define ENUM_SPI_TXCTL_ZERO                  (_ADI_MSK(0x00000100,uint32_t))  /* TDU: Send zeros when SPI_TFIFO is empty */
-
-#define BITM_SPI_TXCTL_TDR                   (_ADI_MSK(0x00000070,uint32_t))  /* Transmit Data Request */
-#define ENUM_SPI_TXCTL_TDR_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TDR: Disabled */
-#define ENUM_SPI_TXCTL_TDR_NF                (_ADI_MSK(0x00000010,uint32_t))  /* TDR: Not full TFIFO */
-#define ENUM_SPI_TXCTL_TDR_25                (_ADI_MSK(0x00000020,uint32_t))  /* TDR: 25% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_50                (_ADI_MSK(0x00000030,uint32_t))  /* TDR: 50% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_75                (_ADI_MSK(0x00000040,uint32_t))  /* TDR: 75% empty TFIFO */
-#define ENUM_SPI_TXCTL_TDR_EMPTY             (_ADI_MSK(0x00000050,uint32_t))  /* TDR: Empty TFIFO */
-
-#define BITM_SPI_TXCTL_TWCEN                 (_ADI_MSK(0x00000008,uint32_t))  /* Transmit Word Counter Enable */
-#define ENUM_SPI_TXCTL_TWC_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TWCEN: Disable */
-#define ENUM_SPI_TXCTL_TWC_EN                (_ADI_MSK(0x00000008,uint32_t))  /* TWCEN: Enable */
-
-#define BITM_SPI_TXCTL_TTI                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Transfer Initiate */
-#define ENUM_SPI_TXCTL_TTI_DIS               (_ADI_MSK(0x00000000,uint32_t))  /* TTI: Disable */
-#define ENUM_SPI_TXCTL_TTI_EN                (_ADI_MSK(0x00000004,uint32_t))  /* TTI: Enable */
-
-#define BITM_SPI_TXCTL_TEN                   (_ADI_MSK(0x00000001,uint32_t))  /* Transmit Enable */
-#define ENUM_SPI_TXCTL_TX_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* TEN: Disable */
-#define ENUM_SPI_TXCTL_TX_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* TEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_CLK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_CLK_BAUD                     0                               /* Baud Rate */
-#define BITM_SPI_CLK_BAUD                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* Baud Rate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_DLY                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_DLY_LAGX                     9                               /* Extended SPI Clock Lag Control */
-#define BITP_SPI_DLY_LEADX                    8                               /* Extended SPI Clock Lead Control */
-#define BITP_SPI_DLY_STOP                     0                               /* Transfer delay time in multiples of SPI clock period */
-#define BITM_SPI_DLY_LAGX                    (_ADI_MSK(0x00000200,uint32_t))  /* Extended SPI Clock Lag Control */
-#define BITM_SPI_DLY_LEADX                   (_ADI_MSK(0x00000100,uint32_t))  /* Extended SPI Clock Lead Control */
-#define BITM_SPI_DLY_STOP                    (_ADI_MSK(0x000000FF,uint32_t))  /* Transfer delay time in multiples of SPI clock period */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_SLVSEL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_SLVSEL_SSEL7                15                               /* Slave Select 7 Input */
-#define BITP_SPI_SLVSEL_SSEL6                14                               /* Slave Select 6 Input */
-#define BITP_SPI_SLVSEL_SSEL5                13                               /* Slave Select 5 Input */
-#define BITP_SPI_SLVSEL_SSEL4                12                               /* Slave Select 4 Input */
-#define BITP_SPI_SLVSEL_SSEL3                11                               /* Slave Select 3 Input */
-#define BITP_SPI_SLVSEL_SSEL2                10                               /* Slave Select 2 Input */
-#define BITP_SPI_SLVSEL_SSEL1                 9                               /* Slave Select 1 Input */
-#define BITP_SPI_SLVSEL_SSE7                  7                               /* Slave Select 7 Enable */
-#define BITP_SPI_SLVSEL_SSE6                  6                               /* Slave Select 6 Enable */
-#define BITP_SPI_SLVSEL_SSE5                  5                               /* Slave Select 5 Enable */
-#define BITP_SPI_SLVSEL_SSE4                  4                               /* Slave Select 4 Enable */
-#define BITP_SPI_SLVSEL_SSE3                  3                               /* Slave Select 3 Enable */
-#define BITP_SPI_SLVSEL_SSE2                  2                               /* Slave Select 2 Enable */
-#define BITP_SPI_SLVSEL_SSE1                  1                               /* Slave Select 1 Enable */
-
-#define BITM_SPI_SLVSEL_SSEL7                (_ADI_MSK(0x00008000,uint32_t))  /* Slave Select 7 Input */
-#define ENUM_SPI_SLVSEL_SSEL7_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL7: Low */
-#define ENUM_SPI_SLVSEL_SSEL7_HI             (_ADI_MSK(0x00008000,uint32_t))  /* SSEL7: High */
-
-#define BITM_SPI_SLVSEL_SSEL6                (_ADI_MSK(0x00004000,uint32_t))  /* Slave Select 6 Input */
-#define ENUM_SPI_SLVSEL_SSEL6_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL6: Low */
-#define ENUM_SPI_SLVSEL_SSEL6_HI             (_ADI_MSK(0x00004000,uint32_t))  /* SSEL6: High */
-
-#define BITM_SPI_SLVSEL_SSEL5                (_ADI_MSK(0x00002000,uint32_t))  /* Slave Select 5 Input */
-#define ENUM_SPI_SLVSEL_SSEL5_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL5: Low */
-#define ENUM_SPI_SLVSEL_SSEL5_HI             (_ADI_MSK(0x00002000,uint32_t))  /* SSEL5: High */
-
-#define BITM_SPI_SLVSEL_SSEL4                (_ADI_MSK(0x00001000,uint32_t))  /* Slave Select 4 Input */
-#define ENUM_SPI_SLVSEL_SSEL4_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL4: Low */
-#define ENUM_SPI_SLVSEL_SSEL4_HI             (_ADI_MSK(0x00001000,uint32_t))  /* SSEL4: High */
-
-#define BITM_SPI_SLVSEL_SSEL3                (_ADI_MSK(0x00000800,uint32_t))  /* Slave Select 3 Input */
-#define ENUM_SPI_SLVSEL_SSEL3_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL3: Low */
-#define ENUM_SPI_SLVSEL_SSEL3_HI             (_ADI_MSK(0x00000800,uint32_t))  /* SSEL3: High */
-
-#define BITM_SPI_SLVSEL_SSEL2                (_ADI_MSK(0x00000400,uint32_t))  /* Slave Select 2 Input */
-#define ENUM_SPI_SLVSEL_SSEL2_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL2: Low */
-#define ENUM_SPI_SLVSEL_SSEL2_HI             (_ADI_MSK(0x00000400,uint32_t))  /* SSEL2: High */
-
-#define BITM_SPI_SLVSEL_SSEL1                (_ADI_MSK(0x00000200,uint32_t))  /* Slave Select 1 Input */
-#define ENUM_SPI_SLVSEL_SSEL1_LO             (_ADI_MSK(0x00000000,uint32_t))  /* SSEL1: Low */
-#define ENUM_SPI_SLVSEL_SSEL1_HI             (_ADI_MSK(0x00000200,uint32_t))  /* SSEL1: High */
-
-#define BITM_SPI_SLVSEL_SSE7                 (_ADI_MSK(0x00000080,uint32_t))  /* Slave Select 7 Enable */
-#define ENUM_SPI_SLVSEL_SSEL7_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE7: Disable */
-#define ENUM_SPI_SLVSEL_SSEL7_EN             (_ADI_MSK(0x00000080,uint32_t))  /* SSE7: Enable */
-
-#define BITM_SPI_SLVSEL_SSE6                 (_ADI_MSK(0x00000040,uint32_t))  /* Slave Select 6 Enable */
-#define ENUM_SPI_SLVSEL_SSEL6_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE6: Disable */
-#define ENUM_SPI_SLVSEL_SSEL6_EN             (_ADI_MSK(0x00000040,uint32_t))  /* SSE6: Enable */
-
-#define BITM_SPI_SLVSEL_SSE5                 (_ADI_MSK(0x00000020,uint32_t))  /* Slave Select 5 Enable */
-#define ENUM_SPI_SLVSEL_SSEL5_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE5: Disable */
-#define ENUM_SPI_SLVSEL_SSEL5_EN             (_ADI_MSK(0x00000020,uint32_t))  /* SSE5: Enable */
-
-#define BITM_SPI_SLVSEL_SSE4                 (_ADI_MSK(0x00000010,uint32_t))  /* Slave Select 4 Enable */
-#define ENUM_SPI_SLVSEL_SSEL4_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE4: Disable */
-#define ENUM_SPI_SLVSEL_SSEL4_EN             (_ADI_MSK(0x00000010,uint32_t))  /* SSE4: Enable */
-
-#define BITM_SPI_SLVSEL_SSE3                 (_ADI_MSK(0x00000008,uint32_t))  /* Slave Select 3 Enable */
-#define ENUM_SPI_SLVSEL_SSEL3_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE3: Disable */
-#define ENUM_SPI_SLVSEL_SSEL3_EN             (_ADI_MSK(0x00000008,uint32_t))  /* SSE3: Enable */
-
-#define BITM_SPI_SLVSEL_SSE2                 (_ADI_MSK(0x00000004,uint32_t))  /* Slave Select 2 Enable */
-#define ENUM_SPI_SLVSEL_SSEL2_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE2: Disable */
-#define ENUM_SPI_SLVSEL_SSEL2_EN             (_ADI_MSK(0x00000004,uint32_t))  /* SSE2: Enable */
-
-#define BITM_SPI_SLVSEL_SSE1                 (_ADI_MSK(0x00000002,uint32_t))  /* Slave Select 1 Enable */
-#define ENUM_SPI_SLVSEL_SSEL1_DIS            (_ADI_MSK(0x00000000,uint32_t))  /* SSE1: Disable */
-#define ENUM_SPI_SLVSEL_SSEL1_EN             (_ADI_MSK(0x00000002,uint32_t))  /* SSE1: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWC_VALUE                    0                               /* Received Word Count */
-#define BITM_SPI_RWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_RWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_RWCR_VALUE                   0                               /* Received Word Count Reload */
-#define BITM_SPI_RWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Received Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWC                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWC_VALUE                    0                               /* Transmitted Word Count */
-#define BITM_SPI_TWC_VALUE                   (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_TWCR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_TWCR_VALUE                   0                               /* Transmitted Word Count Reload */
-#define BITM_SPI_TWCR_VALUE                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Transmitted Word Count Reload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_TF                     11                               /* Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_RF                     10                               /* Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_TS                      9                               /* Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_RS                      8                               /* Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_MF                      7                               /* Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_TC                      6                               /* Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_TUR                     5                               /* Transmit Underrun Interrupt Mask */
-#define BITP_SPI_IMSK_ROR                     4                               /* Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_RUWM                    1                               /* Receive Urgent Watermark Interrupt Mask */
-
-#define BITM_SPI_IMSK_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Mask */
-#define ENUM_SPI_TF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TF: Disable (mask) interrupt */
-#define ENUM_SPI_TF_HI                       (_ADI_MSK(0x00000800,uint32_t))  /* TF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Mask */
-#define ENUM_SPI_RF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RF: Disable (mask) interrupt */
-#define ENUM_SPI_RF_HI                       (_ADI_MSK(0x00000400,uint32_t))  /* RF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Mask */
-#define ENUM_SPI_TS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TS: Disable (mask) interrupt */
-#define ENUM_SPI_TS_HI                       (_ADI_MSK(0x00000200,uint32_t))  /* TS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Mask */
-#define ENUM_SPI_RS_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* RS: Disable (mask) interrupt */
-#define ENUM_SPI_RS_HI                       (_ADI_MSK(0x00000100,uint32_t))  /* RS: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Mask */
-#define ENUM_SPI_MF_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* MF: Disable (mask) interrupt */
-#define ENUM_SPI_MF_HI                       (_ADI_MSK(0x00000080,uint32_t))  /* MF: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Mask */
-#define ENUM_SPI_TC_LO                       (_ADI_MSK(0x00000000,uint32_t))  /* TC: Disable (mask) interrupt */
-#define ENUM_SPI_TC_HI                       (_ADI_MSK(0x00000040,uint32_t))  /* TC: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Interrupt Mask */
-#define ENUM_SPI_TUR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* TUR: Disable (mask) interrupt */
-#define ENUM_SPI_TUR_HI                      (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Mask */
-#define ENUM_SPI_ROR_LO                      (_ADI_MSK(0x00000000,uint32_t))  /* ROR: Disable (mask) interrupt */
-#define ENUM_SPI_ROR_HI                      (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_TUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: Disable (mask) interrupt */
-#define ENUM_SPI_TUWM_HI                     (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Enable (unmask) interrupt */
-
-#define BITM_SPI_IMSK_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Mask */
-#define ENUM_SPI_RUWM_LO                     (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: Disable (mask) interrupt */
-#define ENUM_SPI_RUWM_HI                     (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Enable (unmask) interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RF                 10                               /* Clear Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TS                  9                               /* Clear Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RS                  8                               /* Clear Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_MF                  7                               /* Clear Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_IMSK_SET                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_IMSK_SET_TF                 11                               /* Set Transmit Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RF                 10                               /* Set Receive Finish Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TS                  9                               /* Set Transmit Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RS                  8                               /* Set Receive Start Interrupt Mask */
-#define BITP_SPI_IMSK_SET_MF                  7                               /* Set Mode Fault Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TC                  6                               /* Set Transmit Collision Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUR                 5                               /* Set Transmit Under-run  Interrupt Mask */
-#define BITP_SPI_IMSK_SET_ROR                 4                               /* Set Receive Overrun Interrupt Mask */
-#define BITP_SPI_IMSK_SET_TUWM                2                               /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITP_SPI_IMSK_SET_RUWM                1                               /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* The fields and enumerations for SPI_IMSK_SET are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_IMSK_SET_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Set Transmit Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Set Receive Finish Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Set Transmit Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Set Receive Start Interrupt Mask */
-#define BITM_SPI_IMSK_SET_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Set Mode Fault Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Set Transmit Collision Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Set Transmit Under-run  Interrupt Mask */
-#define BITM_SPI_IMSK_SET_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Set Receive Overrun Interrupt Mask */
-#define BITM_SPI_IMSK_SET_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Set Transmit Urgent Watermark Interrupt Mask */
-#define BITM_SPI_IMSK_SET_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Set Receive Urgent Watermark Interrupt Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_STAT_TFF                    23                               /* SPI_TFIFO Full */
-#define BITP_SPI_STAT_RFE                    22                               /* SPI_RFIFO Empty */
-#define BITP_SPI_STAT_FCS                    20                               /* Flow Control Stall Indication */
-#define BITP_SPI_STAT_TFS                    16                               /* SPI_TFIFO Status */
-#define BITP_SPI_STAT_RFS                    12                               /* SPI_RFIFO Status */
-#define BITP_SPI_STAT_TF                     11                               /* Transmit Finish Indication */
-#define BITP_SPI_STAT_RF                     10                               /* Receive Finish Indication */
-#define BITP_SPI_STAT_TS                      9                               /* Transmit Start */
-#define BITP_SPI_STAT_RS                      8                               /* Receive Start */
-#define BITP_SPI_STAT_MF                      7                               /* Mode Fault Indication */
-#define BITP_SPI_STAT_TC                      6                               /* Transmit Collision Indication */
-#define BITP_SPI_STAT_TUR                     5                               /* Transmit Underrun Indication */
-#define BITP_SPI_STAT_ROR                     4                               /* Receive Overrun Indication */
-#define BITP_SPI_STAT_TUWM                    2                               /* Transmit Urgent Watermark Breached */
-#define BITP_SPI_STAT_RUWM                    1                               /* Receive Urgent Watermark Breached */
-#define BITP_SPI_STAT_SPIF                    0                               /* SPI Finished */
-
-#define BITM_SPI_STAT_TFF                    (_ADI_MSK(0x00800000,uint32_t))  /* SPI_TFIFO Full */
-#define ENUM_SPI_STAT_TFIFO_NF               (_ADI_MSK(0x00000000,uint32_t))  /* TFF: Not full Tx FIFO */
-#define ENUM_SPI_STAT_TFIFO_F                (_ADI_MSK(0x00800000,uint32_t))  /* TFF: Full Tx FIFO */
-
-#define BITM_SPI_STAT_RFE                    (_ADI_MSK(0x00400000,uint32_t))  /* SPI_RFIFO Empty */
-#define ENUM_SPI_STAT_RFIFO_E                (_ADI_MSK(0x00000000,uint32_t))  /* RFE: Empty Rx FIFO */
-#define ENUM_SPI_STAT_RFIFO_NE               (_ADI_MSK(0x00400000,uint32_t))  /* RFE: Not empty Rx FIFO */
-
-#define BITM_SPI_STAT_FCS                    (_ADI_MSK(0x00100000,uint32_t))  /* Flow Control Stall Indication */
-#define ENUM_SPI_STAT_STALL                  (_ADI_MSK(0x00000000,uint32_t))  /* FCS: Stall (RDY pin asserted) */
-#define ENUM_SPI_STAT_NOSTALL                (_ADI_MSK(0x00100000,uint32_t))  /* FCS: No stall (RDY pin de-asserted) */
-
-#define BITM_SPI_STAT_TFS                    (_ADI_MSK(0x00070000,uint32_t))  /* SPI_TFIFO Status */
-#define ENUM_SPI_STAT_TFIFO_FULL             (_ADI_MSK(0x00000000,uint32_t))  /* TFS: Full TFIFO */
-#define ENUM_SPI_STAT_TFIFO_25               (_ADI_MSK(0x00010000,uint32_t))  /* TFS: 25% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_50               (_ADI_MSK(0x00020000,uint32_t))  /* TFS: 50% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_75               (_ADI_MSK(0x00030000,uint32_t))  /* TFS: 75% empty TFIFO */
-#define ENUM_SPI_STAT_TFIFO_EMPTY            (_ADI_MSK(0x00040000,uint32_t))  /* TFS: Empty TFIFO */
-
-#define BITM_SPI_STAT_RFS                    (_ADI_MSK(0x00007000,uint32_t))  /* SPI_RFIFO Status */
-#define ENUM_SPI_STAT_RFIFO_EMPTY            (_ADI_MSK(0x00000000,uint32_t))  /* RFS: Empty RFIFO */
-#define ENUM_SPI_STAT_RFIFO_25               (_ADI_MSK(0x00001000,uint32_t))  /* RFS: 25% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_50               (_ADI_MSK(0x00002000,uint32_t))  /* RFS: 50% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_75               (_ADI_MSK(0x00003000,uint32_t))  /* RFS: 75% full RFIFO */
-#define ENUM_SPI_STAT_RFIFO_FULL             (_ADI_MSK(0x00004000,uint32_t))  /* RFS: Full RFIFO */
-
-#define BITM_SPI_STAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Indication */
-#define ENUM_SPI_STAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No status */
-#define ENUM_SPI_STAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Transmit finish detected */
-
-#define BITM_SPI_STAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Indication */
-#define ENUM_SPI_STAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No status */
-#define ENUM_SPI_STAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Receive finish detected */
-
-#define BITM_SPI_STAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start */
-#define ENUM_SPI_STAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No status */
-#define ENUM_SPI_STAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Transmit start detected */
-
-#define BITM_SPI_STAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start */
-#define ENUM_SPI_STAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No status */
-#define ENUM_SPI_STAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Receive start detected */
-
-#define BITM_SPI_STAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Indication */
-#define ENUM_SPI_STAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No status */
-#define ENUM_SPI_STAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Mode fault occurred */
-
-#define BITM_SPI_STAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Indication */
-#define ENUM_SPI_STAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No status */
-#define ENUM_SPI_STAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Transmit collision occurred */
-
-#define BITM_SPI_STAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Underrun Indication */
-#define ENUM_SPI_STAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No status */
-#define ENUM_SPI_STAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Transmit underrun occurred */
-
-#define BITM_SPI_STAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Indication */
-#define ENUM_SPI_STAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No status */
-#define ENUM_SPI_STAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Receive overrun occurred */
-
-#define BITM_SPI_STAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Breached */
-#define ENUM_SPI_STAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: TX Regular Watermark reached */
-#define ENUM_SPI_STAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: TX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Breached */
-#define ENUM_SPI_STAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: RX Regular Watermark reached */
-#define ENUM_SPI_STAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: RX Urgent Watermark breached */
-
-#define BITM_SPI_STAT_SPIF                   (_ADI_MSK(0x00000001,uint32_t))  /* SPI Finished */
-#define ENUM_SPI_STAT_SPIF_LO                (_ADI_MSK(0x00000000,uint32_t))  /* SPIF: No status */
-#define ENUM_SPI_STAT_SPIF_HI                (_ADI_MSK(0x00000001,uint32_t))  /* SPIF: Completed single-word transfer */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_TF                     11                               /* Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_RF                     10                               /* Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_TS                      9                               /* Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_RS                      8                               /* Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_MF                      7                               /* Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_TC                      6                               /* Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_TUR                     5                               /* Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_ROR                     4                               /* Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_TUWM                    2                               /* Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_RUWM                    1                               /* Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-
-#define BITM_SPI_ILAT_TF                     (_ADI_MSK(0x00000800,uint32_t))  /* Transmit Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_TF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TF: No interrupt */
-#define ENUM_SPI_ILAT_TF_HI                  (_ADI_MSK(0x00000800,uint32_t))  /* TF: Latched interrupt */
-
-#define BITM_SPI_ILAT_RF                     (_ADI_MSK(0x00000400,uint32_t))  /* Receive Finish Interrupt Latch */
-#define ENUM_SPI_ILAT_RF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RF: No interrupt */
-#define ENUM_SPI_ILAT_RF_HI                  (_ADI_MSK(0x00000400,uint32_t))  /* RF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TS                     (_ADI_MSK(0x00000200,uint32_t))  /* Transmit Start Interrupt Latch */
-#define ENUM_SPI_ILAT_TS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TS: No interrupt */
-#define ENUM_SPI_ILAT_TS_HI                  (_ADI_MSK(0x00000200,uint32_t))  /* TS: Latched interrupt */
-
-#define BITM_SPI_ILAT_RS                     (_ADI_MSK(0x00000100,uint32_t))  /* Receive Start Interrupt Latch */
-#define ENUM_SPI_ILAT_RS_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* RS: No interrupt */
-#define ENUM_SPI_ILAT_RS_HI                  (_ADI_MSK(0x00000100,uint32_t))  /* RS: Latched interrupt */
-
-#define BITM_SPI_ILAT_MF                     (_ADI_MSK(0x00000080,uint32_t))  /* Mode Fault Interrupt Latch */
-#define ENUM_SPI_ILAT_MF_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* MF: No interrupt */
-#define ENUM_SPI_ILAT_MF_HI                  (_ADI_MSK(0x00000080,uint32_t))  /* MF: Latched interrupt */
-
-#define BITM_SPI_ILAT_TC                     (_ADI_MSK(0x00000040,uint32_t))  /* Transmit Collision Interrupt Latch */
-#define ENUM_SPI_ILAT_TC_LO                  (_ADI_MSK(0x00000000,uint32_t))  /* TC: No interrupt */
-#define ENUM_SPI_ILAT_TC_HI                  (_ADI_MSK(0x00000040,uint32_t))  /* TC: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUR                    (_ADI_MSK(0x00000020,uint32_t))  /* Transmit Under-run Interrupt Latch */
-#define ENUM_SPI_ILAT_TUR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* TUR: No interrupt */
-#define ENUM_SPI_ILAT_TUR_HI                 (_ADI_MSK(0x00000020,uint32_t))  /* TUR: Latched interrupt */
-
-#define BITM_SPI_ILAT_ROR                    (_ADI_MSK(0x00000010,uint32_t))  /* Receive Overrun Interrupt Latch */
-#define ENUM_SPI_ILAT_ROR_LO                 (_ADI_MSK(0x00000000,uint32_t))  /* ROR: No interrupt */
-#define ENUM_SPI_ILAT_ROR_HI                 (_ADI_MSK(0x00000010,uint32_t))  /* ROR: Latched interrupt */
-
-#define BITM_SPI_ILAT_TUWM                   (_ADI_MSK(0x00000004,uint32_t))  /* Transmit Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_TUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* TUWM: No interrupt */
-#define ENUM_SPI_ILAT_TUWM_HI                (_ADI_MSK(0x00000004,uint32_t))  /* TUWM: Latched interrupt */
-
-#define BITM_SPI_ILAT_RUWM                   (_ADI_MSK(0x00000002,uint32_t))  /* Receive Urgent Watermark Interrupt Latch */
-#define ENUM_SPI_ILAT_RUWM_LO                (_ADI_MSK(0x00000000,uint32_t))  /* RUWM: No interrupt */
-#define ENUM_SPI_ILAT_RUWM_HI                (_ADI_MSK(0x00000002,uint32_t))  /* RUWM: Latched interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPI_ILAT_CLR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPI_ILAT_CLR_TF                 11                               /* Clear Transmit Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RF                 10                               /* Clear Receive Finish Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TS                  9                               /* Clear Transmit Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RS                  8                               /* Clear Receive Start Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_MF                  7                               /* Clear Mode Fault Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TC                  6                               /* Clear Transmit Collision Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUR                 5                               /* Clear Transmit Under-run Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_ROR                 4                               /* Clear Receive Overrun Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_TUWM                2                               /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITP_SPI_ILAT_CLR_RUWM                1                               /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* The fields and enumerations for SPI_ILAT_CLR are also in SPI - see the common set of ENUM_SPI_* #defines located with register SPI_IMSK */
-
-#define BITM_SPI_ILAT_CLR_TF                 (_ADI_MSK(0x00000800,uint32_t))  /* Clear Transmit Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RF                 (_ADI_MSK(0x00000400,uint32_t))  /* Clear Receive Finish Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TS                 (_ADI_MSK(0x00000200,uint32_t))  /* Clear Transmit Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RS                 (_ADI_MSK(0x00000100,uint32_t))  /* Clear Receive Start Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_MF                 (_ADI_MSK(0x00000080,uint32_t))  /* Clear Mode Fault Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TC                 (_ADI_MSK(0x00000040,uint32_t))  /* Clear Transmit Collision Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUR                (_ADI_MSK(0x00000020,uint32_t))  /* Clear Transmit Under-run Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_ROR                (_ADI_MSK(0x00000010,uint32_t))  /* Clear Receive Overrun Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_TUWM               (_ADI_MSK(0x00000004,uint32_t))  /* Clear Transmit Urgent Watermark Interrupt Latch */
-#define BITM_SPI_ILAT_CLR_RUWM               (_ADI_MSK(0x00000002,uint32_t))  /* Clear Receive Urgent Watermark Interrupt Latch */
-
-/* ==================================================
-        DMA Channel Registers
-   ================================================== */
-
-/* =========================
-        DMA0
-   ========================= */
-#define REG_DMA0_DSCPTR_NXT             0xFFC41000         /* DMA0 Pointer to Next Initial Descriptor */
-#define REG_DMA0_ADDRSTART              0xFFC41004         /* DMA0 Start Address of Current Buffer */
-#define REG_DMA0_CFG                    0xFFC41008         /* DMA0 Configuration Register */
-#define REG_DMA0_XCNT                   0xFFC4100C         /* DMA0 Inner Loop Count Start Value */
-#define REG_DMA0_XMOD                   0xFFC41010         /* DMA0 Inner Loop Address Increment */
-#define REG_DMA0_YCNT                   0xFFC41014         /* DMA0 Outer Loop Count Start Value (2D only) */
-#define REG_DMA0_YMOD                   0xFFC41018         /* DMA0 Outer Loop Address Increment (2D only) */
-#define REG_DMA0_DSCPTR_CUR             0xFFC41024         /* DMA0 Current Descriptor Pointer */
-#define REG_DMA0_DSCPTR_PRV             0xFFC41028         /* DMA0 Previous Initial Descriptor Pointer */
-#define REG_DMA0_ADDR_CUR               0xFFC4102C         /* DMA0 Current Address */
-#define REG_DMA0_STAT                   0xFFC41030         /* DMA0 Status Register */
-#define REG_DMA0_XCNT_CUR               0xFFC41034         /* DMA0 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA0_YCNT_CUR               0xFFC41038         /* DMA0 Current Row Count (2D only) */
-#define REG_DMA0_BWLCNT                 0xFFC41040         /* DMA0 Bandwidth Limit Count */
-#define REG_DMA0_BWLCNT_CUR             0xFFC41044         /* DMA0 Bandwidth Limit Count Current */
-#define REG_DMA0_BWMCNT                 0xFFC41048         /* DMA0 Bandwidth Monitor Count */
-#define REG_DMA0_BWMCNT_CUR             0xFFC4104C         /* DMA0 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA1
-   ========================= */
-#define REG_DMA1_DSCPTR_NXT             0xFFC41080         /* DMA1 Pointer to Next Initial Descriptor */
-#define REG_DMA1_ADDRSTART              0xFFC41084         /* DMA1 Start Address of Current Buffer */
-#define REG_DMA1_CFG                    0xFFC41088         /* DMA1 Configuration Register */
-#define REG_DMA1_XCNT                   0xFFC4108C         /* DMA1 Inner Loop Count Start Value */
-#define REG_DMA1_XMOD                   0xFFC41090         /* DMA1 Inner Loop Address Increment */
-#define REG_DMA1_YCNT                   0xFFC41094         /* DMA1 Outer Loop Count Start Value (2D only) */
-#define REG_DMA1_YMOD                   0xFFC41098         /* DMA1 Outer Loop Address Increment (2D only) */
-#define REG_DMA1_DSCPTR_CUR             0xFFC410A4         /* DMA1 Current Descriptor Pointer */
-#define REG_DMA1_DSCPTR_PRV             0xFFC410A8         /* DMA1 Previous Initial Descriptor Pointer */
-#define REG_DMA1_ADDR_CUR               0xFFC410AC         /* DMA1 Current Address */
-#define REG_DMA1_STAT                   0xFFC410B0         /* DMA1 Status Register */
-#define REG_DMA1_XCNT_CUR               0xFFC410B4         /* DMA1 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA1_YCNT_CUR               0xFFC410B8         /* DMA1 Current Row Count (2D only) */
-#define REG_DMA1_BWLCNT                 0xFFC410C0         /* DMA1 Bandwidth Limit Count */
-#define REG_DMA1_BWLCNT_CUR             0xFFC410C4         /* DMA1 Bandwidth Limit Count Current */
-#define REG_DMA1_BWMCNT                 0xFFC410C8         /* DMA1 Bandwidth Monitor Count */
-#define REG_DMA1_BWMCNT_CUR             0xFFC410CC         /* DMA1 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA2
-   ========================= */
-#define REG_DMA2_DSCPTR_NXT             0xFFC41100         /* DMA2 Pointer to Next Initial Descriptor */
-#define REG_DMA2_ADDRSTART              0xFFC41104         /* DMA2 Start Address of Current Buffer */
-#define REG_DMA2_CFG                    0xFFC41108         /* DMA2 Configuration Register */
-#define REG_DMA2_XCNT                   0xFFC4110C         /* DMA2 Inner Loop Count Start Value */
-#define REG_DMA2_XMOD                   0xFFC41110         /* DMA2 Inner Loop Address Increment */
-#define REG_DMA2_YCNT                   0xFFC41114         /* DMA2 Outer Loop Count Start Value (2D only) */
-#define REG_DMA2_YMOD                   0xFFC41118         /* DMA2 Outer Loop Address Increment (2D only) */
-#define REG_DMA2_DSCPTR_CUR             0xFFC41124         /* DMA2 Current Descriptor Pointer */
-#define REG_DMA2_DSCPTR_PRV             0xFFC41128         /* DMA2 Previous Initial Descriptor Pointer */
-#define REG_DMA2_ADDR_CUR               0xFFC4112C         /* DMA2 Current Address */
-#define REG_DMA2_STAT                   0xFFC41130         /* DMA2 Status Register */
-#define REG_DMA2_XCNT_CUR               0xFFC41134         /* DMA2 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA2_YCNT_CUR               0xFFC41138         /* DMA2 Current Row Count (2D only) */
-#define REG_DMA2_BWLCNT                 0xFFC41140         /* DMA2 Bandwidth Limit Count */
-#define REG_DMA2_BWLCNT_CUR             0xFFC41144         /* DMA2 Bandwidth Limit Count Current */
-#define REG_DMA2_BWMCNT                 0xFFC41148         /* DMA2 Bandwidth Monitor Count */
-#define REG_DMA2_BWMCNT_CUR             0xFFC4114C         /* DMA2 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA3
-   ========================= */
-#define REG_DMA3_DSCPTR_NXT             0xFFC41180         /* DMA3 Pointer to Next Initial Descriptor */
-#define REG_DMA3_ADDRSTART              0xFFC41184         /* DMA3 Start Address of Current Buffer */
-#define REG_DMA3_CFG                    0xFFC41188         /* DMA3 Configuration Register */
-#define REG_DMA3_XCNT                   0xFFC4118C         /* DMA3 Inner Loop Count Start Value */
-#define REG_DMA3_XMOD                   0xFFC41190         /* DMA3 Inner Loop Address Increment */
-#define REG_DMA3_YCNT                   0xFFC41194         /* DMA3 Outer Loop Count Start Value (2D only) */
-#define REG_DMA3_YMOD                   0xFFC41198         /* DMA3 Outer Loop Address Increment (2D only) */
-#define REG_DMA3_DSCPTR_CUR             0xFFC411A4         /* DMA3 Current Descriptor Pointer */
-#define REG_DMA3_DSCPTR_PRV             0xFFC411A8         /* DMA3 Previous Initial Descriptor Pointer */
-#define REG_DMA3_ADDR_CUR               0xFFC411AC         /* DMA3 Current Address */
-#define REG_DMA3_STAT                   0xFFC411B0         /* DMA3 Status Register */
-#define REG_DMA3_XCNT_CUR               0xFFC411B4         /* DMA3 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA3_YCNT_CUR               0xFFC411B8         /* DMA3 Current Row Count (2D only) */
-#define REG_DMA3_BWLCNT                 0xFFC411C0         /* DMA3 Bandwidth Limit Count */
-#define REG_DMA3_BWLCNT_CUR             0xFFC411C4         /* DMA3 Bandwidth Limit Count Current */
-#define REG_DMA3_BWMCNT                 0xFFC411C8         /* DMA3 Bandwidth Monitor Count */
-#define REG_DMA3_BWMCNT_CUR             0xFFC411CC         /* DMA3 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA4
-   ========================= */
-#define REG_DMA4_DSCPTR_NXT             0xFFC41200         /* DMA4 Pointer to Next Initial Descriptor */
-#define REG_DMA4_ADDRSTART              0xFFC41204         /* DMA4 Start Address of Current Buffer */
-#define REG_DMA4_CFG                    0xFFC41208         /* DMA4 Configuration Register */
-#define REG_DMA4_XCNT                   0xFFC4120C         /* DMA4 Inner Loop Count Start Value */
-#define REG_DMA4_XMOD                   0xFFC41210         /* DMA4 Inner Loop Address Increment */
-#define REG_DMA4_YCNT                   0xFFC41214         /* DMA4 Outer Loop Count Start Value (2D only) */
-#define REG_DMA4_YMOD                   0xFFC41218         /* DMA4 Outer Loop Address Increment (2D only) */
-#define REG_DMA4_DSCPTR_CUR             0xFFC41224         /* DMA4 Current Descriptor Pointer */
-#define REG_DMA4_DSCPTR_PRV             0xFFC41228         /* DMA4 Previous Initial Descriptor Pointer */
-#define REG_DMA4_ADDR_CUR               0xFFC4122C         /* DMA4 Current Address */
-#define REG_DMA4_STAT                   0xFFC41230         /* DMA4 Status Register */
-#define REG_DMA4_XCNT_CUR               0xFFC41234         /* DMA4 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA4_YCNT_CUR               0xFFC41238         /* DMA4 Current Row Count (2D only) */
-#define REG_DMA4_BWLCNT                 0xFFC41240         /* DMA4 Bandwidth Limit Count */
-#define REG_DMA4_BWLCNT_CUR             0xFFC41244         /* DMA4 Bandwidth Limit Count Current */
-#define REG_DMA4_BWMCNT                 0xFFC41248         /* DMA4 Bandwidth Monitor Count */
-#define REG_DMA4_BWMCNT_CUR             0xFFC4124C         /* DMA4 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA5
-   ========================= */
-#define REG_DMA5_DSCPTR_NXT             0xFFC41280         /* DMA5 Pointer to Next Initial Descriptor */
-#define REG_DMA5_ADDRSTART              0xFFC41284         /* DMA5 Start Address of Current Buffer */
-#define REG_DMA5_CFG                    0xFFC41288         /* DMA5 Configuration Register */
-#define REG_DMA5_XCNT                   0xFFC4128C         /* DMA5 Inner Loop Count Start Value */
-#define REG_DMA5_XMOD                   0xFFC41290         /* DMA5 Inner Loop Address Increment */
-#define REG_DMA5_YCNT                   0xFFC41294         /* DMA5 Outer Loop Count Start Value (2D only) */
-#define REG_DMA5_YMOD                   0xFFC41298         /* DMA5 Outer Loop Address Increment (2D only) */
-#define REG_DMA5_DSCPTR_CUR             0xFFC412A4         /* DMA5 Current Descriptor Pointer */
-#define REG_DMA5_DSCPTR_PRV             0xFFC412A8         /* DMA5 Previous Initial Descriptor Pointer */
-#define REG_DMA5_ADDR_CUR               0xFFC412AC         /* DMA5 Current Address */
-#define REG_DMA5_STAT                   0xFFC412B0         /* DMA5 Status Register */
-#define REG_DMA5_XCNT_CUR               0xFFC412B4         /* DMA5 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA5_YCNT_CUR               0xFFC412B8         /* DMA5 Current Row Count (2D only) */
-#define REG_DMA5_BWLCNT                 0xFFC412C0         /* DMA5 Bandwidth Limit Count */
-#define REG_DMA5_BWLCNT_CUR             0xFFC412C4         /* DMA5 Bandwidth Limit Count Current */
-#define REG_DMA5_BWMCNT                 0xFFC412C8         /* DMA5 Bandwidth Monitor Count */
-#define REG_DMA5_BWMCNT_CUR             0xFFC412CC         /* DMA5 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA6
-   ========================= */
-#define REG_DMA6_DSCPTR_NXT             0xFFC41300         /* DMA6 Pointer to Next Initial Descriptor */
-#define REG_DMA6_ADDRSTART              0xFFC41304         /* DMA6 Start Address of Current Buffer */
-#define REG_DMA6_CFG                    0xFFC41308         /* DMA6 Configuration Register */
-#define REG_DMA6_XCNT                   0xFFC4130C         /* DMA6 Inner Loop Count Start Value */
-#define REG_DMA6_XMOD                   0xFFC41310         /* DMA6 Inner Loop Address Increment */
-#define REG_DMA6_YCNT                   0xFFC41314         /* DMA6 Outer Loop Count Start Value (2D only) */
-#define REG_DMA6_YMOD                   0xFFC41318         /* DMA6 Outer Loop Address Increment (2D only) */
-#define REG_DMA6_DSCPTR_CUR             0xFFC41324         /* DMA6 Current Descriptor Pointer */
-#define REG_DMA6_DSCPTR_PRV             0xFFC41328         /* DMA6 Previous Initial Descriptor Pointer */
-#define REG_DMA6_ADDR_CUR               0xFFC4132C         /* DMA6 Current Address */
-#define REG_DMA6_STAT                   0xFFC41330         /* DMA6 Status Register */
-#define REG_DMA6_XCNT_CUR               0xFFC41334         /* DMA6 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA6_YCNT_CUR               0xFFC41338         /* DMA6 Current Row Count (2D only) */
-#define REG_DMA6_BWLCNT                 0xFFC41340         /* DMA6 Bandwidth Limit Count */
-#define REG_DMA6_BWLCNT_CUR             0xFFC41344         /* DMA6 Bandwidth Limit Count Current */
-#define REG_DMA6_BWMCNT                 0xFFC41348         /* DMA6 Bandwidth Monitor Count */
-#define REG_DMA6_BWMCNT_CUR             0xFFC4134C         /* DMA6 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA7
-   ========================= */
-#define REG_DMA7_DSCPTR_NXT             0xFFC41380         /* DMA7 Pointer to Next Initial Descriptor */
-#define REG_DMA7_ADDRSTART              0xFFC41384         /* DMA7 Start Address of Current Buffer */
-#define REG_DMA7_CFG                    0xFFC41388         /* DMA7 Configuration Register */
-#define REG_DMA7_XCNT                   0xFFC4138C         /* DMA7 Inner Loop Count Start Value */
-#define REG_DMA7_XMOD                   0xFFC41390         /* DMA7 Inner Loop Address Increment */
-#define REG_DMA7_YCNT                   0xFFC41394         /* DMA7 Outer Loop Count Start Value (2D only) */
-#define REG_DMA7_YMOD                   0xFFC41398         /* DMA7 Outer Loop Address Increment (2D only) */
-#define REG_DMA7_DSCPTR_CUR             0xFFC413A4         /* DMA7 Current Descriptor Pointer */
-#define REG_DMA7_DSCPTR_PRV             0xFFC413A8         /* DMA7 Previous Initial Descriptor Pointer */
-#define REG_DMA7_ADDR_CUR               0xFFC413AC         /* DMA7 Current Address */
-#define REG_DMA7_STAT                   0xFFC413B0         /* DMA7 Status Register */
-#define REG_DMA7_XCNT_CUR               0xFFC413B4         /* DMA7 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA7_YCNT_CUR               0xFFC413B8         /* DMA7 Current Row Count (2D only) */
-#define REG_DMA7_BWLCNT                 0xFFC413C0         /* DMA7 Bandwidth Limit Count */
-#define REG_DMA7_BWLCNT_CUR             0xFFC413C4         /* DMA7 Bandwidth Limit Count Current */
-#define REG_DMA7_BWMCNT                 0xFFC413C8         /* DMA7 Bandwidth Monitor Count */
-#define REG_DMA7_BWMCNT_CUR             0xFFC413CC         /* DMA7 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA8
-   ========================= */
-#define REG_DMA8_DSCPTR_NXT             0xFFC41400         /* DMA8 Pointer to Next Initial Descriptor */
-#define REG_DMA8_ADDRSTART              0xFFC41404         /* DMA8 Start Address of Current Buffer */
-#define REG_DMA8_CFG                    0xFFC41408         /* DMA8 Configuration Register */
-#define REG_DMA8_XCNT                   0xFFC4140C         /* DMA8 Inner Loop Count Start Value */
-#define REG_DMA8_XMOD                   0xFFC41410         /* DMA8 Inner Loop Address Increment */
-#define REG_DMA8_YCNT                   0xFFC41414         /* DMA8 Outer Loop Count Start Value (2D only) */
-#define REG_DMA8_YMOD                   0xFFC41418         /* DMA8 Outer Loop Address Increment (2D only) */
-#define REG_DMA8_DSCPTR_CUR             0xFFC41424         /* DMA8 Current Descriptor Pointer */
-#define REG_DMA8_DSCPTR_PRV             0xFFC41428         /* DMA8 Previous Initial Descriptor Pointer */
-#define REG_DMA8_ADDR_CUR               0xFFC4142C         /* DMA8 Current Address */
-#define REG_DMA8_STAT                   0xFFC41430         /* DMA8 Status Register */
-#define REG_DMA8_XCNT_CUR               0xFFC41434         /* DMA8 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA8_YCNT_CUR               0xFFC41438         /* DMA8 Current Row Count (2D only) */
-#define REG_DMA8_BWLCNT                 0xFFC41440         /* DMA8 Bandwidth Limit Count */
-#define REG_DMA8_BWLCNT_CUR             0xFFC41444         /* DMA8 Bandwidth Limit Count Current */
-#define REG_DMA8_BWMCNT                 0xFFC41448         /* DMA8 Bandwidth Monitor Count */
-#define REG_DMA8_BWMCNT_CUR             0xFFC4144C         /* DMA8 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA9
-   ========================= */
-#define REG_DMA9_DSCPTR_NXT             0xFFC41480         /* DMA9 Pointer to Next Initial Descriptor */
-#define REG_DMA9_ADDRSTART              0xFFC41484         /* DMA9 Start Address of Current Buffer */
-#define REG_DMA9_CFG                    0xFFC41488         /* DMA9 Configuration Register */
-#define REG_DMA9_XCNT                   0xFFC4148C         /* DMA9 Inner Loop Count Start Value */
-#define REG_DMA9_XMOD                   0xFFC41490         /* DMA9 Inner Loop Address Increment */
-#define REG_DMA9_YCNT                   0xFFC41494         /* DMA9 Outer Loop Count Start Value (2D only) */
-#define REG_DMA9_YMOD                   0xFFC41498         /* DMA9 Outer Loop Address Increment (2D only) */
-#define REG_DMA9_DSCPTR_CUR             0xFFC414A4         /* DMA9 Current Descriptor Pointer */
-#define REG_DMA9_DSCPTR_PRV             0xFFC414A8         /* DMA9 Previous Initial Descriptor Pointer */
-#define REG_DMA9_ADDR_CUR               0xFFC414AC         /* DMA9 Current Address */
-#define REG_DMA9_STAT                   0xFFC414B0         /* DMA9 Status Register */
-#define REG_DMA9_XCNT_CUR               0xFFC414B4         /* DMA9 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA9_YCNT_CUR               0xFFC414B8         /* DMA9 Current Row Count (2D only) */
-#define REG_DMA9_BWLCNT                 0xFFC414C0         /* DMA9 Bandwidth Limit Count */
-#define REG_DMA9_BWLCNT_CUR             0xFFC414C4         /* DMA9 Bandwidth Limit Count Current */
-#define REG_DMA9_BWMCNT                 0xFFC414C8         /* DMA9 Bandwidth Monitor Count */
-#define REG_DMA9_BWMCNT_CUR             0xFFC414CC         /* DMA9 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA10
-   ========================= */
-#define REG_DMA10_DSCPTR_NXT            0xFFC05000         /* DMA10 Pointer to Next Initial Descriptor */
-#define REG_DMA10_ADDRSTART             0xFFC05004         /* DMA10 Start Address of Current Buffer */
-#define REG_DMA10_CFG                   0xFFC05008         /* DMA10 Configuration Register */
-#define REG_DMA10_XCNT                  0xFFC0500C         /* DMA10 Inner Loop Count Start Value */
-#define REG_DMA10_XMOD                  0xFFC05010         /* DMA10 Inner Loop Address Increment */
-#define REG_DMA10_YCNT                  0xFFC05014         /* DMA10 Outer Loop Count Start Value (2D only) */
-#define REG_DMA10_YMOD                  0xFFC05018         /* DMA10 Outer Loop Address Increment (2D only) */
-#define REG_DMA10_DSCPTR_CUR            0xFFC05024         /* DMA10 Current Descriptor Pointer */
-#define REG_DMA10_DSCPTR_PRV            0xFFC05028         /* DMA10 Previous Initial Descriptor Pointer */
-#define REG_DMA10_ADDR_CUR              0xFFC0502C         /* DMA10 Current Address */
-#define REG_DMA10_STAT                  0xFFC05030         /* DMA10 Status Register */
-#define REG_DMA10_XCNT_CUR              0xFFC05034         /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA10_YCNT_CUR              0xFFC05038         /* DMA10 Current Row Count (2D only) */
-#define REG_DMA10_BWLCNT                0xFFC05040         /* DMA10 Bandwidth Limit Count */
-#define REG_DMA10_BWLCNT_CUR            0xFFC05044         /* DMA10 Bandwidth Limit Count Current */
-#define REG_DMA10_BWMCNT                0xFFC05048         /* DMA10 Bandwidth Monitor Count */
-#define REG_DMA10_BWMCNT_CUR            0xFFC0504C         /* DMA10 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA11
-   ========================= */
-#define REG_DMA11_DSCPTR_NXT            0xFFC05080         /* DMA11 Pointer to Next Initial Descriptor */
-#define REG_DMA11_ADDRSTART             0xFFC05084         /* DMA11 Start Address of Current Buffer */
-#define REG_DMA11_CFG                   0xFFC05088         /* DMA11 Configuration Register */
-#define REG_DMA11_XCNT                  0xFFC0508C         /* DMA11 Inner Loop Count Start Value */
-#define REG_DMA11_XMOD                  0xFFC05090         /* DMA11 Inner Loop Address Increment */
-#define REG_DMA11_YCNT                  0xFFC05094         /* DMA11 Outer Loop Count Start Value (2D only) */
-#define REG_DMA11_YMOD                  0xFFC05098         /* DMA11 Outer Loop Address Increment (2D only) */
-#define REG_DMA11_DSCPTR_CUR            0xFFC050A4         /* DMA11 Current Descriptor Pointer */
-#define REG_DMA11_DSCPTR_PRV            0xFFC050A8         /* DMA11 Previous Initial Descriptor Pointer */
-#define REG_DMA11_ADDR_CUR              0xFFC050AC         /* DMA11 Current Address */
-#define REG_DMA11_STAT                  0xFFC050B0         /* DMA11 Status Register */
-#define REG_DMA11_XCNT_CUR              0xFFC050B4         /* DMA11 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA11_YCNT_CUR              0xFFC050B8         /* DMA11 Current Row Count (2D only) */
-#define REG_DMA11_BWLCNT                0xFFC050C0         /* DMA11 Bandwidth Limit Count */
-#define REG_DMA11_BWLCNT_CUR            0xFFC050C4         /* DMA11 Bandwidth Limit Count Current */
-#define REG_DMA11_BWMCNT                0xFFC050C8         /* DMA11 Bandwidth Monitor Count */
-#define REG_DMA11_BWMCNT_CUR            0xFFC050CC         /* DMA11 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA12
-   ========================= */
-#define REG_DMA12_DSCPTR_NXT            0xFFC05100         /* DMA12 Pointer to Next Initial Descriptor */
-#define REG_DMA12_ADDRSTART             0xFFC05104         /* DMA12 Start Address of Current Buffer */
-#define REG_DMA12_CFG                   0xFFC05108         /* DMA12 Configuration Register */
-#define REG_DMA12_XCNT                  0xFFC0510C         /* DMA12 Inner Loop Count Start Value */
-#define REG_DMA12_XMOD                  0xFFC05110         /* DMA12 Inner Loop Address Increment */
-#define REG_DMA12_YCNT                  0xFFC05114         /* DMA12 Outer Loop Count Start Value (2D only) */
-#define REG_DMA12_YMOD                  0xFFC05118         /* DMA12 Outer Loop Address Increment (2D only) */
-#define REG_DMA12_DSCPTR_CUR            0xFFC05124         /* DMA12 Current Descriptor Pointer */
-#define REG_DMA12_DSCPTR_PRV            0xFFC05128         /* DMA12 Previous Initial Descriptor Pointer */
-#define REG_DMA12_ADDR_CUR              0xFFC0512C         /* DMA12 Current Address */
-#define REG_DMA12_STAT                  0xFFC05130         /* DMA12 Status Register */
-#define REG_DMA12_XCNT_CUR              0xFFC05134         /* DMA12 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA12_YCNT_CUR              0xFFC05138         /* DMA12 Current Row Count (2D only) */
-#define REG_DMA12_BWLCNT                0xFFC05140         /* DMA12 Bandwidth Limit Count */
-#define REG_DMA12_BWLCNT_CUR            0xFFC05144         /* DMA12 Bandwidth Limit Count Current */
-#define REG_DMA12_BWMCNT                0xFFC05148         /* DMA12 Bandwidth Monitor Count */
-#define REG_DMA12_BWMCNT_CUR            0xFFC0514C         /* DMA12 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA13
-   ========================= */
-#define REG_DMA13_DSCPTR_NXT            0xFFC07000         /* DMA13 Pointer to Next Initial Descriptor */
-#define REG_DMA13_ADDRSTART             0xFFC07004         /* DMA13 Start Address of Current Buffer */
-#define REG_DMA13_CFG                   0xFFC07008         /* DMA13 Configuration Register */
-#define REG_DMA13_XCNT                  0xFFC0700C         /* DMA13 Inner Loop Count Start Value */
-#define REG_DMA13_XMOD                  0xFFC07010         /* DMA13 Inner Loop Address Increment */
-#define REG_DMA13_YCNT                  0xFFC07014         /* DMA13 Outer Loop Count Start Value (2D only) */
-#define REG_DMA13_YMOD                  0xFFC07018         /* DMA13 Outer Loop Address Increment (2D only) */
-#define REG_DMA13_DSCPTR_CUR            0xFFC07024         /* DMA13 Current Descriptor Pointer */
-#define REG_DMA13_DSCPTR_PRV            0xFFC07028         /* DMA13 Previous Initial Descriptor Pointer */
-#define REG_DMA13_ADDR_CUR              0xFFC0702C         /* DMA13 Current Address */
-#define REG_DMA13_STAT                  0xFFC07030         /* DMA13 Status Register */
-#define REG_DMA13_XCNT_CUR              0xFFC07034         /* DMA13 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA13_YCNT_CUR              0xFFC07038         /* DMA13 Current Row Count (2D only) */
-#define REG_DMA13_BWLCNT                0xFFC07040         /* DMA13 Bandwidth Limit Count */
-#define REG_DMA13_BWLCNT_CUR            0xFFC07044         /* DMA13 Bandwidth Limit Count Current */
-#define REG_DMA13_BWMCNT                0xFFC07048         /* DMA13 Bandwidth Monitor Count */
-#define REG_DMA13_BWMCNT_CUR            0xFFC0704C         /* DMA13 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA14
-   ========================= */
-#define REG_DMA14_DSCPTR_NXT            0xFFC07080         /* DMA14 Pointer to Next Initial Descriptor */
-#define REG_DMA14_ADDRSTART             0xFFC07084         /* DMA14 Start Address of Current Buffer */
-#define REG_DMA14_CFG                   0xFFC07088         /* DMA14 Configuration Register */
-#define REG_DMA14_XCNT                  0xFFC0708C         /* DMA14 Inner Loop Count Start Value */
-#define REG_DMA14_XMOD                  0xFFC07090         /* DMA14 Inner Loop Address Increment */
-#define REG_DMA14_YCNT                  0xFFC07094         /* DMA14 Outer Loop Count Start Value (2D only) */
-#define REG_DMA14_YMOD                  0xFFC07098         /* DMA14 Outer Loop Address Increment (2D only) */
-#define REG_DMA14_DSCPTR_CUR            0xFFC070A4         /* DMA14 Current Descriptor Pointer */
-#define REG_DMA14_DSCPTR_PRV            0xFFC070A8         /* DMA14 Previous Initial Descriptor Pointer */
-#define REG_DMA14_ADDR_CUR              0xFFC070AC         /* DMA14 Current Address */
-#define REG_DMA14_STAT                  0xFFC070B0         /* DMA14 Status Register */
-#define REG_DMA14_XCNT_CUR              0xFFC070B4         /* DMA14 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA14_YCNT_CUR              0xFFC070B8         /* DMA14 Current Row Count (2D only) */
-#define REG_DMA14_BWLCNT                0xFFC070C0         /* DMA14 Bandwidth Limit Count */
-#define REG_DMA14_BWLCNT_CUR            0xFFC070C4         /* DMA14 Bandwidth Limit Count Current */
-#define REG_DMA14_BWMCNT                0xFFC070C8         /* DMA14 Bandwidth Monitor Count */
-#define REG_DMA14_BWMCNT_CUR            0xFFC070CC         /* DMA14 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA15
-   ========================= */
-#define REG_DMA15_DSCPTR_NXT            0xFFC07100         /* DMA15 Pointer to Next Initial Descriptor */
-#define REG_DMA15_ADDRSTART             0xFFC07104         /* DMA15 Start Address of Current Buffer */
-#define REG_DMA15_CFG                   0xFFC07108         /* DMA15 Configuration Register */
-#define REG_DMA15_XCNT                  0xFFC0710C         /* DMA15 Inner Loop Count Start Value */
-#define REG_DMA15_XMOD                  0xFFC07110         /* DMA15 Inner Loop Address Increment */
-#define REG_DMA15_YCNT                  0xFFC07114         /* DMA15 Outer Loop Count Start Value (2D only) */
-#define REG_DMA15_YMOD                  0xFFC07118         /* DMA15 Outer Loop Address Increment (2D only) */
-#define REG_DMA15_DSCPTR_CUR            0xFFC07124         /* DMA15 Current Descriptor Pointer */
-#define REG_DMA15_DSCPTR_PRV            0xFFC07128         /* DMA15 Previous Initial Descriptor Pointer */
-#define REG_DMA15_ADDR_CUR              0xFFC0712C         /* DMA15 Current Address */
-#define REG_DMA15_STAT                  0xFFC07130         /* DMA15 Status Register */
-#define REG_DMA15_XCNT_CUR              0xFFC07134         /* DMA15 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA15_YCNT_CUR              0xFFC07138         /* DMA15 Current Row Count (2D only) */
-#define REG_DMA15_BWLCNT                0xFFC07140         /* DMA15 Bandwidth Limit Count */
-#define REG_DMA15_BWLCNT_CUR            0xFFC07144         /* DMA15 Bandwidth Limit Count Current */
-#define REG_DMA15_BWMCNT                0xFFC07148         /* DMA15 Bandwidth Monitor Count */
-#define REG_DMA15_BWMCNT_CUR            0xFFC0714C         /* DMA15 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA16
-   ========================= */
-#define REG_DMA16_DSCPTR_NXT            0xFFC07180         /* DMA16 Pointer to Next Initial Descriptor */
-#define REG_DMA16_ADDRSTART             0xFFC07184         /* DMA16 Start Address of Current Buffer */
-#define REG_DMA16_CFG                   0xFFC07188         /* DMA16 Configuration Register */
-#define REG_DMA16_XCNT                  0xFFC0718C         /* DMA16 Inner Loop Count Start Value */
-#define REG_DMA16_XMOD                  0xFFC07190         /* DMA16 Inner Loop Address Increment */
-#define REG_DMA16_YCNT                  0xFFC07194         /* DMA16 Outer Loop Count Start Value (2D only) */
-#define REG_DMA16_YMOD                  0xFFC07198         /* DMA16 Outer Loop Address Increment (2D only) */
-#define REG_DMA16_DSCPTR_CUR            0xFFC071A4         /* DMA16 Current Descriptor Pointer */
-#define REG_DMA16_DSCPTR_PRV            0xFFC071A8         /* DMA16 Previous Initial Descriptor Pointer */
-#define REG_DMA16_ADDR_CUR              0xFFC071AC         /* DMA16 Current Address */
-#define REG_DMA16_STAT                  0xFFC071B0         /* DMA16 Status Register */
-#define REG_DMA16_XCNT_CUR              0xFFC071B4         /* DMA16 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA16_YCNT_CUR              0xFFC071B8         /* DMA16 Current Row Count (2D only) */
-#define REG_DMA16_BWLCNT                0xFFC071C0         /* DMA16 Bandwidth Limit Count */
-#define REG_DMA16_BWLCNT_CUR            0xFFC071C4         /* DMA16 Bandwidth Limit Count Current */
-#define REG_DMA16_BWMCNT                0xFFC071C8         /* DMA16 Bandwidth Monitor Count */
-#define REG_DMA16_BWMCNT_CUR            0xFFC071CC         /* DMA16 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA17
-   ========================= */
-#define REG_DMA17_DSCPTR_NXT            0xFFC07200         /* DMA17 Pointer to Next Initial Descriptor */
-#define REG_DMA17_ADDRSTART             0xFFC07204         /* DMA17 Start Address of Current Buffer */
-#define REG_DMA17_CFG                   0xFFC07208         /* DMA17 Configuration Register */
-#define REG_DMA17_XCNT                  0xFFC0720C         /* DMA17 Inner Loop Count Start Value */
-#define REG_DMA17_XMOD                  0xFFC07210         /* DMA17 Inner Loop Address Increment */
-#define REG_DMA17_YCNT                  0xFFC07214         /* DMA17 Outer Loop Count Start Value (2D only) */
-#define REG_DMA17_YMOD                  0xFFC07218         /* DMA17 Outer Loop Address Increment (2D only) */
-#define REG_DMA17_DSCPTR_CUR            0xFFC07224         /* DMA17 Current Descriptor Pointer */
-#define REG_DMA17_DSCPTR_PRV            0xFFC07228         /* DMA17 Previous Initial Descriptor Pointer */
-#define REG_DMA17_ADDR_CUR              0xFFC0722C         /* DMA17 Current Address */
-#define REG_DMA17_STAT                  0xFFC07230         /* DMA17 Status Register */
-#define REG_DMA17_XCNT_CUR              0xFFC07234         /* DMA17 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA17_YCNT_CUR              0xFFC07238         /* DMA17 Current Row Count (2D only) */
-#define REG_DMA17_BWLCNT                0xFFC07240         /* DMA17 Bandwidth Limit Count */
-#define REG_DMA17_BWLCNT_CUR            0xFFC07244         /* DMA17 Bandwidth Limit Count Current */
-#define REG_DMA17_BWMCNT                0xFFC07248         /* DMA17 Bandwidth Monitor Count */
-#define REG_DMA17_BWMCNT_CUR            0xFFC0724C         /* DMA17 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA18
-   ========================= */
-#define REG_DMA18_DSCPTR_NXT            0xFFC07280         /* DMA18 Pointer to Next Initial Descriptor */
-#define REG_DMA18_ADDRSTART             0xFFC07284         /* DMA18 Start Address of Current Buffer */
-#define REG_DMA18_CFG                   0xFFC07288         /* DMA18 Configuration Register */
-#define REG_DMA18_XCNT                  0xFFC0728C         /* DMA18 Inner Loop Count Start Value */
-#define REG_DMA18_XMOD                  0xFFC07290         /* DMA18 Inner Loop Address Increment */
-#define REG_DMA18_YCNT                  0xFFC07294         /* DMA18 Outer Loop Count Start Value (2D only) */
-#define REG_DMA18_YMOD                  0xFFC07298         /* DMA18 Outer Loop Address Increment (2D only) */
-#define REG_DMA18_DSCPTR_CUR            0xFFC072A4         /* DMA18 Current Descriptor Pointer */
-#define REG_DMA18_DSCPTR_PRV            0xFFC072A8         /* DMA18 Previous Initial Descriptor Pointer */
-#define REG_DMA18_ADDR_CUR              0xFFC072AC         /* DMA18 Current Address */
-#define REG_DMA18_STAT                  0xFFC072B0         /* DMA18 Status Register */
-#define REG_DMA18_XCNT_CUR              0xFFC072B4         /* DMA18 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA18_YCNT_CUR              0xFFC072B8         /* DMA18 Current Row Count (2D only) */
-#define REG_DMA18_BWLCNT                0xFFC072C0         /* DMA18 Bandwidth Limit Count */
-#define REG_DMA18_BWLCNT_CUR            0xFFC072C4         /* DMA18 Bandwidth Limit Count Current */
-#define REG_DMA18_BWMCNT                0xFFC072C8         /* DMA18 Bandwidth Monitor Count */
-#define REG_DMA18_BWMCNT_CUR            0xFFC072CC         /* DMA18 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA19
-   ========================= */
-#define REG_DMA19_DSCPTR_NXT            0xFFC07300         /* DMA19 Pointer to Next Initial Descriptor */
-#define REG_DMA19_ADDRSTART             0xFFC07304         /* DMA19 Start Address of Current Buffer */
-#define REG_DMA19_CFG                   0xFFC07308         /* DMA19 Configuration Register */
-#define REG_DMA19_XCNT                  0xFFC0730C         /* DMA19 Inner Loop Count Start Value */
-#define REG_DMA19_XMOD                  0xFFC07310         /* DMA19 Inner Loop Address Increment */
-#define REG_DMA19_YCNT                  0xFFC07314         /* DMA19 Outer Loop Count Start Value (2D only) */
-#define REG_DMA19_YMOD                  0xFFC07318         /* DMA19 Outer Loop Address Increment (2D only) */
-#define REG_DMA19_DSCPTR_CUR            0xFFC07324         /* DMA19 Current Descriptor Pointer */
-#define REG_DMA19_DSCPTR_PRV            0xFFC07328         /* DMA19 Previous Initial Descriptor Pointer */
-#define REG_DMA19_ADDR_CUR              0xFFC0732C         /* DMA19 Current Address */
-#define REG_DMA19_STAT                  0xFFC07330         /* DMA19 Status Register */
-#define REG_DMA19_XCNT_CUR              0xFFC07334         /* DMA19 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA19_YCNT_CUR              0xFFC07338         /* DMA19 Current Row Count (2D only) */
-#define REG_DMA19_BWLCNT                0xFFC07340         /* DMA19 Bandwidth Limit Count */
-#define REG_DMA19_BWLCNT_CUR            0xFFC07344         /* DMA19 Bandwidth Limit Count Current */
-#define REG_DMA19_BWMCNT                0xFFC07348         /* DMA19 Bandwidth Monitor Count */
-#define REG_DMA19_BWMCNT_CUR            0xFFC0734C         /* DMA19 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA20
-   ========================= */
-#define REG_DMA20_DSCPTR_NXT            0xFFC07380         /* DMA20 Pointer to Next Initial Descriptor */
-#define REG_DMA20_ADDRSTART             0xFFC07384         /* DMA20 Start Address of Current Buffer */
-#define REG_DMA20_CFG                   0xFFC07388         /* DMA20 Configuration Register */
-#define REG_DMA20_XCNT                  0xFFC0738C         /* DMA20 Inner Loop Count Start Value */
-#define REG_DMA20_XMOD                  0xFFC07390         /* DMA20 Inner Loop Address Increment */
-#define REG_DMA20_YCNT                  0xFFC07394         /* DMA20 Outer Loop Count Start Value (2D only) */
-#define REG_DMA20_YMOD                  0xFFC07398         /* DMA20 Outer Loop Address Increment (2D only) */
-#define REG_DMA20_DSCPTR_CUR            0xFFC073A4         /* DMA20 Current Descriptor Pointer */
-#define REG_DMA20_DSCPTR_PRV            0xFFC073A8         /* DMA20 Previous Initial Descriptor Pointer */
-#define REG_DMA20_ADDR_CUR              0xFFC073AC         /* DMA20 Current Address */
-#define REG_DMA20_STAT                  0xFFC073B0         /* DMA20 Status Register */
-#define REG_DMA20_XCNT_CUR              0xFFC073B4         /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA20_YCNT_CUR              0xFFC073B8         /* DMA20 Current Row Count (2D only) */
-#define REG_DMA20_BWLCNT                0xFFC073C0         /* DMA20 Bandwidth Limit Count */
-#define REG_DMA20_BWLCNT_CUR            0xFFC073C4         /* DMA20 Bandwidth Limit Count Current */
-#define REG_DMA20_BWMCNT                0xFFC073C8         /* DMA20 Bandwidth Monitor Count */
-#define REG_DMA20_BWMCNT_CUR            0xFFC073CC         /* DMA20 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA21
-   ========================= */
-#define REG_DMA21_DSCPTR_NXT            0xFFC09000         /* DMA21 Pointer to Next Initial Descriptor */
-#define REG_DMA21_ADDRSTART             0xFFC09004         /* DMA21 Start Address of Current Buffer */
-#define REG_DMA21_CFG                   0xFFC09008         /* DMA21 Configuration Register */
-#define REG_DMA21_XCNT                  0xFFC0900C         /* DMA21 Inner Loop Count Start Value */
-#define REG_DMA21_XMOD                  0xFFC09010         /* DMA21 Inner Loop Address Increment */
-#define REG_DMA21_YCNT                  0xFFC09014         /* DMA21 Outer Loop Count Start Value (2D only) */
-#define REG_DMA21_YMOD                  0xFFC09018         /* DMA21 Outer Loop Address Increment (2D only) */
-#define REG_DMA21_DSCPTR_CUR            0xFFC09024         /* DMA21 Current Descriptor Pointer */
-#define REG_DMA21_DSCPTR_PRV            0xFFC09028         /* DMA21 Previous Initial Descriptor Pointer */
-#define REG_DMA21_ADDR_CUR              0xFFC0902C         /* DMA21 Current Address */
-#define REG_DMA21_STAT                  0xFFC09030         /* DMA21 Status Register */
-#define REG_DMA21_XCNT_CUR              0xFFC09034         /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA21_YCNT_CUR              0xFFC09038         /* DMA21 Current Row Count (2D only) */
-#define REG_DMA21_BWLCNT                0xFFC09040         /* DMA21 Bandwidth Limit Count */
-#define REG_DMA21_BWLCNT_CUR            0xFFC09044         /* DMA21 Bandwidth Limit Count Current */
-#define REG_DMA21_BWMCNT                0xFFC09048         /* DMA21 Bandwidth Monitor Count */
-#define REG_DMA21_BWMCNT_CUR            0xFFC0904C         /* DMA21 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA22
-   ========================= */
-#define REG_DMA22_DSCPTR_NXT            0xFFC09080         /* DMA22 Pointer to Next Initial Descriptor */
-#define REG_DMA22_ADDRSTART             0xFFC09084         /* DMA22 Start Address of Current Buffer */
-#define REG_DMA22_CFG                   0xFFC09088         /* DMA22 Configuration Register */
-#define REG_DMA22_XCNT                  0xFFC0908C         /* DMA22 Inner Loop Count Start Value */
-#define REG_DMA22_XMOD                  0xFFC09090         /* DMA22 Inner Loop Address Increment */
-#define REG_DMA22_YCNT                  0xFFC09094         /* DMA22 Outer Loop Count Start Value (2D only) */
-#define REG_DMA22_YMOD                  0xFFC09098         /* DMA22 Outer Loop Address Increment (2D only) */
-#define REG_DMA22_DSCPTR_CUR            0xFFC090A4         /* DMA22 Current Descriptor Pointer */
-#define REG_DMA22_DSCPTR_PRV            0xFFC090A8         /* DMA22 Previous Initial Descriptor Pointer */
-#define REG_DMA22_ADDR_CUR              0xFFC090AC         /* DMA22 Current Address */
-#define REG_DMA22_STAT                  0xFFC090B0         /* DMA22 Status Register */
-#define REG_DMA22_XCNT_CUR              0xFFC090B4         /* DMA22 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA22_YCNT_CUR              0xFFC090B8         /* DMA22 Current Row Count (2D only) */
-#define REG_DMA22_BWLCNT                0xFFC090C0         /* DMA22 Bandwidth Limit Count */
-#define REG_DMA22_BWLCNT_CUR            0xFFC090C4         /* DMA22 Bandwidth Limit Count Current */
-#define REG_DMA22_BWMCNT                0xFFC090C8         /* DMA22 Bandwidth Monitor Count */
-#define REG_DMA22_BWMCNT_CUR            0xFFC090CC         /* DMA22 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA23
-   ========================= */
-#define REG_DMA23_DSCPTR_NXT            0xFFC09100         /* DMA23 Pointer to Next Initial Descriptor */
-#define REG_DMA23_ADDRSTART             0xFFC09104         /* DMA23 Start Address of Current Buffer */
-#define REG_DMA23_CFG                   0xFFC09108         /* DMA23 Configuration Register */
-#define REG_DMA23_XCNT                  0xFFC0910C         /* DMA23 Inner Loop Count Start Value */
-#define REG_DMA23_XMOD                  0xFFC09110         /* DMA23 Inner Loop Address Increment */
-#define REG_DMA23_YCNT                  0xFFC09114         /* DMA23 Outer Loop Count Start Value (2D only) */
-#define REG_DMA23_YMOD                  0xFFC09118         /* DMA23 Outer Loop Address Increment (2D only) */
-#define REG_DMA23_DSCPTR_CUR            0xFFC09124         /* DMA23 Current Descriptor Pointer */
-#define REG_DMA23_DSCPTR_PRV            0xFFC09128         /* DMA23 Previous Initial Descriptor Pointer */
-#define REG_DMA23_ADDR_CUR              0xFFC0912C         /* DMA23 Current Address */
-#define REG_DMA23_STAT                  0xFFC09130         /* DMA23 Status Register */
-#define REG_DMA23_XCNT_CUR              0xFFC09134         /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA23_YCNT_CUR              0xFFC09138         /* DMA23 Current Row Count (2D only) */
-#define REG_DMA23_BWLCNT                0xFFC09140         /* DMA23 Bandwidth Limit Count */
-#define REG_DMA23_BWLCNT_CUR            0xFFC09144         /* DMA23 Bandwidth Limit Count Current */
-#define REG_DMA23_BWMCNT                0xFFC09148         /* DMA23 Bandwidth Monitor Count */
-#define REG_DMA23_BWMCNT_CUR            0xFFC0914C         /* DMA23 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA24
-   ========================= */
-#define REG_DMA24_DSCPTR_NXT            0xFFC09180         /* DMA24 Pointer to Next Initial Descriptor */
-#define REG_DMA24_ADDRSTART             0xFFC09184         /* DMA24 Start Address of Current Buffer */
-#define REG_DMA24_CFG                   0xFFC09188         /* DMA24 Configuration Register */
-#define REG_DMA24_XCNT                  0xFFC0918C         /* DMA24 Inner Loop Count Start Value */
-#define REG_DMA24_XMOD                  0xFFC09190         /* DMA24 Inner Loop Address Increment */
-#define REG_DMA24_YCNT                  0xFFC09194         /* DMA24 Outer Loop Count Start Value (2D only) */
-#define REG_DMA24_YMOD                  0xFFC09198         /* DMA24 Outer Loop Address Increment (2D only) */
-#define REG_DMA24_DSCPTR_CUR            0xFFC091A4         /* DMA24 Current Descriptor Pointer */
-#define REG_DMA24_DSCPTR_PRV            0xFFC091A8         /* DMA24 Previous Initial Descriptor Pointer */
-#define REG_DMA24_ADDR_CUR              0xFFC091AC         /* DMA24 Current Address */
-#define REG_DMA24_STAT                  0xFFC091B0         /* DMA24 Status Register */
-#define REG_DMA24_XCNT_CUR              0xFFC091B4         /* DMA24 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA24_YCNT_CUR              0xFFC091B8         /* DMA24 Current Row Count (2D only) */
-#define REG_DMA24_BWLCNT                0xFFC091C0         /* DMA24 Bandwidth Limit Count */
-#define REG_DMA24_BWLCNT_CUR            0xFFC091C4         /* DMA24 Bandwidth Limit Count Current */
-#define REG_DMA24_BWMCNT                0xFFC091C8         /* DMA24 Bandwidth Monitor Count */
-#define REG_DMA24_BWMCNT_CUR            0xFFC091CC         /* DMA24 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA25
-   ========================= */
-#define REG_DMA25_DSCPTR_NXT            0xFFC09200         /* DMA25 Pointer to Next Initial Descriptor */
-#define REG_DMA25_ADDRSTART             0xFFC09204         /* DMA25 Start Address of Current Buffer */
-#define REG_DMA25_CFG                   0xFFC09208         /* DMA25 Configuration Register */
-#define REG_DMA25_XCNT                  0xFFC0920C         /* DMA25 Inner Loop Count Start Value */
-#define REG_DMA25_XMOD                  0xFFC09210         /* DMA25 Inner Loop Address Increment */
-#define REG_DMA25_YCNT                  0xFFC09214         /* DMA25 Outer Loop Count Start Value (2D only) */
-#define REG_DMA25_YMOD                  0xFFC09218         /* DMA25 Outer Loop Address Increment (2D only) */
-#define REG_DMA25_DSCPTR_CUR            0xFFC09224         /* DMA25 Current Descriptor Pointer */
-#define REG_DMA25_DSCPTR_PRV            0xFFC09228         /* DMA25 Previous Initial Descriptor Pointer */
-#define REG_DMA25_ADDR_CUR              0xFFC0922C         /* DMA25 Current Address */
-#define REG_DMA25_STAT                  0xFFC09230         /* DMA25 Status Register */
-#define REG_DMA25_XCNT_CUR              0xFFC09234         /* DMA25 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA25_YCNT_CUR              0xFFC09238         /* DMA25 Current Row Count (2D only) */
-#define REG_DMA25_BWLCNT                0xFFC09240         /* DMA25 Bandwidth Limit Count */
-#define REG_DMA25_BWLCNT_CUR            0xFFC09244         /* DMA25 Bandwidth Limit Count Current */
-#define REG_DMA25_BWMCNT                0xFFC09248         /* DMA25 Bandwidth Monitor Count */
-#define REG_DMA25_BWMCNT_CUR            0xFFC0924C         /* DMA25 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA26
-   ========================= */
-#define REG_DMA26_DSCPTR_NXT            0xFFC09280         /* DMA26 Pointer to Next Initial Descriptor */
-#define REG_DMA26_ADDRSTART             0xFFC09284         /* DMA26 Start Address of Current Buffer */
-#define REG_DMA26_CFG                   0xFFC09288         /* DMA26 Configuration Register */
-#define REG_DMA26_XCNT                  0xFFC0928C         /* DMA26 Inner Loop Count Start Value */
-#define REG_DMA26_XMOD                  0xFFC09290         /* DMA26 Inner Loop Address Increment */
-#define REG_DMA26_YCNT                  0xFFC09294         /* DMA26 Outer Loop Count Start Value (2D only) */
-#define REG_DMA26_YMOD                  0xFFC09298         /* DMA26 Outer Loop Address Increment (2D only) */
-#define REG_DMA26_DSCPTR_CUR            0xFFC092A4         /* DMA26 Current Descriptor Pointer */
-#define REG_DMA26_DSCPTR_PRV            0xFFC092A8         /* DMA26 Previous Initial Descriptor Pointer */
-#define REG_DMA26_ADDR_CUR              0xFFC092AC         /* DMA26 Current Address */
-#define REG_DMA26_STAT                  0xFFC092B0         /* DMA26 Status Register */
-#define REG_DMA26_XCNT_CUR              0xFFC092B4         /* DMA26 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA26_YCNT_CUR              0xFFC092B8         /* DMA26 Current Row Count (2D only) */
-#define REG_DMA26_BWLCNT                0xFFC092C0         /* DMA26 Bandwidth Limit Count */
-#define REG_DMA26_BWLCNT_CUR            0xFFC092C4         /* DMA26 Bandwidth Limit Count Current */
-#define REG_DMA26_BWMCNT                0xFFC092C8         /* DMA26 Bandwidth Monitor Count */
-#define REG_DMA26_BWMCNT_CUR            0xFFC092CC         /* DMA26 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA27
-   ========================= */
-#define REG_DMA27_DSCPTR_NXT            0xFFC09300         /* DMA27 Pointer to Next Initial Descriptor */
-#define REG_DMA27_ADDRSTART             0xFFC09304         /* DMA27 Start Address of Current Buffer */
-#define REG_DMA27_CFG                   0xFFC09308         /* DMA27 Configuration Register */
-#define REG_DMA27_XCNT                  0xFFC0930C         /* DMA27 Inner Loop Count Start Value */
-#define REG_DMA27_XMOD                  0xFFC09310         /* DMA27 Inner Loop Address Increment */
-#define REG_DMA27_YCNT                  0xFFC09314         /* DMA27 Outer Loop Count Start Value (2D only) */
-#define REG_DMA27_YMOD                  0xFFC09318         /* DMA27 Outer Loop Address Increment (2D only) */
-#define REG_DMA27_DSCPTR_CUR            0xFFC09324         /* DMA27 Current Descriptor Pointer */
-#define REG_DMA27_DSCPTR_PRV            0xFFC09328         /* DMA27 Previous Initial Descriptor Pointer */
-#define REG_DMA27_ADDR_CUR              0xFFC0932C         /* DMA27 Current Address */
-#define REG_DMA27_STAT                  0xFFC09330         /* DMA27 Status Register */
-#define REG_DMA27_XCNT_CUR              0xFFC09334         /* DMA27 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA27_YCNT_CUR              0xFFC09338         /* DMA27 Current Row Count (2D only) */
-#define REG_DMA27_BWLCNT                0xFFC09340         /* DMA27 Bandwidth Limit Count */
-#define REG_DMA27_BWLCNT_CUR            0xFFC09344         /* DMA27 Bandwidth Limit Count Current */
-#define REG_DMA27_BWMCNT                0xFFC09348         /* DMA27 Bandwidth Monitor Count */
-#define REG_DMA27_BWMCNT_CUR            0xFFC0934C         /* DMA27 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA28
-   ========================= */
-#define REG_DMA28_DSCPTR_NXT            0xFFC09380         /* DMA28 Pointer to Next Initial Descriptor */
-#define REG_DMA28_ADDRSTART             0xFFC09384         /* DMA28 Start Address of Current Buffer */
-#define REG_DMA28_CFG                   0xFFC09388         /* DMA28 Configuration Register */
-#define REG_DMA28_XCNT                  0xFFC0938C         /* DMA28 Inner Loop Count Start Value */
-#define REG_DMA28_XMOD                  0xFFC09390         /* DMA28 Inner Loop Address Increment */
-#define REG_DMA28_YCNT                  0xFFC09394         /* DMA28 Outer Loop Count Start Value (2D only) */
-#define REG_DMA28_YMOD                  0xFFC09398         /* DMA28 Outer Loop Address Increment (2D only) */
-#define REG_DMA28_DSCPTR_CUR            0xFFC093A4         /* DMA28 Current Descriptor Pointer */
-#define REG_DMA28_DSCPTR_PRV            0xFFC093A8         /* DMA28 Previous Initial Descriptor Pointer */
-#define REG_DMA28_ADDR_CUR              0xFFC093AC         /* DMA28 Current Address */
-#define REG_DMA28_STAT                  0xFFC093B0         /* DMA28 Status Register */
-#define REG_DMA28_XCNT_CUR              0xFFC093B4         /* DMA28 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA28_YCNT_CUR              0xFFC093B8         /* DMA28 Current Row Count (2D only) */
-#define REG_DMA28_BWLCNT                0xFFC093C0         /* DMA28 Bandwidth Limit Count */
-#define REG_DMA28_BWLCNT_CUR            0xFFC093C4         /* DMA28 Bandwidth Limit Count Current */
-#define REG_DMA28_BWMCNT                0xFFC093C8         /* DMA28 Bandwidth Monitor Count */
-#define REG_DMA28_BWMCNT_CUR            0xFFC093CC         /* DMA28 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA29
-   ========================= */
-#define REG_DMA29_DSCPTR_NXT            0xFFC0B000         /* DMA29 Pointer to Next Initial Descriptor */
-#define REG_DMA29_ADDRSTART             0xFFC0B004         /* DMA29 Start Address of Current Buffer */
-#define REG_DMA29_CFG                   0xFFC0B008         /* DMA29 Configuration Register */
-#define REG_DMA29_XCNT                  0xFFC0B00C         /* DMA29 Inner Loop Count Start Value */
-#define REG_DMA29_XMOD                  0xFFC0B010         /* DMA29 Inner Loop Address Increment */
-#define REG_DMA29_YCNT                  0xFFC0B014         /* DMA29 Outer Loop Count Start Value (2D only) */
-#define REG_DMA29_YMOD                  0xFFC0B018         /* DMA29 Outer Loop Address Increment (2D only) */
-#define REG_DMA29_DSCPTR_CUR            0xFFC0B024         /* DMA29 Current Descriptor Pointer */
-#define REG_DMA29_DSCPTR_PRV            0xFFC0B028         /* DMA29 Previous Initial Descriptor Pointer */
-#define REG_DMA29_ADDR_CUR              0xFFC0B02C         /* DMA29 Current Address */
-#define REG_DMA29_STAT                  0xFFC0B030         /* DMA29 Status Register */
-#define REG_DMA29_XCNT_CUR              0xFFC0B034         /* DMA29 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA29_YCNT_CUR              0xFFC0B038         /* DMA29 Current Row Count (2D only) */
-#define REG_DMA29_BWLCNT                0xFFC0B040         /* DMA29 Bandwidth Limit Count */
-#define REG_DMA29_BWLCNT_CUR            0xFFC0B044         /* DMA29 Bandwidth Limit Count Current */
-#define REG_DMA29_BWMCNT                0xFFC0B048         /* DMA29 Bandwidth Monitor Count */
-#define REG_DMA29_BWMCNT_CUR            0xFFC0B04C         /* DMA29 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA30
-   ========================= */
-#define REG_DMA30_DSCPTR_NXT            0xFFC0B080         /* DMA30 Pointer to Next Initial Descriptor */
-#define REG_DMA30_ADDRSTART             0xFFC0B084         /* DMA30 Start Address of Current Buffer */
-#define REG_DMA30_CFG                   0xFFC0B088         /* DMA30 Configuration Register */
-#define REG_DMA30_XCNT                  0xFFC0B08C         /* DMA30 Inner Loop Count Start Value */
-#define REG_DMA30_XMOD                  0xFFC0B090         /* DMA30 Inner Loop Address Increment */
-#define REG_DMA30_YCNT                  0xFFC0B094         /* DMA30 Outer Loop Count Start Value (2D only) */
-#define REG_DMA30_YMOD                  0xFFC0B098         /* DMA30 Outer Loop Address Increment (2D only) */
-#define REG_DMA30_DSCPTR_CUR            0xFFC0B0A4         /* DMA30 Current Descriptor Pointer */
-#define REG_DMA30_DSCPTR_PRV            0xFFC0B0A8         /* DMA30 Previous Initial Descriptor Pointer */
-#define REG_DMA30_ADDR_CUR              0xFFC0B0AC         /* DMA30 Current Address */
-#define REG_DMA30_STAT                  0xFFC0B0B0         /* DMA30 Status Register */
-#define REG_DMA30_XCNT_CUR              0xFFC0B0B4         /* DMA30 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA30_YCNT_CUR              0xFFC0B0B8         /* DMA30 Current Row Count (2D only) */
-#define REG_DMA30_BWLCNT                0xFFC0B0C0         /* DMA30 Bandwidth Limit Count */
-#define REG_DMA30_BWLCNT_CUR            0xFFC0B0C4         /* DMA30 Bandwidth Limit Count Current */
-#define REG_DMA30_BWMCNT                0xFFC0B0C8         /* DMA30 Bandwidth Monitor Count */
-#define REG_DMA30_BWMCNT_CUR            0xFFC0B0CC         /* DMA30 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA31
-   ========================= */
-#define REG_DMA31_DSCPTR_NXT            0xFFC0B100         /* DMA31 Pointer to Next Initial Descriptor */
-#define REG_DMA31_ADDRSTART             0xFFC0B104         /* DMA31 Start Address of Current Buffer */
-#define REG_DMA31_CFG                   0xFFC0B108         /* DMA31 Configuration Register */
-#define REG_DMA31_XCNT                  0xFFC0B10C         /* DMA31 Inner Loop Count Start Value */
-#define REG_DMA31_XMOD                  0xFFC0B110         /* DMA31 Inner Loop Address Increment */
-#define REG_DMA31_YCNT                  0xFFC0B114         /* DMA31 Outer Loop Count Start Value (2D only) */
-#define REG_DMA31_YMOD                  0xFFC0B118         /* DMA31 Outer Loop Address Increment (2D only) */
-#define REG_DMA31_DSCPTR_CUR            0xFFC0B124         /* DMA31 Current Descriptor Pointer */
-#define REG_DMA31_DSCPTR_PRV            0xFFC0B128         /* DMA31 Previous Initial Descriptor Pointer */
-#define REG_DMA31_ADDR_CUR              0xFFC0B12C         /* DMA31 Current Address */
-#define REG_DMA31_STAT                  0xFFC0B130         /* DMA31 Status Register */
-#define REG_DMA31_XCNT_CUR              0xFFC0B134         /* DMA31 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA31_YCNT_CUR              0xFFC0B138         /* DMA31 Current Row Count (2D only) */
-#define REG_DMA31_BWLCNT                0xFFC0B140         /* DMA31 Bandwidth Limit Count */
-#define REG_DMA31_BWLCNT_CUR            0xFFC0B144         /* DMA31 Bandwidth Limit Count Current */
-#define REG_DMA31_BWMCNT                0xFFC0B148         /* DMA31 Bandwidth Monitor Count */
-#define REG_DMA31_BWMCNT_CUR            0xFFC0B14C         /* DMA31 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA32
-   ========================= */
-#define REG_DMA32_DSCPTR_NXT            0xFFC0B180         /* DMA32 Pointer to Next Initial Descriptor */
-#define REG_DMA32_ADDRSTART             0xFFC0B184         /* DMA32 Start Address of Current Buffer */
-#define REG_DMA32_CFG                   0xFFC0B188         /* DMA32 Configuration Register */
-#define REG_DMA32_XCNT                  0xFFC0B18C         /* DMA32 Inner Loop Count Start Value */
-#define REG_DMA32_XMOD                  0xFFC0B190         /* DMA32 Inner Loop Address Increment */
-#define REG_DMA32_YCNT                  0xFFC0B194         /* DMA32 Outer Loop Count Start Value (2D only) */
-#define REG_DMA32_YMOD                  0xFFC0B198         /* DMA32 Outer Loop Address Increment (2D only) */
-#define REG_DMA32_DSCPTR_CUR            0xFFC0B1A4         /* DMA32 Current Descriptor Pointer */
-#define REG_DMA32_DSCPTR_PRV            0xFFC0B1A8         /* DMA32 Previous Initial Descriptor Pointer */
-#define REG_DMA32_ADDR_CUR              0xFFC0B1AC         /* DMA32 Current Address */
-#define REG_DMA32_STAT                  0xFFC0B1B0         /* DMA32 Status Register */
-#define REG_DMA32_XCNT_CUR              0xFFC0B1B4         /* DMA32 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA32_YCNT_CUR              0xFFC0B1B8         /* DMA32 Current Row Count (2D only) */
-#define REG_DMA32_BWLCNT                0xFFC0B1C0         /* DMA32 Bandwidth Limit Count */
-#define REG_DMA32_BWLCNT_CUR            0xFFC0B1C4         /* DMA32 Bandwidth Limit Count Current */
-#define REG_DMA32_BWMCNT                0xFFC0B1C8         /* DMA32 Bandwidth Monitor Count */
-#define REG_DMA32_BWMCNT_CUR            0xFFC0B1CC         /* DMA32 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA33
-   ========================= */
-#define REG_DMA33_DSCPTR_NXT            0xFFC0D000         /* DMA33 Pointer to Next Initial Descriptor */
-#define REG_DMA33_ADDRSTART             0xFFC0D004         /* DMA33 Start Address of Current Buffer */
-#define REG_DMA33_CFG                   0xFFC0D008         /* DMA33 Configuration Register */
-#define REG_DMA33_XCNT                  0xFFC0D00C         /* DMA33 Inner Loop Count Start Value */
-#define REG_DMA33_XMOD                  0xFFC0D010         /* DMA33 Inner Loop Address Increment */
-#define REG_DMA33_YCNT                  0xFFC0D014         /* DMA33 Outer Loop Count Start Value (2D only) */
-#define REG_DMA33_YMOD                  0xFFC0D018         /* DMA33 Outer Loop Address Increment (2D only) */
-#define REG_DMA33_DSCPTR_CUR            0xFFC0D024         /* DMA33 Current Descriptor Pointer */
-#define REG_DMA33_DSCPTR_PRV            0xFFC0D028         /* DMA33 Previous Initial Descriptor Pointer */
-#define REG_DMA33_ADDR_CUR              0xFFC0D02C         /* DMA33 Current Address */
-#define REG_DMA33_STAT                  0xFFC0D030         /* DMA33 Status Register */
-#define REG_DMA33_XCNT_CUR              0xFFC0D034         /* DMA33 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA33_YCNT_CUR              0xFFC0D038         /* DMA33 Current Row Count (2D only) */
-#define REG_DMA33_BWLCNT                0xFFC0D040         /* DMA33 Bandwidth Limit Count */
-#define REG_DMA33_BWLCNT_CUR            0xFFC0D044         /* DMA33 Bandwidth Limit Count Current */
-#define REG_DMA33_BWMCNT                0xFFC0D048         /* DMA33 Bandwidth Monitor Count */
-#define REG_DMA33_BWMCNT_CUR            0xFFC0D04C         /* DMA33 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA34
-   ========================= */
-#define REG_DMA34_DSCPTR_NXT            0xFFC0D080         /* DMA34 Pointer to Next Initial Descriptor */
-#define REG_DMA34_ADDRSTART             0xFFC0D084         /* DMA34 Start Address of Current Buffer */
-#define REG_DMA34_CFG                   0xFFC0D088         /* DMA34 Configuration Register */
-#define REG_DMA34_XCNT                  0xFFC0D08C         /* DMA34 Inner Loop Count Start Value */
-#define REG_DMA34_XMOD                  0xFFC0D090         /* DMA34 Inner Loop Address Increment */
-#define REG_DMA34_YCNT                  0xFFC0D094         /* DMA34 Outer Loop Count Start Value (2D only) */
-#define REG_DMA34_YMOD                  0xFFC0D098         /* DMA34 Outer Loop Address Increment (2D only) */
-#define REG_DMA34_DSCPTR_CUR            0xFFC0D0A4         /* DMA34 Current Descriptor Pointer */
-#define REG_DMA34_DSCPTR_PRV            0xFFC0D0A8         /* DMA34 Previous Initial Descriptor Pointer */
-#define REG_DMA34_ADDR_CUR              0xFFC0D0AC         /* DMA34 Current Address */
-#define REG_DMA34_STAT                  0xFFC0D0B0         /* DMA34 Status Register */
-#define REG_DMA34_XCNT_CUR              0xFFC0D0B4         /* DMA34 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA34_YCNT_CUR              0xFFC0D0B8         /* DMA34 Current Row Count (2D only) */
-#define REG_DMA34_BWLCNT                0xFFC0D0C0         /* DMA34 Bandwidth Limit Count */
-#define REG_DMA34_BWLCNT_CUR            0xFFC0D0C4         /* DMA34 Bandwidth Limit Count Current */
-#define REG_DMA34_BWMCNT                0xFFC0D0C8         /* DMA34 Bandwidth Monitor Count */
-#define REG_DMA34_BWMCNT_CUR            0xFFC0D0CC         /* DMA34 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA35
-   ========================= */
-#define REG_DMA35_DSCPTR_NXT            0xFFC10000         /* DMA35 Pointer to Next Initial Descriptor */
-#define REG_DMA35_ADDRSTART             0xFFC10004         /* DMA35 Start Address of Current Buffer */
-#define REG_DMA35_CFG                   0xFFC10008         /* DMA35 Configuration Register */
-#define REG_DMA35_XCNT                  0xFFC1000C         /* DMA35 Inner Loop Count Start Value */
-#define REG_DMA35_XMOD                  0xFFC10010         /* DMA35 Inner Loop Address Increment */
-#define REG_DMA35_YCNT                  0xFFC10014         /* DMA35 Outer Loop Count Start Value (2D only) */
-#define REG_DMA35_YMOD                  0xFFC10018         /* DMA35 Outer Loop Address Increment (2D only) */
-#define REG_DMA35_DSCPTR_CUR            0xFFC10024         /* DMA35 Current Descriptor Pointer */
-#define REG_DMA35_DSCPTR_PRV            0xFFC10028         /* DMA35 Previous Initial Descriptor Pointer */
-#define REG_DMA35_ADDR_CUR              0xFFC1002C         /* DMA35 Current Address */
-#define REG_DMA35_STAT                  0xFFC10030         /* DMA35 Status Register */
-#define REG_DMA35_XCNT_CUR              0xFFC10034         /* DMA35 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA35_YCNT_CUR              0xFFC10038         /* DMA35 Current Row Count (2D only) */
-#define REG_DMA35_BWLCNT                0xFFC10040         /* DMA35 Bandwidth Limit Count */
-#define REG_DMA35_BWLCNT_CUR            0xFFC10044         /* DMA35 Bandwidth Limit Count Current */
-#define REG_DMA35_BWMCNT                0xFFC10048         /* DMA35 Bandwidth Monitor Count */
-#define REG_DMA35_BWMCNT_CUR            0xFFC1004C         /* DMA35 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA36
-   ========================= */
-#define REG_DMA36_DSCPTR_NXT            0xFFC10080         /* DMA36 Pointer to Next Initial Descriptor */
-#define REG_DMA36_ADDRSTART             0xFFC10084         /* DMA36 Start Address of Current Buffer */
-#define REG_DMA36_CFG                   0xFFC10088         /* DMA36 Configuration Register */
-#define REG_DMA36_XCNT                  0xFFC1008C         /* DMA36 Inner Loop Count Start Value */
-#define REG_DMA36_XMOD                  0xFFC10090         /* DMA36 Inner Loop Address Increment */
-#define REG_DMA36_YCNT                  0xFFC10094         /* DMA36 Outer Loop Count Start Value (2D only) */
-#define REG_DMA36_YMOD                  0xFFC10098         /* DMA36 Outer Loop Address Increment (2D only) */
-#define REG_DMA36_DSCPTR_CUR            0xFFC100A4         /* DMA36 Current Descriptor Pointer */
-#define REG_DMA36_DSCPTR_PRV            0xFFC100A8         /* DMA36 Previous Initial Descriptor Pointer */
-#define REG_DMA36_ADDR_CUR              0xFFC100AC         /* DMA36 Current Address */
-#define REG_DMA36_STAT                  0xFFC100B0         /* DMA36 Status Register */
-#define REG_DMA36_XCNT_CUR              0xFFC100B4         /* DMA36 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA36_YCNT_CUR              0xFFC100B8         /* DMA36 Current Row Count (2D only) */
-#define REG_DMA36_BWLCNT                0xFFC100C0         /* DMA36 Bandwidth Limit Count */
-#define REG_DMA36_BWLCNT_CUR            0xFFC100C4         /* DMA36 Bandwidth Limit Count Current */
-#define REG_DMA36_BWMCNT                0xFFC100C8         /* DMA36 Bandwidth Monitor Count */
-#define REG_DMA36_BWMCNT_CUR            0xFFC100CC         /* DMA36 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA37
-   ========================= */
-#define REG_DMA37_DSCPTR_NXT            0xFFC10100         /* DMA37 Pointer to Next Initial Descriptor */
-#define REG_DMA37_ADDRSTART             0xFFC10104         /* DMA37 Start Address of Current Buffer */
-#define REG_DMA37_CFG                   0xFFC10108         /* DMA37 Configuration Register */
-#define REG_DMA37_XCNT                  0xFFC1010C         /* DMA37 Inner Loop Count Start Value */
-#define REG_DMA37_XMOD                  0xFFC10110         /* DMA37 Inner Loop Address Increment */
-#define REG_DMA37_YCNT                  0xFFC10114         /* DMA37 Outer Loop Count Start Value (2D only) */
-#define REG_DMA37_YMOD                  0xFFC10118         /* DMA37 Outer Loop Address Increment (2D only) */
-#define REG_DMA37_DSCPTR_CUR            0xFFC10124         /* DMA37 Current Descriptor Pointer */
-#define REG_DMA37_DSCPTR_PRV            0xFFC10128         /* DMA37 Previous Initial Descriptor Pointer */
-#define REG_DMA37_ADDR_CUR              0xFFC1012C         /* DMA37 Current Address */
-#define REG_DMA37_STAT                  0xFFC10130         /* DMA37 Status Register */
-#define REG_DMA37_XCNT_CUR              0xFFC10134         /* DMA37 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA37_YCNT_CUR              0xFFC10138         /* DMA37 Current Row Count (2D only) */
-#define REG_DMA37_BWLCNT                0xFFC10140         /* DMA37 Bandwidth Limit Count */
-#define REG_DMA37_BWLCNT_CUR            0xFFC10144         /* DMA37 Bandwidth Limit Count Current */
-#define REG_DMA37_BWMCNT                0xFFC10148         /* DMA37 Bandwidth Monitor Count */
-#define REG_DMA37_BWMCNT_CUR            0xFFC1014C         /* DMA37 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA38
-   ========================= */
-#define REG_DMA38_DSCPTR_NXT            0xFFC12000         /* DMA38 Pointer to Next Initial Descriptor */
-#define REG_DMA38_ADDRSTART             0xFFC12004         /* DMA38 Start Address of Current Buffer */
-#define REG_DMA38_CFG                   0xFFC12008         /* DMA38 Configuration Register */
-#define REG_DMA38_XCNT                  0xFFC1200C         /* DMA38 Inner Loop Count Start Value */
-#define REG_DMA38_XMOD                  0xFFC12010         /* DMA38 Inner Loop Address Increment */
-#define REG_DMA38_YCNT                  0xFFC12014         /* DMA38 Outer Loop Count Start Value (2D only) */
-#define REG_DMA38_YMOD                  0xFFC12018         /* DMA38 Outer Loop Address Increment (2D only) */
-#define REG_DMA38_DSCPTR_CUR            0xFFC12024         /* DMA38 Current Descriptor Pointer */
-#define REG_DMA38_DSCPTR_PRV            0xFFC12028         /* DMA38 Previous Initial Descriptor Pointer */
-#define REG_DMA38_ADDR_CUR              0xFFC1202C         /* DMA38 Current Address */
-#define REG_DMA38_STAT                  0xFFC12030         /* DMA38 Status Register */
-#define REG_DMA38_XCNT_CUR              0xFFC12034         /* DMA38 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA38_YCNT_CUR              0xFFC12038         /* DMA38 Current Row Count (2D only) */
-#define REG_DMA38_BWLCNT                0xFFC12040         /* DMA38 Bandwidth Limit Count */
-#define REG_DMA38_BWLCNT_CUR            0xFFC12044         /* DMA38 Bandwidth Limit Count Current */
-#define REG_DMA38_BWMCNT                0xFFC12048         /* DMA38 Bandwidth Monitor Count */
-#define REG_DMA38_BWMCNT_CUR            0xFFC1204C         /* DMA38 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA39
-   ========================= */
-#define REG_DMA39_DSCPTR_NXT            0xFFC12080         /* DMA39 Pointer to Next Initial Descriptor */
-#define REG_DMA39_ADDRSTART             0xFFC12084         /* DMA39 Start Address of Current Buffer */
-#define REG_DMA39_CFG                   0xFFC12088         /* DMA39 Configuration Register */
-#define REG_DMA39_XCNT                  0xFFC1208C         /* DMA39 Inner Loop Count Start Value */
-#define REG_DMA39_XMOD                  0xFFC12090         /* DMA39 Inner Loop Address Increment */
-#define REG_DMA39_YCNT                  0xFFC12094         /* DMA39 Outer Loop Count Start Value (2D only) */
-#define REG_DMA39_YMOD                  0xFFC12098         /* DMA39 Outer Loop Address Increment (2D only) */
-#define REG_DMA39_DSCPTR_CUR            0xFFC120A4         /* DMA39 Current Descriptor Pointer */
-#define REG_DMA39_DSCPTR_PRV            0xFFC120A8         /* DMA39 Previous Initial Descriptor Pointer */
-#define REG_DMA39_ADDR_CUR              0xFFC120AC         /* DMA39 Current Address */
-#define REG_DMA39_STAT                  0xFFC120B0         /* DMA39 Status Register */
-#define REG_DMA39_XCNT_CUR              0xFFC120B4         /* DMA39 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA39_YCNT_CUR              0xFFC120B8         /* DMA39 Current Row Count (2D only) */
-#define REG_DMA39_BWLCNT                0xFFC120C0         /* DMA39 Bandwidth Limit Count */
-#define REG_DMA39_BWLCNT_CUR            0xFFC120C4         /* DMA39 Bandwidth Limit Count Current */
-#define REG_DMA39_BWMCNT                0xFFC120C8         /* DMA39 Bandwidth Monitor Count */
-#define REG_DMA39_BWMCNT_CUR            0xFFC120CC         /* DMA39 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA40
-   ========================= */
-#define REG_DMA40_DSCPTR_NXT            0xFFC12100         /* DMA40 Pointer to Next Initial Descriptor */
-#define REG_DMA40_ADDRSTART             0xFFC12104         /* DMA40 Start Address of Current Buffer */
-#define REG_DMA40_CFG                   0xFFC12108         /* DMA40 Configuration Register */
-#define REG_DMA40_XCNT                  0xFFC1210C         /* DMA40 Inner Loop Count Start Value */
-#define REG_DMA40_XMOD                  0xFFC12110         /* DMA40 Inner Loop Address Increment */
-#define REG_DMA40_YCNT                  0xFFC12114         /* DMA40 Outer Loop Count Start Value (2D only) */
-#define REG_DMA40_YMOD                  0xFFC12118         /* DMA40 Outer Loop Address Increment (2D only) */
-#define REG_DMA40_DSCPTR_CUR            0xFFC12124         /* DMA40 Current Descriptor Pointer */
-#define REG_DMA40_DSCPTR_PRV            0xFFC12128         /* DMA40 Previous Initial Descriptor Pointer */
-#define REG_DMA40_ADDR_CUR              0xFFC1212C         /* DMA40 Current Address */
-#define REG_DMA40_STAT                  0xFFC12130         /* DMA40 Status Register */
-#define REG_DMA40_XCNT_CUR              0xFFC12134         /* DMA40 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA40_YCNT_CUR              0xFFC12138         /* DMA40 Current Row Count (2D only) */
-#define REG_DMA40_BWLCNT                0xFFC12140         /* DMA40 Bandwidth Limit Count */
-#define REG_DMA40_BWLCNT_CUR            0xFFC12144         /* DMA40 Bandwidth Limit Count Current */
-#define REG_DMA40_BWMCNT                0xFFC12148         /* DMA40 Bandwidth Monitor Count */
-#define REG_DMA40_BWMCNT_CUR            0xFFC1214C         /* DMA40 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA41
-   ========================= */
-#define REG_DMA41_DSCPTR_NXT            0xFFC12180         /* DMA41 Pointer to Next Initial Descriptor */
-#define REG_DMA41_ADDRSTART             0xFFC12184         /* DMA41 Start Address of Current Buffer */
-#define REG_DMA41_CFG                   0xFFC12188         /* DMA41 Configuration Register */
-#define REG_DMA41_XCNT                  0xFFC1218C         /* DMA41 Inner Loop Count Start Value */
-#define REG_DMA41_XMOD                  0xFFC12190         /* DMA41 Inner Loop Address Increment */
-#define REG_DMA41_YCNT                  0xFFC12194         /* DMA41 Outer Loop Count Start Value (2D only) */
-#define REG_DMA41_YMOD                  0xFFC12198         /* DMA41 Outer Loop Address Increment (2D only) */
-#define REG_DMA41_DSCPTR_CUR            0xFFC121A4         /* DMA41 Current Descriptor Pointer */
-#define REG_DMA41_DSCPTR_PRV            0xFFC121A8         /* DMA41 Previous Initial Descriptor Pointer */
-#define REG_DMA41_ADDR_CUR              0xFFC121AC         /* DMA41 Current Address */
-#define REG_DMA41_STAT                  0xFFC121B0         /* DMA41 Status Register */
-#define REG_DMA41_XCNT_CUR              0xFFC121B4         /* DMA41 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA41_YCNT_CUR              0xFFC121B8         /* DMA41 Current Row Count (2D only) */
-#define REG_DMA41_BWLCNT                0xFFC121C0         /* DMA41 Bandwidth Limit Count */
-#define REG_DMA41_BWLCNT_CUR            0xFFC121C4         /* DMA41 Bandwidth Limit Count Current */
-#define REG_DMA41_BWMCNT                0xFFC121C8         /* DMA41 Bandwidth Monitor Count */
-#define REG_DMA41_BWMCNT_CUR            0xFFC121CC         /* DMA41 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA42
-   ========================= */
-#define REG_DMA42_DSCPTR_NXT            0xFFC14000         /* DMA42 Pointer to Next Initial Descriptor */
-#define REG_DMA42_ADDRSTART             0xFFC14004         /* DMA42 Start Address of Current Buffer */
-#define REG_DMA42_CFG                   0xFFC14008         /* DMA42 Configuration Register */
-#define REG_DMA42_XCNT                  0xFFC1400C         /* DMA42 Inner Loop Count Start Value */
-#define REG_DMA42_XMOD                  0xFFC14010         /* DMA42 Inner Loop Address Increment */
-#define REG_DMA42_YCNT                  0xFFC14014         /* DMA42 Outer Loop Count Start Value (2D only) */
-#define REG_DMA42_YMOD                  0xFFC14018         /* DMA42 Outer Loop Address Increment (2D only) */
-#define REG_DMA42_DSCPTR_CUR            0xFFC14024         /* DMA42 Current Descriptor Pointer */
-#define REG_DMA42_DSCPTR_PRV            0xFFC14028         /* DMA42 Previous Initial Descriptor Pointer */
-#define REG_DMA42_ADDR_CUR              0xFFC1402C         /* DMA42 Current Address */
-#define REG_DMA42_STAT                  0xFFC14030         /* DMA42 Status Register */
-#define REG_DMA42_XCNT_CUR              0xFFC14034         /* DMA42 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA42_YCNT_CUR              0xFFC14038         /* DMA42 Current Row Count (2D only) */
-#define REG_DMA42_BWLCNT                0xFFC14040         /* DMA42 Bandwidth Limit Count */
-#define REG_DMA42_BWLCNT_CUR            0xFFC14044         /* DMA42 Bandwidth Limit Count Current */
-#define REG_DMA42_BWMCNT                0xFFC14048         /* DMA42 Bandwidth Monitor Count */
-#define REG_DMA42_BWMCNT_CUR            0xFFC1404C         /* DMA42 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA43
-   ========================= */
-#define REG_DMA43_DSCPTR_NXT            0xFFC14080         /* DMA43 Pointer to Next Initial Descriptor */
-#define REG_DMA43_ADDRSTART             0xFFC14084         /* DMA43 Start Address of Current Buffer */
-#define REG_DMA43_CFG                   0xFFC14088         /* DMA43 Configuration Register */
-#define REG_DMA43_XCNT                  0xFFC1408C         /* DMA43 Inner Loop Count Start Value */
-#define REG_DMA43_XMOD                  0xFFC14090         /* DMA43 Inner Loop Address Increment */
-#define REG_DMA43_YCNT                  0xFFC14094         /* DMA43 Outer Loop Count Start Value (2D only) */
-#define REG_DMA43_YMOD                  0xFFC14098         /* DMA43 Outer Loop Address Increment (2D only) */
-#define REG_DMA43_DSCPTR_CUR            0xFFC140A4         /* DMA43 Current Descriptor Pointer */
-#define REG_DMA43_DSCPTR_PRV            0xFFC140A8         /* DMA43 Previous Initial Descriptor Pointer */
-#define REG_DMA43_ADDR_CUR              0xFFC140AC         /* DMA43 Current Address */
-#define REG_DMA43_STAT                  0xFFC140B0         /* DMA43 Status Register */
-#define REG_DMA43_XCNT_CUR              0xFFC140B4         /* DMA43 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA43_YCNT_CUR              0xFFC140B8         /* DMA43 Current Row Count (2D only) */
-#define REG_DMA43_BWLCNT                0xFFC140C0         /* DMA43 Bandwidth Limit Count */
-#define REG_DMA43_BWLCNT_CUR            0xFFC140C4         /* DMA43 Bandwidth Limit Count Current */
-#define REG_DMA43_BWMCNT                0xFFC140C8         /* DMA43 Bandwidth Monitor Count */
-#define REG_DMA43_BWMCNT_CUR            0xFFC140CC         /* DMA43 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA44
-   ========================= */
-#define REG_DMA44_DSCPTR_NXT            0xFFC14100         /* DMA44 Pointer to Next Initial Descriptor */
-#define REG_DMA44_ADDRSTART             0xFFC14104         /* DMA44 Start Address of Current Buffer */
-#define REG_DMA44_CFG                   0xFFC14108         /* DMA44 Configuration Register */
-#define REG_DMA44_XCNT                  0xFFC1410C         /* DMA44 Inner Loop Count Start Value */
-#define REG_DMA44_XMOD                  0xFFC14110         /* DMA44 Inner Loop Address Increment */
-#define REG_DMA44_YCNT                  0xFFC14114         /* DMA44 Outer Loop Count Start Value (2D only) */
-#define REG_DMA44_YMOD                  0xFFC14118         /* DMA44 Outer Loop Address Increment (2D only) */
-#define REG_DMA44_DSCPTR_CUR            0xFFC14124         /* DMA44 Current Descriptor Pointer */
-#define REG_DMA44_DSCPTR_PRV            0xFFC14128         /* DMA44 Previous Initial Descriptor Pointer */
-#define REG_DMA44_ADDR_CUR              0xFFC1412C         /* DMA44 Current Address */
-#define REG_DMA44_STAT                  0xFFC14130         /* DMA44 Status Register */
-#define REG_DMA44_XCNT_CUR              0xFFC14134         /* DMA44 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA44_YCNT_CUR              0xFFC14138         /* DMA44 Current Row Count (2D only) */
-#define REG_DMA44_BWLCNT                0xFFC14140         /* DMA44 Bandwidth Limit Count */
-#define REG_DMA44_BWLCNT_CUR            0xFFC14144         /* DMA44 Bandwidth Limit Count Current */
-#define REG_DMA44_BWMCNT                0xFFC14148         /* DMA44 Bandwidth Monitor Count */
-#define REG_DMA44_BWMCNT_CUR            0xFFC1414C         /* DMA44 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA45
-   ========================= */
-#define REG_DMA45_DSCPTR_NXT            0xFFC14180         /* DMA45 Pointer to Next Initial Descriptor */
-#define REG_DMA45_ADDRSTART             0xFFC14184         /* DMA45 Start Address of Current Buffer */
-#define REG_DMA45_CFG                   0xFFC14188         /* DMA45 Configuration Register */
-#define REG_DMA45_XCNT                  0xFFC1418C         /* DMA45 Inner Loop Count Start Value */
-#define REG_DMA45_XMOD                  0xFFC14190         /* DMA45 Inner Loop Address Increment */
-#define REG_DMA45_YCNT                  0xFFC14194         /* DMA45 Outer Loop Count Start Value (2D only) */
-#define REG_DMA45_YMOD                  0xFFC14198         /* DMA45 Outer Loop Address Increment (2D only) */
-#define REG_DMA45_DSCPTR_CUR            0xFFC141A4         /* DMA45 Current Descriptor Pointer */
-#define REG_DMA45_DSCPTR_PRV            0xFFC141A8         /* DMA45 Previous Initial Descriptor Pointer */
-#define REG_DMA45_ADDR_CUR              0xFFC141AC         /* DMA45 Current Address */
-#define REG_DMA45_STAT                  0xFFC141B0         /* DMA45 Status Register */
-#define REG_DMA45_XCNT_CUR              0xFFC141B4         /* DMA45 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA45_YCNT_CUR              0xFFC141B8         /* DMA45 Current Row Count (2D only) */
-#define REG_DMA45_BWLCNT                0xFFC141C0         /* DMA45 Bandwidth Limit Count */
-#define REG_DMA45_BWLCNT_CUR            0xFFC141C4         /* DMA45 Bandwidth Limit Count Current */
-#define REG_DMA45_BWMCNT                0xFFC141C8         /* DMA45 Bandwidth Monitor Count */
-#define REG_DMA45_BWMCNT_CUR            0xFFC141CC         /* DMA45 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA46
-   ========================= */
-#define REG_DMA46_DSCPTR_NXT            0xFFC14200         /* DMA46 Pointer to Next Initial Descriptor */
-#define REG_DMA46_ADDRSTART             0xFFC14204         /* DMA46 Start Address of Current Buffer */
-#define REG_DMA46_CFG                   0xFFC14208         /* DMA46 Configuration Register */
-#define REG_DMA46_XCNT                  0xFFC1420C         /* DMA46 Inner Loop Count Start Value */
-#define REG_DMA46_XMOD                  0xFFC14210         /* DMA46 Inner Loop Address Increment */
-#define REG_DMA46_YCNT                  0xFFC14214         /* DMA46 Outer Loop Count Start Value (2D only) */
-#define REG_DMA46_YMOD                  0xFFC14218         /* DMA46 Outer Loop Address Increment (2D only) */
-#define REG_DMA46_DSCPTR_CUR            0xFFC14224         /* DMA46 Current Descriptor Pointer */
-#define REG_DMA46_DSCPTR_PRV            0xFFC14228         /* DMA46 Previous Initial Descriptor Pointer */
-#define REG_DMA46_ADDR_CUR              0xFFC1422C         /* DMA46 Current Address */
-#define REG_DMA46_STAT                  0xFFC14230         /* DMA46 Status Register */
-#define REG_DMA46_XCNT_CUR              0xFFC14234         /* DMA46 Current Count(1D) or intra-row XCNT (2D) */
-#define REG_DMA46_YCNT_CUR              0xFFC14238         /* DMA46 Current Row Count (2D only) */
-#define REG_DMA46_BWLCNT                0xFFC14240         /* DMA46 Bandwidth Limit Count */
-#define REG_DMA46_BWLCNT_CUR            0xFFC14244         /* DMA46 Bandwidth Limit Count Current */
-#define REG_DMA46_BWMCNT                0xFFC14248         /* DMA46 Bandwidth Monitor Count */
-#define REG_DMA46_BWMCNT_CUR            0xFFC1424C         /* DMA46 Bandwidth Monitor Count Current */
-
-/* =========================
-        DMA
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_CFG_PDRF                    28                               /* Peripheral Data Request Forward */
-#define BITP_DMA_CFG_TWOD                    26                               /* Two Dimension Addressing Enable */
-#define BITP_DMA_CFG_DESCIDCPY               25                               /* Descriptor ID Copy Control */
-#define BITP_DMA_CFG_TOVEN                   24                               /* Trigger Overrun Error Enable */
-#define BITP_DMA_CFG_TRIG                    22                               /* Generate Outgoing Trigger */
-#define BITP_DMA_CFG_INT                     20                               /* Generate Interrupt */
-#define BITP_DMA_CFG_NDSIZE                  16                               /* Next Descriptor Set Size */
-#define BITP_DMA_CFG_TWAIT                   15                               /* Wait for Trigger */
-#define BITP_DMA_CFG_FLOW                    12                               /* Next Operation */
-#define BITP_DMA_CFG_MSIZE                    8                               /* Memory Transfer Word Size */
-#define BITP_DMA_CFG_PSIZE                    4                               /* Peripheral Transfer Word Size */
-#define BITP_DMA_CFG_CADDR                    3                               /* Use Current Address */
-#define BITP_DMA_CFG_SYNC                     2                               /* Synchronize Work Unit Transitions */
-#define BITP_DMA_CFG_WNR                      1                               /* Write/Read Channel Direction */
-#define BITP_DMA_CFG_EN                       0                               /* DMA Channel Enable */
-
-#define BITM_DMA_CFG_PDRF                    (_ADI_MSK(0x10000000,uint32_t))  /* Peripheral Data Request Forward */
-#define ENUM_DMA_CFG_PDAT_NOTFWD             (_ADI_MSK(0x00000000,uint32_t))  /* PDRF: Peripheral Data Request Not Forwarded */
-#define ENUM_DMA_CFG_PDAT_FWD                (_ADI_MSK(0x10000000,uint32_t))  /* PDRF: Peripheral Data Request Forwarded */
-
-#define BITM_DMA_CFG_TWOD                    (_ADI_MSK(0x04000000,uint32_t))  /* Two Dimension Addressing Enable */
-#define ENUM_DMA_CFG_ADDR1D                  (_ADI_MSK(0x00000000,uint32_t))  /* TWOD: One-Dimensional Addressing */
-#define ENUM_DMA_CFG_ADDR2D                  (_ADI_MSK(0x04000000,uint32_t))  /* TWOD: Two-Dimensional Addressing */
-
-#define BITM_DMA_CFG_DESCIDCPY               (_ADI_MSK(0x02000000,uint32_t))  /* Descriptor ID Copy Control */
-#define ENUM_DMA_CFG_NO_COPY                 (_ADI_MSK(0x00000000,uint32_t))  /* DESCIDCPY: Never Copy */
-#define ENUM_DMA_CFG_COPY                    (_ADI_MSK(0x02000000,uint32_t))  /* DESCIDCPY: Copy on Work Unit Complete */
-
-#define BITM_DMA_CFG_TOVEN                   (_ADI_MSK(0x01000000,uint32_t))  /* Trigger Overrun Error Enable */
-#define ENUM_DMA_CFG_TOV_DIS                 (_ADI_MSK(0x00000000,uint32_t))  /* TOVEN: Ignore Trigger Overrun */
-#define ENUM_DMA_CFG_TOV_EN                  (_ADI_MSK(0x01000000,uint32_t))  /* TOVEN: Error on Trigger Overrun */
-
-#define BITM_DMA_CFG_TRIG                    (_ADI_MSK(0x00C00000,uint32_t))  /* Generate Outgoing Trigger */
-#define ENUM_DMA_CFG_NO_TRIG                 (_ADI_MSK(0x00000000,uint32_t))  /* TRIG: Never assert Trigger */
-#define ENUM_DMA_CFG_XCNT_TRIG               (_ADI_MSK(0x00400000,uint32_t))  /* TRIG: Trigger when XCNTCUR reaches 0 */
-#define ENUM_DMA_CFG_YCNT_TRIG               (_ADI_MSK(0x00800000,uint32_t))  /* TRIG: Trigger when YCNTCUR reaches 0 */
-
-#define BITM_DMA_CFG_INT                     (_ADI_MSK(0x00300000,uint32_t))  /* Generate Interrupt */
-#define ENUM_DMA_CFG_NO_INT                  (_ADI_MSK(0x00000000,uint32_t))  /* INT: Never assert Interrupt */
-#define ENUM_DMA_CFG_XCNT_INT                (_ADI_MSK(0x00100000,uint32_t))  /* INT: Interrupt when X Count Expires */
-#define ENUM_DMA_CFG_YCNT_INT                (_ADI_MSK(0x00200000,uint32_t))  /* INT: Interrupt when Y Count Expires */
-#define ENUM_DMA_CFG_PERIPH_INT              (_ADI_MSK(0x00300000,uint32_t))  /* INT: Peripheral Interrupt */
-
-#define BITM_DMA_CFG_NDSIZE                  (_ADI_MSK(0x00070000,uint32_t))  /* Next Descriptor Set Size */
-#define ENUM_DMA_CFG_FETCH01                 (_ADI_MSK(0x00000000,uint32_t))  /* NDSIZE: Fetch one Descriptor Element */
-#define ENUM_DMA_CFG_FETCH02                 (_ADI_MSK(0x00010000,uint32_t))  /* NDSIZE: Fetch two Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH03                 (_ADI_MSK(0x00020000,uint32_t))  /* NDSIZE: Fetch three Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH04                 (_ADI_MSK(0x00030000,uint32_t))  /* NDSIZE: Fetch four Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH05                 (_ADI_MSK(0x00040000,uint32_t))  /* NDSIZE: Fetch five Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH06                 (_ADI_MSK(0x00050000,uint32_t))  /* NDSIZE: Fetch six Descriptor Elements */
-#define ENUM_DMA_CFG_FETCH07                 (_ADI_MSK(0x00060000,uint32_t))  /* NDSIZE: Fetch seven Descriptor Elements */
-
-#define BITM_DMA_CFG_TWAIT                   (_ADI_MSK(0x00008000,uint32_t))  /* Wait for Trigger */
-#define ENUM_DMA_CFG_NO_TRGWAIT              (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: Begin Work Unit Automatically (No Wait) */
-#define ENUM_DMA_CFG_TRGWAIT                 (_ADI_MSK(0x00008000,uint32_t))  /* TWAIT: Wait for Trigger (Halt before Work Unit) */
-
-#define BITM_DMA_CFG_FLOW                    (_ADI_MSK(0x00007000,uint32_t))  /* Next Operation */
-#define ENUM_DMA_CFG_STOP                    (_ADI_MSK(0x00000000,uint32_t))  /* FLOW: STOP - Stop */
-#define ENUM_DMA_CFG_AUTO                    (_ADI_MSK(0x00001000,uint32_t))  /* FLOW: AUTO - Autobuffer */
-#define ENUM_DMA_CFG_DSCLIST                 (_ADI_MSK(0x00004000,uint32_t))  /* FLOW: DSCL - Descriptor List */
-#define ENUM_DMA_CFG_DSCARRAY                (_ADI_MSK(0x00005000,uint32_t))  /* FLOW: DSCA - Descriptor Array */
-#define ENUM_DMA_CFG_DODLIST                 (_ADI_MSK(0x00006000,uint32_t))  /* FLOW: Descriptor On Demand List */
-#define ENUM_DMA_CFG_DODARRAY                (_ADI_MSK(0x00007000,uint32_t))  /* FLOW: Descriptor On Demand Array */
-
-#define BITM_DMA_CFG_MSIZE                   (_ADI_MSK(0x00000700,uint32_t))  /* Memory Transfer Word Size */
-#define ENUM_DMA_CFG_MSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* MSIZE: 1 Byte */
-#define ENUM_DMA_CFG_MSIZE02                 (_ADI_MSK(0x00000100,uint32_t))  /* MSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_MSIZE04                 (_ADI_MSK(0x00000200,uint32_t))  /* MSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_MSIZE08                 (_ADI_MSK(0x00000300,uint32_t))  /* MSIZE: 8 Bytes */
-#define ENUM_DMA_CFG_MSIZE16                 (_ADI_MSK(0x00000400,uint32_t))  /* MSIZE: 16 Bytes */
-#define ENUM_DMA_CFG_MSIZE32                 (_ADI_MSK(0x00000500,uint32_t))  /* MSIZE: 32 Bytes */
-
-#define BITM_DMA_CFG_PSIZE                   (_ADI_MSK(0x00000070,uint32_t))  /* Peripheral Transfer Word Size */
-#define ENUM_DMA_CFG_PSIZE01                 (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 Byte */
-#define ENUM_DMA_CFG_PSIZE02                 (_ADI_MSK(0x00000010,uint32_t))  /* PSIZE: 2 Bytes */
-#define ENUM_DMA_CFG_PSIZE04                 (_ADI_MSK(0x00000020,uint32_t))  /* PSIZE: 4 Bytes */
-#define ENUM_DMA_CFG_PSIZE08                 (_ADI_MSK(0x00000030,uint32_t))  /* PSIZE: 8 Bytes */
-
-#define BITM_DMA_CFG_CADDR                   (_ADI_MSK(0x00000008,uint32_t))  /* Use Current Address */
-#define ENUM_DMA_CFG_LD_STARTADDR            (_ADI_MSK(0x00000000,uint32_t))  /* CADDR: Load Starting Address */
-#define ENUM_DMA_CFG_LD_CURADDR              (_ADI_MSK(0x00000008,uint32_t))  /* CADDR: Use Current Address */
-
-#define BITM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* Synchronize Work Unit Transitions */
-#define ENUM_DMA_CFG_NO_SYNC                 (_ADI_MSK(0x00000000,uint32_t))  /* SYNC: No Synchronization */
-#define ENUM_DMA_CFG_SYNC                    (_ADI_MSK(0x00000004,uint32_t))  /* SYNC: Synchronize  Channel */
-
-#define BITM_DMA_CFG_WNR                     (_ADI_MSK(0x00000002,uint32_t))  /* Write/Read Channel Direction */
-#define ENUM_DMA_CFG_READ                    (_ADI_MSK(0x00000000,uint32_t))  /* WNR: Transmit (Read from memory) */
-#define ENUM_DMA_CFG_WRITE                   (_ADI_MSK(0x00000002,uint32_t))  /* WNR: Receive (Write to memory) */
-
-#define BITM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* DMA Channel Enable */
-#define ENUM_DMA_CFG_DIS                     (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_DMA_CFG_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_DSCPTR_PRV                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_DSCPTR_PRV_DESCPPREV         2                               /* Pointer for Previous Descriptor Element */
-#define BITP_DMA_DSCPTR_PRV_PDPO              0                               /* Previous Descriptor Pointer Overrun */
-#define BITM_DMA_DSCPTR_PRV_DESCPPREV        (_ADI_MSK(0xFFFFFFFC,uint32_t))  /* Pointer for Previous Descriptor Element */
-#define BITM_DMA_DSCPTR_PRV_PDPO             (_ADI_MSK(0x00000001,uint32_t))  /* Previous Descriptor Pointer Overrun */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_STAT_TWAIT                  20                               /* Trigger Wait Status */
-#define BITP_DMA_STAT_FIFOFILL               16                               /* FIFO Fill Status */
-#define BITP_DMA_STAT_MBWID                  14                               /* Memory Bus Width */
-#define BITP_DMA_STAT_PBWID                  12                               /* Peripheral Bus Width */
-#define BITP_DMA_STAT_RUN                     8                               /* Run Status */
-#define BITP_DMA_STAT_ERRC                    4                               /* Error Cause */
-#define BITP_DMA_STAT_PIRQ                    2                               /* Peripheral Interrupt Request */
-#define BITP_DMA_STAT_IRQERR                  1                               /* Error Interrupt */
-#define BITP_DMA_STAT_IRQDONE                 0                               /* Work Unit/Row Done Interrupt */
-
-#define BITM_DMA_STAT_TWAIT                  (_ADI_MSK(0x00100000,uint32_t))  /* Trigger Wait Status */
-#define ENUM_DMA_STAT_NOTRIGRX               (_ADI_MSK(0x00000000,uint32_t))  /* TWAIT: No trigger received */
-#define ENUM_DMA_STAT_TRIGRX                 (_ADI_MSK(0x00100000,uint32_t))  /* TWAIT: Trigger received */
-
-#define BITM_DMA_STAT_FIFOFILL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFO Fill Status */
-#define ENUM_DMA_STAT_FIFOEMPTY              (_ADI_MSK(0x00000000,uint32_t))  /* FIFOFILL: Empty */
-#define ENUM_DMA_STAT_FIFO25                 (_ADI_MSK(0x00010000,uint32_t))  /* FIFOFILL: Empty < FIFO = 1/4 Full */
-#define ENUM_DMA_STAT_FIFO50                 (_ADI_MSK(0x00020000,uint32_t))  /* FIFOFILL: 1/4 Full < FIFO = 1/2 Full */
-#define ENUM_DMA_STAT_FIFO75                 (_ADI_MSK(0x00030000,uint32_t))  /* FIFOFILL: 1/2 Full < FIFO = 3/4 Full */
-#define ENUM_DMA_STAT_FIFONEARFULL           (_ADI_MSK(0x00040000,uint32_t))  /* FIFOFILL: 3/4 Full < FIFO = Full */
-#define ENUM_DMA_STAT_FIFOFULL               (_ADI_MSK(0x00070000,uint32_t))  /* FIFOFILL: Full */
-
-#define BITM_DMA_STAT_MBWID                  (_ADI_MSK(0x0000C000,uint32_t))  /* Memory Bus Width */
-#define ENUM_DMA_STAT_MBUS02                 (_ADI_MSK(0x00000000,uint32_t))  /* MBWID: 2 Bytes */
-#define ENUM_DMA_STAT_MBUS04                 (_ADI_MSK(0x00004000,uint32_t))  /* MBWID: 4 Bytes */
-#define ENUM_DMA_STAT_MBUS08                 (_ADI_MSK(0x00008000,uint32_t))  /* MBWID: 8 Bytes */
-#define ENUM_DMA_STAT_MBUS16                 (_ADI_MSK(0x0000C000,uint32_t))  /* MBWID: 16 Bytes */
-
-#define BITM_DMA_STAT_PBWID                  (_ADI_MSK(0x00003000,uint32_t))  /* Peripheral Bus Width */
-#define ENUM_DMA_STAT_PBUS01                 (_ADI_MSK(0x00000000,uint32_t))  /* PBWID: 1 Byte */
-#define ENUM_DMA_STAT_PBUS02                 (_ADI_MSK(0x00001000,uint32_t))  /* PBWID: 2 Bytes */
-#define ENUM_DMA_STAT_PBUS04                 (_ADI_MSK(0x00002000,uint32_t))  /* PBWID: 4 Bytes */
-#define ENUM_DMA_STAT_PBUS08                 (_ADI_MSK(0x00003000,uint32_t))  /* PBWID: 8 Bytes */
-
-#define BITM_DMA_STAT_RUN                    (_ADI_MSK(0x00000700,uint32_t))  /* Run Status */
-#define ENUM_DMA_STAT_STOPPED                (_ADI_MSK(0x00000000,uint32_t))  /* RUN: Idle/Stop State */
-#define ENUM_DMA_STAT_DSCFETCH               (_ADI_MSK(0x00000100,uint32_t))  /* RUN: Descriptor Fetch */
-#define ENUM_DMA_STAT_DATAXFER               (_ADI_MSK(0x00000200,uint32_t))  /* RUN: Data Transfer */
-#define ENUM_DMA_STAT_TRGWAIT                (_ADI_MSK(0x00000300,uint32_t))  /* RUN: Waiting for Trigger */
-#define ENUM_DMA_STAT_ACKWAIT                (_ADI_MSK(0x00000400,uint32_t))  /* RUN: Waiting for Write ACK/FIFO Drain to Peripheral */
-
-#define BITM_DMA_STAT_ERRC                   (_ADI_MSK(0x00000070,uint32_t))  /* Error Cause */
-#define ENUM_DMA_STAT_CFGERR                 (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Configuration Error */
-#define ENUM_DMA_STAT_ILLWRERR               (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Illegal Write Occurred While Channel Running */
-#define ENUM_DMA_STAT_ALGNERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: Address Alignment Error */
-#define ENUM_DMA_STAT_MEMERR                 (_ADI_MSK(0x00000030,uint32_t))  /* ERRC: Memory Access/Fabric Error */
-#define ENUM_DMA_STAT_TRGOVERR               (_ADI_MSK(0x00000050,uint32_t))  /* ERRC: Trigger Overrun */
-#define ENUM_DMA_STAT_BWMONERR               (_ADI_MSK(0x00000060,uint32_t))  /* ERRC: Bandwidth Monitor Error */
-
-#define BITM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* Peripheral Interrupt Request */
-#define ENUM_DMA_STAT_NO_PIRQ                (_ADI_MSK(0x00000000,uint32_t))  /* PIRQ: No Interrupt */
-#define ENUM_DMA_STAT_PIRQ                   (_ADI_MSK(0x00000004,uint32_t))  /* PIRQ: Interrupt Signaled by Peripheral */
-
-#define BITM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Interrupt */
-#define ENUM_DMA_STAT_NO_IRQERR              (_ADI_MSK(0x00000000,uint32_t))  /* IRQERR: No Error */
-#define ENUM_DMA_STAT_IRQERR                 (_ADI_MSK(0x00000002,uint32_t))  /* IRQERR: Error Occurred */
-
-#define BITM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* Work Unit/Row Done Interrupt */
-#define ENUM_DMA_STAT_NO_IRQ                 (_ADI_MSK(0x00000000,uint32_t))  /* IRQDONE: Inactive */
-#define ENUM_DMA_STAT_IRQDONE                (_ADI_MSK(0x00000001,uint32_t))  /* IRQDONE: Active */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_VALUE                 0                               /* Bandwidth Limit Count */
-#define BITM_DMA_BWLCNT_VALUE                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMA_BWLCNT_CUR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMA_BWLCNT_CUR_VALUE             0                               /* Bandwidth Limit Count Current */
-#define BITM_DMA_BWLCNT_CUR_VALUE            (_ADI_MSK(0x0000FFFF,uint32_t))  /* Bandwidth Limit Count Current */
-
-/* ==================================================
-        ACM Registers
-   ================================================== */
-
-/* =========================
-        ACM0
-   ========================= */
-#define REG_ACM0_CTL                    0xFFC45000         /* ACM0 ACM Control Register */
-#define REG_ACM0_TC0                    0xFFC45004         /* ACM0 ACM Timing Configuration 0 Register */
-#define REG_ACM0_TC1                    0xFFC45008         /* ACM0 ACM Timing Configuration 1 Register */
-#define REG_ACM0_STAT                   0xFFC4500C         /* ACM0 ACM Status Register */
-#define REG_ACM0_EVSTAT                 0xFFC45010         /* ACM0 ACM Event Status Register */
-#define REG_ACM0_EVMSK                  0xFFC45014         /* ACM0 ACM Completed Event Interrupt Mask Register */
-#define REG_ACM0_MEVSTAT                0xFFC45018         /* ACM0 ACM Missed Event Status Register */
-#define REG_ACM0_MEVMSK                 0xFFC4501C         /* ACM0 ACM Missed Event Interrupt Mask Register */
-#define REG_ACM0_EVCTL0                 0xFFC45020         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL1                 0xFFC45024         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL2                 0xFFC45028         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL3                 0xFFC4502C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL4                 0xFFC45030         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL5                 0xFFC45034         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL6                 0xFFC45038         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL7                 0xFFC4503C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL8                 0xFFC45040         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL9                 0xFFC45044         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL10                0xFFC45048         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL11                0xFFC4504C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL12                0xFFC45050         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL13                0xFFC45054         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL14                0xFFC45058         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVCTL15                0xFFC4505C         /* ACM0 ACM Eventn Control Register */
-#define REG_ACM0_EVTIME0                0xFFC45060         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME1                0xFFC45064         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME2                0xFFC45068         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME3                0xFFC4506C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME4                0xFFC45070         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME5                0xFFC45074         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME6                0xFFC45078         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME7                0xFFC4507C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME8                0xFFC45080         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME9                0xFFC45084         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME10               0xFFC45088         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME11               0xFFC4508C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME12               0xFFC45090         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME13               0xFFC45094         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME14               0xFFC45098         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVTIME15               0xFFC4509C         /* ACM0 ACM Eventn Time Register */
-#define REG_ACM0_EVORD0                 0xFFC450A0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD1                 0xFFC450A4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD2                 0xFFC450A8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD3                 0xFFC450AC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD4                 0xFFC450B0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD5                 0xFFC450B4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD6                 0xFFC450B8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD7                 0xFFC450BC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD8                 0xFFC450C0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD9                 0xFFC450C4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD10                0xFFC450C8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD11                0xFFC450CC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD12                0xFFC450D0         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD13                0xFFC450D4         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD14                0xFFC450D8         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_EVORD15                0xFFC450DC         /* ACM0 ACM Eventn Order Register */
-#define REG_ACM0_TMR0                   0xFFC450E8         /* ACM0 ACM Timer 0 Register */
-#define REG_ACM0_TMR1                   0xFFC450EC         /* ACM0 ACM Timer 1 Register */
-
-/* =========================
-        ACM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_CTL_EPS                     15                               /* External Peripheral Select */
-#define BITP_ACM_CTL_OTSEL                   14                               /* Trigger Select for Order Register Reset */
-#define BITP_ACM_CTL_AOREN                   13                               /* Automatic Order Reset Enable */
-#define BITP_ACM_CTL_ORST                    12                               /* Order Register Reset Bit */
-#define BITP_ACM_CTL_CLKMOD                  11                               /* ADC Clock Mode */
-#define BITP_ACM_CTL_CLKPOL                  10                               /* ADC_CLK Polarity */
-#define BITP_ACM_CTL_CSPOL                    9                               /* CS Polarity */
-#define BITP_ACM_CTL_TRGPOL1                  8                               /* Trigger Polarity for Timer1 Triggers */
-#define BITP_ACM_CTL_TRGPOL0                  7                               /* Trigger Polarity for Timer0 Triggers */
-#define BITP_ACM_CTL_TRGSEL1                  5                               /* Trigger Select 1 */
-#define BITP_ACM_CTL_TRGSEL0                  3                               /* Trigger Select 0 */
-#define BITP_ACM_CTL_TMR1EN                   2                               /* Enable ACM Timer1 */
-#define BITP_ACM_CTL_TMR0EN                   1                               /* Enable ACM Timer0 */
-#define BITP_ACM_CTL_EN                       0                               /* ACM Enable */
-#define BITM_ACM_CTL_EPS                     (_ADI_MSK(0x00008000,uint32_t))  /* External Peripheral Select */
-#define BITM_ACM_CTL_OTSEL                   (_ADI_MSK(0x00004000,uint32_t))  /* Trigger Select for Order Register Reset */
-#define BITM_ACM_CTL_AOREN                   (_ADI_MSK(0x00002000,uint32_t))  /* Automatic Order Reset Enable */
-#define BITM_ACM_CTL_ORST                    (_ADI_MSK(0x00001000,uint32_t))  /* Order Register Reset Bit */
-#define BITM_ACM_CTL_CLKMOD                  (_ADI_MSK(0x00000800,uint32_t))  /* ADC Clock Mode */
-#define BITM_ACM_CTL_CLKPOL                  (_ADI_MSK(0x00000400,uint32_t))  /* ADC_CLK Polarity */
-#define BITM_ACM_CTL_CSPOL                   (_ADI_MSK(0x00000200,uint32_t))  /* CS Polarity */
-#define BITM_ACM_CTL_TRGPOL1                 (_ADI_MSK(0x00000100,uint32_t))  /* Trigger Polarity for Timer1 Triggers */
-#define BITM_ACM_CTL_TRGPOL0                 (_ADI_MSK(0x00000080,uint32_t))  /* Trigger Polarity for Timer0 Triggers */
-#define BITM_ACM_CTL_TRGSEL1                 (_ADI_MSK(0x00000060,uint32_t))  /* Trigger Select 1 */
-#define BITM_ACM_CTL_TRGSEL0                 (_ADI_MSK(0x00000018,uint32_t))  /* Trigger Select 0 */
-#define BITM_ACM_CTL_TMR1EN                  (_ADI_MSK(0x00000004,uint32_t))  /* Enable ACM Timer1 */
-#define BITM_ACM_CTL_TMR0EN                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable ACM Timer0 */
-#define BITM_ACM_CTL_EN                      (_ADI_MSK(0x00000001,uint32_t))  /* ACM Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC0_SC                      16                               /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITP_ACM_TC0_CKDIV                    0                               /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-#define BITM_ACM_TC0_SC                      (_ADI_MSK(0x0FFF0000,uint32_t))  /* Setup Cycle - ADC Control setup in SCLK cycles */
-#define BITM_ACM_TC0_CKDIV                   (_ADI_MSK(0x000000FF,uint32_t))  /* Serial Clock Divide Modulus[7:0] CKDIV=0 is Reserved */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_TC1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_TC1_ZC                      12                               /* Zero Cycle - ADC Control zero duration */
-#define BITP_ACM_TC1_HC                       8                               /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITP_ACM_TC1_CSW                      0                               /* CS Width. Active duration of CS in ACLK cycles */
-#define BITM_ACM_TC1_ZC                      (_ADI_MSK(0x0000F000,uint32_t))  /* Zero Cycle - ADC Control zero duration */
-#define BITM_ACM_TC1_HC                      (_ADI_MSK(0x00000F00,uint32_t))  /* Hold Cycle - ADC Control hold in ACLK cycle */
-#define BITM_ACM_TC1_CSW                     (_ADI_MSK(0x000000FF,uint32_t))  /* CS Width. Active duration of CS in ACLK cycles */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_STAT_CEVNT                   4                               /* Current Event. */
-#define BITP_ACM_STAT_ECOM1                   3                               /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_ECOM0                   2                               /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITP_ACM_STAT_EMISS                   1                               /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITP_ACM_STAT_BSY                     0                               /* ACM Busy */
-#define BITM_ACM_STAT_CEVNT                  (_ADI_MSK(0x000000F0,uint32_t))  /* Current Event. */
-#define BITM_ACM_STAT_ECOM1                  (_ADI_MSK(0x00000008,uint32_t))  /* ACM Timer1 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_ECOM0                  (_ADI_MSK(0x00000004,uint32_t))  /* ACM Timer0 Event Completion. This bit gets cleared with each trigger. */
-#define BITM_ACM_STAT_EMISS                  (_ADI_MSK(0x00000002,uint32_t))  /* Event Missed This bit will be set if any of the bits in MEVSTAT is set, this bit has to be cleared by writing into the MEVSTAT register */
-#define BITM_ACM_STAT_BSY                    (_ADI_MSK(0x00000001,uint32_t))  /* ACM Busy */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVSTAT_ECOM1S               17                               /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_ECOM0S               16                               /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITP_ACM_EVSTAT_EV15                 15                               /* Event15 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV14                 14                               /* Event14 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV13                 13                               /* Event13 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV12                 12                               /* Event12 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV11                 11                               /* Event11 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV10                 10                               /* Event10 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV9                   9                               /* Event9 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV8                   8                               /* Event8 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV7                   7                               /* Event7 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV6                   6                               /* Event6 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV5                   5                               /* Event5 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV4                   4                               /* Event4 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV3                   3                               /* Event3 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV2                   2                               /* Event2 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV1                   1                               /* Event1 Status. W1C bit. */
-#define BITP_ACM_EVSTAT_EV0                   0                               /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-#define BITM_ACM_EVSTAT_ECOM1S               (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the ECOM1 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_ECOM0S               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the ECOM0 bit of ACM_STAT register but this bit will not be cleared by trigger. W1C bit */
-#define BITM_ACM_EVSTAT_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status. W1C bit. */
-#define BITM_ACM_EVSTAT_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status. W1C bit. Creates an interrupt if corresponding bit in EVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVMSK_IECOM1                17                               /* Timer1 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_IECOM0                16                               /* Timer0 Event Completion Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV15                  15                               /* Event15 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV14                  14                               /* Event14 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV13                  13                               /* Event13 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV12                  12                               /* Event12 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV11                  11                               /* Event11 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV10                  10                               /* Event10 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV9                    9                               /* Event9 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV8                    8                               /* Event8 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV7                    7                               /* Event7 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV6                    6                               /* Event6 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV5                    5                               /* Event5 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV4                    4                               /* Event4 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV3                    3                               /* Event3 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV2                    2                               /* Event2 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV1                    1                               /* Event1 Status Interrupt Enable */
-#define BITP_ACM_EVMSK_EV0                    0                               /* Event0 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM1                (_ADI_MSK(0x00020000,uint32_t))  /* Timer1 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_IECOM0                (_ADI_MSK(0x00010000,uint32_t))  /* Timer0 Event Completion Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV15                  (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV14                  (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV13                  (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV12                  (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV11                  (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV10                  (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV9                   (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV8                   (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV7                   (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV6                   (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV5                   (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV4                   (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV3                   (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV2                   (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV1                   (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Status Interrupt Enable */
-#define BITM_ACM_EVMSK_EV0                   (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Status Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVSTAT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVSTAT_EV15                15                               /* Event15 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV14                14                               /* Event14 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV13                13                               /* Event13 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV12                12                               /* Event12 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV11                11                               /* Event11 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV10                10                               /* Event10 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV9                  9                               /* Event9 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV8                  8                               /* Event8 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV7                  7                               /* Event7 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV6                  6                               /* Event6 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV5                  5                               /* Event5 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV4                  4                               /* Event4 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV3                  3                               /* Event3 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV2                  2                               /* Event2 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV1                  1                               /* Event1 Missed. W1C bit. */
-#define BITP_ACM_MEVSTAT_EV0                  0                               /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-#define BITM_ACM_MEVSTAT_EV15                (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV14                (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV13                (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV12                (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV11                (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV10                (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV9                 (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV8                 (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV7                 (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV6                 (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV5                 (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV4                 (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV3                 (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV2                 (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV1                 (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed. W1C bit. */
-#define BITM_ACM_MEVSTAT_EV0                 (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed. W1C bit. Creates an interrupt if corresponding bit in MEVMSK register is set. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_MEVMSK                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_MEVMSK_EV15                 15                               /* Event15 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV14                 14                               /* Event14 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV13                 13                               /* Event13 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV12                 12                               /* Event12 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV11                 11                               /* Event11 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV10                 10                               /* Event10 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV9                   9                               /* Event9 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV8                   8                               /* Event8 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV7                   7                               /* Event7 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV6                   6                               /* Event6 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV5                   5                               /* Event5 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV4                   4                               /* Event4 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV3                   3                               /* Event3 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV2                   2                               /* Event2 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV1                   1                               /* Event1 Missed Interrupt Enable */
-#define BITP_ACM_MEVMSK_EV0                   0                               /* Event0 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV15                 (_ADI_MSK(0x00008000,uint32_t))  /* Event15 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV14                 (_ADI_MSK(0x00004000,uint32_t))  /* Event14 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV13                 (_ADI_MSK(0x00002000,uint32_t))  /* Event13 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV12                 (_ADI_MSK(0x00001000,uint32_t))  /* Event12 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV11                 (_ADI_MSK(0x00000800,uint32_t))  /* Event11 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV10                 (_ADI_MSK(0x00000400,uint32_t))  /* Event10 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV9                  (_ADI_MSK(0x00000200,uint32_t))  /* Event9 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV8                  (_ADI_MSK(0x00000100,uint32_t))  /* Event8 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV7                  (_ADI_MSK(0x00000080,uint32_t))  /* Event7 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV6                  (_ADI_MSK(0x00000040,uint32_t))  /* Event6 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV5                  (_ADI_MSK(0x00000020,uint32_t))  /* Event5 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV4                  (_ADI_MSK(0x00000010,uint32_t))  /* Event4 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV3                  (_ADI_MSK(0x00000008,uint32_t))  /* Event3 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV2                  (_ADI_MSK(0x00000004,uint32_t))  /* Event2 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV1                  (_ADI_MSK(0x00000002,uint32_t))  /* Event1 Missed Interrupt Enable */
-#define BITM_ACM_MEVMSK_EV0                  (_ADI_MSK(0x00000001,uint32_t))  /* Event0 Missed Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVCTL_EPF                    1                               /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITP_ACM_EVCTL_ENAEV                  0                               /* Enable Event */
-#define BITM_ACM_EVCTL_EPF                   (_ADI_MSK(0x0000003E,uint32_t))  /* Event Parameter Field. All EPF[4:0] has same external pin timing. */
-#define BITM_ACM_EVCTL_ENAEV                 (_ADI_MSK(0x00000001,uint32_t))  /* Enable Event */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ACM_EVORD                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ACM_EVORD_EVSTAT                17                               /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITP_ACM_EVORD_MEVSTAT               16                               /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITP_ACM_EVORD_ORD                    0                               /* Order of Event Completion */
-#define BITM_ACM_EVORD_EVSTAT                (_ADI_MSK(0x00020000,uint32_t))  /* Reflects the EVSTATn Bit in the EVSTAT Register */
-#define BITM_ACM_EVORD_MEVSTAT               (_ADI_MSK(0x00010000,uint32_t))  /* Reflects the MEVSTATn Bit in the MEVSTAT Register */
-#define BITM_ACM_EVORD_ORD                   (_ADI_MSK(0x000000FF,uint32_t))  /* Order of Event Completion */
-
-/* ==================================================
-        DDR Registers
-   ================================================== */
-
-/* =========================
-        DMC0
-   ========================= */
-#define REG_DMC0_CTL                    0xFFC80004         /* DMC0 Control Register */
-#define REG_DMC0_STAT                   0xFFC80008         /* DMC0 Status Register */
-#define REG_DMC0_EFFCTL                 0xFFC8000C         /* DMC0 Efficiency Control Register */
-#define REG_DMC0_PRIO                   0xFFC80010         /* DMC0 Priority ID Register */
-#define REG_DMC0_PRIOMSK                0xFFC80014         /* DMC0 Priority ID Mask Register */
-#define REG_DMC0_CFG                    0xFFC80040         /* DMC0 Configuration Register */
-#define REG_DMC0_TR0                    0xFFC80044         /* DMC0 Timing 0 Register */
-#define REG_DMC0_TR1                    0xFFC80048         /* DMC0 Timing 1 Register */
-#define REG_DMC0_TR2                    0xFFC8004C         /* DMC0 Timing 2 Register */
-#define REG_DMC0_MSK                    0xFFC8005C         /* DMC0 Mask (Mode Register Shadow) Register */
-#define REG_DMC0_MR                     0xFFC80060         /* DMC0 Shadow MR Register */
-#define REG_DMC0_EMR1                   0xFFC80064         /* DMC0 Shadow EMR1 Register */
-#define REG_DMC0_EMR2                   0xFFC80068         /* DMC0 Shadow EMR2 Register */
-#define REG_DMC0_EMR3                   0xFFC8006C         /* DMC0 Shadow EMR3 Register */
-#define REG_DMC0_DLLCTL                 0xFFC80080         /* DMC0 DLL Control Register */
-#define REG_DMC0_PHY_CTL0               0xFFC80090         /* DMC0 PHY Control 0 Register */
-#define REG_DMC0_PHY_CTL1               0xFFC80094         /* DMC0 PHY Control 1 Register */
-#define REG_DMC0_PHY_CTL2               0xFFC80098         /* DMC0 PHY Control 2 Register */
-#define REG_DMC0_PHY_CTL3               0xFFC8009C         /* DMC0 PHY Control 3 Register */
-#define REG_DMC0_PADCTL                 0xFFC800C0         /* DMC0 PAD Control Register */
-
-/* =========================
-        DMC
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CTL_DLLCAL                  13                               /* DLL Calibration Start */
-#define BITP_DMC_CTL_PPREF                   12                               /* Postpone Refresh */
-#define BITP_DMC_CTL_RDTOWR                   9                               /* Read-to-Write Cycle */
-#define BITP_DMC_CTL_ADDRMODE                 8                               /* Addressing (Page/Bank) Mode */
-#define BITP_DMC_CTL_PREC                     6                               /* Precharge */
-#define BITP_DMC_CTL_DPDREQ                   5                               /* Deep Power Down Request */
-#define BITP_DMC_CTL_PDREQ                    4                               /* Power Down Request */
-#define BITP_DMC_CTL_SRREQ                    3                               /* Self Refresh Request */
-#define BITP_DMC_CTL_INIT                     2                               /* Initialize DRAM Start */
-#define BITP_DMC_CTL_LPDDR                    1                               /* Low Power DDR Mode */
-#define BITM_DMC_CTL_DLLCAL                  (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Start */
-#define BITM_DMC_CTL_PPREF                   (_ADI_MSK(0x00001000,uint32_t))  /* Postpone Refresh */
-
-#define BITM_DMC_CTL_RDTOWR                  (_ADI_MSK(0x00000E00,uint32_t))  /* Read-to-Write Cycle */
-#define ENUM_DMC_CTL_RDTOWR0                 (_ADI_MSK(0x00000000,uint32_t))  /* RDTOWR: 0 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR1                 (_ADI_MSK(0x00000200,uint32_t))  /* RDTOWR: 1 Cycle Added */
-#define ENUM_DMC_CTL_RDTOWR2                 (_ADI_MSK(0x00000400,uint32_t))  /* RDTOWR: 2 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR3                 (_ADI_MSK(0x00000600,uint32_t))  /* RDTOWR: 3 Cycles Added */
-#define ENUM_DMC_CTL_RDTOWR4                 (_ADI_MSK(0x00000800,uint32_t))  /* RDTOWR: 4 Cycles Added */
-#define BITM_DMC_CTL_ADDRMODE                (_ADI_MSK(0x00000100,uint32_t))  /* Addressing (Page/Bank) Mode */
-#define BITM_DMC_CTL_PREC                    (_ADI_MSK(0x00000040,uint32_t))  /* Precharge */
-#define BITM_DMC_CTL_DPDREQ                  (_ADI_MSK(0x00000020,uint32_t))  /* Deep Power Down Request */
-#define BITM_DMC_CTL_PDREQ                   (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Request */
-#define BITM_DMC_CTL_SRREQ                   (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Request */
-#define BITM_DMC_CTL_INIT                    (_ADI_MSK(0x00000004,uint32_t))  /* Initialize DRAM Start */
-#define BITM_DMC_CTL_LPDDR                   (_ADI_MSK(0x00000002,uint32_t))  /* Low Power DDR Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_STAT_PHYRDPHASE             20                               /* PHY Read Phase */
-#define BITP_DMC_STAT_PENDREF                16                               /* Pending Refresh */
-#define BITP_DMC_STAT_DLLCALDONE             13                               /* DLL Calibration Done */
-#define BITP_DMC_STAT_DPDACK                  5                               /* Deep Powerdown Acknowledge */
-#define BITP_DMC_STAT_PDACK                   4                               /* Power Down Acknowledge */
-#define BITP_DMC_STAT_SRACK                   3                               /* Self Refresh Acknowledge */
-#define BITP_DMC_STAT_MEMINITDONE             1                               /* Memory Initialization Done */
-#define BITP_DMC_STAT_IDLE                    0                               /* Idle State */
-#define BITM_DMC_STAT_PHYRDPHASE             (_ADI_MSK(0x00F00000,uint32_t))  /* PHY Read Phase */
-#define BITM_DMC_STAT_PENDREF                (_ADI_MSK(0x000F0000,uint32_t))  /* Pending Refresh */
-#define BITM_DMC_STAT_DLLCALDONE             (_ADI_MSK(0x00002000,uint32_t))  /* DLL Calibration Done */
-#define BITM_DMC_STAT_DPDACK                 (_ADI_MSK(0x00000020,uint32_t))  /* Deep Powerdown Acknowledge */
-#define BITM_DMC_STAT_PDACK                  (_ADI_MSK(0x00000010,uint32_t))  /* Power Down Acknowledge */
-#define BITM_DMC_STAT_SRACK                  (_ADI_MSK(0x00000008,uint32_t))  /* Self Refresh Acknowledge */
-#define BITM_DMC_STAT_MEMINITDONE            (_ADI_MSK(0x00000002,uint32_t))  /* Memory Initialization Done */
-#define BITM_DMC_STAT_IDLE                   (_ADI_MSK(0x00000001,uint32_t))  /* Idle State */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EFFCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EFFCTL_IDLECYC              20                               /* Idle Cycle */
-#define BITP_DMC_EFFCTL_NUMREF               16                               /* Number of Refresh Commands */
-#define BITP_DMC_EFFCTL_PRECBANK7            15                               /* Precharge Bank 7 */
-#define BITP_DMC_EFFCTL_PRECBANK6            14                               /* Precharge Bank 6 */
-#define BITP_DMC_EFFCTL_PRECBANK5            13                               /* Precharge Bank 5 */
-#define BITP_DMC_EFFCTL_PRECBANK4            12                               /* Precharge Bank 4 */
-#define BITP_DMC_EFFCTL_PRECBANK3            11                               /* Precharge Bank 3 */
-#define BITP_DMC_EFFCTL_PRECBANK2            10                               /* Precharge Bank 2 */
-#define BITP_DMC_EFFCTL_PRECBANK1             9                               /* Precharge Bank 1 */
-#define BITP_DMC_EFFCTL_PRECBANK0             8                               /* Precharge Bank 0 */
-#define BITP_DMC_EFFCTL_WAITWRDATA            7                               /* Wait in Write Data Snapshot */
-#define BITP_DMC_EFFCTL_FULLWRDATA            6                               /* Wait for Full Write Data */
-#define BITM_DMC_EFFCTL_IDLECYC              (_ADI_MSK(0x00F00000,uint32_t))  /* Idle Cycle */
-#define BITM_DMC_EFFCTL_NUMREF               (_ADI_MSK(0x000F0000,uint32_t))  /* Number of Refresh Commands */
-#define BITM_DMC_EFFCTL_PRECBANK7            (_ADI_MSK(0x00008000,uint32_t))  /* Precharge Bank 7 */
-#define BITM_DMC_EFFCTL_PRECBANK6            (_ADI_MSK(0x00004000,uint32_t))  /* Precharge Bank 6 */
-#define BITM_DMC_EFFCTL_PRECBANK5            (_ADI_MSK(0x00002000,uint32_t))  /* Precharge Bank 5 */
-#define BITM_DMC_EFFCTL_PRECBANK4            (_ADI_MSK(0x00001000,uint32_t))  /* Precharge Bank 4 */
-#define BITM_DMC_EFFCTL_PRECBANK3            (_ADI_MSK(0x00000800,uint32_t))  /* Precharge Bank 3 */
-#define BITM_DMC_EFFCTL_PRECBANK2            (_ADI_MSK(0x00000400,uint32_t))  /* Precharge Bank 2 */
-#define BITM_DMC_EFFCTL_PRECBANK1            (_ADI_MSK(0x00000200,uint32_t))  /* Precharge Bank 1 */
-#define BITM_DMC_EFFCTL_PRECBANK0            (_ADI_MSK(0x00000100,uint32_t))  /* Precharge Bank 0 */
-#define BITM_DMC_EFFCTL_WAITWRDATA           (_ADI_MSK(0x00000080,uint32_t))  /* Wait in Write Data Snapshot */
-#define BITM_DMC_EFFCTL_FULLWRDATA           (_ADI_MSK(0x00000040,uint32_t))  /* Wait for Full Write Data */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIO                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIO_ID2                    16                               /* ID2 Requiring Elevated Priority */
-#define BITP_DMC_PRIO_ID1                     0                               /* ID1 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID2                    (_ADI_MSK(0xFFFF0000,uint32_t))  /* ID2 Requiring Elevated Priority */
-#define BITM_DMC_PRIO_ID1                    (_ADI_MSK(0x0000FFFF,uint32_t))  /* ID1 Requiring Elevated Priority */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PRIOMSK                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PRIOMSK_ID2MSK              16                               /* Mask for ID2 */
-#define BITP_DMC_PRIOMSK_ID1MSK               0                               /* Mask for ID1 */
-#define BITM_DMC_PRIOMSK_ID2MSK              (_ADI_MSK(0xFFFF0000,uint32_t))  /* Mask for ID2 */
-#define BITM_DMC_PRIOMSK_ID1MSK              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Mask for ID1 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_CFG                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_CFG_EXTBANK                 12                               /* External Banks */
-#define BITP_DMC_CFG_SDRSIZE                  8                               /* SDRAM Size */
-#define BITP_DMC_CFG_SDRWID                   4                               /* SDRAM Width */
-#define BITP_DMC_CFG_IFWID                    0                               /* Interface Width */
-
-#define BITM_DMC_CFG_EXTBANK                 (_ADI_MSK(0x0000F000,uint32_t))  /* External Banks */
-#define ENUM_DMC_CFG_EXTBANK1                (_ADI_MSK(0x00000000,uint32_t))  /* EXTBANK: 1 External Bank */
-
-#define BITM_DMC_CFG_SDRSIZE                 (_ADI_MSK(0x00000F00,uint32_t))  /* SDRAM Size */
-#define ENUM_DMC_CFG_SDRSIZE64               (_ADI_MSK(0x00000000,uint32_t))  /* SDRSIZE: 64M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE128              (_ADI_MSK(0x00000100,uint32_t))  /* SDRSIZE: 128M Bit SDRAM (LPDDR Only) */
-#define ENUM_DMC_CFG_SDRSIZE256              (_ADI_MSK(0x00000200,uint32_t))  /* SDRSIZE: 256M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE512              (_ADI_MSK(0x00000300,uint32_t))  /* SDRSIZE: 512M Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE1G               (_ADI_MSK(0x00000400,uint32_t))  /* SDRSIZE: 1G Bit SDRAM */
-#define ENUM_DMC_CFG_SDRSIZE2G               (_ADI_MSK(0x00000500,uint32_t))  /* SDRSIZE: 2G Bit SDRAM */
-
-#define BITM_DMC_CFG_SDRWID                  (_ADI_MSK(0x000000F0,uint32_t))  /* SDRAM Width */
-#define ENUM_DMC_CFG_SDRWID16                (_ADI_MSK(0x00000020,uint32_t))  /* SDRWID: 16-Bit Wide SDRAM */
-
-#define BITM_DMC_CFG_IFWID                   (_ADI_MSK(0x0000000F,uint32_t))  /* Interface Width */
-#define ENUM_DMC_CFG_IFWID16                 (_ADI_MSK(0x00000002,uint32_t))  /* IFWID: 16-Bit Wide Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR0                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR0_TMRD                    28                               /* Timing Mode Register Delay */
-#define BITP_DMC_TR0_TRC                     20                               /* Timing Row Cycle */
-#define BITP_DMC_TR0_TRAS                    12                               /* Timing Row Active Time */
-#define BITP_DMC_TR0_TRP                      8                               /* Timing RAS Precharge. */
-#define BITP_DMC_TR0_TWTR                     4                               /* Timing Write to Read */
-#define BITP_DMC_TR0_TRCD                     0                               /* Timing RAS to CAS Delay */
-#define BITM_DMC_TR0_TMRD                    (_ADI_MSK(0xF0000000,uint32_t))  /* Timing Mode Register Delay */
-#define BITM_DMC_TR0_TRC                     (_ADI_MSK(0x03F00000,uint32_t))  /* Timing Row Cycle */
-#define BITM_DMC_TR0_TRAS                    (_ADI_MSK(0x0001F000,uint32_t))  /* Timing Row Active Time */
-#define BITM_DMC_TR0_TRP                     (_ADI_MSK(0x00000F00,uint32_t))  /* Timing RAS Precharge. */
-#define BITM_DMC_TR0_TWTR                    (_ADI_MSK(0x000000F0,uint32_t))  /* Timing Write to Read */
-#define BITM_DMC_TR0_TRCD                    (_ADI_MSK(0x0000000F,uint32_t))  /* Timing RAS to CAS Delay */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR1                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR1_TRRD                    28                               /* Timing Read-Read Delay */
-#define BITP_DMC_TR1_TRFC                    16                               /* Timing Refresh-to-Command */
-#define BITP_DMC_TR1_TREF                     0                               /* Timing Refresh Interval */
-#define BITM_DMC_TR1_TRRD                    (_ADI_MSK(0x70000000,uint32_t))  /* Timing Read-Read Delay */
-#define BITM_DMC_TR1_TRFC                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Timing Refresh-to-Command */
-#define BITM_DMC_TR1_TREF                    (_ADI_MSK(0x00003FFF,uint32_t))  /* Timing Refresh Interval */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_TR2                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_TR2_TCKE                    20                               /* Timing Clock Enable */
-#define BITP_DMC_TR2_TXP                     16                               /* Timing Exit Powerdown */
-#define BITP_DMC_TR2_TWR                     12                               /* Timing Write Recovery */
-#define BITP_DMC_TR2_TRTP                     8                               /* Timing Read-to-Precharge */
-#define BITP_DMC_TR2_TFAW                     0                               /* Timing Four-Activated-Window */
-#define BITM_DMC_TR2_TCKE                    (_ADI_MSK(0x00F00000,uint32_t))  /* Timing Clock Enable */
-#define BITM_DMC_TR2_TXP                     (_ADI_MSK(0x000F0000,uint32_t))  /* Timing Exit Powerdown */
-#define BITM_DMC_TR2_TWR                     (_ADI_MSK(0x0000F000,uint32_t))  /* Timing Write Recovery */
-#define BITM_DMC_TR2_TRTP                    (_ADI_MSK(0x00000F00,uint32_t))  /* Timing Read-to-Precharge */
-#define BITM_DMC_TR2_TFAW                    (_ADI_MSK(0x0000001F,uint32_t))  /* Timing Four-Activated-Window */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MSK                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MSK_EMR3                    11                               /* Shadow EMR3 Unmask */
-#define BITP_DMC_MSK_EMR2                    10                               /* Shadow EMR2 Unmask */
-#define BITP_DMC_MSK_EMR1                     9                               /* Shadow EMR1 Unmask */
-#define BITP_DMC_MSK_MR                       8                               /* Shadow MR Unmask */
-#define BITM_DMC_MSK_EMR3                    (_ADI_MSK(0x00000800,uint32_t))  /* Shadow EMR3 Unmask */
-#define BITM_DMC_MSK_EMR2                    (_ADI_MSK(0x00000400,uint32_t))  /* Shadow EMR2 Unmask */
-#define BITM_DMC_MSK_EMR1                    (_ADI_MSK(0x00000200,uint32_t))  /* Shadow EMR1 Unmask */
-#define BITM_DMC_MSK_MR                      (_ADI_MSK(0x00000100,uint32_t))  /* Shadow MR Unmask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_MR                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_MR_PD                       12                               /* Active Powerdown Mode */
-#define BITP_DMC_MR_WRRECOV                   9                               /* Write Recovery */
-#define BITP_DMC_MR_DLLRST                    8                               /* DLL Reset */
-#define BITP_DMC_MR_CL                        4                               /* CAS Latency */
-#define BITP_DMC_MR_BLEN                      0                               /* Burst Length */
-#define BITM_DMC_MR_PD                       (_ADI_MSK(0x00001000,uint32_t))  /* Active Powerdown Mode */
-#define BITM_DMC_MR_WRRECOV                  (_ADI_MSK(0x00000E00,uint32_t))  /* Write Recovery */
-#define BITM_DMC_MR_DLLRST                   (_ADI_MSK(0x00000100,uint32_t))  /* DLL Reset */
-
-#define BITM_DMC_MR_CL                       (_ADI_MSK(0x00000070,uint32_t))  /* CAS Latency */
-#define ENUM_DMC_MR_CL2                      (_ADI_MSK(0x00000020,uint32_t))  /* CL: 2 clock cycle latency */
-#define ENUM_DMC_MR_CL3                      (_ADI_MSK(0x00000030,uint32_t))  /* CL: 3 clock cycle latency */
-#define ENUM_DMC_MR_CL4                      (_ADI_MSK(0x00000040,uint32_t))  /* CL: 4 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL5                      (_ADI_MSK(0x00000050,uint32_t))  /* CL: 5 clock cycle latency (DDR2) */
-#define ENUM_DMC_MR_CL6                      (_ADI_MSK(0x00000060,uint32_t))  /* CL: 6 clock cycle latency (DDR2) */
-
-#define BITM_DMC_MR_BLEN                     (_ADI_MSK(0x00000007,uint32_t))  /* Burst Length */
-#define ENUM_DMC_MR_BLEN4                    (_ADI_MSK(0x00000002,uint32_t))  /* BLEN: 4-Bit Burst Length */
-#define ENUM_DMC_MR_BLEN8                    (_ADI_MSK(0x00000003,uint32_t))  /* BLEN: 8-Bit Burst Length */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR1                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR1_QOFF                   12                               /* Output Buffer Enable */
-#define BITP_DMC_EMR1_DQS                    10                               /* DQS Enable */
-#define BITP_DMC_EMR1_RTT1                    6                               /* Termination Resistance 1 */
-#define BITP_DMC_EMR1_AL                      3                               /* Additive Latency */
-#define BITP_DMC_EMR1_RTT0                    2                               /* Termination Resistance 0. */
-#define BITP_DMC_EMR1_DIC                     1                               /* Output Driver Impedance Control */
-#define BITP_DMC_EMR1_DLLEN                   0                               /* DLL Enable */
-#define BITM_DMC_EMR1_QOFF                   (_ADI_MSK(0x00001000,uint32_t))  /* Output Buffer Enable */
-#define BITM_DMC_EMR1_DQS                    (_ADI_MSK(0x00000400,uint32_t))  /* DQS Enable */
-
-#define BITM_DMC_EMR1_RTT1                   (_ADI_MSK(0x00000040,uint32_t))  /* Termination Resistance 1 */
-#define ENUM_DMC_EMR1_RTT1_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT1: Disable RTT1 */
-#define ENUM_DMC_EMR1_RTT1_1                 (_ADI_MSK(0x00000040,uint32_t))  /* RTT1: Enable RTT1 */
-#define BITM_DMC_EMR1_AL                     (_ADI_MSK(0x00000038,uint32_t))  /* Additive Latency */
-
-#define BITM_DMC_EMR1_RTT0                   (_ADI_MSK(0x00000004,uint32_t))  /* Termination Resistance 0. */
-#define ENUM_DMC_EMR1_RTT0_0                 (_ADI_MSK(0x00000000,uint32_t))  /* RTT0: Disable RTT0 */
-#define ENUM_DMC_EMR1_RTT0_1                 (_ADI_MSK(0x00000004,uint32_t))  /* RTT0: Enable RTT0 */
-#define BITM_DMC_EMR1_DIC                    (_ADI_MSK(0x00000002,uint32_t))  /* Output Driver Impedance Control */
-#define BITM_DMC_EMR1_DLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* DLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_EMR2                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_EMR2_SRF                     7                               /* High Temp. Self Refresh */
-#define BITP_DMC_EMR2_DS                      5                               /* Drive Strength */
-#define BITP_DMC_EMR2_TCSR                    3                               /* Temp. Comp. Self Refresh */
-#define BITP_DMC_EMR2_PASR                    0                               /* Partial Array Self Refresh */
-#define BITM_DMC_EMR2_SRF                    (_ADI_MSK(0x00000080,uint32_t))  /* High Temp. Self Refresh */
-#define BITM_DMC_EMR2_DS                     (_ADI_MSK(0x00000060,uint32_t))  /* Drive Strength */
-#define BITM_DMC_EMR2_TCSR                   (_ADI_MSK(0x00000018,uint32_t))  /* Temp. Comp. Self Refresh */
-#define BITM_DMC_EMR2_PASR                   (_ADI_MSK(0x00000007,uint32_t))  /* Partial Array Self Refresh */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_DLLCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_DLLCTL_DATACYC               8                               /* Data Cycles */
-#define BITP_DMC_DLLCTL_DLLCALRDCNT           0                               /* DLL Calibration RD Count */
-
-#define BITM_DMC_DLLCTL_DATACYC              (_ADI_MSK(0x00000F00,uint32_t))  /* Data Cycles */
-#define ENUM_DMC_DLLCTL_DATACYC2             (_ADI_MSK(0x00000200,uint32_t))  /* DATACYC: 2 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC3             (_ADI_MSK(0x00000300,uint32_t))  /* DATACYC: 3 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC4             (_ADI_MSK(0x00000400,uint32_t))  /* DATACYC: 4 Clock Cycles Latency */
-#define ENUM_DMC_DLLCTL_DATACYC5             (_ADI_MSK(0x00000500,uint32_t))  /* DATACYC: 5 Clock Cycles Latency */
-#define BITM_DMC_DLLCTL_DLLCALRDCNT          (_ADI_MSK(0x000000FF,uint32_t))  /* DLL Calibration RD Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL1                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL1_CONTODTVAL         19                               /* Select ODT value on controller */
-
-#define BITM_DMC_PHY_CTL1_CONTODTVAL         (_ADI_MSK(0x00080000,uint32_t))  /* Select ODT value on controller */
-#define ENUM_DMC_PHY_CTL1_ODT_75             (_ADI_MSK(0x00000000,uint32_t))  /* CONTODTVAL: 75 Ohms Termination */
-#define ENUM_DMC_PHY_CTL1_ODT_150            (_ADI_MSK(0x00080000,uint32_t))  /* CONTODTVAL: 150 Ohms Termination */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PHY_CTL3                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PHY_CTL3_OFST1              26                               /* Offset Parameter 1 */
-#define BITP_DMC_PHY_CTL3_OFST0              24                               /* Offset Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQS           10                               /* Enables controller ODT on read of DQS */
-#define BITP_DMC_PHY_CTL3_TMG1                7                               /* Timing Parameter 1 */
-#define BITP_DMC_PHY_CTL3_TMG0                6                               /* Timing Parameter 0 */
-#define BITP_DMC_PHY_CTL3_ENODTDQ             2                               /* Enables controller ODT on read of DQ */
-#define BITM_DMC_PHY_CTL3_OFST1              (_ADI_MSK(0x04000000,uint32_t))  /* Offset Parameter 1 */
-#define BITM_DMC_PHY_CTL3_OFST0              (_ADI_MSK(0x01000000,uint32_t))  /* Offset Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQS           (_ADI_MSK(0x00000400,uint32_t))  /* Enables controller ODT on read of DQS */
-#define BITM_DMC_PHY_CTL3_TMG1               (_ADI_MSK(0x00000080,uint32_t))  /* Timing Parameter 1 */
-#define BITM_DMC_PHY_CTL3_TMG0               (_ADI_MSK(0x00000040,uint32_t))  /* Timing Parameter 0 */
-#define BITM_DMC_PHY_CTL3_ENODTDQ            (_ADI_MSK(0x00000004,uint32_t))  /* Enables controller ODT on read of DQ */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMC_PADCTL                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMC_PADCTL_CKEOE                19                               /* CKE Output Enable */
-#define BITP_DMC_PADCTL_CKEPWD               18                               /* CKE pad receiver power down. */
-#define BITP_DMC_PADCTL_CKEODS               16                               /* CKE Output Drive Strength */
-#define BITP_DMC_PADCTL_CMDOE                15                               /* CMD Output Enable */
-#define BITP_DMC_PADCTL_CMDPWD               14                               /* CMD Powerdown */
-#define BITP_DMC_PADCTL_CMDODS               12                               /* CMD Output Drive Strength */
-#define BITP_DMC_PADCTL_CLKOE                11                               /* CLK Output Enable */
-#define BITP_DMC_PADCTL_CLKPWD               10                               /* CLK Powerdown */
-#define BITP_DMC_PADCTL_CLKODS                8                               /* Clock Output Drive Strength */
-#define BITP_DMC_PADCTL_DQSPWD                6                               /* DQ/DQS Powerdown */
-#define BITP_DMC_PADCTL_DQSODS                4                               /* DQS Output Drive Strength */
-#define BITP_DMC_PADCTL_DQPWD                 2                               /* DQ Powerdown. */
-#define BITP_DMC_PADCTL_DQODS                 0                               /* DQ Output Drive Strength */
-#define BITM_DMC_PADCTL_CKEOE                (_ADI_MSK(0x00080000,uint32_t))  /* CKE Output Enable */
-#define BITM_DMC_PADCTL_CKEPWD               (_ADI_MSK(0x00040000,uint32_t))  /* CKE pad receiver power down. */
-#define BITM_DMC_PADCTL_CKEODS               (_ADI_MSK(0x00030000,uint32_t))  /* CKE Output Drive Strength */
-#define BITM_DMC_PADCTL_CMDOE                (_ADI_MSK(0x00008000,uint32_t))  /* CMD Output Enable */
-#define BITM_DMC_PADCTL_CMDPWD               (_ADI_MSK(0x00004000,uint32_t))  /* CMD Powerdown */
-#define BITM_DMC_PADCTL_CMDODS               (_ADI_MSK(0x00003000,uint32_t))  /* CMD Output Drive Strength */
-#define BITM_DMC_PADCTL_CLKOE                (_ADI_MSK(0x00000800,uint32_t))  /* CLK Output Enable */
-#define BITM_DMC_PADCTL_CLKPWD               (_ADI_MSK(0x00000400,uint32_t))  /* CLK Powerdown */
-#define BITM_DMC_PADCTL_CLKODS               (_ADI_MSK(0x00000300,uint32_t))  /* Clock Output Drive Strength */
-#define BITM_DMC_PADCTL_DQSPWD               (_ADI_MSK(0x00000040,uint32_t))  /* DQ/DQS Powerdown */
-#define BITM_DMC_PADCTL_DQSODS               (_ADI_MSK(0x00000030,uint32_t))  /* DQS Output Drive Strength */
-#define BITM_DMC_PADCTL_DQPWD                (_ADI_MSK(0x00000004,uint32_t))  /* DQ Powerdown. */
-#define BITM_DMC_PADCTL_DQODS                (_ADI_MSK(0x00000003,uint32_t))  /* DQ Output Drive Strength */
-
-/* ==================================================
-        System Cross Bar Registers
-   ================================================== */
-
-/* =========================
-        SCB0
-   ========================= */
-#define REG_SCB0_ARBR0                  0xFFCA2408         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR1                  0xFFCA2428         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR2                  0xFFCA2448         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR3                  0xFFCA2468         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR4                  0xFFCA2488         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBR5                  0xFFCA24A8         /* SCB0 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB0_ARBW0                  0xFFCA240C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW1                  0xFFCA242C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW2                  0xFFCA244C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW3                  0xFFCA246C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW4                  0xFFCA248C         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_ARBW5                  0xFFCA24AC         /* SCB0 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB0_SLAVES                 0xFFCA2FC0         /* SCB0 Slave Interfaces Number Register */
-#define REG_SCB0_MASTERS                0xFFCA2FC4         /* SCB0 Master Interfaces Number Register */
-
-/* =========================
-        SCB1
-   ========================= */
-#define REG_SCB1_ARBR0                  0xFFC42408         /* SCB1 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB1_ARBW0                  0xFFC4240C         /* SCB1 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB1_SLAVES                 0xFFC42FC0         /* SCB1 Slave Interfaces Number Register */
-#define REG_SCB1_MASTERS                0xFFC42FC4         /* SCB1 Master Interfaces Number Register */
-
-/* =========================
-        SCB2
-   ========================= */
-#define REG_SCB2_ARBR0                  0xFFC06408         /* SCB2 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB2_ARBW0                  0xFFC0640C         /* SCB2 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB2_SLAVES                 0xFFC06FC0         /* SCB2 Slave Interfaces Number Register */
-#define REG_SCB2_MASTERS                0xFFC06FC4         /* SCB2 Master Interfaces Number Register */
-
-/* =========================
-        SCB3
-   ========================= */
-#define REG_SCB3_ARBR0                  0xFFC08408         /* SCB3 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB3_ARBW0                  0xFFC0840C         /* SCB3 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB3_SLAVES                 0xFFC08FC0         /* SCB3 Slave Interfaces Number Register */
-#define REG_SCB3_MASTERS                0xFFC08FC4         /* SCB3 Master Interfaces Number Register */
-
-/* =========================
-        SCB4
-   ========================= */
-#define REG_SCB4_ARBR0                  0xFFC0A408         /* SCB4 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB4_ARBW0                  0xFFC0A40C         /* SCB4 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB4_SLAVES                 0xFFC0AFC0         /* SCB4 Slave Interfaces Number Register */
-#define REG_SCB4_MASTERS                0xFFC0AFC4         /* SCB4 Master Interfaces Number Register */
-
-/* =========================
-        SCB5
-   ========================= */
-#define REG_SCB5_ARBR0                  0xFFC0C408         /* SCB5 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB5_ARBW0                  0xFFC0C40C         /* SCB5 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB5_SLAVES                 0xFFC0CFC0         /* SCB5 Slave Interfaces Number Register */
-#define REG_SCB5_MASTERS                0xFFC0CFC4         /* SCB5 Master Interfaces Number Register */
-
-/* =========================
-        SCB6
-   ========================= */
-#define REG_SCB6_ARBR0                  0xFFC0E408         /* SCB6 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB6_ARBW0                  0xFFC0E40C         /* SCB6 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB6_SLAVES                 0xFFC0EFC0         /* SCB6 Slave Interfaces Number Register */
-#define REG_SCB6_MASTERS                0xFFC0EFC4         /* SCB6 Master Interfaces Number Register */
-
-/* =========================
-        SCB7
-   ========================= */
-#define REG_SCB7_ARBR0                  0xFFC11408         /* SCB7 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB7_ARBW0                  0xFFC1140C         /* SCB7 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB7_SLAVES                 0xFFC11FC0         /* SCB7 Slave Interfaces Number Register */
-#define REG_SCB7_MASTERS                0xFFC11FC4         /* SCB7 Master Interfaces Number Register */
-
-/* =========================
-        SCB8
-   ========================= */
-#define REG_SCB8_ARBR0                  0xFFC13408         /* SCB8 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB8_ARBW0                  0xFFC1340C         /* SCB8 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB8_SLAVES                 0xFFC13FC0         /* SCB8 Slave Interfaces Number Register */
-#define REG_SCB8_MASTERS                0xFFC13FC4         /* SCB8 Master Interfaces Number Register */
-
-/* =========================
-        SCB9
-   ========================= */
-#define REG_SCB9_ARBR0                  0xFFC15408         /* SCB9 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB9_ARBW0                  0xFFC1540C         /* SCB9 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB9_SLAVES                 0xFFC15FC0         /* SCB9 Slave Interfaces Number Register */
-#define REG_SCB9_MASTERS                0xFFC15FC4         /* SCB9 Master Interfaces Number Register */
-
-/* =========================
-        SCB10
-   ========================= */
-#define REG_SCB10_ARBR0                 0xFFCA1408         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR1                 0xFFCA1428         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBR2                 0xFFCA1448         /* SCB10 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB10_ARBW0                 0xFFCA140C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW1                 0xFFCA142C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_ARBW2                 0xFFCA144C         /* SCB10 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB10_SLAVES                0xFFCA1FC0         /* SCB10 Slave Interfaces Number Register */
-#define REG_SCB10_MASTERS               0xFFCA1FC4         /* SCB10 Master Interfaces Number Register */
-
-/* =========================
-        SCB11
-   ========================= */
-#define REG_SCB11_ARBR0                 0xFFCA0408         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR1                 0xFFCA0428         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR2                 0xFFCA0448         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR3                 0xFFCA0468         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR4                 0xFFCA0488         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR5                 0xFFCA04A8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBR6                 0xFFCA04C8         /* SCB11 Arbitration Read Channel Master Interface n Register */
-#define REG_SCB11_ARBW0                 0xFFCA040C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW1                 0xFFCA042C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW2                 0xFFCA044C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW3                 0xFFCA046C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW4                 0xFFCA048C         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW5                 0xFFCA04AC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_ARBW6                 0xFFCA04CC         /* SCB11 Arbitration Write Channel Master Interface n Register */
-#define REG_SCB11_SLAVES                0xFFCA0FC0         /* SCB11 Slave Interfaces Number Register */
-#define REG_SCB11_MASTERS               0xFFCA0FC4         /* SCB11 Master Interfaces Number Register */
-
-/* =========================
-        SCB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBR                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBR_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBR_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBR_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBR_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_ARBW                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_ARBW_SLOT                   24                               /* Slot Number */
-#define BITP_SCB_ARBW_SLAVE                   0                               /* Slave Interface */
-#define BITM_SCB_ARBW_SLOT                   (_ADI_MSK(0xFF000000,uint32_t))  /* Slot Number */
-#define BITM_SCB_ARBW_SLAVE                  (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_SLAVES                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_SLAVES_SI                    0                               /* Slave Interface Value */
-#define BITM_SCB_SLAVES_SI                   (_ADI_MSK(0x000000FF,uint32_t))  /* Slave Interface Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SCB_MASTERS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SCB_MASTERS_MI                   0                               /* Master Interface Value */
-#define BITM_SCB_MASTERS_MI                  (_ADI_MSK(0x000000FF,uint32_t))  /* Master Interface Value */
-
-/* ==================================================
-        L2 Memory Controller Registers
-   ================================================== */
-
-/* =========================
-        L2CTL0
-   ========================= */
-#define REG_L2CTL0_CTL                  0xFFCA3000         /* L2CTL0 Control Register */
-#define REG_L2CTL0_ACTL_C0              0xFFCA3004         /* L2CTL0 Access Control Core 0 Register */
-#define REG_L2CTL0_ACTL_C1              0xFFCA3008         /* L2CTL0 Access Control Core 1 Register */
-#define REG_L2CTL0_ACTL_SYS             0xFFCA300C         /* L2CTL0 Access Control System Register */
-#define REG_L2CTL0_STAT                 0xFFCA3010         /* L2CTL0 Status Register */
-#define REG_L2CTL0_RPCR                 0xFFCA3014         /* L2CTL0 Read Priority Count Register */
-#define REG_L2CTL0_WPCR                 0xFFCA3018         /* L2CTL0 Write Priority Count Register */
-#define REG_L2CTL0_RFA                  0xFFCA3024         /* L2CTL0 Refresh Address Register */
-#define REG_L2CTL0_ERRADDR0             0xFFCA3040         /* L2CTL0 ECC Error Address 0 Register */
-#define REG_L2CTL0_ERRADDR1             0xFFCA3044         /* L2CTL0 ECC Error Address 1 Register */
-#define REG_L2CTL0_ERRADDR2             0xFFCA3048         /* L2CTL0 ECC Error Address 2 Register */
-#define REG_L2CTL0_ERRADDR3             0xFFCA304C         /* L2CTL0 ECC Error Address 3 Register */
-#define REG_L2CTL0_ERRADDR4             0xFFCA3050         /* L2CTL0 ECC Error Address 4 Register */
-#define REG_L2CTL0_ERRADDR5             0xFFCA3054         /* L2CTL0 ECC Error Address 5 Register */
-#define REG_L2CTL0_ERRADDR6             0xFFCA3058         /* L2CTL0 ECC Error Address 6 Register */
-#define REG_L2CTL0_ERRADDR7             0xFFCA305C         /* L2CTL0 ECC Error Address 7 Register */
-#define REG_L2CTL0_ET0                  0xFFCA3080         /* L2CTL0 Error Type 0 Register */
-#define REG_L2CTL0_EADDR0               0xFFCA3084         /* L2CTL0 Error Type 0 Address Register */
-#define REG_L2CTL0_ET1                  0xFFCA3088         /* L2CTL0 Error Type 1 Register */
-#define REG_L2CTL0_EADDR1               0xFFCA308C         /* L2CTL0 Error Type 1 Address Register */
-
-/* =========================
-        L2CTL
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_CTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_CTL_LOCK                  31                               /* Lock */
-#define BITP_L2CTL_CTL_DISURP                16                               /* Disable Urgent Request Priority */
-#define BITP_L2CTL_CTL_ECCMAP7               15                               /* ECC Map Bank 7 */
-#define BITP_L2CTL_CTL_ECCMAP6               14                               /* ECC Map Bank 6 */
-#define BITP_L2CTL_CTL_ECCMAP5               13                               /* ECC Map Bank 5 */
-#define BITP_L2CTL_CTL_ECCMAP4               12                               /* ECC Map Bank 4 */
-#define BITP_L2CTL_CTL_ECCMAP3               11                               /* ECC Map Bank 3 */
-#define BITP_L2CTL_CTL_ECCMAP2               10                               /* ECC Map Bank 2 */
-#define BITP_L2CTL_CTL_ECCMAP1                9                               /* ECC Map Bank 1 */
-#define BITP_L2CTL_CTL_ECCMAP0                8                               /* ECC Map Bank 0 */
-#define BITP_L2CTL_CTL_BK7EDIS                7                               /* Bank 7 ECC Disable */
-#define BITP_L2CTL_CTL_BK6EDIS                6                               /* Bank 6 ECC Disable */
-#define BITP_L2CTL_CTL_BK5EDIS                5                               /* Bank 5 ECC Disable */
-#define BITP_L2CTL_CTL_BK4EDIS                4                               /* Bank 4 ECC Disable */
-#define BITP_L2CTL_CTL_BK3EDIS                3                               /* Bank 3 ECC Disable */
-#define BITP_L2CTL_CTL_BK2EDIS                2                               /* Bank 2 ECC Disable */
-#define BITP_L2CTL_CTL_BK1EDIS                1                               /* Bank 1 ECC Disable */
-#define BITP_L2CTL_CTL_BK0EDIS                0                               /* Bank 0 ECC Disable */
-#define BITM_L2CTL_CTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_CTL_DISURP                (_ADI_MSK(0x00010000,uint32_t))  /* Disable Urgent Request Priority */
-#define BITM_L2CTL_CTL_ECCMAP7               (_ADI_MSK(0x00008000,uint32_t))  /* ECC Map Bank 7 */
-#define BITM_L2CTL_CTL_ECCMAP6               (_ADI_MSK(0x00004000,uint32_t))  /* ECC Map Bank 6 */
-#define BITM_L2CTL_CTL_ECCMAP5               (_ADI_MSK(0x00002000,uint32_t))  /* ECC Map Bank 5 */
-#define BITM_L2CTL_CTL_ECCMAP4               (_ADI_MSK(0x00001000,uint32_t))  /* ECC Map Bank 4 */
-#define BITM_L2CTL_CTL_ECCMAP3               (_ADI_MSK(0x00000800,uint32_t))  /* ECC Map Bank 3 */
-#define BITM_L2CTL_CTL_ECCMAP2               (_ADI_MSK(0x00000400,uint32_t))  /* ECC Map Bank 2 */
-#define BITM_L2CTL_CTL_ECCMAP1               (_ADI_MSK(0x00000200,uint32_t))  /* ECC Map Bank 1 */
-#define BITM_L2CTL_CTL_ECCMAP0               (_ADI_MSK(0x00000100,uint32_t))  /* ECC Map Bank 0 */
-#define BITM_L2CTL_CTL_BK7EDIS               (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 ECC Disable */
-#define BITM_L2CTL_CTL_BK6EDIS               (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 ECC Disable */
-#define BITM_L2CTL_CTL_BK5EDIS               (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 ECC Disable */
-#define BITM_L2CTL_CTL_BK4EDIS               (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 ECC Disable */
-#define BITM_L2CTL_CTL_BK3EDIS               (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 ECC Disable */
-#define BITM_L2CTL_CTL_BK2EDIS               (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 ECC Disable */
-#define BITM_L2CTL_CTL_BK1EDIS               (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 ECC Disable */
-#define BITM_L2CTL_CTL_BK0EDIS               (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 ECC Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C0                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C0_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C0_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C0_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C0_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C0_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C0_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_C1                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_C1_LOCK              31                               /* Lock */
-#define BITP_L2CTL_ACTL_C1_BK7WDIS            7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK6WDIS            6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK5WDIS            5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK4WDIS            4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK3WDIS            3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK2WDIS            2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK1WDIS            1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_C1_BK0WDIS            0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_C1_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_C1_BK7WDIS           (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK6WDIS           (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK5WDIS           (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK4WDIS           (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK3WDIS           (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK2WDIS           (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK1WDIS           (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_C1_BK0WDIS           (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ACTL_SYS                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ACTL_SYS_LOCK             31                               /* Lock */
-#define BITP_L2CTL_ACTL_SYS_BK7WDIS           7                               /* Bank 7 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK6WDIS           6                               /* Bank 6 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK5WDIS           5                               /* Bank 5 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK4WDIS           4                               /* Bank 4 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK3WDIS           3                               /* Bank 3 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK2WDIS           2                               /* Bank 2 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK1WDIS           1                               /* Bank 1 Write Disable */
-#define BITP_L2CTL_ACTL_SYS_BK0WDIS           0                               /* Bank 0 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_LOCK             (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_L2CTL_ACTL_SYS_BK7WDIS          (_ADI_MSK(0x00000080,uint32_t))  /* Bank 7 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK6WDIS          (_ADI_MSK(0x00000040,uint32_t))  /* Bank 6 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK5WDIS          (_ADI_MSK(0x00000020,uint32_t))  /* Bank 5 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK4WDIS          (_ADI_MSK(0x00000010,uint32_t))  /* Bank 4 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK3WDIS          (_ADI_MSK(0x00000008,uint32_t))  /* Bank 3 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK2WDIS          (_ADI_MSK(0x00000004,uint32_t))  /* Bank 2 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK1WDIS          (_ADI_MSK(0x00000002,uint32_t))  /* Bank 1 Write Disable */
-#define BITM_L2CTL_ACTL_SYS_BK0WDIS          (_ADI_MSK(0x00000001,uint32_t))  /* Bank 0 Write Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_STAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_STAT_ECCERR7              15                               /* ECC Error Bank 7 */
-#define BITP_L2CTL_STAT_ECCERR6              14                               /* ECC Error Bank 6 */
-#define BITP_L2CTL_STAT_ECCERR5              13                               /* ECC Error Bank 5 */
-#define BITP_L2CTL_STAT_ECCERR4              12                               /* ECC Error Bank 4 */
-#define BITP_L2CTL_STAT_ECCERR3              11                               /* ECC Error Bank 3 */
-#define BITP_L2CTL_STAT_ECCERR2              10                               /* ECC Error Bank 2 */
-#define BITP_L2CTL_STAT_ECCERR1               9                               /* ECC Error Bank 1 */
-#define BITP_L2CTL_STAT_ECCERR0               8                               /* ECC Error Bank 0 */
-#define BITP_L2CTL_STAT_RFRS                  4                               /* Refresh Register Status */
-#define BITP_L2CTL_STAT_ERR1                  1                               /* Error Port 1 */
-#define BITP_L2CTL_STAT_ERR0                  0                               /* Error Port 0 */
-#define BITM_L2CTL_STAT_ECCERR7              (_ADI_MSK(0x00008000,uint32_t))  /* ECC Error Bank 7 */
-#define BITM_L2CTL_STAT_ECCERR6              (_ADI_MSK(0x00004000,uint32_t))  /* ECC Error Bank 6 */
-#define BITM_L2CTL_STAT_ECCERR5              (_ADI_MSK(0x00002000,uint32_t))  /* ECC Error Bank 5 */
-#define BITM_L2CTL_STAT_ECCERR4              (_ADI_MSK(0x00001000,uint32_t))  /* ECC Error Bank 4 */
-#define BITM_L2CTL_STAT_ECCERR3              (_ADI_MSK(0x00000800,uint32_t))  /* ECC Error Bank 3 */
-#define BITM_L2CTL_STAT_ECCERR2              (_ADI_MSK(0x00000400,uint32_t))  /* ECC Error Bank 2 */
-#define BITM_L2CTL_STAT_ECCERR1              (_ADI_MSK(0x00000200,uint32_t))  /* ECC Error Bank 1 */
-#define BITM_L2CTL_STAT_ECCERR0              (_ADI_MSK(0x00000100,uint32_t))  /* ECC Error Bank 0 */
-#define BITM_L2CTL_STAT_RFRS                 (_ADI_MSK(0x00000010,uint32_t))  /* Refresh Register Status */
-#define BITM_L2CTL_STAT_ERR1                 (_ADI_MSK(0x00000002,uint32_t))  /* Error Port 1 */
-#define BITM_L2CTL_STAT_ERR0                 (_ADI_MSK(0x00000001,uint32_t))  /* Error Port 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RPCR_RPC1                  8                               /* Read Priority Count 1 */
-#define BITP_L2CTL_RPCR_RPC0                  0                               /* Read Priority Count 0 */
-#define BITM_L2CTL_RPCR_RPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Read Priority Count 1 */
-#define BITM_L2CTL_RPCR_RPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Read Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_WPCR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_WPCR_WPC1                  8                               /* Write Priority Count 1 */
-#define BITP_L2CTL_WPCR_WPC0                  0                               /* Write Priority Count 0 */
-#define BITM_L2CTL_WPCR_WPC1                 (_ADI_MSK(0x0000FF00,uint32_t))  /* Write Priority Count 1 */
-#define BITM_L2CTL_WPCR_WPC0                 (_ADI_MSK(0x000000FF,uint32_t))  /* Write Priority Count 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_RFA                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_RFA_ADDRHI                16                               /* Address High */
-#define BITP_L2CTL_RFA_ADDRLO                 0                               /* Address Low */
-#define BITM_L2CTL_RFA_ADDRHI                (_ADI_MSK(0xFFFF0000,uint32_t))  /* Address High */
-#define BITM_L2CTL_RFA_ADDRLO                (_ADI_MSK(0x0000FFFF,uint32_t))  /* Address Low */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET0                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET0_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET0_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET0_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET0_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET0_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET0_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET0_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET0_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET0_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET0_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET0_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET0_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L2CTL_ET1                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L2CTL_ET1_ID                     8                               /* Error ID */
-#define BITP_L2CTL_ET1_RDWR                   4                               /* Read/Write Error */
-#define BITP_L2CTL_ET1_ECCERR                 3                               /* ECC Error */
-#define BITP_L2CTL_ET1_ACCERR                 2                               /* Access Error */
-#define BITP_L2CTL_ET1_RSVERR                 1                               /* Reserved Error */
-#define BITP_L2CTL_ET1_ROMERR                 0                               /* ROM Error */
-#define BITM_L2CTL_ET1_ID                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Error ID */
-#define BITM_L2CTL_ET1_RDWR                  (_ADI_MSK(0x00000010,uint32_t))  /* Read/Write Error */
-#define BITM_L2CTL_ET1_ECCERR                (_ADI_MSK(0x00000008,uint32_t))  /* ECC Error */
-#define BITM_L2CTL_ET1_ACCERR                (_ADI_MSK(0x00000004,uint32_t))  /* Access Error */
-#define BITM_L2CTL_ET1_RSVERR                (_ADI_MSK(0x00000002,uint32_t))  /* Reserved Error */
-#define BITM_L2CTL_ET1_ROMERR                (_ADI_MSK(0x00000001,uint32_t))  /* ROM Error */
-
-/* ==================================================
-        System Event Controller Registers
-   ================================================== */
-
-/* =========================
-        SEC0
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Core Interface (SCI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_CCTL0                  0xFFCA4400         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CCTL1                  0xFFCA4440         /* SEC0 SCI Control Register n */
-#define REG_SEC0_CSTAT0                 0xFFCA4404         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CSTAT1                 0xFFCA4444         /* SEC0 SCI Status Register n */
-#define REG_SEC0_CPND0                  0xFFCA4408         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CPND1                  0xFFCA4448         /* SEC0 Core Pending Register n */
-#define REG_SEC0_CACT0                  0xFFCA440C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CACT1                  0xFFCA444C         /* SEC0 SCI Active Register n */
-#define REG_SEC0_CPMSK0                 0xFFCA4410         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CPMSK1                 0xFFCA4450         /* SEC0 SCI Priority Mask Register n */
-#define REG_SEC0_CGMSK0                 0xFFCA4414         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CGMSK1                 0xFFCA4454         /* SEC0 SCI Group Mask Register n */
-#define REG_SEC0_CPLVL0                 0xFFCA4418         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CPLVL1                 0xFFCA4458         /* SEC0 SCI Priority Level Register n */
-#define REG_SEC0_CSID0                  0xFFCA441C         /* SEC0 SCI Source ID Register n */
-#define REG_SEC0_CSID1                  0xFFCA445C         /* SEC0 SCI Source ID Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Fault Management Interface (SFI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_FCTL                   0xFFCA4010         /* SEC0 Fault Control Register */
-#define REG_SEC0_FSTAT                  0xFFCA4014         /* SEC0 Fault Status Register */
-#define REG_SEC0_FSID                   0xFFCA4018         /* SEC0 Fault Source ID Register */
-#define REG_SEC0_FEND                   0xFFCA401C         /* SEC0 Fault End Register */
-#define REG_SEC0_FDLY                   0xFFCA4020         /* SEC0 Fault Delay Register */
-#define REG_SEC0_FDLY_CUR               0xFFCA4024         /* SEC0 Fault Delay Current Register */
-#define REG_SEC0_FSRDLY                 0xFFCA4028         /* SEC0 Fault System Reset Delay Register */
-#define REG_SEC0_FSRDLY_CUR             0xFFCA402C         /* SEC0 Fault System Reset Delay Current Register */
-#define REG_SEC0_FCOPP                  0xFFCA4030         /* SEC0 Fault COP Period Register */
-#define REG_SEC0_FCOPP_CUR              0xFFCA4034         /* SEC0 Fault COP Period Current Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Global Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_GCTL                   0xFFCA4000         /* SEC0 Global Control Register */
-#define REG_SEC0_GSTAT                  0xFFCA4004         /* SEC0 Global Status Register */
-#define REG_SEC0_RAISE                  0xFFCA4008         /* SEC0 Global Raise Register */
-#define REG_SEC0_END                    0xFFCA400C         /* SEC0 Global End Register */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-       SEC Source Interface (SSI) Register Definitions
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define REG_SEC0_SCTL0                  0xFFCA4800         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL1                  0xFFCA4808         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL2                  0xFFCA4810         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL3                  0xFFCA4818         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL4                  0xFFCA4820         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL5                  0xFFCA4828         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL6                  0xFFCA4830         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL7                  0xFFCA4838         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL8                  0xFFCA4840         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL9                  0xFFCA4848         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL10                 0xFFCA4850         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL11                 0xFFCA4858         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL12                 0xFFCA4860         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL13                 0xFFCA4868         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL14                 0xFFCA4870         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL15                 0xFFCA4878         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL16                 0xFFCA4880         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL17                 0xFFCA4888         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL18                 0xFFCA4890         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL19                 0xFFCA4898         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL20                 0xFFCA48A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL21                 0xFFCA48A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL22                 0xFFCA48B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL23                 0xFFCA48B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL24                 0xFFCA48C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL25                 0xFFCA48C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL26                 0xFFCA48D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL27                 0xFFCA48D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL28                 0xFFCA48E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL29                 0xFFCA48E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL30                 0xFFCA48F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL31                 0xFFCA48F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL32                 0xFFCA4900         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL33                 0xFFCA4908         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL34                 0xFFCA4910         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL35                 0xFFCA4918         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL36                 0xFFCA4920         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL37                 0xFFCA4928         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL38                 0xFFCA4930         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL39                 0xFFCA4938         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL40                 0xFFCA4940         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL41                 0xFFCA4948         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL42                 0xFFCA4950         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL43                 0xFFCA4958         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL44                 0xFFCA4960         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL45                 0xFFCA4968         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL46                 0xFFCA4970         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL47                 0xFFCA4978         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL48                 0xFFCA4980         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL49                 0xFFCA4988         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL50                 0xFFCA4990         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL51                 0xFFCA4998         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL52                 0xFFCA49A0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL53                 0xFFCA49A8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL54                 0xFFCA49B0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL55                 0xFFCA49B8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL56                 0xFFCA49C0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL57                 0xFFCA49C8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL58                 0xFFCA49D0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL59                 0xFFCA49D8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL60                 0xFFCA49E0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL61                 0xFFCA49E8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL62                 0xFFCA49F0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL63                 0xFFCA49F8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL64                 0xFFCA4A00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL65                 0xFFCA4A08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL66                 0xFFCA4A10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL67                 0xFFCA4A18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL68                 0xFFCA4A20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL69                 0xFFCA4A28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL70                 0xFFCA4A30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL71                 0xFFCA4A38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL72                 0xFFCA4A40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL73                 0xFFCA4A48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL74                 0xFFCA4A50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL75                 0xFFCA4A58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL76                 0xFFCA4A60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL77                 0xFFCA4A68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL78                 0xFFCA4A70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL79                 0xFFCA4A78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL80                 0xFFCA4A80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL81                 0xFFCA4A88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL82                 0xFFCA4A90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL83                 0xFFCA4A98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL84                 0xFFCA4AA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL85                 0xFFCA4AA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL86                 0xFFCA4AB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL87                 0xFFCA4AB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL88                 0xFFCA4AC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL89                 0xFFCA4AC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL90                 0xFFCA4AD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL91                 0xFFCA4AD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL92                 0xFFCA4AE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL93                 0xFFCA4AE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL94                 0xFFCA4AF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL95                 0xFFCA4AF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL96                 0xFFCA4B00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL97                 0xFFCA4B08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL98                 0xFFCA4B10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL99                 0xFFCA4B18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL100                0xFFCA4B20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL101                0xFFCA4B28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL102                0xFFCA4B30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL103                0xFFCA4B38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL104                0xFFCA4B40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL105                0xFFCA4B48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL106                0xFFCA4B50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL107                0xFFCA4B58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL108                0xFFCA4B60         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL109                0xFFCA4B68         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL110                0xFFCA4B70         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL111                0xFFCA4B78         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL112                0xFFCA4B80         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL113                0xFFCA4B88         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL114                0xFFCA4B90         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL115                0xFFCA4B98         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL116                0xFFCA4BA0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL117                0xFFCA4BA8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL118                0xFFCA4BB0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL119                0xFFCA4BB8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL120                0xFFCA4BC0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL121                0xFFCA4BC8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL122                0xFFCA4BD0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL123                0xFFCA4BD8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL124                0xFFCA4BE0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL125                0xFFCA4BE8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL126                0xFFCA4BF0         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL127                0xFFCA4BF8         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL128                0xFFCA4C00         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL129                0xFFCA4C08         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL130                0xFFCA4C10         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL131                0xFFCA4C18         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL132                0xFFCA4C20         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL133                0xFFCA4C28         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL134                0xFFCA4C30         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL135                0xFFCA4C38         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL136                0xFFCA4C40         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL137                0xFFCA4C48         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL138                0xFFCA4C50         /* SEC0 Source Control Register n */
-#define REG_SEC0_SCTL139                0xFFCA4C58         /* SEC0 Source Control Register n */
-#define REG_SEC0_SSTAT0                 0xFFCA4804         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT1                 0xFFCA480C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT2                 0xFFCA4814         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT3                 0xFFCA481C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT4                 0xFFCA4824         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT5                 0xFFCA482C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT6                 0xFFCA4834         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT7                 0xFFCA483C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT8                 0xFFCA4844         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT9                 0xFFCA484C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT10                0xFFCA4854         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT11                0xFFCA485C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT12                0xFFCA4864         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT13                0xFFCA486C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT14                0xFFCA4874         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT15                0xFFCA487C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT16                0xFFCA4884         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT17                0xFFCA488C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT18                0xFFCA4894         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT19                0xFFCA489C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT20                0xFFCA48A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT21                0xFFCA48AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT22                0xFFCA48B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT23                0xFFCA48BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT24                0xFFCA48C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT25                0xFFCA48CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT26                0xFFCA48D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT27                0xFFCA48DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT28                0xFFCA48E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT29                0xFFCA48EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT30                0xFFCA48F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT31                0xFFCA48FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT32                0xFFCA4904         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT33                0xFFCA490C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT34                0xFFCA4914         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT35                0xFFCA491C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT36                0xFFCA4924         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT37                0xFFCA492C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT38                0xFFCA4934         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT39                0xFFCA493C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT40                0xFFCA4944         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT41                0xFFCA494C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT42                0xFFCA4954         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT43                0xFFCA495C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT44                0xFFCA4964         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT45                0xFFCA496C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT46                0xFFCA4974         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT47                0xFFCA497C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT48                0xFFCA4984         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT49                0xFFCA498C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT50                0xFFCA4994         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT51                0xFFCA499C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT52                0xFFCA49A4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT53                0xFFCA49AC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT54                0xFFCA49B4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT55                0xFFCA49BC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT56                0xFFCA49C4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT57                0xFFCA49CC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT58                0xFFCA49D4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT59                0xFFCA49DC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT60                0xFFCA49E4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT61                0xFFCA49EC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT62                0xFFCA49F4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT63                0xFFCA49FC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT64                0xFFCA4A04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT65                0xFFCA4A0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT66                0xFFCA4A14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT67                0xFFCA4A1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT68                0xFFCA4A24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT69                0xFFCA4A2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT70                0xFFCA4A34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT71                0xFFCA4A3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT72                0xFFCA4A44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT73                0xFFCA4A4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT74                0xFFCA4A54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT75                0xFFCA4A5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT76                0xFFCA4A64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT77                0xFFCA4A6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT78                0xFFCA4A74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT79                0xFFCA4A7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT80                0xFFCA4A84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT81                0xFFCA4A8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT82                0xFFCA4A94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT83                0xFFCA4A9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT84                0xFFCA4AA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT85                0xFFCA4AAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT86                0xFFCA4AB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT87                0xFFCA4ABC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT88                0xFFCA4AC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT89                0xFFCA4ACC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT90                0xFFCA4AD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT91                0xFFCA4ADC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT92                0xFFCA4AE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT93                0xFFCA4AEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT94                0xFFCA4AF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT95                0xFFCA4AFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT96                0xFFCA4B04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT97                0xFFCA4B0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT98                0xFFCA4B14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT99                0xFFCA4B1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT100               0xFFCA4B24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT101               0xFFCA4B2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT102               0xFFCA4B34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT103               0xFFCA4B3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT104               0xFFCA4B44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT105               0xFFCA4B4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT106               0xFFCA4B54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT107               0xFFCA4B5C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT108               0xFFCA4B64         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT109               0xFFCA4B6C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT110               0xFFCA4B74         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT111               0xFFCA4B7C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT112               0xFFCA4B84         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT113               0xFFCA4B8C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT114               0xFFCA4B94         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT115               0xFFCA4B9C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT116               0xFFCA4BA4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT117               0xFFCA4BAC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT118               0xFFCA4BB4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT119               0xFFCA4BBC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT120               0xFFCA4BC4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT121               0xFFCA4BCC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT122               0xFFCA4BD4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT123               0xFFCA4BDC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT124               0xFFCA4BE4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT125               0xFFCA4BEC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT126               0xFFCA4BF4         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT127               0xFFCA4BFC         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT128               0xFFCA4C04         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT129               0xFFCA4C0C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT130               0xFFCA4C14         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT131               0xFFCA4C1C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT132               0xFFCA4C24         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT133               0xFFCA4C2C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT134               0xFFCA4C34         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT135               0xFFCA4C3C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT136               0xFFCA4C44         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT137               0xFFCA4C4C         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT138               0xFFCA4C54         /* SEC0 Source Status Register n */
-#define REG_SEC0_SSTAT139               0xFFCA4C5C         /* SEC0 Source Status Register n */
-
-/* =========================
-        SEC
-   ========================= */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_CCTL_NMIEN                  16                               /* NMI Enable */
-#define BITP_SEC_CCTL_WFI                    12                               /* Wait For Idle */
-#define BITP_SEC_CCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_CCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CCTL_NMIEN                  (_ADI_MSK(0x00010000,uint32_t))  /* NMI Enable */
-#define ENUM_SEC_CCTL_NMI_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* NMIEN: Disable */
-#define ENUM_SEC_CCTL_NMI_EN                 (_ADI_MSK(0x00010000,uint32_t))  /* NMIEN: Enable */
-
-#define BITM_SEC_CCTL_WFI                    (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CCTL_NO_WAITIDLE            (_ADI_MSK(0x00000000,uint32_t))  /* WFI: No Action */
-#define ENUM_SEC_CCTL_WAITIDLE               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Wait for Idle */
-
-#define BITM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_CCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_CCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_CCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_CCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSTAT_NMI                   16                               /* NMI */
-#define BITP_SEC_CSTAT_WFI                   12                               /* Wait For Idle */
-#define BITP_SEC_CSTAT_SIDV                  10                               /* SID Valid */
-#define BITP_SEC_CSTAT_ACTV                   9                               /* ACT Valid */
-#define BITP_SEC_CSTAT_PNDV                   8                               /* PND Valid */
-#define BITP_SEC_CSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_CSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI */
-#define ENUM_SEC_CSTAT_NO_NMI                (_ADI_MSK(0x00000000,uint32_t))  /* NMI: No NMI Occured */
-#define ENUM_SEC_CSTAT_NMI                   (_ADI_MSK(0x00010000,uint32_t))  /* NMI: NMI Occurred */
-
-#define BITM_SEC_CSTAT_WFI                   (_ADI_MSK(0x00001000,uint32_t))  /* Wait For Idle */
-#define ENUM_SEC_CSTAT_NOT_WAITING           (_ADI_MSK(0x00000000,uint32_t))  /* WFI: Not Waiting */
-#define ENUM_SEC_CSTAT_WAITING               (_ADI_MSK(0x00001000,uint32_t))  /* WFI: Waiting */
-
-#define BITM_SEC_CSTAT_SIDV                  (_ADI_MSK(0x00000400,uint32_t))  /* SID Valid */
-#define ENUM_SEC_CSTAT_INVALID_SID           (_ADI_MSK(0x00000000,uint32_t))  /* SIDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_SID             (_ADI_MSK(0x00000400,uint32_t))  /* SIDV: Valid */
-
-#define BITM_SEC_CSTAT_ACTV                  (_ADI_MSK(0x00000200,uint32_t))  /* ACT Valid */
-#define ENUM_SEC_CSTAT_INVALID_ACT           (_ADI_MSK(0x00000000,uint32_t))  /* ACTV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_ACT             (_ADI_MSK(0x00000200,uint32_t))  /* ACTV: Valid */
-
-#define BITM_SEC_CSTAT_PNDV                  (_ADI_MSK(0x00000100,uint32_t))  /* PND Valid */
-#define ENUM_SEC_CSTAT_INVALID_PND           (_ADI_MSK(0x00000000,uint32_t))  /* PNDV: Invalid */
-#define ENUM_SEC_CSTAT_VALID_PND             (_ADI_MSK(0x00000100,uint32_t))  /* PNDV: Valid */
-
-#define BITM_SEC_CSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_CSTAT_ACKERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: Acknowledge Error */
-
-#define BITM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_CSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_CSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPND_PRIO                    8                               /* Highest Pending IRQ Priority */
-#define BITP_SEC_CPND_SID                     0                               /* Highest Pending IRQ Source ID */
-#define BITM_SEC_CPND_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Pending IRQ Priority */
-#define BITM_SEC_CPND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Pending IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CACT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CACT_PRIO                    8                               /* Highest Active IRQ Priority */
-#define BITP_SEC_CACT_SID                     0                               /* Highest Active IRQ Source ID */
-#define BITM_SEC_CACT_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Highest Active IRQ Priority */
-#define BITM_SEC_CACT_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Highest Active IRQ Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPMSK_PRIO                   0                               /* IRQ Priority Mask */
-
-#define BITM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPMSK_PRIO                  (_ADI_MSK(0x000000FF,uint32_t))  /* IRQ Priority Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CGMSK                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CGMSK_LOCK                  31                               /* Lock */
-#define BITP_SEC_CGMSK_UGRP                   8                               /* Ungrouped Mask */
-#define BITP_SEC_CGMSK_GRP                    0                               /* Grouped Mask */
-
-#define BITM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CGMSK_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CGMSK_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_CGMSK_UGRP                  (_ADI_MSK(0x00000100,uint32_t))  /* Ungrouped Mask */
-#define ENUM_SEC_CGMSK_UNMASK                (_ADI_MSK(0x00000000,uint32_t))  /* UGRP: Unmask Ungrouped Sources */
-#define ENUM_SEC_CGMSK_MASK                  (_ADI_MSK(0x00000100,uint32_t))  /* UGRP: Mask Ungrouped Sources */
-#define BITM_SEC_CGMSK_GRP                   (_ADI_MSK(0x0000000F,uint32_t))  /* Grouped Mask */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CPLVL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CPLVL_LOCK                  31                               /* Lock */
-#define BITP_SEC_CPLVL_PLVL                   0                               /* Priority Levels */
-
-#define BITM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_CPLVL_UNLOCK                (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_CPLVL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_CPLVL_PLVL                  (_ADI_MSK(0x00000007,uint32_t))  /* Priority Levels */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_CSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_CSID_SID                     0                               /* Source ID */
-#define BITM_SEC_CSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_FCTL_TES                    13                               /* Trigger Event Select */
-#define BITP_SEC_FCTL_CMS                    12                               /* COP Mode Select */
-#define BITP_SEC_FCTL_FIEN                    7                               /* Fault Input Enable */
-#define BITP_SEC_FCTL_SREN                    6                               /* System Reset Enable */
-#define BITP_SEC_FCTL_TOEN                    5                               /* Trigger Output Enable */
-#define BITP_SEC_FCTL_FOEN                    4                               /* Fault Output Enable */
-#define BITP_SEC_FCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_FCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_FCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: UnLock */
-#define ENUM_SEC_FCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_FCTL_TES                    (_ADI_MSK(0x00002000,uint32_t))  /* Trigger Event Select */
-#define ENUM_SEC_FCTL_FLTACT_MODE            (_ADI_MSK(0x00000000,uint32_t))  /* TES: Fault Active Mode */
-#define ENUM_SEC_FCTL_FLTPND_MODE            (_ADI_MSK(0x00002000,uint32_t))  /* TES: Fault Pending Mode */
-
-#define BITM_SEC_FCTL_CMS                    (_ADI_MSK(0x00001000,uint32_t))  /* COP Mode Select */
-#define ENUM_SEC_FCTL_FLT_MODE               (_ADI_MSK(0x00000000,uint32_t))  /* CMS: Fault Mode */
-#define ENUM_SEC_FCTL_COP_MODE               (_ADI_MSK(0x00001000,uint32_t))  /* CMS: COP Mode */
-
-#define BITM_SEC_FCTL_FIEN                   (_ADI_MSK(0x00000080,uint32_t))  /* Fault Input Enable */
-#define ENUM_SEC_FCTL_FLTIN_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FIEN: Disable */
-#define ENUM_SEC_FCTL_FLTIN_EN               (_ADI_MSK(0x00000080,uint32_t))  /* FIEN: Enable */
-
-#define BITM_SEC_FCTL_SREN                   (_ADI_MSK(0x00000040,uint32_t))  /* System Reset Enable */
-#define ENUM_SEC_FCTL_SYSRST_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* SREN: Disable */
-#define ENUM_SEC_FCTL_SYSRST_EN              (_ADI_MSK(0x00000040,uint32_t))  /* SREN: Enable */
-
-#define BITM_SEC_FCTL_TOEN                   (_ADI_MSK(0x00000020,uint32_t))  /* Trigger Output Enable */
-#define ENUM_SEC_FCTL_TRGOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* TOEN: Disable */
-#define ENUM_SEC_FCTL_TRGOUT_EN              (_ADI_MSK(0x00000020,uint32_t))  /* TOEN: Enable */
-
-#define BITM_SEC_FCTL_FOEN                   (_ADI_MSK(0x00000010,uint32_t))  /* Fault Output Enable */
-#define ENUM_SEC_FCTL_FLTOUT_DIS             (_ADI_MSK(0x00000000,uint32_t))  /* FOEN: Disable */
-#define ENUM_SEC_FCTL_FLTOUT_EN              (_ADI_MSK(0x00000010,uint32_t))  /* FOEN: Enable */
-
-#define BITM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_FCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_FCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_FCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_FCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSTAT_NPND                  10                               /* Next Pending Fault */
-#define BITP_SEC_FSTAT_ACT                    9                               /* Fault Active */
-#define BITP_SEC_FSTAT_PND                    8                               /* Pending Fault */
-#define BITP_SEC_FSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_FSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_FSTAT_NPND                  (_ADI_MSK(0x00000400,uint32_t))  /* Next Pending Fault */
-#define ENUM_SEC_FSTAT_NO_NXTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* NPND: Not Pending */
-#define ENUM_SEC_FSTAT_NXTFLT                (_ADI_MSK(0x00000400,uint32_t))  /* NPND: Pending */
-
-#define BITM_SEC_FSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Fault Active */
-#define ENUM_SEC_FSTAT_NO_FLTACT             (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Fault */
-#define ENUM_SEC_FSTAT_FLTACT                (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Fault */
-
-#define BITM_SEC_FSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Fault */
-#define ENUM_SEC_FSTAT_NO_FLTPND             (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_FSTAT_FLTPND                (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_FSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_FSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_FSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_FSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FSID                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FSID_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FSID_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FSID_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FSID_SRC_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FSID_SRC_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FSID_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_FEND                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_FEND_FEXT                   16                               /* Fault External */
-#define BITP_SEC_FEND_SID                     0                               /* Source ID */
-
-#define BITM_SEC_FEND_FEXT                   (_ADI_MSK(0x00010000,uint32_t))  /* Fault External */
-#define ENUM_SEC_FEND_END_INTFLT             (_ADI_MSK(0x00000000,uint32_t))  /* FEXT: Fault Internal */
-#define ENUM_SEC_FEND_END_EXTFLT             (_ADI_MSK(0x00010000,uint32_t))  /* FEXT: Fault External */
-#define BITM_SEC_FEND_SID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_GCTL_RESET                   1                               /* Reset */
-#define BITP_SEC_GCTL_EN                      0                               /* Enable */
-
-#define BITM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_GCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Reset */
-#define ENUM_SEC_GCTL_NO_RESET               (_ADI_MSK(0x00000000,uint32_t))  /* RESET: No Action */
-#define ENUM_SEC_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* RESET: Reset */
-
-#define BITM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable */
-#define ENUM_SEC_GCTL_DIS                    (_ADI_MSK(0x00000000,uint32_t))  /* EN: Disable */
-#define ENUM_SEC_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* EN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_GSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_GSTAT_LWERR                 31                               /* Lock Write Error */
-#define BITP_SEC_GSTAT_ADRERR                30                               /* Address Error */
-#define BITP_SEC_GSTAT_SID                   16                               /* Source ID for SSI Error */
-#define BITP_SEC_GSTAT_SCI                    8                               /* SCI ID for SCI Error */
-#define BITP_SEC_GSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_GSTAT_ERR                    1                               /* Error */
-
-#define BITM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define ENUM_SEC_GSTAT_NO_LWERR              (_ADI_MSK(0x00000000,uint32_t))  /* LWERR: No Error */
-#define ENUM_SEC_GSTAT_LWERR                 (_ADI_MSK(0x80000000,uint32_t))  /* LWERR: Error Occurred */
-
-#define BITM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define ENUM_SEC_GSTAT_NO_ADRERR             (_ADI_MSK(0x00000000,uint32_t))  /* ADRERR: No Error */
-#define ENUM_SEC_GSTAT_ADRERR                (_ADI_MSK(0x40000000,uint32_t))  /* ADRERR: Error Occurred */
-#define BITM_SEC_GSTAT_SID                   (_ADI_MSK(0x00FF0000,uint32_t))  /* Source ID for SSI Error */
-#define BITM_SEC_GSTAT_SCI                   (_ADI_MSK(0x00000F00,uint32_t))  /* SCI ID for SCI Error */
-
-#define BITM_SEC_GSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_GSTAT_SFIERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: SFI Error */
-#define ENUM_SEC_GSTAT_SCIERR                (_ADI_MSK(0x00000010,uint32_t))  /* ERRC: SCI Error */
-#define ENUM_SEC_GSTAT_SSIERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: SSI Error */
-
-#define BITM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_GSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_GSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_RAISE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_RAISE_SID                    0                               /* Source ID IRQ Set to Pending */
-#define BITM_SEC_RAISE_SID                   (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ Set to Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_END                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_END_SID                      0                               /* Source ID IRQ to End */
-#define BITM_SEC_END_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* Source ID IRQ to End */
-
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SCTL_LOCK                   31                               /* Lock */
-#define BITP_SEC_SCTL_CTG                    24                               /* Core Target Select */
-#define BITP_SEC_SCTL_GRP                    16                               /* Group Select */
-#define BITP_SEC_SCTL_PRIO                    8                               /* Priority Level Select */
-#define BITP_SEC_SCTL_ERREN                   4                               /* Error Enable */
-#define BITP_SEC_SCTL_ES                      3                               /* Edge Select */
-#define BITP_SEC_SCTL_SEN                     2                               /* Source (signal) Enable */
-#define BITP_SEC_SCTL_FEN                     1                               /* Fault Enable */
-#define BITP_SEC_SCTL_IEN                     0                               /* Interrupt Enable */
-
-#define BITM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_SEC_SCTL_UNLOCK                 (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_SEC_SCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-#define BITM_SEC_SCTL_CTG                    (_ADI_MSK(0x0F000000,uint32_t))  /* Core Target Select */
-#define BITM_SEC_SCTL_GRP                    (_ADI_MSK(0x000F0000,uint32_t))  /* Group Select */
-#define BITM_SEC_SCTL_PRIO                   (_ADI_MSK(0x0000FF00,uint32_t))  /* Priority Level Select */
-
-#define BITM_SEC_SCTL_ERREN                  (_ADI_MSK(0x00000010,uint32_t))  /* Error Enable */
-#define ENUM_SEC_SCTL_ERR_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* ERREN: Disable */
-#define ENUM_SEC_SCTL_ERR_EN                 (_ADI_MSK(0x00000010,uint32_t))  /* ERREN: Enable */
-
-#define BITM_SEC_SCTL_ES                     (_ADI_MSK(0x00000008,uint32_t))  /* Edge Select */
-#define ENUM_SEC_SCTL_LEVEL                  (_ADI_MSK(0x00000000,uint32_t))  /* ES: Level Sensitive */
-#define ENUM_SEC_SCTL_EDGE                   (_ADI_MSK(0x00000008,uint32_t))  /* ES: Edge Sensitive */
-
-#define BITM_SEC_SCTL_SEN                    (_ADI_MSK(0x00000004,uint32_t))  /* Source (signal) Enable */
-#define ENUM_SEC_SCTL_SRC_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* SEN: Disable */
-#define ENUM_SEC_SCTL_SRC_EN                 (_ADI_MSK(0x00000004,uint32_t))  /* SEN: Enable */
-
-#define BITM_SEC_SCTL_FEN                    (_ADI_MSK(0x00000002,uint32_t))  /* Fault Enable */
-#define ENUM_SEC_SCTL_FAULT_DIS              (_ADI_MSK(0x00000000,uint32_t))  /* FEN: Disable */
-#define ENUM_SEC_SCTL_FAULT_EN               (_ADI_MSK(0x00000002,uint32_t))  /* FEN: Enable */
-
-#define BITM_SEC_SCTL_IEN                    (_ADI_MSK(0x00000001,uint32_t))  /* Interrupt Enable */
-#define ENUM_SEC_SCTL_INT_DIS                (_ADI_MSK(0x00000000,uint32_t))  /* IEN: Disable */
-#define ENUM_SEC_SCTL_INT_EN                 (_ADI_MSK(0x00000001,uint32_t))  /* IEN: Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SEC_SSTAT                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SEC_SSTAT_CHID                  16                               /* Channel ID */
-#define BITP_SEC_SSTAT_ACT                    9                               /* Active Source */
-#define BITP_SEC_SSTAT_PND                    8                               /* Pending Source */
-#define BITP_SEC_SSTAT_ERRC                   4                               /* Error Cause */
-#define BITP_SEC_SSTAT_ERR                    1                               /* Error */
-#define BITM_SEC_SSTAT_CHID                  (_ADI_MSK(0x00FF0000,uint32_t))  /* Channel ID */
-
-#define BITM_SEC_SSTAT_ACT                   (_ADI_MSK(0x00000200,uint32_t))  /* Active Source */
-#define ENUM_SEC_SSTAT_NO_SRC                (_ADI_MSK(0x00000000,uint32_t))  /* ACT: No Source */
-#define ENUM_SEC_SSTAT_ACTIVE_SRC            (_ADI_MSK(0x00000200,uint32_t))  /* ACT: Active Source */
-
-#define BITM_SEC_SSTAT_PND                   (_ADI_MSK(0x00000100,uint32_t))  /* Pending Source */
-#define ENUM_SEC_SSTAT_NOTPENDING            (_ADI_MSK(0x00000000,uint32_t))  /* PND: Not Pending */
-#define ENUM_SEC_SSTAT_PENDING               (_ADI_MSK(0x00000100,uint32_t))  /* PND: Pending */
-
-#define BITM_SEC_SSTAT_ERRC                  (_ADI_MSK(0x00000030,uint32_t))  /* Error Cause */
-#define ENUM_SEC_SSTAT_SOVFERR               (_ADI_MSK(0x00000000,uint32_t))  /* ERRC: Source Overflow Error */
-#define ENUM_SEC_SSTAT_ENDERR                (_ADI_MSK(0x00000020,uint32_t))  /* ERRC: End Error */
-
-#define BITM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* Error */
-#define ENUM_SEC_SSTAT_NO_ERR                (_ADI_MSK(0x00000000,uint32_t))  /* ERR: No Error */
-#define ENUM_SEC_SSTAT_ERR                   (_ADI_MSK(0x00000002,uint32_t))  /* ERR: Error Occurred */
-
-/* ==================================================
-        Trigger Routing Unit Registers
-   ================================================== */
-
-/* =========================
-        TRU0
-   ========================= */
-#define REG_TRU0_SSR0                   0xFFCA5000         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR1                   0xFFCA5004         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR2                   0xFFCA5008         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR3                   0xFFCA500C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR4                   0xFFCA5010         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR5                   0xFFCA5014         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR6                   0xFFCA5018         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR7                   0xFFCA501C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR8                   0xFFCA5020         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR9                   0xFFCA5024         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR10                  0xFFCA5028         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR11                  0xFFCA502C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR12                  0xFFCA5030         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR13                  0xFFCA5034         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR14                  0xFFCA5038         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR15                  0xFFCA503C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR16                  0xFFCA5040         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR17                  0xFFCA5044         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR18                  0xFFCA5048         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR19                  0xFFCA504C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR20                  0xFFCA5050         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR21                  0xFFCA5054         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR22                  0xFFCA5058         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR23                  0xFFCA505C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR24                  0xFFCA5060         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR25                  0xFFCA5064         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR26                  0xFFCA5068         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR27                  0xFFCA506C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR28                  0xFFCA5070         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR29                  0xFFCA5074         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR30                  0xFFCA5078         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR31                  0xFFCA507C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR32                  0xFFCA5080         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR33                  0xFFCA5084         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR34                  0xFFCA5088         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR35                  0xFFCA508C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR36                  0xFFCA5090         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR37                  0xFFCA5094         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR38                  0xFFCA5098         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR39                  0xFFCA509C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR40                  0xFFCA50A0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR41                  0xFFCA50A4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR42                  0xFFCA50A8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR43                  0xFFCA50AC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR44                  0xFFCA50B0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR45                  0xFFCA50B4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR46                  0xFFCA50B8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR47                  0xFFCA50BC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR48                  0xFFCA50C0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR49                  0xFFCA50C4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR50                  0xFFCA50C8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR51                  0xFFCA50CC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR52                  0xFFCA50D0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR53                  0xFFCA50D4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR54                  0xFFCA50D8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR55                  0xFFCA50DC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR56                  0xFFCA50E0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR57                  0xFFCA50E4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR58                  0xFFCA50E8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR59                  0xFFCA50EC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR60                  0xFFCA50F0         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR61                  0xFFCA50F4         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR62                  0xFFCA50F8         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR63                  0xFFCA50FC         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR64                  0xFFCA5100         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR65                  0xFFCA5104         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR66                  0xFFCA5108         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR67                  0xFFCA510C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR68                  0xFFCA5110         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR69                  0xFFCA5114         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR70                  0xFFCA5118         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR71                  0xFFCA511C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR72                  0xFFCA5120         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR73                  0xFFCA5124         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR74                  0xFFCA5128         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR75                  0xFFCA512C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR76                  0xFFCA5130         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR77                  0xFFCA5134         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR78                  0xFFCA5138         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR79                  0xFFCA513C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR80                  0xFFCA5140         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR81                  0xFFCA5144         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR82                  0xFFCA5148         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR83                  0xFFCA514C         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR84                  0xFFCA5150         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR85                  0xFFCA5154         /* TRU0 Slave Select Register */
-#define REG_TRU0_SSR86                  0xFFCA5158         /* TRU0 Slave Select Register */
-#define REG_TRU0_MTR                    0xFFCA57E0         /* TRU0 Master Trigger Register */
-#define REG_TRU0_ERRADDR                0xFFCA57E8         /* TRU0 Error Address Register */
-#define REG_TRU0_STAT                   0xFFCA57EC         /* TRU0 Status Information Register */
-#define REG_TRU0_REVID                  0xFFCA57F0         /* TRU0 Revision ID Register */
-#define REG_TRU0_GCTL                   0xFFCA57F4         /* TRU0 Global Control Register */
-
-/* =========================
-        TRU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_SSR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_SSR_LOCK                    31                               /* SSRn Lock */
-#define BITP_TRU_SSR_SSR                      0                               /* SSRn Slave Select */
-#define BITM_TRU_SSR_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* SSRn Lock */
-#define BITM_TRU_SSR_SSR                     (_ADI_MSK(0x000000FF,uint32_t))  /* SSRn Slave Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_MTR                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_MTR_MTR3                    24                               /* Master Trigger Register 3 */
-#define BITP_TRU_MTR_MTR2                    16                               /* Master Trigger Register 2 */
-#define BITP_TRU_MTR_MTR1                     8                               /* Master Trigger Register 1 */
-#define BITP_TRU_MTR_MTR0                     0                               /* Master Trigger Register 0 */
-#define BITM_TRU_MTR_MTR3                    (_ADI_MSK(0xFF000000,uint32_t))  /* Master Trigger Register 3 */
-#define BITM_TRU_MTR_MTR2                    (_ADI_MSK(0x00FF0000,uint32_t))  /* Master Trigger Register 2 */
-#define BITM_TRU_MTR_MTR1                    (_ADI_MSK(0x0000FF00,uint32_t))  /* Master Trigger Register 1 */
-#define BITM_TRU_MTR_MTR0                    (_ADI_MSK(0x000000FF,uint32_t))  /* Master Trigger Register 0 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_ERRADDR                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_ERRADDR_ADDR                 0                               /* Error Address */
-#define BITM_TRU_ERRADDR_ADDR                (_ADI_MSK(0x00000FFF,uint32_t))  /* Error Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_STAT_ADDRERR                 1                               /* Address Error Status */
-#define BITP_TRU_STAT_LWERR                   0                               /* Lock Write Error Status */
-#define BITM_TRU_STAT_ADDRERR                (_ADI_MSK(0x00000002,uint32_t))  /* Address Error Status */
-#define BITM_TRU_STAT_LWERR                  (_ADI_MSK(0x00000001,uint32_t))  /* Lock Write Error Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_REVID                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_REVID_MAJOR                  4                               /* Major Version ID */
-#define BITP_TRU_REVID_REV                    0                               /* Incremental Version ID */
-#define BITM_TRU_REVID_MAJOR                 (_ADI_MSK(0x000000F0,uint32_t))  /* Major Version ID */
-#define BITM_TRU_REVID_REV                   (_ADI_MSK(0x0000000F,uint32_t))  /* Incremental Version ID */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TRU_GCTL                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TRU_GCTL_LOCK                   31                               /* GCTL Lock Bit */
-#define BITP_TRU_GCTL_MTRL                    2                               /* MTR Lock Bit */
-#define BITP_TRU_GCTL_RESET                   1                               /* Soft Reset */
-#define BITP_TRU_GCTL_EN                      0                               /* Non-MMR Enable */
-#define BITM_TRU_GCTL_LOCK                   (_ADI_MSK(0x80000000,uint32_t))  /* GCTL Lock Bit */
-#define BITM_TRU_GCTL_MTRL                   (_ADI_MSK(0x00000004,uint32_t))  /* MTR Lock Bit */
-#define BITM_TRU_GCTL_RESET                  (_ADI_MSK(0x00000002,uint32_t))  /* Soft Reset */
-#define BITM_TRU_GCTL_EN                     (_ADI_MSK(0x00000001,uint32_t))  /* Non-MMR Enable */
-
-/* ==================================================
-        Reset Control Unit Registers
-   ================================================== */
-
-/* =========================
-        RCU0
-   ========================= */
-#define REG_RCU0_CTL                    0xFFCA6000         /* RCU0 Control Register */
-#define REG_RCU0_STAT                   0xFFCA6004         /* RCU0 Status Register */
-#define REG_RCU0_CRCTL                  0xFFCA6008         /* RCU0 Core Reset Control Register */
-#define REG_RCU0_CRSTAT                 0xFFCA600C         /* RCU0 Core Reset Status Register */
-#define REG_RCU0_SIDIS                  0xFFCA6010         /* RCU0 System Interface Disable Register */
-#define REG_RCU0_SISTAT                 0xFFCA6014         /* RCU0 System Interface Status Register */
-#define REG_RCU0_SVECT_LCK              0xFFCA6018         /* RCU0 SVECT Lock Register */
-#define REG_RCU0_BCODE                  0xFFCA601C         /* RCU0 Boot Code Register */
-#define REG_RCU0_SVECT0                 0xFFCA6020         /* RCU0 Software Vector Register n */
-#define REG_RCU0_SVECT1                 0xFFCA6024         /* RCU0 Software Vector Register n */
-
-/* =========================
-        RCU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CTL_LOCK                    31                               /* Lock */
-#define BITP_RCU_CTL_RSTOUTDSRT               2                               /* Reset Out Deassert */
-#define BITP_RCU_CTL_RSTOUTASRT               1                               /* Reset Out Assert */
-#define BITP_RCU_CTL_SYSRST                   0                               /* System Reset */
-#define BITM_RCU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CTL_RSTOUTDSRT              (_ADI_MSK(0x00000004,uint32_t))  /* Reset Out Deassert */
-#define BITM_RCU_CTL_RSTOUTASRT              (_ADI_MSK(0x00000002,uint32_t))  /* Reset Out Assert */
-#define BITM_RCU_CTL_SYSRST                  (_ADI_MSK(0x00000001,uint32_t))  /* System Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_STAT_RSTOUTERR              18                               /* Reset Out Error */
-#define BITP_RCU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_RCU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_RCU_STAT_BMODE                   8                               /* Boot Mode */
-#define BITP_RCU_STAT_RSTOUT                  5                               /* Reset Out Status */
-#define BITP_RCU_STAT_SWRST                   3                               /* Software Reset */
-#define BITP_RCU_STAT_SSRST                   2                               /* System Source Reset */
-#define BITP_RCU_STAT_HBRST                   1                               /* Hibernate Reset */
-#define BITP_RCU_STAT_HWRST                   0                               /* Hardware Reset */
-#define BITM_RCU_STAT_RSTOUTERR              (_ADI_MSK(0x00040000,uint32_t))  /* Reset Out Error */
-#define BITM_RCU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_RCU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_RCU_STAT_BMODE                  (_ADI_MSK(0x00000F00,uint32_t))  /* Boot Mode */
-#define BITM_RCU_STAT_RSTOUT                 (_ADI_MSK(0x00000020,uint32_t))  /* Reset Out Status */
-#define BITM_RCU_STAT_SWRST                  (_ADI_MSK(0x00000008,uint32_t))  /* Software Reset */
-#define BITM_RCU_STAT_SSRST                  (_ADI_MSK(0x00000004,uint32_t))  /* System Source Reset */
-#define BITM_RCU_STAT_HBRST                  (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Reset */
-#define BITM_RCU_STAT_HWRST                  (_ADI_MSK(0x00000001,uint32_t))  /* Hardware Reset */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRCTL                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRCTL_LOCK                  31                               /* Lock */
-#define BITP_RCU_CRCTL_CR0                    0                               /* Core Reset n */
-#define BITP_RCU_CRCTL_CR1                    1                               /* Core Reset n */
-#define BITM_RCU_CRCTL_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_CRCTL_CR0                   (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRCTL_CR1                   (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_CRSTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_CRSTAT_CR0                   0                               /* Core Reset n */
-#define BITP_RCU_CRSTAT_CR1                   1                               /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR0                  (_ADI_MSK(0x00000001,uint32_t))  /* Core Reset n */
-#define BITM_RCU_CRSTAT_CR1                  (_ADI_MSK(0x00000002,uint32_t))  /* Core Reset n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SIDIS                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SIDIS_LOCK                  31                               /* Lock */
-#define BITP_RCU_SIDIS_SI0                    0                               /* System Interface n */
-#define BITP_RCU_SIDIS_SI1                    1                               /* System Interface n */
-#define BITM_RCU_SIDIS_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SIDIS_SI0                   (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SIDIS_SI1                   (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SISTAT                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SISTAT_SI0                   0                               /* System Interface n */
-#define BITP_RCU_SISTAT_SI1                   1                               /* System Interface n */
-#define BITM_RCU_SISTAT_SI0                  (_ADI_MSK(0x00000001,uint32_t))  /* System Interface n */
-#define BITM_RCU_SISTAT_SI1                  (_ADI_MSK(0x00000002,uint32_t))  /* System Interface n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_SVECT_LCK                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_SVECT_LCK_LOCK              31                               /* Lock */
-#define BITP_RCU_SVECT_LCK_SVECT0             0                               /* Software Vector Register n */
-#define BITP_RCU_SVECT_LCK_SVECT1             1                               /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_SVECT_LCK_SVECT0            (_ADI_MSK(0x00000001,uint32_t))  /* Software Vector Register n */
-#define BITM_RCU_SVECT_LCK_SVECT1            (_ADI_MSK(0x00000002,uint32_t))  /* Software Vector Register n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        RCU_BCODE                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_RCU_BCODE_LOCK                  31                               /* Lock */
-#define BITP_RCU_BCODE_BCODE                  0                               /* Boot Code */
-#define BITM_RCU_BCODE_LOCK                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_RCU_BCODE_BCODE                 (_ADI_MSK(0x7FFFFFFF,uint32_t))  /* Boot Code */
-
-/* ==================================================
-        System Protection Unit Registers
-   ================================================== */
-
-/* =========================
-        SPU0
-   ========================= */
-#define REG_SPU0_CTL                    0xFFCA7000         /* SPU0 Control Register */
-#define REG_SPU0_STAT                   0xFFCA7004         /* SPU0 Status Register */
-#define REG_SPU0_WP0                    0xFFCA7400         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP1                    0xFFCA7404         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP2                    0xFFCA7408         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP3                    0xFFCA740C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP4                    0xFFCA7410         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP5                    0xFFCA7414         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP6                    0xFFCA7418         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP7                    0xFFCA741C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP8                    0xFFCA7420         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP9                    0xFFCA7424         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP10                   0xFFCA7428         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP11                   0xFFCA742C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP12                   0xFFCA7430         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP13                   0xFFCA7434         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP14                   0xFFCA7438         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP15                   0xFFCA743C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP16                   0xFFCA7440         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP17                   0xFFCA7444         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP18                   0xFFCA7448         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP19                   0xFFCA744C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP20                   0xFFCA7450         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP21                   0xFFCA7454         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP22                   0xFFCA7458         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP23                   0xFFCA745C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP24                   0xFFCA7460         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP25                   0xFFCA7464         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP26                   0xFFCA7468         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP27                   0xFFCA746C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP28                   0xFFCA7470         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP29                   0xFFCA7474         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP30                   0xFFCA7478         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP31                   0xFFCA747C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP32                   0xFFCA7480         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP33                   0xFFCA7484         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP34                   0xFFCA7488         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP35                   0xFFCA748C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP36                   0xFFCA7490         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP37                   0xFFCA7494         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP38                   0xFFCA7498         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP39                   0xFFCA749C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP40                   0xFFCA74A0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP41                   0xFFCA74A4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP42                   0xFFCA74A8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP43                   0xFFCA74AC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP44                   0xFFCA74B0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP45                   0xFFCA74B4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP46                   0xFFCA74B8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP47                   0xFFCA74BC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP48                   0xFFCA74C0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP49                   0xFFCA74C4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP50                   0xFFCA74C8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP51                   0xFFCA74CC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP52                   0xFFCA74D0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP53                   0xFFCA74D4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP54                   0xFFCA74D8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP55                   0xFFCA74DC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP56                   0xFFCA74E0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP57                   0xFFCA74E4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP58                   0xFFCA74E8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP59                   0xFFCA74EC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP60                   0xFFCA74F0         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP61                   0xFFCA74F4         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP62                   0xFFCA74F8         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP63                   0xFFCA74FC         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP64                   0xFFCA7500         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP65                   0xFFCA7504         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP66                   0xFFCA7508         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP67                   0xFFCA750C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP68                   0xFFCA7510         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP69                   0xFFCA7514         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP70                   0xFFCA7518         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP71                   0xFFCA751C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP72                   0xFFCA7520         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP73                   0xFFCA7524         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP74                   0xFFCA7528         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP75                   0xFFCA752C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP76                   0xFFCA7530         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP77                   0xFFCA7534         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP78                   0xFFCA7538         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP79                   0xFFCA753C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP80                   0xFFCA7540         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP81                   0xFFCA7544         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP82                   0xFFCA7548         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP83                   0xFFCA754C         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP84                   0xFFCA7550         /* SPU0 Write Protect Register n */
-#define REG_SPU0_WP85                   0xFFCA7554         /* SPU0 Write Protect Register n */
-
-/* =========================
-        SPU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_CTL_WPLCK                   16                               /* Write Protect Register Lock */
-#define BITP_SPU_CTL_GLCK                     0                               /* Global Lock Disable */
-#define BITM_SPU_CTL_WPLCK                   (_ADI_MSK(0x00010000,uint32_t))  /* Write Protect Register Lock */
-#define BITM_SPU_CTL_GLCK                    (_ADI_MSK(0x000000FF,uint32_t))  /* Global Lock Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_STAT_LWERR                  31                               /* Lock Write Error */
-#define BITP_SPU_STAT_ADDRERR                30                               /* Address Error */
-#define BITP_SPU_STAT_GLCK                    0                               /* Global Lock Status */
-#define BITM_SPU_STAT_LWERR                  (_ADI_MSK(0x80000000,uint32_t))  /* Lock Write Error */
-#define BITM_SPU_STAT_ADDRERR                (_ADI_MSK(0x40000000,uint32_t))  /* Address Error */
-#define BITM_SPU_STAT_GLCK                   (_ADI_MSK(0x00000001,uint32_t))  /* Global Lock Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        SPU_WP                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SPU_WP_SM0                      16                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_SM1                      17                               /* System Master x Write Protect Enable */
-#define BITP_SPU_WP_CM0                       0                               /* Core Master x Write Protect Enable */
-#define BITP_SPU_WP_CM1                       1                               /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_SM0                      (_ADI_MSK(0x00010000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_SM1                      (_ADI_MSK(0x00020000,uint32_t))  /* System Master x Write Protect Enable */
-#define BITM_SPU_WP_CM0                      (_ADI_MSK(0x00000001,uint32_t))  /* Core Master x Write Protect Enable */
-#define BITM_SPU_WP_CM1                      (_ADI_MSK(0x00000002,uint32_t))  /* Core Master x Write Protect Enable */
-
-/* ==================================================
-        Clock Generation Unit Registers
-   ================================================== */
-
-/* =========================
-        CGU0
-   ========================= */
-#define REG_CGU0_CTL                    0xFFCA8000         /* CGU0 Control Register */
-#define REG_CGU0_STAT                   0xFFCA8004         /* CGU0 Status Register */
-#define REG_CGU0_DIV                    0xFFCA8008         /* CGU0 Divisor Register */
-#define REG_CGU0_CLKOUTSEL              0xFFCA800C         /* CGU0 CLKOUT Select Register */
-
-/* =========================
-        CGU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CTL_LOCK                    31                               /* Lock */
-#define BITP_CGU_CTL_WFI                     30                               /* Wait For Idle */
-#define BITP_CGU_CTL_MSEL                     8                               /* Multiplier Select */
-#define BITP_CGU_CTL_DF                       0                               /* Divide Frequency */
-#define BITM_CGU_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_CTL_WFI                     (_ADI_MSK(0x40000000,uint32_t))  /* Wait For Idle */
-
-#define BITM_CGU_CTL_MSEL                    (_ADI_MSK(0x00007F00,uint32_t))  /* Multiplier Select */
-#define ENUM_CGU_CTL_MSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* MSEL: MSEL = 1 to 127 */
-#define BITM_CGU_CTL_DF                      (_ADI_MSK(0x00000001,uint32_t))  /* Divide Frequency */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_STAT_PLOCKERR               21                               /* PLL Lock Error */
-#define BITP_CGU_STAT_WDIVERR                20                               /* Write to DIV Error */
-#define BITP_CGU_STAT_WDFMSERR               19                               /* Write to DF or MSEL Error */
-#define BITP_CGU_STAT_DIVERR                 18                               /* DIV Error */
-#define BITP_CGU_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_CGU_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_CGU_STAT_OCBF                    9                               /* OUTCLK Buffer Status */
-#define BITP_CGU_STAT_DCBF                    8                               /* DCLK Buffer Status */
-#define BITP_CGU_STAT_SCBF1                   7                               /* SCLK1 Buffer Status */
-#define BITP_CGU_STAT_SCBF0                   6                               /* SCLK0 Buffer Status */
-#define BITP_CGU_STAT_CCBF1                   5                               /* CCLK1 Buffer Status */
-#define BITP_CGU_STAT_CCBF0                   4                               /* CCLK0 Buffer Status */
-#define BITP_CGU_STAT_CLKSALGN                3                               /* Clock Alignment */
-#define BITP_CGU_STAT_PLOCK                   2                               /* PLL Lock */
-#define BITP_CGU_STAT_PLLBP                   1                               /* PLL Bypass */
-#define BITP_CGU_STAT_PLLEN                   0                               /* PLL Enable */
-#define BITM_CGU_STAT_PLOCKERR               (_ADI_MSK(0x00200000,uint32_t))  /* PLL Lock Error */
-#define BITM_CGU_STAT_WDIVERR                (_ADI_MSK(0x00100000,uint32_t))  /* Write to DIV Error */
-#define BITM_CGU_STAT_WDFMSERR               (_ADI_MSK(0x00080000,uint32_t))  /* Write to DF or MSEL Error */
-#define BITM_CGU_STAT_DIVERR                 (_ADI_MSK(0x00040000,uint32_t))  /* DIV Error */
-#define BITM_CGU_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_CGU_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_CGU_STAT_OCBF                   (_ADI_MSK(0x00000200,uint32_t))  /* OUTCLK Buffer Status */
-#define BITM_CGU_STAT_DCBF                   (_ADI_MSK(0x00000100,uint32_t))  /* DCLK Buffer Status */
-#define BITM_CGU_STAT_SCBF1                  (_ADI_MSK(0x00000080,uint32_t))  /* SCLK1 Buffer Status */
-#define BITM_CGU_STAT_SCBF0                  (_ADI_MSK(0x00000040,uint32_t))  /* SCLK0 Buffer Status */
-#define BITM_CGU_STAT_CCBF1                  (_ADI_MSK(0x00000020,uint32_t))  /* CCLK1 Buffer Status */
-#define BITM_CGU_STAT_CCBF0                  (_ADI_MSK(0x00000010,uint32_t))  /* CCLK0 Buffer Status */
-#define BITM_CGU_STAT_CLKSALGN               (_ADI_MSK(0x00000008,uint32_t))  /* Clock Alignment */
-#define BITM_CGU_STAT_PLOCK                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Lock */
-#define BITM_CGU_STAT_PLLBP                  (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass */
-#define BITM_CGU_STAT_PLLEN                  (_ADI_MSK(0x00000001,uint32_t))  /* PLL Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_DIV                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_DIV_LOCK                    31                               /* Lock */
-#define BITP_CGU_DIV_UPDT                    30                               /* Update Clock Divisors */
-#define BITP_CGU_DIV_ALGN                    29                               /* Align */
-#define BITP_CGU_DIV_OSEL                    22                               /* OUTCLK Divisor */
-#define BITP_CGU_DIV_DSEL                    16                               /* DCLK Divisor */
-#define BITP_CGU_DIV_S1SEL                   13                               /* SCLK 1 Divisor */
-#define BITP_CGU_DIV_SYSSEL                   8                               /* SYSCLK Divisor */
-#define BITP_CGU_DIV_S0SEL                    5                               /* SCLK 0 Divisor */
-#define BITP_CGU_DIV_CSEL                     0                               /* CCLK Divisor */
-#define BITM_CGU_DIV_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_CGU_DIV_UPDT                    (_ADI_MSK(0x40000000,uint32_t))  /* Update Clock Divisors */
-#define BITM_CGU_DIV_ALGN                    (_ADI_MSK(0x20000000,uint32_t))  /* Align */
-
-#define BITM_CGU_DIV_OSEL                    (_ADI_MSK(0x1FC00000,uint32_t))  /* OUTCLK Divisor */
-#define ENUM_CGU_DIV_OSEL1TO127              (_ADI_MSK(0x00000000,uint32_t))  /* OSEL: OSEL = 1 to 127 */
-
-#define BITM_CGU_DIV_DSEL                    (_ADI_MSK(0x001F0000,uint32_t))  /* DCLK Divisor */
-#define ENUM_CGU_DIV_DSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* DSEL: DSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S1SEL                   (_ADI_MSK(0x0000E000,uint32_t))  /* SCLK 1 Divisor */
-#define ENUM_CGU_DIV_S1SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S1SEL: S1SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_SYSSEL                  (_ADI_MSK(0x00001F00,uint32_t))  /* SYSCLK Divisor */
-#define ENUM_CGU_DIV_SYSSEL1TO31             (_ADI_MSK(0x00000000,uint32_t))  /* SYSSEL: SYSSEL = 1 to 31 */
-
-#define BITM_CGU_DIV_S0SEL                   (_ADI_MSK(0x000000E0,uint32_t))  /* SCLK 0 Divisor */
-#define ENUM_CGU_DIV_S0SEL1TO7               (_ADI_MSK(0x00000000,uint32_t))  /* S0SEL: S0SEL = 1 to 7 */
-
-#define BITM_CGU_DIV_CSEL                    (_ADI_MSK(0x0000001F,uint32_t))  /* CCLK Divisor */
-#define ENUM_CGU_DIV_CSEL1TO31               (_ADI_MSK(0x00000000,uint32_t))  /* CSEL: CSEL= 1 to 31 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CGU_CLKOUTSEL                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CGU_CLKOUTSEL_LOCK              31                               /* Lock */
-#define BITP_CGU_CLKOUTSEL_CLKOUTSEL          0                               /* CLKOUT Select */
-
-#define BITM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define ENUM_CGU_CLKOUTSEL_UNLOCK            (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Unlock */
-#define ENUM_CGU_CLKOUTSEL_LOCK              (_ADI_MSK(0x80000000,uint32_t))  /* LOCK: Lock */
-
-#define BITM_CGU_CLKOUTSEL_CLKOUTSEL         (_ADI_MSK(0x0000000F,uint32_t))  /* CLKOUT Select */
-#define ENUM_CGU_CLKOUTSEL_CLKIN             (_ADI_MSK(0x00000000,uint32_t))  /* CLKOUTSEL: CLKIN */
-#define ENUM_CGU_CLKOUTSEL_CCLKDIV4          (_ADI_MSK(0x00000001,uint32_t))  /* CLKOUTSEL: CCLKn/4 */
-#define ENUM_CGU_CLKOUTSEL_GNDDIS            (_ADI_MSK(0x0000000B,uint32_t))  /* CLKOUTSEL: GND (Disable OUTCLK) */
-#define ENUM_CGU_CLKOUTSEL_SYSCLKDIV2        (_ADI_MSK(0x00000002,uint32_t))  /* CLKOUTSEL: SYSCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_SCLK0             (_ADI_MSK(0x00000003,uint32_t))  /* CLKOUTSEL: SCLK0 */
-#define ENUM_CGU_CLKOUTSEL_SCLK1             (_ADI_MSK(0x00000004,uint32_t))  /* CLKOUTSEL: SCLK1 */
-#define ENUM_CGU_CLKOUTSEL_DCLKDIV2          (_ADI_MSK(0x00000005,uint32_t))  /* CLKOUTSEL: DCLK/2 */
-#define ENUM_CGU_CLKOUTSEL_OUTCLK            (_ADI_MSK(0x00000007,uint32_t))  /* CLKOUTSEL: OUTCLK */
-
-/* ==================================================
-        Dynamic Power Management Registers
-   ================================================== */
-
-/* =========================
-        DPM0
-   ========================= */
-#define REG_DPM0_CTL                    0xFFCA9000         /* DPM0 Control Register */
-#define REG_DPM0_STAT                   0xFFCA9004         /* DPM0 Status Register */
-#define REG_DPM0_CCBF_DIS               0xFFCA9008         /* DPM0 Core Clock Buffer Disable Register */
-#define REG_DPM0_CCBF_EN                0xFFCA900C         /* DPM0 Core Clock Buffer Enable Register */
-#define REG_DPM0_CCBF_STAT              0xFFCA9010         /* DPM0 Core Clock Buffer Status Register */
-#define REG_DPM0_CCBF_STAT_STKY         0xFFCA9014         /* DPM0 Core Clock Buffer Status Sticky Register */
-#define REG_DPM0_SCBF_DIS               0xFFCA9018         /* DPM0 System Clock Buffer Disable Register */
-#define REG_DPM0_WAKE_EN                0xFFCA901C         /* DPM0 Wakeup Enable Register */
-#define REG_DPM0_WAKE_POL               0xFFCA9020         /* DPM0 Wakeup Polarity Register */
-#define REG_DPM0_WAKE_STAT              0xFFCA9024         /* DPM0 Wakeup Status Register */
-#define REG_DPM0_HIB_DIS                0xFFCA9028         /* DPM0 Hibernate Disable Register */
-#define REG_DPM0_PGCNTR                 0xFFCA902C         /* DPM0 Power Good Counter Register */
-#define REG_DPM0_RESTORE0               0xFFCA9030         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE1               0xFFCA9034         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE2               0xFFCA9038         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE3               0xFFCA903C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE4               0xFFCA9040         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE5               0xFFCA9044         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE6               0xFFCA9048         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE7               0xFFCA904C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE8               0xFFCA9050         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE9               0xFFCA9054         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE10              0xFFCA9058         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE11              0xFFCA905C         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE12              0xFFCA9060         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE13              0xFFCA9064         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE14              0xFFCA9068         /* DPM0 Restore n Register */
-#define REG_DPM0_RESTORE15              0xFFCA906C         /* DPM0 Restore n Register */
-
-/* =========================
-        DPM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CTL_LOCK                    31                               /* Lock */
-#define BITP_DPM_CTL_HIBERNATE                4                               /* Hibernate */
-#define BITP_DPM_CTL_DEEPSLEEP                3                               /* Deep Sleep */
-#define BITP_DPM_CTL_PLLDIS                   2                               /* PLL Disable */
-#define BITP_DPM_CTL_PLLBPCL                  1                               /* PLL Bypass Clear */
-#define BITP_DPM_CTL_PLLBPST                  0                               /* PLL Bypass Set */
-#define BITM_DPM_CTL_LOCK                    (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CTL_HIBERNATE               (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate */
-#define BITM_DPM_CTL_DEEPSLEEP               (_ADI_MSK(0x00000008,uint32_t))  /* Deep Sleep */
-#define BITM_DPM_CTL_PLLDIS                  (_ADI_MSK(0x00000004,uint32_t))  /* PLL Disable */
-#define BITM_DPM_CTL_PLLBPCL                 (_ADI_MSK(0x00000002,uint32_t))  /* PLL Bypass Clear */
-#define BITM_DPM_CTL_PLLBPST                 (_ADI_MSK(0x00000001,uint32_t))  /* PLL Bypass Set */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_STAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_STAT_PLLCFGERR              19                               /* PLL Configuration Error */
-#define BITP_DPM_STAT_HVBSYERR               18                               /* HV Busy Error */
-#define BITP_DPM_STAT_LWERR                  17                               /* Lock Write Error */
-#define BITP_DPM_STAT_ADDRERR                16                               /* Address Error */
-#define BITP_DPM_STAT_HVBSY                   9                               /* HV Busy */
-#define BITP_DPM_STAT_CCLKDIS                 8                               /* Core Clock(s) Disabled */
-#define BITP_DPM_STAT_PRVMODE                 4                               /* Previous Mode */
-#define BITP_DPM_STAT_CURMODE                 0                               /* Current Mode */
-#define BITM_DPM_STAT_PLLCFGERR              (_ADI_MSK(0x00080000,uint32_t))  /* PLL Configuration Error */
-#define BITM_DPM_STAT_HVBSYERR               (_ADI_MSK(0x00040000,uint32_t))  /* HV Busy Error */
-#define BITM_DPM_STAT_LWERR                  (_ADI_MSK(0x00020000,uint32_t))  /* Lock Write Error */
-#define BITM_DPM_STAT_ADDRERR                (_ADI_MSK(0x00010000,uint32_t))  /* Address Error */
-#define BITM_DPM_STAT_HVBSY                  (_ADI_MSK(0x00000200,uint32_t))  /* HV Busy */
-#define BITM_DPM_STAT_CCLKDIS                (_ADI_MSK(0x00000100,uint32_t))  /* Core Clock(s) Disabled */
-#define BITM_DPM_STAT_PRVMODE                (_ADI_MSK(0x000000F0,uint32_t))  /* Previous Mode */
-#define BITM_DPM_STAT_CURMODE                (_ADI_MSK(0x0000000F,uint32_t))  /* Current Mode */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_CCBF_DIS_CCBF0               0                               /* Core Clock Buffer n Disable */
-#define BITP_DPM_CCBF_DIS_CCBF1               1                               /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_DIS_CCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Disable */
-#define BITM_DPM_CCBF_DIS_CCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_CCBF_EN_CCBF0                0                               /* Core Clock Buffer n Enable */
-#define BITP_DPM_CCBF_EN_CCBF1                1                               /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_CCBF_EN_CCBF0               (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Enable */
-#define BITM_DPM_CCBF_EN_CCBF1               (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_CCBF0              0                               /* Core Clock Buffer n Status */
-#define BITP_DPM_CCBF_STAT_CCBF1              1                               /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF0             (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status */
-#define BITM_DPM_CCBF_STAT_CCBF1             (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_CCBF_STAT_STKY                   Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF0         0                               /* Core Clock Buffer n Status - Sticky */
-#define BITP_DPM_CCBF_STAT_STKY_CCBF1         1                               /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF0        (_ADI_MSK(0x00000001,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-#define BITM_DPM_CCBF_STAT_STKY_CCBF1        (_ADI_MSK(0x00000002,uint32_t))  /* Core Clock Buffer n Status - Sticky */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_SCBF_DIS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_SCBF_DIS_LOCK               31                               /* Lock */
-#define BITP_DPM_SCBF_DIS_SCBF0               0                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF1               1                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF2               2                               /* System Clock Buffer n Disable */
-#define BITP_DPM_SCBF_DIS_SCBF3               3                               /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_SCBF_DIS_SCBF0              (_ADI_MSK(0x00000001,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF1              (_ADI_MSK(0x00000002,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF2              (_ADI_MSK(0x00000004,uint32_t))  /* System Clock Buffer n Disable */
-#define BITM_DPM_SCBF_DIS_SCBF3              (_ADI_MSK(0x00000008,uint32_t))  /* System Clock Buffer n Disable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_EN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_EN_LOCK                31                               /* Lock */
-#define BITP_DPM_WAKE_EN_WS0                  0                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS1                  1                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS2                  2                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS3                  3                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS4                  4                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS5                  5                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS6                  6                               /* Wakeup Source n Enable */
-#define BITP_DPM_WAKE_EN_WS7                  7                               /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_EN_WS0                 (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS1                 (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS2                 (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS3                 (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS4                 (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS5                 (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS6                 (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Enable */
-#define BITM_DPM_WAKE_EN_WS7                 (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_POL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_POL_LOCK               31                               /* Lock */
-#define BITP_DPM_WAKE_POL_WS0                 0                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS1                 1                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS2                 2                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS3                 3                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS4                 4                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS5                 5                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS6                 6                               /* Wakeup Source n Polarity */
-#define BITP_DPM_WAKE_POL_WS7                 7                               /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_LOCK               (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_WAKE_POL_WS0                (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS1                (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS2                (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS3                (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS4                (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS5                (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS6                (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Polarity */
-#define BITM_DPM_WAKE_POL_WS7                (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Polarity */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_WAKE_STAT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_WAKE_STAT_WS0                0                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS1                1                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS2                2                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS3                3                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS4                4                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS5                5                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS6                6                               /* Wakeup Source n Status */
-#define BITP_DPM_WAKE_STAT_WS7                7                               /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS0               (_ADI_MSK(0x00000001,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS1               (_ADI_MSK(0x00000002,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS2               (_ADI_MSK(0x00000004,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS3               (_ADI_MSK(0x00000008,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS4               (_ADI_MSK(0x00000010,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS5               (_ADI_MSK(0x00000020,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS6               (_ADI_MSK(0x00000040,uint32_t))  /* Wakeup Source n Status */
-#define BITM_DPM_WAKE_STAT_WS7               (_ADI_MSK(0x00000080,uint32_t))  /* Wakeup Source n Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_HIB_DIS                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_HIB_DIS_LOCK                31                               /* Lock */
-#define BITP_DPM_HIB_DIS_HD0                  0                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD1                  1                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD2                  2                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD3                  3                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD4                  4                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD5                  5                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD6                  6                               /* Hibernate Disable n */
-#define BITP_DPM_HIB_DIS_HD7                  7                               /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_LOCK                (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_HIB_DIS_HD0                 (_ADI_MSK(0x00000001,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD1                 (_ADI_MSK(0x00000002,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD2                 (_ADI_MSK(0x00000004,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD3                 (_ADI_MSK(0x00000008,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD4                 (_ADI_MSK(0x00000010,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD5                 (_ADI_MSK(0x00000020,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD6                 (_ADI_MSK(0x00000040,uint32_t))  /* Hibernate Disable n */
-#define BITM_DPM_HIB_DIS_HD7                 (_ADI_MSK(0x00000080,uint32_t))  /* Hibernate Disable n */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DPM_PGCNTR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DPM_PGCNTR_LOCK                 31                               /* Lock */
-#define BITP_DPM_PGCNTR_CNT                   0                               /* Power Good Count */
-#define BITM_DPM_PGCNTR_LOCK                 (_ADI_MSK(0x80000000,uint32_t))  /* Lock */
-#define BITM_DPM_PGCNTR_CNT                  (_ADI_MSK(0x0000FFFF,uint32_t))  /* Power Good Count */
-
-/* ==================================================
-        eFUSE Controller Registers
-   ================================================== */
-
-/* =========================
-        EFS0
-   ========================= */
-#define REG_EFS0_CTL                    0xFFCC0000         /* EFS0 Control Register */
-#define REG_EFS0_DAT0                   0xFFCC0008         /* EFS0 Data Register 0 */
-#define REG_EFS0_DAT1                   0xFFCC000C         /* EFS0 Data Register 1 */
-#define REG_EFS0_DAT2                   0xFFCC0010         /* EFS0 Data Register 2 */
-#define REG_EFS0_DAT3                   0xFFCC0014         /* EFS0 Data Register 3 */
-#define REG_EFS0_DAT4                   0xFFCC0018         /* EFS0 Data Register 4 */
-#define REG_EFS0_DAT5                   0xFFCC001C         /* EFS0 Data Register 5 */
-#define REG_EFS0_DAT6                   0xFFCC0020         /* EFS0 Data Register 6 */
-#define REG_EFS0_DAT7                   0xFFCC0024         /* EFS0 Data Register 7 */
-
-/* =========================
-        EFS
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        EFS_CTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_EFS_CTL_READ                     0                               /* Read */
-#define BITM_EFS_CTL_READ                    (_ADI_MSK(0x00000001,uint32_t))  /* Read */
-
-/* ==================================================
-        Universal Serial Bus Controller Registers
-   ================================================== */
-
-/* =========================
-        USB0
-   ========================= */
-#define REG_USB0_FADDR                  0xFFCC1000         /* USB0 Function Address Register */
-#define REG_USB0_POWER                  0xFFCC1001         /* USB0 Power and Device Control Register */
-#define REG_USB0_INTRTX                 0xFFCC1002         /* USB0 Transmit Interrupt Register */
-#define REG_USB0_INTRRX                 0xFFCC1004         /* USB0 Receive Interrupt Register */
-#define REG_USB0_INTRTXE                0xFFCC1006         /* USB0 Transmit Interrupt Enable Register */
-#define REG_USB0_INTRRXE                0xFFCC1008         /* USB0 Receive Interrupt Enable Register */
-#define REG_USB0_IRQ                    0xFFCC100A         /* USB0 Common Interrupts Register */
-#define REG_USB0_IEN                    0xFFCC100B         /* USB0 Common Interrupts Enable Register */
-#define REG_USB0_FRAME                  0xFFCC100C         /* USB0 Frame Number Register */
-#define REG_USB0_INDEX                  0xFFCC100E         /* USB0 Index Register */
-#define REG_USB0_TESTMODE               0xFFCC100F         /* USB0 Testmode Register */
-#define REG_USB0_EPI_TXMAXP0            0xFFCC1010         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EPI_TXCSR_P0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EPI_TXCSR_H0           0xFFCC1012         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0I_CSR0_P            0xFFCC1012         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CSR0_H            0xFFCC1012         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXMAXP0            0xFFCC1014         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EPI_RXCSR_H0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EPI_RXCSR_P0           0xFFCC1016         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0I_CNT0              0xFFCC1018         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EPI_RXCNT0             0xFFCC1018         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EPI_TXTYPE0            0xFFCC101A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0I_TYPE0             0xFFCC101A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EPI_TXINTERVAL0        0xFFCC101B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0I_NAKLIMIT0         0xFFCC101B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EPI_RXTYPE0            0xFFCC101C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EPI_RXINTERVAL0        0xFFCC101D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0I_CFGDATA0          0xFFCC101F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_FIFOB0                 0xFFCC1020         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB1                 0xFFCC1024         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB2                 0xFFCC1028         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB3                 0xFFCC102C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB4                 0xFFCC1030         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB5                 0xFFCC1034         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB6                 0xFFCC1038         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB7                 0xFFCC103C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB8                 0xFFCC1040         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB9                 0xFFCC1044         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB10                0xFFCC1048         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOB11                0xFFCC104C         /* USB0 FIFO Byte (8-Bit) Register */
-#define REG_USB0_FIFOH0                 0xFFCC1020         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH1                 0xFFCC1024         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH2                 0xFFCC1028         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH3                 0xFFCC102C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH4                 0xFFCC1030         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH5                 0xFFCC1034         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH6                 0xFFCC1038         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH7                 0xFFCC103C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH8                 0xFFCC1040         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH9                 0xFFCC1044         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH10                0xFFCC1048         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFOH11                0xFFCC104C         /* USB0 FIFO Half-Word (16-Bit) Register */
-#define REG_USB0_FIFO0                  0xFFCC1020         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO1                  0xFFCC1024         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO2                  0xFFCC1028         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO3                  0xFFCC102C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO4                  0xFFCC1030         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO5                  0xFFCC1034         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO6                  0xFFCC1038         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO7                  0xFFCC103C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO8                  0xFFCC1040         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO9                  0xFFCC1044         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO10                 0xFFCC1048         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_FIFO11                 0xFFCC104C         /* USB0 FIFO Word (32-Bit) Register */
-#define REG_USB0_DEV_CTL                0xFFCC1060         /* USB0 Device Control Register */
-#define REG_USB0_TXFIFOSZ               0xFFCC1062         /* USB0 Transmit FIFO Size Register */
-#define REG_USB0_RXFIFOSZ               0xFFCC1063         /* USB0 Receive FIFO Size Register */
-#define REG_USB0_TXFIFOADDR             0xFFCC1064         /* USB0 Transmit FIFO Address Register */
-#define REG_USB0_RXFIFOADDR             0xFFCC1066         /* USB0 Receive FIFO Address Register */
-#define REG_USB0_EPINFO                 0xFFCC1078         /* USB0 Endpoint Information Register */
-#define REG_USB0_RAMINFO                0xFFCC1079         /* USB0 RAM Information Register */
-#define REG_USB0_LINKINFO               0xFFCC107A         /* USB0 Link Information Register */
-#define REG_USB0_VPLEN                  0xFFCC107B         /* USB0 VBUS Pulse Length Register */
-#define REG_USB0_HS_EOF1                0xFFCC107C         /* USB0 High-Speed EOF 1 Register */
-#define REG_USB0_FS_EOF1                0xFFCC107D         /* USB0 Full-Speed EOF 1 Register */
-#define REG_USB0_LS_EOF1                0xFFCC107E         /* USB0 Low-Speed EOF 1 Register */
-#define REG_USB0_SOFT_RST               0xFFCC107F         /* USB0 Software Reset Register */
-#define REG_USB0_MP0_TXFUNCADDR         0xFFCC1080         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP1_TXFUNCADDR         0xFFCC1088         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP2_TXFUNCADDR         0xFFCC1090         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP3_TXFUNCADDR         0xFFCC1098         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP4_TXFUNCADDR         0xFFCC10A0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP5_TXFUNCADDR         0xFFCC10A8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP6_TXFUNCADDR         0xFFCC10B0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP7_TXFUNCADDR         0xFFCC10B8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP8_TXFUNCADDR         0xFFCC10C0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP9_TXFUNCADDR         0xFFCC10C8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP10_TXFUNCADDR        0xFFCC10D0         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP11_TXFUNCADDR        0xFFCC10D8         /* USB0 MPn Transmit Function Address Register */
-#define REG_USB0_MP0_TXHUBADDR          0xFFCC1082         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP1_TXHUBADDR          0xFFCC108A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP2_TXHUBADDR          0xFFCC1092         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP3_TXHUBADDR          0xFFCC109A         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP4_TXHUBADDR          0xFFCC10A2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP5_TXHUBADDR          0xFFCC10AA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP6_TXHUBADDR          0xFFCC10B2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP7_TXHUBADDR          0xFFCC10BA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP8_TXHUBADDR          0xFFCC10C2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP9_TXHUBADDR          0xFFCC10CA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP10_TXHUBADDR         0xFFCC10D2         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP11_TXHUBADDR         0xFFCC10DA         /* USB0 MPn Transmit Hub Address Register */
-#define REG_USB0_MP0_TXHUBPORT          0xFFCC1083         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP1_TXHUBPORT          0xFFCC108B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP2_TXHUBPORT          0xFFCC1093         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP3_TXHUBPORT          0xFFCC109B         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP4_TXHUBPORT          0xFFCC10A3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP5_TXHUBPORT          0xFFCC10AB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP6_TXHUBPORT          0xFFCC10B3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP7_TXHUBPORT          0xFFCC10BB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP8_TXHUBPORT          0xFFCC10C3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP9_TXHUBPORT          0xFFCC10CB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP10_TXHUBPORT         0xFFCC10D3         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP11_TXHUBPORT         0xFFCC10DB         /* USB0 MPn Transmit Hub Port Register */
-#define REG_USB0_MP0_RXFUNCADDR         0xFFCC1084         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP1_RXFUNCADDR         0xFFCC108C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP2_RXFUNCADDR         0xFFCC1094         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP3_RXFUNCADDR         0xFFCC109C         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP4_RXFUNCADDR         0xFFCC10A4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP5_RXFUNCADDR         0xFFCC10AC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP6_RXFUNCADDR         0xFFCC10B4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP7_RXFUNCADDR         0xFFCC10BC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP8_RXFUNCADDR         0xFFCC10C4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP9_RXFUNCADDR         0xFFCC10CC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP10_RXFUNCADDR        0xFFCC10D4         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP11_RXFUNCADDR        0xFFCC10DC         /* USB0 MPn Receive Function Address Register */
-#define REG_USB0_MP0_RXHUBADDR          0xFFCC1086         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP1_RXHUBADDR          0xFFCC108E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP2_RXHUBADDR          0xFFCC1096         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP3_RXHUBADDR          0xFFCC109E         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP4_RXHUBADDR          0xFFCC10A6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP5_RXHUBADDR          0xFFCC10AE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP6_RXHUBADDR          0xFFCC10B6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP7_RXHUBADDR          0xFFCC10BE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP8_RXHUBADDR          0xFFCC10C6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP9_RXHUBADDR          0xFFCC10CE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP10_RXHUBADDR         0xFFCC10D6         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP11_RXHUBADDR         0xFFCC10DE         /* USB0 MPn Receive Hub Address Register */
-#define REG_USB0_MP0_RXHUBPORT          0xFFCC1087         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP1_RXHUBPORT          0xFFCC108F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP2_RXHUBPORT          0xFFCC1097         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP3_RXHUBPORT          0xFFCC109F         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP4_RXHUBPORT          0xFFCC10A7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP5_RXHUBPORT          0xFFCC10AF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP6_RXHUBPORT          0xFFCC10B7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP7_RXHUBPORT          0xFFCC10BF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP8_RXHUBPORT          0xFFCC10C7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP9_RXHUBPORT          0xFFCC10CF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP10_RXHUBPORT         0xFFCC10D7         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_MP11_RXHUBPORT         0xFFCC10DF         /* USB0 MPn Receive Hub Port Register */
-#define REG_USB0_EP0_TXMAXP             0xFFCC1100         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP1_TXMAXP             0xFFCC1110         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP2_TXMAXP             0xFFCC1120         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP3_TXMAXP             0xFFCC1130         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP4_TXMAXP             0xFFCC1140         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP5_TXMAXP             0xFFCC1150         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP6_TXMAXP             0xFFCC1160         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP7_TXMAXP             0xFFCC1170         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP8_TXMAXP             0xFFCC1180         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP9_TXMAXP             0xFFCC1190         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP10_TXMAXP            0xFFCC11A0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP11_TXMAXP            0xFFCC11B0         /* USB0 EPn Transmit Maximum Packet Length Register */
-#define REG_USB0_EP0_CSR0_H             0xFFCC1102         /* USB0 EP0 Configuration and Status (Host) Register */
-#define REG_USB0_EP0_TXCSR_H            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP1_TXCSR_H            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP2_TXCSR_H            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP3_TXCSR_H            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP4_TXCSR_H            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP5_TXCSR_H            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP6_TXCSR_H            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP7_TXCSR_H            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP8_TXCSR_H            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP9_TXCSR_H            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP10_TXCSR_H           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP11_TXCSR_H           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Host) Register */
-#define REG_USB0_EP0_CSR0_P             0xFFCC1102         /* USB0 EP0 Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_TXCSR_P            0xFFCC1102         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_TXCSR_P            0xFFCC1112         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_TXCSR_P            0xFFCC1122         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_TXCSR_P            0xFFCC1132         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_TXCSR_P            0xFFCC1142         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_TXCSR_P            0xFFCC1152         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_TXCSR_P            0xFFCC1162         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_TXCSR_P            0xFFCC1172         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_TXCSR_P            0xFFCC1182         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_TXCSR_P            0xFFCC1192         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_TXCSR_P           0xFFCC11A2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_TXCSR_P           0xFFCC11B2         /* USB0 EPn Transmit Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_RXMAXP             0xFFCC1104         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP1_RXMAXP             0xFFCC1114         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP2_RXMAXP             0xFFCC1124         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP3_RXMAXP             0xFFCC1134         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP4_RXMAXP             0xFFCC1144         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP5_RXMAXP             0xFFCC1154         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP6_RXMAXP             0xFFCC1164         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP7_RXMAXP             0xFFCC1174         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP8_RXMAXP             0xFFCC1184         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP9_RXMAXP             0xFFCC1194         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP10_RXMAXP            0xFFCC11A4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP11_RXMAXP            0xFFCC11B4         /* USB0 EPn Receive Maximum Packet Length Register */
-#define REG_USB0_EP0_RXCSR_H            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP1_RXCSR_H            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP2_RXCSR_H            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP3_RXCSR_H            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP4_RXCSR_H            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP5_RXCSR_H            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP6_RXCSR_H            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP7_RXCSR_H            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP8_RXCSR_H            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP9_RXCSR_H            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP10_RXCSR_H           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP11_RXCSR_H           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Host) Register */
-#define REG_USB0_EP0_RXCSR_P            0xFFCC1106         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP1_RXCSR_P            0xFFCC1116         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP2_RXCSR_P            0xFFCC1126         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP3_RXCSR_P            0xFFCC1136         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP4_RXCSR_P            0xFFCC1146         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP5_RXCSR_P            0xFFCC1156         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP6_RXCSR_P            0xFFCC1166         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP7_RXCSR_P            0xFFCC1176         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP8_RXCSR_P            0xFFCC1186         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP9_RXCSR_P            0xFFCC1196         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP10_RXCSR_P           0xFFCC11A6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP11_RXCSR_P           0xFFCC11B6         /* USB0 EPn Receive Configuration and Status (Peripheral) Register */
-#define REG_USB0_EP0_CNT0               0xFFCC1108         /* USB0 EP0 Number of Received Bytes Register */
-#define REG_USB0_EP0_RXCNT              0xFFCC1108         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP1_RXCNT              0xFFCC1118         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP2_RXCNT              0xFFCC1128         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP3_RXCNT              0xFFCC1138         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP4_RXCNT              0xFFCC1148         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP5_RXCNT              0xFFCC1158         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP6_RXCNT              0xFFCC1168         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP7_RXCNT              0xFFCC1178         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP8_RXCNT              0xFFCC1188         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP9_RXCNT              0xFFCC1198         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP10_RXCNT             0xFFCC11A8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP11_RXCNT             0xFFCC11B8         /* USB0 EPn Number of Bytes Received Register */
-#define REG_USB0_EP0_TYPE0              0xFFCC110A         /* USB0 EP0 Connection Type Register */
-#define REG_USB0_EP0_TXTYPE             0xFFCC110A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP1_TXTYPE             0xFFCC111A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP2_TXTYPE             0xFFCC112A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP3_TXTYPE             0xFFCC113A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP4_TXTYPE             0xFFCC114A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP5_TXTYPE             0xFFCC115A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP6_TXTYPE             0xFFCC116A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP7_TXTYPE             0xFFCC117A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP8_TXTYPE             0xFFCC118A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP9_TXTYPE             0xFFCC119A         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP10_TXTYPE            0xFFCC11AA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP11_TXTYPE            0xFFCC11BA         /* USB0 EPn Transmit Type Register */
-#define REG_USB0_EP0_NAKLIMIT0          0xFFCC110B         /* USB0 EP0 NAK Limit Register */
-#define REG_USB0_EP0_TXINTERVAL         0xFFCC110B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP1_TXINTERVAL         0xFFCC111B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP2_TXINTERVAL         0xFFCC112B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP3_TXINTERVAL         0xFFCC113B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP4_TXINTERVAL         0xFFCC114B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP5_TXINTERVAL         0xFFCC115B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP6_TXINTERVAL         0xFFCC116B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP7_TXINTERVAL         0xFFCC117B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP8_TXINTERVAL         0xFFCC118B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP9_TXINTERVAL         0xFFCC119B         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP10_TXINTERVAL        0xFFCC11AB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP11_TXINTERVAL        0xFFCC11BB         /* USB0 EPn Transmit Polling Interval Register */
-#define REG_USB0_EP0_RXTYPE             0xFFCC110C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP1_RXTYPE             0xFFCC111C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP2_RXTYPE             0xFFCC112C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP3_RXTYPE             0xFFCC113C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP4_RXTYPE             0xFFCC114C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP5_RXTYPE             0xFFCC115C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP6_RXTYPE             0xFFCC116C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP7_RXTYPE             0xFFCC117C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP8_RXTYPE             0xFFCC118C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP9_RXTYPE             0xFFCC119C         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP10_RXTYPE            0xFFCC11AC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP11_RXTYPE            0xFFCC11BC         /* USB0 EPn Receive Type Register */
-#define REG_USB0_EP0_RXINTERVAL         0xFFCC110D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP1_RXINTERVAL         0xFFCC111D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP2_RXINTERVAL         0xFFCC112D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP3_RXINTERVAL         0xFFCC113D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP4_RXINTERVAL         0xFFCC114D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP5_RXINTERVAL         0xFFCC115D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP6_RXINTERVAL         0xFFCC116D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP7_RXINTERVAL         0xFFCC117D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP8_RXINTERVAL         0xFFCC118D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP9_RXINTERVAL         0xFFCC119D         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP10_RXINTERVAL        0xFFCC11AD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP11_RXINTERVAL        0xFFCC11BD         /* USB0 EPn Receive Polling Interval Register */
-#define REG_USB0_EP0_CFGDATA0           0xFFCC110F         /* USB0 EP0 Configuration Information Register */
-#define REG_USB0_DMA_IRQ                0xFFCC1200         /* USB0 DMA Interrupt Register */
-#define REG_USB0_DMA0_CTL               0xFFCC1204         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA1_CTL               0xFFCC1214         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA2_CTL               0xFFCC1224         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA3_CTL               0xFFCC1234         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA4_CTL               0xFFCC1244         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA5_CTL               0xFFCC1254         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA6_CTL               0xFFCC1264         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA7_CTL               0xFFCC1274         /* USB0 DMA Channel n Control Register */
-#define REG_USB0_DMA0_ADDR              0xFFCC1208         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA1_ADDR              0xFFCC1218         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA2_ADDR              0xFFCC1228         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA3_ADDR              0xFFCC1238         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA4_ADDR              0xFFCC1248         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA5_ADDR              0xFFCC1258         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA6_ADDR              0xFFCC1268         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA7_ADDR              0xFFCC1278         /* USB0 DMA Channel n Address Register */
-#define REG_USB0_DMA0_CNT               0xFFCC120C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA1_CNT               0xFFCC121C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA2_CNT               0xFFCC122C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA3_CNT               0xFFCC123C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA4_CNT               0xFFCC124C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA5_CNT               0xFFCC125C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA6_CNT               0xFFCC126C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_DMA7_CNT               0xFFCC127C         /* USB0 DMA Channel n Count Register */
-#define REG_USB0_RQPKTCNT0              0xFFCC1300         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT1              0xFFCC1304         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT2              0xFFCC1308         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT3              0xFFCC130C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT4              0xFFCC1310         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT5              0xFFCC1314         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT6              0xFFCC1318         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT7              0xFFCC131C         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT8              0xFFCC1320         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT9              0xFFCC1324         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_RQPKTCNT10             0xFFCC1328         /* USB0 EPn Request Packet Count Register */
-#define REG_USB0_CT_UCH                 0xFFCC1344         /* USB0 Chirp Timeout Register */
-#define REG_USB0_CT_HHSRTN              0xFFCC1346         /* USB0 Host High Speed Return to Normal Register */
-#define REG_USB0_CT_HSBT                0xFFCC1348         /* USB0 High Speed Timeout Register */
-#define REG_USB0_LPM_ATTR               0xFFCC1360         /* USB0 LPM Attribute Register */
-#define REG_USB0_LPM_CTL                0xFFCC1362         /* USB0 LPM Control Register */
-#define REG_USB0_LPM_IEN                0xFFCC1363         /* USB0 LPM Interrupt Enable Register */
-#define REG_USB0_LPM_IRQ                0xFFCC1364         /* USB0 LPM Interrupt Status Register */
-#define REG_USB0_LPM_FADDR              0xFFCC1365         /* USB0 LPM Function Address Register */
-#define REG_USB0_VBUS_CTL               0xFFCC1380         /* USB0 VBUS Control Register */
-#define REG_USB0_BAT_CHG                0xFFCC1381         /* USB0 Battery Charging Control Register */
-#define REG_USB0_PHY_CTL                0xFFCC1394         /* USB0 PHY Control Register */
-#define REG_USB0_PLL_OSC                0xFFCC1398         /* USB0 PLL and Oscillator Control Register */
-
-/* =========================
-        USB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FADDR                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FADDR_VALUE                  0                               /* Function Address Value */
-#define BITM_USB_FADDR_VALUE                 (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_POWER                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_POWER_ISOUPDT                7                               /* ISO Update Enable */
-#define BITP_USB_POWER_SOFTCONN               6                               /* Soft Connect/Disconnect Enable */
-#define BITP_USB_POWER_HSEN                   5                               /* High Speed Mode Enable */
-#define BITP_USB_POWER_HSMODE                 4                               /* High Speed Mode */
-#define BITP_USB_POWER_RESET                  3                               /* Reset USB */
-#define BITP_USB_POWER_RESUME                 2                               /* Resume Mode */
-#define BITP_USB_POWER_SUSPEND                1                               /* Suspend Mode */
-#define BITP_USB_POWER_SUSEN                  0                               /* SUSPENDM Output Enable */
-
-#define BITM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISO Update Enable */
-#define ENUM_USB_POWER_NO_ISOUPDT            (_ADI_MSK(0x00000000,uint8_t))   /* ISOUPDT: Disable ISO Update */
-#define ENUM_USB_POWER_ISOUPDT               (_ADI_MSK(0x00000080,uint8_t))   /* ISOUPDT: Enable ISO Update */
-
-#define BITM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* Soft Connect/Disconnect Enable */
-#define ENUM_USB_POWER_NO_SOFTCONN           (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCONN: Disable Soft Connect/Disconnect */
-#define ENUM_USB_POWER_SOFTCONN              (_ADI_MSK(0x00000040,uint8_t))   /* SOFTCONN: Enable Soft Connect/Disconnect */
-
-#define BITM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* High Speed Mode Enable */
-#define ENUM_USB_POWER_HSDIS                 (_ADI_MSK(0x00000000,uint8_t))   /* HSEN: Disable Negotiation for HS Mode */
-#define ENUM_USB_POWER_HSEN                  (_ADI_MSK(0x00000020,uint8_t))   /* HSEN: Enable Negotiation for HS Mode */
-
-#define BITM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* High Speed Mode */
-#define ENUM_USB_POWER_NO_HSMODE             (_ADI_MSK(0x00000000,uint8_t))   /* HSMODE: Full Speed Mode (HS fail during reset) */
-#define ENUM_USB_POWER_HSMODE                (_ADI_MSK(0x00000010,uint8_t))   /* HSMODE: High Speed Mode (HS success during reset) */
-
-#define BITM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* Reset USB */
-#define ENUM_USB_POWER_NO_RESET              (_ADI_MSK(0x00000000,uint8_t))   /* RESET: No Reset */
-#define ENUM_USB_POWER_RESET                 (_ADI_MSK(0x00000008,uint8_t))   /* RESET: Reset USB */
-
-#define BITM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* Resume Mode */
-#define ENUM_USB_POWER_NO_RESUME             (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Resume Signaling */
-#define ENUM_USB_POWER_RESUME                (_ADI_MSK(0x00000004,uint8_t))   /* RESUME: Enable Resume Signaling */
-
-#define BITM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* Suspend Mode */
-#define ENUM_USB_POWER_NO_SUSPEND            (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Suspend Mode (Host) */
-#define ENUM_USB_POWER_SUSPEND               (_ADI_MSK(0x00000002,uint8_t))   /* SUSPEND: Enable Suspend Mode (Host) */
-
-#define BITM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPENDM Output Enable */
-#define ENUM_USB_POWER_SUSDIS                (_ADI_MSK(0x00000000,uint8_t))   /* SUSEN: Disable SUSPENDM Output */
-#define ENUM_USB_POWER_SUSEN                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSEN: Enable SUSPENDM Output */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTX_EP11                 11                               /* End Point 11 Tx Interrupt */
-#define BITP_USB_INTRTX_EP10                 10                               /* End Point 10 Tx Interrupt */
-#define BITP_USB_INTRTX_EP9                   9                               /* End Point 9 Tx Interrupt */
-#define BITP_USB_INTRTX_EP8                   8                               /* End Point 8 Tx Interrupt */
-#define BITP_USB_INTRTX_EP7                   7                               /* End Point 7 Tx Interrupt */
-#define BITP_USB_INTRTX_EP6                   6                               /* End Point 6 Tx Interrupt */
-#define BITP_USB_INTRTX_EP5                   5                               /* End Point 5 Tx Interrupt */
-#define BITP_USB_INTRTX_EP4                   4                               /* End Point 4 Tx Interrupt */
-#define BITP_USB_INTRTX_EP3                   3                               /* End Point 3 Tx Interrupt */
-#define BITP_USB_INTRTX_EP2                   2                               /* End Point 2 Tx Interrupt */
-#define BITP_USB_INTRTX_EP1                   1                               /* End Point 1 Tx Interrupt */
-#define BITP_USB_INTRTX_EP0                   0                               /* End Point 0 Tx Interrupt */
-#define BITM_USB_INTRTX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt */
-#define BITM_USB_INTRTX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt */
-#define BITM_USB_INTRTX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt */
-#define BITM_USB_INTRTX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt */
-#define BITM_USB_INTRTX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt */
-#define BITM_USB_INTRTX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt */
-#define BITM_USB_INTRTX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt */
-#define BITM_USB_INTRTX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt */
-#define BITM_USB_INTRTX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt */
-#define BITM_USB_INTRTX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt */
-#define BITM_USB_INTRTX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt */
-#define BITM_USB_INTRTX_EP0                  (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRX                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRX_EP11                 11                               /* End Point 11 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP10                 10                               /* End Point 10 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP9                   9                               /* End Point 9 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP8                   8                               /* End Point 8 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP7                   7                               /* End Point 7 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP6                   6                               /* End Point 6 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP5                   5                               /* End Point 5 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP4                   4                               /* End Point 4 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP3                   3                               /* End Point 3 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP2                   2                               /* End Point 2 Rx Interrupt. */
-#define BITP_USB_INTRRX_EP1                   1                               /* End Point 1 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP11                 (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP10                 (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP9                  (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP8                  (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP7                  (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP6                  (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP5                  (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP4                  (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP3                  (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP2                  (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt. */
-#define BITM_USB_INTRRX_EP1                  (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt. */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRTXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRTXE_EP11                11                               /* End Point 11 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP10                10                               /* End Point 10 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP9                  9                               /* End Point 9 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP8                  8                               /* End Point 8 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP7                  7                               /* End Point 7 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP6                  6                               /* End Point 6 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP5                  5                               /* End Point 5 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP4                  4                               /* End Point 4 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP3                  3                               /* End Point 3 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP2                  2                               /* End Point 2 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP1                  1                               /* End Point 1 Tx Interrupt Enable */
-#define BITP_USB_INTRTXE_EP0                  0                               /* End Point 0 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Tx Interrupt Enable */
-#define BITM_USB_INTRTXE_EP0                 (_ADI_MSK(0x00000001,uint16_t))  /* End Point 0 Tx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INTRRXE                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INTRRXE_EP11                11                               /* End Point 11 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP10                10                               /* End Point 10 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP9                  9                               /* End Point 9 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP8                  8                               /* End Point 8 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP7                  7                               /* End Point 7 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP6                  6                               /* End Point 6 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP5                  5                               /* End Point 5 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP4                  4                               /* End Point 4 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP3                  3                               /* End Point 3 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP2                  2                               /* End Point 2 Rx Interrupt Enable */
-#define BITP_USB_INTRRXE_EP1                  1                               /* End Point 1 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP11                (_ADI_MSK(0x00000800,uint16_t))  /* End Point 11 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP10                (_ADI_MSK(0x00000400,uint16_t))  /* End Point 10 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP9                 (_ADI_MSK(0x00000200,uint16_t))  /* End Point 9 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP8                 (_ADI_MSK(0x00000100,uint16_t))  /* End Point 8 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP7                 (_ADI_MSK(0x00000080,uint16_t))  /* End Point 7 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP6                 (_ADI_MSK(0x00000040,uint16_t))  /* End Point 6 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP5                 (_ADI_MSK(0x00000020,uint16_t))  /* End Point 5 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP4                 (_ADI_MSK(0x00000010,uint16_t))  /* End Point 4 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP3                 (_ADI_MSK(0x00000008,uint16_t))  /* End Point 3 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP2                 (_ADI_MSK(0x00000004,uint16_t))  /* End Point 2 Rx Interrupt Enable */
-#define BITM_USB_INTRRXE_EP1                 (_ADI_MSK(0x00000002,uint16_t))  /* End Point 1 Rx Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IRQ                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IRQ_VBUSERR                  7                               /* VBUS Threshold Indicator */
-#define BITP_USB_IRQ_SESSREQ                  6                               /* Session Request Indicator */
-#define BITP_USB_IRQ_DISCON                   5                               /* Disconnect Indicator */
-#define BITP_USB_IRQ_CON                      4                               /* Connection Indicator */
-#define BITP_USB_IRQ_SOF                      3                               /* Start-of-frame Indicator */
-#define BITP_USB_IRQ_RSTBABBLE                2                               /* Reset/Babble Indicator */
-#define BITP_USB_IRQ_RESUME                   1                               /* Resume Indicator */
-#define BITP_USB_IRQ_SUSPEND                  0                               /* Suspend Indicator */
-
-#define BITM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator */
-#define ENUM_USB_IRQ_NO_VBUSERR              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: No Interrupt */
-#define ENUM_USB_IRQ_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Interrupt Pending */
-
-#define BITM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator */
-#define ENUM_USB_IRQ_NO_SESSREQ              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: No Interrupt */
-#define ENUM_USB_IRQ_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Interrupt Pending */
-
-#define BITM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator */
-#define ENUM_USB_IRQ_NO_DISCON               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: No Interrupt */
-#define ENUM_USB_IRQ_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Interrupt Pending */
-
-#define BITM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator */
-#define ENUM_USB_IRQ_NO_CON                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: No Interrupt */
-#define ENUM_USB_IRQ_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* CON: Interrupt Pending */
-
-#define BITM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator */
-#define ENUM_USB_IRQ_NO_SOF                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: No Interrupt */
-#define ENUM_USB_IRQ_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Interrupt Pending */
-
-#define BITM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator */
-#define ENUM_USB_IRQ_NO_RSTBABBLE            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: No Interrupt */
-#define ENUM_USB_IRQ_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Interrupt Pending */
-
-#define BITM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator */
-#define ENUM_USB_IRQ_NO_RESUME               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: No Interrupt */
-#define ENUM_USB_IRQ_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Interrupt Pending */
-
-#define BITM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator */
-#define ENUM_USB_IRQ_NO_SUSPEND              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: No Interrupt */
-#define ENUM_USB_IRQ_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Interrupt Pending */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_IEN                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_IEN_VBUSERR                  7                               /* VBUS Threshold Indicator Interrupt Enable */
-#define BITP_USB_IEN_SESSREQ                  6                               /* Session Request Indicator Interrupt Enable */
-#define BITP_USB_IEN_DISCON                   5                               /* Disconnect Indicator Interrupt Enable */
-#define BITP_USB_IEN_CON                      4                               /* Connection Indicator Interrupt Enable */
-#define BITP_USB_IEN_SOF                      3                               /* Start-of-frame Indicator Interrupt Enable */
-#define BITP_USB_IEN_RSTBABBLE                2                               /* Reset/Babble Indicator Interrupt Enable */
-#define BITP_USB_IEN_RESUME                   1                               /* Resume Indicator Interrupt Enable */
-#define BITP_USB_IEN_SUSPEND                  0                               /* Suspend Indicator Interrupt Enable */
-
-#define BITM_USB_IEN_VBUSERR                 (_ADI_MSK(0x00000080,uint8_t))   /* VBUS Threshold Indicator Interrupt Enable */
-#define ENUM_USB_IEN_VBUSERRDIS              (_ADI_MSK(0x00000000,uint8_t))   /* VBUSERR: Disable Interrupt */
-#define ENUM_USB_IEN_VBUSERREN               (_ADI_MSK(0x00000080,uint8_t))   /* VBUSERR: Enable Interrupt */
-
-#define BITM_USB_IEN_SESSREQ                 (_ADI_MSK(0x00000040,uint8_t))   /* Session Request Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SESSREQDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SESSREQ: Disable Interrupt */
-#define ENUM_USB_IEN_SESSREQEN               (_ADI_MSK(0x00000040,uint8_t))   /* SESSREQ: Enable Interrupt */
-
-#define BITM_USB_IEN_DISCON                  (_ADI_MSK(0x00000020,uint8_t))   /* Disconnect Indicator Interrupt Enable */
-#define ENUM_USB_IEN_DISCONDIS               (_ADI_MSK(0x00000000,uint8_t))   /* DISCON: Disable Interrupt */
-#define ENUM_USB_IEN_DISCONEN                (_ADI_MSK(0x00000020,uint8_t))   /* DISCON: Enable Interrupt */
-
-#define BITM_USB_IEN_CON                     (_ADI_MSK(0x00000010,uint8_t))   /* Connection Indicator Interrupt Enable */
-#define ENUM_USB_IEN_CONDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* CON: Disable Interrupt */
-#define ENUM_USB_IEN_CONEN                   (_ADI_MSK(0x00000010,uint8_t))   /* CON: Enable Interrupt */
-
-#define BITM_USB_IEN_SOF                     (_ADI_MSK(0x00000008,uint8_t))   /* Start-of-frame Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SOFDIS                  (_ADI_MSK(0x00000000,uint8_t))   /* SOF: Disable Interrupt */
-#define ENUM_USB_IEN_SOFEN                   (_ADI_MSK(0x00000008,uint8_t))   /* SOF: Enable Interrupt */
-
-#define BITM_USB_IEN_RSTBABBLE               (_ADI_MSK(0x00000004,uint8_t))   /* Reset/Babble Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RSTBABBLEDIS            (_ADI_MSK(0x00000000,uint8_t))   /* RSTBABBLE: Disable Interrupt */
-#define ENUM_USB_IEN_RSTBABBLEEN             (_ADI_MSK(0x00000004,uint8_t))   /* RSTBABBLE: Enable Interrupt */
-
-#define BITM_USB_IEN_RESUME                  (_ADI_MSK(0x00000002,uint8_t))   /* Resume Indicator Interrupt Enable */
-#define ENUM_USB_IEN_RESUMEDIS               (_ADI_MSK(0x00000000,uint8_t))   /* RESUME: Disable Interrupt */
-#define ENUM_USB_IEN_RESUMEEN                (_ADI_MSK(0x00000002,uint8_t))   /* RESUME: Enable Interrupt */
-
-#define BITM_USB_IEN_SUSPEND                 (_ADI_MSK(0x00000001,uint8_t))   /* Suspend Indicator Interrupt Enable */
-#define ENUM_USB_IEN_SUSPENDDIS              (_ADI_MSK(0x00000000,uint8_t))   /* SUSPEND: Disable Interrupt */
-#define ENUM_USB_IEN_SUSPENDEN               (_ADI_MSK(0x00000001,uint8_t))   /* SUSPEND: Enable Interrupt */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_FRAME                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_FRAME_VALUE                  0                               /* Frame Number Value */
-#define BITM_USB_FRAME_VALUE                 (_ADI_MSK(0x000007FF,uint16_t))  /* Frame Number Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_INDEX                            Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_INDEX_EP                     0                               /* Endpoint Index */
-#define BITM_USB_INDEX_EP                    (_ADI_MSK(0x0000000F,uint8_t))   /* Endpoint Index */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TESTMODE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TESTMODE_FIFOACCESS          6                               /* FIFO Access */
-#define BITP_USB_TESTMODE_TESTPACKET          3                               /* Test_Packet Mode */
-#define BITP_USB_TESTMODE_TESTK               2                               /* Test_K Mode */
-#define BITP_USB_TESTMODE_TESTJ               1                               /* Test_J Mode */
-#define BITP_USB_TESTMODE_TESTSE0NAK          0                               /* Test SE0 NAK */
-#define BITM_USB_TESTMODE_FIFOACCESS         (_ADI_MSK(0x00000040,uint8_t))   /* FIFO Access */
-#define BITM_USB_TESTMODE_TESTPACKET         (_ADI_MSK(0x00000008,uint8_t))   /* Test_Packet Mode */
-#define BITM_USB_TESTMODE_TESTK              (_ADI_MSK(0x00000004,uint8_t))   /* Test_K Mode */
-#define BITM_USB_TESTMODE_TESTJ              (_ADI_MSK(0x00000002,uint8_t))   /* Test_J Mode */
-#define BITM_USB_TESTMODE_TESTSE0NAK         (_ADI_MSK(0x00000001,uint8_t))   /* Test SE0 NAK */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_TXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_TXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_TXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_P_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_P_ISO             14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EPI_TXCSR_P_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_P_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_P_INCOMPTX         7                               /* Incomplete Tx */
-#define BITP_USB_EPI_TXCSR_P_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_P_SENTSTALL        5                               /* Sent STALL */
-#define BITP_USB_EPI_TXCSR_P_SENDSTALL        4                               /* Send STALL */
-#define BITP_USB_EPI_TXCSR_P_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_P_URUNERR          2                               /* Underrun Error */
-#define BITP_USB_EPI_TXCSR_P_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_P_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_P_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_P_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EPI_TXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EPI_TXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_P_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_P_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_P_INCOMPTX        (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EPI_TXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EPI_TXCSR_P_INCOMP          (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EPI_TXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_P_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_P_SENTSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_P_STALSNT         (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_TXCSR_P_SENDSTALL       (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_TXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EPI_TXCSR_P_STALL           (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EPI_TXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_P_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EPI_TXCSR_P_NO_URUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EPI_TXCSR_P_URUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EPI_TXCSR_P_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_P_NO_FIFONE       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_P_FIFONE          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_P_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXCSR_H_AUTOSET         15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EPI_TXCSR_H_DMAREQEN        12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EPI_TXCSR_H_FRCDATATGL      11                               /* Force Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_DMAREQMODE      10                               /* DMA Mode Select */
-#define BITP_USB_EPI_TXCSR_H_DATGLEN          9                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_TXCSR_H_DATGL            8                               /* Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_NAKTOINCMP       7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EPI_TXCSR_H_CLRDATATGL       6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_TXCSR_H_RXSTALL          5                               /* Rx STALL */
-#define BITP_USB_EPI_TXCSR_H_SETUPPKT         4                               /* Setup Packet */
-#define BITP_USB_EPI_TXCSR_H_FLUSHFIFO        3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXTOERR          2                               /* Tx Timeout Error */
-#define BITP_USB_EPI_TXCSR_H_NEFIFO           1                               /* Not Empty FIFO */
-#define BITP_USB_EPI_TXCSR_H_TXPKTRDY         0                               /* Tx Packet Ready */
-
-#define BITM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_AUTOSET      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EPI_TXCSR_H_AUTOSET         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_TXCSR_H_DMAREQEN        (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_TXCSR_H_FRCDATATGL      (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_FRCTGL       (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_FRCTGL          (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EPI_TXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_TXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGLEN      (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_TXCSR_H_DATGLEN         (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EPI_TXCSR_H_DATGL           (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EPI_TXCSR_H_NAKTOINCMP      (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EPI_TXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EPI_TXCSR_H_NAKTO           (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EPI_TXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_TXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_TXCSR_H_CLRTGL          (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_TXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_TXCSR_H_RXSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EPI_TXCSR_H_NO_SETUPPK      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EPI_TXCSR_H_SETUPPKT        (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EPI_TXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_TXCSR_H_FLUSH           (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EPI_TXCSR_H_NO_TXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EPI_TXCSR_H_TXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EPI_TXCSR_H_NO_NEFIFO       (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EPI_TXCSR_H_NEFIFO          (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EPI_TXCSR_H_TXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EPI_TXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EPI_TXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_P_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_P_SSETUPEND         7                               /* Service Setup End */
-#define BITP_USB_EP0I_CSR_P_SPKTRDY           6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_SENDSTALL         5                               /* Send Stall */
-#define BITP_USB_EP0I_CSR_P_SETUPEND          4                               /* Setup End */
-#define BITP_USB_EP0I_CSR_P_DATAEND           3                               /* Data End */
-#define BITP_USB_EP0I_CSR_P_SENTSTALL         2                               /* Sent Stall */
-#define BITP_USB_EP0I_CSR_P_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_P_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_P_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0I_CSR_P_NOSSETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0I_CSR_P_SSETUPEND        (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_SPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0I_CSR_P_SPKTRDY          (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0I_CSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0I_CSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0I_CSR_P_NO_SETUPEND      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_SETUPEND         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0I_CSR_P_NO_DATAEND       (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0I_CSR_P_DATAEND          (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0I_CSR_P_SENTSTALL        (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0I_CSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_P_STALSNT          (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0I_CSR_P_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0I_CSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CSR_H_DISPING          11                               /* Disable Ping */
-#define BITP_USB_EP0I_CSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0I_CSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP0I_CSR_H_FLUSHFIFO         8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0I_CSR_H_NAKTO             7                               /* NAK Timeout */
-#define BITP_USB_EP0I_CSR_H_STATUSPKT         6                               /* Status Packet */
-#define BITP_USB_EP0I_CSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP0I_CSR_H_TOERR             4                               /* Timeout Error */
-#define BITP_USB_EP0I_CSR_H_SETUPPKT          3                               /* Setup Packet */
-#define BITP_USB_EP0I_CSR_H_RXSTALL           2                               /* Rx Stall */
-#define BITP_USB_EP0I_CSR_H_TXPKTRDY          1                               /* Tx Packet Ready */
-#define BITP_USB_EP0I_CSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0I_CSR_H_NO_DISPING       (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0I_CSR_H_DISPING          (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0I_CSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0I_CSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0I_CSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0I_CSR_H_NO_DATATGL       (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0I_CSR_H_DATATGL          (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0I_CSR_H_FLUSHFIFO        (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0I_CSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0I_CSR_H_FLUSH            (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0I_CSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0I_CSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0I_CSR_H_STATUSPKT        (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_STATPKT       (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_STATPKT          (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0I_CSR_H_NO_TOERR         (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0I_CSR_H_TOERR            (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0I_CSR_H_NO_SETUPPKT      (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0I_CSR_H_SETUPPKT         (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0I_CSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0I_CSR_H_RXSTALL          (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_TXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0I_CSR_H_TXPKTRDY         (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0I_CSR_H_NO_RXPKTRDY      (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0I_CSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXMAXP                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXMAXP_MULTM1           11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EPI_RXMAXP_MAXPAY            0                               /* Maximum Payload */
-#define BITM_USB_EPI_RXMAXP_MULTM1           (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EPI_RXMAXP_MAXPAY           (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_H                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_H_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_AUTOREQ         14                               /* Auto Request Clear Enable */
-#define BITP_USB_EPI_RXCSR_H_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_H_PIDERR          12                               /* Packet ID Error */
-#define BITP_USB_EPI_RXCSR_H_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_H_DATGLEN         10                               /* Data Toggle Write Enable */
-#define BITP_USB_EPI_RXCSR_H_DATGL            9                               /* Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_H_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_H_RXSTALL          6                               /* Rx STALL */
-#define BITP_USB_EPI_RXCSR_H_REQPKT           5                               /* Request Packet */
-#define BITP_USB_EPI_RXCSR_H_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_H_NAKTODERR        3                               /* NAK Timeout Data Error */
-#define BITP_USB_EPI_RXCSR_H_RXTOERR          2                               /* Rx Timeout Error */
-#define BITP_USB_EPI_RXCSR_H_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_H_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EPI_RXCSR_H_NO_AUTOREQ      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EPI_RXCSR_H_AUTOREQ         (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_H_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_PIDERR       (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_PIDERR          (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EPI_RXCSR_H_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_H_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EPI_RXCSR_H_DATGLDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EPI_RXCSR_H_DATGLEN         (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_DATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EPI_RXCSR_H_DATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EPI_RXCSR_H_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_H_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_H_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_H_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_H_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_H_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXSTALL      (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXSTALL         (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EPI_RXCSR_H_NO_REQPKT       (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EPI_RXCSR_H_REQPKT          (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EPI_RXCSR_H_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_H_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_H_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_H_NAKTODERR       (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_NAKTO        (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_NAKTO           (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EPI_RXCSR_H_NO_RXTOERR      (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EPI_RXCSR_H_RXTOERR         (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EPI_RXCSR_H_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_H_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_H_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_H_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_H_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_H_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCSR_P                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCSR_P_AUTOCLR         15                               /* Auto Clear Enable */
-#define BITP_USB_EPI_RXCSR_P_ISO             14                               /* Isochronous Transfers */
-#define BITP_USB_EPI_RXCSR_P_DMAREQEN        13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EPI_RXCSR_P_DNYETPERR       12                               /* Disable NYET Handshake */
-#define BITP_USB_EPI_RXCSR_P_DMAREQMODE      11                               /* DMA Mode Select */
-#define BITP_USB_EPI_RXCSR_P_INCOMPRX         8                               /* Incomplete Rx */
-#define BITP_USB_EPI_RXCSR_P_CLRDATATGL       7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EPI_RXCSR_P_SENTSTALL        6                               /* Sent STALL */
-#define BITP_USB_EPI_RXCSR_P_SENDSTALL        5                               /* Send STALL */
-#define BITP_USB_EPI_RXCSR_P_FLUSHFIFO        4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EPI_RXCSR_P_DATAERR          3                               /* Data Error */
-#define BITP_USB_EPI_RXCSR_P_ORUNERR          2                               /* OUT Run Error */
-#define BITP_USB_EPI_RXCSR_P_FIFOFULL         1                               /* FIFO Full */
-#define BITP_USB_EPI_RXCSR_P_RXPKTRDY         0                               /* Rx Packet Ready */
-
-#define BITM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EPI_RXCSR_P_NO_AUTOCLR      (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EPI_RXCSR_P_AUTOCLR         (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EPI_RXCSR_P_ISO             (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EPI_RXCSR_P_ISODIS          (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EPI_RXCSR_P_ISOEN           (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQDIS       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EPI_RXCSR_P_DMAREQEN        (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EPI_RXCSR_P_DNYETPERR       (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERREN       (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EPI_RXCSR_P_DNYTERRDIS      (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_DMAREQMODE      (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE0      (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EPI_RXCSR_P_DMARQMODE1      (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EPI_RXCSR_P_INCOMPRX        (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EPI_RXCSR_P_NO_INCOMP       (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EPI_RXCSR_P_INCOMP          (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EPI_RXCSR_P_CLRDATATGL      (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EPI_RXCSR_P_NO_CLRTGL       (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_CLRTGL          (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EPI_RXCSR_P_SENTSTALL       (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALSNT      (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_STALSNT         (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EPI_RXCSR_P_SENDSTALL       (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EPI_RXCSR_P_NO_STALL        (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EPI_RXCSR_P_STALL           (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EPI_RXCSR_P_FLUSHFIFO       (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EPI_RXCSR_P_NO_FLUSH        (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EPI_RXCSR_P_FLUSH           (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_DATAERR      (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_DATAERR         (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EPI_RXCSR_P_NO_ORUNERR      (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EPI_RXCSR_P_ORUNERR         (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EPI_RXCSR_P_FIFOFULL        (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EPI_RXCSR_P_NO_FIFOFUL      (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EPI_RXCSR_P_FIFOFUL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EPI_RXCSR_P_RXPKTRDY        (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EPI_RXCSR_P_NO_PKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EPI_RXCSR_P_PKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CNT_RXCNT               0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0I_CNT_RXCNT              (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXCNT                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXCNT_EPRXCNT            0                               /* EP Rx Count */
-#define BITM_USB_EPI_RXCNT_EPRXCNT           (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_TXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_TXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_TXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_TXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_TXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_TXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_TXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_TXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_TXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_TXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_TXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_TXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_TXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_TXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_TXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_TXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_TXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_TYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_TYPE_SPEED              0                               /* Speed of Operation Value */
-#define BITM_USB_EP0I_TYPE_SPEED             (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_NAKLIMIT                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_NAKLIMIT_VALUE          0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0I_NAKLIMIT_VALUE         (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPI_RXTYPE                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPI_RXTYPE_SPEED             6                               /* Speed of Operation Value */
-#define BITP_USB_EPI_RXTYPE_PROTOCOL          4                               /* Protocol for Transfer */
-#define BITP_USB_EPI_RXTYPE_TGTEP             0                               /* Target Endpoint Number */
-
-#define BITM_USB_EPI_RXTYPE_SPEED            (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EPI_RXTYPE_UNUSED           (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EPI_RXTYPE_HIGHSPEED        (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EPI_RXTYPE_FULLSPEED        (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EPI_RXTYPE_LOWSPEED         (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EPI_RXTYPE_PROTOCOL         (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EPI_RXTYPE_CONTROL          (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EPI_RXTYPE_ISO              (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EPI_RXTYPE_BULK             (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EPI_RXTYPE_INT              (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EPI_RXTYPE_TGTEP            (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EPI_RXTYPE_TGTEP0           (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP1           (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP10          (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP11          (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP12          (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP13          (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP14          (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP15          (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP2           (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP3           (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP4           (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP5           (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP6           (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP7           (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP8           (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EPI_RXTYPE_TGTEP9           (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0I_CFGDATA                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0I_CFGDATA_MPRX            7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_MPTX            6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_BIGEND          5                               /* Big Endian Data */
-#define BITP_USB_EP0I_CFGDATA_HBRX            4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0I_CFGDATA_HBTX            3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0I_CFGDATA_DYNFIFO         2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0I_CFGDATA_SOFTCON         1                               /* Soft Connect Enable */
-#define BITP_USB_EP0I_CFGDATA_UTMIWID         0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0I_CFGDATA_MPRX           (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPRXEN         (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_MPTX           (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_MPTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0I_CFGDATA_MPTXEN         (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0I_CFGDATA_BIGEND         (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDDIS      (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0I_CFGDATA_BIGENDEN       (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0I_CFGDATA_HBRX           (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBRXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0I_CFGDATA_HBRXEN         (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0I_CFGDATA_HBTX           (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0I_CFGDATA_HBTXDIS        (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0I_CFGDATA_HBTXEN         (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0I_CFGDATA_DYNFIFO        (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZDIS       (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0I_CFGDATA_DYNSZEN        (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0I_CFGDATA_SOFTCON        (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONDIS      (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0I_CFGDATA_SFTCONEN       (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0I_CFGDATA_UTMIWID        (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID8       (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0I_CFGDATA_UTMIWID16      (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DEV_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DEV_CTL_BDEVICE              7                               /* A or B Devices Indicator */
-#define BITP_USB_DEV_CTL_FSDEV                6                               /* Full or High-Speed Indicator */
-#define BITP_USB_DEV_CTL_LSDEV                5                               /* Low-Speed Indicator */
-#define BITP_USB_DEV_CTL_VBUS                 3                               /* VBUS Level Indicator */
-#define BITP_USB_DEV_CTL_HOSTMODE             2                               /* Host Mode Indicator */
-#define BITP_USB_DEV_CTL_HOSTREQ              1                               /* Host Negotiation Request */
-#define BITP_USB_DEV_CTL_SESSION              0                               /* Session Indicator */
-
-#define BITM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* A or B Devices Indicator */
-#define ENUM_USB_DEV_CTL_ADEVICE             (_ADI_MSK(0x00000000,uint8_t))   /* BDEVICE: A Device Detected */
-#define ENUM_USB_DEV_CTL_BDEVICE             (_ADI_MSK(0x00000080,uint8_t))   /* BDEVICE: B Device Detected */
-
-#define BITM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* Full or High-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_FSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* FSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_FSDEV               (_ADI_MSK(0x00000040,uint8_t))   /* FSDEV: Full or High Speed Detected */
-
-#define BITM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* Low-Speed Indicator */
-#define ENUM_USB_DEV_CTL_NO_LSDEV            (_ADI_MSK(0x00000000,uint8_t))   /* LSDEV: Not Detected */
-#define ENUM_USB_DEV_CTL_LSDEV               (_ADI_MSK(0x00000020,uint8_t))   /* LSDEV: Low Speed Detected */
-
-#define BITM_USB_DEV_CTL_VBUS                (_ADI_MSK(0x00000018,uint8_t))   /* VBUS Level Indicator */
-#define ENUM_USB_DEV_CTL_VBUS_BS             (_ADI_MSK(0x00000000,uint8_t))   /* VBUS: Below SessionEnd */
-#define ENUM_USB_DEV_CTL_VBUS_ASBA           (_ADI_MSK(0x00000008,uint8_t))   /* VBUS: Above SessionEnd, below AValid */
-#define ENUM_USB_DEV_CTL_VBUS_AABV           (_ADI_MSK(0x00000010,uint8_t))   /* VBUS: Above AValid, below VBUSValid */
-#define ENUM_USB_DEV_CTL_VBUS_AV             (_ADI_MSK(0x00000018,uint8_t))   /* VBUS: Above VBUSValid */
-
-#define BITM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* Host Mode Indicator */
-#define ENUM_USB_DEV_CTL_NO_HOSTMODE         (_ADI_MSK(0x00000000,uint8_t))   /* HOSTMODE: Peripheral Mode */
-#define ENUM_USB_DEV_CTL_HOSTMODE            (_ADI_MSK(0x00000004,uint8_t))   /* HOSTMODE: Host Mode */
-
-#define BITM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* Host Negotiation Request */
-#define ENUM_USB_DEV_CTL_NO_HOSTREQ          (_ADI_MSK(0x00000000,uint8_t))   /* HOSTREQ: No Request */
-#define ENUM_USB_DEV_CTL_HOSTREQ             (_ADI_MSK(0x00000002,uint8_t))   /* HOSTREQ: Place Request */
-
-#define BITM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* Session Indicator */
-#define ENUM_USB_DEV_CTL_NO_SESSION          (_ADI_MSK(0x00000000,uint8_t))   /* SESSION: Not Detected */
-#define ENUM_USB_DEV_CTL_SESSION             (_ADI_MSK(0x00000001,uint8_t))   /* SESSION: Detected Session */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_TXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_TXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_TXFIFOSZ_DPNDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_TXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_TXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_TXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_TXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_TXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_TXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_TXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_TXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_TXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_TXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_TXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_TXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOSZ                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOSZ_DPB                 4                               /* Double Packet Buffering Enable */
-#define BITP_USB_RXFIFOSZ_SZ                  0                               /* Maximum Packet Size */
-
-#define BITM_USB_RXFIFOSZ_DPB                (_ADI_MSK(0x00000010,uint8_t))   /* Double Packet Buffering Enable */
-#define ENUM_USB_RXFIFOSZ_DPBDIS             (_ADI_MSK(0x00000000,uint8_t))   /* DPB: Single Packet Buffering */
-#define ENUM_USB_RXFIFOSZ_DPBEN              (_ADI_MSK(0x00000010,uint8_t))   /* DPB: Double Packet Buffering */
-
-#define BITM_USB_RXFIFOSZ_SZ                 (_ADI_MSK(0x0000000F,uint8_t))   /* Maximum Packet Size */
-#define ENUM_USB_RXFIFOSZ_SZ8                (_ADI_MSK(0x00000000,uint8_t))   /* SZ: PktSz=8, DPB0=8, DPB1=16 */
-#define ENUM_USB_RXFIFOSZ_SZ16               (_ADI_MSK(0x00000001,uint8_t))   /* SZ: PktSz=16, DPB0=16, DPB1=32 */
-#define ENUM_USB_RXFIFOSZ_SZ32               (_ADI_MSK(0x00000002,uint8_t))   /* SZ: PktSz=32, DPB0=32, DPB1=64 */
-#define ENUM_USB_RXFIFOSZ_SZ64               (_ADI_MSK(0x00000003,uint8_t))   /* SZ: PktSz=64, DPB0=64, DPB1=128 */
-#define ENUM_USB_RXFIFOSZ_SZ128              (_ADI_MSK(0x00000004,uint8_t))   /* SZ: PktSz=128, DPB0=128, DPB1=256 */
-#define ENUM_USB_RXFIFOSZ_SZ256              (_ADI_MSK(0x00000005,uint8_t))   /* SZ: PktSz=256, DPB0=256, DPB1=512 */
-#define ENUM_USB_RXFIFOSZ_SZ512              (_ADI_MSK(0x00000006,uint8_t))   /* SZ: PktSz=512, DPB0=512, DPB1=1024 */
-#define ENUM_USB_RXFIFOSZ_SZ1024             (_ADI_MSK(0x00000007,uint8_t))   /* SZ: PktSz=1024, DPB0=1024, DPB1=2048 */
-#define ENUM_USB_RXFIFOSZ_SZ2048             (_ADI_MSK(0x00000008,uint8_t))   /* SZ: PktSz=2048, DPB0=2048, DPB1=4096 */
-#define ENUM_USB_RXFIFOSZ_SZ4096             (_ADI_MSK(0x00000009,uint8_t))   /* SZ: PktSz=4096, DPB0=4096, DPB1=8192 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_TXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_TXFIFOADDR_VALUE             0                               /* Tx FIFO Start Address */
-#define BITM_USB_TXFIFOADDR_VALUE            (_ADI_MSK(0x00001FFF,uint16_t))  /* Tx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RXFIFOADDR                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RXFIFOADDR_VALUE             0                               /* Rx FIFO Start Address */
-#define BITM_USB_RXFIFOADDR_VALUE            (_ADI_MSK(0x00000FFF,uint16_t))  /* Rx FIFO Start Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EPINFO                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EPINFO_RXEP                  4                               /* Rx Endpoints */
-#define BITP_USB_EPINFO_TXEP                  0                               /* Tx Endpoints */
-#define BITM_USB_EPINFO_RXEP                 (_ADI_MSK(0x000000F0,uint8_t))   /* Rx Endpoints */
-#define BITM_USB_EPINFO_TXEP                 (_ADI_MSK(0x0000000F,uint8_t))   /* Tx Endpoints */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_RAMINFO                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_RAMINFO_DMACHANS             4                               /* DMA Channels */
-#define BITP_USB_RAMINFO_RAMBITS              0                               /* RAM Address Bits */
-#define BITM_USB_RAMINFO_DMACHANS            (_ADI_MSK(0x000000F0,uint8_t))   /* DMA Channels */
-#define BITM_USB_RAMINFO_RAMBITS             (_ADI_MSK(0x0000000F,uint8_t))   /* RAM Address Bits */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LINKINFO                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LINKINFO_WTCON               4                               /* Wait for Connect/Disconnect */
-#define BITP_USB_LINKINFO_WTID                0                               /* Wait from ID Pull-up */
-#define BITM_USB_LINKINFO_WTCON              (_ADI_MSK(0x000000F0,uint8_t))   /* Wait for Connect/Disconnect */
-#define BITM_USB_LINKINFO_WTID               (_ADI_MSK(0x0000000F,uint8_t))   /* Wait from ID Pull-up */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_SOFT_RST                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_SOFT_RST_RSTX                1                               /* Reset USB XCLK Domain */
-#define BITP_USB_SOFT_RST_RST                 0                               /* Reset USB CLK Domain */
-
-#define BITM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* Reset USB XCLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RSTX            (_ADI_MSK(0x00000000,uint8_t))   /* RSTX: No Reset */
-#define ENUM_USB_SOFT_RST_RSTX               (_ADI_MSK(0x00000002,uint8_t))   /* RSTX: Reset USB XCLK Domain */
-
-#define BITM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* Reset USB CLK Domain */
-#define ENUM_USB_SOFT_RST_NO_RST             (_ADI_MSK(0x00000000,uint8_t))   /* RST: No Reset */
-#define ENUM_USB_SOFT_RST_RST                (_ADI_MSK(0x00000001,uint8_t))   /* RST: Reset USB CLK Domain */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXFUNCADDR_VALUE          0                               /* Tx Function Address Value */
-#define BITM_USB_MP_TXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Tx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_TXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_TXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_TXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_TXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_TXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_TXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXFUNCADDR                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXFUNCADDR_VALUE          0                               /* Rx Function Address Value */
-#define BITM_USB_MP_RXFUNCADDR_VALUE         (_ADI_MSK(0x0000007F,uint8_t))   /* Rx Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBADDR                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBADDR_MULTTRANS       7                               /* Multiple Transaction Translators */
-#define BITP_USB_MP_RXHUBADDR_ADDR            0                               /* Hub Address Value */
-#define BITM_USB_MP_RXHUBADDR_MULTTRANS      (_ADI_MSK(0x00000080,uint8_t))   /* Multiple Transaction Translators */
-#define BITM_USB_MP_RXHUBADDR_ADDR           (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_MP_RXHUBPORT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_MP_RXHUBPORT_VALUE           0                               /* Hub Port Value */
-#define BITM_USB_MP_RXHUBPORT_VALUE          (_ADI_MSK(0x0000007F,uint8_t))   /* Hub Port Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_TXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_TXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_TXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_H                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_H_DISPING           11                               /* Disable Ping */
-#define BITP_USB_EP0_CSR_H_DATGLEN           10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP0_CSR_H_DATGL              9                               /* Data Toggle */
-#define BITP_USB_EP0_CSR_H_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_H_NAKTO              7                               /* NAK Timeout */
-#define BITP_USB_EP0_CSR_H_STATUSPKT          6                               /* Status Packet */
-#define BITP_USB_EP0_CSR_H_REQPKT             5                               /* Request Packet */
-#define BITP_USB_EP0_CSR_H_TOERR              4                               /* Timeout Error */
-#define BITP_USB_EP0_CSR_H_SETUPPKT           3                               /* Setup Packet */
-#define BITP_USB_EP0_CSR_H_RXSTALL            2                               /* Rx Stall */
-#define BITP_USB_EP0_CSR_H_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_H_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* Disable Ping */
-#define ENUM_USB_EP0_CSR_H_NO_DISPING        (_ADI_MSK(0x00000000,uint16_t))  /* DISPING: Issue PING tokens */
-#define ENUM_USB_EP0_CSR_H_DISPING           (_ADI_MSK(0x00000800,uint16_t))  /* DISPING: Do not issue PING */
-
-#define BITM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP0_CSR_H_NO_DATGLEN        (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP0_CSR_H_DATGLEN           (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP0_CSR_H_DATGL             (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP0_CSR_H_NO_DATATGL        (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP0_CSR_H_DATATGL           (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP0_CSR_H_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_H_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_H_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout */
-#define ENUM_USB_EP0_CSR_H_NO_NAKTO          (_ADI_MSK(0x00000000,uint16_t))  /* NAKTO: No Status */
-#define ENUM_USB_EP0_CSR_H_NAKTO             (_ADI_MSK(0x00000080,uint16_t))  /* NAKTO: Endpoint Halted (NAK Timeout) */
-
-#define BITM_USB_EP0_CSR_H_STATUSPKT         (_ADI_MSK(0x00000040,uint16_t))  /* Status Packet */
-#define ENUM_USB_EP0_CSR_H_NO_STATPKT        (_ADI_MSK(0x00000000,uint16_t))  /* STATUSPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_STATPKT           (_ADI_MSK(0x00000040,uint16_t))  /* STATUSPKT: Request Status Transaction */
-
-#define BITM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP0_CSR_H_NO_REQPKT         (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_REQPKT            (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* Timeout Error */
-#define ENUM_USB_EP0_CSR_H_NO_TOERR          (_ADI_MSK(0x00000000,uint16_t))  /* TOERR: No Status */
-#define ENUM_USB_EP0_CSR_H_TOERR             (_ADI_MSK(0x00000010,uint16_t))  /* TOERR: Timeout Error */
-
-#define BITM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP0_CSR_H_NO_SETUPPKT       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP0_CSR_H_SETUPPKT          (_ADI_MSK(0x00000008,uint16_t))  /* SETUPPKT: Send SETUP token */
-
-#define BITM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* Rx Stall */
-#define ENUM_USB_EP0_CSR_H_NO_RXSTALL        (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP0_CSR_H_RXSTALL           (_ADI_MSK(0x00000004,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP0_CSR_H_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_H_NO_RXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_H_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_H_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_H_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_H_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_H_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_H_DATGLEN           9                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_TXCSR_H_DATGL             8                               /* Data Toggle */
-#define BITP_USB_EP_TXCSR_H_NAKTOINCMP        7                               /* NAK Timeout Incomplete */
-#define BITP_USB_EP_TXCSR_H_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_H_RXSTALL           5                               /* Rx STALL */
-#define BITP_USB_EP_TXCSR_H_SETUPPKT          4                               /* Setup Packet */
-#define BITP_USB_EP_TXCSR_H_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_H_TXTOERR           2                               /* Tx Timeout Error */
-#define BITP_USB_EP_TXCSR_H_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_H_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_H_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_H_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_H_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGLEN       (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_TXCSR_H_DATGLEN          (_ADI_MSK(0x00000200,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is set */
-#define ENUM_USB_EP_TXCSR_H_DATGL            (_ADI_MSK(0x00000100,uint16_t))  /* DATGL: DATA1 is set */
-
-#define BITM_USB_EP_TXCSR_H_NAKTOINCMP       (_ADI_MSK(0x00000080,uint16_t))  /* NAK Timeout Incomplete */
-#define ENUM_USB_EP_TXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTOINCMP: No Status */
-#define ENUM_USB_EP_TXCSR_H_NAKTO            (_ADI_MSK(0x00000080,uint16_t))  /* NAKTOINCMP: NAK Timeout Over Maximum */
-
-#define BITM_USB_EP_TXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_H_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_TXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_H_RXSTALL          (_ADI_MSK(0x00000020,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* Setup Packet */
-#define ENUM_USB_EP_TXCSR_H_NO_SETUPPK       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPPKT: No Request */
-#define ENUM_USB_EP_TXCSR_H_SETUPPKT         (_ADI_MSK(0x00000010,uint16_t))  /* SETUPPKT: Send SETUP Token */
-
-#define BITM_USB_EP_TXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_H_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Tx Timeout Error */
-#define ENUM_USB_EP_TXCSR_H_NO_TXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* TXTOERR: No Status */
-#define ENUM_USB_EP_TXCSR_H_TXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* TXTOERR: Tx Timeout Error */
-
-#define BITM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_H_NO_NEFIFO        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_H_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_H_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CSR_P                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CSR_P_FLUSHFIFO          8                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP0_CSR_P_SSETUPEND          7                               /* Service Setup End */
-#define BITP_USB_EP0_CSR_P_SPKTRDY            6                               /* Service Rx Packet Ready */
-#define BITP_USB_EP0_CSR_P_SENDSTALL          5                               /* Send Stall */
-#define BITP_USB_EP0_CSR_P_SETUPEND           4                               /* Setup End */
-#define BITP_USB_EP0_CSR_P_DATAEND            3                               /* Data End */
-#define BITP_USB_EP0_CSR_P_SENTSTALL          2                               /* Sent Stall */
-#define BITP_USB_EP0_CSR_P_TXPKTRDY           1                               /* Tx Packet Ready */
-#define BITP_USB_EP0_CSR_P_RXPKTRDY           0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP0_CSR_P_FLUSHFIFO         (_ADI_MSK(0x00000100,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP0_CSR_P_NO_FLUSH          (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP0_CSR_P_FLUSH             (_ADI_MSK(0x00000100,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* Service Setup End */
-#define ENUM_USB_EP0_CSR_P_NOSSETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SSETUPEND: No Action */
-#define ENUM_USB_EP0_CSR_P_SSETUPEND         (_ADI_MSK(0x00000080,uint16_t))  /* SSETUPEND: Clear SETUPEND Bit */
-
-#define BITM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* Service Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_SPKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* SPKTRDY: No Action */
-#define ENUM_USB_EP0_CSR_P_SPKTRDY           (_ADI_MSK(0x00000040,uint16_t))  /* SPKTRDY: Clear RXPKTRDY Bit */
-
-#define BITM_USB_EP0_CSR_P_SENDSTALL         (_ADI_MSK(0x00000020,uint16_t))  /* Send Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALL          (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP0_CSR_P_STALL             (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Terminate Current Transaction */
-
-#define BITM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* Setup End */
-#define ENUM_USB_EP0_CSR_P_NO_SETUPEND       (_ADI_MSK(0x00000000,uint16_t))  /* SETUPEND: No Status */
-#define ENUM_USB_EP0_CSR_P_SETUPEND          (_ADI_MSK(0x00000010,uint16_t))  /* SETUPEND: Setup Ended before DATAEND */
-
-#define BITM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* Data End */
-#define ENUM_USB_EP0_CSR_P_NO_DATAEND        (_ADI_MSK(0x00000000,uint16_t))  /* DATAEND: No Status */
-#define ENUM_USB_EP0_CSR_P_DATAEND           (_ADI_MSK(0x00000008,uint16_t))  /* DATAEND: Data End Condition */
-
-#define BITM_USB_EP0_CSR_P_SENTSTALL         (_ADI_MSK(0x00000004,uint16_t))  /* Sent Stall */
-#define ENUM_USB_EP0_CSR_P_NO_STALSNT        (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP0_CSR_P_STALSNT           (_ADI_MSK(0x00000004,uint16_t))  /* SENTSTALL: Transmitted STALL Handshake */
-
-#define BITM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_TXPKTRDY       (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY:  */
-#define ENUM_USB_EP0_CSR_P_TXPKTRDY          (_ADI_MSK(0x00000002,uint16_t))  /* TXPKTRDY: Set this bit after loading a data packet into the FIFO */
-
-#define BITM_USB_EP0_CSR_P_RXPKTRDY          (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP0_CSR_P_NO_PKTRDY         (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP0_CSR_P_PKTRDY            (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXCSR_P_AUTOSET          15                               /* TxPkRdy Autoset Enable */
-#define BITP_USB_EP_TXCSR_P_ISO              14                               /* Isochronous Transfers Enable */
-#define BITP_USB_EP_TXCSR_P_DMAREQEN         12                               /* DMA Request Enable Tx EP */
-#define BITP_USB_EP_TXCSR_P_FRCDATATGL       11                               /* Force Data Toggle */
-#define BITP_USB_EP_TXCSR_P_DMAREQMODE       10                               /* DMA Mode Select */
-#define BITP_USB_EP_TXCSR_P_INCOMPTX          7                               /* Incomplete Tx */
-#define BITP_USB_EP_TXCSR_P_CLRDATATGL        6                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_TXCSR_P_SENTSTALL         5                               /* Sent STALL */
-#define BITP_USB_EP_TXCSR_P_SENDSTALL         4                               /* Send STALL */
-#define BITP_USB_EP_TXCSR_P_FLUSHFIFO         3                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_TXCSR_P_URUNERR           2                               /* Underrun Error */
-#define BITP_USB_EP_TXCSR_P_NEFIFO            1                               /* Not Empty FIFO */
-#define BITP_USB_EP_TXCSR_P_TXPKTRDY          0                               /* Tx Packet Ready */
-
-#define BITM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* TxPkRdy Autoset Enable */
-#define ENUM_USB_EP_TXCSR_P_NO_AUTOSET       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOSET: Disable Autoset */
-#define ENUM_USB_EP_TXCSR_P_AUTOSET          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOSET: Enable Autoset */
-
-#define BITM_USB_EP_TXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers Enable */
-#define ENUM_USB_EP_TXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: Disable Tx EP Isochronous Transfers */
-#define ENUM_USB_EP_TXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: Enable Tx EP Isochronous Transfers */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMA Request Enable Tx EP */
-#define ENUM_USB_EP_TXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_TXCSR_P_DMAREQEN         (_ADI_MSK(0x00001000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_TXCSR_P_FRCDATATGL       (_ADI_MSK(0x00000800,uint16_t))  /* Force Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_FRCTGL        (_ADI_MSK(0x00000000,uint16_t))  /* FRCDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_FRCTGL           (_ADI_MSK(0x00000800,uint16_t))  /* FRCDATATGL: Toggle Endpoint Data */
-
-#define BITM_USB_EP_TXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000400,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_TXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000400,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_TXCSR_P_INCOMPTX         (_ADI_MSK(0x00000080,uint16_t))  /* Incomplete Tx */
-#define ENUM_USB_EP_TXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPTX: No Status */
-#define ENUM_USB_EP_TXCSR_P_INCOMP           (_ADI_MSK(0x00000080,uint16_t))  /* INCOMPTX: Incomplete Tx (Insufficient IN Tokens) */
-
-#define BITM_USB_EP_TXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000040,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_TXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_TXCSR_P_CLRTGL           (_ADI_MSK(0x00000040,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_TXCSR_P_SENTSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_TXCSR_P_STALSNT          (_ADI_MSK(0x00000020,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_TXCSR_P_SENDSTALL        (_ADI_MSK(0x00000010,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_TXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Request */
-#define ENUM_USB_EP_TXCSR_P_STALL            (_ADI_MSK(0x00000010,uint16_t))  /* SENDSTALL: Request STALL Handshake Transmission */
-
-#define BITM_USB_EP_TXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000008,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_TXCSR_P_FLUSH            (_ADI_MSK(0x00000008,uint16_t))  /* FLUSHFIFO: Flush endpoint FIFO */
-
-#define BITM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* Underrun Error */
-#define ENUM_USB_EP_TXCSR_P_NO_URUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* URUNERR: No Status */
-#define ENUM_USB_EP_TXCSR_P_URUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* URUNERR: Underrun Error */
-
-#define BITM_USB_EP_TXCSR_P_NEFIFO           (_ADI_MSK(0x00000002,uint16_t))  /* Not Empty FIFO */
-#define ENUM_USB_EP_TXCSR_P_NO_FIFONE        (_ADI_MSK(0x00000000,uint16_t))  /* NEFIFO: FIFO Empty */
-#define ENUM_USB_EP_TXCSR_P_FIFONE           (_ADI_MSK(0x00000002,uint16_t))  /* NEFIFO: FIFO Not Empty */
-
-#define BITM_USB_EP_TXCSR_P_TXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Tx Packet Ready */
-#define ENUM_USB_EP_TXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* TXPKTRDY: No Tx Packet */
-#define ENUM_USB_EP_TXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* TXPKTRDY: Tx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXMAXP                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXMAXP_MULTM1            11                               /* Multi-Packets per Micro-frame */
-#define BITP_USB_EP_RXMAXP_MAXPAY             0                               /* Maximum Payload */
-#define BITM_USB_EP_RXMAXP_MULTM1            (_ADI_MSK(0x00001800,uint16_t))  /* Multi-Packets per Micro-frame */
-#define BITM_USB_EP_RXMAXP_MAXPAY            (_ADI_MSK(0x000007FF,uint16_t))  /* Maximum Payload */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_H                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_H_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_H_AUTOREQ          14                               /* Auto Request Clear Enable */
-#define BITP_USB_EP_RXCSR_H_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_H_PIDERR           12                               /* Packet ID Error */
-#define BITP_USB_EP_RXCSR_H_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_H_DATGLEN          10                               /* Data Toggle Write Enable */
-#define BITP_USB_EP_RXCSR_H_DATGL             9                               /* Data Toggle */
-#define BITP_USB_EP_RXCSR_H_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_H_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_H_RXSTALL           6                               /* Rx STALL */
-#define BITP_USB_EP_RXCSR_H_REQPKT            5                               /* Request Packet */
-#define BITP_USB_EP_RXCSR_H_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_H_NAKTODERR         3                               /* NAK Timeout Data Error */
-#define BITP_USB_EP_RXCSR_H_RXTOERR           2                               /* Rx Timeout Error */
-#define BITP_USB_EP_RXCSR_H_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_H_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* Auto Request Clear Enable */
-#define ENUM_USB_EP_RXCSR_H_NO_AUTOREQ       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOREQ: Disable Auto Request Clear */
-#define ENUM_USB_EP_RXCSR_H_AUTOREQ          (_ADI_MSK(0x00004000,uint16_t))  /* AUTOREQ: Enable Auto Request Clear */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_H_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_H_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* Packet ID Error */
-#define ENUM_USB_EP_RXCSR_H_NO_PIDERR        (_ADI_MSK(0x00000000,uint16_t))  /* PIDERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_PIDERR           (_ADI_MSK(0x00001000,uint16_t))  /* PIDERR: PID Error */
-
-#define BITM_USB_EP_RXCSR_H_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_H_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* Data Toggle Write Enable */
-#define ENUM_USB_EP_RXCSR_H_DATGLDIS         (_ADI_MSK(0x00000000,uint16_t))  /* DATGLEN: Disable Write to DATGL */
-#define ENUM_USB_EP_RXCSR_H_DATGLEN          (_ADI_MSK(0x00000400,uint16_t))  /* DATGLEN: Enable Write to DATGL */
-
-#define BITM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_DATGL         (_ADI_MSK(0x00000000,uint16_t))  /* DATGL: DATA0 is Set */
-#define ENUM_USB_EP_RXCSR_H_DATGL            (_ADI_MSK(0x00000200,uint16_t))  /* DATGL: DATA1 is Set */
-
-#define BITM_USB_EP_RXCSR_H_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_H_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_H_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_H_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_H_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_H_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* Rx STALL */
-#define ENUM_USB_EP_RXCSR_H_NO_RXSTALL       (_ADI_MSK(0x00000000,uint16_t))  /* RXSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXSTALL          (_ADI_MSK(0x00000040,uint16_t))  /* RXSTALL: Stall Received from Device */
-
-#define BITM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* Request Packet */
-#define ENUM_USB_EP_RXCSR_H_NO_REQPKT        (_ADI_MSK(0x00000000,uint16_t))  /* REQPKT: No Request */
-#define ENUM_USB_EP_RXCSR_H_REQPKT           (_ADI_MSK(0x00000020,uint16_t))  /* REQPKT: Send IN Tokens to Device */
-
-#define BITM_USB_EP_RXCSR_H_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_H_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_H_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_H_NAKTODERR        (_ADI_MSK(0x00000008,uint16_t))  /* NAK Timeout Data Error */
-#define ENUM_USB_EP_RXCSR_H_NO_NAKTO         (_ADI_MSK(0x00000000,uint16_t))  /* NAKTODERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_NAKTO            (_ADI_MSK(0x00000008,uint16_t))  /* NAKTODERR: NAK Timeout Data Error */
-
-#define BITM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* Rx Timeout Error */
-#define ENUM_USB_EP_RXCSR_H_NO_RXTOERR       (_ADI_MSK(0x00000000,uint16_t))  /* RXTOERR: No Status */
-#define ENUM_USB_EP_RXCSR_H_RXTOERR          (_ADI_MSK(0x00000004,uint16_t))  /* RXTOERR: Rx Timeout Error */
-
-#define BITM_USB_EP_RXCSR_H_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_H_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_H_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_H_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_H_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_H_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCSR_P                       Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCSR_P_AUTOCLR          15                               /* Auto Clear Enable */
-#define BITP_USB_EP_RXCSR_P_ISO              14                               /* Isochronous Transfers */
-#define BITP_USB_EP_RXCSR_P_DMAREQEN         13                               /* DMA Request Enable Rx EP */
-#define BITP_USB_EP_RXCSR_P_DNYETPERR        12                               /* Disable NYET Handshake */
-#define BITP_USB_EP_RXCSR_P_DMAREQMODE       11                               /* DMA Mode Select */
-#define BITP_USB_EP_RXCSR_P_INCOMPRX          8                               /* Incomplete Rx */
-#define BITP_USB_EP_RXCSR_P_CLRDATATGL        7                               /* Clear Endpoint Data Toggle */
-#define BITP_USB_EP_RXCSR_P_SENTSTALL         6                               /* Sent STALL */
-#define BITP_USB_EP_RXCSR_P_SENDSTALL         5                               /* Send STALL */
-#define BITP_USB_EP_RXCSR_P_FLUSHFIFO         4                               /* Flush Endpoint FIFO */
-#define BITP_USB_EP_RXCSR_P_DATAERR           3                               /* Data Error */
-#define BITP_USB_EP_RXCSR_P_ORUNERR           2                               /* OUT Run Error */
-#define BITP_USB_EP_RXCSR_P_FIFOFULL          1                               /* FIFO Full */
-#define BITP_USB_EP_RXCSR_P_RXPKTRDY          0                               /* Rx Packet Ready */
-
-#define BITM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* Auto Clear Enable */
-#define ENUM_USB_EP_RXCSR_P_NO_AUTOCLR       (_ADI_MSK(0x00000000,uint16_t))  /* AUTOCLR: Disable Auto Clear */
-#define ENUM_USB_EP_RXCSR_P_AUTOCLR          (_ADI_MSK(0x00008000,uint16_t))  /* AUTOCLR: Enable Auto Clear */
-
-#define BITM_USB_EP_RXCSR_P_ISO              (_ADI_MSK(0x00004000,uint16_t))  /* Isochronous Transfers */
-#define ENUM_USB_EP_RXCSR_P_ISODIS           (_ADI_MSK(0x00000000,uint16_t))  /* ISO: This bit should be cleared for bulk or interrupt transfers. */
-#define ENUM_USB_EP_RXCSR_P_ISOEN            (_ADI_MSK(0x00004000,uint16_t))  /* ISO: This bit should be set for isochronous transfers. */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMA Request Enable Rx EP */
-#define ENUM_USB_EP_RXCSR_P_DMAREQDIS        (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQEN: Disable DMA Request */
-#define ENUM_USB_EP_RXCSR_P_DMAREQEN         (_ADI_MSK(0x00002000,uint16_t))  /* DMAREQEN: Enable DMA Request */
-
-#define BITM_USB_EP_RXCSR_P_DNYETPERR        (_ADI_MSK(0x00001000,uint16_t))  /* Disable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERREN        (_ADI_MSK(0x00000000,uint16_t))  /* DNYETPERR: Enable NYET Handshake */
-#define ENUM_USB_EP_RXCSR_P_DNYTERRDIS       (_ADI_MSK(0x00001000,uint16_t))  /* DNYETPERR: Disable NYET Handshake */
-
-#define BITM_USB_EP_RXCSR_P_DMAREQMODE       (_ADI_MSK(0x00000800,uint16_t))  /* DMA Mode Select */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE0       (_ADI_MSK(0x00000000,uint16_t))  /* DMAREQMODE: DMA Request Mode 0 */
-#define ENUM_USB_EP_RXCSR_P_DMARQMODE1       (_ADI_MSK(0x00000800,uint16_t))  /* DMAREQMODE: DMA Request Mode 1 */
-
-#define BITM_USB_EP_RXCSR_P_INCOMPRX         (_ADI_MSK(0x00000100,uint16_t))  /* Incomplete Rx */
-#define ENUM_USB_EP_RXCSR_P_NO_INCOMP        (_ADI_MSK(0x00000000,uint16_t))  /* INCOMPRX: No Status */
-#define ENUM_USB_EP_RXCSR_P_INCOMP           (_ADI_MSK(0x00000100,uint16_t))  /* INCOMPRX: Incomplete Rx */
-
-#define BITM_USB_EP_RXCSR_P_CLRDATATGL       (_ADI_MSK(0x00000080,uint16_t))  /* Clear Endpoint Data Toggle */
-#define ENUM_USB_EP_RXCSR_P_NO_CLRTGL        (_ADI_MSK(0x00000000,uint16_t))  /* CLRDATATGL: No Action */
-#define ENUM_USB_EP_RXCSR_P_CLRTGL           (_ADI_MSK(0x00000080,uint16_t))  /* CLRDATATGL: Reset EP Data Toggle to 0 */
-
-#define BITM_USB_EP_RXCSR_P_SENTSTALL        (_ADI_MSK(0x00000040,uint16_t))  /* Sent STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALSNT       (_ADI_MSK(0x00000000,uint16_t))  /* SENTSTALL: No Status */
-#define ENUM_USB_EP_RXCSR_P_STALSNT          (_ADI_MSK(0x00000040,uint16_t))  /* SENTSTALL: STALL Handshake Transmitted */
-
-#define BITM_USB_EP_RXCSR_P_SENDSTALL        (_ADI_MSK(0x00000020,uint16_t))  /* Send STALL */
-#define ENUM_USB_EP_RXCSR_P_NO_STALL         (_ADI_MSK(0x00000000,uint16_t))  /* SENDSTALL: No Action */
-#define ENUM_USB_EP_RXCSR_P_STALL            (_ADI_MSK(0x00000020,uint16_t))  /* SENDSTALL: Request STALL Handshake */
-
-#define BITM_USB_EP_RXCSR_P_FLUSHFIFO        (_ADI_MSK(0x00000010,uint16_t))  /* Flush Endpoint FIFO */
-#define ENUM_USB_EP_RXCSR_P_NO_FLUSH         (_ADI_MSK(0x00000000,uint16_t))  /* FLUSHFIFO: No Flush */
-#define ENUM_USB_EP_RXCSR_P_FLUSH            (_ADI_MSK(0x00000010,uint16_t))  /* FLUSHFIFO: Flush Endpoint FIFO */
-
-#define BITM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* Data Error */
-#define ENUM_USB_EP_RXCSR_P_NO_DATAERR       (_ADI_MSK(0x00000000,uint16_t))  /* DATAERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_DATAERR          (_ADI_MSK(0x00000008,uint16_t))  /* DATAERR: Data Error */
-
-#define BITM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* OUT Run Error */
-#define ENUM_USB_EP_RXCSR_P_NO_ORUNERR       (_ADI_MSK(0x00000000,uint16_t))  /* ORUNERR: No Status */
-#define ENUM_USB_EP_RXCSR_P_ORUNERR          (_ADI_MSK(0x00000004,uint16_t))  /* ORUNERR: OUT Run Error */
-
-#define BITM_USB_EP_RXCSR_P_FIFOFULL         (_ADI_MSK(0x00000002,uint16_t))  /* FIFO Full */
-#define ENUM_USB_EP_RXCSR_P_NO_FIFOFUL       (_ADI_MSK(0x00000000,uint16_t))  /* FIFOFULL: No Status */
-#define ENUM_USB_EP_RXCSR_P_FIFOFUL          (_ADI_MSK(0x00000002,uint16_t))  /* FIFOFULL: FIFO Full */
-
-#define BITM_USB_EP_RXCSR_P_RXPKTRDY         (_ADI_MSK(0x00000001,uint16_t))  /* Rx Packet Ready */
-#define ENUM_USB_EP_RXCSR_P_NO_PKTRDY        (_ADI_MSK(0x00000000,uint16_t))  /* RXPKTRDY: No Rx Packet */
-#define ENUM_USB_EP_RXCSR_P_PKTRDY           (_ADI_MSK(0x00000001,uint16_t))  /* RXPKTRDY: Rx Packet in Endpoint FIFO */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CNT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CNT_RXCNT                0                               /* Rx Byte Count Value */
-#define BITM_USB_EP0_CNT_RXCNT               (_ADI_MSK(0x0000007F,uint16_t))  /* Rx Byte Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXCNT                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXCNT_EPRXCNT             0                               /* EP Rx Count */
-#define BITM_USB_EP_RXCNT_EPRXCNT            (_ADI_MSK(0x00003FFF,uint16_t))  /* EP Rx Count */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_TYPE                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_TYPE_SPEED               0                               /* Speed of Operation Value */
-#define BITM_USB_EP0_TYPE_SPEED              (_ADI_MSK(0x00000003,uint8_t))   /* Speed of Operation Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_TXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_TXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_TXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_TXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_TXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_TXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_TXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_TXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_TXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_TXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_TXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_TXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_TXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_TXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_TXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_TXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_TXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_TXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_TXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_TXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_TXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_TXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_TXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_TXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_TXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_TXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_TXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_TXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_TXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_TXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_TXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_NAKLIMIT                     Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_NAKLIMIT_VALUE           0                               /* Endpoint 0 Timeout Value (in Frames) */
-#define BITM_USB_EP0_NAKLIMIT_VALUE          (_ADI_MSK(0x0000001F,uint8_t))   /* Endpoint 0 Timeout Value (in Frames) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP_RXTYPE                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP_RXTYPE_SPEED              6                               /* Speed of Operation Value */
-#define BITP_USB_EP_RXTYPE_PROTOCOL           4                               /* Protocol for Transfer */
-#define BITP_USB_EP_RXTYPE_TGTEP              0                               /* Target Endpoint Number */
-
-#define BITM_USB_EP_RXTYPE_SPEED             (_ADI_MSK(0x000000C0,uint8_t))   /* Speed of Operation Value */
-#define ENUM_USB_EP_RXTYPE_UNUSED            (_ADI_MSK(0x00000000,uint8_t))   /* SPEED: Same Speed as the Core */
-#define ENUM_USB_EP_RXTYPE_HIGHSPEED         (_ADI_MSK(0x00000040,uint8_t))   /* SPEED: High Speed */
-#define ENUM_USB_EP_RXTYPE_FULLSPEED         (_ADI_MSK(0x00000080,uint8_t))   /* SPEED: Full Speed */
-#define ENUM_USB_EP_RXTYPE_LOWSPEED          (_ADI_MSK(0x000000C0,uint8_t))   /* SPEED: Low Speed */
-
-#define BITM_USB_EP_RXTYPE_PROTOCOL          (_ADI_MSK(0x00000030,uint8_t))   /* Protocol for Transfer */
-#define ENUM_USB_EP_RXTYPE_CONTROL           (_ADI_MSK(0x00000000,uint8_t))   /* PROTOCOL: Control */
-#define ENUM_USB_EP_RXTYPE_ISO               (_ADI_MSK(0x00000010,uint8_t))   /* PROTOCOL: Isochronous */
-#define ENUM_USB_EP_RXTYPE_BULK              (_ADI_MSK(0x00000020,uint8_t))   /* PROTOCOL: Bulk */
-#define ENUM_USB_EP_RXTYPE_INT               (_ADI_MSK(0x00000030,uint8_t))   /* PROTOCOL: Interrupt */
-
-#define BITM_USB_EP_RXTYPE_TGTEP             (_ADI_MSK(0x0000000F,uint8_t))   /* Target Endpoint Number */
-#define ENUM_USB_EP_RXTYPE_TGTEP0            (_ADI_MSK(0x00000000,uint8_t))   /* TGTEP: Endpoint 0 */
-#define ENUM_USB_EP_RXTYPE_TGTEP1            (_ADI_MSK(0x00000001,uint8_t))   /* TGTEP: Endpoint 1 */
-#define ENUM_USB_EP_RXTYPE_TGTEP10           (_ADI_MSK(0x0000000A,uint8_t))   /* TGTEP: Endpoint 10 */
-#define ENUM_USB_EP_RXTYPE_TGTEP11           (_ADI_MSK(0x0000000B,uint8_t))   /* TGTEP: Endpoint 11 */
-#define ENUM_USB_EP_RXTYPE_TGTEP12           (_ADI_MSK(0x0000000C,uint8_t))   /* TGTEP: Endpoint 12 */
-#define ENUM_USB_EP_RXTYPE_TGTEP13           (_ADI_MSK(0x0000000D,uint8_t))   /* TGTEP: Endpoint 13 */
-#define ENUM_USB_EP_RXTYPE_TGTEP14           (_ADI_MSK(0x0000000E,uint8_t))   /* TGTEP: Endpoint 14 */
-#define ENUM_USB_EP_RXTYPE_TGTEP15           (_ADI_MSK(0x0000000F,uint8_t))   /* TGTEP: Endpoint 15 */
-#define ENUM_USB_EP_RXTYPE_TGTEP2            (_ADI_MSK(0x00000002,uint8_t))   /* TGTEP: Endpoint 2 */
-#define ENUM_USB_EP_RXTYPE_TGTEP3            (_ADI_MSK(0x00000003,uint8_t))   /* TGTEP: Endpoint 3 */
-#define ENUM_USB_EP_RXTYPE_TGTEP4            (_ADI_MSK(0x00000004,uint8_t))   /* TGTEP: Endpoint 4 */
-#define ENUM_USB_EP_RXTYPE_TGTEP5            (_ADI_MSK(0x00000005,uint8_t))   /* TGTEP: Endpoint 5 */
-#define ENUM_USB_EP_RXTYPE_TGTEP6            (_ADI_MSK(0x00000006,uint8_t))   /* TGTEP: Endpoint 6 */
-#define ENUM_USB_EP_RXTYPE_TGTEP7            (_ADI_MSK(0x00000007,uint8_t))   /* TGTEP: Endpoint 7 */
-#define ENUM_USB_EP_RXTYPE_TGTEP8            (_ADI_MSK(0x00000008,uint8_t))   /* TGTEP: Endpoint 8 */
-#define ENUM_USB_EP_RXTYPE_TGTEP9            (_ADI_MSK(0x00000009,uint8_t))   /* TGTEP: Endpoint 9 */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_EP0_CFGDATA                      Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_EP0_CFGDATA_MPRX             7                               /* Multi-Packet Aggregate for Rx Enable */
-#define BITP_USB_EP0_CFGDATA_MPTX             6                               /* Multi-Packet Split for Tx Enable */
-#define BITP_USB_EP0_CFGDATA_BIGEND           5                               /* Big Endian Data */
-#define BITP_USB_EP0_CFGDATA_HBRX             4                               /* High Bandwidth Rx Enable */
-#define BITP_USB_EP0_CFGDATA_HBTX             3                               /* High Bandwidth Tx Enable */
-#define BITP_USB_EP0_CFGDATA_DYNFIFO          2                               /* Dynamic FIFO Size Enable */
-#define BITP_USB_EP0_CFGDATA_SOFTCON          1                               /* Soft Connect Enable */
-#define BITP_USB_EP0_CFGDATA_UTMIWID          0                               /* UTMI Data Width */
-
-#define BITM_USB_EP0_CFGDATA_MPRX            (_ADI_MSK(0x00000080,uint8_t))   /* Multi-Packet Aggregate for Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPRX: No Aggregate Rx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPRXEN          (_ADI_MSK(0x00000080,uint8_t))   /* MPRX: Aggregate Rx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_MPTX            (_ADI_MSK(0x00000040,uint8_t))   /* Multi-Packet Split for Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_MPTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* MPTX: No Split Tx Bulk Packets */
-#define ENUM_USB_EP0_CFGDATA_MPTXEN          (_ADI_MSK(0x00000040,uint8_t))   /* MPTX: Split Tx Bulk Packets */
-
-#define BITM_USB_EP0_CFGDATA_BIGEND          (_ADI_MSK(0x00000020,uint8_t))   /* Big Endian Data */
-#define ENUM_USB_EP0_CFGDATA_BIGENDDIS       (_ADI_MSK(0x00000000,uint8_t))   /* BIGEND: Little Endian Configuration */
-#define ENUM_USB_EP0_CFGDATA_BIGENDEN        (_ADI_MSK(0x00000020,uint8_t))   /* BIGEND: Big Endian Configuration */
-
-#define BITM_USB_EP0_CFGDATA_HBRX            (_ADI_MSK(0x00000010,uint8_t))   /* High Bandwidth Rx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBRXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBRX: No High Bandwidth Rx */
-#define ENUM_USB_EP0_CFGDATA_HBRXEN          (_ADI_MSK(0x00000010,uint8_t))   /* HBRX: High Bandwidth Rx */
-
-#define BITM_USB_EP0_CFGDATA_HBTX            (_ADI_MSK(0x00000008,uint8_t))   /* High Bandwidth Tx Enable */
-#define ENUM_USB_EP0_CFGDATA_HBTXDIS         (_ADI_MSK(0x00000000,uint8_t))   /* HBTX: No High Bandwidth Tx */
-#define ENUM_USB_EP0_CFGDATA_HBTXEN          (_ADI_MSK(0x00000008,uint8_t))   /* HBTX: High Bandwidth Tx */
-
-#define BITM_USB_EP0_CFGDATA_DYNFIFO         (_ADI_MSK(0x00000004,uint8_t))   /* Dynamic FIFO Size Enable */
-#define ENUM_USB_EP0_CFGDATA_DYNSZDIS        (_ADI_MSK(0x00000000,uint8_t))   /* DYNFIFO: No Dynamic FIFO Size */
-#define ENUM_USB_EP0_CFGDATA_DYNSZEN         (_ADI_MSK(0x00000004,uint8_t))   /* DYNFIFO: Dynamic FIFO Size */
-
-#define BITM_USB_EP0_CFGDATA_SOFTCON         (_ADI_MSK(0x00000002,uint8_t))   /* Soft Connect Enable */
-#define ENUM_USB_EP0_CFGDATA_SFTCONDIS       (_ADI_MSK(0x00000000,uint8_t))   /* SOFTCON: No Soft Connect */
-#define ENUM_USB_EP0_CFGDATA_SFTCONEN        (_ADI_MSK(0x00000002,uint8_t))   /* SOFTCON: Soft Connect */
-
-#define BITM_USB_EP0_CFGDATA_UTMIWID         (_ADI_MSK(0x00000001,uint8_t))   /* UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID8        (_ADI_MSK(0x00000000,uint8_t))   /* UTMIWID: 8-bit UTMI Data Width */
-#define ENUM_USB_EP0_CFGDATA_UTMIWID16       (_ADI_MSK(0x00000001,uint8_t))   /* UTMIWID: 16-bit UTMI Data Width */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_IRQ_D7                   7                               /* DMA 7 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D6                   6                               /* DMA 6 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D5                   5                               /* DMA 5 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D4                   4                               /* DMA 4 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D3                   3                               /* DMA 3 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D2                   2                               /* DMA 2 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D1                   1                               /* DMA 1 Interrupt Pending Status */
-#define BITP_USB_DMA_IRQ_D0                   0                               /* DMA 0 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D7                  (_ADI_MSK(0x00000080,uint8_t))   /* DMA 7 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D6                  (_ADI_MSK(0x00000040,uint8_t))   /* DMA 6 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D5                  (_ADI_MSK(0x00000020,uint8_t))   /* DMA 5 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D4                  (_ADI_MSK(0x00000010,uint8_t))   /* DMA 4 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D3                  (_ADI_MSK(0x00000008,uint8_t))   /* DMA 3 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D2                  (_ADI_MSK(0x00000004,uint8_t))   /* DMA 2 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D1                  (_ADI_MSK(0x00000002,uint8_t))   /* DMA 1 Interrupt Pending Status */
-#define BITM_USB_DMA_IRQ_D0                  (_ADI_MSK(0x00000001,uint8_t))   /* DMA 0 Interrupt Pending Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_DMA_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_DMA_CTL_BRSTM                9                               /* Burst Mode */
-#define BITP_USB_DMA_CTL_ERR                  8                               /* Bus Error */
-#define BITP_USB_DMA_CTL_EP                   4                               /* DMA Channel Endpoint Assignment */
-#define BITP_USB_DMA_CTL_IE                   3                               /* DMA Interrupt Enable */
-#define BITP_USB_DMA_CTL_MODE                 2                               /* DMA Mode */
-#define BITP_USB_DMA_CTL_DIR                  1                               /* DMA Transfer Direction */
-#define BITP_USB_DMA_CTL_EN                   0                               /* DMA Enable */
-
-#define BITM_USB_DMA_CTL_BRSTM               (_ADI_MSK(0x00000600,uint16_t))  /* Burst Mode */
-#define ENUM_USB_DMA_CTL_BRSTM00             (_ADI_MSK(0x00000000,uint16_t))  /* BRSTM: Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM01             (_ADI_MSK(0x00000200,uint16_t))  /* BRSTM: INCR4 or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM10             (_ADI_MSK(0x00000400,uint16_t))  /* BRSTM: INCR8, INCR4, or Unspecified Length */
-#define ENUM_USB_DMA_CTL_BRSTM11             (_ADI_MSK(0x00000600,uint16_t))  /* BRSTM: INCR16, INCR8, INCR4, or Unspecified Length */
-
-#define BITM_USB_DMA_CTL_ERR                 (_ADI_MSK(0x00000100,uint16_t))  /* Bus Error */
-#define ENUM_USB_DMA_CTL_NO_DMAERR           (_ADI_MSK(0x00000000,uint16_t))  /* ERR: No Status */
-#define ENUM_USB_DMA_CTL_DMAERR              (_ADI_MSK(0x00000100,uint16_t))  /* ERR: Bus Error */
-
-#define BITM_USB_DMA_CTL_EP                  (_ADI_MSK(0x000000F0,uint16_t))  /* DMA Channel Endpoint Assignment */
-#define ENUM_USB_DMA_CTL_DMAEP0              (_ADI_MSK(0x00000000,uint16_t))  /* EP: Endpoint 0 */
-#define ENUM_USB_DMA_CTL_DMAEP1              (_ADI_MSK(0x00000010,uint16_t))  /* EP: Endpoint 1 */
-#define ENUM_USB_DMA_CTL_DMAEP10             (_ADI_MSK(0x000000A0,uint16_t))  /* EP: Endpoint 10 */
-#define ENUM_USB_DMA_CTL_DMAEP11             (_ADI_MSK(0x000000B0,uint16_t))  /* EP: Endpoint 11 */
-#define ENUM_USB_DMA_CTL_DMAEP12             (_ADI_MSK(0x000000C0,uint16_t))  /* EP: Endpoint 12 */
-#define ENUM_USB_DMA_CTL_DMAEP13             (_ADI_MSK(0x000000D0,uint16_t))  /* EP: Endpoint 13 */
-#define ENUM_USB_DMA_CTL_DMAEP14             (_ADI_MSK(0x000000E0,uint16_t))  /* EP: Endpoint 14 */
-#define ENUM_USB_DMA_CTL_DMAEP15             (_ADI_MSK(0x000000F0,uint16_t))  /* EP: Endpoint 15 */
-#define ENUM_USB_DMA_CTL_DMAEP2              (_ADI_MSK(0x00000020,uint16_t))  /* EP: Endpoint 2 */
-#define ENUM_USB_DMA_CTL_DMAEP3              (_ADI_MSK(0x00000030,uint16_t))  /* EP: Endpoint 3 */
-#define ENUM_USB_DMA_CTL_DMAEP4              (_ADI_MSK(0x00000040,uint16_t))  /* EP: Endpoint 4 */
-#define ENUM_USB_DMA_CTL_DMAEP5              (_ADI_MSK(0x00000050,uint16_t))  /* EP: Endpoint 5 */
-#define ENUM_USB_DMA_CTL_DMAEP6              (_ADI_MSK(0x00000060,uint16_t))  /* EP: Endpoint 6 */
-#define ENUM_USB_DMA_CTL_DMAEP7              (_ADI_MSK(0x00000070,uint16_t))  /* EP: Endpoint 7 */
-#define ENUM_USB_DMA_CTL_DMAEP8              (_ADI_MSK(0x00000080,uint16_t))  /* EP: Endpoint 8 */
-#define ENUM_USB_DMA_CTL_DMAEP9              (_ADI_MSK(0x00000090,uint16_t))  /* EP: Endpoint 9 */
-
-#define BITM_USB_DMA_CTL_IE                  (_ADI_MSK(0x00000008,uint16_t))  /* DMA Interrupt Enable */
-#define ENUM_USB_DMA_CTL_DMAINTDIS           (_ADI_MSK(0x00000000,uint16_t))  /* IE: Disable Interrupt */
-#define ENUM_USB_DMA_CTL_DMAINTEN            (_ADI_MSK(0x00000008,uint16_t))  /* IE: Enable Interrupt */
-
-#define BITM_USB_DMA_CTL_MODE                (_ADI_MSK(0x00000004,uint16_t))  /* DMA Mode */
-#define ENUM_USB_DMA_CTL_DMAMODE0            (_ADI_MSK(0x00000000,uint16_t))  /* MODE: DMA Mode 0 */
-#define ENUM_USB_DMA_CTL_DMAMODE1            (_ADI_MSK(0x00000004,uint16_t))  /* MODE: DMA Mode 1 */
-
-#define BITM_USB_DMA_CTL_DIR                 (_ADI_MSK(0x00000002,uint16_t))  /* DMA Transfer Direction */
-#define ENUM_USB_DMA_CTL_DMADIR_RX           (_ADI_MSK(0x00000000,uint16_t))  /* DIR: DMA Write (for Rx Endpoint) */
-#define ENUM_USB_DMA_CTL_DMADIR_TX           (_ADI_MSK(0x00000002,uint16_t))  /* DIR: DMA Read (for Tx Endpoint) */
-
-#define BITM_USB_DMA_CTL_EN                  (_ADI_MSK(0x00000001,uint16_t))  /* DMA Enable */
-#define ENUM_USB_DMA_CTL_DMADIS              (_ADI_MSK(0x00000000,uint16_t))  /* EN: Disable DMA */
-#define ENUM_USB_DMA_CTL_DMAEN               (_ADI_MSK(0x00000001,uint16_t))  /* EN: Enable DMA (Start Transfer) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_UCH                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_UCH_VALUE                 0                               /* Chirp Timeout Value */
-#define BITM_USB_CT_UCH_VALUE                (_ADI_MSK(0x00007FFF,uint16_t))  /* Chirp Timeout Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HHSRTN                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HHSRTN_VALUE              0                               /* Host High Speed Return to Normal Value */
-#define BITM_USB_CT_HHSRTN_VALUE             (_ADI_MSK(0x00007FFF,uint16_t))  /* Host High Speed Return to Normal Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_CT_HSBT                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_CT_HSBT_VALUE                0                               /* HS Timeout Adder */
-#define BITM_USB_CT_HSBT_VALUE               (_ADI_MSK(0x0000000F,uint16_t))  /* HS Timeout Adder */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_ATTR                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_ATTR_EP                 12                               /* Endpoint */
-#define BITP_USB_LPM_ATTR_RMTWAK              8                               /* Remote Wakeup Enable */
-#define BITP_USB_LPM_ATTR_HIRD                4                               /* Host Initiated Resume Duration */
-#define BITP_USB_LPM_ATTR_LINKSTATE           0                               /* Link State */
-#define BITM_USB_LPM_ATTR_EP                 (_ADI_MSK(0x0000F000,uint16_t))  /* Endpoint */
-
-#define BITM_USB_LPM_ATTR_RMTWAK             (_ADI_MSK(0x00000100,uint16_t))  /* Remote Wakeup Enable */
-#define ENUM_USB_LPM_ATTR_RMTWAKDIS          (_ADI_MSK(0x00000000,uint16_t))  /* RMTWAK: Disable Remote Wakeup */
-#define ENUM_USB_LPM_ATTR_RMTWAKEN           (_ADI_MSK(0x00000100,uint16_t))  /* RMTWAK: Enable Remote Wakeup */
-#define BITM_USB_LPM_ATTR_HIRD               (_ADI_MSK(0x000000F0,uint16_t))  /* Host Initiated Resume Duration */
-
-#define BITM_USB_LPM_ATTR_LINKSTATE          (_ADI_MSK(0x0000000F,uint16_t))  /* Link State */
-#define ENUM_USB_LPM_ATTR_LNKSTATE_SSL1      (_ADI_MSK(0x00000001,uint16_t))  /* LINKSTATE: Sleep State (L1) */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_CTL_NAK                  4                               /* LPM NAK Enable */
-#define BITP_USB_LPM_CTL_EN                   2                               /* LPM Enable */
-#define BITP_USB_LPM_CTL_RESUME               1                               /* LPM Resume (Remote Wakeup) */
-#define BITP_USB_LPM_CTL_TX                   0                               /* LPM Transmit */
-#define BITM_USB_LPM_CTL_NAK                 (_ADI_MSK(0x00000010,uint8_t))   /* LPM NAK Enable */
-#define BITM_USB_LPM_CTL_EN                  (_ADI_MSK(0x0000000C,uint8_t))   /* LPM Enable */
-#define BITM_USB_LPM_CTL_RESUME              (_ADI_MSK(0x00000002,uint8_t))   /* LPM Resume (Remote Wakeup) */
-#define BITM_USB_LPM_CTL_TX                  (_ADI_MSK(0x00000001,uint8_t))   /* LPM Transmit */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IEN                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IEN_LPMERR               5                               /* LPM Error Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMRES               4                               /* LPM Resume Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNC                3                               /* LPM NYET Control Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMACK               2                               /* LPM ACK Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMNY                1                               /* LPM NYET Interrupt Enable */
-#define BITP_USB_LPM_IEN_LPMST                0                               /* LPM STALL Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt Enable */
-#define BITM_USB_LPM_IEN_LPMST               (_ADI_MSK(0x00000001,uint8_t))   /* LPM STALL Interrupt Enable */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_IRQ                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_IRQ_LPMERR               5                               /* LPM Error Interrupt */
-#define BITP_USB_LPM_IRQ_LPMRES               4                               /* LPM Resume Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNC                3                               /* LPM NYET Control Interrupt */
-#define BITP_USB_LPM_IRQ_LPMACK               2                               /* LPM ACK Interrupt */
-#define BITP_USB_LPM_IRQ_LPMNY                1                               /* LPM NYET Interrupt */
-#define BITP_USB_LPM_IRQ_LPMST                0
-#define BITM_USB_LPM_IRQ_LPMERR              (_ADI_MSK(0x00000020,uint8_t))   /* LPM Error Interrupt */
-#define BITM_USB_LPM_IRQ_LPMRES              (_ADI_MSK(0x00000010,uint8_t))   /* LPM Resume Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNC               (_ADI_MSK(0x00000008,uint8_t))   /* LPM NYET Control Interrupt */
-#define BITM_USB_LPM_IRQ_LPMACK              (_ADI_MSK(0x00000004,uint8_t))   /* LPM ACK Interrupt */
-#define BITM_USB_LPM_IRQ_LPMNY               (_ADI_MSK(0x00000002,uint8_t))   /* LPM NYET Interrupt */
-#define BITM_USB_LPM_IRQ_LPMST               (_ADI_MSK(0x00000001,uint8_t))
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_LPM_FADDR                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_LPM_FADDR_VALUE              0                               /* Function Address Value */
-#define BITM_USB_LPM_FADDR_VALUE             (_ADI_MSK(0x0000007F,uint8_t))   /* Function Address Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_VBUS_CTL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_VBUS_CTL_DRV                 4                               /* VBUS Drive */
-#define BITP_USB_VBUS_CTL_DRVINT              3                               /* VBUS Drive Interrupt */
-#define BITP_USB_VBUS_CTL_DRVIEN              2                               /* VBUS Drive Interrupt Enable */
-#define BITP_USB_VBUS_CTL_DRVOD               1                               /* VBUS Drive Open Drain */
-#define BITP_USB_VBUS_CTL_INVDRV              0                               /* VBUS Invert Drive */
-#define BITM_USB_VBUS_CTL_DRV                (_ADI_MSK(0x00000010,uint8_t))   /* VBUS Drive */
-#define BITM_USB_VBUS_CTL_DRVINT             (_ADI_MSK(0x00000008,uint8_t))   /* VBUS Drive Interrupt */
-#define BITM_USB_VBUS_CTL_DRVIEN             (_ADI_MSK(0x00000004,uint8_t))   /* VBUS Drive Interrupt Enable */
-#define BITM_USB_VBUS_CTL_DRVOD              (_ADI_MSK(0x00000002,uint8_t))   /* VBUS Drive Open Drain */
-#define BITM_USB_VBUS_CTL_INVDRV             (_ADI_MSK(0x00000001,uint8_t))   /* VBUS Invert Drive */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_BAT_CHG                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_BAT_CHG_DEDCHG               4                               /* Dedicated Charging Port */
-#define BITP_USB_BAT_CHG_CHGDET               3                               /* Charging Port Detected */
-#define BITP_USB_BAT_CHG_SNSCHGDET            2                               /* Sense Charger Detection */
-#define BITP_USB_BAT_CHG_CONDET               1                               /* Connected Detected */
-#define BITP_USB_BAT_CHG_SNSCONDET            0                               /* Sense Connection Detection */
-#define BITM_USB_BAT_CHG_DEDCHG              (_ADI_MSK(0x00000010,uint8_t))   /* Dedicated Charging Port */
-#define BITM_USB_BAT_CHG_CHGDET              (_ADI_MSK(0x00000008,uint8_t))   /* Charging Port Detected */
-#define BITM_USB_BAT_CHG_SNSCHGDET           (_ADI_MSK(0x00000004,uint8_t))   /* Sense Charger Detection */
-#define BITM_USB_BAT_CHG_CONDET              (_ADI_MSK(0x00000002,uint8_t))   /* Connected Detected */
-#define BITM_USB_BAT_CHG_SNSCONDET           (_ADI_MSK(0x00000001,uint8_t))   /* Sense Connection Detection */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PHY_CTL                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PHY_CTL_EN                   7                               /* PHY Enable */
-#define BITP_USB_PHY_CTL_RESTORE              1                               /* Restore from Hibernate */
-#define BITP_USB_PHY_CTL_HIBER                0                               /* Hibernate */
-#define BITM_USB_PHY_CTL_EN                  (_ADI_MSK(0x00000080,uint8_t))   /* PHY Enable */
-#define BITM_USB_PHY_CTL_RESTORE             (_ADI_MSK(0x00000002,uint8_t))   /* Restore from Hibernate */
-#define BITM_USB_PHY_CTL_HIBER               (_ADI_MSK(0x00000001,uint8_t))   /* Hibernate */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        USB_PLL_OSC                          Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_USB_PLL_OSC_PLLMSEL              7                               /* PLL Multiplier Select */
-#define BITP_USB_PLL_OSC_PLLM                 1                               /* PLL Multiplier Value */
-#define BITP_USB_PLL_OSC_DIVCLKIN             0                               /* Divide CLKIN */
-#define BITM_USB_PLL_OSC_PLLMSEL             (_ADI_MSK(0x00000080,uint16_t))  /* PLL Multiplier Select */
-#define BITM_USB_PLL_OSC_PLLM                (_ADI_MSK(0x0000007E,uint16_t))  /* PLL Multiplier Value */
-#define BITM_USB_PLL_OSC_DIVCLKIN            (_ADI_MSK(0x00000001,uint16_t))  /* Divide CLKIN */
-
-/* ==================================================
-        Data Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1DM0
-   ========================= */
-#define SRAM_BASE_ADDRESS               0xFFE00000         /* SRAM Base Address */
-#define DMEM_CONTROL                    0xFFE00004         /* Data memory control */
-#define DCPLB_STATUS                    0xFFE00008         /* Data Cacheability Protection Lookaside Buffer Status */
-#define DCPLB_FAULT_STATUS              0xFFE00008         /*     Older definition or alias of above */
-#define DCPLB_FAULT_ADDR                0xFFE0000C         /* Data Cacheability Protection Lookaside Buffer Fault Address */
-#define DCPLB_ADDR0                     0xFFE00100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR1                     0xFFE00104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR2                     0xFFE00108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR3                     0xFFE0010C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR4                     0xFFE00110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR5                     0xFFE00114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR6                     0xFFE00118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR7                     0xFFE0011C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR8                     0xFFE00120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR9                     0xFFE00124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR10                    0xFFE00128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR11                    0xFFE0012C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR12                    0xFFE00130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR13                    0xFFE00134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR14                    0xFFE00138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_ADDR15                    0xFFE0013C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define DCPLB_DATA0                     0xFFE00200         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA1                     0xFFE00204         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA2                     0xFFE00208         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA3                     0xFFE0020C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA4                     0xFFE00210         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA5                     0xFFE00214         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA6                     0xFFE00218         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA7                     0xFFE0021C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA8                     0xFFE00220         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA9                     0xFFE00224         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA10                    0xFFE00228         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA11                    0xFFE0022C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA12                    0xFFE00230         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA13                    0xFFE00234         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA14                    0xFFE00238         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DCPLB_DATA15                    0xFFE0023C         /* Cacheability Protection Lookaside Buffer Descriptor Data */
-#define DTEST_COMMAND                   0xFFE00300         /* Data Test Command Register */
-#define DTEST_DATA0                     0xFFE00400         /* Data Test Data Register */
-#define DTEST_DATA1                     0xFFE00404         /* Data Test Data Register */
-#define L1DBNKA_PELOC                   0xFFE00408         /* Data Bank A Parity Error Location */
-#define L1DBNKB_PELOC                   0xFFE0040C         /* Data Bank B Parity Error Location */
-
-/* =========================
-        L1DM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        SRAM_BASE_ADDRESS                    Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_SRAM_BASE_ADDRESS_ADDR          22                               /* SRAM Base Address */
-#define BITM_SRAM_BASE_ADDRESS_ADDR          (_ADI_MSK(0xFFC00000,uint32_t))  /* SRAM Base Address */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DMEM_CONTROL_PARCTL             15                               /* L1 Scratch Parity Control */
-#define BITP_DMEM_CONTROL_PARSEL             14                               /* L1 Scratch Parity Select */
-#define BITP_DMEM_CONTROL_PPREF1             13                               /* DAG1 Port Preference */
-#define BITP_DMEM_CONTROL_PPREF0             12                               /* DAG0 Port Preference */
-#define BITP_DMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_DMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_DMEM_CONTROL_DCBS                4                               /* L1 Data Cache Bank Select */
-#define BITP_DMEM_CONTROL_CFG                 2                               /* Data Memory Configuration */
-#define BITP_DMEM_CONTROL_ENCPLB              1                               /* Enable DCPLB */
-
-#define BITM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* L1 Scratch Parity Control */
-#define ENUM_DMEM_CONTROL_NO_PARCTL          (_ADI_MSK(0x00000000,uint32_t))  /* PARCTL: No Parity Control  (Normal Behavior for L1 RD / L1 WT) */
-#define ENUM_DMEM_CONTROL_PARCTL             (_ADI_MSK(0x00008000,uint32_t))  /* PARCTL: Parity Control Enabled */
-#define BITM_DMEM_CONTROL_PARSEL             (_ADI_MSK(0x00004000,uint32_t))  /* L1 Scratch Parity Select */
-
-#define BITM_DMEM_CONTROL_PPREF1             (_ADI_MSK(0x00002000,uint32_t))  /* DAG1 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF1A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF1B            (_ADI_MSK(0x00002000,uint32_t))  /* PPREF1: DAG1 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_PPREF0             (_ADI_MSK(0x00001000,uint32_t))  /* DAG0 Port Preference */
-#define ENUM_DMEM_CONTROL_PPREF0A            (_ADI_MSK(0x00000000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port A */
-#define ENUM_DMEM_CONTROL_PPREF0B            (_ADI_MSK(0x00001000,uint32_t))  /* PPREF0: DAG0 Non-cacheable Fetches Use Port B */
-
-#define BITM_DMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_DMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_DMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_DMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_DMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_DMEM_CONTROL_DCBS               (_ADI_MSK(0x00000010,uint32_t))  /* L1 Data Cache Bank Select */
-#define ENUM_DMEM_CONTROL_DCBS14             (_ADI_MSK(0x00000000,uint32_t))  /* DCBS: Address bit 14 used to select Bank A or B for cache access */
-#define ENUM_DMEM_CONTROL_DCBS23             (_ADI_MSK(0x00000010,uint32_t))  /* DCBS: Address bit 23 used to select Bank A or B for cache access */
-
-#define BITM_DMEM_CONTROL_CFG                (_ADI_MSK(0x0000000C,uint32_t))  /* Data Memory Configuration */
-#define ENUM_DMEM_CONTROL_ASRAM_BSRAM        (_ADI_MSK(0x00000000,uint32_t))  /* CFG: A SRAM, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BSRAM       (_ADI_MSK(0x00000008,uint32_t))  /* CFG: A Cache, B SRAM */
-#define ENUM_DMEM_CONTROL_ACACHE_BCACHE      (_ADI_MSK(0x0000000C,uint32_t))  /* CFG: A Cache, B Cache */
-
-#define BITM_DMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable DCPLB */
-#define ENUM_DMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs Disabled */
-#define ENUM_DMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs Enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_DCPLB_STATUS_DAG                18                               /* Access DAG */
-#define BITP_DCPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_DCPLB_STATUS_RW                 16                               /* Access Read/Write */
-#define BITP_DCPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_DCPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_DCPLB_STATUS_DAG                (_ADI_MSK(0x00040000,uint32_t))  /* Access DAG */
-#define BITM_DCPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_DCPLB_STATUS_RW                 (_ADI_MSK(0x00010000,uint32_t))  /* Access Read/Write */
-#define BITM_DCPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_DCPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DCPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DCPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_DCPLB_DATA_WT                   14                               /* CPLB Write Through */
-#define BITP_DCPLB_DATA_L2_CHBL              13                               /* CPLB L2 Cacheable */
-#define BITP_DCPLB_DATA_L1_CHBL              12                               /* CPLB L1 Cacheable */
-#define BITP_DCPLB_DATA_DIRTY                 7                               /* CPLB DIRTY */
-#define BITP_DCPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_DCPLB_DATA_SWRITE                4                               /* CPLB Supervisor Write */
-#define BITP_DCPLB_DATA_UWRITE                3                               /* CPLB User Write */
-#define BITP_DCPLB_DATA_UREAD                 2                               /* CPLB User Read */
-#define BITP_DCPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_DCPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_DCPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_DCPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_DCPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_DCPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_DCPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_DCPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_DCPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_DCPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_DCPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* CPLB Write Through */
-#define ENUM_DCPLB_DATA_WB                   (_ADI_MSK(0x00000000,uint32_t))  /* WT: Write-back */
-#define ENUM_DCPLB_DATA_WT                   (_ADI_MSK(0x00004000,uint32_t))  /* WT: Write-through */
-
-#define BITM_DCPLB_DATA_L2_CHBL              (_ADI_MSK(0x00002000,uint32_t))  /* CPLB L2 Cacheable */
-#define ENUM_DCPLB_DATA_L2CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L2CHBL: Non-cacheable in L2 */
-#define ENUM_DCPLB_DATA_L2CHBL_EN            (_ADI_MSK(0x00002000,uint32_t))  /* L2CHBL: Cacheable in L2 */
-
-#define BITM_DCPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* CPLB L1 Cacheable */
-#define ENUM_DCPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_DCPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* CPLB DIRTY */
-#define ENUM_DCPLB_DATA_CLEAN                (_ADI_MSK(0x00000000,uint32_t))  /* DIRTY: Clean */
-#define ENUM_DCPLB_DATA_DIRTY                (_ADI_MSK(0x00000080,uint32_t))  /* DIRTY: Dirty */
-#define BITM_DCPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* CPLB Supervisor Write */
-#define ENUM_DCPLB_DATA_NO_SWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* SWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_SWRITE               (_ADI_MSK(0x00000010,uint32_t))  /* SWRITE: Write Access Allowed (Supervisor Mode) */
-
-#define BITM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* CPLB User Write */
-#define ENUM_DCPLB_DATA_NO_UWRITE            (_ADI_MSK(0x00000000,uint32_t))  /* UWRITE: No Write Access */
-#define ENUM_DCPLB_DATA_UWRITE               (_ADI_MSK(0x00000008,uint32_t))  /* UWRITE: Write Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* CPLB User Read */
-#define ENUM_DCPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_DCPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_DCPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_DCPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_DCPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_DCPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid Entry */
-#define ENUM_DCPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        DTEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DTEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_DTEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_DTEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bit 11 */
-#define BITP_DTEST_COMMAND_IDSEL             24                               /* Instruction/Data Access */
-#define BITP_DTEST_COMMAND_BNKSEL            23                               /* Data Bank Access */
-#define BITP_DTEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_DTEST_COMMAND_SEL16K            14                               /* Address bit 14 */
-#define BITP_DTEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_DTEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_DTEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_DTEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_DTEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_DTEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_DTEST_COMMAND_WAYSEL            (_ADI_MSK(0x04000000,uint32_t))  /* Access Way/Instruction Address Bit 11 */
-#define BITM_DTEST_COMMAND_IDSEL             (_ADI_MSK(0x01000000,uint32_t))  /* Instruction/Data Access */
-#define BITM_DTEST_COMMAND_BNKSEL            (_ADI_MSK(0x00800000,uint32_t))  /* Data Bank Access */
-#define BITM_DTEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_DTEST_COMMAND_SEL16K            (_ADI_MSK(0x00004000,uint32_t))  /* Address bit 14 */
-#define BITM_DTEST_COMMAND_SET               (_ADI_MSK(0x000007E0,uint32_t))  /* Set Index */
-#define BITM_DTEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_DTEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_DTEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKA_PELOC_SCRATCH_MEM       12                               /* Scratch Memory Parity Status */
-#define BITP_L1DBNKA_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_SCRATCH_MEM       (_ADI_MSK(0x00001000,uint32_t))  /* Scratch Memory Parity Status */
-#define BITM_L1DBNKA_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1DBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1DBNKB_PELOC_TAGPAIR            8                               /* Tag Parity Status */
-#define BITP_L1DBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1DBNKB_PELOC_TAGPAIR           (_ADI_MSK(0x00000300,uint32_t))  /* Tag Parity Status */
-#define BITM_L1DBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Instruction Memory Unit Registers
-   ================================================== */
-
-/* =========================
-        L1IM0
-   ========================= */
-#define IMEM_CONTROL                    0xFFE01004         /* Instruction memory control */
-#define ICPLB_STATUS                    0xFFE01008         /* Cacheability Protection Lookaside Buffer Status */
-#define CODE_FAULT_STATUS               0xFFE01008         /*     Older definition or alias of above */
-#define ICPLB_FAULT_ADDR                0xFFE0100C         /* Cacheability Protection Lookaside Buffer Fault Address */
-#define CODE_FAULT_ADDR                 0xFFE0100C         /*     Older definition or alias of above */
-#define ICPLB_ADDR0                     0xFFE01100         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR1                     0xFFE01104         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR2                     0xFFE01108         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR3                     0xFFE0110C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR4                     0xFFE01110         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR5                     0xFFE01114         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR6                     0xFFE01118         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR7                     0xFFE0111C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR8                     0xFFE01120         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR9                     0xFFE01124         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR10                    0xFFE01128         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR11                    0xFFE0112C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR12                    0xFFE01130         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR13                    0xFFE01134         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR14                    0xFFE01138         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_ADDR15                    0xFFE0113C         /* Cacheability Protection Lookaside Buffer Descriptor Address */
-#define ICPLB_DATA0                     0xFFE01200         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA1                     0xFFE01204         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA2                     0xFFE01208         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA3                     0xFFE0120C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA4                     0xFFE01210         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA5                     0xFFE01214         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA6                     0xFFE01218         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA7                     0xFFE0121C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA8                     0xFFE01220         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA9                     0xFFE01224         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA10                    0xFFE01228         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA11                    0xFFE0122C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA12                    0xFFE01230         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA13                    0xFFE01234         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA14                    0xFFE01238         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ICPLB_DATA15                    0xFFE0123C         /* Cacheability Protection Lookaside Buffer Descriptor Status */
-#define ITEST_COMMAND                   0xFFE01300         /* Instruction Test Command Register */
-#define ITEST_DATA0                     0xFFE01400         /* Instruction Test Data Register */
-#define ITEST_DATA1                     0xFFE01404         /* Instruction Test Data Register */
-#define L1IBNKA_PELOC                   0xFFE01408         /* Instruction Bank A Parity Error Location */
-#define L1IBNKB_PELOC                   0xFFE0140C         /* Instruction Bank B Parity Error Location */
-#define L1IBNKC_PELOC                   0xFFE01410         /* Instruction Bank C Parity Error Location */
-
-/* =========================
-        L1IM
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMEM_CONTROL                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMEM_CONTROL_LRUPRIORST         13                               /* LRU Priority Reset */
-#define BITP_IMEM_CONTROL_RDCHK               9                               /* Read Parity Checking */
-#define BITP_IMEM_CONTROL_CBYPASS             8                               /* Cache Bypass */
-#define BITP_IMEM_CONTROL_LOC                 3                               /* Cache Way Lock */
-#define BITP_IMEM_CONTROL_CFG                 2                               /* Configure L1 code memory as cache */
-#define BITP_IMEM_CONTROL_ENCPLB              1                               /* Enable ICPLB */
-
-#define BITM_IMEM_CONTROL_LRUPRIORST         (_ADI_MSK(0x00002000,uint32_t))  /* LRU Priority Reset */
-#define ENUM_IMEM_CONTROL_LRUPRIO_EN         (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIORST: LRU Priority functionality is enabled */
-#define ENUM_IMEM_CONTROL_LRUPRIO_CLR        (_ADI_MSK(0x00002000,uint32_t))  /* LRUPRIORST: All cached LRU priority bits are cleared */
-
-#define BITM_IMEM_CONTROL_RDCHK              (_ADI_MSK(0x00000200,uint32_t))  /* Read Parity Checking */
-#define ENUM_IMEM_CONTROL_RDCHK_DIS          (_ADI_MSK(0x00000000,uint32_t))  /* RDCHK: Read Parity Checking Disabled */
-#define ENUM_IMEM_CONTROL_RDCHK_EN           (_ADI_MSK(0x00000200,uint32_t))  /* RDCHK: Read Parity Checking Enabled */
-
-#define BITM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* Cache Bypass */
-#define ENUM_IMEM_CONTROL_NO_CBYPASS         (_ADI_MSK(0x00000000,uint32_t))  /* CBYPASS: Normal Cache Behavior */
-#define ENUM_IMEM_CONTROL_CBYPASS            (_ADI_MSK(0x00000100,uint32_t))  /* CBYPASS: Cache Bypassed */
-
-#define BITM_IMEM_CONTROL_LOC                (_ADI_MSK(0x00000078,uint32_t))  /* Cache Way Lock */
-#define ENUM_IMEM_CONTROL_WAYLOCK_NONE       (_ADI_MSK(0x00000000,uint32_t))  /* LOC: All Ways Not Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_0          (_ADI_MSK(0x00000008,uint32_t))  /* LOC: Way3, Way2, Way1 Not Locked, Way0 Locked */
-#define ENUM_IMEM_CONTROL_WAYLOCK_ALL        (_ADI_MSK(0x00000078,uint32_t))  /* LOC: All Ways Locked */
-
-#define BITM_IMEM_CONTROL_CFG                (_ADI_MSK(0x00000004,uint32_t))  /* Configure L1 code memory as cache */
-#define ENUM_IMEM_CONTROL_CFG_SRAM           (_ADI_MSK(0x00000000,uint32_t))  /* CFG: L1 Instruction Memory Configured as SRAM */
-#define ENUM_IMEM_CONTROL_CFG_CACHE          (_ADI_MSK(0x00000004,uint32_t))  /* CFG: L1 Instruction Memory Configures as Cache */
-
-#define BITM_IMEM_CONTROL_ENCPLB             (_ADI_MSK(0x00000002,uint32_t))  /* Enable ICPLB */
-#define ENUM_IMEM_CONTROL_CPLB_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* ENCPLB: CPLBs disabled */
-#define ENUM_IMEM_CONTROL_CPLB_EN            (_ADI_MSK(0x00000002,uint32_t))  /* ENCPLB: CPLBs enabled */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_STATUS                         Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_STATUS_ILLADDR            19                               /* Illegal Address */
-#define BITP_ICPLB_STATUS_MODE               17                               /* Access Mode */
-#define BITP_ICPLB_STATUS_FAULT               0                               /* Fault Status */
-#define BITM_ICPLB_STATUS_ILLADDR            (_ADI_MSK(0x00080000,uint32_t))  /* Illegal Address */
-#define BITM_ICPLB_STATUS_MODE               (_ADI_MSK(0x00020000,uint32_t))  /* Access Mode */
-#define BITM_ICPLB_STATUS_FAULT              (_ADI_MSK(0x0000FFFF,uint32_t))  /* Fault Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_ADDR                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_ADDR_ADDR                 10                               /* Address for match */
-#define BITM_ICPLB_ADDR_ADDR                 (_ADI_MSK(0xFFFFFC00,uint32_t))  /* Address for match */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ICPLB_DATA                           Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ICPLB_DATA_PSIZE                16                               /* Page Size */
-#define BITP_ICPLB_DATA_L1_CHBL              12                               /* L1 Cacheable */
-#define BITP_ICPLB_DATA_LRUPRIO               8                               /* Least Recently Used Priority */
-#define BITP_ICPLB_DATA_L1SRAM                5                               /* CPLB L1SRAM */
-#define BITP_ICPLB_DATA_UREAD                 2                               /* Allow User Read */
-#define BITP_ICPLB_DATA_LOCK                  1                               /* CPLB Lock */
-#define BITP_ICPLB_DATA_VALID                 0                               /* CPLB Valid */
-
-#define BITM_ICPLB_DATA_PSIZE                (_ADI_MSK(0x00070000,uint32_t))  /* Page Size */
-#define ENUM_ICPLB_DATA_1KB                  (_ADI_MSK(0x00000000,uint32_t))  /* PSIZE: 1 KB Page Size */
-#define ENUM_ICPLB_DATA_4KB                  (_ADI_MSK(0x00010000,uint32_t))  /* PSIZE: 4 KB Page Size */
-#define ENUM_ICPLB_DATA_1MB                  (_ADI_MSK(0x00020000,uint32_t))  /* PSIZE: 1 MB Page Size */
-#define ENUM_ICPLB_DATA_4MB                  (_ADI_MSK(0x00030000,uint32_t))  /* PSIZE: 4 MB Page Size */
-#define ENUM_ICPLB_DATA_16KB                 (_ADI_MSK(0x00040000,uint32_t))  /* PSIZE: 16 KB Page Size */
-#define ENUM_ICPLB_DATA_64KB                 (_ADI_MSK(0x00050000,uint32_t))  /* PSIZE: 64 KB Page Size */
-#define ENUM_ICPLB_DATA_16MB                 (_ADI_MSK(0x00060000,uint32_t))  /* PSIZE: 16 MB Page Size */
-#define ENUM_ICPLB_DATA_64MB                 (_ADI_MSK(0x00070000,uint32_t))  /* PSIZE: 64 MB Page Size */
-
-#define BITM_ICPLB_DATA_L1_CHBL              (_ADI_MSK(0x00001000,uint32_t))  /* L1 Cacheable */
-#define ENUM_ICPLB_DATA_L1CHBL_DIS           (_ADI_MSK(0x00000000,uint32_t))  /* L1CHBL: Non-cacheable in L1 */
-#define ENUM_ICPLB_DATA_L1CHBL_EN            (_ADI_MSK(0x00001000,uint32_t))  /* L1CHBL: Cacheable in L1 */
-
-#define BITM_ICPLB_DATA_LRUPRIO              (_ADI_MSK(0x00000100,uint32_t))  /* Least Recently Used Priority */
-#define ENUM_ICPLB_DATA_LRUPRIO_LO           (_ADI_MSK(0x00000000,uint32_t))  /* LRUPRIO: Low Importance */
-#define ENUM_ICPLB_DATA_LRUPRIO_HI           (_ADI_MSK(0x00000100,uint32_t))  /* LRUPRIO: High Importance */
-#define BITM_ICPLB_DATA_L1SRAM               (_ADI_MSK(0x00000020,uint32_t))  /* CPLB L1SRAM */
-
-#define BITM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* Allow User Read */
-#define ENUM_ICPLB_DATA_NO_UREAD             (_ADI_MSK(0x00000000,uint32_t))  /* UREAD: No Read Access */
-#define ENUM_ICPLB_DATA_UREAD                (_ADI_MSK(0x00000004,uint32_t))  /* UREAD: Read Access Allowed (User Mode) */
-
-#define BITM_ICPLB_DATA_LOCK                 (_ADI_MSK(0x00000002,uint32_t))  /* CPLB Lock */
-#define ENUM_ICPLB_DATA_REPLACEABLE          (_ADI_MSK(0x00000000,uint32_t))  /* LOCK: Entry May Be Replaced */
-#define ENUM_ICPLB_DATA_LOCKED               (_ADI_MSK(0x00000002,uint32_t))  /* LOCK: Entry Locked */
-
-#define BITM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* CPLB Valid */
-#define ENUM_ICPLB_DATA_INVALID              (_ADI_MSK(0x00000000,uint32_t))  /* VALID: Invalid (disabled) CPLB Entry */
-#define ENUM_ICPLB_DATA_VALID                (_ADI_MSK(0x00000001,uint32_t))  /* VALID: Valid (enabled) CPLB Entry */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ITEST_COMMAND                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ITEST_COMMAND_PARCTL            30                               /* Parity Control */
-#define BITP_ITEST_COMMAND_PARSEL            29                               /* Parity Select */
-#define BITP_ITEST_COMMAND_WAYSEL            26                               /* Access Way/Instruction Address Bits 11:10 */
-#define BITP_ITEST_COMMAND_SBNK              16                               /* Subbank Access */
-#define BITP_ITEST_COMMAND_SET                5                               /* Set Index */
-#define BITP_ITEST_COMMAND_DW                 3                               /* Double Word Index */
-#define BITP_ITEST_COMMAND_TAGSELB            2                               /* Array Access */
-#define BITP_ITEST_COMMAND_RW                 1                               /* Read/Write Access */
-#define BITM_ITEST_COMMAND_PARCTL            (_ADI_MSK(0x40000000,uint32_t))  /* Parity Control */
-#define BITM_ITEST_COMMAND_PARSEL            (_ADI_MSK(0x20000000,uint32_t))  /* Parity Select */
-#define BITM_ITEST_COMMAND_WAYSEL            (_ADI_MSK(0x0C000000,uint32_t))  /* Access Way/Instruction Address Bits 11:10 */
-#define BITM_ITEST_COMMAND_SBNK              (_ADI_MSK(0x00030000,uint32_t))  /* Subbank Access */
-#define BITM_ITEST_COMMAND_SET               (_ADI_MSK(0x000003E0,uint32_t))  /* Set Index */
-#define BITM_ITEST_COMMAND_DW                (_ADI_MSK(0x00000018,uint32_t))  /* Double Word Index */
-#define BITM_ITEST_COMMAND_TAGSELB           (_ADI_MSK(0x00000004,uint32_t))  /* Array Access */
-#define BITM_ITEST_COMMAND_RW                (_ADI_MSK(0x00000002,uint32_t))  /* Read/Write Access */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKA_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKA_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKA_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKB_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKB_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKB_PELOC_MEMBLK            (_ADI_MSK(0x000000FF,uint32_t))  /* Memory Parity Status */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        L1IBNKC_PELOC                        Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_L1IBNKC_PELOC_TAGPAIR            4                               /* Tag Parity Status */
-#define BITP_L1IBNKC_PELOC_MEMBLK             0                               /* Memory Parity Status */
-#define BITM_L1IBNKC_PELOC_TAGPAIR           (_ADI_MSK(0x00000030,uint32_t))  /* Tag Parity Status */
-#define BITM_L1IBNKC_PELOC_MEMBLK            (_ADI_MSK(0x0000000F,uint32_t))  /* Memory Parity Status */
-
-/* ==================================================
-        Interrupt Controller Registers
-   ================================================== */
-
-/* =========================
-        ICU0
-   ========================= */
-#define EVT0                            0xFFE02000         /* Event Vector */
-#define EVT1                            0xFFE02004         /* Event Vector */
-#define EVT2                            0xFFE02008         /* Event Vector */
-#define EVT3                            0xFFE0200C         /* Event Vector */
-#define EVT4                            0xFFE02010         /* Event Vector */
-#define EVT5                            0xFFE02014         /* Event Vector */
-#define EVT6                            0xFFE02018         /* Event Vector */
-#define EVT7                            0xFFE0201C         /* Event Vector */
-#define EVT8                            0xFFE02020         /* Event Vector */
-#define EVT9                            0xFFE02024         /* Event Vector */
-#define EVT10                           0xFFE02028         /* Event Vector */
-#define EVT11                           0xFFE0202C         /* Event Vector */
-#define EVT12                           0xFFE02030         /* Event Vector */
-#define EVT13                           0xFFE02034         /* Event Vector */
-#define EVT14                           0xFFE02038         /* Event Vector */
-#define EVT15                           0xFFE0203C         /* Event Vector */
-#define IMASK                           0xFFE02104         /* Interrupt Mask Register */
-#define IPEND                           0xFFE02108         /* Interrupts Pending Register */
-#define ILAT                            0xFFE0210C         /* Interrupt Latch Register */
-#define IPRIO                           0xFFE02110         /* Interrupt Priority Register */
-#define CEC_SID                         0xFFE02118         /* Core System Interrupt ID */
-
-/* =========================
-        ICU
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        IMASK                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IMASK_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IMASK_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IMASK_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IMASK_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IMASK_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IMASK_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IMASK_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IMASK_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IMASK_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IMASK_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IMASK_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IMASK_UNMASKABLE                 0                               /* Unmaskable interrupts */
-#define BITM_IMASK_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IMASK_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IMASK_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IMASK_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IMASK_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IMASK_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IMASK_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IMASK_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IMASK_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IMASK_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IMASK_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IMASK_UNMASKABLE                (_ADI_MSK(0x0000001F,uint32_t))  /* Unmaskable interrupts */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPEND                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPEND_IVG15                     15                               /* IVG15 interrupt bit position */
-#define BITP_IPEND_IVG14                     14                               /* IVG14 interrupt bit position */
-#define BITP_IPEND_IVG13                     13                               /* IVG13 interrupt bit position */
-#define BITP_IPEND_IVG12                     12                               /* IVG12 interrupt bit position */
-#define BITP_IPEND_IVG11                     11                               /* IVG11 interrupt bit position */
-#define BITP_IPEND_IVG10                     10                               /* IVG10 interrupt bit position */
-#define BITP_IPEND_IVG9                       9                               /* IVG9 interrupt bit position */
-#define BITP_IPEND_IVG8                       8                               /* IVG8 interrupt bit position */
-#define BITP_IPEND_IVG7                       7                               /* IVG7 interrupt bit position */
-#define BITP_IPEND_IVTMR                      6                               /* Timer interrupt bit position */
-#define BITP_IPEND_IVHW                       5                               /* Hardware Error interrupt bit position */
-#define BITP_IPEND_IRPTEN                     4                               /* Global interrupt enable bit position */
-#define BITP_IPEND_EVX                        3                               /* Exception bit position */
-#define BITP_IPEND_NMI                        2                               /* Non Maskable interrupt bit position */
-#define BITP_IPEND_RST                        1                               /* Reset interrupt bit position */
-#define BITP_IPEND_EMU                        0                               /* Emulator interrupt bit position */
-#define BITM_IPEND_IVG15                     (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_IPEND_IVG14                     (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_IPEND_IVG13                     (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_IPEND_IVG12                     (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_IPEND_IVG11                     (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_IPEND_IVG10                     (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_IPEND_IVG9                      (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_IPEND_IVG8                      (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_IPEND_IVG7                      (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_IPEND_IVTMR                     (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_IPEND_IVHW                      (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_IPEND_IRPTEN                    (_ADI_MSK(0x00000010,uint32_t))  /* Global interrupt enable bit position */
-#define BITM_IPEND_EVX                       (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_IPEND_NMI                       (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_IPEND_RST                       (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_IPEND_EMU                       (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        ILAT                                 Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_ILAT_IVG15                      15                               /* IVG15 interrupt bit position */
-#define BITP_ILAT_IVG14                      14                               /* IVG14 interrupt bit position */
-#define BITP_ILAT_IVG13                      13                               /* IVG13 interrupt bit position */
-#define BITP_ILAT_IVG12                      12                               /* IVG12 interrupt bit position */
-#define BITP_ILAT_IVG11                      11                               /* IVG11 interrupt bit position */
-#define BITP_ILAT_IVG10                      10                               /* IVG10 interrupt bit position */
-#define BITP_ILAT_IVG9                        9                               /* IVG9 interrupt bit position */
-#define BITP_ILAT_IVG8                        8                               /* IVG8 interrupt bit position */
-#define BITP_ILAT_IVG7                        7                               /* IVG7 interrupt bit position */
-#define BITP_ILAT_IVTMR                       6                               /* Timer interrupt bit position */
-#define BITP_ILAT_IVHW                        5                               /* Hardware Error interrupt bit position */
-#define BITP_ILAT_EVX                         3                               /* Exception bit position */
-#define BITP_ILAT_NMI                         2                               /* Non Maskable interrupt bit position */
-#define BITP_ILAT_RST                         1                               /* Reset interrupt bit position */
-#define BITP_ILAT_EMU                         0                               /* Emulator interrupt bit position */
-#define BITM_ILAT_IVG15                      (_ADI_MSK(0x00008000,uint32_t))  /* IVG15 interrupt bit position */
-#define BITM_ILAT_IVG14                      (_ADI_MSK(0x00004000,uint32_t))  /* IVG14 interrupt bit position */
-#define BITM_ILAT_IVG13                      (_ADI_MSK(0x00002000,uint32_t))  /* IVG13 interrupt bit position */
-#define BITM_ILAT_IVG12                      (_ADI_MSK(0x00001000,uint32_t))  /* IVG12 interrupt bit position */
-#define BITM_ILAT_IVG11                      (_ADI_MSK(0x00000800,uint32_t))  /* IVG11 interrupt bit position */
-#define BITM_ILAT_IVG10                      (_ADI_MSK(0x00000400,uint32_t))  /* IVG10 interrupt bit position */
-#define BITM_ILAT_IVG9                       (_ADI_MSK(0x00000200,uint32_t))  /* IVG9 interrupt bit position */
-#define BITM_ILAT_IVG8                       (_ADI_MSK(0x00000100,uint32_t))  /* IVG8 interrupt bit position */
-#define BITM_ILAT_IVG7                       (_ADI_MSK(0x00000080,uint32_t))  /* IVG7 interrupt bit position */
-#define BITM_ILAT_IVTMR                      (_ADI_MSK(0x00000040,uint32_t))  /* Timer interrupt bit position */
-#define BITM_ILAT_IVHW                       (_ADI_MSK(0x00000020,uint32_t))  /* Hardware Error interrupt bit position */
-#define BITM_ILAT_EVX                        (_ADI_MSK(0x00000008,uint32_t))  /* Exception bit position */
-#define BITM_ILAT_NMI                        (_ADI_MSK(0x00000004,uint32_t))  /* Non Maskable interrupt bit position */
-#define BITM_ILAT_RST                        (_ADI_MSK(0x00000002,uint32_t))  /* Reset interrupt bit position */
-#define BITM_ILAT_EMU                        (_ADI_MSK(0x00000001,uint32_t))  /* Emulator interrupt bit position */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        IPRIO                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_IPRIO_IPRIO_MARK                 0                               /* Priority Watermark */
-#define BITM_IPRIO_IPRIO_MARK                (_ADI_MSK(0x0000000F,uint32_t))  /* Priority Watermark */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        CEC_SID                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_CEC_SID_SID                      0                               /* System Interrupt ID */
-#define BITM_CEC_SID_SID                     (_ADI_MSK(0x000000FF,uint32_t))  /* System Interrupt ID */
-
-/* ==================================================
-        Core Timer Registers
-   ================================================== */
-
-/* =========================
-        TMR0
-   ========================= */
-#define TCNTL                           0xFFE03000         /* Timer Control Register */
-#define TPERIOD                         0xFFE03004         /* Timer Period Register */
-#define TSCALE                          0xFFE03008         /* Timer Scale Register */
-#define TCOUNT                          0xFFE0300C         /* Timer Count Register */
-
-/* =========================
-        TMR
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TCNTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TCNTL_INT                        3                               /* Interrupt Status (sticky) */
-#define BITP_TCNTL_AUTORLD                    2                               /* Auto Reload Enable */
-#define BITP_TCNTL_EN                         1                               /* Timer Enable */
-#define BITP_TCNTL_PWR                        0                               /* Low Power Mode Select */
-#define BITM_TCNTL_INT                       (_ADI_MSK(0x00000008,uint32_t))  /* Interrupt Status (sticky) */
-#define BITM_TCNTL_AUTORLD                   (_ADI_MSK(0x00000004,uint32_t))  /* Auto Reload Enable */
-#define BITM_TCNTL_EN                        (_ADI_MSK(0x00000002,uint32_t))  /* Timer Enable */
-#define BITM_TCNTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Low Power Mode Select */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TSCALE                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TSCALE_SCALE                     0                               /* Timer Scaling Value */
-#define BITM_TSCALE_SCALE                    (_ADI_MSK(0x000000FF,uint32_t))  /* Timer Scaling Value */
-
-/* ==================================================
-        Debug Unit Registers
-   ================================================== */
-
-/* =========================
-        DBG0
-   ========================= */
-#define DSPID                           0xFFE05000         /* DSP Identification Register */
-
-/* =========================
-        DBG
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        DSPID                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_DSPID_COMPANY                   24                               /* Analog Devices, Inc. */
-#define BITP_DSPID_MAJOR                     16                               /* Major Architectural Change */
-#define BITP_DSPID_COREID                     0                               /* Core ID */
-#define BITM_DSPID_COMPANY                   (_ADI_MSK(0xFF000000,uint32_t))  /* Analog Devices, Inc. */
-
-#define BITM_DSPID_MAJOR                     (_ADI_MSK(0x00FF0000,uint32_t))  /* Major Architectural Change */
-#define ENUM_DSPID_BF533                     (_ADI_MSK(0x00040000,uint32_t))  /* MAJOR: ADSP-BF533 Core Compatible */
-#define BITM_DSPID_COREID                    (_ADI_MSK(0x000000FF,uint32_t))  /* Core ID */
-
-/* ==================================================
-        Trace Unit Registers
-   ================================================== */
-
-/* =========================
-        TB0
-   ========================= */
-#define TBUFCTL                         0xFFE06000         /* Trace Buffer Control Register */
-#define TBUFSTAT                        0xFFE06004         /* Trace Buffer Status Register */
-#define TBUF                            0xFFE06100         /* Trace Buffer */
-
-/* =========================
-        TB
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFCTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFCTL_COMPRESS                 3                               /* Trace Buffer Compression */
-#define BITP_TBUFCTL_OVF                      2                               /* Trace Buffer Overflow */
-#define BITP_TBUFCTL_EN                       1                               /* Trace Buffer Enable */
-#define BITP_TBUFCTL_PWR                      0                               /* Trace Buffer Power */
-#define BITM_TBUFCTL_COMPRESS                (_ADI_MSK(0x00000018,uint32_t))  /* Trace Buffer Compression */
-#define BITM_TBUFCTL_OVF                     (_ADI_MSK(0x00000004,uint32_t))  /* Trace Buffer Overflow */
-#define BITM_TBUFCTL_EN                      (_ADI_MSK(0x00000002,uint32_t))  /* Trace Buffer Enable */
-#define BITM_TBUFCTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Trace Buffer Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        TBUFSTAT                             Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_TBUFSTAT_CNT                     0                               /* Trace Buffer Count */
-#define BITM_TBUFSTAT_CNT                    (_ADI_MSK(0x0000001F,uint32_t))  /* Trace Buffer Count */
-
-/* ==================================================
-        Watchpoint Unit Registers
-   ================================================== */
-
-/* =========================
-        WP0
-   ========================= */
-#define WPIACTL                         0xFFE07000         /* Watchpoint Instruction Address Control Register 01 */
-#define WPIA0                           0xFFE07040         /* Watchpoint Instruction Address Register */
-#define WPIA1                           0xFFE07044         /* Watchpoint Instruction Address Register */
-#define WPIA2                           0xFFE07048         /* Watchpoint Instruction Address Register */
-#define WPIA3                           0xFFE0704C         /* Watchpoint Instruction Address Register */
-#define WPIA4                           0xFFE07050         /* Watchpoint Instruction Address Register */
-#define WPIA5                           0xFFE07054         /* Watchpoint Instruction Address Register */
-#define WPIACNT0                        0xFFE07080         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT1                        0xFFE07084         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT2                        0xFFE07088         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT3                        0xFFE0708C         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT4                        0xFFE07090         /* Watchpoint Instruction Address Count Register */
-#define WPIACNT5                        0xFFE07094         /* Watchpoint Instruction Address Count Register */
-#define WPDACTL                         0xFFE07100         /* Watchpoint Data Address Control Register */
-#define WPDA0                           0xFFE07140         /* Watchpoint Data Address Register */
-#define WPDA1                           0xFFE07144         /* Watchpoint Data Address Register */
-#define WPDACNT0                        0xFFE07180         /* Watchpoint Data Address Count Value Register */
-#define WPDACNT1                        0xFFE07184         /* Watchpoint Data Address Count Value Register */
-#define WPSTAT                          0xFFE07200         /* Watchpoint Status Register */
-
-/* =========================
-        WP
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACTL_WPAND                   25                               /* And Triggers */
-#define BITP_WPIACTL_ACT5                    24                               /* Action field for WPIA5 */
-#define BITP_WPIACTL_ACT4                    23                               /* Action field for WPIA4 */
-#define BITP_WPIACTL_ENCNT5                  22                               /* Enable Counter for WPIA5 */
-#define BITP_WPIACTL_ENCNT4                  21                               /* Enable Counter for WPIA4 */
-#define BITP_WPIACTL_ENIA5                   20                               /* Enable WPIA5 */
-#define BITP_WPIACTL_ENIA4                   19                               /* Enable WPIA4 */
-#define BITP_WPIACTL_INVIR45                 18                               /* Invert Instruction Range 45 */
-#define BITP_WPIACTL_ENIR45                  17                               /* Enable Instruction Range 45 */
-#define BITP_WPIACTL_ACT3                    16                               /* Action field for WPIA3 */
-#define BITP_WPIACTL_ACT2                    15                               /* Action field for WPIA2 */
-#define BITP_WPIACTL_ENCNT3                  14                               /* Enable Counter for WPIA3 */
-#define BITP_WPIACTL_ENCNT2                  13                               /* Enable Counter for WPIA2 */
-#define BITP_WPIACTL_ENIA3                   12                               /* Enable WPIA3 */
-#define BITP_WPIACTL_ENIA2                   11                               /* Enable WPIA2 */
-#define BITP_WPIACTL_INVIR23                 10                               /* Invert Instruction Range 23 */
-#define BITP_WPIACTL_ENIR23                   9                               /* Enable Instruction Range 23 */
-#define BITP_WPIACTL_ACT1                     8                               /* Action field for WPIA1 */
-#define BITP_WPIACTL_ACT0                     7                               /* Action field for WPIA0 */
-#define BITP_WPIACTL_ENCNT1                   6                               /* Enable Counter for WPIA1 */
-#define BITP_WPIACTL_ENCNT0                   5                               /* Enable Counter for WPIA0 */
-#define BITP_WPIACTL_ENIA1                    4                               /* Enable WPIA1 */
-#define BITP_WPIACTL_ENIA0                    3                               /* Enable WPIA0 */
-#define BITP_WPIACTL_INVIR01                  2                               /* Invert Instruction Range 01 */
-#define BITP_WPIACTL_ENIR01                   1                               /* Enable Instruction Range 01 */
-#define BITP_WPIACTL_PWR                      0                               /* Power */
-#define BITM_WPIACTL_WPAND                   (_ADI_MSK(0x02000000,uint32_t))  /* And Triggers */
-#define BITM_WPIACTL_ACT5                    (_ADI_MSK(0x01000000,uint32_t))  /* Action field for WPIA5 */
-#define BITM_WPIACTL_ACT4                    (_ADI_MSK(0x00800000,uint32_t))  /* Action field for WPIA4 */
-#define BITM_WPIACTL_ENCNT5                  (_ADI_MSK(0x00400000,uint32_t))  /* Enable Counter for WPIA5 */
-#define BITM_WPIACTL_ENCNT4                  (_ADI_MSK(0x00200000,uint32_t))  /* Enable Counter for WPIA4 */
-#define BITM_WPIACTL_ENIA5                   (_ADI_MSK(0x00100000,uint32_t))  /* Enable WPIA5 */
-#define BITM_WPIACTL_ENIA4                   (_ADI_MSK(0x00080000,uint32_t))  /* Enable WPIA4 */
-#define BITM_WPIACTL_INVIR45                 (_ADI_MSK(0x00040000,uint32_t))  /* Invert Instruction Range 45 */
-#define BITM_WPIACTL_ENIR45                  (_ADI_MSK(0x00020000,uint32_t))  /* Enable Instruction Range 45 */
-#define BITM_WPIACTL_ACT3                    (_ADI_MSK(0x00010000,uint32_t))  /* Action field for WPIA3 */
-#define BITM_WPIACTL_ACT2                    (_ADI_MSK(0x00008000,uint32_t))  /* Action field for WPIA2 */
-#define BITM_WPIACTL_ENCNT3                  (_ADI_MSK(0x00004000,uint32_t))  /* Enable Counter for WPIA3 */
-#define BITM_WPIACTL_ENCNT2                  (_ADI_MSK(0x00002000,uint32_t))  /* Enable Counter for WPIA2 */
-#define BITM_WPIACTL_ENIA3                   (_ADI_MSK(0x00001000,uint32_t))  /* Enable WPIA3 */
-#define BITM_WPIACTL_ENIA2                   (_ADI_MSK(0x00000800,uint32_t))  /* Enable WPIA2 */
-#define BITM_WPIACTL_INVIR23                 (_ADI_MSK(0x00000400,uint32_t))  /* Invert Instruction Range 23 */
-#define BITM_WPIACTL_ENIR23                  (_ADI_MSK(0x00000200,uint32_t))  /* Enable Instruction Range 23 */
-#define BITM_WPIACTL_ACT1                    (_ADI_MSK(0x00000100,uint32_t))  /* Action field for WPIA1 */
-#define BITM_WPIACTL_ACT0                    (_ADI_MSK(0x00000080,uint32_t))  /* Action field for WPIA0 */
-#define BITM_WPIACTL_ENCNT1                  (_ADI_MSK(0x00000040,uint32_t))  /* Enable Counter for WPIA1 */
-#define BITM_WPIACTL_ENCNT0                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable Counter for WPIA0 */
-#define BITM_WPIACTL_ENIA1                   (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPIA1 */
-#define BITM_WPIACTL_ENIA0                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPIA0 */
-#define BITM_WPIACTL_INVIR01                 (_ADI_MSK(0x00000004,uint32_t))  /* Invert Instruction Range 01 */
-#define BITM_WPIACTL_ENIR01                  (_ADI_MSK(0x00000002,uint32_t))  /* Enable Instruction Range 01 */
-#define BITM_WPIACTL_PWR                     (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPIACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPIACNT_CNT                      0                               /* Count Value */
-#define BITM_WPIACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACTL                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACTL_ACC1                    12                               /* Access type for WPDA1 */
-#define BITP_WPDACTL_SRC1                    10                               /* DAG Source for WPDA1 */
-#define BITP_WPDACTL_ACC0                     8                               /* Access type for WPDA0 */
-#define BITP_WPDACTL_SRC0                     6                               /* DAG Source for WPDA0 */
-#define BITP_WPDACTL_ENCNT1                   5                               /* Enable WPDA1 Counter */
-#define BITP_WPDACTL_ENCNT0                   4                               /* Enable WPDA0 Counter */
-#define BITP_WPDACTL_ENDA1                    3                               /* Enable WPDA1 */
-#define BITP_WPDACTL_ENDA0                    2                               /* Enable WPDA0 */
-#define BITP_WPDACTL_INVR                     1                               /* Invert Range Comparision */
-#define BITP_WPDACTL_ENR                      0                               /* Enable Range Comparison */
-#define BITM_WPDACTL_ACC1                    (_ADI_MSK(0x00003000,uint32_t))  /* Access type for WPDA1 */
-#define BITM_WPDACTL_SRC1                    (_ADI_MSK(0x00000C00,uint32_t))  /* DAG Source for WPDA1 */
-#define BITM_WPDACTL_ACC0                    (_ADI_MSK(0x00000300,uint32_t))  /* Access type for WPDA0 */
-#define BITM_WPDACTL_SRC0                    (_ADI_MSK(0x000000C0,uint32_t))  /* DAG Source for WPDA0 */
-#define BITM_WPDACTL_ENCNT1                  (_ADI_MSK(0x00000020,uint32_t))  /* Enable WPDA1 Counter */
-#define BITM_WPDACTL_ENCNT0                  (_ADI_MSK(0x00000010,uint32_t))  /* Enable WPDA0 Counter */
-#define BITM_WPDACTL_ENDA1                   (_ADI_MSK(0x00000008,uint32_t))  /* Enable WPDA1 */
-#define BITM_WPDACTL_ENDA0                   (_ADI_MSK(0x00000004,uint32_t))  /* Enable WPDA0 */
-#define BITM_WPDACTL_INVR                    (_ADI_MSK(0x00000002,uint32_t))  /* Invert Range Comparision */
-#define BITM_WPDACTL_ENR                     (_ADI_MSK(0x00000001,uint32_t))  /* Enable Range Comparison */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPDACNT                              Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPDACNT_CNT                      0                               /* Count Value */
-#define BITM_WPDACNT_CNT                     (_ADI_MSK(0x0000FFFF,uint32_t))  /* Count Value */
-
-/* ------------------------------------------------------------------------------------------------------------------------
-        WPSTAT                               Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_WPSTAT_DA1                       7                               /* WPDA1 match */
-#define BITP_WPSTAT_DA0                       6                               /* WPDA0 or WPDA0:1 range match */
-#define BITP_WPSTAT_IA5                       5                               /* WPIA5 match */
-#define BITP_WPSTAT_IA4                       4                               /* WPIA4 or WPIA4:5 range match */
-#define BITP_WPSTAT_IA3                       3                               /* WPIA3 match */
-#define BITP_WPSTAT_IA2                       2                               /* WPIA2 or WPIA2:3 range match */
-#define BITP_WPSTAT_IA1                       1                               /* WPIA1 match */
-#define BITP_WPSTAT_IA0                       0                               /* WPIA0 or WPIA0:1 range match */
-#define BITM_WPSTAT_DA1                      (_ADI_MSK(0x00000080,uint32_t))  /* WPDA1 match */
-#define BITM_WPSTAT_DA0                      (_ADI_MSK(0x00000040,uint32_t))  /* WPDA0 or WPDA0:1 range match */
-#define BITM_WPSTAT_IA5                      (_ADI_MSK(0x00000020,uint32_t))  /* WPIA5 match */
-#define BITM_WPSTAT_IA4                      (_ADI_MSK(0x00000010,uint32_t))  /* WPIA4 or WPIA4:5 range match */
-#define BITM_WPSTAT_IA3                      (_ADI_MSK(0x00000008,uint32_t))  /* WPIA3 match */
-#define BITM_WPSTAT_IA2                      (_ADI_MSK(0x00000004,uint32_t))  /* WPIA2 or WPIA2:3 range match */
-#define BITM_WPSTAT_IA1                      (_ADI_MSK(0x00000002,uint32_t))  /* WPIA1 match */
-#define BITM_WPSTAT_IA0                      (_ADI_MSK(0x00000001,uint32_t))  /* WPIA0 or WPIA0:1 range match */
-
-/* ==================================================
-        Performance Monitor Registers
-   ================================================== */
-
-/* =========================
-        PF0
-   ========================= */
-#define PFCTL                           0xFFE08000         /* Performance Monitor Control Register */
-#define PFCNTR0                         0xFFE08100         /* Performance Monitor Counter 0 */
-#define PFCNTR1                         0xFFE08104         /* Performance Monitor Counter 1 */
-
-/* =========================
-        PF
-   ========================= */
-/* ------------------------------------------------------------------------------------------------------------------------
-        PFCTL                                Pos/Masks                        Description
-   ------------------------------------------------------------------------------------------------------------------------ */
-#define BITP_PFCTL_CNT1                      25                               /* Count Cycles or Edges 1 */
-#define BITP_PFCTL_CNT0                      24                               /* Count Cycles or Edges 0 */
-#define BITP_PFCTL_MON1                      16                               /* Monitor 1 Events */
-#define BITP_PFCTL_ENA1                      14                               /* Enable Monitor 1 */
-#define BITP_PFCTL_EVENT1                    13                               /* Emulator or Exception Event 1 */
-#define BITP_PFCTL_MON0                       5                               /* Monitor 0 Events */
-#define BITP_PFCTL_ENA0                       3                               /* Enable Monitor 0 */
-#define BITP_PFCTL_EVENT0                     2                               /* Emulator or Exception Event 0 */
-#define BITP_PFCTL_PWR                        0                               /* Power */
-#define BITM_PFCTL_CNT1                      (_ADI_MSK(0x02000000,uint32_t))  /* Count Cycles or Edges 1 */
-#define BITM_PFCTL_CNT0                      (_ADI_MSK(0x01000000,uint32_t))  /* Count Cycles or Edges 0 */
-#define BITM_PFCTL_MON1                      (_ADI_MSK(0x00FF0000,uint32_t))  /* Monitor 1 Events */
-#define BITM_PFCTL_ENA1                      (_ADI_MSK(0x0000C000,uint32_t))  /* Enable Monitor 1 */
-#define BITM_PFCTL_EVENT1                    (_ADI_MSK(0x00002000,uint32_t))  /* Emulator or Exception Event 1 */
-#define BITM_PFCTL_MON0                      (_ADI_MSK(0x00001FE0,uint32_t))  /* Monitor 0 Events */
-#define BITM_PFCTL_ENA0                      (_ADI_MSK(0x00000018,uint32_t))  /* Enable Monitor 0 */
-#define BITM_PFCTL_EVENT0                    (_ADI_MSK(0x00000004,uint32_t))  /* Emulator or Exception Event 0 */
-#define BITM_PFCTL_PWR                       (_ADI_MSK(0x00000001,uint32_t))  /* Power */
-
-/* ==================================
-       DMA Alias Definitions
-   ================================== */
-#define SPORT0_A_DMA_DSCPTR_NXT              (REG_DMA0_DSCPTR_NXT)
-#define SPORT0_A_DMA_ADDRSTART               (REG_DMA0_ADDRSTART)
-#define SPORT0_A_DMA_CFG                     (REG_DMA0_CFG)
-#define SPORT0_A_DMA_XCNT                    (REG_DMA0_XCNT)
-#define SPORT0_A_DMA_XMOD                    (REG_DMA0_XMOD)
-#define SPORT0_A_DMA_YCNT                    (REG_DMA0_YCNT)
-#define SPORT0_A_DMA_YMOD                    (REG_DMA0_YMOD)
-#define SPORT0_A_DMA_DSCPTR_CUR              (REG_DMA0_DSCPTR_CUR)
-#define SPORT0_A_DMA_DSCPTR_PRV              (REG_DMA0_DSCPTR_PRV)
-#define SPORT0_A_DMA_ADDR_CUR                (REG_DMA0_ADDR_CUR)
-#define SPORT0_A_DMA_STAT                    (REG_DMA0_STAT)
-#define SPORT0_A_DMA_XCNT_CUR                (REG_DMA0_XCNT_CUR)
-#define SPORT0_A_DMA_YCNT_CUR                (REG_DMA0_YCNT_CUR)
-#define SPORT0_A_DMA_BWLCNT                  (REG_DMA0_BWLCNT)
-#define SPORT0_A_DMA_BWLCNT_CUR              (REG_DMA0_BWLCNT_CUR)
-#define SPORT0_A_DMA_BWMCNT                  (REG_DMA0_BWMCNT)
-#define SPORT0_A_DMA_BWMCNT_CUR              (REG_DMA0_BWMCNT_CUR)
-#define SPORT0_B_DMA_DSCPTR_NXT              (REG_DMA1_DSCPTR_NXT)
-#define SPORT0_B_DMA_ADDRSTART               (REG_DMA1_ADDRSTART)
-#define SPORT0_B_DMA_CFG                     (REG_DMA1_CFG)
-#define SPORT0_B_DMA_XCNT                    (REG_DMA1_XCNT)
-#define SPORT0_B_DMA_XMOD                    (REG_DMA1_XMOD)
-#define SPORT0_B_DMA_YCNT                    (REG_DMA1_YCNT)
-#define SPORT0_B_DMA_YMOD                    (REG_DMA1_YMOD)
-#define SPORT0_B_DMA_DSCPTR_CUR              (REG_DMA1_DSCPTR_CUR)
-#define SPORT0_B_DMA_DSCPTR_PRV              (REG_DMA1_DSCPTR_PRV)
-#define SPORT0_B_DMA_ADDR_CUR                (REG_DMA1_ADDR_CUR)
-#define SPORT0_B_DMA_STAT                    (REG_DMA1_STAT)
-#define SPORT0_B_DMA_XCNT_CUR                (REG_DMA1_XCNT_CUR)
-#define SPORT0_B_DMA_YCNT_CUR                (REG_DMA1_YCNT_CUR)
-#define SPORT0_B_DMA_BWLCNT                  (REG_DMA1_BWLCNT)
-#define SPORT0_B_DMA_BWLCNT_CUR              (REG_DMA1_BWLCNT_CUR)
-#define SPORT0_B_DMA_BWMCNT                  (REG_DMA1_BWMCNT)
-#define SPORT0_B_DMA_BWMCNT_CUR              (REG_DMA1_BWMCNT_CUR)
-#define SPORT1_A_DMA_DSCPTR_NXT              (REG_DMA2_DSCPTR_NXT)
-#define SPORT1_A_DMA_ADDRSTART               (REG_DMA2_ADDRSTART)
-#define SPORT1_A_DMA_CFG                     (REG_DMA2_CFG)
-#define SPORT1_A_DMA_XCNT                    (REG_DMA2_XCNT)
-#define SPORT1_A_DMA_XMOD                    (REG_DMA2_XMOD)
-#define SPORT1_A_DMA_YCNT                    (REG_DMA2_YCNT)
-#define SPORT1_A_DMA_YMOD                    (REG_DMA2_YMOD)
-#define SPORT1_A_DMA_DSCPTR_CUR              (REG_DMA2_DSCPTR_CUR)
-#define SPORT1_A_DMA_DSCPTR_PRV              (REG_DMA2_DSCPTR_PRV)
-#define SPORT1_A_DMA_ADDR_CUR                (REG_DMA2_ADDR_CUR)
-#define SPORT1_A_DMA_STAT                    (REG_DMA2_STAT)
-#define SPORT1_A_DMA_XCNT_CUR                (REG_DMA2_XCNT_CUR)
-#define SPORT1_A_DMA_YCNT_CUR                (REG_DMA2_YCNT_CUR)
-#define SPORT1_A_DMA_BWLCNT                  (REG_DMA2_BWLCNT)
-#define SPORT1_A_DMA_BWLCNT_CUR              (REG_DMA2_BWLCNT_CUR)
-#define SPORT1_A_DMA_BWMCNT                  (REG_DMA2_BWMCNT)
-#define SPORT1_A_DMA_BWMCNT_CUR              (REG_DMA2_BWMCNT_CUR)
-#define SPORT1_B_DMA_DSCPTR_NXT              (REG_DMA3_DSCPTR_NXT)
-#define SPORT1_B_DMA_ADDRSTART               (REG_DMA3_ADDRSTART)
-#define SPORT1_B_DMA_CFG                     (REG_DMA3_CFG)
-#define SPORT1_B_DMA_XCNT                    (REG_DMA3_XCNT)
-#define SPORT1_B_DMA_XMOD                    (REG_DMA3_XMOD)
-#define SPORT1_B_DMA_YCNT                    (REG_DMA3_YCNT)
-#define SPORT1_B_DMA_YMOD                    (REG_DMA3_YMOD)
-#define SPORT1_B_DMA_DSCPTR_CUR              (REG_DMA3_DSCPTR_CUR)
-#define SPORT1_B_DMA_DSCPTR_PRV              (REG_DMA3_DSCPTR_PRV)
-#define SPORT1_B_DMA_ADDR_CUR                (REG_DMA3_ADDR_CUR)
-#define SPORT1_B_DMA_STAT                    (REG_DMA3_STAT)
-#define SPORT1_B_DMA_XCNT_CUR                (REG_DMA3_XCNT_CUR)
-#define SPORT1_B_DMA_YCNT_CUR                (REG_DMA3_YCNT_CUR)
-#define SPORT1_B_DMA_BWLCNT                  (REG_DMA3_BWLCNT)
-#define SPORT1_B_DMA_BWLCNT_CUR              (REG_DMA3_BWLCNT_CUR)
-#define SPORT1_B_DMA_BWMCNT                  (REG_DMA3_BWMCNT)
-#define SPORT1_B_DMA_BWMCNT_CUR              (REG_DMA3_BWMCNT_CUR)
-#define SPORT2_A_DMA_DSCPTR_NXT              (REG_DMA4_DSCPTR_NXT)
-#define SPORT2_A_DMA_ADDRSTART               (REG_DMA4_ADDRSTART)
-#define SPORT2_A_DMA_CFG                     (REG_DMA4_CFG)
-#define SPORT2_A_DMA_XCNT                    (REG_DMA4_XCNT)
-#define SPORT2_A_DMA_XMOD                    (REG_DMA4_XMOD)
-#define SPORT2_A_DMA_YCNT                    (REG_DMA4_YCNT)
-#define SPORT2_A_DMA_YMOD                    (REG_DMA4_YMOD)
-#define SPORT2_A_DMA_DSCPTR_CUR              (REG_DMA4_DSCPTR_CUR)
-#define SPORT2_A_DMA_DSCPTR_PRV              (REG_DMA4_DSCPTR_PRV)
-#define SPORT2_A_DMA_ADDR_CUR                (REG_DMA4_ADDR_CUR)
-#define SPORT2_A_DMA_STAT                    (REG_DMA4_STAT)
-#define SPORT2_A_DMA_XCNT_CUR                (REG_DMA4_XCNT_CUR)
-#define SPORT2_A_DMA_YCNT_CUR                (REG_DMA4_YCNT_CUR)
-#define SPORT2_A_DMA_BWLCNT                  (REG_DMA4_BWLCNT)
-#define SPORT2_A_DMA_BWLCNT_CUR              (REG_DMA4_BWLCNT_CUR)
-#define SPORT2_A_DMA_BWMCNT                  (REG_DMA4_BWMCNT)
-#define SPORT2_A_DMA_BWMCNT_CUR              (REG_DMA4_BWMCNT_CUR)
-#define SPORT2_B_DMA_DSCPTR_NXT              (REG_DMA5_DSCPTR_NXT)
-#define SPORT2_B_DMA_ADDRSTART               (REG_DMA5_ADDRSTART)
-#define SPORT2_B_DMA_CFG                     (REG_DMA5_CFG)
-#define SPORT2_B_DMA_XCNT                    (REG_DMA5_XCNT)
-#define SPORT2_B_DMA_XMOD                    (REG_DMA5_XMOD)
-#define SPORT2_B_DMA_YCNT                    (REG_DMA5_YCNT)
-#define SPORT2_B_DMA_YMOD                    (REG_DMA5_YMOD)
-#define SPORT2_B_DMA_DSCPTR_CUR              (REG_DMA5_DSCPTR_CUR)
-#define SPORT2_B_DMA_DSCPTR_PRV              (REG_DMA5_DSCPTR_PRV)
-#define SPORT2_B_DMA_ADDR_CUR                (REG_DMA5_ADDR_CUR)
-#define SPORT2_B_DMA_STAT                    (REG_DMA5_STAT)
-#define SPORT2_B_DMA_XCNT_CUR                (REG_DMA5_XCNT_CUR)
-#define SPORT2_B_DMA_YCNT_CUR                (REG_DMA5_YCNT_CUR)
-#define SPORT2_B_DMA_BWLCNT                  (REG_DMA5_BWLCNT)
-#define SPORT2_B_DMA_BWLCNT_CUR              (REG_DMA5_BWLCNT_CUR)
-#define SPORT2_B_DMA_BWMCNT                  (REG_DMA5_BWMCNT)
-#define SPORT2_B_DMA_BWMCNT_CUR              (REG_DMA5_BWMCNT_CUR)
-#define SPI0_TXDMA_DSCPTR_NXT                (REG_DMA6_DSCPTR_NXT)
-#define SPI0_TXDMA_ADDRSTART                 (REG_DMA6_ADDRSTART)
-#define SPI0_TXDMA_CFG                       (REG_DMA6_CFG)
-#define SPI0_TXDMA_XCNT                      (REG_DMA6_XCNT)
-#define SPI0_TXDMA_XMOD                      (REG_DMA6_XMOD)
-#define SPI0_TXDMA_YCNT                      (REG_DMA6_YCNT)
-#define SPI0_TXDMA_YMOD                      (REG_DMA6_YMOD)
-#define SPI0_TXDMA_DSCPTR_CUR                (REG_DMA6_DSCPTR_CUR)
-#define SPI0_TXDMA_DSCPTR_PRV                (REG_DMA6_DSCPTR_PRV)
-#define SPI0_TXDMA_ADDR_CUR                  (REG_DMA6_ADDR_CUR)
-#define SPI0_TXDMA_STAT                      (REG_DMA6_STAT)
-#define SPI0_TXDMA_XCNT_CUR                  (REG_DMA6_XCNT_CUR)
-#define SPI0_TXDMA_YCNT_CUR                  (REG_DMA6_YCNT_CUR)
-#define SPI0_TXDMA_BWLCNT                    (REG_DMA6_BWLCNT)
-#define SPI0_TXDMA_BWLCNT_CUR                (REG_DMA6_BWLCNT_CUR)
-#define SPI0_TXDMA_BWMCNT                    (REG_DMA6_BWMCNT)
-#define SPI0_TXDMA_BWMCNT_CUR                (REG_DMA6_BWMCNT_CUR)
-#define SPI0_RXDMA_DSCPTR_NXT                (REG_DMA7_DSCPTR_NXT)
-#define SPI0_RXDMA_ADDRSTART                 (REG_DMA7_ADDRSTART)
-#define SPI0_RXDMA_CFG                       (REG_DMA7_CFG)
-#define SPI0_RXDMA_XCNT                      (REG_DMA7_XCNT)
-#define SPI0_RXDMA_XMOD                      (REG_DMA7_XMOD)
-#define SPI0_RXDMA_YCNT                      (REG_DMA7_YCNT)
-#define SPI0_RXDMA_YMOD                      (REG_DMA7_YMOD)
-#define SPI0_RXDMA_DSCPTR_CUR                (REG_DMA7_DSCPTR_CUR)
-#define SPI0_RXDMA_DSCPTR_PRV                (REG_DMA7_DSCPTR_PRV)
-#define SPI0_RXDMA_ADDR_CUR                  (REG_DMA7_ADDR_CUR)
-#define SPI0_RXDMA_STAT                      (REG_DMA7_STAT)
-#define SPI0_RXDMA_XCNT_CUR                  (REG_DMA7_XCNT_CUR)
-#define SPI0_RXDMA_YCNT_CUR                  (REG_DMA7_YCNT_CUR)
-#define SPI0_RXDMA_BWLCNT                    (REG_DMA7_BWLCNT)
-#define SPI0_RXDMA_BWLCNT_CUR                (REG_DMA7_BWLCNT_CUR)
-#define SPI0_RXDMA_BWMCNT                    (REG_DMA7_BWMCNT)
-#define SPI0_RXDMA_BWMCNT_CUR                (REG_DMA7_BWMCNT_CUR)
-#define SPI1_TXDMA_DSCPTR_NXT                (REG_DMA8_DSCPTR_NXT)
-#define SPI1_TXDMA_ADDRSTART                 (REG_DMA8_ADDRSTART)
-#define SPI1_TXDMA_CFG                       (REG_DMA8_CFG)
-#define SPI1_TXDMA_XCNT                      (REG_DMA8_XCNT)
-#define SPI1_TXDMA_XMOD                      (REG_DMA8_XMOD)
-#define SPI1_TXDMA_YCNT                      (REG_DMA8_YCNT)
-#define SPI1_TXDMA_YMOD                      (REG_DMA8_YMOD)
-#define SPI1_TXDMA_DSCPTR_CUR                (REG_DMA8_DSCPTR_CUR)
-#define SPI1_TXDMA_DSCPTR_PRV                (REG_DMA8_DSCPTR_PRV)
-#define SPI1_TXDMA_ADDR_CUR                  (REG_DMA8_ADDR_CUR)
-#define SPI1_TXDMA_STAT                      (REG_DMA8_STAT)
-#define SPI1_TXDMA_XCNT_CUR                  (REG_DMA8_XCNT_CUR)
-#define SPI1_TXDMA_YCNT_CUR                  (REG_DMA8_YCNT_CUR)
-#define SPI1_TXDMA_BWLCNT                    (REG_DMA8_BWLCNT)
-#define SPI1_TXDMA_BWLCNT_CUR                (REG_DMA8_BWLCNT_CUR)
-#define SPI1_TXDMA_BWMCNT                    (REG_DMA8_BWMCNT)
-#define SPI1_TXDMA_BWMCNT_CUR                (REG_DMA8_BWMCNT_CUR)
-#define SPI1_RXDMA_DSCPTR_NXT                (REG_DMA9_DSCPTR_NXT)
-#define SPI1_RXDMA_ADDRSTART                 (REG_DMA9_ADDRSTART)
-#define SPI1_RXDMA_CFG                       (REG_DMA9_CFG)
-#define SPI1_RXDMA_XCNT                      (REG_DMA9_XCNT)
-#define SPI1_RXDMA_XMOD                      (REG_DMA9_XMOD)
-#define SPI1_RXDMA_YCNT                      (REG_DMA9_YCNT)
-#define SPI1_RXDMA_YMOD                      (REG_DMA9_YMOD)
-#define SPI1_RXDMA_DSCPTR_CUR                (REG_DMA9_DSCPTR_CUR)
-#define SPI1_RXDMA_DSCPTR_PRV                (REG_DMA9_DSCPTR_PRV)
-#define SPI1_RXDMA_ADDR_CUR                  (REG_DMA9_ADDR_CUR)
-#define SPI1_RXDMA_STAT                      (REG_DMA9_STAT)
-#define SPI1_RXDMA_XCNT_CUR                  (REG_DMA9_XCNT_CUR)
-#define SPI1_RXDMA_YCNT_CUR                  (REG_DMA9_YCNT_CUR)
-#define SPI1_RXDMA_BWLCNT                    (REG_DMA9_BWLCNT)
-#define SPI1_RXDMA_BWLCNT_CUR                (REG_DMA9_BWLCNT_CUR)
-#define SPI1_RXDMA_BWMCNT                    (REG_DMA9_BWMCNT)
-#define SPI1_RXDMA_BWMCNT_CUR                (REG_DMA9_BWMCNT_CUR)
-#define RSI0_DMA_DSCPTR_NXT                  (REG_DMA10_DSCPTR_NXT)
-#define RSI0_DMA_ADDRSTART                   (REG_DMA10_ADDRSTART)
-#define RSI0_DMA_CFG                         (REG_DMA10_CFG)
-#define RSI0_DMA_XCNT                        (REG_DMA10_XCNT)
-#define RSI0_DMA_XMOD                        (REG_DMA10_XMOD)
-#define RSI0_DMA_YCNT                        (REG_DMA10_YCNT)
-#define RSI0_DMA_YMOD                        (REG_DMA10_YMOD)
-#define RSI0_DMA_DSCPTR_CUR                  (REG_DMA10_DSCPTR_CUR)
-#define RSI0_DMA_DSCPTR_PRV                  (REG_DMA10_DSCPTR_PRV)
-#define RSI0_DMA_ADDR_CUR                    (REG_DMA10_ADDR_CUR)
-#define RSI0_DMA_STAT                        (REG_DMA10_STAT)
-#define RSI0_DMA_XCNT_CUR                    (REG_DMA10_XCNT_CUR)
-#define RSI0_DMA_YCNT_CUR                    (REG_DMA10_YCNT_CUR)
-#define RSI0_DMA_BWLCNT                      (REG_DMA10_BWLCNT)
-#define RSI0_DMA_BWLCNT_CUR                  (REG_DMA10_BWLCNT_CUR)
-#define RSI0_DMA_BWMCNT                      (REG_DMA10_BWMCNT)
-#define RSI0_DMA_BWMCNT_CUR                  (REG_DMA10_BWMCNT_CUR)
-#define SDU0_DMA_DSCPTR_NXT                  (REG_DMA11_DSCPTR_NXT)
-#define SDU0_DMA_ADDRSTART                   (REG_DMA11_ADDRSTART)
-#define SDU0_DMA_CFG                         (REG_DMA11_CFG)
-#define SDU0_DMA_XCNT                        (REG_DMA11_XCNT)
-#define SDU0_DMA_XMOD                        (REG_DMA11_XMOD)
-#define SDU0_DMA_YCNT                        (REG_DMA11_YCNT)
-#define SDU0_DMA_YMOD                        (REG_DMA11_YMOD)
-#define SDU0_DMA_DSCPTR_CUR                  (REG_DMA11_DSCPTR_CUR)
-#define SDU0_DMA_DSCPTR_PRV                  (REG_DMA11_DSCPTR_PRV)
-#define SDU0_DMA_ADDR_CUR                    (REG_DMA11_ADDR_CUR)
-#define SDU0_DMA_STAT                        (REG_DMA11_STAT)
-#define SDU0_DMA_XCNT_CUR                    (REG_DMA11_XCNT_CUR)
-#define SDU0_DMA_YCNT_CUR                    (REG_DMA11_YCNT_CUR)
-#define SDU0_DMA_BWLCNT                      (REG_DMA11_BWLCNT)
-#define SDU0_DMA_BWLCNT_CUR                  (REG_DMA11_BWLCNT_CUR)
-#define SDU0_DMA_BWMCNT                      (REG_DMA11_BWMCNT)
-#define SDU0_DMA_BWMCNT_CUR                  (REG_DMA11_BWMCNT_CUR)
-#define LP0_DMA_DSCPTR_NXT                   (REG_DMA13_DSCPTR_NXT)
-#define LP0_DMA_ADDRSTART                    (REG_DMA13_ADDRSTART)
-#define LP0_DMA_CFG                          (REG_DMA13_CFG)
-#define LP0_DMA_XCNT                         (REG_DMA13_XCNT)
-#define LP0_DMA_XMOD                         (REG_DMA13_XMOD)
-#define LP0_DMA_YCNT                         (REG_DMA13_YCNT)
-#define LP0_DMA_YMOD                         (REG_DMA13_YMOD)
-#define LP0_DMA_DSCPTR_CUR                   (REG_DMA13_DSCPTR_CUR)
-#define LP0_DMA_DSCPTR_PRV                   (REG_DMA13_DSCPTR_PRV)
-#define LP0_DMA_ADDR_CUR                     (REG_DMA13_ADDR_CUR)
-#define LP0_DMA_STAT                         (REG_DMA13_STAT)
-#define LP0_DMA_XCNT_CUR                     (REG_DMA13_XCNT_CUR)
-#define LP0_DMA_YCNT_CUR                     (REG_DMA13_YCNT_CUR)
-#define LP0_DMA_BWLCNT                       (REG_DMA13_BWLCNT)
-#define LP0_DMA_BWLCNT_CUR                   (REG_DMA13_BWLCNT_CUR)
-#define LP0_DMA_BWMCNT                       (REG_DMA13_BWMCNT)
-#define LP0_DMA_BWMCNT_CUR                   (REG_DMA13_BWMCNT_CUR)
-#define LP1_DMA_DSCPTR_NXT                   (REG_DMA14_DSCPTR_NXT)
-#define LP1_DMA_ADDRSTART                    (REG_DMA14_ADDRSTART)
-#define LP1_DMA_CFG                          (REG_DMA14_CFG)
-#define LP1_DMA_XCNT                         (REG_DMA14_XCNT)
-#define LP1_DMA_XMOD                         (REG_DMA14_XMOD)
-#define LP1_DMA_YCNT                         (REG_DMA14_YCNT)
-#define LP1_DMA_YMOD                         (REG_DMA14_YMOD)
-#define LP1_DMA_DSCPTR_CUR                   (REG_DMA14_DSCPTR_CUR)
-#define LP1_DMA_DSCPTR_PRV                   (REG_DMA14_DSCPTR_PRV)
-#define LP1_DMA_ADDR_CUR                     (REG_DMA14_ADDR_CUR)
-#define LP1_DMA_STAT                         (REG_DMA14_STAT)
-#define LP1_DMA_XCNT_CUR                     (REG_DMA14_XCNT_CUR)
-#define LP1_DMA_YCNT_CUR                     (REG_DMA14_YCNT_CUR)
-#define LP1_DMA_BWLCNT                       (REG_DMA14_BWLCNT)
-#define LP1_DMA_BWLCNT_CUR                   (REG_DMA14_BWLCNT_CUR)
-#define LP1_DMA_BWMCNT                       (REG_DMA14_BWMCNT)
-#define LP1_DMA_BWMCNT_CUR                   (REG_DMA14_BWMCNT_CUR)
-#define LP2_DMA_DSCPTR_NXT                   (REG_DMA15_DSCPTR_NXT)
-#define LP2_DMA_ADDRSTART                    (REG_DMA15_ADDRSTART)
-#define LP2_DMA_CFG                          (REG_DMA15_CFG)
-#define LP2_DMA_XCNT                         (REG_DMA15_XCNT)
-#define LP2_DMA_XMOD                         (REG_DMA15_XMOD)
-#define LP2_DMA_YCNT                         (REG_DMA15_YCNT)
-#define LP2_DMA_YMOD                         (REG_DMA15_YMOD)
-#define LP2_DMA_DSCPTR_CUR                   (REG_DMA15_DSCPTR_CUR)
-#define LP2_DMA_DSCPTR_PRV                   (REG_DMA15_DSCPTR_PRV)
-#define LP2_DMA_ADDR_CUR                     (REG_DMA15_ADDR_CUR)
-#define LP2_DMA_STAT                         (REG_DMA15_STAT)
-#define LP2_DMA_XCNT_CUR                     (REG_DMA15_XCNT_CUR)
-#define LP2_DMA_YCNT_CUR                     (REG_DMA15_YCNT_CUR)
-#define LP2_DMA_BWLCNT                       (REG_DMA15_BWLCNT)
-#define LP2_DMA_BWLCNT_CUR                   (REG_DMA15_BWLCNT_CUR)
-#define LP2_DMA_BWMCNT                       (REG_DMA15_BWMCNT)
-#define LP2_DMA_BWMCNT_CUR                   (REG_DMA15_BWMCNT_CUR)
-#define LP3_DMA_DSCPTR_NXT                   (REG_DMA16_DSCPTR_NXT)
-#define LP3_DMA_ADDRSTART                    (REG_DMA16_ADDRSTART)
-#define LP3_DMA_CFG                          (REG_DMA16_CFG)
-#define LP3_DMA_XCNT                         (REG_DMA16_XCNT)
-#define LP3_DMA_XMOD                         (REG_DMA16_XMOD)
-#define LP3_DMA_YCNT                         (REG_DMA16_YCNT)
-#define LP3_DMA_YMOD                         (REG_DMA16_YMOD)
-#define LP3_DMA_DSCPTR_CUR                   (REG_DMA16_DSCPTR_CUR)
-#define LP3_DMA_DSCPTR_PRV                   (REG_DMA16_DSCPTR_PRV)
-#define LP3_DMA_ADDR_CUR                     (REG_DMA16_ADDR_CUR)
-#define LP3_DMA_STAT                         (REG_DMA16_STAT)
-#define LP3_DMA_XCNT_CUR                     (REG_DMA16_XCNT_CUR)
-#define LP3_DMA_YCNT_CUR                     (REG_DMA16_YCNT_CUR)
-#define LP3_DMA_BWLCNT                       (REG_DMA16_BWLCNT)
-#define LP3_DMA_BWLCNT_CUR                   (REG_DMA16_BWLCNT_CUR)
-#define LP3_DMA_BWMCNT                       (REG_DMA16_BWMCNT)
-#define LP3_DMA_BWMCNT_CUR                   (REG_DMA16_BWMCNT_CUR)
-#define UART0_TXDMA_DSCPTR_NXT               (REG_DMA17_DSCPTR_NXT)
-#define UART0_TXDMA_ADDRSTART                (REG_DMA17_ADDRSTART)
-#define UART0_TXDMA_CFG                      (REG_DMA17_CFG)
-#define UART0_TXDMA_XCNT                     (REG_DMA17_XCNT)
-#define UART0_TXDMA_XMOD                     (REG_DMA17_XMOD)
-#define UART0_TXDMA_YCNT                     (REG_DMA17_YCNT)
-#define UART0_TXDMA_YMOD                     (REG_DMA17_YMOD)
-#define UART0_TXDMA_DSCPTR_CUR               (REG_DMA17_DSCPTR_CUR)
-#define UART0_TXDMA_DSCPTR_PRV               (REG_DMA17_DSCPTR_PRV)
-#define UART0_TXDMA_ADDR_CUR                 (REG_DMA17_ADDR_CUR)
-#define UART0_TXDMA_STAT                     (REG_DMA17_STAT)
-#define UART0_TXDMA_XCNT_CUR                 (REG_DMA17_XCNT_CUR)
-#define UART0_TXDMA_YCNT_CUR                 (REG_DMA17_YCNT_CUR)
-#define UART0_TXDMA_BWLCNT                   (REG_DMA17_BWLCNT)
-#define UART0_TXDMA_BWLCNT_CUR               (REG_DMA17_BWLCNT_CUR)
-#define UART0_TXDMA_BWMCNT                   (REG_DMA17_BWMCNT)
-#define UART0_TXDMA_BWMCNT_CUR               (REG_DMA17_BWMCNT_CUR)
-#define UART0_RXDMA_DSCPTR_NXT               (REG_DMA18_DSCPTR_NXT)
-#define UART0_RXDMA_ADDRSTART                (REG_DMA18_ADDRSTART)
-#define UART0_RXDMA_CFG                      (REG_DMA18_CFG)
-#define UART0_RXDMA_XCNT                     (REG_DMA18_XCNT)
-#define UART0_RXDMA_XMOD                     (REG_DMA18_XMOD)
-#define UART0_RXDMA_YCNT                     (REG_DMA18_YCNT)
-#define UART0_RXDMA_YMOD                     (REG_DMA18_YMOD)
-#define UART0_RXDMA_DSCPTR_CUR               (REG_DMA18_DSCPTR_CUR)
-#define UART0_RXDMA_DSCPTR_PRV               (REG_DMA18_DSCPTR_PRV)
-#define UART0_RXDMA_ADDR_CUR                 (REG_DMA18_ADDR_CUR)
-#define UART0_RXDMA_STAT                     (REG_DMA18_STAT)
-#define UART0_RXDMA_XCNT_CUR                 (REG_DMA18_XCNT_CUR)
-#define UART0_RXDMA_YCNT_CUR                 (REG_DMA18_YCNT_CUR)
-#define UART0_RXDMA_BWLCNT                   (REG_DMA18_BWLCNT)
-#define UART0_RXDMA_BWLCNT_CUR               (REG_DMA18_BWLCNT_CUR)
-#define UART0_RXDMA_BWMCNT                   (REG_DMA18_BWMCNT)
-#define UART0_RXDMA_BWMCNT_CUR               (REG_DMA18_BWMCNT_CUR)
-#define UART1_TXDMA_DSCPTR_NXT               (REG_DMA19_DSCPTR_NXT)
-#define UART1_TXDMA_ADDRSTART                (REG_DMA19_ADDRSTART)
-#define UART1_TXDMA_CFG                      (REG_DMA19_CFG)
-#define UART1_TXDMA_XCNT                     (REG_DMA19_XCNT)
-#define UART1_TXDMA_XMOD                     (REG_DMA19_XMOD)
-#define UART1_TXDMA_YCNT                     (REG_DMA19_YCNT)
-#define UART1_TXDMA_YMOD                     (REG_DMA19_YMOD)
-#define UART1_TXDMA_DSCPTR_CUR               (REG_DMA19_DSCPTR_CUR)
-#define UART1_TXDMA_DSCPTR_PRV               (REG_DMA19_DSCPTR_PRV)
-#define UART1_TXDMA_ADDR_CUR                 (REG_DMA19_ADDR_CUR)
-#define UART1_TXDMA_STAT                     (REG_DMA19_STAT)
-#define UART1_TXDMA_XCNT_CUR                 (REG_DMA19_XCNT_CUR)
-#define UART1_TXDMA_YCNT_CUR                 (REG_DMA19_YCNT_CUR)
-#define UART1_TXDMA_BWLCNT                   (REG_DMA19_BWLCNT)
-#define UART1_TXDMA_BWLCNT_CUR               (REG_DMA19_BWLCNT_CUR)
-#define UART1_TXDMA_BWMCNT                   (REG_DMA19_BWMCNT)
-#define UART1_TXDMA_BWMCNT_CUR               (REG_DMA19_BWMCNT_CUR)
-#define UART1_RXDMA_DSCPTR_NXT               (REG_DMA20_DSCPTR_NXT)
-#define UART1_RXDMA_ADDRSTART                (REG_DMA20_ADDRSTART)
-#define UART1_RXDMA_CFG                      (REG_DMA20_CFG)
-#define UART1_RXDMA_XCNT                     (REG_DMA20_XCNT)
-#define UART1_RXDMA_XMOD                     (REG_DMA20_XMOD)
-#define UART1_RXDMA_YCNT                     (REG_DMA20_YCNT)
-#define UART1_RXDMA_YMOD                     (REG_DMA20_YMOD)
-#define UART1_RXDMA_DSCPTR_CUR               (REG_DMA20_DSCPTR_CUR)
-#define UART1_RXDMA_DSCPTR_PRV               (REG_DMA20_DSCPTR_PRV)
-#define UART1_RXDMA_ADDR_CUR                 (REG_DMA20_ADDR_CUR)
-#define UART1_RXDMA_STAT                     (REG_DMA20_STAT)
-#define UART1_RXDMA_XCNT_CUR                 (REG_DMA20_XCNT_CUR)
-#define UART1_RXDMA_YCNT_CUR                 (REG_DMA20_YCNT_CUR)
-#define UART1_RXDMA_BWLCNT                   (REG_DMA20_BWLCNT)
-#define UART1_RXDMA_BWLCNT_CUR               (REG_DMA20_BWLCNT_CUR)
-#define UART1_RXDMA_BWMCNT                   (REG_DMA20_BWMCNT)
-#define UART1_RXDMA_BWMCNT_CUR               (REG_DMA20_BWMCNT_CUR)
-#define MDMA0_SRC_DSCPTR_NXT                 (REG_DMA21_DSCPTR_NXT)
-#define MDMA0_SRC_ADDRSTART                  (REG_DMA21_ADDRSTART)
-#define MDMA0_SRC_CFG                        (REG_DMA21_CFG)
-#define MDMA0_SRC_XCNT                       (REG_DMA21_XCNT)
-#define MDMA0_SRC_XMOD                       (REG_DMA21_XMOD)
-#define MDMA0_SRC_YCNT                       (REG_DMA21_YCNT)
-#define MDMA0_SRC_YMOD                       (REG_DMA21_YMOD)
-#define MDMA0_SRC_DSCPTR_CUR                 (REG_DMA21_DSCPTR_CUR)
-#define MDMA0_SRC_DSCPTR_PRV                 (REG_DMA21_DSCPTR_PRV)
-#define MDMA0_SRC_ADDR_CUR                   (REG_DMA21_ADDR_CUR)
-#define MDMA0_SRC_STAT                       (REG_DMA21_STAT)
-#define MDMA0_SRC_XCNT_CUR                   (REG_DMA21_XCNT_CUR)
-#define MDMA0_SRC_YCNT_CUR                   (REG_DMA21_YCNT_CUR)
-#define MDMA0_SRC_BWLCNT                     (REG_DMA21_BWLCNT)
-#define MDMA0_SRC_BWLCNT_CUR                 (REG_DMA21_BWLCNT_CUR)
-#define MDMA0_SRC_BWMCNT                     (REG_DMA21_BWMCNT)
-#define MDMA0_SRC_BWMCNT_CUR                 (REG_DMA21_BWMCNT_CUR)
-#define MDMA0_DST_DSCPTR_NXT                 (REG_DMA22_DSCPTR_NXT)
-#define MDMA0_DST_ADDRSTART                  (REG_DMA22_ADDRSTART)
-#define MDMA0_DST_CFG                        (REG_DMA22_CFG)
-#define MDMA0_DST_XCNT                       (REG_DMA22_XCNT)
-#define MDMA0_DST_XMOD                       (REG_DMA22_XMOD)
-#define MDMA0_DST_YCNT                       (REG_DMA22_YCNT)
-#define MDMA0_DST_YMOD                       (REG_DMA22_YMOD)
-#define MDMA0_DST_DSCPTR_CUR                 (REG_DMA22_DSCPTR_CUR)
-#define MDMA0_DST_DSCPTR_PRV                 (REG_DMA22_DSCPTR_PRV)
-#define MDMA0_DST_ADDR_CUR                   (REG_DMA22_ADDR_CUR)
-#define MDMA0_DST_STAT                       (REG_DMA22_STAT)
-#define MDMA0_DST_XCNT_CUR                   (REG_DMA22_XCNT_CUR)
-#define MDMA0_DST_YCNT_CUR                   (REG_DMA22_YCNT_CUR)
-#define MDMA0_DST_BWLCNT                     (REG_DMA22_BWLCNT)
-#define MDMA0_DST_BWLCNT_CUR                 (REG_DMA22_BWLCNT_CUR)
-#define MDMA0_DST_BWMCNT                     (REG_DMA22_BWMCNT)
-#define MDMA0_DST_BWMCNT_CUR                 (REG_DMA22_BWMCNT_CUR)
-#define MDMA1_SRC_DSCPTR_NXT                 (REG_DMA23_DSCPTR_NXT)
-#define MDMA1_SRC_ADDRSTART                  (REG_DMA23_ADDRSTART)
-#define MDMA1_SRC_CFG                        (REG_DMA23_CFG)
-#define MDMA1_SRC_XCNT                       (REG_DMA23_XCNT)
-#define MDMA1_SRC_XMOD                       (REG_DMA23_XMOD)
-#define MDMA1_SRC_YCNT                       (REG_DMA23_YCNT)
-#define MDMA1_SRC_YMOD                       (REG_DMA23_YMOD)
-#define MDMA1_SRC_DSCPTR_CUR                 (REG_DMA23_DSCPTR_CUR)
-#define MDMA1_SRC_DSCPTR_PRV                 (REG_DMA23_DSCPTR_PRV)
-#define MDMA1_SRC_ADDR_CUR                   (REG_DMA23_ADDR_CUR)
-#define MDMA1_SRC_STAT                       (REG_DMA23_STAT)
-#define MDMA1_SRC_XCNT_CUR                   (REG_DMA23_XCNT_CUR)
-#define MDMA1_SRC_YCNT_CUR                   (REG_DMA23_YCNT_CUR)
-#define MDMA1_SRC_BWLCNT                     (REG_DMA23_BWLCNT)
-#define MDMA1_SRC_BWLCNT_CUR                 (REG_DMA23_BWLCNT_CUR)
-#define MDMA1_SRC_BWMCNT                     (REG_DMA23_BWMCNT)
-#define MDMA1_SRC_BWMCNT_CUR                 (REG_DMA23_BWMCNT_CUR)
-#define MDMA1_DST_DSCPTR_NXT                 (REG_DMA24_DSCPTR_NXT)
-#define MDMA1_DST_ADDRSTART                  (REG_DMA24_ADDRSTART)
-#define MDMA1_DST_CFG                        (REG_DMA24_CFG)
-#define MDMA1_DST_XCNT                       (REG_DMA24_XCNT)
-#define MDMA1_DST_XMOD                       (REG_DMA24_XMOD)
-#define MDMA1_DST_YCNT                       (REG_DMA24_YCNT)
-#define MDMA1_DST_YMOD                       (REG_DMA24_YMOD)
-#define MDMA1_DST_DSCPTR_CUR                 (REG_DMA24_DSCPTR_CUR)
-#define MDMA1_DST_DSCPTR_PRV                 (REG_DMA24_DSCPTR_PRV)
-#define MDMA1_DST_ADDR_CUR                   (REG_DMA24_ADDR_CUR)
-#define MDMA1_DST_STAT                       (REG_DMA24_STAT)
-#define MDMA1_DST_XCNT_CUR                   (REG_DMA24_XCNT_CUR)
-#define MDMA1_DST_YCNT_CUR                   (REG_DMA24_YCNT_CUR)
-#define MDMA1_DST_BWLCNT                     (REG_DMA24_BWLCNT)
-#define MDMA1_DST_BWLCNT_CUR                 (REG_DMA24_BWLCNT_CUR)
-#define MDMA1_DST_BWMCNT                     (REG_DMA24_BWMCNT)
-#define MDMA1_DST_BWMCNT_CUR                 (REG_DMA24_BWMCNT_CUR)
-#define MDMA2_SRC_DSCPTR_NXT                 (REG_DMA25_DSCPTR_NXT)
-#define MDMA2_SRC_ADDRSTART                  (REG_DMA25_ADDRSTART)
-#define MDMA2_SRC_CFG                        (REG_DMA25_CFG)
-#define MDMA2_SRC_XCNT                       (REG_DMA25_XCNT)
-#define MDMA2_SRC_XMOD                       (REG_DMA25_XMOD)
-#define MDMA2_SRC_YCNT                       (REG_DMA25_YCNT)
-#define MDMA2_SRC_YMOD                       (REG_DMA25_YMOD)
-#define MDMA2_SRC_DSCPTR_CUR                 (REG_DMA25_DSCPTR_CUR)
-#define MDMA2_SRC_DSCPTR_PRV                 (REG_DMA25_DSCPTR_PRV)
-#define MDMA2_SRC_ADDR_CUR                   (REG_DMA25_ADDR_CUR)
-#define MDMA2_SRC_STAT                       (REG_DMA25_STAT)
-#define MDMA2_SRC_XCNT_CUR                   (REG_DMA25_XCNT_CUR)
-#define MDMA2_SRC_YCNT_CUR                   (REG_DMA25_YCNT_CUR)
-#define MDMA2_SRC_BWLCNT                     (REG_DMA25_BWLCNT)
-#define MDMA2_SRC_BWLCNT_CUR                 (REG_DMA25_BWLCNT_CUR)
-#define MDMA2_SRC_BWMCNT                     (REG_DMA25_BWMCNT)
-#define MDMA2_SRC_BWMCNT_CUR                 (REG_DMA25_BWMCNT_CUR)
-#define MDMA2_DST_DSCPTR_NXT                 (REG_DMA26_DSCPTR_NXT)
-#define MDMA2_DST_ADDRSTART                  (REG_DMA26_ADDRSTART)
-#define MDMA2_DST_CFG                        (REG_DMA26_CFG)
-#define MDMA2_DST_XCNT                       (REG_DMA26_XCNT)
-#define MDMA2_DST_XMOD                       (REG_DMA26_XMOD)
-#define MDMA2_DST_YCNT                       (REG_DMA26_YCNT)
-#define MDMA2_DST_YMOD                       (REG_DMA26_YMOD)
-#define MDMA2_DST_DSCPTR_CUR                 (REG_DMA26_DSCPTR_CUR)
-#define MDMA2_DST_DSCPTR_PRV                 (REG_DMA26_DSCPTR_PRV)
-#define MDMA2_DST_ADDR_CUR                   (REG_DMA26_ADDR_CUR)
-#define MDMA2_DST_STAT                       (REG_DMA26_STAT)
-#define MDMA2_DST_XCNT_CUR                   (REG_DMA26_XCNT_CUR)
-#define MDMA2_DST_YCNT_CUR                   (REG_DMA26_YCNT_CUR)
-#define MDMA2_DST_BWLCNT                     (REG_DMA26_BWLCNT)
-#define MDMA2_DST_BWLCNT_CUR                 (REG_DMA26_BWLCNT_CUR)
-#define MDMA2_DST_BWMCNT                     (REG_DMA26_BWMCNT)
-#define MDMA2_DST_BWMCNT_CUR                 (REG_DMA26_BWMCNT_CUR)
-#define MDMA3_SRC_DSCPTR_NXT                 (REG_DMA27_DSCPTR_NXT)
-#define MDMA3_SRC_ADDRSTART                  (REG_DMA27_ADDRSTART)
-#define MDMA3_SRC_CFG                        (REG_DMA27_CFG)
-#define MDMA3_SRC_XCNT                       (REG_DMA27_XCNT)
-#define MDMA3_SRC_XMOD                       (REG_DMA27_XMOD)
-#define MDMA3_SRC_YCNT                       (REG_DMA27_YCNT)
-#define MDMA3_SRC_YMOD                       (REG_DMA27_YMOD)
-#define MDMA3_SRC_DSCPTR_CUR                 (REG_DMA27_DSCPTR_CUR)
-#define MDMA3_SRC_DSCPTR_PRV                 (REG_DMA27_DSCPTR_PRV)
-#define MDMA3_SRC_ADDR_CUR                   (REG_DMA27_ADDR_CUR)
-#define MDMA3_SRC_STAT                       (REG_DMA27_STAT)
-#define MDMA3_SRC_XCNT_CUR                   (REG_DMA27_XCNT_CUR)
-#define MDMA3_SRC_YCNT_CUR                   (REG_DMA27_YCNT_CUR)
-#define MDMA3_SRC_BWLCNT                     (REG_DMA27_BWLCNT)
-#define MDMA3_SRC_BWLCNT_CUR                 (REG_DMA27_BWLCNT_CUR)
-#define MDMA3_SRC_BWMCNT                     (REG_DMA27_BWMCNT)
-#define MDMA3_SRC_BWMCNT_CUR                 (REG_DMA27_BWMCNT_CUR)
-#define MDMA3_DST_DSCPTR_NXT                 (REG_DMA28_DSCPTR_NXT)
-#define MDMA3_DST_ADDRSTART                  (REG_DMA28_ADDRSTART)
-#define MDMA3_DST_CFG                        (REG_DMA28_CFG)
-#define MDMA3_DST_XCNT                       (REG_DMA28_XCNT)
-#define MDMA3_DST_XMOD                       (REG_DMA28_XMOD)
-#define MDMA3_DST_YCNT                       (REG_DMA28_YCNT)
-#define MDMA3_DST_YMOD                       (REG_DMA28_YMOD)
-#define MDMA3_DST_DSCPTR_CUR                 (REG_DMA28_DSCPTR_CUR)
-#define MDMA3_DST_DSCPTR_PRV                 (REG_DMA28_DSCPTR_PRV)
-#define MDMA3_DST_ADDR_CUR                   (REG_DMA28_ADDR_CUR)
-#define MDMA3_DST_STAT                       (REG_DMA28_STAT)
-#define MDMA3_DST_XCNT_CUR                   (REG_DMA28_XCNT_CUR)
-#define MDMA3_DST_YCNT_CUR                   (REG_DMA28_YCNT_CUR)
-#define MDMA3_DST_BWLCNT                     (REG_DMA28_BWLCNT)
-#define MDMA3_DST_BWLCNT_CUR                 (REG_DMA28_BWLCNT_CUR)
-#define MDMA3_DST_BWMCNT                     (REG_DMA28_BWMCNT)
-#define MDMA3_DST_BWMCNT_CUR                 (REG_DMA28_BWMCNT_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_NXT             (REG_DMA29_DSCPTR_NXT)
-#define EPPI0_CH0_DMA_ADDRSTART              (REG_DMA29_ADDRSTART)
-#define EPPI0_CH0_DMA_CFG                    (REG_DMA29_CFG)
-#define EPPI0_CH0_DMA_XCNT                   (REG_DMA29_XCNT)
-#define EPPI0_CH0_DMA_XMOD                   (REG_DMA29_XMOD)
-#define EPPI0_CH0_DMA_YCNT                   (REG_DMA29_YCNT)
-#define EPPI0_CH0_DMA_YMOD                   (REG_DMA29_YMOD)
-#define EPPI0_CH0_DMA_DSCPTR_CUR             (REG_DMA29_DSCPTR_CUR)
-#define EPPI0_CH0_DMA_DSCPTR_PRV             (REG_DMA29_DSCPTR_PRV)
-#define EPPI0_CH0_DMA_ADDR_CUR               (REG_DMA29_ADDR_CUR)
-#define EPPI0_CH0_DMA_STAT                   (REG_DMA29_STAT)
-#define EPPI0_CH0_DMA_XCNT_CUR               (REG_DMA29_XCNT_CUR)
-#define EPPI0_CH0_DMA_YCNT_CUR               (REG_DMA29_YCNT_CUR)
-#define EPPI0_CH0_DMA_BWLCNT                 (REG_DMA29_BWLCNT)
-#define EPPI0_CH0_DMA_BWLCNT_CUR             (REG_DMA29_BWLCNT_CUR)
-#define EPPI0_CH0_DMA_BWMCNT                 (REG_DMA29_BWMCNT)
-#define EPPI0_CH0_DMA_BWMCNT_CUR             (REG_DMA29_BWMCNT_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_NXT             (REG_DMA30_DSCPTR_NXT)
-#define EPPI0_CH1_DMA_ADDRSTART              (REG_DMA30_ADDRSTART)
-#define EPPI0_CH1_DMA_CFG                    (REG_DMA30_CFG)
-#define EPPI0_CH1_DMA_XCNT                   (REG_DMA30_XCNT)
-#define EPPI0_CH1_DMA_XMOD                   (REG_DMA30_XMOD)
-#define EPPI0_CH1_DMA_YCNT                   (REG_DMA30_YCNT)
-#define EPPI0_CH1_DMA_YMOD                   (REG_DMA30_YMOD)
-#define EPPI0_CH1_DMA_DSCPTR_CUR             (REG_DMA30_DSCPTR_CUR)
-#define EPPI0_CH1_DMA_DSCPTR_PRV             (REG_DMA30_DSCPTR_PRV)
-#define EPPI0_CH1_DMA_ADDR_CUR               (REG_DMA30_ADDR_CUR)
-#define EPPI0_CH1_DMA_STAT                   (REG_DMA30_STAT)
-#define EPPI0_CH1_DMA_XCNT_CUR               (REG_DMA30_XCNT_CUR)
-#define EPPI0_CH1_DMA_YCNT_CUR               (REG_DMA30_YCNT_CUR)
-#define EPPI0_CH1_DMA_BWLCNT                 (REG_DMA30_BWLCNT)
-#define EPPI0_CH1_DMA_BWLCNT_CUR             (REG_DMA30_BWLCNT_CUR)
-#define EPPI0_CH1_DMA_BWMCNT                 (REG_DMA30_BWMCNT)
-#define EPPI0_CH1_DMA_BWMCNT_CUR             (REG_DMA30_BWMCNT_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_NXT             (REG_DMA31_DSCPTR_NXT)
-#define EPPI2_CH0_DMA_ADDRSTART              (REG_DMA31_ADDRSTART)
-#define EPPI2_CH0_DMA_CFG                    (REG_DMA31_CFG)
-#define EPPI2_CH0_DMA_XCNT                   (REG_DMA31_XCNT)
-#define EPPI2_CH0_DMA_XMOD                   (REG_DMA31_XMOD)
-#define EPPI2_CH0_DMA_YCNT                   (REG_DMA31_YCNT)
-#define EPPI2_CH0_DMA_YMOD                   (REG_DMA31_YMOD)
-#define EPPI2_CH0_DMA_DSCPTR_CUR             (REG_DMA31_DSCPTR_CUR)
-#define EPPI2_CH0_DMA_DSCPTR_PRV             (REG_DMA31_DSCPTR_PRV)
-#define EPPI2_CH0_DMA_ADDR_CUR               (REG_DMA31_ADDR_CUR)
-#define EPPI2_CH0_DMA_STAT                   (REG_DMA31_STAT)
-#define EPPI2_CH0_DMA_XCNT_CUR               (REG_DMA31_XCNT_CUR)
-#define EPPI2_CH0_DMA_YCNT_CUR               (REG_DMA31_YCNT_CUR)
-#define EPPI2_CH0_DMA_BWLCNT                 (REG_DMA31_BWLCNT)
-#define EPPI2_CH0_DMA_BWLCNT_CUR             (REG_DMA31_BWLCNT_CUR)
-#define EPPI2_CH0_DMA_BWMCNT                 (REG_DMA31_BWMCNT)
-#define EPPI2_CH0_DMA_BWMCNT_CUR             (REG_DMA31_BWMCNT_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_NXT             (REG_DMA32_DSCPTR_NXT)
-#define EPPI2_CH1_DMA_ADDRSTART              (REG_DMA32_ADDRSTART)
-#define EPPI2_CH1_DMA_CFG                    (REG_DMA32_CFG)
-#define EPPI2_CH1_DMA_XCNT                   (REG_DMA32_XCNT)
-#define EPPI2_CH1_DMA_XMOD                   (REG_DMA32_XMOD)
-#define EPPI2_CH1_DMA_YCNT                   (REG_DMA32_YCNT)
-#define EPPI2_CH1_DMA_YMOD                   (REG_DMA32_YMOD)
-#define EPPI2_CH1_DMA_DSCPTR_CUR             (REG_DMA32_DSCPTR_CUR)
-#define EPPI2_CH1_DMA_DSCPTR_PRV             (REG_DMA32_DSCPTR_PRV)
-#define EPPI2_CH1_DMA_ADDR_CUR               (REG_DMA32_ADDR_CUR)
-#define EPPI2_CH1_DMA_STAT                   (REG_DMA32_STAT)
-#define EPPI2_CH1_DMA_XCNT_CUR               (REG_DMA32_XCNT_CUR)
-#define EPPI2_CH1_DMA_YCNT_CUR               (REG_DMA32_YCNT_CUR)
-#define EPPI2_CH1_DMA_BWLCNT                 (REG_DMA32_BWLCNT)
-#define EPPI2_CH1_DMA_BWLCNT_CUR             (REG_DMA32_BWLCNT_CUR)
-#define EPPI2_CH1_DMA_BWMCNT                 (REG_DMA32_BWMCNT)
-#define EPPI2_CH1_DMA_BWMCNT_CUR             (REG_DMA32_BWMCNT_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_NXT             (REG_DMA33_DSCPTR_NXT)
-#define EPPI1_CH0_DMA_ADDRSTART              (REG_DMA33_ADDRSTART)
-#define EPPI1_CH0_DMA_CFG                    (REG_DMA33_CFG)
-#define EPPI1_CH0_DMA_XCNT                   (REG_DMA33_XCNT)
-#define EPPI1_CH0_DMA_XMOD                   (REG_DMA33_XMOD)
-#define EPPI1_CH0_DMA_YCNT                   (REG_DMA33_YCNT)
-#define EPPI1_CH0_DMA_YMOD                   (REG_DMA33_YMOD)
-#define EPPI1_CH0_DMA_DSCPTR_CUR             (REG_DMA33_DSCPTR_CUR)
-#define EPPI1_CH0_DMA_DSCPTR_PRV             (REG_DMA33_DSCPTR_PRV)
-#define EPPI1_CH0_DMA_ADDR_CUR               (REG_DMA33_ADDR_CUR)
-#define EPPI1_CH0_DMA_STAT                   (REG_DMA33_STAT)
-#define EPPI1_CH0_DMA_XCNT_CUR               (REG_DMA33_XCNT_CUR)
-#define EPPI1_CH0_DMA_YCNT_CUR               (REG_DMA33_YCNT_CUR)
-#define EPPI1_CH0_DMA_BWLCNT                 (REG_DMA33_BWLCNT)
-#define EPPI1_CH0_DMA_BWLCNT_CUR             (REG_DMA33_BWLCNT_CUR)
-#define EPPI1_CH0_DMA_BWMCNT                 (REG_DMA33_BWMCNT)
-#define EPPI1_CH0_DMA_BWMCNT_CUR             (REG_DMA33_BWMCNT_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_NXT             (REG_DMA34_DSCPTR_NXT)
-#define EPPI1_CH1_DMA_ADDRSTART              (REG_DMA34_ADDRSTART)
-#define EPPI1_CH1_DMA_CFG                    (REG_DMA34_CFG)
-#define EPPI1_CH1_DMA_XCNT                   (REG_DMA34_XCNT)
-#define EPPI1_CH1_DMA_XMOD                   (REG_DMA34_XMOD)
-#define EPPI1_CH1_DMA_YCNT                   (REG_DMA34_YCNT)
-#define EPPI1_CH1_DMA_YMOD                   (REG_DMA34_YMOD)
-#define EPPI1_CH1_DMA_DSCPTR_CUR             (REG_DMA34_DSCPTR_CUR)
-#define EPPI1_CH1_DMA_DSCPTR_PRV             (REG_DMA34_DSCPTR_PRV)
-#define EPPI1_CH1_DMA_ADDR_CUR               (REG_DMA34_ADDR_CUR)
-#define EPPI1_CH1_DMA_STAT                   (REG_DMA34_STAT)
-#define EPPI1_CH1_DMA_XCNT_CUR               (REG_DMA34_XCNT_CUR)
-#define EPPI1_CH1_DMA_YCNT_CUR               (REG_DMA34_YCNT_CUR)
-#define EPPI1_CH1_DMA_BWLCNT                 (REG_DMA34_BWLCNT)
-#define EPPI1_CH1_DMA_BWLCNT_CUR             (REG_DMA34_BWLCNT_CUR)
-#define EPPI1_CH1_DMA_BWMCNT                 (REG_DMA34_BWMCNT)
-#define EPPI1_CH1_DMA_BWMCNT_CUR             (REG_DMA34_BWMCNT_CUR)
-#define PIXC0_CH0_DMA_DSCPTR_NXT             (REG_DMA35_DSCPTR_NXT)
-#define PIXC0_CH0_DMA_ADDRSTART              (REG_DMA35_ADDRSTART)
-#define PIXC0_CH0_DMA_CFG                    (REG_DMA35_CFG)
-#define PIXC0_CH0_DMA_XCNT                   (REG_DMA35_XCNT)
-#define PIXC0_CH0_DMA_XMOD                   (REG_DMA35_XMOD)
-#define PIXC0_CH0_DMA_YCNT                   (REG_DMA35_YCNT)
-#define PIXC0_CH0_DMA_YMOD                   (REG_DMA35_YMOD)
-#define PIXC0_CH0_DMA_DSCPTR_CUR             (REG_DMA35_DSCPTR_CUR)
-#define PIXC0_CH0_DMA_DSCPTR_PRV             (REG_DMA35_DSCPTR_PRV)
-#define PIXC0_CH0_DMA_ADDR_CUR               (REG_DMA35_ADDR_CUR)
-#define PIXC0_CH0_DMA_STAT                   (REG_DMA35_STAT)
-#define PIXC0_CH0_DMA_XCNT_CUR               (REG_DMA35_XCNT_CUR)
-#define PIXC0_CH0_DMA_YCNT_CUR               (REG_DMA35_YCNT_CUR)
-#define PIXC0_CH0_DMA_BWLCNT                 (REG_DMA35_BWLCNT)
-#define PIXC0_CH0_DMA_BWLCNT_CUR             (REG_DMA35_BWLCNT_CUR)
-#define PIXC0_CH0_DMA_BWMCNT                 (REG_DMA35_BWMCNT)
-#define PIXC0_CH0_DMA_BWMCNT_CUR             (REG_DMA35_BWMCNT_CUR)
-#define PIXC0_CH1_DMA_DSCPTR_NXT             (REG_DMA36_DSCPTR_NXT)
-#define PIXC0_CH1_DMA_ADDRSTART              (REG_DMA36_ADDRSTART)
-#define PIXC0_CH1_DMA_CFG                    (REG_DMA36_CFG)
-#define PIXC0_CH1_DMA_XCNT                   (REG_DMA36_XCNT)
-#define PIXC0_CH1_DMA_XMOD                   (REG_DMA36_XMOD)
-#define PIXC0_CH1_DMA_YCNT                   (REG_DMA36_YCNT)
-#define PIXC0_CH1_DMA_YMOD                   (REG_DMA36_YMOD)
-#define PIXC0_CH1_DMA_DSCPTR_CUR             (REG_DMA36_DSCPTR_CUR)
-#define PIXC0_CH1_DMA_DSCPTR_PRV             (REG_DMA36_DSCPTR_PRV)
-#define PIXC0_CH1_DMA_ADDR_CUR               (REG_DMA36_ADDR_CUR)
-#define PIXC0_CH1_DMA_STAT                   (REG_DMA36_STAT)
-#define PIXC0_CH1_DMA_XCNT_CUR               (REG_DMA36_XCNT_CUR)
-#define PIXC0_CH1_DMA_YCNT_CUR               (REG_DMA36_YCNT_CUR)
-#define PIXC0_CH1_DMA_BWLCNT                 (REG_DMA36_BWLCNT)
-#define PIXC0_CH1_DMA_BWLCNT_CUR             (REG_DMA36_BWLCNT_CUR)
-#define PIXC0_CH1_DMA_BWMCNT                 (REG_DMA36_BWMCNT)
-#define PIXC0_CH1_DMA_BWMCNT_CUR             (REG_DMA36_BWMCNT_CUR)
-#define PIXC0_CH2_DMA_DSCPTR_NXT             (REG_DMA37_DSCPTR_NXT)
-#define PIXC0_CH2_DMA_ADDRSTART              (REG_DMA37_ADDRSTART)
-#define PIXC0_CH2_DMA_CFG                    (REG_DMA37_CFG)
-#define PIXC0_CH2_DMA_XCNT                   (REG_DMA37_XCNT)
-#define PIXC0_CH2_DMA_XMOD                   (REG_DMA37_XMOD)
-#define PIXC0_CH2_DMA_YCNT                   (REG_DMA37_YCNT)
-#define PIXC0_CH2_DMA_YMOD                   (REG_DMA37_YMOD)
-#define PIXC0_CH2_DMA_DSCPTR_CUR             (REG_DMA37_DSCPTR_CUR)
-#define PIXC0_CH2_DMA_DSCPTR_PRV             (REG_DMA37_DSCPTR_PRV)
-#define PIXC0_CH2_DMA_ADDR_CUR               (REG_DMA37_ADDR_CUR)
-#define PIXC0_CH2_DMA_STAT                   (REG_DMA37_STAT)
-#define PIXC0_CH2_DMA_XCNT_CUR               (REG_DMA37_XCNT_CUR)
-#define PIXC0_CH2_DMA_YCNT_CUR               (REG_DMA37_YCNT_CUR)
-#define PIXC0_CH2_DMA_BWLCNT                 (REG_DMA37_BWLCNT)
-#define PIXC0_CH2_DMA_BWLCNT_CUR             (REG_DMA37_BWLCNT_CUR)
-#define PIXC0_CH2_DMA_BWMCNT                 (REG_DMA37_BWMCNT)
-#define PIXC0_CH2_DMA_BWMCNT_CUR             (REG_DMA37_BWMCNT_CUR)
-#define PVP0_CPDOB_DMA_DSCPTR_NXT            (REG_DMA38_DSCPTR_NXT)
-#define PVP0_CPDOB_DMA_ADDRSTART             (REG_DMA38_ADDRSTART)
-#define PVP0_CPDOB_DMA_CFG                   (REG_DMA38_CFG)
-#define PVP0_CPDOB_DMA_XCNT                  (REG_DMA38_XCNT)
-#define PVP0_CPDOB_DMA_XMOD                  (REG_DMA38_XMOD)
-#define PVP0_CPDOB_DMA_YCNT                  (REG_DMA38_YCNT)
-#define PVP0_CPDOB_DMA_YMOD                  (REG_DMA38_YMOD)
-#define PVP0_CPDOB_DMA_DSCPTR_CUR            (REG_DMA38_DSCPTR_CUR)
-#define PVP0_CPDOB_DMA_DSCPTR_PRV            (REG_DMA38_DSCPTR_PRV)
-#define PVP0_CPDOB_DMA_ADDR_CUR              (REG_DMA38_ADDR_CUR)
-#define PVP0_CPDOB_DMA_STAT                  (REG_DMA38_STAT)
-#define PVP0_CPDOB_DMA_XCNT_CUR              (REG_DMA38_XCNT_CUR)
-#define PVP0_CPDOB_DMA_YCNT_CUR              (REG_DMA38_YCNT_CUR)
-#define PVP0_CPDOB_DMA_BWLCNT                (REG_DMA38_BWLCNT)
-#define PVP0_CPDOB_DMA_BWLCNT_CUR            (REG_DMA38_BWLCNT_CUR)
-#define PVP0_CPDOB_DMA_BWMCNT                (REG_DMA38_BWMCNT)
-#define PVP0_CPDOB_DMA_BWMCNT_CUR            (REG_DMA38_BWMCNT_CUR)
-#define PVP0_CPDOC_DMA_DSCPTR_NXT            (REG_DMA39_DSCPTR_NXT)
-#define PVP0_CPDOC_DMA_ADDRSTART             (REG_DMA39_ADDRSTART)
-#define PVP0_CPDOC_DMA_CFG                   (REG_DMA39_CFG)
-#define PVP0_CPDOC_DMA_XCNT                  (REG_DMA39_XCNT)
-#define PVP0_CPDOC_DMA_XMOD                  (REG_DMA39_XMOD)
-#define PVP0_CPDOC_DMA_YCNT                  (REG_DMA39_YCNT)
-#define PVP0_CPDOC_DMA_YMOD                  (REG_DMA39_YMOD)
-#define PVP0_CPDOC_DMA_DSCPTR_CUR            (REG_DMA39_DSCPTR_CUR)
-#define PVP0_CPDOC_DMA_DSCPTR_PRV            (REG_DMA39_DSCPTR_PRV)
-#define PVP0_CPDOC_DMA_ADDR_CUR              (REG_DMA39_ADDR_CUR)
-#define PVP0_CPDOC_DMA_STAT                  (REG_DMA39_STAT)
-#define PVP0_CPDOC_DMA_XCNT_CUR              (REG_DMA39_XCNT_CUR)
-#define PVP0_CPDOC_DMA_YCNT_CUR              (REG_DMA39_YCNT_CUR)
-#define PVP0_CPDOC_DMA_BWLCNT                (REG_DMA39_BWLCNT)
-#define PVP0_CPDOC_DMA_BWLCNT_CUR            (REG_DMA39_BWLCNT_CUR)
-#define PVP0_CPDOC_DMA_BWMCNT                (REG_DMA39_BWMCNT)
-#define PVP0_CPDOC_DMA_BWMCNT_CUR            (REG_DMA39_BWMCNT_CUR)
-#define PVP0_CPSTAT_DMA_DSCPTR_NXT           (REG_DMA40_DSCPTR_NXT)
-#define PVP0_CPSTAT_DMA_ADDRSTART            (REG_DMA40_ADDRSTART)
-#define PVP0_CPSTAT_DMA_CFG                  (REG_DMA40_CFG)
-#define PVP0_CPSTAT_DMA_XCNT                 (REG_DMA40_XCNT)
-#define PVP0_CPSTAT_DMA_XMOD                 (REG_DMA40_XMOD)
-#define PVP0_CPSTAT_DMA_YCNT                 (REG_DMA40_YCNT)
-#define PVP0_CPSTAT_DMA_YMOD                 (REG_DMA40_YMOD)
-#define PVP0_CPSTAT_DMA_DSCPTR_CUR           (REG_DMA40_DSCPTR_CUR)
-#define PVP0_CPSTAT_DMA_DSCPTR_PRV           (REG_DMA40_DSCPTR_PRV)
-#define PVP0_CPSTAT_DMA_ADDR_CUR             (REG_DMA40_ADDR_CUR)
-#define PVP0_CPSTAT_DMA_STAT                 (REG_DMA40_STAT)
-#define PVP0_CPSTAT_DMA_XCNT_CUR             (REG_DMA40_XCNT_CUR)
-#define PVP0_CPSTAT_DMA_YCNT_CUR             (REG_DMA40_YCNT_CUR)
-#define PVP0_CPSTAT_DMA_BWLCNT               (REG_DMA40_BWLCNT)
-#define PVP0_CPSTAT_DMA_BWLCNT_CUR           (REG_DMA40_BWLCNT_CUR)
-#define PVP0_CPSTAT_DMA_BWMCNT               (REG_DMA40_BWMCNT)
-#define PVP0_CPSTAT_DMA_BWMCNT_CUR           (REG_DMA40_BWMCNT_CUR)
-#define PVP0_CPCI_DMA_DSCPTR_NXT             (REG_DMA41_DSCPTR_NXT)
-#define PVP0_CPCI_DMA_ADDRSTART              (REG_DMA41_ADDRSTART)
-#define PVP0_CPCI_DMA_CFG                    (REG_DMA41_CFG)
-#define PVP0_CPCI_DMA_XCNT                   (REG_DMA41_XCNT)
-#define PVP0_CPCI_DMA_XMOD                   (REG_DMA41_XMOD)
-#define PVP0_CPCI_DMA_YCNT                   (REG_DMA41_YCNT)
-#define PVP0_CPCI_DMA_YMOD                   (REG_DMA41_YMOD)
-#define PVP0_CPCI_DMA_DSCPTR_CUR             (REG_DMA41_DSCPTR_CUR)
-#define PVP0_CPCI_DMA_DSCPTR_PRV             (REG_DMA41_DSCPTR_PRV)
-#define PVP0_CPCI_DMA_ADDR_CUR               (REG_DMA41_ADDR_CUR)
-#define PVP0_CPCI_DMA_STAT                   (REG_DMA41_STAT)
-#define PVP0_CPCI_DMA_XCNT_CUR               (REG_DMA41_XCNT_CUR)
-#define PVP0_CPCI_DMA_YCNT_CUR               (REG_DMA41_YCNT_CUR)
-#define PVP0_CPCI_DMA_BWLCNT                 (REG_DMA41_BWLCNT)
-#define PVP0_CPCI_DMA_BWLCNT_CUR             (REG_DMA41_BWLCNT_CUR)
-#define PVP0_CPCI_DMA_BWMCNT                 (REG_DMA41_BWMCNT)
-#define PVP0_CPCI_DMA_BWMCNT_CUR             (REG_DMA41_BWMCNT_CUR)
-#define PVP0_MPDO_DMA_DSCPTR_NXT             (REG_DMA42_DSCPTR_NXT)
-#define PVP0_MPDO_DMA_ADDRSTART              (REG_DMA42_ADDRSTART)
-#define PVP0_MPDO_DMA_CFG                    (REG_DMA42_CFG)
-#define PVP0_MPDO_DMA_XCNT                   (REG_DMA42_XCNT)
-#define PVP0_MPDO_DMA_XMOD                   (REG_DMA42_XMOD)
-#define PVP0_MPDO_DMA_YCNT                   (REG_DMA42_YCNT)
-#define PVP0_MPDO_DMA_YMOD                   (REG_DMA42_YMOD)
-#define PVP0_MPDO_DMA_DSCPTR_CUR             (REG_DMA42_DSCPTR_CUR)
-#define PVP0_MPDO_DMA_DSCPTR_PRV             (REG_DMA42_DSCPTR_PRV)
-#define PVP0_MPDO_DMA_ADDR_CUR               (REG_DMA42_ADDR_CUR)
-#define PVP0_MPDO_DMA_STAT                   (REG_DMA42_STAT)
-#define PVP0_MPDO_DMA_XCNT_CUR               (REG_DMA42_XCNT_CUR)
-#define PVP0_MPDO_DMA_YCNT_CUR               (REG_DMA42_YCNT_CUR)
-#define PVP0_MPDO_DMA_BWLCNT                 (REG_DMA42_BWLCNT)
-#define PVP0_MPDO_DMA_BWLCNT_CUR             (REG_DMA42_BWLCNT_CUR)
-#define PVP0_MPDO_DMA_BWMCNT                 (REG_DMA42_BWMCNT)
-#define PVP0_MPDO_DMA_BWMCNT_CUR             (REG_DMA42_BWMCNT_CUR)
-#define PVP0_MPDI_DMA_DSCPTR_NXT             (REG_DMA43_DSCPTR_NXT)
-#define PVP0_MPDI_DMA_ADDRSTART              (REG_DMA43_ADDRSTART)
-#define PVP0_MPDI_DMA_CFG                    (REG_DMA43_CFG)
-#define PVP0_MPDI_DMA_XCNT                   (REG_DMA43_XCNT)
-#define PVP0_MPDI_DMA_XMOD                   (REG_DMA43_XMOD)
-#define PVP0_MPDI_DMA_YCNT                   (REG_DMA43_YCNT)
-#define PVP0_MPDI_DMA_YMOD                   (REG_DMA43_YMOD)
-#define PVP0_MPDI_DMA_DSCPTR_CUR             (REG_DMA43_DSCPTR_CUR)
-#define PVP0_MPDI_DMA_DSCPTR_PRV             (REG_DMA43_DSCPTR_PRV)
-#define PVP0_MPDI_DMA_ADDR_CUR               (REG_DMA43_ADDR_CUR)
-#define PVP0_MPDI_DMA_STAT                   (REG_DMA43_STAT)
-#define PVP0_MPDI_DMA_XCNT_CUR               (REG_DMA43_XCNT_CUR)
-#define PVP0_MPDI_DMA_YCNT_CUR               (REG_DMA43_YCNT_CUR)
-#define PVP0_MPDI_DMA_BWLCNT                 (REG_DMA43_BWLCNT)
-#define PVP0_MPDI_DMA_BWLCNT_CUR             (REG_DMA43_BWLCNT_CUR)
-#define PVP0_MPDI_DMA_BWMCNT                 (REG_DMA43_BWMCNT)
-#define PVP0_MPDI_DMA_BWMCNT_CUR             (REG_DMA43_BWMCNT_CUR)
-#define PVP0_MPSTAT_DMA_DSCPTR_NXT           (REG_DMA44_DSCPTR_NXT)
-#define PVP0_MPSTAT_DMA_ADDRSTART            (REG_DMA44_ADDRSTART)
-#define PVP0_MPSTAT_DMA_CFG                  (REG_DMA44_CFG)
-#define PVP0_MPSTAT_DMA_XCNT                 (REG_DMA44_XCNT)
-#define PVP0_MPSTAT_DMA_XMOD                 (REG_DMA44_XMOD)
-#define PVP0_MPSTAT_DMA_YCNT                 (REG_DMA44_YCNT)
-#define PVP0_MPSTAT_DMA_YMOD                 (REG_DMA44_YMOD)
-#define PVP0_MPSTAT_DMA_DSCPTR_CUR           (REG_DMA44_DSCPTR_CUR)
-#define PVP0_MPSTAT_DMA_DSCPTR_PRV           (REG_DMA44_DSCPTR_PRV)
-#define PVP0_MPSTAT_DMA_ADDR_CUR             (REG_DMA44_ADDR_CUR)
-#define PVP0_MPSTAT_DMA_STAT                 (REG_DMA44_STAT)
-#define PVP0_MPSTAT_DMA_XCNT_CUR             (REG_DMA44_XCNT_CUR)
-#define PVP0_MPSTAT_DMA_YCNT_CUR             (REG_DMA44_YCNT_CUR)
-#define PVP0_MPSTAT_DMA_BWLCNT               (REG_DMA44_BWLCNT)
-#define PVP0_MPSTAT_DMA_BWLCNT_CUR           (REG_DMA44_BWLCNT_CUR)
-#define PVP0_MPSTAT_DMA_BWMCNT               (REG_DMA44_BWMCNT)
-#define PVP0_MPSTAT_DMA_BWMCNT_CUR           (REG_DMA44_BWMCNT_CUR)
-#define PVP0_MPCI_DMA_DSCPTR_NXT             (REG_DMA45_DSCPTR_NXT)
-#define PVP0_MPCI_DMA_ADDRSTART              (REG_DMA45_ADDRSTART)
-#define PVP0_MPCI_DMA_CFG                    (REG_DMA45_CFG)
-#define PVP0_MPCI_DMA_XCNT                   (REG_DMA45_XCNT)
-#define PVP0_MPCI_DMA_XMOD                   (REG_DMA45_XMOD)
-#define PVP0_MPCI_DMA_YCNT                   (REG_DMA45_YCNT)
-#define PVP0_MPCI_DMA_YMOD                   (REG_DMA45_YMOD)
-#define PVP0_MPCI_DMA_DSCPTR_CUR             (REG_DMA45_DSCPTR_CUR)
-#define PVP0_MPCI_DMA_DSCPTR_PRV             (REG_DMA45_DSCPTR_PRV)
-#define PVP0_MPCI_DMA_ADDR_CUR               (REG_DMA45_ADDR_CUR)
-#define PVP0_MPCI_DMA_STAT                   (REG_DMA45_STAT)
-#define PVP0_MPCI_DMA_XCNT_CUR               (REG_DMA45_XCNT_CUR)
-#define PVP0_MPCI_DMA_YCNT_CUR               (REG_DMA45_YCNT_CUR)
-#define PVP0_MPCI_DMA_BWLCNT                 (REG_DMA45_BWLCNT)
-#define PVP0_MPCI_DMA_BWLCNT_CUR             (REG_DMA45_BWLCNT_CUR)
-#define PVP0_MPCI_DMA_BWMCNT                 (REG_DMA45_BWMCNT)
-#define PVP0_MPCI_DMA_BWMCNT_CUR             (REG_DMA45_BWMCNT_CUR)
-#define PVP0_CPDOA_DMA_DSCPTR_NXT            (REG_DMA46_DSCPTR_NXT)
-#define PVP0_CPDOA_DMA_ADDRSTART             (REG_DMA46_ADDRSTART)
-#define PVP0_CPDOA_DMA_CFG                   (REG_DMA46_CFG)
-#define PVP0_CPDOA_DMA_XCNT                  (REG_DMA46_XCNT)
-#define PVP0_CPDOA_DMA_XMOD                  (REG_DMA46_XMOD)
-#define PVP0_CPDOA_DMA_YCNT                  (REG_DMA46_YCNT)
-#define PVP0_CPDOA_DMA_YMOD                  (REG_DMA46_YMOD)
-#define PVP0_CPDOA_DMA_DSCPTR_CUR            (REG_DMA46_DSCPTR_CUR)
-#define PVP0_CPDOA_DMA_DSCPTR_PRV            (REG_DMA46_DSCPTR_PRV)
-#define PVP0_CPDOA_DMA_ADDR_CUR              (REG_DMA46_ADDR_CUR)
-#define PVP0_CPDOA_DMA_STAT                  (REG_DMA46_STAT)
-#define PVP0_CPDOA_DMA_XCNT_CUR              (REG_DMA46_XCNT_CUR)
-#define PVP0_CPDOA_DMA_YCNT_CUR              (REG_DMA46_YCNT_CUR)
-#define PVP0_CPDOA_DMA_BWLCNT                (REG_DMA46_BWLCNT)
-#define PVP0_CPDOA_DMA_BWLCNT_CUR            (REG_DMA46_BWLCNT_CUR)
-#define PVP0_CPDOA_DMA_BWMCNT                (REG_DMA46_BWMCNT)
-#define PVP0_CPDOA_DMA_BWMCNT_CUR            (REG_DMA46_BWMCNT_CUR)
-
-/* ==================================
-       DMA Error CHID Definitions
-   ================================== */
-#define CHID_SPORT0_A_DMA                      0           /* Channel A DMA */
-#define CHID_SPORT0_B_DMA                      1           /* Channel B DMA */
-#define CHID_SPORT1_A_DMA                      2           /* Channel A DMA */
-#define CHID_SPORT1_B_DMA                      3           /* Channel B DMA */
-#define CHID_SPORT2_A_DMA                      4           /* Channel A DMA */
-#define CHID_SPORT2_B_DMA                      5           /* Channel B DMA */
-#define CHID_SPI0_TXDMA                        6           /* TX DMA Channel */
-#define CHID_SPI0_RXDMA                        7           /* RX DMA Channel */
-#define CHID_SPI1_TXDMA                        8           /* TX DMA Channel */
-#define CHID_SPI1_RXDMA                        9           /* RX DMA Channel */
-#define CHID_RSI0_DMA                         10           /* DMA Channel */
-#define CHID_SDU0_DMA                         11           /* DMA */
-/*      -- RESERVED --                        12  */
-#define CHID_LP0_DMA                          13           /* DMA Channel */
-#define CHID_LP1_DMA                          14           /* DMA Channel */
-#define CHID_LP2_DMA                          15           /* DMA Channel */
-#define CHID_LP3_DMA                          16           /* DMA Channel */
-#define CHID_UART0_TXDMA                      17           /* Transmit DMA */
-#define CHID_UART0_RXDMA                      18           /* Receive DMA */
-#define CHID_UART1_TXDMA                      19           /* Transmit DMA */
-#define CHID_UART1_RXDMA                      20           /* Receive DMA */
-#define CHID_MDMA0_SRC                        21           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define CHID_MDMA0_DST                        22           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define CHID_MDMA1_SRC                        23           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define CHID_MDMA1_DST                        24           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define CHID_MDMA2_SRC                        25           /* Memory DMA Stream 2 Source Channel */
-#define CHID_MDMA2_DST                        26           /* Memory DMA Stream 2 Destination Channel */
-#define CHID_MDMA3_SRC                        27           /* Memory DMA Stream 3 Source Channel */
-#define CHID_MDMA3_DST                        28           /* Memory DMA Stream 3 Destination Channel */
-#define CHID_EPPI0_CH0_DMA                    29           /* Channel 0 DMA */
-#define CHID_EPPI0_CH1_DMA                    30           /* Channel 1 DMA */
-#define CHID_EPPI2_CH0_DMA                    31           /* Channel 0 DMA */
-#define CHID_EPPI2_CH1_DMA                    32           /* Channel 1 DMA */
-#define CHID_EPPI1_CH0_DMA                    33           /* Channel 0 DMA */
-#define CHID_EPPI1_CH1_DMA                    34           /* Channel 1 DMA */
-#define CHID_PIXC0_CH0_DMA                    35           /* Channel 0 DMA */
-#define CHID_PIXC0_CH1_DMA                    36           /* Channel 1 DMA */
-#define CHID_PIXC0_CH2_DMA                    37           /* Channel 2 DMA */
-#define CHID_PVP0_CPDOB_DMA                   38           /* Camera Pipe Data Out B DMA Channel */
-#define CHID_PVP0_CPDOC_DMA                   39           /* Camera Pipe Data Out C DMA Channel */
-#define CHID_PVP0_CPSTAT_DMA                  40           /* Camera Pipe Status Out DMA Channel */
-#define CHID_PVP0_CPCI_DMA                    41           /* Camera Pipe Control In DMA Channel */
-#define CHID_PVP0_MPDO_DMA                    42           /* Memory Pipe Data Out DMA Channel */
-#define CHID_PVP0_MPDI_DMA                    43           /* Memory Pipe Data In DMA Channel */
-#define CHID_PVP0_MPSTAT_DMA                  44           /* Memory Pipe Status Out DMA Channel */
-#define CHID_PVP0_MPCI_DMA                    45           /* Memory Pipe Control In DMA Channel */
-#define CHID_PVP0_CPDOA_DMA                   46           /* Camera Pipe Data Out A DMA Channel */
-
-/* ==============================
-       Interrupt Definitions
-   ============================== */
-#define INTR_SEC0_ERR                          0           /* Error */
-#define INTR_CGU0_EVT                          1           /* Event */
-#define INTR_WDOG0_EXP                         2           /* Expiration */
-#define INTR_WDOG1_EXP                         3           /* Expiration */
-#define INTR_L2CTL0_ECC_ERR                    4           /* ECC Error */
-#define INTR_L2CTL0_ECC_WARNING                5           /* ECC Warning */
-#define INTR_C0_DBL_FAULT                      6           /* Core 0 Double Fault */
-#define INTR_C1_DBL_FAULT                      7           /* Core 1 Double Fault */
-#define INTR_C0_HW_ERR                         8           /* Core 0 Hardware Error */
-#define INTR_C1_HW_ERR                         9           /* Core 1 Hardware Error */
-#define INTR_C0_NMI_L1_PARITY_ERR             10           /* Core 0 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_C1_NMI_L1_PARITY_ERR             11           /* Core 1 Unhandled NMI or L1 Memory Parity Error */
-#define INTR_TIMER0_TMR0                      12           /* Timer 0 */
-#define INTR_TIMER0_TMR1                      13           /* Timer 1 */
-#define INTR_TIMER0_TMR2                      14           /* Timer 2 */
-#define INTR_TIMER0_TMR3                      15           /* Timer 3 */
-#define INTR_TIMER0_TMR4                      16           /* Timer 4 */
-#define INTR_TIMER0_TMR5                      17           /* Timer 5 */
-#define INTR_TIMER0_TMR6                      18           /* Timer 6 */
-#define INTR_TIMER0_TMR7                      19           /* Timer 7 */
-#define INTR_TIMER0_STAT                      20           /* Status */
-#define INTR_PINT0_BLOCK                      21           /* Pin Interrupt Block */
-#define INTR_PINT1_BLOCK                      22           /* Pin Interrupt Block */
-#define INTR_PINT2_BLOCK                      23           /* Pin Interrupt Block */
-#define INTR_PINT3_BLOCK                      24           /* Pin Interrupt Block */
-#define INTR_PINT4_BLOCK                      25           /* Pin Interrupt Block */
-#define INTR_PINT5_BLOCK                      26           /* Pin Interrupt Block */
-#define INTR_CNT0_STAT                        27           /* Status */
-#define INTR_PWM0_SYNC                        28           /* PWMTMR Group */
-#define INTR_PWM0_TRIP                        29           /* Trip */
-#define INTR_PWM1_SYNC                        30           /* PWMTMR Group */
-#define INTR_PWM1_TRIP                        31           /* Trip */
-#define INTR_TWI0_DATA                        32           /* Data Interrupt */
-#define INTR_TWI1_DATA                        33           /* Data Interrupt */
-#define INTR_SOFT0                            34           /* Software-driven Interrupt 0 */
-#define INTR_SOFT1                            35           /* Software-driven Interrupt 1 */
-#define INTR_SOFT2                            36           /* Software-driven Interrupt 2 */
-#define INTR_SOFT3                            37           /* Software-driven Interrupt 3 */
-#define INTR_ACM0_EVT_MISS                    38           /* Event Miss */
-#define INTR_ACM0_EVT_COMPLETE                39           /* Event Complete */
-#define INTR_CAN0_RX                          40           /* Receive */
-#define INTR_CAN0_TX                          41           /* Transmit */
-#define INTR_CAN0_STAT                        42           /* Status */
-#define INTR_SPORT0_A_DMA                     43           /* Channel A DMA */
-#define INTR_SPORT0_A_STAT                    44           /* Channel A Status */
-#define INTR_SPORT0_B_DMA                     45           /* Channel B DMA */
-#define INTR_SPORT0_B_STAT                    46           /* Channel B Status */
-#define INTR_SPORT1_A_DMA                     47           /* Channel A DMA */
-#define INTR_SPORT1_A_STAT                    48           /* Channel A Status */
-#define INTR_SPORT1_B_DMA                     49           /* Channel B DMA */
-#define INTR_SPORT1_B_STAT                    50           /* Channel B Status */
-#define INTR_SPORT2_A_DMA                     51           /* Channel A DMA */
-#define INTR_SPORT2_A_STAT                    52           /* Channel A Status */
-#define INTR_SPORT2_B_DMA                     53           /* Channel B DMA */
-#define INTR_SPORT2_B_STAT                    54           /* Channel B Status */
-#define INTR_SPI0_TXDMA                       55           /* TX DMA Channel */
-#define INTR_SPI0_RXDMA                       56           /* RX DMA Channel */
-#define INTR_SPI0_STAT                        57           /* Status */
-#define INTR_SPI1_TXDMA                       58           /* TX DMA Channel */
-#define INTR_SPI1_RXDMA                       59           /* RX DMA Channel */
-#define INTR_SPI1_STAT                        60           /* Status */
-#define INTR_RSI0_DMA                         61           /* DMA Channel */
-#define INTR_RSI0_INT0                        62           /* Interrupt 0 */
-#define INTR_RSI0_INT1                        63           /* Interrupt 1 */
-#define INTR_SDU0_DMA                         64           /* DMA */
-/*      -- RESERVED --                        65  */
-/*      -- RESERVED --                        66  */
-/*      -- RESERVED --                        67  */
-#define INTR_EMAC0_STAT                       68           /* Status */
-/*      -- RESERVED --                        69  */
-#define INTR_EMAC1_STAT                       70           /* Status */
-/*      -- RESERVED --                        71  */
-#define INTR_LP0_DMA                          72           /* DMA Channel */
-#define INTR_LP0_STAT                         73           /* Status */
-#define INTR_LP1_DMA                          74           /* DMA Channel */
-#define INTR_LP1_STAT                         75           /* Status */
-#define INTR_LP2_DMA                          76           /* DMA Channel */
-#define INTR_LP2_STAT                         77           /* Status */
-#define INTR_LP3_DMA                          78           /* DMA Channel */
-#define INTR_LP3_STAT                         79           /* Status */
-#define INTR_UART0_TXDMA                      80           /* Transmit DMA */
-#define INTR_UART0_RXDMA                      81           /* Receive DMA */
-#define INTR_UART0_STAT                       82           /* Status */
-#define INTR_UART1_TXDMA                      83           /* Transmit DMA */
-#define INTR_UART1_RXDMA                      84           /* Receive DMA */
-#define INTR_UART1_STAT                       85           /* Status */
-#define INTR_MDMA0_SRC                        86           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define INTR_MDMA0_DST                        87           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define INTR_CRC0_DCNTEXP                     88           /* Datacount expiration */
-#define INTR_CRC0_ERR                         89           /* Error */
-#define INTR_MDMA1_SRC                        90           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define INTR_MDMA1_DST                        91           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define INTR_CRC1_DCNTEXP                     92           /* Datacount expiration */
-#define INTR_CRC1_ERR                         93           /* Error */
-#define INTR_MDMA2_SRC                        94           /* Memory DMA Stream 2 Source Channel */
-#define INTR_MDMA2_DST                        95           /* Memory DMA Stream 2 Destination Channel */
-#define INTR_MDMA3_SRC                        96           /* Memory DMA Stream 3 Source Channel */
-#define INTR_MDMA3_DST                        97           /* Memory DMA Stream 3 Destination Channel */
-#define INTR_EPPI0_CH0_DMA                    98           /* Channel 0 DMA */
-#define INTR_EPPI0_CH1_DMA                    99           /* Channel 1 DMA */
-#define INTR_EPPI0_STAT                      100           /* Status */
-#define INTR_EPPI2_CH0_DMA                   101           /* Channel 0 DMA */
-#define INTR_EPPI2_CH1_DMA                   102           /* Channel 1 DMA */
-#define INTR_EPPI2_STAT                      103           /* Status */
-#define INTR_EPPI1_CH0_DMA                   104           /* Channel 0 DMA */
-#define INTR_EPPI1_CH1_DMA                   105           /* Channel 1 DMA */
-#define INTR_EPPI1_STAT                      106           /* Status */
-#define INTR_PIXC0_CH0_DMA                   107           /* Channel 0 DMA */
-#define INTR_PIXC0_CH1_DMA                   108           /* Channel 1 DMA */
-#define INTR_PIXC0_CH2_DMA                   109           /* Channel 2 DMA */
-#define INTR_PIXC0_STAT                      110           /* Status */
-#define INTR_PVP0_CPDOB_DMA                  111           /* Camera Pipe Data Out B DMA Channel */
-#define INTR_PVP0_CPDOC_DMA                  112           /* Camera Pipe Data Out C DMA Channel */
-#define INTR_PVP0_CPSTAT_DMA                 113           /* Camera Pipe Status Out DMA Channel */
-#define INTR_PVP0_CPCI_DMA                   114           /* Camera Pipe Control In DMA Channel */
-#define INTR_PVP0_STAT0                      115           /* Status 0 */
-#define INTR_PVP0_MPDO_DMA                   116           /* Memory Pipe Data Out DMA Channel */
-#define INTR_PVP0_MPDI_DMA                   117           /* Memory Pipe Data In DMA Channel */
-#define INTR_PVP0_MPSTAT_DMA                 118           /* Memory Pipe Status Out DMA Channel */
-#define INTR_PVP0_MPCI_DMA                   119           /* Memory Pipe Control In DMA Channel */
-#define INTR_PVP0_CPDOA_DMA                  120           /* Camera Pipe Data Out A DMA Channel */
-#define INTR_PVP0_STAT1                      121           /* Status 1 */
-#define INTR_USB0_STAT                       122           /* Status/FIFO Data Ready */
-#define INTR_USB0_DATA                       123           /* DMA Status/Transfer Complete */
-#define INTR_TRU0_INT0                       124           /* Interrupt 0 */
-#define INTR_TRU0_INT1                       125           /* Interrupt 1 */
-#define INTR_TRU0_INT2                       126           /* Interrupt 2 */
-#define INTR_TRU0_INT3                       127           /* Interrupt 3 */
-#define INTR_DMAC_ERR                        128           /* DMA Controller Error */
-#define INTR_CGU0_ERR                        129           /* Error */
-/*      -- RESERVED --                       130  */
-#define INTR_DPM0_EVT                        131           /* Event */
-/*      -- RESERVED --                       132  */
-#define INTR_SWU0_EVT                        133           /* Event */
-#define INTR_SWU1_EVT                        134           /* Event */
-#define INTR_SWU2_EVT                        135           /* Event */
-#define INTR_SWU3_EVT                        136           /* Event */
-#define INTR_SWU4_EVT                        137           /* Event */
-#define INTR_SWU5_EVT                        138           /* Event */
-#define INTR_SWU6_EVT                        139           /* Event */
-
-/* ==============================
-       Parameters
-   ============================== */
-
-
-/* Generic System Module Parameters */
-
-#define PARAM_SYS0_NUM_BMODE                          3
-#define PARAM_SYS0_NUM_CORES                          2
-#define PARAM_SYS0_NUM_MDMA_STREAMS                   4
-#define PARAM_SYS0_NUM_RSVD_INT                       7
-#define PARAM_SYS0_NUM_RSVD_TRIG                      6
-#define PARAM_SYS0_NUM_SW_INT                         4
-#define PARAM_SYS0_NUM_SW_TRIG                        6
-
-
-
-
-/* RSI Parameters */
-
-#define PARAM_RSI0_NUM_DATA                           8
-#define PARAM_RSI0_NUM_INT                            2
-
-
-
-/* Link Port Parameters */
-
-#define PARAM_LP0_NUM_DATA                            8
-#define PARAM_LP1_NUM_DATA                            8
-#define PARAM_LP2_NUM_DATA                            8
-#define PARAM_LP3_NUM_DATA                            8
-
-
-/* General Purpose Timer Block Parameters */
-
-#define PARAM_TIMER0_NUMTIMERS                        8
-
-
-
-
-
-/* General Purpose Input/Output Parameters */
-
-#define PARAM_PORTA_PORT_WIDTH                       16
-#define PARAM_PORTB_PORT_WIDTH                       16
-#define PARAM_PORTC_PORT_WIDTH                       16
-#define PARAM_PORTD_PORT_WIDTH                       16
-#define PARAM_PORTE_PORT_WIDTH                       16
-#define PARAM_PORTF_PORT_WIDTH                       16
-#define PARAM_PORTG_PORT_WIDTH                       16
-
-
-
-
-/* Static Memory Controller Parameters */
-
-#define PARAM_SMC0_NUM_ABE                            2
-#define PARAM_SMC0_NUM_ADDR                          26
-#define PARAM_SMC0_NUM_AMS                            4
-#define PARAM_SMC0_NUM_DATA                          16
-
-
-
-/* EPPI Parameters */
-
-#define PARAM_EPPI0_MAXWIDTH                         24
-#define PARAM_EPPI0_NUM_DATA                         24
-#define PARAM_EPPI1_MAXWIDTH                         24
-#define PARAM_EPPI1_NUM_DATA                         18
-#define PARAM_EPPI2_MAXWIDTH                         24
-#define PARAM_EPPI2_NUM_DATA                         18
-
-
-
-
-/* Pulse-Width Modulator Parameters */
-
-#define PARAM_PWM0_ASYM_DEADTIME                      0
-#define PARAM_PWM0_COMPRESS                           1
-#define PARAM_PWM0_DOUBLE_UPDATE                      0
-#define PARAM_PWM0_FULL_DUTY_REGS                     0
-#define PARAM_PWM0_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM0_LO_HP_REGS                         0
-#define PARAM_PWM0_NUM_TRIP                           2
-#define PARAM_PWM0_NUM_TRIP_PINS                      2
-#define PARAM_PWM0_NUM_TRIP_TRIG                      0
-#define PARAM_PWM0_REVID_MAJOR                        0
-#define PARAM_PWM0_REVID_REV                          0
-#define PARAM_PWM1_ASYM_DEADTIME                      0
-#define PARAM_PWM1_COMPRESS                           1
-#define PARAM_PWM1_DOUBLE_UPDATE                      0
-#define PARAM_PWM1_FULL_DUTY_REGS                     0
-#define PARAM_PWM1_HI_HP_REGS_PRIVATE                 1
-#define PARAM_PWM1_LO_HP_REGS                         0
-#define PARAM_PWM1_NUM_TRIP                           2
-#define PARAM_PWM1_NUM_TRIP_PINS                      2
-#define PARAM_PWM1_NUM_TRIP_TRIG                      0
-#define PARAM_PWM1_REVID_MAJOR                        0
-#define PARAM_PWM1_REVID_REV                          0
-
-
-/* Video Subsystem Registers Parameters */
-
-#define PARAM_VID0_PIXC_ABSENT                        0
-#define PARAM_VID0_PVP_ABSENT                         0
-
-
-
-/* System Debug Unit Parameters */
-
-#define PARAM_SDU0_IDCODE_PRID                        0
-#define PARAM_SDU0_IDCODE_REVID                       0
-
-
-/* Ethernet MAC Parameters */
-
-#define PARAM_EMAC0_NUM_RX                            2
-#define PARAM_EMAC0_NUM_TX                            2
-#define PARAM_EMAC1_NUM_RX                            2
-#define PARAM_EMAC1_NUM_TX                            2
-
-
-
-/* Serial Peripheral Interface Parameters */
-
-#define PARAM_SPI0_MEM_MAPPED                         0
-#define PARAM_SPI0_NUM_SEL                            7
-#define PARAM_SPI0_PTM_EXISTS                         1
-#define PARAM_SPI0_REVID_MAJOR                        3
-#define PARAM_SPI0_REVID_REV                          0
-#define PARAM_SPI1_MEM_MAPPED                         0
-#define PARAM_SPI1_NUM_SEL                            7
-#define PARAM_SPI1_PTM_EXISTS                         1
-#define PARAM_SPI1_REVID_MAJOR                        3
-#define PARAM_SPI1_REVID_REV                          0
-
-
-
-/* ACM Parameters */
-
-#define PARAM_ACM0_NUM_ADDR                           5
-#define PARAM_ACM0_NUM_TRIG                           2
-
-
-/* DDR Parameters */
-
-#define PARAM_DMC0_NUM_ADDR                          14
-#define PARAM_DMC0_NUM_BA                             3
-#define PARAM_DMC0_NUM_CS                             1
-#define PARAM_DMC0_NUM_DATA                          16
-
-
-/* System Cross Bar Parameters */
-
-#define PARAM_SCB0_NUM_MASTERS                        6
-#define PARAM_SCB0_NUM_SLOTS                         32
-#define PARAM_SCB1_NUM_MASTERS                        1
-#define PARAM_SCB1_NUM_SLOTS                         32
-#define PARAM_SCB2_NUM_MASTERS                        1
-#define PARAM_SCB2_NUM_SLOTS                         32
-#define PARAM_SCB3_NUM_MASTERS                        1
-#define PARAM_SCB3_NUM_SLOTS                         32
-#define PARAM_SCB4_NUM_MASTERS                        1
-#define PARAM_SCB4_NUM_SLOTS                         32
-#define PARAM_SCB5_NUM_MASTERS                        1
-#define PARAM_SCB5_NUM_SLOTS                         32
-#define PARAM_SCB6_NUM_MASTERS                        1
-#define PARAM_SCB6_NUM_SLOTS                         32
-#define PARAM_SCB7_NUM_MASTERS                        1
-#define PARAM_SCB7_NUM_SLOTS                         32
-#define PARAM_SCB8_NUM_MASTERS                        1
-#define PARAM_SCB8_NUM_SLOTS                         32
-#define PARAM_SCB9_NUM_MASTERS                        1
-#define PARAM_SCB9_NUM_SLOTS                         32
-#define PARAM_SCB10_NUM_MASTERS                       3
-#define PARAM_SCB10_NUM_SLOTS                        32
-#define PARAM_SCB11_NUM_MASTERS                       7
-#define PARAM_SCB11_NUM_SLOTS                        32
-
-
-
-/* System Event Controller Parameters */
-
-#define PARAM_SEC0_CCOUNT                             2
-#define PARAM_SEC0_SCOUNT                           140
-
-
-/* Trigger Routing Unit Parameters */
-
-#define PARAM_TRU0_NUM_INTS                           4
-#define PARAM_TRU0_NUM_TRIGS                          4
-#define PARAM_TRU0_SSRCOUNT                          87
-
-
-/* Reset Control Unit Parameters */
-
-#define PARAM_RCU0_CCOUNT                             2
-#define PARAM_RCU0_CRCTL_CR_INIT                      2
-#define PARAM_RCU0_CRSTAT_CR_INIT                     3
-#define PARAM_RCU0_SICOUNT                            2
-#define PARAM_RCU0_SVECT_INIT                     65440
-
-
-/* System Protection Unit Parameters */
-
-#define PARAM_SPU0_CM_COUNT                           2
-#define PARAM_SPU0_END_POINT_COUNT                   86
-#define PARAM_SPU0_SM_COUNT                           2
-
-
-/* Clock Generation Unit Parameters */
-
-#define PARAM_CGU0_CSEL_DEFAULT                       4
-#define PARAM_CGU0_DSEL_DEFAULT                       8
-#define PARAM_CGU0_MSEL_DEFAULT                      16
-#define PARAM_CGU0_OSEL_DEFAULT                      16
-#define PARAM_CGU0_PLLBP_DEFAULT                      0
-#define PARAM_CGU0_S0SEL_DEFAULT                      2
-#define PARAM_CGU0_S1SEL_DEFAULT                      2
-#define PARAM_CGU0_SYSSEL_DEFAULT                     8
-
-
-/* Dynamic Power Management Parameters */
-
-#define PARAM_DPM0_NUM_CCLK                           2
-#define PARAM_DPM0_NUM_HV                             8
-#define PARAM_DPM0_NUM_SCLK                           4
-#define PARAM_DPM0_NUM_WAKE                           8
-
-
-
-/* Universal Serial Bus Controller Parameters */
-
-#define PARAM_USB0_DMA_CHAN                           8
-#define PARAM_USB0_DYN_FIFO_SIZE                      1
-#define PARAM_USB0_FS_PHY                             0
-#define PARAM_USB0_HS_PHY                             1
-#define PARAM_USB0_LOOPBACK                           1
-#define PARAM_USB0_NUM_ENDPTS                        12
-#define PARAM_USB0_NUM_ENDPTS_MINUS_1                11
-
-
-/* Data Memory Unit Parameters */
-
-#define PARAM_L1DM0_L1_BASE_ADDRESS          1111111110
-
-
-
-
-
-
-
-
-/* ===================================
-       Trigger Master Definitions
-   =================================== */
-/*      -- RESERVED --                         0  */
-#define TRGM_CGU0_EVT                          1           /* Event */
-#define TRGM_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGM_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGM_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGM_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGM_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGM_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGM_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGM_TIMER0_TMR7                       9           /* Timer 7 */
-#define TRGM_PINT0_BLOCK                      10           /* Pin Interrupt Block */
-#define TRGM_PINT1_BLOCK                      11           /* Pin Interrupt Block */
-#define TRGM_PINT2_BLOCK                      12           /* Pin Interrupt Block */
-#define TRGM_PINT3_BLOCK                      13           /* Pin Interrupt Block */
-#define TRGM_PINT4_BLOCK                      14           /* Pin Interrupt Block */
-#define TRGM_PINT5_BLOCK                      15           /* Pin Interrupt Block */
-#define TRGM_CNT0_STAT                        16           /* Status */
-#define TRGM_PWM0_SYNC                        17           /* PWMTMR Group */
-#define TRGM_PWM1_SYNC                        18           /* PWMTMR Group */
-#define TRGM_ACM0_EVT_COMPLETE                19           /* Event Complete */
-#define TRGM_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGM_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGM_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGM_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGM_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGM_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGM_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGM_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGM_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGM_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGM_RSI0_DMA                         30           /* DMA Channel */
-#define TRGM_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGM_EMAC0_STAT                       33           /* Status */
-#define TRGM_EMAC1_STAT                       34           /* Status */
-#define TRGM_LP0_DMA                          35           /* DMA Channel */
-#define TRGM_LP1_DMA                          36           /* DMA Channel */
-#define TRGM_LP2_DMA                          37           /* DMA Channel */
-#define TRGM_LP3_DMA                          38           /* DMA Channel */
-#define TRGM_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGM_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGM_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGM_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGM_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGM_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGM_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGM_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGM_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGM_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGM_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGM_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGM_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGM_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGM_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGM_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGM_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGM_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGM_PIXC0_CH0_DMA                    57           /* Channel 0 DMA */
-#define TRGM_PIXC0_CH1_DMA                    58           /* Channel 1 DMA */
-#define TRGM_PIXC0_CH2_DMA                    59           /* Channel 2 DMA */
-#define TRGM_PVP0_CPDOB_DMA                   60           /* Camera Pipe Data Out B DMA Channel */
-#define TRGM_PVP0_CPDOC_DMA                   61           /* Camera Pipe Data Out C DMA Channel */
-#define TRGM_PVP0_CPSTAT_DMA                  62           /* Camera Pipe Status Out DMA Channel */
-#define TRGM_PVP0_CPCI_DMA                    63           /* Camera Pipe Control In DMA Channel */
-#define TRGM_PVP0_MPDO_DMA                    64           /* Memory Pipe Data Out DMA Channel */
-#define TRGM_PVP0_MPDI_DMA                    65           /* Memory Pipe Data In DMA Channel */
-#define TRGM_PVP0_MPSTAT_DMA                  66           /* Memory Pipe Status Out DMA Channel */
-#define TRGM_PVP0_MPCI_DMA                    67           /* Memory Pipe Control In DMA Channel */
-#define TRGM_PVP0_CPDOA_DMA                   68           /* Camera Pipe Data Out A DMA Channel */
-#define TRGM_USB0_DATA                        69           /* DMA Status/Transfer Complete */
-/*      -- RESERVED --                        70  */
-#define TRGM_SEC0_FAULT                       71           /* Fault */
-#define TRGM_SOFT0                            72           /* Software-driven Trigger 0 */
-#define TRGM_SOFT1                            73           /* Software-driven Trigger 1 */
-#define TRGM_SOFT2                            74           /* Software-driven Trigger 2 */
-#define TRGM_SOFT3                            75           /* Software-driven Trigger 3 */
-#define TRGM_SOFT4                            76           /* Software-driven Trigger 4 */
-#define TRGM_SOFT5                            77           /* Software-driven Trigger 5 */
-#define TRGM_PVP0_STAT0                       78           /* Status 0 */
-#define TRGM_PVP0_STAT1                       79           /* Status 1 */
-#define TRGM_SWU0_EVT                         80           /* Event */
-#define TRGM_SWU1_EVT                         81           /* Event */
-#define TRGM_SWU2_EVT                         82           /* Event */
-#define TRGM_SWU3_EVT                         83           /* Event */
-#define TRGM_SWU4_EVT                         84           /* Event */
-#define TRGM_SWU5_EVT                         85           /* Event */
-#define TRGM_SWU6_EVT                         86           /* Event */
-
-/* ===================================
-       Trigger Slave Definitions
-   =================================== */
-#define TRGS_RCU0_SYSRST0                      0           /* System Reset 0 */
-#define TRGS_RCU0_SYSRST1                      1           /* System Reset 1 */
-#define TRGS_TIMER0_TMR0                       2           /* Timer 0 */
-#define TRGS_TIMER0_TMR1                       3           /* Timer 1 */
-#define TRGS_TIMER0_TMR2                       4           /* Timer 2 */
-#define TRGS_TIMER0_TMR3                       5           /* Timer 3 */
-#define TRGS_TIMER0_TMR4                       6           /* Timer 4 */
-#define TRGS_TIMER0_TMR5                       7           /* Timer 5 */
-#define TRGS_TIMER0_TMR6                       8           /* Timer 6 */
-#define TRGS_TIMER0_TMR7                       9           /* Timer 7 */
-/*      -- RESERVED --                        10  */
-/*      -- RESERVED --                        11  */
-#define TRGS_C0_NMI_S0                        12           /* NMI (Core 0) Slave 0 */
-#define TRGS_C0_NMI_S1                        13           /* NMI (Core 0) Slave 1 */
-#define TRGS_C1_NMI_S0                        14           /* NMI (Core 1) Slave 0 */
-#define TRGS_C1_NMI_S1                        15           /* NMI (Core 1) Slave 1 */
-#define TRGS_TRU0_IRQ0                        16           /* Interrupt Request 0 */
-#define TRGS_TRU0_IRQ1                        17           /* Interrupt Request 1 */
-#define TRGS_TRU0_IRQ2                        18           /* Interrupt Request 2 */
-#define TRGS_TRU0_IRQ3                        19           /* Interrupt Request 3 */
-#define TRGS_SPORT0_A_DMA                     20           /* Channel A DMA */
-#define TRGS_SPORT0_B_DMA                     21           /* Channel B DMA */
-#define TRGS_SPORT1_A_DMA                     22           /* Channel A DMA */
-#define TRGS_SPORT1_B_DMA                     23           /* Channel B DMA */
-#define TRGS_SPORT2_A_DMA                     24           /* Channel A DMA */
-#define TRGS_SPORT2_B_DMA                     25           /* Channel B DMA */
-#define TRGS_SPI0_TXDMA                       26           /* TX DMA Channel */
-#define TRGS_SPI0_RXDMA                       27           /* RX DMA Channel */
-#define TRGS_SPI1_TXDMA                       28           /* TX DMA Channel */
-#define TRGS_SPI1_RXDMA                       29           /* RX DMA Channel */
-#define TRGS_RSI0_DMA                         30           /* DMA Channel */
-#define TRGS_SDU0_DMA                         31           /* DMA */
-/*      -- RESERVED --                        32  */
-#define TRGS_ACM0_TRIG2                       33           /* Trigger Input 2 */
-#define TRGS_ACM0_TRIG3                       34           /* Trigger Input 3 */
-#define TRGS_LP0_DMA                          35           /* DMA Channel */
-#define TRGS_LP1_DMA                          36           /* DMA Channel */
-#define TRGS_LP2_DMA                          37           /* DMA Channel */
-#define TRGS_LP3_DMA                          38           /* DMA Channel */
-#define TRGS_UART0_TXDMA                      39           /* Transmit DMA */
-#define TRGS_UART0_RXDMA                      40           /* Receive DMA */
-#define TRGS_UART1_TXDMA                      41           /* Transmit DMA */
-#define TRGS_UART1_RXDMA                      42           /* Receive DMA */
-#define TRGS_MDMA0_SRC                        43           /* Memory DMA Stream 0 Source / CRC0 Input Channel */
-#define TRGS_MDMA0_DST                        44           /* Memory DMA Stream 0 Destination / CRC0 Output Channel */
-#define TRGS_MDMA1_SRC                        45           /* Memory DMA Stream 1 Source / CRC1 Input Channel */
-#define TRGS_MDMA1_DST                        46           /* Memory DMA Stream 1 Destination / CRC1 Output Channel */
-#define TRGS_MDMA2_SRC                        47           /* Memory DMA Stream 2 Source Channel */
-#define TRGS_MDMA2_DST                        48           /* Memory DMA Stream 2 Destination Channel */
-#define TRGS_MDMA3_SRC                        49           /* Memory DMA Stream 3 Source Channel */
-#define TRGS_MDMA3_DST                        50           /* Memory DMA Stream 3 Destination Channel */
-#define TRGS_EPPI0_CH0_DMA                    51           /* Channel 0 DMA */
-#define TRGS_EPPI0_CH1_DMA                    52           /* Channel 1 DMA */
-#define TRGS_EPPI2_CH0_DMA                    53           /* Channel 0 DMA */
-#define TRGS_EPPI2_CH1_DMA                    54           /* Channel 1 DMA */
-#define TRGS_EPPI1_CH0_DMA                    55           /* Channel 0 DMA */
-#define TRGS_EPPI1_CH1_DMA                    56           /* Channel 1 DMA */
-#define TRGS_PIXC0_CH0_DMA                    57           /* Channel 0 DMA */
-#define TRGS_PIXC0_CH1_DMA                    58           /* Channel 1 DMA */
-#define TRGS_PIXC0_CH2_DMA                    59           /* Channel 2 DMA */
-#define TRGS_PVP0_CPDOB_DMA                   60           /* Camera Pipe Data Out B DMA Channel */
-#define TRGS_PVP0_CPDOC_DMA                   61           /* Camera Pipe Data Out C DMA Channel */
-#define TRGS_PVP0_CPSTAT_DMA                  62           /* Camera Pipe Status Out DMA Channel */
-#define TRGS_PVP0_CPCI_DMA                    63           /* Camera Pipe Control In DMA Channel */
-#define TRGS_PVP0_MPDO_DMA                    64           /* Memory Pipe Data Out DMA Channel */
-#define TRGS_PVP0_MPDI_DMA                    65           /* Memory Pipe Data In DMA Channel */
-#define TRGS_PVP0_MPSTAT_DMA                  66           /* Memory Pipe Status Out DMA Channel */
-#define TRGS_PVP0_MPCI_DMA                    67           /* Memory Pipe Control In DMA Channel */
-#define TRGS_PVP0_CPDOA_DMA                   68           /* Camera Pipe Data Out A DMA Channel */
-#define TRGS_SDU0_SLAVE                       69           /* Slave Trigger */
-/*      -- RESERVED --                        70  */
-#define TRGS_C0_WAKE0                         71           /* Core 0 Wakeup Input 0 */
-#define TRGS_C0_WAKE1                         72           /* Core 0 Wakeup Input 1 */
-#define TRGS_C0_WAKE2                         73           /* Core 0 Wakeup Input 2 */
-#define TRGS_C0_WAKE3                         74           /* Core 0 Wakeup Input 3 */
-#define TRGS_C1_WAKE0                         75           /* Core 1 Wakeup Input 0 */
-#define TRGS_C1_WAKE1                         76           /* Core 1 Wakeup Input 1 */
-#define TRGS_C1_WAKE2                         77           /* Core 1 Wakeup Input 2 */
-#define TRGS_C1_WAKE3                         78           /* Core 1 Wakeup Input 3 */
-/*      -- RESERVED --                        79  */
-#define TRGS_SWU0_EVT                         80           /* Event */
-#define TRGS_SWU1_EVT                         81           /* Event */
-#define TRGS_SWU2_EVT                         82           /* Event */
-#define TRGS_SWU3_EVT                         83           /* Event */
-#define TRGS_SWU4_EVT                         84           /* Event */
-#define TRGS_SWU5_EVT                         85           /* Event */
-#define TRGS_SWU6_EVT                         86           /* Event */
-
-
-/* ============================================================================
-       Memory Map Macros
-   ============================================================================ */
-
-/* ADSP-BF609 is a multi-core processor */
-
-#define MEM_NUM_CORES                   2
-
-/* Internal memory range */
-
-#define MEM_BASE_INTERNAL               0xC0000000
-#define MEM_END_INTERNAL                0xFFFFFFFF
-#define MEM_SIZE_INTERNAL               0x40000000
-
-/* External memory range */
-
-#define MEM_BASE_EXTERNAL               0x00000000
-#define MEM_END_EXTERNAL                0xBFFFFFFF
-#define MEM_SIZE_EXTERNAL               0xC0000000
-
-/* Shared DDR2 or LPDDR Memory (256 MB) */
-
-#define MEM_BASE_DDR                    0x00000000
-#define MEM_END_DDR                     0x0FFFFFFF
-#define MEM_SIZE_DDR                    0x10000000
-
-/* Shared Async Memory (256 MB) */
-
-#define MEM_BASE_ASYNC                  0xB0000000
-#define MEM_END_ASYNC                   0xBFFFFFFF
-#define MEM_SIZE_ASYNC                  0x10000000
-
-/* Shared Async Memory Bank 0 (64 MB) */
-
-#define MEM_BASE_ASYNC_0                0xB0000000
-#define MEM_END_ASYNC_0                 0xB3FFFFFF
-#define MEM_SIZE_ASYNC_0                0x4000000
-
-/* Shared Async Memory Bank 1 (64 MB) */
-
-#define MEM_BASE_ASYNC_1                0xB4000000
-#define MEM_END_ASYNC_1                 0xB7FFFFFF
-#define MEM_SIZE_ASYNC_1                0x4000000
-
-/* Shared Async Memory Bank 2 (64 MB) */
-
-#define MEM_BASE_ASYNC_2                0xB8000000
-#define MEM_END_ASYNC_2                 0xBBFFFFFF
-#define MEM_SIZE_ASYNC_2                0x4000000
-
-/* Shared Async Memory Bank 3 (64 MB) */
-
-#define MEM_BASE_ASYNC_3                0xBC000000
-#define MEM_END_ASYNC_3                 0xBFFFFFFF
-#define MEM_SIZE_ASYNC_3                0x4000000
-
-/* Shared L2 ROM (32 KB) */
-
-#define MEM_BASE_L2_ROM                 0xC8000000
-#define MEM_END_L2_ROM                  0xC8007FFF
-#define MEM_SIZE_L2_ROM                 0x8000
-
-/* Shared L2 SRAM (256 KB) */
-
-#define MEM_BASE_L2_SRAM                0xC8080000
-#define MEM_END_L2_SRAM                 0xC80BFFFF
-#define MEM_SIZE_L2_SRAM                0x40000
-
-/* Core 1 L1 Data Bank A (32 KB) */
-
-#define MEM_C1_BASE_L1DM_A              0xFF400000
-#define MEM_C1_END_L1DM_A               0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A              0x8000
-
-/* Core 1 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM         0xFF400000
-#define MEM_C1_END_L1DM_A_SRAM          0xFF403FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 1 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_A_SRAM_CACHE   0xFF404000
-#define MEM_C1_END_L1DM_A_SRAM_CACHE    0xFF407FFF
-#define MEM_C1_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Data Bank B (32 KB) */
-
-#define MEM_C1_BASE_L1DM_B              0xFF500000
-#define MEM_C1_END_L1DM_B               0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B              0x8000
-
-/* Core 1 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM         0xFF500000
-#define MEM_C1_END_L1DM_B_SRAM          0xFF503FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 1 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1DM_B_SRAM_CACHE   0xFF504000
-#define MEM_C1_END_L1DM_B_SRAM_CACHE    0xFF507FFF
-#define MEM_C1_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 1 L1 Instruction (80 KB) */
-
-#define MEM_C1_BASE_L1IM                0xFF600000
-#define MEM_C1_END_L1IM                 0xFF613FFF
-#define MEM_C1_SIZE_L1IM                0x14000
-
-/* Core 1 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM           0xFF600000
-#define MEM_C1_END_L1IM_SRAM            0xFF60FFFF
-#define MEM_C1_SIZE_L1IM_SRAM           0x10000
-
-/* Core 1 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C1_BASE_L1IM_SRAM_CACHE     0xFF610000
-#define MEM_C1_END_L1IM_SRAM_CACHE      0xFF613FFF
-#define MEM_C1_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 1 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C1_BASE_L1_XPAD_SRAM        0xFF700000
-#define MEM_C1_END_L1_XPAD_SRAM         0xFF700FFF
-#define MEM_C1_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Core 0 L1 Data Bank A (32 KB) */
-
-#define MEM_C0_BASE_L1DM_A              0xFF800000
-#define MEM_C0_END_L1DM_A               0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A              0x8000
-
-/* Core 0 L1 Data Bank A SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM         0xFF800000
-#define MEM_C0_END_L1DM_A_SRAM          0xFF803FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM         0x4000
-
-/* Core 0 L1 Data Bank A SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_A_SRAM_CACHE   0xFF804000
-#define MEM_C0_END_L1DM_A_SRAM_CACHE    0xFF807FFF
-#define MEM_C0_SIZE_L1DM_A_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Data Bank B (32 KB) */
-
-#define MEM_C0_BASE_L1DM_B              0xFF900000
-#define MEM_C0_END_L1DM_B               0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B              0x8000
-
-/* Core 0 L1 Data Bank B SRAM (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM         0xFF900000
-#define MEM_C0_END_L1DM_B_SRAM          0xFF903FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM         0x4000
-
-/* Core 0 L1 Data Bank B SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1DM_B_SRAM_CACHE   0xFF904000
-#define MEM_C0_END_L1DM_B_SRAM_CACHE    0xFF907FFF
-#define MEM_C0_SIZE_L1DM_B_SRAM_CACHE   0x4000
-
-/* Core 0 L1 Instruction (80 KB) */
-
-#define MEM_C0_BASE_L1IM                0xFFA00000
-#define MEM_C0_END_L1IM                 0xFFA13FFF
-#define MEM_C0_SIZE_L1IM                0x14000
-
-/* Core 0 L1 Instruction SRAM (64 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM           0xFFA00000
-#define MEM_C0_END_L1IM_SRAM            0xFFA0FFFF
-#define MEM_C0_SIZE_L1IM_SRAM           0x10000
-
-/* Core 0 L1 Instruction SRAM/Cache (16 KB) */
-
-#define MEM_C0_BASE_L1IM_SRAM_CACHE     0xFFA10000
-#define MEM_C0_END_L1IM_SRAM_CACHE      0xFFA13FFF
-#define MEM_C0_SIZE_L1IM_SRAM_CACHE     0x4000
-
-/* Core 0 L1 Scratchpad SRAM (4 KB) */
-
-#define MEM_C0_BASE_L1_XPAD_SRAM        0xFFB00000
-#define MEM_C0_END_L1_XPAD_SRAM         0xFFB00FFF
-#define MEM_C0_SIZE_L1_XPAD_SRAM        0x1000
-
-/* Shared System MMR Registers (2 MB) */
-
-#define MEM_BASE_MMR_SYSTEM             0xFFC00000
-#define MEM_END_MMR_SYSTEM              0xFFDFFFFF
-#define MEM_SIZE_MMR_SYSTEM             0x200000
-
-/* Core 0 Core MMR Registers (2 MB) */
-
-#define MEM_C0_BASE_MMR_CORE            0xFFE00000
-#define MEM_C0_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C0_SIZE_MMR_CORE            0x200000
-
-/* Core 1 Core MMR Registers (2 MB) */
-
-#define MEM_C1_BASE_MMR_CORE            0xFFE00000
-#define MEM_C1_END_MMR_CORE             0xFFFFFFFF
-#define MEM_C1_SIZE_MMR_CORE            0x200000
-
-
-#endif	/* end ifndef _DEF_BF609_H */
diff --git a/libgloss/bfin/include/def_LPBlackfin.h b/libgloss/bfin/include/def_LPBlackfin.h
deleted file mode 100644
index a12080e34..000000000
--- a/libgloss/bfin/include/def_LPBlackfin.h
+++ /dev/null
@@ -1,479 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * def_LPBlackfin.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#endif /* _MISRA_RULES */
-
-
-#if !defined(__ADSPLPBLACKFIN__)
-#warning def_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
-#ifdef _MISRA_RULES
-#define MK_BMSK_( x ) (1ul<<(x))    /* Make a bit mask from a bit position */
-#else
-#define MK_BMSK_( x ) (1<<(x))    /* Make a bit mask from a bit position */
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System Register Bits */
-/*********************************************************************************** */
-
-/*************************************************** */
-/*   ASTAT register */
-/*************************************************** */
-
-/* definitions of ASTAT bit positions */
-#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
-#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
-#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
-#define ASTAT_AC0_P        0x0000000C                  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC0_COPY_P   0x00000002                  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1_P        0x0000000D                  /* Result of last ALU1 operation generated a carry */
-#define ASTAT_AV0_P        0x00000010                  /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV0S_P       0x00000011                  /* Sticky version of ASTAT_AV0  */
-#define ASTAT_AV1_P        0x00000012                  /* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_AV1S_P       0x00000013                  /* Sticky version of ASTAT_AV1  */
-#define ASTAT_V_P          0x00000018		       /* Result of last ALU0 or MAC0 operation overflowed */
-#define ASTAT_V_COPY_P     0x00000003                  /* Result of last ALU0 or MAC0 operation overflowed */
-#define ASTAT_VS_P         0x00000019		       /* Sticky version of ASTAT_V */
-
-/* ** Masks */
-#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)        /* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)        /* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)       /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)       /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)       /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)       /* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)        /* Condition Code, used for holding comparison results */
-#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)        /* Quotient Bit */
-#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)   /* Rounding mode, set for biased, clear for unbiased */
-#define ASTAT_V            MK_BMSK_(ASTAT_V_P)         /* Overflow Bit */
-#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)    /* Overflow Bit */
-
-/*************************************************** */
-/*   SEQSTAT register */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define SEQSTAT_EXCAUSE0_P      0x00000000     /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P      0x00000001  /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P      0x00000002  /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P      0x00000003  /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P      0x00000004  /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P      0x00000005  /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P      0x0000000C  /* Pending idle mode request, set by IDLE instruction */
-#define SEQSTAT_SFTRESET_P      0x0000000D  /* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_HWERRCAUSE0_P   0x0000000E  /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P   0x0000000F  /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P   0x00000010  /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P   0x00000011  /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P   0x00000012  /* Last hw error cause bit 4 */
-#define SEQSTAT_HWERRCAUSE5_P   0x00000013  /* Last hw error cause bit 5 */
-#define SEQSTAT_HWERRCAUSE6_P   0x00000014  /* Last hw error cause bit 6 */
-#define SEQSTAT_HWERRCAUSE7_P   0x00000015  /* Last hw error cause bit 7 */
-/* ** Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE        ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE5_P ) )
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P )
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE     ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) )
-
-/*************************************************** */
-/*   SYSCFG register */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define SYSCFG_SSSTEP_P         0x00000000              /* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN_P           0x00000001              /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P           0x00000002              /* Self nesting Interrupt Enable */
-
-/* ** Masks */
-#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )   /* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )     /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN	       MK_BMSK_(SYSCFG_SNEN_P)      /* Self Nesting Interrupt Enable */
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
-#define SYSCFG_CCCEN           SYSCFG_CCEN
-
-/*********************************************************************************** */
-/* Core MMR Register Map */
-/*********************************************************************************** */
-
-/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
-
-
-#define SRAM_BASE_ADDRESS	   0xFFE00000  /* SRAM Base Address Register */
-#define DMEM_CONTROL           0xFFE00004  /* Data memory control */
-#define DCPLB_STATUS		   0xFFE00008  /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_STATUS     0xFFE00008  /* "" (older define) */
-#define DCPLB_FAULT_ADDR       0xFFE0000C  /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define DCPLB_ADDR0            0xFFE00100  /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1            0xFFE00104  /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2            0xFFE00108  /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3            0xFFE0010C  /* Data Cacheability Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4            0xFFE00110  /* Data Cacheability Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5            0xFFE00114  /* Data Cacheability Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6            0xFFE00118  /* Data Cacheability Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7            0xFFE0011C  /* Data Cacheability Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8            0xFFE00120  /* Data Cacheability Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9            0xFFE00124  /* Data Cacheability Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10           0xFFE00128  /* Data Cacheability Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11           0xFFE0012C  /* Data Cacheability Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12           0xFFE00130  /* Data Cacheability Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13           0xFFE00134  /* Data Cacheability Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14           0xFFE00138  /* Data Cacheability Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15           0xFFE0013C  /* Data Cacheability Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0            0xFFE00200  /* Data Cache 0 Status */
-#define DCPLB_DATA1            0xFFE00204  /* Data Cache 1 Status */
-#define DCPLB_DATA2            0xFFE00208  /* Data Cache 2 Status */
-#define DCPLB_DATA3            0xFFE0020C  /* Data Cache 3 Status */
-#define DCPLB_DATA4            0xFFE00210  /* Data Cache 4 Status */
-#define DCPLB_DATA5            0xFFE00214  /* Data Cache 5 Status */
-#define DCPLB_DATA6            0xFFE00218  /* Data Cache 6 Status */
-#define DCPLB_DATA7            0xFFE0021C  /* Data Cache 7 Status */
-#define DCPLB_DATA8            0xFFE00220  /* Data Cache 8 Status */
-#define DCPLB_DATA9            0xFFE00224  /* Data Cache 9 Status */
-#define DCPLB_DATA10           0xFFE00228  /* Data Cache 10 Status */
-#define DCPLB_DATA11           0xFFE0022C  /* Data Cache 11 Status */
-#define DCPLB_DATA12           0xFFE00230  /* Data Cache 12 Status */
-#define DCPLB_DATA13           0xFFE00234  /* Data Cache 13 Status */
-#define DCPLB_DATA14           0xFFE00238  /* Data Cache 14 Status */
-#define DCPLB_DATA15           0xFFE0023C  /* Data Cache 15 Status */
-#define DTEST_COMMAND          0xFFE00300  /* Data Test Command Register */
-#define DTEST_DATA0            0xFFE00400  /* Data Test Data Register */
-#define DTEST_DATA1            0xFFE00404  /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL           0xFFE01004  /* Instruction Memory Control */
-#define ICPLB_STATUS		   0xFFE01008 /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS      0xFFE01008  /* "" (older define) */
-#define ICPLB_FAULT_ADDR	   0xFFE0100C  /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR        0xFFE0100C  /* "" (older define) */
-#define ICPLB_ADDR0            0xFFE01100  /* Instruction Cacheability Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1            0xFFE01104  /* Instruction Cacheability Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2            0xFFE01108  /* Instruction Cacheability Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3            0xFFE0110C  /* Instruction Cacheability Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4            0xFFE01110  /* Instruction Cacheability Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5            0xFFE01114  /* Instruction Cacheability Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6            0xFFE01118  /* Instruction Cacheability Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7            0xFFE0111C  /* Instruction Cacheability Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8            0xFFE01120  /* Instruction Cacheability Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9            0xFFE01124  /* Instruction Cacheability Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10           0xFFE01128  /* Instruction Cacheability Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11           0xFFE0112C  /* Instruction Cacheability Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12           0xFFE01130  /* Instruction Cacheability Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13           0xFFE01134  /* Instruction Cacheability Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14           0xFFE01138  /* Instruction Cacheability Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15           0xFFE0113C  /* Instruction Cacheability Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0            0xFFE01200  /* Instruction Cache 0 Status */
-#define ICPLB_DATA1            0xFFE01204  /* Instruction Cache 1 Status */
-#define ICPLB_DATA2            0xFFE01208  /* Instruction Cache 2 Status */
-#define ICPLB_DATA3            0xFFE0120C  /* Instruction Cache 3 Status */
-#define ICPLB_DATA4            0xFFE01210  /* Instruction Cache 4 Status */
-#define ICPLB_DATA5            0xFFE01214  /* Instruction Cache 5 Status */
-#define ICPLB_DATA6            0xFFE01218  /* Instruction Cache 6 Status */
-#define ICPLB_DATA7            0xFFE0121C  /* Instruction Cache 7 Status */
-#define ICPLB_DATA8            0xFFE01220  /* Instruction Cache 8 Status */
-#define ICPLB_DATA9            0xFFE01224  /* Instruction Cache 9 Status */
-#define ICPLB_DATA10           0xFFE01228  /* Instruction Cache 10 Status */
-#define ICPLB_DATA11           0xFFE0122C  /* Instruction Cache 11 Status */
-#define ICPLB_DATA12           0xFFE01230  /* Instruction Cache 12 Status */
-#define ICPLB_DATA13           0xFFE01234  /* Instruction Cache 13 Status */
-#define ICPLB_DATA14           0xFFE01238  /* Instruction Cache 14 Status */
-#define ICPLB_DATA15           0xFFE0123C  /* Instruction Cache 15 Status */
-#define ITEST_COMMAND          0xFFE01300  /* Instruction Test Command Register */
-#define ITEST_DATA0            0xFFE01400  /* Instruction Test Data Register */
-#define ITEST_DATA1            0xFFE01404  /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0                   0xFFE02000  /* Event Vector 0 ESR Address */
-#define EVT1                   0xFFE02004  /* Event Vector 1 ESR Address */
-#define EVT2                   0xFFE02008  /* Event Vector 2 ESR Address */
-#define EVT3                   0xFFE0200C  /* Event Vector 3 ESR Address */
-#define EVT4                   0xFFE02010  /* Event Vector 4 ESR Address */
-#define EVT5                   0xFFE02014  /* Event Vector 5 ESR Address */
-#define EVT6                   0xFFE02018  /* Event Vector 6 ESR Address */
-#define EVT7                   0xFFE0201C  /* Event Vector 7 ESR Address */
-#define EVT8                   0xFFE02020  /* Event Vector 8 ESR Address */
-#define EVT9                   0xFFE02024  /* Event Vector 9 ESR Address */
-#define EVT10                  0xFFE02028  /* Event Vector 10 ESR Address */
-#define EVT11                  0xFFE0202C  /* Event Vector 11 ESR Address */
-#define EVT12                  0xFFE02030  /* Event Vector 12 ESR Address */
-#define EVT13                  0xFFE02034  /* Event Vector 13 ESR Address */
-#define EVT14                  0xFFE02038  /* Event Vector 14 ESR Address */
-#define EVT15                  0xFFE0203C  /* Event Vector 15 ESR Address */
-#define IMASK                  0xFFE02104  /* Interrupt Mask Register */
-#define IPEND                  0xFFE02108  /* Interrupt Pending Register */
-#define ILAT                   0xFFE0210C  /* Interrupt Latch Register */
-#define IPRIO                  0xFFE02110  /* Core Interrupt Priority Register */
-
-/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL                  0xFFE03000  /* Core Timer Control Register */
-#define TPERIOD                0xFFE03004  /* Core Timer Period Register */
-#define TSCALE                 0xFFE03008  /* Core Timer Scale Register */
-#define TCOUNT                 0xFFE0300C  /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
-#define DSPID                  0xFFE05000  /* DSP Processor ID Register for MP implementations */
-
-#define DBGSTAT                0xFFE05008  /* Debug Status Register */
-
-
-/* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL                0xFFE06000  /* Trace Buffer Control Register */
-#define TBUFSTAT               0xFFE06004  /* Trace Buffer Status Register */
-#define TBUF                   0xFFE06100  /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-#define WPIACTL                0xFFE07000  /* Watchpoint Instruction Address Control Register  */
-#define WPIA0                  0xFFE07040  /* Watchpoint Instruction Address Register 0 */
-#define WPIA1                  0xFFE07044  /* Watchpoint Instruction Address Register 1 */
-#define WPIA2                  0xFFE07048  /* Watchpoint Instruction Address Register 2 */
-#define WPIA3                  0xFFE0704C  /* Watchpoint Instruction Address Register 3 */
-#define WPIA4                  0xFFE07050  /* Watchpoint Instruction Address Register 4 */
-#define WPIA5                  0xFFE07054  /* Watchpoint Instruction Address Register 5 */
-#define WPIACNT0               0xFFE07080  /* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT1               0xFFE07084  /* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT2               0xFFE07088  /* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT3               0xFFE0708C  /* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT4               0xFFE07090  /* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT5               0xFFE07094  /* Watchpoint Instruction Address Count Register 5 */
-#define WPDACTL                0xFFE07100  /* Watchpoint Data Address Control Register */
-#define WPDA0                  0xFFE07140  /* Watchpoint Data Address Register 0  */
-#define WPDA1                  0xFFE07144  /* Watchpoint Data Address Register 1 */
-#define WPDACNT0               0xFFE07180  /* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT1               0xFFE07184  /* Watchpoint Data Address Count Value Register 1 */
-#define WPSTAT                 0xFFE07200  /* Watchpoint Status Register */
-
-/* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
-
-#define PFCTL                  0xFFE08000  /* Performance Monitor Control Register */
-#define PFCNTR0                0xFFE08100  /* Performance Monitor Counter Register 0 */
-#define PFCNTR1                0xFFE08104  /* Performance Monitor Counter Register 1 */
-
-
-/*********************************************************************************** */
-/* Core MMR Register Bits */
-/*********************************************************************************** */
-
-/*************************************************** */
-/*   EVT registers (ILAT, IMASK, and IPEND). */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define EVT_EMU_P            0x00000000  /* Emulator interrupt bit position */
-#define EVT_RST_P            0x00000001  /* Reset interrupt bit position */
-#define EVT_NMI_P            0x00000002  /* Non Maskable interrupt bit position */
-#define EVT_EVX_P            0x00000003  /* Exception bit position */
-#define EVT_IRPTEN_P         0x00000004  /* Global interrupt enable bit position */
-#define EVT_IVHW_P           0x00000005  /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P          0x00000006  /* Timer interrupt bit position */
-#define EVT_IVG7_P           0x00000007  /* IVG7 interrupt bit position */
-#define EVT_IVG8_P           0x00000008  /* IVG8 interrupt bit position */
-#define EVT_IVG9_P           0x00000009  /* IVG9 interrupt bit position */
-#define EVT_IVG10_P          0x0000000a  /* IVG10 interrupt bit position */
-#define EVT_IVG11_P          0x0000000b  /* IVG11 interrupt bit position */
-#define EVT_IVG12_P          0x0000000c  /* IVG12 interrupt bit position */
-#define EVT_IVG13_P          0x0000000d  /* IVG13 interrupt bit position */
-#define EVT_IVG14_P          0x0000000e  /* IVG14 interrupt bit position */
-#define EVT_IVG15_P          0x0000000f  /* IVG15 interrupt bit position */
-
-/* ** Masks */
-#define EVT_EMU              MK_BMSK_(EVT_EMU_P   ) /* Emulator interrupt mask */
-#define EVT_RST              MK_BMSK_(EVT_RST_P   ) /* Reset interrupt mask */
-#define EVT_NMI              MK_BMSK_(EVT_NMI_P   ) /* Non Maskable interrupt mask */
-#define EVT_EVX              MK_BMSK_(EVT_EVX_P   ) /* Exception mask */
-#define EVT_IRPTEN           MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW             MK_BMSK_(EVT_IVHW_P  ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR            MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7             MK_BMSK_(EVT_IVG7_P  ) /* IVG7 interrupt mask */
-#define EVT_IVG8             MK_BMSK_(EVT_IVG8_P  ) /* IVG8 interrupt mask */
-#define EVT_IVG9             MK_BMSK_(EVT_IVG9_P  ) /* IVG9 interrupt mask */
-#define EVT_IVG10            MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11            MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12            MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13            MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14            MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15            MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/*************************************************** */
-/*   DMEM_CONTROL Register */
-/*************************************************** */
-/* ** Bit Positions */
-#define ENDM_P						 0x00			/* (doesn't really exist) Enable Data Memory L1 */
-#define DMCTL_ENDM_P				 ENDM_P		/* "" (older define) */
-
-#define ENDCPLB_P					 0x01			/* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P			 ENDCPLB_P  /* "" (older define) */
-#if defined(__ADSPBF50x__)
-#define DMC_P						 0x03			/* L1 Data Memory Configure bit   */
-#else
-#define DMC0_P						 0x02			/* L1 Data Memory Configure bit 0 */
-#define DMC1_P						 0x03			/* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC0_P				 DMC0_P		/* "" (older define) */
-#define DMCTL_DMC1_P				 DMC1_P		/* "" (older define) */
-#endif
-#define DCBS_P						 0x04			/* L1 Data Cache Bank Select */
-#define PORT_PREF0_P				 0x12			/* DAG0 Port Preference */
-#define PORT_PREF1_P				 0x13			/* DAG1 Port Preference */
-
-/* ** Masks */
-#define ENDM                   0x00000001   /* (doesn't really exist) Enable Data Memory L1 */
-#define ENDCPLB                0x00000002   /* Enable DCPLB */
-#define ASRAM_BSRAM            0x00000000
-#define ACACHE_BSRAM           0x00000008
-#define ACACHE_BCACHE          0x0000000C
-#define DCBS                   0x00000010   /*  L1 Data Cache Bank Select */
-#define PORT_PREF0			   0x00001000   /* DAG0 Port Preference */
-#define PORT_PREF1			   0x00002000   /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* ** Bit Positions */
-#define ENICPLB_P					 0x01  /* Enable ICPLB */
-#define IMCTL_ENICPLB_P				 0x01  /* "" (older define) */
-#define IMC_P						 0x02  /* Enable  */
-#define IMCTL_IMC_P					 0x02  /* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0_P						 0x03  /* Lock Way 0 */
-#define ILOC1_P						 0x04  /* Lock Way 1 */
-#define ILOC2_P						 0x05  /* Lock Way 2 */
-#define ILOC3_P						 0x06  /* Lock Way 3 */
-#define LRUPRIORST_P				 0x0D  /* Least Recently Used Replacement Priority */
-/* ** Masks */
-#define ENICPLB                0x00000002  /* Enable ICPLB */
-#define IMC                    0x00000004  /* Configure L1 code memory as cache (0=SRAM) */
-#define ILOC0				   0x00000008  /* Lock Way 0 */
-#define ILOC1				   0x00000010  /* Lock Way 1 */
-#define ILOC2				   0x00000020  /* Lock Way 2 */
-#define ILOC3				   0x00000040  /* Lock Way 3 */
-#define LRUPRIORST			   0x00002000  /* Least Recently Used Replacement Priority */
-
-/* TCNTL Masks */
-#define TMPWR                  0x00000001  /* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN                  0x00000002  /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD               0x00000004  /* Timer auto reload */
-#define TINT                   0x00000008  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* TCNTL Bit Positions */
-#define TMPWR_P                 0x00000000  /* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN_P                 0x00000001  /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD_P              0x00000002  /* Timer auto reload */
-#define TINT_P                  0x00000003  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* DCPLB_DATA and ICPLB_DATA Registers - bit positions */
-#define CPLB_VALID_P            0  /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P             1  /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P          2  /* 0=no read access, 1=read access allowed (user mode) */
-#define CPLB_PORTPRIO_P         9  /* 0=low priority port, 1= high priority port */
-/*** ICPLB_DATA only */
-#define CPLB_LRUPRIO_P          8  /* 0=can be replaced by any line, 1=priority for non-replacement */
-/*** DCPLB_DATA only */
-#define CPLB_USER_WR_P          3  /* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR_P          4  /* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_DIRTY_P            7  /* 1=dirty, 0=clean */
-#define CPLB_L1_CHBL_P          12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
-#define CPLB_WT_P               14 /* 0=write-back, 1=write-through */
-#define CPLB_L1_AOW_P           15 /* 0=do not allocate cache lines on write-through writes,  */
-                                   /* 1= allocate cache lines on write-through writes. */
-
-/* DCPLB_DATA and ICPLB_DATA Registers - Masks */
-#define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
-#define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
-#define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
-#define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
-#define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
-#define CPLB_PORTPRIO          0x00000200  /* 0=low priority port, 1= high priority port */
-#define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
-/*** ICPLB_DATA only */
-#define CPLB_LRUPRIO           0x00000100  /* 0=can be replaced by any line, 1=priority for non-replacement */
-/*** DCPLB_DATA only */
-#define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW            0x00008000  /* 0=do not allocate cache lines on write-through writes,  */
-                                           /* 1= allocate cache lines on write-through writes. */
-#define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
-
-
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/*** Masks */
-#define TEST_READ			   0x00000000  /* Read Access */
-#define TEST_WRITE			   0x00000002  /* Write Access */
-#define TEST_TAG			   0x00000000  /* Access TAG */
-#define TEST_DATA			   0x00000004  /* Access DATA */
-#define TEST_DW0			   0x00000000  /* Select Double Word 0 */
-#define TEST_DW1			   0x00000008  /* Select Double Word 1 */
-#define TEST_DW2			   0x00000010  /* Select Double Word 2 */
-#define TEST_DW3			   0x00000018  /* Select Double Word 3 */
-#define TEST_MB0			   0x00000000  /* Select Mini-Bank 0 */
-#define TEST_MB1			   0x00010000  /* Select Mini-Bank 1 */
-#define TEST_MB2			   0x00020000  /* Select Mini-Bank 2 */
-#define TEST_MB3			   0x00030000  /* Select Mini-Bank 3 */
-/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
-#ifdef _MISRA_RULES
-#define TEST_SET(x)		       (((x) << 5) & 0x03E0u)  /* Set Index 0->31 */
-#else
-#define TEST_SET(x)		       (((x) << 5) & 0x03E0)  /* Set Index 0->31 */
-#endif /* _MISRA_RULES */
-#define TEST_WAY0			   0x00000000  /* Access Way0 */
-#define TEST_WAY1			   0x04000000  /* Access Way1 */
-/*** ITEST_COMMAND only */
-#define TEST_WAY2			   0x08000000  /* Access Way2 */
-#define TEST_WAY3			   0x0C000000  /* Access Way3 */
-/*** DTEST_COMMAND only */
-#define TEST_BNKSELA		   0x00000000  /* Access SuperBank A */
-#define TEST_BNKSELB		   0x00800000  /* Access SuperBank B */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_LPBLACKFIN_H */
diff --git a/libgloss/bfin/include/defblackfin.h b/libgloss/bfin/include/defblackfin.h
deleted file mode 100644
index c0c122ef0..000000000
--- a/libgloss/bfin/include/defblackfin.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * defblackfin.h
- *
- * (c) Copyright 2001-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
-
-#ifndef _DEF_BLACKFIN_H
-#define _DEF_BLACKFIN_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#endif /* _MISRA_RULES */
-
-
-#if defined(__ADSPLPBLACKFIN__)
-#warning defblackfin.h should only be included for 535 compatible chips.
-#endif
-/* Macro parameters should be enclosed in parentheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
-#ifdef _MISRA_RULES
-#define MK_BMSK_( x ) (1ul<<(x))    /* Make a bit mask from a bit position */
-#else
-#define MK_BMSK_( x ) (1<<(x))    /* Make a bit mask from a bit position */
-#endif /* _MISRA_RULES */
-
-/*********************************************************************************** */
-/* System Register Bits */
-/*********************************************************************************** */
-
-/*************************************************** */
-/*   ASTAT register */
-/*************************************************** */
-
-#if !defined(__ADSPLPBLACKFIN__)
-/* ** Bit Positions */
-#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_AC0_COPY_P   0x00000002                  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_V_COPY_P     0x00000003                  /* Result of last DAG operation overflowed */
-#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
-#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
-#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
-
-#else	/* !__ADSPLPBLACKFIN__ */
-
-/* definitions of ASTAT bit positions for next revision of BLACKFIN */
-#define ASTAT_AZ_P         0x00000000                  /* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN_P         0x00000001                  /* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_CC_P         0x00000005                  /* Condition Code, used for holding comparison results */
-#define ASTAT_AQ_P         0x00000006                  /* Quotient Bit */
-#define ASTAT_RND_MOD_P    0x00000008                  /* Rounding mode, set for biased, clear for unbiased */
-#define ASTAT_AC0_P        0x0000000C                  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1_P        0x0000000D                  /* Result of last ALU1 operation generated a carry */
-#define ASTAT_AV0_P        0x00000010                  /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV0S_P       0x00000011                  /* Sticky version of ASTAT_AV0_P */
-#define ASTAT_AV1_P        0x00000012                  /* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_AV1S_P       0x00000013                  /* Sticky version of ASTAT_AV1_P */
-#define ASTAT_V_P          0x00000018                  /* Result of last op written to data register file. */
-#define ASTAT_VS_P         0x00000019                  /* Sticky version of ASTAT_V_P */
-#endif /* !__ADSPLPBLACKFIN__ */
-
-/* ** Masks */
-#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)        /* Result of last ALU0 or shifter operation is zero */
-#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)        /* Result of last ALU0 or shifter operation is negative */
-#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)        /* Condition Code, used for holding comparison results */
-#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)        /* Quotient Bit */
-#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)   /* Rounding mode, set for biased, clear for unbiased */
-
-#if !defined(__ADSPLPBLACKFIN__)
-
-#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)  /* Result of last ALU0 operation generated a carry */
-#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)    /* Result of last DAG operation overflowed */
-
-#else /* !__ADSPLPBLACKFIN__ */
-
-#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)       /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
-#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)       /* Result of last MAC1 operation overflowed, sticky for MAC */
-#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)       /* Result of last ALU0 operation generated a carry */
-#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)       /* Result of last ALU1 operation generated a carry */
-#define ASTAT_AV0S         MK_BMSK_(ASTAT_AV0S_P)      /* Sticky version of ASTAT_AV0_P */
-#define ASTAT_AV1S         MK_BMSK_(ASTAT_AV1S_P)      /* Sticky version of ASTAT_AV1_P */
-#define ASTAT_V            MK_BMSK_(ASTAT_V_P)         /* Result of last op written to data register file. */
-#define ASTAT_VS           MK_BMSK_(ASTAT_VS_P)        /* Sticky version of ASTAT_V_P */
-
-#endif	/* !__ADSPLPBLACKFIN__ */
-
-/*************************************************** */
-/*   SEQSTAT register */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define SEQSTAT_EXCAUSE0_P     0x00000000     /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P     0x00000001  /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P     0x00000002  /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P     0x00000003  /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P     0x00000004  /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P     0x00000005  /* Last exception cause bit 5 */
-#define SEQSTAT_OMODE0_P       0x0000000A  /* Operating mode: 00 user, 01 supervisor, 1x debug */
-#define SEQSTAT_OMODE1_P       0x0000000B  /* Operating mode: 00 user, 01 supervisor, 1x debug */
-#define SEQSTAT_IDLE_REQ_P     0x0000000C  /* Pending idle mode request, set by IDLE instruction */
-#define SEQSTAT_SFTRESET_P     0x0000000D  /* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_HWERRCAUSE0_P  0x0000000E  /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P  0x0000000F  /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P  0x00000010  /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P  0x00000011  /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P  0x00000012  /* Last hw error cause bit 4 */
-
-/* ** Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE        ( MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
-                                 MK_BMSK_(SEQSTAT_EXCAUSE5_P) )
-
-/* Operating mode: 00 user, 01 supervisor, 1x debug */
-#define SEQSTAT_OMODE          ( MK_BMSK_(SEQSTAT_OMODE0_P) | \
-                                 MK_BMSK_(SEQSTAT_OMODE1_P) )
-
-/* Pending idle mode request, set by IDLE instruction */
-#define SEQSTAT_IDLE_REQ       MK_BMSK_(SEQSTAT_IDLE_REQ_P)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET       MK_BMSK_(SEQSTAT_SFTRESET_P)
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE     ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
-                                 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) )
-
-/*************************************************** */
-/*   SYSCFG register */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define SYSCFG_SSSTEP_P        0x00000000              /* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN_P          0x00000001              /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P          0x00000002              /* Enable self-nesting interrupts (=1) */
-
-/* ** Masks */
-#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P)   /* Supervisor single step, when set it forces an exception for each instruction executed */
-#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P)     /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN           MK_BMSK_(SYSCFG_SNEN_P)     /* Enable self-nesting interrupts (=1) */
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
-#define SYSCFG_CCCEN           SYSCFG_CCEN
-
-
-/*********************************************************************************** */
-/* Core MMR Register Map */
-/*********************************************************************************** */
-
-/* Cache & SRAM Memory */
-#define SRAM_BASE_ADDRESS      0xFFE00000  /* SRAM Base Address (Read Only) */
-#define DMEM_CONTROL           0xFFE00004  /* Data memory control */
-#define DCPLB_STATUS           0xFFE00008  /* Data Cache Programmable Look-Aside Buffer Status */
-#define DCPLB_FAULT_ADDR       0xFFE0000C  /* Data Cache Programmable Look-Aside Buffer Fault Address */
-#define MMR_TIMEOUT            0xFFE00010  /* Memory-Mapped Register Timeout Register */
-#define DCPLB_ADDR0            0xFFE00100  /* Data Cache Protection Lookaside Buffer 0 */
-#define DCPLB_ADDR1            0xFFE00104  /* Data Cache Protection Lookaside Buffer 1 */
-#define DCPLB_ADDR2            0xFFE00108  /* Data Cache Protection Lookaside Buffer 2 */
-#define DCPLB_ADDR3            0xFFE0010C  /* Data Cache Protection Lookaside Buffer 3 */
-#define DCPLB_ADDR4            0xFFE00110  /* Data Cache Protection Lookaside Buffer 4 */
-#define DCPLB_ADDR5            0xFFE00114  /* Data Cache Protection Lookaside Buffer 5 */
-#define DCPLB_ADDR6            0xFFE00118  /* Data Cache Protection Lookaside Buffer 6 */
-#define DCPLB_ADDR7            0xFFE0011C  /* Data Cache Protection Lookaside Buffer 7 */
-#define DCPLB_ADDR8            0xFFE00120  /* Data Cache Protection Lookaside Buffer 8 */
-#define DCPLB_ADDR9            0xFFE00124  /* Data Cache Protection Lookaside Buffer 9 */
-#define DCPLB_ADDR10           0xFFE00128  /* Data Cache Protection Lookaside Buffer 10 */
-#define DCPLB_ADDR11           0xFFE0012C  /* Data Cache Protection Lookaside Buffer 11 */
-#define DCPLB_ADDR12           0xFFE00130  /* Data Cache Protection Lookaside Buffer 12 */
-#define DCPLB_ADDR13           0xFFE00134  /* Data Cache Protection Lookaside Buffer 13 */
-#define DCPLB_ADDR14           0xFFE00138  /* Data Cache Protection Lookaside Buffer 14 */
-#define DCPLB_ADDR15           0xFFE0013C  /* Data Cache Protection Lookaside Buffer 15 */
-#define DCPLB_DATA0            0xFFE00200  /* Data Cache 0 Status */
-#define DCPLB_DATA1            0xFFE00204  /* Data Cache 1 Status */
-#define DCPLB_DATA2            0xFFE00208  /* Data Cache 2 Status */
-#define DCPLB_DATA3            0xFFE0020C  /* Data Cache 3 Status */
-#define DCPLB_DATA4            0xFFE00210  /* Data Cache 4 Status */
-#define DCPLB_DATA5            0xFFE00214  /* Data Cache 5 Status */
-#define DCPLB_DATA6            0xFFE00218  /* Data Cache 6 Status */
-#define DCPLB_DATA7            0xFFE0021C  /* Data Cache 7 Status */
-#define DCPLB_DATA8            0xFFE00220  /* Data Cache 8 Status */
-#define DCPLB_DATA9            0xFFE00224  /* Data Cache 9 Status */
-#define DCPLB_DATA10           0xFFE00228  /* Data Cache 10 Status */
-#define DCPLB_DATA11           0xFFE0022C  /* Data Cache 11 Status */
-#define DCPLB_DATA12           0xFFE00230  /* Data Cache 12 Status */
-#define DCPLB_DATA13           0xFFE00234  /* Data Cache 13 Status */
-#define DCPLB_DATA14           0xFFE00238  /* Data Cache 14 Status */
-#define DCPLB_DATA15           0xFFE0023C  /* Data Cache 15 Status */
-#define DTEST_COMMAND          0xFFE00300  /* Data Test Command Register */
-#define DTEST_INDEX            0xFFE00304  /* Data Test Index Register */
-#define DTEST_DATA0            0xFFE00400  /* Data Test Data Register */
-#define DTEST_DATA1            0xFFE00404  /* Data Test Data Register */
-#define DTEST_DATA2            0xFFE00408  /* Data Test Data Register */
-#define DTEST_DATA3            0xFFE0040C  /* Data Test Data Register */
-#define IMEM_CONTROL           0xFFE01004  /* Instruction Memory Control */
-#define ICPLB_STATUS           0xFFE01008  /* Instruction Cache miss status */
-#define ICPLB_FAULT_ADDR       0xFFE0100C  /* Instruction Cache miss address */
-#define ICPLB_ADDR0            0xFFE01100  /* Instruction Cache Protection Lookaside Buffer 0 */
-#define ICPLB_ADDR1            0xFFE01104  /* Instruction Cache Protection Lookaside Buffer 1 */
-#define ICPLB_ADDR2            0xFFE01108  /* Instruction Cache Protection Lookaside Buffer 2 */
-#define ICPLB_ADDR3            0xFFE0110C  /* Instruction Cache Protection Lookaside Buffer 3 */
-#define ICPLB_ADDR4            0xFFE01110  /* Instruction Cache Protection Lookaside Buffer 4 */
-#define ICPLB_ADDR5            0xFFE01114  /* Instruction Cache Protection Lookaside Buffer 5 */
-#define ICPLB_ADDR6            0xFFE01118  /* Instruction Cache Protection Lookaside Buffer 6 */
-#define ICPLB_ADDR7            0xFFE0111C  /* Instruction Cache Protection Lookaside Buffer 7 */
-#define ICPLB_ADDR8            0xFFE01120  /* Instruction Cache Protection Lookaside Buffer 8 */
-#define ICPLB_ADDR9            0xFFE01124  /* Instruction Cache Protection Lookaside Buffer 9 */
-#define ICPLB_ADDR10           0xFFE01128  /* Instruction Cache Protection Lookaside Buffer 10 */
-#define ICPLB_ADDR11           0xFFE0112C  /* Instruction Cache Protection Lookaside Buffer 11 */
-#define ICPLB_ADDR12           0xFFE01130  /* Instruction Cache Protection Lookaside Buffer 12 */
-#define ICPLB_ADDR13           0xFFE01134  /* Instruction Cache Protection Lookaside Buffer 13 */
-#define ICPLB_ADDR14           0xFFE01138  /* Instruction Cache Protection Lookaside Buffer 14 */
-#define ICPLB_ADDR15           0xFFE0113C  /* Instruction Cache Protection Lookaside Buffer 15 */
-#define ICPLB_DATA0            0xFFE01200  /* Instruction Cache 0 Status */
-#define ICPLB_DATA1            0xFFE01204  /* Instruction Cache 1 Status */
-#define ICPLB_DATA2            0xFFE01208  /* Instruction Cache 2 Status */
-#define ICPLB_DATA3            0xFFE0120C  /* Instruction Cache 3 Status */
-#define ICPLB_DATA4            0xFFE01210  /* Instruction Cache 4 Status */
-#define ICPLB_DATA5            0xFFE01214  /* Instruction Cache 5 Status */
-#define ICPLB_DATA6            0xFFE01218  /* Instruction Cache 6 Status */
-#define ICPLB_DATA7            0xFFE0121C  /* Instruction Cache 7 Status */
-#define ICPLB_DATA8            0xFFE01220  /* Instruction Cache 8 Status */
-#define ICPLB_DATA9            0xFFE01224  /* Instruction Cache 9 Status */
-#define ICPLB_DATA10           0xFFE01228  /* Instruction Cache 10 Status */
-#define ICPLB_DATA11           0xFFE0122C  /* Instruction Cache 11 Status */
-#define ICPLB_DATA12           0xFFE01230  /* Instruction Cache 12 Status */
-#define ICPLB_DATA13           0xFFE01234  /* Instruction Cache 13 Status */
-#define ICPLB_DATA14           0xFFE01238  /* Instruction Cache 14 Status */
-#define ICPLB_DATA15           0xFFE0123C  /* Instruction Cache 15 Status */
-#define ITEST_COMMAND          0xFFE01300  /* Instruction Test Command Register */
-#define ITEST_INDEX            0xFFE01304  /* Instruction Test Index Register */
-#define ITEST_DATA0            0xFFE01400  /* Instruction Test Data Register */
-#define ITEST_DATA1            0xFFE01404  /* Instruction Test Data Register */
-
-/* Event/Interrupt Registers */
-#define EVT0                   0xFFE02000  /* Event Vector 0 ESR Address */
-#define EVT1                   0xFFE02004  /* Event Vector 1 ESR Address */
-#define EVT2                   0xFFE02008  /* Event Vector 2 ESR Address */
-#define EVT3                   0xFFE0200C  /* Event Vector 3 ESR Address */
-#define EVT4                   0xFFE02010  /* Event Vector 4 ESR Address */
-#define EVT5                   0xFFE02014  /* Event Vector 5 ESR Address */
-#define EVT6                   0xFFE02018  /* Event Vector 6 ESR Address */
-#define EVT7                   0xFFE0201C  /* Event Vector 7 ESR Address */
-#define EVT8                   0xFFE02020  /* Event Vector 8 ESR Address */
-#define EVT9                   0xFFE02024  /* Event Vector 9 ESR Address */
-#define EVT10                  0xFFE02028  /* Event Vector 10 ESR Address */
-#define EVT11                  0xFFE0202C  /* Event Vector 11 ESR Address */
-#define EVT12                  0xFFE02030  /* Event Vector 12 ESR Address */
-#define EVT13                  0xFFE02034  /* Event Vector 13 ESR Address */
-#define EVT14                  0xFFE02038  /* Event Vector 14 ESR Address */
-#define EVT15                  0xFFE0203C  /* Event Vector 15 ESR Address */
-#define IMASK                  0xFFE02104  /* Interrupt Mask Register */
-#define IPEND                  0xFFE02108  /* Interrupt Pending Register */
-#define ILAT                   0xFFE0210C  /* Interrupt Latch Register */
-
-/* Core Timer Registers */
-#define TCNTL                  0xFFE03000  /* Core Timer Control Register */
-#define TPERIOD                0xFFE03004  /* Core Timer Period Register */
-#define TSCALE                 0xFFE03008  /* Core Timer Scale Register */
-#define TCOUNT                 0xFFE0300C  /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers */
-#define DSPID                  0xFFE05000  /* DSP Processor ID Register for MP implementations */
-#define DBGCTL                 0xFFE05004  /* Debug Control Register */
-#define DBGSTAT                0xFFE05008  /* Debug Status Register */
-#define EMUDAT                 0xFFE0500C  /* Emulator Data Register */
-
-/* Trace Buffer Registers */
-#define TBUFCTL                0xFFE06000  /* Trace Buffer Control Register */
-#define TBUFSTAT               0xFFE06004  /* Trace Buffer Status Register */
-#define TBUF                   0xFFE06100  /* Trace Buffer */
-
-/* Watch Point Control Registers */
-#define WPIACTL                0xFFE07000  /* Instruction Watch Point Control Register */
-#define WPIA0                  0xFFE07040  /* Instruction Watch Point Address 0 */
-#define WPIA1                  0xFFE07044  /* Instruction Watch Point Address 1 */
-#define WPIA2                  0xFFE07048  /* Instruction Watch Point Address 2 */
-#define WPIA3                  0xFFE0704C  /* Instruction Watch Point Address 3 */
-#define WPIA4                  0xFFE07050  /* Instruction Watch Point Address 4 */
-#define WPIA5                  0xFFE07054  /* Instruction Watch Point Address 5 */
-#define WPIACNT0               0xFFE07080  /* Instruction Watch Point Counter 0 */
-#define WPIACNT1               0xFFE07084  /* Instruction Watch Point Counter 1 */
-#define WPIACNT2               0xFFE07088  /* Instruction Watch Point Counter 2 */
-#define WPIACNT3               0xFFE0708C  /* Instruction Watch Point Counter 3 */
-#define WPIACNT4               0xFFE07090  /* Instruction Watch Point Counter 4 */
-#define WPIACNT5               0xFFE07094  /* Instruction Watch Point Counter 5 */
-#define WPDACTL                0xFFE07100  /* Data Watch Point Control Register */
-#define WPDA0                  0xFFE07140  /* Data Watch Point Address 0 */
-#define WPDA1                  0xFFE07144  /* Data Watch Point Address 1 */
-#define WPDACNT0               0xFFE07180  /* Data Watch Point Counter 0 */
-#define WPDACNT1               0xFFE07184  /* Data Watch Point Counter 1 */
-#define WPSTAT                 0xFFE07200  /* Watch Point Status Register */
-
-/* Performance Monitor Registers */
-#define PFCTL                  0xFFE08000  /* Performance Monitor Control Register */
-#define PFCNTR0                0xFFE08100  /* Performance Monitor Counter Register 0 */
-#define PFCNTR1                0xFFE08104  /* Performance Monitor Counter Register 1 */
-
-
-/*********************************************************************************** */
-/* Core MMR Register Bits */
-/*********************************************************************************** */
-
-/*************************************************** */
-/*   EVT registers (ILAT, IMASK, and IPEND). */
-/*************************************************** */
-
-/* ** Bit Positions */
-#define EVT_EMU_P            0x00000000  /* Emulator interrupt bit position */
-#define EVT_RST_P            0x00000001  /* Reset interrupt bit position */
-#define EVT_NMI_P            0x00000002  /* Non Maskable interrupt bit position */
-#define EVT_EVX_P            0x00000003  /* Exception bit position */
-#define EVT_IRPTEN_P         0x00000004  /* Global interrupt enable bit position */
-#define EVT_IVHW_P           0x00000005  /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P          0x00000006  /* Timer interrupt bit position */
-#define EVT_IVG7_P           0x00000007  /* IVG7 interrupt bit position */
-#define EVT_IVG8_P           0x00000008  /* IVG8 interrupt bit position */
-#define EVT_IVG9_P           0x00000009  /* IVG9 interrupt bit position */
-#define EVT_IVG10_P          0x0000000a  /* IVG10 interrupt bit position */
-#define EVT_IVG11_P          0x0000000b  /* IVG11 interrupt bit position */
-#define EVT_IVG12_P          0x0000000c  /* IVG12 interrupt bit position */
-#define EVT_IVG13_P          0x0000000d  /* IVG13 interrupt bit position */
-#define EVT_IVG14_P          0x0000000e  /* IVG14 interrupt bit position */
-#define EVT_IVG15_P          0x0000000f  /* IVG15 interrupt bit position */
-
-/* ** Masks */
-#define EVT_EMU              MK_BMSK_(EVT_EMU_P   ) /* Emulator interrupt mask */
-#define EVT_RST              MK_BMSK_(EVT_RST_P   ) /* Reset interrupt mask */
-#define EVT_NMI              MK_BMSK_(EVT_NMI_P   ) /* Non Maskable interrupt mask */
-#define EVT_EVX              MK_BMSK_(EVT_EVX_P   ) /* Exception mask */
-#define EVT_IRPTEN           MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
-#define EVT_IVHW             MK_BMSK_(EVT_IVHW_P  ) /* Hardware Error interrupt mask */
-#define EVT_IVTMR            MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
-#define EVT_IVG7             MK_BMSK_(EVT_IVG7_P  ) /* IVG7 interrupt mask */
-#define EVT_IVG8             MK_BMSK_(EVT_IVG8_P  ) /* IVG8 interrupt mask */
-#define EVT_IVG9             MK_BMSK_(EVT_IVG9_P  ) /* IVG9 interrupt mask */
-#define EVT_IVG10            MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
-#define EVT_IVG11            MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
-#define EVT_IVG12            MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
-#define EVT_IVG13            MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
-#define EVT_IVG14            MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
-#define EVT_IVG15            MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
-
-/*************************************************** */
-/*   DMEM_CONTROL register */
-/*************************************************** */
-/* ** Bit Positions */
-#define ENDM_P						 0x00			/* Enable Data Memory L1 */
-#define DMCTL_ENDM_P				 ENDM_P		/* "" (older define) */
-#define ENDCPLB_P					 0x01			/* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P			 ENDCPLB_P	/* "" (older define) */
-#define DMC0_P						 0x02			/* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P				 DMC0_P		/* "" (older define) */
-#define DMC1_P						 0x03			/* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P				 DMC1_P		/* "" (older define) */
-
-/* ** Masks */
-#define ENDM                   MK_BMSK_(DMCTL_ENDM_P)  /* Enable Data Memory L1 */
-
-/* Bank A set as SRAM, Bank B set as SRAM */
-#define ASRAM_BSRAM            0x00000000
-
-/* Enable DCPLB */
-#define ENDCPLB                MK_BMSK_(DMCTL_ENDCPLB_P)
-
-/* Bank A set as CACHE, Bank B set as SRAM */
-#define ACACHE_BSRAM           0x00000008
-/* Bank A set as CACHE, Bank B set as CACHE */
-#define ACACHE_BCACHE          0x0000000C
-#define DCBS                   0x00000010  /* If HIGHBIT is 1, select L1 data memory B */
-                                           /* If HIGHBIT is 0, select L1 data memory A */
-                                           /* If LOWBIT is 1, select L1 memory bank B */
-                                           /* If LOWBIT is 0, select L1 memory bank A */
-
-/* IMEM_CONTROL Masks */
-#define ENIM                   0x00000001  /* Enable L1 Code Memory */
-#define ENICPLB                0x00000002  /* Enable ICPLB */
-#define IMC                    0x00000004  /* Configure L1 code memory as cache (0=SRAM) */
-
-/* TCNTL Masks */
-#define TMPWR                  0x00000001  /* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN                  0x00000002  /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD               0x00000004  /* Timer auto reload */
-#define TINT                   0x00000008  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* TCNTL Bit Positions */
-#define TMPWR_P                0x00000000  /* Timer Low Power Control, 0=low power mode, 1=active state */
-#define TMREN_P                0x00000001  /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD_P             0x00000002  /* Timer auto reload */
-#define TINT_P                 0x00000003  /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
-
-/* DCPLB_DATA and ICPLB_DATA Masks */
-#define CPLB_VALID             0x00000001  /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK              0x00000002  /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD           0x00000004  /* 0=no read access, 1=read access allowed (user mode) */
-#define CPLB_USER_WR           0x00000008  /* 0=no write access, 0=write access allowed (user mode) */
-         /* only applies to L1 data memory */
-#define CPLB_SUPV_WR           0x00000010  /* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_L1SRAM            0x00000020  /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
-#define CPLB_DA0ACC            0x00000040  /* 0=access allowed from either DAG, 1=access from DAG0 only */
-         /* only applies in L1 data memory controller */
-#define CPLB_DIRTY             0x00000080  /* 1=dirty, 0=clean */
-         /* only applies in L1 data memory controller */
-#define CPLB_L1_CHBL           0x00001000  /* 0=non-cacheable in L1, 1=cacheable in L1 */
-#define CPLB_WT                0x00004000  /* 0=write-back, 1=write-through */
-         /* only applies in L1 data memory controller in cache mode */
-#define PAGE_SIZE_1KB          0x00000000  /* 1 KB page size */
-#define PAGE_SIZE_4KB          0x00010000  /* 4 KB page size */
-#define PAGE_SIZE_1MB          0x00020000  /* 1 MB page size */
-#define PAGE_SIZE_4MB          0x00030000  /* 4 MB page size */
-
-
-/* DCPLB_DATA and ICPLB_DATA Bit Positions */
-#define CPLB_VALID_P            0  /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P             1  /* 0=entry may be replaced, 1=entry locked */
-#define CPLB_USER_RD_P          2  /* 0=no read access, 1=read access allowed (user mode) */
-/*** DCPLB_DATA only */
-#define CPLB_USER_WR_P          3  /* 0=no write access, 0=write access allowed (user mode) */
-#define CPLB_SUPV_WR_P          4  /* 0=no write access, 0=write access allowed (supervisor mode) */
-#define CPLB_L1SRAM_P           5  /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
-#define CPLB_DA0ACC_P           6  /* 0=access allowed from either DAG, 1=access from DAG0 only */
-#define CPLB_DIRTY_P            7  /* 1=dirty, 0=clean */
-#define CPLB_L1_CHBL_P          12 /* 0=non-cacheable in L1, 1=cacheable in L1 */
-#define CPLB_WT_P               14 /* 0=write-back, 1=write-through */
-
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#if !defined(__ADSPLPBLACKFIN__)
-#define ASTAT_AC0_P ASTAT_AC0_COPY_P
-#define ASTAT_AC_P  ASTAT_AC0_COPY_P
-#define ASTAT_AV0_P ASTAT_V_COPY_P
-#define ASTAT_AC    MK_BMSK_(ASTAT_AC0_COPY_P)
-#define ASTAT_AV1   MK_BMSK_(ASTAT_V_COPY_P)
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _DEF_BLACKFIN_H */
diff --git a/libgloss/bfin/include/sys/_adi_platform.h b/libgloss/bfin/include/sys/_adi_platform.h
deleted file mode 100644
index b121537b9..000000000
--- a/libgloss/bfin/include/sys/_adi_platform.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/*
-** Include appropriate header file for platform.
-** Copyright (C) 2004-2009 Analog Devices Inc. All Rights Reserved.
-*/
-
-#ifndef __ADI_PLATFORM_H
-#define __ADI_PLATFORM_H
-
-#ifndef __ASSEMBLER__
-
-#if defined (__ADSPBF531__)
-#include <cdefBF531.h>
-#elif defined (__ADSPBF532__)
-#include <cdefBF532.h>
-#elif defined (__ADSPBF533__)
-#include <cdefBF533.h>
-#elif defined (__ADSPBF534__)
-#include <cdefBF534.h>
-#elif defined (__ADSPBF535__)
-#include <cdefBF535.h>
-#elif defined (__ADSPBF536__)
-#include <cdefBF536.h>
-#elif defined (__ADSPBF537__)
-#include <cdefBF537.h>
-#elif defined (__ADSPBF538__)
-#include <cdefBF538.h>
-#elif defined (__ADSPBF539__)
-#include <cdefBF539.h>
-#elif defined (__ADSPBF561__)
-#include <cdefBF561.h>
-#elif defined (__AD6531__)
-#include <cdefAD6531.h>
-#elif defined (__AD6532__)
-#include <cdefAD6532.h>
-#elif defined (__AD6723__)
-#include <cdefAD6723.h>
-#elif defined (__AD6900__)
-#include <cdefAD6900.h>
-#elif defined (__AD6901__)
-#include <cdefAD6901.h>
-#elif defined (__AD6902__)
-#include <cdefAD6902.h>
-#elif defined (__AD6903__)
-#include <cdefAD6903.h>
-#elif defined (__AD6904__)
-#include <cdefAD6904.h>
-#elif defined (__AD6905__)
-#include <cdefAD6905.h>
-#elif defined (__MT6906__)
-#include <cdefMT6906.h>
-#elif defined (__ADSPBF504__)
-#include <cdefBF504.h>
-#elif defined (__ADSPBF504F__)
-#include <cdefBF504F.h>
-#elif defined (__ADSPBF506__) || defined (__ADSPBF506F__)
-#include <cdefBF506F.h>
-#elif defined (__ADSPBF512__)
-#include <cdefBF512.h>
-#elif defined (__ADSPBF514__)
-#include <cdefBF514.h>
-#elif defined (__ADSPBF516__)
-#include <cdefBF516.h>
-#elif defined (__ADSPBF518__)
-#include <cdefBF518.h>
-#elif defined (__ADSPBF522__)
-#include <cdefBF522.h>
-#elif defined (__ADSPBF523__)
-#include <cdefBF523.h>
-#elif defined (__ADSPBF524__)
-#include <cdefBF524.h>
-#elif defined (__ADSPBF525__)
-#include <cdefBF525.h>
-#elif defined (__ADSPBF526__)
-#include <cdefBF526.h>
-#elif defined (__ADSPBF527__)
-#include <cdefBF527.h>
-#elif defined (__ADSPBF542__)
-#include <cdefBF542.h>
-#elif defined (__ADSPBF542M__)
-#include <cdefBF542M.h>
-#elif defined (__ADSPBF544__)
-#include <cdefBF544.h>
-#elif defined (__ADSPBF544M__)
-#include <cdefBF544M.h>
-#elif defined (__ADSPBF547__)
-#include <cdefBF547.h>
-#elif defined (__ADSPBF547M__)
-#include <cdefBF547M.h>
-#elif defined (__ADSPBF548__)
-#include <cdefBF548.h>
-#elif defined (__ADSPBF548M__)
-#include <cdefBF548M.h>
-#elif defined (__ADSPBF549__)
-#include <cdefBF549.h>
-#elif defined (__ADSPBF549M__)
-#include <cdefBF549M.h>
-#elif defined (__ADSPBF592A__)
-#include <cdefBF592-A.h>
-#elif defined (__ADSPBF606__)
-#include <cdefBF606.h>
-#elif defined (__ADSPBF607__)
-#include <cdefBF607.h>
-#elif defined (__ADSPBF608__)
-#include <cdefBF608.h>
-#elif defined (__ADSPBF609__)
-#include <cdefBF609.h>
-#else
-#error Processor Type Not Supported
-#endif
-
-
-#else
-
-#if defined (__ADSPBF531__)
-#include <defBF531.h>
-#elif defined (__ADSPBF532__)
-#include <defBF532.h>
-#elif defined (__ADSPBF533__)
-#include <defBF533.h>
-#elif defined (__ADSPBF534__)
-#include <defBF534.h>
-#elif defined (__ADSPBF535__)
-#include <defBF535.h>
-#elif defined (__ADSPBF536__)
-#include <defBF536.h>
-#elif defined (__ADSPBF537__)
-#include <defBF537.h>
-#elif defined (__ADSPBF538__)
-#include <defBF538.h>
-#elif defined (__ADSPBF539__)
-#include <defBF539.h>
-#elif defined (__ADSPBF561__)
-#include <defBF561.h>
-#elif defined (__AD6531__)
-#include <defAD6531.h>
-#elif defined (__AD6532__)
-#include <defAD6532.h>
-#elif defined (__AD6723__)
-#include <defAD6723.h>
-#elif defined (__AD6900__)
-#include <defAD6900.h>
-#elif defined (__AD6901__)
-#include <defAD6901.h>
-#elif defined (__AD6902__)
-#include <defAD6902.h>
-#elif defined (__AD6903__)
-#include <defAD6903.h>
-#elif defined (__AD6904__)
-#include <defAD6904.h>
-#elif defined (__AD6905__)
-#include <defAD6905.h>
-#elif defined (__MT6906__)
-#include <defMT6906.h>
-#elif defined (__ADSPBF504__)
-#include <defBF504.h>
-#elif defined (__ADSPBF504F__)
-#include <defBF504F.h>
-#elif defined (__ADSPBF506__) || defined (__ADSPBF506F__)
-#include <defBF506F.h>
-#elif defined (__ADSPBF512__)
-#include <defBF512.h>
-#elif defined (__ADSPBF514__)
-#include <defBF514.h>
-#elif defined (__ADSPBF516__)
-#include <defBF516.h>
-#elif defined (__ADSPBF518__)
-#include <defBF518.h>
-#elif defined (__ADSPBF522__)
-#include <defBF522.h>
-#elif defined (__ADSPBF523__)
-#include <defBF523.h>
-#elif defined (__ADSPBF524__)
-#include <defBF524.h>
-#elif defined (__ADSPBF525__)
-#include <defBF525.h>
-#elif defined (__ADSPBF526__)
-#include <defBF526.h>
-#elif defined (__ADSPBF527__)
-#include <defBF527.h>
-#elif defined (__ADSPBF542__)
-#include <defBF542.h>
-#elif defined (__ADSPBF542M__)
-#include <defBF542M.h>
-#elif defined (__ADSPBF544__)
-#include <defBF544.h>
-#elif defined (__ADSPBF544M__)
-#include <defBF544M.h>
-#elif defined (__ADSPBF547__)
-#include <defBF547.h>
-#elif defined (__ADSPBF547M__)
-#include <defBF547M.h>
-#elif defined (__ADSPBF548__)
-#include <defBF548.h>
-#elif defined (__ADSPBF548M__)
-#include <defBF548M.h>
-#elif defined (__ADSPBF549__)
-#include <defBF549.h>
-#elif defined (__ADSPBF549M__)
-#include <defBF549M.h>
-#elif defined (__ADSPBF592A__)
-#include <defBF592-A.h>
-#elif defined (__ADSPBF606__)
-#include <defBF606.h>
-#elif defined (__ADSPBF607__)
-#include <defBF607.h>
-#elif defined (__ADSPBF608__)
-#include <defBF608.h>
-#elif defined (__ADSPBF609__)
-#include <defBF609.h>
-
-#else
-#error Processor Type Not Supported
-#endif
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* __INC_BLACKFIN__ */
-
diff --git a/libgloss/bfin/include/sys/anomaly_macros_rtl.h b/libgloss/bfin/include/sys/anomaly_macros_rtl.h
deleted file mode 100644
index b5110f09d..000000000
--- a/libgloss/bfin/include/sys/anomaly_macros_rtl.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * anomaly_macros_rtl.h : $Revision$
- *
- * (c) Copyright 2005-2011 Analog Devices, Inc.  All rights reserved.
- *
- * This file defines macros used within the run-time libraries to enable
- * certain anomaly workarounds for the appropriate chips and silicon
- * revisions. Certain macros are defined for silicon-revision none - this
- * is to ensure behaviour is unchanged from libraries supplied with
- * earlier tools versions, where a small number of anomaly workarounds
- * were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
- * is defined in this case.
- *
- * This file defines macros for a subset of all anomalies that may impact
- * the run-time libraries.
- *
- ************************************************************************/
-
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_2_4:"Assembly code in comment used to illustrate anomalous behaviour")
-#endif /* _MISRA_RULES */
-
-#if !defined(__SILICON_REVISION__)
-#define __FORCE_LEGACY_WORKAROUNDS__
-#endif
-
-
-/* 050000245 - "False Hardware Error from an Access in the Shadow of a
-**              Conditional Branch"
-**
-** If a load accesses reserved or illegal memory on the opposite control
-** flow of a conditional jump to the taken path, a false hardware error
-** will occur.
-**
-** This macro is used by System Services/Device Drivers.
-**
-** This is for all Blackfin LP parts.
-*/
-#define WA_05000245 \
-  (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
-
-
-/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
- * When the SPI slave boot completes, the final DMA IRQ is cleared
- * but the DMA5_CONFIG and SPI_CTL registers are not reset to their
- * default states.
- *
- * We work around this by resetting the registers to their default
- * values at the beginning of the CRT. The only issue would be when
- * users boot from flash and make use of the DMA or serial port.
- * In this case, users would need to modify the CRT.
- *
- * This problem impacts all revisions of ADSP-BF531/2/3/8/9
- */
-#define WA_05000229 \
-	(defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
-	 (defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
-	  defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
-	  defined(__ADSPBF539__)))
-
-
-/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
- * particular stage".
- *
- * Where an interrupt occurs killing a stalled system MMR write, and the ISR
- * executes an SSYNC, execution execution may stall indefinitely".
- *
- * The workaround is to execute a mispredicted jump over a dummy MMR read,
- * thus killing the read. Also to avoid a system MMR write in two slots
- * after a not predicted conditional jump.
- *
- * This problem impacts:
- * BF531/2/3 - < 0.6
- * BF534/6/7 - < 0.3
- * BF538/9 - < 0.4
- * BF561/6 - < 0.5
- *
- * Since this impacts 538/9 0.3 but not 534 0.3 (the libraries that they use)
- * we have to enable this workaround for the 534 0.3 libraries (see bottom
- * two lines).
- */
-#define WA_05000283 \
-        (defined (__SILICON_REVISION__) && \
-         (((defined(__ADSPBF531__) ||  \
-            defined(__ADSPBF532__) ||  \
-            defined(__ADSPBF533__)) && \
-           (__SILICON_REVISION__ == 0xffff || \
-            __SILICON_REVISION__ < 0x6)) || \
-          ((defined(__ADSPBF534__) ||  \
-            defined(__ADSPBF536__) ||  \
-            defined(__ADSPBF537__)) && \
-           (__SILICON_REVISION__ == 0xffff || \
-            __SILICON_REVISION__ < 0x3)) || \
-          ((defined(__ADSPBF538__) ||  \
-            defined(__ADSPBF539__)) &&  \
-           (__SILICON_REVISION__ == 0xffff || \
-            __SILICON_REVISION__ < 0x4)) || \
-          (defined(__ADSPBF561__)) || \
-          (defined(__ADSPBF534__) && __SILICON_REVISION__ == 0x3 && \
-           defined(__ADI_LIB_BUILD__))))
-
-
-/* 05-00-0311 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
-**
-**  Impacted:
-**     ADSP-BF53[123] - 0.0-0.5 (fixed in 0.6)
-**
-** Use by System Services/Device Drivers.
-*/
-#define WA_05000311 \
-  (defined(__ADSPBF533_FAMILY__) && \
-   (defined(__SILICON_REVISION__) && \
-    (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)))
-
-
-/* 05-00-0312 - Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers
-**              Are Interrupted
-**
-**  Impacted:
-**     ADSP-BF53[123]   - 0.0-0.5 (fixed in 0.6)
-**     ADSP-BF53[467]   - all supported revisions
-**     ADSP-BF53[89]    - 0.0-0.4 (fixed in 0.5)
-**     ADSP-BF561       - all supported revisions
-**     ADSP-BF54[24789] - 0.0 (fixed in 0.1)
-**
-** Used by VDK
-*/
-#define WA_05000312 \
-        (defined(__SILICON_REVISION__) && \
-         ((defined(__ADSPBF533_FAMILY__) &&  \
-           (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
-          (defined(__ADSPBF537_FAMILY__)) ||  \
-          (defined(__ADSPBF538_FAMILY__) &&  \
-           (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
-          (defined(__ADSPBF548_FAMILY__) && \
-           (__SILICON_REVISION__ == 0x0 || __SILICON_REVISION__ == 0xffff)) || \
-          (defined(__ADSPBF561_FAMILY__))))
-
-
-/* 05-00-0323 - Erroneous Flag (GPIO) Pin Operations under Specific Sequences
-**
-**  Impacted:
-**     ADSP-BF561 - all supported revisions
-**
-** Use by System Services/Device Drivers.
-*/
-#define WA_05000323 \
-  (defined(__ADSPBF561__) && defined(__SILICON_REVISION__))
-
-
-/* 05-00-0365 - DMAs that Go Urgent during Tight Core Writes to External
-**              Memory Are Blocked
-**
-**  Impacted:
-**     ADSP-BF54[24789] - all supported revisions
-**     ADSP-BF54[24789]M - all supported revisions
-**
-** Use by System Services/Device Drivers.
-*/
-#define WA_05000365 \
-  ((defined(__ADSPBF548_FAMILY__) || defined(__ADSPBF548M_FAMILY__)) && \
-   defined(__SILICON_REVISION__))
-
-
-/* 05-00-0371 - Possible RETS Register Corruption when Subroutine Is under
-**              5 Cycles in Duration
-**
-** This problem impacts:
-** BF531/2/3 - 0.0-0.5 (fixed in 0.6)
-** BF534/6/7 - 0.0-0.3
-** BF538/9   - 0.0-0.4 (fixed in 0.5)
-** BF561     - 0.0-0.5
-** BF542/4/7/8/9  - 0.0-0.1 (fixed in 0.2)
-** BF523/5/7 - 0.0-0.1 (fixed in 0.2)
-**
-*/
-#define WA_05000371 \
-  (defined(__SILICON_REVISION__) && \
-   ((defined(__ADSPBF533_FAMILY__) && \
-     (__SILICON_REVISION__ <= 0x5 || __SILICON_REVISION__ == 0xffff)) || \
-    (defined(__ADSPBF537_FAMILY__) && \
-     (__SILICON_REVISION__ <= 0x3 || __SILICON_REVISION__ == 0xffff)) || \
-    (defined(__ADSPBF538_FAMILY__) && \
-     (__SILICON_REVISION__ <= 0x4 || __SILICON_REVISION__ == 0xffff)) || \
-    (defined(__ADSPBF548_FAMILY__) && \
-     (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
-    (defined(__ADSPBF527_FAMILY__) && \
-     (__SILICON_REVISION__ <= 0x1 || __SILICON_REVISION__ == 0xffff)) || \
-    (defined(__ADSPBF561__) || defined(__ADSPBF566__))))
-
-
-/* 05-00-0412 - "TESTSET Instruction Causes Data Corruption with Writeback Data
- * Cache Enabled"
- *
- * If you use the testset instruction to operate on L2 memory and you have data
- * in external memory that is cached using WB mode, data in external memory
- * and/or L2 memory can be corrupted.
- *
- * Workaround: Either do not use writeback cache or precede the TESTSET
- * instruction with an SSYNC instruction. If preceding the TESTSET instruction
- * by an SSYNC instruction, do the following:
- *
- *   CLI R0
- *   R1 = [P0]  // perform a dummy read to make sure CPLB is installed
- *   NOP
- *   NOP
- *   SSYNC
- *   TESTSET (P0)
- *   STI R0
- *
- * This problem impacts:
- * BF561/6 - rev 0.0-0.5
- *
- */
-#define WA_05000412 \
-        (defined (__SILICON_REVISION__) && defined(__ADSPBF561__))
-
-
-/* 05-00-0426 - Speculative Fetches of Indirect-Pointer Instructions Can
-**              Cause False Hardware Errors
-**
-**
-** A false hardware error is generated if there is an indirect jump or
-** call through a pointer which may point to reserved or illegal memory
-** on the opposite control flow of a conditional jump to the taken path.
-** This commonly occurs when using function pointers, which can be
-** invalid (e.g., set to -1).
-**
-** Workaround: If instruction cache is on or the ICPLBs are enabled,
-** this anomaly does not apply. If instruction cache is off and ICPLBs
-** are disabled, the indirect pointer instructions must be 2 instructions
-** away from the branch instruction, which can be implemented using NOPs:
-**
-**
-**  Impacted:
-**     All parts and revisions other than BF535 based parts.
-**
-** Used by System Services/Device Drivers.
-*/
-#define WA_05000426 \
-   (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
-
-
-/* 05-00-0428 - "Lost/Corrupted Write to L2 Memory Following Speculative Read
- * by Core B from L2 Memory"
- *
- * This issue occurs only when the accesses are performed by core B of a BF561.
- *
- * When a write to internal L2 memory follows a speculative read from internal
- * L2 memory, the L2 write may be lost or corrupted. For this anomaly to occur,
- * the speculative read must be caused by a read in the shadow of a branch. The
- * accesses do not have to be consecutive accesses. In other words, the problem
- * can occur even if there are multiple instructions between the speculative
- * read and the write, as shown in the following example:
- *
- *   R1 = 1; R2 = 1;
- *   CC = R1 == R2;
- *   IF CC JUMP X;  // Always true...
- *   R0 = [P0];     // If any of these three loads accesses L2 memory from Core
- *   R1 = [P1];     // B, speculative execution in the pipeline causes the
- *   R2 = [P2];     // anomaly trigger condition.
- *   X:
- *   ...            // Any number of instructions...
- *   [P0] = R0;  // This write can be corrupted or lost.
- *
- * The issue does not occur if the speculative read access is caused by an
- * interrupt or exception.
- *
- * The workaround required depends upon the conditional branch instruction.
- * If the evaluated condition is true and the branch is predicted, then the
- * workaround is to ensure that the target instruction is not be a load
- * instruction, for example:
- *
- *   IF CC JUMP X (BP);
- *   ...
- *   X: <load that might be from L2 memory>
- *
- * If the evaluated condition is false and the branch is not predicted, then
- * the workaround is to make sure that none of the three instructions that
- * are executed after the conditional JUMP are load instructions, for example:
- *
- *   IF CC JUMP ...;
- *   <load that might be from L2 memory>
- *   <load that might be from L2 memory>
- *   <load that might be from L2 memory>
- *
- * This problem impacts:
- * BF561 - rev 0.4,0.5
- *
- */
-#define WA_05000428 \
-        (defined(__SILICON_REVISION__) && \
-         defined(__ADSPBF561__)        && \
-         ((__SILICON_REVISION__ == 0xffff) || \
-          (__SILICON_REVISION__ == 0x4)    || \
-          (__SILICON_REVISION__ == 0x5)))
-
-
-/* 05-00-0443 - IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall
-**
-**  Impacted:
-**     All parts and revisions other than BF535 based parts.
-**
-** Used by System Services/Device Drivers.
-*/
-#define WA_05000443 \
-   (defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__))
-
-
-/* 16-00-0005 - "Using L1 Instruction Cache with Parity Enabled is Unreliable."
-**
-** Using L1 instruction cache with parity enabled is unreliable and may cause
-** unpredictable results.
-**
-** Impacted:
-**    BF6xx.
-*/
-#define WA_16000005 \
-  (defined(__ADSPBF60x__) && defined(__SILICON_REVISION__))
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
diff --git a/libgloss/bfin/include/sys/excause.h b/libgloss/bfin/include/sys/excause.h
deleted file mode 100644
index 2fe9a05e3..000000000
--- a/libgloss/bfin/include/sys/excause.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * excause.h
- *
- * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/*
-** Definitions of constants for the four user-level bits in EXCAUSE,
-** the field from SYSSTAT that is set when the EXCPT instruction is
-** invoked.
-*/
-
-#ifndef _EXCAUSE_H
-#define _EXCAUSE_H
-
-/*
-** Value 0x0 - exit program. (halt)
-** R0 => exit status.
-*/
-
-#define EX_EXIT_PROG	0x0
-
-/*
-** Value 0x1 - abnormal exit (abort)
-*/
-
-#define EX_ABORT_PROG	0x1
-
-/*
-** Value 0x2 - invoke system service.
-** R0 => command.
-** R1 => first arg
-** R2 => second arg
-*/
-
-#define EX_SYS_REQ	0x2
-
-/*
-** Available commands:
-*/
-
-#define EX_SYSREQ_NONE		0x00	/* Do nothing */
-#define EX_SYSREQ_REG_ISR	0x01	/* Register an interrupt handler.
-					   R1==EVT entry, R2==func ptr
-					   Returns previous entry in R0. */
-#define EX_SYSREQ_RAISE_INT	0x02	/* Cause an interrupt
-					   R1 = int number */
-/*
-** Values 0x3 to 0x4 currently undefined.
-*/
-
-/*
-** Value 0x5 - File I/O
-** R0 => first arg
-** R1 => second arg
-** R2 => third arg
-** R4 => command
-** result => R0
-*/
-
-#define EX_FILE_IO 0x5
-
-/*
-** Available commands:
-** XXX stdout/stderr are handled separately for writing.
-*/
-
-#define EX_FILEIO_OPEN		0x00	/* R0 => dev, R1=> path, R2=>mode */
-#define EX_FILEIO_CLOSE		0x01	/* R0=> fid */
-#define EX_FILEIO_WRITE		0x02	/* R0=>fid, R1=>data, R2=>length */
-#define EX_FILEIO_READ		0x03	/* R0=>fid, R1=>data, R2=>length */
-#define EX_FILEIO_SEEK		0x04	/* R0=>fid, R1=>offset, R2=>mode */
-#define EX_FILEIO_DUP		0x05	/* R0=>fid */
-
-/*
-** Values 0x6 to 0xF currently undefined.
-*/
-
-#endif /*  _EXCAUSE_H */
diff --git a/libgloss/bfin/include/sys/exception.h b/libgloss/bfin/include/sys/exception.h
deleted file mode 100644
index d1a531aa7..000000000
--- a/libgloss/bfin/include/sys/exception.h
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#pragma once
-#ifndef __NO_BUILTIN
-#pragma system_header /* exception.h */
-#endif
-/************************************************************************
- *
- * exception.h
- *
- * (c) Copyright 2001-2008 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef _EXCEPTION_H
-#define _EXCEPTION_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_5_6)
-#pragma diag(suppress:misra_rule_5_7)
-#pragma diag(suppress:misra_rule_6_3)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#pragma diag(suppress:misra_rule_19_10)
-#pragma diag(suppress:misra_rule_19_13)
-#endif /* _MISRA_RULES */
-
-
-
-/*
-** Definitions for user-friendly interrupt handling.
-*/
-
-/*
-** Memory-Mapped Registers (MMRs) - these record what causes address
-** exceptions.
-*/
-
-#define EX_DATA_FAULT_STATUS	0xFFE00008
-#define EX_DATA_FAULT_ADDR	0xFFE0000C
-#define EX_CODE_FAULT_STATUS	0xFFE01008
-#define EX_CODE_FAULT_ADDR	0xFFE0100C
-
-/*
-** Event Vector Table
-*/
-
-#define EX_EVENT_VECTOR_TABLE	0xFFE02000
-
-/*
-** Meaning of the various bits in EXCAUSE field in SEQSTAT register.
-*/
-
-#define EX_BITS		0x3F	/* All EXCAUSE bits */
-#define EX_TYPE		0x30	/* The bits which define the type */
-#define EX_DEBUG	0x10	/* If set, is a debug exception type */
-#define EX_SYS		0x20	/* If set, is a system exception type */
-				/* If neither set, is from EXCPT instr */
-
-#define EX_IS_DEBUG_EXCEPTION(E)	(((E)&EX_TYPE)==EX_DEBUG)
-#define EX_IS_SYSTEM_EXCEPTION(E)	(((E)&EX_TYPE)==EX_SYS)
-#define EX_IS_USER_EXCEPTION(E)		(((E)&EX_TYPE)==0)
-
-/*
-** Service exceptions continue from the instruction after the one
-** that raised the exception.
-** Error exceptions restart the instruction that raised the exception.
-*/
-
-#define EX_IS_SERVICE_EXCEPTION(E)	(!EX_IS_SYSTEM_EXCEPTION(E))
-#define EX_IS_ERROR_EXCEPTION(E)	(EX_IS_SYSTEM_EXCEPTION(E))
-
-#define EX_DB_SINGLE_STEP 0x10	/* Processor is single-stepping */
-#define EX_DB_EMTRCOVRFLW 0x11	/* Emulation Trace buffer overflowed */
-
-#define EX_SYS_UNDEFINSTR 0x21	/* Undefined instruction */
-#define EX_SYS_ILLINSTRC  0x22	/* Illegal instruction combination */
-#define EX_SYS_DCPLBPROT  0x23	/* Data CPLB Protection violation */
-#define EX_SYS_DALIGN     0x24	/* Data access misaligned address violation */
-#define EX_SYS_UNRECEVT   0x25	/* Unrecoverable event */
-#define EX_SYS_DCPLBMISS  0x26	/* Data access CPLB Miss */
-#define EX_SYS_DCPLBMHIT  0x27	/* Data access CPLB Multiple Hits */
-#define EX_SYS_EMWATCHPT  0x28	/* Emulation watch point match */
-#define EX_SYS_CACCESSEX  0x29	/* Code fetch access exception */
-#define EX_SYS_CALIGN     0x2A	/* Attempted misaligned instr cache fetch */
-#define EX_SYS_CCPLBPROT  0x2B	/* Code fetch CPLB Protection */
-#define EX_SYS_CCPLBMISS  0x2C	/* CPLB miss on an instruction fetch */
-#define EX_SYS_CCPLBMHIT  0x2D	/* Code fetch CPLB Multiple Hits */
-#define EX_SYS_ILLUSESUP  0x2E	/* Illegal use of Supervisor Resource */
-
-/*
-** Meaning of the various bits in HWERRCAUSE in SEQSTAT
-*/
-
-#define EX_HWBITS (0x1F<<14)	/* bits 18:14 */
-
-#if !defined(__ADSPLPBLACKFIN__)
-#define EX_HW_NOMEM1	(0x16<<14)
-#define EX_HW_NOMEM2	(0x17<<14)
-#else
-#define EX_HW_SYSMMR	(0x02<<14)
-#define EX_HW_EXTMEM	(0x03<<14)
-#endif
-#define EX_HW_DMAHIT	(0x01<<14)
-#define EX_HW_PERFMON (0x12<<14)
-#define EX_HW_RAISE	(0x18<<14)
-
-/*
-** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS
-*/
-
-#define EX_DATA_FAULT_ILLADDR   (1<<19)	/* non-existent memory */
-#define EX_DATA_FAULT_DAG       (1<<18)	/* 0=>DAG0, 1=>DAG1 */
-#define EX_DATA_FAULT_USERSUPV  (1<<17)	/* 0=>user mode, 1=> supervisor */
-#define EX_DATA_FAULT_READWRITE (1<<16)	/* 0=>read, 1=>write */
-#define EX_DATA_FAULT_CPLB       0xFFFF	/* 0=>CPLB0, 1=>CPLB1, etc */
-
-#define EX_CODE_FAULT_ILLADDR   (1<<19)	/* non-existent memory */
-#define EX_CODE_FAULT_USERSUPV  (1<<17)	/* 0=>user mode, 1=> supervisor */
-#define EX_CODE_FAULT_CPLB       0xFFFF	/* 0=>CPLB0, 1=>CPLB1, etc */
-
-/*
-** The kinds of interrupt that can occur. These are also the
-** indices into the Event Vector Table.
-*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-  ik_err=-1,
-  ik_emulation,
-  ik_reset,
-  ik_nmi,
-  ik_exception,
-  ik_global_int_enable,
-  ik_hardware_err,
-  ik_timer,
-  ik_ivg7,
-  ik_ivg8,
-  ik_ivg9,
-  ik_ivg10,
-  ik_ivg11,
-  ik_ivg12,
-  ik_ivg13,
-  ik_ivg14,
-  ik_ivg15,
-  num_interrupt_kind
-} interrupt_kind;
-
-/*
-** Structure for recording details of an exception or interrupt
-** that has occurred.
-*/
-
-typedef struct {
-  interrupt_kind kind;		/* whether interrupt, exception, etc. */
-  int value;			/* interrupt number, exception type, etc. */
-  void *pc;			/* PC at point where exception occurred */
-  void *addr;			/* if an address faulted, which one. */
-  unsigned status;		/* if an address faulted, why. */
-} interrupt_info;
-
-/*
-** Macro for defining an interrupt routine
-*/
-
-typedef void (*ex_handler_fn)();
-
-#define EX_HANDLER(KIND,NAME) \
-_Pragma(#KIND) \
-void NAME (void)
-
-#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME)
-
-#define EX_INTERRUPT_HANDLER(NAME)	EX_HANDLER(interrupt,NAME)
-#define EX_EXCEPTION_HANDLER(NAME)	EX_HANDLER(exception,NAME)
-#define EX_NMI_HANDLER(NAME)		EX_HANDLER(nmi,NAME)
-#define EX_REENTRANT_HANDLER(NAME) \
-_Pragma("interrupt_reentrant") \
-EX_HANDLER(interrupt,NAME)
-
-/*
-** A convenience function for setting up the interrupt_info contents.
-** Must be called from immediately with the interrupt handler.
-*/
-
-void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info);
-
-/*
-** Diagnostics function for reporting unexpected events.
-*/
-
-void _ex_report_event(interrupt_info *int_info);
-
-/*
-** Register an interrupt handler within the EVT.
-** Return previous value if there was one.
-*/
-ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler);
-
-/*
-** Some magic values for registering default and null handlers.
-*/
-
-#define EX_INT_DEFAULT ((ex_handler_fn)-1)
-#define EX_INT_IGNORE  ((ex_handler_fn)0)
-
-/*
-** Extended function to register an interrupt handler within the EVT.
-** Returns the old handler.
-**
-** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE
-** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then
-** return
-**
-** If fn == EX_INT_IGNORE, disable the interrupt
-** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable
-**   the interrupt in IMASK
-** Otherwise, install the new interrupt handler.  Then,
-**  If enabled == EX_INT_DISABLE, disable the interrupt in IMASK
-**  If enabled == EX_INT_ENABLE, enable the interrupt in IMASK
-**  otherwise leave the interrupt status alone.
-*/
-ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn,
-                                  int enable);
-
-/* Constants for the enabled parameter of register_handler_ex */
-#define EX_INT_DISABLE 0
-#define EX_INT_ENABLE 1
-#define EX_INT_KEEP_IMASK -1
-#define EX_INT_ALWAYS_ENABLE 2
-
-/*
-** Allow the user to raise exceptions from C.
-*/
-
-int raise_interrupt(interrupt_kind kind, int which,
-   int cmd, int arg1, int arg2);
-
-#ifdef __cplusplus
-  } /* extern "C" */
-#endif
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _EXCEPTION_H */
diff --git a/libgloss/bfin/include/sys/mc_typedef.h b/libgloss/bfin/include/sys/mc_typedef.h
deleted file mode 100644
index abcd62dd5..000000000
--- a/libgloss/bfin/include/sys/mc_typedef.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#pragma once
-#ifndef __NO_BUILTIN
-#pragma system_header /* sys/mc_typedef.h */
-#endif
-/************************************************************************
- *
- * sys/mc_typedef.h
- *
- * (c) Copyright 2007-2009 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-/* Define testset_t. */
-
-#ifndef _SYS_MC_TYPEDEF_H
-#define _SYS_MC_TYPEDEF_H
-
-#if !defined(__ADSPLPBLACKFIN__)
-  typedef volatile unsigned char testset_t;
-#elif defined(__WORKAROUND_TESTSET_ALIGN) || defined(__WORKAROUND_05000412)
-  /* these workarounds require 32-bit aligned address */
-  typedef volatile unsigned int testset_t;
-#else
-  typedef volatile unsigned short testset_t;
-#endif
-
-#endif /* _SYS_MC_TYPEDEF_H */
diff --git a/libgloss/bfin/include/sys/platform.h b/libgloss/bfin/include/sys/platform.h
deleted file mode 100644
index b78f8902e..000000000
--- a/libgloss/bfin/include/sys/platform.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-#ifndef _PLATFORM_H
-#define _PLATFORM_H
-/* Generic Wrapper for platform specific header file.
-   Copyright (C.) 2004, Analog Devices Inc.  All Rights Reserved.
- */
-#include <sys/_adi_platform.h>
-#endif
diff --git a/libgloss/bfin/include/sys/pll.h b/libgloss/bfin/include/sys/pll.h
deleted file mode 100644
index 7525d04cc..000000000
--- a/libgloss/bfin/include/sys/pll.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/************************************************************************
- *
- * pll.h
- *
- * (c) Copyright 2003-2004 Analog Devices, Inc.  All rights reserved.
- *
- ************************************************************************/
-
-#ifndef __ASSEMBLER__
-#pragma once
-#pragma system_header
-#endif
-
-#ifndef _PLL_H
-#define _PLL_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_6_3)
-#endif /* _MISRA_RULES */
-
-#define NO_STARTUP_SET 0
-#define MAX_IN_STARTUP 1
-
-#ifndef __ASSEMBLER__
-
-enum clkctrl_t {
-    /* no modification of PLL rates in CRT startup - default */
-   no_startup_set=NO_STARTUP_SET,
-
-    /* CRT startup sets PLL rates to suitable maximum values */
-   max_in_startup=MAX_IN_STARTUP
-};
-
-/*
-** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum
-** speed performance rates.  The default version defined in the runtime-
-** libraries defines __clk_ctrl to 0 which disables the feature.
-*/
-extern enum clkctrl_t __clk_ctrl;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ADSPLPBLACKFIN__)
-
-/* Sets SSEL and CSEL bits in PLL_DIV to passed values.
-** Returns -1 on failure.
-*/
-int pll_set_system_clocks(int _csel, int _ssel);
-
-/*
-** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT.
-** Returns -1 on failure.
-*/
-int pll_set_system_vco(int _msel, int _df, int _lockcnt);
-
-#endif /* __ADSPLPBLACKFIN__ */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLER__ */
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _PLL_H */
-
diff --git a/libgloss/bfin/include/sysreg.h b/libgloss/bfin/include/sysreg.h
deleted file mode 100644
index 3b3a2909a..000000000
--- a/libgloss/bfin/include/sysreg.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * The authors hereby grant permission to use, copy, modify, distribute,
- * and license this software and its documentation for any purpose, provided
- * that existing copyright notices are retained in all copies and that this
- * notice is included verbatim in any distributions. No written agreement,
- * license, or royalty fee is required for any of the authorized uses.
- * Modifications to this software may be copyrighted by their authors
- * and need not follow the licensing terms described here, provided that
- * the new terms are clearly indicated on the first page of each file where
- * they apply.
- */
-
-/* This file must be used with compiler version 8.0.8.1 */
-
-#ifdef __VERSIONNUM__
-#if __VERSIONNUM__ != 0x08000801
-#error The compiler version does not match the version of the sysreg.h include
-#endif
-#endif
-
-/************************************************************************
- *
- * sysreg.h
- *
- * (c) Copyright 2001-2006 Analog Devices, Inc.  All rights reserved.
- *
- ***********************************************************************/
-
-#pragma once
-#ifndef __NO_BUILTIN
-#pragma system_header /* sysreg.h */
-#endif
-
-/* sysreg definitions for use in sysreg_read and sysreg_write calls. */
-
-#ifndef _SYSREG_H
-#define _SYSREG_H
-
-#ifdef _MISRA_RULES
-#pragma diag(push)
-#pragma diag(suppress:misra_rule_2_4)
-#pragma diag(suppress:misra_rule_6_3)
-#pragma diag(suppress:misra_rule_19_4)
-#pragma diag(suppress:misra_rule_19_7)
-#pragma diag(suppress:misra_rule_19_10)
-#endif /* _MISRA_RULES */
-
-enum {
-  /* the following can be used in word-sized sysreg reads and writes */
-  reg_I0,
-  reg_I1,
-  reg_I2,
-  reg_I3,
-  reg_M0,
-  reg_M1,
-  reg_M2,
-  reg_M3,
-  reg_B0,
-  reg_B1,
-  reg_B2,
-  reg_B3,
-  reg_L0,
-  reg_L1,
-  reg_L2,
-  reg_L3,
-  reg_LC0,
-  reg_LC1,
-  reg_LT0,
-  reg_LT1,
-  reg_LB0,
-  reg_LB1,
-  reg_RETS,
-  reg_RETI,
-  reg_RETX,
-  reg_RETN,
-  reg_RETE,
-  reg_SEQSTAT,
-  reg_SYSCFG,
-  reg_CYCLES,
-  reg_CYCLES2,
-  reg_A0W,
-  reg_A0X,
-  reg_A1W,
-  reg_A1X,
-  reg_FP,
-  reg_SP,
-  reg_ASTAT,
-
-  /* the following can be used in double-word sysreg reads and writes */
-  reg_A0,
-  reg_A1,
-  __num_SysRegs
-};
-
-#define STACKPOINTER reg_SP
-#define FRAMEPOINTER reg_FP
-
-#ifdef _MISRA_RULES
-#pragma diag(pop)
-#endif /* _MISRA_RULES */
-
-#endif /* _SYSREG_H */